+++ /dev/null
-#
-# Copyright (C) 2010 OpenWrt.org
-#
-# This is free software, licensed under the GNU General Public License v2.
-# See /LICENSE for more information.
-#
-
-include $(TOPDIR)/rules.mk
-include $(INCLUDE_DIR)/kernel.mk
-
-PKG_NAME:=drv_kpi2udp
-PKG_VERSION:=2.2.0
-PKG_RELEASE:=1
-
-PKG_SOURCE:=drv_kpi2udp-$(PKG_VERSION).tar.gz
-PKG_SOURCE_URL:=http://mirror2.openwrt.org/sources
-PKG_MD5SUM:=af3855609554c7f3d2c3df8c597f50a7
-
-include $(INCLUDE_DIR)/package.mk
-
-define KernelPackage/ltq-kpi2udp
- SUBMENU:=Voice over IP
- TITLE:=TAPI KPI2UDP plug-in
- URL:=http://www.lantiq.com/
- DEPENDS:=+kmod-ltq-tapi @TARGET_lantiq
- FILES:=$(PKG_BUILD_DIR)/drv_kpi2udp.ko
- AUTOLOAD:=$(call AutoLoad,26,drv_kpi2udp)
- MAINTAINER:=John Crispin <blogic@openwrt.org>
-endef
-
-define KernelPackage/ltq-kpi2udp/description
- RTP packet path accelleration into IP stack (strongly recommended)
-endef
-
-CONFIGURE_ARGS += --enable-kernelincl="$(LINUX_DIR)/include" \
- --enable-tapiincl="$(STAGING_DIR)/usr/include/drv_tapi" \
- --with-ifxos-incl=$(STAGING_DIR)/usr/include/ifxos \
- --enable-warning \
- --enable-linux-26 \
- --enable-kernelbuild="$(LINUX_DIR)" \
- ARCH=$(LINUX_KARCH)
-
-define Build/Configure
- (cd $(PKG_BUILD_DIR); aclocal && autoconf && automake)
- $(call Build/Configure/Default)
-endef
-
-$(eval $(call KernelPackage,ltq-kpi2udp))
+++ /dev/null
---- a/configure.in
-+++ b/configure.in
-@@ -113,7 +113,7 @@
- AC_ARG_ENABLE(kernelbuild,
- AS_HELP_STRING(--enable-kernelbuild=x,Set the target kernel build path),
- [
-- if test -r $enableval/include/linux/autoconf.h; then
-+ if test -r $enableval/include/generated/autoconf.h; then
- AC_SUBST([KERNEL_BUILD_PATH],[$enableval])
- else
- AC_MSG_ERROR([The kernel build directory is not valid or not configured!])
+++ /dev/null
---- a/ifx_udp_redirect.c
-+++ b/ifx_udp_redirect.c
-@@ -256,7 +256,7 @@
- {
- if (redtab.channels[i].in_use == IFX_TRUE)
- {
-- if (redtab.channels[i].sk->sk_lock.owner != 0)
-+ if (redtab.channels[i].sk->sk_lock.owned != 0)
- return IFX_TRUE;
- }
- }
-@@ -545,7 +545,7 @@
- #if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0))
- if (sk->num != htons(sport))
- #else
-- if (((struct inet_sock *)sk)->num != htons(sport))
-+ if (((struct inet_sock *)sk)->inet_num != htons(sport))
- #endif
- {
- return CALL_MK_SESSION_ERR;
-@@ -628,7 +628,7 @@
- #if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0))
- if((vsock != NULL)&&(vsk != NULL)&&(vsk->num > 0))
- #else
-- if((vsock != NULL)&&(vsk != NULL)&&(((struct inet_sock *)vsk)->num > 0))
-+ if((vsock != NULL)&&(vsk != NULL)&&(((struct inet_sock *)vsk)->inet_num > 0))
- #endif
- {
- /*printk("[KPI2UDP] releasing vsock...%p, ops %p\n", vsock, vsock->ops);*/
+++ /dev/null
-choice
- prompt "board selection"
- depends on PACKAGE_ltq-tapidemo
- default VOICE_CPE_TAPIDEMO_BOARD_EASY50712_V3 if TARGET_lantiq_danube
- default VOICE_CPE_TAPIDEMO_BOARD_EASY508xx if TARGET_lantiq_ar9
- default VOICE_CPE_TAPIDEMO_BOARD_EASY80910 if TARGET_lantiq_vr9
- help
- Select the target platform.
-
- config VOICE_CPE_TAPIDEMO_BOARD_EASY50712
- bool "Danube reference board"
-
- config VOICE_CPE_TAPIDEMO_BOARD_EASY50712_V3
- bool "Danube reference board V3"
-
- config VOICE_CPE_TAPIDEMO_BOARD_EASY508xx
- bool "AR9/GR9 reference board"
-
- config VOICE_CPE_TAPIDEMO_BOARD_EASY80910
- bool "VR9 reference board"
-endchoice
-
-config VOICE_CPE_TAPIDEMO_QOS
- bool "enable QOS support"
- depends on PACKAGE_ltq-tapidemo
- select PACKAGE_kmod-ltq-kpi2udp
- default y
- help
- Option to enable the KPI2UDP RTP packet acceleration path
- (highly recommended for VoIP).
-
-config VOICE_CPE_TAPIDEMO_FAX_T.38_FW
- bool "enable T.38 fax relay"
- depends on (TARGET_lantiq_ar9 || TARGET_lantiq_vr9) && PACKAGE_ltq-tapidemo
- default n
- help
- enable T.38 fax relay demo.
-
-config VOICE_CPE_TAPIDEMO_FW_FILE
- string "override default firmware file"
- depends on PACKAGE_ltq-tapidemo
- default "falcon_voip_fw.bin" if TARGET_lantiq_falcon
-
-config VOICE_CPE_TAPIDEMO_BBD_FILE
- string "override default coefficient file"
- depends on PACKAGE_ltq-tapidemo
- default "falcon_bbd.bin" if TARGET_lantiq_falcon
+++ /dev/null
-#
-# Copyright (C) 2008-2010 OpenWrt.org
-#
-# This is free software, licensed under the GNU General Public License v2.
-# See /LICENSE for more information.
-#
-
-include $(TOPDIR)/rules.mk
-include $(INCLUDE_DIR)/kernel.mk
-
-PKG_NAME:=tapidemo
-PKG_VERSION:=5.1.0.53
-PKG_RELEASE:=1
-
-PKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.gz
-PKG_SOURCE_URL:=http://mirror2.openwrt.org/sources
-PKG_MD5SUM:=c970becc46b2935fb9e18f795d4e8469
-
-PKG_FIXUP:=autoreconf
-
-include $(INCLUDE_DIR)/ltqtapi.mk
-include $(INCLUDE_DIR)/package.mk
-
-define Package/ltq-tapidemo
- SUBMENU:=Telephony
- SECTION:=net
- CATEGORY:=Network
- TITLE:=TAPIdemo application for Lantiq boards
- URL:=http://www.lantiq.com/
- DEPENDS:=$(LTQ_TAPI_DEPENDS) +libpthread
- MAINTAINER:=John Crispin <blogic@openwrt.org>
- MENU:=1
-endef
-
-define Package/ltq-tapidemo/description
- Voice Access mini-PBX Demo Application
-endef
-
-define Package/ltq-tapidemo/config
- source "$(SOURCE)/Config.in"
-endef
-
-TARGET_LDFLAGS+=-lpthread
-
-CONFIGURE_ARGS += \
- ARCH=$(LINUX_KARCH) \
- --enable-linux-26 \
- --enable-kernelincl="$(LINUX_DIR)/include" \
- --with-drvincl="$(STAGING_DIR)/usr/include" \
- --with-ifxos-incl=$(STAGING_DIR)/usr/include/ifxos \
- --with-ifxos-lib=$(STAGING_DIR)/usr/lib \
- $(call autoconf_bool,CONFIG_VOICE_CPE_TAPI_QOS,qos) \
- $(call autoconf_bool,CONFIG_VOICE_CPE_TAPIDEMO_FAX_T,fax-t38) \
- --enable-trace \
- --enable-fs
-
-ifeq ($(CONFIG_VOICE_CPE_TAPIDEMO_BOARD_EASY50712),y)
- CONFIGURE_ARGS += --enable-boardname=EASY50712
-endif
-ifeq ($(CONFIG_VOICE_CPE_TAPIDEMO_BOARD_EASY50712_V3),y)
- CONFIGURE_ARGS += --enable-boardname=EASY50712_V3
-endif
-ifeq ($(CONFIG_VOICE_CPE_TAPIDEMO_BOARD_EASY508xx),y)
- CONFIGURE_ARGS += --enable-boardname=EASY508XX
-endif
-ifeq ($(CONFIG_VOICE_CPE_TAPIDEMO_BOARD_EASY80910),y)
- CONFIGURE_ARGS += --enable-boardname=EASY508XX
-endif
-ifneq ($(CONFIG_VOICE_CPE_TAPIDEMO_FW_FILE),)
- CONFIGURE_ARGS += --with-fw-file="$(strip $(subst ",, $(CONFIG_VOICE_CPE_TAPIDEMO_FW_FILE)))"
-endif
-ifneq ($(CONFIG_VOICE_CPE_TAPIDEMO_BBD_FILE), "")
-CONFIGURE_ARGS += --with-bbd-file="$(strip $(subst ",, $(CONFIG_VOICE_CPE_TAPIDEMO_BBD_FILE)))"
-endif
-
-define Package/ltq-tapidemo/install
- $(INSTALL_DIR) $(1)/usr/sbin $(1)/etc/init.d/
- $(INSTALL_BIN) $(PKG_BUILD_DIR)/src/tapidemo $(1)/usr/sbin
- $(INSTALL_BIN) ./files/bringup_tapidemo $(1)/etc/init.d/tapidemo
-endef
-
-$(eval $(call BuildPackage,ltq-tapidemo))
+++ /dev/null
-#!/bin/sh /etc/rc.common
-# (C) 2008 openwrt.org
-
-START=96
-
-[ ! -f /dev/vmmc10 ] && {
- mknod /dev/vmmc10 c 122 10
- mknod /dev/vmmc11 c 122 11
- mknod /dev/vmmc12 c 122 12
- mknod /dev/vmmc13 c 122 13
- mknod /dev/vmmc14 c 122 14
- mknod /dev/vmmc15 c 122 15
- mknod /dev/vmmc16 c 122 16
- mknod /dev/vmmc17 c 122 17
- mknod /dev/vmmc18 c 122 18
-}
-
-TD_EXTRA_FLAGS_FXO=
-TD_EXTRA_FLAGS_KPI2UDP=
-TD_DOWNLOAD_PATH=/lib/firmware/
-DEV_NODE_TERIDIAN=ter10
-
- # Show help
-help()
-{
- echo "Usage:"
- echo " - $0 WAN-IF-NAME - start TAPIDEMO without FXO support"
- echo " - $0 WAN-IF-NAME fxo - start TAPIDEMO with FXO support."
- echo " - $0 stop - stop TAPIDEMO"
-}
-
-# Check if device node for Teridian exists
-checkFxoSupport()
-{
- if [ ! -e /dev/$DEV_NODE_TERIDIAN ];then
- echo "FXO support is disabled. Can not find required driver's device node."
- else
- TD_EXTRA_FLAGS_FXO="-x"
- fi
-}
-
-# Check if module drv_kpi2udp is loaded
-checkKpi2UdpSupport()
-{
- tmp=`cat /proc/modules | grep 'drv_kpi2udp '`
- if [ "$tmp" != "" ]; then
- TD_EXTRA_FLAGS_KPI2UDP="-q"
- fi
-}
-
-start()
-{
- TD_WANIF=$1
-
- TD_WANIF_IP=`ifconfig $TD_WANIF | grep 'inet addr:' | cut -f2 -d: | cut -f1 -d' '`
- if [ "$TD_WANIF_IP" = "" ]; then
- echo "Error, getting IP address for network device $TD_WANIF failed."
- exit 1
- fi
-
- if [ "$2" = "" ];then
- # FXO support is disabled.
- continue
- elif [ "$2" = "fxo" ];then
- checkFxoSupport
- else
- echo "Error, unknown second parameter."
- help
- exit 1
- fi
-
- checkKpi2UdpSupport
-
- if [ -r /etc/rc.conf ]; then
- . /etc/rc.conf
- fi
-
- TD_DEBUG_LEVEL=$tapiDebugLevel
- if [ "$TD_DEBUG_LEVEL" = "" ]; then
- TD_DEBUG_LEVEL=3
- fi
-
- /usr/sbin/tapidemo -d $TD_DEBUG_LEVEL $TD_EXTRA_FLAGS_FXO $TD_EXTRA_FLAGS_KPI2UDP -i $TD_WANIF_IP -l $TD_DOWNLOAD_PATH &
-}
-
-stop()
-{
- killall tapidemo > /dev/null 2> /dev/null
-}
+++ /dev/null
---- a/src/board_easy50712.c
-+++ b/src/board_easy50712.c
-@@ -32,7 +32,9 @@
- #ifdef OLD_BSP
- #include "asm/danube/port.h"
- #else
-- #include "asm/ifx/ifx_gpio.h"
-+#ifdef FXO
-+# include "asm/ifx/ifx_gpio.h"
-+#endif
- #endif
-
- /* ============================= */
---- a/src/board_easy508xx.c
-+++ b/src/board_easy508xx.c
-@@ -32,8 +32,6 @@
- #endif /* FXO */
- #include "pcm.h"
-
--#include "asm/ifx/ifx_gpio.h"
--
- #ifdef TD_DECT
- #include "td_dect.h"
- #endif /* TD_DECT */
---- a/src/common.c
-+++ b/src/common.c
-@@ -7117,7 +7117,7 @@ IFX_return_t Common_GPIO_ClosePort(IFX_c
- IFX_return_t Common_GPIO_ReservePin(IFX_int32_t nFd, IFX_int32_t nPort,
- IFX_int32_t nPin, IFX_int32_t nModule)
- {
--#ifndef OLD_BSP
-+#if !defined(OLD_BSP) && defined(IFX_GPIO_IOC_PIN_RESERVE)
- TD_PARAMETER_CHECK((NO_GPIO_FD >= nFd), nFd, IFX_ERROR);
-
- IFX_return_t nRet;
-@@ -7155,7 +7155,7 @@ IFX_return_t Common_GPIO_ReservePin(IFX_
- IFX_return_t Common_GPIO_FreePin(IFX_int32_t nFd, IFX_int32_t nPort,
- IFX_int32_t nPin, IFX_int32_t nModule)
- {
--#ifndef OLD_BSP
-+#if !defined(OLD_BSP) && defined(IFX_GPIO_IOC_PIN_RESERVE)
- TD_PARAMETER_CHECK((NO_GPIO_FD >= nFd), nFd, IFX_ERROR);
-
- IFX_return_t nRet;
---- a/src/common.h
-+++ b/src/common.h
-@@ -79,12 +79,12 @@
- #ifdef OLD_BSP
- #include "asm/danube/port.h"
- #else
-- #include "asm/ifx/ifx_gpio.h"
-+ /*#include "asm/ifx/ifx_gpio.h"*/
- #endif
- #endif
-
- #if (defined(AR9) || defined(VR9))
-- #include "asm/ifx/ifx_gpio.h"
-+ /*#include "asm/ifx/ifx_gpio.h"*/
- #endif
-
- #ifdef TD_DECT
+++ /dev/null
---- a/configure.in
-+++ b/configure.in
-@@ -1665,6 +1665,30 @@ AC_ARG_WITH(cflags,
- ]
- )
-
-+dnl overwrite default FW file name
-+AC_ARG_WITH(fw-file,
-+ AS_HELP_STRING(
-+ [--with-fw-file=val],
-+ [overwrite default FW file name]
-+ ),
-+ [
-+ AC_MSG_RESULT([using firmware file $withval])
-+ AC_DEFINE_UNQUOTED([TD_FW_FILE], ["$withval"], [using firmware file])
-+ ]
-+)
-+
-+dnl overwrite default BBD file name
-+AC_ARG_WITH(bbd-file,
-+ AS_HELP_STRING(
-+ [--with-bbd-file=val],
-+ [overwrite default BBD file name]
-+ ),
-+ [
-+ AC_MSG_RESULT([using BBD file $withval])
-+ AC_DEFINE_UNQUOTED([TD_BBD_FILE], ["$withval"], [using BBD file])
-+ ]
-+)
-+
- AC_CONFIG_FILES([Makefile])
- AC_CONFIG_FILES([src/Makefile])
-
---- a/src/device_vmmc.c
-+++ b/src/device_vmmc.c
-@@ -49,40 +49,55 @@
-
-
- #ifdef USE_FILESYSTEM
-+#ifdef TD_BBD_FILE
-+ IFX_char_t* sBBD_CRAM_File_VMMC = TD_BBD_FILE;
-+ IFX_char_t* sBBD_CRAM_File_VMMC_Old = TD_BBD_FILE;
-+#else
-+ /** File holding coefficients. */
-+#ifdef DANUBE
-+ /** Prepare file names for DANUBE */
-+ IFX_char_t* sBBD_CRAM_File_VMMC = "danube_bbd.bin";
-+ IFX_char_t* sBBD_CRAM_File_VMMC_Old = "danube_bbd_fxs.bin";
-+#elif AR9
-+ IFX_char_t* sBBD_CRAM_File_VMMC = "ar9_bbd.bin";
-+ IFX_char_t* sBBD_CRAM_File_VMMC_Old = "ar9_bbd_fxs.bin";
-+#elif VINAX
-+ IFX_char_t* sBBD_CRAM_File_VMMC = "bbd.bin";
-+ IFX_char_t* sBBD_CRAM_File_VMMC_Old = "";
-+#elif VR9
-+ IFX_char_t* sBBD_CRAM_File_VMMC = "vr9_bbd.bin";
-+ IFX_char_t* sBBD_CRAM_File_VMMC_Old = "vr9_bbd_fxs.bin";
-+#else
-+#endif
-+#endif /* TD_BBD_FILE */
-+#ifdef TD_FW_FILE
-+ IFX_char_t* sPRAMFile_VMMC = TD_FW_FILE;
-+ IFX_char_t* sPRAMFile_VMMC_Old = TD_FW_FILE;
-+ IFX_char_t* sDRAMFile_VMMC = "";
-+#else
- #ifdef DANUBE
- /** Prepare file names for DANUBE */
- IFX_char_t* sPRAMFile_VMMC = "voice_danube_firmware.bin";
- IFX_char_t* sPRAMFile_VMMC_Old = "danube_firmware.bin";
- IFX_char_t* sDRAMFile_VMMC = "";
-- /** File holding coefficients. */
-- IFX_char_t* sBBD_CRAM_File_VMMC = "danube_bbd.bin";
-- IFX_char_t* sBBD_CRAM_File_VMMC_Old = "danube_bbd_fxs.bin";
- #elif AR9
- /** Prepare file names for AR9 */
- IFX_char_t* sPRAMFile_VMMC = "voice_ar9_firmware.bin";
- IFX_char_t* sPRAMFile_VMMC_Old = "ar9_firmware.bin";
- IFX_char_t* sDRAMFile_VMMC = "";
-- /** File holding coefficients. */
-- IFX_char_t* sBBD_CRAM_File_VMMC = "ar9_bbd.bin";
-- IFX_char_t* sBBD_CRAM_File_VMMC_Old = "ar9_bbd_fxs.bin";
- #elif VINAX
- /** Prepare file names for VINAX */
- IFX_char_t* sPRAMFile_VMMC = "voice_vinax_firmware.bin";
- IFX_char_t* sPRAMFile_VMMC_Old = "firmware.bin";
- IFX_char_t* sDRAMFile_VMMC = "";
-- /** File holding coefficients. */
-- IFX_char_t* sBBD_CRAM_File_VMMC = "bbd.bin";
-- IFX_char_t* sBBD_CRAM_File_VMMC_Old = "";
- #elif VR9
- /** Prepare file names for VR9 */
- IFX_char_t* sPRAMFile_VMMC = "voice_vr9_firmware.bin";
- IFX_char_t* sPRAMFile_VMMC_Old = "vr9_firmware.bin";
- IFX_char_t* sDRAMFile_VMMC = "";
-- /** File holding coefficients. */
-- IFX_char_t* sBBD_CRAM_File_VMMC = "vr9_bbd.bin";
-- IFX_char_t* sBBD_CRAM_File_VMMC_Old = "vr9_bbd_fxs.bin";
- #else
- #endif
-+#endif /* TD_FW_FILE */
- #endif /* USE_FILESYSTEM */
-
- /** Device names */
---- a/src/common.c
-+++ b/src/common.c
-@@ -509,6 +509,10 @@ IFX_return_t Common_CheckDownloadPath(IF
- if (IFX_TRUE != Common_FindBBD_CRAM(pCpuDevice, psPath, psFile))
- {
- ret = IFX_ERROR;
-+ if(bPrintTrace)
-+ TRACE(TAPIDEMO, DBG_LEVEL_LOW,
-+ ("Download path %s does not contain the required file %s.\n",
-+ psPath, psFile));
- }
-
- if ((IFX_SUCCESS == ret) &&
-@@ -521,6 +525,10 @@ IFX_return_t Common_CheckDownloadPath(IF
- {
- ret = Common_CheckFileExists(psFile);
- }
-+ if(bPrintTrace && ret != IFX_SUCCESS)
-+ TRACE(TAPIDEMO, DBG_LEVEL_LOW,
-+ ("Download path %s does not contain the required file %s.\n",
-+ psPath, psFile));
- }
- #ifndef TAPI_VERSION4
- if (IFX_SUCCESS == ret)
-@@ -532,13 +540,6 @@ IFX_return_t Common_CheckDownloadPath(IF
- }
- #endif
-
-- if (IFX_ERROR == ret)
-- {
-- if(bPrintTrace)
-- TRACE(TAPIDEMO, DBG_LEVEL_LOW,
-- ("Download path %s does not contain the required files.\n",
-- psPath));
-- }
-
- return ret;
- } /* Common_CheckDownloadPath */
+++ /dev/null
-#
-# Copyright (C) 2012 OpenWrt.org
-#
-# This is free software, licensed under the GNU General Public License v2.
-# See /LICENSE for more information.
-#
-
-include $(TOPDIR)/rules.mk
-
-OWSIP_VERSION=2012-02-14
-OWSIP_RELEASE=1
-
-PKG_NAME:=owsip
-PKG_VERSION:=$(OWSIP_VERSION)$(if $(OWSIP_RELEASE),.$(OWSIP_RELEASE))
-PKG_RELEASE:=1
-PKG_REV:=da53a53db28b47ca1714ffba72d0df5bea357706
-
-PKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.gz
-PKG_SOURCE_URL:=git://nbd.name/owsip.git
-PKG_SOURCE_SUBDIR:=owsip-$(PKG_VERSION)
-PKG_SOURCE_VERSION:=$(PKG_REV)
-PKG_SOURCE_PROTO:=git
-PKG_MIRROR_MD5SUM:=74b0ab930321c4f85f220ff3852e210a
-
-include $(INCLUDE_DIR)/ltqtapi.mk
-include $(INCLUDE_DIR)/package.mk
-
-define Package/owsip-template
- SUBMENU:=Telephony
- SECTION:=net
- CATEGORY:=Network
- TITLE:=owsip using $(2)
- VARIANT:=$(1)
- DEPENDS:=+librt +libuci +libubox +pjsip-$(1) $(3)
-endef
-
-Package/owsip-oss=$(call Package/owsip-template,oss,OSS,BROKEN)
-Package/owsip-ltq-tapi=$(call Package/owsip-template,ltq-tapi,Lantiq VMMC,$(LTQ_TAPI_DEPENDS) +kmod-ltq-kpi2udp)
-
-define Package/owsip-$(BUILD_VARIANT)/description
- OpenWrt sip daemon - $(BUILD_VARIANT)
-endef
-
-USE_LOCAL=$(shell ls ./src/ 2>/dev/null >/dev/null && echo 1)
-ifneq ($(USE_LOCAL),)
-define Build/Prepare
- $(CP) ./src/* $(PKG_BUILD_DIR)/
-endef
-endif
-
-EXTRA_CFLAGS=-I$(STAGING_DIR)/usr/include -I$(STAGING_DIR)/include \
- -I$(STAGING_DIR)/usr/pjsip-$(BUILD_VARIANT)/include
-EXTRA_LDFLAGS=-L$(STAGING_DIR)/usr/lib -L$(STAGING_DIR)/usr/pjsip-$(BUILD_VARIANT)/lib
-
-define Build/Compile
- PKG_CONFIG_PATH=$(STAGING_DIR)/usr/pjsip-$(BUILD_VARIANT)/lib/pkgconfig \
- BACKEND=$(BUILD_VARIANT) CFLAGS="$(EXTRA_CFLAGS)" LDFLAGS="$(EXTRA_LDFLAGS)" $(MAKE) -C $(PKG_BUILD_DIR) $(TARGET_CONFIGURE_OPTS)
-endef
-
-define Package/owsip-$(BUILD_VARIANT)/conffiles
-/etc/config/telephony.conf
-endef
-
-define Package/owsip-$(BUILD_VARIANT)/install
- $(INSTALL_DIR) $(1)/usr/bin $(1)/etc/init.d $(1)/etc/config $(1)/etc/uci-defaults
- $(INSTALL_BIN) $(PKG_BUILD_DIR)/owsip_ua $(1)/usr/bin
- $(INSTALL_BIN) ./files/telephony.init $(1)/etc/init.d/telephony
- $(INSTALL_DATA) ./files/telephony.conf $(1)/etc/config/telephony
- $(INSTALL_DATA) ./files/telephony.defaults $(1)/etc/uci-defaults/telephony
-endef
-
-$(eval $(call BuildPackage,owsip-oss))
-$(eval $(call BuildPackage,owsip-ltq-tapi))
+++ /dev/null
-config general general
- option name owsip
- option backend ltq_tapi
- option ossdev 0
- option log_level 3
- option interface nas0
- option local_port 5060
- option rtp_port 4000
- option locale germany
-
-config stun stun
- option host stun.myrealm.com
- option port 3478
-
-config account example1
- option realm myrealm1.com
- option username myuser1
- option password mypass1
- option disabled 1
-
-config account example2
- option realm myrealm2.com
- option username myuser2
- option password mypass2
- option disabled 1
-
-config contact
- option desc "example contact description"
- option code "example"
- option dial "0123456789"
- option type realm
-
+++ /dev/null
-#!/bin/sh
-#
-# Copyright (C) 2011 OpenWrt.org
-# based on ar71xx
-#
-
-COMMIT_TELEPHONY=0
-
-set_relay() {
- local cfg="relay_$1"
- local gpio=$1
- local val=$2
-
- uci -q get telephony.$cfg && return 0
-
- uci batch <<EOF
-set telephony.$cfg='relay'
-set telephony.$cfg.gpio='$gpio'
-set telephony.$cfg.value='$val'
-EOF
- COMMIT_TELEPHONY=1
-}
-
-set_port() {
- local cfg="port$1"
- local id=$1
- local led=$2
-
- uci -q get telephony.$cfg && return 0
-
- uci batch <<EOF
-set telephony.$cfg='port'
-set telephony.$cfg.id='$id'
-set telephony.$cfg.led='$led'
-set telephony.$cfg.noring='0'
-set telephony.$cfg.nodial='0'
-EOF
- COMMIT_TELEPHONY=1
-}
-
-. /lib/lantiq.sh
-
-board=$(lantiq_board_name)
-
-case "$board" in
-ARV7525PW)
- set_relay 31 1
- set_port 0 "soc:green:fxs1"
- #set_port 1 "soc:green:fxs2"
- ;;
-esac
-
-[ "$COMMIT_TELEPHONY" == "1" ] && uci commit telephony
-
-exit 0
+++ /dev/null
-#!/bin/sh /etc/rc.common
-START=80
-
-SERVICE_WRITE_PID=1
-SERVICE_DAEMONIZE=1
-SERVICE_PID_FILE=/var/run/owsip.pid
-
-. /lib/functions.sh
-
-relay_set () {
- local cfg="$1"
- local gpio value
-
- config_get gpio "$cfg" gpio
- config_get value "$cfg" value
- [ -n "gpio" ] || return 0
- [ ! -f "/sys/class/gpio/gpio$gpio/direction" ] &&
- echo "$gpio" > /sys/class/gpio/export
- [ -f "/sys/class/gpio/gpio$gpio/direction" ] && {
- echo "out" > /sys/class/gpio/gpio$gpio/direction
- echo "$value" > /sys/class/gpio/gpio$gpio/value
- }
-}
-
-start() {
- config_load telephony
- config_foreach relay_set relay
- service_start /usr/bin/owsip_ua
-}
-
-stop() {
- service_stop /usr/bin/owsip_ua
-}
+++ /dev/null
-#
-# Copyright (C) 2010-2012 OpenWrt.org
-#
-# This is free software, licensed under the GNU General Public License v2.
-# See /LICENSE for more information.
-#
-
-include $(TOPDIR)/rules.mk
-
-PKG_NAME:=pjsip
-PKG_VERSION:=1.14.2
-PKG_RELEASE:=1
-
-PKG_SOURCE:=pjproject-$(PKG_VERSION).tar.bz2
-PKG_SOURCE_URL:=http://www.pjsip.org/release/$(PKG_VERSION)/
-PKG_MD5SUM:=05428502384c16e7abd85f047e6e2f6c
-
-PKG_INSTALL:=1
-PKG_BUILD_PARALLEL:=1
-
-PKG_BUILD_DIR:=$(BUILD_DIR)/$(PKG_NAME)-$(BUILD_VARIANT)/pjproject-$(PKG_VERSION)
-
-include $(INCLUDE_DIR)/ltqtapi.mk
-PKG_BUILD_DEPENDS:=$(LTQ_TAPI_BUILD_DEPENDS)
-
-include $(INCLUDE_DIR)/package.mk
-
-define Package/pjsip-template
- SECTION:=lib
- CATEGORY:=Libraries
- URL:=http://www.pjsip.org/
- MAINTAINER:=John Crispin <blogic@openwrt.org>
- TITLE:=pjsip-$(1)
- VARIANT:=$(1)
- DEPENDS:=+libuuid $(2)
-endef
-
-CONFIGURE_PREFIX=/usr/pjsip-$(BUILD_VARIANT)
-
-ifeq ($(BUILD_VARIANT),oss)
-CONFIGURE_ARGS += \
- --disable-floating-point \
- --enable-g711-codec \
- --disable-l16-codec \
- --disable-g722-codec \
- --disable-g7221-codec \
- --disable-gsm-codec \
- --disable-ilbc-coder \
- --disable-libsamplerate \
- --disable-ipp \
- --disable-ssl \
- --enable-oss \
- --enable-sound
-endif
-
-ifeq ($(BUILD_VARIANT),ltq-tapi)
-CONFIGURE_ARGS += \
- --disable-floating-point \
- --enable-g711-codec \
- --disable-l16-codec \
- --disable-g722-codec \
- --disable-g7221-codec \
- --disable-ilbc-coder \
- --disable-gsm-codec \
- --disable-libsamplerate \
- --disable-ipp \
- --disable-ssl \
- --enable-sound \
- --enable-ltq-tapi
-EXTRA_CFLAGS:=-I$(STAGING_DIR)/usr/include/drv_tapi -I$(STAGING_DIR)/usr/include/drv_vmmc
-endif
-
-Package/pjsip-oss=$(call Package/pjsip-template,oss,BROKEN)
-Package/pjsip-ltq-tapi=$(call Package/pjsip-template,ltq-tapi,$(LTQ_TAPI_DEPENDS))
-
-USE_LOCAL=$(shell ls ./src/ 2>/dev/null >/dev/null && echo 1)
-ifneq ($(USE_LOCAL),)
-define Build/Prepare
- $(CP) ./src/* $(PKG_BUILD_DIR)
-endef
-endif
-
-define Build/Configure
- (cd $(PKG_BUILD_DIR); autoconf aconfigure.ac > aconfigure)
- $(call Build/Configure/Default)
-endef
-
-define Build/Compile
- +CFLAGS="$(TARGET_CFLAGS) $(EXTRA_CFLAGS) $(TARGET_CPPFLAGS) $(EXTRA_CPPFLAGS)" \
- CXXFLAGS="$(TARGET_CFLAGS) $(EXTRA_CFLAGS) $(TARGET_CPPFLAGS) $(EXTRA_CPPFLAGS)" \
- LDFLAGS="$(TARGET_LDFLAGS) -lc $(LIBGCC_S) -lm" \
- $(MAKE) $(PKG_JOBS) -C $(PKG_BUILD_DIR)/$(MAKE_PATH)
-endef
-
-define Build/InstallDev
- $(INSTALL_DIR) $(1)/usr
- $(CP) $(PKG_INSTALL_DIR)/usr/pjsip-$(BUILD_VARIANT) $(1)/usr
-endef
-
-$(eval $(call BuildPackage,pjsip-oss))
-$(eval $(call BuildPackage,pjsip-ltq-tapi))
+++ /dev/null
-Index: pjproject-1.14.2/aconfigure.ac
-===================================================================
---- pjproject-1.14.2.orig/aconfigure.ac 2012-04-27 03:22:15.000000000 +0200
-+++ pjproject-1.14.2/aconfigure.ac 2012-08-13 14:42:33.204641678 +0200
-@@ -48,9 +48,8 @@
- CROSS_COMPILE=`echo ${CC} | sed 's/gcc//'`
- fi
-
--if test "$AR" = ""; then AR="${CROSS_COMPILE}ar rv"; fi
-+AR="${AR} rv"
- AC_SUBST(AR)
--if test "$LD" = ""; then LD="$CC"; fi
- AC_SUBST(LD)
- if test "$LDOUT" = ""; then LDOUT="-o "; fi
- AC_SUBST(LDOUT)
-@@ -584,13 +583,7 @@
- ;;
- *)
- dnl # Check if ALSA is available
-- ac_pjmedia_snd=pa_unix
-- AC_CHECK_HEADER(alsa/version.h,
-- [AC_SUBST(ac_pa_use_alsa,1)
-- LIBS="$LIBS -lasound"
-- ],
-- [AC_SUBST(ac_pa_use_alsa,0)])
-- AC_MSG_RESULT([Checking sound device backend... unix])
-+ AC_SUBST(ac_pa_use_alsa,0)
-
- dnl # Check if OSS is disabled
- AC_SUBST(ac_pa_use_oss,1)
-@@ -617,6 +610,15 @@
- fi]
- )
-
-+AC_ARG_ENABLE(ltq_tapi,
-+ AC_HELP_STRING([--enable-ltq-tapi],
-+ [PJMEDIA will use ltq tapi backend]),
-+ [if test "$enable_ltq_tapi" = "yes"; then
-+ [ac_pjmedia_snd=ltqtapi]
-+ AC_MSG_RESULT([Checking if external sound is set... yes])
-+ fi]
-+ )
-+
- dnl # Include resampling small filter
- AC_SUBST(ac_no_small_filter)
- AC_ARG_ENABLE(small-filter,
-@@ -737,14 +739,6 @@
- AC_MSG_RESULT([Checking if iLBC codec is disabled...no]))
-
- dnl # Include libsamplerate
--AC_ARG_ENABLE(libsamplerate,
-- AC_HELP_STRING([--enable-libsamplerate],
-- [Link with libsamplerate when available. Note that PJMEDIA_RESAMPLE_IMP must also be configured]),
-- [ AC_CHECK_LIB(samplerate,src_new) ],
-- AC_MSG_RESULT([Skipping libsamplerate detection])
-- )
--
--dnl # Include libsamplerate
- AC_SUBST(ac_resample_dll)
- AC_ARG_ENABLE(resample_dll,
- AC_HELP_STRING([--enable-resample-dll],
-Index: pjproject-1.14.2/pjmedia/build/os-auto.mak.in
-===================================================================
---- pjproject-1.14.2.orig/pjmedia/build/os-auto.mak.in 2011-10-14 06:15:15.000000000 +0200
-+++ pjproject-1.14.2/pjmedia/build/os-auto.mak.in 2012-08-13 14:40:47.680637171 +0200
-@@ -125,4 +125,11 @@
- export CFLAGS += -DPJMEDIA_AUDIO_DEV_HAS_PORTAUDIO=0 -DPJMEDIA_AUDIO_DEV_HAS_WMME=0
- endif
-
--
-+#
-+# Lantiq tapi backend
-+#
-+ifeq ($(AC_PJMEDIA_SND),ltqtapi)
-+export CFLAGS += -DPJMEDIA_AUDIO_DEV_HAS_PORTAUDIO=0 -DPJMEDIA_AUDIO_DEV_HAS_WMME=0
-+export PJMEDIA_AUDIODEV_OBJS += tapi_dev.o
-+export CFLAGS += -DPJMEDIA_AUDIO_DEV_HAS_TAPI_DEVICE=1
-+endif
+++ /dev/null
---- a/pjmedia/src/pjmedia-audiodev/audiodev.c
-+++ b/pjmedia/src/pjmedia-audiodev/audiodev.c
-@@ -98,6 +98,10 @@ pjmedia_aud_dev_factory* pjmedia_symb_md
- pjmedia_aud_dev_factory* pjmedia_null_audio_factory(pj_pool_factory *pf);
- #endif
-
-+#if PJMEDIA_AUDIO_DEV_HAS_TAPI_DEVICE
-+pjmedia_aud_dev_factory* pjmedia_tapi_factory(pj_pool_factory *pf);
-+#endif
-+
- #define MAX_DRIVERS 16
- #define MAX_DEVS 64
-
-@@ -409,6 +413,9 @@ PJ_DEF(pj_status_t) pjmedia_aud_subsys_i
- #if PJMEDIA_AUDIO_DEV_HAS_NULL_AUDIO
- aud_subsys.drv[aud_subsys.drv_cnt++].create = &pjmedia_null_audio_factory;
- #endif
-+#if PJMEDIA_AUDIO_DEV_HAS_TAPI_DEVICE
-+ aud_subsys.drv[aud_subsys.drv_cnt++].create = &pjmedia_tapi_factory;
-+#endif
-
- /* Initialize each factory and build the device ID list */
- for (i=0; i<aud_subsys.drv_cnt; ++i) {
---- /dev/null
-+++ b/pjmedia/src/pjmedia-audiodev/tapi_dev.c
-@@ -0,0 +1,1307 @@
-+/******************************************************************************
-+
-+ Copyright (c) 2010
-+ Lantiq Deutschland GmbH
-+ Am Campeon 3; 85579 Neubiberg, Germany
-+
-+ For licensing information, see the file 'LICENSE' in the root folder of
-+ this software module.
-+
-+******************************************************************************/
-+#include <pjmedia-audiodev/audiodev_imp.h>
-+#include <pjmedia/errno.h>
-+#include <pj/assert.h>
-+#include <pj/pool.h>
-+#include <pj/log.h>
-+#include <pj/os.h>
-+
-+#if defined(PJMEDIA_AUDIO_DEV_HAS_TAPI_DEVICE) && PJMEDIA_AUDIO_DEV_HAS_TAPI_DEVICE
-+
-+/* Linux includes */
-+#include <stdio.h>
-+#include <string.h>
-+#include <stdlib.h>
-+#include <ctype.h>
-+#include <sys/stat.h>
-+#include <fcntl.h>
-+#include <sys/types.h>
-+#include <sys/ioctl.h>
-+#include <sys/select.h>
-+#include <sys/time.h>
-+#include <unistd.h>
-+#include <poll.h>
-+
-+/* TAPI includes */
-+#include "drv_tapi_io.h"
-+#include "vmmc_io.h"
-+
-+/* Maximum 2 devices */
-+#define TAPI_AUDIO_PORT_NUM 2
-+#define TAPI_BASE_NAME "TAPI"
-+#define TAPI_LL_DEV_BASE_PATH "/dev/vmmc"
-+#define TAPI_LL_DEV_FIRMWARE_NAME "/lib/firmware/danube_firmware.bin"
-+#define TAPI_LL_BBD_NAME "/lib/firmware/danube_bbd_fxs.bin"
-+
-+#define TAPI_LL_DEV_SELECT_TIMEOUT_MS 2000
-+#define TAPI_LL_DEV_MAX_PACKET_SIZE 800
-+#define TAPI_LL_DEV_RTP_HEADER_SIZE_BYTE 12
-+#define TAPI_LL_DEV_ENC_FRAME_LEN_MS 20
-+#define TAPI_LL_DEV_ENC_SMPL_PER_SEC 8000
-+#define TAPI_LL_DEV_ENC_BITS_PER_SMPLS 16
-+#define TAPI_LL_DEV_ENC_SMPL_PER_FRAME 160
-+#define TAPI_LL_DEV_ENC_BYTES_PER_FRAME (TAPI_LL_DEV_ENC_SMPL_PER_FRAME * (TAPI_LL_DEV_ENC_BITS_PER_SMPLS / 8))
-+
-+#define THIS_FILE "tapi_dev.c"
-+
-+/* Set to 1 to enable tracing */
-+#if 1
-+# define TRACE_(expr) PJ_LOG(1,expr)
-+#else
-+# define TRACE_(expr)
-+#endif
-+
-+pj_int32_t ch_fd[TAPI_AUDIO_PORT_NUM];
-+
-+typedef struct
-+{
-+ pj_int32_t dev_fd;
-+ pj_int32_t ch_fd[TAPI_AUDIO_PORT_NUM];
-+ pj_int8_t data2phone_map[TAPI_AUDIO_PORT_NUM];
-+} tapi_ctx;
-+
-+struct tapi_aud_factory
-+{
-+ pjmedia_aud_dev_factory base;
-+ pj_pool_t *pool;
-+ pj_pool_factory *pf;
-+ pj_uint32_t dev_count;
-+ pjmedia_aud_dev_info *dev_info;
-+ tapi_ctx dev_ctx;
-+};
-+
-+typedef struct tapi_aud_factory tapi_aud_factory_t;
-+
-+struct tapi_aud_stream
-+{
-+ pjmedia_aud_stream base;
-+ pj_pool_t *pool;
-+ pjmedia_aud_param param;
-+ pjmedia_aud_rec_cb rec_cb;
-+ pjmedia_aud_play_cb play_cb;
-+ void *user_data;
-+
-+ pj_thread_desc thread_desc;
-+ pj_thread_t *thread;
-+ tapi_ctx *dev_ctx;
-+ pj_uint8_t run_flag;
-+ pj_timestamp timestamp;
-+};
-+
-+typedef struct tapi_aud_stream tapi_aud_stream_t;
-+
-+/* Factory prototypes */
-+static pj_status_t factory_init(pjmedia_aud_dev_factory *f);
-+static pj_status_t factory_destroy(pjmedia_aud_dev_factory *f);
-+static unsigned factory_get_dev_count(pjmedia_aud_dev_factory *f);
-+static pj_status_t factory_get_dev_info(pjmedia_aud_dev_factory *f,
-+ unsigned index,
-+ pjmedia_aud_dev_info *info);
-+static pj_status_t factory_default_param(pjmedia_aud_dev_factory *f,
-+ unsigned index,
-+ pjmedia_aud_param *param);
-+static pj_status_t factory_create_stream(pjmedia_aud_dev_factory *f,
-+ const pjmedia_aud_param *param,
-+ pjmedia_aud_rec_cb rec_cb,
-+ pjmedia_aud_play_cb play_cb,
-+ void *user_data,
-+ pjmedia_aud_stream **p_aud_strm);
-+
-+/* Stream prototypes */
-+static pj_status_t stream_get_param(pjmedia_aud_stream *strm,
-+ pjmedia_aud_param *param);
-+static pj_status_t stream_get_cap(pjmedia_aud_stream *strm,
-+ pjmedia_aud_dev_cap cap,
-+ void *value);
-+static pj_status_t stream_set_cap(pjmedia_aud_stream *strm,
-+ pjmedia_aud_dev_cap cap,
-+ const void *value);
-+static pj_status_t stream_start(pjmedia_aud_stream *strm);
-+static pj_status_t stream_stop(pjmedia_aud_stream *strm);
-+static pj_status_t stream_destroy(pjmedia_aud_stream *strm);
-+
-+static pjmedia_aud_dev_factory_op tapi_fact_op =
-+{
-+ &factory_init,
-+ &factory_destroy,
-+ &factory_get_dev_count,
-+ &factory_get_dev_info,
-+ &factory_default_param,
-+ &factory_create_stream
-+};
-+
-+static pjmedia_aud_stream_op tapi_strm_op =
-+{
-+ &stream_get_param,
-+ &stream_get_cap,
-+ &stream_set_cap,
-+ &stream_start,
-+ &stream_stop,
-+ &stream_destroy
-+};
-+
-+/* TAPI configuration */
-+static struct tapi_aud_stream streams[TAPI_AUDIO_PORT_NUM];
-+
-+void (*tapi_digit_callback)(pj_uint8_t port, pj_uint8_t digit) = NULL;
-+void (*tapi_hook_callback)(pj_uint8_t port, pj_uint8_t event) = NULL;
-+
-+#define TAPI_TONE_LOCALE_NONE 32
-+#define TAPI_TONE_LOCALE_BUSY_CODE 33
-+#define TAPI_TONE_LOCALE_CONGESTION_CODE 34
-+#define TAPI_TONE_LOCALE_DIAL_CODE 35
-+#define TAPI_TONE_LOCALE_RING_CODE 36
-+#define TAPI_TONE_LOCALE_WAITING_CODE 37
-+
-+static pj_uint8_t tapi_channel_revert = 0;
-+static pj_uint8_t tapi_cid_type = 0;
-+static pj_uint8_t tapi_locale = 0;
-+
-+void tapi_revert_channels(void)
-+{
-+ tapi_channel_revert = 1;
-+ PJ_LOG(3, (THIS_FILE, "using reverted configuration for TAPI channels"));
-+}
-+
-+void tapi_cid_select(char *cid)
-+{
-+ if (!stricmp(cid, "telecordia")) {
-+ tapi_cid_type = IFX_TAPI_CID_STD_TELCORDIA;
-+ PJ_LOG(3, (THIS_FILE, "using TELECORDIA configuration for TAPI CID"));
-+ } else if (!stricmp(cid, "etsi_fsk")) {
-+ tapi_cid_type = IFX_TAPI_CID_STD_ETSI_FSK;
-+ PJ_LOG(3, (THIS_FILE, "using ETSI FSK configuration for TAPI CID"));
-+ } else if (!stricmp(cid, "etsi_dtmf")) {
-+ tapi_cid_type = IFX_TAPI_CID_STD_ETSI_DTMF;
-+ PJ_LOG(3, (THIS_FILE, "using ETSI DTMF configuration for TAPI CID"));
-+ } else if (!stricmp(cid, "sin")) {
-+ tapi_cid_type = IFX_TAPI_CID_STD_SIN;
-+ PJ_LOG(3, (THIS_FILE, "using SIN CID configuration for TAPI CID"));
-+ } else if (!stricmp(cid, "ntt")) {
-+ tapi_cid_type = IFX_TAPI_CID_STD_NTT;
-+ PJ_LOG(3, (THIS_FILE, "using NTT configuration for TAPI CID"));
-+ } else if (!stricmp(cid, "kpn_dtmf")) {
-+ tapi_cid_type = IFX_TAPI_CID_STD_KPN_DTMF;
-+ PJ_LOG(3, (THIS_FILE, "using KPN DTMF configuration for TAPI CID"));
-+ } else if (!stricmp(cid, "kpn_dtmf_fsk")) {
-+ tapi_cid_type = IFX_TAPI_CID_STD_KPN_DTMF_FSK;
-+ PJ_LOG(3, (THIS_FILE, "using KPN DTMF FSK configuration for TAPI CID"));
-+ }
-+}
-+
-+void tapi_locale_select(char *country)
-+{
-+ IFX_TAPI_TONE_t tone;
-+ pj_status_t status;
-+ pj_uint8_t c;
-+
-+ tapi_locale = 1;
-+
-+ if (!stricmp(country, "croatia")) {
-+ PJ_LOG(3, (THIS_FILE, "using localized tones for Croatia"));
-+
-+ memset(&tone, 0, sizeof(IFX_TAPI_TONE_t));
-+ tone.simple.format = IFX_TAPI_TONE_TYPE_SIMPLE;
-+ tone.simple.index = TAPI_TONE_LOCALE_BUSY_CODE;
-+ tone.simple.freqA = 425;
-+ tone.simple.levelA = 0;
-+ tone.simple.cadence[0] = 500;
-+ tone.simple.cadence[1] = 500;
-+ tone.simple.frequencies[0] = IFX_TAPI_TONE_FREQA;
-+ tone.simple.frequencies[1] = IFX_TAPI_TONE_FREQNONE;
-+ tone.simple.loop = 0;
-+ tone.simple.pause = 0;
-+ for (c = 0; c < TAPI_AUDIO_PORT_NUM; c++) {
-+ status = ioctl(ch_fd[c], IFX_TAPI_TONE_TABLE_CFG_SET, &tone);
-+ if (status != PJ_SUCCESS)
-+ TRACE_((THIS_FILE, "IFX_TAPI_TONE_TABLE_CFG_SET failed!\n"));
-+ }
-+
-+ memset(&tone, 0, sizeof(IFX_TAPI_TONE_t));
-+ tone.simple.format = IFX_TAPI_TONE_TYPE_SIMPLE;
-+ tone.simple.index = TAPI_TONE_LOCALE_CONGESTION_CODE;
-+ tone.simple.freqA = 425;
-+ tone.simple.levelA = 0;
-+ tone.simple.cadence[0] = 250;
-+ tone.simple.cadence[1] = 250;
-+ tone.simple.frequencies[0] = IFX_TAPI_TONE_FREQA;
-+ tone.simple.frequencies[1] = IFX_TAPI_TONE_FREQNONE;
-+ tone.simple.loop = 0;
-+ tone.simple.pause = 0;
-+ for (c = 0; c < TAPI_AUDIO_PORT_NUM; c++) {
-+ status = ioctl(ch_fd[c], IFX_TAPI_TONE_TABLE_CFG_SET, &tone);
-+ if (status != PJ_SUCCESS)
-+ TRACE_((THIS_FILE, "IFX_TAPI_TONE_TABLE_CFG_SET failed!\n"));
-+ }
-+
-+ memset(&tone, 0, sizeof(IFX_TAPI_TONE_t));
-+ tone.simple.format = IFX_TAPI_TONE_TYPE_SIMPLE;
-+ tone.simple.index = TAPI_TONE_LOCALE_DIAL_CODE;
-+ tone.simple.freqA = 425;
-+ tone.simple.levelA = 0;
-+ tone.simple.cadence[0] = 200;
-+ tone.simple.cadence[1] = 300;
-+ tone.simple.cadence[2] = 700;
-+ tone.simple.cadence[3] = 800;
-+ tone.simple.frequencies[0] = IFX_TAPI_TONE_FREQA;
-+ tone.simple.frequencies[1] = IFX_TAPI_TONE_FREQNONE;
-+ tone.simple.frequencies[2] = IFX_TAPI_TONE_FREQA;
-+ tone.simple.frequencies[3] = IFX_TAPI_TONE_FREQNONE;
-+ tone.simple.loop = 0;
-+ tone.simple.pause = 0;
-+ for (c = 0; c < TAPI_AUDIO_PORT_NUM; c++) {
-+ status = ioctl(ch_fd[c], IFX_TAPI_TONE_TABLE_CFG_SET, &tone);
-+ if (status != PJ_SUCCESS)
-+ TRACE_((THIS_FILE, "IFX_TAPI_TONE_TABLE_CFG_SET failed!\n"));
-+ }
-+
-+ memset(&tone, 0, sizeof(IFX_TAPI_TONE_t));
-+ tone.simple.format = IFX_TAPI_TONE_TYPE_SIMPLE;
-+ tone.simple.index = TAPI_TONE_LOCALE_RING_CODE;
-+ tone.simple.freqA = 425;
-+ tone.simple.levelA = 0;
-+ tone.simple.cadence[0] = 1000;
-+ tone.simple.cadence[1] = 4000;
-+ tone.simple.frequencies[0] = IFX_TAPI_TONE_FREQA;
-+ tone.simple.frequencies[1] = IFX_TAPI_TONE_FREQNONE;
-+ tone.simple.loop = 0;
-+ tone.simple.pause = 0;
-+ for (c = 0; c < TAPI_AUDIO_PORT_NUM; c++) {
-+ status = ioctl(ch_fd[c], IFX_TAPI_TONE_TABLE_CFG_SET, &tone);
-+ if (status != PJ_SUCCESS)
-+ TRACE_((THIS_FILE, "IFX_TAPI_TONE_TABLE_CFG_SET failed!\n"));
-+ }
-+
-+ memset(&tone, 0, sizeof(IFX_TAPI_TONE_t));
-+ tone.simple.format = IFX_TAPI_TONE_TYPE_SIMPLE;
-+ tone.simple.index = TAPI_TONE_LOCALE_WAITING_CODE;
-+ tone.simple.freqA = 425;
-+ tone.simple.levelA = 0;
-+ tone.simple.cadence[0] = 300;
-+ tone.simple.cadence[1] = 8000;
-+ tone.simple.frequencies[0] = IFX_TAPI_TONE_FREQA;
-+ tone.simple.frequencies[1] = IFX_TAPI_TONE_FREQNONE;
-+ tone.simple.loop = 0;
-+ tone.simple.pause = 0;
-+ for (c = 0; c < TAPI_AUDIO_PORT_NUM; c++) {
-+ status = ioctl(ch_fd[c], IFX_TAPI_TONE_TABLE_CFG_SET, &tone);
-+ if (status != PJ_SUCCESS)
-+ TRACE_((THIS_FILE, "IFX_TAPI_TONE_TABLE_CFG_SET failed!\n"));
-+ }
-+ } else if (!stricmp(country, "germany")) {
-+ PJ_LOG(3, (THIS_FILE, "using localized tones for Germany"));
-+
-+ memset(&tone, 0, sizeof(IFX_TAPI_TONE_t));
-+ tone.simple.format = IFX_TAPI_TONE_TYPE_SIMPLE;
-+ tone.simple.index = TAPI_TONE_LOCALE_BUSY_CODE;
-+ tone.simple.freqA = 425;
-+ tone.simple.levelA = 0;
-+ tone.simple.cadence[0] = 480;
-+ tone.simple.cadence[1] = 480;
-+ tone.simple.frequencies[0] = IFX_TAPI_TONE_FREQA;
-+ tone.simple.frequencies[1] = IFX_TAPI_TONE_FREQNONE;
-+ tone.simple.loop = 0;
-+ tone.simple.pause = 0;
-+ for (c = 0; c < TAPI_AUDIO_PORT_NUM; c++) {
-+ status = ioctl(ch_fd[c], IFX_TAPI_TONE_TABLE_CFG_SET, &tone);
-+ if (status != PJ_SUCCESS)
-+ TRACE_((THIS_FILE, "IFX_TAPI_TONE_TABLE_CFG_SET failed!\n"));
-+ }
-+
-+ memset(&tone, 0, sizeof(IFX_TAPI_TONE_t));
-+ tone.simple.format = IFX_TAPI_TONE_TYPE_SIMPLE;
-+ tone.simple.index = TAPI_TONE_LOCALE_CONGESTION_CODE;
-+ tone.simple.freqA = 425;
-+ tone.simple.levelA = 0;
-+ tone.simple.cadence[0] = 240;
-+ tone.simple.cadence[1] = 240;
-+ tone.simple.frequencies[0] = IFX_TAPI_TONE_FREQA;
-+ tone.simple.frequencies[1] = IFX_TAPI_TONE_FREQNONE;
-+ tone.simple.loop = 0;
-+ tone.simple.pause = 0;
-+ for (c = 0; c < TAPI_AUDIO_PORT_NUM; c++) {
-+ status = ioctl(ch_fd[c], IFX_TAPI_TONE_TABLE_CFG_SET, &tone);
-+ if (status != PJ_SUCCESS)
-+ TRACE_((THIS_FILE, "IFX_TAPI_TONE_TABLE_CFG_SET failed!\n"));
-+ }
-+
-+ memset(&tone, 0, sizeof(IFX_TAPI_TONE_t));
-+ tone.simple.format = IFX_TAPI_TONE_TYPE_SIMPLE;
-+ tone.simple.index = TAPI_TONE_LOCALE_DIAL_CODE;
-+ tone.simple.freqA = 425;
-+ tone.simple.levelA = 0;
-+ tone.simple.cadence[0] = 1000;
-+ tone.simple.frequencies[0] = IFX_TAPI_TONE_FREQA;
-+ tone.simple.loop = 0;
-+ tone.simple.pause = 0;
-+ for (c = 0; c < TAPI_AUDIO_PORT_NUM; c++) {
-+ status = ioctl(ch_fd[c], IFX_TAPI_TONE_TABLE_CFG_SET, &tone);
-+ if (status != PJ_SUCCESS)
-+ TRACE_((THIS_FILE, "IFX_TAPI_TONE_TABLE_CFG_SET failed!\n"));
-+ }
-+
-+ memset(&tone, 0, sizeof(IFX_TAPI_TONE_t));
-+ tone.simple.format = IFX_TAPI_TONE_TYPE_SIMPLE;
-+ tone.simple.index = TAPI_TONE_LOCALE_RING_CODE;
-+ tone.simple.freqA = 425;
-+ tone.simple.levelA = 0;
-+ tone.simple.cadence[0] = 1000;
-+ tone.simple.cadence[1] = 4000;
-+ tone.simple.frequencies[0] = IFX_TAPI_TONE_FREQA;
-+ tone.simple.frequencies[1] = IFX_TAPI_TONE_FREQNONE;
-+ tone.simple.loop = 0;
-+ tone.simple.pause = 0;
-+ for (c = 0; c < TAPI_AUDIO_PORT_NUM; c++) {
-+ status = ioctl(ch_fd[c], IFX_TAPI_TONE_TABLE_CFG_SET, &tone);
-+ if (status != PJ_SUCCESS)
-+ TRACE_((THIS_FILE, "IFX_TAPI_TONE_TABLE_CFG_SET failed!\n"));
-+ }
-+
-+ memset(&tone, 0, sizeof(IFX_TAPI_TONE_t));
-+ tone.simple.format = IFX_TAPI_TONE_TYPE_SIMPLE;
-+ tone.simple.index = TAPI_TONE_LOCALE_WAITING_CODE;
-+ tone.simple.freqA = 425;
-+ tone.simple.levelA = 0;
-+ tone.simple.cadence[0] = 200;
-+ tone.simple.cadence[1] = 200;
-+ tone.simple.cadence[2] = 200;
-+ tone.simple.cadence[3] = 5000;
-+ tone.simple.frequencies[0] = IFX_TAPI_TONE_FREQA;
-+ tone.simple.frequencies[1] = IFX_TAPI_TONE_FREQNONE;
-+ tone.simple.frequencies[2] = IFX_TAPI_TONE_FREQA;
-+ tone.simple.frequencies[3] = IFX_TAPI_TONE_FREQNONE;
-+ tone.simple.loop = 0;
-+ tone.simple.pause = 0;
-+ for (c = 0; c < TAPI_AUDIO_PORT_NUM; c++) {
-+ status = ioctl(ch_fd[c], IFX_TAPI_TONE_TABLE_CFG_SET, &tone);
-+ if (status != PJ_SUCCESS)
-+ TRACE_((THIS_FILE, "IFX_TAPI_TONE_TABLE_CFG_SET failed!\n"));
-+ }
-+ }
-+}
-+
-+static pj_int32_t
-+tapi_dev_open(char* dev_path, const pj_int32_t ch_num)
-+{
-+ char devname[128] = { 0 };
-+ pj_ansi_sprintf(devname,"%s%u%u", dev_path, 1, ch_num);
-+ return open((const char*)devname, O_RDWR, 0644);
-+}
-+
-+static pj_status_t
-+tapi_dev_binary_buffer_create(const char *pPath, pj_uint8_t **ppBuf, pj_uint32_t *pBufSz)
-+{
-+ pj_status_t status = PJ_SUCCESS;
-+ FILE *fd;
-+ struct stat file_stat;
-+
-+ fd = fopen(pPath, "rb");
-+ if (fd == NULL) {
-+ TRACE_((THIS_FILE, "ERROR - binary file %s open failed!\n", pPath));
-+ return PJ_EUNKNOWN;
-+ }
-+
-+ if (stat(pPath, &file_stat) != 0) {
-+ TRACE_((THIS_FILE, "ERROR - file %s statistics get failed!\n", pPath));
-+ return PJ_EUNKNOWN;
-+ }
-+
-+ *ppBuf = malloc(file_stat.st_size);
-+ if (*ppBuf == NULL) {
-+ TRACE_((THIS_FILE, "ERROR - binary file %s memory allocation failed!\n", pPath));
-+ status = PJ_EUNKNOWN;
-+ goto on_exit;
-+ }
-+
-+ if (fread (*ppBuf, sizeof(pj_uint8_t), file_stat.st_size, fd) <= 0) {
-+ TRACE_((THIS_FILE, "ERROR - file %s read failed!\n", pPath));
-+ status = PJ_EUNKNOWN;
-+ goto on_exit;
-+ }
-+
-+ *pBufSz = file_stat.st_size;
-+
-+on_exit:
-+ if (fd != NULL)
-+ fclose(fd);
-+
-+ if (*ppBuf != NULL && status != PJ_SUCCESS)
-+ free(*ppBuf);
-+
-+ return status;
-+}
-+
-+static void
-+tapi_dev_binary_buffer_delete(pj_uint8_t *pBuf)
-+{
-+ if (pBuf != NULL)
-+ free(pBuf);
-+}
-+
-+static pj_status_t
-+tapi_dev_firmware_download(pj_int32_t fd, const char *pPath)
-+{
-+ pj_status_t status = PJ_SUCCESS;
-+ pj_uint8_t *pFirmware = NULL;
-+ pj_uint32_t binSz = 0;
-+ VMMC_IO_INIT vmmc_io_init;
-+
-+ status = tapi_dev_binary_buffer_create(pPath, &pFirmware, &binSz);
-+ if (status != PJ_SUCCESS) {
-+ TRACE_((THIS_FILE, "ERROR - binary buffer create failed!\n"));
-+ return PJ_EUNKNOWN;
-+ }
-+
-+ memset(&vmmc_io_init, 0, sizeof(VMMC_IO_INIT));
-+ vmmc_io_init.pPRAMfw = pFirmware;
-+ vmmc_io_init.pram_size = binSz;
-+
-+ status = ioctl(fd, FIO_FW_DOWNLOAD, &vmmc_io_init);
-+ if (status != PJ_SUCCESS)
-+ TRACE_((THIS_FILE, "ERROR - FIO_FW_DOWNLOAD ioctl failed!"));
-+
-+ tapi_dev_binary_buffer_delete(pFirmware);
-+
-+ return status;
-+}
-+
-+/* NOT USED */
-+#if 0
-+static int
-+tapi_dev_bbd_download(int fd, const char *pPath)
-+{
-+ int status = PJ_SUCCESS;
-+ unsigned char *pFirmware = NULL;
-+ unsigned int binSz = 0;
-+ VMMC_DWLD_t bbd_data;
-+
-+
-+ /* Create binary buffer */
-+ status = tapi_dev_binary_buffer_create(pPath, &pFirmware, &binSz);
-+ if (status != PJ_SUCCESS) {
-+ TRACE_((THIS_FILE, "ERROR - binary buffer create failed!\n"));
-+ return status;
-+ }
-+
-+ /* Download Voice Firmware */
-+ memset(&bbd_data, 0, sizeof(VMMC_DWLD_t));
-+ bbd_data.buf = pFirmware;
-+ bbd_data.size = binSz;
-+
-+ status = ioctl(fd, FIO_BBD_DOWNLOAD, &bbd_data);
-+ if (status != PJ_SUCCESS) {
-+ TRACE_((THIS_FILE, "ERROR - FIO_BBD_DOWNLOAD failed!\n"));
-+ }
-+
-+ /* Delete binary buffer */
-+ tapi_dev_binary_buffer_delete(pFirmware);
-+
-+ return status;
-+}
-+#endif
-+
-+static pj_status_t tapi_dev_start(tapi_aud_factory_t *f)
-+{
-+ pj_uint8_t c, hook_status;
-+ IFX_TAPI_TONE_t tone;
-+ IFX_TAPI_DEV_START_CFG_t tapistart;
-+ IFX_TAPI_MAP_DATA_t datamap;
-+ IFX_TAPI_ENC_CFG_t enc_cfg;
-+ IFX_TAPI_LINE_VOLUME_t line_vol;
-+ IFX_TAPI_WLEC_CFG_t lec_cfg;
-+ IFX_TAPI_JB_CFG_t jb_cfg;
-+ IFX_TAPI_CID_CFG_t cid_cfg;
-+ pj_status_t status;
-+
-+ /* Open device */
-+ f->dev_ctx.dev_fd = tapi_dev_open(TAPI_LL_DEV_BASE_PATH, 0);
-+
-+ if (f->dev_ctx.dev_fd < 0) {
-+ TRACE_((THIS_FILE, "ERROR - TAPI device open failed!"));
-+ return PJ_EUNKNOWN;
-+ }
-+
-+ for (c = 0; c < TAPI_AUDIO_PORT_NUM; c++) {
-+ if (tapi_channel_revert)
-+ ch_fd[c] = f->dev_ctx.ch_fd[c] = tapi_dev_open(TAPI_LL_DEV_BASE_PATH, c + 1);
-+ else
-+ ch_fd[c] = f->dev_ctx.ch_fd[c] = tapi_dev_open(TAPI_LL_DEV_BASE_PATH, TAPI_AUDIO_PORT_NUM - c);
-+
-+ if (f->dev_ctx.dev_fd < 0) {
-+ TRACE_((THIS_FILE, "ERROR - TAPI channel%d open failed!", c));
-+ return PJ_EUNKNOWN;
-+ }
-+ if (tapi_channel_revert)
-+ f->dev_ctx.data2phone_map[c] = c & 0x1 ? 1 : 0;
-+ else
-+ f->dev_ctx.data2phone_map[c] = c & 0x1 ? 0 : 1;
-+ }
-+
-+ status = tapi_dev_firmware_download(f->dev_ctx.dev_fd, TAPI_LL_DEV_FIRMWARE_NAME);
-+ if (status != PJ_SUCCESS) {
-+ TRACE_((THIS_FILE, "ERROR - Voice Firmware Download failed!"));
-+ return PJ_EUNKNOWN;
-+ }
-+
-+ /* Download coefficients */
-+ /*
-+ status = tapi_dev_bbd_download(f->dev_ctx.dev_fd, TAPI_LL_BBD_NAME);
-+ if (status != PJ_SUCCESS) {
-+ TRACE_((THIS_FILE, "ERROR - Voice Coefficients Download failed!"));
-+ return PJ_EUNKNOWN;
-+ }
-+ */
-+
-+ memset(&tapistart, 0x0, sizeof(IFX_TAPI_DEV_START_CFG_t));
-+ tapistart.nMode = IFX_TAPI_INIT_MODE_VOICE_CODER;
-+
-+ /* Start TAPI */
-+ status = ioctl(f->dev_ctx.dev_fd, IFX_TAPI_DEV_START, &tapistart);
-+ if (status != PJ_SUCCESS) {
-+ TRACE_((THIS_FILE, "ERROR - IFX_TAPI_DEV_START ioctl failed"));
-+ return PJ_EUNKNOWN;
-+ }
-+
-+
-+ /* OpenWrt default tone */
-+ memset(&tone, 0, sizeof(IFX_TAPI_TONE_t));
-+ tone.simple.format = IFX_TAPI_TONE_TYPE_SIMPLE;
-+ tone.simple.index = TAPI_TONE_LOCALE_NONE;
-+ tone.simple.freqA = 400;
-+ tone.simple.levelA = 0;
-+ tone.simple.freqB = 450;
-+ tone.simple.levelB = 0;
-+ tone.simple.freqC = 550;
-+ tone.simple.levelC = 0;
-+ tone.simple.freqD = 600;
-+ tone.simple.levelD = 0;
-+ tone.simple.cadence[0] = 100;
-+ tone.simple.cadence[1] = 150;
-+ tone.simple.cadence[2] = 100;
-+ tone.simple.cadence[3] = 150;
-+ tone.simple.frequencies[0] = IFX_TAPI_TONE_FREQA | IFX_TAPI_TONE_FREQB;
-+ tone.simple.frequencies[1] = IFX_TAPI_TONE_FREQNONE;
-+ tone.simple.frequencies[2] = IFX_TAPI_TONE_FREQC | IFX_TAPI_TONE_FREQD;
-+ tone.simple.frequencies[3] = IFX_TAPI_TONE_FREQNONE;
-+ tone.simple.loop = 0;
-+ tone.simple.pause = 0;
-+ for (c = 0; c < TAPI_AUDIO_PORT_NUM; c++) {
-+ /* OpenWrt default tone */
-+ status = ioctl(ch_fd[c], IFX_TAPI_TONE_TABLE_CFG_SET, &tone);
-+ if (status != PJ_SUCCESS)
-+ TRACE_((THIS_FILE, "IFX_TAPI_TONE_TABLE_CFG_SET failed!\n"));
-+
-+ /* Perform mapping */
-+ memset(&datamap, 0x0, sizeof(IFX_TAPI_MAP_DATA_t));
-+ datamap.nDstCh = f->dev_ctx.data2phone_map[c];
-+ datamap.nChType = IFX_TAPI_MAP_TYPE_PHONE;
-+
-+ status = ioctl(f->dev_ctx.ch_fd[c], IFX_TAPI_MAP_DATA_ADD, &datamap);
-+ if (status != PJ_SUCCESS) {
-+ TRACE_((THIS_FILE, "ERROR - IFX_TAPI_MAP_DATA_ADD ioctl failed"));
-+ return PJ_EUNKNOWN;
-+ }
-+
-+ /* Set Line feed */
-+ status = ioctl(f->dev_ctx.ch_fd[c], IFX_TAPI_LINE_FEED_SET, IFX_TAPI_LINE_FEED_STANDBY);
-+ if (status != PJ_SUCCESS) {
-+ TRACE_((THIS_FILE, "ERROR - IFX_TAPI_LINE_FEED_SET ioctl failed"));
-+ return PJ_EUNKNOWN;
-+ }
-+
-+ /* Configure encoder for linear stream */
-+ memset(&enc_cfg, 0x0, sizeof(IFX_TAPI_ENC_CFG_t));
-+ enc_cfg.nFrameLen = IFX_TAPI_COD_LENGTH_20;
-+ enc_cfg.nEncType = IFX_TAPI_COD_TYPE_LIN16_8;
-+
-+ status = ioctl(f->dev_ctx.ch_fd[c], IFX_TAPI_ENC_CFG_SET, &enc_cfg);
-+ if (status != PJ_SUCCESS) {
-+ TRACE_((THIS_FILE, "ERROR - IFX_TAPI_ENC_CFG_SET ioctl failed"));
-+ return PJ_EUNKNOWN;
-+ }
-+
-+ /* Suppress TAPI volume, otherwise PJSIP starts autogeneration */
-+ memset(&line_vol, 0, sizeof(line_vol));
-+ line_vol.nGainRx = -8;
-+ line_vol.nGainTx = -8;
-+
-+ status = ioctl(f->dev_ctx.ch_fd[c], IFX_TAPI_PHONE_VOLUME_SET, &line_vol);
-+ if (status != PJ_SUCCESS) {
-+ TRACE_((THIS_FILE, "ERROR - IFX_TAPI_PHONE_VOLUME_SET ioctl failed"));
-+ return PJ_EUNKNOWN;
-+ }
-+
-+ /* Configure line echo canceller */
-+ memset(&lec_cfg, 0, sizeof(lec_cfg));
-+ lec_cfg.nType = IFX_TAPI_WLEC_TYPE_NFE;
-+ lec_cfg.bNlp = IFX_TAPI_LEC_NLP_OFF;
-+
-+ status = ioctl(f->dev_ctx.ch_fd[c], IFX_TAPI_WLEC_PHONE_CFG_SET, &lec_cfg);
-+ if (status != PJ_SUCCESS) {
-+ TRACE_((THIS_FILE, "ERROR - IFX_TAPI_WLEC_PHONE_CFG_SET ioctl failed"));
-+ return PJ_EUNKNOWN;
-+ }
-+
-+ /* Configure jitter buffer */
-+ memset(&jb_cfg, 0, sizeof(jb_cfg));
-+ jb_cfg.nJbType = IFX_TAPI_JB_TYPE_ADAPTIVE;
-+ jb_cfg.nPckAdpt = IFX_TAPI_JB_PKT_ADAPT_VOICE;
-+ jb_cfg.nLocalAdpt = IFX_TAPI_JB_LOCAL_ADAPT_ON;
-+ jb_cfg.nScaling = 0x10;
-+ jb_cfg.nInitialSize = 0x2d0;
-+ jb_cfg.nMinSize = 0x50;
-+ jb_cfg.nMaxSize = 0x5a0;
-+
-+ status = ioctl(f->dev_ctx.ch_fd[c], IFX_TAPI_JB_CFG_SET, &jb_cfg);
-+ if (status != PJ_SUCCESS) {
-+ TRACE_((THIS_FILE, "ERROR - IFX_TAPI_JB_CFG_SET ioctl failed"));
-+ return PJ_EUNKNOWN;
-+ }
-+
-+ /* Configure Caller ID type */
-+ if (tapi_cid_type) {
-+ memset(&cid_cfg, 0, sizeof(cid_cfg));
-+ cid_cfg.nStandard = tapi_cid_type;
-+ status = ioctl(f->dev_ctx.ch_fd[c], IFX_TAPI_CID_CFG_SET, &cid_cfg);
-+ if (status != PJ_SUCCESS) {
-+ TRACE_((THIS_FILE, "ERROR - IFX_TAPI_CID_CFG_SET ioctl failed"));
-+ return PJ_EUNKNOWN;
-+ }
-+ }
-+
-+ /* check hook status */
-+ hook_status = 0;
-+ status = ioctl(f->dev_ctx.ch_fd[c], IFX_TAPI_LINE_HOOK_STATUS_GET, &hook_status);
-+ if (status != PJ_SUCCESS) {
-+ TRACE_((THIS_FILE, "ERROR - IFX_TAPI_LINE_HOOK_STATUS_GET ioctl failed!"));
-+ return PJ_EUNKNOWN;
-+ }
-+
-+ /* if off hook do initialization */
-+ if (hook_status) {
-+ status = ioctl(f->dev_ctx.ch_fd[c], IFX_TAPI_LINE_FEED_SET, IFX_TAPI_LINE_FEED_ACTIVE);
-+ if (status != PJ_SUCCESS) {
-+ TRACE_((THIS_FILE, "ERROR - IFX_TAPI_LINE_FEED_SET ioctl failed!"));
-+ return PJ_EUNKNOWN;
-+ }
-+ status = ioctl(c, IFX_TAPI_ENC_START, 0);
-+ if (status != PJ_SUCCESS) {
-+ TRACE_((THIS_FILE, "ERROR - IFX_TAPI_ENC_START ioctl failed!"));
-+ return PJ_EUNKNOWN;
-+ }
-+
-+ status = ioctl(c, IFX_TAPI_DEC_START, 0);
-+ if (status != PJ_SUCCESS) {
-+ TRACE_((THIS_FILE, "ERROR - IFX_TAPI_DEC_START ioctl failed!"));
-+ return PJ_EUNKNOWN;
-+ }
-+ }
-+ }
-+
-+ return status;
-+}
-+
-+static pj_status_t
-+tapi_dev_stop(tapi_aud_factory_t *f)
-+{
-+ pj_status_t status = PJ_SUCCESS;
-+ pj_uint8_t c;
-+
-+ if (ioctl(f->dev_ctx.dev_fd, IFX_TAPI_DEV_STOP, 0) != PJ_SUCCESS) {
-+ TRACE_((THIS_FILE, "ERROR - IFX_TAPI_DEV_STOP ioctl failed"));
-+ status = PJ_EUNKNOWN;
-+ }
-+
-+ close(f->dev_ctx.dev_fd);
-+ for (c = TAPI_AUDIO_PORT_NUM; c > 0; c--)
-+ close(f->dev_ctx.ch_fd[TAPI_AUDIO_PORT_NUM-c]);
-+
-+ return status;
-+}
-+
-+static pj_status_t
-+tapi_dev_codec_control(pj_int32_t fd, pj_uint8_t start)
-+{
-+ if (ioctl(fd, start ? IFX_TAPI_ENC_START : IFX_TAPI_ENC_STOP, 0) != PJ_SUCCESS) {
-+ TRACE_((THIS_FILE, "ERROR - IFX_TAPI_ENC_%s ioctl failed!",
-+ start ? "START" : "STOP"));
-+ return PJ_EUNKNOWN;
-+ }
-+
-+ if (ioctl(fd, start ? IFX_TAPI_DEC_START : IFX_TAPI_DEC_STOP, 0) != IFX_SUCCESS) {
-+ TRACE_((THIS_FILE, "ERROR - IFX_TAPI_DEC_%s ioctl failed!",
-+ start ? "START" : "STOP"));
-+ return PJ_EUNKNOWN;
-+ }
-+
-+ return PJ_SUCCESS;
-+}
-+
-+static pj_status_t tapi_dev_event_on_hook(tapi_ctx *dev_ctx, pj_uint32_t dev_idx)
-+{
-+ PJ_LOG(1,(THIS_FILE, "TAPI: ONHOOK"));
-+
-+ if (ioctl(dev_ctx->ch_fd[dev_idx], IFX_TAPI_LINE_FEED_SET,
-+ IFX_TAPI_LINE_FEED_STANDBY) != PJ_SUCCESS) {
-+ TRACE_((THIS_FILE, "ERROR - IFX_TAPI_LINE_FEED_SET ioctl failed!"));
-+ return PJ_EUNKNOWN;
-+ }
-+
-+ /* enc/dec stop */
-+ if (tapi_dev_codec_control(dev_ctx->ch_fd[dev_idx], 0) != PJ_SUCCESS) {
-+ TRACE_((THIS_FILE, "ERROR - codec start failed!"));
-+ return PJ_EUNKNOWN;
-+ }
-+
-+ return PJ_SUCCESS;
-+}
-+
-+static pj_status_t tapi_dev_event_off_hook(tapi_ctx *dev_ctx, pj_uint32_t dev_idx)
-+{
-+ PJ_LOG(1,(THIS_FILE, "TAPI: OFFHOOK"));
-+
-+ if (ioctl(dev_ctx->ch_fd[dev_idx], IFX_TAPI_LINE_FEED_SET,
-+ IFX_TAPI_LINE_FEED_ACTIVE) != PJ_SUCCESS) {
-+ TRACE_((THIS_FILE, "ERROR - IFX_TAPI_LINE_FEED_SET ioctl failed!"));
-+ return PJ_EUNKNOWN;
-+ }
-+
-+ /* enc/dec stop */
-+ if (tapi_dev_codec_control(dev_ctx->ch_fd[dev_idx], 1) != PJ_SUCCESS) {
-+ TRACE_((THIS_FILE, "ERROR - codec start failed!"));
-+ return PJ_EUNKNOWN;
-+ }
-+
-+ return PJ_SUCCESS;
-+}
-+
-+static pj_status_t
-+tapi_dev_event_digit(tapi_ctx *dev_ctx, pj_uint32_t dev_idx)
-+{
-+ PJ_LOG(1,(THIS_FILE, "TAPI: OFFHOOK"));
-+
-+ if (ioctl(dev_ctx->ch_fd[dev_idx], IFX_TAPI_LINE_FEED_SET,
-+ IFX_TAPI_LINE_FEED_ACTIVE) != PJ_SUCCESS) {
-+ TRACE_((THIS_FILE, "ERROR - IFX_TAPI_LINE_FEED_SET ioctl failed!"));
-+ return PJ_EUNKNOWN;
-+ }
-+
-+ /* enc/dec stop */
-+ if (tapi_dev_codec_control(dev_ctx->ch_fd[dev_idx], 1) != PJ_SUCCESS) {
-+ TRACE_((THIS_FILE, "ERROR - codec start failed!"));
-+ return PJ_EUNKNOWN;
-+ }
-+
-+ return PJ_SUCCESS;
-+}
-+
-+static pj_status_t
-+tapi_dev_event_handler(tapi_aud_stream_t *stream)
-+{
-+ IFX_TAPI_EVENT_t tapiEvent;
-+ tapi_ctx *dev_ctx = stream->dev_ctx;
-+ pj_status_t status = PJ_SUCCESS;
-+ unsigned int i;
-+
-+ for (i = 0; i < TAPI_AUDIO_PORT_NUM; i++) {
-+ memset (&tapiEvent, 0, sizeof(tapiEvent));
-+ tapiEvent.ch = dev_ctx->data2phone_map[i];
-+ status = ioctl(dev_ctx->dev_fd, IFX_TAPI_EVENT_GET, &tapiEvent);
-+
-+ if ((status == PJ_SUCCESS) && (tapiEvent.id != IFX_TAPI_EVENT_NONE)) {
-+ switch(tapiEvent.id) {
-+ case IFX_TAPI_EVENT_FXS_ONHOOK:
-+ status = tapi_dev_event_on_hook(dev_ctx, i);
-+ if(tapi_hook_callback)
-+ tapi_hook_callback(i, 0);
-+ break;
-+ case IFX_TAPI_EVENT_FXS_OFFHOOK:
-+ status = tapi_dev_event_off_hook(dev_ctx, i);
-+ if(tapi_hook_callback)
-+ tapi_hook_callback(i, 1);
-+ break;
-+ case IFX_TAPI_EVENT_DTMF_DIGIT:
-+ if(tapi_digit_callback)
-+ tapi_digit_callback(i, tapiEvent.data.dtmf.ascii);
-+ break;
-+ case IFX_TAPI_EVENT_PULSE_DIGIT:
-+ if(tapi_digit_callback)
-+ if(tapiEvent.data.pulse.digit == 0xB)
-+ tapi_digit_callback(i, '0');
-+ else
-+ tapi_digit_callback(i, '0' + tapiEvent.data.pulse.digit);
-+ break;
-+ case IFX_TAPI_EVENT_COD_DEC_CHG:
-+ case IFX_TAPI_EVENT_TONE_GEN_END:
-+ case IFX_TAPI_EVENT_CID_TX_SEQ_END:
-+ break;
-+ default:
-+ PJ_LOG(1,(THIS_FILE, "unknown tapi event %08X", tapiEvent.id));
-+ break;
-+ }
-+ }
-+ }
-+
-+ return status;
-+}
-+
-+static pj_status_t
-+tapi_dev_data_handler(tapi_aud_stream_t *stream) {
-+ pj_status_t status = PJ_SUCCESS;
-+ tapi_ctx *dev_ctx = stream->dev_ctx;
-+ pj_uint32_t dev_idx = stream->param.rec_id;
-+ pj_uint8_t buf_rec[TAPI_LL_DEV_ENC_BYTES_PER_FRAME + TAPI_LL_DEV_RTP_HEADER_SIZE_BYTE]={0};
-+ pj_uint8_t buf_play[TAPI_LL_DEV_ENC_BYTES_PER_FRAME + TAPI_LL_DEV_RTP_HEADER_SIZE_BYTE]={0};
-+ pjmedia_frame frame_rec, frame_play;
-+ pj_int32_t ret;
-+
-+ /* Get data from driver */
-+ ret = read(dev_ctx->ch_fd[dev_idx], buf_rec, sizeof(buf_rec));
-+ if (ret < 0) {
-+ TRACE_((THIS_FILE, "ERROR - no data available from device!"));
-+ return PJ_EUNKNOWN;
-+ }
-+
-+ if (ret > 0) {
-+ frame_rec.type = PJMEDIA_FRAME_TYPE_AUDIO;
-+ frame_rec.buf = buf_rec + TAPI_LL_DEV_RTP_HEADER_SIZE_BYTE;
-+ frame_rec.size = ret - TAPI_LL_DEV_RTP_HEADER_SIZE_BYTE;
-+ frame_rec.timestamp.u64 = stream->timestamp.u64;
-+
-+ status = stream->rec_cb(stream->user_data, &frame_rec);
-+ if (status != PJ_SUCCESS)
-+ PJ_LOG(1, (THIS_FILE, "rec_cb() failed %d", status));
-+
-+ frame_play.type = PJMEDIA_FRAME_TYPE_AUDIO;
-+ frame_play.buf = buf_play + TAPI_LL_DEV_RTP_HEADER_SIZE_BYTE;
-+ frame_play.size = TAPI_LL_DEV_ENC_BYTES_PER_FRAME;
-+ frame_play.timestamp.u64 = stream->timestamp.u64;
-+
-+ status = (*stream->play_cb)(stream->user_data, &frame_play);
-+ if (status != PJ_SUCCESS) {
-+ PJ_LOG(1, (THIS_FILE, "play_cb() failed %d", status));
-+ } else {
-+ memcpy(buf_play, buf_rec, TAPI_LL_DEV_RTP_HEADER_SIZE_BYTE);
-+
-+ ret = write(dev_ctx->ch_fd[dev_idx], buf_play, sizeof(buf_play));
-+
-+ if (ret < 0) {
-+ PJ_LOG(1, (THIS_FILE, "ERROR - device data writing failed!"));
-+ return PJ_EUNKNOWN;
-+ }
-+
-+ if (ret == 0) {
-+ PJ_LOG(1, (THIS_FILE, "ERROR - no data written to device!"));
-+ return PJ_EUNKNOWN;
-+ }
-+ }
-+
-+ stream->timestamp.u64 += TAPI_LL_DEV_ENC_SMPL_PER_FRAME;
-+ }
-+
-+ return PJ_SUCCESS;
-+}
-+
-+static int
-+PJ_THREAD_FUNC tapi_dev_thread(void *arg) {
-+ tapi_ctx *dev_ctx = streams[0].dev_ctx;
-+ pj_uint32_t sretval;
-+ struct pollfd fds[3];
-+
-+ PJ_LOG(1,(THIS_FILE, "TAPI: thread starting..."));
-+
-+ streams[0].run_flag = 1;
-+ streams[1].run_flag = 1;
-+
-+ fds[0].fd = dev_ctx->dev_fd;
-+ fds[0].events = POLLIN;
-+ fds[1].fd = dev_ctx->ch_fd[0];
-+ fds[1].events = POLLIN;
-+ fds[2].fd = dev_ctx->ch_fd[1];
-+ fds[2].events = POLLIN;
-+
-+ while(1)
-+ {
-+ sretval = poll(fds, TAPI_AUDIO_PORT_NUM + 1, TAPI_LL_DEV_SELECT_TIMEOUT_MS);
-+
-+ if (!streams[0].run_flag && !streams[0].run_flag)
-+ break;
-+ if (sretval <= 0)
-+ continue;
-+
-+ if (fds[0].revents == POLLIN) {
-+ if (tapi_dev_event_handler(&streams[0]) != PJ_SUCCESS) {
-+ PJ_LOG(1, (THIS_FILE, "TAPI: event hanldler failed"));
-+ break;
-+ }
-+ }
-+
-+ if (fds[1].revents == POLLIN) {
-+ if (tapi_dev_data_handler(&streams[0]) != PJ_SUCCESS) {
-+ PJ_LOG(1, (THIS_FILE, "TAPI: data hanldler failed"));
-+ break;
-+ }
-+ }
-+
-+ if (fds[2].revents == POLLIN) {
-+ if (tapi_dev_data_handler(&streams[1]) != PJ_SUCCESS) {
-+ PJ_LOG(1, (THIS_FILE, "TAPI: data hanldler failed"));
-+ break;
-+ }
-+ }
-+ }
-+ PJ_LOG(1, (THIS_FILE, "TAPI: thread stopping..."));
-+
-+ return 0;
-+}
-+
-+/* Factory operations */
-+
-+pjmedia_aud_dev_factory*
-+pjmedia_tapi_factory(pj_pool_factory *pf) {
-+ struct tapi_aud_factory *f;
-+ pj_pool_t *pool;
-+
-+ TRACE_((THIS_FILE, "pjmedia_tapi_factory()"));
-+
-+ pool = pj_pool_create(pf, "tapi", 512, 512, NULL);
-+ f = PJ_POOL_ZALLOC_T(pool, struct tapi_aud_factory);
-+ f->pf = pf;
-+ f->pool = pool;
-+ f->base.op = &tapi_fact_op;
-+
-+ return &f->base;
-+}
-+
-+static pj_status_t
-+factory_init(pjmedia_aud_dev_factory *f)
-+{
-+ struct tapi_aud_factory *af = (struct tapi_aud_factory*)f;
-+ pj_uint8_t i;
-+
-+ TRACE_((THIS_FILE, "factory_init()"));
-+
-+ af->dev_count = TAPI_AUDIO_PORT_NUM;
-+ af->dev_info = (pjmedia_aud_dev_info*)
-+ pj_pool_calloc(af->pool, af->dev_count, sizeof(pjmedia_aud_dev_info));
-+ for (i = 0; i < TAPI_AUDIO_PORT_NUM; i++) {
-+ pj_ansi_sprintf(af->dev_info[i].name,"%s_%02d", TAPI_BASE_NAME, i);
-+ af->dev_info[i].input_count = af->dev_info[i].output_count = 1;
-+ af->dev_info[i].default_samples_per_sec = TAPI_LL_DEV_ENC_SMPL_PER_SEC;
-+ pj_ansi_strcpy(af->dev_info[i].driver, "/dev/vmmc");
-+ af->dev_info[i].caps = PJMEDIA_AUD_DEV_CAP_OUTPUT_VOLUME_SETTING |
-+ PJMEDIA_AUD_DEV_CAP_OUTPUT_LATENCY |
-+ PJMEDIA_AUD_DEV_CAP_INPUT_LATENCY;
-+ af->dev_info[i].routes = PJMEDIA_AUD_DEV_ROUTE_DEFAULT ;
-+ }
-+ if (tapi_dev_start(af) != PJ_SUCCESS) {
-+ TRACE_((THIS_FILE, "ERROR - TAPI device init failed!"));
-+ return PJ_EUNKNOWN;
-+ }
-+
-+ return PJ_SUCCESS;
-+}
-+
-+static pj_status_t
-+factory_destroy(pjmedia_aud_dev_factory *f)
-+{
-+ struct tapi_aud_factory *af = (struct tapi_aud_factory*)f;
-+ pj_pool_t *pool;
-+ pj_status_t status = PJ_SUCCESS;
-+
-+ TRACE_((THIS_FILE, "factory_destroy()"));
-+
-+ if (tapi_dev_stop(af) != PJ_SUCCESS) {
-+ TRACE_((THIS_FILE, "ERROR - TAPI device stop failed!"));
-+ status = PJ_EUNKNOWN;
-+ }
-+ pool = af->pool;
-+ af->pool = NULL;
-+ pj_pool_release(pool);
-+
-+ return status;
-+}
-+
-+static unsigned
-+factory_get_dev_count(pjmedia_aud_dev_factory *f)
-+{
-+ struct tapi_aud_factory *af = (struct tapi_aud_factory*)f;
-+ TRACE_((THIS_FILE, "factory_get_dev_count()"));
-+
-+ return af->dev_count;
-+}
-+
-+static pj_status_t
-+factory_get_dev_info(pjmedia_aud_dev_factory *f, unsigned index, pjmedia_aud_dev_info *info)
-+{
-+ struct tapi_aud_factory *af = (struct tapi_aud_factory*)f;
-+
-+ TRACE_((THIS_FILE, "factory_get_dev_info()"));
-+ PJ_ASSERT_RETURN(index < af->dev_count, PJMEDIA_EAUD_INVDEV);
-+
-+ pj_memcpy(info, &af->dev_info[index], sizeof(*info));
-+
-+ return PJ_SUCCESS;
-+}
-+
-+static pj_status_t
-+factory_default_param(pjmedia_aud_dev_factory *f, unsigned index, pjmedia_aud_param *param)
-+{
-+ struct tapi_aud_factory *af = (struct tapi_aud_factory*)f;
-+ struct pjmedia_aud_dev_info *di = &af->dev_info[index];
-+
-+ TRACE_((THIS_FILE, "factory_default_param."));
-+ PJ_ASSERT_RETURN(index < af->dev_count, PJMEDIA_EAUD_INVDEV);
-+
-+ pj_bzero(param, sizeof(*param));
-+ if (di->input_count && di->output_count) {
-+ param->dir = PJMEDIA_DIR_CAPTURE_PLAYBACK;
-+ param->rec_id = index;
-+ param->play_id = index;
-+ } else if (di->input_count) {
-+ param->dir = PJMEDIA_DIR_CAPTURE;
-+ param->rec_id = index;
-+ param->play_id = PJMEDIA_AUD_INVALID_DEV;
-+ } else if (di->output_count) {
-+ param->dir = PJMEDIA_DIR_PLAYBACK;
-+ param->play_id = index;
-+ param->rec_id = PJMEDIA_AUD_INVALID_DEV;
-+ } else {
-+ return PJMEDIA_EAUD_INVDEV;
-+ }
-+
-+ param->clock_rate = TAPI_LL_DEV_ENC_SMPL_PER_SEC; //di->default_samples_per_sec;
-+ param->channel_count = 1;
-+ param->samples_per_frame = TAPI_LL_DEV_ENC_SMPL_PER_FRAME;
-+ param->bits_per_sample = TAPI_LL_DEV_ENC_BITS_PER_SMPLS;
-+ param->flags = PJMEDIA_AUD_DEV_CAP_OUTPUT_ROUTE | di->caps;
-+ param->output_route = PJMEDIA_AUD_DEV_ROUTE_DEFAULT;
-+
-+ return PJ_SUCCESS;
-+}
-+
-+
-+static pj_status_t
-+factory_create_stream(pjmedia_aud_dev_factory *f, const pjmedia_aud_param *param,
-+ pjmedia_aud_rec_cb rec_cb, pjmedia_aud_play_cb play_cb,
-+ void *user_data, pjmedia_aud_stream **p_aud_strm)
-+{
-+ struct tapi_aud_factory *af = (struct tapi_aud_factory*)f;
-+ pj_pool_t *pool;
-+ pj_status_t status;
-+ int id = param->rec_id;
-+ struct tapi_aud_stream *strm = &streams[param->rec_id];
-+ TRACE_((THIS_FILE, "factory_create_stream() rec_id:%d play_id:%d", param->rec_id, param->play_id));
-+
-+ /* Can only support 16bits per sample */
-+ PJ_ASSERT_RETURN(param->bits_per_sample == TAPI_LL_DEV_ENC_BITS_PER_SMPLS, PJ_EINVAL);
-+ PJ_ASSERT_RETURN(param->clock_rate == TAPI_LL_DEV_ENC_SMPL_PER_SEC, PJ_EINVAL);
-+ PJ_ASSERT_RETURN(param->samples_per_frame == TAPI_LL_DEV_ENC_SMPL_PER_FRAME, PJ_EINVAL);
-+
-+ /* Can only support bidirectional stream */
-+ PJ_ASSERT_RETURN(param->dir & PJMEDIA_DIR_CAPTURE_PLAYBACK, PJ_EINVAL);
-+
-+ if (id == 0) {
-+ /* Initialize our stream data */
-+ pool = pj_pool_create(af->pf, "tapi-dev", 1000, 1000, NULL);
-+ PJ_ASSERT_RETURN(pool != NULL, PJ_ENOMEM);
-+
-+ strm->pool = pool;
-+ } else {
-+ pool = strm->pool = streams[0].pool;
-+ }
-+
-+ strm->rec_cb = rec_cb;
-+ strm->play_cb = play_cb;
-+ strm->user_data = user_data;
-+
-+ pj_memcpy(&strm->param, param, sizeof(*param));
-+
-+ if ((strm->param.flags & PJMEDIA_AUD_DEV_CAP_EXT_FORMAT) == 0) {
-+ strm->param.ext_fmt.id = PJMEDIA_FORMAT_L16;
-+ }
-+
-+ strm->timestamp.u64 = 0;
-+ strm->dev_ctx = &(af->dev_ctx);
-+
-+ /* Create and start the thread */
-+ if (id == 1) {
-+ status = pj_thread_create(pool, "tapi", &tapi_dev_thread, strm, 0, 0, &streams[0].thread);
-+ if (status != PJ_SUCCESS) {
-+ stream_destroy(&strm->base);
-+ return status;
-+ }
-+ }
-+
-+ /* Done */
-+ strm->base.op = &tapi_strm_op;
-+ *p_aud_strm = &strm->base;
-+
-+ return PJ_SUCCESS;
-+}
-+
-+static pj_status_t
-+stream_get_param(pjmedia_aud_stream *s, pjmedia_aud_param *pi)
-+{
-+ struct tapi_aud_stream *strm = (struct tapi_aud_stream*)s;
-+
-+ PJ_ASSERT_RETURN(strm && pi, PJ_EINVAL);
-+ pj_memcpy(pi, &strm->param, sizeof(*pi));
-+
-+ if (stream_get_cap(s, PJMEDIA_AUD_DEV_CAP_OUTPUT_VOLUME_SETTING,
-+ &pi->output_vol) == PJ_SUCCESS)
-+ pi->flags |= PJMEDIA_AUD_DEV_CAP_OUTPUT_VOLUME_SETTING;
-+
-+ if (stream_get_cap(s, PJMEDIA_AUD_DEV_CAP_OUTPUT_LATENCY,
-+ &pi->output_latency_ms) == PJ_SUCCESS)
-+ pi->flags |= PJMEDIA_AUD_DEV_CAP_OUTPUT_LATENCY;
-+
-+ if (stream_get_cap(s, PJMEDIA_AUD_DEV_CAP_INPUT_LATENCY,
-+ &pi->input_latency_ms) == PJ_SUCCESS)
-+ pi->flags |= PJMEDIA_AUD_DEV_CAP_INPUT_LATENCY;
-+
-+ return PJ_SUCCESS;
-+}
-+
-+static pj_status_t
-+stream_get_cap(pjmedia_aud_stream *s, pjmedia_aud_dev_cap cap, void *pval)
-+{
-+ // struct tapi_aud_stream *strm = (struct tapi_aud_stream*)s;
-+ return PJ_SUCCESS;
-+}
-+
-+static pj_status_t
-+stream_set_cap(pjmedia_aud_stream *s, pjmedia_aud_dev_cap cap, const void *pval)
-+{
-+ // struct tapi_aud_stream *strm = (struct tapi_aud_stream*)s;
-+ return PJ_SUCCESS;
-+}
-+
-+static pj_status_t
-+stream_start(pjmedia_aud_stream *s)
-+{
-+ struct tapi_aud_stream *strm = (struct tapi_aud_stream*)s;
-+ pj_uint32_t dev_idx;
-+
-+ TRACE_((THIS_FILE, "stream_start()"));
-+
-+ dev_idx = strm->param.rec_id;
-+
-+ return PJ_SUCCESS;
-+}
-+
-+static pj_status_t
-+stream_stop(pjmedia_aud_stream *s)
-+{
-+ struct tapi_aud_stream *strm = (struct tapi_aud_stream*)s;
-+ tapi_ctx *dev_ctx = strm->dev_ctx;
-+ pj_uint32_t dev_idx;
-+
-+ TRACE_((THIS_FILE, "stream_stop()"));
-+ dev_idx = strm->param.rec_id;
-+
-+ if (tapi_dev_codec_control(dev_ctx->ch_fd[dev_idx], 0) != PJ_SUCCESS) {
-+ TRACE_((THIS_FILE, "ERROR - codec start failed!"));
-+ return PJ_EUNKNOWN;
-+ }
-+
-+ return PJ_SUCCESS;
-+}
-+
-+static pj_status_t
-+stream_destroy(pjmedia_aud_stream *s)
-+{
-+ pj_status_t state = PJ_SUCCESS;
-+ struct tapi_aud_stream *stream = (struct tapi_aud_stream*)s;
-+ pj_pool_t *pool;
-+
-+ PJ_ASSERT_RETURN(stream != NULL, PJ_EINVAL);
-+ TRACE_((THIS_FILE, "stream_destroy()"));
-+
-+ stream_stop(&stream->base);
-+ stream->run_flag = 0;
-+
-+ if (stream->thread)
-+ {
-+ pj_thread_join(stream->thread);
-+ pj_thread_destroy(stream->thread);
-+ stream->thread = NULL;
-+ }
-+
-+ pool = stream->pool;
-+ pj_bzero(stream, sizeof(stream));
-+ pj_pool_release(pool);
-+
-+ return state;
-+}
-+
-+pj_status_t
-+tapi_hook_status(pj_uint8_t port, pj_int32_t *status)
-+{
-+ PJ_ASSERT_RETURN(port < TAPI_AUDIO_PORT_NUM, PJ_EINVAL);
-+
-+ if (ioctl(ch_fd[port], IFX_TAPI_LINE_HOOK_STATUS_GET, status)
-+ != PJ_SUCCESS) {
-+ TRACE_((THIS_FILE, "ERROR - IFX_TAPI_LINE_HOOK_STATUS_GET ioctl failed!"));
-+ return PJ_EUNKNOWN;
-+ }
-+
-+ return PJ_SUCCESS;
-+}
-+
-+pj_status_t
-+tapi_ring(pj_uint8_t port, pj_uint8_t state, char *caller_number)
-+{
-+ PJ_ASSERT_RETURN(port < TAPI_AUDIO_PORT_NUM, PJ_EINVAL);
-+
-+ if (state) {
-+ if (tapi_cid_type && caller_number) {
-+ IFX_TAPI_CID_MSG_t cid_msg;
-+ IFX_TAPI_CID_MSG_ELEMENT_t cid_msg_el[1];
-+ memset(&cid_msg, 0, sizeof(cid_msg));
-+ memset(&cid_msg_el, 0, sizeof(cid_msg_el));
-+
-+ cid_msg_el[0].string.elementType = IFX_TAPI_CID_ST_CLI;
-+ cid_msg_el[0].string.len = strlen(caller_number);
-+ strncpy(cid_msg_el[0].string.element, caller_number, sizeof(cid_msg_el[0].string.element));
-+
-+ cid_msg.txMode = IFX_TAPI_CID_HM_ONHOOK;
-+ cid_msg.messageType = IFX_TAPI_CID_MT_CSUP;
-+ cid_msg.nMsgElements = 1;
-+ cid_msg.message = cid_msg_el;
-+ ioctl(ch_fd[port], IFX_TAPI_CID_TX_SEQ_START, &cid_msg);
-+ } else {
-+ ioctl(ch_fd[port], IFX_TAPI_RING_START, 0);
-+ }
-+ } else {
-+ ioctl(ch_fd[port], IFX_TAPI_RING_STOP, 0);
-+ }
-+
-+ return PJ_SUCCESS;
-+}
-+
-+pj_status_t
-+tapi_tone(pj_uint8_t port, pj_uint8_t code)
-+{
-+ PJ_ASSERT_RETURN(port < TAPI_AUDIO_PORT_NUM, PJ_EINVAL);
-+
-+ if (tapi_locale && code)
-+ ioctl(ch_fd[port], IFX_TAPI_TONE_LOCAL_PLAY, code);
-+ else if (code)
-+ ioctl(ch_fd[port], IFX_TAPI_TONE_LOCAL_PLAY, TAPI_TONE_LOCALE_NONE);
-+ else
-+ ioctl(ch_fd[port], IFX_TAPI_TONE_LOCAL_PLAY, 0);
-+
-+ return PJ_SUCCESS;
-+}
-+
-+#endif /* PJMEDIA_AUDIO_DEV_HAS_TAPI_DEVICE */
+++ /dev/null
---- a/pjsip/include/pjsua-lib/pjsua.h
-+++ b/pjsip/include/pjsua-lib/pjsua.h
-@@ -1543,6 +1543,8 @@ PJ_DECL(pjmedia_endpt*) pjsua_get_pjmedi
- PJ_DECL(pj_pool_factory*) pjsua_get_pool_factory(void);
-
-
-+PJ_DECL(pj_status_t) pjsua_add_snd_port(int id, pjsua_conf_port_id *p_id);
-+
-
- /*****************************************************************************
- * Utilities.
---- a/pjsip/include/pjsua-lib/pjsua_internal.h
-+++ b/pjsip/include/pjsua-lib/pjsua_internal.h
-@@ -261,6 +261,8 @@ typedef struct pjsua_stun_resolve
- } pjsua_stun_resolve;
-
-
-+#define MAX_PORT 2
-+
- /**
- * Global pjsua application data.
- */
-@@ -336,7 +338,7 @@ struct pjsua_data
- pj_bool_t aud_open_cnt;/**< How many # device is opened */
- pj_bool_t no_snd; /**< No sound (app will manage it) */
- pj_pool_t *snd_pool; /**< Sound's private pool. */
-- pjmedia_snd_port *snd_port; /**< Sound port. */
-+ pjmedia_snd_port *snd_port[MAX_PORT]; /**< Sound port. */
- pj_timer_entry snd_idle_timer;/**< Sound device idle timer. */
- pjmedia_master_port *null_snd; /**< Master port for null sound. */
- pjmedia_port *null_port; /**< Null port. */
---- a/pjsip/src/pjsua-lib/pjsua_media.c
-+++ b/pjsip/src/pjsua-lib/pjsua_media.c
-@@ -588,7 +588,7 @@ static void check_snd_dev_idle()
- * It is idle when there is no port connection in the bridge and
- * there is no active call.
- */
-- if ((pjsua_var.snd_port!=NULL || pjsua_var.null_snd!=NULL) &&
-+ if ((pjsua_var.snd_port[0]!=NULL || pjsua_var.null_snd!=NULL) &&
- pjsua_var.snd_idle_timer.id == PJ_FALSE &&
- pjmedia_conf_get_connect_count(pjsua_var.mconf) == 0 &&
- call_cnt == 0 &&
-@@ -2008,7 +2008,7 @@ PJ_DEF(pj_status_t) pjsua_conf_connect(
- pj_assert(status == PJ_SUCCESS);
-
- /* Check if sound device is instantiated. */
-- need_reopen = (pjsua_var.snd_port==NULL && pjsua_var.null_snd==NULL &&
-+ need_reopen = (pjsua_var.snd_port[0]==NULL && pjsua_var.null_snd==NULL &&
- !pjsua_var.no_snd);
-
- /* Check if sound device need to reopen because it needs to modify
-@@ -2072,7 +2072,7 @@ PJ_DEF(pj_status_t) pjsua_conf_connect(
- /* The bridge version */
-
- /* Create sound port if none is instantiated */
-- if (pjsua_var.snd_port==NULL && pjsua_var.null_snd==NULL &&
-+ if (pjsua_var.snd_port[0]==NULL && pjsua_var.null_snd==NULL &&
- !pjsua_var.no_snd)
- {
- pj_status_t status;
-@@ -2686,9 +2686,9 @@ static pj_status_t update_initial_aud_pa
- pjmedia_aud_param param;
- pj_status_t status;
-
-- PJ_ASSERT_RETURN(pjsua_var.snd_port != NULL, PJ_EBUG);
-+ PJ_ASSERT_RETURN(pjsua_var.snd_port[0] != NULL, PJ_EBUG);
-
-- strm = pjmedia_snd_port_get_snd_stream(pjsua_var.snd_port);
-+ strm = pjmedia_snd_port_get_snd_stream(pjsua_var.snd_port[0]);
-
- status = pjmedia_aud_stream_get_param(strm, ¶m);
- if (status != PJ_SUCCESS) {
-@@ -2754,7 +2754,7 @@ static pj_status_t open_snd_dev(pjmedia_
- 1000 / param->base.clock_rate));
-
- status = pjmedia_snd_port_create2( pjsua_var.snd_pool,
-- param, &pjsua_var.snd_port);
-+ param, &pjsua_var.snd_port[0]);
- if (status != PJ_SUCCESS)
- return status;
-
-@@ -2812,13 +2812,13 @@ static pj_status_t open_snd_dev(pjmedia_
- }
-
- /* Connect sound port to the bridge */
-- status = pjmedia_snd_port_connect(pjsua_var.snd_port,
-+ status = pjmedia_snd_port_connect(pjsua_var.snd_port[0],
- conf_port );
- if (status != PJ_SUCCESS) {
- pjsua_perror(THIS_FILE, "Unable to connect conference port to "
- "sound device", status);
-- pjmedia_snd_port_destroy(pjsua_var.snd_port);
-- pjsua_var.snd_port = NULL;
-+ pjmedia_snd_port_destroy(pjsua_var.snd_port[0]);
-+ pjsua_var.snd_port[0] = NULL;
- return status;
- }
-
-@@ -2833,7 +2833,7 @@ static pj_status_t open_snd_dev(pjmedia_
- pjmedia_aud_param si;
- pj_str_t tmp;
-
-- strm = pjmedia_snd_port_get_snd_stream(pjsua_var.snd_port);
-+ strm = pjmedia_snd_port_get_snd_stream(pjsua_var.snd_port[0]);
- status = pjmedia_aud_stream_get_param(strm, &si);
- if (status == PJ_SUCCESS)
- status = pjmedia_aud_dev_get_info(si.rec_id, &rec_info);
-@@ -2876,12 +2876,12 @@ static pj_status_t open_snd_dev(pjmedia_
- static void close_snd_dev(void)
- {
- /* Close sound device */
-- if (pjsua_var.snd_port) {
-+ if (pjsua_var.snd_port[0]) {
- pjmedia_aud_dev_info cap_info, play_info;
- pjmedia_aud_stream *strm;
- pjmedia_aud_param param;
-
-- strm = pjmedia_snd_port_get_snd_stream(pjsua_var.snd_port);
-+ strm = pjmedia_snd_port_get_snd_stream(pjsua_var.snd_port[0]);
- pjmedia_aud_stream_get_param(strm, ¶m);
-
- if (pjmedia_aud_dev_get_info(param.rec_id, &cap_info) != PJ_SUCCESS)
-@@ -2893,9 +2893,9 @@ static void close_snd_dev(void)
- "%s sound capture device",
- play_info.name, cap_info.name));
-
-- pjmedia_snd_port_disconnect(pjsua_var.snd_port);
-- pjmedia_snd_port_destroy(pjsua_var.snd_port);
-- pjsua_var.snd_port = NULL;
-+ pjmedia_snd_port_disconnect(pjsua_var.snd_port[0]);
-+ pjmedia_snd_port_destroy(pjsua_var.snd_port[0]);
-+ pjsua_var.snd_port[0] = NULL;
- }
-
- /* Close null sound device */
-@@ -2984,6 +2984,35 @@ PJ_DEF(pj_status_t) pjsua_set_snd_dev( i
- return PJ_SUCCESS;
- }
-
-+PJ_DEF(pj_status_t) pjsua_add_snd_port(int id, pjsua_conf_port_id *p_id)
-+{
-+ unsigned alt_cr_cnt = 1;
-+ unsigned alt_cr = 0;
-+ pj_status_t status = -1;
-+ pjmedia_snd_port_param param;
-+ unsigned samples_per_frame;
-+ pjmedia_port *port;
-+ const pj_str_t name = pj_str("tapi2");
-+ alt_cr = pjsua_var.media_cfg.clock_rate;
-+ samples_per_frame = alt_cr *
-+ pjsua_var.media_cfg.audio_frame_ptime *
-+ pjsua_var.media_cfg.channel_count / 1000;
-+ status = create_aud_param(¶m.base,
-+ pjsua_var.play_dev,
-+ pjsua_var.cap_dev,
-+ alt_cr,
-+ pjsua_var.media_cfg.channel_count,
-+ samples_per_frame, 16);
-+ if (status != PJ_SUCCESS)
-+ return status;
-+ param.base.rec_id = id;
-+ param.base.play_id = id;
-+ param.options = 0;
-+ status = pjmedia_snd_port_create2(pjsua_var.snd_pool,
-+ ¶m, &pjsua_var.snd_port[id]);
-+ return PJ_SUCCESS;
-+}
-+
-
- /*
- * Get currently active sound devices. If sound devices has not been created
-@@ -3088,7 +3117,7 @@ PJ_DEF(pj_status_t) pjsua_set_ec(unsigne
- pjsua_var.media_cfg.ec_options = options;
-
- if (pjsua_var.snd_port)
-- status = pjmedia_snd_port_set_ec(pjsua_var.snd_port, pjsua_var.pool,
-+ status = pjmedia_snd_port_set_ec(pjsua_var.snd_port[0], pjsua_var.pool,
- tail_ms, options);
-
- PJSUA_UNLOCK();
-@@ -3111,7 +3140,7 @@ PJ_DEF(pj_status_t) pjsua_get_ec_tail(un
- */
- PJ_DEF(pj_bool_t) pjsua_snd_is_active(void)
- {
-- return pjsua_var.snd_port != NULL;
-+ return pjsua_var.snd_port[0] != NULL;
- }
-
-
-@@ -3135,7 +3164,7 @@ PJ_DEF(pj_status_t) pjsua_snd_set_settin
- if (pjsua_snd_is_active()) {
- pjmedia_aud_stream *strm;
-
-- strm = pjmedia_snd_port_get_snd_stream(pjsua_var.snd_port);
-+ strm = pjmedia_snd_port_get_snd_stream(pjsua_var.snd_port[0]);
- status = pjmedia_aud_stream_set_cap(strm, cap, pval);
- } else {
- status = PJ_SUCCESS;
-@@ -3181,7 +3210,7 @@ PJ_DEF(pj_status_t) pjsua_snd_get_settin
- /* Sound is active, retrieve from device directly */
- pjmedia_aud_stream *strm;
-
-- strm = pjmedia_snd_port_get_snd_stream(pjsua_var.snd_port);
-+ strm = pjmedia_snd_port_get_snd_stream(pjsua_var.snd_port[0]);
- status = pjmedia_aud_stream_get_cap(strm, cap, pval);
- } else {
- /* Otherwise retrieve from internal param */
+++ /dev/null
-#
-# Copyright (C) 2010 OpenWrt.org
-#
-# This is free software, licensed under the GNU General Public License v2.
-# See /LICENSE for more information.
-#
-
-include $(TOPDIR)/rules.mk
-include $(INCLUDE_DIR)/kernel.mk
-
-PKG_NAME:=u-boot
-
-PKG_VERSION:=2010.03
-PKG_MD5SUM:=2bf5ebf497dddc52440b1ea386cc1332
-PKG_RELEASE:=1
-
-PKG_BUILD_DIR:=$(KERNEL_BUILD_DIR)/$(PKG_NAME)-$(PKG_VERSION)
-PKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.bz2
-PKG_SOURCE_URL:=ftp://ftp.denx.de/pub/u-boot
-PKG_TARGETS:=bin
-
-include $(INCLUDE_DIR)/package.mk
-
-ifeq ($(DUMP),)
- STAMP_CONFIGURED:=$(PKG_BUILD_DIR)/$(BUILD_VARIANT)/.configured
- STAMP_BUILT:=$(PKG_BUILD_DIR)/$(BUILD_VARIANT)/.built
-endif
-
-define Package/uboot-lantiq-template
- SECTION:=boot
- CATEGORY:=Boot Loaders
- DEPENDS:=@TARGET_lantiq_danube
- URL:=http://www.denx.de/wiki/U-Boot
- VARIANT:=$(1)
- TITLE:=$(1) ($(2))
- MAINTAINER:=John Crispin <blogic@openwrt.org>
-endef
-
-#Lantiq
-Package/uboot-lantiq-easy50712_DDR166M_flash=$(call Package/uboot-lantiq-template,easy50712_DDR166M_flash,NOR)
-Package/uboot-lantiq-easy50712_DDR166M_ramboot=$(call Package/uboot-lantiq-template,easy50712_DDR166M_ramboot,RAM)
-Package/uboot-lantiq-easy50812_DDR166M_flash=$(call Package/uboot-lantiq-template,easy50812_DDR166M_flash,NOR)
-Package/uboot-lantiq-easy50812_DDR166M_ramboot=$(call Package/uboot-lantiq-template,easy50812_DDR166M_ramboot,RAM)
-
-DDR_CONFIG_easy50712_DDR166M_ramboot:=easy50712_DDR166M
-DDR_CONFIG_easy50812_DDR166M_ramboot:=easy50812
-
-#Siemens
-Package/uboot-lantiq-gigaSX76X_DDRsamsung166_flash=$(call Package/uboot-lantiq-template,gigaSX76X_DDRsamsung166_flash,NOR)
-Package/uboot-lantiq-gigaSX76X_DDRsamsung166_ramboot=$(call Package/uboot-lantiq-template,gigaSX76X_DDRsamsung166_ramboot,RAM)
-
-DDR_CONFIG_gigaSX76X_DDRsamsung166_ramboot:=easy50712_DDR166M
-
-#Arcadyan
-Package/uboot-lantiq-arv3527P_flash=$(call Package/uboot-lantiq-template,arv3527P_flash,NOR)
-Package/uboot-lantiq-arv3527P_ramboot=$(call Package/uboot-lantiq-template,arv3527P_ramboot,RAM)
-Package/uboot-lantiq-arv3527P_brnboot=$(call Package/uboot-lantiq-template,arv3527P_brnboot,BRN)
-Package/uboot-lantiq-arv4518PW_flash=$(call Package/uboot-lantiq-template,arv4518PW_flash,NOR)
-Package/uboot-lantiq-arv4518PW_ramboot=$(call Package/uboot-lantiq-template,arv4518PW_ramboot,RAM)
-Package/uboot-lantiq-arv4518PW_brnboot=$(call Package/uboot-lantiq-template,arv4518PW_brnboot,BRN)
-Package/uboot-lantiq-arv4519PW_flash=$(call Package/uboot-lantiq-template,arv4519PW_flash,NOR)
-Package/uboot-lantiq-arv4519PW_ramboot=$(call Package/uboot-lantiq-template,arv4519PW_ramboot,RAM)
-Package/uboot-lantiq-arv4519PW_brnboot=$(call Package/uboot-lantiq-template,arv4519PW_brnboot,BRN)
-Package/uboot-lantiq-arv4520PW_flash=$(call Package/uboot-lantiq-template,arv4520PW_flash,NOR)
-Package/uboot-lantiq-arv4520PW_ramboot=$(call Package/uboot-lantiq-template,arv4520PW_ramboot,RAM)
-Package/uboot-lantiq-arv4520PW_brnboot=$(call Package/uboot-lantiq-template,arv4520PW_brnboot,BRN)
-Package/uboot-lantiq-arv4525PW_flash=$(call Package/uboot-lantiq-template,arv4525PW_flash,NOR)
-Package/uboot-lantiq-arv4525PW_ramboot=$(call Package/uboot-lantiq-template,arv4525PW_ramboot,RAM)
-Package/uboot-lantiq-arv4525PW_brnboot=$(call Package/uboot-lantiq-template,arv4525PW_brnboot,BRN)
-Package/uboot-lantiq-arv7525PW_flash=$(call Package/uboot-lantiq-template,arv7525PW_flash,NOR)
-Package/uboot-lantiq-arv7525PW_ramboot=$(call Package/uboot-lantiq-template,arv7525PW_ramboot,RAM)
-Package/uboot-lantiq-arv7525PW_brnboot=$(call Package/uboot-lantiq-template,arv7525PW_brnboot,BRN)
-Package/uboot-lantiq-arv452CPW_flash=$(call Package/uboot-lantiq-template,arv452CPW_flash,NOR)
-Package/uboot-lantiq-arv452CPW_ramboot=$(call Package/uboot-lantiq-template,arv452CPW_ramboot,RAM)
-Package/uboot-lantiq-arv452CPW_brnboot=$(call Package/uboot-lantiq-template,arv452CPW_brnboot,BRN)
-Package/uboot-lantiq-arv752DPW_flash=$(call Package/uboot-lantiq-template,arv752DPW_flash,NOR)
-Package/uboot-lantiq-arv752DPW_ramboot=$(call Package/uboot-lantiq-template,arv752DPW_ramboot,RAM)
-Package/uboot-lantiq-arv752DPW_brnboot=$(call Package/uboot-lantiq-template,arv752DPW_brnboot,BRN)
-Package/uboot-lantiq-arv752DPW22_flash=$(call Package/uboot-lantiq-template,arv752DPW22_flash,NOR)
-Package/uboot-lantiq-arv752DPW22_ramboot=$(call Package/uboot-lantiq-template,arv752DPW22_ramboot,RAM)
-Package/uboot-lantiq-arv752DPW22_brnboot=$(call Package/uboot-lantiq-template,arv752DPW22_brnboot,BRN)
-Package/uboot-lantiq-arv7518PW_flash=$(call Package/uboot-lantiq-template,arv7518PW_flash,NOR)
-Package/uboot-lantiq-arv7518PW_ramboot=$(call Package/uboot-lantiq-template,arv7518PW_ramboot,RAM)
-Package/uboot-lantiq-arv7518PW_brnboot=$(call Package/uboot-lantiq-template,arv7518PW_brnboot,BRN)
-
-DDR_CONFIG_arv3527P_ramboot:=arcadyan_psc166_32
-DDR_CONFIG_arv4518PW_ramboot:=arcadyan_psc166_64
-DDR_CONFIG_arv4519PW_ramboot:=arcadyan_psc166_32
-DDR_CONFIG_arv4520PW_ramboot:=arcadyan_psc166_32
-DDR_CONFIG_arv4525PW_ramboot:=arcadyan_psc166_32
-DDR_CONFIG_arv7525PW_ramboot:=arcadyan_psc166_32
-DDR_CONFIG_arv452CPW_ramboot:=arcadyan_psc166_32
-DDR_CONFIG_arv752DPW_ramboot:=arcadyan_psc166_64
-DDR_CONFIG_arv752DPW22_ramboot:=arcadyan_psc166_64
-DDR_CONFIG_arv7518PW_ramboot:=arcadyan_psc166_64
-
-define Build/Prepare
- $(PKG_UNPACK)
- cp -r $(CP_OPTS) $(FILES_DIR)/* $(PKG_BUILD_DIR)/
- $(Build/Patch)
- find $(PKG_BUILD_DIR) -name .svn | $(XARGS) rm -rf
-endef
-
-UBOOT_MAKE_OPTS:= \
- CROSS_COMPILE=$(TARGET_CROSS) \
- ENDIANNESS= \
- V=1
-
-define Build/Configure/Target
- $(MAKE) -s -C $(PKG_BUILD_DIR) \
- $(UBOOT_MAKE_OPTS) \
- O=$(PKG_BUILD_DIR)/$(BUILD_VARIANT) \
- $(1)_config
-endef
-
-define Build/Configure
- $(call Build/Configure/Target,$(BUILD_VARIANT))
-endef
-
-define Build/Compile/Target
- $(MAKE) -s -C $(PKG_BUILD_DIR) \
- $(UBOOT_MAKE_OPTS) \
- O=$(PKG_BUILD_DIR)/$(1) \
- all
-endef
-
-define Build/Compile
- $(call Build/Compile/Target,$(BUILD_VARIANT))
-endef
-
-define Package/uboot-lantiq-$(BUILD_VARIANT)/install
- mkdir -p $(1)
-ifneq ($(findstring flash,$(BUILD_VARIANT)),)
- dd \
- if=$(PKG_BUILD_DIR)/$(BUILD_VARIANT)/u-boot-bootstrap.bin \
- of=$(1)/u-boot-bootstrap.bin \
- bs=64k conv=sync
-else
- dd \
- if=$(PKG_BUILD_DIR)/$(BUILD_VARIANT)/u-boot.bin \
- of=$(1)/u-boot.bin \
- bs=64k conv=sync
-endif
-ifneq ($(findstring ramboot,$(BUILD_VARIANT)),)
- if [ -e $(DDR_CONFIG_$(BUILD_VARIANT)).conf ]; then \
- perl ./gct \
- $(DDR_CONFIG_$(BUILD_VARIANT)).conf \
- $(PKG_BUILD_DIR)/$(BUILD_VARIANT)/u-boot.srec \
- $(1)/u-boot.asc; \
- fi
-endif
-endef
-
-$(eval $(call BuildPackage,uboot-lantiq-easy50712_DDR166M_flash))
-$(eval $(call BuildPackage,uboot-lantiq-easy50712_DDR166M_ramboot))
-$(eval $(call BuildPackage,uboot-lantiq-easy50812_DDR166M_flash))
-$(eval $(call BuildPackage,uboot-lantiq-easy50812_DDR166M_ramboot))
-$(eval $(call BuildPackage,uboot-lantiq-gigaSX76X_DDRsamsung166_flash))
-$(eval $(call BuildPackage,uboot-lantiq-gigaSX76X_DDRsamsung166_ramboot))
-#$(eval $(call BuildPackage,uboot-lantiq-arv3527P_flash))
-#$(eval $(call BuildPackage,uboot-lantiq-arv3527P_brnboot))
-#$(eval $(call BuildPackage,uboot-lantiq-arv3527P_ramboot))
-$(eval $(call BuildPackage,uboot-lantiq-arv4518PW_flash))
-$(eval $(call BuildPackage,uboot-lantiq-arv4518PW_brnboot))
-$(eval $(call BuildPackage,uboot-lantiq-arv4518PW_ramboot))
-$(eval $(call BuildPackage,uboot-lantiq-arv4519PW_flash))
-$(eval $(call BuildPackage,uboot-lantiq-arv4519PW_brnboot))
-$(eval $(call BuildPackage,uboot-lantiq-arv4519PW_ramboot))
-$(eval $(call BuildPackage,uboot-lantiq-arv4520PW_flash))
-$(eval $(call BuildPackage,uboot-lantiq-arv4520PW_brnboot))
-$(eval $(call BuildPackage,uboot-lantiq-arv4520PW_ramboot))
-$(eval $(call BuildPackage,uboot-lantiq-arv4525PW_flash))
-$(eval $(call BuildPackage,uboot-lantiq-arv4525PW_brnboot))
-$(eval $(call BuildPackage,uboot-lantiq-arv4525PW_ramboot))
-$(eval $(call BuildPackage,uboot-lantiq-arv7525PW_flash))
-$(eval $(call BuildPackage,uboot-lantiq-arv7525PW_brnboot))
-$(eval $(call BuildPackage,uboot-lantiq-arv7525PW_ramboot))
-$(eval $(call BuildPackage,uboot-lantiq-arv452CPW_flash))
-$(eval $(call BuildPackage,uboot-lantiq-arv452CPW_brnboot))
-$(eval $(call BuildPackage,uboot-lantiq-arv452CPW_ramboot))
-$(eval $(call BuildPackage,uboot-lantiq-arv752DPW_flash))
-$(eval $(call BuildPackage,uboot-lantiq-arv752DPW_brnboot))
-$(eval $(call BuildPackage,uboot-lantiq-arv752DPW_ramboot))
-$(eval $(call BuildPackage,uboot-lantiq-arv752DPW22_flash))
-$(eval $(call BuildPackage,uboot-lantiq-arv752DPW22_brnboot))
-$(eval $(call BuildPackage,uboot-lantiq-arv752DPW22_ramboot))
-$(eval $(call BuildPackage,uboot-lantiq-arv7518PW_flash))
-$(eval $(call BuildPackage,uboot-lantiq-arv7518PW_brnboot))
-$(eval $(call BuildPackage,uboot-lantiq-arv7518PW_ramboot))
-
+++ /dev/null
- 0xbf800060 0x7
- 0xbf800010 0x0
- 0xbf800020 0x0
- 0xbf800200 0x02
- 0xbf800210 0x0
-
- 0xbf801000 0x1b1b
- 0xbf801010 0x0
- 0xbf801020 0x0
- 0xbf801030 0x0
- 0xbf801040 0x0
- 0xbf801050 0x200
- 0xbf801060 0x605
- 0xbf801070 0x0303
- 0xbf801080 0x102
- 0xbf801090 0x70a
- 0xbf8010a0 0x203
- 0xbf8010b0 0xc02
- 0xbf8010c0 0x1c8
- 0xbf8010d0 0x1
- 0xbf8010e0 0x0
- 0xbf8010f0 0x120
- 0xbf801100 0xc800
- 0xbf801110 0xd
- 0xbf801120 0x301
- 0xbf801130 0x200
- 0xbf801140 0xa04
- 0xbf801150 0x1700
- 0xbf801160 0x1717
- 0xbf801170 0x0
- 0xbf801180 0x52
- 0xbf801190 0x0
- 0xbf8011a0 0x0
- 0xbf8011b0 0x0
- 0xbf8011c0 0x510
- 0xbf8011d0 0x4e20
- 0xbf8011e0 0x8235
- 0xbf8011f0 0x0
- 0xbf801200 0x0
- 0xbf801210 0x0
- 0xbf801220 0x0
- 0xbf801230 0x0
- 0xbf801240 0x0
- 0xbf801250 0x0
- 0xbf801260 0x0
- 0xbf801270 0x0
- 0xbf801280 0x0
- 0xbf801290 0x0
- 0xbf8012a0 0x0
- 0xbf8012b0 0x0
- 0xbf8012c0 0x0
- 0xbf8012d0 0x500
- 0xbf8012e0 0x0
-
- 0xbf800060 0x05
- 0xbf801030 0x100
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
+++ /dev/null
- 0xbf800060 0x7
- 0xbf800010 0x0
- 0xbf800020 0x0
- 0xbf800200 0x02
- 0xbf800210 0x0
-
-;REG32(MC_DC0) = 0x00001B1B;
- 0xbf801000 0x1b1b
-;REG32(MC_DC1) = 0x00000000;
- 0xbf801010 0x0
-;REG32(MC_DC2) = 0x00000000;
- 0xbf801020 0x0
-;REG32(MC_DC3) = 0x00000000;
- 0xbf801030 0x0
-;REG32(MC_DC4) = 0x00000000;
- 0xbf801040 0x0
-;REG32(MC_DC5) = 0x00000200;
- 0xbf801050 0x200
-;REG32(MC_DC6) = 0x00000306;
-; 0xbf801060 0x0306
- 0xbf801060 0x0605
-;REG32(MC_DC7) = 0x00000303;
-; 0xbf801070 0x302
-; 0xbf801070 0x0203
- 0xbf801070 0x0303
-;REG32(MC_DC8) = 0x00000102;
- 0xbf801080 0x102
-;REG32(MC_DC9) = 0x0000070A;
- 0xbf801090 0x70a
-; 0xbf801090 0x608
-;REG32(MC_DC10) = 0x00000203;
- 0xbf8010a0 0x203
-;REG32(MC_DC11) = 0x00000C02;
- 0xbf8010b0 0xc02
-; 0xbf8010b0 0x0a02
-;REG32(MC_DC12) = 0x000001C8;
- 0xbf8010c0 0x1c8
-;REG32(MC_DC13) = 0x00000001;
- 0xbf8010d0 0x1
-;REG32(MC_DC14) = 0x00000000;
- 0xbf8010e0 0x0
-;REG32(MC_DC15) = 0x00000F5F;
-; 0xbf8010f0 0xf5f
-; 0xbf8010f0 0xf3c
- 0xbf8010f0 0x130
-;REG32(MC_DC16) = 0x0000C800;
- 0xbf801100 0xc800
-;REG32(MC_DC17) = 0x0000000D;
-; 0xbf801110 0xd
- 0xbf801110 0xd
-;REG32(MC_DC18) = 0x00000300;
-; 0xbf801120 0x300
- 0xbf801120 0x301
-;REG32(MC_DC19) = 0x00000300;
-; 0xbf801130 0x300
- 0xbf801130 0x200
-;REG32(MC_DC20) = 0x00000A04;
-; 0xbf801140 0xa04
- 0xbf801140 0xa03
-;REG32(MC_DC21) = 0x00001c00;
-; 0xbf801150 0xd00
-; 0xbf801150 0x1f00
- 0xbf801150 0x1b00
-;REG32(MC_DC22) = 0x00001E1E;
-; 0xbf801160 0xd0d
-; 0xbf801160 0x1f1f
- 0xbf801160 0x1b1b
-;REG32(MC_DC23) = 0x00000000;
- 0xbf801170 0x0
-;//Disable ECC
-;REG32(MC_DC24) = 0x0000007F;
-; 0xbf801180 0x7f
-; 0xbf801180 0x062
-; 0xbf801180 0x37f
- 0xbf801180 0x59
-;REG32(MC_DC25) = 0x00000000;
- 0xbf801190 0x0
-;REG32(MC_DC26) = 0x00000000;
- 0xbf8011a0 0x0
-;REG32(MC_DC27) = 0x00000000;
- 0xbf8011b0 0x0
-;REG32(MC_DC28) = 0x00000A24;
-; 0xbf8011c0 0xa24
- 0xbf8011c0 0x510
-;REG32(MC_DC29) = 0x00002D89;
-; 0xbf8011d0 0x2d89
-; 0xbf8011d0 0x2d92
- 0xbf8011d0 0x4e20
-;REG32(MC_DC30) = 0x00000022;
-; 0xbf8011e0 0x8300
- 0xbf8011e0 0x8235
-;REG32(MC_DC31) = 0x00000000;
- 0xbf8011f0 0x0
-;REG32(MC_DC32) = 0x00000000;
- 0xbf801200 0x0
-;REG32(MC_DC33) = 0x00000000;
- 0xbf801210 0x0
-;REG32(MC_DC34) = 0x00000000;
- 0xbf801220 0x0
-;REG32(MC_DC35) = 0x00000000;
- 0xbf801230 0x0
-;REG32(MC_DC36) = 0x00000000;
- 0xbf801240 0x0
-;REG32(MC_DC37) = 0x00000000;
- 0xbf801250 0x0
-;REG32(MC_DC38) = 0x00000000;
- 0xbf801260 0x0
-;REG32(MC_DC39) = 0x00000000;
- 0xbf801270 0x0
-;REG32(MC_DC40) = 0x00000000;
- 0xbf801280 0x0
-;REG32(MC_DC41) = 0x00000000;
- 0xbf801290 0x0
-;REG32(MC_DC42) = 0x00000000;
- 0xbf8012a0 0x0
-;REG32(MC_DC43) = 0x00000000;
- 0xbf8012b0 0x0
-;REG32(MC_DC44) = 0x00000000;
- 0xbf8012c0 0x0
-;REG32(MC_DC45) = 0x00000600;
- 0xbf8012d0 0x500
-;REG32(MC_DC46) = 0x00000000;
- 0xbf8012e0 0x0
-
- 0xbf800060 0x05
- 0xbf801030 0x100
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
+++ /dev/null
- 0xbf800060 0x7
- 0xbf800010 0x0
- 0xbf800020 0x0
- 0xbf800200 0x02
- 0xbf800210 0x0
-
-;REG32(MC_DC0) = 0x00001B1B;
- 0xbf801000 0x1b1b
-;REG32(MC_DC1) = 0x00000000;
- 0xbf801010 0x0
-;REG32(MC_DC2) = 0x00000000;
- 0xbf801020 0x0
-;REG32(MC_DC3) = 0x00000000;
- 0xbf801030 0x0
-;REG32(MC_DC4) = 0x00000000;
- 0xbf801040 0x0
-;REG32(MC_DC5) = 0x00000200;
- 0xbf801050 0x200
-;REG32(MC_DC6) = 0x00000306;
-; 0xbf801060 0x0306
- 0xbf801060 0x0605
-;REG32(MC_DC7) = 0x00000303;
- 0xbf801070 0x302
-; 0xbf801070 0x0203
-;REG32(MC_DC8) = 0x00000102;
- 0xbf801080 0x102
-;REG32(MC_DC9) = 0x0000070A;
- 0xbf801090 0x70a
-; 0xbf801090 0x608
-;REG32(MC_DC10) = 0x00000203;
- 0xbf8010a0 0x203
-;REG32(MC_DC11) = 0x00000C02;
- 0xbf8010b0 0xc02
-; 0xbf8010b0 0x0a02
-;REG32(MC_DC12) = 0x000001C8;
- 0xbf8010c0 0x1c8
-;REG32(MC_DC13) = 0x00000001;
- 0xbf8010d0 0x1
-;REG32(MC_DC14) = 0x00000000;
- 0xbf8010e0 0x0
-;REG32(MC_DC15) = 0x00000F5F;
-; 0xbf8010f0 0xf5f
- 0xbf8010f0 0xf3c
-;REG32(MC_DC16) = 0x0000C800;
- 0xbf801100 0xc800
-;REG32(MC_DC17) = 0x0000000D;
-; 0xbf801110 0xd
- 0xbf801110 0xd
-;REG32(MC_DC18) = 0x00000300;
- 0xbf801120 0x300
-;REG32(MC_DC19) = 0x00000300;
-; 0xbf801130 0x300
- 0xbf801130 0x200
-;REG32(MC_DC20) = 0x00000A04;
-; 0xbf801140 0xa04
- 0xbf801140 0xa04
-;REG32(MC_DC21) = 0x00001c00;
- 0xbf801150 0xd00
-; 0xbf801150 0x1f00
-;REG32(MC_DC22) = 0x00001E1E;
- 0xbf801160 0xd0d
-; 0xbf801160 0x1f1f
-;REG32(MC_DC23) = 0x00000000;
- 0xbf801170 0x0
-;//Disable ECC
-;REG32(MC_DC24) = 0x0000007F;
-; 0xbf801180 0x7f
- 0xbf801180 0x062
-; 0xbf801180 0x37f
-;REG32(MC_DC25) = 0x00000000;
- 0xbf801190 0x0
-;REG32(MC_DC26) = 0x00000000;
- 0xbf8011a0 0x0
-;REG32(MC_DC27) = 0x00000000;
- 0xbf8011b0 0x0
-;REG32(MC_DC28) = 0x00000A24;
-; 0xbf8011c0 0xa24
- 0xbf8011c0 0x510
-;REG32(MC_DC29) = 0x00002D89;
- 0xbf8011d0 0x2d89
-; 0xbf8011d0 0x2d92
-;REG32(MC_DC30) = 0x00000022;
- 0xbf8011e0 0x8300
-; 0xbf8011e0 0x8235
-;REG32(MC_DC31) = 0x00000000;
- 0xbf8011f0 0x0
-;REG32(MC_DC32) = 0x00000000;
- 0xbf801200 0x0
-;REG32(MC_DC33) = 0x00000000;
- 0xbf801210 0x0
-;REG32(MC_DC34) = 0x00000000;
- 0xbf801220 0x0
-;REG32(MC_DC35) = 0x00000000;
- 0xbf801230 0x0
-;REG32(MC_DC36) = 0x00000000;
- 0xbf801240 0x0
-;REG32(MC_DC37) = 0x00000000;
- 0xbf801250 0x0
-;REG32(MC_DC38) = 0x00000000;
- 0xbf801260 0x0
-;REG32(MC_DC39) = 0x00000000;
- 0xbf801270 0x0
-;REG32(MC_DC40) = 0x00000000;
- 0xbf801280 0x0
-;REG32(MC_DC41) = 0x00000000;
- 0xbf801290 0x0
-;REG32(MC_DC42) = 0x00000000;
- 0xbf8012a0 0x0
-;REG32(MC_DC43) = 0x00000000;
- 0xbf8012b0 0x0
-;REG32(MC_DC44) = 0x00000000;
- 0xbf8012c0 0x0
-;REG32(MC_DC45) = 0x00000600;
- 0xbf8012d0 0x500
-;REG32(MC_DC46) = 0x00000000;
- 0xbf8012e0 0x0
-
- 0xbf800060 0x05
- 0xbf801030 0x100
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
+++ /dev/null
-0xbf800060 0x0000000f
-0xbf800010 0x00000000
-0xbf800020 0x00000000
-0xbf800200 0x00000002
-0xbf800210 0x00000000
-0xbf801000 0x00001b1b
-0xbf801010 0x00000000
-0xbf801020 0x00000000
-0xbf801030 0x00000000
-0xbf801040 0x00000000
-0xbf801050 0x00000200
-0xbf801060 0x00000306
-0xbf801070 0x00000303
-0xbf801080 0x00000102
-0xbf801090 0x0000070a
-0xbf8010a0 0x00000203
-0xbf8010b0 0x00000c02
-0xbf8010c0 0x000001c8
-0xbf8010d0 0x00000001
-0xbf8010e0 0x00000000
-0xbf8010f0 0x00000139
-0xbf801100 0x00002200
-0xbf801110 0x0000000d
-0xbf801120 0x00000301
-0xbf801130 0x00000200
-0xbf801140 0x00000a04
-0xbf801150 0x00001800
-0xbf801160 0x00001818
-0xbf801170 0x00000000
-0xbf801180 0x00000059
-0xbf801190 0x00000000
-0xbf8011a0 0x00000000
-0xbf8011b0 0x00000000
-0xbf8011c0 0x00000514
-0xbf8011d0 0x00002d93
-0xbf8011e0 0x00008235
-0xbf8011f0 0x00000000
-0xbf801200 0x00000000
-0xbf801210 0x00000000
-0xbf801220 0x00000000
-0xbf801230 0x00000000
-0xbf801240 0x00000000
-0xbf801250 0x00000000
-0xbf801260 0x00000000
-0xbf801270 0x00000000
-0xbf801280 0x00000000
-0xbf801290 0x00000000
-0xbf8012a0 0x00000000
-0xbf8012b0 0x00000000
-0xbf8012c0 0x00000000
-0xbf8012d0 0x00000600
-0xbf8012e0 0x00000000
-0xbf800060 0x0000000d
-0xbf801030 0x00000100
-
+++ /dev/null
-#
-# (C) Copyright 2003-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-include $(TOPDIR)/config.mk
-
-LIB = $(obj)lib$(BOARD).a
-BOOTSTRAP_LIB = $(obj)lib$(BOARD)_bootstrap.a
-
-BOOTSTRAP_LIB-$(CONFIG_BOOTSTRAP) = $(BOOTSTRAP_LIB)
-
-COBJS-y += board.o athrs26_phy.o
-
-SOBJS = lowlevel_init.o pmuenable.o
-
-BOOTSTRAP_COBJS-$(CONFIG_BOOTSTRAP) = $(BOARD)_bootstrap.o
-BOOTSTRAP_SOBJS-$(CONFIG_BOOTSTRAP) = lowlevel_bootstrap_init.o
-
-BOOTSTRAP_SRCS := $(BOOTSTRAP_SOBJS-y:.o=.S) $(BOOTSTRAP_COBJS-y:.o=.c)
-
-SRCS := $(sort $(SOBJS:.o=.S) $(COBJS:.o=.c) $(BOOTSTRAP_SOBJS:.o=.S))
-OBJS := $(addprefix $(obj),$(COBJS-y))
-SOBJS := $(addprefix $(obj),$(SOBJS))
-BOOTSTRAP_OBJS := $(addprefix $(obj),$(BOOTSTRAP_COBJS-y))
-BOOTSTRAP_SOBJS := $(addprefix $(obj),$(BOOTSTRAP_SOBJS-y))
-
-
-all: $(obj).depend $(LIB) $(BOOTSTRAP_LIB)
-
-$(LIB): $(obj).depend $(OBJS) $(SOBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
-
-$(BOOTSTRAP_LIB): $(BOOTSTRAP_OBJS) $(BOOTSTRAP_SOBJS)
- $(AR) $(ARFLAGS) $@ $(BOOTSTRAP_OBJS) $(BOOTSTRAP_SOBJS)
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+++ /dev/null
-/*
- * (C) Copyright 2010 Industrie Dial Face S.p.A.
- * Luigi 'Comio' Mantellini, luigi.mantellini@idf-hit.com
- *
- * (C) Copyright 2007
- * Vlad Lungu vlad.lungu@windriver.com
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <command.h>
-#include <asm/mipsregs.h>
-#include <asm/io.h>
-
-phys_size_t bootstrap_initdram(int board_type)
-{
- /* Sdram is setup by assembler code */
- /* If memory could be changed, we should return the true value here */
- return CONFIG_SYS_MAX_RAM;
-}
-
-int bootstrap_checkboard(void)
-{
- return 0;
-}
-
-int bootstrap_misc_init_r(void)
-{
- set_io_port_base(0);
- return 0;
-}
+++ /dev/null
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License. See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright © 2003 Atheros Communications, Inc., All Rights Reserved.
- */
-
-/*
- * Manage the atheros ethernet PHY.
- *
- * All definitions in this file are operating system independent!
- */
-
-#include <config.h>
-#include <linux/types.h>
-#include <common.h>
-#include <miiphy.h>
-//#include "phy.h"
-//#include "ar7100_soc.h"
-#include "athrs26_phy.h"
-
-#define phy_reg_read(base, addr, reg, datap) \
- miiphy_read("lq_cpe_eth", addr, reg, datap);
-#define phy_reg_write(base, addr, reg, data) \
- miiphy_write("lq_cpe_eth", addr, reg, data);
-
-
-/* PHY selections and access functions */
-
-typedef enum {
- PHY_SRCPORT_INFO,
- PHY_PORTINFO_SIZE,
-} PHY_CAP_TYPE;
-
-typedef enum {
- PHY_SRCPORT_NONE,
- PHY_SRCPORT_VLANTAG,
- PHY_SRCPORT_TRAILER,
-} PHY_SRCPORT_TYPE;
-
-#ifdef DEBUG
-#define DRV_DEBUG 1
-#endif
-//#define DRV_DEBUG 1
-
-#define DRV_DEBUG_PHYERROR 0x00000001
-#define DRV_DEBUG_PHYCHANGE 0x00000002
-#define DRV_DEBUG_PHYSETUP 0x00000004
-
-#if DRV_DEBUG
-int athrPhyDebug = DRV_DEBUG_PHYERROR|DRV_DEBUG_PHYCHANGE|DRV_DEBUG_PHYSETUP;
-
-#define DRV_LOG(FLG, X0, X1, X2, X3, X4, X5, X6) \
-{ \
- if (athrPhyDebug & (FLG)) { \
- logMsg(X0, X1, X2, X3, X4, X5, X6); \
- } \
-}
-
-#define DRV_MSG(x,a,b,c,d,e,f) \
- logMsg(x,a,b,c,d,e,f)
-
-#define DRV_PRINT(FLG, X) \
-{ \
- if (athrPhyDebug & (FLG)) { \
- printf X; \
- } \
-}
-
-#else /* !DRV_DEBUG */
-#define DRV_LOG(DBG_SW, X0, X1, X2, X3, X4, X5, X6)
-#define DRV_MSG(x,a,b,c,d,e,f)
-#define DRV_PRINT(DBG_SW,X)
-#endif
-
-#define ATHR_LAN_PORT_VLAN 1
-#define ATHR_WAN_PORT_VLAN 2
-
-#define ENET_UNIT_LAN 0
-
-#define TRUE 1
-#define FALSE 0
-
-#define ATHR_PHY0_ADDR 0x0
-#define ATHR_PHY1_ADDR 0x1
-#define ATHR_PHY2_ADDR 0x2
-#define ATHR_PHY3_ADDR 0x3
-#define ATHR_PHY4_ADDR 0x4
-
-/*
- * Track per-PHY port information.
- */
-typedef struct {
- BOOL isEnetPort; /* normal enet port */
- BOOL isPhyAlive; /* last known state of link */
- int ethUnit; /* MAC associated with this phy port */
- uint32_t phyBase;
- uint32_t phyAddr; /* PHY registers associated with this phy port */
- uint32_t VLANTableSetting; /* Value to be written to VLAN table */
-} athrPhyInfo_t;
-
-/*
- * Per-PHY information, indexed by PHY unit number.
- */
-static athrPhyInfo_t athrPhyInfo[] = {
- {TRUE, /* phy port 0 -- LAN port 0 */
- FALSE,
- ENET_UNIT_LAN,
- 0,
- ATHR_PHY0_ADDR,
- ATHR_LAN_PORT_VLAN
- },
-
- {TRUE, /* phy port 1 -- LAN port 1 */
- FALSE,
- ENET_UNIT_LAN,
- 0,
- ATHR_PHY1_ADDR,
- ATHR_LAN_PORT_VLAN
- },
-
- {TRUE, /* phy port 2 -- LAN port 2 */
- FALSE,
- ENET_UNIT_LAN,
- 0,
- ATHR_PHY2_ADDR,
- ATHR_LAN_PORT_VLAN
- },
-
- {TRUE, /* phy port 3 -- LAN port 3 */
- FALSE,
- ENET_UNIT_LAN,
- 0,
- ATHR_PHY3_ADDR,
- ATHR_LAN_PORT_VLAN
- },
-
- {TRUE, /* phy port 4 -- WAN port or LAN port 4 */
- FALSE,
- 1,
- 0,
- ATHR_PHY4_ADDR,
- ATHR_LAN_PORT_VLAN /* Send to all ports */
- },
-
- {FALSE, /* phy port 5 -- CPU port (no RJ45 connector) */
- TRUE,
- ENET_UNIT_LAN,
- 0,
- 0x00,
- ATHR_LAN_PORT_VLAN /* Send to all ports */
- },
-};
-
-#ifdef CFG_ATHRHDR_EN
-typedef struct {
- uint8_t data[ATHRHDR_MAX_DATA];
- uint8_t len;
- uint32_t seq;
-} cmd_resp_t;
-
-typedef struct {
- uint16_t reg_addr;
- uint16_t cmd_len;
- uint8_t *reg_data;
-}cmd_write_t;
-
-static cmd_write_t cmd_write,cmd_read;
-static cmd_resp_t cmd_resp;
-static struct eth_device *lan_mac;
-//static atomic_t seqcnt = ATOMIC_INIT(0);
-static int seqcnt = 0;
-static int cmd = 1;
-//volatile uchar AthrHdrPkt[60];
-#endif
-
-#define ATHR_GLOBALREGBASE 0
-
-//#define ATHR_PHY_MAX (sizeof(athrPhyInfo) / sizeof(athrPhyInfo[0]))
-#define ATHR_PHY_MAX 5
-
-/* Range of valid PHY IDs is [MIN..MAX] */
-#define ATHR_ID_MIN 0
-#define ATHR_ID_MAX (ATHR_PHY_MAX-1)
-
-/* Convenience macros to access myPhyInfo */
-#define ATHR_IS_ENET_PORT(phyUnit) (athrPhyInfo[phyUnit].isEnetPort)
-#define ATHR_IS_PHY_ALIVE(phyUnit) (athrPhyInfo[phyUnit].isPhyAlive)
-#define ATHR_ETHUNIT(phyUnit) (athrPhyInfo[phyUnit].ethUnit)
-#define ATHR_PHYBASE(phyUnit) (athrPhyInfo[phyUnit].phyBase)
-#define ATHR_PHYADDR(phyUnit) (athrPhyInfo[phyUnit].phyAddr)
-#define ATHR_VLAN_TABLE_SETTING(phyUnit) (athrPhyInfo[phyUnit].VLANTableSetting)
-
-
-#define ATHR_IS_ETHUNIT(phyUnit, ethUnit) \
- (ATHR_IS_ENET_PORT(phyUnit) && \
- ATHR_ETHUNIT(phyUnit) == (ethUnit))
-
-#define ATHR_IS_WAN_PORT(phyUnit) (!(ATHR_ETHUNIT(phyUnit)==ENET_UNIT_LAN))
-
-/* Forward references */
-BOOL athrs26_phy_is_link_alive(int phyUnit);
-//static uint32_t athrs26_reg_read(uint16_t reg_addr);
-static void athrs26_reg_write(uint16_t reg_addr,
- uint32_t reg_val);
-
-/******************************************************************************
-*
-* athrs26_phy_is_link_alive - test to see if the specified link is alive
-*
-* RETURNS:
-* TRUE --> link is alive
-* FALSE --> link is down
-*/
-
-void athrs26_reg_init(void)
-{
-
- athrs26_reg_write(0x200, 0x200);
- athrs26_reg_write(0x300, 0x200);
- athrs26_reg_write(0x400, 0x200);
- athrs26_reg_write(0x500, 0x200);
- athrs26_reg_write(0x600, 0x7d);
-
-#ifdef S26_VER_1_0
- phy_reg_write(0, 0, 29, 41);
- phy_reg_write(0, 0, 30, 0);
- phy_reg_write(0, 1, 29, 41);
- phy_reg_write(0, 1, 30, 0);
- phy_reg_write(0, 2, 29, 41);
- phy_reg_write(0, 2, 30, 0);
- phy_reg_write(0, 3, 29, 41);
- phy_reg_write(0, 3, 30, 0);
- phy_reg_write(0, 4, 29, 41);
- phy_reg_write(0, 4, 30, 0);
-#endif
-
- athrs26_reg_write(0x38, 0xc000050e);
-
-#ifdef CFG_ATHRHDR_EN
- athrs26_reg_write(0x104, 0x4804);
-#else
- athrs26_reg_write(0x104, 0x4004);
-#endif
-
- athrs26_reg_write(0x60, 0xffffffff);
- athrs26_reg_write(0x64, 0xaaaaaaaa);
- athrs26_reg_write(0x68, 0x55555555);
- athrs26_reg_write(0x6c, 0x0);
-
- athrs26_reg_write(0x70, 0x41af);
-}
-
-BOOL
-athrs26_phy_is_link_alive(int phyUnit)
-{
- uint16_t phyHwStatus;
- uint32_t phyBase;
- uint32_t phyAddr;
-
- phyBase = ATHR_PHYBASE(phyUnit);
- phyAddr = ATHR_PHYADDR(phyUnit);
-
- phy_reg_read(phyBase, phyAddr, ATHR_PHY_SPEC_STATUS, &phyHwStatus);
-
- if (phyHwStatus & ATHR_STATUS_LINK_PASS)
- return TRUE;
-
- return FALSE;
-}
-
-
-/******************************************************************************
-*
-* athrs26_phy_setup - reset and setup the PHY associated with
-* the specified MAC unit number.
-*
-* Resets the associated PHY port.
-*
-* RETURNS:
-* TRUE --> associated PHY is alive
-* FALSE --> no LINKs on this ethernet unit
-*/
-
-BOOL
-athrs26_phy_setup(int ethUnit)
-{
- int phyUnit;
- uint16_t phyHwStatus;
- uint16_t timeout;
- int liveLinks = 0;
- uint32_t phyBase = 0;
- BOOL foundPhy = FALSE;
- uint32_t phyAddr = 0;
- uint32_t regVal;
-
-
- /* See if there's any configuration data for this enet */
- /* start auto negogiation on each phy */
- for (phyUnit=0; phyUnit < ATHR_PHY_MAX; phyUnit++) {
- if (!ATHR_IS_ETHUNIT(phyUnit, ethUnit)) {
- continue;
- }
-
-
- foundPhy = TRUE;
- phyBase = ATHR_PHYBASE(phyUnit);
- phyAddr = ATHR_PHYADDR(phyUnit);
-
- phy_reg_write(phyBase, phyAddr, ATHR_AUTONEG_ADVERT,
- ATHR_ADVERTISE_ALL);
-
- /* Reset PHYs*/
- phy_reg_write(phyBase, phyAddr, ATHR_PHY_CONTROL,
- ATHR_CTRL_AUTONEGOTIATION_ENABLE
- | ATHR_CTRL_SOFTWARE_RESET);
-
- }
-
- if (!foundPhy) {
- return FALSE; /* No PHY's configured for this ethUnit */
- }
-
- /*
- * After the phy is reset, it takes a little while before
- * it can respond properly.
- */
- sysMsDelay(1000);
-
- /*
- * Wait up to .75 seconds for ALL associated PHYs to finish
- * autonegotiation. The only way we get out of here sooner is
- * if ALL PHYs are connected AND finish autonegotiation.
- */
- for (phyUnit=0; (phyUnit < ATHR_PHY_MAX) /*&& (timeout > 0) */; phyUnit++) {
- if (!ATHR_IS_ETHUNIT(phyUnit, ethUnit)) {
- continue;
- }
-
- timeout=20;
- for (;;) {
- phyHwStatus = 0;
- phy_reg_read(phyBase, phyAddr, ATHR_PHY_CONTROL, &phyHwStatus);
-
- if (ATHR_RESET_DONE(phyHwStatus)) {
- DRV_PRINT(DRV_DEBUG_PHYSETUP,
- ("Port %d, Neg Success\n", phyUnit));
- break;
- }
- if (timeout == 0) {
- DRV_PRINT(DRV_DEBUG_PHYSETUP,
- ("Port %d, Negogiation timeout\n", phyUnit));
- break;
- }
- if (--timeout == 0) {
- DRV_PRINT(DRV_DEBUG_PHYSETUP,
- ("Port %d, Negogiation timeout\n", phyUnit));
- break;
- }
-
- sysMsDelay(150);
- }
- }
-
- /*
- * All PHYs have had adequate time to autonegotiate.
- * Now initialize software status.
- *
- * It's possible that some ports may take a bit longer
- * to autonegotiate; but we can't wait forever. They'll
- * get noticed by mv_phyCheckStatusChange during regular
- * polling activities.
- */
- for (phyUnit=0; phyUnit < ATHR_PHY_MAX; phyUnit++) {
- if (!ATHR_IS_ETHUNIT(phyUnit, ethUnit)) {
- continue;
- }
-
- if (athrs26_phy_is_link_alive(phyUnit)) {
- liveLinks++;
- ATHR_IS_PHY_ALIVE(phyUnit) = TRUE;
- } else {
- ATHR_IS_PHY_ALIVE(phyUnit) = FALSE;
- }
-
- phy_reg_read(ATHR_PHYBASE(phyUnit), ATHR_PHYADDR(phyUnit),
- ATHR_PHY_SPEC_STATUS, ®Val);
- DRV_PRINT(DRV_DEBUG_PHYSETUP,
- ("eth%d: Phy Specific Status=%4.4x\n", ethUnit, regVal));
- }
-#if 0
- /* if using header for register configuration, we have to */
- /* configure s26 register after frame transmission is enabled */
-
- athrs26_reg_write(0x200, 0x200);
- athrs26_reg_write(0x300, 0x200);
- athrs26_reg_write(0x400, 0x200);
- athrs26_reg_write(0x500, 0x200);
- athrs26_reg_write(0x600, 0x200);
- athrs26_reg_write(0x38, 0x50e);
-#endif
-#ifndef CFG_ATHRHDR_EN
-/* if using header for register configuration, we have to */
- /* configure s26 register after frame transmission is enabled */
- athrs26_reg_init();
-#endif
-
- return (liveLinks > 0);
-}
-
-/******************************************************************************
-*
-* athrs26_phy_is_fdx - Determines whether the phy ports associated with the
-* specified device are FULL or HALF duplex.
-*
-* RETURNS:
-* 1 --> FULL
-* 0 --> HALF
-*/
-int
-athrs26_phy_is_fdx(int ethUnit)
-{
- int phyUnit;
- uint32_t phyBase;
- uint32_t phyAddr;
- uint16_t phyHwStatus;
- int ii = 200;
-
- if (ethUnit == ENET_UNIT_LAN)
- return TRUE;
-
- for (phyUnit=0; phyUnit < ATHR_PHY_MAX; phyUnit++) {
- if (!ATHR_IS_ETHUNIT(phyUnit, ethUnit)) {
- continue;
- }
-
- if (athrs26_phy_is_link_alive(phyUnit)) {
-
- phyBase = ATHR_PHYBASE(phyUnit);
- phyAddr = ATHR_PHYADDR(phyUnit);
-
- do {
- phy_reg_read(phyBase, phyAddr, ATHR_PHY_SPEC_STATUS, &phyHwStatus);
- sysMsDelay(10);
- } while((!(phyHwStatus & ATHR_STATUS_RESOVLED)) && --ii);
-
- if (phyHwStatus & ATHER_STATUS_FULL_DEPLEX)
- return TRUE;
- }
- }
-
- return FALSE;
-}
-
-
-/******************************************************************************
-*
-* athrs26_phy_speed - Determines the speed of phy ports associated with the
-* specified device.
-*
-* RETURNS:
-* AG7100_PHY_SPEED_10T, AG7100_PHY_SPEED_100TX;
-* AG7100_PHY_SPEED_1000T;
-*/
-
-BOOL
-athrs26_phy_speed(int ethUnit)
-{
- int phyUnit;
- uint16_t phyHwStatus;
- uint32_t phyBase;
- uint32_t phyAddr;
- int ii = 200;
-
- if (ethUnit == ENET_UNIT_LAN)
- return _100BASET;
-
- for (phyUnit=0; phyUnit < ATHR_PHY_MAX; phyUnit++) {
- if (!ATHR_IS_ETHUNIT(phyUnit, ethUnit)) {
- continue;
- }
-
- if (athrs26_phy_is_link_alive(phyUnit)) {
-
- phyBase = ATHR_PHYBASE(phyUnit);
- phyAddr = ATHR_PHYADDR(phyUnit);
-
- do {
- phy_reg_read(phyBase, phyAddr,
- ATHR_PHY_SPEC_STATUS, &phyHwStatus);
- sysMsDelay(10);
- }while((!(phyHwStatus & ATHR_STATUS_RESOVLED)) && --ii);
-
- phyHwStatus = ((phyHwStatus & ATHER_STATUS_LINK_MASK) >>
- ATHER_STATUS_LINK_SHIFT);
-
- switch(phyHwStatus) {
- case 0:
- return _10BASET;
- case 1:
- return _100BASET;
- case 2:
- return _1000BASET;
- default:
- DRV_PRINT(DRV_DEBUG_PHYERROR, ("Unkown speed read!\n"));
- }
- }
- }
-
- return _10BASET;
-}
-
-/*****************************************************************************
-*
-* athr_phy_is_up -- checks for significant changes in PHY state.
-*
-* A "significant change" is:
-* dropped link (e.g. ethernet cable unplugged) OR
-* autonegotiation completed + link (e.g. ethernet cable plugged in)
-*
-* When a PHY is plugged in, phyLinkGained is called.
-* When a PHY is unplugged, phyLinkLost is called.
-*/
-
-int
-athrs26_phy_is_up(int ethUnit)
-{
- int phyUnit;
- uint16_t phyHwStatus;
- athrPhyInfo_t *lastStatus;
- int linkCount = 0;
- int lostLinks = 0;
- int gainedLinks = 0;
- uint32_t phyBase;
- uint32_t phyAddr;
-#ifdef CFG_ATHRHDR_REG
- /* if using header to config s26, the link of MAC0 should always be up */
- if (ethUnit == ENET_UNIT_LAN)
- return 1;
-#endif
-
- for (phyUnit=0; phyUnit < ATHR_PHY_MAX; phyUnit++) {
- if (!ATHR_IS_ETHUNIT(phyUnit, ethUnit)) {
- continue;
- }
-
- phyBase = ATHR_PHYBASE(phyUnit);
- phyAddr = ATHR_PHYADDR(phyUnit);
-
-
- lastStatus = &athrPhyInfo[phyUnit];
- phy_reg_read(phyBase, phyAddr, ATHR_PHY_SPEC_STATUS, &phyHwStatus);
-
- if (lastStatus->isPhyAlive) { /* last known link status was ALIVE */
- /* See if we've lost link */
- if (phyHwStatus & ATHR_STATUS_LINK_PASS) {
- linkCount++;
- } else {
- lostLinks++;
- DRV_PRINT(DRV_DEBUG_PHYCHANGE,("\nenet%d port%d down\n",
- ethUnit, phyUnit));
- lastStatus->isPhyAlive = FALSE;
- }
- } else { /* last known link status was DEAD */
- /* Check for reset complete */
- phy_reg_read(phyBase, phyAddr, ATHR_PHY_STATUS, &phyHwStatus);
- if (!ATHR_RESET_DONE(phyHwStatus))
- continue;
-
- /* Check for AutoNegotiation complete */
- if (ATHR_AUTONEG_DONE(phyHwStatus)) {
- //printk("autoneg done\n");
- gainedLinks++;
- linkCount++;
- DRV_PRINT(DRV_DEBUG_PHYCHANGE,("\nenet%d port%d up\n",
- ethUnit, phyUnit));
- lastStatus->isPhyAlive = TRUE;
- }
- }
- }
-
- return (linkCount);
-
-#if 0
- if (linkCount == 0) {
- if (lostLinks) {
- /* We just lost the last link for this MAC */
- phyLinkLost(ethUnit);
- }
- } else {
- if (gainedLinks == linkCount) {
- /* We just gained our first link(s) for this MAC */
- phyLinkGained(ethUnit);
- }
- }
-#endif
-}
-
-#ifdef CFG_ATHRHDR_EN
-void athr_hdr_timeout(void){
- eth_halt();
- NetState = NETLOOP_FAIL;
-}
-
-void athr_hdr_handler(uchar *recv_pkt, unsigned dest, unsigned src, unsigned len){
- header_receive_pkt(recv_pkt);
- NetState = NETLOOP_SUCCESS;
-}
-static int
-athrs26_header_config_reg (struct eth_device *dev, uint8_t wr_flag,
- uint16_t reg_addr, uint16_t cmd_len,
- uint8_t *val)
-{
- at_header_t at_header;
- reg_cmd_t reg_cmd;
- uchar *AthrHdrPkt;
-
- AthrHdrPkt = NetTxPacket;
-
- if(AthrHdrPkt == NULL) {
- printf("Null packet\n");
- return;
- }
- memset(AthrHdrPkt,0,60);
-
- /*fill at_header*/
- at_header.reserved0 = 0x10; //default
- at_header.priority = 0;
- at_header.type = 0x5;
- at_header.broadcast = 0;
- at_header.from_cpu = 1;
- at_header.reserved1 = 0x01; //default
- at_header.port_num = 0;
-
- AthrHdrPkt[0] = at_header.port_num;
- AthrHdrPkt[0] |= at_header.reserved1 << 4;
- AthrHdrPkt[0] |= at_header.from_cpu << 6;
- AthrHdrPkt[0] |= at_header.broadcast << 7;
-
- AthrHdrPkt[1] = at_header.type;
- AthrHdrPkt[1] |= at_header.priority << 4;
- AthrHdrPkt[1] |= at_header.reserved0 << 6;
-
-
- /*fill reg cmd*/
- if(cmd_len > 4)
- cmd_len = 4;//only support 32bits register r/w
-
- reg_cmd.reg_addr = reg_addr&0x3FFFC;
- reg_cmd.cmd_len = cmd_len;
- reg_cmd.cmd = wr_flag;
- reg_cmd.reserved2 = 0x5; //default
- reg_cmd.seq_num = seqcnt;
-
- AthrHdrPkt[2] = reg_cmd.reg_addr & 0xff;
- AthrHdrPkt[3] = (reg_cmd.reg_addr & 0xff00) >> 8;
- AthrHdrPkt[4] = (reg_cmd.reg_addr & 0x30000) >> 16;
- AthrHdrPkt[4] |= reg_cmd.cmd_len << 4;
- AthrHdrPkt[5] = reg_cmd.cmd << 4;
- AthrHdrPkt[5] |= reg_cmd.reserved2 << 5;
- AthrHdrPkt[6] = (reg_cmd.seq_num & 0x7f) << 1;
- AthrHdrPkt[7] = (reg_cmd.seq_num & 0x7f80) >> 7;
- AthrHdrPkt[8] = (reg_cmd.seq_num & 0x7f8000) >> 15;
- AthrHdrPkt[9] = (reg_cmd.seq_num & 0x7f800000) >> 23;
-
- /*fill reg data*/
- if(!wr_flag)//write
- memcpy((AthrHdrPkt + 10), val, cmd_len);
-
- /*start xmit*/
- if(dev == NULL) {
- printf("ERROR device not found\n");
- return -1;
- }
- header_xmit(dev, AthrHdrPkt ,60);
- return 0;
-}
-void athr_hdr_func(void) {
-
- NetSetTimeout (1 * CFG_HZ,athr_hdr_timeout );
- NetSetHandler (athr_hdr_handler);
-
- if(cmd)
- athrs26_header_config_reg(lan_mac, cmd, cmd_read.reg_addr, cmd_read.cmd_len, cmd_read.reg_data);
- else
- athrs26_header_config_reg(lan_mac, cmd, cmd_write.reg_addr, cmd_write.cmd_len, cmd_write.reg_data);
-}
-static int
-athrs26_header_write_reg(uint16_t reg_addr, uint16_t cmd_len, uint8_t *reg_data)
-{
- int i = 2;
- cmd_write.reg_addr = reg_addr;
- cmd_write.cmd_len = cmd_len;
- cmd_write.reg_data = reg_data;
- cmd = 0;
- seqcnt++;
-
- do {
- if (NetLoop(ATHRHDR) >= 0) /* polls for read/write ack from PHY */
- break;
- } while (i--);
-
- return i;
-}
-
-static int
-athrs26_header_read_reg(uint16_t reg_addr, uint16_t cmd_len, uint8_t *reg_data)
-{
- int i = 2;
-
- cmd_read.reg_addr = reg_addr;
- cmd_read.cmd_len = cmd_len;
- cmd_read.reg_data = reg_data;
- cmd = 1;
- seqcnt++;
-
- do {
- if (NetLoop(ATHRHDR) >= 0) /* polls for read/write ack from PHY */
- break;
- } while (i--);
-
- if ((i==0) || (seqcnt != cmd_resp.seq) || (cmd_len != cmd_resp.len)) {
- return -1;
- }
- memcpy (cmd_read.reg_data, cmd_resp.data, cmd_len);
- return 0;
-}
-int header_receive_pkt(uchar *recv_pkt)
-{
- cmd_resp.len = recv_pkt[4] >> 4;
- if (cmd_resp.len > 10)
- goto out;
-
- cmd_resp.seq = recv_pkt[6] >> 1;
- cmd_resp.seq |= recv_pkt[7] << 7;
- cmd_resp.seq |= recv_pkt[8] << 15;
- cmd_resp.seq |= recv_pkt[9] << 23;
-
- if (cmd_resp.seq < seqcnt)
- goto out;
- memcpy (cmd_resp.data, (recv_pkt + 10), cmd_resp.len);
-out:
- return 0;
-}
-
-void athrs26_reg_dev(struct eth_device *mac)
-{
- lan_mac = mac;
-}
-
-#endif
-
-/*static uint32_t
-athrs26_reg_read(uint16_t reg_addr)
-{
-#ifndef CFG_ATHRHDR_REG
- uint16_t reg_word_addr = reg_addr / 2, phy_val;
- uint32_t phy_addr;
- uint8_t phy_reg;
-
- phy_addr = 0x18;
- phy_reg = 0x0;
- phy_val = (reg_word_addr >> 8) & 0x1ff;
- phy_reg_write (0, phy_addr, phy_reg, phy_val);
-
- phy_addr = 0x10 | ((reg_word_addr >> 5) & 0x7);
- phy_reg = reg_word_addr & 0x1f;
- phy_reg_read(0, phy_addr, phy_reg, &phy_val);
-
- return phy_val;
-#else
- uint8_t reg_data[4];
-
- memset (reg_data, 0, 4);
- athrs26_header_read_reg(reg_addr, 4, reg_data);
- return (reg_data[0] | (reg_data[1] << 8) | (reg_data[2] << 16) | (reg_data[3] << 24));
-#endif
-}
-*/
-static void
-athrs26_reg_write(uint16_t reg_addr, uint32_t reg_val)
-{
-#ifndef CFG_ATHRHDR_REG
- uint16_t reg_word_addr = reg_addr / 2, phy_val;
- uint32_t phy_addr;
- uint8_t phy_reg;
-
- /* configure register high address */
- phy_addr = 0x18;
- phy_reg = 0x0;
- phy_val = (reg_word_addr >> 8) & 0x1ff; /* bit16-8 of reg address*/
- phy_reg_write (0, phy_addr, phy_reg, phy_val);
-
- /* read register with low address */
- phy_addr = 0x10 | ((reg_word_addr >> 5) & 0x7); /* bit7-5 of reg address */
- phy_reg = reg_word_addr & 0x1f; /* bit 4-0 of reg address */
- phy_reg_write (0, phy_addr, phy_reg, reg_val);
-#else
- uint8_t reg_data[4];
-
- memset (reg_data, 0, 4);
- reg_data[0] = (uint8_t)(0x00ff & reg_val);
- reg_data[1] = (uint8_t)((0xff00 & reg_val) >> 8);
- reg_data[2] = (uint8_t)((0xff0000 & reg_val) >> 16);
- reg_data[3] = (uint8_t)((0xff000000 & reg_val) >> 24);
-
- athrs26_header_write_reg (reg_addr, 4, reg_data);
-#endif
-
-}
-
+++ /dev/null
-#ifndef _ATHRS26_PHY_H
-#define _ATHRS26_PHY_H
-
-/*****************/
-/* PHY Registers */
-/*****************/
-#define ATHR_PHY_CONTROL 0
-#define ATHR_PHY_STATUS 1
-#define ATHR_PHY_ID1 2
-#define ATHR_PHY_ID2 3
-#define ATHR_AUTONEG_ADVERT 4
-#define ATHR_LINK_PARTNER_ABILITY 5
-#define ATHR_AUTONEG_EXPANSION 6
-#define ATHR_NEXT_PAGE_TRANSMIT 7
-#define ATHR_LINK_PARTNER_NEXT_PAGE 8
-#define ATHR_1000BASET_CONTROL 9
-#define ATHR_1000BASET_STATUS 10
-#define ATHR_PHY_SPEC_CONTROL 16
-#define ATHR_PHY_SPEC_STATUS 17
-#define ATHR_DEBUG_PORT_ADDRESS 29
-#define ATHR_DEBUG_PORT_DATA 30
-
-/* ATHR_PHY_CONTROL fields */
-#define ATHR_CTRL_SOFTWARE_RESET 0x8000
-#define ATHR_CTRL_SPEED_LSB 0x2000
-#define ATHR_CTRL_AUTONEGOTIATION_ENABLE 0x1000
-#define ATHR_CTRL_RESTART_AUTONEGOTIATION 0x0200
-#define ATHR_CTRL_SPEED_FULL_DUPLEX 0x0100
-#define ATHR_CTRL_SPEED_MSB 0x0040
-
-#define ATHR_RESET_DONE(phy_control) \
- (((phy_control) & (ATHR_CTRL_SOFTWARE_RESET)) == 0)
-
-/* Phy status fields */
-#define ATHR_STATUS_AUTO_NEG_DONE 0x0020
-
-#define ATHR_AUTONEG_DONE(ip_phy_status) \
- (((ip_phy_status) & \
- (ATHR_STATUS_AUTO_NEG_DONE)) == \
- (ATHR_STATUS_AUTO_NEG_DONE))
-
-/* Link Partner ability */
-#define ATHR_LINK_100BASETX_FULL_DUPLEX 0x0100
-#define ATHR_LINK_100BASETX 0x0080
-#define ATHR_LINK_10BASETX_FULL_DUPLEX 0x0040
-#define ATHR_LINK_10BASETX 0x0020
-
-/* Advertisement register. */
-#define ATHR_ADVERTISE_NEXT_PAGE 0x8000
-#define ATHR_ADVERTISE_ASYM_PAUSE 0x0800
-#define ATHR_ADVERTISE_PAUSE 0x0400
-#define ATHR_ADVERTISE_100FULL 0x0100
-#define ATHR_ADVERTISE_100HALF 0x0080
-#define ATHR_ADVERTISE_10FULL 0x0040
-#define ATHR_ADVERTISE_10HALF 0x0020
-
-#define ATHR_ADVERTISE_ALL (ATHR_ADVERTISE_10HALF | ATHR_ADVERTISE_10FULL | \
- ATHR_ADVERTISE_100HALF | ATHR_ADVERTISE_100FULL)
-
-/* 1000BASET_CONTROL */
-#define ATHR_ADVERTISE_1000FULL 0x0200
-
-/* Phy Specific status fields */
-#define ATHER_STATUS_LINK_MASK 0xC000
-#define ATHER_STATUS_LINK_SHIFT 14
-#define ATHER_STATUS_FULL_DEPLEX 0x2000
-#define ATHR_STATUS_LINK_PASS 0x0400
-#define ATHR_STATUS_RESOVLED 0x0800
-
-/*phy debug port register */
-#define ATHER_DEBUG_SERDES_REG 5
-
-/* Serdes debug fields */
-#define ATHER_SERDES_BEACON 0x0100
-
-#ifndef BOOL
-#define BOOL int
-#define TRUE 1
-#define FALSE 0
-#endif
-
-#define sysMsDelay(_x) udelay((_x) * 1000)
-
-#undef S26_VER_1_0
-
-#ifdef CFG_ATHRHDR_EN
-
-#include <net.h>
-#define header_xmit(dev,pkt,len) dev->send(dev,pkt,len) //dev_queue_xmit(skb)
-#define header_recv_ack(dev) dev->recv(dev) //dev_queue_xmit(skb)
-
-typedef enum {
- NORMAL_PACKET,
- RESERVED0,
- MIB_1ST,
- RESERVED1,
- RESERVED2,
- READ_WRITE_REG,
- READ_WRITE_REG_ACK,
- RESERVED3
-} ATHR_HDR_TYPE;
-
-typedef struct {
- uint16_t reserved0;
- uint16_t priority;
- uint16_t type ;
- uint16_t broadcast;
- uint16_t from_cpu;
- uint16_t reserved1;
- uint16_t port_num;
-}at_header_t;
-
-typedef struct {
- uint64_t reg_addr;
- uint64_t reserved0;
- uint64_t cmd_len;
- uint64_t reserved1;
- uint64_t cmd;
- uint64_t reserved2;
- uint64_t seq_num;
-}reg_cmd_t;
-void athrs26_reg_init(void);
-int header_receive_pkt(uchar *pkt);
-void athrs26_reg_dev(struct eth_device *mac);
-
-#endif
-
-int athrs26_phy_is_up(int unit);
-int athrs26_phy_is_fdx(int unit);
-int athrs26_phy_speed(int unit);
-BOOL athrs26_phy_setup(int unit);
-
-#endif /* _ATHRS26_PHY_H */
-
+++ /dev/null
-/*
- * (C) Copyright 2003
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * (C) Copyright 2010
- * Thomas Langer, Ralph Hempel
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <command.h>
-#include <netdev.h>
-#include <miiphy.h>
-#include <asm/addrspace.h>
-#include <asm/danube.h>
-#include <asm/reboot.h>
-#include <asm/io.h>
-#if defined(CONFIG_CMD_HTTPD)
-#include <httpd.h>
-#endif
-#if defined(CONFIG_PCI)
-#include <pci.h>
-#endif
-#if defined(CONFIG_AR8216_SWITCH)
-#include "athrs26_phy.h"
-#endif
-
-extern ulong ifx_get_ddr_hz(void);
-extern ulong ifx_get_cpuclk(void);
-
-/* IDs and registers of known external switches */
-void _machine_restart(void)
-{
- *DANUBE_RCU_RST_REQ |=1<<30;
-}
-
-#ifdef CONFIG_SYS_RAMBOOT
-phys_size_t initdram(int board_type)
-{
- return get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, CONFIG_SYS_MAX_RAM);
-}
-#elif defined(CONFIG_USE_DDR_RAM)
-phys_size_t initdram(int board_type)
-{
- return (CONFIG_SYS_MAX_RAM);
-}
-#else
-
-static ulong max_sdram_size(void) /* per Chip Select */
-{
- /* The only supported SDRAM data width is 16bit.
- */
-#define CFG_DW 4
-
- /* The only supported number of SDRAM banks is 4.
- */
-#define CFG_NB 4
-
- ulong cfgpb0 = *DANUBE_SDRAM_MC_CFGPB0;
- int cols = cfgpb0 & 0xF;
- int rows = (cfgpb0 & 0xF0) >> 4;
- ulong size = (1 << (rows + cols)) * CFG_DW * CFG_NB;
-
- return size;
-}
-
-/*
- * Check memory range for valid RAM. A simple memory test determines
- * the actually available RAM size between addresses `base' and
- * `base + maxsize'.
- */
-
-static long int dram_size(long int *base, long int maxsize)
-{
- volatile long int *addr;
- ulong cnt, val;
- ulong save[32]; /* to make test non-destructive */
- unsigned char i = 0;
-
- for (cnt = (maxsize / sizeof (long)) >> 1; cnt > 0; cnt >>= 1) {
- addr = base + cnt; /* pointer arith! */
-
- save[i++] = *addr;
- *addr = ~cnt;
- }
-
- /* write 0 to base address */
- addr = base;
- save[i] = *addr;
- *addr = 0;
-
- /* check at base address */
- if ((val = *addr) != 0) {
- *addr = save[i];
- return (0);
- }
-
- for (cnt = 1; cnt < maxsize / sizeof (long); cnt <<= 1) {
- addr = base + cnt; /* pointer arith! */
-
- val = *addr;
- *addr = save[--i];
-
- if (val != (~cnt)) {
- return (cnt * sizeof (long));
- }
- }
- return (maxsize);
-}
-
-phys_size_t initdram(int board_type)
-{
- int rows, cols, best_val = *DANUBE_SDRAM_MC_CFGPB0;
- ulong size, max_size = 0;
- ulong our_address;
-
- /* load t9 into our_address */
- asm volatile ("move %0, $25" : "=r" (our_address) :);
-
- /* Can't probe for RAM size unless we are running from Flash.
- * find out whether running from DRAM or Flash.
- */
- if (CPHYSADDR(our_address) < CPHYSADDR(PHYS_FLASH_1))
- {
- return max_sdram_size();
- }
-
- for (cols = 0x8; cols <= 0xC; cols++)
- {
- for (rows = 0xB; rows <= 0xD; rows++)
- {
- *DANUBE_SDRAM_MC_CFGPB0 = (0x14 << 8) |
- (rows << 4) | cols;
- size = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE,
- max_sdram_size());
-
- if (size > max_size)
- {
- best_val = *DANUBE_SDRAM_MC_CFGPB0;
- max_size = size;
- }
- }
- }
-
- *DANUBE_SDRAM_MC_CFGPB0 = best_val;
- return max_size;
-}
-#endif
-
-static void gpio_default(void)
-{
-#ifdef CONFIG_SWITCH_PORT0
- *DANUBE_GPIO_P0_ALTSEL0 &= ~(1<<CONFIG_SWITCH_PIN);
- *DANUBE_GPIO_P0_ALTSEL1 &= ~(1<<CONFIG_SWITCH_PIN);
- *DANUBE_GPIO_P0_OD |= (1<<CONFIG_SWITCH_PIN);
- *DANUBE_GPIO_P0_DIR |= (1<<CONFIG_SWITCH_PIN);
- *DANUBE_GPIO_P0_OUT |= (1<<CONFIG_SWITCH_PIN);
-#elif defined(CONFIG_SWITCH_PORT1)
- *DANUBE_GPIO_P1_ALTSEL0 &= ~(1<<CONFIG_SWITCH_PIN);
- *DANUBE_GPIO_P1_ALTSEL1 &= ~(1<<CONFIG_SWITCH_PIN);
- *DANUBE_GPIO_P1_OD |= (1<<CONFIG_SWITCH_PIN);
- *DANUBE_GPIO_P1_DIR |= (1<<CONFIG_SWITCH_PIN);
- *DANUBE_GPIO_P1_OUT |= (1<<CONFIG_SWITCH_PIN);
-#endif
-#ifdef CONFIG_EBU_GPIO
- {
- int i = 0;
- printf ("bring up ebu gpio\n");
- *DANUBE_EBU_BUSCON1 = 0x1e7ff;
- *DANUBE_EBU_ADDSEL1 = 0x14000001;
-
- *((volatile u16*)0xb4000000) = 0x0;
- for(i = 0; i < 1000; i++)
- udelay(1000);
- *((volatile u16*)0xb4000000) = CONFIG_EBU_GPIO;
- *DANUBE_EBU_BUSCON1 = 0x8001e7ff;
- }
-#endif
-#ifdef CONFIG_BUTTON_PORT0
- *DANUBE_GPIO_P0_ALTSEL0 &= ~(1<<CONFIG_BUTTON_PIN);
- *DANUBE_GPIO_P0_ALTSEL1 &= ~(1<<CONFIG_BUTTON_PIN);
- *DANUBE_GPIO_P0_DIR &= ~(1<<CONFIG_BUTTON_PIN);
- if(!!(*DANUBE_GPIO_P0_IN & (1<<CONFIG_BUTTON_PIN)) == CONFIG_BUTTON_LEVEL)
- {
- printf("button is pressed\n");
- setenv("bootdelay", "0");
- setenv("bootcmd", "httpd");
- }
-#elif defined(CONFIG_BUTTON_PORT1)
- *DANUBE_GPIO_P1_ALTSEL0 &= ~(1<<CONFIG_BUTTON_PIN);
- *DANUBE_GPIO_P1_ALTSEL1 &= ~(1<<CONFIG_BUTTON_PIN);
- *DANUBE_GPIO_P1_DIR &= ~(1<<CONFIG_BUTTON_PIN);
- if(!!(*DANUBE_GPIO_P1_IN & (1<<CONFIG_BUTTON_PIN)) == CONFIG_BUTTON_LEVEL)
- {
- printf("button is pressed\n");
- setenv("bootdelay", "0");
- setenv("bootcmd", "httpd");
- }
-#endif
-#ifdef CONFIG_ARV4525
- *DANUBE_GPIO_P0_ALTSEL0 &= ~((1<<4)|(1<<5)|(1<<6)|(1<<8)|(1<<9));
- *DANUBE_GPIO_P0_ALTSEL1 &= ~((1<<4)|(1<<5)|(1<<6)|(1<<8)|(1<<9));
- *DANUBE_GPIO_P0_OD |= ((1<<4)|(1<<5)|(1<<6)|(1<<8)|(1<<9));
- *DANUBE_GPIO_P0_DIR |= ((1<<4)|(1<<5)|(1<<6)|(1<<8)|(1<<9));
- *DANUBE_GPIO_P0_OUT &= ~((1<<4)|(1<<5)|(1<<6)|(1<<8)|(1<<9));
-#endif
-}
-
-int checkboard (void)
-{
- unsigned long chipid = *DANUBE_MPS_CHIPID;
- int part_num;
-
- puts ("Board: "CONFIG_ARCADYAN"\n");
- puts ("SoC: ");
-
- part_num = DANUBE_MPS_CHIPID_PARTNUM_GET(chipid);
- switch (part_num)
- {
- case 0x129:
- case 0x12D:
- case 0x12b:
- puts("Danube/Twinpass/Vinax-VE ");
- break;
- default:
- printf ("unknown, chip part number 0x%03X ", part_num);
- break;
- }
- printf ("V1.%ld, ", DANUBE_MPS_CHIPID_VERSION_GET(chipid));
-
- printf("DDR Speed %ld MHz, ", ifx_get_ddr_hz()/1000000);
- printf("CPU Speed %ld MHz\n", ifx_get_cpuclk()/1000000);
-
-
- return 0;
-}
-
-#ifdef CONFIG_SKIP_LOWLEVEL_INIT
-int board_early_init_f(void)
-{
-#ifdef CONFIG_EBU_ADDSEL0
- (*DANUBE_EBU_ADDSEL0) = CONFIG_EBU_ADDSEL0;
-#endif
-#ifdef CONFIG_EBU_ADDSEL1
- (*DANUBE_EBU_ADDSEL1) = CONFIG_EBU_ADDSEL1;
-#endif
-#ifdef CONFIG_EBU_ADDSEL2
- (*DANUBE_EBU_ADDSEL2) = CONFIG_EBU_ADDSEL2;
-#endif
-#ifdef CONFIG_EBU_ADDSEL3
- (*DANUBE_EBU_ADDSEL3) = CONFIG_EBU_ADDSEL3;
-#endif
-#ifdef CONFIG_EBU_BUSCON0
- (*DANUBE_EBU_BUSCON0) = CONFIG_EBU_BUSCON0;
-#endif
-#ifdef CONFIG_EBU_BUSCON1
- (*DANUBE_EBU_BUSCON1) = CONFIG_EBU_BUSCON1;
-#endif
-#ifdef CONFIG_EBU_BUSCON2
- (*DANUBE_EBU_BUSCON2) = CONFIG_EBU_BUSCON2;
-#endif
-#ifdef CONFIG_EBU_BUSCON3
- (*DANUBE_EBU_BUSCON3) = CONFIG_EBU_BUSCON3;
-#endif
-
- return 0;
-}
-#endif /* CONFIG_SKIP_LOWLEVEL_INIT */
-
-#ifdef CONFIG_RTL8306_SWITCH
-#define ID_RTL8306 0x5988
-static int external_switch_rtl8306(void)
-{
- unsigned short chipid;
- static char * const name = "lq_cpe_eth";
-
- udelay(100000);
-
- puts("\nsearching for rtl8306 switch ... ");
- if (miiphy_read(name, 4, 30, &chipid) == 0) {
- if (chipid == ID_RTL8306) {
- puts("found");
- /* set led mode */
- miiphy_write(name, 0, 19, 0xffff);
- /* magic */
- miiphy_write(name, 4, 22, 0x877f);
- puts("\n");
- return 0;
- }
- puts("failed\n");
- }
- puts("\nno known switch found ... \n");
-
- return 0;
-}
-#endif
-
-#ifdef CONFIG_RTL8306G_SWITCH
-#define ID_RTL8306 0x5988
-
-static int external_switch_rtl8306G(void)
-{
- unsigned short chipid,val;
- int i;
- static char * const name = "lq_cpe_eth";
- unsigned int chipid2, chipver, chiptype;
- char str[128];
- int cpu_mask = 1 << 5;
- udelay(100000);
-
- puts("\nsearching for rtl8306 switch ... ");
- if (miiphy_read(name, 4, 30, &chipid) == 0) {
- if (chipid == ID_RTL8306) {
- puts("found\nReset Hard\n");
-#ifdef CONFIG_ARV752DPW
- //gpio 19
- //reset reset ping to high
- *DANUBE_GPIO_P1_DIR |= 8;
- *DANUBE_GPIO_P1_OUT |= 8;
- udelay(500*1000);
- *DANUBE_GPIO_P1_OUT &= ~(8); // now low again for at least 10 ms
- udelay(500*1000);
- *DANUBE_GPIO_P1_OUT |= 8;
- udelay(500*1000);
- puts("Done\n");
-#endif
- /* set led mode */
-
- miiphy_write(name, 0, 0, 0x3100);
- miiphy_write(name, 0, 18, 0x7fff);
- miiphy_write(name, 0, 19, 0xffff);
- miiphy_write(name, 0, 22, 0x877f);
- miiphy_write(name, 0, 24, 0x0ed1);
-
- miiphy_write(name, 1, 0, 0x3100);
- miiphy_write(name, 1, 22, 0x877f);
- miiphy_write(name, 1, 24, 0x1ed2);
-
- miiphy_write(name, 2, 0, 0x3100);
- miiphy_write(name, 2, 22, 0x877f);
- miiphy_write(name, 2, 23, 0x0020);
- miiphy_write(name, 2, 24, 0x2ed4);
-
- miiphy_write(name, 3, 0, 0x3100);
- miiphy_write(name, 3, 22, 0x877f);
- miiphy_write(name, 3, 24, 0x3ed8);
-
- miiphy_write(name, 4, 0, 0x3100);
- miiphy_write(name, 4, 22, 0x877f);
- miiphy_write(name, 4, 24, 0x4edf);
-
- miiphy_write(name, 5, 0, 0x3100);
- miiphy_write(name, 6, 0, 0x2100);
-
- //important. enable phy 5 link status, for rmii
- miiphy_write(name, 6, 22, 0x873f);
-
- miiphy_write(name, 6, 24, 0x8eff);
- //disable ports
- for (i=0;i<5;i++) {
- miiphy_read(name, 0, 24, &val);
- val&=~(1<<10);
- val&=~(1<<11);
- miiphy_write(name, 0, 24, val);
- }
-
- puts("Reset Soft\n");
- miiphy_write(name,0 ,0 ,1<<15);
- for (i=0;i<1000;i++)
- {
- miiphy_read(name,0 ,0 ,&val);
- if (!(val&1<<15))
- break;
- udelay(1000);
- }
- if (i==1000)
- puts("Failed\n");
- else
- puts("Success\n");
- //enable ports egain
- for (i=0;i<5;i++) // enable ports
- {
- miiphy_read(name, 0, 24, &val);
- val|=(1<<10);
- val|=(1<<11);
- miiphy_write(name, 0, 24, val);
- }
- puts("\n");
- return 0;
- }
- puts("failed\n");
- }
- puts("\nno known switch found ... \n");
-
- return 0;
-}
-#endif
-
-#ifdef CONFIG_AR8216_SWITCH
-static int external_switch_ar8216(void)
-{
- puts("initializing ar8216 switch... ");
- if (athrs26_phy_setup(0)==0) {
- printf("initialized\n");
- return 0;
- }
- puts("failed ... \n");
- return 0;
-}
-#endif
-
-int board_eth_init(bd_t *bis)
-{
- gpio_default();
-
-#if defined(CONFIG_IFX_ETOP)
- uchar enetaddr[6];
- if (!eth_getenv_enetaddr("ethaddr", enetaddr))
- eth_setenv_enetaddr("ethaddr", (uchar *)0xb03f0016);
-
- *DANUBE_PMU_PWDCR &= 0xFFFFEFDF;
- *DANUBE_PMU_PWDCR &=~(1<<DANUBE_PMU_DMA_SHIFT);/*enable DMA from PMU*/
-
- if (lq_eth_initialize(bis))
- return -1;
-
- *DANUBE_RCU_RST_REQ |=1;
- udelay(200000);
- *DANUBE_RCU_RST_REQ &=(unsigned long)~1;
- udelay(1000);
-
-#ifdef CONFIG_RTL8306G_SWITCH
- if (external_switch_rtl8306G()<0)
- return -1;
-#endif
-#ifdef CONFIG_RTL8306_SWITCH
- if (external_switch_rtl8306()<0)
- return -1;
-#endif
-#ifdef CONFIG_AR8216_SWITCH
- if (external_switch_ar8216()<0)
- return -1;
-#endif
-#endif
- return 0;
-}
-
-#if defined(CONFIG_CMD_HTTPD)
-int do_http_upgrade(const unsigned char *data, const ulong size)
-{
- char buf[128];
-
- if(getenv ("ram_addr") == NULL)
- return -1;
- if(getenv ("kernel_addr") == NULL)
- return -1;
- /* check the image */
- if(run_command("imi ${ram_addr}", 0) < 0) {
- return -1;
- }
- /* write the image to the flash */
- puts("http ugrade ...\n");
- sprintf(buf, "era ${kernel_addr} +0x%lx; cp.b ${ram_addr} ${kernel_addr} 0x%lx", size, size);
- return run_command(buf, 0);
-}
-
-int do_http_progress(const int state)
-{
- /* toggle LED's here */
- switch(state) {
- case HTTP_PROGRESS_START:
- puts("http start\n");
- break;
- case HTTP_PROGRESS_TIMEOUT:
- puts(".");
- break;
- case HTTP_PROGRESS_UPLOAD_READY:
- puts("http upload ready\n");
- break;
- case HTTP_PROGRESS_UGRADE_READY:
- puts("http ugrade ready\n");
- break;
- case HTTP_PROGRESS_UGRADE_FAILED:
- puts("http ugrade failed\n");
- break;
- }
- return 0;
-}
-
-unsigned long do_http_tmp_address(void)
-{
- char *s = getenv ("ram_addr");
- if (s) {
- ulong tmp = simple_strtoul (s, NULL, 16);
- return tmp;
- }
- return 0 /*0x80a00000*/;
-}
-
-#endif
+++ /dev/null
-#
-# (C) Copyright 2003
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-sinclude $(OBJTREE)/board/$(BOARDDIR)/config.tmp
-
-ifdef CONFIG_BOOTSTRAP
-TEXT_BASE = 0x80001000
-CONFIG_BOOTSTRAP_TEXT_BASE = 0xb0000000
-CONFIG_SYS_RAMBOOT = y
-else
-
-ifndef TEXT_BASE
-$(info redefine TEXT_BASE = 0xB0000000 )
-TEXT_BASE = 0xB0000000
-endif
-
-endif
+++ /dev/null
-/* Settings for Denali DDR SDRAM controller */
-/* Optimise for DDR PSC A3S12D40ETP for arv4518pw Danube Board DDR 166 Mhz - by Ngp 14th Sept. 2010 */
-
-#define MC_DC0_VALUE 0x1B1B
-#define MC_DC1_VALUE 0x0
-#define MC_DC2_VALUE 0x0
-#define MC_DC3_VALUE 0x0
-#define MC_DC4_VALUE 0x0
-#define MC_DC5_VALUE 0x200
-#define MC_DC6_VALUE 0x605
-#define MC_DC7_VALUE 0x303
-#define MC_DC8_VALUE 0x102
-#define MC_DC9_VALUE 0x70a
-#define MC_DC10_VALUE 0x203
-#define MC_DC11_VALUE 0xc02
-#define MC_DC12_VALUE 0x1C8
-#define MC_DC13_VALUE 0x1
-#define MC_DC14_VALUE 0x0
-#define MC_DC15_VALUE 0x130 /* WDQS tuning for clk_wr*/
-#define MC_DC16_VALUE 0xC800
-#define MC_DC17_VALUE 0xd
-#define MC_DC18_VALUE 0x301
-#define MC_DC19_VALUE 0x200
-#define MC_DC20_VALUE 0xA03 /* A04 for reference board, A03 for Eval board */
-#define MC_DC21_VALUE 0x1b00
-#define MC_DC22_VALUE 0x1b1b
-#define MC_DC23_VALUE 0x0
-#define MC_DC24_VALUE 0x59 /* WDQS Tuning for DQS */
-#define MC_DC25_VALUE 0x0
-#define MC_DC26_VALUE 0x0
-#define MC_DC27_VALUE 0x0
-#define MC_DC28_VALUE 0x510
-#define MC_DC29_VALUE 0x4e20
-#define MC_DC30_VALUE 0x8235
-#define MC_DC31_VALUE 0x0
-#define MC_DC32_VALUE 0x0
-#define MC_DC33_VALUE 0x0
-#define MC_DC34_VALUE 0x0
-#define MC_DC35_VALUE 0x0
-#define MC_DC36_VALUE 0x0
-#define MC_DC37_VALUE 0x0
-#define MC_DC38_VALUE 0x0
-#define MC_DC39_VALUE 0x0
-#define MC_DC40_VALUE 0x0
-#define MC_DC41_VALUE 0x0
-#define MC_DC42_VALUE 0x0
-#define MC_DC43_VALUE 0x0
-#define MC_DC44_VALUE 0x0
-#define MC_DC45_VALUE 0x500
-#define MC_DC46_VALUE 0x0
+++ /dev/null
-/* Settings for Denali DDR SDRAM controller */
-/* Optimise for PSC DDR A2S56D40CTP for Danube Ref Board DDR 166 Mhz - by Ng Aik Ann 27th Nov 2006 */
-
-#define MC_DC0_VALUE 0x1B1B
-#define MC_DC1_VALUE 0x0
-#define MC_DC2_VALUE 0x0
-#define MC_DC3_VALUE 0x0
-#define MC_DC4_VALUE 0x0
-#define MC_DC5_VALUE 0x200
-#define MC_DC6_VALUE 0x605
-#define MC_DC7_VALUE 0x303
-#define MC_DC8_VALUE 0x102
-#define MC_DC9_VALUE 0x70a
-#define MC_DC10_VALUE 0x203
-#define MC_DC11_VALUE 0xc02
-#define MC_DC12_VALUE 0x1C8
-#define MC_DC13_VALUE 0x1
-#define MC_DC14_VALUE 0x0
-#define MC_DC15_VALUE 0x120 /* WDQS tuning for clk_wr*/
-#define MC_DC16_VALUE 0xC800
-#define MC_DC17_VALUE 0xd
-#define MC_DC18_VALUE 0x301
-#define MC_DC19_VALUE 0x200
-#define MC_DC20_VALUE 0xA04 /* A04 for reference board, A03 for Eval board */
-#define MC_DC21_VALUE 0x1700
-#define MC_DC22_VALUE 0x1717
-#define MC_DC23_VALUE 0x0
-#define MC_DC24_VALUE 0x52 /* WDQS Tuning for DQS */
-#define MC_DC25_VALUE 0x0
-#define MC_DC26_VALUE 0x0
-#define MC_DC27_VALUE 0x0
-#define MC_DC28_VALUE 0x510
-#define MC_DC29_VALUE 0x4e20
-#define MC_DC30_VALUE 0x8235
-#define MC_DC31_VALUE 0x0
-#define MC_DC32_VALUE 0x0
-#define MC_DC33_VALUE 0x0
-#define MC_DC34_VALUE 0x0
-#define MC_DC35_VALUE 0x0
-#define MC_DC36_VALUE 0x0
-#define MC_DC37_VALUE 0x0
-#define MC_DC38_VALUE 0x0
-#define MC_DC39_VALUE 0x0
-#define MC_DC40_VALUE 0x0
-#define MC_DC41_VALUE 0x0
-#define MC_DC42_VALUE 0x0
-#define MC_DC43_VALUE 0x0
-#define MC_DC44_VALUE 0x0
-#define MC_DC45_VALUE 0x500
-//#define MC_DC45_VALUE 0x400
-#define MC_DC46_VALUE 0x0
+++ /dev/null
-#define MC_DC0_VALUE 0x1B1B
-#define MC_DC1_VALUE 0x0
-#define MC_DC2_VALUE 0x0
-#define MC_DC3_VALUE 0x0
-#define MC_DC4_VALUE 0x0
-#define MC_DC5_VALUE 0x200
-#define MC_DC6_VALUE 0x605
-#define MC_DC7_VALUE 0x303
-#define MC_DC8_VALUE 0x102
-#define MC_DC9_VALUE 0x70a
-#define MC_DC10_VALUE 0x203
-#define MC_DC11_VALUE 0xc02
-#define MC_DC12_VALUE 0x1C8
-#define MC_DC13_VALUE 0x1
-#define MC_DC14_VALUE 0x0
-#define MC_DC15_VALUE 0x134 /* WDQS tuning for clk_wr*/
-#define MC_DC16_VALUE 0xC800
-#define MC_DC17_VALUE 0xd
-#define MC_DC18_VALUE 0x301
-#define MC_DC19_VALUE 0x200
-#define MC_DC20_VALUE 0xA03 /* A04 for reference board, A03 for Eval board */
-#define MC_DC21_VALUE 0x1400
-#define MC_DC22_VALUE 0x1414
-#define MC_DC23_VALUE 0x0
-#define MC_DC24_VALUE 0x5b /* WDQS Tuning for DQS */
-#define MC_DC25_VALUE 0x0
-#define MC_DC26_VALUE 0x0
-#define MC_DC27_VALUE 0x0
-#define MC_DC28_VALUE 0x510
-#define MC_DC29_VALUE 0x4e20
-#define MC_DC30_VALUE 0x8235
-#define MC_DC31_VALUE 0x0
-#define MC_DC32_VALUE 0x0
-#define MC_DC33_VALUE 0x0
-#define MC_DC34_VALUE 0x0
-#define MC_DC35_VALUE 0x0
-#define MC_DC36_VALUE 0x0
-#define MC_DC37_VALUE 0x0
-#define MC_DC38_VALUE 0x0
-#define MC_DC39_VALUE 0x0
-#define MC_DC40_VALUE 0x0
-#define MC_DC41_VALUE 0x0
-#define MC_DC42_VALUE 0x0
-#define MC_DC43_VALUE 0x0
-#define MC_DC44_VALUE 0x0
-#define MC_DC45_VALUE 0x500
-#define MC_DC46_VALUE 0x0
+++ /dev/null
-/*
- * Memory sub-system initialization code for Danube board.
- * Andre Messerschmidt
- * Copyright (c) 2005 Infineon Technologies AG
- *
- * Based on Inca-IP code
- * Copyright (c) 2003 Wolfgang Denk <wd@denx.de>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-/* History:
- peng liu May 25, 2006, for PLL setting after reset, 05252006
- */
-#include <config.h>
-#include <version.h>
-#include <asm/regdef.h>
-
-#if defined(CONFIG_USE_DDR_PSC_32)
-#include "ddr_settings_psc_32.h"
-#define DDR166
-#elif defined(CONFIG_USE_DDR_PSC_64)
-#include "ddr_settings_psc_64.h"
-#define DDR166
-#else
-#error "missing definition for RAM"
-#endif
-
-#define EBU_MODUL_BASE 0xBE105300
-#define EBU_CLC(value) 0x0000(value)
-#define EBU_CON(value) 0x0010(value)
-#define EBU_ADDSEL0(value) 0x0020(value)
-#define EBU_ADDSEL1(value) 0x0024(value)
-#define EBU_ADDSEL2(value) 0x0028(value)
-#define EBU_ADDSEL3(value) 0x002C(value)
-#define EBU_BUSCON0(value) 0x0060(value)
-#define EBU_BUSCON1(value) 0x0064(value)
-#define EBU_BUSCON2(value) 0x0068(value)
-#define EBU_BUSCON3(value) 0x006C(value)
-
-#define MC_MODUL_BASE 0xBF800000
-#define MC_ERRCAUSE(value) 0x0010(value)
-#define MC_ERRADDR(value) 0x0020(value)
-#define MC_CON(value) 0x0060(value)
-
-#define MC_SRAM_ENABLE 0x00000004
-#define MC_SDRAM_ENABLE 0x00000002
-#define MC_DDRRAM_ENABLE 0x00000001
-
-#define MC_SDR_MODUL_BASE 0xBF800200
-#define MC_IOGP(value) 0x0000(value)
-#define MC_CTRLENA(value) 0x0010(value)
-#define MC_MRSCODE(value) 0x0020(value)
-#define MC_CFGDW(value) 0x0030(value)
-#define MC_CFGPB0(value) 0x0040(value)
-#define MC_LATENCY(value) 0x0080(value)
-#define MC_TREFRESH(value) 0x0090(value)
-#define MC_SELFRFSH(value) 0x00A0(value)
-
-#define MC_DDR_MODUL_BASE 0xBF801000
-#define MC_DC00(value) 0x0000(value)
-#define MC_DC01(value) 0x0010(value)
-#define MC_DC02(value) 0x0020(value)
-#define MC_DC03(value) 0x0030(value)
-#define MC_DC04(value) 0x0040(value)
-#define MC_DC05(value) 0x0050(value)
-#define MC_DC06(value) 0x0060(value)
-#define MC_DC07(value) 0x0070(value)
-#define MC_DC08(value) 0x0080(value)
-#define MC_DC09(value) 0x0090(value)
-#define MC_DC10(value) 0x00A0(value)
-#define MC_DC11(value) 0x00B0(value)
-#define MC_DC12(value) 0x00C0(value)
-#define MC_DC13(value) 0x00D0(value)
-#define MC_DC14(value) 0x00E0(value)
-#define MC_DC15(value) 0x00F0(value)
-#define MC_DC16(value) 0x0100(value)
-#define MC_DC17(value) 0x0110(value)
-#define MC_DC18(value) 0x0120(value)
-#define MC_DC19(value) 0x0130(value)
-#define MC_DC20(value) 0x0140(value)
-#define MC_DC21(value) 0x0150(value)
-#define MC_DC22(value) 0x0160(value)
-#define MC_DC23(value) 0x0170(value)
-#define MC_DC24(value) 0x0180(value)
-#define MC_DC25(value) 0x0190(value)
-#define MC_DC26(value) 0x01A0(value)
-#define MC_DC27(value) 0x01B0(value)
-#define MC_DC28(value) 0x01C0(value)
-#define MC_DC29(value) 0x01D0(value)
-#define MC_DC30(value) 0x01E0(value)
-#define MC_DC31(value) 0x01F0(value)
-#define MC_DC32(value) 0x0200(value)
-#define MC_DC33(value) 0x0210(value)
-#define MC_DC34(value) 0x0220(value)
-#define MC_DC35(value) 0x0230(value)
-#define MC_DC36(value) 0x0240(value)
-#define MC_DC37(value) 0x0250(value)
-#define MC_DC38(value) 0x0260(value)
-#define MC_DC39(value) 0x0270(value)
-#define MC_DC40(value) 0x0280(value)
-#define MC_DC41(value) 0x0290(value)
-#define MC_DC42(value) 0x02A0(value)
-#define MC_DC43(value) 0x02B0(value)
-#define MC_DC44(value) 0x02C0(value)
-#define MC_DC45(value) 0x02D0(value)
-#define MC_DC46(value) 0x02E0(value)
-
-#define RCU_OFFSET 0xBF203000
-#define RCU_RST_REQ (RCU_OFFSET + 0x0010)
-#define RCU_STS (RCU_OFFSET + 0x0014)
-
-#define CGU_OFFSET 0xBF103000
-#define PLL0_CFG (CGU_OFFSET + 0x0004)
-#define PLL1_CFG (CGU_OFFSET + 0x0008)
-#define PLL2_CFG (CGU_OFFSET + 0x000C)
-#define CGU_SYS (CGU_OFFSET + 0x0010)
-#define CGU_UPDATE (CGU_OFFSET + 0x0014)
-#define IF_CLK (CGU_OFFSET + 0x0018)
-#define CGU_SMD (CGU_OFFSET + 0x0020)
-#define CGU_CT1SR (CGU_OFFSET + 0x0028)
-#define CGU_CT2SR (CGU_OFFSET + 0x002C)
-#define CGU_PCMCR (CGU_OFFSET + 0x0030)
-#define PCI_CR_PCI (CGU_OFFSET + 0x0034)
-#define CGU_OSC_CTRL (CGU_OFFSET + 0x001C)
-#define CGU_MIPS_PWR_DWN (CGU_OFFSET + 0x0038)
-#define CLK_MEASURE (CGU_OFFSET + 0x003C)
-
-//05252006
-#define pll0_35MHz_CONFIG 0x9D861059
-#define pll1_35MHz_CONFIG 0x1A260CD9
-#define pll2_35MHz_CONFIG 0x8000f1e5
-#define pll0_36MHz_CONFIG 0x1000125D
-#define pll1_36MHz_CONFIG 0x1B1E0C99
-#define pll2_36MHz_CONFIG 0x8002f2a1
-//05252006
-
-//06063001-joelin disable the PCI CFRAME mask -start
-/*CFRAME is an I/O signal, in the chip, the output CFRAME is selected via GPIO altsel pins, so if you select MII1 RXD1, the CFRAME will not come out.
-But the CFRAME input still take the signal from the pad and not disabled when altsel choose other function. So when MII1_RXD1 is low from other device, the EBU interface will be disabled.
-
-The chip function in such a way that disable the CFRAME mask mean EBU not longer check CFRAME to be the device using the bus.
-The side effect is the entire PCI block will see CFRAME low all the time meaning PCI cannot use the bus at all so no more PCI function.
-*/
-#define PCI_CR_PR_OFFSET 0xBE105400
-#define PCI_CR_PCI_MOD_REG (PCI_CR_PR_OFFSET + 0x0030)
-#define PCI_CONFIG_SPACE 0xB7000000
-#define CS_CFM (PCI_CONFIG_SPACE + 0x6C)
-//06063001-joelin disable the PCI CFRAME mask -end
- .set noreorder
-
-
-/*
- * void ebu_init(void)
- */
- .globl ebu_init
- .ent ebu_init
-ebu_init:
-
-#if defined(CONFIG_EBU_ADDSEL0) || defined(CONFIG_EBU_ADDSEL1) || \
- defined(CONFIG_EBU_ADDSEL2) || defined(CONFIG_EBU_ADDSEL3) || \
- defined(CONFIG_EBU_BUSCON0) || defined(CONFIG_EBU_BUSCON1) || \
- defined(CONFIG_EBU_BUSCON2) || defined(CONFIG_EBU_BUSCON3)
-
- li t1, EBU_MODUL_BASE
-#if defined(CONFIG_EBU_ADDSEL0)
- li t2, CONFIG_EBU_ADDSEL0
- sw t2, EBU_ADDSEL0(t1)
-#endif
-#if defined(CONFIG_EBU_ADDSEL1)
- li t2, CONFIG_EBU_ADDSEL1
- sw t2, EBU_ADDSEL1(t1)
-#endif
-#if defined(CONFIG_EBU_ADDSEL2)
- li t2, CONFIG_EBU_ADDSEL2
- sw t2, EBU_ADDSEL2(t1)
-#endif
-#if defined(CONFIG_EBU_ADDSEL3)
- li t2, CONFIG_EBU_ADDSEL3
- sw t2, EBU_ADDSEL3(t1)
-#endif
-
-#if defined(CONFIG_EBU_BUSCON0)
- li t2, CONFIG_EBU_BUSCON0
- sw t2, EBU_BUSCON0(t1)
-#endif
-#if defined(CONFIG_EBU_BUSCON1)
- li t2, CONFIG_EBU_BUSCON1
- sw t2, EBU_BUSCON1(t1)
-#endif
-#if defined(CONFIG_EBU_BUSCON2)
- li t2, CONFIG_EBU_BUSCON2
- sw t2, EBU_BUSCON2(t1)
-#endif
-#if defined(CONFIG_EBU_BUSCON3)
- li t2, CONFIG_EBU_BUSCON3
- sw t2, EBU_BUSCON3(t1)
-#endif
-
-#endif
-
- j ra
- nop
-
- .end ebu_init
-
-
-/*
- * void cgu_init(long)
- *
- * a0 has the clock value
- */
- .globl cgu_init
- .ent cgu_init
-cgu_init:
- li t2, CGU_SYS
- lw t2,0(t2)
- beq t2,a0,freq_up2date
- nop
-
- li t2, RCU_STS
- lw t2, 0(t2)
- and t2,0x00020000
- beq t2,0x00020000,boot_36MHZ
- nop
-//05252006
- li t1, PLL0_CFG
- li t2, pll0_35MHz_CONFIG
- sw t2,0(t1)
- li t1, PLL1_CFG
- li t2, pll1_35MHz_CONFIG
- sw t2,0(t1)
- li t1, PLL2_CFG
- li t2, pll2_35MHz_CONFIG
- sw t2,0(t1)
- li t1, CGU_SYS
- sw a0,0(t1)
- li t1, RCU_RST_REQ
- li t2, 0x40000008
- sw t2,0(t1)
- b wait_reset
- nop
-boot_36MHZ:
- li t1, PLL0_CFG
- li t2, pll0_36MHz_CONFIG
- sw t2,0(t1)
- li t1, PLL1_CFG
- li t2, pll1_36MHz_CONFIG
- sw t2,0(t1)
- li t1, PLL2_CFG
- li t2, pll2_36MHz_CONFIG
- sw t2,0(t1)
- li t1, CGU_SYS
- sw a0,0(t1)
- li t1, RCU_RST_REQ
- li t2, 0x40000008
- sw t2,0(t1)
-//05252006
-
-wait_reset:
- b wait_reset
- nop
-freq_up2date:
- j ra
- nop
-
- .end cgu_init
-
-#ifndef CONFIG_USE_DDR_RAM
-/*
- * void sdram_init(long)
- *
- * a0 has the clock value
- */
- .globl sdram_init
- .ent sdram_init
-sdram_init:
-
- /* SDRAM Initialization
- */
- li t1, MC_MODUL_BASE
-
- /* Clear Error log registers */
- sw zero, MC_ERRCAUSE(t1)
- sw zero, MC_ERRADDR(t1)
-
- /* Enable SDRAM module in memory controller */
- li t3, MC_SDRAM_ENABLE
- lw t2, MC_CON(t1)
- or t3, t2, t3
- sw t3, MC_CON(t1)
-
- li t1, MC_SDR_MODUL_BASE
-
- /* disable the controller */
- li t2, 0
- sw t2, MC_CTRLENA(t1)
-
- li t2, 0x822
- sw t2, MC_IOGP(t1)
-
- li t2, 0x2
- sw t2, MC_CFGDW(t1)
-
- /* Set CAS Latency */
- li t2, 0x00000020
- sw t2, MC_MRSCODE(t1)
-
- /* Set CS0 to SDRAM parameters */
- li t2, 0x000014d8
- sw t2, MC_CFGPB0(t1)
-
- /* Set SDRAM latency parameters */
- li t2, 0x00036325; /* BC PC100 */
- sw t2, MC_LATENCY(t1)
-
- /* Set SDRAM refresh rate */
- li t2, 0x00000C30
- sw t2, MC_TREFRESH(t1)
-
- /* Clear Power-down registers */
- sw zero, MC_SELFRFSH(t1)
-
- /* Finally enable the controller */
- li t2, 1
- sw t2, MC_CTRLENA(t1)
-
- j ra
- nop
-
- .end sdram_init
-
-#endif /* !CONFIG_USE_DDR_RAM */
-
-#ifdef CONFIG_USE_DDR_RAM
-/*
- * void ddrram_init(long)
- *
- * a0 has the clock value
- */
- .globl ddrram_init
- .ent ddrram_init
-ddrram_init:
-
- /* DDR-DRAM Initialization
- */
- li t1, MC_MODUL_BASE
-
- /* Clear Error log registers */
- sw zero, MC_ERRCAUSE(t1)
- sw zero, MC_ERRADDR(t1)
-
- /* Enable DDR module in memory controller */
- li t3, MC_DDRRAM_ENABLE
- lw t2, MC_CON(t1)
- or t3, t2, t3
- sw t3, MC_CON(t1)
-
- li t1, MC_DDR_MODUL_BASE
-
- /* Write configuration to DDR controller registers */
- li t2, MC_DC0_VALUE
- sw t2, MC_DC00(t1)
-
- li t2, MC_DC1_VALUE
- sw t2, MC_DC01(t1)
-
- li t2, MC_DC2_VALUE
- sw t2, MC_DC02(t1)
-
- li t2, MC_DC3_VALUE
- sw t2, MC_DC03(t1)
-
- li t2, MC_DC4_VALUE
- sw t2, MC_DC04(t1)
-
- li t2, MC_DC5_VALUE
- sw t2, MC_DC05(t1)
-
- li t2, MC_DC6_VALUE
- sw t2, MC_DC06(t1)
-
- li t2, MC_DC7_VALUE
- sw t2, MC_DC07(t1)
-
- li t2, MC_DC8_VALUE
- sw t2, MC_DC08(t1)
-
- li t2, MC_DC9_VALUE
- sw t2, MC_DC09(t1)
-
- li t2, MC_DC10_VALUE
- sw t2, MC_DC10(t1)
-
- li t2, MC_DC11_VALUE
- sw t2, MC_DC11(t1)
-
- li t2, MC_DC12_VALUE
- sw t2, MC_DC12(t1)
-
- li t2, MC_DC13_VALUE
- sw t2, MC_DC13(t1)
-
- li t2, MC_DC14_VALUE
- sw t2, MC_DC14(t1)
-
- li t2, MC_DC15_VALUE
- sw t2, MC_DC15(t1)
-
- li t2, MC_DC16_VALUE
- sw t2, MC_DC16(t1)
-
- li t2, MC_DC17_VALUE
- sw t2, MC_DC17(t1)
-
- li t2, MC_DC18_VALUE
- sw t2, MC_DC18(t1)
-
- li t2, MC_DC19_VALUE
- sw t2, MC_DC19(t1)
-
- li t2, MC_DC20_VALUE
- sw t2, MC_DC20(t1)
-
- li t2, MC_DC21_VALUE
- sw t2, MC_DC21(t1)
-
- li t2, MC_DC22_VALUE
- sw t2, MC_DC22(t1)
-
- li t2, MC_DC23_VALUE
- sw t2, MC_DC23(t1)
-
- li t2, MC_DC24_VALUE
- sw t2, MC_DC24(t1)
-
- li t2, MC_DC25_VALUE
- sw t2, MC_DC25(t1)
-
- li t2, MC_DC26_VALUE
- sw t2, MC_DC26(t1)
-
- li t2, MC_DC27_VALUE
- sw t2, MC_DC27(t1)
-
- li t2, MC_DC28_VALUE
- sw t2, MC_DC28(t1)
-
- li t2, MC_DC29_VALUE
- sw t2, MC_DC29(t1)
-
- li t2, MC_DC30_VALUE
- sw t2, MC_DC30(t1)
-
- li t2, MC_DC31_VALUE
- sw t2, MC_DC31(t1)
-
- li t2, MC_DC32_VALUE
- sw t2, MC_DC32(t1)
-
- li t2, MC_DC33_VALUE
- sw t2, MC_DC33(t1)
-
- li t2, MC_DC34_VALUE
- sw t2, MC_DC34(t1)
-
- li t2, MC_DC35_VALUE
- sw t2, MC_DC35(t1)
-
- li t2, MC_DC36_VALUE
- sw t2, MC_DC36(t1)
-
- li t2, MC_DC37_VALUE
- sw t2, MC_DC37(t1)
-
- li t2, MC_DC38_VALUE
- sw t2, MC_DC38(t1)
-
- li t2, MC_DC39_VALUE
- sw t2, MC_DC39(t1)
-
- li t2, MC_DC40_VALUE
- sw t2, MC_DC40(t1)
-
- li t2, MC_DC41_VALUE
- sw t2, MC_DC41(t1)
-
- li t2, MC_DC42_VALUE
- sw t2, MC_DC42(t1)
-
- li t2, MC_DC43_VALUE
- sw t2, MC_DC43(t1)
-
- li t2, MC_DC44_VALUE
- sw t2, MC_DC44(t1)
-
- li t2, MC_DC45_VALUE
- sw t2, MC_DC45(t1)
-
- li t2, MC_DC46_VALUE
- sw t2, MC_DC46(t1)
-
- li t2, 0x00000100
- sw t2, MC_DC03(t1)
-
- j ra
- nop
-
- .end ddrram_init
-#endif /* CONFIG_USE_DDR_RAM */
-
- .globl lowlevel_init
- .ent lowlevel_init
-lowlevel_init:
- /* EBU, CGU and SDRAM/DDR-RAM Initialization.
- */
- move t0, ra
- /* We rely on the fact that non of the following ..._init() functions
- * modify t0
- */
-#if defined(DDR166)
- /* 0xe8 means CPU0/CPU1 333M, DDR 167M, FPI 83M, PPE 240M */
- li a0,0xe8
-#elif defined(DDR133)
- /* 0xe9 means CPU0/CPU1 333M, DDR 133M, FPI 83M, PPE 240M */
- li a0,0xe9
-#else /* defined(DDR111) */
- /* 0xea means CPU0/CPU1 333M, DDR 111M, FPI 83M, PPE 240M */
- li a0,0xea
-#endif
- bal cgu_init
- nop
-
- bal ebu_init
- nop
-
-//06063001-joelin disable the PCI CFRAME mask-start
-#ifdef DISABLE_CFRAME
- li t1, PCI_CR_PCI //mw bf103034 80000000
- li t2, 0x80000000
- sw t2,0(t1)
-
- li t1, PCI_CR_PCI_MOD_REG //mw be105430 103
- li t2, 0x103
- sw t2,0(t1)
-
- li t1, CS_CFM //mw b700006c 0
- li t2, 0x00
- sw t2, 0(t1)
-
- li t1, PCI_CR_PCI_MOD_REG //mw be105430 103
- li t2, 0x1000103
- sw t2, 0(t1)
-#endif
-//06063001-joelin disable the PCI CFRAME mask-end
-
-#ifdef CONFIG_USE_DDR_RAM
- bal ddrram_init
- nop
-#else
- bal sdram_init
- nop
-#endif
- move ra, t0
- j ra
- nop
-
- .end lowlevel_init
+++ /dev/null
-/*
- * Memory sub-system initialization code for Danube board.
- * Andre Messerschmidt
- * Copyright (c) 2005 Infineon Technologies AG
- *
- * Based on Inca-IP code
- * Copyright (c) 2003 Wolfgang Denk <wd@denx.de>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-/* History:
- peng liu May 25, 2006, for PLL setting after reset, 05252006
- */
-#include <config.h>
-#include <version.h>
-#include <asm/regdef.h>
-
-#if defined(CONFIG_USE_DDR_PSC_32)
-#include "ddr_settings_psc_32.h"
-#define DDR166
-#elif defined(CONFIG_USE_DDR_PSC_64)
-#include "ddr_settings_psc_64.h"
-#define DDR166
-#else
-#error "missing definition for RAM"
-#endif
-
-#define EBU_MODUL_BASE 0xBE105300
-#define EBU_CLC(value) 0x0000(value)
-#define EBU_CON(value) 0x0010(value)
-#define EBU_ADDSEL0(value) 0x0020(value)
-#define EBU_ADDSEL1(value) 0x0024(value)
-#define EBU_ADDSEL2(value) 0x0028(value)
-#define EBU_ADDSEL3(value) 0x002C(value)
-#define EBU_BUSCON0(value) 0x0060(value)
-#define EBU_BUSCON1(value) 0x0064(value)
-#define EBU_BUSCON2(value) 0x0068(value)
-#define EBU_BUSCON3(value) 0x006C(value)
-
-#define MC_MODUL_BASE 0xBF800000
-#define MC_ERRCAUSE(value) 0x0010(value)
-#define MC_ERRADDR(value) 0x0020(value)
-#define MC_CON(value) 0x0060(value)
-
-#define MC_SRAM_ENABLE 0x00000004
-#define MC_SDRAM_ENABLE 0x00000002
-#define MC_DDRRAM_ENABLE 0x00000001
-
-#define MC_SDR_MODUL_BASE 0xBF800200
-#define MC_IOGP(value) 0x0000(value)
-#define MC_CTRLENA(value) 0x0010(value)
-#define MC_MRSCODE(value) 0x0020(value)
-#define MC_CFGDW(value) 0x0030(value)
-#define MC_CFGPB0(value) 0x0040(value)
-#define MC_LATENCY(value) 0x0080(value)
-#define MC_TREFRESH(value) 0x0090(value)
-#define MC_SELFRFSH(value) 0x00A0(value)
-
-#define MC_DDR_MODUL_BASE 0xBF801000
-#define MC_DC00(value) 0x0000(value)
-#define MC_DC01(value) 0x0010(value)
-#define MC_DC02(value) 0x0020(value)
-#define MC_DC03(value) 0x0030(value)
-#define MC_DC04(value) 0x0040(value)
-#define MC_DC05(value) 0x0050(value)
-#define MC_DC06(value) 0x0060(value)
-#define MC_DC07(value) 0x0070(value)
-#define MC_DC08(value) 0x0080(value)
-#define MC_DC09(value) 0x0090(value)
-#define MC_DC10(value) 0x00A0(value)
-#define MC_DC11(value) 0x00B0(value)
-#define MC_DC12(value) 0x00C0(value)
-#define MC_DC13(value) 0x00D0(value)
-#define MC_DC14(value) 0x00E0(value)
-#define MC_DC15(value) 0x00F0(value)
-#define MC_DC16(value) 0x0100(value)
-#define MC_DC17(value) 0x0110(value)
-#define MC_DC18(value) 0x0120(value)
-#define MC_DC19(value) 0x0130(value)
-#define MC_DC20(value) 0x0140(value)
-#define MC_DC21(value) 0x0150(value)
-#define MC_DC22(value) 0x0160(value)
-#define MC_DC23(value) 0x0170(value)
-#define MC_DC24(value) 0x0180(value)
-#define MC_DC25(value) 0x0190(value)
-#define MC_DC26(value) 0x01A0(value)
-#define MC_DC27(value) 0x01B0(value)
-#define MC_DC28(value) 0x01C0(value)
-#define MC_DC29(value) 0x01D0(value)
-#define MC_DC30(value) 0x01E0(value)
-#define MC_DC31(value) 0x01F0(value)
-#define MC_DC32(value) 0x0200(value)
-#define MC_DC33(value) 0x0210(value)
-#define MC_DC34(value) 0x0220(value)
-#define MC_DC35(value) 0x0230(value)
-#define MC_DC36(value) 0x0240(value)
-#define MC_DC37(value) 0x0250(value)
-#define MC_DC38(value) 0x0260(value)
-#define MC_DC39(value) 0x0270(value)
-#define MC_DC40(value) 0x0280(value)
-#define MC_DC41(value) 0x0290(value)
-#define MC_DC42(value) 0x02A0(value)
-#define MC_DC43(value) 0x02B0(value)
-#define MC_DC44(value) 0x02C0(value)
-#define MC_DC45(value) 0x02D0(value)
-#define MC_DC46(value) 0x02E0(value)
-
-#define RCU_OFFSET 0xBF203000
-#define RCU_RST_REQ (RCU_OFFSET + 0x0010)
-#define RCU_STS (RCU_OFFSET + 0x0014)
-
-#define CGU_OFFSET 0xBF103000
-#define PLL0_CFG (CGU_OFFSET + 0x0004)
-#define PLL1_CFG (CGU_OFFSET + 0x0008)
-#define PLL2_CFG (CGU_OFFSET + 0x000C)
-#define CGU_SYS (CGU_OFFSET + 0x0010)
-#define CGU_UPDATE (CGU_OFFSET + 0x0014)
-#define IF_CLK (CGU_OFFSET + 0x0018)
-#define CGU_SMD (CGU_OFFSET + 0x0020)
-#define CGU_CT1SR (CGU_OFFSET + 0x0028)
-#define CGU_CT2SR (CGU_OFFSET + 0x002C)
-#define CGU_PCMCR (CGU_OFFSET + 0x0030)
-#define PCI_CR_PCI (CGU_OFFSET + 0x0034)
-#define CGU_OSC_CTRL (CGU_OFFSET + 0x001C)
-#define CGU_MIPS_PWR_DWN (CGU_OFFSET + 0x0038)
-#define CLK_MEASURE (CGU_OFFSET + 0x003C)
-
-//05252006
-#define pll0_35MHz_CONFIG 0x9D861059
-#define pll1_35MHz_CONFIG 0x1A260CD9
-#define pll2_35MHz_CONFIG 0x8000f1e5
-#define pll0_36MHz_CONFIG 0x1000125D
-#define pll1_36MHz_CONFIG 0x1B1E0C99
-#define pll2_36MHz_CONFIG 0x8002f2a1
-//05252006
-
-//06063001-joelin disable the PCI CFRAME mask -start
-/*CFRAME is an I/O signal, in the chip, the output CFRAME is selected via GPIO altsel pins, so if you select MII1 RXD1, the CFRAME will not come out.
-But the CFRAME input still take the signal from the pad and not disabled when altsel choose other function. So when MII1_RXD1 is low from other device, the EBU interface will be disabled.
-
-The chip function in such a way that disable the CFRAME mask mean EBU not longer check CFRAME to be the device using the bus.
-The side effect is the entire PCI block will see CFRAME low all the time meaning PCI cannot use the bus at all so no more PCI function.
-*/
-#define PCI_CR_PR_OFFSET 0xBE105400
-#define PCI_CR_PCI_MOD_REG (PCI_CR_PR_OFFSET + 0x0030)
-#define PCI_CONFIG_SPACE 0xB7000000
-#define CS_CFM (PCI_CONFIG_SPACE + 0x6C)
-//06063001-joelin disable the PCI CFRAME mask -end
- .set noreorder
-
-
-/*
- * void ebu_init(void)
- */
- .globl ebu_init
- .ent ebu_init
-ebu_init:
-
- j ra
- nop
-
- .end ebu_init
-
-
-/*
- * void cgu_init(long)
- *
- * a0 has the clock value
- */
- .globl cgu_init
- .ent cgu_init
-cgu_init:
- li t2, CGU_SYS
- lw t2,0(t2)
- beq t2,a0,freq_up2date
- nop
-
- li t2, RCU_STS
- lw t2, 0(t2)
- and t2,0x00020000
- beq t2,0x00020000,boot_36MHZ
- nop
-//05252006
- li t1, PLL0_CFG
- li t2, pll0_35MHz_CONFIG
- sw t2,0(t1)
- li t1, PLL1_CFG
- li t2, pll1_35MHz_CONFIG
- sw t2,0(t1)
- li t1, PLL2_CFG
- li t2, pll2_35MHz_CONFIG
- sw t2,0(t1)
- li t1, CGU_SYS
- sw a0,0(t1)
- li t1, RCU_RST_REQ
- li t2, 0x40000008
- sw t2,0(t1)
- b wait_reset
- nop
-boot_36MHZ:
- li t1, PLL0_CFG
- li t2, pll0_36MHz_CONFIG
- sw t2,0(t1)
- li t1, PLL1_CFG
- li t2, pll1_36MHz_CONFIG
- sw t2,0(t1)
- li t1, PLL2_CFG
- li t2, pll2_36MHz_CONFIG
- sw t2,0(t1)
- li t1, CGU_SYS
- sw a0,0(t1)
- li t1, RCU_RST_REQ
- li t2, 0x40000008
- sw t2,0(t1)
-//05252006
-
-wait_reset:
- b wait_reset
- nop
-freq_up2date:
- j ra
- nop
-
- .end cgu_init
-
- .globl lowlevel_init
- .ent lowlevel_init
-lowlevel_init:
- /* EBU, CGU and SDRAM/DDR-RAM Initialization.
- */
- move t0, ra
- /* We rely on the fact that non of the following ..._init() functions
- * modify t0
- */
-
- bal ebu_init
- nop
-
-//06063001-joelin disable the PCI CFRAME mask-start
-#ifdef DISABLE_CFRAME
- li t1, PCI_CR_PCI //mw bf103034 80000000
- li t2, 0x80000000
- sw t2,0(t1)
-
- li t1, PCI_CR_PCI_MOD_REG //mw be105430 103
- li t2, 0x103
- sw t2,0(t1)
-
- li t1, CS_CFM //mw b700006c 0
- li t2, 0x00
- sw t2, 0(t1)
-
- li t1, PCI_CR_PCI_MOD_REG //mw be105430 103
- li t2, 0x1000103
- sw t2, 0(t1)
-#endif
-//06063001-joelin disable the PCI CFRAME mask-end
-
- move ra, t0
- j ra
- nop
-
- .end lowlevel_init
+++ /dev/null
-/*
- * Power Management unit initialization code for AMAZON development board.
- *
- * Copyright (c) 2003 Ou Ke, Infineon.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <config.h>
-#include <version.h>
-#include <asm/regdef.h>
-
-#define PMU_PWDCR 0xBF10201C
-#define PMU_SR 0xBF102020
-
- .globl pmuenable
-
-pmuenable:
- li t0, PMU_PWDCR
- li t1, 0x2 /* enable everything */
- sw t1, 0(t0)
-#if 0
-1:
- li t0, PMU_SR
- lw t2, 0(t0)
- bne t1, t2, 1b
- nop
-#endif
- j ra
- nop
-
-
+++ /dev/null
-/*
- * (C) Copyright 2010 Industrie Dial Face S.p.A.
- * Luigi 'Comio' Mantellini, luigi.mantellini@idf-hit.com
- *
- * (C) Copyright 2003
- * Wolfgang Denk Engineering, <wd@denx.de>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/*
-OUTPUT_FORMAT("elf32-bigmips", "elf32-bigmips", "elf32-bigmips")
-*/
-OUTPUT_FORMAT("elf32-tradbigmips", "elf32-tradbigmips", "elf32-tradlittlemips")
-OUTPUT_ARCH(mips)
-ENTRY(_start)
-SECTIONS
-{
- . = 0x00000000;
-
- . = ALIGN(4);
- .text :
- {
- *(.text)
- }
-
- . = ALIGN(4);
- .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
-
- . = ALIGN(4);
- .data : { *(.data) }
-
- . = .;
- _gp = ALIGN(16) +0x7ff0;
-
- .got : {
- __got_start = .;
- *(.got)
- __got_end = .;
- }
-
- . = ALIGN(4);
- .sdata : { *(.sdata) }
-
- . = .;
- . = ALIGN(4);
- .payload : { *(.payload) }
- . = ALIGN(4);
-
- uboot_end_data = .;
- num_got_entries = (__got_end - __got_start) >> 2;
-
- . = ALIGN(4);
- .sbss : { *(.sbss) }
- .bss : { *(.bss) . = ALIGN(4); }
- uboot_end = .;
-}
-
+++ /dev/null
-/*
- * (C) Copyright 2003
- * Wolfgang Denk Engineering, <wd@denx.de>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/*
-OUTPUT_FORMAT("elf32-bigmips", "elf32-bigmips", "elf32-bigmips")
-*/
-OUTPUT_FORMAT("elf32-tradbigmips", "elf32-tradbigmips", "elf32-tradbigmips")
-OUTPUT_ARCH(mips)
-ENTRY(_start)
-SECTIONS
-{
- . = 0x00000000;
-
- . = ALIGN(4);
- .text :
- {
- *(.text)
- }
-
- . = ALIGN(4);
- .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
-
- . = ALIGN(4);
- .data : { *(.data) }
-
- . = .;
- _gp = ALIGN(16) + 0x7ff0;
-
- .got : {
- __got_start = .;
- *(.got)
- __got_end = .;
- }
-
- .sdata : { *(.sdata) }
-
- .u_boot_cmd : {
- __u_boot_cmd_start = .;
- *(.u_boot_cmd)
- __u_boot_cmd_end = .;
- }
-
- uboot_end_data = .;
- num_got_entries = (__got_end - __got_start) >> 2;
-
- . = ALIGN(4);
- .sbss (NOLOAD) : { *(.sbss) }
- .bss (NOLOAD) : { *(.bss) . = ALIGN(4); }
- uboot_end = .;
-}
+++ /dev/null
-#
-# (C) Copyright 2003-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-include $(TOPDIR)/config.mk
-
-LIB = $(obj)lib$(BOARD).a
-BOOTSTRAP_LIB = $(obj)lib$(BOARD)_bootstrap.a
-
-BOOTSTRAP_LIB-$(CONFIG_BOOTSTRAP) = $(BOOTSTRAP_LIB)
-
-COBJS-y += danube.o
-
-SOBJS = lowlevel_init.o pmuenable.o
-
-BOOTSTRAP_COBJS-$(CONFIG_BOOTSTRAP) = $(BOARD)_bootstrap.o
-BOOTSTRAP_SOBJS-$(CONFIG_BOOTSTRAP) = lowlevel_bootstrap_init.o
-
-BOOTSTRAP_SRCS := $(BOOTSTRAP_SOBJS-y:.o=.S) $(BOOTSTRAP_COBJS-y:.o=.c)
-
-SRCS := $(sort $(SOBJS:.o=.S) $(COBJS:.o=.c) $(BOOTSTRAP_SOBJS:.o=.S))
-OBJS := $(addprefix $(obj),$(COBJS-y))
-SOBJS := $(addprefix $(obj),$(SOBJS))
-BOOTSTRAP_OBJS := $(addprefix $(obj),$(BOOTSTRAP_COBJS-y))
-BOOTSTRAP_SOBJS := $(addprefix $(obj),$(BOOTSTRAP_SOBJS-y))
-
-
-all: $(obj).depend $(LIB) $(BOOTSTRAP_LIB)
-
-$(LIB): $(obj).depend $(OBJS) $(SOBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
-
-$(BOOTSTRAP_LIB): $(BOOTSTRAP_OBJS) $(BOOTSTRAP_SOBJS)
- $(AR) $(ARFLAGS) $@ $(BOOTSTRAP_OBJS) $(BOOTSTRAP_SOBJS)
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+++ /dev/null
-#
-# (C) Copyright 2003
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-#
-# Danube board with MIPS 24Kc CPU core
-#
-sinclude $(OBJTREE)/board/$(BOARDDIR)/config.tmp
-
-ifdef CONFIG_BOOTSTRAP
-TEXT_BASE = 0x80001000
-CONFIG_BOOTSTRAP_TEXT_BASE = 0xb0000000
-CONFIG_SYS_RAMBOOT = y
-else
-
-ifndef TEXT_BASE
-$(info redefine TEXT_BASE = 0xB0000000 )
-TEXT_BASE = 0xB0000000
-endif
-
-endif
+++ /dev/null
-/*
- * (C) Copyright 2003
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * (C) Copyright 2010
- * Thomas Langer, Ralph Hempel
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <command.h>
-#include <netdev.h>
-#include <miiphy.h>
-#include <asm/addrspace.h>
-#include <asm/danube.h>
-#include <asm/reboot.h>
-#include <asm/io.h>
-#if defined(CONFIG_CMD_HTTPD)
-#include <httpd.h>
-#endif
-
-extern ulong ifx_get_ddr_hz(void);
-extern ulong ifx_get_cpuclk(void);
-
-/* definitions for external PHYs / Switches */
-/* Split values into phy address and register address */
-#define PHYADDR(_reg) ((_reg >> 5) & 0xff), (_reg & 0x1f)
-
-/* IDs and registers of known external switches */
-#define ID_SAMURAI_0 0x1020
-#define ID_SAMURAI_1 0x0007
-#define SAMURAI_ID_REG0 0xA0
-#define SAMURAI_ID_REG1 0xA1
-
-#define ID_TANTOS 0x2599
-
-void _machine_restart(void)
-{
- *DANUBE_RCU_RST_REQ |=1<<30;
-}
-
-#ifdef CONFIG_SYS_RAMBOOT
-phys_size_t initdram(int board_type)
-{
- return get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, CONFIG_SYS_MAX_RAM);
-}
-#elif defined(CONFIG_USE_DDR_RAM)
-phys_size_t initdram(int board_type)
-{
- return (CONFIG_SYS_MAX_RAM);
-}
-#else
-
-static ulong max_sdram_size(void) /* per Chip Select */
-{
- /* The only supported SDRAM data width is 16bit.
- */
-#define CFG_DW 4
-
- /* The only supported number of SDRAM banks is 4.
- */
-#define CFG_NB 4
-
- ulong cfgpb0 = *DANUBE_SDRAM_MC_CFGPB0;
- int cols = cfgpb0 & 0xF;
- int rows = (cfgpb0 & 0xF0) >> 4;
- ulong size = (1 << (rows + cols)) * CFG_DW * CFG_NB;
-
- return size;
-}
-
-/*
- * Check memory range for valid RAM. A simple memory test determines
- * the actually available RAM size between addresses `base' and
- * `base + maxsize'.
- */
-
-static long int dram_size(long int *base, long int maxsize)
-{
- volatile long int *addr;
- ulong cnt, val;
- ulong save[32]; /* to make test non-destructive */
- unsigned char i = 0;
-
- for (cnt = (maxsize / sizeof (long)) >> 1; cnt > 0; cnt >>= 1) {
- addr = base + cnt; /* pointer arith! */
-
- save[i++] = *addr;
- *addr = ~cnt;
- }
-
- /* write 0 to base address */
- addr = base;
- save[i] = *addr;
- *addr = 0;
-
- /* check at base address */
- if ((val = *addr) != 0) {
- *addr = save[i];
- return (0);
- }
-
- for (cnt = 1; cnt < maxsize / sizeof (long); cnt <<= 1) {
- addr = base + cnt; /* pointer arith! */
-
- val = *addr;
- *addr = save[--i];
-
- if (val != (~cnt)) {
- return (cnt * sizeof (long));
- }
- }
- return (maxsize);
-}
-
-phys_size_t initdram(int board_type)
-{
- int rows, cols, best_val = *DANUBE_SDRAM_MC_CFGPB0;
- ulong size, max_size = 0;
- ulong our_address;
-
- /* load t9 into our_address */
- asm volatile ("move %0, $25" : "=r" (our_address) :);
-
- /* Can't probe for RAM size unless we are running from Flash.
- * find out whether running from DRAM or Flash.
- */
- if (CPHYSADDR(our_address) < CPHYSADDR(PHYS_FLASH_1))
- {
- return max_sdram_size();
- }
-
- for (cols = 0x8; cols <= 0xC; cols++)
- {
- for (rows = 0xB; rows <= 0xD; rows++)
- {
- *DANUBE_SDRAM_MC_CFGPB0 = (0x14 << 8) |
- (rows << 4) | cols;
- size = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE,
- max_sdram_size());
-
- if (size > max_size)
- {
- best_val = *DANUBE_SDRAM_MC_CFGPB0;
- max_size = size;
- }
- }
- }
-
- *DANUBE_SDRAM_MC_CFGPB0 = best_val;
- return max_size;
-}
-#endif
-
-int checkboard (void)
-{
- unsigned long chipid = *DANUBE_MPS_CHIPID;
- int part_num;
-
- puts ("Board: ");
-
- part_num = DANUBE_MPS_CHIPID_PARTNUM_GET(chipid);
- switch (part_num)
- {
- case 0x129:
- case 0x12B:
- case 0x12D:
- puts("Danube/Twinpass/Vinax-VE ");
- break;
- default:
- printf ("unknown, chip part number 0x%03X ", part_num);
- break;
- }
- printf ("V1.%ld, ", DANUBE_MPS_CHIPID_VERSION_GET(chipid));
-
- printf("DDR Speed %ld MHz, ", ifx_get_ddr_hz()/1000000);
- printf("CPU Speed %ld MHz\n", ifx_get_cpuclk()/1000000);
-
- return 0;
-}
-
-#ifdef CONFIG_SKIP_LOWLEVEL_INIT
-int board_early_init_f(void)
-{
-#ifdef CONFIG_EBU_ADDSEL0
- (*DANUBE_EBU_ADDSEL0) = CONFIG_EBU_ADDSEL0;
-#endif
-#ifdef CONFIG_EBU_ADDSEL1
- (*DANUBE_EBU_ADDSEL1) = CONFIG_EBU_ADDSEL1;
-#endif
-#ifdef CONFIG_EBU_ADDSEL2
- (*DANUBE_EBU_ADDSEL2) = CONFIG_EBU_ADDSEL2;
-#endif
-#ifdef CONFIG_EBU_ADDSEL3
- (*DANUBE_EBU_ADDSEL3) = CONFIG_EBU_ADDSEL3;
-#endif
-#ifdef CONFIG_EBU_BUSCON0
- (*DANUBE_EBU_BUSCON0) = CONFIG_EBU_BUSCON0;
-#endif
-#ifdef CONFIG_EBU_BUSCON1
- (*DANUBE_EBU_BUSCON1) = CONFIG_EBU_BUSCON1;
-#endif
-#ifdef CONFIG_EBU_BUSCON2
- (*DANUBE_EBU_BUSCON2) = CONFIG_EBU_BUSCON2;
-#endif
-#ifdef CONFIG_EBU_BUSCON3
- (*DANUBE_EBU_BUSCON3) = CONFIG_EBU_BUSCON3;
-#endif
-
- return 0;
-}
-#endif /* CONFIG_SKIP_LOWLEVEL_INIT */
-
-#ifdef CONFIG_EXTRA_SWITCH
-static int external_switch_init(void)
-{
- unsigned short chipid0=0xdead, chipid1=0xbeef;
- static char * const name = "lq_cpe_eth";
-
-#ifdef CONFIG_SWITCH_PORT0
- *DANUBE_GPIO_P0_ALTSEL0 &= ~(1<<CONFIG_SWITCH_PIN);
- *DANUBE_GPIO_P0_ALTSEL1 &= ~(1<<CONFIG_SWITCH_PIN);
- *DANUBE_GPIO_P0_OD |= (1<<CONFIG_SWITCH_PIN);
- *DANUBE_GPIO_P0_DIR |= (1<<CONFIG_SWITCH_PIN);
- *DANUBE_GPIO_P0_OUT |= (1<<CONFIG_SWITCH_PIN);
-#elif defined(CONFIG_SWITCH_PORT1)
- *DANUBE_GPIO_P1_ALTSEL0 &= ~(1<<CONFIG_SWITCH_PIN);
- *DANUBE_GPIO_P1_ALTSEL1 &= ~(1<<CONFIG_SWITCH_PIN);
- *DANUBE_GPIO_P1_OD |= (1<<CONFIG_SWITCH_PIN);
- *DANUBE_GPIO_P1_DIR |= (1<<CONFIG_SWITCH_PIN);
- *DANUBE_GPIO_P1_OUT |= (1<<CONFIG_SWITCH_PIN);
-#endif
-#ifdef CLK_OUT2_25MHZ
- *DANUBE_GPIO_P0_DIR=0x0000ae78;
- *DANUBE_GPIO_P0_ALTSEL0=0x00008078;
- //joelin for Mii-1 *DANUBE_GPIO_P0_ALTSEL1=0x80000080;
- *DANUBE_GPIO_P0_ALTSEL1=0x80000000; //joelin for Mii-1
- *DANUBE_CGU_IFCCR=0x00400010;
- *DANUBE_GPIO_P0_OD=0x0000ae78;
-#endif
-
- /* earlier no valid response is available, at least on Twinpass & Tantos @ 111MHz, M4530 platform */
- udelay(100000);
-
- debug("\nsearching for Samurai switch ... ");
- if ( (miiphy_read(name, PHYADDR(SAMURAI_ID_REG0), &chipid0)==0) &&
- (miiphy_read(name, PHYADDR(SAMURAI_ID_REG1), &chipid1)==0) ) {
- if (((chipid0 & 0xFFF0) == ID_SAMURAI_0) &&
- ((chipid1 & 0x000F) == ID_SAMURAI_1)) {
- debug("found");
-
- /* enable "Crossover Auto Detect" + defaults */
- /* P0 */
- miiphy_write(name, PHYADDR(0x01), 0x840F);
- /* P1 */
- miiphy_write(name, PHYADDR(0x03), 0x840F);
- /* P2 */
- miiphy_write(name, PHYADDR(0x05), 0x840F);
- /* P3 */
- miiphy_write(name, PHYADDR(0x07), 0x840F);
- /* P4 */
- miiphy_write(name, PHYADDR(0x08), 0x840F);
- /* P5 */
- miiphy_write(name, PHYADDR(0x09), 0x840F);
- /* System Control 4: CPU on port 1 and other */
- miiphy_write(name, PHYADDR(0x12), 0x3602);
- #ifdef CLK_OUT2_25MHZ
- /* Bandwidth Control Enable Register: enable */
- miiphy_write(name, PHYADDR(0x33), 0x4000);
- #endif
- }
- }
-
- debug("\nsearching for TANTOS switch ... ");
- if (miiphy_read(name, PHYADDR(0x101), &chipid0) == 0) {
- if (chipid0 == ID_TANTOS) {
- debug("found");
-
- /* P5 Basic Control: Force Link Up */
- miiphy_write(name, PHYADDR(0xA1), 0x0004);
- /* P6 Basic Control: Force Link Up */
- miiphy_write(name, PHYADDR(0xC1), 0x0004);
- /* RGMII/MII Port Control (P4/5/6) */
- miiphy_write(name, PHYADDR(0xF5), 0x0773);
-
- /* Software workaround. */
- /* PHY reset from P0 to P4. */
-
- /* set data for indirect write */
- miiphy_write(name, PHYADDR(0x121), 0x8000);
-
- /* P0 */
- miiphy_write(name, PHYADDR(0x120), 0x0400);
- udelay(1000);
- /* P1 */
- miiphy_write(name, PHYADDR(0x120), 0x0420);
- udelay(1000);
- /* P2 */
- miiphy_write(name, PHYADDR(0x120), 0x0440);
- udelay(1000);
- /* P3 */
- miiphy_write(name, PHYADDR(0x120), 0x0460);
- udelay(1000);
- /* P4 */
- miiphy_write(name, PHYADDR(0x120), 0x0480);
- udelay(1000);
- }
- }
- debug("\n");
-
- return 0;
-}
-#endif /* CONFIG_EXTRA_SWITCH */
-
-int board_gpio_init(void)
-{
-#ifdef CONFIG_BUTTON_PORT0
- *DANUBE_GPIO_P0_ALTSEL0 &= ~(1<<CONFIG_BUTTON_PIN);
- *DANUBE_GPIO_P0_ALTSEL1 &= ~(1<<CONFIG_BUTTON_PIN);
- *DANUBE_GPIO_P0_DIR &= ~(1<<CONFIG_BUTTON_PIN);
- if(!!(*DANUBE_GPIO_P0_IN & (1<<CONFIG_BUTTON_PIN)) == CONFIG_BUTTON_LEVEL)
- {
- printf("button is pressed\n");
- setenv("bootdelay", "0");
- setenv("bootcmd", "httpd");
- }
-#elif defined(CONFIG_BUTTON_PORT1)
- *DANUBE_GPIO_P1_ALTSEL0 &= ~(1<<CONFIG_BUTTON_PIN);
- *DANUBE_GPIO_P1_ALTSEL1 &= ~(1<<CONFIG_BUTTON_PIN);
- *DANUBE_GPIO_P1_DIR &= ~(1<<CONFIG_BUTTON_PIN);
- if(!!(*DANUBE_GPIO_P1_IN & (1<<CONFIG_BUTTON_PIN)) == CONFIG_BUTTON_LEVEL)
- {
- printf("button is pressed\n");
- setenv("bootdelay", "0");
- setenv("bootcmd", "httpd");
- }
-#endif
-}
-
-int board_eth_init(bd_t *bis)
-{
-
- board_gpio_init();
-
-#if defined(CONFIG_IFX_ETOP)
-
- *DANUBE_PMU_PWDCR &= 0xFFFFEFDF;
- *DANUBE_PMU_PWDCR &=~(1<<DANUBE_PMU_DMA_SHIFT);/*enable DMA from PMU*/
-
- if (lq_eth_initialize(bis)<0)
- return -1;
-
- *DANUBE_RCU_RST_REQ |=1;
- udelay(200000);
- *DANUBE_RCU_RST_REQ &=(unsigned long)~1;
- udelay(1000);
-
-#ifdef CONFIG_EXTRA_SWITCH
- if (external_switch_init()<0)
- return -1;
-#endif /* CONFIG_EXTRA_SWITCH */
-#endif /* CONFIG_IFX_ETOP */
-
- return 0;
-}
-
-#if defined(CONFIG_CMD_HTTPD)
-int do_http_upgrade(const unsigned char *data, const ulong size)
-{
- char buf[128];
-
- if(getenv ("ram_addr") == NULL)
- return -1;
- if(getenv ("kernel_addr") == NULL)
- return -1;
- /* check the image */
- if(run_command("imi ${ram_addr}", 0) < 0) {
- return -1;
- }
- /* write the image to the flash */
- puts("http ugrade ...\n");
- sprintf(buf, "era ${kernel_addr} +0x%x; cp.b ${ram_addr} ${kernel_addr} 0x%x", size, size);
- return run_command(buf, 0);
-}
-
-int do_http_progress(const int state)
-{
- /* toggle LED's here */
- switch(state) {
- case HTTP_PROGRESS_START:
- puts("http start\n");
- break;
- case HTTP_PROGRESS_TIMEOUT:
- puts(".");
- break;
- case HTTP_PROGRESS_UPLOAD_READY:
- puts("http upload ready\n");
- break;
- case HTTP_PROGRESS_UGRADE_READY:
- puts("http ugrade ready\n");
- break;
- case HTTP_PROGRESS_UGRADE_FAILED:
- puts("http ugrade failed\n");
- break;
- }
- return 0;
-}
-
-unsigned long do_http_tmp_address(void)
-{
- char *s = getenv ("ram_addr");
- if (s) {
- ulong tmp = simple_strtoul (s, NULL, 16);
- return tmp;
- }
- return 0 /*0x80a00000*/;
-}
-
-#endif
+++ /dev/null
-/* Settings for Denali DDR SDRAM controller */
-/* Optimise for Danube Eval Board DDR 167 Mhz - by Ng Aik Ann 29th April */
-#define MC_DC0_VALUE 0x1B1B
-#define MC_DC1_VALUE 0x0
-#define MC_DC2_VALUE 0x0
-#define MC_DC3_VALUE 0x0
-#define MC_DC4_VALUE 0x0
-#define MC_DC5_VALUE 0x200
-#define MC_DC6_VALUE 0x605
-#define MC_DC7_VALUE 0x303
-#define MC_DC8_VALUE 0x102
-#define MC_DC9_VALUE 0x70a
-#define MC_DC10_VALUE 0x203
-#define MC_DC11_VALUE 0xc02
-#define MC_DC12_VALUE 0x1C8
-#define MC_DC13_VALUE 0x1
-#define MC_DC14_VALUE 0x0
-#define MC_DC15_VALUE 0xf3c
-#define MC_DC16_VALUE 0xC800
-#define MC_DC17_VALUE 0xd
-#define MC_DC18_VALUE 0x300
-#define MC_DC19_VALUE 0x200
-#define MC_DC20_VALUE 0xA03
-#define MC_DC21_VALUE 0x1d00
-#define MC_DC22_VALUE 0x1d1d
-#define MC_DC23_VALUE 0x0
-#define MC_DC24_VALUE 0x5e /* was 0x7f */
-#define MC_DC25_VALUE 0x0
-#define MC_DC26_VALUE 0x0
-#define MC_DC27_VALUE 0x0
-#define MC_DC28_VALUE 0x510
-#define MC_DC29_VALUE 0x2d89
-#define MC_DC30_VALUE 0x8300
-#define MC_DC31_VALUE 0x0
-#define MC_DC32_VALUE 0x0
-#define MC_DC33_VALUE 0x0
-#define MC_DC34_VALUE 0x0
-#define MC_DC35_VALUE 0x0
-#define MC_DC36_VALUE 0x0
-#define MC_DC37_VALUE 0x0
-#define MC_DC38_VALUE 0x0
-#define MC_DC39_VALUE 0x0
-#define MC_DC40_VALUE 0x0
-#define MC_DC41_VALUE 0x0
-#define MC_DC42_VALUE 0x0
-#define MC_DC43_VALUE 0x0
-#define MC_DC44_VALUE 0x0
-#define MC_DC45_VALUE 0x500
-//#define MC_DC45_VALUE 0x400
-#define MC_DC46_VALUE 0x0
+++ /dev/null
-/* Settings for Denali DDR SDRAM controller */
-/* Optimise for Danube Ref Board DDR 166 Mhz - by Ng Aik Ann 29th April */
-#define MC_DC0_VALUE 0x1B1B
-#define MC_DC1_VALUE 0x0
-#define MC_DC2_VALUE 0x0
-#define MC_DC3_VALUE 0x0
-#define MC_DC4_VALUE 0x0
-#define MC_DC5_VALUE 0x200
-#define MC_DC6_VALUE 0x605
-#define MC_DC7_VALUE 0x303
-#define MC_DC8_VALUE 0x102
-#define MC_DC9_VALUE 0x70a
-#define MC_DC10_VALUE 0x203
-#define MC_DC11_VALUE 0xa02
-#define MC_DC12_VALUE 0x1C8
-#define MC_DC13_VALUE 0x0
-#define MC_DC14_VALUE 0x0
-#define MC_DC15_VALUE 0xf3c /* WDQS tuning for clk_wr*/
-#define MC_DC16_VALUE 0xC800
-#define MC_DC17_VALUE 0xd
-#define MC_DC18_VALUE 0x300
-#define MC_DC19_VALUE 0x200
-#define MC_DC20_VALUE 0xA04 /* A04 for reference board, A03 for Eval board */
-#define MC_DC21_VALUE 0x1200
-#define MC_DC22_VALUE 0x1212
-#define MC_DC23_VALUE 0x0
-#define MC_DC24_VALUE 0x62 /* WDQS Tuning for DQS */
-#define MC_DC25_VALUE 0x0
-#define MC_DC26_VALUE 0x0
-#define MC_DC27_VALUE 0x0
-#define MC_DC28_VALUE 0x510
-#define MC_DC29_VALUE 0x4e20
-#define MC_DC30_VALUE 0x8300
-#define MC_DC31_VALUE 0x0
-#define MC_DC32_VALUE 0x0
-#define MC_DC33_VALUE 0x0
-#define MC_DC34_VALUE 0x0
-#define MC_DC35_VALUE 0x0
-#define MC_DC36_VALUE 0x0
-#define MC_DC37_VALUE 0x0
-#define MC_DC38_VALUE 0x0
-#define MC_DC39_VALUE 0x0
-#define MC_DC40_VALUE 0x0
-#define MC_DC41_VALUE 0x0
-#define MC_DC42_VALUE 0x0
-#define MC_DC43_VALUE 0x0
-#define MC_DC44_VALUE 0x0
-#define MC_DC45_VALUE 0x500
-//#define MC_DC45_VALUE 0x400
-#define MC_DC46_VALUE 0x0
+++ /dev/null
-/* Settings for Denali DDR SDRAM controller */
-/* Optimise for Samsung DDR K4H561638H Danube Ref Board DDR 166 Mhz - by Ng Aik Ann 27th Nov 2006 */
-
-#define MC_DC0_VALUE 0x1B1B
-#define MC_DC1_VALUE 0x0
-#define MC_DC2_VALUE 0x0
-#define MC_DC3_VALUE 0x0
-#define MC_DC4_VALUE 0x0
-#define MC_DC5_VALUE 0x200
-#define MC_DC6_VALUE 0x605
-#define MC_DC7_VALUE 0x303
-#define MC_DC8_VALUE 0x102
-#define MC_DC9_VALUE 0x70a
-#define MC_DC10_VALUE 0x203
-#define MC_DC11_VALUE 0xc02
-#define MC_DC12_VALUE 0x1C8
-#define MC_DC13_VALUE 0x1
-#define MC_DC14_VALUE 0x0
-#define MC_DC15_VALUE 0x120 /* WDQS tuning for clk_wr*/
-#define MC_DC16_VALUE 0xC800
-#define MC_DC17_VALUE 0xd
-#define MC_DC18_VALUE 0x301
-#define MC_DC19_VALUE 0x200
-#define MC_DC20_VALUE 0xA04 /* A04 for reference board, A03 for Eval board */
-#define MC_DC21_VALUE 0x1400
-#define MC_DC22_VALUE 0x1414
-#define MC_DC23_VALUE 0x0
-#define MC_DC24_VALUE 0x4e /* WDQS Tuning for DQS */
-#define MC_DC25_VALUE 0x0
-#define MC_DC26_VALUE 0x0
-#define MC_DC27_VALUE 0x0
-#define MC_DC28_VALUE 0x510
-#define MC_DC29_VALUE 0x2d93
-#define MC_DC30_VALUE 0x8235
-#define MC_DC31_VALUE 0x0
-#define MC_DC32_VALUE 0x0
-#define MC_DC33_VALUE 0x0
-#define MC_DC34_VALUE 0x0
-#define MC_DC35_VALUE 0x0
-#define MC_DC36_VALUE 0x0
-#define MC_DC37_VALUE 0x0
-#define MC_DC38_VALUE 0x0
-#define MC_DC39_VALUE 0x0
-#define MC_DC40_VALUE 0x0
-#define MC_DC41_VALUE 0x0
-#define MC_DC42_VALUE 0x0
-#define MC_DC43_VALUE 0x0
-#define MC_DC44_VALUE 0x0
-#define MC_DC45_VALUE 0x500
-//#define MC_DC45_VALUE 0x400
-#define MC_DC46_VALUE 0x0
+++ /dev/null
-/* Settings for Denali DDR SDRAM controller */
-/* Optimise for Danube Eval Board DDR 167 Mhz - by Ng Aik Ann 29th April */
-#define MC_DC0_VALUE 0x1B1B
-#define MC_DC1_VALUE 0x0
-#define MC_DC2_VALUE 0x0
-#define MC_DC3_VALUE 0x0
-#define MC_DC4_VALUE 0x0
-#define MC_DC5_VALUE 0x200
-#define MC_DC6_VALUE 0x605
-#define MC_DC7_VALUE 0x303
-#define MC_DC8_VALUE 0x102
-#define MC_DC9_VALUE 0x70a
-#define MC_DC10_VALUE 0x203
-#define MC_DC11_VALUE 0xc02
-#define MC_DC12_VALUE 0x1C8
-#define MC_DC13_VALUE 0x1
-#define MC_DC14_VALUE 0x0
-#define MC_DC15_VALUE 0xf3c /* WDQS tuning for clk_wr*/
-#define MC_DC16_VALUE 0xC800
-#define MC_DC17_VALUE 0xd
-#define MC_DC18_VALUE 0x300
-#define MC_DC19_VALUE 0x200
-#define MC_DC20_VALUE 0xA03 /* A04 for reference board, A03 for Eval board */
-#define MC_DC21_VALUE 0x1800
-#define MC_DC22_VALUE 0x1818
-#define MC_DC23_VALUE 0x0
-#define MC_DC24_VALUE 0x5e /* WDQS Tuning for DQS */
-#define MC_DC25_VALUE 0x0
-#define MC_DC26_VALUE 0x0
-#define MC_DC27_VALUE 0x0
-#define MC_DC28_VALUE 0x510
-#define MC_DC29_VALUE 0x2d89
-#define MC_DC30_VALUE 0x8300
-#define MC_DC31_VALUE 0x0
-#define MC_DC32_VALUE 0x0
-#define MC_DC33_VALUE 0x0
-#define MC_DC34_VALUE 0x0
-#define MC_DC35_VALUE 0x0
-#define MC_DC36_VALUE 0x0
-#define MC_DC37_VALUE 0x0
-#define MC_DC38_VALUE 0x0
-#define MC_DC39_VALUE 0x0
-#define MC_DC40_VALUE 0x0
-#define MC_DC41_VALUE 0x0
-#define MC_DC42_VALUE 0x0
-#define MC_DC43_VALUE 0x0
-#define MC_DC44_VALUE 0x0
-#define MC_DC45_VALUE 0x500
-//#define MC_DC45_VALUE 0x400
-#define MC_DC46_VALUE 0x0
+++ /dev/null
-/* Settings for Denali DDR SDRAM controller */
-/* Optimise for Danube Eval Board DDR 167 Mhz - by Ng Aik Ann 29th April */
-#define MC_DC0_VALUE 0x1B1B
-#define MC_DC1_VALUE 0x0
-#define MC_DC2_VALUE 0x0
-#define MC_DC3_VALUE 0x0
-#define MC_DC4_VALUE 0x0
-#define MC_DC5_VALUE 0x200
-#define MC_DC6_VALUE 0x605
-#define MC_DC7_VALUE 0x303
-#define MC_DC8_VALUE 0x102
-#define MC_DC9_VALUE 0x70a
-#define MC_DC10_VALUE 0x203
-#define MC_DC11_VALUE 0xc02
-#define MC_DC12_VALUE 0x1C8
-#define MC_DC13_VALUE 0x1
-#define MC_DC14_VALUE 0x0
-#define MC_DC15_VALUE 0xf3c /* WDQS tuning for clk_wr*/
-#define MC_DC16_VALUE 0xC800
-#define MC_DC17_VALUE 0xd
-#define MC_DC18_VALUE 0x300
-#define MC_DC19_VALUE 0x200
-#define MC_DC20_VALUE 0xA03 /* A04 for reference board, A03 for Eval board */
-#define MC_DC21_VALUE 0x1800
-#define MC_DC22_VALUE 0x1818
-#define MC_DC23_VALUE 0x0
-#define MC_DC24_VALUE 0x5e /* WDQS Tuning for DQS */
-#define MC_DC25_VALUE 0x0
-#define MC_DC26_VALUE 0x0
-#define MC_DC27_VALUE 0x0
-#define MC_DC28_VALUE 0x510
-#define MC_DC29_VALUE 0x2d89
-#define MC_DC30_VALUE 0x8300
-#define MC_DC31_VALUE 0x0
-#define MC_DC32_VALUE 0x0
-#define MC_DC33_VALUE 0x0
-#define MC_DC34_VALUE 0x0
-#define MC_DC35_VALUE 0x0
-#define MC_DC36_VALUE 0x0
-#define MC_DC37_VALUE 0x0
-#define MC_DC38_VALUE 0x0
-#define MC_DC39_VALUE 0x0
-#define MC_DC40_VALUE 0x0
-#define MC_DC41_VALUE 0x0
-#define MC_DC42_VALUE 0x0
-#define MC_DC43_VALUE 0x0
-#define MC_DC44_VALUE 0x0
-#define MC_DC45_VALUE 0x500
-//#define MC_DC45_VALUE 0x400
-#define MC_DC46_VALUE 0x0
+++ /dev/null
-/* Settings for Denali DDR SDRAM controller */
-/* Optimise for PSC DDR A2S56D40CTP for Danube Ref Board DDR 166 Mhz - by Ng Aik Ann 27th Nov 2006 */
-
-#define MC_DC0_VALUE 0x1B1B
-#define MC_DC1_VALUE 0x0
-#define MC_DC2_VALUE 0x0
-#define MC_DC3_VALUE 0x0
-#define MC_DC4_VALUE 0x0
-#define MC_DC5_VALUE 0x200
-#define MC_DC6_VALUE 0x605
-#define MC_DC7_VALUE 0x303
-#define MC_DC8_VALUE 0x102
-#define MC_DC9_VALUE 0x70a
-#define MC_DC10_VALUE 0x203
-#define MC_DC11_VALUE 0xc02
-#define MC_DC12_VALUE 0x1C8
-#define MC_DC13_VALUE 0x1
-#define MC_DC14_VALUE 0x0
-#define MC_DC15_VALUE 0x120 /* WDQS tuning for clk_wr*/
-#define MC_DC16_VALUE 0xC800
-#define MC_DC17_VALUE 0xd
-#define MC_DC18_VALUE 0x301
-#define MC_DC19_VALUE 0x200
-#define MC_DC20_VALUE 0xA04 /* A04 for reference board, A03 for Eval board */
-#define MC_DC21_VALUE 0x1700
-#define MC_DC22_VALUE 0x1717
-#define MC_DC23_VALUE 0x0
-#define MC_DC24_VALUE 0x52 /* WDQS Tuning for DQS */
-#define MC_DC25_VALUE 0x0
-#define MC_DC26_VALUE 0x0
-#define MC_DC27_VALUE 0x0
-#define MC_DC28_VALUE 0x510
-#define MC_DC29_VALUE 0x4e20
-#define MC_DC30_VALUE 0x8235
-#define MC_DC31_VALUE 0x0
-#define MC_DC32_VALUE 0x0
-#define MC_DC33_VALUE 0x0
-#define MC_DC34_VALUE 0x0
-#define MC_DC35_VALUE 0x0
-#define MC_DC36_VALUE 0x0
-#define MC_DC37_VALUE 0x0
-#define MC_DC38_VALUE 0x0
-#define MC_DC39_VALUE 0x0
-#define MC_DC40_VALUE 0x0
-#define MC_DC41_VALUE 0x0
-#define MC_DC42_VALUE 0x0
-#define MC_DC43_VALUE 0x0
-#define MC_DC44_VALUE 0x0
-#define MC_DC45_VALUE 0x500
-//#define MC_DC45_VALUE 0x400
-#define MC_DC46_VALUE 0x0
+++ /dev/null
-/* Settings for Denali DDR SDRAM controller */
-/* Optimise for Danube Ref Board DDR 166 Mhz - by Ng Aik Ann 29th April */
-#define MC_DC0_VALUE 0x1B1B
-#define MC_DC1_VALUE 0x0
-#define MC_DC2_VALUE 0x0
-#define MC_DC3_VALUE 0x0
-#define MC_DC4_VALUE 0x0
-#define MC_DC5_VALUE 0x200
-#define MC_DC6_VALUE 0x605
-#define MC_DC7_VALUE 0x303
-#define MC_DC8_VALUE 0x102
-#define MC_DC9_VALUE 0x70a
-#define MC_DC10_VALUE 0x203
-#define MC_DC11_VALUE 0xc02
-#define MC_DC12_VALUE 0x1C8
-#define MC_DC13_VALUE 0x1
-#define MC_DC14_VALUE 0x0
-#define MC_DC15_VALUE 0xf3c /* WDQS tuning for clk_wr*/
-#define MC_DC16_VALUE 0xC800
-#define MC_DC17_VALUE 0xd
-#define MC_DC18_VALUE 0x300
-#define MC_DC19_VALUE 0x200
-#define MC_DC20_VALUE 0xA04 /* A04 for reference board, A03 for Eval board */
-#define MC_DC21_VALUE 0x1200
-#define MC_DC22_VALUE 0x1212
-#define MC_DC23_VALUE 0x0
-#define MC_DC24_VALUE 0x5e /* WDQS Tuning for DQS */
-#define MC_DC25_VALUE 0x0
-#define MC_DC26_VALUE 0x0
-#define MC_DC27_VALUE 0x0
-#define MC_DC28_VALUE 0x510
-#define MC_DC29_VALUE 0x2d89
-#define MC_DC30_VALUE 0x8300
-#define MC_DC31_VALUE 0x0
-#define MC_DC32_VALUE 0x0
-#define MC_DC33_VALUE 0x0
-#define MC_DC34_VALUE 0x0
-#define MC_DC35_VALUE 0x0
-#define MC_DC36_VALUE 0x0
-#define MC_DC37_VALUE 0x0
-#define MC_DC38_VALUE 0x0
-#define MC_DC39_VALUE 0x0
-#define MC_DC40_VALUE 0x0
-#define MC_DC41_VALUE 0x0
-#define MC_DC42_VALUE 0x0
-#define MC_DC43_VALUE 0x0
-#define MC_DC44_VALUE 0x0
-#define MC_DC45_VALUE 0x500
-//#define MC_DC45_VALUE 0x400
-#define MC_DC46_VALUE 0x0
+++ /dev/null
-/* Settings for Denali DDR SDRAM controller */
-/* Optimise for Danube Ref Board DDR 166 Mhz - by Ng Aik Ann 29th April */
-#define MC_DC0_VALUE 0x1B1B
-#define MC_DC1_VALUE 0x0
-#define MC_DC2_VALUE 0x0
-#define MC_DC3_VALUE 0x0
-#define MC_DC4_VALUE 0x0
-#define MC_DC5_VALUE 0x200
-#define MC_DC6_VALUE 0x605
-#define MC_DC7_VALUE 0x303
-#define MC_DC8_VALUE 0x102
-#define MC_DC9_VALUE 0x70a
-#define MC_DC10_VALUE 0x203
-#define MC_DC11_VALUE 0xc02
-#define MC_DC12_VALUE 0x1C8
-#define MC_DC13_VALUE 0x1
-#define MC_DC14_VALUE 0x0
-#define MC_DC15_VALUE 0xf3c /* WDQS tuning for clk_wr*/
-#define MC_DC16_VALUE 0xC800
-#define MC_DC17_VALUE 0xd
-#define MC_DC18_VALUE 0x300
-#define MC_DC19_VALUE 0x200
-#define MC_DC20_VALUE 0xA04 /* A04 for reference board, A03 for Eval board */
-#define MC_DC21_VALUE 0xd00
-#define MC_DC22_VALUE 0xd0d
-#define MC_DC23_VALUE 0x0
-#define MC_DC24_VALUE 0x62 /* WDQS Tuning for DQS */
-#define MC_DC25_VALUE 0x0
-#define MC_DC26_VALUE 0x0
-#define MC_DC27_VALUE 0x0
-#define MC_DC28_VALUE 0x510
-#define MC_DC29_VALUE 0x2d89
-#define MC_DC30_VALUE 0x8300
-#define MC_DC31_VALUE 0x0
-#define MC_DC32_VALUE 0x0
-#define MC_DC33_VALUE 0x0
-#define MC_DC34_VALUE 0x0
-#define MC_DC35_VALUE 0x0
-#define MC_DC36_VALUE 0x0
-#define MC_DC37_VALUE 0x0
-#define MC_DC38_VALUE 0x0
-#define MC_DC39_VALUE 0x0
-#define MC_DC40_VALUE 0x0
-#define MC_DC41_VALUE 0x0
-#define MC_DC42_VALUE 0x0
-#define MC_DC43_VALUE 0x0
-#define MC_DC44_VALUE 0x0
-#define MC_DC45_VALUE 0x500
-//#define MC_DC45_VALUE 0x400
-#define MC_DC46_VALUE 0x0
+++ /dev/null
-/*
- * (C) Copyright 2010 Industrie Dial Face S.p.A.
- * Luigi 'Comio' Mantellini, luigi.mantellini@idf-hit.com
- *
- * (C) Copyright 2007
- * Vlad Lungu vlad.lungu@windriver.com
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <command.h>
-#include <asm/mipsregs.h>
-#include <asm/io.h>
-
-phys_size_t bootstrap_initdram(int board_type)
-{
- /* Sdram is setup by assembler code */
- /* If memory could be changed, we should return the true value here */
- return CONFIG_SYS_MAX_RAM;
-}
-
-int bootstrap_checkboard(void)
-{
- return 0;
-}
-
-int bootstrap_misc_init_r(void)
-{
- set_io_port_base(0);
- return 0;
-}
+++ /dev/null
-/*
- * Memory sub-system initialization code for Danube board.
- * Andre Messerschmidt
- * Copyright (c) 2005 Infineon Technologies AG
- *
- * Based on Inca-IP code
- * Copyright (c) 2003 Wolfgang Denk <wd@denx.de>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-/* History:
- peng liu May 25, 2006, for PLL setting after reset, 05252006
- */
-#include <config.h>
-#include <version.h>
-#include <asm/regdef.h>
-
-#if defined(CONFIG_USE_DDR_RAM)
-
-#if defined(CONFIG_USE_DDR_RAM_CFG_111M)
-#include "ddr_settings_r111.h"
-#define DDR111
-#elif defined(CONFIG_USE_DDR_RAM_CFG_166M)
-#include "ddr_settings_r166.h"
-#define DDR166
-#elif defined(CONFIG_USE_DDR_RAM_CFG_e111M)
-#include "ddr_settings_e111.h"
-#define DDR111
-#elif defined(CONFIG_USE_DDR_RAM_CFG_e166M)
-#include "ddr_settings_e166.h"
-#define DDR166
-#elif defined(CONFIG_USE_DDR_RAM_CFG_promos400)
-#include "ddr_settings_PROMOSDDR400.h"
-#define DDR166
-#elif defined(CONFIG_USE_DDR_RAM_CFG_samsung166)
-#include "ddr_settings_Samsung_166.h"
-#define DDR166
-#elif defined(CONFIG_USE_DDR_RAM_CFG_psc166)
-#include "ddr_settings_psc_166.h"
-#define DDR166
-#else
-#warning "missing definition for ddr_settings.h, use default!"
-#include "ddr_settings.h"
-#endif
-#endif /* CONFIG_USE_DDR_RAM */
-
-#if defined(CONFIG_USE_DDR_RAM) && !defined(MC_DC0_VALUE)
-#error "missing include of ddr_settings.h"
-#endif
-
-#define EBU_MODUL_BASE 0xBE105300
-#define EBU_CLC(value) 0x0000(value)
-#define EBU_CON(value) 0x0010(value)
-#define EBU_ADDSEL0(value) 0x0020(value)
-#define EBU_ADDSEL1(value) 0x0024(value)
-#define EBU_ADDSEL2(value) 0x0028(value)
-#define EBU_ADDSEL3(value) 0x002C(value)
-#define EBU_BUSCON0(value) 0x0060(value)
-#define EBU_BUSCON1(value) 0x0064(value)
-#define EBU_BUSCON2(value) 0x0068(value)
-#define EBU_BUSCON3(value) 0x006C(value)
-
-#define MC_MODUL_BASE 0xBF800000
-#define MC_ERRCAUSE(value) 0x0010(value)
-#define MC_ERRADDR(value) 0x0020(value)
-#define MC_CON(value) 0x0060(value)
-
-#define MC_SRAM_ENABLE 0x00000004
-#define MC_SDRAM_ENABLE 0x00000002
-#define MC_DDRRAM_ENABLE 0x00000001
-
-#define MC_SDR_MODUL_BASE 0xBF800200
-#define MC_IOGP(value) 0x0000(value)
-#define MC_CTRLENA(value) 0x0010(value)
-#define MC_MRSCODE(value) 0x0020(value)
-#define MC_CFGDW(value) 0x0030(value)
-#define MC_CFGPB0(value) 0x0040(value)
-#define MC_LATENCY(value) 0x0080(value)
-#define MC_TREFRESH(value) 0x0090(value)
-#define MC_SELFRFSH(value) 0x00A0(value)
-
-#define MC_DDR_MODUL_BASE 0xBF801000
-#define MC_DC00(value) 0x0000(value)
-#define MC_DC01(value) 0x0010(value)
-#define MC_DC02(value) 0x0020(value)
-#define MC_DC03(value) 0x0030(value)
-#define MC_DC04(value) 0x0040(value)
-#define MC_DC05(value) 0x0050(value)
-#define MC_DC06(value) 0x0060(value)
-#define MC_DC07(value) 0x0070(value)
-#define MC_DC08(value) 0x0080(value)
-#define MC_DC09(value) 0x0090(value)
-#define MC_DC10(value) 0x00A0(value)
-#define MC_DC11(value) 0x00B0(value)
-#define MC_DC12(value) 0x00C0(value)
-#define MC_DC13(value) 0x00D0(value)
-#define MC_DC14(value) 0x00E0(value)
-#define MC_DC15(value) 0x00F0(value)
-#define MC_DC16(value) 0x0100(value)
-#define MC_DC17(value) 0x0110(value)
-#define MC_DC18(value) 0x0120(value)
-#define MC_DC19(value) 0x0130(value)
-#define MC_DC20(value) 0x0140(value)
-#define MC_DC21(value) 0x0150(value)
-#define MC_DC22(value) 0x0160(value)
-#define MC_DC23(value) 0x0170(value)
-#define MC_DC24(value) 0x0180(value)
-#define MC_DC25(value) 0x0190(value)
-#define MC_DC26(value) 0x01A0(value)
-#define MC_DC27(value) 0x01B0(value)
-#define MC_DC28(value) 0x01C0(value)
-#define MC_DC29(value) 0x01D0(value)
-#define MC_DC30(value) 0x01E0(value)
-#define MC_DC31(value) 0x01F0(value)
-#define MC_DC32(value) 0x0200(value)
-#define MC_DC33(value) 0x0210(value)
-#define MC_DC34(value) 0x0220(value)
-#define MC_DC35(value) 0x0230(value)
-#define MC_DC36(value) 0x0240(value)
-#define MC_DC37(value) 0x0250(value)
-#define MC_DC38(value) 0x0260(value)
-#define MC_DC39(value) 0x0270(value)
-#define MC_DC40(value) 0x0280(value)
-#define MC_DC41(value) 0x0290(value)
-#define MC_DC42(value) 0x02A0(value)
-#define MC_DC43(value) 0x02B0(value)
-#define MC_DC44(value) 0x02C0(value)
-#define MC_DC45(value) 0x02D0(value)
-#define MC_DC46(value) 0x02E0(value)
-
-#define RCU_OFFSET 0xBF203000
-#define RCU_RST_REQ (RCU_OFFSET + 0x0010)
-#define RCU_STS (RCU_OFFSET + 0x0014)
-
-#define CGU_OFFSET 0xBF103000
-#define PLL0_CFG (CGU_OFFSET + 0x0004)
-#define PLL1_CFG (CGU_OFFSET + 0x0008)
-#define PLL2_CFG (CGU_OFFSET + 0x000C)
-#define CGU_SYS (CGU_OFFSET + 0x0010)
-#define CGU_UPDATE (CGU_OFFSET + 0x0014)
-#define IF_CLK (CGU_OFFSET + 0x0018)
-#define CGU_SMD (CGU_OFFSET + 0x0020)
-#define CGU_CT1SR (CGU_OFFSET + 0x0028)
-#define CGU_CT2SR (CGU_OFFSET + 0x002C)
-#define CGU_PCMCR (CGU_OFFSET + 0x0030)
-#define PCI_CR_PCI (CGU_OFFSET + 0x0034)
-#define CGU_OSC_CTRL (CGU_OFFSET + 0x001C)
-#define CGU_MIPS_PWR_DWN (CGU_OFFSET + 0x0038)
-#define CLK_MEASURE (CGU_OFFSET + 0x003C)
-
-//05252006
-#define pll0_35MHz_CONFIG 0x9D861059
-#define pll1_35MHz_CONFIG 0x1A260CD9
-#define pll2_35MHz_CONFIG 0x8000f1e5
-#define pll0_36MHz_CONFIG 0x1000125D
-#define pll1_36MHz_CONFIG 0x1B1E0C99
-#define pll2_36MHz_CONFIG 0x8002f2a1
-//05252006
-
-//06063001-joelin disable the PCI CFRAME mask -start
-/*CFRAME is an I/O signal, in the chip, the output CFRAME is selected via GPIO altsel pins, so if you select MII1 RXD1, the CFRAME will not come out.
-But the CFRAME input still take the signal from the pad and not disabled when altsel choose other function. So when MII1_RXD1 is low from other device, the EBU interface will be disabled.
-
-The chip function in such a way that disable the CFRAME mask mean EBU not longer check CFRAME to be the device using the bus.
-The side effect is the entire PCI block will see CFRAME low all the time meaning PCI cannot use the bus at all so no more PCI function.
-*/
-#define PCI_CR_PR_OFFSET 0xBE105400
-#define PCI_CR_PCI_MOD_REG (PCI_CR_PR_OFFSET + 0x0030)
-#define PCI_CONFIG_SPACE 0xB7000000
-#define CS_CFM (PCI_CONFIG_SPACE + 0x6C)
-//06063001-joelin disable the PCI CFRAME mask -end
- .set noreorder
-
-
-/*
- * void ebu_init(void)
- */
- .globl ebu_init
- .ent ebu_init
-ebu_init:
-
-#if defined(CONFIG_EBU_ADDSEL0) || defined(CONFIG_EBU_ADDSEL1) || \
- defined(CONFIG_EBU_ADDSEL2) || defined(CONFIG_EBU_ADDSEL3) || \
- defined(CONFIG_EBU_BUSCON0) || defined(CONFIG_EBU_BUSCON1) || \
- defined(CONFIG_EBU_BUSCON2) || defined(CONFIG_EBU_BUSCON3)
-
- li t1, EBU_MODUL_BASE
-#if defined(CONFIG_EBU_ADDSEL0)
- li t2, CONFIG_EBU_ADDSEL0
- sw t2, EBU_ADDSEL0(t1)
-#endif
-#if defined(CONFIG_EBU_ADDSEL1)
- li t2, CONFIG_EBU_ADDSEL1
- sw t2, EBU_ADDSEL1(t1)
-#endif
-#if defined(CONFIG_EBU_ADDSEL2)
- li t2, CONFIG_EBU_ADDSEL2
- sw t2, EBU_ADDSEL2(t1)
-#endif
-#if defined(CONFIG_EBU_ADDSEL3)
- li t2, CONFIG_EBU_ADDSEL3
- sw t2, EBU_ADDSEL3(t1)
-#endif
-
-#if defined(CONFIG_EBU_BUSCON0)
- li t2, CONFIG_EBU_BUSCON0
- sw t2, EBU_BUSCON0(t1)
-#endif
-#if defined(CONFIG_EBU_BUSCON1)
- li t2, CONFIG_EBU_BUSCON1
- sw t2, EBU_BUSCON1(t1)
-#endif
-#if defined(CONFIG_EBU_BUSCON2)
- li t2, CONFIG_EBU_BUSCON2
- sw t2, EBU_BUSCON2(t1)
-#endif
-#if defined(CONFIG_EBU_BUSCON3)
- li t2, CONFIG_EBU_BUSCON3
- sw t2, EBU_BUSCON3(t1)
-#endif
-
-#endif
-
- j ra
- nop
-
- .end ebu_init
-
-
-/*
- * void cgu_init(long)
- *
- * a0 has the clock value
- */
- .globl cgu_init
- .ent cgu_init
-cgu_init:
- li t2, CGU_SYS
- lw t2,0(t2)
- beq t2,a0,freq_up2date
- nop
-
- li t2, RCU_STS
- lw t2, 0(t2)
- and t2,0x00020000
- beq t2,0x00020000,boot_36MHZ
- nop
-//05252006
- li t1, PLL0_CFG
- li t2, pll0_35MHz_CONFIG
- sw t2,0(t1)
- li t1, PLL1_CFG
- li t2, pll1_35MHz_CONFIG
- sw t2,0(t1)
- li t1, PLL2_CFG
- li t2, pll2_35MHz_CONFIG
- sw t2,0(t1)
- li t1, CGU_SYS
- sw a0,0(t1)
- li t1, RCU_RST_REQ
- li t2, 0x40000008
- sw t2,0(t1)
- b wait_reset
- nop
-boot_36MHZ:
- li t1, PLL0_CFG
- li t2, pll0_36MHz_CONFIG
- sw t2,0(t1)
- li t1, PLL1_CFG
- li t2, pll1_36MHz_CONFIG
- sw t2,0(t1)
- li t1, PLL2_CFG
- li t2, pll2_36MHz_CONFIG
- sw t2,0(t1)
- li t1, CGU_SYS
- sw a0,0(t1)
- li t1, RCU_RST_REQ
- li t2, 0x40000008
- sw t2,0(t1)
-//05252006
-
-wait_reset:
- b wait_reset
- nop
-freq_up2date:
- j ra
- nop
-
- .end cgu_init
-
-#ifndef CONFIG_USE_DDR_RAM
-/*
- * void sdram_init(long)
- *
- * a0 has the clock value
- */
- .globl sdram_init
- .ent sdram_init
-sdram_init:
-
- /* SDRAM Initialization
- */
- li t1, MC_MODUL_BASE
-
- /* Clear Error log registers */
- sw zero, MC_ERRCAUSE(t1)
- sw zero, MC_ERRADDR(t1)
-
- /* Enable SDRAM module in memory controller */
- li t3, MC_SDRAM_ENABLE
- lw t2, MC_CON(t1)
- or t3, t2, t3
- sw t3, MC_CON(t1)
-
- li t1, MC_SDR_MODUL_BASE
-
- /* disable the controller */
- li t2, 0
- sw t2, MC_CTRLENA(t1)
-
- li t2, 0x822
- sw t2, MC_IOGP(t1)
-
- li t2, 0x2
- sw t2, MC_CFGDW(t1)
-
- /* Set CAS Latency */
- li t2, 0x00000020
- sw t2, MC_MRSCODE(t1)
-
- /* Set CS0 to SDRAM parameters */
- li t2, 0x000014d8
- sw t2, MC_CFGPB0(t1)
-
- /* Set SDRAM latency parameters */
- li t2, 0x00036325; /* BC PC100 */
- sw t2, MC_LATENCY(t1)
-
- /* Set SDRAM refresh rate */
- li t2, 0x00000C30
- sw t2, MC_TREFRESH(t1)
-
- /* Clear Power-down registers */
- sw zero, MC_SELFRFSH(t1)
-
- /* Finally enable the controller */
- li t2, 1
- sw t2, MC_CTRLENA(t1)
-
- j ra
- nop
-
- .end sdram_init
-
-#endif /* !CONFIG_USE_DDR_RAM */
-
-#ifdef CONFIG_USE_DDR_RAM
-/*
- * void ddrram_init(long)
- *
- * a0 has the clock value
- */
- .globl ddrram_init
- .ent ddrram_init
-ddrram_init:
-
- /* DDR-DRAM Initialization
- */
- li t1, MC_MODUL_BASE
-
- /* Clear Error log registers */
- sw zero, MC_ERRCAUSE(t1)
- sw zero, MC_ERRADDR(t1)
-
- /* Enable DDR module in memory controller */
- li t3, MC_DDRRAM_ENABLE
- lw t2, MC_CON(t1)
- or t3, t2, t3
- sw t3, MC_CON(t1)
-
- li t1, MC_DDR_MODUL_BASE
-
- /* Write configuration to DDR controller registers */
- li t2, MC_DC0_VALUE
- sw t2, MC_DC00(t1)
-
- li t2, MC_DC1_VALUE
- sw t2, MC_DC01(t1)
-
- li t2, MC_DC2_VALUE
- sw t2, MC_DC02(t1)
-
- li t2, MC_DC3_VALUE
- sw t2, MC_DC03(t1)
-
- li t2, MC_DC4_VALUE
- sw t2, MC_DC04(t1)
-
- li t2, MC_DC5_VALUE
- sw t2, MC_DC05(t1)
-
- li t2, MC_DC6_VALUE
- sw t2, MC_DC06(t1)
-
- li t2, MC_DC7_VALUE
- sw t2, MC_DC07(t1)
-
- li t2, MC_DC8_VALUE
- sw t2, MC_DC08(t1)
-
- li t2, MC_DC9_VALUE
- sw t2, MC_DC09(t1)
-
- li t2, MC_DC10_VALUE
- sw t2, MC_DC10(t1)
-
- li t2, MC_DC11_VALUE
- sw t2, MC_DC11(t1)
-
- li t2, MC_DC12_VALUE
- sw t2, MC_DC12(t1)
-
- li t2, MC_DC13_VALUE
- sw t2, MC_DC13(t1)
-
- li t2, MC_DC14_VALUE
- sw t2, MC_DC14(t1)
-
- li t2, MC_DC15_VALUE
- sw t2, MC_DC15(t1)
-
- li t2, MC_DC16_VALUE
- sw t2, MC_DC16(t1)
-
- li t2, MC_DC17_VALUE
- sw t2, MC_DC17(t1)
-
- li t2, MC_DC18_VALUE
- sw t2, MC_DC18(t1)
-
- li t2, MC_DC19_VALUE
- sw t2, MC_DC19(t1)
-
- li t2, MC_DC20_VALUE
- sw t2, MC_DC20(t1)
-
- li t2, MC_DC21_VALUE
- sw t2, MC_DC21(t1)
-
- li t2, MC_DC22_VALUE
- sw t2, MC_DC22(t1)
-
- li t2, MC_DC23_VALUE
- sw t2, MC_DC23(t1)
-
- li t2, MC_DC24_VALUE
- sw t2, MC_DC24(t1)
-
- li t2, MC_DC25_VALUE
- sw t2, MC_DC25(t1)
-
- li t2, MC_DC26_VALUE
- sw t2, MC_DC26(t1)
-
- li t2, MC_DC27_VALUE
- sw t2, MC_DC27(t1)
-
- li t2, MC_DC28_VALUE
- sw t2, MC_DC28(t1)
-
- li t2, MC_DC29_VALUE
- sw t2, MC_DC29(t1)
-
- li t2, MC_DC30_VALUE
- sw t2, MC_DC30(t1)
-
- li t2, MC_DC31_VALUE
- sw t2, MC_DC31(t1)
-
- li t2, MC_DC32_VALUE
- sw t2, MC_DC32(t1)
-
- li t2, MC_DC33_VALUE
- sw t2, MC_DC33(t1)
-
- li t2, MC_DC34_VALUE
- sw t2, MC_DC34(t1)
-
- li t2, MC_DC35_VALUE
- sw t2, MC_DC35(t1)
-
- li t2, MC_DC36_VALUE
- sw t2, MC_DC36(t1)
-
- li t2, MC_DC37_VALUE
- sw t2, MC_DC37(t1)
-
- li t2, MC_DC38_VALUE
- sw t2, MC_DC38(t1)
-
- li t2, MC_DC39_VALUE
- sw t2, MC_DC39(t1)
-
- li t2, MC_DC40_VALUE
- sw t2, MC_DC40(t1)
-
- li t2, MC_DC41_VALUE
- sw t2, MC_DC41(t1)
-
- li t2, MC_DC42_VALUE
- sw t2, MC_DC42(t1)
-
- li t2, MC_DC43_VALUE
- sw t2, MC_DC43(t1)
-
- li t2, MC_DC44_VALUE
- sw t2, MC_DC44(t1)
-
- li t2, MC_DC45_VALUE
- sw t2, MC_DC45(t1)
-
- li t2, MC_DC46_VALUE
- sw t2, MC_DC46(t1)
-
- li t2, 0x00000100
- sw t2, MC_DC03(t1)
-
- j ra
- nop
-
- .end ddrram_init
-#endif /* CONFIG_USE_DDR_RAM */
-
- .globl lowlevel_init
- .ent lowlevel_init
-lowlevel_init:
- /* EBU, CGU and SDRAM/DDR-RAM Initialization.
- */
- move t0, ra
- /* We rely on the fact that non of the following ..._init() functions
- * modify t0
- */
-#if defined(DDR166)
- /* 0xe8 means CPU0/CPU1 333M, DDR 167M, FPI 83M, PPE 240M */
- li a0,0xe8
-#elif defined(DDR133)
- /* 0xe9 means CPU0/CPU1 333M, DDR 133M, FPI 83M, PPE 240M */
- li a0,0xe9
-#else /* defined(DDR111) */
- /* 0xea means CPU0/CPU1 333M, DDR 111M, FPI 83M, PPE 240M */
- li a0,0xea
-#endif
- bal cgu_init
- nop
-
- bal ebu_init
- nop
-
-//06063001-joelin disable the PCI CFRAME mask-start
-#ifdef DISABLE_CFRAME
- li t1, PCI_CR_PCI //mw bf103034 80000000
- li t2, 0x80000000
- sw t2,0(t1)
-
- li t1, PCI_CR_PCI_MOD_REG //mw be105430 103
- li t2, 0x103
- sw t2,0(t1)
-
- li t1, CS_CFM //mw b700006c 0
- li t2, 0x00
- sw t2, 0(t1)
-
- li t1, PCI_CR_PCI_MOD_REG //mw be105430 103
- li t2, 0x1000103
- sw t2, 0(t1)
-#endif
-//06063001-joelin disable the PCI CFRAME mask-end
-
-#ifdef CONFIG_USE_DDR_RAM
- bal ddrram_init
- nop
-#else
- bal sdram_init
- nop
-#endif
- move ra, t0
- j ra
- nop
-
- .end lowlevel_init
+++ /dev/null
-/*
- * Memory sub-system initialization code for Danube board.
- * Andre Messerschmidt
- * Copyright (c) 2005 Infineon Technologies AG
- *
- * Based on Inca-IP code
- * Copyright (c) 2003 Wolfgang Denk <wd@denx.de>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-/* History:
- peng liu May 25, 2006, for PLL setting after reset, 05252006
- */
-#include <config.h>
-#include <version.h>
-#include <asm/regdef.h>
-
-#if defined(CONFIG_USE_DDR_RAM)
-
-#if defined(CONFIG_USE_DDR_RAM_CFG_111M)
-#include "ddr_settings_r111.h"
-#define DDR111
-#elif defined(CONFIG_USE_DDR_RAM_CFG_166M)
-#include "ddr_settings_r166.h"
-#define DDR166
-#elif defined(CONFIG_USE_DDR_RAM_CFG_e111M)
-#include "ddr_settings_e111.h"
-#define DDR111
-#elif defined(CONFIG_USE_DDR_RAM_CFG_e166M)
-#include "ddr_settings_e166.h"
-#define DDR166
-#elif defined(CONFIG_USE_DDR_RAM_CFG_promos400)
-#include "ddr_settings_PROMOSDDR400.h"
-#define DDR166
-#elif defined(CONFIG_USE_DDR_RAM_CFG_samsung166)
-#include "ddr_settings_Samsung_166.h"
-#define DDR166
-#elif defined(CONFIG_USE_DDR_RAM_CFG_psc166)
-#include "ddr_settings_psc_166.h"
-#define DDR166
-#else
-#warning "missing definition for ddr_settings.h, use default!"
-#include "ddr_settings.h"
-#endif
-#endif /* CONFIG_USE_DDR_RAM */
-
-#if defined(CONFIG_USE_DDR_RAM) && !defined(MC_DC0_VALUE)
-#error "missing include of ddr_settings.h"
-#endif
-
-#define EBU_MODUL_BASE 0xBE105300
-#define EBU_CLC(value) 0x0000(value)
-#define EBU_CON(value) 0x0010(value)
-#define EBU_ADDSEL0(value) 0x0020(value)
-#define EBU_ADDSEL1(value) 0x0024(value)
-#define EBU_ADDSEL2(value) 0x0028(value)
-#define EBU_ADDSEL3(value) 0x002C(value)
-#define EBU_BUSCON0(value) 0x0060(value)
-#define EBU_BUSCON1(value) 0x0064(value)
-#define EBU_BUSCON2(value) 0x0068(value)
-#define EBU_BUSCON3(value) 0x006C(value)
-
-#define MC_MODUL_BASE 0xBF800000
-#define MC_ERRCAUSE(value) 0x0010(value)
-#define MC_ERRADDR(value) 0x0020(value)
-#define MC_CON(value) 0x0060(value)
-
-#define MC_SRAM_ENABLE 0x00000004
-#define MC_SDRAM_ENABLE 0x00000002
-#define MC_DDRRAM_ENABLE 0x00000001
-
-#define MC_SDR_MODUL_BASE 0xBF800200
-#define MC_IOGP(value) 0x0000(value)
-#define MC_CTRLENA(value) 0x0010(value)
-#define MC_MRSCODE(value) 0x0020(value)
-#define MC_CFGDW(value) 0x0030(value)
-#define MC_CFGPB0(value) 0x0040(value)
-#define MC_LATENCY(value) 0x0080(value)
-#define MC_TREFRESH(value) 0x0090(value)
-#define MC_SELFRFSH(value) 0x00A0(value)
-
-#define MC_DDR_MODUL_BASE 0xBF801000
-#define MC_DC00(value) 0x0000(value)
-#define MC_DC01(value) 0x0010(value)
-#define MC_DC02(value) 0x0020(value)
-#define MC_DC03(value) 0x0030(value)
-#define MC_DC04(value) 0x0040(value)
-#define MC_DC05(value) 0x0050(value)
-#define MC_DC06(value) 0x0060(value)
-#define MC_DC07(value) 0x0070(value)
-#define MC_DC08(value) 0x0080(value)
-#define MC_DC09(value) 0x0090(value)
-#define MC_DC10(value) 0x00A0(value)
-#define MC_DC11(value) 0x00B0(value)
-#define MC_DC12(value) 0x00C0(value)
-#define MC_DC13(value) 0x00D0(value)
-#define MC_DC14(value) 0x00E0(value)
-#define MC_DC15(value) 0x00F0(value)
-#define MC_DC16(value) 0x0100(value)
-#define MC_DC17(value) 0x0110(value)
-#define MC_DC18(value) 0x0120(value)
-#define MC_DC19(value) 0x0130(value)
-#define MC_DC20(value) 0x0140(value)
-#define MC_DC21(value) 0x0150(value)
-#define MC_DC22(value) 0x0160(value)
-#define MC_DC23(value) 0x0170(value)
-#define MC_DC24(value) 0x0180(value)
-#define MC_DC25(value) 0x0190(value)
-#define MC_DC26(value) 0x01A0(value)
-#define MC_DC27(value) 0x01B0(value)
-#define MC_DC28(value) 0x01C0(value)
-#define MC_DC29(value) 0x01D0(value)
-#define MC_DC30(value) 0x01E0(value)
-#define MC_DC31(value) 0x01F0(value)
-#define MC_DC32(value) 0x0200(value)
-#define MC_DC33(value) 0x0210(value)
-#define MC_DC34(value) 0x0220(value)
-#define MC_DC35(value) 0x0230(value)
-#define MC_DC36(value) 0x0240(value)
-#define MC_DC37(value) 0x0250(value)
-#define MC_DC38(value) 0x0260(value)
-#define MC_DC39(value) 0x0270(value)
-#define MC_DC40(value) 0x0280(value)
-#define MC_DC41(value) 0x0290(value)
-#define MC_DC42(value) 0x02A0(value)
-#define MC_DC43(value) 0x02B0(value)
-#define MC_DC44(value) 0x02C0(value)
-#define MC_DC45(value) 0x02D0(value)
-#define MC_DC46(value) 0x02E0(value)
-
-#define RCU_OFFSET 0xBF203000
-#define RCU_RST_REQ (RCU_OFFSET + 0x0010)
-#define RCU_STS (RCU_OFFSET + 0x0014)
-
-#define CGU_OFFSET 0xBF103000
-#define PLL0_CFG (CGU_OFFSET + 0x0004)
-#define PLL1_CFG (CGU_OFFSET + 0x0008)
-#define PLL2_CFG (CGU_OFFSET + 0x000C)
-#define CGU_SYS (CGU_OFFSET + 0x0010)
-#define CGU_UPDATE (CGU_OFFSET + 0x0014)
-#define IF_CLK (CGU_OFFSET + 0x0018)
-#define CGU_SMD (CGU_OFFSET + 0x0020)
-#define CGU_CT1SR (CGU_OFFSET + 0x0028)
-#define CGU_CT2SR (CGU_OFFSET + 0x002C)
-#define CGU_PCMCR (CGU_OFFSET + 0x0030)
-#define PCI_CR_PCI (CGU_OFFSET + 0x0034)
-#define CGU_OSC_CTRL (CGU_OFFSET + 0x001C)
-#define CGU_MIPS_PWR_DWN (CGU_OFFSET + 0x0038)
-#define CLK_MEASURE (CGU_OFFSET + 0x003C)
-
-//05252006
-#define pll0_35MHz_CONFIG 0x9D861059
-#define pll1_35MHz_CONFIG 0x1A260CD9
-#define pll2_35MHz_CONFIG 0x8000f1e5
-#define pll0_36MHz_CONFIG 0x1000125D
-#define pll1_36MHz_CONFIG 0x1B1E0C99
-#define pll2_36MHz_CONFIG 0x8002f2a1
-//05252006
-
-//06063001-joelin disable the PCI CFRAME mask -start
-/*CFRAME is an I/O signal, in the chip, the output CFRAME is selected via GPIO altsel pins, so if you select MII1 RXD1, the CFRAME will not come out.
-But the CFRAME input still take the signal from the pad and not disabled when altsel choose other function. So when MII1_RXD1 is low from other device, the EBU interface will be disabled.
-
-The chip function in such a way that disable the CFRAME mask mean EBU not longer check CFRAME to be the device using the bus.
-The side effect is the entire PCI block will see CFRAME low all the time meaning PCI cannot use the bus at all so no more PCI function.
-*/
-#define PCI_CR_PR_OFFSET 0xBE105400
-#define PCI_CR_PCI_MOD_REG (PCI_CR_PR_OFFSET + 0x0030)
-#define PCI_CONFIG_SPACE 0xB7000000
-#define CS_CFM (PCI_CONFIG_SPACE + 0x6C)
-//06063001-joelin disable the PCI CFRAME mask -end
- .set noreorder
-
-
-/*
- * void ebu_init(void)
- */
- .globl ebu_init
- .ent ebu_init
-ebu_init:
-
-#if defined(CONFIG_EBU_ADDSEL0) || defined(CONFIG_EBU_ADDSEL1) || \
- defined(CONFIG_EBU_ADDSEL2) || defined(CONFIG_EBU_ADDSEL3) || \
- defined(CONFIG_EBU_BUSCON0) || defined(CONFIG_EBU_BUSCON1) || \
- defined(CONFIG_EBU_BUSCON2) || defined(CONFIG_EBU_BUSCON3)
-
- li t1, EBU_MODUL_BASE
-#if defined(CONFIG_EBU_ADDSEL0)
- li t2, CONFIG_EBU_ADDSEL0
- sw t2, EBU_ADDSEL0(t1)
-#endif
-#if defined(CONFIG_EBU_ADDSEL1)
- li t2, CONFIG_EBU_ADDSEL1
- sw t2, EBU_ADDSEL1(t1)
-#endif
-#if defined(CONFIG_EBU_ADDSEL2)
- li t2, CONFIG_EBU_ADDSEL2
- sw t2, EBU_ADDSEL2(t1)
-#endif
-#if defined(CONFIG_EBU_ADDSEL3)
- li t2, CONFIG_EBU_ADDSEL3
- sw t2, EBU_ADDSEL3(t1)
-#endif
-
-#if defined(CONFIG_EBU_BUSCON0)
- li t2, CONFIG_EBU_BUSCON0
- sw t2, EBU_BUSCON0(t1)
-#endif
-#if defined(CONFIG_EBU_BUSCON1)
- li t2, CONFIG_EBU_BUSCON1
- sw t2, EBU_BUSCON1(t1)
-#endif
-#if defined(CONFIG_EBU_BUSCON2)
- li t2, CONFIG_EBU_BUSCON2
- sw t2, EBU_BUSCON2(t1)
-#endif
-#if defined(CONFIG_EBU_BUSCON3)
- li t2, CONFIG_EBU_BUSCON3
- sw t2, EBU_BUSCON3(t1)
-#endif
-
-#endif
-
- j ra
- nop
-
- .end ebu_init
-
-
-/*
- * void cgu_init(long)
- *
- * a0 has the clock value
- */
- .globl cgu_init
- .ent cgu_init
-cgu_init:
- li t2, CGU_SYS
- lw t2,0(t2)
- beq t2,a0,freq_up2date
- nop
-
- li t2, RCU_STS
- lw t2, 0(t2)
- and t2,0x00020000
- beq t2,0x00020000,boot_36MHZ
- nop
-//05252006
- li t1, PLL0_CFG
- li t2, pll0_35MHz_CONFIG
- sw t2,0(t1)
- li t1, PLL1_CFG
- li t2, pll1_35MHz_CONFIG
- sw t2,0(t1)
- li t1, PLL2_CFG
- li t2, pll2_35MHz_CONFIG
- sw t2,0(t1)
- li t1, CGU_SYS
- sw a0,0(t1)
- li t1, RCU_RST_REQ
- li t2, 0x40000008
- sw t2,0(t1)
- b wait_reset
- nop
-boot_36MHZ:
- li t1, PLL0_CFG
- li t2, pll0_36MHz_CONFIG
- sw t2,0(t1)
- li t1, PLL1_CFG
- li t2, pll1_36MHz_CONFIG
- sw t2,0(t1)
- li t1, PLL2_CFG
- li t2, pll2_36MHz_CONFIG
- sw t2,0(t1)
- li t1, CGU_SYS
- sw a0,0(t1)
- li t1, RCU_RST_REQ
- li t2, 0x40000008
- sw t2,0(t1)
-//05252006
-
-wait_reset:
- b wait_reset
- nop
-freq_up2date:
- j ra
- nop
-
- .end cgu_init
-
-#ifndef CONFIG_USE_DDR_RAM
-/*
- * void sdram_init(long)
- *
- * a0 has the clock value
- */
- .globl sdram_init
- .ent sdram_init
-sdram_init:
-
- /* SDRAM Initialization
- */
- li t1, MC_MODUL_BASE
-
- /* Clear Error log registers */
- sw zero, MC_ERRCAUSE(t1)
- sw zero, MC_ERRADDR(t1)
-
- /* Enable SDRAM module in memory controller */
- li t3, MC_SDRAM_ENABLE
- lw t2, MC_CON(t1)
- or t3, t2, t3
- sw t3, MC_CON(t1)
-
- li t1, MC_SDR_MODUL_BASE
-
- /* disable the controller */
- li t2, 0
- sw t2, MC_CTRLENA(t1)
-
- li t2, 0x822
- sw t2, MC_IOGP(t1)
-
- li t2, 0x2
- sw t2, MC_CFGDW(t1)
-
- /* Set CAS Latency */
- li t2, 0x00000020
- sw t2, MC_MRSCODE(t1)
-
- /* Set CS0 to SDRAM parameters */
- li t2, 0x000014d8
- sw t2, MC_CFGPB0(t1)
-
- /* Set SDRAM latency parameters */
- li t2, 0x00036325; /* BC PC100 */
- sw t2, MC_LATENCY(t1)
-
- /* Set SDRAM refresh rate */
- li t2, 0x00000C30
- sw t2, MC_TREFRESH(t1)
-
- /* Clear Power-down registers */
- sw zero, MC_SELFRFSH(t1)
-
- /* Finally enable the controller */
- li t2, 1
- sw t2, MC_CTRLENA(t1)
-
- j ra
- nop
-
- .end sdram_init
-
-#endif /* !CONFIG_USE_DDR_RAM */
-
-#ifdef CONFIG_USE_DDR_RAM
-/*
- * void ddrram_init(long)
- *
- * a0 has the clock value
- */
- .globl ddrram_init
- .ent ddrram_init
-ddrram_init:
-
- /* DDR-DRAM Initialization
- */
- li t1, MC_MODUL_BASE
-
- /* Clear Error log registers */
- sw zero, MC_ERRCAUSE(t1)
- sw zero, MC_ERRADDR(t1)
-
- /* Enable DDR module in memory controller */
- li t3, MC_DDRRAM_ENABLE
- lw t2, MC_CON(t1)
- or t3, t2, t3
- sw t3, MC_CON(t1)
-
- li t1, MC_DDR_MODUL_BASE
-
- /* Write configuration to DDR controller registers */
- li t2, MC_DC0_VALUE
- sw t2, MC_DC00(t1)
-
- li t2, MC_DC1_VALUE
- sw t2, MC_DC01(t1)
-
- li t2, MC_DC2_VALUE
- sw t2, MC_DC02(t1)
-
- li t2, MC_DC3_VALUE
- sw t2, MC_DC03(t1)
-
- li t2, MC_DC4_VALUE
- sw t2, MC_DC04(t1)
-
- li t2, MC_DC5_VALUE
- sw t2, MC_DC05(t1)
-
- li t2, MC_DC6_VALUE
- sw t2, MC_DC06(t1)
-
- li t2, MC_DC7_VALUE
- sw t2, MC_DC07(t1)
-
- li t2, MC_DC8_VALUE
- sw t2, MC_DC08(t1)
-
- li t2, MC_DC9_VALUE
- sw t2, MC_DC09(t1)
-
- li t2, MC_DC10_VALUE
- sw t2, MC_DC10(t1)
-
- li t2, MC_DC11_VALUE
- sw t2, MC_DC11(t1)
-
- li t2, MC_DC12_VALUE
- sw t2, MC_DC12(t1)
-
- li t2, MC_DC13_VALUE
- sw t2, MC_DC13(t1)
-
- li t2, MC_DC14_VALUE
- sw t2, MC_DC14(t1)
-
- li t2, MC_DC15_VALUE
- sw t2, MC_DC15(t1)
-
- li t2, MC_DC16_VALUE
- sw t2, MC_DC16(t1)
-
- li t2, MC_DC17_VALUE
- sw t2, MC_DC17(t1)
-
- li t2, MC_DC18_VALUE
- sw t2, MC_DC18(t1)
-
- li t2, MC_DC19_VALUE
- sw t2, MC_DC19(t1)
-
- li t2, MC_DC20_VALUE
- sw t2, MC_DC20(t1)
-
- li t2, MC_DC21_VALUE
- sw t2, MC_DC21(t1)
-
- li t2, MC_DC22_VALUE
- sw t2, MC_DC22(t1)
-
- li t2, MC_DC23_VALUE
- sw t2, MC_DC23(t1)
-
- li t2, MC_DC24_VALUE
- sw t2, MC_DC24(t1)
-
- li t2, MC_DC25_VALUE
- sw t2, MC_DC25(t1)
-
- li t2, MC_DC26_VALUE
- sw t2, MC_DC26(t1)
-
- li t2, MC_DC27_VALUE
- sw t2, MC_DC27(t1)
-
- li t2, MC_DC28_VALUE
- sw t2, MC_DC28(t1)
-
- li t2, MC_DC29_VALUE
- sw t2, MC_DC29(t1)
-
- li t2, MC_DC30_VALUE
- sw t2, MC_DC30(t1)
-
- li t2, MC_DC31_VALUE
- sw t2, MC_DC31(t1)
-
- li t2, MC_DC32_VALUE
- sw t2, MC_DC32(t1)
-
- li t2, MC_DC33_VALUE
- sw t2, MC_DC33(t1)
-
- li t2, MC_DC34_VALUE
- sw t2, MC_DC34(t1)
-
- li t2, MC_DC35_VALUE
- sw t2, MC_DC35(t1)
-
- li t2, MC_DC36_VALUE
- sw t2, MC_DC36(t1)
-
- li t2, MC_DC37_VALUE
- sw t2, MC_DC37(t1)
-
- li t2, MC_DC38_VALUE
- sw t2, MC_DC38(t1)
-
- li t2, MC_DC39_VALUE
- sw t2, MC_DC39(t1)
-
- li t2, MC_DC40_VALUE
- sw t2, MC_DC40(t1)
-
- li t2, MC_DC41_VALUE
- sw t2, MC_DC41(t1)
-
- li t2, MC_DC42_VALUE
- sw t2, MC_DC42(t1)
-
- li t2, MC_DC43_VALUE
- sw t2, MC_DC43(t1)
-
- li t2, MC_DC44_VALUE
- sw t2, MC_DC44(t1)
-
- li t2, MC_DC45_VALUE
- sw t2, MC_DC45(t1)
-
- li t2, MC_DC46_VALUE
- sw t2, MC_DC46(t1)
-
- li t2, 0x00000100
- sw t2, MC_DC03(t1)
-
- j ra
- nop
-
- .end ddrram_init
-#endif /* CONFIG_USE_DDR_RAM */
-
- .globl lowlevel_init
- .ent lowlevel_init
-lowlevel_init:
- /* EBU, CGU and SDRAM/DDR-RAM Initialization.
- */
- move t0, ra
- /* We rely on the fact that non of the following ..._init() functions
- * modify t0
- */
-#if defined(CONFIG_SYS_EBU_BOOT)
-#if defined(DDR166)
- /* 0xe8 means CPU0/CPU1 333M, DDR 167M, FPI 83M, PPE 240M */
- li a0,0xe8
-#elif defined(DDR133)
- /* 0xe9 means CPU0/CPU1 333M, DDR 133M, FPI 83M, PPE 240M */
- li a0,0xe9
-#else /* defined(DDR111) */
- /* 0xea means CPU0/CPU1 333M, DDR 111M, FPI 83M, PPE 240M */
- li a0,0xea
-#endif
- bal cgu_init
- nop
-#endif /* CONFIG_SYS_EBU_BOOT */
-
- bal ebu_init
- nop
-
-//06063001-joelin disable the PCI CFRAME mask-start
-#ifdef DISABLE_CFRAME
- li t1, PCI_CR_PCI //mw bf103034 80000000
- li t2, 0x80000000
- sw t2,0(t1)
-
- li t1, PCI_CR_PCI_MOD_REG //mw be105430 103
- li t2, 0x103
- sw t2,0(t1)
-
- li t1, CS_CFM //mw b700006c 0
- li t2, 0x00
- sw t2, 0(t1)
-
- li t1, PCI_CR_PCI_MOD_REG //mw be105430 103
- li t2, 0x1000103
- sw t2, 0(t1)
-#endif
-//06063001-joelin disable the PCI CFRAME mask-end
-
-#ifdef CONFIG_SYS_EBU_BOOT
-#ifndef CONFIG_SYS_RAMBOOT
-#ifdef CONFIG_USE_DDR_RAM
- bal ddrram_init
- nop
-#else
- bal sdram_init
- nop
-#endif
-#endif /* CONFIG_SYS_RAMBOOT */
-#endif /* CONFIG_SYS_EBU_BOOT */
-
- move ra, t0
- j ra
- nop
-
- .end lowlevel_init
+++ /dev/null
-/*
- * Power Management unit initialization code for AMAZON development board.
- *
- * Copyright (c) 2003 Ou Ke, Infineon.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <config.h>
-#include <version.h>
-#include <asm/regdef.h>
-
-#define PMU_PWDCR 0xBF10201C
-#define PMU_SR 0xBF102020
-
- .globl pmuenable
-
-pmuenable:
- li t0, PMU_PWDCR
- li t1, 0x2 /* enable everything */
- sw t1, 0(t0)
-#if 0
-1:
- li t0, PMU_SR
- lw t2, 0(t0)
- bne t1, t2, 1b
- nop
-#endif
- j ra
- nop
-
-
+++ /dev/null
-/*
- * (C) Copyright 2010 Industrie Dial Face S.p.A.
- * Luigi 'Comio' Mantellini, luigi.mantellini@idf-hit.com
- *
- * (C) Copyright 2003
- * Wolfgang Denk Engineering, <wd@denx.de>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/*
-OUTPUT_FORMAT("elf32-bigmips", "elf32-bigmips", "elf32-bigmips")
-*/
-OUTPUT_FORMAT("elf32-tradbigmips", "elf32-tradbigmips", "elf32-tradlittlemips")
-OUTPUT_ARCH(mips)
-ENTRY(_start)
-SECTIONS
-{
- . = 0x00000000;
-
- . = ALIGN(4);
- .text :
- {
- *(.text)
- }
-
- . = ALIGN(4);
- .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
-
- . = ALIGN(4);
- .data : { *(.data) }
-
- . = .;
- _gp = ALIGN(16) +0x7ff0;
-
- .got : {
- __got_start = .;
- *(.got)
- __got_end = .;
- }
-
- . = ALIGN(4);
- .sdata : { *(.sdata) }
-
- . = .;
- . = ALIGN(4);
- .payload : { *(.payload) }
- . = ALIGN(4);
-
- uboot_end_data = .;
- num_got_entries = (__got_end - __got_start) >> 2;
-
- . = ALIGN(4);
- .sbss : { *(.sbss) }
- .bss : { *(.bss) . = ALIGN(4); }
- uboot_end = .;
-}
-
+++ /dev/null
-/*
- * (C) Copyright 2003
- * Wolfgang Denk Engineering, <wd@denx.de>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/*
-OUTPUT_FORMAT("elf32-bigmips", "elf32-bigmips", "elf32-bigmips")
-*/
-OUTPUT_FORMAT("elf32-tradbigmips", "elf32-tradbigmips", "elf32-tradbigmips")
-OUTPUT_ARCH(mips)
-ENTRY(_start)
-SECTIONS
-{
- . = 0x00000000;
-
- . = ALIGN(4);
- .text :
- {
- *(.text)
- }
-
- . = ALIGN(4);
- .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
-
- . = ALIGN(4);
- .data : { *(.data) }
-
- . = .;
- _gp = ALIGN(16) + 0x7ff0;
-
- .got : {
- __got_start = .;
- *(.got)
- __got_end = .;
- }
-
- .sdata : { *(.sdata) }
-
- .u_boot_cmd : {
- __u_boot_cmd_start = .;
- *(.u_boot_cmd)
- __u_boot_cmd_end = .;
- }
-
- uboot_end_data = .;
- num_got_entries = (__got_end - __got_start) >> 2;
-
- . = ALIGN(4);
- .sbss (NOLOAD) : { *(.sbss) }
- .bss (NOLOAD) : { *(.bss) . = ALIGN(4); }
- uboot_end = .;
-}
+++ /dev/null
-#
-# (C) Copyright 2003-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-include $(TOPDIR)/config.mk
-
-LIB = $(obj)lib$(BOARD).a
-BOOTSTRAP_LIB = $(obj)lib$(BOARD)_bootstrap.a
-
-BOOTSTRAP_LIB-$(CONFIG_BOOTSTRAP) = $(BOOTSTRAP_LIB)
-
-COBJS-y += ar9.o
-
-SOBJS = lowlevel_init.o pmuenable.o
-
-BOOTSTRAP_COBJS-$(CONFIG_BOOTSTRAP) = $(BOARD)_bootstrap.o
-BOOTSTRAP_SOBJS-$(CONFIG_BOOTSTRAP) = lowlevel_bootstrap_init.o
-
-BOOTSTRAP_SRCS := $(BOOTSTRAP_SOBJS-y:.o=.S) $(BOOTSTRAP_COBJS-y:.o=.c)
-
-SRCS := $(sort $(SOBJS:.o=.S) $(COBJS:.o=.c) $(BOOTSTRAP_SOBJS:.o=.S))
-OBJS := $(addprefix $(obj),$(COBJS-y))
-SOBJS := $(addprefix $(obj),$(SOBJS))
-BOOTSTRAP_OBJS := $(addprefix $(obj),$(BOOTSTRAP_COBJS-y))
-BOOTSTRAP_SOBJS := $(addprefix $(obj),$(BOOTSTRAP_SOBJS-y))
-
-
-all: $(obj).depend $(LIB) $(BOOTSTRAP_LIB)
-
-$(LIB): $(obj).depend $(OBJS) $(SOBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
-
-$(BOOTSTRAP_LIB): $(BOOTSTRAP_OBJS) $(BOOTSTRAP_SOBJS)
- $(AR) $(ARFLAGS) $@ $(BOOTSTRAP_OBJS) $(BOOTSTRAP_SOBJS)
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+++ /dev/null
-/*
-* (C) Copyright 2003
-* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-*
-* (C) Copyright 2010
-* Thomas Langer, Ralph Hempel
-*
-* See file CREDITS for list of people who contributed to this
-* project.
-*
-* This program is free software; you can redistribute it and/or
-* modify it under the terms of the GNU General Public License as
-* published by the Free Software Foundation; either version 2 of
-* the License, or (at your option) any later version.
-*
-* This program is distributed in the hope that it will be useful,
-* but WITHOUT ANY WARRANTY; without even the implied warranty of
-* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-* GNU General Public License for more details.
-*
-* You should have received a copy of the GNU General Public License
-* along with this program; if not, write to the Free Software
-* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-* MA 02111-1307 USA
-*/
-
-#include <common.h>
-#include <command.h>
-#include <netdev.h>
-#include <miiphy.h>
-#include <asm/addrspace.h>
-#include <asm/ar9.h>
-#include <asm/reboot.h>
-#include <asm/io.h>
-#if defined(CONFIG_CMD_HTTPD)
-#include <httpd.h>
-#endif
-
-extern ulong ifx_get_ddr_hz(void);
-extern ulong ifx_get_cpuclk(void);
-
-/* definitions for external PHYs / Switches */
-/* Split values into phy address and register address */
-#define PHYADDR(_reg) ((_reg >> 5) & 0xff), (_reg & 0x1f)
-
-/* IDs and registers of known external switches */
-#define ID_SAMURAI_0 0x1020
-#define ID_SAMURAI_1 0x0007
-#define SAMURAI_ID_REG0 0xA0
-#define SAMURAI_ID_REG1 0xA1
-#define ID_TANTOS 0x2599
-
-#define RGMII_MODE 0
-#define MII_MODE 1
-#define REV_MII_MODE 2
-#define RED_MII_MODE_IC 3 /*Input clock */
-#define RGMII_MODE_100MB 4
-#define TURBO_REV_MII_MODE 6 /*Turbo Rev Mii mode */
-#define RED_MII_MODE_OC 7 /*Output clock */
-#define RGMII_MODE_10MB 8
-
-#define mdelay(n) udelay((n)*1000)
-
-static void ar9_sw_chip_init(u8 port, u8 mode);
-static void ar9_enable_sw_port(u8 port, u8 state);
-static void ar9_configure_sw_port(u8 port, u8 mode);
-static u16 ar9_smi_reg_read(u16 reg);
-static u16 ar9_smi_reg_write(u16 reg, u16 data);
-static char * const name = "lq_cpe_eth";
-static int external_switch_init(void);
-
-void _machine_restart(void)
-{
- *AR9_RCU_RST_REQ |= AR9_RST_ALL;
-}
-
-#ifdef CONFIG_SYS_RAMBOOT
-phys_size_t initdram(int board_type)
-{
- return get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, CONFIG_SYS_MAX_RAM);
-}
-#elif defined(CONFIG_USE_DDR_RAM)
-phys_size_t initdram(int board_type)
-{
- return (CONFIG_SYS_MAX_RAM);
-}
-#else
-
-static ulong max_sdram_size(void) /* per Chip Select */
-{
- /* The only supported SDRAM data width is 16bit.
- */
-#define CFG_DW 4
-
- /* The only supported number of SDRAM banks is 4.
- */
-#define CFG_NB 4
-
- ulong cfgpb0 = *AR9_SDRAM_MC_CFGPB0;
- int cols = cfgpb0 & 0xF;
- int rows = (cfgpb0 & 0xF0) >> 4;
- ulong size = (1 << (rows + cols)) * CFG_DW * CFG_NB;
-
- return size;
-}
-
-/*
-* Check memory range for valid RAM. A simple memory test determines
-* the actually available RAM size between addresses `base' and
-* `base + maxsize'.
-*/
-
-static long int dram_size(long int *base, long int maxsize)
-{
- volatile long int *addr;
- ulong cnt, val;
- ulong save[32]; /* to make test non-destructive */
- unsigned char i = 0;
-
- for (cnt = (maxsize / sizeof (long)) >> 1; cnt > 0; cnt >>= 1) {
- addr = base + cnt; /* pointer arith! */
-
- save[i++] = *addr;
- *addr = ~cnt;
- }
-
- /* write 0 to base address */
- addr = base;
- save[i] = *addr;
- *addr = 0;
-
- /* check at base address */
- if ((val = *addr) != 0) {
- *addr = save[i];
- return (0);
- }
-
- for (cnt = 1; cnt < maxsize / sizeof (long); cnt <<= 1) {
- addr = base + cnt; /* pointer arith! */
-
- val = *addr;
- *addr = save[--i];
-
- if (val != (~cnt)) {
- return (cnt * sizeof (long));
- }
- }
- return (maxsize);
-}
-
-phys_size_t initdram(int board_type)
-{
- int rows, cols, best_val = *AR9_SDRAM_MC_CFGPB0;
- ulong size, max_size = 0;
- ulong our_address;
-
- /* load t9 into our_address */
- asm volatile ("move %0, $25" : "=r" (our_address) :);
-
- /* Can't probe for RAM size unless we are running from Flash.
- * find out whether running from DRAM or Flash.
- */
- if (CPHYSADDR(our_address) < CPHYSADDR(PHYS_FLASH_1))
- {
- return max_sdram_size();
- }
-
- for (cols = 0x8; cols <= 0xC; cols++)
- {
- for (rows = 0xB; rows <= 0xD; rows++)
- {
- *AR9_SDRAM_MC_CFGPB0 = (0x14 << 8) |
- (rows << 4) | cols;
- size = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE,
- max_sdram_size());
-
- if (size > max_size)
- {
- best_val = *AR9_SDRAM_MC_CFGPB0;
- max_size = size;
- }
- }
- }
-
- *AR9_SDRAM_MC_CFGPB0 = best_val;
- return max_size;
-}
-#endif
-
-int checkboard (void)
-{
- unsigned long chipid = *AR9_MPS_CHIPID;
- int part_num;
-
- puts ("Board: ");
-
- part_num = AR9_MPS_CHIPID_PARTNUM_GET(chipid);
- switch (part_num)
- {
- case 0x16C:
- puts("ARX188 ");
- break;
- case 0x16D:
- puts("ARX168 ");
- break;
- case 0x16F:
- puts("ARX182 ");
- break;
- case 0x170:
- puts("GRX188 ");
- break;
- case 0x171:
- puts("GRX168 ");
- break;
- default:
- printf ("unknown, chip part number 0x%03X ", part_num);
- break;
- }
- printf ("V1.%ld, ", AR9_MPS_CHIPID_VERSION_GET(chipid));
-
- printf("DDR Speed %ld MHz, ", ifx_get_ddr_hz()/1000000);
- printf("CPU Speed %ld MHz\n", ifx_get_cpuclk()/1000000);
-
- return 0;
-}
-
-#ifdef CONFIG_SKIP_LOWLEVEL_INIT
-int board_early_init_f(void)
-{
-#ifdef CONFIG_EBU_ADDSEL0
- (*AR9_EBU_ADDSEL0) = CONFIG_EBU_ADDSEL0;
-#endif
-#ifdef CONFIG_EBU_ADDSEL1
- (*AR9_EBU_ADDSEL1) = CONFIG_EBU_ADDSEL1;
-#endif
-#ifdef CONFIG_EBU_ADDSEL2
- (*AR9_EBU_ADDSEL2) = CONFIG_EBU_ADDSEL2;
-#endif
-#ifdef CONFIG_EBU_ADDSEL3
- (*AR9_EBU_ADDSEL3) = CONFIG_EBU_ADDSEL3;
-#endif
-#ifdef CONFIG_EBU_BUSCON0
- (*AR9_EBU_BUSCON0) = CONFIG_EBU_BUSCON0;
-#endif
-#ifdef CONFIG_EBU_BUSCON1
- (*AR9_EBU_BUSCON1) = CONFIG_EBU_BUSCON1;
-#endif
-#ifdef CONFIG_EBU_BUSCON2
- (*AR9_EBU_BUSCON2) = CONFIG_EBU_BUSCON2;
-#endif
-#ifdef CONFIG_EBU_BUSCON3
- (*AR9_EBU_BUSCON3) = CONFIG_EBU_BUSCON3;
-#endif
-
- return 0;
-}
-#endif /* CONFIG_SKIP_LOWLEVEL_INIT */
-
-int board_eth_init(bd_t *bis)
-{
-#if defined(CONFIG_IFX_ETOP)
-
- *AR9_PMU_PWDCR &= 0xFFFFEFDF;
- *AR9_PMU_PWDCR &= ~AR9_PMU_DMA; /* enable DMA from PMU */
-
- if (lq_eth_initialize(bis) < 0)
- return -1;
-
- *AR9_RCU_RST_REQ |= 1;
- udelay(200000);
- *AR9_RCU_RST_REQ &= (unsigned long)~1;
- udelay(1000);
-
-#ifdef CONFIG_EXTRA_SWITCH
- if (external_switch_init()<0)
- return -1;
-#endif /* CONFIG_EXTRA_SWITCH */
-#endif /* CONFIG_IFX_ETOP */
-
- return 0;
-}
-
-static void ar9_configure_sw_port(u8 port, u8 mode)
-{
- if(port)
- {
- if (mode == 1) //MII mode
- {
- *AR9_GPIO_P2_ALTSEL0 = *AR9_GPIO_P2_ALTSEL0 | (0xf000);
- *AR9_GPIO_P2_ALTSEL1 = *AR9_GPIO_P2_ALTSEL1 & ~(0xf000);
- *AR9_GPIO_P2_DIR = (*AR9_GPIO_P2_DIR & ~(0xf000)) | 0x2000;
- *AR9_GPIO_P2_OD = *AR9_GPIO_P2_OD | 0x2000;
- }
- else if(mode == 2 || mode == 6) //Rev Mii mode
- {
- *AR9_GPIO_P2_ALTSEL0 = *AR9_GPIO_P2_ALTSEL0 | (0xf000);
- *AR9_GPIO_P2_ALTSEL1 = *AR9_GPIO_P2_ALTSEL1 & ~(0xf000);
- *AR9_GPIO_P2_DIR = (*AR9_GPIO_P2_DIR | (0xf000)) & ~0x2000;
- *AR9_GPIO_P2_OD = *AR9_GPIO_P2_OD | 0xd000;
- }
- }
- else //Port 0
- {
- if (mode == 1) //MII mode
- {
- *AR9_GPIO_P2_ALTSEL0 = *AR9_GPIO_P2_ALTSEL0 | (0x0303);
- *AR9_GPIO_P2_ALTSEL1 = *AR9_GPIO_P2_ALTSEL1 & ~(0x0303);
- *AR9_GPIO_P2_DIR = (*AR9_GPIO_P2_DIR & ~(0x0303)) | 0x0100;
- *AR9_GPIO_P2_OD = *AR9_GPIO_P2_OD | 0x0100;
- }
- else if(mode ==2 || mode ==6) //Rev Mii mode
- {
- *AR9_GPIO_P2_ALTSEL0 = *AR9_GPIO_P2_ALTSEL0 | (0x0303);
- *AR9_GPIO_P2_ALTSEL1 = *AR9_GPIO_P2_ALTSEL1 & ~(0x0303);
- *AR9_GPIO_P2_DIR = (*AR9_GPIO_P2_DIR | (0x0303)) & ~0x0100;
- *AR9_GPIO_P2_OD = *AR9_GPIO_P2_OD | 0x0203;
- }
- }
-}
-
-/*
-Call this function to place either MAC port 0 or 1 into working mode.
-Parameters:
-port - select ports 0 or 1.
-state of interface : state
-0: RGMII
-1: MII
-2: Rev MII
-3: Reduce MII (input clock)
-4: RGMII 100mb
-5: Reserve
-6: Turbo Rev MII
-7: Reduce MII (output clock)
-*/
-void ar9_enable_sw_port(u8 port, u8 state)
-{
- REG32(AR9_SW_GCTL0) |= 0x80000000;
- if (port == 0)
- {
- REG32(AR9_SW_RGMII_CTL) &= 0xffcffc0e ;
- //#if AR9_REFBOARD_TANTOS
- REG32(0xbf20302c) &= 0xffff81ff;
- REG32(0xbf20302c) |= 4<<9 ;
- //#endif
- REG32(AR9_SW_RGMII_CTL) |= ((u32)(state &0x3))<<8;
- if((state &0x3) == 0)
- {
- REG32(AR9_SW_RGMII_CTL) &= 0xfffffff3;
- if(state == 4)
- REG32(AR9_SW_RGMII_CTL) |= 0x4;
- else
- REG32(AR9_SW_RGMII_CTL) |= 0x8;
- }
- if(state == 6)
- REG32(AR9_SW_RGMII_CTL) |= ((u32) (1<<20));
- if(state == 7)
- REG32(AR9_SW_RGMII_CTL) |= ((u32) (1<<21));
- }
-// *AR9_PPE32_ETOP_CFG = *AR9_PPE32_ETOP_CFG & 0xfffffffe;
- else
- {
- REG32(AR9_SW_RGMII_CTL) &= 0xff303fff ;
- REG32(AR9_SW_RGMII_CTL) |= ((u32)(state &0x3))<<18;
- if((state &0x3) == 0)
- {
- REG32(AR9_SW_RGMII_CTL) &= 0xffffcfff;
- if(state == 4)
- REG32(AR9_SW_RGMII_CTL) |= 0x1000;
- else
- REG32(AR9_SW_RGMII_CTL) |= 0x2000;
- }
- if(state == 6)
- REG32(AR9_SW_RGMII_CTL) |= ((u32) (1<<22));
- if(state == 7)
- REG32(AR9_SW_RGMII_CTL) |= ((u32) (1<<23));
- }
-}
-
-void pci_reset(void)
-{
- int i,j;
-#define AR9_V1_PCI_RST_FIX 1
-#if AR9_V1_PCI_RST_FIX // 5th June 2008 Add GPIO19 to control EJTAG_TRST
- *AR9_GPIO_P1_ALTSEL0 = *AR9_GPIO_P1_ALTSEL0 & ~0x8;
- *AR9_GPIO_P1_ALTSEL1 = *AR9_GPIO_P1_ALTSEL1 & ~0x8;
- *AR9_GPIO_P1_DIR = *AR9_GPIO_P1_DIR | 0x8;
- *AR9_GPIO_P1_OD = *AR9_GPIO_P1_OD | 0x8;
- *AR9_GPIO_P1_OUT = *AR9_GPIO_P1_OUT | 0x8;
- *AR9_GPIO_P0_ALTSEL0 = *AR9_GPIO_P0_ALTSEL0 & ~0x4000;
- *AR9_GPIO_P0_ALTSEL1 = *AR9_GPIO_P0_ALTSEL1 & ~0x4000;
- *AR9_GPIO_P0_DIR = *AR9_GPIO_P0_DIR | 0x4000;
- *AR9_GPIO_P0_OD = *AR9_GPIO_P0_OD | 0x4000;
- for(j=0;j<5;j++) {
- *AR9_GPIO_P0_OUT = *AR9_GPIO_P0_OUT & ~0x4000;
- for(i=0;i<0x10000;i++);
- *AR9_GPIO_P0_OUT = *AR9_GPIO_P0_OUT | 0x4000;
- for(i=0;i<0x10000;i++);
- }
- *AR9_GPIO_P0_DIR = *AR9_GPIO_P0_DIR & ~0x4000;
- *AR9_GPIO_P1_DIR = *AR9_GPIO_P1_DIR & ~0x8;
-#endif
-}
-
-static u16 ar9_smi_reg_read(u16 reg)
-{
- int i;
- while(REG32(AR9_SW_MDIO_CTL) & 0x8000);
- REG32(AR9_SW_MDIO_CTL) = 0x8000| 0x2<<10 | ((u32) (reg&0x3ff)) ; /*0x10=MDIO_OP_READ*/
- for(i=0;i<0x3fff;i++);
- udelay(50);
- while(REG32(AR9_SW_MDIO_CTL) & 0x8000);
- return((u16) (REG32(AR9_SW_MDIO_DATA)));
-}
-
-static u16 ar9_smi_reg_write(u16 reg, u16 data)
-{
- int i;
- while(REG32(AR9_SW_MDIO_CTL) & 0x8000);
- REG32(AR9_SW_MDIO_CTL) = 0x8000| (((u32) data)<<16) | 0x01<<10 | ((u32) (reg&0x3ff)) ; /*0x01=MDIO_OP_WRITE*/
- for(i=0;i<0x3fff;i++);
- udelay(50);
- return 0;
-}
-
-static void ar9_sw_chip_init(u8 port, u8 mode)
-{
- int i;
- u16 chipid;
-
- debug("\nsearching for switches ... ");
-
- asm("sync");
- pci_reset();
-
- /* 25mhz clock out */
- *AR9_CGU_IFCCR &= ~(3<<10);
- *AR9_GPIO_P0_ALTSEL0 = *AR9_GPIO_P0_ALTSEL0 | (1<<3);
- *AR9_GPIO_P0_ALTSEL1 = *AR9_GPIO_P0_ALTSEL1 & ~(1<<3);
- *AR9_GPIO_P0_DIR = *AR9_GPIO_P0_DIR | (1<<3);
- *AR9_GPIO_P0_OD = *AR9_GPIO_P0_OD | (1<<3);
- *AR9_GPIO_P2_ALTSEL0 = *AR9_GPIO_P2_ALTSEL0 & ~(1<<0);
- *AR9_GPIO_P2_ALTSEL1 = *AR9_GPIO_P2_ALTSEL1 & ~(1<<0);
- *AR9_GPIO_P2_DIR = *AR9_GPIO_P2_DIR | (1<<0);
- *AR9_GPIO_P2_OD = *AR9_GPIO_P2_OD | (1<<0);
-
- *AR9_PMU_PWDCR = (*AR9_PMU_PWDCR & 0xFFFBDFDF) ;
- *AR9_PMU_PWDCR = (*AR9_PMU_PWDCR & ~(AR9_PMU_DMA | AR9_PMU_SWITCH));
- *AR9_PMU_PWDCR = (*AR9_PMU_PWDCR | AR9_PMU_USB0 | AR9_PMU_USB0_P);
-
- *AR9_GPIO_P2_OUT &= ~(1<<0);
- asm("sync");
-
- ar9_configure_sw_port(port, mode);
- ar9_enable_sw_port(port, mode);
- REG32(AR9_SW_P0_CTL) |= 0x400000; /* disable mdio polling for tantos */
- asm("sync");
-
- /*GPIO 55(P3.7) used as output, set high*/
- *AR9_GPIO_P3_OD |=(1<<7);
- *AR9_GPIO_P3_DIR |= (1<<7);
- *AR9_GPIO_P3_ALTSEL0 &=~(1<<7);
- *AR9_GPIO_P3_ALTSEL1 &=~(1<<7);
- asm("sync");
- udelay(10);
-
- *AR9_GPIO_P3_OUT &= ~(1<<7);
- for(i=0;i<1000;i++)
- udelay(110);
- *AR9_GPIO_P3_OUT |=(1<<7);
- udelay(100);
-
- if(port==0)
- REG32(AR9_SW_P0_CTL) |= 0x40001;
- else
- REG32(AR9_SW_P1_CTL) |= 0x40001;
-
- REG32(AR9_SW_P2_CTL) |= 0x40001;
- REG32(AR9_SW_PMAC_HD_CTL) |= 0x40000; /* enable CRC */
-
- *AR9_GPIO_P2_ALTSEL0 = *AR9_GPIO_P2_ALTSEL0 | (0xc00);
- *AR9_GPIO_P2_ALTSEL1 = *AR9_GPIO_P2_ALTSEL1 & ~(0xc00);
- *AR9_GPIO_P2_DIR = *AR9_GPIO_P2_DIR | 0xc00;
- *AR9_GPIO_P2_OD = *AR9_GPIO_P2_OD | 0xc00;
-
- asm("sync");
- chipid = (unsigned short)(ar9_smi_reg_read(0x101));
- printf("\nswitch chip id=%08x\n",chipid);
- if (chipid != ID_TANTOS) {
- debug("whatever detected\n");
- ar9_smi_reg_write(0x1,0x840f);
- ar9_smi_reg_write(0x3,0x840f);
- ar9_smi_reg_write(0x5,0x840f);
- ar9_smi_reg_write(0x7,0x840f);
- ar9_smi_reg_write(0x8,0x840f);
- ar9_smi_reg_write(0x12,0x3602);
-#ifdef CLK_OUT2_25MHZ
- ar9_smi_reg_write(0x33,0x4000);
-#endif
- } else { // Tantos switch ship
- debug("Tantos switch detected\n");
- ar9_smi_reg_write(0xa1,0x0004); /*port 5 force link up*/
- ar9_smi_reg_write(0xc1,0x0004); /*port 6 force link up*/
- ar9_smi_reg_write(0xf5,0x0BBB); /*port 4 duplex mode, flow control enable,1000Mbit/s*/
- /*port 5 duplex mode, flow control enable, 1000Mbit/s*/
- /*port 6 duplex mode, flow control enable, 1000Mbit/s*/
- }
- asm("sync");
-
- /*reset GPHY*/
- mdelay(200);
- *AR9_RCU_RST_REQ |= (AR9_RCU_RST_REQ_DMA | AR9_RCU_RST_REQ_PPE) ;
- udelay(50);
- *AR9_GPIO_P2_OUT |= (1<<0);
-}
-
-static void ar9_dma_init(void)
-{
- /* select port */
- *AR9_DMA_PS = 0;
-
- /*
- TXWGT 14:12 rw Port Weight for Transmit Direction (the default value \93001\94)
-
- TXENDI 11:10 rw Endianness for Transmit Direction
- Determine a byte swap between memory interface (left hand side) and
- peripheral interface (right hand side).
- 00B B0_B1_B2_B3 No byte switching
- 01B B1_B0_B3_B2 B0B1B2B3 => B1B0B3B2
- 10B B2_B3_B0_B1 B0B1B2B3 => B2B3B0B1
-
- RXENDI 9:8 rw Endianness for Receive Direction
- Determine a byte swap between peripheral (left hand side) and memory
- interface (right hand side).
- 00B B0_B1_B2_B3 No byte switching
- 01B B1_B0_B3_B2 B0B1B2B3 => B1B0B3B2
- 10B B2_B3_B0_B1 B0B1B2B3 => B2B3B0B1
- 11B B3_B2_B1_B0 B0B1B2B3 => B3B2B1B0
-
- TXBL 5:4 rw Burst Length for Transmit Direction
- Selects burst length for TX direction.
- Others are reserved and will result in 2_WORDS burst length.
- 01B 2_WORDS 2 words
- 10B 4_WORDS 4 words
- 11B 8_WORDS 8 words
-
- RXBL 3:2 rw Burst Length for Receive Direction
- Selects burst length for RX direction.
- Others are reserved and will result in 2_WORDS burst length.
- 01B 2_WORDS 2 words
- 10B 4_WORDS 4 words
- 11B 8_WORDS 8 words
- */
- *AR9_DMA_PCTRL = 0x1f28;
-}
-
-#ifdef CONFIG_EXTRA_SWITCH
-static int external_switch_init(void)
-{
- ar9_sw_chip_init(0, RGMII_MODE);
-
- ar9_dma_init();
-
- return 0;
-}
-#endif /* CONFIG_EXTRA_SWITCH */
-
-#if defined(CONFIG_CMD_HTTPD)
-int do_http_upgrade(const unsigned char *data, const ulong size)
-{
- char buf[128];
-
- if(getenv ("ram_addr") == NULL)
- return -1;
- if(getenv ("kernel_addr") == NULL)
- return -1;
- /* check the image */
- if(run_command("imi ${ram_addr}", 0) < 0) {
- return -1;
- }
- /* write the image to the flash */
- puts("http ugrade ...\n");
- sprintf(buf, "era ${kernel_addr} +0x%x; cp.b ${ram_addr} ${kernel_addr} 0x%x", size, size);
- return run_command(buf, 0);
-}
-
-int do_http_progress(const int state)
-{
- /* toggle LED's here */
- switch(state) {
- case HTTP_PROGRESS_START:
- puts("http start\n");
- break;
- case HTTP_PROGRESS_TIMEOUT:
- puts(".");
- break;
- case HTTP_PROGRESS_UPLOAD_READY:
- puts("http upload ready\n");
- break;
- case HTTP_PROGRESS_UGRADE_READY:
- puts("http ugrade ready\n");
- break;
- case HTTP_PROGRESS_UGRADE_FAILED:
- puts("http ugrade failed\n");
- break;
- }
- return 0;
-}
-
-unsigned long do_http_tmp_address(void)
-{
- char *s = getenv ("ram_addr");
- if (s) {
- ulong tmp = simple_strtoul (s, NULL, 16);
- return tmp;
- }
- return 0 /*0x80a00000*/;
-}
-
-#endif
+++ /dev/null
-/* Settings for Denali DDR SDRAM controller */
-/* Optimise for Samsung DDR K4H561638H Danube Ref Board DDR 166 Mhz - by Ng Aik Ann 27th Nov 2006 */
-
-#define MC_DC0_VALUE 0x1B1B
-#define MC_DC1_VALUE 0x0
-#define MC_DC2_VALUE 0x0
-#define MC_DC3_VALUE 0x0
-#define MC_DC4_VALUE 0x0
-#define MC_DC5_VALUE 0x200
-#define MC_DC6_VALUE 0x306
-#define MC_DC7_VALUE 0x303
-#define MC_DC8_VALUE 0x102
-#define MC_DC9_VALUE 0x70a
-#define MC_DC10_VALUE 0x203
-#define MC_DC11_VALUE 0xc02
-#define MC_DC12_VALUE 0x1C8
-#define MC_DC13_VALUE 0x1
-#define MC_DC14_VALUE 0x0
-#define MC_DC15_VALUE 0x139 /* WDQS tuning for clk_wr*/
-#define MC_DC16_VALUE 0x2200
-#define MC_DC17_VALUE 0xd
-#define MC_DC18_VALUE 0x301
-#define MC_DC19_VALUE 0x200
-#define MC_DC20_VALUE 0xA04 /* A04 for reference board, A03 for Eval board */
-#define MC_DC21_VALUE 0x1800
-#define MC_DC22_VALUE 0x1818
-#define MC_DC23_VALUE 0x0
-#define MC_DC24_VALUE 0x59 /* WDQS Tuning for DQS */
-#define MC_DC25_VALUE 0x0
-#define MC_DC26_VALUE 0x0
-#define MC_DC27_VALUE 0x0
-#define MC_DC28_VALUE 0x514
-#define MC_DC29_VALUE 0x2d93
-#define MC_DC30_VALUE 0x8235
-#define MC_DC31_VALUE 0x0
-#define MC_DC32_VALUE 0x0
-#define MC_DC33_VALUE 0x0
-#define MC_DC34_VALUE 0x0
-#define MC_DC35_VALUE 0x0
-#define MC_DC36_VALUE 0x0
-#define MC_DC37_VALUE 0x0
-#define MC_DC38_VALUE 0x0
-#define MC_DC39_VALUE 0x0
-#define MC_DC40_VALUE 0x0
-#define MC_DC41_VALUE 0x0
-#define MC_DC42_VALUE 0x0
-#define MC_DC43_VALUE 0x0
-#define MC_DC44_VALUE 0x0
-#define MC_DC45_VALUE 0x600
-//#define MC_DC45_VALUE 0x400
-#define MC_DC46_VALUE 0x0
+++ /dev/null
-/* Settings for Denali DDR SDRAM controller */
-/* Optimise for Samsung DDR K4H561638H Danube Ref Board DDR 166 Mhz - by Ng Aik Ann 27th Nov 2006 */
-
-#define MC_DC0_VALUE 0x1B1B
-#define MC_DC1_VALUE 0x0
-#define MC_DC2_VALUE 0x0
-#define MC_DC3_VALUE 0x0
-#define MC_DC4_VALUE 0x0
-#define MC_DC5_VALUE 0x200
-#define MC_DC6_VALUE 0x306
-#define MC_DC7_VALUE 0x303
-#define MC_DC8_VALUE 0x102
-#define MC_DC9_VALUE 0x70a
-#define MC_DC10_VALUE 0x203
-#define MC_DC11_VALUE 0xc02
-#define MC_DC12_VALUE 0x1C8
-#define MC_DC13_VALUE 0x1
-#define MC_DC14_VALUE 0x0
-#define MC_DC15_VALUE 0x13f /* WDQS tuning for clk_wr*/
-#define MC_DC16_VALUE 0x2200
-#define MC_DC17_VALUE 0xd
-#define MC_DC18_VALUE 0x301
-#define MC_DC19_VALUE 0x200
-#define MC_DC20_VALUE 0xA04 /* A04 for reference board, A03 for Eval board */
-#define MC_DC21_VALUE 0x1600
-#define MC_DC22_VALUE 0x1616
-#define MC_DC23_VALUE 0x0
-#define MC_DC24_VALUE 0x5d /* WDQS Tuning for DQS */
-#define MC_DC25_VALUE 0x0
-#define MC_DC26_VALUE 0x0
-#define MC_DC27_VALUE 0x0
-#define MC_DC28_VALUE 0x514
-#define MC_DC29_VALUE 0x2d93
-#define MC_DC30_VALUE 0x8235
-#define MC_DC31_VALUE 0x0
-#define MC_DC32_VALUE 0x0
-#define MC_DC33_VALUE 0x0
-#define MC_DC34_VALUE 0x0
-#define MC_DC35_VALUE 0x0
-#define MC_DC36_VALUE 0x0
-#define MC_DC37_VALUE 0x0
-#define MC_DC38_VALUE 0x0
-#define MC_DC39_VALUE 0x0
-#define MC_DC40_VALUE 0x0
-#define MC_DC41_VALUE 0x0
-#define MC_DC42_VALUE 0x0
-#define MC_DC43_VALUE 0x0
-#define MC_DC44_VALUE 0x0
-#define MC_DC45_VALUE 0x600
-//#define MC_DC45_VALUE 0x400
-#define MC_DC46_VALUE 0x0
+++ /dev/null
-/* Settings for Denali DDR SDRAM controller */
-/* Optimise for Samsung DDR K4H561638H Danube Ref Board DDR 166 Mhz - by Ng Aik Ann 27th Nov 2006 */
-
-#define MC_DC0_VALUE 0x1B1B
-#define MC_DC1_VALUE 0x0
-#define MC_DC2_VALUE 0x0
-#define MC_DC3_VALUE 0x0
-#define MC_DC4_VALUE 0x0
-#define MC_DC5_VALUE 0x200
-#define MC_DC6_VALUE 0x306
-#define MC_DC7_VALUE 0x303
-#define MC_DC8_VALUE 0x102
-#define MC_DC9_VALUE 0x80B
-#define MC_DC10_VALUE 0x203
-#define MC_DC11_VALUE 0xD02
-#define MC_DC12_VALUE 0x1C8
-#define MC_DC13_VALUE 0x1
-#define MC_DC14_VALUE 0x0
-#define MC_DC15_VALUE 0x144 /* WDQS tuning for clk_wr*/
-#define MC_DC16_VALUE 0xC800
-#define MC_DC17_VALUE 0xF
-#define MC_DC18_VALUE 0x301
-#define MC_DC19_VALUE 0x200
-#define MC_DC20_VALUE 0xA04 /* A04 for reference board, A03 for Eval board */
-#define MC_DC21_VALUE 0x1200
-#define MC_DC22_VALUE 0x1212
-#define MC_DC23_VALUE 0x0
-#define MC_DC24_VALUE 0x66 /* WDQS Tuning for DQS */
-#define MC_DC25_VALUE 0x0
-#define MC_DC26_VALUE 0x0
-#define MC_DC27_VALUE 0x0
-#define MC_DC28_VALUE 0x5FB
-#define MC_DC29_VALUE 0x35DF
-#define MC_DC30_VALUE 0x99E9
-#define MC_DC31_VALUE 0x0
-#define MC_DC32_VALUE 0x0
-#define MC_DC33_VALUE 0x0
-#define MC_DC34_VALUE 0x0
-#define MC_DC35_VALUE 0x0
-#define MC_DC36_VALUE 0x0
-#define MC_DC37_VALUE 0x0
-#define MC_DC38_VALUE 0x0
-#define MC_DC39_VALUE 0x0
-#define MC_DC40_VALUE 0x0
-#define MC_DC41_VALUE 0x0
-#define MC_DC42_VALUE 0x0
-#define MC_DC43_VALUE 0x0
-#define MC_DC44_VALUE 0x0
-#define MC_DC45_VALUE 0x600
-//#define MC_DC45_VALUE 0x400
-#define MC_DC46_VALUE 0x0
+++ /dev/null
-/* Settings for Denali DDR SDRAM controller */
-/* Optimise for AR9 Ref Board DDR 221 Mhz - by Ng Aik Ann 16th May 2008 */
-
-#define MC_DC0_VALUE 0x1B1B
-#define MC_DC1_VALUE 0x0
-#define MC_DC2_VALUE 0x0
-#define MC_DC3_VALUE 0x0
-#define MC_DC4_VALUE 0x0
-#define MC_DC5_VALUE 0x200
-#define MC_DC6_VALUE 0x306
-#define MC_DC7_VALUE 0x403
-#define MC_DC8_VALUE 0x102
-#define MC_DC9_VALUE 0x90c
-#define MC_DC10_VALUE 0x203
-#define MC_DC11_VALUE 0xf02
-#define MC_DC12_VALUE 0x2c8
-#define MC_DC13_VALUE 0x1
-#define MC_DC14_VALUE 0x0
-#define MC_DC15_VALUE 0x12f /* WDQS tuning for clk_wr*/
-#define MC_DC16_VALUE 0xc800
-#define MC_DC17_VALUE 0xf
-#define MC_DC18_VALUE 0x301
-#define MC_DC19_VALUE 0x200
-#define MC_DC20_VALUE 0xA04 /* A04 for reference board, A03 for Eval board */
-#define MC_DC21_VALUE 0x1500
-#define MC_DC22_VALUE 0x1515
-#define MC_DC23_VALUE 0x0
-#define MC_DC24_VALUE 0x57 /* WDQS Tuning for DQS */
-#define MC_DC25_VALUE 0x0
-#define MC_DC26_VALUE 0x0
-#define MC_DC27_VALUE 0x0
-#define MC_DC28_VALUE 0x6b8
-#define MC_DC29_VALUE 0x3c84
-#define MC_DC30_VALUE 0xace5
-#define MC_DC31_VALUE 0x0
-#define MC_DC32_VALUE 0x0
projects / openwrt.git / commitdiff