package/uboot-lantiq/files/board/infineon/easy50712/danube.c

   1 /*
   2  * (C) Copyright 2003
   3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4  *
   5  * (C) Copyright 2010
   6  * Thomas Langer, Ralph Hempel
   7  *
   8  * See file CREDITS for list of people who contributed to this
   9  * project.
  10  *
  11  * This program is free software; you can redistribute it and/or
  12  * modify it under the terms of the GNU General Public License as
  13  * published by the Free Software Foundation; either version 2 of
  14  * the License, or (at your option) any later version.
  15  *
  16  * This program is distributed in the hope that it will be useful,
  17  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  18  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  19  * GNU General Public License for more details.
  20  *
  21  * You should have received a copy of the GNU General Public License
  22  * along with this program; if not, write to the Free Software
  23  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  24  * MA 02111-1307 USA
  25  */
  26
  27 #include <common.h>
  28 #include <command.h>
  29 #include <netdev.h>
  30 #include <miiphy.h>
  31 #include <asm/addrspace.h>
  32 #include <asm/danube.h>
  33 #include <asm/reboot.h>
  34 #include <asm/io.h>
  35 #if defined(CONFIG_CMD_HTTPD)
  36 #include <httpd.h>
  37 #endif
  38
  39 extern ulong ifx_get_ddr_hz(void);
  40 extern ulong ifx_get_cpuclk(void);
  41
  42 /* definitions for external PHYs / Switches */
  43 /* Split values into phy address and register address */
  44 #define PHYADDR(_reg)   ((_reg >> 5) & 0xff), (_reg & 0x1f)
  45
  46 /* IDs and registers of known external switches */
  47 #define ID_SAMURAI_0    0x1020
  48 #define ID_SAMURAI_1    0x0007
  49 #define SAMURAI_ID_REG0 0xA0
  50 #define SAMURAI_ID_REG1 0xA1
  51
  52 #define ID_TANTOS       0x2599
  53
  54 void _machine_restart(void)
  55 {
  56         *DANUBE_RCU_RST_REQ |=1<<30;
  57 }
  58
  59 #ifdef CONFIG_SYS_RAMBOOT
  60 phys_size_t initdram(int board_type)
  61 {
  62         return get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, CONFIG_SYS_MAX_RAM);
  63 }
  64 #elif defined(CONFIG_USE_DDR_RAM)
  65 phys_size_t initdram(int board_type)
  66 {
  67         return (CONFIG_SYS_MAX_RAM);
  68 }
  69 #else
  70
  71 static ulong max_sdram_size(void)     /* per Chip Select */
  72 {
  73         /* The only supported SDRAM data width is 16bit.
  74          */
  75 #define CFG_DW  4
  76
  77         /* The only supported number of SDRAM banks is 4.
  78          */
  79 #define CFG_NB  4
  80
  81         ulong cfgpb0 = *DANUBE_SDRAM_MC_CFGPB0;
  82         int   cols   = cfgpb0 & 0xF;
  83         int   rows   = (cfgpb0 & 0xF0) >> 4;
  84         ulong size   = (1 << (rows + cols)) * CFG_DW * CFG_NB;
  85
  86         return size;
  87 }
  88
  89 /*
  90  * Check memory range for valid RAM. A simple memory test determines
  91  * the actually available RAM size between addresses `base' and
  92  * `base + maxsize'.
  93  */
  94
  95 static long int dram_size(long int *base, long int maxsize)
  96 {
  97         volatile long int *addr;
  98         ulong cnt, val;
  99         ulong save[32];                 /* to make test non-destructive */
 100         unsigned char i = 0;
 101
 102         for (cnt = (maxsize / sizeof (long)) >> 1; cnt > 0; cnt >>= 1) {
 103                 addr = base + cnt;              /* pointer arith! */
 104
 105                 save[i++] = *addr;
 106                 *addr = ~cnt;
 107         }
 108
 109         /* write 0 to base address */
 110         addr = base;
 111         save[i] = *addr;
 112         *addr = 0;
 113
 114         /* check at base address */
 115         if ((val = *addr) != 0) {
 116                 *addr = save[i];
 117                 return (0);
 118         }
 119
 120         for (cnt = 1; cnt < maxsize / sizeof (long); cnt <<= 1) {
 121                 addr = base + cnt;              /* pointer arith! */
 122
 123                 val = *addr;
 124                 *addr = save[--i];
 125
 126                 if (val != (~cnt)) {
 127                         return (cnt * sizeof (long));
 128                 }
 129         }
 130         return (maxsize);
 131 }
 132
 133 phys_size_t initdram(int board_type)
 134 {
 135         int   rows, cols, best_val = *DANUBE_SDRAM_MC_CFGPB0;
 136         ulong size, max_size       = 0;
 137         ulong our_address;
 138
 139         /* load t9 into our_address */
 140         asm volatile ("move %0, $25" : "=r" (our_address) :);
 141
 142         /* Can't probe for RAM size unless we are running from Flash.
 143          * find out whether running from DRAM or Flash.
 144          */
 145         if (CPHYSADDR(our_address) < CPHYSADDR(PHYS_FLASH_1))
 146         {
 147                 return max_sdram_size();
 148         }
 149
 150         for (cols = 0x8; cols <= 0xC; cols++)
 151         {
 152                 for (rows = 0xB; rows <= 0xD; rows++)
 153                 {
 154                         *DANUBE_SDRAM_MC_CFGPB0 = (0x14 << 8) |
 155                                                   (rows << 4) | cols;
 156                         size = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE,
 157                                                   max_sdram_size());
 158
 159                         if (size > max_size)
 160                         {
 161                                 best_val = *DANUBE_SDRAM_MC_CFGPB0;
 162                                 max_size = size;
 163                         }
 164                 }
 165         }
 166
 167         *DANUBE_SDRAM_MC_CFGPB0 = best_val;
 168         return max_size;
 169 }
 170 #endif
 171
 172 int checkboard (void)
 173 {
 174         unsigned long chipid = *DANUBE_MPS_CHIPID;
 175         int part_num;
 176
 177         puts ("Board: ");
 178
 179         part_num = DANUBE_MPS_CHIPID_PARTNUM_GET(chipid);
 180         switch (part_num)
 181         {
 182         case 0x129:
 183         case 0x12B:
 184         case 0x12D:
 185                 puts("Danube/Twinpass/Vinax-VE ");
 186                 break;
 187         default:
 188                 printf ("unknown, chip part number 0x%03X ", part_num);
 189                 break;
 190         }
 191         printf ("V1.%ld, ", DANUBE_MPS_CHIPID_VERSION_GET(chipid));
 192
 193         printf("DDR Speed %ld MHz, ", ifx_get_ddr_hz()/1000000);
 194         printf("CPU Speed %ld MHz\n", ifx_get_cpuclk()/1000000);
 195
 196         return 0;
 197 }
 198
 199 #ifdef CONFIG_SKIP_LOWLEVEL_INIT
 200 int board_early_init_f(void)
 201 {
 202 #ifdef CONFIG_EBU_ADDSEL0
 203         (*DANUBE_EBU_ADDSEL0) = CONFIG_EBU_ADDSEL0;
 204 #endif
 205 #ifdef CONFIG_EBU_ADDSEL1
 206         (*DANUBE_EBU_ADDSEL1) = CONFIG_EBU_ADDSEL1;
 207 #endif
 208 #ifdef CONFIG_EBU_ADDSEL2
 209         (*DANUBE_EBU_ADDSEL2) = CONFIG_EBU_ADDSEL2;
 210 #endif
 211 #ifdef CONFIG_EBU_ADDSEL3
 212         (*DANUBE_EBU_ADDSEL3) = CONFIG_EBU_ADDSEL3;
 213 #endif
 214 #ifdef CONFIG_EBU_BUSCON0
 215         (*DANUBE_EBU_BUSCON0) = CONFIG_EBU_BUSCON0;
 216 #endif
 217 #ifdef CONFIG_EBU_BUSCON1
 218         (*DANUBE_EBU_BUSCON1) = CONFIG_EBU_BUSCON1;
 219 #endif
 220 #ifdef CONFIG_EBU_BUSCON2
 221         (*DANUBE_EBU_BUSCON2) = CONFIG_EBU_BUSCON2;
 222 #endif
 223 #ifdef CONFIG_EBU_BUSCON3
 224         (*DANUBE_EBU_BUSCON3) = CONFIG_EBU_BUSCON3;
 225 #endif
 226
 227         return 0;
 228 }
 229 #endif /* CONFIG_SKIP_LOWLEVEL_INIT */
 230
 231 #ifdef CONFIG_EXTRA_SWITCH
 232 static int external_switch_init(void)
 233 {
 234         unsigned short chipid0=0xdead, chipid1=0xbeef;
 235         static char * const name = "lq_cpe_eth";
 236
 237 #ifdef CONFIG_SWITCH_PORT0
 238         *DANUBE_GPIO_P0_ALTSEL0 &= ~(1<<CONFIG_SWITCH_PIN);
 239         *DANUBE_GPIO_P0_ALTSEL1 &= ~(1<<CONFIG_SWITCH_PIN);
 240         *DANUBE_GPIO_P0_OD |= (1<<CONFIG_SWITCH_PIN);
 241         *DANUBE_GPIO_P0_DIR |= (1<<CONFIG_SWITCH_PIN);
 242         *DANUBE_GPIO_P0_OUT |= (1<<CONFIG_SWITCH_PIN);
 243 #elif defined(CONFIG_SWITCH_PORT1)
 244         *DANUBE_GPIO_P1_ALTSEL0 &= ~(1<<CONFIG_SWITCH_PIN);
 245         *DANUBE_GPIO_P1_ALTSEL1 &= ~(1<<CONFIG_SWITCH_PIN);
 246         *DANUBE_GPIO_P1_OD |= (1<<CONFIG_SWITCH_PIN);
 247         *DANUBE_GPIO_P1_DIR |= (1<<CONFIG_SWITCH_PIN);
 248         *DANUBE_GPIO_P1_OUT |= (1<<CONFIG_SWITCH_PIN);
 249 #endif
 250 #ifdef CLK_OUT2_25MHZ
 251         *DANUBE_GPIO_P0_DIR=0x0000ae78;
 252         *DANUBE_GPIO_P0_ALTSEL0=0x00008078;
 253         //joelin for Mii-1       *DANUBE_GPIO_P0_ALTSEL1=0x80000080;
 254         *DANUBE_GPIO_P0_ALTSEL1=0x80000000; //joelin for Mii-1
 255         *DANUBE_CGU_IFCCR=0x00400010;
 256         *DANUBE_GPIO_P0_OD=0x0000ae78;
 257 #endif
 258
 259         /* earlier no valid response is available, at least on Twinpass & Tantos @ 111MHz, M4530 platform */
 260         udelay(100000);
 261
 262         debug("\nsearching for Samurai switch ... ");
 263         if ( (miiphy_read(name, PHYADDR(SAMURAI_ID_REG0), &chipid0)==0) &&
 264              (miiphy_read(name, PHYADDR(SAMURAI_ID_REG1), &chipid1)==0) ) {
 265                 if (((chipid0 & 0xFFF0) == ID_SAMURAI_0) &&
 266                     ((chipid1 & 0x000F) == ID_SAMURAI_1)) {
 267                         debug("found");
 268
 269                         /* enable "Crossover Auto Detect" + defaults */
 270                         /* P0 */
 271                         miiphy_write(name, PHYADDR(0x01), 0x840F);
 272                         /* P1 */
 273                         miiphy_write(name, PHYADDR(0x03), 0x840F);
 274                         /* P2 */
 275                         miiphy_write(name, PHYADDR(0x05), 0x840F);
 276                         /* P3 */
 277                         miiphy_write(name, PHYADDR(0x07), 0x840F);
 278                         /* P4 */
 279                         miiphy_write(name, PHYADDR(0x08), 0x840F);
 280                         /* P5 */
 281                         miiphy_write(name, PHYADDR(0x09), 0x840F);
 282                         /* System Control 4: CPU on port 1 and other */
 283                         miiphy_write(name, PHYADDR(0x12), 0x3602);
 284                         #ifdef CLK_OUT2_25MHZ
 285                         /* Bandwidth Control Enable Register: enable */
 286                         miiphy_write(name, PHYADDR(0x33), 0x4000);
 287                         #endif
 288                 }
 289         }
 290
 291         debug("\nsearching for TANTOS switch ... ");
 292         if (miiphy_read(name, PHYADDR(0x101), &chipid0) == 0) {
 293                 if (chipid0 == ID_TANTOS) {
 294                         debug("found");
 295
 296                         /* P5 Basic Control: Force Link Up */
 297                         miiphy_write(name, PHYADDR(0xA1), 0x0004);
 298                         /* P6 Basic Control: Force Link Up */
 299                         miiphy_write(name, PHYADDR(0xC1), 0x0004);
 300                         /* RGMII/MII Port Control (P4/5/6) */
 301                         miiphy_write(name, PHYADDR(0xF5), 0x0773);
 302
 303                         /* Software workaround. */
 304                         /* PHY reset from P0 to P4. */
 305
 306                         /* set data for indirect write */
 307                         miiphy_write(name, PHYADDR(0x121), 0x8000);
 308
 309                         /* P0 */
 310                         miiphy_write(name, PHYADDR(0x120), 0x0400);
 311                         udelay(1000);
 312                         /* P1 */
 313                         miiphy_write(name, PHYADDR(0x120), 0x0420);
 314                         udelay(1000);
 315                         /* P2 */
 316                         miiphy_write(name, PHYADDR(0x120), 0x0440);
 317                         udelay(1000);
 318                         /* P3 */
 319                         miiphy_write(name, PHYADDR(0x120), 0x0460);
 320                         udelay(1000);
 321                         /* P4 */
 322                         miiphy_write(name, PHYADDR(0x120), 0x0480);
 323                         udelay(1000);
 324                 }
 325         }
 326         debug("\n");
 327
 328         return 0;
 329 }
 330 #endif /* CONFIG_EXTRA_SWITCH */
 331
 332 int board_gpio_init(void)
 333 {
 334 #ifdef CONFIG_BUTTON_PORT0
 335         *DANUBE_GPIO_P0_ALTSEL0 &= ~(1<<CONFIG_BUTTON_PIN);
 336         *DANUBE_GPIO_P0_ALTSEL1 &= ~(1<<CONFIG_BUTTON_PIN);
 337         *DANUBE_GPIO_P0_DIR &= ~(1<<CONFIG_BUTTON_PIN);
 338         if(!!(*DANUBE_GPIO_P0_IN & (1<<CONFIG_BUTTON_PIN)) == CONFIG_BUTTON_LEVEL)
 339         {
 340                 printf("button is pressed\n");
 341                 setenv("bootdelay", "0");
 342                 setenv("bootcmd", "httpd");
 343         }
 344 #elif defined(CONFIG_BUTTON_PORT1)
 345         *DANUBE_GPIO_P1_ALTSEL0 &= ~(1<<CONFIG_BUTTON_PIN);
 346         *DANUBE_GPIO_P1_ALTSEL1 &= ~(1<<CONFIG_BUTTON_PIN);
 347         *DANUBE_GPIO_P1_DIR &= ~(1<<CONFIG_BUTTON_PIN);
 348         if(!!(*DANUBE_GPIO_P1_IN & (1<<CONFIG_BUTTON_PIN)) == CONFIG_BUTTON_LEVEL)
 349         {
 350                 printf("button is pressed\n");
 351                 setenv("bootdelay", "0");
 352                 setenv("bootcmd", "httpd");
 353         }
 354 #endif
 355 }
 356
 357 int board_eth_init(bd_t *bis)
 358 {
 359
 360         board_gpio_init();
 361
 362 #if defined(CONFIG_IFX_ETOP)
 363
 364         *DANUBE_PMU_PWDCR &= 0xFFFFEFDF;
 365         *DANUBE_PMU_PWDCR &=~(1<<DANUBE_PMU_DMA_SHIFT);/*enable DMA from PMU*/
 366
 367         if (lq_eth_initialize(bis)<0)
 368                 return -1;
 369
 370         *DANUBE_RCU_RST_REQ |=1;
 371         udelay(200000);
 372         *DANUBE_RCU_RST_REQ &=(unsigned long)~1;
 373         udelay(1000);
 374
 375 #ifdef CONFIG_EXTRA_SWITCH
 376         if (external_switch_init()<0)
 377                 return -1;
 378 #endif /* CONFIG_EXTRA_SWITCH */
 379 #endif /* CONFIG_IFX_ETOP */
 380
 381         return 0;
 382 }
 383
 384 #if defined(CONFIG_CMD_HTTPD)
 385 int do_http_upgrade(const unsigned char *data, const ulong size)
 386 {
 387         char buf[128];
 388
 389         if(getenv ("ram_addr") == NULL)
 390                 return -1;
 391         if(getenv ("kernel_addr") == NULL)
 392                 return -1;
 393         /* check the image */
 394         if(run_command("imi ${ram_addr}", 0) < 0) {
 395                 return -1;
 396         }
 397         /* write the image to the flash */
 398         puts("http ugrade ...\n");
 399         sprintf(buf, "era ${kernel_addr} +0x%x; cp.b ${ram_addr} ${kernel_addr} 0x%x", size, size);
 400         return run_command(buf, 0);
 401 }
 402
 403 int do_http_progress(const int state)
 404 {
 405         /* toggle LED's here */
 406         switch(state) {
 407                 case HTTP_PROGRESS_START:
 408                 puts("http start\n");
 409                 break;
 410                 case HTTP_PROGRESS_TIMEOUT:
 411                 puts(".");
 412                 break;
 413                 case HTTP_PROGRESS_UPLOAD_READY:
 414                 puts("http upload ready\n");
 415                 break;
 416                 case HTTP_PROGRESS_UGRADE_READY:
 417                 puts("http ugrade ready\n");
 418                 break;
 419                 case HTTP_PROGRESS_UGRADE_FAILED:
 420                 puts("http ugrade failed\n");
 421                 break;
 422         }
 423         return 0;
 424 }
 425
 426 unsigned long do_http_tmp_address(void)
 427 {
 428         char *s = getenv ("ram_addr");
 429         if (s) {
 430                 ulong tmp = simple_strtoul (s, NULL, 16);
 431                 return tmp;
 432         }
 433         return 0 /*0x80a00000*/;
 434 }
 435
 436 #endif