target/linux/ramips/patches-3.8/0039-MIPS-ralink-add-memory-definition-for-RT305x.patch

   1 From 7d0aa01494353532bbdc644469ef2a06ee089f3e Mon Sep 17 00:00:00 2001
   2 From: John Crispin <blogic@openwrt.org>
   3 Date: Sat, 13 Apr 2013 15:13:40 +0200
   4 Subject: [PATCH 39/79] MIPS: ralink: add memory definition for RT305x
   5
   6 Populate struct soc_info with the data that describes our RAM window.
   7
   8 As memory detection fails on RT5350 we read the amount of available memory
   9 from the system controller.
  10
  11 Signed-off-by: John Crispin <blogic@openwrt.org>
  12 Patchwork: http://patchwork.linux-mips.org/patch/5180/
  13 ---
  14  arch/mips/include/asm/mach-ralink/rt305x.h |    6 ++++
  15  arch/mips/ralink/rt305x.c                  |   45 ++++++++++++++++++++++++++++
  16  2 files changed, 51 insertions(+)
  17
  18 diff --git a/arch/mips/include/asm/mach-ralink/rt305x.h b/arch/mips/include/asm/mach-ralink/rt305x.h
  19 index 80cda8a..069bf37 100644
  20 --- a/arch/mips/include/asm/mach-ralink/rt305x.h
  21 +++ b/arch/mips/include/asm/mach-ralink/rt305x.h
  22 @@ -157,4 +157,10 @@ static inline int soc_is_rt5350(void)
  23  #define RT3352_RSTCTRL_UDEV            BIT(25)
  24  #define RT3352_SYSCFG1_USB0_HOST_MODE  BIT(10)
  25
  26 +#define RT305X_SDRAM_BASE              0x00000000
  27 +#define RT305X_MEM_SIZE_MIN            2
  28 +#define RT305X_MEM_SIZE_MAX            64
  29 +#define RT3352_MEM_SIZE_MIN            2
  30 +#define RT3352_MEM_SIZE_MAX            256
  31 +
  32  #endif
  33 diff --git a/arch/mips/ralink/rt305x.c b/arch/mips/ralink/rt305x.c
  34 index 6aa3cb1..ca7ee3a 100644
  35 --- a/arch/mips/ralink/rt305x.c
  36 +++ b/arch/mips/ralink/rt305x.c
  37 @@ -122,6 +122,40 @@ struct ralink_pinmux rt_gpio_pinmux = {
  38         .wdt_reset = rt305x_wdt_reset,
  39  };
  40
  41 +static unsigned long rt5350_get_mem_size(void)
  42 +{
  43 +       void __iomem *sysc = (void __iomem *) KSEG1ADDR(RT305X_SYSC_BASE);
  44 +       unsigned long ret;
  45 +       u32 t;
  46 +
  47 +       t = __raw_readl(sysc + SYSC_REG_SYSTEM_CONFIG);
  48 +       t = (t >> RT5350_SYSCFG0_DRAM_SIZE_SHIFT) &
  49 +               RT5350_SYSCFG0_DRAM_SIZE_MASK;
  50 +
  51 +       switch (t) {
  52 +       case RT5350_SYSCFG0_DRAM_SIZE_2M:
  53 +               ret = 2;
  54 +               break;
  55 +       case RT5350_SYSCFG0_DRAM_SIZE_8M:
  56 +               ret = 8;
  57 +               break;
  58 +       case RT5350_SYSCFG0_DRAM_SIZE_16M:
  59 +               ret = 16;
  60 +               break;
  61 +       case RT5350_SYSCFG0_DRAM_SIZE_32M:
  62 +               ret = 32;
  63 +               break;
  64 +       case RT5350_SYSCFG0_DRAM_SIZE_64M:
  65 +               ret = 64;
  66 +               break;
  67 +       default:
  68 +               panic("rt5350: invalid DRAM size: %u", t);
  69 +               break;
  70 +       }
  71 +
  72 +       return ret;
  73 +}
  74 +
  75  void __init ralink_clk_init(void)
  76  {
  77         unsigned long cpu_rate, sys_rate, wdt_rate, uart_rate;
  78 @@ -252,4 +286,15 @@ void prom_soc_init(struct ralink_soc_info *soc_info)
  79                 name,
  80                 (id >> CHIP_ID_ID_SHIFT) & CHIP_ID_ID_MASK,
  81                 (id & CHIP_ID_REV_MASK));
  82 +
  83 +       soc_info->mem_base = RT305X_SDRAM_BASE;
  84 +       if (soc_is_rt5350()) {
  85 +               soc_info->mem_size = rt5350_get_mem_size();
  86 +       } else if (soc_is_rt305x() || soc_is_rt3350()) {
  87 +               soc_info->mem_size_min = RT305X_MEM_SIZE_MIN;
  88 +               soc_info->mem_size_max = RT305X_MEM_SIZE_MAX;
  89 +       } else if (soc_is_rt3352()) {
  90 +               soc_info->mem_size_min = RT3352_MEM_SIZE_MIN;
  91 +               soc_info->mem_size_max = RT3352_MEM_SIZE_MAX;
  92 +       }
  93  }
  94 --
  95 1.7.10.4
  96