ralink: update patches
authorblogic <blogic@3c298f89-4303-0410-b956-a3cf2f4a3e73>
Sun, 23 Jun 2013 15:50:49 +0000 (15:50 +0000)
committerblogic <blogic@3c298f89-4303-0410-b956-a3cf2f4a3e73>
Sun, 23 Jun 2013 15:50:49 +0000 (15:50 +0000)
Signed-off-by: John Crispin <blogic@openwrt.org>
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@37016 3c298f89-4303-0410-b956-a3cf2f4a3e73

242 files changed:
target/linux/ramips/Makefile
target/linux/ramips/dts/DIR-645.dts
target/linux/ramips/dts/F5D8235_V1.dts
target/linux/ramips/dts/FREESTATION5.dts
target/linux/ramips/dts/MPRA2.dts
target/linux/ramips/dts/MT7620a.dts [new file with mode: 0644]
target/linux/ramips/dts/OMNI-EMB-HPM.dts
target/linux/ramips/dts/RT-N15.dts
target/linux/ramips/dts/RTN56U.dts
target/linux/ramips/dts/TEW-691GR.dts
target/linux/ramips/dts/TEW-692GR.dts
target/linux/ramips/dts/WLI-TX4-AG300N.dts
target/linux/ramips/dts/WR6202.dts
target/linux/ramips/dts/mt7620.dtsi [deleted file]
target/linux/ramips/dts/mt7620a.dtsi [new file with mode: 0644]
target/linux/ramips/dts/mt7620a_mt7610e_eval.dts [new file with mode: 0644]
target/linux/ramips/dts/rt2880.dtsi
target/linux/ramips/dts/rt3050.dtsi
target/linux/ramips/dts/rt3352.dtsi
target/linux/ramips/dts/rt3883.dtsi
target/linux/ramips/dts/rt5350.dtsi
target/linux/ramips/image/Makefile
target/linux/ramips/image/lzma-loader/Makefile [new file with mode: 0644]
target/linux/ramips/image/lzma-loader/src/LzmaDecode.c [new file with mode: 0644]
target/linux/ramips/image/lzma-loader/src/LzmaDecode.h [new file with mode: 0644]
target/linux/ramips/image/lzma-loader/src/LzmaTypes.h [new file with mode: 0644]
target/linux/ramips/image/lzma-loader/src/Makefile [new file with mode: 0644]
target/linux/ramips/image/lzma-loader/src/board-ralink.c [new file with mode: 0644]
target/linux/ramips/image/lzma-loader/src/cache.c [new file with mode: 0644]
target/linux/ramips/image/lzma-loader/src/cache.h [new file with mode: 0644]
target/linux/ramips/image/lzma-loader/src/cacheops.h [new file with mode: 0644]
target/linux/ramips/image/lzma-loader/src/config.h [new file with mode: 0644]
target/linux/ramips/image/lzma-loader/src/cp0regdef.h [new file with mode: 0644]
target/linux/ramips/image/lzma-loader/src/head.S [new file with mode: 0644]
target/linux/ramips/image/lzma-loader/src/lantiq.mk [new file with mode: 0644]
target/linux/ramips/image/lzma-loader/src/loader.c [new file with mode: 0644]
target/linux/ramips/image/lzma-loader/src/loader.lds [new file with mode: 0644]
target/linux/ramips/image/lzma-loader/src/loader2.lds [new file with mode: 0644]
target/linux/ramips/image/lzma-loader/src/lzma-data.lds [new file with mode: 0644]
target/linux/ramips/image/lzma-loader/src/printf.c [new file with mode: 0644]
target/linux/ramips/image/lzma-loader/src/printf.h [new file with mode: 0644]
target/linux/ramips/image/lzma-loader/src/ralink.mk [new file with mode: 0644]
target/linux/ramips/mt7620a/config-3.8 [new file with mode: 0644]
target/linux/ramips/mt7620a/config-3.9 [new file with mode: 0644]
target/linux/ramips/mt7620a/profiles/00-default.mk [new file with mode: 0644]
target/linux/ramips/mt7620a/target.mk [new file with mode: 0644]
target/linux/ramips/patches-3.8/0001-MIPS-ralink-adds-include-files.patch
target/linux/ramips/patches-3.8/0002-MIPS-ralink-adds-irq-code.patch
target/linux/ramips/patches-3.8/0003-MIPS-ralink-adds-reset-code.patch
target/linux/ramips/patches-3.8/0004-MIPS-ralink-adds-prom-and-cmdline-code.patch
target/linux/ramips/patches-3.8/0005-MIPS-ralink-adds-clkdev-code.patch
target/linux/ramips/patches-3.8/0006-MIPS-ralink-adds-OF-code.patch
target/linux/ramips/patches-3.8/0007-MIPS-ralink-adds-early_printk-support.patch
target/linux/ramips/patches-3.8/0008-MIPS-ralink-adds-support-for-RT305x-SoC-family.patch
target/linux/ramips/patches-3.8/0009-MIPS-ralink-adds-rt305x-devicetree.patch
target/linux/ramips/patches-3.8/0010-MIPS-ralink-adds-Kbuild-files.patch
target/linux/ramips/patches-3.8/0011-MIPS-ralink-adds-default-config-file.patch
target/linux/ramips/patches-3.8/0012-Document-devicetree-add-OF-documents-for-MIPS-interr.patch
target/linux/ramips/patches-3.8/0013-MIPS-add-irqdomain-support-for-the-CPU-IRQ-controlle.patch
target/linux/ramips/patches-3.8/0014-MIPS-ralink-add-CPU-interrupt-controller-to-of_irq_i.patch
target/linux/ramips/patches-3.8/0015-serial-ralink-adds-support-for-the-serial-core-found.patch
target/linux/ramips/patches-3.8/0016-MIPS-move-mips_-set-get-_machine_name-to-a-more-gene.patch [new file with mode: 0644]
target/linux/ramips/patches-3.8/0017-MIPS-ralink-add-PCI-IRQ-handling.patch [new file with mode: 0644]
target/linux/ramips/patches-3.8/0018-MIPS-ralink-add-RT3352-register-defines.patch [new file with mode: 0644]
target/linux/ramips/patches-3.8/0019-MIPS-ralink-fix-RT305x-clock-setup.patch [new file with mode: 0644]
target/linux/ramips/patches-3.8/0020-MIPS-ralink-add-missing-comment-in-irq-driver.patch [new file with mode: 0644]
target/linux/ramips/patches-3.8/0021-MIPS-ralink-add-RT5350-sdram-register-defines.patch [new file with mode: 0644]
target/linux/ramips/patches-3.8/0022-MIPS-ralink-make-early_printk-work-on-RT2880.patch [new file with mode: 0644]
target/linux/ramips/patches-3.8/0023-MIPS-ralink-rename-gpio_pinmux-to-rt_gpio_pinmux.patch [new file with mode: 0644]
target/linux/ramips/patches-3.8/0024-MIPS-ralink-make-the-RT305x-pinmuxing-structure-stat.patch [new file with mode: 0644]
target/linux/ramips/patches-3.8/0025-MIPS-ralink-add-pci-group-to-struct-ralink_pinmux.patch [new file with mode: 0644]
target/linux/ramips/patches-3.8/0026-MIPS-ralink-add-uart-mask-to-struct-ralink_pinmux.patch [new file with mode: 0644]
target/linux/ramips/patches-3.8/0027-MIPS-ralink-adds-support-for-RT2880-SoC-family.patch [new file with mode: 0644]
target/linux/ramips/patches-3.8/0028-MIPS-ralink-adds-support-for-RT3883-SoC-family.patch [new file with mode: 0644]
target/linux/ramips/patches-3.8/0029-MIPS-ralink-adds-support-for-MT7620-SoC-family.patch [new file with mode: 0644]
target/linux/ramips/patches-3.8/0030-MIPS-ralink-add-cpu-feature-overrides.h.patch [new file with mode: 0644]
target/linux/ramips/patches-3.8/0031-DT-add-vendor-prefixes-for-Ralink.patch [new file with mode: 0644]
target/linux/ramips/patches-3.8/0032-DT-add-documentation-for-the-Ralink-MIPS-SoCs.patch [new file with mode: 0644]
target/linux/ramips/patches-3.8/0033-DT-MIPS-ralink-clean-up-RT3050-dtsi-and-dts-file.patch [new file with mode: 0644]
target/linux/ramips/patches-3.8/0034-DT-MIPS-ralink-add-RT2880-dts-files.patch [new file with mode: 0644]
target/linux/ramips/patches-3.8/0035-DT-MIPS-ralink-add-RT3883-dts-files.patch [new file with mode: 0644]
target/linux/ramips/patches-3.8/0036-DT-MIPS-ralink-add-MT7620A-dts-files.patch [new file with mode: 0644]
target/linux/ramips/patches-3.8/0037-MIPS-add-detect_memory_region.patch [new file with mode: 0644]
target/linux/ramips/patches-3.8/0038-MIPS-ralink-add-memory-definition-to-struct-ralink_s.patch [new file with mode: 0644]
target/linux/ramips/patches-3.8/0039-MIPS-ralink-add-memory-definition-for-RT305x.patch [new file with mode: 0644]
target/linux/ramips/patches-3.8/0040-MIPS-ralink-add-memory-definition-for-RT2880.patch [new file with mode: 0644]
target/linux/ramips/patches-3.8/0041-MIPS-ralink-add-memory-definition-for-RT3883.patch [new file with mode: 0644]
target/linux/ramips/patches-3.8/0042-MIPS-ralink-add-memory-definition-for-MT7620.patch [new file with mode: 0644]
target/linux/ramips/patches-3.8/0043-MIPS-ralink-make-use-of-the-new-memory-detection-cod.patch [new file with mode: 0644]
target/linux/ramips/patches-3.8/0044-MIPS-ralink-upstream-v3.10.patch [new file with mode: 0644]
target/linux/ramips/patches-3.8/0045-MIPS-ralink-add-pinmux-driver.patch [new file with mode: 0644]
target/linux/ramips/patches-3.8/0046-MIPS-ralink-add-support-for-periodic-timer-irq.patch [new file with mode: 0644]
target/linux/ramips/patches-3.8/0047-MIPS-ralink-add-rt_sysc_m32-helper.patch [new file with mode: 0644]
target/linux/ramips/patches-3.8/0048-MIPS-ralink-make-mt7620-ram-detect-verbose.patch [new file with mode: 0644]
target/linux/ramips/patches-3.8/0049-MIPS-ralink-add-verbose-pmu-info.patch [new file with mode: 0644]
target/linux/ramips/patches-3.8/0050-MIPS-ralink-adds-a-bootrom-dumper-module.patch [new file with mode: 0644]
target/linux/ramips/patches-3.8/0051-MIPS-ralink-add-missing-SZ_1M-multiplier.patch [new file with mode: 0644]
target/linux/ramips/patches-3.8/0052-MIPS-use-set_mode-to-enable-disable-the-cevt-r4k-irq.patch [new file with mode: 0644]
target/linux/ramips/patches-3.8/0053-MIPS-ralink-add-illegal-access-driver.patch [new file with mode: 0644]
target/linux/ramips/patches-3.8/0054-MIPS-ralink-workaround-DTB-memory-issue.patch [new file with mode: 0644]
target/linux/ramips/patches-3.8/0055-MIPS-ralink-add-spi-clock-definition-to-mt7620a.patch [new file with mode: 0644]
target/linux/ramips/patches-3.8/0056-MIPS-ralink-DTS-file-updates.patch [new file with mode: 0644]
target/linux/ramips/patches-3.8/0057-GPIO-MIPS-ralink-adds-ralink-gpio-support.patch [new file with mode: 0644]
target/linux/ramips/patches-3.8/0058-SPI-ralink-add-Ralink-SoC-spi-driver.patch [new file with mode: 0644]
target/linux/ramips/patches-3.8/0059-serial-of-allow-au1x00-and-rt288x-to-load-from-OF.patch [new file with mode: 0644]
target/linux/ramips/patches-3.8/0060-serial-ralink-adds-mt7620-serial.patch [new file with mode: 0644]
target/linux/ramips/patches-3.8/0061-DMA-MIPS-ralink-add-dmaengine-driver.patch [new file with mode: 0644]
target/linux/ramips/patches-3.8/0062-PCI-MIPS-adds-rt2880-pci-support.patch [new file with mode: 0644]
target/linux/ramips/patches-3.8/0063-PCI-MIPS-adds-rt3883-pci-support.patch [new file with mode: 0644]
target/linux/ramips/patches-3.8/0064-PCI-MIPS-adds-mt7620a-pcie-driver.patch [new file with mode: 0644]
target/linux/ramips/patches-3.8/0065-watchdog-adds-ralink-wdt.patch [new file with mode: 0644]
target/linux/ramips/patches-3.8/0066-i2c-MIPS-adds-ralink-I2C-driver.patch [new file with mode: 0644]
target/linux/ramips/patches-3.8/0067-reset-Add-reset-controller-API.patch [new file with mode: 0644]
target/linux/ramips/patches-3.8/0068-reset-MIPS-ralink-add-core-device-reset-wrapper.patch [new file with mode: 0644]
target/linux/ramips/patches-3.8/0069-NET-add-of_get_mac_address_mtd.patch [new file with mode: 0644]
target/linux/ramips/patches-3.8/0070-NET-multi-phy-support.patch [new file with mode: 0644]
target/linux/ramips/patches-3.8/0072-NET-MIPS-add-ralink-SoC-ethernet-driver.patch [new file with mode: 0644]
target/linux/ramips/patches-3.8/0073-USB-phy-add-ralink-SoC-driver.patch [new file with mode: 0644]
target/linux/ramips/patches-3.8/0074-USB-MIPS-ralink-fix-usb-issue-on-mt7620.patch [new file with mode: 0644]
target/linux/ramips/patches-3.8/0075-Kbuild-add-missing-space.patch [new file with mode: 0644]
target/linux/ramips/patches-3.8/0076-mmc-MIPS-ralink-add-sdhci-for-mt7620a-SoC.patch [new file with mode: 0644]
target/linux/ramips/patches-3.8/0077-clocksource-add-common-of_clksrc_init-function.patch [new file with mode: 0644]
target/linux/ramips/patches-3.8/0078-clocksource-make-clocksource_of_init-pass-a-device_n.patch [new file with mode: 0644]
target/linux/ramips/patches-3.8/0079-clocksource-MIPS-ralink-add-support-for-systick-time.patch [new file with mode: 0644]
target/linux/ramips/patches-3.8/0080-MIPS-add-ohci-ehci-support.patch [new file with mode: 0644]
target/linux/ramips/patches-3.8/0100-MIPS-move-mips_-set-get-_machine_name-to-a-more-gene.patch [deleted file]
target/linux/ramips/patches-3.8/0101-MIPS-ralink-add-PCI-IRQ-handling.patch [deleted file]
target/linux/ramips/patches-3.8/0102-MIPS-ralink-add-RT3352-register-defines.patch [deleted file]
target/linux/ramips/patches-3.8/0103-MIPS-ralink-fix-RT305x-clock-setup.patch [deleted file]
target/linux/ramips/patches-3.8/0104-MIPS-ralink-add-missing-comment-in-irq-driver.patch [deleted file]
target/linux/ramips/patches-3.8/0105-MIPS-ralink-add-RT5350-sdram-register-defines.patch [deleted file]
target/linux/ramips/patches-3.8/0106-MIPS-ralink-make-early_printk-work-on-RT2880.patch [deleted file]
target/linux/ramips/patches-3.8/0107-MIPS-ralink-rename-gpio_pinmux-to-rt_gpio_pinmux.patch [deleted file]
target/linux/ramips/patches-3.8/0108-MIPS-ralink-make-the-RT305x-pinmuxing-structure-stat.patch [deleted file]
target/linux/ramips/patches-3.8/0109-MIPS-ralink-add-pci-group-to-struct-ralink_pinmux.patch [deleted file]
target/linux/ramips/patches-3.8/0110-MIPS-ralink-add-uart-mask-to-struct-ralink_pinmux.patch [deleted file]
target/linux/ramips/patches-3.8/0111-MIPS-ralink-adds-support-for-RT2880-SoC-family.patch [deleted file]
target/linux/ramips/patches-3.8/0112-MIPS-ralink-adds-support-for-RT3883-SoC-family.patch [deleted file]
target/linux/ramips/patches-3.8/0113-MIPS-ralink-adds-support-for-MT7620-SoC-family.patch [deleted file]
target/linux/ramips/patches-3.8/0114-MIPS-ralink-add-cpu-feature-overrides.h.patch [deleted file]
target/linux/ramips/patches-3.8/0115-DT-add-vendor-prefixes-for-Ralink.patch [deleted file]
target/linux/ramips/patches-3.8/0116-DT-add-documentation-for-the-Ralink-MIPS-SoCs.patch [deleted file]
target/linux/ramips/patches-3.8/0117-DT-MIPS-ralink-clean-up-RT3050-dtsi-and-dts-file.patch [deleted file]
target/linux/ramips/patches-3.8/0118-DT-MIPS-ralink-add-RT2880-dts-files.patch [deleted file]
target/linux/ramips/patches-3.8/0119-DT-MIPS-ralink-add-RT3883-dts-files.patch [deleted file]
target/linux/ramips/patches-3.8/0120-DT-MIPS-ralink-add-MT7620A-dts-files.patch [deleted file]
target/linux/ramips/patches-3.8/0121-MIPS-add-detect_memory_region.patch [deleted file]
target/linux/ramips/patches-3.8/0122-MIPS-ralink-add-memory-definition-to-struct-ralink_s.patch [deleted file]
target/linux/ramips/patches-3.8/0123-MIPS-ralink-add-memory-definition-for-RT305x.patch [deleted file]
target/linux/ramips/patches-3.8/0124-MIPS-ralink-add-memory-definition-for-RT2880.patch [deleted file]
target/linux/ramips/patches-3.8/0125-MIPS-ralink-add-memory-definition-for-RT3883.patch [deleted file]
target/linux/ramips/patches-3.8/0126-MIPS-ralink-add-memory-definition-for-MT7620.patch [deleted file]
target/linux/ramips/patches-3.8/0127-MIPS-ralink-make-use-of-the-new-memory-detection-cod.patch [deleted file]
target/linux/ramips/patches-3.8/0128-MIPS-ralink-add-pinmux-driver.patch [deleted file]
target/linux/ramips/patches-3.8/0129-MIPS-ralink-add-support-for-periodic-timer-irq.patch [deleted file]
target/linux/ramips/patches-3.8/0130-GPIO-MIPS-ralink-adds-ralink-gpio-support.patch [deleted file]
target/linux/ramips/patches-3.8/0131-SPI-ralink-add-Ralink-SoC-spi-driver.patch [deleted file]
target/linux/ramips/patches-3.8/0132-serial-of-allow-au1x00-and-rt288x-to-load-from-OF.patch [deleted file]
target/linux/ramips/patches-3.8/0133-serial-ralink-adds-mt7620-serial.patch [deleted file]
target/linux/ramips/patches-3.8/0134-PCI-MIPS-adds-rt2880-pci-support.patch [deleted file]
target/linux/ramips/patches-3.8/0135-PCI-MIPS-adds-rt3883-pci-support.patch [deleted file]
target/linux/ramips/patches-3.8/0136-NET-MIPS-add-ralink-SoC-ethernet-driver.patch [deleted file]
target/linux/ramips/patches-3.8/0137-watchdog-adds-ralink-wdt.patch [deleted file]
target/linux/ramips/patches-3.8/0201-owrt-OF-NET-add-of_get_mac_address_mtd.patch [deleted file]
target/linux/ramips/patches-3.8/0203-owrt-OF-USB-add-OF-binding-for-ehci-and-ohci-platfor.patch [deleted file]
target/linux/ramips/patches-3.8/0204-owrt-MIPS-ralink-add-usb-platform-support.patch [deleted file]
target/linux/ramips/patches-3.9/0100-MIPS-move-mips_-set-get-_machine_name-to-a-more-gene.patch [new file with mode: 0644]
target/linux/ramips/patches-3.9/0101-MIPS-ralink-add-PCI-IRQ-handling.patch [new file with mode: 0644]
target/linux/ramips/patches-3.9/0102-MIPS-ralink-add-RT3352-register-defines.patch [new file with mode: 0644]
target/linux/ramips/patches-3.9/0103-MIPS-ralink-fix-RT305x-clock-setup.patch [new file with mode: 0644]
target/linux/ramips/patches-3.9/0104-MIPS-ralink-add-missing-comment-in-irq-driver.patch [new file with mode: 0644]
target/linux/ramips/patches-3.9/0105-MIPS-ralink-add-RT5350-sdram-register-defines.patch [new file with mode: 0644]
target/linux/ramips/patches-3.9/0106-MIPS-ralink-make-early_printk-work-on-RT2880.patch [new file with mode: 0644]
target/linux/ramips/patches-3.9/0107-MIPS-ralink-rename-gpio_pinmux-to-rt_gpio_pinmux.patch [new file with mode: 0644]
target/linux/ramips/patches-3.9/0108-MIPS-ralink-make-the-RT305x-pinmuxing-structure-stat.patch [new file with mode: 0644]
target/linux/ramips/patches-3.9/0109-MIPS-ralink-add-pci-group-to-struct-ralink_pinmux.patch [new file with mode: 0644]
target/linux/ramips/patches-3.9/0110-MIPS-ralink-add-uart-mask-to-struct-ralink_pinmux.patch [new file with mode: 0644]
target/linux/ramips/patches-3.9/0111-MIPS-ralink-adds-support-for-RT2880-SoC-family.patch [new file with mode: 0644]
target/linux/ramips/patches-3.9/0112-MIPS-ralink-adds-support-for-RT3883-SoC-family.patch [new file with mode: 0644]
target/linux/ramips/patches-3.9/0113-MIPS-ralink-adds-support-for-MT7620-SoC-family.patch [new file with mode: 0644]
target/linux/ramips/patches-3.9/0114-MIPS-ralink-add-cpu-feature-overrides.h.patch [new file with mode: 0644]
target/linux/ramips/patches-3.9/0115-DT-add-vendor-prefixes-for-Ralink.patch [new file with mode: 0644]
target/linux/ramips/patches-3.9/0116-DT-add-documentation-for-the-Ralink-MIPS-SoCs.patch [new file with mode: 0644]
target/linux/ramips/patches-3.9/0117-DT-MIPS-ralink-clean-up-RT3050-dtsi-and-dts-file.patch [new file with mode: 0644]
target/linux/ramips/patches-3.9/0118-DT-MIPS-ralink-add-RT2880-dts-files.patch [new file with mode: 0644]
target/linux/ramips/patches-3.9/0119-DT-MIPS-ralink-add-RT3883-dts-files.patch [new file with mode: 0644]
target/linux/ramips/patches-3.9/0120-DT-MIPS-ralink-add-MT7620A-dts-files.patch [new file with mode: 0644]
target/linux/ramips/patches-3.9/0121-MIPS-add-detect_memory_region.patch [new file with mode: 0644]
target/linux/ramips/patches-3.9/0122-MIPS-ralink-add-memory-definition-to-struct-ralink_s.patch [new file with mode: 0644]
target/linux/ramips/patches-3.9/0123-MIPS-ralink-add-memory-definition-for-RT305x.patch [new file with mode: 0644]
target/linux/ramips/patches-3.9/0124-MIPS-ralink-add-memory-definition-for-RT2880.patch [new file with mode: 0644]
target/linux/ramips/patches-3.9/0125-MIPS-ralink-add-memory-definition-for-RT3883.patch [new file with mode: 0644]
target/linux/ramips/patches-3.9/0126-MIPS-ralink-add-memory-definition-for-MT7620.patch [new file with mode: 0644]
target/linux/ramips/patches-3.9/0127-MIPS-ralink-make-use-of-the-new-memory-detection-cod.patch [new file with mode: 0644]
target/linux/ramips/patches-3.9/0128-MIPS-ralink-upstream-v3.10.patch [new file with mode: 0644]
target/linux/ramips/patches-3.9/0129-MIPS-ralink-add-pinmux-driver.patch [new file with mode: 0644]
target/linux/ramips/patches-3.9/0130-MIPS-ralink-add-support-for-periodic-timer-irq.patch [new file with mode: 0644]
target/linux/ramips/patches-3.9/0131-MIPS-ralink-add-rt_sysc_m32-helper.patch [new file with mode: 0644]
target/linux/ramips/patches-3.9/0132-MIPS-ralink-make-mt7620-ram-detect-verbose.patch [new file with mode: 0644]
target/linux/ramips/patches-3.9/0133-MIPS-ralink-add-verbose-pmu-info.patch [new file with mode: 0644]
target/linux/ramips/patches-3.9/0134-MIPS-ralink-adds-a-bootrom-dumper-module.patch [new file with mode: 0644]
target/linux/ramips/patches-3.9/0135-MIPS-ralink-add-missing-SZ_1M-multiplier.patch [new file with mode: 0644]
target/linux/ramips/patches-3.9/0136-MIPS-use-set_mode-to-enable-disable-the-cevt-r4k-irq.patch [new file with mode: 0644]
target/linux/ramips/patches-3.9/0137-MIPS-ralink-add-illegal-access-driver.patch [new file with mode: 0644]
target/linux/ramips/patches-3.9/0138-MIPS-ralink-workaround-DTB-memory-issue.patch [new file with mode: 0644]
target/linux/ramips/patches-3.9/0139-MIPS-ralink-add-spi-clock-definition-to-mt7620a.patch [new file with mode: 0644]
target/linux/ramips/patches-3.9/0140-MIPS-ralink-DTS-file-updates.patch [new file with mode: 0644]
target/linux/ramips/patches-3.9/0141-clocksource-make-clocksource_of_init-pass-a-device_n.patch [new file with mode: 0644]
target/linux/ramips/patches-3.9/0142-clocksource-MIPS-ralink-add-support-for-systick-time.patch [new file with mode: 0644]
target/linux/ramips/patches-3.9/0143-GPIO-MIPS-ralink-adds-ralink-gpio-support.patch [new file with mode: 0644]
target/linux/ramips/patches-3.9/0144-SPI-ralink-add-Ralink-SoC-spi-driver.patch [new file with mode: 0644]
target/linux/ramips/patches-3.9/0145-serial-of-allow-au1x00-and-rt288x-to-load-from-OF.patch [new file with mode: 0644]
target/linux/ramips/patches-3.9/0146-serial-ralink-adds-mt7620-serial.patch [new file with mode: 0644]
target/linux/ramips/patches-3.9/0147-mmc-MIPS-ralink-add-sdhci-for-mt7620a-SoC.patch [new file with mode: 0644]
target/linux/ramips/patches-3.9/0148-DMA-MIPS-ralink-add-dmaengine-driver.patch [new file with mode: 0644]
target/linux/ramips/patches-3.9/0149-PCI-MIPS-adds-rt2880-pci-support.patch [new file with mode: 0644]
target/linux/ramips/patches-3.9/0150-PCI-MIPS-adds-rt3883-pci-support.patch [new file with mode: 0644]
target/linux/ramips/patches-3.9/0151-PCI-MIPS-adds-mt7620a-pcie-driver.patch [new file with mode: 0644]
target/linux/ramips/patches-3.9/0152-watchdog-adds-ralink-wdt.patch [new file with mode: 0644]
target/linux/ramips/patches-3.9/0153-i2c-MIPS-adds-ralink-I2C-driver.patch [new file with mode: 0644]
target/linux/ramips/patches-3.9/0154-reset-Add-reset-controller-API.patch [new file with mode: 0644]
target/linux/ramips/patches-3.9/0155-reset-MIPS-ralink-add-core-device-reset-wrapper.patch [new file with mode: 0644]
target/linux/ramips/patches-3.9/0156-NET-add-of_get_mac_address_mtd.patch [new file with mode: 0644]
target/linux/ramips/patches-3.9/0157-NET-multi-phy-support.patch [new file with mode: 0644]
target/linux/ramips/patches-3.9/0159-NET-MIPS-add-ralink-SoC-ethernet-driver.patch [new file with mode: 0644]
target/linux/ramips/patches-3.9/0160-USB-phy-add-ralink-SoC-driver.patch [new file with mode: 0644]
target/linux/ramips/patches-3.9/0161-USB-add-OHCI-EHCI-OF-binding.patch [new file with mode: 0644]
target/linux/ramips/patches-3.9/0162-USB-MIPS-ralink-add-rt5350-mt7620-UDC.patch [new file with mode: 0644]
target/linux/ramips/patches-3.9/0163-USB-MIPS-ralink-fix-usb-issue-on-mt7620.patch [new file with mode: 0644]
target/linux/ramips/patches-3.9/0164-Kbuild-add-missing-space.patch [new file with mode: 0644]
target/linux/ramips/patches-3.9/0200-owrt-GPIO-add-gpio_export_with_name.patch [new file with mode: 0644]
target/linux/ramips/patches-3.9/0202-owrt-USB-adds-dwc_otg.patch [new file with mode: 0644]
target/linux/ramips/patches-3.9/0205-owrt-MIPS-add-OWRTDTB-secion.patch [new file with mode: 0644]
target/linux/ramips/patches-3.9/0206-owrt-MIPS-ralink-add-pseudo-pwm-led-trigger-based-on.patch [new file with mode: 0644]
target/linux/ramips/patches-3.9/0208-owrt-mtd-split.patch [new file with mode: 0644]
target/linux/ramips/patches-3.9/0210-mtd_fix_cfi_cmdset_0002_erase_status_check.patch [new file with mode: 0644]
target/linux/ramips/patches-3.9/0211-mtd-cfi_cmdset_0002-force-word-write.patch [new file with mode: 0644]
target/linux/ramips/patches-3.9/0999-net.patch [new file with mode: 0644]
target/linux/ramips/rt288x/config-3.9 [new file with mode: 0644]
target/linux/ramips/rt305x/config-3.8
target/linux/ramips/rt305x/config-3.9 [new file with mode: 0644]
target/linux/ramips/rt3883/config-3.9 [new file with mode: 0644]

index 1214a02..2ddf37d 100644 (file)
@@ -9,11 +9,11 @@ include $(TOPDIR)/rules.mk
 ARCH:=mipsel
 BOARD:=ramips
 BOARDNAME:=Ralink RT288x/RT3xxx
-SUBTARGETS:=rt288x rt305x rt3883
+SUBTARGETS:=rt288x rt305x rt3883 mt7620a
 CFLAGS:=-Os -pipe -fno-caller-saves -mno-branch-likely
 FEATURES:=squashfs gpio
 
-LINUX_VERSION:=3.8.13
+LINUX_VERSION:=3.9.6
 
 include $(INCLUDE_DIR)/target.mk
 DEFAULT_PACKAGES+=\
index e0b3752..960d2cb 100644 (file)
                status = "okay";
 
                mtd-mac-address = <&factory 0x28>;
-               ralink,fixed-link = <1000 1 1 1>;
+               port@0 {
+                       ralink,fixed-link = <1000 1 1 0>;
+               };
+
        };
 
        wmac@10180000 {
                };
        };
 
-       gpio_export {
-               compatible = "gpio-export";
-               #size-cells = <0>;
+       usb0: gpio-regulator {
+               compatible = "regulator-gpio";
 
-               usb {
-                       gpio-export,name = "usb";
-                       gpio-export,output = <1>;
-                       gpios = <&gpio1 6 0>;
-               };
+               regulator-type = "voltage";
+               regulator-name = "usb-power";
+               regulator-min-microvolt = <5000000>;
+               regulator-max-microvolt = <5000000>;
+               regulator-boot-on;
+
+               enable-active-high;
+               enable-gpio = <&gpio1 6 0>;
        };
 };
index 41a7f12..52b789b 100644 (file)
@@ -54,7 +54,9 @@
        ethernet@400000 {
                status = "okay";
 
-               ralink,fixed-link = <1000 1 1 1>;
+                port@0 {
+                       ralink,fixed-link = <1000 1 1 1>;
+               };
        };
 
        wmac@480000 {
index a3cc8fc..442cd26 100644 (file)
                status = "okay";
        };
 
-       gpio-export {
-               compatible = "gpio-export";
+       poe: gpio-regulator {
                // Used to enable power-over-ethernet passthrough from port0 to port1.
                // Disable passthrough by default to prevent accidental equipment damage.
-               poe {
-                       gpio-export,name = "poe-passthrough";
-                       gpio-export,output = <1>; // OUT_INIT_HIGH
-                       gpios = <&gpio0 11 1>;    // GPIO 11, ACTIVE_LOW
-               };
+               compatible = "regulator-gpio";
+
+               regulator-name = "poe-power";
+               regulator-min-microvolt = <5000000>;
+               regulator-max-microvolt = <5000000>;
+
+               enable-gpio = <&gpio0 12 0>;
        };
 
        gpio-leds {
index 8fb226b..9f8edb6 100644 (file)
                };
        };
 
-       gpio_export {
-               compatible = "gpio-export";
-               #size-cells = <0>;
+       usb0: gpio-regulator {
+               compatible = "regulator-gpio";
 
-               usb {
-                       gpio-export,name = "usb";
-                       gpio-export,output = <1>;
-                       gpios = <&gpio0 7 0>;
-               };
-               root_hub {
-                       gpio-export,name = "root_hub";
-                       gpio-export,output = <1>;
-                       gpios = <&gpio0 12 0>;
-               };
+               regulator-name = "usb0-power";
+               regulator-min-microvolt = <5000000>;
+               regulator-max-microvolt = <5000000>;
+               regulator-boot-on;
+
+               enable-active-high;
+               enable-gpio = <&gpio0 7 0>;
+       };
+
+       hub0: gpio-regulator {
+               compatible = "regulator-gpio";
+
+               regulator-name = "hub0-power";
+               regulator-min-microvolt = <5000000>;
+               regulator-max-microvolt = <5000000>;
+               regulator-boot-on;
+
+               enable-active-high;
+               enable-gpio = <&gpio0 12 0>;
        };
 };
diff --git a/target/linux/ramips/dts/MT7620a.dts b/target/linux/ramips/dts/MT7620a.dts
new file mode 100644 (file)
index 0000000..773ac51
--- /dev/null
@@ -0,0 +1,127 @@
+/dts-v1/;
+
+/include/ "mt7620a.dtsi"
+
+/ {
+       compatible = "ralink,mt7620a-eval-board", "ralink,mt7620a-soc";
+       model = "Ralink MT7620a + MT7610e evaluation board";
+
+       memory@0 {
+               reg = <0x0 0x2000000>;
+       };
+
+       chosen {
+               bootargs = "console=ttyS0,57600";
+       };
+
+       palmbus@10000000 {
+               sysc@0 {
+                       ralink,pinmux = "spi", "uartlite", "mdio", "wled", "ephy", "rgmii1", "rgmii2";
+                       ralink,gpiomux = "i2c", "jtag";
+                       ralink,uartmux = "gpio";
+                       ralink,wdtmux = <1>;
+               };
+
+               gpio0: gpio@600 {
+                       status = "okay";
+               };
+
+               spi@b00 {
+                       status = "okay";
+               
+                       m25p80@0 {
+                               #address-cells = <1>;
+                               #size-cells = <1>;
+                               compatible = "en25q64";
+                               reg = <0 0>;
+                               linux,modalias = "m25p80", "en25q64";
+                               spi-max-frequency = <10000000>;
+
+                               partition@0 {
+                                       label = "u-boot";
+                                       reg = <0x0 0x30000>;
+                                       read-only;
+                               };
+
+                               partition@30000 {
+                                       label = "u-boot-env";
+                                       reg = <0x30000 0x10000>;
+                                       read-only;
+                               };
+
+                               factory: partition@40000 {
+                                       label = "factory";
+                                       reg = <0x40000 0x10000>;
+                                       read-only;
+                               };
+
+                               partition@50000 {
+                                       label = "firmware";
+                                       reg = <0x50000 0x7b0000>;
+                               };
+                       };
+               };
+       };
+
+       ethernet@10100000 {
+               status = "okay";
+               
+               port@4 {
+                       compatible = "lantiq,mt7620a-gsw-port", "ralink,eth-port";
+                       reg = <4>;
+                       phy-mode = "rgmii";
+                       phy-handle = <&phy4>;
+               };
+
+               port@5 {
+                       compatible = "lantiq,mt7620a-gsw-port", "ralink,eth-port";
+                       reg = <5>;
+                       phy-mode = "rgmii";
+                       phy-handle = <&phy5>;
+               };
+
+               mdio-bus {
+                       status = "okay";
+
+                       phy4: ethernet-phy@4 {
+                               reg = <4>;
+                               phy-mode = "rgmii";
+                       };
+
+                       phy5: ethernet-phy@5 {
+                               reg = <5>;
+                               phy-mode = "rgmii";
+                       };
+               };
+       };
+
+       gsw@10110000 {
+               status = "okay";
+               ralink,port4 = "gmac";
+       };
+
+       sdhci@10130000 {
+               status = "okay";
+       };
+
+       pcie@10140000 {
+               status = "okay";
+       };
+
+       gpio-keys-polled {
+               compatible = "gpio-keys";
+               #address-cells = <1>;
+               #size-cells = <0>;
+               poll-interval = <20>;
+               s2 {
+                       label = "S2";
+                       gpios = <&gpio0 1 1>;
+                       linux,code = <0x100>;
+               };
+               s3 {
+                       label = "S3";
+                       gpios = <&gpio0 2 1>;
+                       linux,code = <0x101>;
+               };
+       };
+};
index 8148294..875df14 100644 (file)
                };
        };
 
-       gpio_export {
-               compatible = "gpio-export";
-               #size-cells = <0>;
-               /* gpio 12 and 13 handle the OC input */
-               usb0 {
-                       gpio-export,name = "usb0";
-                       gpio-export,output = <1>;
-                       gpios = <&gpio0 2 0>;
-               };
-               usb1 {
-                       gpio-export,name = "usb1";
-                       gpio-export,output = <1>;
-                       gpios = <&gpio0 1 0>;
-               };
+       /* gpio 12 and 13 handle the OC input */
+       usb0: gpio-regulator {
+               compatible = "regulator-gpio";
+
+               regulator-name = "usb0-power";
+               regulator-min-microvolt = <5000000>;
+               regulator-max-microvolt = <5000000>;
+               regulator-boot-on;
+
+               enable-active-high;
+               enable-gpio = <&gpio0 2 0>;
+       };
+
+       usb1: gpio-regulator {
+               compatible = "regulator-gpio";
+
+               regulator-name = "usb1-power";
+               regulator-min-microvolt = <5000000>;
+               regulator-max-microvolt = <5000000>;
+               regulator-boot-on;
+
+               enable-active-high;
+               enable-gpio = <&gpio0 1 0>;
        };
 };
index 2ff266c..8351449 100644 (file)
@@ -54,7 +54,9 @@
        ethernet@400000 {
                status = "okay";
 
-               ralink,fixed-link = <1000 1 1 1>;
+                port@0 {
+                       ralink,fixed-link = <1000 1 1 1>;
+               };
        };
 
        wmac@480000 {
index 0c09904..9c36af5 100644 (file)
@@ -31,7 +31,9 @@
        ethernet@10100000 {
                status = "okay";
 
-               ralink,fixed-link = <1000 1 1 1>;
+                port@0 {
+                       ralink,fixed-link = <1000 1 1 1>;
+               };
        };
 
        pci@10140000 {
index eb2d4bc..0027195 100644 (file)
 
        ethernet@10100000 {
                status = "okay";
-               phy-handle = <&phy0>;
-               phy-mode = "rgmii";
-
+               port@0 {
+                       phy-handle = <&phy0>;
+                       phy-mode = "rgmii";
+               };
                mdio-bus {
                        status = "okay";
 
index f5d0d04..eee4b2a 100644 (file)
 
        ethernet@10100000 {
                status = "okay";
-               ralink,phy-mask = <0x1>;
-               phy-mode = "rgmii";
+               port@0 {
+                       phy-handle = <&phy0>;
+                       phy-mode = "rgmii";
+               };
+               mdio-bus {
+                       status = "okay";
+
+                       phy0: ethernet-phy@0 {
+                               reg = <0>;
+                       };
+               };
        };
 
        pci@10140000 {
index ff33a8a..2296c3f 100644 (file)
@@ -53,7 +53,9 @@
        ethernet@400000 {
                status = "okay";
 
-               ralink,fixed-link = <100 1 1 1>;
+                port@0 {
+                       ralink,fixed-link = <1000 1 1 1>;
+               };
        };
 
        wmac@480000 {
index a970849..1e41756 100644 (file)
                status = "okay";
        };
 
-       gpio_export {
-               compatible = "gpio-export";
-               #size-cells = <0>;
+       usb0: gpio-regulator {
+               compatible = "regulator-gpio";
 
-               usb {
-                       gpio-export,name = "usb";
-                       gpio-export,output = <0>;
-                       gpios = <&gpio0 11 0>;
-               };
+               regulator-name = "usb0-power";
+               regulator-min-microvolt = <5000000>;
+               regulator-max-microvolt = <5000000>;
+               regulator-boot-on;
+
+               enable-gpio = <&gpio0 11 0>;
        };
 };
diff --git a/target/linux/ramips/dts/mt7620.dtsi b/target/linux/ramips/dts/mt7620.dtsi
deleted file mode 100644 (file)
index 9f913cd..0000000
+++ /dev/null
@@ -1,140 +0,0 @@
-/ {
-       #address-cells = <1>;
-       #size-cells = <1>;
-       compatible = "ralink,mtk7620n-soc", "ralink,mt7620-soc";
-
-       cpus {
-               cpu@0 {
-                       compatible = "mips,mips24KEc";
-               };
-       };
-
-       chosen {
-               bootargs = "console=ttyS0,57600";
-       };
-
-       cpuintc: cpuintc@0 {
-               #address-cells = <0>;
-               #interrupt-cells = <1>;
-               interrupt-controller;
-               compatible = "mti,cpu-interrupt-controller";
-       };
-
-       palmbus@10000000 {
-               compatible = "palmbus";
-               reg = <0x10000000 0x200000>;
-                ranges = <0x0 0x10000000 0x1FFFFF>;
-
-               #address-cells = <1>;
-               #size-cells = <1>;
-
-               sysc@0 {
-                       compatible = "ralink,mt7620-sysc", "ralink,mt7620n-sysc";
-                       reg = <0x0 0x100>;
-               };
-
-               timer@100 {
-                       compatible = "ralink,mt7620-timer", "ralink,rt2880-timer";
-                       reg = <0x100 0x20>;
-
-                       interrupt-parent = <&intc>;
-                       interrupts = <1>;
-               };
-
-               watchdog@120 {
-                       compatible = "ralink,mt7620-wdt", "ralink,rt2880-wdt";
-                       reg = <0x120 0x10>;
-               };
-
-               intc: intc@200 {
-                       compatible = "ralink,mt7620-intc", "ralink,rt2880-intc";
-                       reg = <0x200 0x100>;
-
-                       interrupt-controller;
-                       #interrupt-cells = <1>;
-
-                       interrupt-parent = <&cpuintc>;
-                       interrupts = <2>;
-               };
-
-               memc@300 {
-                       compatible = "ralink,mt7620-memc", "ralink,rt3050-memc";
-                       reg = <0x300 0x100>;
-               };
-
-               gpio0: gpio@600 {
-                       compatible = "ralink,mt7620-gpio", "ralink,rt2880-gpio";
-                       reg = <0x600 0x34>;
-
-                       gpio-controller;
-                       #gpio-cells = <2>;
-
-                       ralink,gpio-base = <0>;
-                       ralink,num-gpios = <24>;
-                       ralink,register-map = [ 00 04 08 0c
-                                               20 24 28 2c
-                                               30 34 ];
-               };
-
-               gpio1: gpio@638 {
-                       compatible = "ralink,mt7620-gpio", "ralink,rt2880-gpio";
-                       reg = <0x638 0x24>;
-
-                       gpio-controller;
-                       #gpio-cells = <2>;
-
-                       ralink,gpio-base = <24>;
-                       ralink,num-gpios = <16>;
-                       ralink,register-map = [ 00 04 08 0c
-                                               10 14 18 1c
-                                               20 24 ];
-               };
-
-               gpio2: gpio@660 {
-                       compatible = "ralink,mt7620-gpio", "ralink,rt2880-gpio";
-                       reg = <0x660 0x24>;
-
-                       gpio-controller;
-                       #gpio-cells = <2>;
-
-                       ralink,gpio-base = <40>;
-                       ralink,num-gpios = <32>;
-                       ralink,register-map = [ 00 04 08 0c
-                                               10 14 18 1c
-                                               20 24 ];
-               };
-
-               gpio3: gpio@688 {
-                       compatible = "ralink,mt7620-gpio", "ralink,rt2880-gpio";
-                       reg = <0x688 0x24>;
-
-                       gpio-controller;
-                       #gpio-cells = <2>;
-
-                       ralink,gpio-base = <72>;
-                       ralink,num-gpios = <1>;
-                       ralink,register-map = [ 00 04 08 0c
-                                               10 14 18 1c
-                                               20 24 ];
-               };
-
-               spi@b00 {
-                       compatible = "ralink,rt3883-spi", "ralink,rt2880-spi";
-                       reg = <0xb00 0x100>;
-                       #address-cells = <1>;
-                       #size-cells = <0>;
-
-                       status = "disabled";
-               };
-
-               uartlite@c00 {
-                       compatible = "ralink,mt7620-uart", "ralink,rt2880-uart", "ns16550a";
-                       reg = <0xc00 0x100>;
-
-                       interrupt-parent = <&intc>;
-                       interrupts = <12>;
-
-                       reg-shift = <2>;
-               };
-       };
-};
diff --git a/target/linux/ramips/dts/mt7620a.dtsi b/target/linux/ramips/dts/mt7620a.dtsi
new file mode 100644 (file)
index 0000000..104abfb
--- /dev/null
@@ -0,0 +1,294 @@
+/ {
+       #address-cells = <1>;
+       #size-cells = <1>;
+       compatible = "ralink,mtk7620a-soc";
+
+       cpus {
+               cpu@0 {
+                       compatible = "mips,mips24KEc";
+               };
+       };
+
+       cpuintc: cpuintc@0 {
+               #address-cells = <0>;
+               #interrupt-cells = <1>;
+               interrupt-controller;
+               compatible = "mti,cpu-interrupt-controller";
+       };
+
+       palmbus@10000000 {
+               compatible = "palmbus";
+               reg = <0x10000000 0x200000>;
+                ranges = <0x0 0x10000000 0x1FFFFF>;
+
+               #address-cells = <1>;
+               #size-cells = <1>;
+
+               sysc@0 {
+                       compatible = "ralink,mt7620a-sysc", "ralink,rt3050-sysc";
+                       reg = <0x0 0x100>;
+               };
+
+               timer@100 {
+                       compatible = "ralink,mt7620a-timer", "ralink,rt2880-timer";
+                       reg = <0x100 0x20>;
+
+                       interrupt-parent = <&intc>;
+                       interrupts = <1>;
+               };
+
+               watchdog@120 {
+                       compatible = "ralink,mt7620a-wdt", "ralink,rt2880-wdt";
+                       reg = <0x120 0x10>;
+
+                       resets = <&rstctrl 8>;
+                       reset-names = "wdt";
+
+                       interrupt-parent = <&intc>;
+                       interrupts = <1>;
+               };
+
+               intc: intc@200 {
+                       compatible = "ralink,mt7620a-intc", "ralink,rt2880-intc";
+                       reg = <0x200 0x100>;
+
+                       resets = <&rstctrl 19>;
+                       reset-names = "intc";
+
+                       interrupt-controller;
+                       #interrupt-cells = <1>;
+
+                       interrupt-parent = <&cpuintc>;
+                       interrupts = <2>;
+               };
+
+               memc@300 {
+                       compatible = "ralink,mt7620a-memc", "ralink,rt3050-memc";
+                       reg = <0x300 0x100>;
+
+                       resets = <&rstctrl 20>;
+                       reset-names = "mc";
+
+                       interrupt-parent = <&intc>;
+                       interrupts = <3>;
+               };
+
+               uart@500 {
+                       compatible = "ralink,mt7620a-uart", "ralink,rt2880-uart", "ns16550a";
+                       reg = <0x500 0x100>;
+
+                       resets = <&rstctrl 12>;
+                       reset-names = "uart";
+
+                       interrupt-parent = <&intc>;
+                       interrupts = <5>;
+
+                       reg-shift = <2>;
+
+                       status = "disabled";
+               };
+
+               gpio0: gpio@600 {
+                       compatible = "ralink,mt7620a-gpio", "ralink,rt2880-gpio";
+                       reg = <0x600 0x34>;
+
+                       resets = <&rstctrl 13>;
+                       reset-names = "pio";
+
+                       interrupt-parent = <&intc>;
+                       interrupts = <6>;
+
+                       gpio-controller;
+                       #gpio-cells = <2>;
+
+                       ralink,gpio-base = <0>;
+                       ralink,num-gpios = <24>;
+                       ralink,register-map = [ 00 04 08 0c
+                                               20 24 28 2c
+                                               30 34 ];
+
+                       status = "disabled";
+               };
+
+               gpio1: gpio@638 {
+                       compatible = "ralink,mt7620a-gpio", "ralink,rt2880-gpio";
+                       reg = <0x638 0x24>;
+
+                       interrupt-parent = <&intc>;
+                       interrupts = <6>;
+
+                       gpio-controller;
+                       #gpio-cells = <2>;
+
+                       ralink,gpio-base = <24>;
+                       ralink,num-gpios = <16>;
+                       ralink,register-map = [ 00 04 08 0c
+                                               10 14 18 1c
+                                               20 24 ];
+
+                       status = "disabled";
+               };
+
+               gpio2: gpio@660 {
+                       compatible = "ralink,mt7620a-gpio", "ralink,rt2880-gpio";
+                       reg = <0x660 0x24>;
+
+                       interrupt-parent = <&intc>;
+                       interrupts = <6>;
+
+                       gpio-controller;
+                       #gpio-cells = <2>;
+
+                       ralink,gpio-base = <40>;
+                       ralink,num-gpios = <32>;
+                       ralink,register-map = [ 00 04 08 0c
+                                               10 14 18 1c
+                                               20 24 ];
+
+                       status = "disabled";
+               };
+
+               i2c@900 {
+                       compatible = "link,mt7620a-i2c", "ralink,rt2880-i2c";
+                       reg = <0x900 0x100>;
+
+                       resets = <&rstctrl 16>;
+                       reset-names = "i2c";
+
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+
+                       status = "disabled";
+               };
+
+               spi@b00 {
+                       compatible = "ralink,mt7620a-spi", "ralink,rt2880-spi";
+                       reg = <0xb00 0x100>;
+
+                       resets = <&rstctrl 18>;
+                       reset-names = "spi";
+
+                       #address-cells = <1>;
+                       #size-cells = <1>;
+
+                       status = "disabled";
+               };
+
+               uartlite@c00 {
+                       compatible = "ralink,mt7620a-uart", "ralink,rt2880-uart", "ns16550a";
+                       reg = <0xc00 0x100>;
+
+                       resets = <&rstctrl 19>;
+                       reset-names = "uartl";
+
+                       interrupt-parent = <&intc>;
+                       interrupts = <12>;
+
+                       reg-shift = <2>;
+               };
+
+               systick@d00 {
+                       compatible = "ralink,mt7620a-systick", "ralink,cevt-systick";
+                       reg = <0xd00 0x10>;
+
+                       resets = <&rstctrl 28>;
+                       reset-names = "intc";
+
+                       interrupt-parent = <&cpuintc>;
+                       interrupts = <7>;
+               };
+
+               gdma@2800 {
+                       compatible = "ralink,mt7620a-gdma", "ralink,rt2880-gdma";
+                       reg = <0x2800 0x800>;
+
+                       resets = <&rstctrl 14>;
+                       reset-names = "dma";
+
+                       interrupt-parent = <&intc>;
+                       interrupts = <7>;
+               };
+       };
+
+       rstctrl: rstctrl {
+               compatible = "ralink,mt7620a-reset", "ralink,rt2880-reset";
+               #reset-cells = <1>;
+       };
+
+       ubsphy {
+               compatible = "ralink,mt7620a-usbphy";
+
+               resets = <&rstctrl 22 &rstctrl 25>;
+               reset-names = "host", "device";
+       };
+
+       ethernet@10100000 {
+               compatible = "ralink,mt7620a-eth";
+               reg = <0x10100000 10000>;
+
+               #address-cells = <1>;
+               #size-cells = <0>;
+
+               interrupt-parent = <&cpuintc>;
+               interrupts = <5>;
+
+               status = "disabled";
+       
+               mdio-bus {
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+
+                       status = "disabled";
+               };
+       };
+
+       gsw@10110000 {
+               compatible = "ralink,mt7620a-gsw";
+               reg = <0x10110000 8000>;
+
+               interrupt-parent = <&intc>;
+               interrupts = <17>;
+
+               status = "disabled";
+       };
+
+       sdhci@10130000 {
+               compatible = "ralink,mt7620a-sdhci";
+               reg = <0x10130000 4000>;
+
+               interrupt-parent = <&intc>;
+               interrupts = <14>;
+
+               status = "disabled";
+       };
+
+       ehci@101c0000 {
+               compatible = "ralink,rt3xxx-ehci";
+               reg = <0x101c0000 0x1000>;
+
+               interrupt-parent = <&intc>;
+               interrupts = <18>;
+       };
+
+       ohci@101c1000 {
+               compatible = "ralink,rt3xxx-ohci";
+               reg = <0x101c1000 0x1000>;
+
+               interrupt-parent = <&intc>;
+               interrupts = <18>;
+       };
+
+       pcie@10140000 {
+               compatible = "ralink,mt7620a-pci";
+               reg = <0x10140000 0x100
+                       0x10142000 0x100>;
+
+               resets = <&rstctrl 26>;
+               reset-names = "pcie0";
+
+               interrupt-parent = <&cpuintc>;
+               interrupts = <4>;
+
+               status = "disabled";
+       };
+};
diff --git a/target/linux/ramips/dts/mt7620a_mt7610e_eval.dts b/target/linux/ramips/dts/mt7620a_mt7610e_eval.dts
new file mode 100644 (file)
index 0000000..0d7755b
--- /dev/null
@@ -0,0 +1,99 @@
+/dts-v1/;
+
+/include/ "mt7620a.dtsi"
+
+/ {
+       compatible = "ralink,mt7620a-eval-board", "ralink,mt7620a-soc";
+       model = "Ralink MT7620A evaluation board";
+
+       memory@0 {
+               reg = <0x0 0x2000000>;
+       };
+
+       chosen {
+               bootargs = "console=ttyS0,57600";
+       };
+
+       palmbus@10000000 {
+               sysc@0 {
+                       ralink,pinmux = "spi", "uartlite", "mdio", "wled", "ephy", "rgmii1", "rgmii2";
+                       ralink,gpiomux = "i2c", "jtag";
+                       ralink,uartmux = "gpio";
+                       ralink,wdtmux = <1>;
+               };
+
+               gpio0: gpio@600 {
+                       status = "okay";
+               };
+
+               spi@b00 {
+                       status = "okay";
+               
+                       m25p80@0 {
+                               #address-cells = <1>;
+                               #size-cells = <1>;
+                               compatible = "en25q64";
+                               reg = <0 0>;
+                               linux,modalias = "m25p80", "en25q64";
+                               spi-max-frequency = <10000000>;
+
+                               partition@0 {
+                                       label = "u-boot";
+                                       reg = <0x0 0x30000>;
+                                       read-only;
+                               };
+
+                               partition@30000 {
+                                       label = "u-boot-env";
+                                       reg = <0x30000 0x10000>;
+                                       read-only;
+                               };
+
+                               factory: partition@40000 {
+                                       label = "factory";
+                                       reg = <0x40000 0x10000>;
+                                       read-only;
+                               };
+
+                               partition@50000 {
+                                       label = "firmware";
+                                       reg = <0x50000 0x7b0000>;
+                               };
+                       };
+               };
+       };
+
+       ethernet@10100000 {
+               status = "okay";
+       };
+
+       gsw@10110000 {
+               status = "okay";
+               ralink,port4 = "ephy";
+       };
+
+       sdhci@10130000 {
+               status = "okay";
+       };
+
+       pcie@10140000 {
+               status = "okay";
+       };
+
+       gpio-keys-polled {
+               compatible = "gpio-keys";
+               #address-cells = <1>;
+               #size-cells = <0>;
+               poll-interval = <20>;
+               wps {
+                       label = "wps";
+                       gpios = <&gpio0 12 1>;
+                       linux,code = <0x100>;
+               };
+               reset {
+                       label = "reset";
+                       gpios = <&gpio0 13 1>;
+                       linux,code = <0x101>;
+               };
+       };
+};
index 637409f..b513148 100644 (file)
                bootargs = "console=ttyS0,57600";
        };
 
-       memorydetect {
-               ralink,memory = <0x8000000 0x200000 0x8000000>;
-       };
-
        cpuintc: cpuintc@0 {
                #address-cells = <0>;
                #interrupt-cells = <1>;
index 45d9238..29cd536 100644 (file)
                bootargs = "console=ttyS0,57600";
        };
 
-       memorydetect {
-               ralink,memory = <0x0 0x200000 0x4000000>;
-       };
-
        cpuintc: cpuintc@0 {
                #address-cells = <0>;
                #interrupt-cells = <1>;
                watchdog@120 {
                        compatible = "ralink,rt3052-wdt", "ralink,rt2880-wdt";
                        reg = <0x120 0x10>;
+
+                       resets = <&rstctrl 8>;
+                       reset-names = "wdt";
+
+                       interrupt-parent = <&intc>;
+                       interrupts = <1>;
                };
 
                intc: intc@200 {
                        compatible = "ralink,rt3052-intc", "ralink,rt2880-intc";
                        reg = <0x200 0x100>;
 
+                       resets = <&rstctrl 19>;
+                       reset-names = "intc";
+
                        interrupt-controller;
                        #interrupt-cells = <1>;
 
                memc@300 {
                        compatible = "ralink,rt3052-memc", "ralink,rt3050-memc";
                        reg = <0x300 0x100>;
+
+                       resets = <&rstctrl 20>;
+                       reset-names = "mc";
+
+                       interrupt-parent = <&intc>;
+                       interrupts = <3>;
+               };
+
+               uart@500 {
+                       compatible = "ralink,rt5350-uart", "ralink,rt2880-uart", "ns16550a";
+                       reg = <0x500 0x100>;
+
+                       resets = <&rstctrl 12>;
+                       reset-names = "uart";
+
+                       interrupt-parent = <&intc>;
+                       interrupts = <5>;
+
+                       reg-shift = <2>;
+
+                       status = "disabled";
                };
 
                gpio0: gpio@600 {
                                                20 24 28 2c
                                                30 34 ];
 
+                       resets = <&rstctrl 13>;
+                       reset-names = "pio";
+
+                       interrupt-parent = <&intc>;
+                       interrupts = <6>;
+
                        status = "disabled";
                };
 
                spi@b00 {
                        compatible = "ralink,rt3050-spi", "ralink,rt2880-spi";
                        reg = <0xb00 0x100>;
+                       
+                       resets = <&rstctrl 18>;
+                       reset-names = "spi";
+
                        #address-cells = <1>;
                        #size-cells = <0>;
 
                uartlite@c00 {
                        compatible = "ralink,rt3052-uart", "ralink,rt2880-uart", "ns16550a";
                        reg = <0xc00 0x100>;
+                       resets = <&rstctrl 19>;
+                       reset-names = "uartl";
 
                        interrupt-parent = <&intc>;
                        interrupts = <12>;
 
        };
 
+       rstctrl: rstctrl {
+               compatible = "ralink,rt3050-reset", "ralink,rt2880-reset";
+               #reset-cells = <1>;
+       };
+
        ethernet@10100000 {
                compatible = "ralink,rt3050-eth";
                reg = <0x10100000 10000>;
index 9c7c268..e4d35d8 100644 (file)
                bootargs = "console=ttyS0,57600";
        };
 
-       memorydetect {
-               ralink,memory = <0x0 0x200000 0x10000000>;
-       };
-
        cpuintc: cpuintc@0 {
                #address-cells = <0>;
                #interrupt-cells = <1>;
                watchdog@120 {
                        compatible = "ralink,rt3352-wdt", "ralink,rt2880-wdt";
                        reg = <0x120 0x10>;
+
+                       resets = <&rstctrl 8>;
+                       reset-names = "wdt";
+
+                       interrupt-parent = <&intc>;
+                       interrupts = <1>;
                };
 
                intc: intc@200 {
                memc@300 {
                        compatible = "ralink,rt3352-memc", "ralink,rt3050-memc";
                        reg = <0x300 0x100>;
+
+                       resets = <&rstctrl 20>;
+                       reset-names = "mc";
+
+                       interrupt-parent = <&intc>;
+                       interrupts = <3>;
+               };
+
+               uart@500 {
+                       compatible = "ralink,rt3352-uart", "ralink,rt2880-uart", "ns16550a";
+                       reg = <0x500 0x100>;
+
+                       resets = <&rstctrl 12>;
+                       reset-names = "uart";
+
+                       interrupt-parent = <&intc>;
+                       interrupts = <5>;
+
+                       reg-shift = <2>;
+
+                       status = "disabled";
                };
 
                gpio0: gpio@600 {
                        ralink,register-map = [ 00 04 08 0c
                                                20 24 28 2c
                                                30 34 ];
+                       resets = <&rstctrl 13>;
+                       reset-names = "pio";
+
+                       interrupt-parent = <&intc>;
+                       interrupts = <6>;
 
                        status = "disabled";
                };
                        #address-cells = <1>;
                        #size-cells = <1>;
 
+                       resets = <&rstctrl 18>;
+                       reset-names = "spi";
+       
                        status = "disabled";
                };
 
                        compatible = "ralink,rt3352-uart", "ralink,rt2880-uart", "ns16550a";
                        reg = <0xc00 0x100>;
 
+                       resets = <&rstctrl 19>;
+                       reset-names = "uartl";
+
                        interrupt-parent = <&intc>;
                        interrupts = <12>;
 
                };
        };
 
+       rstctrl: rstctrl {
+               compatible = "ralink,rt3352-reset", "ralink,rt2880-reset";
+               #reset-cells = <1>;
+       };
+
        ethernet@10100000 {
                compatible = "ralink,rt3352-eth", "ralink,rt3050-eth";
                reg = <0x10100000 10000>;
index 6f824d5..046c9e9 100644 (file)
                spi0 = &spi0;
        };
 
-       memorydetect {
-               ralink,memory = <0x0 0x200000 0x10000000>;
-       };
-
        cpuintc: cpuintc@0 {
                #address-cells = <0>;
                #interrupt-cells = <1>;
                watchdog@120 {
                        compatible = "ralink,rt3883-wdt", "ralink,rt2880-wdt";
                        reg = <0x120 0x10>;
+
+                       resets = <&rstctrl 8>;
+                       reset-names = "wdt";
+
+                       interrupt-parent = <&intc>;
+                       interrupts = <1>;
                };
 
                intc: intc@200 {
                        compatible = "ralink,rt3883-intc", "ralink,rt2880-intc";
                        reg = <0x200 0x100>;
 
+                       resets = <&rstctrl 19>;
+                       reset-names = "intc";
+
                        interrupt-controller;
                        #interrupt-cells = <1>;
 
                memc@300 {
                        compatible = "ralink,rt3883-memc", "ralink,rt3050-memc";
                        reg = <0x300 0x100>;
+
+                       resets = <&rstctrl 20>;
+                       reset-names = "mc";
+
+                       interrupt-parent = <&intc>;
+                       interrupts = <3>;
+               };
+
+               uart@500 {
+                       compatible = "ralink,rt3883-uart", "ralink,rt2880-uart", "ns16550a";
+                       reg = <0x500 0x100>;
+
+                       resets = <&rstctrl 12>;
+                       reset-names = "uart";
+
+                       interrupt-parent = <&intc>;
+                       interrupts = <5>;
+
+                       reg-shift = <2>;
+
+                       status = "disabled";
                };
 
                gpio0: gpio@600 {
                        compatible = "ralink,rt3883-gpio", "ralink,rt2880-gpio";
                        reg = <0x600 0x34>;
 
+                       resets = <&rstctrl 13>;
+                       reset-names = "pio";
+
+                       interrupt-parent = <&intc>;
+                       interrupts = <6>;
+
                        gpio-controller;
                        #gpio-cells = <2>;
 
                        #address-cells = <1>;
                        #size-cells = <0>;
 
+                       resets = <&rstctrl 18>;
+                       reset-names = "spi";
+
                        status = "disabled";
                };
 
                        compatible = "ralink,rt3883-uart", "ralink,rt2880-uart", "ns16550a";
                        reg = <0xc00 0x100>;
 
+                       resets = <&rstctrl 19>;
+                       reset-names = "uartl";
+
                        interrupt-parent = <&intc>;
                        interrupts = <12>;
 
 
                status = "disabled";
 
+               port@0 {
+                       compatible = "lantiq,rt3883-port", "ralink,eth-port";
+                       reg = <0>;
+               };
+
                mdio-bus {
                        #address-cells = <1>;
                        #size-cells = <0>;
                };
        };
 
+       rstctrl: rstctrl {
+               compatible = "ralink,rt3883-reset", "ralink,rt2880-reset";
+               #reset-cells = <1>;
+       };
+
        pci@10140000 {
                compatible = "ralink,rt3883-pci";
                reg = <0x10140000 0x20000>;
                };
        };
 
+       ubsphy {
+               compatible = "ralink,rt3xxx-usbphy";
+
+               resets = <&rstctrl 22 &rstctrl 25>;
+               reset-names = "host", "device";
+       };
+
        wmac@10180000 {
                compatible = "ralink,rt3883-wmac", "ralink,rt2880-wmac";
                reg = <0x10180000 40000>;
index c48d781..e132699 100644 (file)
                bootargs = "console=ttyS0,57600";
        };
 
-       memorydetect {
-               ralink,memory = <0x0 0x200000 0x4000000>;
-       };
-
        cpuintc: cpuintc@0 {
                #address-cells = <0>;
                #interrupt-cells = <1>;
                watchdog@120 {
                        compatible = "ralink,rt5350-wdt", "ralink,rt2880-wdt";
                        reg = <0x120 0x10>;
+
+                       resets = <&rstctrl 8>;
+                       reset-names = "wdt";
+
+                       interrupt-parent = <&intc>;
+                       interrupts = <1>;
                };
 
                intc: intc@200 {
                        compatible = "ralink,rt5350-intc", "ralink,rt2880-intc";
                        reg = <0x200 0x100>;
 
+                       resets = <&rstctrl 19>;
+                       reset-names = "intc";
+
                        interrupt-controller;
                        #interrupt-cells = <1>;
 
                memc@300 {
                        compatible = "ralink,rt5350-memc", "ralink,rt3050-memc";
                        reg = <0x300 0x100>;
+
+                       resets = <&rstctrl 20>;
+                       reset-names = "mc";
+
+                       interrupt-parent = <&intc>;
+                       interrupts = <3>;
+               };
+
+               uart@500 {
+                       compatible = "ralink,rt5350-uart", "ralink,rt2880-uart", "ns16550a";
+                       reg = <0x500 0x100>;
+
+                       resets = <&rstctrl 12>;
+                       reset-names = "uart";
+
+                       interrupt-parent = <&intc>;
+                       interrupts = <5>;
+
+                       reg-shift = <2>;
+
+                       status = "disabled";
                };
 
                gpio0: gpio@600 {
                        compatible = "ralink,rt5350-gpio", "ralink,rt2880-gpio";
                        reg = <0x600 0x34>;
 
+                       resets = <&rstctrl 13>;
+                       reset-names = "pio";
+
+                       interrupt-parent = <&intc>;
+                       interrupts = <6>;
+
                        gpio-controller;
                        #gpio-cells = <2>;
 
                        compatible = "ralink,rt5350-gpio", "ralink,rt2880-gpio";
                        reg = <0x638 0x24>;
 
+                       interrupt-parent = <&intc>;
+                       interrupts = <6>;
+
                        gpio-controller;
                        #gpio-cells = <2>;
 
                        compatible = "ralink,rt5350-gpio", "ralink,rt2880-gpio";
                        reg = <0x660 0x24>;
 
+                       interrupt-parent = <&intc>;
+                       interrupts = <6>;
+
                        gpio-controller;
                        #gpio-cells = <2>;
 
                        status = "disabled";
                };
 
+               i2c@900 {
+                       compatible = "link,rt5350-i2c", "ralink,rt2880-i2c";
+                       reg = <0x900 0x100>;
+
+                       resets = <&rstctrl 16>;
+                       reset-names = "i2c";
+
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+
+                       status = "disabled";
+               };
+
                spi@b00 {
                        compatible = "ralink,rt5350-spi", "ralink,rt2880-spi";
                        reg = <0xb00 0x100>;
+
+                       resets = <&rstctrl 18>;
+                       reset-names = "spi";
+
                        #address-cells = <1>;
                        #size-cells = <1>;
 
                        compatible = "ralink,rt5350-uart", "ralink,rt2880-uart", "ns16550a";
                        reg = <0xc00 0x100>;
 
+                       resets = <&rstctrl 19>;
+                       reset-names = "uartl";
+
                        interrupt-parent = <&intc>;
                        interrupts = <12>;
 
                        reg-shift = <2>;
                };
+
+               systick@d00 {
+                       compatible = "ralink,rt5350-systick", "ralink,cevt-systick";
+                       reg = <0xd00 0x10>;
+
+                       interrupt-parent = <&cpuintc>;
+                       interrupts = <7>;
+               };
+       };
+
+       rstctrl: rstctrl {
+               compatible = "ralink,rt5350-reset", "ralink,rt2880-reset";
+               #reset-cells = <1>;
+       };
+
+       ubsphy {
+               compatible = "ralink,rt3xxx-usbphy";
+
+               resets = <&rstctrl 22 &rstctrl 25>;
+               reset-names = "host", "device";
        };
 
        ethernet@10100000 {
-               compatible = "ralink,rt5350-eth", "ralink,rt3050-eth";
+               compatible = "ralink,rt5350-eth";
                reg = <0x10100000 10000>;
 
                interrupt-parent = <&cpuintc>;
        };
 
        esw@10110000 {
-               compatible = "ralink,rt5350-esw", "ralink,rt3050-esw";
+               compatible = "ralink,rt3050-esw";
                reg = <0x10110000 8000>;
 
                interrupt-parent = <&intc>;
        };
 
        ehci@101c0000 {
-               compatible = "ralink,rt5350-ehci", "ehci-platform";
+               compatible = "ralink,rt3xxx-ehci", "ehci-platform";
                reg = <0x101c0000 0x1000>;
 
                interrupt-parent = <&intc>;
                interrupts = <18>;
-
-               status = "disabled";
        };
 
        ohci@101c1000 {
-               compatible = "ralink,rt5350-ohci", "ohci-platform";
+               compatible = "ralink,rt3xxx-ohci", "ohci-platform";
                reg = <0x101c1000 0x1000>;
 
                interrupt-parent = <&intc>;
                interrupts = <18>;
-
-               status = "disabled";
        };
 };
index f00eb6c..5f2c311 100644 (file)
@@ -519,6 +519,18 @@ define Image/Build/Profile/Default
 endef
 endif
 
+#
+# MT7620A Profiles
+#
+
+Image/Build/Profile/MT7620a=$(call BuildFirmware/Default8M/$(1),$(1),mt7620a,MT7620a)
+
+ifeq ($(SUBTARGET),mt7620a)
+define Image/Build/Profile/Default
+       $(call Image/Build/Profile/MT7620a,$(1))
+endef
+endif
+
 
 #
 # Generic Targets
diff --git a/target/linux/ramips/image/lzma-loader/Makefile b/target/linux/ramips/image/lzma-loader/Makefile
new file mode 100644 (file)
index 0000000..7833016
--- /dev/null
@@ -0,0 +1,65 @@
+#
+# Copyright (C) 2011 OpenWrt.org
+# Copyright (C) 2011 Gabor Juhos <juhosg@openwrt.org>
+#
+# This is free software, licensed under the GNU General Public License v2.
+# See /LICENSE for more information.
+#
+
+include $(TOPDIR)/rules.mk
+
+LZMA_TEXT_START        := 0x80a00000
+LOADER         := loader.bin
+LOADER_NAME    := $(basename $(notdir $(LOADER)))
+LOADER_DATA    :=
+TARGET_DIR     :=
+FLASH_OFFS     :=
+FLASH_MAX      :=
+BOARD          :=
+
+ifeq ($(TARGET_DIR),)
+TARGET_DIR     := $(KDIR)
+endif
+
+LOADER_BIN     := $(TARGET_DIR)/$(LOADER_NAME).bin
+LOADER_GZ      := $(TARGET_DIR)/$(LOADER_NAME).gz
+LOADER_ELF     := $(TARGET_DIR)/$(LOADER_NAME).elf
+
+PKG_NAME := lzma-loader
+PKG_BUILD_DIR := $(KDIR)/$(PKG_NAME)
+
+.PHONY : loader-compile loader.bin loader.elf loader.gz
+
+$(PKG_BUILD_DIR)/.prepared:
+       mkdir $(PKG_BUILD_DIR)
+       $(CP) ./src/* $(PKG_BUILD_DIR)/
+       touch $@
+
+loader-compile: $(PKG_BUILD_DIR)/.prepared
+       $(MAKE) -C $(PKG_BUILD_DIR) CROSS_COMPILE="$(TARGET_CROSS)" \
+               LZMA_TEXT_START=$(LZMA_TEXT_START) \
+               LOADER_DATA=$(LOADER_DATA) \
+               FLASH_OFFS=$(FLASH_OFFS) \
+               FLASH_MAX=$(FLASH_MAX) \
+               BOARD="$(BOARD)" \
+               PLATFORM="ralink" \
+               clean all
+
+loader.gz: $(PKG_BUILD_DIR)/loader.bin
+       gzip -nc9 $< > $(LOADER_GZ)
+
+loader.elf: $(PKG_BUILD_DIR)/loader.elf
+       $(CP) $< $(LOADER_ELF)
+
+loader.bin: $(PKG_BUILD_DIR)/loader.bin
+       $(CP) $< $(LOADER_BIN)
+
+download:
+prepare: $(PKG_BUILD_DIR)/.prepared
+compile: loader-compile
+
+install:
+
+clean:
+       rm -rf $(PKG_BUILD_DIR)
+
diff --git a/target/linux/ramips/image/lzma-loader/src/LzmaDecode.c b/target/linux/ramips/image/lzma-loader/src/LzmaDecode.c
new file mode 100644 (file)
index 0000000..cb83453
--- /dev/null
@@ -0,0 +1,584 @@
+/*
+  LzmaDecode.c
+  LZMA Decoder (optimized for Speed version)
+  
+  LZMA SDK 4.40 Copyright (c) 1999-2006 Igor Pavlov (2006-05-01)
+  http://www.7-zip.org/
+
+  LZMA SDK is licensed under two licenses:
+  1) GNU Lesser General Public License (GNU LGPL)
+  2) Common Public License (CPL)
+  It means that you can select one of these two licenses and 
+  follow rules of that license.
+
+  SPECIAL EXCEPTION:
+  Igor Pavlov, as the author of this Code, expressly permits you to 
+  statically or dynamically link your Code (or bind by name) to the 
+  interfaces of this file without subjecting your linked Code to the 
+  terms of the CPL or GNU LGPL. Any modifications or additions 
+  to this file, however, are subject to the LGPL or CPL terms.
+*/
+
+#include "LzmaDecode.h"
+
+#define kNumTopBits 24
+#define kTopValue ((UInt32)1 << kNumTopBits)
+
+#define kNumBitModelTotalBits 11
+#define kBitModelTotal (1 << kNumBitModelTotalBits)
+#define kNumMoveBits 5
+
+#define RC_READ_BYTE (*Buffer++)
+
+#define RC_INIT2 Code = 0; Range = 0xFFFFFFFF; \
+  { int i; for(i = 0; i < 5; i++) { RC_TEST; Code = (Code << 8) | RC_READ_BYTE; }}
+
+#ifdef _LZMA_IN_CB
+
+#define RC_TEST { if (Buffer == BufferLim) \
+  { SizeT size; int result = InCallback->Read(InCallback, &Buffer, &size); if (result != LZMA_RESULT_OK) return result; \
+  BufferLim = Buffer + size; if (size == 0) return LZMA_RESULT_DATA_ERROR; }}
+
+#define RC_INIT Buffer = BufferLim = 0; RC_INIT2
+
+#else
+
+#define RC_TEST { if (Buffer == BufferLim) return LZMA_RESULT_DATA_ERROR; }
+
+#define RC_INIT(buffer, bufferSize) Buffer = buffer; BufferLim = buffer + bufferSize; RC_INIT2
+#endif
+
+#define RC_NORMALIZE if (Range < kTopValue) { RC_TEST; Range <<= 8; Code = (Code << 8) | RC_READ_BYTE; }
+
+#define IfBit0(p) RC_NORMALIZE; bound = (Range >> kNumBitModelTotalBits) * *(p); if (Code < bound)
+#define UpdateBit0(p) Range = bound; *(p) += (kBitModelTotal - *(p)) >> kNumMoveBits;
+#define UpdateBit1(p) Range -= bound; Code -= bound; *(p) -= (*(p)) >> kNumMoveBits;
+
+#define RC_GET_BIT2(p, mi, A0, A1) IfBit0(p) \
+  { UpdateBit0(p); mi <<= 1; A0; } else \
+  { UpdateBit1(p); mi = (mi + mi) + 1; A1; } 
+  
+#define RC_GET_BIT(p, mi) RC_GET_BIT2(p, mi, ; , ;)               
+
+#define RangeDecoderBitTreeDecode(probs, numLevels, res) \
+  { int i = numLevels; res = 1; \
+  do { CProb *p = probs + res; RC_GET_BIT(p, res) } while(--i != 0); \
+  res -= (1 << numLevels); }
+
+
+#define kNumPosBitsMax 4
+#define kNumPosStatesMax (1 << kNumPosBitsMax)
+
+#define kLenNumLowBits 3
+#define kLenNumLowSymbols (1 << kLenNumLowBits)
+#define kLenNumMidBits 3
+#define kLenNumMidSymbols (1 << kLenNumMidBits)
+#define kLenNumHighBits 8
+#define kLenNumHighSymbols (1 << kLenNumHighBits)
+
+#define LenChoice 0
+#define LenChoice2 (LenChoice + 1)
+#define LenLow (LenChoice2 + 1)
+#define LenMid (LenLow + (kNumPosStatesMax << kLenNumLowBits))
+#define LenHigh (LenMid + (kNumPosStatesMax << kLenNumMidBits))
+#define kNumLenProbs (LenHigh + kLenNumHighSymbols) 
+
+
+#define kNumStates 12
+#define kNumLitStates 7
+
+#define kStartPosModelIndex 4
+#define kEndPosModelIndex 14
+#define kNumFullDistances (1 << (kEndPosModelIndex >> 1))
+
+#define kNumPosSlotBits 6
+#define kNumLenToPosStates 4
+
+#define kNumAlignBits 4
+#define kAlignTableSize (1 << kNumAlignBits)
+
+#define kMatchMinLen 2
+
+#define IsMatch 0
+#define IsRep (IsMatch + (kNumStates << kNumPosBitsMax))
+#define IsRepG0 (IsRep + kNumStates)
+#define IsRepG1 (IsRepG0 + kNumStates)
+#define IsRepG2 (IsRepG1 + kNumStates)
+#define IsRep0Long (IsRepG2 + kNumStates)
+#define PosSlot (IsRep0Long + (kNumStates << kNumPosBitsMax))
+#define SpecPos (PosSlot + (kNumLenToPosStates << kNumPosSlotBits))
+#define Align (SpecPos + kNumFullDistances - kEndPosModelIndex)
+#define LenCoder (Align + kAlignTableSize)
+#define RepLenCoder (LenCoder + kNumLenProbs)
+#define Literal (RepLenCoder + kNumLenProbs)
+
+#if Literal != LZMA_BASE_SIZE
+StopCompilingDueBUG
+#endif
+
+int LzmaDecodeProperties(CLzmaProperties *propsRes, const unsigned char *propsData, int size)
+{
+  unsigned char prop0;
+  if (size < LZMA_PROPERTIES_SIZE)
+    return LZMA_RESULT_DATA_ERROR;
+  prop0 = propsData[0];
+  if (prop0 >= (9 * 5 * 5))
+    return LZMA_RESULT_DATA_ERROR;
+  {
+    for (propsRes->pb = 0; prop0 >= (9 * 5); propsRes->pb++, prop0 -= (9 * 5));
+    for (propsRes->lp = 0; prop0 >= 9; propsRes->lp++, prop0 -= 9);
+    propsRes->lc = prop0;
+    /*
+    unsigned char remainder = (unsigned char)(prop0 / 9);
+    propsRes->lc = prop0 % 9;
+    propsRes->pb = remainder / 5;
+    propsRes->lp = remainder % 5;
+    */
+  }
+
+  #ifdef _LZMA_OUT_READ
+  {
+    int i;
+    propsRes->DictionarySize = 0;
+    for (i = 0; i < 4; i++)
+      propsRes->DictionarySize += (UInt32)(propsData[1 + i]) << (i * 8);
+    if (propsRes->DictionarySize == 0)
+      propsRes->DictionarySize = 1;
+  }
+  #endif
+  return LZMA_RESULT_OK;
+}
+
+#define kLzmaStreamWasFinishedId (-1)
+
+int LzmaDecode(CLzmaDecoderState *vs,
+    #ifdef _LZMA_IN_CB
+    ILzmaInCallback *InCallback,
+    #else
+    const unsigned char *inStream, SizeT inSize, SizeT *inSizeProcessed,
+    #endif
+    unsigned char *outStream, SizeT outSize, SizeT *outSizeProcessed)
+{
+  CProb *p = vs->Probs;
+  SizeT nowPos = 0;
+  Byte previousByte = 0;
+  UInt32 posStateMask = (1 << (vs->Properties.pb)) - 1;
+  UInt32 literalPosMask = (1 << (vs->Properties.lp)) - 1;
+  int lc = vs->Properties.lc;
+
+  #ifdef _LZMA_OUT_READ
+  
+  UInt32 Range = vs->Range;
+  UInt32 Code = vs->Code;
+  #ifdef _LZMA_IN_CB
+  const Byte *Buffer = vs->Buffer;
+  const Byte *BufferLim = vs->BufferLim;
+  #else
+  const Byte *Buffer = inStream;
+  const Byte *BufferLim = inStream + inSize;
+  #endif
+  int state = vs->State;
+  UInt32 rep0 = vs->Reps[0], rep1 = vs->Reps[1], rep2 = vs->Reps[2], rep3 = vs->Reps[3];
+  int len = vs->RemainLen;
+  UInt32 globalPos = vs->GlobalPos;
+  UInt32 distanceLimit = vs->DistanceLimit;
+
+  Byte *dictionary = vs->Dictionary;
+  UInt32 dictionarySize = vs->Properties.DictionarySize;
+  UInt32 dictionaryPos = vs->DictionaryPos;
+
+  Byte tempDictionary[4];
+
+  #ifndef _LZMA_IN_CB
+  *inSizeProcessed = 0;
+  #endif
+  *outSizeProcessed = 0;
+  if (len == kLzmaStreamWasFinishedId)
+    return LZMA_RESULT_OK;
+
+  if (dictionarySize == 0)
+  {
+    dictionary = tempDictionary;
+    dictionarySize = 1;
+    tempDictionary[0] = vs->TempDictionary[0];
+  }
+
+  if (len == kLzmaNeedInitId)
+  {
+    {
+      UInt32 numProbs = Literal + ((UInt32)LZMA_LIT_SIZE << (lc + vs->Properties.lp));
+      UInt32 i;
+      for (i = 0; i < numProbs; i++)
+        p[i] = kBitModelTotal >> 1; 
+      rep0 = rep1 = rep2 = rep3 = 1;
+      state = 0;
+      globalPos = 0;
+      distanceLimit = 0;
+      dictionaryPos = 0;
+      dictionary[dictionarySize - 1] = 0;
+      #ifdef _LZMA_IN_CB
+      RC_INIT;
+      #else
+      RC_INIT(inStream, inSize);
+      #endif
+    }
+    len = 0;
+  }
+  while(len != 0 && nowPos < outSize)
+  {
+    UInt32 pos = dictionaryPos - rep0;
+    if (pos >= dictionarySize)
+      pos += dictionarySize;
+    outStream[nowPos++] = dictionary[dictionaryPos] = dictionary[pos];
+    if (++dictionaryPos == dictionarySize)
+      dictionaryPos = 0;
+    len--;
+  }
+  if (dictionaryPos == 0)
+    previousByte = dictionary[dictionarySize - 1];
+  else
+    previousByte = dictionary[dictionaryPos - 1];
+
+  #else /* if !_LZMA_OUT_READ */
+
+  int state = 0;
+  UInt32 rep0 = 1, rep1 = 1, rep2 = 1, rep3 = 1;
+  int len = 0;
+  const Byte *Buffer;
+  const Byte *BufferLim;
+  UInt32 Range;
+  UInt32 Code;
+
+  #ifndef _LZMA_IN_CB
+  *inSizeProcessed = 0;
+  #endif
+  *outSizeProcessed = 0;
+
+  {
+    UInt32 i;
+    UInt32 numProbs = Literal + ((UInt32)LZMA_LIT_SIZE << (lc + vs->Properties.lp));
+    for (i = 0; i < numProbs; i++)
+      p[i] = kBitModelTotal >> 1;
+  }
+  
+  #ifdef _LZMA_IN_CB
+  RC_INIT;
+  #else
+  RC_INIT(inStream, inSize);
+  #endif
+
+  #endif /* _LZMA_OUT_READ */
+
+  while(nowPos < outSize)
+  {
+    CProb *prob;
+    UInt32 bound;
+    int posState = (int)(
+        (nowPos 
+        #ifdef _LZMA_OUT_READ
+        + globalPos
+        #endif
+        )
+        & posStateMask);
+
+    prob = p + IsMatch + (state << kNumPosBitsMax) + posState;
+    IfBit0(prob)
+    {
+      int symbol = 1;
+      UpdateBit0(prob)
+      prob = p + Literal + (LZMA_LIT_SIZE * 
+        (((
+        (nowPos 
+        #ifdef _LZMA_OUT_READ
+        + globalPos
+        #endif
+        )
+        & literalPosMask) << lc) + (previousByte >> (8 - lc))));
+
+      if (state >= kNumLitStates)
+      {
+        int matchByte;
+        #ifdef _LZMA_OUT_READ
+        UInt32 pos = dictionaryPos - rep0;
+        if (pos >= dictionarySize)
+          pos += dictionarySize;
+        matchByte = dictionary[pos];
+        #else
+        matchByte = outStream[nowPos - rep0];
+        #endif
+        do
+        {
+          int bit;
+          CProb *probLit;
+          matchByte <<= 1;
+          bit = (matchByte & 0x100);
+          probLit = prob + 0x100 + bit + symbol;
+          RC_GET_BIT2(probLit, symbol, if (bit != 0) break, if (bit == 0) break)
+        }
+        while (symbol < 0x100);
+      }
+      while (symbol < 0x100)
+      {
+        CProb *probLit = prob + symbol;
+        RC_GET_BIT(probLit, symbol)
+      }
+      previousByte = (Byte)symbol;
+
+      outStream[nowPos++] = previousByte;
+      #ifdef _LZMA_OUT_READ
+      if (distanceLimit < dictionarySize)
+        distanceLimit++;
+
+      dictionary[dictionaryPos] = previousByte;
+      if (++dictionaryPos == dictionarySize)
+        dictionaryPos = 0;
+      #endif
+      if (state < 4) state = 0;
+      else if (state < 10) state -= 3;
+      else state -= 6;
+    }
+    else             
+    {
+      UpdateBit1(prob);
+      prob = p + IsRep + state;
+      IfBit0(prob)
+      {
+        UpdateBit0(prob);
+        rep3 = rep2;
+        rep2 = rep1;
+        rep1 = rep0;
+        state = state < kNumLitStates ? 0 : 3;
+        prob = p + LenCoder;
+      }
+      else
+      {
+        UpdateBit1(prob);
+        prob = p + IsRepG0 + state;
+        IfBit0(prob)
+        {
+          UpdateBit0(prob);
+          prob = p + IsRep0Long + (state << kNumPosBitsMax) + posState;
+          IfBit0(prob)
+          {
+            #ifdef _LZMA_OUT_READ
+            UInt32 pos;
+            #endif
+            UpdateBit0(prob);
+            
+            #ifdef _LZMA_OUT_READ
+            if (distanceLimit == 0)
+            #else
+            if (nowPos == 0)
+            #endif
+              return LZMA_RESULT_DATA_ERROR;
+            
+            state = state < kNumLitStates ? 9 : 11;
+            #ifdef _LZMA_OUT_READ
+            pos = dictionaryPos - rep0;
+            if (pos >= dictionarySize)
+              pos += dictionarySize;
+            previousByte = dictionary[pos];
+            dictionary[dictionaryPos] = previousByte;
+            if (++dictionaryPos == dictionarySize)
+              dictionaryPos = 0;
+            #else
+            previousByte = outStream[nowPos - rep0];
+            #endif
+            outStream[nowPos++] = previousByte;
+            #ifdef _LZMA_OUT_READ
+            if (distanceLimit < dictionarySize)
+              distanceLimit++;
+            #endif
+
+            continue;
+          }
+          else
+          {
+            UpdateBit1(prob);
+          }
+        }
+        else
+        {
+          UInt32 distance;
+          UpdateBit1(prob);
+          prob = p + IsRepG1 + state;
+          IfBit0(prob)
+          {
+            UpdateBit0(prob);
+            distance = rep1;
+          }
+          else 
+          {
+            UpdateBit1(prob);
+            prob = p + IsRepG2 + state;
+            IfBit0(prob)
+            {
+              UpdateBit0(prob);
+              distance = rep2;
+            }
+            else
+            {
+              UpdateBit1(prob);
+              distance = rep3;
+              rep3 = rep2;
+            }
+            rep2 = rep1;
+          }
+          rep1 = rep0;
+          rep0 = distance;
+        }
+        state = state < kNumLitStates ? 8 : 11;
+        prob = p + RepLenCoder;
+      }
+      {
+        int numBits, offset;
+        CProb *probLen = prob + LenChoice;
+        IfBit0(probLen)
+        {
+          UpdateBit0(probLen);
+          probLen = prob + LenLow + (posState << kLenNumLowBits);
+          offset = 0;
+          numBits = kLenNumLowBits;
+        }
+        else
+        {
+          UpdateBit1(probLen);
+          probLen = prob + LenChoice2;
+          IfBit0(probLen)
+          {
+            UpdateBit0(probLen);
+            probLen = prob + LenMid + (posState << kLenNumMidBits);
+            offset = kLenNumLowSymbols;
+            numBits = kLenNumMidBits;
+          }
+          else
+          {
+            UpdateBit1(probLen);
+            probLen = prob + LenHigh;
+            offset = kLenNumLowSymbols + kLenNumMidSymbols;
+            numBits = kLenNumHighBits;
+          }
+        }
+        RangeDecoderBitTreeDecode(probLen, numBits, len);
+        len += offset;
+      }
+
+      if (state < 4)
+      {
+        int posSlot;
+        state += kNumLitStates;
+        prob = p + PosSlot +
+            ((len < kNumLenToPosStates ? len : kNumLenToPosStates - 1) << 
+            kNumPosSlotBits);
+        RangeDecoderBitTreeDecode(prob, kNumPosSlotBits, posSlot);
+        if (posSlot >= kStartPosModelIndex)
+        {
+          int numDirectBits = ((posSlot >> 1) - 1);
+          rep0 = (2 | ((UInt32)posSlot & 1));
+          if (posSlot < kEndPosModelIndex)
+          {
+            rep0 <<= numDirectBits;
+            prob = p + SpecPos + rep0 - posSlot - 1;
+          }
+          else
+          {
+            numDirectBits -= kNumAlignBits;
+            do
+            {
+              RC_NORMALIZE
+              Range >>= 1;
+              rep0 <<= 1;
+              if (Code >= Range)
+              {
+                Code -= Range;
+                rep0 |= 1;
+              }
+            }
+            while (--numDirectBits != 0);
+            prob = p + Align;
+            rep0 <<= kNumAlignBits;
+            numDirectBits = kNumAlignBits;
+          }
+          {
+            int i = 1;
+            int mi = 1;
+            do
+            {
+              CProb *prob3 = prob + mi;
+              RC_GET_BIT2(prob3, mi, ; , rep0 |= i);
+              i <<= 1;
+            }
+            while(--numDirectBits != 0);
+          }
+        }
+        else
+          rep0 = posSlot;
+        if (++rep0 == (UInt32)(0))
+        {
+          /* it's for stream version */
+          len = kLzmaStreamWasFinishedId;
+          break;
+        }
+      }
+
+      len += kMatchMinLen;
+      #ifdef _LZMA_OUT_READ
+      if (rep0 > distanceLimit) 
+      #else
+      if (rep0 > nowPos)
+      #endif
+        return LZMA_RESULT_DATA_ERROR;
+
+      #ifdef _LZMA_OUT_READ
+      if (dictionarySize - distanceLimit > (UInt32)len)
+        distanceLimit += len;
+      else
+        distanceLimit = dictionarySize;
+      #endif
+
+      do
+      {
+        #ifdef _LZMA_OUT_READ
+        UInt32 pos = dictionaryPos - rep0;
+        if (pos >= dictionarySize)
+          pos += dictionarySize;
+        previousByte = dictionary[pos];
+        dictionary[dictionaryPos] = previousByte;
+        if (++dictionaryPos == dictionarySize)
+          dictionaryPos = 0;
+        #else
+        previousByte = outStream[nowPos - rep0];
+        #endif
+        len--;
+        outStream[nowPos++] = previousByte;
+      }
+      while(len != 0 && nowPos < outSize);
+    }
+  }
+  RC_NORMALIZE;
+
+  #ifdef _LZMA_OUT_READ
+  vs->Range = Range;
+  vs->Code = Code;
+  vs->DictionaryPos = dictionaryPos;
+  vs->GlobalPos = globalPos + (UInt32)nowPos;
+  vs->DistanceLimit = distanceLimit;
+  vs->Reps[0] = rep0;
+  vs->Reps[1] = rep1;
+  vs->Reps[2] = rep2;
+  vs->Reps[3] = rep3;
+  vs->State = state;
+  vs->RemainLen = len;
+  vs->TempDictionary[0] = tempDictionary[0];
+  #endif
+
+  #ifdef _LZMA_IN_CB
+  vs->Buffer = Buffer;
+  vs->BufferLim = BufferLim;
+  #else
+  *inSizeProcessed = (SizeT)(Buffer - inStream);
+  #endif
+  *outSizeProcessed = nowPos;
+  return LZMA_RESULT_OK;
+}
diff --git a/target/linux/ramips/image/lzma-loader/src/LzmaDecode.h b/target/linux/ramips/image/lzma-loader/src/LzmaDecode.h
new file mode 100644 (file)
index 0000000..2870eeb
--- /dev/null
@@ -0,0 +1,113 @@
+/* 
+  LzmaDecode.h
+  LZMA Decoder interface
+
+  LZMA SDK 4.40 Copyright (c) 1999-2006 Igor Pavlov (2006-05-01)
+  http://www.7-zip.org/
+
+  LZMA SDK is licensed under two licenses:
+  1) GNU Lesser General Public License (GNU LGPL)
+  2) Common Public License (CPL)
+  It means that you can select one of these two licenses and 
+  follow rules of that license.
+
+  SPECIAL EXCEPTION:
+  Igor Pavlov, as the author of this code, expressly permits you to 
+  statically or dynamically link your code (or bind by name) to the 
+  interfaces of this file without subjecting your linked code to the 
+  terms of the CPL or GNU LGPL. Any modifications or additions 
+  to this file, however, are subject to the LGPL or CPL terms.
+*/
+
+#ifndef __LZMADECODE_H
+#define __LZMADECODE_H
+
+#include "LzmaTypes.h"
+
+/* #define _LZMA_IN_CB */
+/* Use callback for input data */
+
+/* #define _LZMA_OUT_READ */
+/* Use read function for output data */
+
+/* #define _LZMA_PROB32 */
+/* It can increase speed on some 32-bit CPUs, 
+   but memory usage will be doubled in that case */
+
+/* #define _LZMA_LOC_OPT */
+/* Enable local speed optimizations inside code */
+
+#ifdef _LZMA_PROB32
+#define CProb UInt32
+#else
+#define CProb UInt16
+#endif
+
+#define LZMA_RESULT_OK 0
+#define LZMA_RESULT_DATA_ERROR 1
+
+#ifdef _LZMA_IN_CB
+typedef struct _ILzmaInCallback
+{
+  int (*Read)(void *object, const unsigned char **buffer, SizeT *bufferSize);
+} ILzmaInCallback;
+#endif
+
+#define LZMA_BASE_SIZE 1846
+#define LZMA_LIT_SIZE 768
+
+#define LZMA_PROPERTIES_SIZE 5
+
+typedef struct _CLzmaProperties
+{
+  int lc;
+  int lp;
+  int pb;
+  #ifdef _LZMA_OUT_READ
+  UInt32 DictionarySize;
+  #endif
+}CLzmaProperties;
+
+int LzmaDecodeProperties(CLzmaProperties *propsRes, const unsigned char *propsData, int size);
+
+#define LzmaGetNumProbs(Properties) (LZMA_BASE_SIZE + (LZMA_LIT_SIZE << ((Properties)->lc + (Properties)->lp)))
+
+#define kLzmaNeedInitId (-2)
+
+typedef struct _CLzmaDecoderState
+{
+  CLzmaProperties Properties;
+  CProb *Probs;
+
+  #ifdef _LZMA_IN_CB
+  const unsigned char *Buffer;
+  const unsigned char *BufferLim;
+  #endif
+
+  #ifdef _LZMA_OUT_READ
+  unsigned char *Dictionary;
+  UInt32 Range;
+  UInt32 Code;
+  UInt32 DictionaryPos;
+  UInt32 GlobalPos;
+  UInt32 DistanceLimit;
+  UInt32 Reps[4];
+  int State;
+  int RemainLen;
+  unsigned char TempDictionary[4];
+  #endif
+} CLzmaDecoderState;
+
+#ifdef _LZMA_OUT_READ
+#define LzmaDecoderInit(vs) { (vs)->RemainLen = kLzmaNeedInitId; }
+#endif
+
+int LzmaDecode(CLzmaDecoderState *vs,
+    #ifdef _LZMA_IN_CB
+    ILzmaInCallback *inCallback,
+    #else
+    const unsigned char *inStream, SizeT inSize, SizeT *inSizeProcessed,
+    #endif
+    unsigned char *outStream, SizeT outSize, SizeT *outSizeProcessed);
+
+#endif
diff --git a/target/linux/ramips/image/lzma-loader/src/LzmaTypes.h b/target/linux/ramips/image/lzma-loader/src/LzmaTypes.h
new file mode 100644 (file)
index 0000000..9c27290
--- /dev/null
@@ -0,0 +1,45 @@
+/* 
+LzmaTypes.h 
+
+Types for LZMA Decoder
+
+This file written and distributed to public domain by Igor Pavlov.
+This file is part of LZMA SDK 4.40 (2006-05-01)
+*/
+
+#ifndef __LZMATYPES_H
+#define __LZMATYPES_H
+
+#ifndef _7ZIP_BYTE_DEFINED
+#define _7ZIP_BYTE_DEFINED
+typedef unsigned char Byte;
+#endif 
+
+#ifndef _7ZIP_UINT16_DEFINED
+#define _7ZIP_UINT16_DEFINED
+typedef unsigned short UInt16;
+#endif 
+
+#ifndef _7ZIP_UINT32_DEFINED
+#define _7ZIP_UINT32_DEFINED
+#ifdef _LZMA_UINT32_IS_ULONG
+typedef unsigned long UInt32;
+#else
+typedef unsigned int UInt32;
+#endif
+#endif 
+
+/* #define _LZMA_NO_SYSTEM_SIZE_T */
+/* You can use it, if you don't want <stddef.h> */
+
+#ifndef _7ZIP_SIZET_DEFINED
+#define _7ZIP_SIZET_DEFINED
+#ifdef _LZMA_NO_SYSTEM_SIZE_T
+typedef UInt32 SizeT;
+#else
+#include <stddef.h>
+typedef size_t SizeT;
+#endif
+#endif
+
+#endif
diff --git a/target/linux/ramips/image/lzma-loader/src/Makefile b/target/linux/ramips/image/lzma-loader/src/Makefile
new file mode 100644 (file)
index 0000000..f861666
--- /dev/null
@@ -0,0 +1,110 @@
+#
+# Makefile for the LZMA compressed kernel loader for
+# Atheros AR7XXX/AR9XXX based boards
+#
+# Copyright (C) 2011 Gabor Juhos <juhosg@openwrt.org>
+#
+# Some parts of this file was based on the OpenWrt specific lzma-loader
+# for the BCM47xx and ADM5120 based boards:
+#      Copyright (C) 2004 Manuel Novoa III (mjn3@codepoet.org)
+#      Copyright (C) 2005 Mineharu Takahara <mtakahar@yahoo.com>
+#      Copyright (C) 2005 by Oleg I. Vdovikin <oleg@cs.msu.su>
+#
+# This program is free software; you can redistribute it and/or modify it
+# under the terms of the GNU General Public License version 2 as published
+# by the Free Software Foundation.
+#
+
+LOADADDR       :=
+LZMA_TEXT_START        := 0x80a00000
+LOADER_DATA    :=
+BOARD          :=
+FLASH_OFFS     :=
+FLASH_MAX      :=
+PLATFORM       :=
+
+CC             := $(CROSS_COMPILE)gcc
+LD             := $(CROSS_COMPILE)ld
+OBJCOPY                := $(CROSS_COMPILE)objcopy
+OBJDUMP                := $(CROSS_COMPILE)objdump
+
+BIN_FLAGS      := -O binary -R .reginfo -R .note -R .comment -R .mdebug -S
+
+CFLAGS         = -D__KERNEL__ -Wall -Wstrict-prototypes -Wno-trigraphs -Os \
+                 -fno-strict-aliasing -fno-common -fomit-frame-pointer -G 0 \
+                 -mno-abicalls -fno-pic -ffunction-sections -pipe -mlong-calls \
+                 -fno-common -ffreestanding -fhonour-copts \
+                 -mabi=32 -march=mips32r2 \
+                 -Wa,-32 -Wa,-march=mips32r2 -Wa,-mips32r2 -Wa,--trap
+CFLAGS         += -D_LZMA_PROB32 -DARCH=$(PLATFORM)
+
+ASFLAGS                = $(CFLAGS) -D__ASSEMBLY__
+
+LDFLAGS                = -static --gc-sections -no-warn-mismatch
+LDFLAGS                += -e startup -T loader.lds -Ttext $(LZMA_TEXT_START)
+
+O_FORMAT       = $(shell $(OBJDUMP) -i | head -2 | grep elf32)
+
+OBJECTS                := head.o loader.o cache.o board-$(PLATFORM).o printf.o LzmaDecode.o
+
+include $(PLATFORM).mk
+CFLAGS+=$(CACHE_FLAGS)
+ASFLAGS+=$(CACHE_FLAGS)
+
+ifneq ($(strip $(LOADER_DATA)),)
+OBJECTS                += data.o
+CFLAGS         += -DLZMA_WRAPPER=1 -DLOADADDR=$(LOADADDR)
+endif
+
+ifneq ($(strip $(KERNEL_CMDLINE)),)
+CFLAGS         += -DCONFIG_KERNEL_CMDLINE='"$(KERNEL_CMDLINE)"'
+endif
+
+ifneq ($(strip $(FLASH_OFFS)),)
+CFLAGS         += -DCONFIG_FLASH_OFFS=$(FLASH_OFFS)
+endif
+
+ifneq ($(strip $(FLASH_MAX)),)
+CFLAGS         += -DCONFIG_FLASH_MAX=$(FLASH_MAX)
+endif
+
+BOARD_DEF := $(shell echo $(strip $(BOARD)) | tr a-z A-Z | tr - _)
+ifneq ($(BOARD_DEF),)
+CFLAGS         += -DCONFIG_BOARD_$(BOARD_DEF)
+endif
+
+all: loader.elf
+
+# Don't build dependencies, this may die if $(CC) isn't gcc
+dep:
+
+install:
+
+%.o : %.c
+       $(CC) $(CFLAGS) -c -o $@ $<
+
+%.o : %.S
+       $(CC) $(ASFLAGS) -c -o $@ $<
+
+data.o: $(LOADER_DATA)
+       $(LD) -r -b binary --oformat $(O_FORMAT) -T lzma-data.lds -o $@ $<
+
+loader: $(OBJECTS)
+       $(LD) $(LDFLAGS) -o $@ $(OBJECTS)
+
+loader.bin: loader
+       $(OBJCOPY) $(BIN_FLAGS) $< $@
+
+loader2.o: loader.bin
+       $(LD) -r -b binary --oformat $(O_FORMAT) -o $@ $<
+
+loader.elf: loader2.o
+       $(LD) -e startup -T loader2.lds -Ttext $(LOADADDR) -o $@ $<
+
+mrproper: clean
+
+clean:
+       rm -f loader *.elf *.bin *.o
+
+
+
diff --git a/target/linux/ramips/image/lzma-loader/src/board-ralink.c b/target/linux/ramips/image/lzma-loader/src/board-ralink.c
new file mode 100644 (file)
index 0000000..7c947ec
--- /dev/null
@@ -0,0 +1,42 @@
+/*
+ * Arch specific code for Ralink based boards
+ *
+ * Copyright (C) 2013 John Crispin <blogic@openwrt.org>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ */
+
+#include <stddef.h>
+#include "config.h"
+
+#define READREG(r)             *(volatile unsigned int *)(r)
+#define WRITEREG(r,v)          *(volatile unsigned int *)(r) = v
+
+#define KSEG1ADDR(_x)          (((_x) & 0x1fffffff) | 0xa0000000)
+
+#ifdef CONFIG_SOC_RT288X
+#define UART_BASE              0xb0300c00
+#else
+#define UART_BASE              0xb0000c00
+#endif
+
+#define UART_TX                        1
+#define UART_LSR               7
+
+#define UART_LSR_THRE          0x20
+
+#define UART_READ(r)           READREG(UART_BASE + 4 * (r))
+#define UART_WRITE(r,v)                WRITEREG(UART_BASE + 4 * (r), (v))
+
+void board_putc(int ch)
+{
+       while (((UART_READ(UART_LSR)) & UART_LSR_THRE) == 0);
+       UART_WRITE(UART_TX, ch);
+       while (((UART_READ(UART_LSR)) & UART_LSR_THRE) == 0);
+}
+
+void board_init(void)
+{
+}
diff --git a/target/linux/ramips/image/lzma-loader/src/cache.c b/target/linux/ramips/image/lzma-loader/src/cache.c
new file mode 100644 (file)
index 0000000..28cc848
--- /dev/null
@@ -0,0 +1,43 @@
+/*
+ * LZMA compressed kernel loader for Atheros AR7XXX/AR9XXX based boards
+ *
+ * Copyright (C) 2011 Gabor Juhos <juhosg@openwrt.org>
+ *
+ * The cache manipulation routine has been taken from the U-Boot project.
+ *     (C) Copyright 2003
+ *     Wolfgang Denk, DENX Software Engineering, <wd@denx.de>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ *
+ */
+
+#include "cache.h"
+#include "cacheops.h"
+#include "config.h"
+
+#define cache_op(op,addr)                                              \
+       __asm__ __volatile__(                                           \
+       "       .set    push                                    \n"     \
+       "       .set    noreorder                               \n"     \
+       "       .set    mips3\n\t                               \n"     \
+       "       cache   %0, %1                                  \n"     \
+       "       .set    pop                                     \n"     \
+       :                                                               \
+       : "i" (op), "R" (*(unsigned char *)(addr)))
+
+void flush_cache(unsigned long start_addr, unsigned long size)
+{
+       unsigned long lsize = CONFIG_CACHELINE_SIZE;
+       unsigned long addr = start_addr & ~(lsize - 1);
+       unsigned long aend = (start_addr + size - 1) & ~(lsize - 1);
+
+       while (1) {
+               cache_op(Hit_Writeback_Inv_D, addr);
+               cache_op(Hit_Invalidate_I, addr);
+               if (addr == aend)
+                       break;
+               addr += lsize;
+       }
+}
diff --git a/target/linux/ramips/image/lzma-loader/src/cache.h b/target/linux/ramips/image/lzma-loader/src/cache.h
new file mode 100644 (file)
index 0000000..506a235
--- /dev/null
@@ -0,0 +1,17 @@
+/*
+ * LZMA compressed kernel loader for Atheros AR7XXX/AR9XXX based boards
+ *
+ * Copyright (C) 2011 Gabor Juhos <juhosg@openwrt.org>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ *
+ */
+
+#ifndef __CACHE_H
+#define __CACHE_H
+
+void flush_cache(unsigned long start_addr, unsigned long size);
+
+#endif /* __CACHE_H */
diff --git a/target/linux/ramips/image/lzma-loader/src/cacheops.h b/target/linux/ramips/image/lzma-loader/src/cacheops.h
new file mode 100644 (file)
index 0000000..70bcad7
--- /dev/null
@@ -0,0 +1,85 @@
+/*
+ * Cache operations for the cache instruction.
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * (C) Copyright 1996, 97, 99, 2002, 03 Ralf Baechle
+ * (C) Copyright 1999 Silicon Graphics, Inc.
+ */
+#ifndef        __ASM_CACHEOPS_H
+#define        __ASM_CACHEOPS_H
+
+/*
+ * Cache Operations available on all MIPS processors with R4000-style caches
+ */
+#define Index_Invalidate_I      0x00
+#define Index_Writeback_Inv_D   0x01
+#define Index_Load_Tag_I       0x04
+#define Index_Load_Tag_D       0x05
+#define Index_Store_Tag_I      0x08
+#define Index_Store_Tag_D      0x09
+#if defined(CONFIG_CPU_LOONGSON2)
+#define Hit_Invalidate_I       0x00
+#else
+#define Hit_Invalidate_I       0x10
+#endif
+#define Hit_Invalidate_D       0x11
+#define Hit_Writeback_Inv_D    0x15
+
+/*
+ * R4000-specific cacheops
+ */
+#define Create_Dirty_Excl_D    0x0d
+#define Fill                   0x14
+#define Hit_Writeback_I                0x18
+#define Hit_Writeback_D                0x19
+
+/*
+ * R4000SC and R4400SC-specific cacheops
+ */
+#define Index_Invalidate_SI     0x02
+#define Index_Writeback_Inv_SD  0x03
+#define Index_Load_Tag_SI      0x06
+#define Index_Load_Tag_SD      0x07
+#define Index_Store_Tag_SI     0x0A
+#define Index_Store_Tag_SD     0x0B
+#define Create_Dirty_Excl_SD   0x0f
+#define Hit_Invalidate_SI      0x12
+#define Hit_Invalidate_SD      0x13
+#define Hit_Writeback_Inv_SD   0x17
+#define Hit_Writeback_SD       0x1b
+#define Hit_Set_Virtual_SI     0x1e
+#define Hit_Set_Virtual_SD     0x1f
+
+/*
+ * R5000-specific cacheops
+ */
+#define R5K_Page_Invalidate_S  0x17
+
+/*
+ * RM7000-specific cacheops
+ */
+#define Page_Invalidate_T      0x16
+
+/*
+ * R10000-specific cacheops
+ *
+ * Cacheops 0x02, 0x06, 0x0a, 0x0c-0x0e, 0x16, 0x1a and 0x1e are unused.
+ * Most of the _S cacheops are identical to the R4000SC _SD cacheops.
+ */
+#define Index_Writeback_Inv_S  0x03
+#define Index_Load_Tag_S       0x07
+#define Index_Store_Tag_S      0x0B
+#define Hit_Invalidate_S       0x13
+#define Cache_Barrier          0x14
+#define Hit_Writeback_Inv_S    0x17
+#define Index_Load_Data_I      0x18
+#define Index_Load_Data_D      0x19
+#define Index_Load_Data_S      0x1b
+#define Index_Store_Data_I     0x1c
+#define Index_Store_Data_D     0x1d
+#define Index_Store_Data_S     0x1f
+
+#endif /* __ASM_CACHEOPS_H */
diff --git a/target/linux/ramips/image/lzma-loader/src/config.h b/target/linux/ramips/image/lzma-loader/src/config.h
new file mode 100644 (file)
index 0000000..b7719e9
--- /dev/null
@@ -0,0 +1,27 @@
+/*
+ * LZMA compressed kernel loader for Atheros AR7XXX/AR9XXX based boards
+ *
+ * Copyright (C) 2011 Gabor Juhos <juhosg@openwrt.org>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ *
+ */
+
+#ifndef _CONFIG_H_
+#define _CONFIG_H_
+
+#ifndef CONFIG_FLASH_OFFS
+#define CONFIG_FLASH_OFFS      0
+#endif
+
+#ifndef CONFIG_FLASH_MAX
+#define CONFIG_FLASH_MAX       0
+#endif
+
+#ifndef CONFIG_FLASH_STEP
+#define CONFIG_FLASH_STEP      0x1000
+#endif
+
+#endif /* _CONFIG_H_ */
diff --git a/target/linux/ramips/image/lzma-loader/src/cp0regdef.h b/target/linux/ramips/image/lzma-loader/src/cp0regdef.h
new file mode 100644 (file)
index 0000000..c1188ad
--- /dev/null
@@ -0,0 +1,39 @@
+/*
+ * Copyright (C) 1994, 1995, 1996, 1997, 2000, 2001 by Ralf Baechle
+ *
+ * Copyright (C) 2001, Monta Vista Software
+ * Author: jsun@mvista.com or jsun@junsun.net
+ */
+#ifndef _cp0regdef_h_
+#define _cp0regdef_h_
+
+#define CP0_INDEX $0
+#define CP0_RANDOM $1
+#define CP0_ENTRYLO0 $2
+#define CP0_ENTRYLO1 $3
+#define CP0_CONTEXT $4
+#define CP0_PAGEMASK $5
+#define CP0_WIRED $6
+#define CP0_BADVADDR $8
+#define CP0_COUNT $9
+#define CP0_ENTRYHI $10
+#define CP0_COMPARE $11
+#define CP0_STATUS $12
+#define CP0_CAUSE $13
+#define CP0_EPC $14
+#define CP0_PRID $15
+#define CP0_CONFIG $16
+#define CP0_LLADDR $17
+#define CP0_WATCHLO $18
+#define CP0_WATCHHI $19
+#define CP0_XCONTEXT $20
+#define CP0_FRAMEMASK $21
+#define CP0_DIAGNOSTIC $22
+#define CP0_PERFORMANCE $25
+#define CP0_ECC $26
+#define CP0_CACHEERR $27
+#define CP0_TAGLO $28
+#define CP0_TAGHI $29
+#define CP0_ERROREPC $30
+
+#endif
diff --git a/target/linux/ramips/image/lzma-loader/src/head.S b/target/linux/ramips/image/lzma-loader/src/head.S
new file mode 100644 (file)
index 0000000..543996a
--- /dev/null
@@ -0,0 +1,118 @@
+/*
+ * LZMA compressed kernel loader for Atheros AR7XXX/AR9XXX based boards
+ *
+ * Copyright (C) 2011 Gabor Juhos <juhosg@openwrt.org>
+ *
+ * Some parts of this code was based on the OpenWrt specific lzma-loader
+ * for the BCM47xx and ADM5120 based boards:
+ *     Copyright (C) 2004 Manuel Novoa III (mjn3@codepoet.org)
+ *     Copyright (C) 2005 by Oleg I. Vdovikin <oleg@cs.msu.su>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ */
+
+#include <asm/asm.h>
+#include <asm/regdef.h>
+#include "cp0regdef.h"
+#include "cacheops.h"
+#include "config.h"
+
+#define KSEG0          0x80000000
+
+       .macro  ehb
+       sll     zero, 3
+       .endm
+
+       .text
+
+LEAF(startup)
+       .set noreorder
+       .set mips32
+
+       mtc0    zero, CP0_WATCHLO       # clear watch registers
+       mtc0    zero, CP0_WATCHHI
+       mtc0    zero, CP0_CAUSE         # clear before writing status register
+
+       mfc0    t0, CP0_STATUS
+       li      t1, 0x1000001f
+       or      t0, t1
+       xori    t0, 0x1f
+       mtc0    t0, CP0_STATUS
+       ehb
+
+       mtc0    zero, CP0_COUNT
+       mtc0    zero, CP0_COMPARE
+       ehb
+
+       la      t0, __reloc_label       # get linked address of label
+       bal     __reloc_label           # branch and link to label to
+       nop                             # get actual address
+__reloc_label:
+       subu    t0, ra, t0              # get reloc_delta
+
+       beqz    t0, __reloc_done         # if delta is 0 we are in the right place
+       nop
+
+       /* Copy our code to the right place */
+       la      t1, _code_start         # get linked address of _code_start
+       la      t2, _code_end           # get linked address of _code_end
+       addu    t0, t0, t1              # calculate actual address of _code_start
+
+__reloc_copy:
+       lw      t3, 0(t0)
+       sw      t3, 0(t1)
+       add     t1, 4
+       blt     t1, t2, __reloc_copy
+       add     t0, 4
+
+       /* flush cache */
+       la      t0, _code_start
+       la      t1, _code_end
+
+       li      t2, ~(CONFIG_CACHELINE_SIZE - 1)
+       and     t0, t2
+       and     t1, t2
+       li      t2, CONFIG_CACHELINE_SIZE
+
+       b       __flush_check
+       nop
+
+__flush_line:
+       cache   Hit_Writeback_Inv_D, 0(t0)
+       cache   Hit_Invalidate_I, 0(t0)
+       add     t0, t2
+
+__flush_check:
+       bne     t0, t1, __flush_line
+       nop
+
+       sync
+
+__reloc_done:
+
+       /* clear bss */
+       la      t0, _bss_start
+       la      t1, _bss_end
+       b       __bss_check
+       nop
+
+__bss_fill:
+       sw      zero, 0(t0)
+       addi    t0, 4
+
+__bss_check:
+       bne     t0, t1, __bss_fill
+       nop
+
+       /* Setup new "C" stack */
+       la      sp, _stack
+
+       /* jump to the decompressor routine */
+       la      t0, loader_main
+       jr      t0
+       nop
+
+       .set reorder
+END(startup)
diff --git a/target/linux/ramips/image/lzma-loader/src/lantiq.mk b/target/linux/ramips/image/lzma-loader/src/lantiq.mk
new file mode 100644 (file)
index 0000000..4137645
--- /dev/null
@@ -0,0 +1 @@
+CACHE_FLAGS+=-DCONFIG_ICACHE_SIZE="(32 * 1024)" -DCONFIG_DCACHE_SIZE="(32 * 1024)" -DCONFIG_CACHELINE_SIZE=32
diff --git a/target/linux/ramips/image/lzma-loader/src/loader.c b/target/linux/ramips/image/lzma-loader/src/loader.c
new file mode 100644 (file)
index 0000000..1d42bfa
--- /dev/null
@@ -0,0 +1,263 @@
+/*
+ * LZMA compressed kernel loader for Atheros AR7XXX/AR9XXX based boards
+ *
+ * Copyright (C) 2011 Gabor Juhos <juhosg@openwrt.org>
+ *
+ * Some parts of this code was based on the OpenWrt specific lzma-loader
+ * for the BCM47xx and ADM5120 based boards:
+ *     Copyright (C) 2004 Manuel Novoa III (mjn3@codepoet.org)
+ *     Copyright (C) 2005 Mineharu Takahara <mtakahar@yahoo.com>
+ *     Copyright (C) 2005 by Oleg I. Vdovikin <oleg@cs.msu.su>
+ *
+ * The image_header structure has been taken from the U-Boot project.
+ *     (C) Copyright 2008 Semihalf
+ *     (C) Copyright 2000-2005
+ *     Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ */
+
+#include <stddef.h>
+#include <stdint.h>
+
+#include "config.h"
+#include "cache.h"
+#include "printf.h"
+#include "LzmaDecode.h"
+
+#define AR71XX_FLASH_START     0x1f000000
+#define AR71XX_FLASH_END       0x1fe00000
+
+#define KSEG0                  0x80000000
+#define KSEG1                  0xa0000000
+
+#define KSEG1ADDR(a)           ((((unsigned)(a)) & 0x1fffffffU) | KSEG1)
+
+#undef LZMA_DEBUG
+
+#ifdef LZMA_DEBUG
+#  define DBG(f, a...) printf(f, ## a)
+#else
+#  define DBG(f, a...) do {} while (0)
+#endif
+
+#define IH_MAGIC_OKLI          0x4f4b4c49      /* 'OKLI' */
+
+#define IH_NMLEN               32      /* Image Name Length            */
+
+typedef struct image_header {
+       uint32_t        ih_magic;       /* Image Header Magic Number    */
+       uint32_t        ih_hcrc;        /* Image Header CRC Checksum    */
+       uint32_t        ih_time;        /* Image Creation Timestamp     */
+       uint32_t        ih_size;        /* Image Data Size              */
+       uint32_t        ih_load;        /* Data  Load  Address          */
+       uint32_t        ih_ep;          /* Entry Point Address          */
+       uint32_t        ih_dcrc;        /* Image Data CRC Checksum      */
+       uint8_t         ih_os;          /* Operating System             */
+       uint8_t         ih_arch;        /* CPU architecture             */
+       uint8_t         ih_type;        /* Image Type                   */
+       uint8_t         ih_comp;        /* Compression Type             */
+       uint8_t         ih_name[IH_NMLEN];      /* Image Name           */
+} image_header_t;
+
+/* beyond the image end, size not known in advance */
+extern unsigned char workspace[];
+extern void board_init(void);
+
+static CLzmaDecoderState lzma_state;
+static unsigned char *lzma_data;
+static unsigned long lzma_datasize;
+static unsigned long lzma_outsize;
+static unsigned long kernel_la;
+
+#ifdef CONFIG_KERNEL_CMDLINE
+#define kernel_argc    1
+static const char kernel_cmdline[] = CONFIG_KERNEL_CMDLINE;
+static const char *kernel_argv[] = {
+       kernel_cmdline,
+       NULL,
+};
+#endif /* CONFIG_KERNEL_CMDLINE */
+
+static void halt(void)
+{
+       printf("\nSystem halted!\n");
+       for(;;);
+}
+
+static __inline__ unsigned long get_be32(void *buf)
+{
+       unsigned char *p = buf;
+
+       return (((unsigned long) p[0] << 24) +
+               ((unsigned long) p[1] << 16) +
+               ((unsigned long) p[2] << 8) +
+               (unsigned long) p[3]);
+}
+
+static __inline__ unsigned char lzma_get_byte(void)
+{
+       unsigned char c;
+
+       lzma_datasize--;
+       c = *lzma_data++;
+
+       return c;
+}
+
+static int lzma_init_props(void)
+{
+       unsigned char props[LZMA_PROPERTIES_SIZE];
+       int res;
+       int i;
+
+       /* read lzma properties */
+       for (i = 0; i < LZMA_PROPERTIES_SIZE; i++)
+               props[i] = lzma_get_byte();
+
+       /* read the lower half of uncompressed size in the header */
+       lzma_outsize = ((SizeT) lzma_get_byte()) +
+                      ((SizeT) lzma_get_byte() << 8) +
+                      ((SizeT) lzma_get_byte() << 16) +
+                      ((SizeT) lzma_get_byte() << 24);
+
+       /* skip rest of the header (upper half of uncompressed size) */
+       for (i = 0; i < 4; i++)
+               lzma_get_byte();
+
+       res = LzmaDecodeProperties(&lzma_state.Properties, props,
+                                       LZMA_PROPERTIES_SIZE);
+       return res;
+}
+
+static int lzma_decompress(unsigned char *outStream)
+{
+       SizeT ip, op;
+       int ret;
+
+       lzma_state.Probs = (CProb *) workspace;
+
+       ret = LzmaDecode(&lzma_state, lzma_data, lzma_datasize, &ip, outStream,
+                        lzma_outsize, &op);
+
+       if (ret != LZMA_RESULT_OK) {
+               int i;
+
+               DBG("LzmaDecode error %d at %08x, osize:%d ip:%d op:%d\n",
+                   ret, lzma_data + ip, lzma_outsize, ip, op);
+
+               for (i = 0; i < 16; i++)
+                       DBG("%02x ", lzma_data[ip + i]);
+
+               DBG("\n");
+       }
+
+       return ret;
+}
+
+#if (LZMA_WRAPPER)
+static void lzma_init_data(void)
+{
+       extern unsigned char _lzma_data_start[];
+       extern unsigned char _lzma_data_end[];
+
+       kernel_la = LOADADDR;
+       lzma_data = _lzma_data_start;
+       lzma_datasize = _lzma_data_end - _lzma_data_start;
+}
+#else
+static void lzma_init_data(void)
+{
+       struct image_header *hdr = NULL;
+       unsigned char *flash_base;
+       unsigned long flash_ofs;
+       unsigned long kernel_ofs;
+       unsigned long kernel_size;
+
+       flash_base = (unsigned char *) KSEG1ADDR(AR71XX_FLASH_START);
+
+       printf("Looking for OpenWrt image... ");
+
+       for (flash_ofs = CONFIG_FLASH_OFFS;
+            flash_ofs <= (CONFIG_FLASH_OFFS + CONFIG_FLASH_MAX);
+            flash_ofs += CONFIG_FLASH_STEP) {
+               unsigned long magic;
+               unsigned char *p;
+
+               p = flash_base + flash_ofs;
+               magic = get_be32(p);
+               if (magic == IH_MAGIC_OKLI) {
+                       hdr = (struct image_header *) p;
+                       break;
+               }
+       }
+
+       if (hdr == NULL) {
+               printf("not found!\n");
+               halt();
+       }
+
+       printf("found at 0x%08x\n", flash_base + flash_ofs);
+
+       kernel_ofs = sizeof(struct image_header);
+       kernel_size = get_be32(&hdr->ih_size);
+       kernel_la = get_be32(&hdr->ih_load);
+
+       lzma_data = flash_base + flash_ofs + kernel_ofs;
+       lzma_datasize = kernel_size;
+}
+#endif /* (LZMA_WRAPPER) */
+
+void loader_main(unsigned long reg_a0, unsigned long reg_a1,
+                unsigned long reg_a2, unsigned long reg_a3)
+{
+       void (*kernel_entry) (unsigned long, unsigned long, unsigned long,
+                             unsigned long);
+       int res;
+
+       board_init();
+
+       printf("\n\nOpenWrt kernel loader for MIPS based SoC\n");
+       printf("Copyright (C) 2011 Gabor Juhos <juhosg@openwrt.org>\n");
+
+       lzma_init_data();
+
+       res = lzma_init_props();
+       if (res != LZMA_RESULT_OK) {
+               printf("Incorrect LZMA stream properties!\n");
+               halt();
+       }
+
+       printf("Decompressing kernel... ");
+
+       res = lzma_decompress((unsigned char *) kernel_la);
+       if (res != LZMA_RESULT_OK) {
+               printf("failed, ");
+               switch (res) {
+               case LZMA_RESULT_DATA_ERROR:
+                       printf("data error!\n");
+                       break;
+               default:
+                       printf("unknown error %d!\n", res);
+               }
+               halt();
+       } else {
+               printf("done!\n");
+       }
+
+       flush_cache(kernel_la, lzma_outsize);
+
+       printf("Starting kernel at %08x...\n\n", kernel_la);
+
+#ifdef CONFIG_KERNEL_CMDLINE
+       reg_a0 = kernel_argc;
+       reg_a1 = (unsigned long) kernel_argv;
+       reg_a2 = 0;
+       reg_a3 = 0;
+#endif
+
+       kernel_entry = (void *) kernel_la;
+       kernel_entry(reg_a0, reg_a1, reg_a2, reg_a3);
+}
diff --git a/target/linux/ramips/image/lzma-loader/src/loader.lds b/target/linux/ramips/image/lzma-loader/src/loader.lds
new file mode 100644 (file)
index 0000000..80cc7ca
--- /dev/null
@@ -0,0 +1,35 @@
+OUTPUT_ARCH(mips)
+SECTIONS {
+       .text : {
+               _code_start = .;
+               *(.text)
+               *(.text.*)
+               *(.rodata)
+               *(.rodata.*)
+               *(.data.lzma)
+       }
+
+       . = ALIGN(32);
+       .data : {
+               *(.data)
+               *(.data.*)
+               . = . + 524288;         /* workaround for buggy bootloaders */
+       }
+
+       . = ALIGN(32);
+       _code_end = .;
+
+       _bss_start = .;
+       .bss : {
+               *(.bss)
+               *(.bss.*)
+       }
+
+       . = ALIGN(32);
+       _bss_end = .;
+
+       . = . + 8192;
+       _stack = .;
+
+       workspace = .;
+}
diff --git a/target/linux/ramips/image/lzma-loader/src/loader2.lds b/target/linux/ramips/image/lzma-loader/src/loader2.lds
new file mode 100644 (file)
index 0000000..db0bb46
--- /dev/null
@@ -0,0 +1,10 @@
+OUTPUT_ARCH(mips)
+SECTIONS {
+       .text : {
+               startup = .;
+               *(.text)
+               *(.text.*)
+               *(.data)
+               *(.data.*)
+       }
+}
diff --git a/target/linux/ramips/image/lzma-loader/src/lzma-data.lds b/target/linux/ramips/image/lzma-loader/src/lzma-data.lds
new file mode 100644 (file)
index 0000000..abf756b
--- /dev/null
@@ -0,0 +1,8 @@
+OUTPUT_ARCH(mips)
+SECTIONS {
+       .data.lzma : {
+               _lzma_data_start = .;
+               *(.data)
+               _lzma_data_end = .;
+       }
+}
diff --git a/target/linux/ramips/image/lzma-loader/src/printf.c b/target/linux/ramips/image/lzma-loader/src/printf.c
new file mode 100644 (file)
index 0000000..7bb5a86
--- /dev/null
@@ -0,0 +1,350 @@
+/*
+ * Copyright (C) 2001 MontaVista Software Inc.
+ * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ *
+ */
+
+#include       "printf.h"
+
+extern void board_putc(int ch);
+
+/* this is the maximum width for a variable */
+#define                LP_MAX_BUF      256
+
+/* macros */
+#define                IsDigit(x)      ( ((x) >= '0') && ((x) <= '9') )
+#define                Ctod(x)         ( (x) - '0')
+
+/* forward declaration */
+static int PrintChar(char *, char, int, int);
+static int PrintString(char *, char *, int, int);
+static int PrintNum(char *, unsigned long, int, int, int, int, char, int);
+
+/* private variable */
+static const char theFatalMsg[] = "fatal error in lp_Print!";
+
+/* -*-
+ * A low level printf() function.
+ */
+static void
+lp_Print(void (*output)(void *, char *, int),
+        void * arg,
+        char *fmt,
+        va_list ap)
+{
+
+#define        OUTPUT(arg, s, l)  \
+  { if (((l) < 0) || ((l) > LP_MAX_BUF)) { \
+       (*output)(arg, (char*)theFatalMsg, sizeof(theFatalMsg)-1); for(;;); \
+    } else { \
+      (*output)(arg, s, l); \
+    } \
+  }
+
+    char buf[LP_MAX_BUF];
+
+    char c;
+    char *s;
+    long int num;
+
+    int longFlag;
+    int negFlag;
+    int width;
+    int prec;
+    int ladjust;
+    char padc;
+
+    int length;
+
+    for(;;) {
+       {
+           /* scan for the next '%' */
+           char *fmtStart = fmt;
+           while ( (*fmt != '\0') && (*fmt != '%')) {
+               fmt ++;
+           }
+
+           /* flush the string found so far */
+           OUTPUT(arg, fmtStart, fmt-fmtStart);
+
+           /* are we hitting the end? */
+           if (*fmt == '\0') break;
+       }
+
+       /* we found a '%' */
+       fmt ++;
+
+       /* check for long */
+       if (*fmt == 'l') {
+           longFlag = 1;
+           fmt ++;
+       } else {
+           longFlag = 0;
+       }
+
+       /* check for other prefixes */
+       width = 0;
+       prec = -1;
+       ladjust = 0;
+       padc = ' ';
+
+       if (*fmt == '-') {
+           ladjust = 1;
+           fmt ++;
+       }
+
+       if (*fmt == '0') {
+           padc = '0';
+           fmt++;
+       }
+
+       if (IsDigit(*fmt)) {
+           while (IsDigit(*fmt)) {
+               width = 10 * width + Ctod(*fmt++);
+           }
+       }
+
+       if (*fmt == '.') {
+           fmt ++;
+           if (IsDigit(*fmt)) {
+               prec = 0;
+               while (IsDigit(*fmt)) {
+                   prec = prec*10 + Ctod(*fmt++);
+               }
+           }
+       }
+
+
+       /* check format flag */
+       negFlag = 0;
+       switch (*fmt) {
+        case 'b':
+           if (longFlag) {
+               num = va_arg(ap, long int);
+           } else {
+               num = va_arg(ap, int);
+           }
+           length = PrintNum(buf, num, 2, 0, width, ladjust, padc, 0);
+           OUTPUT(arg, buf, length);
+           break;
+
+        case 'd':
+        case 'D':
+           if (longFlag) {
+               num = va_arg(ap, long int);
+           } else {
+               num = va_arg(ap, int);
+           }
+           if (num < 0) {
+               num = - num;
+               negFlag = 1;
+           }
+           length = PrintNum(buf, num, 10, negFlag, width, ladjust, padc, 0);
+           OUTPUT(arg, buf, length);
+           break;
+
+        case 'o':
+        case 'O':
+           if (longFlag) {
+               num = va_arg(ap, long int);
+           } else {
+               num = va_arg(ap, int);
+           }
+           length = PrintNum(buf, num, 8, 0, width, ladjust, padc, 0);
+           OUTPUT(arg, buf, length);
+           break;
+
+        case 'u':
+        case 'U':
+           if (longFlag) {
+               num = va_arg(ap, long int);
+           } else {
+               num = va_arg(ap, int);
+           }
+           length = PrintNum(buf, num, 10, 0, width, ladjust, padc, 0);
+           OUTPUT(arg, buf, length);
+           break;
+
+        case 'x':
+           if (longFlag) {
+               num = va_arg(ap, long int);
+           } else {
+               num = va_arg(ap, int);
+           }
+           length = PrintNum(buf, num, 16, 0, width, ladjust, padc, 0);
+           OUTPUT(arg, buf, length);
+           break;
+
+        case 'X':
+           if (longFlag) {
+               num = va_arg(ap, long int);
+           } else {
+               num = va_arg(ap, int);
+           }
+           length = PrintNum(buf, num, 16, 0, width, ladjust, padc, 1);
+           OUTPUT(arg, buf, length);
+           break;
+
+        case 'c':
+           c = (char)va_arg(ap, int);
+           length = PrintChar(buf, c, width, ladjust);
+           OUTPUT(arg, buf, length);
+           break;
+
+        case 's':
+           s = (char*)va_arg(ap, char *);
+           length = PrintString(buf, s, width, ladjust);
+           OUTPUT(arg, buf, length);
+           break;
+
+        case '\0':
+           fmt --;
+           break;
+
+        default:
+           /* output this char as it is */
+           OUTPUT(arg, fmt, 1);
+       }       /* switch (*fmt) */
+
+       fmt ++;
+    }          /* for(;;) */
+
+    /* special termination call */
+    OUTPUT(arg, "\0", 1);
+}
+
+
+/* --------------- local help functions --------------------- */
+static int
+PrintChar(char * buf, char c, int length, int ladjust)
+{
+    int i;
+
+    if (length < 1) length = 1;
+    if (ladjust) {
+       *buf = c;
+       for (i=1; i< length; i++) buf[i] = ' ';
+    } else {
+       for (i=0; i< length-1; i++) buf[i] = ' ';
+       buf[length - 1] = c;
+    }
+    return length;
+}
+
+static int
+PrintString(char * buf, char* s, int length, int ladjust)
+{
+    int i;
+    int len=0;
+    char* s1 = s;
+    while (*s1++) len++;
+    if (length < len) length = len;
+
+    if (ladjust) {
+       for (i=0; i< len; i++) buf[i] = s[i];
+       for (i=len; i< length; i++) buf[i] = ' ';
+    } else {
+       for (i=0; i< length-len; i++) buf[i] = ' ';
+       for (i=length-len; i < length; i++) buf[i] = s[i-length+len];
+    }
+    return length;
+}
+
+static int
+PrintNum(char * buf, unsigned long u, int base, int negFlag,
+        int length, int ladjust, char padc, int upcase)
+{
+    /* algorithm :
+     *  1. prints the number from left to right in reverse form.
+     *  2. fill the remaining spaces with padc if length is longer than
+     *     the actual length
+     *     TRICKY : if left adjusted, no "0" padding.
+     *             if negtive, insert  "0" padding between "0" and number.
+     *  3. if (!ladjust) we reverse the whole string including paddings
+     *  4. otherwise we only reverse the actual string representing the num.
+     */
+
+    int actualLength =0;
+    char *p = buf;
+    int i;
+
+    do {
+       int tmp = u %base;
+       if (tmp <= 9) {
+           *p++ = '0' + tmp;
+       } else if (upcase) {
+           *p++ = 'A' + tmp - 10;
+       } else {
+           *p++ = 'a' + tmp - 10;
+       }
+       u /= base;
+    } while (u != 0);
+
+    if (negFlag) {
+       *p++ = '-';
+    }
+
+    /* figure out actual length and adjust the maximum length */
+    actualLength = p - buf;
+    if (length < actualLength) length = actualLength;
+
+    /* add padding */
+    if (ladjust) {
+       padc = ' ';
+    }
+    if (negFlag && !ladjust && (padc == '0')) {
+       for (i = actualLength-1; i< length-1; i++) buf[i] = padc;
+       buf[length -1] = '-';
+    } else {
+       for (i = actualLength; i< length; i++) buf[i] = padc;
+    }
+
+
+    /* prepare to reverse the string */
+    {
+       int begin = 0;
+       int end;
+       if (ladjust) {
+           end = actualLength - 1;
+       } else {
+           end = length -1;
+       }
+
+       while (end > begin) {
+           char tmp = buf[begin];
+           buf[begin] = buf[end];
+           buf[end] = tmp;
+           begin ++;
+           end --;
+       }
+    }
+
+    /* adjust the string pointer */
+    return length;
+}
+
+static void printf_output(void *arg, char *s, int l)
+{
+    int i;
+
+    // special termination call
+    if ((l==1) && (s[0] == '\0')) return;
+
+    for (i=0; i< l; i++) {
+       board_putc(s[i]);
+       if (s[i] == '\n') board_putc('\r');
+    }
+}
+
+void printf(char *fmt, ...)
+{
+    va_list ap;
+    va_start(ap, fmt);
+    lp_Print(printf_output, 0, fmt, ap);
+    va_end(ap);
+}
diff --git a/target/linux/ramips/image/lzma-loader/src/printf.h b/target/linux/ramips/image/lzma-loader/src/printf.h
new file mode 100644 (file)
index 0000000..9b1c1df
--- /dev/null
@@ -0,0 +1,18 @@
+/*
+ * Copyright (C) 2001 MontaVista Software Inc.
+ * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ *
+ */
+
+#ifndef _printf_h_
+#define _printf_h_
+
+#include <stdarg.h>
+void printf(char *fmt, ...);
+
+#endif /* _printf_h_ */
diff --git a/target/linux/ramips/image/lzma-loader/src/ralink.mk b/target/linux/ramips/image/lzma-loader/src/ralink.mk
new file mode 100644 (file)
index 0000000..3ff5fdd
--- /dev/null
@@ -0,0 +1 @@
+CACHE_FLAGS+=-DCONFIG_ICACHE_SIZE="(32 * 1024)" -DCONFIG_DCACHE_SIZE="(16 * 1024)" -DCONFIG_CACHELINE_SIZE=32
diff --git a/target/linux/ramips/mt7620a/config-3.8 b/target/linux/ramips/mt7620a/config-3.8
new file mode 100644 (file)
index 0000000..5eeb11e
--- /dev/null
@@ -0,0 +1,168 @@
+CONFIG_ARCH_BINFMT_ELF_RANDOMIZE_PIE=y
+CONFIG_ARCH_DISCARD_MEMBLOCK=y
+CONFIG_ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE=y
+CONFIG_ARCH_HAS_RESET_CONTROLLER=y
+CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y
+CONFIG_ARCH_HIBERNATION_POSSIBLE=y
+CONFIG_ARCH_REQUIRE_GPIOLIB=y
+CONFIG_ARCH_SUSPEND_POSSIBLE=y
+CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y
+CONFIG_CC_OPTIMIZE_FOR_SIZE=y
+CONFIG_CEVT_R4K=y
+CONFIG_CLKDEV_LOOKUP=y
+CONFIG_CLKEVT_RT3352=y
+CONFIG_CLKSRC_MMIO=y
+CONFIG_CLKSRC_OF=y
+CONFIG_CMDLINE="rootfstype=squashfs,jffs2"
+CONFIG_CMDLINE_BOOL=y
+# CONFIG_CMDLINE_OVERRIDE is not set
+CONFIG_CPU_GENERIC_DUMP_TLB=y
+CONFIG_CPU_HAS_PREFETCH=y
+CONFIG_CPU_HAS_SYNC=y
+CONFIG_CPU_LITTLE_ENDIAN=y
+CONFIG_CPU_MIPS32=y
+# CONFIG_CPU_MIPS32_R1 is not set
+CONFIG_CPU_MIPS32_R2=y
+CONFIG_CPU_MIPSR2=y
+CONFIG_CPU_R4K_CACHE_TLB=y
+CONFIG_CPU_R4K_FPU=y
+CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y
+CONFIG_CPU_SUPPORTS_HIGHMEM=y
+CONFIG_CSRC_R4K=y
+CONFIG_DECOMPRESS_LZMA=y
+CONFIG_DMA_NONCOHERENT=y
+# CONFIG_DTB_MT7620A_EVAL is not set
+# CONFIG_DTB_MT7620A_MT7610E_EVAL is not set
+CONFIG_DTB_RT_NONE=y
+CONFIG_DTC=y
+CONFIG_EARLY_PRINTK=y
+CONFIG_GENERIC_ATOMIC64=y
+CONFIG_GENERIC_CLOCKEVENTS=y
+CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
+CONFIG_GENERIC_CMOS_UPDATE=y
+CONFIG_GENERIC_GPIO=y
+CONFIG_GENERIC_IO=y
+CONFIG_GENERIC_IRQ_SHOW=y
+CONFIG_GENERIC_PCI_IOMAP=y
+CONFIG_GENERIC_SMP_IDLE_THREAD=y
+CONFIG_GPIOLIB=y
+CONFIG_GPIO_RALINK=y
+CONFIG_GPIO_SYSFS=y
+CONFIG_HARDWARE_WATCHPOINTS=y
+CONFIG_HAS_DMA=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT=y
+CONFIG_HAVE_ARCH_JUMP_LABEL=y
+CONFIG_HAVE_ARCH_KGDB=y
+CONFIG_HAVE_ARCH_TRANSPARENT_HUGEPAGE=y
+CONFIG_HAVE_CLK=y
+CONFIG_HAVE_C_RECORDMCOUNT=y
+CONFIG_HAVE_DEBUG_KMEMLEAK=y
+CONFIG_HAVE_DMA_API_DEBUG=y
+CONFIG_HAVE_DMA_ATTRS=y
+CONFIG_HAVE_DYNAMIC_FTRACE=y
+CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
+CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
+CONFIG_HAVE_FUNCTION_TRACER=y
+CONFIG_HAVE_FUNCTION_TRACE_MCOUNT_TEST=y
+CONFIG_HAVE_GENERIC_DMA_COHERENT=y
+CONFIG_HAVE_GENERIC_HARDIRQS=y
+CONFIG_HAVE_IDE=y
+CONFIG_HAVE_IRQ_WORK=y
+CONFIG_HAVE_MACH_CLKDEV=y
+CONFIG_HAVE_MEMBLOCK=y
+CONFIG_HAVE_MEMBLOCK_NODE_MAP=y
+CONFIG_HAVE_MOD_ARCH_SPECIFIC=y
+CONFIG_HAVE_NET_DSA=y
+CONFIG_HAVE_OPROFILE=y
+CONFIG_HAVE_PERF_EVENTS=y
+CONFIG_HW_HAS_PCI=y
+CONFIG_HW_RANDOM=m
+CONFIG_IMAGE_CMDLINE_HACK=y
+CONFIG_INITRAMFS_SOURCE=""
+CONFIG_IRQ_CPU=y
+CONFIG_IRQ_DOMAIN=y
+CONFIG_IRQ_FORCED_THREADING=y
+CONFIG_M25PXX_USE_FAST_READ=y
+CONFIG_MDIO_BOARDINFO=y
+# CONFIG_MII is not set
+CONFIG_MIPS=y
+# CONFIG_MIPS_HUGE_TLB_SUPPORT is not set
+CONFIG_MIPS_L1_CACHE_SHIFT=5
+# CONFIG_MIPS_MACHINE is not set
+CONFIG_MIPS_MT_DISABLED=y
+CONFIG_MMC=y
+CONFIG_MMC_BLOCK=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_IO_ACCESSORS=y
+CONFIG_MMC_SDHCI_MT7620=y
+# CONFIG_MMC_SDHCI_PCI is not set
+CONFIG_MMC_SDHCI_PLTFM=y
+# CONFIG_MMC_TIFM_SD is not set
+CONFIG_MODULES_USE_ELF_REL=y
+# CONFIG_MTD_CFI_INTELEXT is not set
+CONFIG_MTD_CMDLINE_PARTS=y
+CONFIG_MTD_M25P80=y
+CONFIG_MTD_OF_PARTS=y
+CONFIG_MTD_PHYSMAP=y
+CONFIG_MTD_PHYSMAP_OF=y
+CONFIG_MTD_UIMAGE_SPLIT=y
+CONFIG_NEED_DMA_MAP_STATE=y
+CONFIG_NEED_PER_CPU_KM=y
+CONFIG_NET_RALINK=y
+CONFIG_NET_RALINK_GSW_MT7620=y
+CONFIG_NET_RALINK_MDIO=y
+CONFIG_NO_GENERIC_PCI_IOPORT_MAP=y
+CONFIG_OF=y
+CONFIG_OF_ADDRESS=y
+CONFIG_OF_DEVICE=y
+CONFIG_OF_EARLY_FLATTREE=y
+CONFIG_OF_FLATTREE=y
+CONFIG_OF_GPIO=y
+CONFIG_OF_IRQ=y
+CONFIG_OF_MDIO=y
+CONFIG_OF_MTD=y
+CONFIG_OF_NET=y
+CONFIG_OF_PCI=y
+CONFIG_OF_PCI_IRQ=y
+CONFIG_PAGEFLAGS_EXTENDED=y
+CONFIG_PCI=y
+# CONFIG_PCIEAER is not set
+CONFIG_PCIEPORTBUS=y
+CONFIG_PCI_DOMAINS=y
+CONFIG_PERCPU_RWSEM=y
+CONFIG_PERF_USE_VMALLOC=y
+CONFIG_PHYLIB=y
+# CONFIG_PREEMPT_RCU is not set
+CONFIG_RALINK=y
+CONFIG_RALINK_USBPHY=y
+CONFIG_RALINK_WDT=y
+CONFIG_RESET_CONTROLLER=y
+# CONFIG_SCSI_DMA is not set
+CONFIG_SERIAL_8250_NR_UARTS=4
+CONFIG_SERIAL_8250_RT288X=y
+CONFIG_SERIAL_OF_PLATFORM=y
+# CONFIG_SLAB is not set
+CONFIG_SLUB=y
+CONFIG_SOC_MT7620=y
+# CONFIG_SOC_RT288X is not set
+# CONFIG_SOC_RT305X is not set
+# CONFIG_SOC_RT3883 is not set
+CONFIG_SPI=y
+CONFIG_SPI_MASTER=y
+CONFIG_SPI_RALINK=y
+CONFIG_SWCONFIG=y
+CONFIG_SYS_HAS_CPU_MIPS32_R1=y
+CONFIG_SYS_HAS_CPU_MIPS32_R2=y
+CONFIG_SYS_HAS_EARLY_PRINTK=y
+CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y
+CONFIG_SYS_SUPPORTS_ARBIT_HZ=y
+CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y
+CONFIG_TICK_CPU_ACCOUNTING=y
+CONFIG_UIDGID_CONVERTED=y
+CONFIG_USB_ARCH_HAS_XHCI=y
+CONFIG_USB_OTG_UTILS=y
+CONFIG_USB_SUPPORT=y
+CONFIG_USE_OF=y
+CONFIG_WATCHDOG_CORE=y
+CONFIG_ZONE_DMA_FLAG=0
diff --git a/target/linux/ramips/mt7620a/config-3.9 b/target/linux/ramips/mt7620a/config-3.9
new file mode 100644 (file)
index 0000000..ea7d6bc
--- /dev/null
@@ -0,0 +1,172 @@
+CONFIG_ARCH_BINFMT_ELF_RANDOMIZE_PIE=y
+CONFIG_ARCH_DISCARD_MEMBLOCK=y
+CONFIG_ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE=y
+CONFIG_ARCH_HAS_RESET_CONTROLLER=y
+CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y
+CONFIG_ARCH_HIBERNATION_POSSIBLE=y
+CONFIG_ARCH_REQUIRE_GPIOLIB=y
+CONFIG_ARCH_SUSPEND_POSSIBLE=y
+CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y
+CONFIG_CC_OPTIMIZE_FOR_SIZE=y
+CONFIG_CEVT_R4K=y
+CONFIG_CLKDEV_LOOKUP=y
+CONFIG_CLKEVT_RT3352=y
+CONFIG_CLKSRC_MMIO=y
+CONFIG_CLKSRC_OF=y
+CONFIG_CLONE_BACKWARDS=y
+CONFIG_CMDLINE="rootfstype=squashfs,jffs2"
+CONFIG_CMDLINE_BOOL=y
+# CONFIG_CMDLINE_OVERRIDE is not set
+CONFIG_CPU_GENERIC_DUMP_TLB=y
+CONFIG_CPU_HAS_PREFETCH=y
+CONFIG_CPU_HAS_SYNC=y
+CONFIG_CPU_LITTLE_ENDIAN=y
+CONFIG_CPU_MIPS32=y
+# CONFIG_CPU_MIPS32_R1 is not set
+CONFIG_CPU_MIPS32_R2=y
+CONFIG_CPU_MIPSR2=y
+CONFIG_CPU_R4K_CACHE_TLB=y
+CONFIG_CPU_R4K_FPU=y
+CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y
+CONFIG_CPU_SUPPORTS_HIGHMEM=y
+CONFIG_CSRC_R4K=y
+CONFIG_DECOMPRESS_LZMA=y
+CONFIG_DMA_NONCOHERENT=y
+# CONFIG_DTB_MT7620A_EVAL is not set
+# CONFIG_DTB_MT7620A_MT7610E_EVAL is not set
+CONFIG_DTB_RT_NONE=y
+CONFIG_DTC=y
+CONFIG_EARLY_PRINTK=y
+CONFIG_GENERIC_ATOMIC64=y
+CONFIG_GENERIC_CLOCKEVENTS=y
+CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
+CONFIG_GENERIC_CMOS_UPDATE=y
+CONFIG_GENERIC_GPIO=y
+CONFIG_GENERIC_IO=y
+CONFIG_GENERIC_IRQ_SHOW=y
+CONFIG_GENERIC_PCI_IOMAP=y
+CONFIG_GENERIC_SMP_IDLE_THREAD=y
+CONFIG_GPIOLIB=y
+CONFIG_GPIO_DEVRES=y
+CONFIG_GPIO_RALINK=y
+CONFIG_GPIO_SYSFS=y
+CONFIG_HARDWARE_WATCHPOINTS=y
+CONFIG_HAS_DMA=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT=y
+# CONFIG_HAVE_64BIT_ALIGNED_ACCESS is not set
+CONFIG_HAVE_ARCH_JUMP_LABEL=y
+CONFIG_HAVE_ARCH_KGDB=y
+# CONFIG_HAVE_BOOTMEM_INFO_NODE is not set
+CONFIG_HAVE_CLK=y
+CONFIG_HAVE_C_RECORDMCOUNT=y
+CONFIG_HAVE_DEBUG_KMEMLEAK=y
+CONFIG_HAVE_DMA_API_DEBUG=y
+CONFIG_HAVE_DMA_ATTRS=y
+CONFIG_HAVE_DYNAMIC_FTRACE=y
+CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
+CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
+CONFIG_HAVE_FUNCTION_TRACER=y
+CONFIG_HAVE_FUNCTION_TRACE_MCOUNT_TEST=y
+CONFIG_HAVE_GENERIC_DMA_COHERENT=y
+CONFIG_HAVE_GENERIC_HARDIRQS=y
+CONFIG_HAVE_IDE=y
+CONFIG_HAVE_MACH_CLKDEV=y
+CONFIG_HAVE_MEMBLOCK=y
+CONFIG_HAVE_MEMBLOCK_NODE_MAP=y
+CONFIG_HAVE_MOD_ARCH_SPECIFIC=y
+CONFIG_HAVE_NET_DSA=y
+CONFIG_HAVE_OPROFILE=y
+CONFIG_HAVE_PERF_EVENTS=y
+CONFIG_HW_HAS_PCI=y
+CONFIG_HW_RANDOM=m
+CONFIG_IMAGE_CMDLINE_HACK=y
+CONFIG_INITRAMFS_SOURCE=""
+CONFIG_IRQCHIP=y
+CONFIG_IRQ_CPU=y
+CONFIG_IRQ_DOMAIN=y
+CONFIG_IRQ_FORCED_THREADING=y
+CONFIG_IRQ_WORK=y
+CONFIG_M25PXX_USE_FAST_READ=y
+CONFIG_MDIO_BOARDINFO=y
+# CONFIG_MII is not set
+CONFIG_MIPS=y
+# CONFIG_MIPS_HUGE_TLB_SUPPORT is not set
+CONFIG_MIPS_L1_CACHE_SHIFT=5
+# CONFIG_MIPS_MACHINE is not set
+CONFIG_MIPS_MT_DISABLED=y
+CONFIG_MMC=y
+CONFIG_MMC_BLOCK=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_IO_ACCESSORS=y
+CONFIG_MMC_SDHCI_MT7620=y
+# CONFIG_MMC_SDHCI_PCI is not set
+CONFIG_MMC_SDHCI_PLTFM=y
+# CONFIG_MMC_TIFM_SD is not set
+CONFIG_MODULES_USE_ELF_REL=y
+# CONFIG_MTD_CFI_INTELEXT is not set
+CONFIG_MTD_CMDLINE_PARTS=y
+CONFIG_MTD_M25P80=y
+CONFIG_MTD_OF_PARTS=y
+CONFIG_MTD_PHYSMAP=y
+CONFIG_MTD_PHYSMAP_OF=y
+CONFIG_MTD_UIMAGE_SPLIT=y
+CONFIG_NEED_DMA_MAP_STATE=y
+CONFIG_NEED_PER_CPU_KM=y
+CONFIG_NET_RALINK=y
+CONFIG_NET_RALINK_GSW_MT7620=y
+CONFIG_NET_RALINK_MDIO=y
+CONFIG_NO_GENERIC_PCI_IOPORT_MAP=y
+CONFIG_OF=y
+CONFIG_OF_ADDRESS=y
+CONFIG_OF_DEVICE=y
+# CONFIG_OF_DISPLAY_TIMING is not set
+CONFIG_OF_EARLY_FLATTREE=y
+CONFIG_OF_FLATTREE=y
+CONFIG_OF_GPIO=y
+CONFIG_OF_IRQ=y
+CONFIG_OF_MDIO=y
+CONFIG_OF_MTD=y
+CONFIG_OF_NET=y
+CONFIG_OF_PCI=y
+CONFIG_OF_PCI_IRQ=y
+# CONFIG_OF_VIDEOMODE is not set
+CONFIG_PAGEFLAGS_EXTENDED=y
+CONFIG_PCI=y
+CONFIG_PCI_DOMAINS=y
+CONFIG_PERF_USE_VMALLOC=y
+CONFIG_PHYLIB=y
+# CONFIG_PREEMPT_RCU is not set
+CONFIG_RALINK=y
+CONFIG_RALINK_USBPHY=y
+CONFIG_RALINK_WDT=y
+# CONFIG_RCU_STALL_COMMON is not set
+CONFIG_RESET_CONTROLLER=y
+# CONFIG_SCSI_DMA is not set
+CONFIG_SERIAL_8250_NR_UARTS=4
+CONFIG_SERIAL_8250_RT288X=y
+CONFIG_SERIAL_OF_PLATFORM=y
+# CONFIG_SLAB is not set
+CONFIG_SLUB=y
+CONFIG_SOC_MT7620=y
+# CONFIG_SOC_RT288X is not set
+# CONFIG_SOC_RT305X is not set
+# CONFIG_SOC_RT3883 is not set
+CONFIG_SPI=y
+CONFIG_SPI_MASTER=y
+CONFIG_SPI_RALINK=y
+CONFIG_SWCONFIG=y
+CONFIG_SYS_HAS_CPU_MIPS32_R1=y
+CONFIG_SYS_HAS_CPU_MIPS32_R2=y
+CONFIG_SYS_HAS_EARLY_PRINTK=y
+CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y
+CONFIG_SYS_SUPPORTS_ARBIT_HZ=y
+CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y
+CONFIG_TICK_CPU_ACCOUNTING=y
+CONFIG_UIDGID_CONVERTED=y
+CONFIG_USB_ARCH_HAS_XHCI=y
+CONFIG_USB_OTG_UTILS=y
+CONFIG_USB_SUPPORT=y
+CONFIG_USE_OF=y
+CONFIG_WATCHDOG_CORE=y
+CONFIG_ZONE_DMA_FLAG=0
diff --git a/target/linux/ramips/mt7620a/profiles/00-default.mk b/target/linux/ramips/mt7620a/profiles/00-default.mk
new file mode 100644 (file)
index 0000000..55ac015
--- /dev/null
@@ -0,0 +1,18 @@
+#
+# Copyright (C) 2011 OpenWrt.org
+#
+# This is free software, licensed under the GNU General Public License v2.
+# See /LICENSE for more information.
+#
+
+define Profile/Default
+       NAME:=Default Profile
+       PACKAGES:=\
+               kmod-usb-core kmod-usb-rt305x-dwc_otg \
+               kmod-ledtrig-usbdev
+endef
+
+define Profile/Default/Description
+       Default package set compatible with most boards.
+endef
+$(eval $(call Profile,Default))
diff --git a/target/linux/ramips/mt7620a/target.mk b/target/linux/ramips/mt7620a/target.mk
new file mode 100644 (file)
index 0000000..4d4dd28
--- /dev/null
@@ -0,0 +1,14 @@
+#
+# Copyright (C) 2009 OpenWrt.org
+#
+
+SUBTARGET:=mt7620a
+BOARDNAME:=MT7620a based boards
+ARCH_PACKAGES:=ramips_24kec
+FEATURES+=usb
+CFLAGS+= -march=24kec -mdsp
+
+define Target/Description
+       Build firmware images for Ralink MT7620a based boards.
+endef
+
index 3539ece..cc32caa 100644 (file)
@@ -1,7 +1,7 @@
-From 8563991026ee98bb5e477167236972a45dfea0e3 Mon Sep 17 00:00:00 2001
+From 72bd3fcd16225f46ca318435a4d8f3f3f154b1bc Mon Sep 17 00:00:00 2001
 From: John Crispin <blogic@openwrt.org>
 Date: Mon, 21 Jan 2013 18:25:59 +0100
-Subject: [PATCH 01/14] MIPS: ralink: adds include files
+Subject: [PATCH 01/79] MIPS: ralink: adds include files
 
 Before we start adding the platform code we add the common include files.
 
@@ -17,6 +17,9 @@ Patchwork: http://patchwork.linux-mips.org/patch/4893/
  create mode 100644 arch/mips/include/asm/mach-ralink/war.h
  create mode 100644 arch/mips/ralink/common.h
 
+diff --git a/arch/mips/include/asm/mach-ralink/ralink_regs.h b/arch/mips/include/asm/mach-ralink/ralink_regs.h
+new file mode 100644
+index 0000000..5a508f9
 --- /dev/null
 +++ b/arch/mips/include/asm/mach-ralink/ralink_regs.h
 @@ -0,0 +1,39 @@
@@ -59,6 +62,9 @@ Patchwork: http://patchwork.linux-mips.org/patch/4893/
 +}
 +
 +#endif /* _RALINK_REGS_H_ */
+diff --git a/arch/mips/include/asm/mach-ralink/war.h b/arch/mips/include/asm/mach-ralink/war.h
+new file mode 100644
+index 0000000..a7b712c
 --- /dev/null
 +++ b/arch/mips/include/asm/mach-ralink/war.h
 @@ -0,0 +1,25 @@
@@ -87,6 +93,9 @@ Patchwork: http://patchwork.linux-mips.org/patch/4893/
 +#define MIPS34K_MISSED_ITLB_WAR               0
 +
 +#endif /* __ASM_MACH_RALINK_WAR_H */
+diff --git a/arch/mips/ralink/common.h b/arch/mips/ralink/common.h
+new file mode 100644
+index 0000000..3009903
 --- /dev/null
 +++ b/arch/mips/ralink/common.h
 @@ -0,0 +1,44 @@
@@ -134,3 +143,6 @@ Patchwork: http://patchwork.linux-mips.org/patch/4893/
 +__iomem void *plat_of_remap_node(const char *node);
 +
 +#endif /* _RALINK_COMMON_H__ */
+-- 
+1.7.10.4
+
index c559a87..01beef7 100644 (file)
@@ -1,7 +1,7 @@
-From 19d3814e7b325f8965fd71f329b3467a97f8d217 Mon Sep 17 00:00:00 2001
+From 833836f47b4191e93267b91fcab38dd15affcd28 Mon Sep 17 00:00:00 2001
 From: John Crispin <blogic@openwrt.org>
 Date: Sun, 20 Jan 2013 22:00:50 +0100
-Subject: [PATCH 02/14] MIPS: ralink: adds irq code
+Subject: [PATCH 02/79] MIPS: ralink: adds irq code
 
 All of the Ralink Wifi SoC currently supported by this series share the same
 interrupt controller (INTC).
@@ -14,6 +14,9 @@ Patchwork: http://patchwork.linux-mips.org/patch/4890/
  1 file changed, 176 insertions(+)
  create mode 100644 arch/mips/ralink/irq.c
 
+diff --git a/arch/mips/ralink/irq.c b/arch/mips/ralink/irq.c
+new file mode 100644
+index 0000000..e62c975
 --- /dev/null
 +++ b/arch/mips/ralink/irq.c
 @@ -0,0 +1,176 @@
@@ -193,3 +196,6 @@ Patchwork: http://patchwork.linux-mips.org/patch/4890/
 +      of_irq_init(of_irq_ids);
 +}
 +
+-- 
+1.7.10.4
+
index 57cad76..ee9a509 100644 (file)
@@ -1,7 +1,7 @@
-From c06e836ada59fbc6d1109277e693e5b3e056ac12 Mon Sep 17 00:00:00 2001
+From 3cdf3d713c81ffd3032d7c664f0be89d1ddce3e3 Mon Sep 17 00:00:00 2001
 From: John Crispin <blogic@openwrt.org>
 Date: Sun, 20 Jan 2013 22:00:57 +0100
-Subject: [PATCH 03/14] MIPS: ralink: adds reset code
+Subject: [PATCH 03/79] MIPS: ralink: adds reset code
 
 Resetting these SoCs requires no real magic. The code is straight forward.
 
@@ -13,6 +13,9 @@ Patchwork: http://patchwork.linux-mips.org/patch/4891/
  1 file changed, 44 insertions(+)
  create mode 100644 arch/mips/ralink/reset.c
 
+diff --git a/arch/mips/ralink/reset.c b/arch/mips/ralink/reset.c
+new file mode 100644
+index 0000000..22120e5
 --- /dev/null
 +++ b/arch/mips/ralink/reset.c
 @@ -0,0 +1,44 @@
@@ -60,3 +63,6 @@ Patchwork: http://patchwork.linux-mips.org/patch/4891/
 +}
 +
 +arch_initcall(mips_reboot_setup);
+-- 
+1.7.10.4
+
index da38629..8b8bb56 100644 (file)
@@ -1,7 +1,7 @@
-From 7e47cefa69c8ed2c889522ce29fcce73ce8cf08e Mon Sep 17 00:00:00 2001
+From 36424b3f1f184c752562d19d0df1a427c8c584a2 Mon Sep 17 00:00:00 2001
 From: John Crispin <blogic@openwrt.org>
 Date: Sun, 20 Jan 2013 22:01:05 +0100
-Subject: [PATCH 04/14] MIPS: ralink: adds prom and cmdline code
+Subject: [PATCH 04/79] MIPS: ralink: adds prom and cmdline code
 
 Add minimal code to handle commandlines.
 
@@ -13,6 +13,9 @@ Patchwork: http://patchwork.linux-mips.org/patch/4892/
  1 file changed, 69 insertions(+)
  create mode 100644 arch/mips/ralink/prom.c
 
+diff --git a/arch/mips/ralink/prom.c b/arch/mips/ralink/prom.c
+new file mode 100644
+index 0000000..9c64f02
 --- /dev/null
 +++ b/arch/mips/ralink/prom.c
 @@ -0,0 +1,69 @@
@@ -85,3 +88,6 @@ Patchwork: http://patchwork.linux-mips.org/patch/4892/
 +void __init prom_free_prom_memory(void)
 +{
 +}
+-- 
+1.7.10.4
+
index a8218d1..1fd6057 100644 (file)
@@ -1,7 +1,7 @@
-From 3f0a06b0368d25608841843e9d65a7289ad9f14a Mon Sep 17 00:00:00 2001
+From b99289db258ee8a84e1bd555b2897476acf390c1 Mon Sep 17 00:00:00 2001
 From: John Crispin <blogic@openwrt.org>
 Date: Sun, 20 Jan 2013 22:01:29 +0100
-Subject: [PATCH 05/14] MIPS: ralink: adds clkdev code
+Subject: [PATCH 05/79] MIPS: ralink: adds clkdev code
 
 These SoCs have a limited number of fixed rate clocks. Add support for the
 clk and clkdev api.
@@ -14,6 +14,9 @@ Patchwork: http://patchwork.linux-mips.org/patch/4894/
  1 file changed, 72 insertions(+)
  create mode 100644 arch/mips/ralink/clk.c
 
+diff --git a/arch/mips/ralink/clk.c b/arch/mips/ralink/clk.c
+new file mode 100644
+index 0000000..8dfa22f
 --- /dev/null
 +++ b/arch/mips/ralink/clk.c
 @@ -0,0 +1,72 @@
@@ -89,3 +92,6 @@ Patchwork: http://patchwork.linux-mips.org/patch/4894/
 +      mips_hpt_frequency = clk_get_rate(clk) / 2;
 +      clk_put(clk);
 +}
+-- 
+1.7.10.4
+
index b6bd78b..7747c81 100644 (file)
@@ -1,7 +1,7 @@
-From 3a5bfe7bdbfd37c9206d7c6dfd7eb9664ccc5038 Mon Sep 17 00:00:00 2001
+From 4b2f9abbbaf3463a0fc1a65afeb0d12f890ada35 Mon Sep 17 00:00:00 2001
 From: John Crispin <blogic@openwrt.org>
 Date: Sun, 20 Jan 2013 22:02:01 +0100
-Subject: [PATCH 06/14] MIPS: ralink: adds OF code
+Subject: [PATCH 06/79] MIPS: ralink: adds OF code
 
 Until there is a generic MIPS way of handing the DTB over from bootloader to
 kernel we rely on a built in devicetrees. The OF code also remaps those register
@@ -15,6 +15,9 @@ Patchwork: http://patchwork.linux-mips.org/patch/4895/
  1 file changed, 107 insertions(+)
  create mode 100644 arch/mips/ralink/of.c
 
+diff --git a/arch/mips/ralink/of.c b/arch/mips/ralink/of.c
+new file mode 100644
+index 0000000..4165e70
 --- /dev/null
 +++ b/arch/mips/ralink/of.c
 @@ -0,0 +1,107 @@
@@ -125,3 +128,6 @@ Patchwork: http://patchwork.linux-mips.org/patch/4895/
 +}
 +
 +arch_initcall(plat_of_setup);
+-- 
+1.7.10.4
+
index 80a5b1e..e22bbbd 100644 (file)
@@ -1,7 +1,7 @@
-From 5fff610b7c60195de98e68bec00c357f393ce634 Mon Sep 17 00:00:00 2001
+From 4efba82d0e4059588f2b2fc0ac2576eaf37f1d22 Mon Sep 17 00:00:00 2001
 From: John Crispin <blogic@openwrt.org>
 Date: Sun, 20 Jan 2013 22:02:55 +0100
-Subject: [PATCH 07/14] MIPS: ralink: adds early_printk support
+Subject: [PATCH 07/79] MIPS: ralink: adds early_printk support
 
 Add the code needed to make early printk work.
 
@@ -13,6 +13,9 @@ Patchwork: http://patchwork.linux-mips.org/patch/4897/
  1 file changed, 44 insertions(+)
  create mode 100644 arch/mips/ralink/early_printk.c
 
+diff --git a/arch/mips/ralink/early_printk.c b/arch/mips/ralink/early_printk.c
+new file mode 100644
+index 0000000..c4ae47e
 --- /dev/null
 +++ b/arch/mips/ralink/early_printk.c
 @@ -0,0 +1,44 @@
@@ -60,3 +63,6 @@ Patchwork: http://patchwork.linux-mips.org/patch/4897/
 +      while ((uart_r32(UART_REG_LSR) & UART_LSR_THRE) == 0)
 +              ;
 +}
+-- 
+1.7.10.4
+
index 083526b..01b0869 100644 (file)
@@ -1,7 +1,7 @@
-From 2809b31770d7fd934a748692e1922a5e613f06e5 Mon Sep 17 00:00:00 2001
+From 433f4f524aba81358353ca4ebc00c3e916521ec6 Mon Sep 17 00:00:00 2001
 From: John Crispin <blogic@openwrt.org>
 Date: Sun, 20 Jan 2013 22:03:46 +0100
-Subject: [PATCH 08/14] MIPS: ralink: adds support for RT305x SoC family
+Subject: [PATCH 08/79] MIPS: ralink: adds support for RT305x SoC family
 
 Add support code for rt3050, rt3052, rt3350, rt3352 and rt5350 SOC.
 
@@ -17,6 +17,9 @@ Patchwork: http://patchwork.linux-mips.org/patch/4896/
  create mode 100644 arch/mips/include/asm/mach-ralink/rt305x.h
  create mode 100644 arch/mips/ralink/rt305x.c
 
+diff --git a/arch/mips/include/asm/mach-ralink/rt305x.h b/arch/mips/include/asm/mach-ralink/rt305x.h
+new file mode 100644
+index 0000000..7d344f2
 --- /dev/null
 +++ b/arch/mips/include/asm/mach-ralink/rt305x.h
 @@ -0,0 +1,139 @@
@@ -159,6 +162,9 @@ Patchwork: http://patchwork.linux-mips.org/patch/4896/
 +#define RT305X_GPIO_MODE_RGMII                BIT(9)
 +
 +#endif
+diff --git a/arch/mips/ralink/rt305x.c b/arch/mips/ralink/rt305x.c
+new file mode 100644
+index 0000000..0a4bbdc
 --- /dev/null
 +++ b/arch/mips/ralink/rt305x.c
 @@ -0,0 +1,242 @@
@@ -404,3 +410,6 @@ Patchwork: http://patchwork.linux-mips.org/patch/4896/
 +              (id >> CHIP_ID_ID_SHIFT) & CHIP_ID_ID_MASK,
 +              (id & CHIP_ID_REV_MASK));
 +}
+-- 
+1.7.10.4
+
index 2c2bb14..81d9fea 100644 (file)
@@ -1,7 +1,7 @@
-From 5644da4f635a30fc03b4f12d81b2197d716d9cef Mon Sep 17 00:00:00 2001
+From 8208a43c301d9164802dedeec7455dbdd70ca286 Mon Sep 17 00:00:00 2001
 From: John Crispin <blogic@openwrt.org>
 Date: Tue, 22 Jan 2013 20:19:33 +0100
-Subject: [PATCH 09/14] MIPS: ralink: adds rt305x devicetree
+Subject: [PATCH 09/79] MIPS: ralink: adds rt305x devicetree
 
 This adds the devicetree file that describes the rt305x evaluation kit.
 
@@ -15,6 +15,9 @@ Patchwork: http://patchwork.linux-mips.org/patch/4898/
  create mode 100644 arch/mips/ralink/dts/rt3050.dtsi
  create mode 100644 arch/mips/ralink/dts/rt3052_eval.dts
 
+diff --git a/arch/mips/ralink/dts/rt3050.dtsi b/arch/mips/ralink/dts/rt3050.dtsi
+new file mode 100644
+index 0000000..fd49daa
 --- /dev/null
 +++ b/arch/mips/ralink/dts/rt3050.dtsi
 @@ -0,0 +1,96 @@
@@ -114,6 +117,9 @@ Patchwork: http://patchwork.linux-mips.org/patch/4898/
 +              };
 +      };
 +};
+diff --git a/arch/mips/ralink/dts/rt3052_eval.dts b/arch/mips/ralink/dts/rt3052_eval.dts
+new file mode 100644
+index 0000000..dc56e58
 --- /dev/null
 +++ b/arch/mips/ralink/dts/rt3052_eval.dts
 @@ -0,0 +1,52 @@
@@ -169,3 +175,6 @@ Patchwork: http://patchwork.linux-mips.org/patch/4898/
 +              };
 +      };
 +};
+-- 
+1.7.10.4
+
index bccc3b8..88c018c 100644 (file)
@@ -1,7 +1,7 @@
-From ae2b5bb6570481b50a7175c64176b82da0a81836 Mon Sep 17 00:00:00 2001
+From 79e69b7a01246e945448039f7dce170eef0b6e3b Mon Sep 17 00:00:00 2001
 From: John Crispin <blogic@openwrt.org>
 Date: Sun, 20 Jan 2013 22:05:30 +0100
-Subject: [PATCH 10/14] MIPS: ralink: adds Kbuild files
+Subject: [PATCH 10/79] MIPS: ralink: adds Kbuild files
 
 Add the Kbuild symbols and Makefiles needed to actually build the ralink code
 from this series
@@ -22,6 +22,8 @@ Patchwork: http://patchwork.linux-mips.org/patch/4899/
  create mode 100644 arch/mips/ralink/Platform
  create mode 100644 arch/mips/ralink/dts/Makefile
 
+diff --git a/arch/mips/Kbuild.platforms b/arch/mips/Kbuild.platforms
+index 91b9d69..9a73ce6 100644
 --- a/arch/mips/Kbuild.platforms
 +++ b/arch/mips/Kbuild.platforms
 @@ -22,6 +22,7 @@ platforms += pmc-sierra
@@ -32,6 +34,8 @@ Patchwork: http://patchwork.linux-mips.org/patch/4899/
  platforms += rb532
  platforms += sgi-ip22
  platforms += sgi-ip27
+diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
+index 2ac626a..b5081b5 100644
 --- a/arch/mips/Kconfig
 +++ b/arch/mips/Kconfig
 @@ -434,6 +434,22 @@ config POWERTV
@@ -65,6 +69,9 @@ Patchwork: http://patchwork.linux-mips.org/patch/4899/
  source "arch/mips/sgi-ip27/Kconfig"
  source "arch/mips/sibyte/Kconfig"
  source "arch/mips/txx9/Kconfig"
+diff --git a/arch/mips/ralink/Kconfig b/arch/mips/ralink/Kconfig
+new file mode 100644
+index 0000000..a0b0197
 --- /dev/null
 +++ b/arch/mips/ralink/Kconfig
 @@ -0,0 +1,32 @@
@@ -100,6 +107,9 @@ Patchwork: http://patchwork.linux-mips.org/patch/4899/
 +endchoice
 +
 +endif
+diff --git a/arch/mips/ralink/Makefile b/arch/mips/ralink/Makefile
+new file mode 100644
+index 0000000..939757f
 --- /dev/null
 +++ b/arch/mips/ralink/Makefile
 @@ -0,0 +1,15 @@
@@ -118,6 +128,9 @@ Patchwork: http://patchwork.linux-mips.org/patch/4899/
 +obj-$(CONFIG_EARLY_PRINTK) += early_printk.o
 +
 +obj-y += dts/
+diff --git a/arch/mips/ralink/Platform b/arch/mips/ralink/Platform
+new file mode 100644
+index 0000000..6babd65
 --- /dev/null
 +++ b/arch/mips/ralink/Platform
 @@ -0,0 +1,10 @@
@@ -131,7 +144,13 @@ Patchwork: http://patchwork.linux-mips.org/patch/4899/
 +# Ralink RT305x
 +#
 +load-$(CONFIG_SOC_RT305X)     += 0xffffffff80000000
+diff --git a/arch/mips/ralink/dts/Makefile b/arch/mips/ralink/dts/Makefile
+new file mode 100644
+index 0000000..1a69fb3
 --- /dev/null
 +++ b/arch/mips/ralink/dts/Makefile
 @@ -0,0 +1 @@
 +obj-$(CONFIG_DTB_RT305X_EVAL) := rt3052_eval.dtb.o
+-- 
+1.7.10.4
+
index 5998b11..1f4a1e2 100644 (file)
@@ -1,7 +1,7 @@
-From 6d63d70f9fe4c1b3d293ac3b9d2fcaf937d95cea Mon Sep 17 00:00:00 2001
+From 428bb7af86ffb6171e11c36dfcdacd87ed5341e6 Mon Sep 17 00:00:00 2001
 From: John Crispin <blogic@openwrt.org>
 Date: Fri, 1 Feb 2013 12:50:49 +0100
-Subject: [PATCH 11/14] MIPS: ralink: adds default config file
+Subject: [PATCH 11/79] MIPS: ralink: adds default config file
 
 Signed-off-by: John Crispin <blogic@openwrt.org>
 ---
@@ -9,6 +9,9 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
  1 file changed, 167 insertions(+)
  create mode 100644 arch/mips/configs/rt305x_defconfig
 
+diff --git a/arch/mips/configs/rt305x_defconfig b/arch/mips/configs/rt305x_defconfig
+new file mode 100644
+index 0000000..d1741bc
 --- /dev/null
 +++ b/arch/mips/configs/rt305x_defconfig
 @@ -0,0 +1,167 @@
@@ -179,3 +182,6 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
 +# CONFIG_XZ_DEC_ARMTHUMB is not set
 +# CONFIG_XZ_DEC_SPARC is not set
 +CONFIG_AVERAGE=y
+-- 
+1.7.10.4
+
index 6a07d8d..b7ce7c9 100644 (file)
@@ -1,7 +1,7 @@
-From dcc7310e144c3bf17a86d2f058d60fb525d4b34a Mon Sep 17 00:00:00 2001
+From dae867771332e7541783ebb6bacf33356ad449b3 Mon Sep 17 00:00:00 2001
 From: John Crispin <blogic@openwrt.org>
 Date: Thu, 31 Jan 2013 13:44:10 +0100
-Subject: [PATCH 12/14] Document: devicetree: add OF documents for MIPS
+Subject: [PATCH 12/79] Document: devicetree: add OF documents for MIPS
  interrupt controller
 
 Signed-off-by: John Crispin <blogic@openwrt.org>
@@ -12,6 +12,9 @@ Patchwork: http://patchwork.linux-mips.org/patch/4901/
  1 file changed, 47 insertions(+)
  create mode 100644 Documentation/devicetree/bindings/mips/cpu_irq.txt
 
+diff --git a/Documentation/devicetree/bindings/mips/cpu_irq.txt b/Documentation/devicetree/bindings/mips/cpu_irq.txt
+new file mode 100644
+index 0000000..13aa4b6
 --- /dev/null
 +++ b/Documentation/devicetree/bindings/mips/cpu_irq.txt
 @@ -0,0 +1,47 @@
@@ -62,3 +65,6 @@ Patchwork: http://patchwork.linux-mips.org/patch/4901/
 +{
 +      of_irq_init(of_irq_ids);
 +}
+-- 
+1.7.10.4
+
index 3139106..e5387a2 100644 (file)
@@ -1,7 +1,7 @@
-From 0916b46962cbcac9465d253d0a398435b3965fd5 Mon Sep 17 00:00:00 2001
+From 65e39f763eeca6fb93f48ed5a9b296277a543429 Mon Sep 17 00:00:00 2001
 From: Gabor Juhos <juhosg@openwrt.org>
 Date: Thu, 31 Jan 2013 12:20:43 +0000
-Subject: [PATCH 13/14] MIPS: add irqdomain support for the CPU IRQ controller
+Subject: [PATCH 13/79] MIPS: add irqdomain support for the CPU IRQ controller
 
 Add code to load a irq_domain for the MIPS IRQ controller from a devicetree
 file.
@@ -15,6 +15,8 @@ Patchwork: http://patchwork.linux-mips.org/patch/4902/
  arch/mips/kernel/irq_cpu.c      |   42 +++++++++++++++++++++++++++++++++++++++
  2 files changed, 48 insertions(+)
 
+diff --git a/arch/mips/include/asm/irq_cpu.h b/arch/mips/include/asm/irq_cpu.h
+index ef6a07c..3f11fdb 100644
 --- a/arch/mips/include/asm/irq_cpu.h
 +++ b/arch/mips/include/asm/irq_cpu.h
 @@ -17,4 +17,10 @@ extern void mips_cpu_irq_init(void);
@@ -28,6 +30,8 @@ Patchwork: http://patchwork.linux-mips.org/patch/4902/
 +#endif
 +
  #endif /* _ASM_IRQ_CPU_H */
+diff --git a/arch/mips/kernel/irq_cpu.c b/arch/mips/kernel/irq_cpu.c
+index 972263b..49bc9ca 100644
 --- a/arch/mips/kernel/irq_cpu.c
 +++ b/arch/mips/kernel/irq_cpu.c
 @@ -31,6 +31,7 @@
@@ -83,3 +87,6 @@ Patchwork: http://patchwork.linux-mips.org/patch/4902/
 +      return 0;
 +}
 +#endif /* CONFIG_IRQ_DOMAIN */
+-- 
+1.7.10.4
+
index e9e2f56..e346131 100644 (file)
@@ -1,7 +1,7 @@
-From d3d2b4200b5a42851365e903d101f8f0882eb9eb Mon Sep 17 00:00:00 2001
+From 9afd2ba44145009578d9d445183480a698cc04f2 Mon Sep 17 00:00:00 2001
 From: Gabor Juhos <juhosg@openwrt.org>
 Date: Thu, 31 Jan 2013 20:43:30 +0100
-Subject: [PATCH 14/14] MIPS: ralink: add CPU interrupt controller to
+Subject: [PATCH 14/79] MIPS: ralink: add CPU interrupt controller to
  of_irq_ids
 
 Convert the ralink IRQ code to make use of the new MIPS IRQ controller OF
@@ -16,6 +16,8 @@ Patchwork: http://patchwork.linux-mips.org/patch/4900/
  arch/mips/ralink/irq.c           |   10 +++++++---
  2 files changed, 17 insertions(+), 3 deletions(-)
 
+diff --git a/arch/mips/ralink/dts/rt3050.dtsi b/arch/mips/ralink/dts/rt3050.dtsi
+index fd49daa..069d066 100644
 --- a/arch/mips/ralink/dts/rt3050.dtsi
 +++ b/arch/mips/ralink/dts/rt3050.dtsi
 @@ -13,6 +13,13 @@
@@ -42,9 +44,11 @@ Patchwork: http://patchwork.linux-mips.org/patch/4900/
                };
  
                memc@300 {
+diff --git a/arch/mips/ralink/irq.c b/arch/mips/ralink/irq.c
+index e62c975..6d054c5 100644
 --- a/arch/mips/ralink/irq.c
 +++ b/arch/mips/ralink/irq.c
-@@ -128,8 +128,11 @@ static int __init intc_of_init(struct de
+@@ -128,8 +128,11 @@ static int __init intc_of_init(struct device_node *node,
  {
        struct resource res;
        struct irq_domain *domain;
@@ -57,7 +61,7 @@ Patchwork: http://patchwork.linux-mips.org/patch/4900/
  
        if (of_address_to_resource(node, 0, &res))
                panic("Failed to get intc memory range");
-@@ -156,8 +159,8 @@ static int __init intc_of_init(struct de
+@@ -156,8 +159,8 @@ static int __init intc_of_init(struct device_node *node,
  
        rt_intc_w32(INTC_INT_GLOBAL, INTC_REG_ENABLE);
  
@@ -68,7 +72,7 @@ Patchwork: http://patchwork.linux-mips.org/patch/4900/
  
        cp0_perfcount_irq = irq_create_mapping(domain, 9);
  
-@@ -165,6 +168,7 @@ static int __init intc_of_init(struct de
+@@ -165,6 +168,7 @@ static int __init intc_of_init(struct device_node *node,
  }
  
  static struct of_device_id __initdata of_irq_ids[] = {
@@ -76,3 +80,6 @@ Patchwork: http://patchwork.linux-mips.org/patch/4900/
        { .compatible = "ralink,rt2880-intc", .data = intc_of_init },
        {},
  };
+-- 
+1.7.10.4
+
index 38ef41a..b995422 100644 (file)
@@ -1,8 +1,8 @@
-From c420811f117a59a4a7d4e34b362437b91c7fafa1 Mon Sep 17 00:00:00 2001
+From 219ec2244c2e9085e6900dc515a24f6655c79827 Mon Sep 17 00:00:00 2001
 From: John Crispin <blogic@openwrt.org>
 Date: Fri, 25 Jan 2013 19:39:51 +0100
-Subject: [PATCH] serial: ralink: adds support for the serial core found on
- ralink wisoc
+Subject: [PATCH 15/79] serial: ralink: adds support for the serial core found
on ralink wisoc
 
 The MIPS based Ralink WiSoC platform has 1 or more 8250 compatible serial cores.
 To make them work we require the same quirks that are used by AU1x00.
@@ -15,9 +15,11 @@ Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
  include/linux/serial_core.h     |    2 +-
  3 files changed, 12 insertions(+), 4 deletions(-)
 
+diff --git a/drivers/tty/serial/8250/8250.c b/drivers/tty/serial/8250/8250.c
+index f932043..f72eb7d 100644
 --- a/drivers/tty/serial/8250/8250.c
 +++ b/drivers/tty/serial/8250/8250.c
-@@ -345,9 +345,9 @@ static void default_serial_dl_write(stru
+@@ -324,9 +324,9 @@ static void default_serial_dl_write(struct uart_8250_port *up, int value)
        serial_out(up, UART_DLM, value >> 8 & 0xff);
  }
  
@@ -29,7 +31,7 @@ Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
  static const u8 au_io_in_map[] = {
        [UART_RX]  = 0,
        [UART_IER] = 2,
-@@ -527,7 +527,7 @@ static void set_io_from_upio(struct uart
+@@ -506,7 +506,7 @@ static void set_io_from_upio(struct uart_port *p)
                break;
  #endif
  
@@ -38,6 +40,8 @@ Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
        case UPIO_AU:
                p->serial_in = au_serial_in;
                p->serial_out = au_serial_out;
+diff --git a/drivers/tty/serial/8250/Kconfig b/drivers/tty/serial/8250/Kconfig
+index c31133a..9e4febd 100644
 --- a/drivers/tty/serial/8250/Kconfig
 +++ b/drivers/tty/serial/8250/Kconfig
 @@ -277,3 +277,11 @@ config SERIAL_8250_EM
@@ -52,6 +56,8 @@ Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
 +        If you have a Ralink RT288x/RT305x SoC based board and want to use the
 +        serial port, say Y to this option. The driver can handle up to 2 serial
 +        ports. If unsure, say N.
+diff --git a/include/linux/serial_core.h b/include/linux/serial_core.h
+index c6690a2..0b428d6 100644
 --- a/include/linux/serial_core.h
 +++ b/include/linux/serial_core.h
 @@ -134,7 +134,7 @@ struct uart_port {
@@ -63,3 +69,6 @@ Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
  #define UPIO_TSI              (5)                     /* Tsi108/109 type IO */
  #define UPIO_RM9000           (6)                     /* RM9000 type IO */
  
+-- 
+1.7.10.4
+
diff --git a/target/linux/ramips/patches-3.8/0016-MIPS-move-mips_-set-get-_machine_name-to-a-more-gene.patch b/target/linux/ramips/patches-3.8/0016-MIPS-move-mips_-set-get-_machine_name-to-a-more-gene.patch
new file mode 100644 (file)
index 0000000..8886cd7
--- /dev/null
@@ -0,0 +1,167 @@
+From 231e989ef4a11073ad6be8af797f96d51256d07a Mon Sep 17 00:00:00 2001
+From: John Crispin <blogic@openwrt.org>
+Date: Thu, 11 Apr 2013 05:34:59 +0000
+Subject: [PATCH 16/79] MIPS: move mips_{set,get}_machine_name() to a more
+ generic place
+
+Previously this functionality was only available to users of the mips_machine
+api. Moving the code to prom.c allows us to also add a OF wrapper.
+
+Signed-off-by: John Crispin <blogic@openwrt.org>
+Patchwork: http://patchwork.linux-mips.org/patch/5164/
+---
+ arch/mips/include/asm/mips_machine.h |    4 ----
+ arch/mips/include/asm/prom.h         |    3 +++
+ arch/mips/kernel/mips_machine.c      |   21 ---------------------
+ arch/mips/kernel/proc.c              |    2 +-
+ arch/mips/kernel/prom.c              |   31 +++++++++++++++++++++++++++++++
+ 5 files changed, 35 insertions(+), 26 deletions(-)
+
+diff --git a/arch/mips/include/asm/mips_machine.h b/arch/mips/include/asm/mips_machine.h
+index 363bb35..9d00aeb 100644
+--- a/arch/mips/include/asm/mips_machine.h
++++ b/arch/mips/include/asm/mips_machine.h
+@@ -42,13 +42,9 @@ extern long __mips_machines_end;
+ #ifdef CONFIG_MIPS_MACHINE
+ int  mips_machtype_setup(char *id) __init;
+ void mips_machine_setup(void) __init;
+-void mips_set_machine_name(const char *name) __init;
+-char *mips_get_machine_name(void);
+ #else
+ static inline int mips_machtype_setup(char *id) { return 1; }
+ static inline void mips_machine_setup(void) { }
+-static inline void mips_set_machine_name(const char *name) { }
+-static inline char *mips_get_machine_name(void) { return NULL; }
+ #endif /* CONFIG_MIPS_MACHINE */
+ #endif /* __ASM_MIPS_MACHINE_H */
+diff --git a/arch/mips/include/asm/prom.h b/arch/mips/include/asm/prom.h
+index 8808bf5..1e7e096 100644
+--- a/arch/mips/include/asm/prom.h
++++ b/arch/mips/include/asm/prom.h
+@@ -48,4 +48,7 @@ extern void __dt_setup_arch(struct boot_param_header *bph);
+ static inline void device_tree_init(void) { }
+ #endif /* CONFIG_OF */
++extern char *mips_get_machine_name(void);
++extern void mips_set_machine_name(const char *name);
++
+ #endif /* __ASM_PROM_H */
+diff --git a/arch/mips/kernel/mips_machine.c b/arch/mips/kernel/mips_machine.c
+index 411a058..6dc5866 100644
+--- a/arch/mips/kernel/mips_machine.c
++++ b/arch/mips/kernel/mips_machine.c
+@@ -13,7 +13,6 @@
+ #include <asm/mips_machine.h>
+ static struct mips_machine *mips_machine __initdata;
+-static char *mips_machine_name = "Unknown";
+ #define for_each_machine(mach) \
+       for ((mach) = (struct mips_machine *)&__mips_machines_start; \
+@@ -21,25 +20,6 @@ static char *mips_machine_name = "Unknown";
+            (unsigned long)(mach) < (unsigned long)&__mips_machines_end; \
+            (mach)++)
+-__init void mips_set_machine_name(const char *name)
+-{
+-      char *p;
+-
+-      if (name == NULL)
+-              return;
+-
+-      p = kstrdup(name, GFP_KERNEL);
+-      if (!p)
+-              pr_err("MIPS: no memory for machine_name\n");
+-
+-      mips_machine_name = p;
+-}
+-
+-char *mips_get_machine_name(void)
+-{
+-      return mips_machine_name;
+-}
+-
+ __init int mips_machtype_setup(char *id)
+ {
+       struct mips_machine *mach;
+@@ -79,7 +59,6 @@ __init void mips_machine_setup(void)
+               return;
+       mips_set_machine_name(mips_machine->mach_name);
+-      pr_info("MIPS: machine is %s\n", mips_machine_name);
+       if (mips_machine->mach_setup)
+               mips_machine->mach_setup();
+diff --git a/arch/mips/kernel/proc.c b/arch/mips/kernel/proc.c
+index 07dff54..8779237 100644
+--- a/arch/mips/kernel/proc.c
++++ b/arch/mips/kernel/proc.c
+@@ -12,7 +12,7 @@
+ #include <asm/cpu-features.h>
+ #include <asm/mipsregs.h>
+ #include <asm/processor.h>
+-#include <asm/mips_machine.h>
++#include <asm/prom.h>
+ unsigned int vced_count, vcei_count;
+diff --git a/arch/mips/kernel/prom.c b/arch/mips/kernel/prom.c
+index 028f6f8..b68e53b 100644
+--- a/arch/mips/kernel/prom.c
++++ b/arch/mips/kernel/prom.c
+@@ -23,6 +23,22 @@
+ #include <asm/page.h>
+ #include <asm/prom.h>
++static char mips_machine_name[64] = "Unknown";
++
++__init void mips_set_machine_name(const char *name)
++{
++      if (name == NULL)
++              return;
++
++      strncpy(mips_machine_name, name, sizeof(mips_machine_name));
++      pr_info("MIPS: machine is %s\n", mips_get_machine_name());
++}
++
++char *mips_get_machine_name(void)
++{
++      return mips_machine_name;
++}
++
+ int __init early_init_dt_scan_memory_arch(unsigned long node,
+                                         const char *uname, int depth,
+                                         void *data)
+@@ -50,6 +66,18 @@ void __init early_init_dt_setup_initrd_arch(unsigned long start,
+ }
+ #endif
++int __init early_init_dt_scan_model(unsigned long node,       const char *uname,
++                                  int depth, void *data)
++{
++      if (!depth) {
++              char *model = of_get_flat_dt_prop(node, "model", NULL);
++
++              if (model)
++                      mips_set_machine_name(model);
++      }
++      return 0;
++}
++
+ void __init early_init_devtree(void *params)
+ {
+       /* Setup flat device-tree pointer */
+@@ -65,6 +93,9 @@ void __init early_init_devtree(void *params)
+       /* Scan memory nodes */
+       of_scan_flat_dt(early_init_dt_scan_root, NULL);
+       of_scan_flat_dt(early_init_dt_scan_memory_arch, NULL);
++
++      /* try to load the mips machine name */
++      of_scan_flat_dt(early_init_dt_scan_model, NULL);
+ }
+ void __init __dt_setup_arch(struct boot_param_header *bph)
+-- 
+1.7.10.4
+
diff --git a/target/linux/ramips/patches-3.8/0017-MIPS-ralink-add-PCI-IRQ-handling.patch b/target/linux/ramips/patches-3.8/0017-MIPS-ralink-add-PCI-IRQ-handling.patch
new file mode 100644 (file)
index 0000000..c18817e
--- /dev/null
@@ -0,0 +1,40 @@
+From 98ab228172e66e43766d9e2a0ddb73603c22dbd1 Mon Sep 17 00:00:00 2001
+From: Gabor Juhos <juhosg@openwrt.org>
+Date: Wed, 10 Apr 2013 09:07:27 +0200
+Subject: [PATCH 17/79] MIPS: ralink: add PCI IRQ handling
+
+The Ralink IRQ code was not handling the PCI IRQ yet. Add this functionaility
+to make PCI work on rt3883.
+
+Signed-off-by: John Crispin <blogic@openwrt.org>
+Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
+Patchwork: http://patchwork.linux-mips.org/patch/5165/
+---
+ arch/mips/ralink/irq.c |    4 ++++
+ 1 file changed, 4 insertions(+)
+
+diff --git a/arch/mips/ralink/irq.c b/arch/mips/ralink/irq.c
+index 6d054c5..d9807d0 100644
+--- a/arch/mips/ralink/irq.c
++++ b/arch/mips/ralink/irq.c
+@@ -31,6 +31,7 @@
+ #define INTC_INT_GLOBAL               BIT(31)
+ #define RALINK_CPU_IRQ_INTC   (MIPS_CPU_IRQ_BASE + 2)
++#define RALINK_CPU_IRQ_PCI    (MIPS_CPU_IRQ_BASE + 4)
+ #define RALINK_CPU_IRQ_FE     (MIPS_CPU_IRQ_BASE + 5)
+ #define RALINK_CPU_IRQ_WIFI   (MIPS_CPU_IRQ_BASE + 6)
+ #define RALINK_CPU_IRQ_COUNTER        (MIPS_CPU_IRQ_BASE + 7)
+@@ -104,6 +105,9 @@ asmlinkage void plat_irq_dispatch(void)
+       else if (pending & STATUSF_IP6)
+               do_IRQ(RALINK_CPU_IRQ_WIFI);
++      else if (pending & STATUSF_IP4)
++              do_IRQ(RALINK_CPU_IRQ_PCI);
++
+       else if (pending & STATUSF_IP2)
+               do_IRQ(RALINK_CPU_IRQ_INTC);
+-- 
+1.7.10.4
+
diff --git a/target/linux/ramips/patches-3.8/0018-MIPS-ralink-add-RT3352-register-defines.patch b/target/linux/ramips/patches-3.8/0018-MIPS-ralink-add-RT3352-register-defines.patch
new file mode 100644 (file)
index 0000000..1a8950f
--- /dev/null
@@ -0,0 +1,40 @@
+From 8667d984d1b4f3be1c5da71788762b9945a25c90 Mon Sep 17 00:00:00 2001
+From: John Crispin <blogic@openwrt.org>
+Date: Thu, 21 Mar 2013 19:01:49 +0100
+Subject: [PATCH 18/79] MIPS: ralink: add RT3352 register defines
+
+Add a few missing defines that are needed to make USB and clock detection work
+on the RT3352.
+
+Signed-off-by: John Crispin <blogic@openwrt.org>
+Acked-by: Gabor Juhos <juhosg@openwrt.org>
+Patchwork: http://patchwork.linux-mips.org/patch/5166/
+---
+ arch/mips/include/asm/mach-ralink/rt305x.h |   13 +++++++++++++
+ 1 file changed, 13 insertions(+)
+
+diff --git a/arch/mips/include/asm/mach-ralink/rt305x.h b/arch/mips/include/asm/mach-ralink/rt305x.h
+index 7d344f2..e36c3c5 100644
+--- a/arch/mips/include/asm/mach-ralink/rt305x.h
++++ b/arch/mips/include/asm/mach-ralink/rt305x.h
+@@ -136,4 +136,17 @@ static inline int soc_is_rt5350(void)
+ #define RT305X_GPIO_MODE_SDRAM                BIT(8)
+ #define RT305X_GPIO_MODE_RGMII                BIT(9)
++#define RT3352_SYSC_REG_SYSCFG0               0x010
++#define RT3352_SYSC_REG_SYSCFG1         0x014
++#define RT3352_SYSC_REG_CLKCFG1         0x030
++#define RT3352_SYSC_REG_RSTCTRL         0x034
++#define RT3352_SYSC_REG_USB_PS          0x05c
++
++#define RT3352_CLKCFG0_XTAL_SEL               BIT(20)
++#define RT3352_CLKCFG1_UPHY0_CLK_EN   BIT(18)
++#define RT3352_CLKCFG1_UPHY1_CLK_EN   BIT(20)
++#define RT3352_RSTCTRL_UHST           BIT(22)
++#define RT3352_RSTCTRL_UDEV           BIT(25)
++#define RT3352_SYSCFG1_USB0_HOST_MODE BIT(10)
++
+ #endif
+-- 
+1.7.10.4
+
diff --git a/target/linux/ramips/patches-3.8/0019-MIPS-ralink-fix-RT305x-clock-setup.patch b/target/linux/ramips/patches-3.8/0019-MIPS-ralink-fix-RT305x-clock-setup.patch
new file mode 100644 (file)
index 0000000..ebecdf2
--- /dev/null
@@ -0,0 +1,52 @@
+From 853823a469a8123657bf32bc5e1843c40529a20d Mon Sep 17 00:00:00 2001
+From: John Crispin <blogic@openwrt.org>
+Date: Fri, 22 Mar 2013 19:25:59 +0100
+Subject: [PATCH 19/79] MIPS: ralink: fix RT305x clock setup
+
+Add a few missing clocks.
+
+Signed-off-by: John Crispin <blogic@openwrt.org>
+Acked-by: Gabor Juhos <juhosg@openwrt.org>
+Patchwork: http://patchwork.linux-mips.org/patch/5167/
+---
+ arch/mips/ralink/rt305x.c |   12 ++++++++++++
+ 1 file changed, 12 insertions(+)
+
+diff --git a/arch/mips/ralink/rt305x.c b/arch/mips/ralink/rt305x.c
+index 0a4bbdc..5d49a54 100644
+--- a/arch/mips/ralink/rt305x.c
++++ b/arch/mips/ralink/rt305x.c
+@@ -124,6 +124,8 @@ struct ralink_pinmux gpio_pinmux = {
+ void __init ralink_clk_init(void)
+ {
+       unsigned long cpu_rate, sys_rate, wdt_rate, uart_rate;
++      unsigned long wmac_rate = 40000000;
++
+       u32 t = rt_sysc_r32(SYSC_REG_SYSTEM_CONFIG);
+       if (soc_is_rt305x() || soc_is_rt3350()) {
+@@ -176,11 +178,21 @@ void __init ralink_clk_init(void)
+               BUG();
+       }
++      if (soc_is_rt3352() || soc_is_rt5350()) {
++              u32 val = rt_sysc_r32(RT3352_SYSC_REG_SYSCFG0);
++
++              if (!(val & RT3352_CLKCFG0_XTAL_SEL))
++                      wmac_rate = 20000000;
++      }
++
+       ralink_clk_add("cpu", cpu_rate);
+       ralink_clk_add("10000b00.spi", sys_rate);
+       ralink_clk_add("10000100.timer", wdt_rate);
++      ralink_clk_add("10000120.watchdog", wdt_rate);
+       ralink_clk_add("10000500.uart", uart_rate);
+       ralink_clk_add("10000c00.uartlite", uart_rate);
++      ralink_clk_add("10100000.ethernet", sys_rate);
++      ralink_clk_add("10180000.wmac", wmac_rate);
+ }
+ void __init ralink_of_remap(void)
+-- 
+1.7.10.4
+
diff --git a/target/linux/ramips/patches-3.8/0020-MIPS-ralink-add-missing-comment-in-irq-driver.patch b/target/linux/ramips/patches-3.8/0020-MIPS-ralink-add-missing-comment-in-irq-driver.patch
new file mode 100644 (file)
index 0000000..51cfe0c
--- /dev/null
@@ -0,0 +1,29 @@
+From 7c268f1b47669be2efce1607ee02193cb49424cf Mon Sep 17 00:00:00 2001
+From: John Crispin <blogic@openwrt.org>
+Date: Sat, 16 Mar 2013 16:28:54 +0100
+Subject: [PATCH 20/79] MIPS: ralink: add missing comment in irq driver
+
+Trivial patch that adds a comment that makes the code more readable.
+
+Signed-off-by: John Crispin <blogic@openwrt.org>
+Acked-by: Gabor Juhos <juhosg@openwrt.org>
+Patchwork: http://patchwork.linux-mips.org/patch/5168/
+---
+ arch/mips/ralink/irq.c |    1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/arch/mips/ralink/irq.c b/arch/mips/ralink/irq.c
+index d9807d0..320b1f1 100644
+--- a/arch/mips/ralink/irq.c
++++ b/arch/mips/ralink/irq.c
+@@ -166,6 +166,7 @@ static int __init intc_of_init(struct device_node *node,
+       irq_set_chained_handler(irq, ralink_intc_irq_handler);
+       irq_set_handler_data(irq, domain);
++      /* tell the kernel which irq is used for performance monitoring */
+       cp0_perfcount_irq = irq_create_mapping(domain, 9);
+       return 0;
+-- 
+1.7.10.4
+
diff --git a/target/linux/ramips/patches-3.8/0021-MIPS-ralink-add-RT5350-sdram-register-defines.patch b/target/linux/ramips/patches-3.8/0021-MIPS-ralink-add-RT5350-sdram-register-defines.patch
new file mode 100644 (file)
index 0000000..8ecaea2
--- /dev/null
@@ -0,0 +1,37 @@
+From 0df8c2fdd0fe1095b834fbf2b098d6f1b3e56608 Mon Sep 17 00:00:00 2001
+From: John Crispin <blogic@openwrt.org>
+Date: Mon, 25 Mar 2013 11:19:58 +0100
+Subject: [PATCH 21/79] MIPS: ralink: add RT5350 sdram register defines
+
+Add a few missing defines that are needed to make memory detection work on the
+RT5350.
+
+Signed-off-by: John Crispin <blogic@openwrt.org>
+Acked-by: Gabor Juhos <juhosg@openwrt.org>
+Patchwork: http://patchwork.linux-mips.org/patch/5169/
+---
+ arch/mips/include/asm/mach-ralink/rt305x.h |    8 ++++++++
+ 1 file changed, 8 insertions(+)
+
+diff --git a/arch/mips/include/asm/mach-ralink/rt305x.h b/arch/mips/include/asm/mach-ralink/rt305x.h
+index e36c3c5..80cda8a 100644
+--- a/arch/mips/include/asm/mach-ralink/rt305x.h
++++ b/arch/mips/include/asm/mach-ralink/rt305x.h
+@@ -97,6 +97,14 @@ static inline int soc_is_rt5350(void)
+ #define RT5350_SYSCFG0_CPUCLK_320     0x2
+ #define RT5350_SYSCFG0_CPUCLK_300     0x3
++#define RT5350_SYSCFG0_DRAM_SIZE_SHIFT  12
++#define RT5350_SYSCFG0_DRAM_SIZE_MASK   7
++#define RT5350_SYSCFG0_DRAM_SIZE_2M     0
++#define RT5350_SYSCFG0_DRAM_SIZE_8M     1
++#define RT5350_SYSCFG0_DRAM_SIZE_16M    2
++#define RT5350_SYSCFG0_DRAM_SIZE_32M    3
++#define RT5350_SYSCFG0_DRAM_SIZE_64M    4
++
+ /* multi function gpio pins */
+ #define RT305X_GPIO_I2C_SD            1
+ #define RT305X_GPIO_I2C_SCLK          2
+-- 
+1.7.10.4
+
diff --git a/target/linux/ramips/patches-3.8/0022-MIPS-ralink-make-early_printk-work-on-RT2880.patch b/target/linux/ramips/patches-3.8/0022-MIPS-ralink-make-early_printk-work-on-RT2880.patch
new file mode 100644 (file)
index 0000000..2788397
--- /dev/null
@@ -0,0 +1,33 @@
+From 9ed190912864c8b96d888af2cb66efcf1dc5562a Mon Sep 17 00:00:00 2001
+From: John Crispin <blogic@openwrt.org>
+Date: Tue, 9 Apr 2013 18:31:15 +0200
+Subject: [PATCH 22/79] MIPS: ralink: make early_printk work on RT2880
+
+RT2880 has a different location for the early serial port.
+
+Signed-off-by: John Crispin <blogic@openwrt.org>
+Acked-by: Gabor Juhos <juhosg@openwrt.org>
+Patchwork: http://patchwork.linux-mips.org/patch/5170/
+---
+ arch/mips/ralink/early_printk.c |    4 ++++
+ 1 file changed, 4 insertions(+)
+
+diff --git a/arch/mips/ralink/early_printk.c b/arch/mips/ralink/early_printk.c
+index c4ae47e..b46d041 100644
+--- a/arch/mips/ralink/early_printk.c
++++ b/arch/mips/ralink/early_printk.c
+@@ -11,7 +11,11 @@
+ #include <asm/addrspace.h>
++#ifdef CONFIG_SOC_RT288X
++#define EARLY_UART_BASE         0x300c00
++#else
+ #define EARLY_UART_BASE         0x10000c00
++#endif
+ #define UART_REG_RX             0x00
+ #define UART_REG_TX             0x04
+-- 
+1.7.10.4
+
diff --git a/target/linux/ramips/patches-3.8/0023-MIPS-ralink-rename-gpio_pinmux-to-rt_gpio_pinmux.patch b/target/linux/ramips/patches-3.8/0023-MIPS-ralink-rename-gpio_pinmux-to-rt_gpio_pinmux.patch
new file mode 100644 (file)
index 0000000..03d95df
--- /dev/null
@@ -0,0 +1,43 @@
+From d5b75031f6ad0f9f82c3b8faeab3cda1cb4ebfe9 Mon Sep 17 00:00:00 2001
+From: John Crispin <blogic@openwrt.org>
+Date: Fri, 12 Apr 2013 22:12:09 +0200
+Subject: [PATCH 23/79] MIPS: ralink: rename gpio_pinmux to rt_gpio_pinmux
+
+Add proper namespacing to the variable.
+
+Signed-off-by: John Crispin <blogic@openwrt.org>
+Patchwork: http://patchwork.linux-mips.org/patch/5171/
+---
+ arch/mips/ralink/common.h |    2 +-
+ arch/mips/ralink/rt305x.c |    2 +-
+ 2 files changed, 2 insertions(+), 2 deletions(-)
+
+diff --git a/arch/mips/ralink/common.h b/arch/mips/ralink/common.h
+index 3009903..f4b19c6 100644
+--- a/arch/mips/ralink/common.h
++++ b/arch/mips/ralink/common.h
+@@ -24,7 +24,7 @@ struct ralink_pinmux {
+       int uart_shift;
+       void (*wdt_reset)(void);
+ };
+-extern struct ralink_pinmux gpio_pinmux;
++extern struct ralink_pinmux rt_gpio_pinmux;
+ struct ralink_soc_info {
+       unsigned char sys_type[RAMIPS_SYS_TYPE_LEN];
+diff --git a/arch/mips/ralink/rt305x.c b/arch/mips/ralink/rt305x.c
+index 5d49a54..f1a6c33 100644
+--- a/arch/mips/ralink/rt305x.c
++++ b/arch/mips/ralink/rt305x.c
+@@ -114,7 +114,7 @@ void rt305x_wdt_reset(void)
+       rt_sysc_w32(t, SYSC_REG_SYSTEM_CONFIG);
+ }
+-struct ralink_pinmux gpio_pinmux = {
++struct ralink_pinmux rt_gpio_pinmux = {
+       .mode = mode_mux,
+       .uart = uart_mux,
+       .uart_shift = RT305X_GPIO_MODE_UART0_SHIFT,
+-- 
+1.7.10.4
+
diff --git a/target/linux/ramips/patches-3.8/0024-MIPS-ralink-make-the-RT305x-pinmuxing-structure-stat.patch b/target/linux/ramips/patches-3.8/0024-MIPS-ralink-make-the-RT305x-pinmuxing-structure-stat.patch
new file mode 100644 (file)
index 0000000..60a8a53
--- /dev/null
@@ -0,0 +1,49 @@
+From 2793deaf4d3d364ba2ed075abf2b9022a152f253 Mon Sep 17 00:00:00 2001
+From: John Crispin <blogic@openwrt.org>
+Date: Fri, 12 Apr 2013 22:16:12 +0200
+Subject: [PATCH 24/79] MIPS: ralink: make the RT305x pinmuxing structure
+ static
+
+These structures are exported via struct ralink_pinmux rt_gpio_pinmux and can
+hence be static.
+
+Signed-off-by: John Crispin <blogic@openwrt.org>
+Patchwork: http://patchwork.linux-mips.org/patch/5172/
+---
+ arch/mips/ralink/rt305x.c |    6 +++---
+ 1 file changed, 3 insertions(+), 3 deletions(-)
+
+diff --git a/arch/mips/ralink/rt305x.c b/arch/mips/ralink/rt305x.c
+index f1a6c33..5b42078 100644
+--- a/arch/mips/ralink/rt305x.c
++++ b/arch/mips/ralink/rt305x.c
+@@ -22,7 +22,7 @@
+ enum rt305x_soc_type rt305x_soc;
+-struct ralink_pinmux_grp mode_mux[] = {
++static struct ralink_pinmux_grp mode_mux[] = {
+       {
+               .name = "i2c",
+               .mask = RT305X_GPIO_MODE_I2C,
+@@ -61,7 +61,7 @@ struct ralink_pinmux_grp mode_mux[] = {
+       }, {0}
+ };
+-struct ralink_pinmux_grp uart_mux[] = {
++static struct ralink_pinmux_grp uart_mux[] = {
+       {
+               .name = "uartf",
+               .mask = RT305X_GPIO_MODE_UARTF,
+@@ -103,7 +103,7 @@ struct ralink_pinmux_grp uart_mux[] = {
+       }, {0}
+ };
+-void rt305x_wdt_reset(void)
++static void rt305x_wdt_reset(void)
+ {
+       u32 t;
+-- 
+1.7.10.4
+
diff --git a/target/linux/ramips/patches-3.8/0025-MIPS-ralink-add-pci-group-to-struct-ralink_pinmux.patch b/target/linux/ramips/patches-3.8/0025-MIPS-ralink-add-pci-group-to-struct-ralink_pinmux.patch
new file mode 100644 (file)
index 0000000..368fcde
--- /dev/null
@@ -0,0 +1,31 @@
+From e859bf709e73acb5735cf1207422f53fc3202632 Mon Sep 17 00:00:00 2001
+From: Gabor Juhos <juhosg@openwrt.org>
+Date: Fri, 12 Apr 2013 12:40:23 +0200
+Subject: [PATCH 25/79] MIPS: ralink: add pci group to struct ralink_pinmux
+
+This will be used for RT3662/RT3883.
+
+Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
+Acked-by: John Crispin <blogic@openwrt.org>
+Patchwork: http://patchwork.linux-mips.org/patch/5173/
+---
+ arch/mips/ralink/common.h |    3 +++
+ 1 file changed, 3 insertions(+)
+
+diff --git a/arch/mips/ralink/common.h b/arch/mips/ralink/common.h
+index f4b19c6..bebd149 100644
+--- a/arch/mips/ralink/common.h
++++ b/arch/mips/ralink/common.h
+@@ -23,6 +23,9 @@ struct ralink_pinmux {
+       struct ralink_pinmux_grp *uart;
+       int uart_shift;
+       void (*wdt_reset)(void);
++      struct ralink_pinmux_grp *pci;
++      int pci_shift;
++      u32 pci_mask;
+ };
+ extern struct ralink_pinmux rt_gpio_pinmux;
+-- 
+1.7.10.4
+
diff --git a/target/linux/ramips/patches-3.8/0026-MIPS-ralink-add-uart-mask-to-struct-ralink_pinmux.patch b/target/linux/ramips/patches-3.8/0026-MIPS-ralink-add-uart-mask-to-struct-ralink_pinmux.patch
new file mode 100644 (file)
index 0000000..1ee9fd4
--- /dev/null
@@ -0,0 +1,56 @@
+From 6e09e0465b342b52ecda583cbc41e6a31c363b3f Mon Sep 17 00:00:00 2001
+From: John Crispin <blogic@openwrt.org>
+Date: Fri, 12 Apr 2013 12:45:27 +0200
+Subject: [PATCH 26/79] MIPS: ralink: add uart mask to struct ralink_pinmux
+
+Add a field for the uart muxing mask and set it inside the rt305x setup code.
+
+Signed-off-by: John Crispin <blogic@openwrt.org>
+Patchwork: http://patchwork.linux-mips.org/patch/5744/
+---
+ arch/mips/ralink/common.h |    1 +
+ arch/mips/ralink/rt305x.c |    5 +++--
+ 2 files changed, 4 insertions(+), 2 deletions(-)
+
+diff --git a/arch/mips/ralink/common.h b/arch/mips/ralink/common.h
+index bebd149..299119b 100644
+--- a/arch/mips/ralink/common.h
++++ b/arch/mips/ralink/common.h
+@@ -22,6 +22,7 @@ struct ralink_pinmux {
+       struct ralink_pinmux_grp *mode;
+       struct ralink_pinmux_grp *uart;
+       int uart_shift;
++      u32 uart_mask;
+       void (*wdt_reset)(void);
+       struct ralink_pinmux_grp *pci;
+       int pci_shift;
+diff --git a/arch/mips/ralink/rt305x.c b/arch/mips/ralink/rt305x.c
+index 5b42078..6aa3cb1 100644
+--- a/arch/mips/ralink/rt305x.c
++++ b/arch/mips/ralink/rt305x.c
+@@ -91,12 +91,12 @@ static struct ralink_pinmux_grp uart_mux[] = {
+               .name = "gpio uartf",
+               .mask = RT305X_GPIO_MODE_GPIO_UARTF,
+               .gpio_first = RT305X_GPIO_7,
+-              .gpio_last = RT305X_GPIO_14,
++              .gpio_last = RT305X_GPIO_10,
+       }, {
+               .name = "gpio i2s",
+               .mask = RT305X_GPIO_MODE_GPIO_I2S,
+               .gpio_first = RT305X_GPIO_7,
+-              .gpio_last = RT305X_GPIO_14,
++              .gpio_last = RT305X_GPIO_10,
+       }, {
+               .name = "gpio",
+               .mask = RT305X_GPIO_MODE_GPIO,
+@@ -118,6 +118,7 @@ struct ralink_pinmux rt_gpio_pinmux = {
+       .mode = mode_mux,
+       .uart = uart_mux,
+       .uart_shift = RT305X_GPIO_MODE_UART0_SHIFT,
++      .uart_mask = RT305X_GPIO_MODE_UART0_MASK,
+       .wdt_reset = rt305x_wdt_reset,
+ };
+-- 
+1.7.10.4
+
diff --git a/target/linux/ramips/patches-3.8/0027-MIPS-ralink-adds-support-for-RT2880-SoC-family.patch b/target/linux/ramips/patches-3.8/0027-MIPS-ralink-adds-support-for-RT2880-SoC-family.patch
new file mode 100644 (file)
index 0000000..bd8ad22
--- /dev/null
@@ -0,0 +1,281 @@
+From 2a0d9878985bb3274bb61535f76ea293991635a9 Mon Sep 17 00:00:00 2001
+From: John Crispin <blogic@openwrt.org>
+Date: Sun, 27 Jan 2013 09:17:20 +0100
+Subject: [PATCH 27/79] MIPS: ralink: adds support for RT2880 SoC family
+
+Add support code for rt2880 SOC.
+
+The code detects the SoC and registers the clk / pinmux settings.
+
+Signed-off-by: John Crispin <blogic@openwrt.org>
+Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
+Patchwork: http://patchwork.linux-mips.org/patch/5176/
+---
+ arch/mips/Kconfig                          |    2 +-
+ arch/mips/include/asm/mach-ralink/rt288x.h |   49 ++++++++++
+ arch/mips/ralink/Kconfig                   |    3 +
+ arch/mips/ralink/Makefile                  |    1 +
+ arch/mips/ralink/Platform                  |    5 +
+ arch/mips/ralink/rt288x.c                  |  139 ++++++++++++++++++++++++++++
+ 6 files changed, 198 insertions(+), 1 deletion(-)
+ create mode 100644 arch/mips/include/asm/mach-ralink/rt288x.h
+ create mode 100644 arch/mips/ralink/rt288x.c
+
+diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
+index b5081b5..b5fd476 100644
+--- a/arch/mips/Kconfig
++++ b/arch/mips/Kconfig
+@@ -1177,7 +1177,7 @@ config BOOT_ELF32
+ config MIPS_L1_CACHE_SHIFT
+       int
+-      default "4" if MACH_DECSTATION || MIKROTIK_RB532 || PMC_MSP4200_EVAL
++      default "4" if MACH_DECSTATION || MIKROTIK_RB532 || PMC_MSP4200_EVAL || SOC_RT288X
+       default "6" if MIPS_CPU_SCACHE
+       default "7" if SGI_IP22 || SGI_IP27 || SGI_IP28 || SNI_RM || CPU_CAVIUM_OCTEON
+       default "5"
+diff --git a/arch/mips/include/asm/mach-ralink/rt288x.h b/arch/mips/include/asm/mach-ralink/rt288x.h
+new file mode 100644
+index 0000000..ad8b42d
+--- /dev/null
++++ b/arch/mips/include/asm/mach-ralink/rt288x.h
+@@ -0,0 +1,49 @@
++/*
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of the GNU General Public License version 2 as published
++ * by the Free Software Foundation.
++ *
++ * Parts of this file are based on Ralink's 2.6.21 BSP
++ *
++ * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
++ * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
++ * Copyright (C) 2013 John Crispin <blogic@openwrt.org>
++ */
++
++#ifndef _RT288X_REGS_H_
++#define _RT288X_REGS_H_
++
++#define RT2880_SYSC_BASE              0x00300000
++
++#define SYSC_REG_CHIP_NAME0           0x00
++#define SYSC_REG_CHIP_NAME1           0x04
++#define SYSC_REG_CHIP_ID              0x0c
++#define SYSC_REG_SYSTEM_CONFIG                0x10
++#define SYSC_REG_CLKCFG                       0x30
++
++#define RT2880_CHIP_NAME0             0x38325452
++#define RT2880_CHIP_NAME1             0x20203038
++
++#define CHIP_ID_ID_MASK                       0xff
++#define CHIP_ID_ID_SHIFT              8
++#define CHIP_ID_REV_MASK              0xff
++
++#define SYSTEM_CONFIG_CPUCLK_SHIFT    20
++#define SYSTEM_CONFIG_CPUCLK_MASK     0x3
++#define SYSTEM_CONFIG_CPUCLK_250      0x0
++#define SYSTEM_CONFIG_CPUCLK_266      0x1
++#define SYSTEM_CONFIG_CPUCLK_280      0x2
++#define SYSTEM_CONFIG_CPUCLK_300      0x3
++
++#define RT2880_GPIO_MODE_I2C          BIT(0)
++#define RT2880_GPIO_MODE_UART0                BIT(1)
++#define RT2880_GPIO_MODE_SPI          BIT(2)
++#define RT2880_GPIO_MODE_UART1                BIT(3)
++#define RT2880_GPIO_MODE_JTAG         BIT(4)
++#define RT2880_GPIO_MODE_MDIO         BIT(5)
++#define RT2880_GPIO_MODE_SDRAM                BIT(6)
++#define RT2880_GPIO_MODE_PCI          BIT(7)
++
++#define CLKCFG_SRAM_CS_N_WDT          BIT(9)
++
++#endif
+diff --git a/arch/mips/ralink/Kconfig b/arch/mips/ralink/Kconfig
+index a0b0197..6723b94 100644
+--- a/arch/mips/ralink/Kconfig
++++ b/arch/mips/ralink/Kconfig
+@@ -6,6 +6,9 @@ choice
+       help
+         Select Ralink MIPS SoC type.
++      config SOC_RT288X
++              bool "RT288x"
++
+       config SOC_RT305X
+               bool "RT305x"
+               select USB_ARCH_HAS_HCD
+diff --git a/arch/mips/ralink/Makefile b/arch/mips/ralink/Makefile
+index 939757f..6d826f2 100644
+--- a/arch/mips/ralink/Makefile
++++ b/arch/mips/ralink/Makefile
+@@ -8,6 +8,7 @@
+ obj-y := prom.o of.o reset.o clk.o irq.o
++obj-$(CONFIG_SOC_RT288X) += rt288x.o
+ obj-$(CONFIG_SOC_RT305X) += rt305x.o
+ obj-$(CONFIG_EARLY_PRINTK) += early_printk.o
+diff --git a/arch/mips/ralink/Platform b/arch/mips/ralink/Platform
+index 6babd65..3f49e51 100644
+--- a/arch/mips/ralink/Platform
++++ b/arch/mips/ralink/Platform
+@@ -5,6 +5,11 @@ core-$(CONFIG_RALINK)         += arch/mips/ralink/
+ cflags-$(CONFIG_RALINK)               += -I$(srctree)/arch/mips/include/asm/mach-ralink
+ #
++# Ralink RT288x
++#
++load-$(CONFIG_SOC_RT288X)     += 0xffffffff88000000
++
++#
+ # Ralink RT305x
+ #
+ load-$(CONFIG_SOC_RT305X)     += 0xffffffff80000000
+diff --git a/arch/mips/ralink/rt288x.c b/arch/mips/ralink/rt288x.c
+new file mode 100644
+index 0000000..1e0788e
+--- /dev/null
++++ b/arch/mips/ralink/rt288x.c
+@@ -0,0 +1,139 @@
++/*
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of the GNU General Public License version 2 as published
++ * by the Free Software Foundation.
++ *
++ * Parts of this file are based on Ralink's 2.6.21 BSP
++ *
++ * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
++ * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
++ * Copyright (C) 2013 John Crispin <blogic@openwrt.org>
++ */
++
++#include <linux/kernel.h>
++#include <linux/init.h>
++#include <linux/module.h>
++
++#include <asm/mipsregs.h>
++#include <asm/mach-ralink/ralink_regs.h>
++#include <asm/mach-ralink/rt288x.h>
++
++#include "common.h"
++
++static struct ralink_pinmux_grp mode_mux[] = {
++      {
++              .name = "i2c",
++              .mask = RT2880_GPIO_MODE_I2C,
++              .gpio_first = 1,
++              .gpio_last = 2,
++      }, {
++              .name = "spi",
++              .mask = RT2880_GPIO_MODE_SPI,
++              .gpio_first = 3,
++              .gpio_last = 6,
++      }, {
++              .name = "uartlite",
++              .mask = RT2880_GPIO_MODE_UART0,
++              .gpio_first = 7,
++              .gpio_last = 14,
++      }, {
++              .name = "jtag",
++              .mask = RT2880_GPIO_MODE_JTAG,
++              .gpio_first = 17,
++              .gpio_last = 21,
++      }, {
++              .name = "mdio",
++              .mask = RT2880_GPIO_MODE_MDIO,
++              .gpio_first = 22,
++              .gpio_last = 23,
++      }, {
++              .name = "sdram",
++              .mask = RT2880_GPIO_MODE_SDRAM,
++              .gpio_first = 24,
++              .gpio_last = 39,
++      }, {
++              .name = "pci",
++              .mask = RT2880_GPIO_MODE_PCI,
++              .gpio_first = 40,
++              .gpio_last = 71,
++      }, {0}
++};
++
++static void rt288x_wdt_reset(void)
++{
++      u32 t;
++
++      /* enable WDT reset output on pin SRAM_CS_N */
++      t = rt_sysc_r32(SYSC_REG_CLKCFG);
++      t |= CLKCFG_SRAM_CS_N_WDT;
++      rt_sysc_w32(t, SYSC_REG_CLKCFG);
++}
++
++struct ralink_pinmux rt_gpio_pinmux = {
++      .mode = mode_mux,
++      .wdt_reset = rt288x_wdt_reset,
++};
++
++void __init ralink_clk_init(void)
++{
++      unsigned long cpu_rate;
++      u32 t = rt_sysc_r32(SYSC_REG_SYSTEM_CONFIG);
++      t = ((t >> SYSTEM_CONFIG_CPUCLK_SHIFT) & SYSTEM_CONFIG_CPUCLK_MASK);
++
++      switch (t) {
++      case SYSTEM_CONFIG_CPUCLK_250:
++              cpu_rate = 250000000;
++              break;
++      case SYSTEM_CONFIG_CPUCLK_266:
++              cpu_rate = 266666667;
++              break;
++      case SYSTEM_CONFIG_CPUCLK_280:
++              cpu_rate = 280000000;
++              break;
++      case SYSTEM_CONFIG_CPUCLK_300:
++              cpu_rate = 300000000;
++              break;
++      }
++
++      ralink_clk_add("cpu", cpu_rate);
++      ralink_clk_add("300100.timer", cpu_rate / 2);
++      ralink_clk_add("300120.watchdog", cpu_rate / 2);
++      ralink_clk_add("300500.uart", cpu_rate / 2);
++      ralink_clk_add("300c00.uartlite", cpu_rate / 2);
++      ralink_clk_add("400000.ethernet", cpu_rate / 2);
++}
++
++void __init ralink_of_remap(void)
++{
++      rt_sysc_membase = plat_of_remap_node("ralink,rt2880-sysc");
++      rt_memc_membase = plat_of_remap_node("ralink,rt2880-memc");
++
++      if (!rt_sysc_membase || !rt_memc_membase)
++              panic("Failed to remap core resources");
++}
++
++void prom_soc_init(struct ralink_soc_info *soc_info)
++{
++      void __iomem *sysc = (void __iomem *) KSEG1ADDR(RT2880_SYSC_BASE);
++      const char *name;
++      u32 n0;
++      u32 n1;
++      u32 id;
++
++      n0 = __raw_readl(sysc + SYSC_REG_CHIP_NAME0);
++      n1 = __raw_readl(sysc + SYSC_REG_CHIP_NAME1);
++      id = __raw_readl(sysc + SYSC_REG_CHIP_ID);
++
++      if (n0 == RT2880_CHIP_NAME0 && n1 == RT2880_CHIP_NAME1) {
++              soc_info->compatible = "ralink,r2880-soc";
++              name = "RT2880";
++      } else {
++              panic("rt288x: unknown SoC, n0:%08x n1:%08x", n0, n1);
++      }
++
++      snprintf(soc_info->sys_type, RAMIPS_SYS_TYPE_LEN,
++              "Ralink %s id:%u rev:%u",
++              name,
++              (id >> CHIP_ID_ID_SHIFT) & CHIP_ID_ID_MASK,
++              (id & CHIP_ID_REV_MASK));
++}
+-- 
+1.7.10.4
+
diff --git a/target/linux/ramips/patches-3.8/0028-MIPS-ralink-adds-support-for-RT3883-SoC-family.patch b/target/linux/ramips/patches-3.8/0028-MIPS-ralink-adds-support-for-RT3883-SoC-family.patch
new file mode 100644 (file)
index 0000000..f124fec
--- /dev/null
@@ -0,0 +1,567 @@
+From c75f4a5af758494595fded27efb95732365d10db Mon Sep 17 00:00:00 2001
+From: John Crispin <blogic@openwrt.org>
+Date: Sun, 27 Jan 2013 09:39:02 +0100
+Subject: [PATCH 28/79] MIPS: ralink: adds support for RT3883 SoC family
+
+Add support code for rt3883 SOC.
+
+The code detects the SoC and registers the clk / pinmux settings.
+
+Signed-off-by: John Crispin <blogic@openwrt.org>
+Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
+Patchwork: http://patchwork.linux-mips.org/patch/5185/
+---
+ arch/mips/include/asm/mach-ralink/rt3883.h |  247 ++++++++++++++++++++++++++++
+ arch/mips/ralink/Kconfig                   |    5 +
+ arch/mips/ralink/Makefile                  |    1 +
+ arch/mips/ralink/Platform                  |    5 +
+ arch/mips/ralink/rt3883.c                  |  242 +++++++++++++++++++++++++++
+ 5 files changed, 500 insertions(+)
+ create mode 100644 arch/mips/include/asm/mach-ralink/rt3883.h
+ create mode 100644 arch/mips/ralink/rt3883.c
+
+diff --git a/arch/mips/include/asm/mach-ralink/rt3883.h b/arch/mips/include/asm/mach-ralink/rt3883.h
+new file mode 100644
+index 0000000..b91c6c1
+--- /dev/null
++++ b/arch/mips/include/asm/mach-ralink/rt3883.h
+@@ -0,0 +1,247 @@
++/*
++ * Ralink RT3662/RT3883 SoC register definitions
++ *
++ * Copyright (C) 2011-2012 Gabor Juhos <juhosg@openwrt.org>
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of the GNU General Public License version 2 as published
++ * by the Free Software Foundation.
++ */
++
++#ifndef _RT3883_REGS_H_
++#define _RT3883_REGS_H_
++
++#include <linux/bitops.h>
++
++#define RT3883_SDRAM_BASE     0x00000000
++#define RT3883_SYSC_BASE      0x10000000
++#define RT3883_TIMER_BASE     0x10000100
++#define RT3883_INTC_BASE      0x10000200
++#define RT3883_MEMC_BASE      0x10000300
++#define RT3883_UART0_BASE     0x10000500
++#define RT3883_PIO_BASE               0x10000600
++#define RT3883_FSCC_BASE      0x10000700
++#define RT3883_NANDC_BASE     0x10000810
++#define RT3883_I2C_BASE               0x10000900
++#define RT3883_I2S_BASE               0x10000a00
++#define RT3883_SPI_BASE               0x10000b00
++#define RT3883_UART1_BASE     0x10000c00
++#define RT3883_PCM_BASE               0x10002000
++#define RT3883_GDMA_BASE      0x10002800
++#define RT3883_CODEC1_BASE    0x10003000
++#define RT3883_CODEC2_BASE    0x10003800
++#define RT3883_FE_BASE                0x10100000
++#define RT3883_ROM_BASE               0x10118000
++#define RT3883_USBDEV_BASE    0x10112000
++#define RT3883_PCI_BASE               0x10140000
++#define RT3883_WLAN_BASE      0x10180000
++#define RT3883_USBHOST_BASE   0x101c0000
++#define RT3883_BOOT_BASE      0x1c000000
++#define RT3883_SRAM_BASE      0x1e000000
++#define RT3883_PCIMEM_BASE    0x20000000
++
++#define RT3883_EHCI_BASE      (RT3883_USBHOST_BASE)
++#define RT3883_OHCI_BASE      (RT3883_USBHOST_BASE + 0x1000)
++
++#define RT3883_SYSC_SIZE      0x100
++#define RT3883_TIMER_SIZE     0x100
++#define RT3883_INTC_SIZE      0x100
++#define RT3883_MEMC_SIZE      0x100
++#define RT3883_UART0_SIZE     0x100
++#define RT3883_UART1_SIZE     0x100
++#define RT3883_PIO_SIZE               0x100
++#define RT3883_FSCC_SIZE      0x100
++#define RT3883_NANDC_SIZE     0x0f0
++#define RT3883_I2C_SIZE               0x100
++#define RT3883_I2S_SIZE               0x100
++#define RT3883_SPI_SIZE               0x100
++#define RT3883_PCM_SIZE               0x800
++#define RT3883_GDMA_SIZE      0x800
++#define RT3883_CODEC1_SIZE    0x800
++#define RT3883_CODEC2_SIZE    0x800
++#define RT3883_FE_SIZE                0x10000
++#define RT3883_ROM_SIZE               0x4000
++#define RT3883_USBDEV_SIZE    0x4000
++#define RT3883_PCI_SIZE               0x40000
++#define RT3883_WLAN_SIZE      0x40000
++#define RT3883_USBHOST_SIZE   0x40000
++#define RT3883_BOOT_SIZE      (32 * 1024 * 1024)
++#define RT3883_SRAM_SIZE      (32 * 1024 * 1024)
++
++/* SYSC registers */
++#define RT3883_SYSC_REG_CHIPID0_3     0x00    /* Chip ID 0 */
++#define RT3883_SYSC_REG_CHIPID4_7     0x04    /* Chip ID 1 */
++#define RT3883_SYSC_REG_REVID         0x0c    /* Chip Revision Identification */
++#define RT3883_SYSC_REG_SYSCFG0               0x10    /* System Configuration 0 */
++#define RT3883_SYSC_REG_SYSCFG1               0x14    /* System Configuration 1 */
++#define RT3883_SYSC_REG_CLKCFG0               0x2c    /* Clock Configuration 0 */
++#define RT3883_SYSC_REG_CLKCFG1               0x30    /* Clock Configuration 1 */
++#define RT3883_SYSC_REG_RSTCTRL               0x34    /* Reset Control*/
++#define RT3883_SYSC_REG_RSTSTAT               0x38    /* Reset Status*/
++#define RT3883_SYSC_REG_USB_PS                0x5c    /* USB Power saving control */
++#define RT3883_SYSC_REG_GPIO_MODE     0x60    /* GPIO Purpose Select */
++#define RT3883_SYSC_REG_PCIE_CLK_GEN0 0x7c
++#define RT3883_SYSC_REG_PCIE_CLK_GEN1 0x80
++#define RT3883_SYSC_REG_PCIE_CLK_GEN2 0x84
++#define RT3883_SYSC_REG_PMU           0x88
++#define RT3883_SYSC_REG_PMU1          0x8c
++
++#define RT3883_CHIP_NAME0             0x38335452
++#define RT3883_CHIP_NAME1             0x20203338
++
++#define RT3883_REVID_VER_ID_MASK      0x0f
++#define RT3883_REVID_VER_ID_SHIFT     8
++#define RT3883_REVID_ECO_ID_MASK      0x0f
++
++#define RT3883_SYSCFG0_DRAM_TYPE_DDR2 BIT(17)
++#define RT3883_SYSCFG0_CPUCLK_SHIFT   8
++#define RT3883_SYSCFG0_CPUCLK_MASK    0x3
++#define RT3883_SYSCFG0_CPUCLK_250     0x0
++#define RT3883_SYSCFG0_CPUCLK_384     0x1
++#define RT3883_SYSCFG0_CPUCLK_480     0x2
++#define RT3883_SYSCFG0_CPUCLK_500     0x3
++
++#define RT3883_SYSCFG1_USB0_HOST_MODE BIT(10)
++#define RT3883_SYSCFG1_PCIE_RC_MODE   BIT(8)
++#define RT3883_SYSCFG1_PCI_HOST_MODE  BIT(7)
++#define RT3883_SYSCFG1_PCI_66M_MODE   BIT(6)
++#define RT3883_SYSCFG1_GPIO2_AS_WDT_OUT       BIT(2)
++
++#define RT3883_CLKCFG1_PCIE_CLK_EN    BIT(21)
++#define RT3883_CLKCFG1_UPHY1_CLK_EN   BIT(20)
++#define RT3883_CLKCFG1_PCI_CLK_EN     BIT(19)
++#define RT3883_CLKCFG1_UPHY0_CLK_EN   BIT(18)
++
++#define RT3883_GPIO_MODE_I2C          BIT(0)
++#define RT3883_GPIO_MODE_SPI          BIT(1)
++#define RT3883_GPIO_MODE_UART0_SHIFT  2
++#define RT3883_GPIO_MODE_UART0_MASK   0x7
++#define RT3883_GPIO_MODE_UART0(x)     ((x) << RT3883_GPIO_MODE_UART0_SHIFT)
++#define RT3883_GPIO_MODE_UARTF                0x0
++#define RT3883_GPIO_MODE_PCM_UARTF    0x1
++#define RT3883_GPIO_MODE_PCM_I2S      0x2
++#define RT3883_GPIO_MODE_I2S_UARTF    0x3
++#define RT3883_GPIO_MODE_PCM_GPIO     0x4
++#define RT3883_GPIO_MODE_GPIO_UARTF   0x5
++#define RT3883_GPIO_MODE_GPIO_I2S     0x6
++#define RT3883_GPIO_MODE_GPIO         0x7
++#define RT3883_GPIO_MODE_UART1                BIT(5)
++#define RT3883_GPIO_MODE_JTAG         BIT(6)
++#define RT3883_GPIO_MODE_MDIO         BIT(7)
++#define RT3883_GPIO_MODE_GE1          BIT(9)
++#define RT3883_GPIO_MODE_GE2          BIT(10)
++#define RT3883_GPIO_MODE_PCI_SHIFT    11
++#define RT3883_GPIO_MODE_PCI_MASK     0x7
++#define RT3883_GPIO_MODE_PCI          (RT3883_GPIO_MODE_PCI_MASK << RT3883_GPIO_MODE_PCI_SHIFT)
++#define RT3883_GPIO_MODE_LNA_A_SHIFT  16
++#define RT3883_GPIO_MODE_LNA_A_MASK   0x3
++#define _RT3883_GPIO_MODE_LNA_A(_x)   ((_x) << RT3883_GPIO_MODE_LNA_A_SHIFT)
++#define RT3883_GPIO_MODE_LNA_A_GPIO   0x3
++#define RT3883_GPIO_MODE_LNA_A                _RT3883_GPIO_MODE_LNA_A(RT3883_GPIO_MODE_LNA_A_MASK)
++#define RT3883_GPIO_MODE_LNA_G_SHIFT  18
++#define RT3883_GPIO_MODE_LNA_G_MASK   0x3
++#define _RT3883_GPIO_MODE_LNA_G(_x)   ((_x) << RT3883_GPIO_MODE_LNA_G_SHIFT)
++#define RT3883_GPIO_MODE_LNA_G_GPIO   0x3
++#define RT3883_GPIO_MODE_LNA_G                _RT3883_GPIO_MODE_LNA_G(RT3883_GPIO_MODE_LNA_G_MASK)
++
++#define RT3883_GPIO_I2C_SD            1
++#define RT3883_GPIO_I2C_SCLK          2
++#define RT3883_GPIO_SPI_CS0           3
++#define RT3883_GPIO_SPI_CLK           4
++#define RT3883_GPIO_SPI_MOSI          5
++#define RT3883_GPIO_SPI_MISO          6
++#define RT3883_GPIO_7                 7
++#define RT3883_GPIO_10                        10
++#define RT3883_GPIO_14                        14
++#define RT3883_GPIO_UART1_TXD         15
++#define RT3883_GPIO_UART1_RXD         16
++#define RT3883_GPIO_JTAG_TDO          17
++#define RT3883_GPIO_JTAG_TDI          18
++#define RT3883_GPIO_JTAG_TMS          19
++#define RT3883_GPIO_JTAG_TCLK         20
++#define RT3883_GPIO_JTAG_TRST_N               21
++#define RT3883_GPIO_MDIO_MDC          22
++#define RT3883_GPIO_MDIO_MDIO         23
++#define RT3883_GPIO_LNA_PE_A0         32
++#define RT3883_GPIO_LNA_PE_A1         33
++#define RT3883_GPIO_LNA_PE_A2         34
++#define RT3883_GPIO_LNA_PE_G0         35
++#define RT3883_GPIO_LNA_PE_G1         36
++#define RT3883_GPIO_LNA_PE_G2         37
++#define RT3883_GPIO_PCI_AD0           40
++#define RT3883_GPIO_PCI_AD31          71
++#define RT3883_GPIO_GE2_TXD0          72
++#define RT3883_GPIO_GE2_TXD1          73
++#define RT3883_GPIO_GE2_TXD2          74
++#define RT3883_GPIO_GE2_TXD3          75
++#define RT3883_GPIO_GE2_TXEN          76
++#define RT3883_GPIO_GE2_TXCLK         77
++#define RT3883_GPIO_GE2_RXD0          78
++#define RT3883_GPIO_GE2_RXD1          79
++#define RT3883_GPIO_GE2_RXD2          80
++#define RT3883_GPIO_GE2_RXD3          81
++#define RT3883_GPIO_GE2_RXDV          82
++#define RT3883_GPIO_GE2_RXCLK         83
++#define RT3883_GPIO_GE1_TXD0          84
++#define RT3883_GPIO_GE1_TXD1          85
++#define RT3883_GPIO_GE1_TXD2          86
++#define RT3883_GPIO_GE1_TXD3          87
++#define RT3883_GPIO_GE1_TXEN          88
++#define RT3883_GPIO_GE1_TXCLK         89
++#define RT3883_GPIO_GE1_RXD0          90
++#define RT3883_GPIO_GE1_RXD1          91
++#define RT3883_GPIO_GE1_RXD2          92
++#define RT3883_GPIO_GE1_RXD3          93
++#define RT3883_GPIO_GE1_RXDV          94
++#define RT3883_GPIO_GE1_RXCLK 95
++
++#define RT3883_RSTCTRL_PCIE_PCI_PDM   BIT(27)
++#define RT3883_RSTCTRL_FLASH          BIT(26)
++#define RT3883_RSTCTRL_UDEV           BIT(25)
++#define RT3883_RSTCTRL_PCI            BIT(24)
++#define RT3883_RSTCTRL_PCIE           BIT(23)
++#define RT3883_RSTCTRL_UHST           BIT(22)
++#define RT3883_RSTCTRL_FE             BIT(21)
++#define RT3883_RSTCTRL_WLAN           BIT(20)
++#define RT3883_RSTCTRL_UART1          BIT(29)
++#define RT3883_RSTCTRL_SPI            BIT(18)
++#define RT3883_RSTCTRL_I2S            BIT(17)
++#define RT3883_RSTCTRL_I2C            BIT(16)
++#define RT3883_RSTCTRL_NAND           BIT(15)
++#define RT3883_RSTCTRL_DMA            BIT(14)
++#define RT3883_RSTCTRL_PIO            BIT(13)
++#define RT3883_RSTCTRL_UART           BIT(12)
++#define RT3883_RSTCTRL_PCM            BIT(11)
++#define RT3883_RSTCTRL_MC             BIT(10)
++#define RT3883_RSTCTRL_INTC           BIT(9)
++#define RT3883_RSTCTRL_TIMER          BIT(8)
++#define RT3883_RSTCTRL_SYS            BIT(0)
++
++#define RT3883_INTC_INT_SYSCTL        BIT(0)
++#define RT3883_INTC_INT_TIMER0        BIT(1)
++#define RT3883_INTC_INT_TIMER1        BIT(2)
++#define RT3883_INTC_INT_IA    BIT(3)
++#define RT3883_INTC_INT_PCM   BIT(4)
++#define RT3883_INTC_INT_UART0 BIT(5)
++#define RT3883_INTC_INT_PIO   BIT(6)
++#define RT3883_INTC_INT_DMA   BIT(7)
++#define RT3883_INTC_INT_NAND  BIT(8)
++#define RT3883_INTC_INT_PERFC BIT(9)
++#define RT3883_INTC_INT_I2S   BIT(10)
++#define RT3883_INTC_INT_UART1 BIT(12)
++#define RT3883_INTC_INT_UHST  BIT(18)
++#define RT3883_INTC_INT_UDEV  BIT(19)
++
++/* FLASH/SRAM/Codec Controller registers */
++#define RT3883_FSCC_REG_FLASH_CFG0    0x00
++#define RT3883_FSCC_REG_FLASH_CFG1    0x04
++#define RT3883_FSCC_REG_CODEC_CFG0    0x40
++#define RT3883_FSCC_REG_CODEC_CFG1    0x44
++
++#define RT3883_FLASH_CFG_WIDTH_SHIFT  26
++#define RT3883_FLASH_CFG_WIDTH_MASK   0x3
++#define RT3883_FLASH_CFG_WIDTH_8BIT   0x0
++#define RT3883_FLASH_CFG_WIDTH_16BIT  0x1
++#define RT3883_FLASH_CFG_WIDTH_32BIT  0x2
++
++#endif /* _RT3883_REGS_H_ */
+diff --git a/arch/mips/ralink/Kconfig b/arch/mips/ralink/Kconfig
+index 6723b94..ce57d3e 100644
+--- a/arch/mips/ralink/Kconfig
++++ b/arch/mips/ralink/Kconfig
+@@ -15,6 +15,11 @@ choice
+               select USB_ARCH_HAS_OHCI
+               select USB_ARCH_HAS_EHCI
++      config SOC_RT3883
++              bool "RT3883"
++              select USB_ARCH_HAS_OHCI
++              select USB_ARCH_HAS_EHCI
++
+ endchoice
+ choice
+diff --git a/arch/mips/ralink/Makefile b/arch/mips/ralink/Makefile
+index 6d826f2..ba9669c 100644
+--- a/arch/mips/ralink/Makefile
++++ b/arch/mips/ralink/Makefile
+@@ -10,6 +10,7 @@ obj-y := prom.o of.o reset.o clk.o irq.o
+ obj-$(CONFIG_SOC_RT288X) += rt288x.o
+ obj-$(CONFIG_SOC_RT305X) += rt305x.o
++obj-$(CONFIG_SOC_RT3883) += rt3883.o
+ obj-$(CONFIG_EARLY_PRINTK) += early_printk.o
+diff --git a/arch/mips/ralink/Platform b/arch/mips/ralink/Platform
+index 3f49e51..f67c08d 100644
+--- a/arch/mips/ralink/Platform
++++ b/arch/mips/ralink/Platform
+@@ -13,3 +13,8 @@ load-$(CONFIG_SOC_RT288X)    += 0xffffffff88000000
+ # Ralink RT305x
+ #
+ load-$(CONFIG_SOC_RT305X)     += 0xffffffff80000000
++
++#
++# Ralink RT3883
++#
++load-$(CONFIG_SOC_RT3883)     += 0xffffffff80000000
+diff --git a/arch/mips/ralink/rt3883.c b/arch/mips/ralink/rt3883.c
+new file mode 100644
+index 0000000..2d90aa9
+--- /dev/null
++++ b/arch/mips/ralink/rt3883.c
+@@ -0,0 +1,242 @@
++/*
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of the GNU General Public License version 2 as published
++ * by the Free Software Foundation.
++ *
++ * Parts of this file are based on Ralink's 2.6.21 BSP
++ *
++ * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
++ * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
++ * Copyright (C) 2013 John Crispin <blogic@openwrt.org>
++ */
++
++#include <linux/kernel.h>
++#include <linux/init.h>
++#include <linux/module.h>
++
++#include <asm/mipsregs.h>
++#include <asm/mach-ralink/ralink_regs.h>
++#include <asm/mach-ralink/rt3883.h>
++
++#include "common.h"
++
++static struct ralink_pinmux_grp mode_mux[] = {
++      {
++              .name = "i2c",
++              .mask = RT3883_GPIO_MODE_I2C,
++              .gpio_first = RT3883_GPIO_I2C_SD,
++              .gpio_last = RT3883_GPIO_I2C_SCLK,
++      }, {
++              .name = "spi",
++              .mask = RT3883_GPIO_MODE_SPI,
++              .gpio_first = RT3883_GPIO_SPI_CS0,
++              .gpio_last = RT3883_GPIO_SPI_MISO,
++      }, {
++              .name = "uartlite",
++              .mask = RT3883_GPIO_MODE_UART1,
++              .gpio_first = RT3883_GPIO_UART1_TXD,
++              .gpio_last = RT3883_GPIO_UART1_RXD,
++      }, {
++              .name = "jtag",
++              .mask = RT3883_GPIO_MODE_JTAG,
++              .gpio_first = RT3883_GPIO_JTAG_TDO,
++              .gpio_last = RT3883_GPIO_JTAG_TCLK,
++      }, {
++              .name = "mdio",
++              .mask = RT3883_GPIO_MODE_MDIO,
++              .gpio_first = RT3883_GPIO_MDIO_MDC,
++              .gpio_last = RT3883_GPIO_MDIO_MDIO,
++      }, {
++              .name = "ge1",
++              .mask = RT3883_GPIO_MODE_GE1,
++              .gpio_first = RT3883_GPIO_GE1_TXD0,
++              .gpio_last = RT3883_GPIO_GE1_RXCLK,
++      }, {
++              .name = "ge2",
++              .mask = RT3883_GPIO_MODE_GE2,
++              .gpio_first = RT3883_GPIO_GE2_TXD0,
++              .gpio_last = RT3883_GPIO_GE2_RXCLK,
++      }, {
++              .name = "pci",
++              .mask = RT3883_GPIO_MODE_PCI,
++              .gpio_first = RT3883_GPIO_PCI_AD0,
++              .gpio_last = RT3883_GPIO_PCI_AD31,
++      }, {
++              .name = "lna a",
++              .mask = RT3883_GPIO_MODE_LNA_A,
++              .gpio_first = RT3883_GPIO_LNA_PE_A0,
++              .gpio_last = RT3883_GPIO_LNA_PE_A2,
++      }, {
++              .name = "lna g",
++              .mask = RT3883_GPIO_MODE_LNA_G,
++              .gpio_first = RT3883_GPIO_LNA_PE_G0,
++              .gpio_last = RT3883_GPIO_LNA_PE_G2,
++      }, {0}
++};
++
++static struct ralink_pinmux_grp uart_mux[] = {
++      {
++              .name = "uartf",
++              .mask = RT3883_GPIO_MODE_UARTF,
++              .gpio_first = RT3883_GPIO_7,
++              .gpio_last = RT3883_GPIO_14,
++      }, {
++              .name = "pcm uartf",
++              .mask = RT3883_GPIO_MODE_PCM_UARTF,
++              .gpio_first = RT3883_GPIO_7,
++              .gpio_last = RT3883_GPIO_14,
++      }, {
++              .name = "pcm i2s",
++              .mask = RT3883_GPIO_MODE_PCM_I2S,
++              .gpio_first = RT3883_GPIO_7,
++              .gpio_last = RT3883_GPIO_14,
++      }, {
++              .name = "i2s uartf",
++              .mask = RT3883_GPIO_MODE_I2S_UARTF,
++              .gpio_first = RT3883_GPIO_7,
++              .gpio_last = RT3883_GPIO_14,
++      }, {
++              .name = "pcm gpio",
++              .mask = RT3883_GPIO_MODE_PCM_GPIO,
++              .gpio_first = RT3883_GPIO_11,
++              .gpio_last = RT3883_GPIO_14,
++      }, {
++              .name = "gpio uartf",
++              .mask = RT3883_GPIO_MODE_GPIO_UARTF,
++              .gpio_first = RT3883_GPIO_7,
++              .gpio_last = RT3883_GPIO_10,
++      }, {
++              .name = "gpio i2s",
++              .mask = RT3883_GPIO_MODE_GPIO_I2S,
++              .gpio_first = RT3883_GPIO_7,
++              .gpio_last = RT3883_GPIO_10,
++      }, {
++              .name = "gpio",
++              .mask = RT3883_GPIO_MODE_GPIO,
++      }, {0}
++};
++
++static struct ralink_pinmux_grp pci_mux[] = {
++      {
++              .name = "pci-dev",
++              .mask = 0,
++              .gpio_first = RT3883_GPIO_PCI_AD0,
++              .gpio_last = RT3883_GPIO_PCI_AD31,
++      }, {
++              .name = "pci-host2",
++              .mask = 1,
++              .gpio_first = RT3883_GPIO_PCI_AD0,
++              .gpio_last = RT3883_GPIO_PCI_AD31,
++      }, {
++              .name = "pci-host1",
++              .mask = 2,
++              .gpio_first = RT3883_GPIO_PCI_AD0,
++              .gpio_last = RT3883_GPIO_PCI_AD31,
++      }, {
++              .name = "pci-fnc",
++              .mask = 3,
++              .gpio_first = RT3883_GPIO_PCI_AD0,
++              .gpio_last = RT3883_GPIO_PCI_AD31,
++      }, {
++              .name = "pci-gpio",
++              .mask = 7,
++              .gpio_first = RT3883_GPIO_PCI_AD0,
++              .gpio_last = RT3883_GPIO_PCI_AD31,
++      }, {0}
++};
++
++static void rt3883_wdt_reset(void)
++{
++      u32 t;
++
++      /* enable WDT reset output on GPIO 2 */
++      t = rt_sysc_r32(RT3883_SYSC_REG_SYSCFG1);
++      t |= RT3883_SYSCFG1_GPIO2_AS_WDT_OUT;
++      rt_sysc_w32(t, RT3883_SYSC_REG_SYSCFG1);
++}
++
++struct ralink_pinmux rt_gpio_pinmux = {
++      .mode = mode_mux,
++      .uart = uart_mux,
++      .uart_shift = RT3883_GPIO_MODE_UART0_SHIFT,
++      .uart_mask = RT3883_GPIO_MODE_GPIO,
++      .wdt_reset = rt3883_wdt_reset,
++      .pci = pci_mux,
++      .pci_shift = RT3883_GPIO_MODE_PCI_SHIFT,
++      .pci_mask = RT3883_GPIO_MODE_PCI_MASK,
++};
++
++void __init ralink_clk_init(void)
++{
++      unsigned long cpu_rate, sys_rate;
++      u32 syscfg0;
++      u32 clksel;
++      u32 ddr2;
++
++      syscfg0 = rt_sysc_r32(RT3883_SYSC_REG_SYSCFG0);
++      clksel = ((syscfg0 >> RT3883_SYSCFG0_CPUCLK_SHIFT) &
++              RT3883_SYSCFG0_CPUCLK_MASK);
++      ddr2 = syscfg0 & RT3883_SYSCFG0_DRAM_TYPE_DDR2;
++
++      switch (clksel) {
++      case RT3883_SYSCFG0_CPUCLK_250:
++              cpu_rate = 250000000;
++              sys_rate = (ddr2) ? 125000000 : 83000000;
++              break;
++      case RT3883_SYSCFG0_CPUCLK_384:
++              cpu_rate = 384000000;
++              sys_rate = (ddr2) ? 128000000 : 96000000;
++              break;
++      case RT3883_SYSCFG0_CPUCLK_480:
++              cpu_rate = 480000000;
++              sys_rate = (ddr2) ? 160000000 : 120000000;
++              break;
++      case RT3883_SYSCFG0_CPUCLK_500:
++              cpu_rate = 500000000;
++              sys_rate = (ddr2) ? 166000000 : 125000000;
++              break;
++      }
++
++      ralink_clk_add("cpu", cpu_rate);
++      ralink_clk_add("10000100.timer", sys_rate);
++      ralink_clk_add("10000120.watchdog", sys_rate);
++      ralink_clk_add("10000500.uart", 40000000);
++      ralink_clk_add("10000b00.spi", sys_rate);
++      ralink_clk_add("10000c00.uartlite", 40000000);
++      ralink_clk_add("10100000.ethernet", sys_rate);
++}
++
++void __init ralink_of_remap(void)
++{
++      rt_sysc_membase = plat_of_remap_node("ralink,rt3883-sysc");
++      rt_memc_membase = plat_of_remap_node("ralink,rt3883-memc");
++
++      if (!rt_sysc_membase || !rt_memc_membase)
++              panic("Failed to remap core resources");
++}
++
++void prom_soc_init(struct ralink_soc_info *soc_info)
++{
++      void __iomem *sysc = (void __iomem *) KSEG1ADDR(RT3883_SYSC_BASE);
++      const char *name;
++      u32 n0;
++      u32 n1;
++      u32 id;
++
++      n0 = __raw_readl(sysc + RT3883_SYSC_REG_CHIPID0_3);
++      n1 = __raw_readl(sysc + RT3883_SYSC_REG_CHIPID4_7);
++      id = __raw_readl(sysc + RT3883_SYSC_REG_REVID);
++
++      if (n0 == RT3883_CHIP_NAME0 && n1 == RT3883_CHIP_NAME1) {
++              soc_info->compatible = "ralink,rt3883-soc";
++              name = "RT3883";
++      } else {
++              panic("rt3883: unknown SoC, n0:%08x n1:%08x", n0, n1);
++      }
++
++      snprintf(soc_info->sys_type, RAMIPS_SYS_TYPE_LEN,
++              "Ralink %s ver:%u eco:%u",
++              name,
++              (id >> RT3883_REVID_VER_ID_SHIFT) & RT3883_REVID_VER_ID_MASK,
++              (id & RT3883_REVID_ECO_ID_MASK));
++}
+-- 
+1.7.10.4
+
diff --git a/target/linux/ramips/patches-3.8/0029-MIPS-ralink-adds-support-for-MT7620-SoC-family.patch b/target/linux/ramips/patches-3.8/0029-MIPS-ralink-adds-support-for-MT7620-SoC-family.patch
new file mode 100644 (file)
index 0000000..f03c10f
--- /dev/null
@@ -0,0 +1,366 @@
+From 41b7b06b494eef5a081363566314960306437d73 Mon Sep 17 00:00:00 2001
+From: John Crispin <blogic@openwrt.org>
+Date: Thu, 21 Mar 2013 17:49:02 +0100
+Subject: [PATCH 29/79] MIPS: ralink: adds support for MT7620 SoC family
+
+Add support code for mt7620 SOC.
+
+The code detects the SoC and registers the clk / pinmux settings.
+
+Signed-off-by: John Crispin <blogic@openwrt.org>
+Acked-by: Gabor Juhos <juhosg@openwrt.org>
+Patchwork: http://patchwork.linux-mips.org/patch/5177/
+---
+ arch/mips/include/asm/mach-ralink/mt7620.h |   76 ++++++++++
+ arch/mips/ralink/Kconfig                   |    3 +
+ arch/mips/ralink/Makefile                  |    1 +
+ arch/mips/ralink/Platform                  |    5 +
+ arch/mips/ralink/mt7620.c                  |  214 ++++++++++++++++++++++++++++
+ 5 files changed, 299 insertions(+)
+ create mode 100644 arch/mips/include/asm/mach-ralink/mt7620.h
+ create mode 100644 arch/mips/ralink/mt7620.c
+
+diff --git a/arch/mips/include/asm/mach-ralink/mt7620.h b/arch/mips/include/asm/mach-ralink/mt7620.h
+new file mode 100644
+index 0000000..b272649
+--- /dev/null
++++ b/arch/mips/include/asm/mach-ralink/mt7620.h
+@@ -0,0 +1,76 @@
++/*
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of the GNU General Public License version 2 as published
++ * by the Free Software Foundation.
++ *
++ * Parts of this file are based on Ralink's 2.6.21 BSP
++ *
++ * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
++ * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
++ * Copyright (C) 2013 John Crispin <blogic@openwrt.org>
++ */
++
++#ifndef _MT7620_REGS_H_
++#define _MT7620_REGS_H_
++
++#define MT7620_SYSC_BASE              0x10000000
++
++#define SYSC_REG_CHIP_NAME0           0x00
++#define SYSC_REG_CHIP_NAME1           0x04
++#define SYSC_REG_CHIP_REV             0x0c
++#define SYSC_REG_SYSTEM_CONFIG0               0x10
++#define SYSC_REG_SYSTEM_CONFIG1               0x14
++#define SYSC_REG_CPLL_CONFIG0         0x54
++#define SYSC_REG_CPLL_CONFIG1         0x58
++
++#define MT7620N_CHIP_NAME0            0x33365452
++#define MT7620N_CHIP_NAME1            0x20203235
++
++#define MT7620A_CHIP_NAME0            0x3637544d
++#define MT7620A_CHIP_NAME1            0x20203032
++
++#define CHIP_REV_PKG_MASK             0x1
++#define CHIP_REV_PKG_SHIFT            16
++#define CHIP_REV_VER_MASK             0xf
++#define CHIP_REV_VER_SHIFT            8
++#define CHIP_REV_ECO_MASK             0xf
++
++#define CPLL_SW_CONFIG_SHIFT          31
++#define CPLL_SW_CONFIG_MASK           0x1
++#define CPLL_CPU_CLK_SHIFT            24
++#define CPLL_CPU_CLK_MASK             0x1
++#define CPLL_MULT_RATIO_SHIFT           16
++#define CPLL_MULT_RATIO                 0x7
++#define CPLL_DIV_RATIO_SHIFT            10
++#define CPLL_DIV_RATIO                  0x3
++
++#define SYSCFG0_DRAM_TYPE_MASK                0x3
++#define SYSCFG0_DRAM_TYPE_SHIFT               4
++#define SYSCFG0_DRAM_TYPE_SDRAM               0
++#define SYSCFG0_DRAM_TYPE_DDR1                1
++#define SYSCFG0_DRAM_TYPE_DDR2                2
++
++#define MT7620_GPIO_MODE_I2C          BIT(0)
++#define MT7620_GPIO_MODE_UART0_SHIFT  2
++#define MT7620_GPIO_MODE_UART0_MASK   0x7
++#define MT7620_GPIO_MODE_UART0(x)     ((x) << MT7620_GPIO_MODE_UART0_SHIFT)
++#define MT7620_GPIO_MODE_UARTF                0x0
++#define MT7620_GPIO_MODE_PCM_UARTF    0x1
++#define MT7620_GPIO_MODE_PCM_I2S      0x2
++#define MT7620_GPIO_MODE_I2S_UARTF    0x3
++#define MT7620_GPIO_MODE_PCM_GPIO     0x4
++#define MT7620_GPIO_MODE_GPIO_UARTF   0x5
++#define MT7620_GPIO_MODE_GPIO_I2S     0x6
++#define MT7620_GPIO_MODE_GPIO         0x7
++#define MT7620_GPIO_MODE_UART1                BIT(5)
++#define MT7620_GPIO_MODE_MDIO         BIT(8)
++#define MT7620_GPIO_MODE_RGMII1               BIT(9)
++#define MT7620_GPIO_MODE_RGMII2               BIT(10)
++#define MT7620_GPIO_MODE_SPI          BIT(11)
++#define MT7620_GPIO_MODE_SPI_REF_CLK  BIT(12)
++#define MT7620_GPIO_MODE_WLED         BIT(13)
++#define MT7620_GPIO_MODE_JTAG         BIT(15)
++#define MT7620_GPIO_MODE_EPHY         BIT(15)
++#define MT7620_GPIO_MODE_WDT          BIT(22)
++
++#endif
+diff --git a/arch/mips/ralink/Kconfig b/arch/mips/ralink/Kconfig
+index ce57d3e..86f6c77 100644
+--- a/arch/mips/ralink/Kconfig
++++ b/arch/mips/ralink/Kconfig
+@@ -20,6 +20,9 @@ choice
+               select USB_ARCH_HAS_OHCI
+               select USB_ARCH_HAS_EHCI
++      config SOC_MT7620
++              bool "MT7620"
++
+ endchoice
+ choice
+diff --git a/arch/mips/ralink/Makefile b/arch/mips/ralink/Makefile
+index ba9669c..38cf1a8 100644
+--- a/arch/mips/ralink/Makefile
++++ b/arch/mips/ralink/Makefile
+@@ -11,6 +11,7 @@ obj-y := prom.o of.o reset.o clk.o irq.o
+ obj-$(CONFIG_SOC_RT288X) += rt288x.o
+ obj-$(CONFIG_SOC_RT305X) += rt305x.o
+ obj-$(CONFIG_SOC_RT3883) += rt3883.o
++obj-$(CONFIG_SOC_MT7620) += mt7620.o
+ obj-$(CONFIG_EARLY_PRINTK) += early_printk.o
+diff --git a/arch/mips/ralink/Platform b/arch/mips/ralink/Platform
+index f67c08d..b2cbf16 100644
+--- a/arch/mips/ralink/Platform
++++ b/arch/mips/ralink/Platform
+@@ -18,3 +18,8 @@ load-$(CONFIG_SOC_RT305X)    += 0xffffffff80000000
+ # Ralink RT3883
+ #
+ load-$(CONFIG_SOC_RT3883)     += 0xffffffff80000000
++
++#
++# Ralink MT7620
++#
++load-$(CONFIG_SOC_MT7620)     += 0xffffffff80000000
+diff --git a/arch/mips/ralink/mt7620.c b/arch/mips/ralink/mt7620.c
+new file mode 100644
+index 0000000..eb00ab8
+--- /dev/null
++++ b/arch/mips/ralink/mt7620.c
+@@ -0,0 +1,214 @@
++/*
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of the GNU General Public License version 2 as published
++ * by the Free Software Foundation.
++ *
++ * Parts of this file are based on Ralink's 2.6.21 BSP
++ *
++ * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
++ * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
++ * Copyright (C) 2013 John Crispin <blogic@openwrt.org>
++ */
++
++#include <linux/kernel.h>
++#include <linux/init.h>
++#include <linux/module.h>
++
++#include <asm/mipsregs.h>
++#include <asm/mach-ralink/ralink_regs.h>
++#include <asm/mach-ralink/mt7620.h>
++
++#include "common.h"
++
++/* does the board have sdram or ddram */
++static int dram_type;
++
++/* the pll dividers */
++static u32 mt7620_clk_divider[] = { 2, 3, 4, 8 };
++
++static struct ralink_pinmux_grp mode_mux[] = {
++      {
++              .name = "i2c",
++              .mask = MT7620_GPIO_MODE_I2C,
++              .gpio_first = 1,
++              .gpio_last = 2,
++      }, {
++              .name = "spi",
++              .mask = MT7620_GPIO_MODE_SPI,
++              .gpio_first = 3,
++              .gpio_last = 6,
++      }, {
++              .name = "uartlite",
++              .mask = MT7620_GPIO_MODE_UART1,
++              .gpio_first = 15,
++              .gpio_last = 16,
++      }, {
++              .name = "wdt",
++              .mask = MT7620_GPIO_MODE_WDT,
++              .gpio_first = 17,
++              .gpio_last = 17,
++      }, {
++              .name = "mdio",
++              .mask = MT7620_GPIO_MODE_MDIO,
++              .gpio_first = 22,
++              .gpio_last = 23,
++      }, {
++              .name = "rgmii1",
++              .mask = MT7620_GPIO_MODE_RGMII1,
++              .gpio_first = 24,
++              .gpio_last = 35,
++      }, {
++              .name = "spi refclk",
++              .mask = MT7620_GPIO_MODE_SPI_REF_CLK,
++              .gpio_first = 37,
++              .gpio_last = 39,
++      }, {
++              .name = "jtag",
++              .mask = MT7620_GPIO_MODE_JTAG,
++              .gpio_first = 40,
++              .gpio_last = 44,
++      }, {
++              /* shared lines with jtag */
++              .name = "ephy",
++              .mask = MT7620_GPIO_MODE_EPHY,
++              .gpio_first = 40,
++              .gpio_last = 44,
++      }, {
++              .name = "nand",
++              .mask = MT7620_GPIO_MODE_JTAG,
++              .gpio_first = 45,
++              .gpio_last = 59,
++      }, {
++              .name = "rgmii2",
++              .mask = MT7620_GPIO_MODE_RGMII2,
++              .gpio_first = 60,
++              .gpio_last = 71,
++      }, {
++              .name = "wled",
++              .mask = MT7620_GPIO_MODE_WLED,
++              .gpio_first = 72,
++              .gpio_last = 72,
++      }, {0}
++};
++
++static struct ralink_pinmux_grp uart_mux[] = {
++      {
++              .name = "uartf",
++              .mask = MT7620_GPIO_MODE_UARTF,
++              .gpio_first = 7,
++              .gpio_last = 14,
++      }, {
++              .name = "pcm uartf",
++              .mask = MT7620_GPIO_MODE_PCM_UARTF,
++              .gpio_first = 7,
++              .gpio_last = 14,
++      }, {
++              .name = "pcm i2s",
++              .mask = MT7620_GPIO_MODE_PCM_I2S,
++              .gpio_first = 7,
++              .gpio_last = 14,
++      }, {
++              .name = "i2s uartf",
++              .mask = MT7620_GPIO_MODE_I2S_UARTF,
++              .gpio_first = 7,
++              .gpio_last = 14,
++      }, {
++              .name = "pcm gpio",
++              .mask = MT7620_GPIO_MODE_PCM_GPIO,
++              .gpio_first = 11,
++              .gpio_last = 14,
++      }, {
++              .name = "gpio uartf",
++              .mask = MT7620_GPIO_MODE_GPIO_UARTF,
++              .gpio_first = 7,
++              .gpio_last = 10,
++      }, {
++              .name = "gpio i2s",
++              .mask = MT7620_GPIO_MODE_GPIO_I2S,
++              .gpio_first = 7,
++              .gpio_last = 10,
++      }, {
++              .name = "gpio",
++              .mask = MT7620_GPIO_MODE_GPIO,
++      }, {0}
++};
++
++struct ralink_pinmux rt_gpio_pinmux = {
++      .mode = mode_mux,
++      .uart = uart_mux,
++      .uart_shift = MT7620_GPIO_MODE_UART0_SHIFT,
++      .uart_mask = MT7620_GPIO_MODE_GPIO,
++};
++
++void __init ralink_clk_init(void)
++{
++      unsigned long cpu_rate, sys_rate;
++      u32 c0 = rt_sysc_r32(SYSC_REG_CPLL_CONFIG0);
++      u32 c1 = rt_sysc_r32(SYSC_REG_CPLL_CONFIG1);
++      u32 swconfig = (c0 >> CPLL_SW_CONFIG_SHIFT) & CPLL_SW_CONFIG_MASK;
++      u32 cpu_clk = (c1 >> CPLL_CPU_CLK_SHIFT) & CPLL_CPU_CLK_MASK;
++
++      if (cpu_clk) {
++              cpu_rate = 480000000;
++      } else if (!swconfig) {
++              cpu_rate = 600000000;
++      } else {
++              u32 m = (c0 >> CPLL_MULT_RATIO_SHIFT) & CPLL_MULT_RATIO;
++              u32 d = (c0 >> CPLL_DIV_RATIO_SHIFT) & CPLL_DIV_RATIO;
++
++              cpu_rate = ((40 * (m + 24)) / mt7620_clk_divider[d]) * 1000000;
++      }
++
++      if (dram_type == SYSCFG0_DRAM_TYPE_SDRAM)
++              sys_rate = cpu_rate / 4;
++      else
++              sys_rate = cpu_rate / 3;
++
++      ralink_clk_add("cpu", cpu_rate);
++      ralink_clk_add("10000100.timer", 40000000);
++      ralink_clk_add("10000500.uart", 40000000);
++      ralink_clk_add("10000c00.uartlite", 40000000);
++}
++
++void __init ralink_of_remap(void)
++{
++      rt_sysc_membase = plat_of_remap_node("ralink,mt7620a-sysc");
++      rt_memc_membase = plat_of_remap_node("ralink,mt7620a-memc");
++
++      if (!rt_sysc_membase || !rt_memc_membase)
++              panic("Failed to remap core resources");
++}
++
++void prom_soc_init(struct ralink_soc_info *soc_info)
++{
++      void __iomem *sysc = (void __iomem *) KSEG1ADDR(MT7620_SYSC_BASE);
++      unsigned char *name = NULL;
++      u32 n0;
++      u32 n1;
++      u32 rev;
++      u32 cfg0;
++
++      n0 = __raw_readl(sysc + SYSC_REG_CHIP_NAME0);
++      n1 = __raw_readl(sysc + SYSC_REG_CHIP_NAME1);
++
++      if (n0 == MT7620N_CHIP_NAME0 && n1 == MT7620N_CHIP_NAME1) {
++              name = "MT7620N";
++              soc_info->compatible = "ralink,mt7620n-soc";
++      } else if (n0 == MT7620A_CHIP_NAME0 && n1 == MT7620A_CHIP_NAME1) {
++              name = "MT7620A";
++              soc_info->compatible = "ralink,mt7620a-soc";
++      } else {
++              panic("mt7620: unknown SoC, n0:%08x n1:%08x\n", n0, n1);
++      }
++
++      rev = __raw_readl(sysc + SYSC_REG_CHIP_REV);
++
++      snprintf(soc_info->sys_type, RAMIPS_SYS_TYPE_LEN,
++              "Ralink %s ver:%u eco:%u",
++              name,
++              (rev >> CHIP_REV_VER_SHIFT) & CHIP_REV_VER_MASK,
++              (rev & CHIP_REV_ECO_MASK));
++
++      cfg0 = __raw_readl(sysc + SYSC_REG_SYSTEM_CONFIG0);
++      dram_type = (cfg0 >> SYSCFG0_DRAM_TYPE_SHIFT) & SYSCFG0_DRAM_TYPE_MASK;
++}
+-- 
+1.7.10.4
+
diff --git a/target/linux/ramips/patches-3.8/0030-MIPS-ralink-add-cpu-feature-overrides.h.patch b/target/linux/ramips/patches-3.8/0030-MIPS-ralink-add-cpu-feature-overrides.h.patch
new file mode 100644 (file)
index 0000000..21205a3
--- /dev/null
@@ -0,0 +1,232 @@
+From 8a7cac5e324f044f3970d686d79e3489260f6d21 Mon Sep 17 00:00:00 2001
+From: Gabor Juhos <juhosg@openwrt.org>
+Date: Wed, 10 Apr 2013 09:19:07 +0200
+Subject: [PATCH 30/79] MIPS: ralink: add cpu-feature-overrides.h
+
+Add cpu-feature-overrides.h for RT288x, RT305x and RT3883.
+
+Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
+Signed-off-by: John Crispin <blogic@openwrt.org>
+Patchwork: http://patchwork.linux-mips.org/patch/5175/
+---
+ .../asm/mach-ralink/rt288x/cpu-feature-overrides.h |   56 ++++++++++++++++++++
+ .../asm/mach-ralink/rt305x/cpu-feature-overrides.h |   56 ++++++++++++++++++++
+ .../asm/mach-ralink/rt3883/cpu-feature-overrides.h |   55 +++++++++++++++++++
+ arch/mips/ralink/Platform                          |    3 ++
+ 4 files changed, 170 insertions(+)
+ create mode 100644 arch/mips/include/asm/mach-ralink/rt288x/cpu-feature-overrides.h
+ create mode 100644 arch/mips/include/asm/mach-ralink/rt305x/cpu-feature-overrides.h
+ create mode 100644 arch/mips/include/asm/mach-ralink/rt3883/cpu-feature-overrides.h
+
+diff --git a/arch/mips/include/asm/mach-ralink/rt288x/cpu-feature-overrides.h b/arch/mips/include/asm/mach-ralink/rt288x/cpu-feature-overrides.h
+new file mode 100644
+index 0000000..72fc106
+--- /dev/null
++++ b/arch/mips/include/asm/mach-ralink/rt288x/cpu-feature-overrides.h
+@@ -0,0 +1,56 @@
++/*
++ * Ralink RT288x specific CPU feature overrides
++ *
++ * Copyright (C) 2008-2009 Gabor Juhos <juhosg@openwrt.org>
++ * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
++ *
++ * This file was derived from: include/asm-mips/cpu-features.h
++ *    Copyright (C) 2003, 2004 Ralf Baechle
++ *    Copyright (C) 2004 Maciej W. Rozycki
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of the GNU General Public License version 2 as published
++ * by the Free Software Foundation.
++ *
++ */
++#ifndef _RT288X_CPU_FEATURE_OVERRIDES_H
++#define _RT288X_CPU_FEATURE_OVERRIDES_H
++
++#define cpu_has_tlb           1
++#define cpu_has_4kex          1
++#define cpu_has_3k_cache      0
++#define cpu_has_4k_cache      1
++#define cpu_has_tx39_cache    0
++#define cpu_has_sb1_cache     0
++#define cpu_has_fpu           0
++#define cpu_has_32fpr         0
++#define cpu_has_counter               1
++#define cpu_has_watch         1
++#define cpu_has_divec         1
++
++#define cpu_has_prefetch      1
++#define cpu_has_ejtag         1
++#define cpu_has_llsc          1
++
++#define cpu_has_mips16                1
++#define cpu_has_mdmx          0
++#define cpu_has_mips3d                0
++#define cpu_has_smartmips     0
++
++#define cpu_has_mips32r1      1
++#define cpu_has_mips32r2      1
++#define cpu_has_mips64r1      0
++#define cpu_has_mips64r2      0
++
++#define cpu_has_dsp           0
++#define cpu_has_mipsmt                0
++
++#define cpu_has_64bits                0
++#define cpu_has_64bit_zero_reg        0
++#define cpu_has_64bit_gp_regs 0
++#define cpu_has_64bit_addresses       0
++
++#define cpu_dcache_line_size()        16
++#define cpu_icache_line_size()        16
++
++#endif /* _RT288X_CPU_FEATURE_OVERRIDES_H */
+diff --git a/arch/mips/include/asm/mach-ralink/rt305x/cpu-feature-overrides.h b/arch/mips/include/asm/mach-ralink/rt305x/cpu-feature-overrides.h
+new file mode 100644
+index 0000000..917c286
+--- /dev/null
++++ b/arch/mips/include/asm/mach-ralink/rt305x/cpu-feature-overrides.h
+@@ -0,0 +1,56 @@
++/*
++ * Ralink RT305x specific CPU feature overrides
++ *
++ * Copyright (C) 2008-2009 Gabor Juhos <juhosg@openwrt.org>
++ * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
++ *
++ * This file was derived from: include/asm-mips/cpu-features.h
++ *    Copyright (C) 2003, 2004 Ralf Baechle
++ *    Copyright (C) 2004 Maciej W. Rozycki
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of the GNU General Public License version 2 as published
++ * by the Free Software Foundation.
++ *
++ */
++#ifndef _RT305X_CPU_FEATURE_OVERRIDES_H
++#define _RT305X_CPU_FEATURE_OVERRIDES_H
++
++#define cpu_has_tlb           1
++#define cpu_has_4kex          1
++#define cpu_has_3k_cache      0
++#define cpu_has_4k_cache      1
++#define cpu_has_tx39_cache    0
++#define cpu_has_sb1_cache     0
++#define cpu_has_fpu           0
++#define cpu_has_32fpr         0
++#define cpu_has_counter               1
++#define cpu_has_watch         1
++#define cpu_has_divec         1
++
++#define cpu_has_prefetch      1
++#define cpu_has_ejtag         1
++#define cpu_has_llsc          1
++
++#define cpu_has_mips16                1
++#define cpu_has_mdmx          0
++#define cpu_has_mips3d                0
++#define cpu_has_smartmips     0
++
++#define cpu_has_mips32r1      1
++#define cpu_has_mips32r2      1
++#define cpu_has_mips64r1      0
++#define cpu_has_mips64r2      0
++
++#define cpu_has_dsp           1
++#define cpu_has_mipsmt                0
++
++#define cpu_has_64bits                0
++#define cpu_has_64bit_zero_reg        0
++#define cpu_has_64bit_gp_regs 0
++#define cpu_has_64bit_addresses       0
++
++#define cpu_dcache_line_size()        32
++#define cpu_icache_line_size()        32
++
++#endif /* _RT305X_CPU_FEATURE_OVERRIDES_H */
+diff --git a/arch/mips/include/asm/mach-ralink/rt3883/cpu-feature-overrides.h b/arch/mips/include/asm/mach-ralink/rt3883/cpu-feature-overrides.h
+new file mode 100644
+index 0000000..181fbf4
+--- /dev/null
++++ b/arch/mips/include/asm/mach-ralink/rt3883/cpu-feature-overrides.h
+@@ -0,0 +1,55 @@
++/*
++ * Ralink RT3662/RT3883 specific CPU feature overrides
++ *
++ * Copyright (C) 2011-2013 Gabor Juhos <juhosg@openwrt.org>
++ *
++ * This file was derived from: include/asm-mips/cpu-features.h
++ *    Copyright (C) 2003, 2004 Ralf Baechle
++ *    Copyright (C) 2004 Maciej W. Rozycki
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of the GNU General Public License version 2 as published
++ * by the Free Software Foundation.
++ *
++ */
++#ifndef _RT3883_CPU_FEATURE_OVERRIDES_H
++#define _RT3883_CPU_FEATURE_OVERRIDES_H
++
++#define cpu_has_tlb           1
++#define cpu_has_4kex          1
++#define cpu_has_3k_cache      0
++#define cpu_has_4k_cache      1
++#define cpu_has_tx39_cache    0
++#define cpu_has_sb1_cache     0
++#define cpu_has_fpu           0
++#define cpu_has_32fpr         0
++#define cpu_has_counter               1
++#define cpu_has_watch         1
++#define cpu_has_divec         1
++
++#define cpu_has_prefetch      1
++#define cpu_has_ejtag         1
++#define cpu_has_llsc          1
++
++#define cpu_has_mips16                1
++#define cpu_has_mdmx          0
++#define cpu_has_mips3d                0
++#define cpu_has_smartmips     0
++
++#define cpu_has_mips32r1      1
++#define cpu_has_mips32r2      1
++#define cpu_has_mips64r1      0
++#define cpu_has_mips64r2      0
++
++#define cpu_has_dsp           1
++#define cpu_has_mipsmt                0
++
++#define cpu_has_64bits                0
++#define cpu_has_64bit_zero_reg        0
++#define cpu_has_64bit_gp_regs 0
++#define cpu_has_64bit_addresses       0
++
++#define cpu_dcache_line_size()        32
++#define cpu_icache_line_size()        32
++
++#endif /* _RT3883_CPU_FEATURE_OVERRIDES_H */
+diff --git a/arch/mips/ralink/Platform b/arch/mips/ralink/Platform
+index b2cbf16..cda4b66 100644
+--- a/arch/mips/ralink/Platform
++++ b/arch/mips/ralink/Platform
+@@ -8,16 +8,19 @@ cflags-$(CONFIG_RALINK)              += -I$(srctree)/arch/mips/include/asm/mach-ralink
+ # Ralink RT288x
+ #
+ load-$(CONFIG_SOC_RT288X)     += 0xffffffff88000000
++cflags-$(CONFIG_SOC_RT288X)   += -I$(srctree)/arch/mips/include/asm/mach-ralink/rt288x
+ #
+ # Ralink RT305x
+ #
+ load-$(CONFIG_SOC_RT305X)     += 0xffffffff80000000
++cflags-$(CONFIG_SOC_RT305X)   += -I$(srctree)/arch/mips/include/asm/mach-ralink/rt305x
+ #
+ # Ralink RT3883
+ #
+ load-$(CONFIG_SOC_RT3883)     += 0xffffffff80000000
++cflags-$(CONFIG_SOC_RT3883)   += -I$(srctree)/arch/mips/include/asm/mach-ralink/rt3883
+ #
+ # Ralink MT7620
+-- 
+1.7.10.4
+
diff --git a/target/linux/ramips/patches-3.8/0031-DT-add-vendor-prefixes-for-Ralink.patch b/target/linux/ramips/patches-3.8/0031-DT-add-vendor-prefixes-for-Ralink.patch
new file mode 100644 (file)
index 0000000..7a81af6
--- /dev/null
@@ -0,0 +1,26 @@
+From f13cb76f8ad8714eaf691ef24aebfb57f62dab66 Mon Sep 17 00:00:00 2001
+From: John Crispin <blogic@openwrt.org>
+Date: Sat, 13 Apr 2013 10:11:51 +0200
+Subject: [PATCH 31/79] DT: add vendor prefixes for Ralink
+
+Signed-off-by: John Crispin <blogic@openwrt.org>
+Acked-by: Grant Likely <grant.likely@secretlab.ca>
+---
+ Documentation/devicetree/bindings/vendor-prefixes.txt |    1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/Documentation/devicetree/bindings/vendor-prefixes.txt b/Documentation/devicetree/bindings/vendor-prefixes.txt
+index 902b1b1..d1cc7bb 100644
+--- a/Documentation/devicetree/bindings/vendor-prefixes.txt
++++ b/Documentation/devicetree/bindings/vendor-prefixes.txt
+@@ -40,6 +40,7 @@ onnn ON Semiconductor Corp.
+ picochip      Picochip Ltd
+ powervr       PowerVR (deprecated, use img)
+ qcom  Qualcomm, Inc.
++ralink        Mediatek/Ralink Technology Corp.
+ ramtron       Ramtron International
+ realtek Realtek Semiconductor Corp.
+ samsung       Samsung Semiconductor
+-- 
+1.7.10.4
+
diff --git a/target/linux/ramips/patches-3.8/0032-DT-add-documentation-for-the-Ralink-MIPS-SoCs.patch b/target/linux/ramips/patches-3.8/0032-DT-add-documentation-for-the-Ralink-MIPS-SoCs.patch
new file mode 100644 (file)
index 0000000..1a66e63
--- /dev/null
@@ -0,0 +1,44 @@
+From 441d0189a47391c6882bbc6a11494e7cd394f1fc Mon Sep 17 00:00:00 2001
+From: Gabor Juhos <juhosg@openwrt.org>
+Date: Sat, 13 Apr 2013 09:02:40 +0200
+Subject: [PATCH 32/79] DT: add documentation for the Ralink MIPS SoCs
+
+This patch adds binding documentation for the
+compatible values of the Ralink MIPS SoCs.
+
+Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
+Signed-off-by: John Crispin <blogic@openwrt.org>
+Acked-by: Grant Likely <grant.likely@secretlab.ca>
+Patchwork: http://patchwork.linux-mips.org/patch/5187/
+---
+ Documentation/devicetree/bindings/mips/ralink.txt |   18 ++++++++++++++++++
+ 1 file changed, 18 insertions(+)
+ create mode 100644 Documentation/devicetree/bindings/mips/ralink.txt
+
+diff --git a/Documentation/devicetree/bindings/mips/ralink.txt b/Documentation/devicetree/bindings/mips/ralink.txt
+new file mode 100644
+index 0000000..59b6a35
+--- /dev/null
++++ b/Documentation/devicetree/bindings/mips/ralink.txt
+@@ -0,0 +1,18 @@
++Ralink MIPS SoC device tree bindings
++
++1. SoCs
++
++Each device tree must specify a compatible value for the Ralink SoC
++it uses in the compatible property of the root node. The compatible
++value must be one of the following values:
++
++  ralink,rt2880-soc
++  ralink,rt3050-soc
++  ralink,rt3052-soc
++  ralink,rt3350-soc
++  ralink,rt3352-soc
++  ralink,rt3883-soc
++  ralink,rt5350-soc
++  ralink,mt7620a-soc
++  ralink,mt7620n-soc
++
+-- 
+1.7.10.4
+
diff --git a/target/linux/ramips/patches-3.8/0033-DT-MIPS-ralink-clean-up-RT3050-dtsi-and-dts-file.patch b/target/linux/ramips/patches-3.8/0033-DT-MIPS-ralink-clean-up-RT3050-dtsi-and-dts-file.patch
new file mode 100644 (file)
index 0000000..a3a674f
--- /dev/null
@@ -0,0 +1,139 @@
+From 29d1bb6fc97d4391e4ecf96298b6ac42d0daefca Mon Sep 17 00:00:00 2001
+From: John Crispin <blogic@openwrt.org>
+Date: Thu, 20 Jun 2013 18:44:43 +0200
+Subject: [PATCH 33/79] DT: MIPS: ralink: clean up RT3050 dtsi and dts file
+
+* remove nodes for cores whose drivers are not upstream yet
+* add compat string for an additional soc
+* fix a whitespace error
+
+Signed-off-by: John Crispin <blogic@openwrt.org>
+Acked-by: Grant Likely <grant.likely@secretlab.ca>
+Patchwork: http://patchwork.linux-mips.org/patch/5186/
+---
+ arch/mips/ralink/dts/rt3050.dtsi     |   52 ++--------------------------------
+ arch/mips/ralink/dts/rt3052_eval.dts |   10 ++-----
+ 2 files changed, 4 insertions(+), 58 deletions(-)
+
+diff --git a/arch/mips/ralink/dts/rt3050.dtsi b/arch/mips/ralink/dts/rt3050.dtsi
+index 069d066..ef7da1e 100644
+--- a/arch/mips/ralink/dts/rt3050.dtsi
++++ b/arch/mips/ralink/dts/rt3050.dtsi
+@@ -1,7 +1,7 @@
+ / {
+       #address-cells = <1>;
+       #size-cells = <1>;
+-      compatible = "ralink,rt3050-soc", "ralink,rt3052-soc";
++      compatible = "ralink,rt3050-soc", "ralink,rt3052-soc", "ralink,rt3350-soc";
+       cpus {
+               cpu@0 {
+@@ -9,10 +9,6 @@
+               };
+       };
+-      chosen {
+-              bootargs = "console=ttyS0,57600 init=/init";
+-      };
+-
+       cpuintc: cpuintc@0 {
+               #address-cells = <0>;
+               #interrupt-cells = <1>;
+@@ -23,7 +19,7 @@
+       palmbus@10000000 {
+               compatible = "palmbus";
+               reg = <0x10000000 0x200000>;
+-                ranges = <0x0 0x10000000 0x1FFFFF>;
++              ranges = <0x0 0x10000000 0x1FFFFF>;
+               #address-cells = <1>;
+               #size-cells = <1>;
+@@ -33,11 +29,6 @@
+                       reg = <0x0 0x100>;
+               };
+-              timer@100 {
+-                      compatible = "ralink,rt3052-wdt", "ralink,rt2880-wdt";
+-                      reg = <0x100 0x100>;
+-              };
+-
+               intc: intc@200 {
+                       compatible = "ralink,rt3052-intc", "ralink,rt2880-intc";
+                       reg = <0x200 0x100>;
+@@ -54,45 +45,6 @@
+                       reg = <0x300 0x100>;
+               };
+-              gpio0: gpio@600 {
+-                      compatible = "ralink,rt3052-gpio", "ralink,rt2880-gpio";
+-                      reg = <0x600 0x34>;
+-
+-                      gpio-controller;
+-                      #gpio-cells = <2>;
+-
+-                      ralink,ngpio = <24>;
+-                      ralink,regs = [ 00 04 08 0c
+-                                      20 24 28 2c
+-                                      30 34 ];
+-              };
+-
+-              gpio1: gpio@638 {
+-                      compatible = "ralink,rt3052-gpio", "ralink,rt2880-gpio";
+-                      reg = <0x638 0x24>;
+-
+-                      gpio-controller;
+-                      #gpio-cells = <2>;
+-
+-                      ralink,ngpio = <16>;
+-                      ralink,regs = [ 00 04 08 0c
+-                                      10 14 18 1c
+-                                      20 24 ];
+-              };
+-
+-              gpio2: gpio@660 {
+-                      compatible = "ralink,rt3052-gpio", "ralink,rt2880-gpio";
+-                      reg = <0x660 0x24>;
+-
+-                      gpio-controller;
+-                      #gpio-cells = <2>;
+-
+-                      ralink,ngpio = <12>;
+-                      ralink,regs = [ 00 04 08 0c
+-                                      10 14 18 1c
+-                                      20 24 ];
+-              };
+-
+               uartlite@c00 {
+                       compatible = "ralink,rt3052-uart", "ralink,rt2880-uart", "ns16550a";
+                       reg = <0xc00 0x100>;
+diff --git a/arch/mips/ralink/dts/rt3052_eval.dts b/arch/mips/ralink/dts/rt3052_eval.dts
+index dc56e58..df17f5f 100644
+--- a/arch/mips/ralink/dts/rt3052_eval.dts
++++ b/arch/mips/ralink/dts/rt3052_eval.dts
+@@ -3,8 +3,6 @@
+ /include/ "rt3050.dtsi"
+ / {
+-      #address-cells = <1>;
+-      #size-cells = <1>;
+       compatible = "ralink,rt3052-eval-board", "ralink,rt3052-soc";
+       model = "Ralink RT3052 evaluation board";
+@@ -12,12 +10,8 @@
+               reg = <0x0 0x2000000>;
+       };
+-      palmbus@10000000 {
+-              sysc@0 {
+-                      ralink,pinmux = "uartlite", "spi";
+-                      ralink,uartmux = "gpio";
+-                      ralink,wdtmux = <0>;
+-              };
++      chosen {
++              bootargs = "console=ttyS0,57600";
+       };
+       cfi@1f000000 {
+-- 
+1.7.10.4
+
diff --git a/target/linux/ramips/patches-3.8/0034-DT-MIPS-ralink-add-RT2880-dts-files.patch b/target/linux/ramips/patches-3.8/0034-DT-MIPS-ralink-add-RT2880-dts-files.patch
new file mode 100644 (file)
index 0000000..affa771
--- /dev/null
@@ -0,0 +1,160 @@
+From b3cda181b5f9986b05bd95ee322504a8f2ed0b69 Mon Sep 17 00:00:00 2001
+From: John Crispin <blogic@openwrt.org>
+Date: Fri, 12 Apr 2013 06:27:37 +0000
+Subject: [PATCH 34/79] DT: MIPS: ralink: add RT2880 dts files
+
+Add a dtsi file for RT2880 SoC and a sample dts file.
+
+Signed-off-by: John Crispin <blogic@openwrt.org>
+Acked-by: Grant Likely <grant.likely@secretlab.ca>
+Patchwork: http://patchwork.linux-mips.org/patch/5188/
+---
+ arch/mips/ralink/Kconfig             |    4 +++
+ arch/mips/ralink/dts/Makefile        |    1 +
+ arch/mips/ralink/dts/rt2880.dtsi     |   58 ++++++++++++++++++++++++++++++++++
+ arch/mips/ralink/dts/rt2880_eval.dts |   46 +++++++++++++++++++++++++++
+ 4 files changed, 109 insertions(+)
+ create mode 100644 arch/mips/ralink/dts/rt2880.dtsi
+ create mode 100644 arch/mips/ralink/dts/rt2880_eval.dts
+
+diff --git a/arch/mips/ralink/Kconfig b/arch/mips/ralink/Kconfig
+index 86f6c77..2f6fbb8 100644
+--- a/arch/mips/ralink/Kconfig
++++ b/arch/mips/ralink/Kconfig
+@@ -34,6 +34,10 @@ choice
+       config DTB_RT_NONE
+               bool "None"
++      config DTB_RT2880_EVAL
++              bool "RT2880 eval kit"
++              depends on SOC_RT288X
++
+       config DTB_RT305X_EVAL
+               bool "RT305x eval kit"
+               depends on SOC_RT305X
+diff --git a/arch/mips/ralink/dts/Makefile b/arch/mips/ralink/dts/Makefile
+index 1a69fb3..f635a01 100644
+--- a/arch/mips/ralink/dts/Makefile
++++ b/arch/mips/ralink/dts/Makefile
+@@ -1 +1,2 @@
++obj-$(CONFIG_DTB_RT2880_EVAL) := rt2880_eval.dtb.o
+ obj-$(CONFIG_DTB_RT305X_EVAL) := rt3052_eval.dtb.o
+diff --git a/arch/mips/ralink/dts/rt2880.dtsi b/arch/mips/ralink/dts/rt2880.dtsi
+new file mode 100644
+index 0000000..182afde
+--- /dev/null
++++ b/arch/mips/ralink/dts/rt2880.dtsi
+@@ -0,0 +1,58 @@
++/ {
++      #address-cells = <1>;
++      #size-cells = <1>;
++      compatible = "ralink,rt2880-soc";
++
++      cpus {
++              cpu@0 {
++                      compatible = "mips,mips4KEc";
++              };
++      };
++
++      cpuintc: cpuintc@0 {
++              #address-cells = <0>;
++              #interrupt-cells = <1>;
++              interrupt-controller;
++              compatible = "mti,cpu-interrupt-controller";
++      };
++
++      palmbus@300000 {
++              compatible = "palmbus";
++              reg = <0x300000 0x200000>;
++                ranges = <0x0 0x300000 0x1FFFFF>;
++
++              #address-cells = <1>;
++              #size-cells = <1>;
++
++              sysc@0 {
++                      compatible = "ralink,rt2880-sysc";
++                      reg = <0x0 0x100>;
++              };
++
++              intc: intc@200 {
++                      compatible = "ralink,rt2880-intc";
++                      reg = <0x200 0x100>;
++
++                      interrupt-controller;
++                      #interrupt-cells = <1>;
++
++                      interrupt-parent = <&cpuintc>;
++                      interrupts = <2>;
++              };
++
++              memc@300 {
++                      compatible = "ralink,rt2880-memc";
++   &