target/linux/ramips/patches-3.10/0121-USB-adds-dwc_otg.patch

   1 From b74db0e9bae6bbe14e9f725db855621db22e9984 Mon Sep 17 00:00:00 2001
   2 From: John Crispin <blogic@openwrt.org>
   3 Date: Fri, 15 Mar 2013 20:58:18 +0100
   4 Subject: [PATCH 121/133] USB: adds dwc_otg
   5
   6 Signed-off-by: John Crispin <blogic@openwrt.org>
   7 ---
   8  drivers/usb/Kconfig                      |    2 +
   9  drivers/usb/Makefile                     |    1 +
  10  drivers/usb/dwc_otg/Kconfig              |   24 +
  11  drivers/usb/dwc_otg/Makefile             |   25 +
  12  drivers/usb/dwc_otg/dummy_audio.c        | 1575 +++++++++++++
  13  drivers/usb/dwc_otg/dwc_otg_attr.c       |  966 ++++++++
  14  drivers/usb/dwc_otg/dwc_otg_attr.h       |   67 +
  15  drivers/usb/dwc_otg/dwc_otg_cil.c        | 3692 ++++++++++++++++++++++++++++++
  16  drivers/usb/dwc_otg/dwc_otg_cil.h        | 1098 +++++++++
  17  drivers/usb/dwc_otg/dwc_otg_cil_intr.c   |  750 ++++++
  18  drivers/usb/dwc_otg/dwc_otg_driver.c     | 1273 ++++++++++
  19  drivers/usb/dwc_otg/dwc_otg_driver.h     |   83 +
  20  drivers/usb/dwc_otg/dwc_otg_hcd.c        | 2852 +++++++++++++++++++++++
  21  drivers/usb/dwc_otg/dwc_otg_hcd.h        |  668 ++++++
  22  drivers/usb/dwc_otg/dwc_otg_hcd_intr.c   | 1873 +++++++++++++++
  23  drivers/usb/dwc_otg/dwc_otg_hcd_queue.c  |  684 ++++++
  24  drivers/usb/dwc_otg/dwc_otg_pcd.c        | 2523 ++++++++++++++++++++
  25  drivers/usb/dwc_otg/dwc_otg_pcd.h        |  248 ++
  26  drivers/usb/dwc_otg/dwc_otg_pcd_intr.c   | 3654 +++++++++++++++++++++++++++++
  27  drivers/usb/dwc_otg/dwc_otg_regs.h       | 2075 +++++++++++++++++
  28  drivers/usb/dwc_otg/linux/dwc_otg_plat.h |  260 +++
  29  21 files changed, 24393 insertions(+)
  30  create mode 100644 drivers/usb/dwc_otg/Kconfig
  31  create mode 100644 drivers/usb/dwc_otg/Makefile
  32  create mode 100644 drivers/usb/dwc_otg/dummy_audio.c
  33  create mode 100644 drivers/usb/dwc_otg/dwc_otg_attr.c
  34  create mode 100644 drivers/usb/dwc_otg/dwc_otg_attr.h
  35  create mode 100644 drivers/usb/dwc_otg/dwc_otg_cil.c
  36  create mode 100644 drivers/usb/dwc_otg/dwc_otg_cil.h
  37  create mode 100644 drivers/usb/dwc_otg/dwc_otg_cil_intr.c
  38  create mode 100644 drivers/usb/dwc_otg/dwc_otg_driver.c
  39  create mode 100644 drivers/usb/dwc_otg/dwc_otg_driver.h
  40  create mode 100644 drivers/usb/dwc_otg/dwc_otg_hcd.c
  41  create mode 100644 drivers/usb/dwc_otg/dwc_otg_hcd.h
  42  create mode 100644 drivers/usb/dwc_otg/dwc_otg_hcd_intr.c
  43  create mode 100644 drivers/usb/dwc_otg/dwc_otg_hcd_queue.c
  44  create mode 100644 drivers/usb/dwc_otg/dwc_otg_pcd.c
  45  create mode 100644 drivers/usb/dwc_otg/dwc_otg_pcd.h
  46  create mode 100644 drivers/usb/dwc_otg/dwc_otg_pcd_intr.c
  47  create mode 100644 drivers/usb/dwc_otg/dwc_otg_regs.h
  48  create mode 100644 drivers/usb/dwc_otg/linux/dwc_otg_plat.h
  49
  50 --- a/drivers/usb/Kconfig
  51 +++ b/drivers/usb/Kconfig
  52 @@ -126,6 +126,8 @@ if USB
  53
  54  source "drivers/usb/core/Kconfig"
  55
  56 +source "drivers/usb/dwc_otg/Kconfig"
  57 +
  58  source "drivers/usb/mon/Kconfig"
  59
  60  source "drivers/usb/wusbcore/Kconfig"
  61 --- a/drivers/usb/Makefile
  62 +++ b/drivers/usb/Makefile
  63 @@ -7,6 +7,7 @@
  64  obj-$(CONFIG_USB)              += core/
  65
  66  obj-$(CONFIG_USB_DWC3)         += dwc3/
  67 +obj-$(CONFIG_DWC_OTG)          += dwc_otg/
  68
  69  obj-$(CONFIG_USB_MON)          += mon/
  70
  71 --- /dev/null
  72 +++ b/drivers/usb/dwc_otg/Kconfig
  73 @@ -0,0 +1,24 @@
  74 +config DWC_OTG
  75 +       tristate "Ralink RT305X DWC_OTG support"
  76 +       depends on SOC_RT305X
  77 +       ---help---
  78 +         This driver supports Ralink DWC_OTG
  79 +
  80 +choice
  81 +       prompt "USB Operation Mode"
  82 +       depends on DWC_OTG
  83 +       default DWC_OTG_HOST_ONLY
  84 +
  85 +config DWC_OTG_HOST_ONLY
  86 +       bool "HOST ONLY MODE"
  87 +       depends on DWC_OTG
  88 +
  89 +config DWC_OTG_DEVICE_ONLY
  90 +       bool "DEVICE ONLY MODE"
  91 +       depends on DWC_OTG
  92 +
  93 +endchoice
  94 +
  95 +config DWC_OTG_DEBUG
  96 +       bool "Enable debug mode"
  97 +       depends on DWC_OTG
  98 --- /dev/null
  99 +++ b/drivers/usb/dwc_otg/Makefile
 100 @@ -0,0 +1,25 @@
 101 +#
 102 +# Makefile for DWC_otg Highspeed USB controller driver
 103 +#
 104 +
 105 +ifeq ($(CONFIG_DWC_OTG_DEBUG),y)
 106 +EXTRA_CFLAGS   += -DDEBUG
 107 +endif
 108 +
 109 +# Use one of the following flags to compile the software in host-only or
 110 +# device-only mode.
 111 +ifeq ($(CONFIG_DWC_OTG_HOST_ONLY),y)
 112 +EXTRA_CFLAGS   += -DDWC_HOST_ONLY
 113 +EXTRA_CFLAGS   += -DDWC_EN_ISOC
 114 +endif
 115 +
 116 +ifeq ($(CONFIG_DWC_OTG_DEVICE_ONLY),y)
 117 +EXTRA_CFLAGS   += -DDWC_DEVICE_ONLY
 118 +endif
 119 +
 120 +obj-$(CONFIG_DWC_OTG)  := dwc_otg.o
 121 +
 122 +dwc_otg-objs   := dwc_otg_driver.o dwc_otg_attr.o
 123 +dwc_otg-objs   += dwc_otg_cil.o dwc_otg_cil_intr.o
 124 +dwc_otg-objs   += dwc_otg_pcd.o dwc_otg_pcd_intr.o
 125 +dwc_otg-objs   += dwc_otg_hcd.o dwc_otg_hcd_intr.o dwc_otg_hcd_queue.o
 126 --- /dev/null
 127 +++ b/drivers/usb/dwc_otg/dummy_audio.c
 128 @@ -0,0 +1,1575 @@
 129 +/*
 130 + * zero.c -- Gadget Zero, for USB development
 131 + *
 132 + * Copyright (C) 2003-2004 David Brownell
 133 + * All rights reserved.
 134 + *
 135 + * Redistribution and use in source and binary forms, with or without
 136 + * modification, are permitted provided that the following conditions
 137 + * are met:
 138 + * 1. Redistributions of source code must retain the above copyright
 139 + *    notice, this list of conditions, and the following disclaimer,
 140 + *    without modification.
 141 + * 2. Redistributions in binary form must reproduce the above copyright
 142 + *    notice, this list of conditions and the following disclaimer in the
 143 + *    documentation and/or other materials provided with the distribution.
 144 + * 3. The names of the above-listed copyright holders may not be used
 145 + *    to endorse or promote products derived from this software without
 146 + *    specific prior written permission.
 147 + *
 148 + * ALTERNATIVELY, this software may be distributed under the terms of the
 149 + * GNU General Public License ("GPL") as published by the Free Software
 150 + * Foundation, either version 2 of that License or (at your option) any
 151 + * later version.
 152 + *
 153 + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
 154 + * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
 155 + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
 156 + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
 157 + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
 158 + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
 159 + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
 160 + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
 161 + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
 162 + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
 163 + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 164 + */
 165 +
 166 +
 167 +/*
 168 + * Gadget Zero only needs two bulk endpoints, and is an example of how you
 169 + * can write a hardware-agnostic gadget driver running inside a USB device.
 170 + *
 171 + * Hardware details are visible (see CONFIG_USB_ZERO_* below) but don't
 172 + * affect most of the driver.
 173 + *
 174 + * Use it with the Linux host/master side "usbtest" driver to get a basic
 175 + * functional test of your device-side usb stack, or with "usb-skeleton".
 176 + *
 177 + * It supports two similar configurations.  One sinks whatever the usb host
 178 + * writes, and in return sources zeroes.  The other loops whatever the host
 179 + * writes back, so the host can read it.  Module options include:
 180 + *
 181 + *   buflen=N          default N=4096, buffer size used
 182 + *   qlen=N            default N=32, how many buffers in the loopback queue
 183 + *   loopdefault       default false, list loopback config first
 184 + *
 185 + * Many drivers will only have one configuration, letting them be much
 186 + * simpler if they also don't support high speed operation (like this
 187 + * driver does).
 188 + */
 189 +
 190 +#include <linux/config.h>
 191 +#include <linux/module.h>
 192 +#include <linux/kernel.h>
 193 +#include <linux/delay.h>
 194 +#include <linux/ioport.h>
 195 +#include <linux/sched.h>
 196 +#include <linux/slab.h>
 197 +#include <linux/smp_lock.h>
 198 +#include <linux/errno.h>
 199 +#include <linux/init.h>
 200 +#include <linux/timer.h>
 201 +#include <linux/list.h>
 202 +#include <linux/interrupt.h>
 203 +#include <linux/uts.h>
 204 +#include <linux/version.h>
 205 +#include <linux/device.h>
 206 +#include <linux/moduleparam.h>
 207 +#include <linux/proc_fs.h>
 208 +
 209 +#include <asm/byteorder.h>
 210 +#include <asm/io.h>
 211 +#include <asm/irq.h>
 212 +#include <asm/system.h>
 213 +#include <asm/unaligned.h>
 214 +
 215 +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,21)
 216 +# include <linux/usb/ch9.h>
 217 +#else
 218 +# include <linux/usb_ch9.h>
 219 +#endif
 220 +
 221 +#include <linux/usb_gadget.h>
 222 +
 223 +
 224 +/*-------------------------------------------------------------------------*/
 225 +/*-------------------------------------------------------------------------*/
 226 +
 227 +
 228 +static int utf8_to_utf16le(const char *s, u16 *cp, unsigned len)
 229 +{
 230 +       int     count = 0;
 231 +       u8      c;
 232 +       u16     uchar;
 233 +
 234 +       /* this insists on correct encodings, though not minimal ones.
 235 +        * BUT it currently rejects legit 4-byte UTF-8 code points,
 236 +        * which need surrogate pairs.  (Unicode 3.1 can use them.)
 237 +        */
 238 +       while (len != 0 && (c = (u8) *s++) != 0) {
 239 +               if (unlikely(c & 0x80)) {
 240 +                       // 2-byte sequence:
 241 +                       // 00000yyyyyxxxxxx = 110yyyyy 10xxxxxx
 242 +                       if ((c & 0xe0) == 0xc0) {
 243 +                               uchar = (c & 0x1f) << 6;
 244 +
 245 +                               c = (u8) *s++;
 246 +                               if ((c & 0xc0) != 0xc0)
 247 +                                       goto fail;
 248 +                               c &= 0x3f;
 249 +                               uchar |= c;
 250 +
 251 +                       // 3-byte sequence (most CJKV characters):
 252 +                       // zzzzyyyyyyxxxxxx = 1110zzzz 10yyyyyy 10xxxxxx
 253 +                       } else if ((c & 0xf0) == 0xe0) {
 254 +                               uchar = (c & 0x0f) << 12;
 255 +
 256 +                               c = (u8) *s++;
 257 +                               if ((c & 0xc0) != 0xc0)
 258 +                                       goto fail;
 259 +                               c &= 0x3f;
 260 +                               uchar |= c << 6;
 261 +
 262 +                               c = (u8) *s++;
 263 +                               if ((c & 0xc0) != 0xc0)
 264 +                                       goto fail;
 265 +                               c &= 0x3f;
 266 +                               uchar |= c;
 267 +
 268 +                               /* no bogus surrogates */
 269 +                               if (0xd800 <= uchar && uchar <= 0xdfff)
 270 +                                       goto fail;
 271 +
 272 +                       // 4-byte sequence (surrogate pairs, currently rare):
 273 +                       // 11101110wwwwzzzzyy + 110111yyyyxxxxxx
 274 +                       //     = 11110uuu 10uuzzzz 10yyyyyy 10xxxxxx
 275 +                       // (uuuuu = wwww + 1)
 276 +                       // FIXME accept the surrogate code points (only)
 277 +
 278 +                       } else
 279 +                               goto fail;
 280 +               } else
 281 +                       uchar = c;
 282 +               put_unaligned (cpu_to_le16 (uchar), cp++);
 283 +               count++;
 284 +               len--;
 285 +       }
 286 +       return count;
 287 +fail:
 288 +       return -1;
 289 +}
 290 +
 291 +
 292 +/**
 293 + * usb_gadget_get_string - fill out a string descriptor
 294 + * @table: of c strings encoded using UTF-8
 295 + * @id: string id, from low byte of wValue in get string descriptor
 296 + * @buf: at least 256 bytes
 297 + *
 298 + * Finds the UTF-8 string matching the ID, and converts it into a
 299 + * string descriptor in utf16-le.
 300 + * Returns length of descriptor (always even) or negative errno
 301 + *
 302 + * If your driver needs stings in multiple languages, you'll probably
 303 + * "switch (wIndex) { ... }"  in your ep0 string descriptor logic,
 304 + * using this routine after choosing which set of UTF-8 strings to use.
 305 + * Note that US-ASCII is a strict subset of UTF-8; any string bytes with
 306 + * the eighth bit set will be multibyte UTF-8 characters, not ISO-8859/1
 307 + * characters (which are also widely used in C strings).
 308 + */
 309 +int
 310 +usb_gadget_get_string (struct usb_gadget_strings *table, int id, u8 *buf)
 311 +{
 312 +       struct usb_string       *s;
 313 +       int                     len;
 314 +
 315 +       /* descriptor 0 has the language id */
 316 +       if (id == 0) {
 317 +               buf [0] = 4;
 318 +               buf [1] = USB_DT_STRING;
 319 +               buf [2] = (u8) table->language;
 320 +               buf [3] = (u8) (table->language >> 8);
 321 +               return 4;
 322 +       }
 323 +       for (s = table->strings; s && s->s; s++)
 324 +               if (s->id == id)
 325 +                       break;
 326 +
 327 +       /* unrecognized: stall. */
 328 +       if (!s || !s->s)
 329 +               return -EINVAL;
 330 +
 331 +       /* string descriptors have length, tag, then UTF16-LE text */
 332 +       len = min ((size_t) 126, strlen (s->s));
 333 +       memset (buf + 2, 0, 2 * len);   /* zero all the bytes */
 334 +       len = utf8_to_utf16le(s->s, (u16 *)&buf[2], len);
 335 +       if (len < 0)
 336 +               return -EINVAL;
 337 +       buf [0] = (len + 1) * 2;
 338 +       buf [1] = USB_DT_STRING;
 339 +       return buf [0];
 340 +}
 341 +
 342 +
 343 +/*-------------------------------------------------------------------------*/
 344 +/*-------------------------------------------------------------------------*/
 345 +
 346 +
 347 +/**
 348 + * usb_descriptor_fillbuf - fill buffer with descriptors
 349 + * @buf: Buffer to be filled
 350 + * @buflen: Size of buf
 351 + * @src: Array of descriptor pointers, terminated by null pointer.
 352 + *
 353 + * Copies descriptors into the buffer, returning the length or a
 354 + * negative error code if they can't all be copied.  Useful when
 355 + * assembling descriptors for an associated set of interfaces used
 356 + * as part of configuring a composite device; or in other cases where
 357 + * sets of descriptors need to be marshaled.
 358 + */
 359 +int
 360 +usb_descriptor_fillbuf(void *buf, unsigned buflen,
 361 +               const struct usb_descriptor_header **src)
 362 +{
 363 +       u8      *dest = buf;
 364 +
 365 +       if (!src)
 366 +               return -EINVAL;
 367 +
 368 +       /* fill buffer from src[] until null descriptor ptr */
 369 +       for (; 0 != *src; src++) {
 370 +               unsigned                len = (*src)->bLength;
 371 +
 372 +               if (len > buflen)
 373 +                       return -EINVAL;
 374 +               memcpy(dest, *src, len);
 375 +               buflen -= len;
 376 +               dest += len;
 377 +       }
 378 +       return dest - (u8 *)buf;
 379 +}
 380 +
 381 +
 382 +/**
 383 + * usb_gadget_config_buf - builts a complete configuration descriptor
 384 + * @config: Header for the descriptor, including characteristics such
 385 + *     as power requirements and number of interfaces.
 386 + * @desc: Null-terminated vector of pointers to the descriptors (interface,
 387 + *     endpoint, etc) defining all functions in this device configuration.
 388 + * @buf: Buffer for the resulting configuration descriptor.
 389 + * @length: Length of buffer.  If this is not big enough to hold the
 390 + *     entire configuration descriptor, an error code will be returned.
 391 + *
 392 + * This copies descriptors into the response buffer, building a descriptor
 393 + * for that configuration.  It returns the buffer length or a negative
 394 + * status code.  The config.wTotalLength field is set to match the length
 395 + * of the result, but other descriptor fields (including power usage and
 396 + * interface count) must be set by the caller.
 397 + *
 398 + * Gadget drivers could use this when constructing a config descriptor
 399 + * in response to USB_REQ_GET_DESCRIPTOR.  They will need to patch the
 400 + * resulting bDescriptorType value if USB_DT_OTHER_SPEED_CONFIG is needed.
 401 + */
 402 +int usb_gadget_config_buf(
 403 +       const struct usb_config_descriptor      *config,
 404 +       void                                    *buf,
 405 +       unsigned                                length,
 406 +       const struct usb_descriptor_header      **desc
 407 +)
 408 +{
 409 +       struct usb_config_descriptor            *cp = buf;
 410 +       int                                     len;
 411 +
 412 +       /* config descriptor first */
 413 +       if (length < USB_DT_CONFIG_SIZE || !desc)
 414 +               return -EINVAL;
 415 +       *cp = *config;
 416 +
 417 +       /* then interface/endpoint/class/vendor/... */
 418 +       len = usb_descriptor_fillbuf(USB_DT_CONFIG_SIZE + (u8*)buf,
 419 +                       length - USB_DT_CONFIG_SIZE, desc);
 420 +       if (len < 0)
 421 +               return len;
 422 +       len += USB_DT_CONFIG_SIZE;
 423 +       if (len > 0xffff)
 424 +               return -EINVAL;
 425 +
 426 +       /* patch up the config descriptor */
 427 +       cp->bLength = USB_DT_CONFIG_SIZE;
 428 +       cp->bDescriptorType = USB_DT_CONFIG;
 429 +       cp->wTotalLength = cpu_to_le16(len);
 430 +       cp->bmAttributes |= USB_CONFIG_ATT_ONE;
 431 +       return len;
 432 +}
 433 +
 434 +/*-------------------------------------------------------------------------*/
 435 +/*-------------------------------------------------------------------------*/
 436 +
 437 +
 438 +#define RBUF_LEN (1024*1024)
 439 +static int rbuf_start;
 440 +static int rbuf_len;
 441 +static __u8 rbuf[RBUF_LEN];
 442 +
 443 +/*-------------------------------------------------------------------------*/
 444 +
 445 +#define DRIVER_VERSION         "St Patrick's Day 2004"
 446 +
 447 +static const char shortname [] = "zero";
 448 +static const char longname [] = "YAMAHA YST-MS35D USB Speaker  ";
 449 +
 450 +static const char source_sink [] = "source and sink data";
 451 +static const char loopback [] = "loop input to output";
 452 +
 453 +/*-------------------------------------------------------------------------*/
 454 +
 455 +/*
 456 + * driver assumes self-powered hardware, and
 457 + * has no way for users to trigger remote wakeup.
 458 + *
 459 + * this version autoconfigures as much as possible,
 460 + * which is reasonable for most "bulk-only" drivers.
 461 + */
 462 +static const char *EP_IN_NAME;         /* source */
 463 +static const char *EP_OUT_NAME;                /* sink */
 464 +
 465 +/*-------------------------------------------------------------------------*/
 466 +
 467 +/* big enough to hold our biggest descriptor */
 468 +#define USB_BUFSIZ     512
 469 +
 470 +struct zero_dev {
 471 +       spinlock_t              lock;
 472 +       struct usb_gadget       *gadget;
 473 +       struct usb_request      *req;           /* for control responses */
 474 +
 475 +       /* when configured, we have one of two configs:
 476 +        * - source data (in to host) and sink it (out from host)
 477 +        * - or loop it back (out from host back in to host)
 478 +        */
 479 +       u8                      config;
 480 +       struct usb_ep           *in_ep, *out_ep;
 481 +
 482 +       /* autoresume timer */
 483 +       struct timer_list       resume;
 484 +};
 485 +
 486 +#define xprintk(d,level,fmt,args...) \
 487 +       dev_printk(level , &(d)->gadget->dev , fmt , ## args)
 488 +
 489 +#ifdef DEBUG
 490 +#define DBG(dev,fmt,args...) \
 491 +       xprintk(dev , KERN_DEBUG , fmt , ## args)
 492 +#else
 493 +#define DBG(dev,fmt,args...) \
 494 +       do { } while (0)
 495 +#endif /* DEBUG */
 496 +
 497 +#ifdef VERBOSE
 498 +#define VDBG   DBG
 499 +#else
 500 +#define VDBG(dev,fmt,args...) \
 501 +       do { } while (0)
 502 +#endif /* VERBOSE */
 503 +
 504 +#define ERROR(dev,fmt,args...) \
 505 +       xprintk(dev , KERN_ERR , fmt , ## args)
 506 +#define WARN(dev,fmt,args...) \
 507 +       xprintk(dev , KERN_WARNING , fmt , ## args)
 508 +#define INFO(dev,fmt,args...) \
 509 +       xprintk(dev , KERN_INFO , fmt , ## args)
 510 +
 511 +/*-------------------------------------------------------------------------*/
 512 +
 513 +static unsigned buflen = 4096;
 514 +static unsigned qlen = 32;
 515 +static unsigned pattern = 0;
 516 +
 517 +module_param (buflen, uint, S_IRUGO|S_IWUSR);
 518 +module_param (qlen, uint, S_IRUGO|S_IWUSR);
 519 +module_param (pattern, uint, S_IRUGO|S_IWUSR);
 520 +
 521 +/*
 522 + * if it's nonzero, autoresume says how many seconds to wait
 523 + * before trying to wake up the host after suspend.
 524 + */
 525 +static unsigned autoresume = 0;
 526 +module_param (autoresume, uint, 0);
 527 +
 528 +/*
 529 + * Normally the "loopback" configuration is second (index 1) so
 530 + * it's not the default.  Here's where to change that order, to
 531 + * work better with hosts where config changes are problematic.
 532 + * Or controllers (like superh) that only support one config.
 533 + */
 534 +static int loopdefault = 0;
 535 +
 536 +module_param (loopdefault, bool, S_IRUGO|S_IWUSR);
 537 +
 538 +/*-------------------------------------------------------------------------*/
 539 +
 540 +/* Thanks to NetChip Technologies for donating this product ID.
 541 + *
 542 + * DO NOT REUSE THESE IDs with a protocol-incompatible driver!!  Ever!!
 543 + * Instead:  allocate your own, using normal USB-IF procedures.
 544 + */
 545 +#ifndef        CONFIG_USB_ZERO_HNPTEST
 546 +#define DRIVER_VENDOR_NUM      0x0525          /* NetChip */
 547 +#define DRIVER_PRODUCT_NUM     0xa4a0          /* Linux-USB "Gadget Zero" */
 548 +#else
 549 +#define DRIVER_VENDOR_NUM      0x1a0a          /* OTG test device IDs */
 550 +#define DRIVER_PRODUCT_NUM     0xbadd
 551 +#endif
 552 +
 553 +/*-------------------------------------------------------------------------*/
 554 +
 555 +/*
 556 + * DESCRIPTORS ... most are static, but strings and (full)
 557 + * configuration descriptors are built on demand.
 558 + */
 559 +
 560 +/*
 561 +#define STRING_MANUFACTURER            25
 562 +#define STRING_PRODUCT                 42
 563 +#define STRING_SERIAL                  101
 564 +*/
 565 +#define STRING_MANUFACTURER            1
 566 +#define STRING_PRODUCT                 2
 567 +#define STRING_SERIAL                  3
 568 +
 569 +#define STRING_SOURCE_SINK             250
 570 +#define STRING_LOOPBACK                        251
 571 +
 572 +/*
 573 + * This device advertises two configurations; these numbers work
 574 + * on a pxa250 as well as more flexible hardware.
 575 + */
 576 +#define        CONFIG_SOURCE_SINK      3
 577 +#define        CONFIG_LOOPBACK         2
 578 +
 579 +/*
 580 +static struct usb_device_descriptor
 581 +device_desc = {
 582 +       .bLength =              sizeof device_desc,
 583 +       .bDescriptorType =      USB_DT_DEVICE,
 584 +
 585 +       .bcdUSB =               __constant_cpu_to_le16 (0x0200),
 586 +       .bDeviceClass =         USB_CLASS_VENDOR_SPEC,
 587 +
 588 +       .idVendor =             __constant_cpu_to_le16 (DRIVER_VENDOR_NUM),
 589 +       .idProduct =            __constant_cpu_to_le16 (DRIVER_PRODUCT_NUM),
 590 +       .iManufacturer =        STRING_MANUFACTURER,
 591 +       .iProduct =             STRING_PRODUCT,
 592 +       .iSerialNumber =        STRING_SERIAL,
 593 +       .bNumConfigurations =   2,
 594 +};
 595 +*/
 596 +static struct usb_device_descriptor
 597 +device_desc = {
 598 +       .bLength =              sizeof device_desc,
 599 +       .bDescriptorType =      USB_DT_DEVICE,
 600 +       .bcdUSB =               __constant_cpu_to_le16 (0x0100),
 601 +       .bDeviceClass =         USB_CLASS_PER_INTERFACE,
 602 +       .bDeviceSubClass =      0,
 603 +       .bDeviceProtocol =      0,
 604 +       .bMaxPacketSize0 =      64,
 605 +       .bcdDevice =            __constant_cpu_to_le16 (0x0100),
 606 +       .idVendor =             __constant_cpu_to_le16 (0x0499),
 607 +       .idProduct =            __constant_cpu_to_le16 (0x3002),
 608 +       .iManufacturer =        STRING_MANUFACTURER,
 609 +       .iProduct =             STRING_PRODUCT,
 610 +       .iSerialNumber =        STRING_SERIAL,
 611 +       .bNumConfigurations =   1,
 612 +};
 613 +
 614 +static struct usb_config_descriptor
 615 +z_config = {
 616 +       .bLength =              sizeof z_config,
 617 +       .bDescriptorType =      USB_DT_CONFIG,
 618 +
 619 +       /* compute wTotalLength on the fly */
 620 +       .bNumInterfaces =       2,
 621 +       .bConfigurationValue =  1,
 622 +       .iConfiguration =       0,
 623 +       .bmAttributes =         0x40,
 624 +       .bMaxPower =            0,      /* self-powered */
 625 +};
 626 +
 627 +
 628 +static struct usb_otg_descriptor
 629 +otg_descriptor = {
 630 +       .bLength =              sizeof otg_descriptor,
 631 +       .bDescriptorType =      USB_DT_OTG,
 632 +
 633 +       .bmAttributes =         USB_OTG_SRP,
 634 +};
 635 +
 636 +/* one interface in each configuration */
 637 +#ifdef CONFIG_USB_GADGET_DUALSPEED
 638 +
 639 +/*
 640 + * usb 2.0 devices need to expose both high speed and full speed
 641 + * descriptors, unless they only run at full speed.
 642 + *
 643 + * that means alternate endpoint descriptors (bigger packets)
 644 + * and a "device qualifier" ... plus more construction options
 645 + * for the config descriptor.
 646 + */
 647 +
 648 +static struct usb_qualifier_descriptor
 649 +dev_qualifier = {
 650 +       .bLength =              sizeof dev_qualifier,
 651 +       .bDescriptorType =      USB_DT_DEVICE_QUALIFIER,
 652 +
 653 +       .bcdUSB =               __constant_cpu_to_le16 (0x0200),
 654 +       .bDeviceClass =         USB_CLASS_VENDOR_SPEC,
 655 +
 656 +       .bNumConfigurations =   2,
 657 +};
 658 +
 659 +
 660 +struct usb_cs_as_general_descriptor {
 661 +       __u8  bLength;
 662 +       __u8  bDescriptorType;
 663 +
 664 +       __u8  bDescriptorSubType;
 665 +       __u8  bTerminalLink;
 666 +       __u8  bDelay;
 667 +       __u16  wFormatTag;
 668 +} __attribute__ ((packed));
 669 +
 670 +struct usb_cs_as_format_descriptor {
 671 +       __u8  bLength;
 672 +       __u8  bDescriptorType;
 673 +
 674 +       __u8  bDescriptorSubType;
 675 +       __u8  bFormatType;
 676 +       __u8  bNrChannels;
 677 +       __u8  bSubframeSize;
 678 +       __u8  bBitResolution;
 679 +       __u8  bSamfreqType;
 680 +       __u8  tLowerSamFreq[3];
 681 +       __u8  tUpperSamFreq[3];
 682 +} __attribute__ ((packed));
 683 +
 684 +static const struct usb_interface_descriptor
 685 +z_audio_control_if_desc = {
 686 +       .bLength =              sizeof z_audio_control_if_desc,
 687 +       .bDescriptorType =      USB_DT_INTERFACE,
 688 +       .bInterfaceNumber = 0,
 689 +       .bAlternateSetting = 0,
 690 +       .bNumEndpoints = 0,
 691 +       .bInterfaceClass = USB_CLASS_AUDIO,
 692 +       .bInterfaceSubClass = 0x1,
 693 +       .bInterfaceProtocol = 0,
 694 +       .iInterface = 0,
 695 +};
 696 +
 697 +static const struct usb_interface_descriptor
 698 +z_audio_if_desc = {
 699 +       .bLength =              sizeof z_audio_if_desc,
 700 +       .bDescriptorType =      USB_DT_INTERFACE,
 701 +       .bInterfaceNumber = 1,
 702 +       .bAlternateSetting = 0,
 703 +       .bNumEndpoints = 0,
 704 +       .bInterfaceClass = USB_CLASS_AUDIO,
 705 +       .bInterfaceSubClass = 0x2,
 706 +       .bInterfaceProtocol = 0,
 707 +       .iInterface = 0,
 708 +};
 709 +
 710 +static const struct usb_interface_descriptor
 711 +z_audio_if_desc2 = {
 712 +       .bLength =              sizeof z_audio_if_desc,
 713 +       .bDescriptorType =      USB_DT_INTERFACE,
 714 +       .bInterfaceNumber = 1,
 715 +       .bAlternateSetting = 1,
 716 +       .bNumEndpoints = 1,
 717 +       .bInterfaceClass = USB_CLASS_AUDIO,
 718 +       .bInterfaceSubClass = 0x2,
 719 +       .bInterfaceProtocol = 0,
 720 +       .iInterface = 0,
 721 +};
 722 +
 723 +static const struct usb_cs_as_general_descriptor
 724 +z_audio_cs_as_if_desc = {
 725 +       .bLength = 7,
 726 +       .bDescriptorType = 0x24,
 727 +
 728 +       .bDescriptorSubType = 0x01,
 729 +       .bTerminalLink = 0x01,
 730 +       .bDelay = 0x0,
 731 +       .wFormatTag = __constant_cpu_to_le16 (0x0001)
 732 +};
 733 +
 734 +
 735 +static const struct usb_cs_as_format_descriptor
 736 +z_audio_cs_as_format_desc = {
 737 +       .bLength = 0xe,
 738 +       .bDescriptorType = 0x24,
 739 +
 740 +       .bDescriptorSubType = 2,
 741 +       .bFormatType = 1,
 742 +       .bNrChannels = 1,
 743 +       .bSubframeSize = 1,
 744 +       .bBitResolution = 8,
 745 +       .bSamfreqType = 0,
 746 +       .tLowerSamFreq = {0x7e, 0x13, 0x00},
 747 +       .tUpperSamFreq = {0xe2, 0xd6, 0x00},
 748 +};
 749 +
 750 +static const struct usb_endpoint_descriptor
 751 +z_iso_ep = {
 752 +       .bLength = 0x09,
 753 +       .bDescriptorType = 0x05,
 754 +       .bEndpointAddress = 0x04,
 755 +       .bmAttributes = 0x09,
 756 +       .wMaxPacketSize = 0x0038,
 757 +       .bInterval = 0x01,
 758 +       .bRefresh = 0x00,
 759 +       .bSynchAddress = 0x00,
 760 +};
 761 +
 762 +static char z_iso_ep2[] = {0x07, 0x25, 0x01, 0x00, 0x02, 0x00, 0x02};
 763 +
 764 +// 9 bytes
 765 +static char z_ac_interface_header_desc[] =
 766 +{ 0x09, 0x24, 0x01, 0x00, 0x01, 0x2b, 0x00, 0x01, 0x01 };
 767 +
 768 +// 12 bytes
 769 +static char z_0[] = {0x0c, 0x24, 0x02, 0x01, 0x01, 0x01, 0x00, 0x02,
 770 +                    0x03, 0x00, 0x00, 0x00};
 771 +// 13 bytes
 772 +static char z_1[] = {0x0d, 0x24, 0x06, 0x02, 0x01, 0x02, 0x15, 0x00,
 773 +                    0x02, 0x00, 0x02, 0x00, 0x00};
 774 +// 9 bytes
 775 +static char z_2[] = {0x09, 0x24, 0x03, 0x03, 0x01, 0x03, 0x00, 0x02,
 776 +                    0x00};
 777 +
 778 +static char za_0[] = {0x09, 0x04, 0x01, 0x02, 0x01, 0x01, 0x02, 0x00,
 779 +                     0x00};
 780 +
 781 +static char za_1[] = {0x07, 0x24, 0x01, 0x01, 0x00, 0x01, 0x00};
 782 +
 783 +static char za_2[] = {0x0e, 0x24, 0x02, 0x01, 0x02, 0x01, 0x08, 0x00,
 784 +                     0x7e, 0x13, 0x00, 0xe2, 0xd6, 0x00};
 785 +
 786 +static char za_3[] = {0x09, 0x05, 0x04, 0x09, 0x70, 0x00, 0x01, 0x00,
 787 +                     0x00};
 788 +
 789 +static char za_4[] = {0x07, 0x25, 0x01, 0x00, 0x02, 0x00, 0x02};
 790 +
 791 +static char za_5[] = {0x09, 0x04, 0x01, 0x03, 0x01, 0x01, 0x02, 0x00,
 792 +                     0x00};
 793 +
 794 +static char za_6[] = {0x07, 0x24, 0x01, 0x01, 0x00, 0x01, 0x00};
 795 +
 796 +static char za_7[] = {0x0e, 0x24, 0x02, 0x01, 0x01, 0x02, 0x10, 0x00,
 797 +                     0x7e, 0x13, 0x00, 0xe2, 0xd6, 0x00};
 798 +
 799 +static char za_8[] = {0x09, 0x05, 0x04, 0x09, 0x70, 0x00, 0x01, 0x00,
 800 +                     0x00};
 801 +
 802 +static char za_9[] = {0x07, 0x25, 0x01, 0x00, 0x02, 0x00, 0x02};
 803 +
 804 +static char za_10[] = {0x09, 0x04, 0x01, 0x04, 0x01, 0x01, 0x02, 0x00,
 805 +                      0x00};
 806 +
 807 +static char za_11[] = {0x07, 0x24, 0x01, 0x01, 0x00, 0x01, 0x00};
 808 +
 809 +static char za_12[] = {0x0e, 0x24, 0x02, 0x01, 0x02, 0x02, 0x10, 0x00,
 810 +                      0x73, 0x13, 0x00, 0xe2, 0xd6, 0x00};
 811 +
 812 +static char za_13[] = {0x09, 0x05, 0x04, 0x09, 0xe0, 0x00, 0x01, 0x00,
 813 +                      0x00};
 814 +
 815 +static char za_14[] = {0x07, 0x25, 0x01, 0x00, 0x02, 0x00, 0x02};
 816 +
 817 +static char za_15[] = {0x09, 0x04, 0x01, 0x05, 0x01, 0x01, 0x02, 0x00,
 818 +                      0x00};
 819 +
 820 +static char za_16[] = {0x07, 0x24, 0x01, 0x01, 0x00, 0x01, 0x00};
 821 +
 822 +static char za_17[] = {0x0e, 0x24, 0x02, 0x01, 0x01, 0x03, 0x14, 0x00,
 823 +                      0x7e, 0x13, 0x00, 0xe2, 0xd6, 0x00};
 824 +
 825 +static char za_18[] = {0x09, 0x05, 0x04, 0x09, 0xa8, 0x00, 0x01, 0x00,
 826 +                      0x00};
 827 +
 828 +static char za_19[] = {0x07, 0x25, 0x01, 0x00, 0x02, 0x00, 0x02};
 829 +
 830 +static char za_20[] = {0x09, 0x04, 0x01, 0x06, 0x01, 0x01, 0x02, 0x00,
 831 +                      0x00};
 832 +
 833 +static char za_21[] = {0x07, 0x24, 0x01, 0x01, 0x00, 0x01, 0x00};
 834 +
 835 +static char za_22[] = {0x0e, 0x24, 0x02, 0x01, 0x02, 0x03, 0x14, 0x00,
 836 +                      0x7e, 0x13, 0x00, 0xe2, 0xd6, 0x00};
 837 +
 838 +static char za_23[] = {0x09, 0x05, 0x04, 0x09, 0x50, 0x01, 0x01, 0x00,
 839 +                      0x00};
 840 +
 841 +static char za_24[] = {0x07, 0x25, 0x01, 0x00, 0x02, 0x00, 0x02};
 842 +
 843 +
 844 +
 845 +static const struct usb_descriptor_header *z_function [] = {
 846 +       (struct usb_descriptor_header *) &z_audio_control_if_desc,
 847 +       (struct usb_descriptor_header *) &z_ac_interface_header_desc,
 848 +       (struct usb_descriptor_header *) &z_0,
 849 +       (struct usb_descriptor_header *) &z_1,
 850 +       (struct usb_descriptor_header *) &z_2,
 851 +       (struct usb_descriptor_header *) &z_audio_if_desc,
 852 +       (struct usb_descriptor_header *) &z_audio_if_desc2,
 853 +       (struct usb_descriptor_header *) &z_audio_cs_as_if_desc,
 854 +       (struct usb_descriptor_header *) &z_audio_cs_as_format_desc,
 855 +       (struct usb_descriptor_header *) &z_iso_ep,
 856 +       (struct usb_descriptor_header *) &z_iso_ep2,
 857 +       (struct usb_descriptor_header *) &za_0,
 858 +       (struct usb_descriptor_header *) &za_1,
 859 +       (struct usb_descriptor_header *) &za_2,
 860 +       (struct usb_descriptor_header *) &za_3,
 861 +       (struct usb_descriptor_header *) &za_4,
 862 +       (struct usb_descriptor_header *) &za_5,
 863 +       (struct usb_descriptor_header *) &za_6,
 864 +       (struct usb_descriptor_header *) &za_7,
 865 +       (struct usb_descriptor_header *) &za_8,
 866 +       (struct usb_descriptor_header *) &za_9,
 867 +       (struct usb_descriptor_header *) &za_10,
 868 +       (struct usb_descriptor_header *) &za_11,
 869 +       (struct usb_descriptor_header *) &za_12,
 870 +       (struct usb_descriptor_header *) &za_13,
 871 +       (struct usb_descriptor_header *) &za_14,
 872 +       (struct usb_descriptor_header *) &za_15,
 873 +       (struct usb_descriptor_header *) &za_16,
 874 +       (struct usb_descriptor_header *) &za_17,
 875 +       (struct usb_descriptor_header *) &za_18,
 876 +       (struct usb_descriptor_header *) &za_19,
 877 +       (struct usb_descriptor_header *) &za_20,
 878 +       (struct usb_descriptor_header *) &za_21,
 879 +       (struct usb_descriptor_header *) &za_22,
 880 +       (struct usb_descriptor_header *) &za_23,
 881 +       (struct usb_descriptor_header *) &za_24,
 882 +       NULL,
 883 +};
 884 +
 885 +/* maxpacket and other transfer characteristics vary by speed. */
 886 +#define ep_desc(g,hs,fs) (((g)->speed==USB_SPEED_HIGH)?(hs):(fs))
 887 +
 888 +#else
 889 +
 890 +/* if there's no high speed support, maxpacket doesn't change. */
 891 +#define ep_desc(g,hs,fs) fs
 892 +
 893 +#endif /* !CONFIG_USB_GADGET_DUALSPEED */
 894 +
 895 +static char                            manufacturer [40];
 896 +//static char                          serial [40];
 897 +static char                            serial [] = "Ser 00 em";
 898 +
 899 +/* static strings, in UTF-8 */
 900 +static struct usb_string               strings [] = {
 901 +       { STRING_MANUFACTURER, manufacturer, },
 902 +       { STRING_PRODUCT, longname, },
 903 +       { STRING_SERIAL, serial, },
 904 +       { STRING_LOOPBACK, loopback, },
 905 +       { STRING_SOURCE_SINK, source_sink, },
 906 +       {  }                    /* end of list */
 907 +};
 908 +
 909 +static struct usb_gadget_strings       stringtab = {
 910 +       .language       = 0x0409,       /* en-us */
 911 +       .strings        = strings,
 912 +};
 913 +
 914 +/*
 915 + * config descriptors are also handcrafted.  these must agree with code
 916 + * that sets configurations, and with code managing interfaces and their
 917 + * altsettings.  other complexity may come from:
 918 + *
 919 + *  - high speed support, including "other speed config" rules
 920 + *  - multiple configurations
 921 + *  - interfaces with alternate settings
 922 + *  - embedded class or vendor-specific descriptors
 923 + *
 924 + * this handles high speed, and has a second config that could as easily
 925 + * have been an alternate interface setting (on most hardware).
 926 + *
 927 + * NOTE:  to demonstrate (and test) more USB capabilities, this driver
 928 + * should include an altsetting to test interrupt transfers, including
 929 + * high bandwidth modes at high speed.  (Maybe work like Intel's test
 930 + * device?)
 931 + */
 932 +static int
 933 +config_buf (struct usb_gadget *gadget, u8 *buf, u8 type, unsigned index)
 934 +{
 935 +       int len;
 936 +       const struct usb_descriptor_header **function;
 937 +
 938 +       function = z_function;
 939 +       len = usb_gadget_config_buf (&z_config, buf, USB_BUFSIZ, function);
 940 +       if (len < 0)
 941 +               return len;
 942 +       ((struct usb_config_descriptor *) buf)->bDescriptorType = type;
 943 +       return len;
 944 +}
 945 +
 946 +/*-------------------------------------------------------------------------*/
 947 +
 948 +static struct usb_request *
 949 +alloc_ep_req (struct usb_ep *ep, unsigned length)
 950 +{
 951 +       struct usb_request      *req;
 952 +
 953 +       req = usb_ep_alloc_request (ep, GFP_ATOMIC);
 954 +       if (req) {
 955 +               req->length = length;
 956 +               req->buf = usb_ep_alloc_buffer (ep, length,
 957 +                               &req->dma, GFP_ATOMIC);
 958 +               if (!req->buf) {
 959 +                       usb_ep_free_request (ep, req);
 960 +                       req = NULL;
 961 +               }
 962 +       }
 963 +       return req;
 964 +}
 965 +
 966 +static void free_ep_req (struct usb_ep *ep, struct usb_request *req)
 967 +{
 968 +       if (req->buf)
 969 +               usb_ep_free_buffer (ep, req->buf, req->dma, req->length);
 970 +       usb_ep_free_request (ep, req);
 971 +}
 972 +
 973 +/*-------------------------------------------------------------------------*/
 974 +
 975 +/* optionally require specific source/sink data patterns  */
 976 +
 977 +static int
 978 +check_read_data (
 979 +       struct zero_dev         *dev,
 980 +       struct usb_ep           *ep,
 981 +       struct usb_request      *req
 982 +)
 983 +{
 984 +       unsigned        i;
 985 +       u8              *buf = req->buf;
 986 +
 987 +       for (i = 0; i < req->actual; i++, buf++) {
 988 +               switch (pattern) {
 989 +               /* all-zeroes has no synchronization issues */
 990 +               case 0:
 991 +                       if (*buf == 0)
 992 +                               continue;
 993 +                       break;
 994 +               /* mod63 stays in sync with short-terminated transfers,
 995 +                * or otherwise when host and gadget agree on how large
 996 +                * each usb transfer request should be.  resync is done
 997 +                * with set_interface or set_config.
 998 +                */
 999 +               case 1:
1000 +                       if (*buf == (u8)(i % 63))
1001 +                               continue;
1002 +                       break;
1003 +               }
1004 +               ERROR (dev, "bad OUT byte, buf [%d] = %d\n", i, *buf);
1005 +               usb_ep_set_halt (ep);
1006 +               return -EINVAL;
1007 +       }
1008 +       return 0;
1009 +}
1010 +
1011 +/*-------------------------------------------------------------------------*/
1012 +
1013 +static void zero_reset_config (struct zero_dev *dev)
1014 +{
1015 +       if (dev->config == 0)
1016 +               return;
1017 +
1018 +       DBG (dev, "reset config\n");
1019 +
1020 +       /* just disable endpoints, forcing completion of pending i/o.
1021 +        * all our completion handlers free their requests in this case.
1022 +        */
1023 +       if (dev->in_ep) {
1024 +               usb_ep_disable (dev->in_ep);
1025 +               dev->in_ep = NULL;
1026 +       }
1027 +       if (dev->out_ep) {
1028 +               usb_ep_disable (dev->out_ep);
1029 +               dev->out_ep = NULL;
1030 +       }
1031 +       dev->config = 0;
1032 +       del_timer (&dev->resume);
1033 +}
1034 +
1035 +#define _write(f, buf, sz) (f->f_op->write(f, buf, sz, &f->f_pos))
1036 +
1037 +static void
1038 +zero_isoc_complete (struct usb_ep *ep, struct usb_request *req)
1039 +{
1040 +       struct zero_dev *dev = ep->driver_data;
1041 +       int             status = req->status;
1042 +       int i, j;
1043 +
1044 +       switch (status) {
1045 +
1046 +       case 0:                         /* normal completion? */
1047 +               //printk ("\nzero ---------------> isoc normal completion %d bytes\n", req->actual);
1048 +               for (i=0, j=rbuf_start; i<req->actual; i++) {
1049 +                       //printk ("%02x ", ((__u8*)req->buf)[i]);
1050 +                       rbuf[j] = ((__u8*)req->buf)[i];
1051 +                       j++;
1052 +                       if (j >= RBUF_LEN) j=0;
1053 +               }
1054 +               rbuf_start = j;
1055 +               //printk ("\n\n");
1056 +
1057 +               if (rbuf_len < RBUF_LEN) {
1058 +                       rbuf_len += req->actual;
1059 +                       if (rbuf_len > RBUF_LEN) {
1060 +                               rbuf_len = RBUF_LEN;
1061 +                       }
1062 +               }
1063 +
1064 +               break;
1065 +
1066 +       /* this endpoint is normally active while we're configured */
1067 +       case -ECONNABORTED:             /* hardware forced ep reset */
1068 +       case -ECONNRESET:               /* request dequeued */
1069 +       case -ESHUTDOWN:                /* disconnect from host */
1070 +               VDBG (dev, "%s gone (%d), %d/%d\n", ep->name, status,
1071 +                               req->actual, req->length);
1072 +               if (ep == dev->out_ep)
1073 +                       check_read_data (dev, ep, req);
1074 +               free_ep_req (ep, req);
1075 +               return;
1076 +
1077 +       case -EOVERFLOW:                /* buffer overrun on read means that
1078 +                                        * we didn't provide a big enough
1079 +                                        * buffer.
1080 +                                        */
1081 +       default:
1082 +#if 1
1083 +               DBG (dev, "%s complete --> %d, %d/%d\n", ep->name,
1084 +                               status, req->actual, req->length);
1085 +#endif
1086 +       case -EREMOTEIO:                /* short read */
1087 +               break;
1088 +       }
1089 +
1090 +       status = usb_ep_queue (ep, req, GFP_ATOMIC);
1091 +       if (status) {
1092 +               ERROR (dev, "kill %s:  resubmit %d bytes --> %d\n",
1093 +                               ep->name, req->length, status);
1094 +               usb_ep_set_halt (ep);
1095 +               /* FIXME recover later ... somehow */
1096 +       }
1097 +}
1098 +
1099 +static struct usb_request *
1100 +zero_start_isoc_ep (struct usb_ep *ep, int gfp_flags)
1101 +{
1102 +       struct usb_request      *req;
1103 +       int                     status;
1104 +
1105 +       req = alloc_ep_req (ep, 512);
1106 +       if (!req)
1107 +               return NULL;
1108 +
1109 +       req->complete = zero_isoc_complete;
1110 +
1111 +       status = usb_ep_queue (ep, req, gfp_flags);
1112 +       if (status) {
1113 +               struct zero_dev *dev = ep->driver_data;
1114 +
1115 +               ERROR (dev, "start %s --> %d\n", ep->name, status);
1116 +               free_ep_req (ep, req);
1117 +               req = NULL;
1118 +       }
1119 +
1120 +       return req;
1121 +}
1122 +
1123 +/* change our operational config.  this code must agree with the code
1124 + * that returns config descriptors, and altsetting code.
1125 + *
1126 + * it's also responsible for power management interactions. some
1127 + * configurations might not work with our current power sources.
1128 + *
1129 + * note that some device controller hardware will constrain what this
1130 + * code can do, perhaps by disallowing more than one configuration or
1131 + * by limiting configuration choices (like the pxa2xx).
1132 + */
1133 +static int
1134 +zero_set_config (struct zero_dev *dev, unsigned number, int gfp_flags)
1135 +{
1136 +       int                     result = 0;
1137 +       struct usb_gadget       *gadget = dev->gadget;
1138 +       const struct usb_endpoint_descriptor    *d;
1139 +       struct usb_ep           *ep;
1140 +
1141 +       if (number == dev->config)
1142 +               return 0;
1143 +
1144 +       zero_reset_config (dev);
1145 +
1146 +       gadget_for_each_ep (ep, gadget) {
1147 +
1148 +               if (strcmp (ep->name, "ep4") == 0) {
1149 +
1150 +                       d = (struct usb_endpoint_descripter *)&za_23; // isoc ep desc for audio i/f alt setting 6
1151 +                       result = usb_ep_enable (ep, d);
1152 +
1153 +                       if (result == 0) {
1154 +                               ep->driver_data = dev;
1155 +                               dev->in_ep = ep;
1156 +
1157 +                               if (zero_start_isoc_ep (ep, gfp_flags) != 0) {
1158 +
1159 +                                       dev->in_ep = ep;
1160 +                                       continue;
1161 +                               }
1162 +
1163 +                               usb_ep_disable (ep);
1164 +                               result = -EIO;
1165 +                       }
1166 +               }
1167 +
1168 +       }
1169 +
1170 +       dev->config = number;
1171 +       return result;
1172 +}
1173 +
1174 +/*-------------------------------------------------------------------------*/
1175 +
1176 +static void zero_setup_complete (struct usb_ep *ep, struct usb_request *req)
1177 +{
1178 +       if (req->status || req->actual != req->length)
1179 +               DBG ((struct zero_dev *) ep->driver_data,
1180 +                               "setup complete --> %d, %d/%d\n",
1181 +                               req->status, req->actual, req->length);
1182 +}
1183 +
1184 +/*
1185 + * The setup() callback implements all the ep0 functionality that's
1186 + * not handled lower down, in hardware or the hardware driver (like
1187 + * device and endpoint feature flags, and their status).  It's all
1188 + * housekeeping for the gadget function we're implementing.  Most of
1189 + * the work is in config-specific setup.
1190 + */
1191 +static int
1192 +zero_setup (struct usb_gadget *gadget, const struct usb_ctrlrequest *ctrl)
1193 +{
1194 +       struct zero_dev         *dev = get_gadget_data (gadget);
1195 +       struct usb_request      *req = dev->req;
1196 +       int                     value = -EOPNOTSUPP;
1197 +
1198 +       /* usually this stores reply data in the pre-allocated ep0 buffer,
1199 +        * but config change events will reconfigure hardware.
1200 +        */
1201 +       req->zero = 0;
1202 +       switch (ctrl->bRequest) {
1203 +
1204 +       case USB_REQ_GET_DESCRIPTOR:
1205 +
1206 +               switch (ctrl->wValue >> 8) {
1207 +
1208 +               case USB_DT_DEVICE:
1209 +                       value = min (ctrl->wLength, (u16) sizeof device_desc);
1210 +                       memcpy (req->buf, &device_desc, value);
1211 +                       break;
1212 +#ifdef CONFIG_USB_GADGET_DUALSPEED
1213 +               case USB_DT_DEVICE_QUALIFIER:
1214 +                       if (!gadget->is_dualspeed)
1215 +                               break;
1216 +                       value = min (ctrl->wLength, (u16) sizeof dev_qualifier);
1217 +                       memcpy (req->buf, &dev_qualifier, value);
1218 +                       break;
1219 +
1220 +               case USB_DT_OTHER_SPEED_CONFIG:
1221 +                       if (!gadget->is_dualspeed)
1222 +                               break;
1223 +                       // FALLTHROUGH
1224 +#endif /* CONFIG_USB_GADGET_DUALSPEED */
1225 +               case USB_DT_CONFIG:
1226 +                       value = config_buf (gadget, req->buf,
1227 +                                       ctrl->wValue >> 8,
1228 +                                       ctrl->wValue & 0xff);
1229 +                       if (value >= 0)
1230 +                               value = min (ctrl->wLength, (u16) value);
1231 +                       break;
1232 +
1233 +               case USB_DT_STRING:
1234 +                       /* wIndex == language code.
1235 +                        * this driver only handles one language, you can
1236 +                        * add string tables for other languages, using
1237 +                        * any UTF-8 characters
1238 +                        */
1239 +                       value = usb_gadget_get_string (&stringtab,
1240 +                                       ctrl->wValue & 0xff, req->buf);
1241 +                       if (value >= 0) {
1242 +                               value = min (ctrl->wLength, (u16) value);
1243 +                       }
1244 +                       break;
1245 +               }
1246 +               break;
1247 +
1248 +       /* currently two configs, two speeds */
1249 +       case USB_REQ_SET_CONFIGURATION:
1250 +               if (ctrl->bRequestType != 0)
1251 +                       goto unknown;
1252 +
1253 +               spin_lock (&dev->lock);
1254 +               value = zero_set_config (dev, ctrl->wValue, GFP_ATOMIC);
1255 +               spin_unlock (&dev->lock);
1256 +               break;
1257 +       case USB_REQ_GET_CONFIGURATION:
1258 +               if (ctrl->bRequestType != USB_DIR_IN)
1259 +                       goto unknown;
1260 +               *(u8 *)req->buf = dev->config;
1261 +               value = min (ctrl->wLength, (u16) 1);
1262 +               break;
1263 +
1264 +       /* until we add altsetting support, or other interfaces,
1265 +        * only 0/0 are possible.  pxa2xx only supports 0/0 (poorly)
1266 +        * and already killed pending endpoint I/O.
1267 +        */
1268 +       case USB_REQ_SET_INTERFACE:
1269 +
1270 +               if (ctrl->bRequestType != USB_RECIP_INTERFACE)
1271 +                       goto unknown;
1272 +               spin_lock (&dev->lock);
1273 +               if (dev->config) {
1274 +                       u8              config = dev->config;
1275 +
1276 +                       /* resets interface configuration, forgets about
1277 +                        * previous transaction state (queued bufs, etc)
1278 +                        * and re-inits endpoint state (toggle etc)
1279 +                        * no response queued, just zero status == success.
1280 +                        * if we had more than one interface we couldn't
1281 +                        * use this "reset the config" shortcut.
1282 +                        */
1283 +                       zero_reset_config (dev);
1284 +                       zero_set_config (dev, config, GFP_ATOMIC);
1285 +                       value = 0;
1286 +               }
1287 +               spin_unlock (&dev->lock);
1288 +               break;
1289 +       case USB_REQ_GET_INTERFACE:
1290 +               if ((ctrl->bRequestType == 0x21) && (ctrl->wIndex == 0x02)) {
1291 +                       value = ctrl->wLength;
1292 +                       break;
1293 +               }
1294 +               else {
1295 +                       if (ctrl->bRequestType != (USB_DIR_IN|USB_RECIP_INTERFACE))
1296 +                               goto unknown;
1297 +                       if (!dev->config)
1298 +                               break;
1299 +                       if (ctrl->wIndex != 0) {
1300 +                               value = -EDOM;
1301 +                               break;
1302 +                       }
1303 +                       *(u8 *)req->buf = 0;
1304 +                       value = min (ctrl->wLength, (u16) 1);
1305 +               }
1306 +               break;
1307 +
1308 +       /*
1309 +        * These are the same vendor-specific requests supported by
1310 +        * Intel's USB 2.0 compliance test devices.  We exceed that
1311 +        * device spec by allowing multiple-packet requests.
1312 +        */
1313 +       case 0x5b:      /* control WRITE test -- fill the buffer */
1314 +               if (ctrl->bRequestType != (USB_DIR_OUT|USB_TYPE_VENDOR))
1315 +                       goto unknown;
1316 +               if (ctrl->wValue || ctrl->wIndex)
1317 +                       break;
1318 +               /* just read that many bytes into the buffer */
1319 +               if (ctrl->wLength > USB_BUFSIZ)
1320 +                       break;
1321 +               value = ctrl->wLength;
1322 +               break;
1323 +       case 0x5c:      /* control READ test -- return the buffer */
1324 +               if (ctrl->bRequestType != (USB_DIR_IN|USB_TYPE_VENDOR))
1325 +                       goto unknown;
1326 +               if (ctrl->wValue || ctrl->wIndex)
1327 +                       break;
1328 +               /* expect those bytes are still in the buffer; send back */
1329 +               if (ctrl->wLength > USB_BUFSIZ
1330 +                               || ctrl->wLength != req->length)
1331 +                       break;
1332 +               value = ctrl->wLength;
1333 +               break;
1334 +
1335 +       case 0x01: // SET_CUR
1336 +       case 0x02:
1337 +       case 0x03:
1338 +       case 0x04:
1339 +       case 0x05:
1340 +               value = ctrl->wLength;
1341 +               break;
1342 +       case 0x81:
1343 +               switch (ctrl->wValue) {
1344 +               case 0x0201:
1345 +               case 0x0202:
1346 +                       ((u8*)req->buf)[0] = 0x00;
1347 +                       ((u8*)req->buf)[1] = 0xe3;
1348 +                       break;
1349 +               case 0x0300:
1350 +               case 0x0500:
1351 +                       ((u8*)req->buf)[0] = 0x00;
1352 +                       break;
1353 +               }
1354 +               //((u8*)req->buf)[0] = 0x81;
1355 +               //((u8*)req->buf)[1] = 0x81;
1356 +               value = ctrl->wLength;
1357 +               break;
1358 +       case 0x82:
1359 +               switch (ctrl->wValue) {
1360 +               case 0x0201:
1361 +               case 0x0202:
1362 +                       ((u8*)req->buf)[0] = 0x00;
1363 +                       ((u8*)req->buf)[1] = 0xc3;
1364 +                       break;
1365 +               case 0x0300:
1366 +               case 0x0500:
1367 +                       ((u8*)req->buf)[0] = 0x00;
1368 +                       break;
1369 +               }
1370 +               //((u8*)req->buf)[0] = 0x82;
1371 +               //((u8*)req->buf)[1] = 0x82;
1372 +               value = ctrl->wLength;
1373 +               break;
1374 +       case 0x83:
1375 +               switch (ctrl->wValue) {
1376 +               case 0x0201:
1377 +               case 0x0202:
1378 +                       ((u8*)req->buf)[0] = 0x00;
1379 +                       ((u8*)req->buf)[1] = 0x00;
1380 +                       break;
1381 +               case 0x0300:
1382 +                       ((u8*)req->buf)[0] = 0x60;
1383 +                       break;
1384 +               case 0x0500:
1385 +                       ((u8*)req->buf)[0] = 0x18;
1386 +                       break;
1387 +               }
1388 +               //((u8*)req->buf)[0] = 0x83;
1389 +               //((u8*)req->buf)[1] = 0x83;
1390 +               value = ctrl->wLength;
1391 +               break;
1392 +       case 0x84:
1393 +               switch (ctrl->wValue) {
1394 +               case 0x0201:
1395 +               case 0x0202:
1396 +                       ((u8*)req->buf)[0] = 0x00;
1397 +                       ((u8*)req->buf)[1] = 0x01;
1398 +                       break;
1399 +               case 0x0300:
1400 +               case 0x0500:
1401 +                       ((u8*)req->buf)[0] = 0x08;
1402 +                       break;
1403 +               }
1404 +               //((u8*)req->buf)[0] = 0x84;
1405 +               //((u8*)req->buf)[1] = 0x84;
1406 +               value = ctrl->wLength;
1407 +               break;
1408 +       case 0x85:
1409 +               ((u8*)req->buf)[0] = 0x85;
1410 +               ((u8*)req->buf)[1] = 0x85;
1411 +               value = ctrl->wLength;
1412 +               break;
1413 +
1414 +
1415 +       default:
1416 +unknown:
1417 +               printk("unknown control req%02x.%02x v%04x i%04x l%d\n",
1418 +                       ctrl->bRequestType, ctrl->bRequest,
1419 +                       ctrl->wValue, ctrl->wIndex, ctrl->wLength);
1420 +       }
1421 +
1422 +       /* respond with data transfer before status phase? */
1423 +       if (value >= 0) {
1424 +               req->length = value;
1425 +               req->zero = value < ctrl->wLength
1426 +                               && (value % gadget->ep0->maxpacket) == 0;
1427 +               value = usb_ep_queue (gadget->ep0, req, GFP_ATOMIC);
1428 +               if (value < 0) {
1429 +                       DBG (dev, "ep_queue < 0 --> %d\n", value);
1430 +                       req->status = 0;
1431 +                       zero_setup_complete (gadget->ep0, req);
1432 +               }
1433 +       }
1434 +
1435 +       /* device either stalls (value < 0) or reports success */
1436 +       return value;
1437 +}
1438 +
1439 +static void
1440 +zero_disconnect (struct usb_gadget *gadget)
1441 +{
1442 +       struct zero_dev         *dev = get_gadget_data (gadget);
1443 +       unsigned long           flags;
1444 +
1445 +       spin_lock_irqsave (&dev->lock, flags);
1446 +       zero_reset_config (dev);
1447 +
1448 +       /* a more significant application might have some non-usb
1449 +        * activities to quiesce here, saving resources like power
1450 +        * or pushing the notification up a network stack.
1451 +        */
1452 +       spin_unlock_irqrestore (&dev->lock, flags);
1453 +
1454 +       /* next we may get setup() calls to enumerate new connections;
1455 +        * or an unbind() during shutdown (including removing module).
1456 +        */
1457 +}
1458 +
1459 +static void
1460 +zero_autoresume (unsigned long _dev)
1461 +{
1462 +       struct zero_dev *dev = (struct zero_dev *) _dev;
1463 +       int             status;
1464 +
1465 +       /* normally the host would be woken up for something
1466 +        * more significant than just a timer firing...
1467 +        */
1468 +       if (dev->gadget->speed != USB_SPEED_UNKNOWN) {
1469 +               status = usb_gadget_wakeup (dev->gadget);
1470 +               DBG (dev, "wakeup --> %d\n", status);
1471 +       }
1472 +}
1473 +
1474 +/*-------------------------------------------------------------------------*/
1475 +
1476 +static void
1477 +zero_unbind (struct usb_gadget *gadget)
1478 +{
1479 +       struct zero_dev         *dev = get_gadget_data (gadget);
1480 +
1481 +       DBG (dev, "unbind\n");
1482 +
1483 +       /* we've already been disconnected ... no i/o is active */
1484 +       if (dev->req)
1485 +               free_ep_req (gadget->ep0, dev->req);
1486 +       del_timer_sync (&dev->resume);
1487 +       kfree (dev);
1488 +       set_gadget_data (gadget, NULL);
1489 +}
1490 +
1491 +static int
1492 +zero_bind (struct usb_gadget *gadget)
1493 +{
1494 +       struct zero_dev         *dev;
1495 +       //struct usb_ep         *ep;
1496 +
1497 +       printk("binding\n");
1498 +       /*
1499 +        * DRIVER POLICY CHOICE:  you may want to do this differently.
1500 +        * One thing to avoid is reusing a bcdDevice revision code
1501 +        * with different host-visible configurations or behavior
1502 +        * restrictions -- using ep1in/ep2out vs ep1out/ep3in, etc
1503 +        */
1504 +       //device_desc.bcdDevice = __constant_cpu_to_le16 (0x0201);
1505 +
1506 +
1507 +       /* ok, we made sense of the hardware ... */
1508 +       dev = kmalloc (sizeof *dev, SLAB_KERNEL);
1509 +       if (!dev)
1510 +               return -ENOMEM;
1511 +       memset (dev, 0, sizeof *dev);
1512 +       spin_lock_init (&dev->lock);
1513 +       dev->gadget = gadget;
1514 +       set_gadget_data (gadget, dev);
1515 +
1516 +       /* preallocate control response and buffer */
1517 +       dev->req = usb_ep_alloc_request (gadget->ep0, GFP_KERNEL);
1518 +       if (!dev->req)
1519 +               goto enomem;
1520 +       dev->req->buf = usb_ep_alloc_buffer (gadget->ep0, USB_BUFSIZ,
1521 +                               &dev->req->dma, GFP_KERNEL);
1522 +       if (!dev->req->buf)
1523 +               goto enomem;
1524 +
1525 +       dev->req->complete = zero_setup_complete;
1526 +
1527 +       device_desc.bMaxPacketSize0 = gadget->ep0->maxpacket;
1528 +
1529 +#ifdef CONFIG_USB_GADGET_DUALSPEED
1530 +       /* assume ep0 uses the same value for both speeds ... */
1531 +       dev_qualifier.bMaxPacketSize0 = device_desc.bMaxPacketSize0;
1532 +
1533 +       /* and that all endpoints are dual-speed */
1534 +       //hs_source_desc.bEndpointAddress = fs_source_desc.bEndpointAddress;
1535 +       //hs_sink_desc.bEndpointAddress = fs_sink_desc.bEndpointAddress;
1536 +#endif
1537 +
1538 +       usb_gadget_set_selfpowered (gadget);
1539 +
1540 +       init_timer (&dev->resume);
1541 +       dev->resume.function = zero_autoresume;
1542 +       dev->resume.data = (unsigned long) dev;
1543 +
1544 +       gadget->ep0->driver_data = dev;
1545 +
1546 +       INFO (dev, "%s, version: " DRIVER_VERSION "\n", longname);
1547 +       INFO (dev, "using %s, OUT %s IN %s\n", gadget->name,
1548 +               EP_OUT_NAME, EP_IN_NAME);
1549 +
1550 +       snprintf (manufacturer, sizeof manufacturer,
1551 +               UTS_SYSNAME " " UTS_RELEASE " with %s",
1552 +               gadget->name);
1553 +
1554 +       return 0;
1555 +
1556 +enomem:
1557 +       zero_unbind (gadget);
1558 +       return -ENOMEM;
1559 +}
1560 +
1561 +/*-------------------------------------------------------------------------*/
1562 +
1563 +static void
1564 +zero_suspend (struct usb_gadget *gadget)
1565 +{
1566 +       struct zero_dev         *dev = get_gadget_data (gadget);
1567 +
1568 +       if (gadget->speed == USB_SPEED_UNKNOWN)
1569 +               return;
1570 +
1571 +       if (autoresume) {
1572 +               mod_timer (&dev->resume, jiffies + (HZ * autoresume));
1573 +               DBG (dev, "suspend, wakeup in %d seconds\n", autoresume);
1574 +       } else
1575 +               DBG (dev, "suspend\n");
1576 +}
1577 +
1578 +static void
1579 +zero_resume (struct usb_gadget *gadget)
1580 +{
1581 +       struct zero_dev         *dev = get_gadget_data (gadget);
1582 +
1583 +       DBG (dev, "resume\n");
1584 +       del_timer (&dev->resume);
1585 +}
1586 +
1587 +
1588 +/*-------------------------------------------------------------------------*/
1589 +
1590 +static struct usb_gadget_driver zero_driver = {
1591 +#ifdef CONFIG_USB_GADGET_DUALSPEED
1592 +       .speed          = USB_SPEED_HIGH,
1593 +#else
1594 +       .speed          = USB_SPEED_FULL,
1595 +#endif
1596 +       .function       = (char *) longname,
1597 +       .bind           = zero_bind,
1598 +       .unbind         = zero_unbind,
1599 +
1600 +       .setup          = zero_setup,
1601 +       .disconnect     = zero_disconnect,
1602 +
1603 +       .suspend        = zero_suspend,
1604 +       .resume         = zero_resume,
1605 +
1606 +       .driver         = {
1607 +               .name           = (char *) shortname,
1608 +               // .shutdown = ...
1609 +               // .suspend = ...
1610 +               // .resume = ...
1611 +       },
1612 +};
1613 +
1614 +MODULE_AUTHOR ("David Brownell");
1615 +MODULE_LICENSE ("Dual BSD/GPL");
1616 +
1617 +static struct proc_dir_entry *pdir, *pfile;
1618 +
1619 +static int isoc_read_data (char *page, char **start,
1620 +                          off_t off, int count,
1621 +                          int *eof, void *data)
1622 +{
1623 +       int i;
1624 +       static int c = 0;
1625 +       static int done = 0;
1626 +       static int s = 0;
1627 +
1628 +/*
1629 +       printk ("\ncount: %d\n", count);
1630 +       printk ("rbuf_start: %d\n", rbuf_start);
1631 +       printk ("rbuf_len: %d\n", rbuf_len);
1632 +       printk ("off: %d\n", off);
1633 +       printk ("start: %p\n\n", *start);
1634 +*/
1635 +       if (done) {
1636 +               c = 0;
1637 +               done = 0;
1638 +               *eof = 1;
1639 +               return 0;
1640 +       }
1641 +
1642 +       if (c == 0) {
1643 +               if (rbuf_len == RBUF_LEN)
1644 +                       s = rbuf_start;
1645 +               else s = 0;
1646 +       }
1647 +
1648 +       for (i=0; i<count && c<rbuf_len; i++, c++) {
1649 +               page[i] = rbuf[(c+s) % RBUF_LEN];
1650 +       }
1651 +       *start = page;
1652 +
1653 +       if (c >= rbuf_len) {
1654 +               *eof = 1;
1655 +               done = 1;
1656 +       }
1657 +
1658 +
1659 +       return i;
1660 +}
1661 +
1662 +static int __init init (void)
1663 +{
1664 +
1665 +       int retval = 0;
1666 +
1667 +       pdir = proc_mkdir("isoc_test", NULL);
1668 +       if(pdir == NULL) {
1669 +               retval = -ENOMEM;
1670 +               printk("Error creating dir\n");
1671 +               goto done;
1672 +       }
1673 +       pdir->owner = THIS_MODULE;
1674 +
1675 +       pfile = create_proc_read_entry("isoc_data",
1676 +                                      0444, pdir,
1677 +                                      isoc_read_data,
1678 +                                      NULL);
1679 +       if (pfile == NULL) {
1680 +               retval = -ENOMEM;
1681 +               printk("Error creating file\n");
1682 +               goto no_file;
1683 +       }
1684 +       pfile->owner = THIS_MODULE;
1685 +
1686 +       return usb_gadget_register_driver (&zero_driver);
1687 +
1688 + no_file:
1689 +       remove_proc_entry("isoc_data", NULL);
1690 + done:
1691 +       return retval;
1692 +}
1693 +module_init (init);
1694 +
1695 +static void __exit cleanup (void)
1696 +{
1697 +
1698 +       usb_gadget_unregister_driver (&zero_driver);
1699 +
1700 +       remove_proc_entry("isoc_data", pdir);
1701 +       remove_proc_entry("isoc_test", NULL);
1702 +}
1703 +module_exit (cleanup);
1704 --- /dev/null
1705 +++ b/drivers/usb/dwc_otg/dwc_otg_attr.c
1706 @@ -0,0 +1,966 @@
1707 +/* ==========================================================================
1708 + * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_attr.c $
1709 + * $Revision: 1.2 $
1710 + * $Date: 2008-11-21 05:39:15 $
1711 + * $Change: 1064918 $
1712 + *
1713 + * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
1714 + * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
1715 + * otherwise expressly agreed to in writing between Synopsys and you.
1716 + *
1717 + * The Software IS NOT an item of Licensed Software or Licensed Product under
1718 + * any End User Software License Agreement or Agreement for Licensed Product
1719 + * with Synopsys or any supplement thereto. You are permitted to use and
1720 + * redistribute this Software in source and binary forms, with or without
1721 + * modification, provided that redistributions of source code must retain this
1722 + * notice. You may not view, use, disclose, copy or distribute this file or
1723 + * any information contained herein except pursuant to this license grant from
1724 + * Synopsys. If you do not agree with this notice, including the disclaimer
1725 + * below, then you are not authorized to use the Software.
1726 + *
1727 + * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
1728 + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
1729 + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
1730 + * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
1731 + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
1732 + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
1733 + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
1734 + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
1735 + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
1736 + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
1737 + * DAMAGE.
1738 + * ========================================================================== */
1739 +
1740 +/** @file
1741 + *
1742 + * The diagnostic interface will provide access to the controller for
1743 + * bringing up the hardware and testing.  The Linux driver attributes
1744 + * feature will be used to provide the Linux Diagnostic
1745 + * Interface. These attributes are accessed through sysfs.
1746 + */
1747 +
1748 +/** @page "Linux Module Attributes"
1749 + *
1750 + * The Linux module attributes feature is used to provide the Linux
1751 + * Diagnostic Interface.  These attributes are accessed through sysfs.
1752 + * The diagnostic interface will provide access to the controller for
1753 + * bringing up the hardware and testing.
1754 +
1755 +
1756 + The following table shows the attributes.
1757 + <table>
1758 + <tr>
1759 + <td><b> Name</b></td>
1760 + <td><b> Description</b></td>
1761 + <td><b> Access</b></td>
1762 + </tr>
1763 +
1764 + <tr>
1765 + <td> mode </td>
1766 + <td> Returns the current mode: 0 for device mode, 1 for host mode</td>
1767 + <td> Read</td>
1768 + </tr>
1769 +
1770 + <tr>
1771 + <td> hnpcapable </td>
1772 + <td> Gets or sets the "HNP-capable" bit in the Core USB Configuraton Register.
1773 + Read returns the current value.</td>
1774 + <td> Read/Write</td>
1775 + </tr>
1776 +
1777 + <tr>
1778 + <td> srpcapable </td>
1779 + <td> Gets or sets the "SRP-capable" bit in the Core USB Configuraton Register.
1780 + Read returns the current value.</td>
1781 + <td> Read/Write</td>
1782 + </tr>
1783 +
1784 + <tr>
1785 + <td> hnp </td>
1786 + <td> Initiates the Host Negotiation Protocol.  Read returns the status.</td>
1787 + <td> Read/Write</td>
1788 + </tr>
1789 +
1790 + <tr>
1791 + <td> srp </td>
1792 + <td> Initiates the Session Request Protocol.  Read returns the status.</td>
1793 + <td> Read/Write</td>
1794 + </tr>
1795 +
1796 + <tr>
1797 + <td> buspower </td>
1798 + <td> Gets or sets the Power State of the bus (0 - Off or 1 - On)</td>
1799 + <td> Read/Write</td>
1800 + </tr>
1801 +
1802 + <tr>
1803 + <td> bussuspend </td>
1804 + <td> Suspends the USB bus.</td>
1805 + <td> Read/Write</td>
1806 + </tr>
1807 +
1808 + <tr>
1809 + <td> busconnected </td>
1810 + <td> Gets the connection status of the bus</td>
1811 + <td> Read</td>
1812 + </tr>
1813 +
1814 + <tr>
1815 + <td> gotgctl </td>
1816 + <td> Gets or sets the Core Control Status Register.</td>
1817 + <td> Read/Write</td>
1818 + </tr>
1819 +
1820 + <tr>
1821 + <td> gusbcfg </td>
1822 + <td> Gets or sets the Core USB Configuration Register</td>
1823 + <td> Read/Write</td>
1824 + </tr>
1825 +
1826 + <tr>
1827 + <td> grxfsiz </td>
1828 + <td> Gets or sets the Receive FIFO Size Register</td>
1829 + <td> Read/Write</td>
1830 + </tr>
1831 +
1832 + <tr>
1833 + <td> gnptxfsiz </td>
1834 + <td> Gets or sets the non-periodic Transmit Size Register</td>
1835 + <td> Read/Write</td>
1836 + </tr>
1837 +
1838 + <tr>
1839 + <td> gpvndctl </td>
1840 + <td> Gets or sets the PHY Vendor Control Register</td>
1841 + <td> Read/Write</td>
1842 + </tr>
1843 +
1844 + <tr>
1845 + <td> ggpio </td>
1846 + <td> Gets the value in the lower 16-bits of the General Purpose IO Register
1847 + or sets the upper 16 bits.</td>
1848 + <td> Read/Write</td>
1849 + </tr>
1850 +
1851 + <tr>
1852 + <td> guid </td>
1853 + <td> Gets or sets the value of the User ID Register</td>
1854 + <td> Read/Write</td>
1855 + </tr>
1856 +
1857 + <tr>
1858 + <td> gsnpsid </td>
1859 + <td> Gets the value of the Synopsys ID Regester</td>
1860 + <td> Read</td>
1861 + </tr>
1862 +
1863 + <tr>
1864 + <td> devspeed </td>
1865 + <td> Gets or sets the device speed setting in the DCFG register</td>
1866 + <td> Read/Write</td>
1867 + </tr>
1868 +
1869 + <tr>
1870 + <td> enumspeed </td>
1871 + <td> Gets the device enumeration Speed.</td>
1872 + <td> Read</td>
1873 + </tr>
1874 +
1875 + <tr>
1876 + <td> hptxfsiz </td>
1877 + <td> Gets the value of the Host Periodic Transmit FIFO</td>
1878 + <td> Read</td>
1879 + </tr>
1880 +
1881 + <tr>
1882 + <td> hprt0 </td>
1883 + <td> Gets or sets the value in the Host Port Control and Status Register</td>
1884 + <td> Read/Write</td>
1885 + </tr>
1886 +
1887 + <tr>
1888 + <td> regoffset </td>
1889 + <td> Sets the register offset for the next Register Access</td>
1890 + <td> Read/Write</td>
1891 + </tr>
1892 +
1893 + <tr>
1894 + <td> regvalue </td>
1895 + <td> Gets or sets the value of the register at the offset in the regoffset attribute.</td>
1896 + <td> Read/Write</td>
1897 + </tr>
1898 +
1899 + <tr>
1900 + <td> remote_wakeup </td>
1901 + <td> On read, shows the status of Remote Wakeup. On write, initiates a remote
1902 + wakeup of the host. When bit 0 is 1 and Remote Wakeup is enabled, the Remote
1903 + Wakeup signalling bit in the Device Control Register is set for 1
1904 + milli-second.</td>
1905 + <td> Read/Write</td>
1906 + </tr>
1907 +
1908 + <tr>
1909 + <td> regdump </td>
1910 + <td> Dumps the contents of core registers.</td>
1911 + <td> Read</td>
1912 + </tr>
1913 +
1914 + <tr>
1915 + <td> spramdump </td>
1916 + <td> Dumps the contents of core registers.</td>
1917 + <td> Read</td>
1918 + </tr>
1919 +
1920 + <tr>
1921 + <td> hcddump </td>
1922 + <td> Dumps the current HCD state.</td>
1923 + <td> Read</td>
1924 + </tr>
1925 +
1926 + <tr>
1927 + <td> hcd_frrem </td>
1928 + <td> Shows the average value of the Frame Remaining
1929 + field in the Host Frame Number/Frame Remaining register when an SOF interrupt
1930 + occurs. This can be used to determine the average interrupt latency. Also
1931 + shows the average Frame Remaining value for start_transfer and the "a" and
1932 + "b" sample points. The "a" and "b" sample points may be used during debugging
1933 + bto determine how long it takes to execute a section of the HCD code.</td>
1934 + <td> Read</td>
1935 + </tr>
1936 +
1937 + <tr>
1938 + <td> rd_reg_test </td>
1939 + <td> Displays the time required to read the GNPTXFSIZ register many times
1940 + (the output shows the number of times the register is read).
1941 + <td> Read</td>
1942 + </tr>
1943 +
1944 + <tr>
1945 + <td> wr_reg_test </td>
1946 + <td> Displays the time required to write the GNPTXFSIZ register many times
1947 + (the output shows the number of times the register is written).
1948 + <td> Read</td>
1949 + </tr>
1950 +
1951 + </table>
1952 +
1953 + Example usage:
1954 + To get the current mode:
1955 + cat /sys/devices/lm0/mode
1956 +
1957 + To power down the USB:
1958 + echo 0 > /sys/devices/lm0/buspower
1959 + */
1960 +
1961 +#include <linux/kernel.h>
1962 +#include <linux/module.h>
1963 +#include <linux/moduleparam.h>
1964 +#include <linux/init.h>
1965 +#include <linux/device.h>
1966 +#include <linux/errno.h>
1967 +#include <linux/types.h>
1968 +#include <linux/stat.h>  /* permission constants */
1969 +#include <linux/version.h>
1970 +
1971 +#include <asm/io.h>
1972 +
1973 +#include "linux/dwc_otg_plat.h"
1974 +#include "dwc_otg_attr.h"
1975 +#include "dwc_otg_driver.h"
1976 +#include "dwc_otg_pcd.h"
1977 +#include "dwc_otg_hcd.h"
1978 +
1979 +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20)
1980 +/*
1981 + * MACROs for defining sysfs attribute
1982 + */
1983 +#define DWC_OTG_DEVICE_ATTR_BITFIELD_SHOW(_otg_attr_name_,_addr_,_mask_,_shift_,_string_) \
1984 +static ssize_t _otg_attr_name_##_show (struct device *_dev, struct device_attribute *attr, char *buf) \
1985 +{ \
1986 +       dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);              \
1987 +       uint32_t val; \
1988 +       val = dwc_read_reg32 (_addr_); \
1989 +       val = (val & (_mask_)) >> _shift_; \
1990 +       return sprintf (buf, "%s = 0x%x\n", _string_, val); \
1991 +}
1992 +#define DWC_OTG_DEVICE_ATTR_BITFIELD_STORE(_otg_attr_name_,_addr_,_mask_,_shift_,_string_) \
1993 +static ssize_t _otg_attr_name_##_store (struct device *_dev, struct device_attribute *attr, \
1994 +                                       const char *buf, size_t count) \
1995 +{ \
1996 +       dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev); \
1997 +       uint32_t set = simple_strtoul(buf, NULL, 16); \
1998 +       uint32_t clear = set; \
1999 +       clear = ((~clear) << _shift_) & _mask_; \
2000 +       set = (set << _shift_) & _mask_; \
2001 +       dev_dbg(_dev, "Storing Address=0x%08x Set=0x%08x Clear=0x%08x\n", (uint32_t)_addr_, set, clear); \
2002 +       dwc_modify_reg32(_addr_, clear, set); \
2003 +       return count; \
2004 +}
2005 +
2006 +/*
2007 + * MACROs for defining sysfs attribute for 32-bit registers
2008 + */
2009 +#define DWC_OTG_DEVICE_ATTR_REG_SHOW(_otg_attr_name_,_addr_,_string_) \
2010 +static ssize_t _otg_attr_name_##_show (struct device *_dev, struct device_attribute *attr, char *buf) \
2011 +{ \
2012 +       dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev); \
2013 +       uint32_t val; \
2014 +       val = dwc_read_reg32 (_addr_); \
2015 +       return sprintf (buf, "%s = 0x%08x\n", _string_, val); \
2016 +}
2017 +#define DWC_OTG_DEVICE_ATTR_REG_STORE(_otg_attr_name_,_addr_,_string_) \
2018 +static ssize_t _otg_attr_name_##_store (struct device *_dev, struct device_attribute *attr, \
2019 +                                       const char *buf, size_t count) \
2020 +{ \
2021 +       dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev); \
2022 +       uint32_t val = simple_strtoul(buf, NULL, 16); \
2023 +       dev_dbg(_dev, "Storing Address=0x%08x Val=0x%08x\n", (uint32_t)_addr_, val); \
2024 +       dwc_write_reg32(_addr_, val); \
2025 +       return count; \
2026 +}
2027 +
2028 +#else
2029 +
2030 +/*
2031 + * MACROs for defining sysfs attribute
2032 + */
2033 +#define DWC_OTG_DEVICE_ATTR_BITFIELD_SHOW(_otg_attr_name_,_addr_,_mask_,_shift_,_string_) \
2034 +static ssize_t _otg_attr_name_##_show (struct device *_dev, char *buf) \
2035 +{ \
2036 +       dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);\
2037 +       uint32_t val; \
2038 +       val = dwc_read_reg32 (_addr_); \
2039 +       val = (val & (_mask_)) >> _shift_; \
2040 +       return sprintf (buf, "%s = 0x%x\n", _string_, val); \
2041 +}
2042 +#define DWC_OTG_DEVICE_ATTR_BITFIELD_STORE(_otg_attr_name_,_addr_,_mask_,_shift_,_string_) \
2043 +static ssize_t _otg_attr_name_##_store (struct device *_dev, const char *buf, size_t count) \
2044 +{ \
2045 +       dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);\
2046 +       uint32_t set = simple_strtoul(buf, NULL, 16); \
2047 +       uint32_t clear = set; \
2048 +       clear = ((~clear) << _shift_) & _mask_; \
2049 +       set = (set << _shift_) & _mask_; \
2050 +       dev_dbg(_dev, "Storing Address=0x%08x Set=0x%08x Clear=0x%08x\n", (uint32_t)_addr_, set, clear); \
2051 +       dwc_modify_reg32(_addr_, clear, set); \
2052 +       return count; \
2053 +}
2054 +
2055 +/*
2056 + * MACROs for defining sysfs attribute for 32-bit registers
2057 + */
2058 +#define DWC_OTG_DEVICE_ATTR_REG_SHOW(_otg_attr_name_,_addr_,_string_) \
2059 +static ssize_t _otg_attr_name_##_show (struct device *_dev, char *buf) \
2060 +{ \
2061 +       dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);\
2062 +       uint32_t val; \
2063 +       val = dwc_read_reg32 (_addr_); \
2064 +       return sprintf (buf, "%s = 0x%08x\n", _string_, val); \
2065 +}
2066 +#define DWC_OTG_DEVICE_ATTR_REG_STORE(_otg_attr_name_,_addr_,_string_) \
2067 +static ssize_t _otg_attr_name_##_store (struct device *_dev, const char *buf, size_t count) \
2068 +{ \
2069 +       dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);\
2070 +       uint32_t val = simple_strtoul(buf, NULL, 16); \
2071 +       dev_dbg(_dev, "Storing Address=0x%08x Val=0x%08x\n", (uint32_t)_addr_, val); \
2072 +       dwc_write_reg32(_addr_, val); \
2073 +       return count; \
2074 +}
2075 +
2076 +#endif
2077 +
2078 +#define DWC_OTG_DEVICE_ATTR_BITFIELD_RW(_otg_attr_name_,_addr_,_mask_,_shift_,_string_) \
2079 +DWC_OTG_DEVICE_ATTR_BITFIELD_SHOW(_otg_attr_name_,_addr_,_mask_,_shift_,_string_) \
2080 +DWC_OTG_DEVICE_ATTR_BITFIELD_STORE(_otg_attr_name_,_addr_,_mask_,_shift_,_string_) \
2081 +DEVICE_ATTR(_otg_attr_name_,0644,_otg_attr_name_##_show,_otg_attr_name_##_store);
2082 +
2083 +#define DWC_OTG_DEVICE_ATTR_BITFIELD_RO(_otg_attr_name_,_addr_,_mask_,_shift_,_string_) \
2084 +DWC_OTG_DEVICE_ATTR_BITFIELD_SHOW(_otg_attr_name_,_addr_,_mask_,_shift_,_string_) \
2085 +DEVICE_ATTR(_otg_attr_name_,0444,_otg_attr_name_##_show,NULL);
2086 +
2087 +#define DWC_OTG_DEVICE_ATTR_REG32_RW(_otg_attr_name_,_addr_,_string_) \
2088 +DWC_OTG_DEVICE_ATTR_REG_SHOW(_otg_attr_name_,_addr_,_string_) \
2089 +DWC_OTG_DEVICE_ATTR_REG_STORE(_otg_attr_name_,_addr_,_string_) \
2090 +DEVICE_ATTR(_otg_attr_name_,0644,_otg_attr_name_##_show,_otg_attr_name_##_store);
2091 +
2092 +#define DWC_OTG_DEVICE_ATTR_REG32_RO(_otg_attr_name_,_addr_,_string_) \
2093 +DWC_OTG_DEVICE_ATTR_REG_SHOW(_otg_attr_name_,_addr_,_string_) \
2094 +DEVICE_ATTR(_otg_attr_name_,0444,_otg_attr_name_##_show,NULL);
2095 +
2096 +
2097 +/** @name Functions for Show/Store of Attributes */
2098 +/**@{*/
2099 +
2100 +/**
2101 + * Show the register offset of the Register Access.
2102 + */
2103 +static ssize_t regoffset_show( struct device *_dev,
2104 +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20)
2105 +                              struct device_attribute *attr,
2106 +#endif
2107 +                              char *buf)
2108 +{
2109 +       dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);
2110 +       return snprintf(buf, sizeof("0xFFFFFFFF\n")+1,"0x%08x\n", otg_dev->reg_offset);
2111 +}
2112 +
2113 +/**
2114 + * Set the register offset for the next Register Access        Read/Write
2115 + */
2116 +static ssize_t regoffset_store( struct device *_dev,
2117 +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20)
2118 +                               struct device_attribute *attr,
2119 +#endif
2120 +                               const char *buf,
2121 +                               size_t count )
2122 +{
2123 +       dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);
2124 +
2125 +       uint32_t offset = simple_strtoul(buf, NULL, 16);
2126 +       //dev_dbg(_dev, "Offset=0x%08x\n", offset);
2127 +       if (offset < 0x00040000 ) {
2128 +               otg_dev->reg_offset = offset;
2129 +       }
2130 +       else {
2131 +               dev_err( _dev, "invalid offset\n" );
2132 +       }
2133 +
2134 +       return count;
2135 +}
2136 +DEVICE_ATTR(regoffset, S_IRUGO|S_IWUSR, (void *)regoffset_show, regoffset_store);
2137 +
2138 +
2139 +/**
2140 + * Show the value of the register at the offset in the reg_offset
2141 + * attribute.
2142 + */
2143 +static ssize_t regvalue_show( struct device *_dev,
2144 +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20)
2145 +                             struct device_attribute *attr,
2146 +#endif
2147 +                             char *buf)
2148 +{
2149 +       dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);
2150 +
2151 +       uint32_t val;
2152 +       volatile uint32_t *addr;
2153 +
2154 +       if (otg_dev->reg_offset != 0xFFFFFFFF &&
2155 +           0 != otg_dev->base) {
2156 +               /* Calculate the address */
2157 +               addr = (uint32_t*)(otg_dev->reg_offset +
2158 +                                  (uint8_t*)otg_dev->base);
2159 +               //dev_dbg(_dev, "@0x%08x\n", (unsigned)addr);
2160 +               val = dwc_read_reg32( addr );
2161 +               return snprintf(buf, sizeof("Reg@0xFFFFFFFF = 0xFFFFFFFF\n")+1,
2162 +                               "Reg@0x%06x = 0x%08x\n",
2163 +                               otg_dev->reg_offset, val);
2164 +       }
2165 +       else {
2166 +               dev_err(_dev, "Invalid offset (0x%0x)\n",
2167 +                       otg_dev->reg_offset);
2168 +               return sprintf(buf, "invalid offset\n" );
2169 +       }
2170 +}
2171 +
2172 +/**
2173 + * Store the value in the register at the offset in the reg_offset
2174 + * attribute.
2175 + *
2176 + */
2177 +static ssize_t regvalue_store( struct device *_dev,
2178 +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20)
2179 +                              struct device_attribute *attr,
2180 +#endif
2181 +                              const char *buf,
2182 +                              size_t count )
2183 +{
2184 +       dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);
2185 +
2186 +       volatile uint32_t * addr;
2187 +       uint32_t val = simple_strtoul(buf, NULL, 16);
2188 +       //dev_dbg(_dev, "Offset=0x%08x Val=0x%08x\n", otg_dev->reg_offset, val);
2189 +       if (otg_dev->reg_offset != 0xFFFFFFFF && 0 != otg_dev->base) {
2190 +               /* Calculate the address */
2191 +               addr = (uint32_t*)(otg_dev->reg_offset +
2192 +                                  (uint8_t*)otg_dev->base);
2193 +               //dev_dbg(_dev, "@0x%08x\n", (unsigned)addr);
2194 +               dwc_write_reg32( addr, val );
2195 +       }
2196 +       else {
2197 +               dev_err(_dev, "Invalid Register Offset (0x%08x)\n",
2198 +                       otg_dev->reg_offset);
2199 +       }
2200 +       return count;
2201 +}
2202 +DEVICE_ATTR(regvalue,  S_IRUGO|S_IWUSR, regvalue_show, regvalue_store);
2203 +
2204 +/*
2205 + * Attributes
2206 + */
2207 +DWC_OTG_DEVICE_ATTR_BITFIELD_RO(mode,&(otg_dev->core_if->core_global_regs->gotgctl),(1<<20),20,"Mode");
2208 +DWC_OTG_DEVICE_ATTR_BITFIELD_RW(hnpcapable,&(otg_dev->core_if->core_global_regs->gusbcfg),(1<<9),9,"Mode");
2209 +DWC_OTG_DEVICE_ATTR_BITFIELD_RW(srpcapable,&(otg_dev->core_if->core_global_regs->gusbcfg),(1<<8),8,"Mode");
2210 +
2211 +//DWC_OTG_DEVICE_ATTR_BITFIELD_RW(buspower,&(otg_dev->core_if->core_global_regs->gotgctl),(1<<8),8,"Mode");
2212 +//DWC_OTG_DEVICE_ATTR_BITFIELD_RW(bussuspend,&(otg_dev->core_if->core_global_regs->gotgctl),(1<<8),8,"Mode");
2213 +DWC_OTG_DEVICE_ATTR_BITFIELD_RO(busconnected,otg_dev->core_if->host_if->hprt0,0x01,0,"Bus Connected");
2214 +
2215 +DWC_OTG_DEVICE_ATTR_REG32_RW(gotgctl,&(otg_dev->core_if->core_global_regs->gotgctl),"GOTGCTL");
2216 +DWC_OTG_DEVICE_ATTR_REG32_RW(gusbcfg,&(otg_dev->core_if->core_global_regs->gusbcfg),"GUSBCFG");
2217 +DWC_OTG_DEVICE_ATTR_REG32_RW(grxfsiz,&(otg_dev->core_if->core_global_regs->grxfsiz),"GRXFSIZ");
2218 +DWC_OTG_DEVICE_ATTR_REG32_RW(gnptxfsiz,&(otg_dev->core_if->core_global_regs->gnptxfsiz),"GNPTXFSIZ");
2219 +DWC_OTG_DEVICE_ATTR_REG32_RW(gpvndctl,&(otg_dev->core_if->core_global_regs->gpvndctl),"GPVNDCTL");
2220 +DWC_OTG_DEVICE_ATTR_REG32_RW(ggpio,&(otg_dev->core_if->core_global_regs->ggpio),"GGPIO");
2221 +DWC_OTG_DEVICE_ATTR_REG32_RW(guid,&(otg_dev->core_if->core_global_regs->guid),"GUID");
2222 +DWC_OTG_DEVICE_ATTR_REG32_RO(gsnpsid,&(otg_dev->core_if->core_global_regs->gsnpsid),"GSNPSID");
2223 +DWC_OTG_DEVICE_ATTR_BITFIELD_RW(devspeed,&(otg_dev->core_if->dev_if->dev_global_regs->dcfg),0x3,0,"Device Speed");
2224 +DWC_OTG_DEVICE_ATTR_BITFIELD_RO(enumspeed,&(otg_dev->core_if->dev_if->dev_global_regs->dsts),0x6,1,"Device Enumeration Speed");
2225 +
2226 +DWC_OTG_DEVICE_ATTR_REG32_RO(hptxfsiz,&(otg_dev->core_if->core_global_regs->hptxfsiz),"HPTXFSIZ");
2227 +DWC_OTG_DEVICE_ATTR_REG32_RW(hprt0,otg_dev->core_if->host_if->hprt0,"HPRT0");
2228 +
2229 +
2230 +/**
2231 + * @todo Add code to initiate the HNP.
2232 + */
2233 +/**
2234 + * Show the HNP status bit
2235 + */
2236 +static ssize_t hnp_show( struct device *_dev,
2237 +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20)
2238 +                        struct device_attribute *attr,
2239 +#endif
2240 +                        char *buf)
2241 +{
2242 +       dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);
2243 +
2244 +       gotgctl_data_t val;
2245 +       val.d32 = dwc_read_reg32 (&(otg_dev->core_if->core_global_regs->gotgctl));
2246 +       return sprintf (buf, "HstNegScs = 0x%x\n", val.b.hstnegscs);
2247 +}
2248 +
2249 +/**
2250 + * Set the HNP Request bit
2251 + */
2252 +static ssize_t hnp_store( struct device *_dev,
2253 +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20)
2254 +                         struct device_attribute *attr,
2255 +#endif
2256 +                         const char *buf,
2257 +                         size_t count )
2258 +{
2259 +       dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);
2260 +
2261 +       uint32_t in = simple_strtoul(buf, NULL, 16);
2262 +       uint32_t *addr = (uint32_t *)&(otg_dev->core_if->core_global_regs->gotgctl);
2263 +       gotgctl_data_t mem;
2264 +       mem.d32 = dwc_read_reg32(addr);
2265 +       mem.b.hnpreq = in;
2266 +       dev_dbg(_dev, "Storing Address=0x%08x Data=0x%08x\n", (uint32_t)addr, mem.d32);
2267 +       dwc_write_reg32(addr, mem.d32);
2268 +       return count;
2269 +}
2270 +DEVICE_ATTR(hnp, 0644, hnp_show, hnp_store);
2271 +
2272 +/**
2273 + * @todo Add code to initiate the SRP.
2274 + */
2275 +/**
2276 + * Show the SRP status bit
2277 + */
2278 +static ssize_t srp_show( struct device *_dev,
2279 +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20)
2280 +                        struct device_attribute *attr,
2281 +#endif
2282 +                        char *buf)
2283 +{
2284 +#ifndef DWC_HOST_ONLY
2285 +       dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);
2286 +
2287 +       gotgctl_data_t val;
2288 +       val.d32 = dwc_read_reg32 (&(otg_dev->core_if->core_global_regs->gotgctl));
2289 +       return sprintf (buf, "SesReqScs = 0x%x\n", val.b.sesreqscs);
2290 +#else
2291 +       return sprintf(buf, "Host Only Mode!\n");
2292 +#endif
2293 +}
2294 +
2295 +
2296 +
2297 +/**
2298 + * Set the SRP Request bit
2299 + */
2300 +static ssize_t srp_store( struct device *_dev,
2301 +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20)
2302 +                         struct device_attribute *attr,
2303 +#endif
2304 +                         const char *buf,
2305 +                         size_t count )
2306 +{
2307 +#ifndef DWC_HOST_ONLY
2308 +       dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);
2309 +
2310 +       dwc_otg_pcd_initiate_srp(otg_dev->pcd);
2311 +#endif
2312 +       return count;
2313 +}
2314 +DEVICE_ATTR(srp, 0644, srp_show, srp_store);
2315 +
2316 +/**
2317 + * @todo Need to do more for power on/off?
2318 + */
2319 +/**
2320 + * Show the Bus Power status
2321 + */
2322 +static ssize_t buspower_show( struct device *_dev,
2323 +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20)
2324 +                             struct device_attribute *attr,
2325 +#endif
2326 +                             char *buf)
2327 +{
2328 +       dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);
2329 +
2330 +       hprt0_data_t val;
2331 +       val.d32 = dwc_read_reg32 (otg_dev->core_if->host_if->hprt0);
2332 +       return sprintf (buf, "Bus Power = 0x%x\n", val.b.prtpwr);
2333 +}
2334 +
2335 +
2336 +/**
2337 + * Set the Bus Power status
2338 + */
2339 +static ssize_t buspower_store( struct device *_dev,
2340 +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20)
2341 +                              struct device_attribute *attr,
2342 +#endif
2343 +                              const char *buf,
2344 +                              size_t count )
2345 +{
2346 +       dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);
2347 +
2348 +       uint32_t on = simple_strtoul(buf, NULL, 16);
2349 +       uint32_t *addr = (uint32_t *)otg_dev->core_if->host_if->hprt0;
2350 +       hprt0_data_t mem;
2351 +
2352 +       mem.d32 = dwc_read_reg32(addr);
2353 +       mem.b.prtpwr = on;
2354 +
2355 +       //dev_dbg(_dev, "Storing Address=0x%08x Data=0x%08x\n", (uint32_t)addr, mem.d32);
2356 +       dwc_write_reg32(addr, mem.d32);
2357 +
2358 +       return count;
2359 +}
2360 +DEVICE_ATTR(buspower, 0644, buspower_show, buspower_store);
2361 +
2362 +/**
2363 + * @todo Need to do more for suspend?
2364 + */
2365 +/**
2366 + * Show the Bus Suspend status
2367 + */
2368 +static ssize_t bussuspend_show( struct device *_dev,
2369 +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20)
2370 +                               struct device_attribute *attr,
2371 +#endif
2372 +                               char *buf)
2373 +{
2374 +       dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);
2375 +
2376 +       hprt0_data_t val;
2377 +       val.d32 = dwc_read_reg32 (otg_dev->core_if->host_if->hprt0);
2378 +       return sprintf (buf, "Bus Suspend = 0x%x\n", val.b.prtsusp);
2379 +}
2380 +
2381 +/**
2382 + * Set the Bus Suspend status
2383 + */
2384 +static ssize_t bussuspend_store( struct device *_dev,
2385 +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20)
2386 +                                struct device_attribute *attr,
2387 +#endif
2388 +                                const char *buf,
2389 +                                size_t count )
2390 +{
2391 +       dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);
2392 +
2393 +       uint32_t in = simple_strtoul(buf, NULL, 16);
2394 +       uint32_t *addr = (uint32_t *)otg_dev->core_if->host_if->hprt0;
2395 +       hprt0_data_t mem;
2396 +       mem.d32 = dwc_read_reg32(addr);
2397 +       mem.b.prtsusp = in;
2398 +       dev_dbg(_dev, "Storing Address=0x%08x Data=0x%08x\n", (uint32_t)addr, mem.d32);
2399 +       dwc_write_reg32(addr, mem.d32);
2400 +       return count;
2401 +}
2402 +DEVICE_ATTR(bussuspend, 0644, bussuspend_show, bussuspend_store);
2403 +
2404 +/**
2405 + * Show the status of Remote Wakeup.
2406 + */
2407 +static ssize_t remote_wakeup_show( struct device *_dev,
2408 +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20)
2409 +                                  struct device_attribute *attr,
2410 +#endif
2411 +                                  char *buf)
2412 +{
2413 +#ifndef DWC_HOST_ONLY
2414 +       dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);
2415 +
2416 +       dctl_data_t val;
2417 +       val.d32 =
2418 +               dwc_read_reg32( &otg_dev->core_if->dev_if->dev_global_regs->dctl);
2419 +       return sprintf( buf, "Remote Wakeup = %d Enabled = %d\n",
2420 +                       val.b.rmtwkupsig, otg_dev->pcd->remote_wakeup_enable);
2421 +#else
2422 +       return sprintf(buf, "Host Only Mode!\n");
2423 +#endif
2424 +}
2425 +/**
2426 + * Initiate a remote wakeup of the host.  The Device control register
2427 + * Remote Wakeup Signal bit is written if the PCD Remote wakeup enable
2428 + * flag is set.
2429 + *
2430 + */
2431 +static ssize_t remote_wakeup_store( struct device *_dev,
2432 +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20)
2433 +                                   struct device_attribute *attr,
2434 +#endif
2435 +                                   const char *buf,
2436 +                                   size_t count )
2437 +{
2438 +#ifndef DWC_HOST_ONLY
2439 +       dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);
2440 +
2441 +       uint32_t val = simple_strtoul(buf, NULL, 16);
2442 +       if (val&1) {
2443 +               dwc_otg_pcd_remote_wakeup(otg_dev->pcd, 1);
2444 +       }
2445 +       else {
2446 +               dwc_otg_pcd_remote_wakeup(otg_dev->pcd, 0);
2447 +       }
2448 +#endif
2449 +       return count;
2450 +}
2451 +DEVICE_ATTR(remote_wakeup,  S_IRUGO|S_IWUSR, remote_wakeup_show,
2452 +           remote_wakeup_store);
2453 +
2454 +/**
2455 + * Dump global registers and either host or device registers (depending on the
2456 + * current mode of the core).
2457 + */
2458 +static ssize_t regdump_show( struct device *_dev,
2459 +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20)
2460 +                            struct device_attribute *attr,
2461 +#endif
2462 +                            char *buf)
2463 +{
2464 +       dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);
2465 +
2466 +        dwc_otg_dump_global_registers( otg_dev->core_if);
2467 +        if (dwc_otg_is_host_mode(otg_dev->core_if)) {
2468 +                dwc_otg_dump_host_registers( otg_dev->core_if);
2469 +        } else {
2470 +                dwc_otg_dump_dev_registers( otg_dev->core_if);
2471 +
2472 +        }
2473 +       return sprintf( buf, "Register Dump\n" );
2474 +}
2475 +
2476 +DEVICE_ATTR(regdump, S_IRUGO|S_IWUSR, regdump_show, 0);
2477 +
2478 +/**
2479 + * Dump global registers and either host or device registers (depending on the
2480 + * current mode of the core).
2481 + */
2482 +static ssize_t spramdump_show( struct device *_dev,
2483 +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20)
2484 +                              struct device_attribute *attr,
2485 +#endif
2486 +                              char *buf)
2487 +{
2488 +       dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);
2489 +
2490 +        dwc_otg_dump_spram( otg_dev->core_if);
2491 +
2492 +        return sprintf( buf, "SPRAM Dump\n" );
2493 +}
2494 +
2495 +DEVICE_ATTR(spramdump, S_IRUGO|S_IWUSR, spramdump_show, 0);
2496 +
2497 +/**
2498 + * Dump the current hcd state.
2499 + */
2500 +static ssize_t hcddump_show( struct device *_dev,
2501 +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20)
2502 +                            struct device_attribute *attr,
2503 +#endif
2504 +                            char *buf)
2505 +{
2506 +#ifndef DWC_DEVICE_ONLY
2507 +       dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);
2508 +
2509 +       dwc_otg_hcd_dump_state(otg_dev->hcd);
2510 +#endif
2511 +       return sprintf( buf, "HCD Dump\n" );
2512 +}
2513 +
2514 +DEVICE_ATTR(hcddump, S_IRUGO|S_IWUSR, hcddump_show, 0);
2515 +
2516 +/**
2517 + * Dump the average frame remaining at SOF. This can be used to
2518 + * determine average interrupt latency. Frame remaining is also shown for
2519 + * start transfer and two additional sample points.
2520 + */
2521 +static ssize_t hcd_frrem_show( struct device *_dev,
2522 +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20)
2523 +                              struct device_attribute *attr,
2524 +#endif
2525 +                              char *buf)
2526 +{
2527 +#ifndef DWC_DEVICE_ONLY
2528 +       dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);
2529 +
2530 +       dwc_otg_hcd_dump_frrem(otg_dev->hcd);
2531 +#endif
2532 +       return sprintf( buf, "HCD Dump Frame Remaining\n" );
2533 +}
2534 +
2535 +DEVICE_ATTR(hcd_frrem, S_IRUGO|S_IWUSR, hcd_frrem_show, 0);
2536 +
2537 +/**
2538 + * Displays the time required to read the GNPTXFSIZ register many times (the
2539 + * output shows the number of times the register is read).
2540 + */
2541 +#define RW_REG_COUNT 10000000
2542 +#define MSEC_PER_JIFFIE 1000/HZ
2543 +static ssize_t rd_reg_test_show( struct device *_dev,
2544 +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20)
2545 +                                struct device_attribute *attr,
2546 +#endif
2547 +                                char *buf)
2548 +{
2549 +       dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);
2550 +
2551 +       int i;
2552 +       int time;
2553 +       int start_jiffies;
2554 +
2555 +       printk("HZ %d, MSEC_PER_JIFFIE %d, loops_per_jiffy %lu\n",
2556 +              HZ, MSEC_PER_JIFFIE, loops_per_jiffy);
2557 +       start_jiffies = jiffies;
2558 +       for (i = 0; i < RW_REG_COUNT; i++) {
2559 +               dwc_read_reg32(&otg_dev->core_if->core_global_regs->gnptxfsiz);
2560 +       }
2561 +       time = jiffies - start_jiffies;
2562 +       return sprintf( buf, "Time to read GNPTXFSIZ reg %d times: %d msecs (%d jiffies)\n",
2563 +                       RW_REG_COUNT, time * MSEC_PER_JIFFIE, time );
2564 +}
2565 +
2566 +DEVICE_ATTR(rd_reg_test, S_IRUGO|S_IWUSR, rd_reg_test_show, 0);
2567 +
2568 +/**
2569 + * Displays the time required to write the GNPTXFSIZ register many times (the
2570 + * output shows the number of times the register is written).
2571 + */
2572 +static ssize_t wr_reg_test_show( struct device *_dev,
2573 +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20)
2574 +                                struct device_attribute *attr,
2575 +#endif
2576 +                                char *buf)
2577 +{
2578 +       dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);
2579 +
2580 +       uint32_t reg_val;
2581 +       int i;
2582 +       int time;
2583 +       int start_jiffies;
2584 +
2585 +       printk("HZ %d, MSEC_PER_JIFFIE %d, loops_per_jiffy %lu\n",
2586 +              HZ, MSEC_PER_JIFFIE, loops_per_jiffy);
2587 +       reg_val = dwc_read_reg32(&otg_dev->core_if->core_global_regs->gnptxfsiz);
2588 +       start_jiffies = jiffies;
2589 +       for (i = 0; i < RW_REG_COUNT; i++) {
2590 +               dwc_write_reg32(&otg_dev->core_if->core_global_regs->gnptxfsiz, reg_val);
2591 +       }
2592 +       time = jiffies - start_jiffies;
2593 +       return sprintf( buf, "Time to write GNPTXFSIZ reg %d times: %d msecs (%d jiffies)\n",
2594 +                       RW_REG_COUNT, time * MSEC_PER_JIFFIE, time);
2595 +}
2596 +
2597 +DEVICE_ATTR(wr_reg_test, S_IRUGO|S_IWUSR, wr_reg_test_show, 0);
2598 +/**@}*/
2599 +
2600 +/**
2601 + * Create the device files
2602 + */
2603 +void dwc_otg_attr_create (struct device *dev)
2604 +{
2605 +       int error;
2606 +
2607 +       error = device_create_file(dev, &dev_attr_regoffset);
2608 +       error = device_create_file(dev, &dev_attr_regvalue);
2609 +       error = device_create_file(dev, &dev_attr_mode);
2610 +       error = device_create_file(dev, &dev_attr_hnpcapable);
2611 +       error = device_create_file(dev, &dev_attr_srpcapable);
2612 +       error = device_create_file(dev, &dev_attr_hnp);
2613 +       error = device_create_file(dev, &dev_attr_srp);
2614 +       error = device_create_file(dev, &dev_attr_buspower);
2615 +       error = device_create_file(dev, &dev_attr_bussuspend);
2616 +       error = device_create_file(dev, &dev_attr_busconnected);
2617 +       error = device_create_file(dev, &dev_attr_gotgctl);
2618 +       error = device_create_file(dev, &dev_attr_gusbcfg);
2619 +       error = device_create_file(dev, &dev_attr_grxfsiz);
2620 +       error = device_create_file(dev, &dev_attr_gnptxfsiz);
2621 +       error = device_create_file(dev, &dev_attr_gpvndctl);
2622 +       error = device_create_file(dev, &dev_attr_ggpio);
2623 +       error = device_create_file(dev, &dev_attr_guid);
2624 +       error = device_create_file(dev, &dev_attr_gsnpsid);
2625 +       error = device_create_file(dev, &dev_attr_devspeed);
2626 +       error = device_create_file(dev, &dev_attr_enumspeed);
2627 +       error = device_create_file(dev, &dev_attr_hptxfsiz);
2628 +       error = device_create_file(dev, &dev_attr_hprt0);
2629 +       error = device_create_file(dev, &dev_attr_remote_wakeup);
2630 +       error = device_create_file(dev, &dev_attr_regdump);
2631 +       error = device_create_file(dev, &dev_attr_spramdump);
2632 +       error = device_create_file(dev, &dev_attr_hcddump);
2633 +       error = device_create_file(dev, &dev_attr_hcd_frrem);
2634 +       error = device_create_file(dev, &dev_attr_rd_reg_test);
2635 +       error = device_create_file(dev, &dev_attr_wr_reg_test);
2636 +}
2637 +
2638 +/**
2639 + * Remove the device files
2640 + */
2641 +void dwc_otg_attr_remove (struct device *dev)
2642 +{
2643 +       device_remove_file(dev, &dev_attr_regoffset);
2644 +       device_remove_file(dev, &dev_attr_regvalue);
2645 +       device_remove_file(dev, &dev_attr_mode);
2646 +       device_remove_file(dev, &dev_attr_hnpcapable);
2647 +       device_remove_file(dev, &dev_attr_srpcapable);
2648 +       device_remove_file(dev, &dev_attr_hnp);
2649 +       device_remove_file(dev, &dev_attr_srp);
2650 +       device_remove_file(dev, &dev_attr_buspower);
2651 +       device_remove_file(dev, &dev_attr_bussuspend);
2652 +       device_remove_file(dev, &dev_attr_busconnected);
2653 +       device_remove_file(dev, &dev_attr_gotgctl);
2654 +       device_remove_file(dev, &dev_attr_gusbcfg);
2655 +       device_remove_file(dev, &dev_attr_grxfsiz);
2656 +       device_remove_file(dev, &dev_attr_gnptxfsiz);
2657 +       device_remove_file(dev, &dev_attr_gpvndctl);
2658 +       device_remove_file(dev, &dev_attr_ggpio);
2659 +       device_remove_file(dev, &dev_attr_guid);
2660 +       device_remove_file(dev, &dev_attr_gsnpsid);
2661 +       device_remove_file(dev, &dev_attr_devspeed);
2662 +       device_remove_file(dev, &dev_attr_enumspeed);
2663 +       device_remove_file(dev, &dev_attr_hptxfsiz);
2664 +       device_remove_file(dev, &dev_attr_hprt0);
2665 +       device_remove_file(dev, &dev_attr_remote_wakeup);
2666 +       device_remove_file(dev, &dev_attr_regdump);
2667 +       device_remove_file(dev, &dev_attr_spramdump);
2668 +       device_remove_file(dev, &dev_attr_hcddump);
2669 +       device_remove_file(dev, &dev_attr_hcd_frrem);
2670 +       device_remove_file(dev, &dev_attr_rd_reg_test);
2671 +       device_remove_file(dev, &dev_attr_wr_reg_test);
2672 +}
2673 --- /dev/null
2674 +++ b/drivers/usb/dwc_otg/dwc_otg_attr.h
2675 @@ -0,0 +1,67 @@
2676 +/* ==========================================================================
2677 + * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_attr.h $
2678 + * $Revision: 1.2 $
2679 + * $Date: 2008-11-21 05:39:15 $
2680 + * $Change: 477051 $
2681 + *
2682 + * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
2683 + * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
2684 + * otherwise expressly agreed to in writing between Synopsys and you.
2685 + *
2686 + * The Software IS NOT an item of Licensed Software or Licensed Product under
2687 + * any End User Software License Agreement or Agreement for Licensed Product
2688 + * with Synopsys or any supplement thereto. You are permitted to use and
2689 + * redistribute this Software in source and binary forms, with or without
2690 + * modification, provided that redistributions of source code must retain this
2691 + * notice. You may not view, use, disclose, copy or distribute this file or
2692 + * any information contained herein except pursuant to this license grant from
2693 + * Synopsys. If you do not agree with this notice, including the disclaimer
2694 + * below, then you are not authorized to use the Software.
2695 + *
2696 + * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
2697 + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
2698 + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
2699 + * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
2700 + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
2701 + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
2702 + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
2703 + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
2704 + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
2705 + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
2706 + * DAMAGE.
2707 + * ========================================================================== */
2708 +
2709 +#if !defined(__DWC_OTG_ATTR_H__)
2710 +#define __DWC_OTG_ATTR_H__
2711 +
2712 +/** @file
2713 + * This file contains the interface to the Linux device attributes.
2714 + */
2715 +extern struct device_attribute dev_attr_regoffset;
2716 +extern struct device_attribute dev_attr_regvalue;
2717 +
2718 +extern struct device_attribute dev_attr_mode;
2719 +extern struct device_attribute dev_attr_hnpcapable;
2720 +extern struct device_attribute dev_attr_srpcapable;
2721 +extern struct device_attribute dev_attr_hnp;
2722 +extern struct device_attribute dev_attr_srp;
2723 +extern struct device_attribute dev_attr_buspower;
2724 +extern struct device_attribute dev_attr_bussuspend;
2725 +extern struct device_attribute dev_attr_busconnected;
2726 +extern struct device_attribute dev_attr_gotgctl;
2727 +extern struct device_attribute dev_attr_gusbcfg;
2728 +extern struct device_attribute dev_attr_grxfsiz;
2729 +extern struct device_attribute dev_attr_gnptxfsiz;
2730 +extern struct device_attribute dev_attr_gpvndctl;
2731 +extern struct device_attribute dev_attr_ggpio;
2732 +extern struct device_attribute dev_attr_guid;
2733 +extern struct device_attribute dev_attr_gsnpsid;
2734 +extern struct device_attribute dev_attr_devspeed;
2735 +extern struct device_attribute dev_attr_enumspeed;
2736 +extern struct device_attribute dev_attr_hptxfsiz;
2737 +extern struct device_attribute dev_attr_hprt0;
2738 +
2739 +void dwc_otg_attr_create (struct device *dev);
2740 +void dwc_otg_attr_remove (struct device *dev);
2741 +
2742 +#endif
2743 --- /dev/null
2744 +++ b/drivers/usb/dwc_otg/dwc_otg_cil.c
2745 @@ -0,0 +1,3692 @@
2746 +/* ==========================================================================
2747 + * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_cil.c $
2748 + * $Revision: 1.7 $
2749 + * $Date: 2008-12-22 11:43:05 $
2750 + * $Change: 1117667 $
2751 + *
2752 + * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
2753 + * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
2754 + * otherwise expressly agreed to in writing between Synopsys and you.
2755 + *
2756 + * The Software IS NOT an item of Licensed Software or Licensed Product under
2757 + * any End User Software License Agreement or Agreement for Licensed Product
2758 + * with Synopsys or any supplement thereto. You are permitted to use and
2759 + * redistribute this Software in source and binary forms, with or without
2760 + * modification, provided that redistributions of source code must retain this
2761 + * notice. You may not view, use, disclose, copy or distribute this file or
2762 + * any information contained herein except pursuant to this license grant from
2763 + * Synopsys. If you do not agree with this notice, including the disclaimer
2764 + * below, then you are not authorized to use the Software.
2765 + *
2766 + * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
2767 + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
2768 + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
2769 + * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
2770 + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
2771 + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
2772 + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
2773 + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
2774 + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
2775 + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
2776 + * DAMAGE.
2777 + * ========================================================================== */
2778 +
2779 +/** @file
2780 + *
2781 + * The Core Interface Layer provides basic services for accessing and
2782 + * managing the DWC_otg hardware. These services are used by both the
2783 + * Host Controller Driver and the Peripheral Controller Driver.
2784 + *
2785 + * The CIL manages the memory map for the core so that the HCD and PCD
2786 + * don't have to do this separately. It also handles basic tasks like
2787 + * reading/writing the registers and data FIFOs in the controller.
2788 + * Some of the data access functions provide encapsulation of several
2789 + * operations required to perform a task, such as writing multiple
2790 + * registers to start a transfer. Finally, the CIL performs basic
2791 + * services that are not specific to either the host or device modes
2792 + * of operation. These services include management of the OTG Host
2793 + * Negotiation Protocol (HNP) and Session Request Protocol (SRP). A
2794 + * Diagnostic API is also provided to allow testing of the controller
2795 + * hardware.
2796 + *
2797 + * The Core Interface Layer has the following requirements:
2798 + * - Provides basic controller operations.
2799 + * - Minimal use of OS services.
2800 + * - The OS services used will be abstracted by using inline functions
2801 + *      or macros.
2802 + *
2803 + */
2804 +#include <asm/unaligned.h>
2805 +#include <linux/dma-mapping.h>
2806 +#ifdef DEBUG
2807 +#include <linux/jiffies.h>
2808 +#endif
2809 +
2810 +#include "linux/dwc_otg_plat.h"
2811 +#include "dwc_otg_regs.h"
2812 +#include "dwc_otg_cil.h"
2813 +
2814 +/* Included only to access hc->qh for non-dword buffer handling
2815 + * TODO: account it
2816 + */
2817 +#include "dwc_otg_hcd.h"
2818 +
2819 +/**
2820 + * This function is called to initialize the DWC_otg CSR data
2821 + * structures. The register addresses in the device and host
2822 + * structures are initialized from the base address supplied by the
2823 + * caller.     The calling function must make the OS calls to get the
2824 + * base address of the DWC_otg controller registers.  The core_params
2825 + * argument holds the parameters that specify how the core should be
2826 + * configured.
2827 + *
2828 + * @param[in] reg_base_addr Base address of DWC_otg core registers
2829 + * @param[in] core_params Pointer to the core configuration parameters
2830 + *
2831 + */
2832 +dwc_otg_core_if_t *dwc_otg_cil_init(const uint32_t *reg_base_addr,
2833 +                                       dwc_otg_core_params_t *core_params)
2834 +{
2835 +       dwc_otg_core_if_t *core_if = 0;
2836 +       dwc_otg_dev_if_t *dev_if = 0;
2837 +       dwc_otg_host_if_t *host_if = 0;
2838 +       uint8_t *reg_base = (uint8_t *)reg_base_addr;
2839 +       int i = 0;
2840 +
2841 +       DWC_DEBUGPL(DBG_CILV, "%s(%p,%p)\n", __func__, reg_base_addr, core_params);
2842 +
2843 +       core_if = kmalloc(sizeof(dwc_otg_core_if_t), GFP_KERNEL);
2844 +
2845 +       if (core_if == 0) {
2846 +               DWC_DEBUGPL(DBG_CIL, "Allocation of dwc_otg_core_if_t failed\n");
2847 +               return 0;
2848 +       }
2849 +
2850 +       memset(core_if, 0, sizeof(dwc_otg_core_if_t));
2851 +
2852 +       core_if->core_params = core_params;
2853 +       core_if->core_global_regs = (dwc_otg_core_global_regs_t *)reg_base;
2854 +
2855 +       /*
2856 +        * Allocate the Device Mode structures.
2857 +        */
2858 +       dev_if = kmalloc(sizeof(dwc_otg_dev_if_t), GFP_KERNEL);
2859 +
2860 +       if (dev_if == 0) {
2861 +               DWC_DEBUGPL(DBG_CIL, "Allocation of dwc_otg_dev_if_t failed\n");
2862 +               kfree(core_if);
2863 +               return 0;
2864 +       }
2865 +
2866 +       dev_if->dev_global_regs =
2867 +                       (dwc_otg_device_global_regs_t *)(reg_base + DWC_DEV_GLOBAL_REG_OFFSET);
2868 +
2869 +       for (i=0; i<MAX_EPS_CHANNELS; i++)
2870 +       {
2871 +               dev_if->in_ep_regs[i] = (dwc_otg_dev_in_ep_regs_t *)
2872 +                               (reg_base + DWC_DEV_IN_EP_REG_OFFSET +
2873 +                                (i * DWC_EP_REG_OFFSET));
2874 +
2875 +               dev_if->out_ep_regs[i] = (dwc_otg_dev_out_ep_regs_t *)
2876 +                               (reg_base + DWC_DEV_OUT_EP_REG_OFFSET +
2877 +                                (i * DWC_EP_REG_OFFSET));
2878 +               DWC_DEBUGPL(DBG_CILV, "in_ep_regs[%d]->diepctl=%p\n",
2879 +                                       i, &dev_if->in_ep_regs[i]->diepctl);
2880 +               DWC_DEBUGPL(DBG_CILV, "out_ep_regs[%d]->doepctl=%p\n",
2881 +                                       i, &dev_if->out_ep_regs[i]->doepctl);
2882 +       }
2883 +
2884 +       dev_if->speed = 0; // unknown
2885 +
2886 +       core_if->dev_if = dev_if;
2887 +
2888 +       /*
2889 +        * Allocate the Host Mode structures.
2890 +        */
2891 +       host_if = kmalloc(sizeof(dwc_otg_host_if_t), GFP_KERNEL);
2892 +
2893 +       if (host_if == 0) {
2894 +               DWC_DEBUGPL(DBG_CIL, "Allocation of dwc_otg_host_if_t failed\n");
2895 +               kfree(dev_if);
2896 +               kfree(core_if);
2897 +               return 0;
2898 +       }
2899 +
2900 +       host_if->host_global_regs = (dwc_otg_host_global_regs_t *)
2901 +                       (reg_base + DWC_OTG_HOST_GLOBAL_REG_OFFSET);
2902 +
2903 +       host_if->hprt0 = (uint32_t*)(reg_base + DWC_OTG_HOST_PORT_REGS_OFFSET);
2904 +
2905 +       for (i=0; i<MAX_EPS_CHANNELS; i++)
2906 +       {
2907 +               host_if->hc_regs[i] = (dwc_otg_hc_regs_t *)
2908 +                               (reg_base + DWC_OTG_HOST_CHAN_REGS_OFFSET +
2909 +                                (i * DWC_OTG_CHAN_REGS_OFFSET));
2910 +               DWC_DEBUGPL(DBG_CILV, "hc_reg[%d]->hcchar=%p\n",
2911 +                                       i, &host_if->hc_regs[i]->hcchar);
2912 +       }
2913 +
2914 +       host_if->num_host_channels = MAX_EPS_CHANNELS;
2915 +       core_if->host_if = host_if;
2916 +
2917 +       for (i=0; i<MAX_EPS_CHANNELS; i++)
2918 +       {
2919 +               core_if->data_fifo[i] =
2920 +                               (uint32_t *)(reg_base + DWC_OTG_DATA_FIFO_OFFSET +
2921 +                                                        (i * DWC_OTG_DATA_FIFO_SIZE));
2922 +               DWC_DEBUGPL(DBG_CILV, "data_fifo[%d]=0x%08x\n",
2923 +                                       i, (unsigned)core_if->data_fifo[i]);
2924 +       }
2925 +
2926 +       core_if->pcgcctl = (uint32_t*)(reg_base + DWC_OTG_PCGCCTL_OFFSET);
2927 +
2928 +       /*
2929 +        * Store the contents of the hardware configuration registers here for
2930 +        * easy access later.
2931 +        */
2932 +       core_if->hwcfg1.d32 = dwc_read_reg32(&core_if->core_global_regs->ghwcfg1);
2933 +       core_if->hwcfg2.d32 = dwc_read_reg32(&core_if->core_global_regs->ghwcfg2);
2934 +       core_if->hwcfg3.d32 = dwc_read_reg32(&core_if->core_global_regs->ghwcfg3);
2935 +       core_if->hwcfg4.d32 = dwc_read_reg32(&core_if->core_global_regs->ghwcfg4);
2936 +
2937 +       DWC_DEBUGPL(DBG_CILV,"hwcfg1=%08x\n",core_if->hwcfg1.d32);
2938 +       DWC_DEBUGPL(DBG_CILV,"hwcfg2=%08x\n",core_if->hwcfg2.d32);
2939 +       DWC_DEBUGPL(DBG_CILV,"hwcfg3=%08x\n",core_if->hwcfg3.d32);
2940 +       DWC_DEBUGPL(DBG_CILV,"hwcfg4=%08x\n",core_if->hwcfg4.d32);
2941 +
2942 +       core_if->hcfg.d32 = dwc_read_reg32(&core_if->host_if->host_global_regs->hcfg);
2943 +       core_if->dcfg.d32 = dwc_read_reg32(&core_if->dev_if->dev_global_regs->dcfg);
2944 +
2945 +       DWC_DEBUGPL(DBG_CILV,"hcfg=%08x\n",core_if->hcfg.d32);
2946 +       DWC_DEBUGPL(DBG_CILV,"dcfg=%08x\n",core_if->dcfg.d32);
2947 +
2948 +       DWC_DEBUGPL(DBG_CILV,"op_mode=%0x\n",core_if->hwcfg2.b.op_mode);
2949 +       DWC_DEBUGPL(DBG_CILV,"arch=%0x\n",core_if->hwcfg2.b.architecture);
2950 +       DWC_DEBUGPL(DBG_CILV,"num_dev_ep=%d\n",core_if->hwcfg2.b.num_dev_ep);
2951 +       DWC_DEBUGPL(DBG_CILV,"num_host_chan=%d\n",core_if->hwcfg2.b.num_host_chan);
2952 +       DWC_DEBUGPL(DBG_CILV,"nonperio_tx_q_depth=0x%0x\n",core_if->hwcfg2.b.nonperio_tx_q_depth);
2953 +       DWC_DEBUGPL(DBG_CILV,"host_perio_tx_q_depth=0x%0x\n",core_if->hwcfg2.b.host_perio_tx_q_depth);
2954 +       DWC_DEBUGPL(DBG_CILV,"dev_token_q_depth=0x%0x\n",core_if->hwcfg2.b.dev_token_q_depth);
2955 +
2956 +       DWC_DEBUGPL(DBG_CILV,"Total FIFO SZ=%d\n", core_if->hwcfg3.b.dfifo_depth);
2957 +       DWC_DEBUGPL(DBG_CILV,"xfer_size_cntr_width=%0x\n", core_if->hwcfg3.b.xfer_size_cntr_width);
2958 +
2959 +       /*
2960 +        * Set the SRP sucess bit for FS-I2c
2961 +        */
2962 +       core_if->srp_success = 0;
2963 +       core_if->srp_timer_started = 0;
2964 +
2965 +
2966 +       /*
2967 +        * Create new workqueue and init works
2968 +        */
2969 +       core_if->wq_otg = create_singlethread_workqueue("dwc_otg");
2970 +       if(core_if->wq_otg == 0) {
2971 +               DWC_DEBUGPL(DBG_CIL, "Creation of wq_otg failed\n");
2972 +               kfree(host_if);
2973 +               kfree(dev_if);
2974 +               kfree(core_if);
2975 +               return 0 * HZ;
2976 +       }
2977 +
2978 +
2979 +
2980 +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,20)
2981 +
2982 +       INIT_WORK(&core_if->w_conn_id, w_conn_id_status_change, core_if);
2983 +       INIT_WORK(&core_if->w_wkp, w_wakeup_detected, core_if);
2984 +
2985 +#else
2986 +
2987 +       INIT_WORK(&core_if->w_conn_id, w_conn_id_status_change);
2988 +       INIT_DELAYED_WORK(&core_if->w_wkp, w_wakeup_detected);
2989 +
2990 +#endif
2991 +       return core_if;
2992 +}
2993 +
2994 +/**
2995 + * This function frees the structures allocated by dwc_otg_cil_init().
2996 + *
2997 + * @param[in] core_if The core interface pointer returned from
2998 + * dwc_otg_cil_init().
2999 + *
3000 + */
3001 +void dwc_otg_cil_remove(dwc_otg_core_if_t *core_if)
3002 +{
3003 +       /* Disable all interrupts */
3004 +       dwc_modify_reg32(&core_if->core_global_regs->gahbcfg, 1, 0);
3005 +       dwc_write_reg32(&core_if->core_global_regs->gintmsk, 0);
3006 +
3007 +       if (core_if->wq_otg) {
3008 +               destroy_workqueue(core_if->wq_otg);
3009 +       }
3010 +       if (core_if->dev_if) {
3011 +               kfree(core_if->dev_if);
3012 +       }
3013 +       if (core_if->host_if) {
3014 +               kfree(core_if->host_if);
3015 +       }
3016 +       kfree(core_if);
3017 +}
3018 +
3019 +/**
3020 + * This function enables the controller's Global Interrupt in the AHB Config
3021 + * register.
3022 + *
3023 + * @param[in] core_if Programming view of DWC_otg controller.
3024 + */
3025 +void dwc_otg_enable_global_interrupts(dwc_otg_core_if_t *core_if)
3026 +{
3027 +       gahbcfg_data_t ahbcfg = { .d32 = 0};
3028 +       ahbcfg.b.glblintrmsk = 1; /* Enable interrupts */
3029 +       dwc_modify_reg32(&core_if->core_global_regs->gahbcfg, 0, ahbcfg.d32);
3030 +}
3031 +
3032 +/**
3033 + * This function disables the controller's Global Interrupt in the AHB Config
3034 + * register.
3035 + *
3036 + * @param[in] core_if Programming view of DWC_otg controller.
3037 + */
3038 +void dwc_otg_disable_global_interrupts(dwc_otg_core_if_t *core_if)
3039 +{
3040 +       gahbcfg_data_t ahbcfg = { .d32 = 0};
3041 +       ahbcfg.b.glblintrmsk = 1; /* Enable interrupts */
3042 +       dwc_modify_reg32(&core_if->core_global_regs->gahbcfg, ahbcfg.d32, 0);
3043 +}
3044 +
3045 +/**
3046 + * This function initializes the commmon interrupts, used in both
3047 + * device and host modes.
3048 + *
3049 + * @param[in] core_if Programming view of the DWC_otg controller
3050 + *
3051 + */
3052 +static void dwc_otg_enable_common_interrupts(dwc_otg_core_if_t *core_if)
3053 +{
3054 +       dwc_otg_core_global_regs_t *global_regs =
3055 +                       core_if->core_global_regs;
3056 +       gintmsk_data_t intr_mask = { .d32 = 0};
3057 +
3058 +       /* Clear any pending OTG Interrupts */
3059 +       dwc_write_reg32(&global_regs->gotgint, 0xFFFFFFFF);
3060 +
3061 +       /* Clear any pending interrupts */
3062 +       dwc_write_reg32(&global_regs->gintsts, 0xFFFFFFFF);
3063 +
3064 +       /*
3065 +        * Enable the interrupts in the GINTMSK.
3066 +        */
3067 +       intr_mask.b.modemismatch = 1;
3068 +       intr_mask.b.otgintr = 1;
3069 +
3070 +       if (!core_if->dma_enable) {
3071 +               intr_mask.b.rxstsqlvl = 1;
3072 +       }
3073 +
3074 +       intr_mask.b.conidstschng = 1;
3075 +       intr_mask.b.wkupintr = 1;
3076 +       intr_mask.b.disconnect = 1;
3077 +       intr_mask.b.usbsuspend = 1;
3078 +       intr_mask.b.sessreqintr = 1;
3079 +       dwc_write_reg32(&global_regs->gintmsk, intr_mask.d32);
3080 +}
3081 +
3082 +/**
3083 + * Initializes the FSLSPClkSel field of the HCFG register depending on the PHY
3084 + * type.
3085 + */
3086 +static void init_fslspclksel(dwc_otg_core_if_t *core_if)
3087 +{
3088 +       uint32_t        val;
3089 +       hcfg_data_t             hcfg;
3090 +
3091 +       if (((core_if->hwcfg2.b.hs_phy_type == 2) &&
3092 +                (core_if->hwcfg2.b.fs_phy_type == 1) &&
3093 +                (core_if->core_params->ulpi_fs_ls)) ||
3094 +               (core_if->core_params->phy_type == DWC_PHY_TYPE_PARAM_FS)) {
3095 +               /* Full speed PHY */
3096 +               val = DWC_HCFG_48_MHZ;
3097 +       }
3098 +       else {
3099 +               /* High speed PHY running at full speed or high speed */
3100 +               val = DWC_HCFG_30_60_MHZ;
3101 +       }
3102 +
3103 +       DWC_DEBUGPL(DBG_CIL, "Initializing HCFG.FSLSPClkSel to 0x%1x\n", val);
3104 +       hcfg.d32 = dwc_read_reg32(&core_if->host_if->host_global_regs->hcfg);
3105 +       hcfg.b.fslspclksel = val;
3106 +       dwc_write_reg32(&core_if->host_if->host_global_regs->hcfg, hcfg.d32);
3107 +}
3108 +
3109 +/**
3110 + * Initializes the DevSpd field of the DCFG register depending on the PHY type
3111 + * and the enumeration speed of the device.
3112 + */
3113 +static void init_devspd(dwc_otg_core_if_t *core_if)
3114 +{
3115 +       uint32_t        val;
3116 +       dcfg_data_t             dcfg;
3117 +
3118 +       if (((core_if->hwcfg2.b.hs_phy_type == 2) &&
3119 +                (core_if->hwcfg2.b.fs_phy_type == 1) &&
3120 +                (core_if->core_params->ulpi_fs_ls)) ||
3121 +               (core_if->core_params->phy_type == DWC_PHY_TYPE_PARAM_FS)) {
3122 +               /* Full speed PHY */
3123 +               val = 0x3;
3124 +       }
3125 +       else if (core_if->core_params->speed == DWC_SPEED_PARAM_FULL) {
3126 +               /* High speed PHY running at full speed */
3127 +               val = 0x1;
3128 +       }
3129 +       else {
3130 +               /* High speed PHY running at high speed */
3131 +               val = 0x0;
3132 +       }
3133 +
3134 +       DWC_DEBUGPL(DBG_CIL, "Initializing DCFG.DevSpd to 0x%1x\n", val);
3135 +
3136 +       dcfg.d32 = dwc_read_reg32(&core_if->dev_if->dev_global_regs->dcfg);
3137 +       dcfg.b.devspd = val;
3138 +       dwc_write_reg32(&core_if->dev_if->dev_global_regs->dcfg, dcfg.d32);
3139 +}
3140 +
3141 +/**
3142 + * This function calculates the number of IN EPS
3143 + * using GHWCFG1 and GHWCFG2 registers values
3144 + *
3145 + * @param core_if Programming view of the DWC_otg controller
3146 + */
3147 +static uint32_t calc_num_in_eps(dwc_otg_core_if_t *core_if)
3148 +{
3149 +       uint32_t num_in_eps = 0;
3150 +       uint32_t num_eps = core_if->hwcfg2.b.num_dev_ep;
3151 +       uint32_t hwcfg1 = core_if->hwcfg1.d32 >> 3;
3152 +       uint32_t num_tx_fifos = core_if->hwcfg4.b.num_in_eps;
3153 +       int i;
3154 +
3155 +
3156 +       for(i = 0; i < num_eps; ++i)
3157 +       {
3158 +               if(!(hwcfg1 & 0x1))
3159 +                       num_in_eps++;
3160 +
3161 +               hwcfg1 >>= 2;
3162 +       }
3163 +
3164 +       if(core_if->hwcfg4.b.ded_fifo_en) {
3165 +               num_in_eps = (num_in_eps > num_tx_fifos) ? num_tx_fifos : num_in_eps;
3166 +       }
3167 +
3168 +       return num_in_eps;
3169 +}
3170 +
3171 +
3172 +/**
3173 + * This function calculates the number of OUT EPS
3174 + * using GHWCFG1 and GHWCFG2 registers values
3175 + *
3176 + * @param core_if Programming view of the DWC_otg controller
3177 + */
3178 +static uint32_t calc_num_out_eps(dwc_otg_core_if_t *core_if)
3179 +{
3180 +       uint32_t num_out_eps = 0;
3181 +       uint32_t num_eps = core_if->hwcfg2.b.num_dev_ep;
3182 +       uint32_t hwcfg1 = core_if->hwcfg1.d32 >> 2;
3183 +       int i;
3184 +
3185 +       for(i = 0; i < num_eps; ++i)
3186 +       {
3187 +               if(!(hwcfg1 & 0x2))
3188 +                       num_out_eps++;
3189 +
3190 +               hwcfg1 >>= 2;
3191 +       }
3192 +       return num_out_eps;
3193 +}
3194 +/**
3195 + * This function initializes the DWC_otg controller registers and
3196 + * prepares the core for device mode or host mode operation.
3197 + *
3198 + * @param core_if Programming view of the DWC_otg controller
3199 + *
3200 + */
3201 +void dwc_otg_core_init(dwc_otg_core_if_t *core_if)
3202 +{
3203 +       int i = 0;
3204 +       dwc_otg_core_global_regs_t *global_regs =
3205 +                       core_if->core_global_regs;
3206 +       dwc_otg_dev_if_t *dev_if = core_if->dev_if;
3207 +       gahbcfg_data_t ahbcfg = { .d32 = 0 };
3208 +       gusbcfg_data_t usbcfg = { .d32 = 0 };
3209 +       gi2cctl_data_t i2cctl = { .d32 = 0 };
3210 +
3211 +       DWC_DEBUGPL(DBG_CILV, "dwc_otg_core_init(%p)\n", core_if);
3212 +
3213 +       /* Common Initialization */
3214 +
3215 +       usbcfg.d32 = dwc_read_reg32(&global_regs->gusbcfg);
3216 +
3217 +//     usbcfg.b.tx_end_delay = 1;
3218 +       /* Program the ULPI External VBUS bit if needed */
3219 +       usbcfg.b.ulpi_ext_vbus_drv =
3220 +               (core_if->core_params->phy_ulpi_ext_vbus == DWC_PHY_ULPI_EXTERNAL_VBUS) ? 1 : 0;
3221 +
3222 +       /* Set external TS Dline pulsing */
3223 +       usbcfg.b.term_sel_dl_pulse = (core_if->core_params->ts_dline == 1) ? 1 : 0;
3224 +       dwc_write_reg32 (&global_regs->gusbcfg, usbcfg.d32);
3225 +
3226 +
3227 +       /* Reset the Controller */
3228 +       dwc_otg_core_reset(core_if);
3229 +
3230 +       /* Initialize parameters from Hardware configuration registers. */
3231 +       dev_if->num_in_eps = calc_num_in_eps(core_if);
3232 +       dev_if->num_out_eps = calc_num_out_eps(core_if);
3233 +
3234 +
3235 +       DWC_DEBUGPL(DBG_CIL, "num_dev_perio_in_ep=%d\n", core_if->hwcfg4.b.num_dev_perio_in_ep);
3236 +
3237 +       for (i=0; i < core_if->hwcfg4.b.num_dev_perio_in_ep; i++)
3238 +       {
3239 +               dev_if->perio_tx_fifo_size[i] =
3240 +                       dwc_read_reg32(&global_regs->dptxfsiz_dieptxf[i]) >> 16;
3241 +               DWC_DEBUGPL(DBG_CIL, "Periodic Tx FIFO SZ #%d=0x%0x\n",
3242 +                               i, dev_if->perio_tx_fifo_size[i]);
3243 +       }
3244 +
3245 +       for (i=0; i < core_if->hwcfg4.b.num_in_eps; i++)
3246 +       {
3247 +               dev_if->tx_fifo_size[i] =
3248 +                       dwc_read_reg32(&global_regs->dptxfsiz_dieptxf[i]) >> 16;
3249 +               DWC_DEBUGPL(DBG_CIL, "Tx FIFO SZ #%d=0x%0x\n",
3250 +                       i, dev_if->perio_tx_fifo_size[i]);
3251 +       }
3252 +
3253 +       core_if->total_fifo_size = core_if->hwcfg3.b.dfifo_depth;
3254 +       core_if->rx_fifo_size =
3255 +                       dwc_read_reg32(&global_regs->grxfsiz);
3256 +       core_if->nperio_tx_fifo_size =
3257 +                       dwc_read_reg32(&global_regs->gnptxfsiz) >> 16;
3258 +
3259 +       DWC_DEBUGPL(DBG_CIL, "Total FIFO SZ=%d\n", core_if->total_fifo_size);
3260 +       DWC_DEBUGPL(DBG_CIL, "Rx FIFO SZ=%d\n", core_if->rx_fifo_size);
3261 +       DWC_DEBUGPL(DBG_CIL, "NP Tx FIFO SZ=%d\n", core_if->nperio_tx_fifo_size);
3262 +
3263 +       /* This programming sequence needs to happen in FS mode before any other
3264 +        * programming occurs */
3265 +       if ((core_if->core_params->speed == DWC_SPEED_PARAM_FULL) &&
3266 +               (core_if->core_params->phy_type == DWC_PHY_TYPE_PARAM_FS)) {
3267 +                       /* If FS mode with FS PHY */
3268 +
3269 +                       /* core_init() is now called on every switch so only call the
3270 +                        * following for the first time through. */
3271 +                       if (!core_if->phy_init_done) {
3272 +                               core_if->phy_init_done = 1;
3273 +                               DWC_DEBUGPL(DBG_CIL, "FS_PHY detected\n");
3274 +                               usbcfg.d32 = dwc_read_reg32(&global_regs->gusbcfg);
3275 +                               usbcfg.b.physel = 1;
3276 +                               dwc_write_reg32 (&global_regs->gusbcfg, usbcfg.d32);
3277 +
3278 +                               /* Reset after a PHY select */
3279 +                               dwc_otg_core_reset(core_if);
3280 +                       }
3281 +
3282 +                       /* Program DCFG.DevSpd or HCFG.FSLSPclkSel to 48Mhz in FS.      Also
3283 +                        * do this on HNP Dev/Host mode switches (done in dev_init and
3284 +                        * host_init). */
3285 +                       if (dwc_otg_is_host_mode(core_if)) {
3286 +                               init_fslspclksel(core_if);
3287 +                       }
3288 +                       else {
3289 +                               init_devspd(core_if);
3290 +                       }
3291 +
3292 +                       if (core_if->core_params->i2c_enable) {
3293 +                               DWC_DEBUGPL(DBG_CIL, "FS_PHY Enabling I2c\n");
3294 +                               /* Program GUSBCFG.OtgUtmifsSel to I2C */
3295 +                               usbcfg.d32 = dwc_read_reg32(&global_regs->gusbcfg);
3296 +                               usbcfg.b.otgutmifssel = 1;
3297 +                               dwc_write_reg32 (&global_regs->gusbcfg, usbcfg.d32);
3298 +
3299 +                               /* Program GI2CCTL.I2CEn */
3300 +                               i2cctl.d32 = dwc_read_reg32(&global_regs->gi2cctl);
3301 +                               i2cctl.b.i2cdevaddr = 1;
3302 +                               i2cctl.b.i2cen = 0;
3303 +                               dwc_write_reg32 (&global_regs->gi2cctl, i2cctl.d32);
3304 +                               i2cctl.b.i2cen = 1;
3305 +                               dwc_write_reg32 (&global_regs->gi2cctl, i2cctl.d32);
3306 +                       }
3307 +
3308 +               } /* endif speed == DWC_SPEED_PARAM_FULL */
3309 +
3310 +               else {
3311 +                       /* High speed PHY. */
3312 +                       if (!core_if->phy_init_done) {
3313 +                               core_if->phy_init_done = 1;
3314 +                               /* HS PHY parameters.  These parameters are preserved
3315 +                                * during soft reset so only program the first time.  Do
3316 +                                * a soft reset immediately after setting phyif.  */
3317 +                               usbcfg.b.ulpi_utmi_sel = core_if->core_params->phy_type;
3318 +                               if (usbcfg.b.ulpi_utmi_sel == 1) {
3319 +                                       /* ULPI interface */
3320 +                                       usbcfg.b.phyif = 0;
3321 +                                       usbcfg.b.ddrsel = core_if->core_params->phy_ulpi_ddr;
3322 +                               }
3323 +                               else {
3324 +                                       /* UTMI+ interface */
3325 +                                       if (core_if->core_params->phy_utmi_width == 16) {
3326 +                                               usbcfg.b.phyif = 1;
3327 +                               }
3328 +                               else {
3329 +                                       usbcfg.b.phyif = 0;
3330 +                               }
3331 +                       }
3332 +
3333 +                       dwc_write_reg32(&global_regs->gusbcfg, usbcfg.d32);
3334 +
3335 +                       /* Reset after setting the PHY parameters */
3336 +                       dwc_otg_core_reset(core_if);
3337 +               }
3338 +       }
3339 +
3340 +       if ((core_if->hwcfg2.b.hs_phy_type == 2) &&
3341 +               (core_if->hwcfg2.b.fs_phy_type == 1) &&
3342 +               (core_if->core_params->ulpi_fs_ls)) {
3343 +               DWC_DEBUGPL(DBG_CIL, "Setting ULPI FSLS\n");
3344 +               usbcfg.d32 = dwc_read_reg32(&global_regs->gusbcfg);
3345 +               usbcfg.b.ulpi_fsls = 1;
3346 +               usbcfg.b.ulpi_clk_sus_m = 1;
3347 +               dwc_write_reg32(&global_regs->gusbcfg, usbcfg.d32);
3348 +       }
3349 +       else {
3350 +               usbcfg.d32 = dwc_read_reg32(&global_regs->gusbcfg);
3351 +               usbcfg.b.ulpi_fsls = 0;
3352 +               usbcfg.b.ulpi_clk_sus_m = 0;
3353 +               dwc_write_reg32(&global_regs->gusbcfg, usbcfg.d32);
3354 +       }
3355 +
3356 +       /* Program the GAHBCFG Register.*/
3357 +       switch (core_if->hwcfg2.b.architecture) {
3358 +
3359 +       case DWC_SLAVE_ONLY_ARCH:
3360 +               DWC_DEBUGPL(DBG_CIL, "Slave Only Mode\n");
3361 +               ahbcfg.b.nptxfemplvl_txfemplvl = DWC_GAHBCFG_TXFEMPTYLVL_HALFEMPTY;
3362 +               ahbcfg.b.ptxfemplvl = DWC_GAHBCFG_TXFEMPTYLVL_HALFEMPTY;
3363 +               core_if->dma_enable = 0;
3364 +               core_if->dma_desc_enable = 0;
3365 +               break;
3366 +
3367 +       case DWC_EXT_DMA_ARCH:
3368 +               DWC_DEBUGPL(DBG_CIL, "External DMA Mode\n");
3369 +               ahbcfg.b.hburstlen = core_if->core_params->dma_burst_size;
3370 +               core_if->dma_enable = (core_if->core_params->dma_enable != 0);
3371 +               core_if->dma_desc_enable = (core_if->core_params->dma_desc_enable != 0);
3372 +               break;
3373 +
3374 +       case DWC_INT_DMA_ARCH:
3375 +               DWC_DEBUGPL(DBG_CIL, "Internal DMA Mode\n");
3376 +               ahbcfg.b.hburstlen = DWC_GAHBCFG_INT_DMA_BURST_INCR;
3377 +               core_if->dma_enable = (core_if->core_params->dma_enable != 0);
3378 +               core_if->dma_desc_enable = (core_if->core_params->dma_desc_enable != 0);
3379 +               break;
3380 +
3381 +       }
3382 +       ahbcfg.b.dmaenable = core_if->dma_enable;
3383 +       dwc_write_reg32(&global_regs->gahbcfg, ahbcfg.d32);
3384 +
3385 +       core_if->en_multiple_tx_fifo = core_if->hwcfg4.b.ded_fifo_en;
3386 +
3387 +       core_if->pti_enh_enable = core_if->core_params->pti_enable != 0;
3388 +       core_if->multiproc_int_enable = core_if->core_params->mpi_enable;
3389 +       DWC_PRINT("Periodic Transfer Interrupt Enhancement - %s\n", ((core_if->pti_enh_enable) ? "enabled": "disabled"));
3390 +       DWC_PRINT("Multiprocessor Interrupt Enhancement - %s\n", ((core_if->multiproc_int_enable) ? "enabled": "disabled"));
3391 +
3392 +       /*
3393 +        * Program the GUSBCFG register.
3394 +        */
3395 +       usbcfg.d32 = dwc_read_reg32(&global_regs->gusbcfg);
3396 +
3397 +       switch (core_if->hwcfg2.b.op_mode) {
3398 +       case DWC_MODE_HNP_SRP_CAPABLE:
3399 +               usbcfg.b.hnpcap = (core_if->core_params->otg_cap ==
3400 +                  DWC_OTG_CAP_PARAM_HNP_SRP_CAPABLE);
3401 +               usbcfg.b.srpcap = (core_if->core_params->otg_cap !=
3402 +                  DWC_OTG_CAP_PARAM_NO_HNP_SRP_CAPABLE);
3403 +               break;
3404 +
3405 +       case DWC_MODE_SRP_ONLY_CAPABLE:
3406 +               usbcfg.b.hnpcap = 0;
3407 +               usbcfg.b.srpcap = (core_if->core_params->otg_cap !=
3408 +                  DWC_OTG_CAP_PARAM_NO_HNP_SRP_CAPABLE);
3409 +               break;
3410 +
3411 +       case DWC_MODE_NO_HNP_SRP_CAPABLE:
3412 +               usbcfg.b.hnpcap = 0;
3413 +               usbcfg.b.srpcap = 0;
3414 +               break;
3415 +
3416 +       case DWC_MODE_SRP_CAPABLE_DEVICE:
3417 +               usbcfg.b.hnpcap = 0;
3418 +               usbcfg.b.srpcap = (core_if->core_params->otg_cap !=
3419 +               DWC_OTG_CAP_PARAM_NO_HNP_SRP_CAPABLE);
3420 +               break;
3421 +
3422 +       case DWC_MODE_NO_SRP_CAPABLE_DEVICE:
3423 +               usbcfg.b.hnpcap = 0;
3424 +               usbcfg.b.srpcap = 0;
3425 +               break;
3426 +
3427 +       case DWC_MODE_SRP_CAPABLE_HOST:
3428 +               usbcfg.b.hnpcap = 0;
3429 +               usbcfg.b.srpcap = (core_if->core_params->otg_cap !=
3430 +               DWC_OTG_CAP_PARAM_NO_HNP_SRP_CAPABLE);
3431 +               break;
3432 +
3433 +       case DWC_MODE_NO_SRP_CAPABLE_HOST:
3434 +               usbcfg.b.hnpcap = 0;
3435 +               usbcfg.b.srpcap = 0;
3436 +               break;
3437 +       }
3438 +
3439 +       dwc_write_reg32(&global_regs->gusbcfg, usbcfg.d32);
3440 +
3441 +       /* Enable common interrupts */
3442 +       dwc_otg_enable_common_interrupts(core_if);
3443 +
3444 +       /* Do device or host intialization based on mode during PCD
3445 +        * and HCD initialization  */
3446 +       if (dwc_otg_is_host_mode(core_if)) {
3447 +               DWC_DEBUGPL(DBG_ANY, "Host Mode\n");
3448 +               core_if->op_state = A_HOST;
3449 +       }
3450 +       else {
3451 +               DWC_DEBUGPL(DBG_ANY, "Device Mode\n");
3452 +               core_if->op_state = B_PERIPHERAL;
3453 +#ifdef DWC_DEVICE_ONLY
3454 +               dwc_otg_core_dev_init(core_if);
3455 +#endif
3456 +       }
3457 +}
3458 +
3459 +
3460 +/**
3461 + * This function enables the Device mode interrupts.
3462 + *
3463 + * @param core_if Programming view of DWC_otg controller
3464 + */
3465 +void dwc_otg_enable_device_interrupts(dwc_otg_core_if_t *core_if)
3466 +{
3467 +       gintmsk_data_t intr_mask = { .d32 = 0};
3468 +       dwc_otg_core_global_regs_t *global_regs =
3469 +               core_if->core_global_regs;
3470 +
3471 +       DWC_DEBUGPL(DBG_CIL, "%s()\n", __func__);
3472 +
3473 +       /* Disable all interrupts. */
3474 +       dwc_write_reg32(&global_regs->gintmsk, 0);
3475 +
3476 +       /* Clear any pending interrupts */
3477 +       dwc_write_reg32(&global_regs->gintsts, 0xFFFFFFFF);
3478 +
3479 +       /* Enable the common interrupts */
3480 +       dwc_otg_enable_common_interrupts(core_if);
3481 +
3482 +       /* Enable interrupts */
3483 +       intr_mask.b.usbreset = 1;
3484 +       intr_mask.b.enumdone = 1;
3485 +
3486 +       if(!core_if->multiproc_int_enable) {
3487 +               intr_mask.b.inepintr = 1;
3488 +               intr_mask.b.outepintr = 1;
3489 +       }
3490 +
3491 +       intr_mask.b.erlysuspend = 1;
3492 +
3493 +       if(core_if->en_multiple_tx_fifo == 0) {
3494 +               intr_mask.b.epmismatch = 1;
3495 +       }
3496 +
3497 +
3498 +#ifdef DWC_EN_ISOC
3499 +       if(core_if->dma_enable) {
3500 +               if(core_if->dma_desc_enable == 0) {
3501 +                       if(core_if->pti_enh_enable) {
3502 +                               dctl_data_t dctl = { .d32 = 0 };
3503 +                               dctl.b.ifrmnum = 1;
3504 +                               dwc_modify_reg32(&core_if->dev_if->dev_global_regs->dctl, 0, dctl.d32);
3505 +                       } else {
3506 +                               intr_mask.b.incomplisoin = 1;
3507 +                               intr_mask.b.incomplisoout = 1;
3508 +                       }
3509 +               }
3510 +       } else {
3511 +               intr_mask.b.incomplisoin = 1;
3512 +               intr_mask.b.incomplisoout = 1;
3513 +       }
3514 +#endif // DWC_EN_ISOC
3515 +
3516 +/** @todo NGS: Should this be a module parameter? */
3517 +#ifdef USE_PERIODIC_EP
3518 +       intr_mask.b.isooutdrop = 1;
3519 +       intr_mask.b.eopframe = 1;
3520 +       intr_mask.b.incomplisoin = 1;
3521 +       intr_mask.b.incomplisoout = 1;
3522 +#endif
3523 +
3524 +       dwc_modify_reg32(&global_regs->gintmsk, intr_mask.d32, intr_mask.d32);
3525 +
3526 +       DWC_DEBUGPL(DBG_CIL, "%s() gintmsk=%0x\n", __func__,
3527 +               dwc_read_reg32(&global_regs->gintmsk));
3528 +}
3529 +
3530 +/**
3531 + * This function initializes the DWC_otg controller registers for
3532 + * device mode.
3533 + *
3534 + * @param core_if Programming view of DWC_otg controller
3535 + *
3536 + */
3537 +void dwc_otg_core_dev_init(dwc_otg_core_if_t *core_if)
3538 +{
3539 +       int i;
3540 +       dwc_otg_core_global_regs_t *global_regs =
3541 +               core_if->core_global_regs;
3542 +       dwc_otg_dev_if_t *dev_if = core_if->dev_if;
3543 +       dwc_otg_core_params_t *params = core_if->core_params;
3544 +       dcfg_data_t dcfg = { .d32 = 0};
3545 +       grstctl_t resetctl = { .d32 = 0 };
3546 +       uint32_t rx_fifo_size;
3547 +       fifosize_data_t nptxfifosize;
3548 +       fifosize_data_t txfifosize;
3549 +       dthrctl_data_t dthrctl;
3550 +       fifosize_data_t ptxfifosize;
3551 +
3552 +       /* Restart the Phy Clock */
3553 +       dwc_write_reg32(core_if->pcgcctl, 0);
3554 +
3555 +       /* Device configuration register */
3556 +       init_devspd(core_if);
3557 +       dcfg.d32 = dwc_read_reg32(&dev_if->dev_global_regs->dcfg);
3558 +       dcfg.b.descdma = (core_if->dma_desc_enable) ? 1 : 0;
3559 +       dcfg.b.perfrint = DWC_DCFG_FRAME_INTERVAL_80;
3560 +
3561 +       dwc_write_reg32(&dev_if->dev_global_regs->dcfg, dcfg.d32);
3562 +
3563 +       /* Configure data FIFO sizes */
3564 +       if (core_if->hwcfg2.b.dynamic_fifo && params->enable_dynamic_fifo) {
3565 +               DWC_DEBUGPL(DBG_CIL, "Total FIFO Size=%d\n", core_if->total_fifo_size);
3566 +               DWC_DEBUGPL(DBG_CIL, "Rx FIFO Size=%d\n", params->dev_rx_fifo_size);
3567 +               DWC_DEBUGPL(DBG_CIL, "NP Tx FIFO Size=%d\n", params->dev_nperio_tx_fifo_size);
3568 +
3569 +               /* Rx FIFO */
3570 +               DWC_DEBUGPL(DBG_CIL, "initial grxfsiz=%08x\n",
3571 +                                               dwc_read_reg32(&global_regs->grxfsiz));
3572 +
3573 +               rx_fifo_size = params->dev_rx_fifo_size;
3574 +               dwc_write_reg32(&global_regs->grxfsiz, rx_fifo_size);
3575 +
3576 +               DWC_DEBUGPL(DBG_CIL, "new grxfsiz=%08x\n",
3577 +                       dwc_read_reg32(&global_regs->grxfsiz));
3578 +
3579 +               /** Set Periodic Tx FIFO Mask all bits 0 */
3580 +               core_if->p_tx_msk = 0;
3581 +
3582 +               /** Set Tx FIFO Mask all bits 0 */
3583 +               core_if->tx_msk = 0;
3584 +
3585 +               if(core_if->en_multiple_tx_fifo == 0) {
3586 +                       /* Non-periodic Tx FIFO */
3587 +                       DWC_DEBUGPL(DBG_CIL, "initial gnptxfsiz=%08x\n",
3588 +                                                  dwc_read_reg32(&global_regs->gnptxfsiz));
3589 +
3590 +                       nptxfifosize.b.depth  = params->dev_nperio_tx_fifo_size;
3591 +                       nptxfifosize.b.startaddr = params->dev_rx_fifo_size;
3592 +
3593 +                       dwc_write_reg32(&global_regs->gnptxfsiz, nptxfifosize.d32);
3594 +
3595 +                       DWC_DEBUGPL(DBG_CIL, "new gnptxfsiz=%08x\n",
3596 +                                                  dwc_read_reg32(&global_regs->gnptxfsiz));
3597 +
3598 +                       /**@todo NGS: Fix Periodic FIFO Sizing! */
3599 +                       /*
3600 +                        * Periodic Tx FIFOs These FIFOs are numbered from 1 to 15.
3601 +                        * Indexes of the FIFO size module parameters in the
3602 +                        * dev_perio_tx_fifo_size array and the FIFO size registers in
3603 +                        * the dptxfsiz array run from 0 to 14.
3604 +                        */
3605 +                       /** @todo Finish debug of this */
3606 +                       ptxfifosize.b.startaddr = nptxfifosize.b.startaddr + nptxfifosize.b.depth;
3607 +                       for (i=0; i < core_if->hwcfg4.b.num_dev_perio_in_ep; i++)
3608 +                       {
3609 +                               ptxfifosize.b.depth = params->dev_perio_tx_fifo_size[i];
3610 +                               DWC_DEBUGPL(DBG_CIL, "initial dptxfsiz_dieptxf[%d]=%08x\n", i,
3611 +                                                       dwc_read_reg32(&global_regs->dptxfsiz_dieptxf[i]));
3612 +                               dwc_write_reg32(&global_regs->dptxfsiz_dieptxf[i],
3613 +                                                                ptxfifosize.d32);
3614 +                               DWC_DEBUGPL(DBG_CIL, "new dptxfsiz_dieptxf[%d]=%08x\n", i,
3615 +                                                       dwc_read_reg32(&global_regs->dptxfsiz_dieptxf[i]));
3616 +                               ptxfifosize.b.startaddr += ptxfifosize.b.depth;
3617 +                       }
3618 +               }
3619 +               else {
3620 +                       /*
3621 +                        * Tx FIFOs These FIFOs are numbered from 1 to 15.
3622 +                        * Indexes of the FIFO size module parameters in the
3623 +                        * dev_tx_fifo_size array and the FIFO size registers in
3624 +                        * the dptxfsiz_dieptxf array run from 0 to 14.
3625 +                        */
3626 +
3627 +
3628 +                       /* Non-periodic Tx FIFO */
3629 +                       DWC_DEBUGPL(DBG_CIL, "initial gnptxfsiz=%08x\n",
3630 +                                                       dwc_read_reg32(&global_regs->gnptxfsiz));
3631 +
3632 +                       nptxfifosize.b.depth  = params->dev_nperio_tx_fifo_size;
3633 +                       nptxfifosize.b.startaddr = params->dev_rx_fifo_size;
3634 +
3635 +                       dwc_write_reg32(&global_regs->gnptxfsiz, nptxfifosize.d32);
3636 +
3637 +                       DWC_DEBUGPL(DBG_CIL, "new gnptxfsiz=%08x\n",
3638 +                                                       dwc_read_reg32(&global_regs->gnptxfsiz));
3639 +
3640 +                       txfifosize.b.startaddr = nptxfifosize.b.startaddr + nptxfifosize.b.depth;
3641 +                       /*
3642 +                            Modify by kaiker ,for RT3052 device mode config
3643 +
3644 +                            In RT3052,Since the _core_if->hwcfg4.b.num_dev_perio_in_ep is
3645 +                            configed to 0 so these TX_FIF0 not config.IN EP will can't
3646 +                            more than 1 if not modify it.
3647 +
3648 +                       */
3649 +#if 1
3650 +                       for (i=1 ; i <= dev_if->num_in_eps; i++)
3651 +#else
3652 +                       for (i=1; i < _core_if->hwcfg4.b.num_dev_perio_in_ep; i++)
3653 +#endif
3654 +                       {
3655 +
3656 +                               txfifosize.b.depth = params->dev_tx_fifo_size[i];
3657 +
3658 +                               DWC_DEBUGPL(DBG_CIL, "initial dptxfsiz_dieptxf[%d]=%08x\n", i,
3659 +                                       dwc_read_reg32(&global_regs->dptxfsiz_dieptxf[i]));
3660 +
3661 +                               dwc_write_reg32(&global_regs->dptxfsiz_dieptxf[i-1],
3662 +                                       txfifosize.d32);
3663 +
3664 +                               DWC_DEBUGPL(DBG_CIL, "new dptxfsiz_dieptxf[%d]=%08x\n", i,
3665 +                                       dwc_read_reg32(&global_regs->dptxfsiz_dieptxf[i-1]));
3666 +
3667 +                               txfifosize.b.startaddr += txfifosize.b.depth;
3668 +                       }
3669 +               }
3670 +       }
3671 +       /* Flush the FIFOs */
3672 +       dwc_otg_flush_tx_fifo(core_if, 0x10); /* all Tx FIFOs */
3673 +       dwc_otg_flush_rx_fifo(core_if);
3674 +
3675 +       /* Flush the Learning Queue. */
3676 +       resetctl.b.intknqflsh = 1;
3677 +       dwc_write_reg32(&core_if->core_global_regs->grstctl, resetctl.d32);
3678 +
3679 +       /* Clear all pending Device Interrupts */
3680 +
3681 +       if(core_if->multiproc_int_enable) {
3682 +       }
3683 +
3684 +       /** @todo - if the condition needed to be checked
3685 +        *  or in any case all pending interrutps should be cleared?
3686 +         */
3687 +       if(core_if->multiproc_int_enable) {
3688 +               for(i = 0; i < core_if->dev_if->num_in_eps; ++i) {
3689 +                       dwc_write_reg32(&dev_if->dev_global_regs->diepeachintmsk[i], 0);
3690 +               }
3691 +
3692 +               for(i = 0; i < core_if->dev_if->num_out_eps; ++i) {
3693 +                       dwc_write_reg32(&dev_if->dev_global_regs->doepeachintmsk[i], 0);
3694 +               }
3695 +
3696 +               dwc_write_reg32(&dev_if->dev_global_regs->deachint, 0xFFFFFFFF);
3697 +               dwc_write_reg32(&dev_if->dev_global_regs->deachintmsk, 0);
3698 +       } else {
3699 +                dwc_write_reg32(&dev_if->dev_global_regs->diepmsk, 0);
3700 +                dwc_write_reg32(&dev_if->dev_global_regs->doepmsk, 0);
3701 +                dwc_write_reg32(&dev_if->dev_global_regs->daint, 0xFFFFFFFF);
3702 +                dwc_write_reg32(&dev_if->dev_global_regs->daintmsk, 0);
3703 +       }
3704 +
3705 +       for (i=0; i <= dev_if->num_in_eps; i++)
3706 +       {
3707 +               depctl_data_t depctl;
3708 +               depctl.d32 = dwc_read_reg32(&dev_if->in_ep_regs[i]->diepctl);
3709 +               if (depctl.b.epena) {
3710 +                       depctl.d32 = 0;
3711 +                       depctl.b.epdis = 1;
3712 +                       depctl.b.snak = 1;
3713 +               }
3714 +               else {
3715 +                       depctl.d32 = 0;
3716 +               }
3717 +
3718 +               dwc_write_reg32(&dev_if->in_ep_regs[i]->diepctl, depctl.d32);
3719 +
3720 +
3721 +               dwc_write_reg32(&dev_if->in_ep_regs[i]->dieptsiz, 0);
3722 +               dwc_write_reg32(&dev_if->in_ep_regs[i]->diepdma, 0);
3723 +               dwc_write_reg32(&dev_if->in_ep_regs[i]->diepint, 0xFF);
3724 +       }
3725 +
3726 +       for (i=0; i <= dev_if->num_out_eps; i++)
3727 +       {
3728 +               depctl_data_t depctl;
3729 +               depctl.d32 = dwc_read_reg32(&dev_if->out_ep_regs[i]->doepctl);
3730 +               if (depctl.b.epena) {
3731 +                       depctl.d32 = 0;
3732 +                       depctl.b.epdis = 1;
3733 +                       depctl.b.snak = 1;
3734 +               }
3735 +               else {
3736 +                       depctl.d32 = 0;
3737 +               }
3738 +
3739 +               dwc_write_reg32(&dev_if->out_ep_regs[i]->doepctl, depctl.d32);
3740 +
3741 +               dwc_write_reg32(&dev_if->out_ep_regs[i]->doeptsiz, 0);
3742 +               dwc_write_reg32(&dev_if->out_ep_regs[i]->doepdma, 0);
3743 +               dwc_write_reg32(&dev_if->out_ep_regs[i]->doepint, 0xFF);
3744 +       }
3745 +
3746 +       if(core_if->en_multiple_tx_fifo && core_if->dma_enable) {
3747 +               dev_if->non_iso_tx_thr_en = params->thr_ctl & 0x1;
3748 +               dev_if->iso_tx_thr_en = (params->thr_ctl >> 1) & 0x1;
3749 +               dev_if->rx_thr_en = (params->thr_ctl >> 2) & 0x1;
3750 +
3751 +               dev_if->rx_thr_length = params->rx_thr_length;
3752 +               dev_if->tx_thr_length = params->tx_thr_length;
3753 +
3754 +               dev_if->setup_desc_index = 0;
3755 +
3756 +               dthrctl.d32 = 0;
3757 +               dthrctl.b.non_iso_thr_en = dev_if->non_iso_tx_thr_en;
3758 +               dthrctl.b.iso_thr_en = dev_if->iso_tx_thr_en;
3759 +               dthrctl.b.tx_thr_len = dev_if->tx_thr_length;
3760 +               dthrctl.b.rx_thr_en = dev_if->rx_thr_en;
3761 +               dthrctl.b.rx_thr_len = dev_if->rx_thr_length;
3762 +
3763 +               dwc_write_reg32(&dev_if->dev_global_regs->dtknqr3_dthrctl, dthrctl.d32);
3764 +
3765 +               DWC_DEBUGPL(DBG_CIL, "Non ISO Tx Thr - %d\nISO Tx Thr - %d\nRx Thr - %d\nTx Thr Len - %d\nRx Thr Len - %d\n",
3766 +                       dthrctl.b.non_iso_thr_en, dthrctl.b.iso_thr_en, dthrctl.b.rx_thr_en, dthrctl.b.tx_thr_len, dthrctl.b.rx_thr_len);
3767 +
3768 +       }
3769 +
3770 +       dwc_otg_enable_device_interrupts(core_if);
3771 +
3772 +       {
3773 +               diepmsk_data_t msk = { .d32 = 0 };
3774 +               msk.b.txfifoundrn = 1;
3775 +               if(core_if->multiproc_int_enable) {
3776 +                       dwc_modify_reg32(&dev_if->dev_global_regs->diepeachintmsk[0], msk.d32, msk.d32);
3777 +               } else {
3778 +                       dwc_modify_reg32(&dev_if->dev_global_regs->diepmsk, msk.d32, msk.d32);
3779 +               }
3780 +       }
3781 +
3782 +
3783 +       if(core_if->multiproc_int_enable) {
3784 +               /* Set NAK on Babble */
3785 +               dctl_data_t dctl = { .d32 = 0};
3786 +               dctl.b.nakonbble = 1;
3787 +               dwc_modify_reg32(&dev_if->dev_global_regs->dctl, 0, dctl.d32);
3788 +       }
3789 +}
3790 +
3791 +/**
3792 + * This function enables the Host mode interrupts.
3793 + *
3794 + * @param core_if Programming view of DWC_otg controller
3795 + */
3796 +void dwc_otg_enable_host_interrupts(dwc_otg_core_if_t *core_if)
3797 +{
3798 +       dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs;
3799 +       gintmsk_data_t intr_mask = { .d32 = 0 };
3800 +
3801 +       DWC_DEBUGPL(DBG_CIL, "%s()\n", __func__);
3802 +
3803 +       /* Disable all interrupts. */
3804 +       dwc_write_reg32(&global_regs->gintmsk, 0);
3805 +
3806 +       /* Clear any pending interrupts. */
3807 +       dwc_write_reg32(&global_regs->gintsts, 0xFFFFFFFF);
3808 +
3809 +       /* Enable the common interrupts */
3810 +       dwc_otg_enable_common_interrupts(core_if);
3811 +
3812 +       /*
3813 +        * Enable host mode interrupts without disturbing common
3814 +        * interrupts.
3815 +        */
3816 +       intr_mask.b.sofintr = 1;
3817 +       intr_mask.b.portintr = 1;
3818 +       intr_mask.b.hcintr = 1;
3819 +
3820 +       dwc_modify_reg32(&global_regs->gintmsk, intr_mask.d32, intr_mask.d32);
3821 +}
3822 +
3823 +/**
3824 + * This function disables the Host Mode interrupts.
3825 + *
3826 + * @param core_if Programming view of DWC_otg controller
3827 + */
3828 +void dwc_otg_disable_host_interrupts(dwc_otg_core_if_t *core_if)
3829 +{
3830 +       dwc_otg_core_global_regs_t *global_regs =
3831 +       core_if->core_global_regs;
3832 +       gintmsk_data_t intr_mask = { .d32 = 0 };
3833 +
3834 +       DWC_DEBUGPL(DBG_CILV, "%s()\n", __func__);
3835 +
3836 +       /*
3837 +        * Disable host mode interrupts without disturbing common
3838 +        * interrupts.
3839 +        */
3840 +       intr_mask.b.sofintr = 1;
3841 +       intr_mask.b.portintr = 1;
3842 +       intr_mask.b.hcintr = 1;
3843 +       intr_mask.b.ptxfempty = 1;
3844 +       intr_mask.b.nptxfempty = 1;
3845 +
3846 +       dwc_modify_reg32(&global_regs->gintmsk, intr_mask.d32, 0);
3847 +}
3848 +
3849 +/**
3850 + * This function initializes the DWC_otg controller registers for
3851 + * host mode.
3852 + *
3853 + * This function flushes the Tx and Rx FIFOs and it flushes any entries in the
3854 + * request queues. Host channels are reset to ensure that they are ready for
3855 + * performing transfers.
3856 + *
3857 + * @param core_if Programming view of DWC_otg controller
3858 + *
3859 + */
3860 +void dwc_otg_core_host_init(dwc_otg_core_if_t *core_if)
3861 +{
3862 +       dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs;
3863 +       dwc_otg_host_if_t       *host_if = core_if->host_if;
3864 +       dwc_otg_core_params_t   *params = core_if->core_params;
3865 +       hprt0_data_t            hprt0 = { .d32 = 0 };
3866 +       fifosize_data_t         nptxfifosize;
3867 +       fifosize_data_t         ptxfifosize;
3868 +       int                     i;
3869 +       hcchar_data_t           hcchar;
3870 +       hcfg_data_t             hcfg;
3871 +       dwc_otg_hc_regs_t       *hc_regs;
3872 +       int                     num_channels;
3873 +       gotgctl_data_t  gotgctl = { .d32 = 0 };
3874 +
3875 +       DWC_DEBUGPL(DBG_CILV,"%s(%p)\n", __func__, core_if);
3876 +
3877 +       /* Restart the Phy Clock */
3878 +       dwc_write_reg32(core_if->pcgcctl, 0);
3879 +
3880 +       /* Initialize Host Configuration Register */
3881 +       init_fslspclksel(core_if);
3882 +       if (core_if->core_params->speed == DWC_SPEED_PARAM_FULL)
3883 +       {
3884 +               hcfg.d32 = dwc_read_reg32(&host_if->host_global_regs->hcfg);
3885 +               hcfg.b.fslssupp = 1;
3886 +               dwc_write_reg32(&host_if->host_global_regs->hcfg, hcfg.d32);
3887 +       }
3888 +
3889 +       /* Configure data FIFO sizes */
3890 +       if (core_if->hwcfg2.b.dynamic_fifo && params->enable_dynamic_fifo) {
3891 +               DWC_DEBUGPL(DBG_CIL,"Total FIFO Size=%d\n", core_if->total_fifo_size);
3892 +               DWC_DEBUGPL(DBG_CIL,"Rx FIFO Size=%d\n", params->host_rx_fifo_size);
3893 +               DWC_DEBUGPL(DBG_CIL,"NP Tx FIFO Size=%d\n", params->host_nperio_tx_fifo_size);
3894 +               DWC_DEBUGPL(DBG_CIL,"P Tx FIFO Size=%d\n", params->host_perio_tx_fifo_size);
3895 +
3896 +               /* Rx FIFO */
3897 +               DWC_DEBUGPL(DBG_CIL,"initial grxfsiz=%08x\n", dwc_read_reg32(&global_regs->grxfsiz));
3898 +               dwc_write_reg32(&global_regs->grxfsiz, params->host_rx_fifo_size);
3899 +               DWC_DEBUGPL(DBG_CIL,"new grxfsiz=%08x\n", dwc_read_reg32(&global_regs->grxfsiz));
3900 +
3901 +               /* Non-periodic Tx FIFO */
3902 +               DWC_DEBUGPL(DBG_CIL,"initial gnptxfsiz=%08x\n", dwc_read_reg32(&global_regs->gnptxfsiz));
3903 +               nptxfifosize.b.depth  = params->host_nperio_tx_fifo_size;
3904 +               nptxfifosize.b.startaddr = params->host_rx_fifo_size;
3905 +               dwc_write_reg32(&global_regs->gnptxfsiz, nptxfifosize.d32);
3906 +               DWC_DEBUGPL(DBG_CIL,"new gnptxfsiz=%08x\n", dwc_read_reg32(&global_regs->gnptxfsiz));
3907 +
3908 +               /* Periodic Tx FIFO */
3909 +               DWC_DEBUGPL(DBG_CIL,"initial hptxfsiz=%08x\n", dwc_read_reg32(&global_regs->hptxfsiz));
3910 +               ptxfifosize.b.depth      = params->host_perio_tx_fifo_size;
3911 +               ptxfifosize.b.startaddr = nptxfifosize.b.startaddr + nptxfifosize.b.depth;
3912 +               dwc_write_reg32(&global_regs->hptxfsiz, ptxfifosize.d32);
3913 +               DWC_DEBUGPL(DBG_CIL,"new hptxfsiz=%08x\n", dwc_read_reg32(&global_regs->hptxfsiz));
3914 +       }
3915 +
3916 +       /* Clear Host Set HNP Enable in the OTG Control Register */
3917 +       gotgctl.b.hstsethnpen = 1;
3918 +       dwc_modify_reg32(&global_regs->gotgctl, gotgctl.d32, 0);
3919 +
3920 +       /* Make sure the FIFOs are flushed. */
3921 +       dwc_otg_flush_tx_fifo(core_if, 0x10 /* all Tx FIFOs */);
3922 +       dwc_otg_flush_rx_fifo(core_if);
3923 +
3924 +       /* Flush out any leftover queued requests. */
3925 +       num_channels = core_if->core_params->host_channels;
3926 +       for (i = 0; i < num_channels; i++)
3927 +       {
3928 +               hc_regs = core_if->host_if->hc_regs[i];
3929 +               hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
3930 +               hcchar.b.chen = 0;
3931 +               hcchar.b.chdis = 1;
3932 +               hcchar.b.epdir = 0;
3933 +               dwc_write_reg32(&hc_regs->hcchar, hcchar.d32);
3934 +       }
3935 +
3936 +       /* Halt all channels to put them into a known state. */
3937 +       for (i = 0; i < num_channels; i++)
3938 +       {
3939 +               int count = 0;
3940 +               hc_regs = core_if->host_if->hc_regs[i];
3941 +               hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
3942 +               hcchar.b.chen = 1;
3943 +               hcchar.b.chdis = 1;
3944 +               hcchar.b.epdir = 0;
3945 +               dwc_write_reg32(&hc_regs->hcchar, hcchar.d32);
3946 +               DWC_DEBUGPL(DBG_HCDV, "%s: Halt channel %d\n", __func__, i);
3947 +               do {
3948 +                       hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
3949 +                       if (++count > 1000)
3950 +                       {
3951 +                               DWC_ERROR("%s: Unable to clear halt on channel %d\n",
3952 +                                         __func__, i);
3953 +                               break;
3954 +                       }
3955 +               }
3956 +               while (hcchar.b.chen);
3957 +       }
3958 +
3959 +       /* Turn on the vbus power. */
3960 +       DWC_PRINT("Init: Port Power? op_state=%d\n", core_if->op_state);
3961 +       if (core_if->op_state == A_HOST) {
3962 +               hprt0.d32 = dwc_otg_read_hprt0(core_if);
3963 +               DWC_PRINT("Init: Power Port (%d)\n", hprt0.b.prtpwr);
3964 +               if (hprt0.b.prtpwr == 0) {
3965 +                       hprt0.b.prtpwr = 1;
3966 +                       dwc_write_reg32(host_if->hprt0, hprt0.d32);
3967 +               }
3968 +       }
3969 +
3970 +       dwc_otg_enable_host_interrupts(core_if);
3971 +}
3972 +
3973 +/**
3974 + * Prepares a host channel for transferring packets to/from a specific
3975 + * endpoint. The HCCHARn register is set up with the characteristics specified
3976 + * in _hc. Host channel interrupts that may need to be serviced while this
3977 + * transfer is in progress are enabled.
3978 + *
3979 + * @param core_if Programming view of DWC_otg controller
3980 + * @param hc Information needed to initialize the host channel
3981 + */
3982 +void dwc_otg_hc_init(dwc_otg_core_if_t *core_if, dwc_hc_t *hc)
3983 +{
3984 +       uint32_t intr_enable;
3985 +       hcintmsk_data_t hc_intr_mask;
3986 +       gintmsk_data_t gintmsk = { .d32 = 0 };
3987 +       hcchar_data_t hcchar;
3988 +       hcsplt_data_t hcsplt;
3989 +
3990 +       uint8_t hc_num = hc->hc_num;
3991 +       dwc_otg_host_if_t *host_if = core_if->host_if;
3992 +       dwc_otg_hc_regs_t *hc_regs = host_if->hc_regs[hc_num];
3993 +
3994 +       /* Clear old interrupt conditions for this host channel. */
3995 +       hc_intr_mask.d32 = 0xFFFFFFFF;
3996 +       hc_intr_mask.b.reserved = 0;
3997 +       dwc_write_reg32(&hc_regs->hcint, hc_intr_mask.d32);
3998 +
3999 +       /* Enable channel interrupts required for this transfer. */
4000 +       hc_intr_mask.d32 = 0;
4001 +       hc_intr_mask.b.chhltd = 1;
4002 +       if (core_if->dma_enable) {
4003 +               hc_intr_mask.b.ahberr = 1;
4004 +               if (hc->error_state && !hc->do_split &&
4005 +                       hc->ep_type != DWC_OTG_EP_TYPE_ISOC) {
4006 +                       hc_intr_mask.b.ack = 1;
4007 +                       if (hc->ep_is_in) {
4008 +                               hc_intr_mask.b.datatglerr = 1;
4009 +                               if (hc->ep_type != DWC_OTG_EP_TYPE_INTR) {
4010 +                                       hc_intr_mask.b.nak = 1;
4011 +                               }
4012 +                       }
4013 +               }
4014 +       }
4015 +       else {
4016 +               switch (hc->ep_type) {
4017 +               case DWC_OTG_EP_TYPE_CONTROL:
4018 +               case DWC_OTG_EP_TYPE_BULK:
4019 +                       hc_intr_mask.b.xfercompl = 1;
4020 +                       hc_intr_mask.b.stall = 1;
4021 +                       hc_intr_mask.b.xacterr = 1;
4022 +                       hc_intr_mask.b.datatglerr = 1;
4023 +                       if (hc->ep_is_in) {
4024 +                               hc_intr_mask.b.bblerr = 1;
4025 +                       }
4026 +                       else {
4027 +                               hc_intr_mask.b.nak = 1;
4028 +                               hc_intr_mask.b.nyet = 1;
4029 +                               if (hc->do_ping) {
4030 +                                       hc_intr_mask.b.ack = 1;
4031 +                               }
4032 +                       }
4033 +
4034 +                       if (hc->do_split) {
4035 +                               hc_intr_mask.b.nak = 1;
4036 +                               if (hc->complete_split) {
4037 +                                       hc_intr_mask.b.nyet = 1;
4038 +                               }
4039 +                               else {
4040 +                                       hc_intr_mask.b.ack = 1;
4041 +                               }
4042 +                       }
4043 +
4044 +                       if (hc->error_state) {
4045 +                               hc_intr_mask.b.ack = 1;
4046 +                       }
4047 +                       break;
4048 +               case DWC_OTG_EP_TYPE_INTR:
4049 +                       hc_intr_mask.b.xfercompl = 1;
4050 +                       hc_intr_mask.b.nak = 1;
4051 +                       hc_intr_mask.b.stall = 1;
4052 +                       hc_intr_mask.b.xacterr = 1;
4053 +                       hc_intr_mask.b.datatglerr = 1;
4054 +                       hc_intr_mask.b.frmovrun = 1;
4055 +
4056 +                       if (hc->ep_is_in) {
4057 +                               hc_intr_mask.b.bblerr = 1;
4058 +                       }
4059 +                       if (hc->error_state) {
4060 +                               hc_intr_mask.b.ack = 1;
4061 +                       }
4062 +                       if (hc->do_split) {
4063 +                               if (hc->complete_split) {
4064 +                                       hc_intr_mask.b.nyet = 1;
4065 +                               }
4066 +                               else {
4067 +                                       hc_intr_mask.b.ack = 1;
4068 +                               }
4069 +                       }
4070 +                       break;
4071 +               case DWC_OTG_EP_TYPE_ISOC:
4072 +                       hc_intr_mask.b.xfercompl = 1;
4073 +                       hc_intr_mask.b.frmovrun = 1;
4074 +                       hc_intr_mask.b.ack = 1;
4075 +
4076 +                       if (hc->ep_is_in) {
4077 +                               hc_intr_mask.b.xacterr = 1;
4078 +                               hc_intr_mask.b.bblerr = 1;
4079 +                       }
4080 +                       break;
4081 +               }
4082 +       }
4083 +       dwc_write_reg32(&hc_regs->hcintmsk, hc_intr_mask.d32);
4084 +
4085 +//     if(hc->ep_type == DWC_OTG_EP_TYPE_BULK && !hc->ep_is_in)
4086 +//                     hc->max_packet = 512;
4087 +       /* Enable the top level host channel interrupt. */
4088 +       intr_enable = (1 << hc_num);
4089 +       dwc_modify_reg32(&host_if->host_global_regs->haintmsk, 0, intr_enable);
4090 +
4091 +       /* Make sure host channel interrupts are enabled. */
4092 +       gintmsk.b.hcintr = 1;
4093 +       dwc_modify_reg32(&core_if->core_global_regs->gintmsk, 0, gintmsk.d32);
4094 +
4095 +       /*
4096 +        * Program the HCCHARn register with the endpoint characteristics for
4097 +        * the current transfer.
4098 +        */
4099 +       hcchar.d32 = 0;
4100 +       hcchar.b.devaddr = hc->dev_addr;
4101 +       hcchar.b.epnum = hc->ep_num;
4102 +       hcchar.b.epdir = hc->ep_is_in;
4103 +       hcchar.b.lspddev = (hc->speed == DWC_OTG_EP_SPEED_LOW);
4104 +       hcchar.b.eptype = hc->ep_type;
4105 +       hcchar.b.mps = hc->max_packet;
4106 +
4107 +       dwc_write_reg32(&host_if->hc_regs[hc_num]->hcchar, hcchar.d32);
4108 +
4109 +       DWC_DEBUGPL(DBG_HCDV, "%s: Channel %d\n", __func__, hc->hc_num);
4110 +       DWC_DEBUGPL(DBG_HCDV, "  Dev Addr: %d\n", hcchar.b.devaddr);
4111 +       DWC_DEBUGPL(DBG_HCDV, "  Ep Num: %d\n", hcchar.b.epnum);
4112 +       DWC_DEBUGPL(DBG_HCDV, "  Is In: %d\n", hcchar.b.epdir);
4113 +       DWC_DEBUGPL(DBG_HCDV, "  Is Low Speed: %d\n", hcchar.b.lspddev);
4114 +       DWC_DEBUGPL(DBG_HCDV, "  Ep Type: %d\n", hcchar.b.eptype);
4115 +       DWC_DEBUGPL(DBG_HCDV, "  Max Pkt: %d\n", hcchar.b.mps);
4116 +       DWC_DEBUGPL(DBG_HCDV, "  Multi Cnt: %d\n", hcchar.b.multicnt);
4117 +
4118 +       /*
4119 +        * Program the HCSPLIT register for SPLITs
4120 +        */
4121 +       hcsplt.d32 = 0;
4122 +       if (hc->do_split) {
4123 +               DWC_DEBUGPL(DBG_HCDV, "Programming HC %d with split --> %s\n", hc->hc_num,
4124 +                          hc->complete_split ? "CSPLIT" : "SSPLIT");
4125 +               hcsplt.b.compsplt = hc->complete_split;
4126 +               hcsplt.b.xactpos = hc->xact_pos;
4127 +               hcsplt.b.hubaddr = hc->hub_addr;
4128 +               hcsplt.b.prtaddr = hc->port_addr;
4129 +               DWC_DEBUGPL(DBG_HCDV, "   comp split %d\n", hc->complete_split);
4130 +               DWC_DEBUGPL(DBG_HCDV, "   xact pos %d\n", hc->xact_pos);
4131 +               DWC_DEBUGPL(DBG_HCDV, "   hub addr %d\n", hc->hub_addr);
4132 +               DWC_DEBUGPL(DBG_HCDV, "   port addr %d\n", hc->port_addr);
4133 +               DWC_DEBUGPL(DBG_HCDV, "   is_in %d\n", hc->ep_is_in);
4134 +               DWC_DEBUGPL(DBG_HCDV, "   Max Pkt: %d\n", hcchar.b.mps);
4135 +               DWC_DEBUGPL(DBG_HCDV, "   xferlen: %d\n", hc->xfer_len);
4136 +       }
4137 +       dwc_write_reg32(&host_if->hc_regs[hc_num]->hcsplt, hcsplt.d32);
4138 +
4139 +}
4140 +
4141 +/**
4142 + * Attempts to halt a host channel. This function should only be called in
4143 + * Slave mode or to abort a transfer in either Slave mode or DMA mode. Under
4144 + * normal circumstances in DMA mode, the controller halts the channel when the
4145 + * transfer is complete or a condition occurs that requires application
4146 + * intervention.
4147 + *
4148 + * In slave mode, checks for a free request queue entry, then sets the Channel
4149 + * Enable and Channel Disable bits of the Host Channel Characteristics
4150 + * register of the specified channel to intiate the halt. If there is no free
4151 + * request queue entry, sets only the Channel Disable bit of the HCCHARn
4152 + * register to flush requests for this channel. In the latter case, sets a
4153 + * flag to indicate that the host channel needs to be halted when a request
4154 + * queue slot is open.
4155 + *
4156 + * In DMA mode, always sets the Channel Enable and Channel Disable bits of the
4157 + * HCCHARn register. The controller ensures there is space in the request
4158 + * queue before submitting the halt request.
4159 + *
4160 + * Some time may elapse before the core flushes any posted requests for this
4161 + * host channel and halts. The Channel Halted interrupt handler completes the
4162 + * deactivation of the host channel.
4163 + *
4164 + * @param core_if Controller register interface.
4165 + * @param hc Host channel to halt.
4166 + * @param halt_status Reason for halting the channel.
4167 + */
4168 +void dwc_otg_hc_halt(dwc_otg_core_if_t *core_if,
4169 +                        dwc_hc_t *hc,
4170 +                        dwc_otg_halt_status_e halt_status)
4171 +{
4172 +       gnptxsts_data_t                 nptxsts;
4173 +       hptxsts_data_t                  hptxsts;
4174 +       hcchar_data_t                   hcchar;
4175 +       dwc_otg_hc_regs_t               *hc_regs;
4176 +       dwc_otg_core_global_regs_t      *global_regs;
4177 +       dwc_otg_host_global_regs_t      *host_global_regs;
4178 +
4179 +       hc_regs = core_if->host_if->hc_regs[hc->hc_num];
4180 +       global_regs = core_if->core_global_regs;
4181 +       host_global_regs = core_if->host_if->host_global_regs;
4182 +
4183 +       WARN_ON(halt_status == DWC_OTG_HC_XFER_NO_HALT_STATUS);
4184 +
4185 +       if (halt_status == DWC_OTG_HC_XFER_URB_DEQUEUE ||
4186 +               halt_status == DWC_OTG_HC_XFER_AHB_ERR) {
4187 +               /*
4188 +                * Disable all channel interrupts except Ch Halted. The QTD
4189 +                * and QH state associated with this transfer has been cleared
4190 +                * (in the case of URB_DEQUEUE), so the channel needs to be
4191 +                * shut down carefully to prevent crashes.
4192 +                */
4193 +               hcintmsk_data_t hcintmsk;
4194 +               hcintmsk.d32 = 0;
4195 +               hcintmsk.b.chhltd = 1;
4196 +               dwc_write_reg32(&hc_regs->hcintmsk, hcintmsk.d32);
4197 +
4198 +               /*
4199 +                * Make sure no other interrupts besides halt are currently
4200 +                * pending. Handling another interrupt could cause a crash due
4201 +                * to the QTD and QH state.
4202 +                */
4203 +               dwc_write_reg32(&hc_regs->hcint, ~hcintmsk.d32);
4204 +
4205 +               /*
4206 +                * Make sure the halt status is set to URB_DEQUEUE or AHB_ERR
4207 +                * even if the channel was already halted for some other
4208 +                * reason.
4209 +                */
4210 +               hc->halt_status = halt_status;
4211 +
4212 +               hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
4213 +               if (hcchar.b.chen == 0) {
4214 +                       /*
4215 +                        * The channel is either already halted or it hasn't
4216 +                        * started yet. In DMA mode, the transfer may halt if
4217 +                        * it finishes normally or a condition occurs that
4218 +                        * requires driver intervention. Don't want to halt
4219 +                        * the channel again. In either Slave or DMA mode,
4220 +                        * it's possible that the transfer has been assigned
4221 +                        * to a channel, but not started yet when an URB is
4222 +                        * dequeued. Don't want to halt a channel that hasn't
4223 +                        * started yet.
4224 +                        */
4225 +                       return;
4226 +               }
4227 +       }
4228 +
4229 +       if (hc->halt_pending) {
4230 +               /*
4231 +                * A halt has already been issued for this channel. This might
4232 +                * happen when a transfer is aborted by a higher level in
4233 +                * the stack.
4234 +                */
4235 +#ifdef DEBUG
4236 +               DWC_PRINT("*** %s: Channel %d, _hc->halt_pending already set ***\n",
4237 +                         __func__, hc->hc_num);
4238 +
4239 +/*             dwc_otg_dump_global_registers(core_if); */
4240 +/*             dwc_otg_dump_host_registers(core_if); */
4241 +#endif
4242 +               return;
4243 +       }
4244 +
4245 +       hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
4246 +       hcchar.b.chen = 1;
4247 +       hcchar.b.chdis = 1;
4248 +
4249 +       if (!core_if->dma_enable) {
4250 +               /* Check for space in the request queue to issue the halt. */
4251 +               if (hc->ep_type == DWC_OTG_EP_TYPE_CONTROL ||
4252 +                       hc->ep_type == DWC_OTG_EP_TYPE_BULK) {
4253 +                       nptxsts.d32 = dwc_read_reg32(&global_regs->gnptxsts);
4254 +                       if (nptxsts.b.nptxqspcavail == 0) {
4255 +                               hcchar.b.chen = 0;
4256 +                       }
4257 +               }
4258 +               else {
4259 +                       hptxsts.d32 = dwc_read_reg32(&host_global_regs->hptxsts);
4260 +                       if ((hptxsts.b.ptxqspcavail == 0) || (core_if->queuing_high_bandwidth)) {
4261 +                               hcchar.b.chen = 0;
4262 +                       }
4263 +               }
4264 +       }
4265 +
4266 +       dwc_write_reg32(&hc_regs->hcchar, hcchar.d32);
4267 +
4268 +       hc->halt_status = halt_status;
4269 +
4270 +       if (hcchar.b.chen) {
4271 +               hc->halt_pending = 1;
4272 +               hc->halt_on_queue = 0;
4273 +       }
4274 +       else {
4275 +               hc->halt_on_queue = 1;
4276 +       }
4277 +
4278 +       DWC_DEBUGPL(DBG_HCDV, "%s: Channel %d\n", __func__, hc->hc_num);
4279 +       DWC_DEBUGPL(DBG_HCDV, "  hcchar: 0x%08x\n", hcchar.d32);
4280 +       DWC_DEBUGPL(DBG_HCDV, "  halt_pending: %d\n", hc->halt_pending);
4281 +       DWC_DEBUGPL(DBG_HCDV, "  halt_on_queue: %d\n", hc->halt_on_queue);
4282 +       DWC_DEBUGPL(DBG_HCDV, "  halt_status: %d\n", hc->halt_status);
4283 +
4284 +       return;
4285 +}
4286 +
4287 +/**
4288 + * Clears the transfer state for a host channel. This function is normally
4289 + * called after a transfer is done and the host channel is being released.
4290 + *
4291 + * @param core_if Programming view of DWC_otg controller.
4292 + * @param hc Identifies the host channel to clean up.
4293 + */
4294 +void dwc_otg_hc_cleanup(dwc_otg_core_if_t *core_if, dwc_hc_t *hc)
4295 +{
4296 +       dwc_otg_hc_regs_t *hc_regs;
4297 +
4298 +       hc->xfer_started = 0;
4299 +
4300 +       /*
4301 +        * Clear channel interrupt enables and any unhandled channel interrupt
4302 +        * conditions.
4303 +        */
4304 +       hc_regs = core_if->host_if->hc_regs[hc->hc_num];
4305 +       dwc_write_reg32(&hc_regs->hcintmsk, 0);
4306 +       dwc_write_reg32(&hc_regs->hcint, 0xFFFFFFFF);
4307 +
4308 +#ifdef DEBUG
4309 +       del_timer(&core_if->hc_xfer_timer[hc->hc_num]);
4310 +       {
4311 +               hcchar_data_t hcchar;
4312 +               hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
4313 +               if (hcchar.b.chdis) {
4314 +                       DWC_WARN("%s: chdis set, channel %d, hcchar 0x%08x\n",
4315 +                                __func__, hc->hc_num, hcchar.d32);
4316 +               }
4317 +       }
4318 +#endif
4319 +}
4320 +
4321 +/**
4322 + * Sets the channel property that indicates in which frame a periodic transfer
4323 + * should occur. This is always set to the _next_ frame. This function has no
4324 + * effect on non-periodic transfers.
4325 + *
4326 + * @param core_if Programming view of DWC_otg controller.
4327 + * @param hc Identifies the host channel to set up and its properties.
4328 + * @param hcchar Current value of the HCCHAR register for the specified host
4329 + * channel.
4330 + */
4331 +static inline void hc_set_even_odd_frame(dwc_otg_core_if_t *core_if,
4332 +                                        dwc_hc_t *hc,
4333 +                                        hcchar_data_t *hcchar)
4334 +{
4335 +       if (hc->ep_type == DWC_OTG_EP_TYPE_INTR ||
4336 +               hc->ep_type == DWC_OTG_EP_TYPE_ISOC) {
4337 +               hfnum_data_t    hfnum;
4338 +               hfnum.d32 = dwc_read_reg32(&core_if->host_if->host_global_regs->hfnum);
4339 +
4340 +               /* 1 if _next_ frame is odd, 0 if it's even */
4341 +               hcchar->b.oddfrm = (hfnum.b.frnum & 0x1) ? 0 : 1;
4342 +#ifdef DEBUG
4343 +               if (hc->ep_type == DWC_OTG_EP_TYPE_INTR && hc->do_split && !hc->complete_split) {
4344 +                       switch (hfnum.b.frnum & 0x7) {
4345 +                       case 7:
4346 +                               core_if->hfnum_7_samples++;
4347 +                               core_if->hfnum_7_frrem_accum += hfnum.b.frrem;
4348 +                               break;
4349 +                       case 0:
4350 +                               core_if->hfnum_0_samples++;
4351 +                               core_if->hfnum_0_frrem_accum += hfnum.b.frrem;
4352 +                               break;
4353 +                       default:
4354 +                               core_if->hfnum_other_samples++;
4355 +                               core_if->hfnum_other_frrem_accum += hfnum.b.frrem;
4356 +                               break;
4357 +                       }
4358 +               }
4359 +#endif
4360 +       }
4361 +}
4362 +
4363 +#ifdef DEBUG
4364 +static void hc_xfer_timeout(unsigned long ptr)
4365 +{
4366 +       hc_xfer_info_t *xfer_info = (hc_xfer_info_t *)ptr;
4367 +       int hc_num = xfer_info->hc->hc_num;
4368 +       DWC_WARN("%s: timeout on channel %d\n", __func__, hc_num);
4369 +       DWC_WARN("      start_hcchar_val 0x%08x\n", xfer_info->core_if->start_hcchar_val[hc_num]);
4370 +}
4371 +#endif
4372 +
4373 +/*
4374 + * This function does the setup for a data transfer for a host channel and
4375 + * starts the transfer. May be called in either Slave mode or DMA mode. In
4376 + * Slave mode, the caller must ensure that there is sufficient space in the
4377 + * request queue and Tx Data FIFO.
4378 + *
4379 + * For an OUT transfer in Slave mode, it loads a data packet into the
4380 + * appropriate FIFO. If necessary, additional data packets will be loaded in
4381 + * the Host ISR.
4382 + *
4383 + * For an IN transfer in Slave mode, a data packet is requested. The data
4384 + * packets are unloaded from the Rx FIFO in the Host ISR. If necessary,
4385 + * additional data packets are requested in the Host ISR.
4386 + *
4387 + * For a PING transfer in Slave mode, the Do Ping bit is set in the egards,
4388 + *
4389 + * Steven
4390 + *
4391 + * register along with a packet count of 1 and the channel is enabled. This
4392 + * causes a single PING transaction to occur. Other fields in HCTSIZ are
4393 + * simply set to 0 since no data transfer occurs in this case.
4394 + *
4395 + * For a PING transfer in DMA mode, the HCTSIZ register is initialized with
4396 + * all the information required to perform the subsequent data transfer. In
4397 + * addition, the Do Ping bit is set in the HCTSIZ register. In this case, the
4398 + * controller performs the entire PING protocol, then starts the data
4399 + * transfer.
4400 + *
4401 + * @param core_if Programming view of DWC_otg controller.
4402 + * @param hc Information needed to initialize the host channel. The xfer_len
4403 + * value may be reduced to accommodate the max widths of the XferSize and
4404 + * PktCnt fields in the HCTSIZn register. The multi_count value may be changed
4405 + * to reflect the final xfer_len value.
4406 + */
4407 +void dwc_otg_hc_start_transfer(dwc_otg_core_if_t *core_if, dwc_hc_t *hc)
4408 +{
4409 +       hcchar_data_t hcchar;
4410 +       hctsiz_data_t hctsiz;
4411 +       uint16_t num_packets;
4412 +       uint32_t max_hc_xfer_size = core_if->core_params->max_transfer_size;
4413 +       uint16_t max_hc_pkt_count = core_if->core_params->max_packet_count;
4414 +       dwc_otg_hc_regs_t *hc_regs = core_if->host_if->hc_regs[hc->hc_num];
4415 +
4416 +       hctsiz.d32 = 0;
4417 +
4418 +       if (hc->do_ping) {
4419 +               if (!core_if->dma_enable) {
4420 +                       dwc_otg_hc_do_ping(core_if, hc);
4421 +                       hc->xfer_started = 1;
4422 +                       return;
4423 +               }
4424 +               else {
4425 +                       hctsiz.b.dopng = 1;
4426 +               }
4427 +       }
4428 +
4429 +       if (hc->do_split) {
4430 +               num_packets = 1;
4431 +
4432 +               if (hc->complete_split && !hc->ep_is_in) {
4433 +                       /* For CSPLIT OUT Transfer, set the size to 0 so the
4434 +                        * core doesn't expect any data written to the FIFO */
4435 +                       hc->xfer_len = 0;
4436 +               }
4437 +               else if (hc->ep_is_in || (hc->xfer_len > hc->max_packet)) {
4438 +                       hc->xfer_len = hc->max_packet;
4439 +               }
4440 +               else if (!hc->ep_is_in && (hc->xfer_len > 188)) {
4441 +                       hc->xfer_len = 188;
4442 +               }
4443 +
4444 +               hctsiz.b.xfersize = hc->xfer_len;
4445 +       }
4446 +       else {
4447 +               /*
4448 +                * Ensure that the transfer length and packet count will fit
4449 +                * in the widths allocated for them in the HCTSIZn register.
4450 +                */
4451 +               if (hc->ep_type == DWC_OTG_EP_TYPE_INTR ||
4452 +                       hc->ep_type == DWC_OTG_EP_TYPE_ISOC) {
4453 +                       /*
4454 +                        * Make sure the transfer size is no larger than one
4455 +                        * (micro)frame's worth of data. (A check was done
4456 +                        * when the periodic transfer was accepted to ensure
4457 +                        * that a (micro)frame's worth of data can be
4458 +                        * programmed into a channel.)
4459 +                        */
4460 +                       uint32_t max_periodic_len = hc->multi_count * hc->max_packet;
4461 +                       if (hc->xfer_len > max_periodic_len) {
4462 +                               hc->xfer_len = max_periodic_len;
4463 +                       }
4464 +                       else {
4465 +                       }
4466 +
4467 +               }
4468 +               else if (hc->xfer_len > max_hc_xfer_size) {
4469 +                       /* Make sure that xfer_len is a multiple of max packet size. */
4470 +                       hc->xfer_len = max_hc_xfer_size - hc->max_packet + 1;
4471 +               }
4472 +
4473 +               if (hc->xfer_len > 0) {
4474 +                       num_packets = (hc->xfer_len + hc->max_packet - 1) / hc->max_packet;
4475 +                       if (num_packets > max_hc_pkt_count) {
4476 +                               num_packets = max_hc_pkt_count;
4477 +                               hc->xfer_len = num_packets * hc->max_packet;
4478 +                       }
4479 +               }
4480 +               else {
4481 +                       /* Need 1 packet for transfer length of 0. */
4482 +                       num_packets = 1;
4483 +               }
4484 +
4485 +               if (hc->ep_is_in) {
4486 +                       /* Always program an integral # of max packets for IN transfers. */
4487 +                       hc->xfer_len = num_packets * hc->max_packet;
4488 +               }
4489 +
4490 +               if (hc->ep_type == DWC_OTG_EP_TYPE_INTR ||
4491 +                       hc->ep_type == DWC_OTG_EP_TYPE_ISOC) {
4492 +                       /*
4493 +                        * Make sure that the multi_count field matches the
4494 +                        * actual transfer length.
4495 +                        */
4496 +                       hc->multi_count = num_packets;
4497 +               }
4498 +
4499 +               if (hc->ep_type == DWC_OTG_EP_TYPE_ISOC) {
4500 +                       /* Set up the initial PID for the transfer. */
4501 +                       if (hc->speed == DWC_OTG_EP_SPEED_HIGH) {
4502 +                               if (hc->ep_is_in) {
4503 +                                       if (hc->multi_count == 1) {
4504 +                                               hc->data_pid_start = DWC_OTG_HC_PID_DATA0;
4505 +                                       }
4506 +                                       else if (hc->multi_count == 2) {
4507 +                                               hc->data_pid_start = DWC_OTG_HC_PID_DATA1;
4508 +                                       }
4509 +                                       else {
4510 +                                               hc->data_pid_start = DWC_OTG_HC_PID_DATA2;
4511 +                                       }
4512 +                               }
4513 +                               else {
4514 +                                       if (hc->multi_count == 1) {
4515 +                                               hc->data_pid_start = DWC_OTG_HC_PID_DATA0;
4516 +                                       }
4517 +                                       else {
4518 +                                               hc->data_pid_start = DWC_OTG_HC_PID_MDATA;
4519 +                                       }
4520 +                               }
4521 +                       }
4522 +                       else {
4523 +                               hc->data_pid_start = DWC_OTG_HC_PID_DATA0;
4524 +                       }
4525 +               }
4526 +
4527 +               hctsiz.b.xfersize = hc->xfer_len;
4528 +       }
4529 +
4530 +       hc->start_pkt_count = num_packets;
4531 +       hctsiz.b.pktcnt = num_packets;
4532 +       hctsiz.b.pid = hc->data_pid_start;
4533 +       dwc_write_reg32(&hc_regs->hctsiz, hctsiz.d32);
4534 +
4535 +       DWC_DEBUGPL(DBG_HCDV, "%s: Channel %d\n", __func__, hc->hc_num);
4536 +       DWC_DEBUGPL(DBG_HCDV, "  Xfer Size: %d\n", hctsiz.b.xfersize);
4537 +       DWC_DEBUGPL(DBG_HCDV, "  Num Pkts: %d\n", hctsiz.b.pktcnt);
4538 +       DWC_DEBUGPL(DBG_HCDV, "  Start PID: %d\n", hctsiz.b.pid);
4539 +
4540 +       if (core_if->dma_enable) {
4541 +#if defined (CONFIG_DWC_OTG_HOST_ONLY)
4542 +               if ((uint32_t)hc->xfer_buff & 0x3) {
4543 +                       /* non DWORD-aligned buffer case*/
4544 +                       if(!hc->qh->dw_align_buf) {
4545 +                               hc->qh->dw_align_buf =
4546 +                                       dma_alloc_coherent(NULL,
4547 +                                                          core_if->core_params->max_transfer_size,
4548 +                                                          &hc->qh->dw_align_buf_dma,
4549 +                                                          GFP_ATOMIC | GFP_DMA);
4550 +                               if (!hc->qh->dw_align_buf) {
4551 +
4552 +                                       DWC_ERROR("%s: Failed to allocate memory to handle "
4553 +                                                 "non-dword aligned buffer case\n", __func__);
4554 +                                       return;
4555 +                               }
4556 +
4557 +                       }
4558 +                       if (!hc->ep_is_in) {
4559 +                           memcpy(hc->qh->dw_align_buf, phys_to_virt((uint32_t)hc->xfer_buff), hc->xfer_len);
4560 +                       }
4561 +
4562 +                       dwc_write_reg32(&hc_regs->hcdma, hc->qh->dw_align_buf_dma);
4563 +               }
4564 +               else
4565 +#endif
4566 +                   dwc_write_reg32(&hc_regs->hcdma, (uint32_t)hc->xfer_buff);
4567 +       }
4568 +
4569 +       /* Start the split */
4570 +       if (hc->do_split) {
4571 +               hcsplt_data_t hcsplt;
4572 +               hcsplt.d32 = dwc_read_reg32 (&hc_regs->hcsplt);
4573 +               hcsplt.b.spltena = 1;
4574 +               dwc_write_reg32(&hc_regs->hcsplt, hcsplt.d32);
4575 +       }
4576 +
4577 +       hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
4578 +       hcchar.b.multicnt = hc->multi_count;
4579 +       hc_set_even_odd_frame(core_if, hc, &hcchar);
4580 +#ifdef DEBUG
4581 +       core_if->start_hcchar_val[hc->hc_num] = hcchar.d32;
4582 +       if (hcchar.b.chdis) {
4583 +               DWC_WARN("%s: chdis set, channel %d, hcchar 0x%08x\n",
4584 +                        __func__, hc->hc_num, hcchar.d32);
4585 +       }
4586 +#endif
4587 +
4588 +       /* Set host channel enable after all other setup is complete. */
4589 +       hcchar.b.chen = 1;
4590 +       hcchar.b.chdis = 0;
4591 +       dwc_write_reg32(&hc_regs->hcchar, hcchar.d32);
4592 +
4593 +       hc->xfer_started = 1;
4594 +       hc->requests++;
4595 +
4596 +       if (!core_if->dma_enable &&
4597 +               !hc->ep_is_in && hc->xfer_len > 0) {
4598 +               /* Load OUT packet into the appropriate Tx FIFO. */
4599 +               dwc_otg_hc_write_packet(core_if, hc);
4600 +       }
4601 +
4602 +#ifdef DEBUG
4603 +       /* Start a timer for this transfer. */
4604 +       core_if->hc_xfer_timer[hc->hc_num].function = hc_xfer_timeout;
4605 +       core_if->hc_xfer_info[hc->hc_num].core_if = core_if;
4606 +       core_if->hc_xfer_info[hc->hc_num].hc = hc;
4607 +       core_if->hc_xfer_timer[hc->hc_num].data = (unsigned long)(&core_if->hc_xfer_info[hc->hc_num]);
4608 +       core_if->hc_xfer_timer[hc->hc_num].expires = jiffies + (HZ*10);
4609 +       add_timer(&core_if->hc_xfer_timer[hc->hc_num]);
4610 +#endif
4611 +}
4612 +
4613 +/**
4614 + * This function continues a data transfer that was started by previous call
4615 + * to <code>dwc_otg_hc_start_transfer</code>. The caller must ensure there is
4616 + * sufficient space in the request queue and Tx Data FIFO. This function
4617 + * should only be called in Slave mode. In DMA mode, the controller acts
4618 + * autonomously to complete transfers programmed to a host channel.
4619 + *
4620 + * For an OUT transfer, a new data packet is loaded into the appropriate FIFO
4621 + * if there is any data remaining to be queued. For an IN transfer, another
4622 + * data packet is always requested. For the SETUP phase of a control transfer,
4623 + * this function does nothing.
4624 + *
4625 + * @return 1 if a new request is queued, 0 if no more requests are required
4626 + * for this transfer.
4627 + */
4628 +int dwc_otg_hc_continue_transfer(dwc_otg_core_if_t *core_if, dwc_hc_t *hc)
4629 +{
4630 +       DWC_DEBUGPL(DBG_HCDV, "%s: Channel %d\n", __func__, hc->hc_num);
4631 +
4632 +       if (hc->do_split) {
4633 +               /* SPLITs always queue just once per channel */
4634 +               return 0;
4635 +       }
4636 +       else if (hc->data_pid_start == DWC_OTG_HC_PID_SETUP) {
4637 +               /* SETUPs are queued only once since they can't be NAKed. */
4638 +               return 0;
4639 +       }
4640 +       else if (hc->ep_is_in) {
4641 +               /*
4642 +                * Always queue another request for other IN transfers. If
4643 +                * back-to-back INs are issued and NAKs are received for both,
4644 +                * the driver may still be processing the first NAK when the
4645 +                * second NAK is received. When the interrupt handler clears
4646 +                * the NAK interrupt for the first NAK, the second NAK will
4647 +                * not be seen. So we can't depend on the NAK interrupt
4648 +                * handler to requeue a NAKed request. Instead, IN requests
4649 +                * are issued each time this function is called. When the
4650 +                * transfer completes, the extra requests for the channel will
4651 +                * be flushed.
4652 +                */
4653 +               hcchar_data_t hcchar;
4654 +               dwc_otg_hc_regs_t *hc_regs = core_if->host_if->hc_regs[hc->hc_num];
4655 +
4656 +               hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
4657 +               hc_set_even_odd_frame(core_if, hc, &hcchar);
4658 +               hcchar.b.chen = 1;
4659 +               hcchar.b.chdis = 0;
4660 +               DWC_DEBUGPL(DBG_HCDV, "  IN xfer: hcchar = 0x%08x\n", hcchar.d32);
4661 +               dwc_write_reg32(&hc_regs->hcchar, hcchar.d32);
4662 +               hc->requests++;
4663 +               return 1;
4664 +       }
4665 +       else {
4666 +               /* OUT transfers. */
4667 +               if (hc->xfer_count < hc->xfer_len) {
4668 +                       if (hc->ep_type == DWC_OTG_EP_TYPE_INTR ||
4669 +                               hc->ep_type == DWC_OTG_EP_TYPE_ISOC) {
4670 +                               hcchar_data_t hcchar;
4671 +                               dwc_otg_hc_regs_t *hc_regs;
4672 +                               hc_regs = core_if->host_if->hc_regs[hc->hc_num];
4673 +                               hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
4674 +                               hc_set_even_odd_frame(core_if, hc, &hcchar);
4675 +                       }
4676 +
4677 +                       /* Load OUT packet into the appropriate Tx FIFO. */
4678 +                       dwc_otg_hc_write_packet(core_if, hc);
4679 +                       hc->requests++;
4680 +                       return 1;
4681 +               }
4682 +               else {
4683 +                       return 0;
4684 +               }
4685 +       }
4686 +}
4687 +
4688 +/**
4689 + * Starts a PING transfer. This function should only be called in Slave mode.
4690 + * The Do Ping bit is set in the HCTSIZ register, then the channel is enabled.
4691 + */
4692 +void dwc_otg_hc_do_ping(dwc_otg_core_if_t *core_if, dwc_hc_t *hc)
4693 +{
4694 +       hcchar_data_t hcchar;
4695 +       hctsiz_data_t hctsiz;
4696 +       dwc_otg_hc_regs_t *hc_regs = core_if->host_if->hc_regs[hc->hc_num];
4697 +
4698 +       DWC_DEBUGPL(DBG_HCDV, "%s: Channel %d\n", __func__, hc->hc_num);
4699 +
4700 +       hctsiz.d32 = 0;
4701 +       hctsiz.b.dopng = 1;
4702 +       hctsiz.b.pktcnt = 1;
4703 +       dwc_write_reg32(&hc_regs->hctsiz, hctsiz.d32);
4704 +
4705 +       hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
4706 +       hcchar.b.chen = 1;
4707 +       hcchar.b.chdis = 0;
4708 +       dwc_write_reg32(&hc_regs->hcchar, hcchar.d32);
4709 +}
4710 +
4711 +/*
4712 + * This function writes a packet into the Tx FIFO associated with the Host
4713 + * Channel. For a channel associated with a non-periodic EP, the non-periodic
4714 + * Tx FIFO is written. For a channel associated with a periodic EP, the
4715 + * periodic Tx FIFO is written. This function should only be called in Slave
4716 + * mode.
4717 + *
4718 + * Upon return the xfer_buff and xfer_count fields in _hc are incremented by
4719 + * then number of bytes written to the Tx FIFO.
4720 + */
4721 +void dwc_otg_hc_write_packet(dwc_otg_core_if_t *core_if, dwc_hc_t *hc)
4722 +{
4723 +       uint32_t i;
4724 +       uint32_t remaining_count;
4725 +       uint32_t byte_count;
4726 +       uint32_t dword_count;
4727 +
4728 +       uint32_t *data_buff = (uint32_t *)(hc->xfer_buff);
4729 +       uint32_t *data_fifo = core_if->data_fifo[hc->hc_num];
4730 +
4731 +       remaining_count = hc->xfer_len - hc->xfer_count;
4732 +       if (remaining_count > hc->max_packet) {
4733 +               byte_count = hc->max_packet;
4734 +       }
4735 +       else {
4736 +               byte_count = remaining_count;
4737 +       }
4738 +
4739 +       dword_count = (byte_count + 3) / 4;
4740 +
4741 +       if ((((unsigned long)data_buff) & 0x3) == 0) {
4742 +               /* xfer_buff is DWORD aligned. */
4743 +               for (i = 0; i < dword_count; i++, data_buff++)
4744 +               {
4745 +                       dwc_write_reg32(data_fifo, *data_buff);
4746 +               }
4747 +       }
4748 +       else {
4749 +               /* xfer_buff is not DWORD aligned. */
4750 +               for (i = 0; i < dword_count; i++, data_buff++)
4751 +               {
4752 +                       dwc_write_reg32(data_fifo, get_unaligned(data_buff));
4753 +               }
4754 +       }
4755 +
4756 +       hc->xfer_count += byte_count;
4757 +       hc->xfer_buff += byte_count;
4758 +}
4759 +
4760 +/**
4761 + * Gets the current USB frame number. This is the frame number from the last
4762 + * SOF packet.
4763 + */
4764 +uint32_t dwc_otg_get_frame_number(dwc_otg_core_if_t *core_if)
4765 +{
4766 +       dsts_data_t dsts;
4767 +       dsts.d32 = dwc_read_reg32(&core_if->dev_if->dev_global_regs->dsts);
4768 +
4769 +       /* read current frame/microframe number from DSTS register */
4770 +       return dsts.b.soffn;
4771 +}
4772 +
4773 +/**
4774 + * This function reads a setup packet from the Rx FIFO into the destination
4775 + * buffer.     This function is called from the Rx Status Queue Level (RxStsQLvl)
4776 + * Interrupt routine when a SETUP packet has been received in Slave mode.
4777 + *
4778 + * @param core_if Programming view of DWC_otg controller.
4779 + * @param dest Destination buffer for packet data.
4780 + */
4781 +void dwc_otg_read_setup_packet(dwc_otg_core_if_t *core_if, uint32_t *dest)
4782 +{
4783 +       /* Get the 8 bytes of a setup transaction data */
4784 +
4785 +       /* Pop 2 DWORDS off the receive data FIFO into memory */
4786 +       dest[0] = dwc_read_reg32(core_if->data_fifo[0]);
4787 +       dest[1] = dwc_read_reg32(core_if->data_fifo[0]);
4788 +}
4789 +
4790 +
4791 +/**
4792 + * This function enables EP0 OUT to receive SETUP packets and configures EP0
4793 + * IN for transmitting packets.         It is normally called when the
4794 + * "Enumeration Done" interrupt occurs.
4795 + *
4796 + * @param core_if Programming view of DWC_otg controller.
4797 + * @param ep The EP0 data.
4798 + */
4799 +void dwc_otg_ep0_activate(dwc_otg_core_if_t *core_if, dwc_ep_t *ep)
4800 +{
4801 +       dwc_otg_dev_if_t *dev_if = core_if->dev_if;
4802 +       dsts_data_t dsts;
4803 +       depctl_data_t diepctl;
4804 +       depctl_data_t doepctl;
4805 +       dctl_data_t dctl = { .d32 = 0 };
4806 +
4807 +       /* Read the Device Status and Endpoint 0 Control registers */
4808 +       dsts.d32 = dwc_read_reg32(&dev_if->dev_global_regs->dsts);
4809 +       diepctl.d32 = dwc_read_reg32(&dev_if->in_ep_regs[0]->diepctl);
4810 +       doepctl.d32 = dwc_read_reg32(&dev_if->out_ep_regs[0]->doepctl);
4811 +
4812 +       /* Set the MPS of the IN EP based on the enumeration speed */
4813 +       switch (dsts.b.enumspd) {
4814 +       case DWC_DSTS_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ:
4815 +       case DWC_DSTS_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ:
4816 +       case DWC_DSTS_ENUMSPD_FS_PHY_48MHZ:
4817 +               diepctl.b.mps = DWC_DEP0CTL_MPS_64;
4818 +               break;
4819 +       case DWC_DSTS_ENUMSPD_LS_PHY_6MHZ:
4820 +               diepctl.b.mps = DWC_DEP0CTL_MPS_8;
4821 +               break;
4822 +       }
4823 +
4824 +       dwc_write_reg32(&dev_if->in_ep_regs[0]->diepctl, diepctl.d32);
4825 +
4826 +       /* Enable OUT EP for receive */
4827 +       doepctl.b.epena = 1;
4828 +       dwc_write_reg32(&dev_if->out_ep_regs[0]->doepctl, doepctl.d32);
4829 +
4830 +#ifdef VERBOSE
4831 +       DWC_DEBUGPL(DBG_PCDV,"doepctl0=%0x\n",
4832 +               dwc_read_reg32(&dev_if->out_ep_regs[0]->doepctl));
4833 +       DWC_DEBUGPL(DBG_PCDV,"diepctl0=%0x\n",
4834 +               dwc_read_reg32(&dev_if->in_ep_regs[0]->diepctl));
4835 +#endif
4836 +       dctl.b.cgnpinnak = 1;
4837 +
4838 +       dwc_modify_reg32(&dev_if->dev_global_regs->dctl, dctl.d32, dctl.d32);
4839 +       DWC_DEBUGPL(DBG_PCDV,"dctl=%0x\n",
4840 +               dwc_read_reg32(&dev_if->dev_global_regs->dctl));
4841 +}
4842 +
4843 +/**
4844 + * This function activates an EP.  The Device EP control register for
4845 + * the EP is configured as defined in the ep structure.         Note: This
4846 + * function is not used for EP0.
4847 + *
4848 + * @param core_if Programming view of DWC_otg controller.
4849 + * @param ep The EP to activate.
4850 + */
4851 +void dwc_otg_ep_activate(dwc_otg_core_if_t *core_if, dwc_ep_t *ep)
4852 +{
4853 +       dwc_otg_dev_if_t *dev_if = core_if->dev_if;
4854 +       depctl_data_t depctl;
4855 +       volatile uint32_t *addr;
4856 +       daint_data_t daintmsk = { .d32 = 0 };
4857 +
4858 +       DWC_DEBUGPL(DBG_PCDV, "%s() EP%d-%s\n", __func__, ep->num,
4859 +               (ep->is_in?"IN":"OUT"));
4860 +
4861 +       /* Read DEPCTLn register */
4862 +       if (ep->is_in == 1) {
4863 +               addr = &dev_if->in_ep_regs[ep->num]->diepctl;
4864 +               daintmsk.ep.in = 1<<ep->num;
4865 +       }
4866 +       else {
4867 +               addr = &dev_if->out_ep_regs[ep->num]->doepctl;
4868 +               daintmsk.ep.out = 1<<ep->num;
4869 +       }
4870 +
4871 +       /* If the EP is already active don't change the EP Control
4872 +        * register. */
4873 +       depctl.d32 = dwc_read_reg32(addr);
4874 +       if (!depctl.b.usbactep) {
4875 +               depctl.b.mps = ep->maxpacket;
4876 +               depctl.b.eptype = ep->type;
4877 +               depctl.b.txfnum = ep->tx_fifo_num;
4878 +
4879 +               if (ep->type == DWC_OTG_EP_TYPE_ISOC) {
4880 +                       depctl.b.setd0pid = 1; // ???
4881 +               }
4882 +               else {
4883 +                       depctl.b.setd0pid = 1;
4884 +               }
4885 +               depctl.b.usbactep = 1;
4886 +
4887 +               dwc_write_reg32(addr, depctl.d32);
4888 +               DWC_DEBUGPL(DBG_PCDV,"DEPCTL=%08x\n", dwc_read_reg32(addr));
4889 +       }
4890 +
4891 +       /* Enable the Interrupt for this EP */
4892 +       if(core_if->multiproc_int_enable) {
4893 +               if (ep->is_in == 1) {
4894 +                       diepmsk_data_t diepmsk = { .d32 = 0};
4895 +                       diepmsk.b.xfercompl = 1;
4896 +                       diepmsk.b.timeout = 1;
4897 +                       diepmsk.b.epdisabled = 1;
4898 +                       diepmsk.b.ahberr = 1;
4899 +                       diepmsk.b.intknepmis = 1;
4900 +                       diepmsk.b.txfifoundrn = 1; //?????
4901 +
4902 +
4903 +                       if(core_if->dma_desc_enable) {
4904 +                               diepmsk.b.bna = 1;
4905 +                       }
4906 +/*
4907 +                       if(core_if->dma_enable) {
4908 +                               doepmsk.b.nak = 1;
4909 +                       }
4910 +*/
4911 +                       dwc_write_reg32(&dev_if->dev_global_regs->diepeachintmsk[ep->num], diepmsk.d32);
4912 +
4913 +               } else {
4914 +                       doepmsk_data_t doepmsk = { .d32 = 0};
4915 +                       doepmsk.b.xfercompl = 1;
4916 +                       doepmsk.b.ahberr = 1;
4917 +                       doepmsk.b.epdisabled = 1;
4918 +
4919 +
4920 +                       if(core_if->dma_desc_enable) {
4921 +                               doepmsk.b.bna = 1;
4922 +                       }
4923 +/*
4924 +                       doepmsk.b.babble = 1;
4925 +                       doepmsk.b.nyet = 1;
4926 +                       doepmsk.b.nak = 1;
4927 +*/
4928 +                       dwc_write_reg32(&dev_if->dev_global_regs->doepeachintmsk[ep->num], doepmsk.d32);
4929 +               }
4930 +               dwc_modify_reg32(&dev_if->dev_global_regs->deachintmsk,
4931 +                        0, daintmsk.d32);
4932 +       } else {
4933 +               dwc_modify_reg32(&dev_if->dev_global_regs->daintmsk,
4934 +                                0, daintmsk.d32);
4935 +       }
4936 +
4937 +       DWC_DEBUGPL(DBG_PCDV,"DAINTMSK=%0x\n",
4938 +               dwc_read_reg32(&dev_if->dev_global_regs->daintmsk));
4939 +
4940 +       ep->stall_clear_flag = 0;
4941 +       return;
4942 +}
4943 +
4944 +/**
4945 + * This function deactivates an EP. This is done by clearing the USB Active
4946 + * EP bit in the Device EP control register. Note: This function is not used
4947 + * for EP0. EP0 cannot be deactivated.
4948 + *
4949 + * @param core_if Programming view of DWC_otg controller.
4950 + * @param ep The EP to deactivate.
4951 + */
4952 +void dwc_otg_ep_deactivate(dwc_otg_core_if_t *core_if, dwc_ep_t *ep)
4953 +{
4954 +       depctl_data_t depctl = { .d32 = 0 };
4955 +       volatile uint32_t *addr;
4956 +       daint_data_t daintmsk = { .d32 = 0};
4957 +
4958 +       /* Read DEPCTLn register */
4959 +       if (ep->is_in == 1) {
4960 +               addr = &core_if->dev_if->in_ep_regs[ep->num]->diepctl;
4961 +               daintmsk.ep.in = 1<<ep->num;
4962 +       }
4963 +       else {
4964 +               addr = &core_if->dev_if->out_ep_regs[ep->num]->doepctl;
4965 +               daintmsk.ep.out = 1<<ep->num;
4966 +       }
4967 +
4968 +       depctl.b.usbactep = 0;
4969 +
4970 +       if(core_if->dma_desc_enable)
4971 +               depctl.b.epdis = 1;
4972 +
4973 +       dwc_write_reg32(addr, depctl.d32);
4974 +
4975 +       /* Disable the Interrupt for this EP */
4976 +       if(core_if->multiproc_int_enable) {
4977 +               dwc_modify_reg32(&core_if->dev_if->dev_global_regs->deachintmsk,
4978 +                                daintmsk.d32, 0);
4979 +
4980 +               if (ep->is_in == 1) {
4981 +                       dwc_write_reg32(&core_if->dev_if->dev_global_regs->diepeachintmsk[ep->num], 0);
4982 +               } else {
4983 +                       dwc_write_reg32(&core_if->dev_if->dev_global_regs->doepeachintmsk[ep->num], 0);
4984 +               }
4985 +       } else {
4986 +               dwc_modify_reg32(&core_if->dev_if->dev_global_regs->daintmsk,
4987 +                                        daintmsk.d32, 0);
4988 +       }
4989 +}
4990 +
4991 +/**
4992 + * This function does the setup for a data transfer for an EP and
4993 + * starts the transfer.         For an IN transfer, the packets will be
4994 + * loaded into the appropriate Tx FIFO in the ISR. For OUT transfers,
4995 + * the packets are unloaded from the Rx FIFO in the ISR.  the ISR.
4996 + *
4997 + * @param core_if Programming view of DWC_otg controller.
4998 + * @param ep The EP to start the transfer on.
4999 + */
5000 +static void init_dma_desc_chain(dwc_otg_core_if_t *core_if, dwc_ep_t *ep)
5001 +{
5002 +       dwc_otg_dma_desc_t* dma_desc;
5003 +       uint32_t offset;
5004 +       uint32_t xfer_est;
5005 +       int i;
5006 +
5007 +       ep->desc_cnt = ( ep->total_len / ep->maxxfer)  +
5008 +               ((ep->total_len % ep->maxxfer) ? 1 : 0);
5009 +       if(!ep->desc_cnt)
5010 +               ep->desc_cnt = 1;
5011 +
5012 +       dma_desc = ep->desc_addr;
5013 +       xfer_est = ep->total_len;
5014 +       offset = 0;
5015 +       for( i = 0; i < ep->desc_cnt; ++i) {
5016 +               /** DMA Descriptor Setup */
5017 +               if(xfer_est > ep->maxxfer) {
5018 +                       dma_desc->status.b.bs = BS_HOST_BUSY;
5019 +                       dma_desc->status.b.l = 0;
5020 +                       dma_desc->status.b.ioc = 0;
5021 +                       dma_desc->status.b.sp = 0;
5022 +                       dma_desc->status.b.bytes = ep->maxxfer;
5023 +                       dma_desc->buf = ep->dma_addr + offset;
5024 +                       dma_desc->status.b.bs = BS_HOST_READY;
5025 +
5026 +                       xfer_est -= ep->maxxfer;
5027 +                       offset += ep->maxxfer;
5028 +               } else {
5029 +                       dma_desc->status.b.bs = BS_HOST_BUSY;
5030 +                       dma_desc->status.b.l = 1;
5031 +                       dma_desc->status.b.ioc = 1;
5032 +                       if(ep->is_in) {
5033 +                               dma_desc->status.b.sp = (xfer_est % ep->maxpacket) ?
5034 +                                       1 : ((ep->sent_zlp) ? 1 : 0);
5035 +                               dma_desc->status.b.bytes = xfer_est;
5036 +                       } else  {
5037 +                               dma_desc->status.b.bytes = xfer_est + ((4 - (xfer_est & 0x3)) & 0x3) ;
5038 +                       }
5039 +
5040 +                       dma_desc->buf = ep->dma_addr + offset;
5041 +                       dma_desc->status.b.bs = BS_HOST_READY;
5042 +               }
5043 +               dma_desc ++;
5044 +       }
5045 +}
5046 +
5047 +/**
5048 + * This function does the setup for a data transfer for an EP and
5049 + * starts the transfer.         For an IN transfer, the packets will be
5050 + * loaded into the appropriate Tx FIFO in the ISR. For OUT transfers,
5051 + * the packets are unloaded from the Rx FIFO in the ISR.  the ISR.
5052 + *
5053 + * @param core_if Programming view of DWC_otg controller.
5054 + * @param ep The EP to start the transfer on.
5055 + */
5056 +
5057 +void dwc_otg_ep_start_transfer(dwc_otg_core_if_t *core_if, dwc_ep_t *ep)
5058 +{
5059 +       depctl_data_t   depctl;
5060 +       deptsiz_data_t  deptsiz;
5061 +       gintmsk_data_t  intr_mask = { .d32 = 0};
5062 +
5063 +       DWC_DEBUGPL((DBG_PCDV | DBG_CILV), "%s()\n", __func__);
5064 +
5065 +       DWC_DEBUGPL(DBG_PCD, "ep%d-%s xfer_len=%d xfer_cnt=%d "
5066 +               "xfer_buff=%p start_xfer_buff=%p\n",
5067 +               ep->num, (ep->is_in?"IN":"OUT"), ep->xfer_len,
5068 +               ep->xfer_count, ep->xfer_buff, ep->start_xfer_buff);
5069 +
5070 +       /* IN endpoint */
5071 +       if (ep->is_in == 1) {
5072 +               dwc_otg_dev_in_ep_regs_t *in_regs =
5073 +                       core_if->dev_if->in_ep_regs[ep->num];
5074 +
5075 +               gnptxsts_data_t gtxstatus;
5076 +
5077 +               gtxstatus.d32 =
5078 +                       dwc_read_reg32(&core_if->core_global_regs->gnptxsts);
5079 +
5080 +               if(core_if->en_multiple_tx_fifo == 0 && gtxstatus.b.nptxqspcavail == 0) {
5081 +#ifdef DEBUG
5082 +                       DWC_PRINT("TX Queue Full (0x%0x)\n", gtxstatus.d32);
5083 +#endif
5084 +                       return;
5085 +               }
5086 +
5087 +               depctl.d32 = dwc_read_reg32(&(in_regs->diepctl));
5088 +               deptsiz.d32 = dwc_read_reg32(&(in_regs->dieptsiz));
5089 +
5090 +               ep->xfer_len += (ep->maxxfer < (ep->total_len - ep->xfer_len)) ?
5091 +                               ep->maxxfer : (ep->total_len - ep->xfer_len);
5092 +
5093 +               /* Zero Length Packet? */
5094 +               if ((ep->xfer_len - ep->xfer_count) == 0) {
5095 +                       deptsiz.b.xfersize = 0;
5096 +                       deptsiz.b.pktcnt = 1;
5097 +               }
5098 +               else {
5099 +                       /* Program the transfer size and packet count
5100 +                        *      as follows: xfersize = N * maxpacket +
5101 +                        *      short_packet pktcnt = N + (short_packet
5102 +                        *      exist ? 1 : 0)
5103 +                        */
5104 +                       deptsiz.b.xfersize = ep->xfer_len - ep->xfer_count;
5105 +                       deptsiz.b.pktcnt =
5106 +                               (ep->xfer_len - ep->xfer_count - 1 + ep->maxpacket) /
5107 +                               ep->maxpacket;
5108 +               }
5109 +
5110 +
5111 +               /* Write the DMA register */
5112 +               if (core_if->dma_enable) {
5113 +                       if (core_if->dma_desc_enable == 0) {
5114 +                               dwc_write_reg32(&in_regs->dieptsiz, deptsiz.d32);
5115 +                               dwc_write_reg32 (&(in_regs->diepdma),
5116 +                                                (uint32_t)ep->dma_addr);
5117 +                       }
5118 +                       else {
5119 +                               init_dma_desc_chain(core_if, ep);
5120 +                               /** DIEPDMAn Register write */
5121 +                               dwc_write_reg32(&in_regs->diepdma, ep->dma_desc_addr);
5122 +                       }
5123 +               }
5124 +               else {
5125 +                       dwc_write_reg32(&in_regs->dieptsiz, deptsiz.d32);
5126 +                       if(ep->type != DWC_OTG_EP_TYPE_ISOC) {
5127 +                               /**
5128 +                                * Enable the Non-Periodic Tx FIFO empty interrupt,
5129 +                                * or the Tx FIFO epmty interrupt in dedicated Tx FIFO mode,
5130 +                                * the data will be written into the fifo by the ISR.
5131 +                                */
5132 +                               if(core_if->en_multiple_tx_fifo == 0) {
5133 +                                       intr_mask.b.nptxfempty = 1;
5134 +                                       dwc_modify_reg32(&core_if->core_global_regs->gintmsk,
5135 +                                               intr_mask.d32, intr_mask.d32);
5136 +                               }
5137 +                               else {
5138 +                                       /* Enable the Tx FIFO Empty Interrupt for this EP */
5139 +                                       if(ep->xfer_len > 0) {
5140 +                                               uint32_t fifoemptymsk = 0;
5141 +                                               fifoemptymsk = 1 << ep->num;
5142 +                                               dwc_modify_reg32(&core_if->dev_if->dev_global_regs->dtknqr4_fifoemptymsk,
5143 +                                               0, fifoemptymsk);
5144 +
5145 +                                       }
5146 +                               }
5147 +                       }
5148 +               }
5149 +
5150 +               /* EP enable, IN data in FIFO */
5151 +               depctl.b.cnak = 1;
5152 +               depctl.b.epena = 1;
5153 +               dwc_write_reg32(&in_regs->diepctl, depctl.d32);
5154 +
5155 +               depctl.d32 = dwc_read_reg32 (&core_if->dev_if->in_ep_regs[0]->diepctl);
5156 +               depctl.b.nextep = ep->num;
5157 +               dwc_write_reg32 (&core_if->dev_if->in_ep_regs[0]->diepctl, depctl.d32);
5158 +
5159 +       }
5160 +       else {
5161 +               /* OUT endpoint */
5162 +               dwc_otg_dev_out_ep_regs_t *out_regs =
5163 +               core_if->dev_if->out_ep_regs[ep->num];
5164 +
5165 +               depctl.d32 = dwc_read_reg32(&(out_regs->doepctl));
5166 +               deptsiz.d32 = dwc_read_reg32(&(out_regs->doeptsiz));
5167 +
5168 +               ep->xfer_len += (ep->maxxfer < (ep->total_len - ep->xfer_len)) ?
5169 +                               ep->maxxfer : (ep->total_len - ep->xfer_len);
5170 +
5171 +               /* Program the transfer size and packet count as follows:
5172 +                *
5173 +                *      pktcnt = N
5174 +                *      xfersize = N * maxpacket
5175 +                */
5176 +               if ((ep->xfer_len - ep->xfer_count) == 0) {
5177 +                       /* Zero Length Packet */
5178 +                       deptsiz.b.xfersize = ep->maxpacket;
5179 +                       deptsiz.b.pktcnt = 1;
5180 +               }
5181 +               else {
5182 +                       deptsiz.b.pktcnt =
5183 +                                       (ep->xfer_len - ep->xfer_count + (ep->maxpacket - 1)) /
5184 +                                       ep->maxpacket;
5185 +                       ep->xfer_len = deptsiz.b.pktcnt * ep->maxpacket + ep->xfer_count;
5186 +                       deptsiz.b.xfersize = ep->xfer_len - ep->xfer_count;
5187 +               }
5188 +
5189 +               DWC_DEBUGPL(DBG_PCDV, "ep%d xfersize=%d pktcnt=%d\n",
5190 +                       ep->num,
5191 +                       deptsiz.b.xfersize, deptsiz.b.pktcnt);
5192 +
5193 +               if (core_if->dma_enable) {
5194 +                       if (!core_if->dma_desc_enable) {
5195 +                               dwc_write_reg32(&out_regs->doeptsiz, deptsiz.d32);
5196 +
5197 +                               dwc_write_reg32 (&(out_regs->doepdma),
5198 +                                       (uint32_t)ep->dma_addr);
5199 +                       }
5200 +                       else {
5201 +                               init_dma_desc_chain(core_if, ep);
5202 +
5203 +                               /** DOEPDMAn Register write */
5204 +                               dwc_write_reg32(&out_regs->doepdma, ep->dma_desc_addr);
5205 +                       }
5206 +               }
5207 +               else {
5208 +                       dwc_write_reg32(&out_regs->doeptsiz, deptsiz.d32);
5209 +               }
5210 +
5211 +               /* EP enable */
5212 +               depctl.b.cnak = 1;
5213 +               depctl.b.epena = 1;
5214 +
5215 +               dwc_write_reg32(&out_regs->doepctl, depctl.d32);
5216 +
5217 +               DWC_DEBUGPL(DBG_PCD, "DOEPCTL=%08x DOEPTSIZ=%08x\n",
5218 +                       dwc_read_reg32(&out_regs->doepctl),
5219 +                       dwc_read_reg32(&out_regs->doeptsiz));
5220 +               DWC_DEBUGPL(DBG_PCD, "DAINTMSK=%08x GINTMSK=%08x\n",
5221 +                       dwc_read_reg32(&core_if->dev_if->dev_global_regs->daintmsk),
5222 +                       dwc_read_reg32(&core_if->core_global_regs->gintmsk));
5223 +       }
5224 +}
5225 +
5226 +/**
5227 + * This function setup a zero length transfer in Buffer DMA and
5228 + * Slave modes for usb requests with zero field set
5229 + *
5230 + * @param core_if Programming view of DWC_otg controller.
5231 + * @param ep The EP to start the transfer on.
5232 + *
5233 + */
5234 +void dwc_otg_ep_start_zl_transfer(dwc_otg_core_if_t *core_if, dwc_ep_t *ep)
5235 +{
5236 +
5237 +       depctl_data_t depctl;
5238 +       deptsiz_data_t deptsiz;
5239 +       gintmsk_data_t intr_mask = { .d32 = 0};
5240 +
5241 +       DWC_DEBUGPL((DBG_PCDV | DBG_CILV), "%s()\n", __func__);
5242 +
5243 +       /* IN endpoint */
5244 +       if (ep->is_in == 1) {
5245 +               dwc_otg_dev_in_ep_regs_t *in_regs =
5246 +                       core_if->dev_if->in_ep_regs[ep->num];
5247 +
5248 +               depctl.d32 = dwc_read_reg32(&(in_regs->diepctl));
5249 +               deptsiz.d32 = dwc_read_reg32(&(in_regs->dieptsiz));
5250 +
5251 +               deptsiz.b.xfersize = 0;
5252 +               deptsiz.b.pktcnt = 1;
5253 +
5254 +
5255 +               /* Write the DMA register */
5256 +               if (core_if->dma_enable) {
5257 +                       if (core_if->dma_desc_enable == 0) {
5258 +                               dwc_write_reg32(&in_regs->dieptsiz, deptsiz.d32);
5259 +                               dwc_write_reg32 (&(in_regs->diepdma),
5260 +                                                (uint32_t)ep->dma_addr);
5261 +                       }
5262 +               }
5263 +               else {
5264 +                       dwc_write_reg32(&in_regs->dieptsiz, deptsiz.d32);
5265 +                       /**
5266 +                        * Enable the Non-Periodic Tx FIFO empty interrupt,
5267 +                        * or the Tx FIFO epmty interrupt in dedicated Tx FIFO mode,
5268 +                        * the data will be written into the fifo by the ISR.
5269 +                        */
5270 +                       if(core_if->en_multiple_tx_fifo == 0) {
5271 +                               intr_mask.b.nptxfempty = 1;
5272 +                               dwc_modify_reg32(&core_if->core_global_regs->gintmsk,
5273 +                                       intr_mask.d32, intr_mask.d32);
5274 +                       }
5275 +                       else {
5276 +                               /* Enable the Tx FIFO Empty Interrupt for this EP */
5277 +                               if(ep->xfer_len > 0) {
5278 +                                       uint32_t fifoemptymsk = 0;
5279 +                                       fifoemptymsk = 1 << ep->num;
5280 +                                       dwc_modify_reg32(&core_if->dev_if->dev_global_regs->dtknqr4_fifoemptymsk,
5281 +                                       0, fifoemptymsk);
5282 +                               }
5283 +                       }
5284 +               }
5285 +
5286 +               /* EP enable, IN data in FIFO */
5287 +               depctl.b.cnak = 1;
5288 +               depctl.b.epena = 1;
5289 +               dwc_write_reg32(&in_regs->diepctl, depctl.d32);
5290 +
5291 +               depctl.d32 = dwc_read_reg32 (&core_if->dev_if->in_ep_regs[0]->diepctl);
5292 +               depctl.b.nextep = ep->num;
5293 +               dwc_write_reg32 (&core_if->dev_if->in_ep_regs[0]->diepctl, depctl.d32);
5294 +
5295 +       }
5296 +       else {
5297 +               /* OUT endpoint */
5298 +               dwc_otg_dev_out_ep_regs_t *out_regs =
5299 +               core_if->dev_if->out_ep_regs[ep->num];
5300 +
5301 +               depctl.d32 = dwc_read_reg32(&(out_regs->doepctl));
5302 +               deptsiz.d32 = dwc_read_reg32(&(out_regs->doeptsiz));
5303 +
5304 +               /* Zero Length Packet */
5305 +               deptsiz.b.xfersize = ep->maxpacket;
5306 +               deptsiz.b.pktcnt = 1;
5307 +
5308 +               if (core_if->dma_enable) {
5309 +                       if (!core_if->dma_desc_enable) {
5310 +                               dwc_write_reg32(&out_regs->doeptsiz, deptsiz.d32);
5311 +
5312 +                               dwc_write_reg32 (&(out_regs->doepdma),
5313 +                                       (uint32_t)ep->dma_addr);
5314 +                       }
5315 +               }
5316 +               else {
5317 +                       dwc_write_reg32(&out_regs->doeptsiz, deptsiz.d32);
5318 +               }
5319 +
5320 +               /* EP enable */
5321 +               depctl.b.cnak = 1;
5322 +               depctl.b.epena = 1;
5323 +
5324 +               dwc_write_reg32(&out_regs->doepctl, depctl.d32);
5325 +
5326 +       }
5327 +}
5328 +
5329 +/**
5330 + * This function does the setup for a data transfer for EP0 and starts
5331 + * the transfer.  For an IN transfer, the packets will be loaded into
5332 + * the appropriate Tx FIFO in the ISR. For OUT transfers, the packets are
5333 + * unloaded from the Rx FIFO in the ISR.
5334 + *
5335 + * @param core_if Programming view of DWC_otg controller.
5336 + * @param ep The EP0 data.
5337 + */
5338 +void dwc_otg_ep0_start_transfer(dwc_otg_core_if_t *core_if, dwc_ep_t *ep)
5339 +{
5340 +       depctl_data_t depctl;
5341 +       deptsiz0_data_t deptsiz;
5342 +       gintmsk_data_t intr_mask = { .d32 = 0};
5343 +       dwc_otg_dma_desc_t* dma_desc;
5344 +
5345 +       DWC_DEBUGPL(DBG_PCD, "ep%d-%s xfer_len=%d xfer_cnt=%d "
5346 +       "xfer_buff=%p start_xfer_buff=%p \n",
5347 +       ep->num, (ep->is_in?"IN":"OUT"), ep->xfer_len,
5348 +       ep->xfer_count, ep->xfer_buff, ep->start_xfer_buff);
5349 +
5350 +       ep->total_len = ep->xfer_len;
5351 +
5352 +       /* IN endpoint */
5353 +       if (ep->is_in == 1) {
5354 +               dwc_otg_dev_in_ep_regs_t *in_regs =
5355 +               core_if->dev_if->in_ep_regs[0];
5356 +
5357 +               gnptxsts_data_t gtxstatus;
5358 +
5359 +               gtxstatus.d32 =
5360 +                       dwc_read_reg32(&core_if->core_global_regs->gnptxsts);
5361 +
5362 +               if(core_if->en_multiple_tx_fifo == 0 && gtxstatus.b.nptxqspcavail == 0) {
5363 +#ifdef DEBUG
5364 +                       deptsiz.d32 = dwc_read_reg32(&in_regs->dieptsiz);
5365 +                       DWC_DEBUGPL(DBG_PCD,"DIEPCTL0=%0x\n",
5366 +                               dwc_read_reg32(&in_regs->diepctl));
5367 +                       DWC_DEBUGPL(DBG_PCD, "DIEPTSIZ0=%0x (sz=%d, pcnt=%d)\n",
5368 +                               deptsiz.d32,
5369 +                               deptsiz.b.xfersize, deptsiz.b.pktcnt);
5370 +                       DWC_PRINT("TX Queue or FIFO Full (0x%0x)\n",
5371 +                                 gtxstatus.d32);
5372 +#endif
5373 +                       return;
5374 +               }
5375 +
5376 +
5377 +               depctl.d32 = dwc_read_reg32(&in_regs->diepctl);
5378 +               deptsiz.d32 = dwc_read_reg32(&in_regs->dieptsiz);
5379 +
5380 +               /* Zero Length Packet? */
5381 +               if (ep->xfer_len == 0) {
5382 +                       deptsiz.b.xfersize = 0;
5383 +                       deptsiz.b.pktcnt = 1;
5384 +               }
5385 +               else {
5386 +                       /* Program the transfer size and packet count
5387 +                        *      as follows: xfersize = N * maxpacket +
5388 +                        *      short_packet pktcnt = N + (short_packet
5389 +                        *      exist ? 1 : 0)
5390 +                        */
5391 +                       if (ep->xfer_len > ep->maxpacket) {
5392 +                               ep->xfer_len = ep->maxpacket;
5393 +                               deptsiz.b.xfersize = ep->maxpacket;
5394 +                       }
5395 +                       else {
5396 +                               deptsiz.b.xfersize = ep->xfer_len;
5397 +                       }
5398 +                       deptsiz.b.pktcnt = 1;
5399 +
5400 +               }
5401 +               DWC_DEBUGPL(DBG_PCDV, "IN len=%d  xfersize=%d pktcnt=%d [%08x]\n",
5402 +                       ep->xfer_len,
5403 +                       deptsiz.b.xfersize, deptsiz.b.pktcnt, deptsiz.d32);
5404 +
5405 +               /* Write the DMA register */
5406 +               if (core_if->dma_enable) {
5407 +                       if(core_if->dma_desc_enable == 0) {
5408 +                               dwc_write_reg32(&in_regs->dieptsiz, deptsiz.d32);
5409 +
5410 +                               dwc_write_reg32 (&(in_regs->diepdma),
5411 +                               (uint32_t)ep->dma_addr);
5412 +                       }
5413 +                       else {
5414 +                               dma_desc = core_if->dev_if->in_desc_addr;
5415 +
5416 +                               /** DMA Descriptor Setup */
5417 +                               dma_desc->status.b.bs = BS_HOST_BUSY;
5418 +                               dma_desc->status.b.l = 1;
5419 +                               dma_desc->status.b.ioc = 1;
5420 +                               dma_desc->status.b.sp = (ep->xfer_len == ep->maxpacket) ? 0 : 1;
5421 +                               dma_desc->status.b.bytes = ep->xfer_len;
5422 +                               dma_desc->buf = ep->dma_addr;
5423 +                               dma_desc->status.b.bs = BS_HOST_READY;
5424 +
5425 +                               /** DIEPDMA0 Register write */
5426 +                               dwc_write_reg32(&in_regs->diepdma, core_if->dev_if->dma_in_desc_addr);
5427 +                       }
5428 +               }
5429 +               else {
5430 +                       dwc_write_reg32(&in_regs->dieptsiz, deptsiz.d32);
5431 +               }
5432 +
5433 +               /* EP enable, IN data in FIFO */
5434 +               depctl.b.cnak = 1;
5435 +               depctl.b.epena = 1;
5436 +               dwc_write_reg32(&in_regs->diepctl, depctl.d32);
5437 +
5438 +               /**
5439 +                * Enable the Non-Periodic Tx FIFO empty interrupt, the
5440 +                * data will be written into the fifo by the ISR.
5441 +                */
5442 +               if (!core_if->dma_enable) {
5443 +                       if(core_if->en_multiple_tx_fifo == 0) {
5444 +                               intr_mask.b.nptxfempty = 1;
5445 +                               dwc_modify_reg32(&core_if->core_global_regs->gintmsk,
5446 +                                       intr_mask.d32, intr_mask.d32);
5447 +                       }
5448 +                       else {
5449 +                               /* Enable the Tx FIFO Empty Interrupt for this EP */
5450 +                               if(ep->xfer_len > 0) {
5451 +                                       uint32_t fifoemptymsk = 0;
5452 +                                       fifoemptymsk |= 1 << ep->num;
5453 +                                       dwc_modify_reg32(&core_if->dev_if->dev_global_regs->dtknqr4_fifoemptymsk,
5454 +                                               0, fifoemptymsk);
5455 +                               }
5456 +                       }
5457 +               }
5458 +       }
5459 +       else {
5460 +               /* OUT endpoint */
5461 +               dwc_otg_dev_out_ep_regs_t *out_regs =
5462 +                       core_if->dev_if->out_ep_regs[0];
5463 +
5464 +               depctl.d32 = dwc_read_reg32(&out_regs->doepctl);
5465 +               deptsiz.d32 = dwc_read_reg32(&out_regs->doeptsiz);
5466 +
5467 +               /* Program the transfer size and packet count as follows:
5468 +                *      xfersize = N * (maxpacket + 4 - (maxpacket % 4))
5469 +                *      pktcnt = N                                                                                      */
5470 +               /* Zero Length Packet */
5471 +               deptsiz.b.xfersize = ep->maxpacket;
5472 +               deptsiz.b.pktcnt = 1;
5473 +
5474 +               DWC_DEBUGPL(DBG_PCDV, "len=%d  xfersize=%d pktcnt=%d\n",
5475 +                       ep->xfer_len,
5476 +                       deptsiz.b.xfersize, deptsiz.b.pktcnt);
5477 +
5478 +               if (core_if->dma_enable) {
5479 +                       if(!core_if->dma_desc_enable) {
5480 +                               dwc_write_reg32(&out_regs->doeptsiz, deptsiz.d32);
5481 +
5482 +                               dwc_write_reg32 (&(out_regs->doepdma),
5483 +                                (uint32_t)ep->dma_addr);
5484 +                       }
5485 +                       else {
5486 +                               dma_desc = core_if->dev_if->out_desc_addr;
5487 +
5488 +                               /** DMA Descriptor Setup */
5489 +                               dma_desc->status.b.bs = BS_HOST_BUSY;
5490 +                               dma_desc->status.b.l = 1;
5491 +                               dma_desc->status.b.ioc = 1;
5492 +                               dma_desc->status.b.bytes = ep->maxpacket;
5493 +                               dma_desc->buf = ep->dma_addr;
5494 +                               dma_desc->status.b.bs = BS_HOST_READY;
5495 +
5496 +                               /** DOEPDMA0 Register write */
5497 +                               dwc_write_reg32(&out_regs->doepdma, core_if->dev_if->dma_out_desc_addr);
5498 +                       }
5499 +               }
5500 +               else {
5501 +                       dwc_write_reg32(&out_regs->doeptsiz, deptsiz.d32);
5502 +               }
5503 +
5504 +               /* EP enable */
5505 +               depctl.b.cnak = 1;
5506 +               depctl.b.epena = 1;
5507 +               dwc_write_reg32 (&(out_regs->doepctl), depctl.d32);
5508 +       }
5509 +}
5510 +
5511 +/**
5512 + * This function continues control IN transfers started by
5513 + * dwc_otg_ep0_start_transfer, when the transfer does not fit in a
5514 + * single packet.  NOTE: The DIEPCTL0/DOEPCTL0 registers only have one
5515 + * bit for the packet count.
5516 + *
5517 + * @param core_if Programming view of DWC_otg controller.
5518 + * @param ep The EP0 data.
5519 + */
5520 +void dwc_otg_ep0_continue_transfer(dwc_otg_core_if_t *core_if, dwc_ep_t *ep)
5521 +{
5522 +       depctl_data_t depctl;
5523 +       deptsiz0_data_t deptsiz;
5524 +       gintmsk_data_t intr_mask = { .d32 = 0};
5525 +       dwc_otg_dma_desc_t* dma_desc;
5526 +
5527 +       if (ep->is_in == 1) {
5528 +               dwc_otg_dev_in_ep_regs_t *in_regs =
5529 +                       core_if->dev_if->in_ep_regs[0];
5530 +               gnptxsts_data_t tx_status = { .d32 = 0 };
5531 +
5532 +               tx_status.d32 = dwc_read_reg32(&core_if->core_global_regs->gnptxsts);
5533 +               /** @todo Should there be check for room in the Tx
5534 +                * Status Queue.  If not remove the code above this comment. */
5535 +
5536 +               depctl.d32 = dwc_read_reg32(&in_regs->diepctl);
5537 +               deptsiz.d32 = dwc_read_reg32(&in_regs->dieptsiz);
5538 +
5539 +               /* Program the transfer size and packet count
5540 +                *      as follows: xfersize = N * maxpacket +
5541 +                *      short_packet pktcnt = N + (short_packet
5542 +                *      exist ? 1 : 0)
5543 +                */
5544 +
5545 +
5546 +               if(core_if->dma_desc_enable == 0) {
5547 +                       deptsiz.b.xfersize = (ep->total_len - ep->xfer_count) > ep->maxpacket ? ep->maxpacket :
5548 +                                       (ep->total_len - ep->xfer_count);
5549 +                       deptsiz.b.pktcnt = 1;
5550 +                       if(core_if->dma_enable == 0) {
5551 +                               ep->xfer_len += deptsiz.b.xfersize;
5552 +                       } else {
5553 +                               ep->xfer_len = deptsiz.b.xfersize;
5554 +                       }
5555 +                       dwc_write_reg32(&in_regs->dieptsiz, deptsiz.d32);
5556 +               }
5557 +               else {
5558 +                       ep->xfer_len = (ep->total_len - ep->xfer_count) > ep->maxpacket ? ep->maxpacket :
5559 +                               (ep->total_len - ep->xfer_count);
5560 +
5561 +                       dma_desc = core_if->dev_if->in_desc_addr;
5562 +
5563 +                       /** DMA Descriptor Setup */
5564 +                       dma_desc->status.b.bs = BS_HOST_BUSY;
5565 +                       dma_desc->status.b.l = 1;
5566 +                       dma_desc->status.b.ioc = 1;
5567 +                       dma_desc->status.b.sp = (ep->xfer_len == ep->maxpacket) ? 0 : 1;
5568 +                       dma_desc->status.b.bytes = ep->xfer_len;
5569 +                       dma_desc->buf = ep->dma_addr;
5570 +                       dma_desc->status.b.bs = BS_HOST_READY;
5571 +
5572 +                       /** DIEPDMA0 Register write */
5573 +                       dwc_write_reg32(&in_regs->diepdma, core_if->dev_if->dma_in_desc_addr);
5574 +               }
5575 +
5576 +
5577 +               DWC_DEBUGPL(DBG_PCDV, "IN len=%d  xfersize=%d pktcnt=%d [%08x]\n",
5578 +                       ep->xfer_len,
5579 +                       deptsiz.b.xfersize, deptsiz.b.pktcnt, deptsiz.d32);
5580 +
5581 +               /* Write the DMA register */
5582 +               if (core_if->hwcfg2.b.architecture == DWC_INT_DMA_ARCH) {
5583 +                       if(core_if->dma_desc_enable == 0)
5584 +                               dwc_write_reg32 (&(in_regs->diepdma), (uint32_t)ep->dma_addr);
5585 +               }
5586 +
5587 +               /* EP enable, IN data in FIFO */
5588 +               depctl.b.cnak = 1;
5589 +               depctl.b.epena = 1;
5590 +               dwc_write_reg32(&in_regs->diepctl, depctl.d32);
5591 +
5592 +               /**
5593 +                * Enable the Non-Periodic Tx FIFO empty interrupt, the
5594 +                * data will be written into the fifo by the ISR.
5595 +                */
5596 +               if (!core_if->dma_enable) {
5597 +                       if(core_if->en_multiple_tx_fifo == 0) {
5598 +                               /* First clear it from GINTSTS */
5599 +                               intr_mask.b.nptxfempty = 1;
5600 +                               dwc_modify_reg32(&core_if->core_global_regs->gintmsk,
5601 +                                       intr_mask.d32, intr_mask.d32);
5602 +
5603 +                       }
5604 +                       else {
5605 +                               /* Enable the Tx FIFO Empty Interrupt for this EP */
5606 +                               if(ep->xfer_len > 0) {
5607 +                                       uint32_t fifoemptymsk = 0;
5608 +                                       fifoemptymsk |= 1 << ep->num;
5609 +                                       dwc_modify_reg32(&core_if->dev_if->dev_global_regs->dtknqr4_fifoemptymsk,
5610 +                                               0, fifoemptymsk);
5611 +                               }
5612 +                       }
5613 +               }
5614 +       }
5615 +       else {
5616 +               dwc_otg_dev_out_ep_regs_t *out_regs =
5617 +                       core_if->dev_if->out_ep_regs[0];
5618 +
5619 +
5620 +               depctl.d32 = dwc_read_reg32(&out_regs->doepctl);
5621 +               deptsiz.d32 = dwc_read_reg32(&out_regs->doeptsiz);
5622 +
5623 +               /* Program the transfer size and packet count
5624 +                *      as follows: xfersize = N * maxpacket +
5625 +                *      short_packet pktcnt = N + (short_packet
5626 +                *      exist ? 1 : 0)
5627 +                */
5628 +               deptsiz.b.xfersize = ep->maxpacket;
5629 +               deptsiz.b.pktcnt = 1;
5630 +
5631 +
5632 +               if(core_if->dma_desc_enable == 0) {
5633 +                       dwc_write_reg32(&out_regs->doeptsiz, deptsiz.d32);
5634 +               }
5635 +               else {
5636 +                       dma_desc = core_if->dev_if->out_desc_addr;
5637 +
5638 +                       /** DMA Descriptor Setup */
5639 +                       dma_desc->status.b.bs = BS_HOST_BUSY;
5640 +                       dma_desc->status.b.l = 1;
5641 +                       dma_desc->status.b.ioc = 1;
5642 +                       dma_desc->status.b.bytes = ep->maxpacket;
5643 +                       dma_desc->buf = ep->dma_addr;
5644 +                       dma_desc->status.b.bs = BS_HOST_READY;
5645 +
5646 +                       /** DOEPDMA0 Register write */
5647 +                       dwc_write_reg32(&out_regs->doepdma, core_if->dev_if->dma_out_desc_addr);
5648 +               }
5649 +
5650 +
5651 +               DWC_DEBUGPL(DBG_PCDV, "IN len=%d  xfersize=%d pktcnt=%d [%08x]\n",
5652 +                       ep->xfer_len,
5653 +                       deptsiz.b.xfersize, deptsiz.b.pktcnt, deptsiz.d32);
5654 +
5655 +               /* Write the DMA register */
5656 +               if (core_if->hwcfg2.b.architecture == DWC_INT_DMA_ARCH) {
5657 +                       if(core_if->dma_desc_enable == 0)
5658 +                               dwc_write_reg32 (&(out_regs->doepdma), (uint32_t)ep->dma_addr);
5659 +               }
5660 +
5661 +               /* EP enable, IN data in FIFO */
5662 +               depctl.b.cnak = 1;
5663 +               depctl.b.epena = 1;
5664 +               dwc_write_reg32(&out_regs->doepctl, depctl.d32);
5665 +
5666 +       }
5667 +}
5668 +
5669 +#ifdef DEBUG
5670 +void dump_msg(const u8 *buf, unsigned int length)
5671 +{
5672 +       unsigned int    start, num, i;
5673 +       char            line[52], *p;
5674 +
5675 +       if (length >= 512)
5676 +               return;
5677 +       start = 0;
5678 +       while (length > 0) {
5679 +               num = min(length, 16u);
5680 +               p = line;
5681 +               for (i = 0; i < num; ++i)
5682 +               {
5683 +                       if (i == 8)
5684 +                               *p++ = ' ';
5685 +                       sprintf(p, " %02x", buf[i]);
5686 +                       p += 3;
5687 +               }
5688 +               *p = 0;
5689 +               DWC_PRINT("%6x: %s\n", start, line);
5690 +               buf += num;
5691 +               start += num;
5692 +               length -= num;
5693 +       }
5694 +}
5695 +#else
5696 +static inline void dump_msg(const u8 *buf, unsigned int length)
5697 +{
5698 +}
5699 +#endif
5700 +
5701 +/**
5702 + * This function writes a packet into the Tx FIFO associated with the
5703 + * EP. For non-periodic EPs the non-periodic Tx FIFO is written.  For
5704 + * periodic EPs the periodic Tx FIFO associated with the EP is written
5705 + * with all packets for the next micro-frame.
5706 + *
5707 + * @param core_if Programming view of DWC_otg controller.
5708 + * @param ep The EP to write packet for.
5709 + * @param dma Indicates if DMA is being used.
5710 + */
5711 +void dwc_otg_ep_write_packet(dwc_otg_core_if_t *core_if, dwc_ep_t *ep, int dma)
5712 +{
5713 +       /**
5714 +        * The buffer is padded to DWORD on a per packet basis in
5715 +        * slave/dma mode if the MPS is not DWORD aligned.      The last
5716 +        * packet, if short, is also padded to a multiple of DWORD.
5717 +        *
5718 +        * ep->xfer_buff always starts DWORD aligned in memory and is a
5719 +        * multiple of DWORD in length
5720 +        *
5721 +        * ep->xfer_len can be any number of bytes
5722 +        *
5723 +        * ep->xfer_count is a multiple of ep->maxpacket until the last
5724 +        *      packet
5725 +        *
5726 +        * FIFO access is DWORD */
5727 +
5728 +       uint32_t i;
5729 +       uint32_t byte_count;
5730 +       uint32_t dword_count;
5731 +       uint32_t *fifo;
5732 +       uint32_t *data_buff = (uint32_t *)ep->xfer_buff;
5733 +
5734 +       DWC_DEBUGPL((DBG_PCDV | DBG_CILV), "%s(%p,%p)\n", __func__, core_if, ep);
5735 +       if (ep->xfer_count >= ep->xfer_len) {
5736 +                       DWC_WARN("%s() No data for EP%d!!!\n", __func__, ep->num);
5737 +                       return;
5738 +       }
5739 +
5740 +       /* Find the byte length of the packet either short packet or MPS */
5741 +       if ((ep->xfer_len - ep->xfer_count) < ep->maxpacket) {
5742 +               byte_count = ep->xfer_len - ep->xfer_count;
5743 +       }
5744 +       else {
5745 +               byte_count = ep->maxpacket;
5746 +       }
5747 +
5748 +       /* Find the DWORD length, padded by extra bytes as neccessary if MPS
5749 +        * is not a multiple of DWORD */
5750 +       dword_count =  (byte_count + 3) / 4;
5751 +
5752 +#ifdef VERBOSE
5753 +       dump_msg(ep->xfer_buff, byte_count);
5754 +#endif
5755 +
5756 +       /**@todo NGS Where are the Periodic Tx FIFO addresses
5757 +        * intialized?  What should this be? */
5758 +
5759 +       fifo = core_if->data_fifo[ep->num];
5760 +
5761 +
5762 +       DWC_DEBUGPL((DBG_PCDV|DBG_CILV), "fifo=%p buff=%p *p=%08x bc=%d\n", fifo, data_buff, *data_buff, byte_count);
5763 +
5764 +       if (!dma) {
5765 +               for (i=0; i<dword_count; i++, data_buff++) {
5766 +                       dwc_write_reg32(fifo, *data_buff);
5767 +               }
5768 +       }
5769 +
5770 +       ep->xfer_count += byte_count;
5771 +       ep->xfer_buff += byte_count;
5772 +       ep->dma_addr += byte_count;
5773 +}
5774 +
5775 +/**
5776 + * Set the EP STALL.
5777 + *
5778 + * @param core_if Programming view of DWC_otg controller.
5779 + * @param ep The EP to set the stall on.
5780 + */
5781 +void dwc_otg_ep_set_stall(dwc_otg_core_if_t *core_if, dwc_ep_t *ep)
5782 +{
5783 +       depctl_data_t depctl;
5784 +       volatile uint32_t *depctl_addr;
5785 +
5786 +       DWC_DEBUGPL(DBG_PCD, "%s ep%d-%s\n", __func__, ep->num,
5787 +               (ep->is_in?"IN":"OUT"));
5788 +
5789 +       DWC_PRINT("%s ep%d-%s\n", __func__, ep->num,
5790 +               (ep->is_in?"in":"out"));
5791 +
5792 +       if (ep->is_in == 1) {
5793 +               depctl_addr = &(core_if->dev_if->in_ep_regs[ep->num]->diepctl);
5794 +               depctl.d32 = dwc_read_reg32(depctl_addr);
5795 +
5796 +               /* set the disable and stall bits */
5797 +               if (depctl.b.epena) {
5798 +                       depctl.b.epdis = 1;
5799 +               }
5800 +               depctl.b.stall = 1;
5801 +               dwc_write_reg32(depctl_addr, depctl.d32);
5802 +       }
5803 +       else {
5804 +               depctl_addr = &(core_if->dev_if->out_ep_regs[ep->num]->doepctl);
5805 +               depctl.d32 = dwc_read_reg32(depctl_addr);
5806 +
5807 +               /* set the stall bit */
5808 +               depctl.b.stall = 1;
5809 +               dwc_write_reg32(depctl_addr, depctl.d32);
5810 +       }
5811 +
5812 +       DWC_DEBUGPL(DBG_PCD,"DEPCTL=%0x\n",dwc_read_reg32(depctl_addr));
5813 +
5814 +       return;
5815 +}
5816 +
5817 +/**
5818 + * Clear the EP STALL.
5819 + *
5820 + * @param core_if Programming view of DWC_otg controller.
5821 + * @param ep The EP to clear stall from.
5822 + */
5823 +void dwc_otg_ep_clear_stall(dwc_otg_core_if_t *core_if, dwc_ep_t *ep)
5824 +{
5825 +       depctl_data_t depctl;
5826 +       volatile uint32_t *depctl_addr;
5827 +
5828 +       DWC_DEBUGPL(DBG_PCD, "%s ep%d-%s\n", __func__, ep->num,
5829 +               (ep->is_in?"IN":"OUT"));
5830 +
5831 +       if (ep->is_in == 1) {
5832 +               depctl_addr = &(core_if->dev_if->in_ep_regs[ep->num]->diepctl);
5833 +       }
5834 +       else {
5835 +               depctl_addr = &(core_if->dev_if->out_ep_regs[ep->num]->doepctl);
5836 +       }
5837 +
5838 +       depctl.d32 = dwc_read_reg32(depctl_addr);
5839 +
5840 +       /* clear the stall bits */
5841 +       depctl.b.stall = 0;
5842 +
5843 +       /*
5844 +        * USB Spec 9.4.5: For endpoints using data toggle, regardless
5845 +        * of whether an endpoint has the Halt feature set, a
5846 +        * ClearFeature(ENDPOINT_HALT) request always results in the
5847 +        * data toggle being reinitialized to DATA0.
5848 +        */
5849 +       if (ep->type == DWC_OTG_EP_TYPE_INTR ||
5850 +               ep->type == DWC_OTG_EP_TYPE_BULK) {
5851 +               depctl.b.setd0pid = 1; /* DATA0 */
5852 +       }
5853 +
5854 +       dwc_write_reg32(depctl_addr, depctl.d32);
5855 +       DWC_DEBUGPL(DBG_PCD,"DEPCTL=%0x\n",dwc_read_reg32(depctl_addr));
5856 +       return;
5857 +}
5858 +
5859 +/**
5860 + * This function reads a packet from the Rx FIFO into the destination
5861 + * buffer.     To read SETUP data use dwc_otg_read_setup_packet.
5862 + *
5863 + * @param core_if Programming view of DWC_otg controller.
5864 + * @param dest   Destination buffer for the packet.
5865 + * @param bytes  Number of bytes to copy to the destination.
5866 + */
5867 +void dwc_otg_read_packet(dwc_otg_core_if_t *core_if,
5868 +                        uint8_t *dest,
5869 +                        uint16_t bytes)
5870 +{
5871 +       int i;
5872 +       int word_count = (bytes + 3) / 4;
5873 +
5874 +       volatile uint32_t *fifo = core_if->data_fifo[0];
5875 +       uint32_t *data_buff = (uint32_t *)dest;
5876 +
5877 +       /**
5878 +        * @todo Account for the case where _dest is not dword aligned. This
5879 +        * requires reading data from the FIFO into a uint32_t temp buffer,
5880 +        * then moving it into the data buffer.
5881 +        */
5882 +
5883 +       DWC_DEBUGPL((DBG_PCDV | DBG_CILV), "%s(%p,%p,%d)\n", __func__,
5884 +                                       core_if, dest, bytes);
5885 +
5886 +       for (i=0; i<word_count; i++, data_buff++)
5887 +       {
5888 +               *data_buff = dwc_read_reg32(fifo);
5889 +       }
5890 +
5891 +       return;
5892 +}
5893 +
5894 +
5895 +
5896 +/**
5897 + * This functions reads the device registers and prints them
5898 + *
5899 + * @param core_if Programming view of DWC_otg controller.
5900 + */
5901 +void dwc_otg_dump_dev_registers(dwc_otg_core_if_t *core_if)
5902 +{
5903 +       int i;
5904 +       volatile uint32_t *addr;
5905 +
5906 +       DWC_PRINT("Device Global Registers\n");
5907 +       addr=&core_if->dev_if->dev_global_regs->dcfg;
5908 +       DWC_PRINT("DCFG          @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
5909 +       addr=&core_if->dev_if->dev_global_regs->dctl;
5910 +       DWC_PRINT("DCTL          @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
5911 +       addr=&core_if->dev_if->dev_global_regs->dsts;
5912 +       DWC_PRINT("DSTS          @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
5913 +       addr=&core_if->dev_if->dev_global_regs->diepmsk;
5914 +       DWC_PRINT("DIEPMSK       @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
5915 +       addr=&core_if->dev_if->dev_global_regs->doepmsk;
5916 +       DWC_PRINT("DOEPMSK       @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
5917 +       addr=&core_if->dev_if->dev_global_regs->daint;
5918 +       DWC_PRINT("DAINT         @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
5919 +       addr=&core_if->dev_if->dev_global_regs->daintmsk;
5920 +       DWC_PRINT("DAINTMSK      @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
5921 +       addr=&core_if->dev_if->dev_global_regs->dtknqr1;
5922 +       DWC_PRINT("DTKNQR1       @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
5923 +       if (core_if->hwcfg2.b.dev_token_q_depth > 6) {
5924 +               addr=&core_if->dev_if->dev_global_regs->dtknqr2;
5925 +               DWC_PRINT("DTKNQR2       @0x%08X : 0x%08X\n",
5926 +                 (uint32_t)addr,dwc_read_reg32(addr));
5927 +       }
5928 +
5929 +       addr=&core_if->dev_if->dev_global_regs->dvbusdis;
5930 +       DWC_PRINT("DVBUSID       @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
5931 +
5932 +       addr=&core_if->dev_if->dev_global_regs->dvbuspulse;
5933 +       DWC_PRINT("DVBUSPULSE   @0x%08X : 0x%08X\n",
5934 +                                 (uint32_t)addr,dwc_read_reg32(addr));
5935 +
5936 +       if (core_if->hwcfg2.b.dev_token_q_depth > 14) {
5937 +               addr=&core_if->dev_if->dev_global_regs->dtknqr3_dthrctl;
5938 +               DWC_PRINT("DTKNQR3_DTHRCTL       @0x%08X : 0x%08X\n",
5939 +                 (uint32_t)addr, dwc_read_reg32(addr));
5940 +       }
5941 +/*
5942 +       if (core_if->hwcfg2.b.dev_token_q_depth > 22) {
5943 +               addr=&core_if->dev_if->dev_global_regs->dtknqr4_fifoemptymsk;
5944 +               DWC_PRINT("DTKNQR4       @0x%08X : 0x%08X\n",
5945 +                                 (uint32_t)addr, dwc_read_reg32(addr));
5946 +       }
5947 +*/
5948 +       addr=&core_if->dev_if->dev_global_regs->dtknqr4_fifoemptymsk;
5949 +       DWC_PRINT("FIFOEMPMSK    @0x%08X : 0x%08X\n", (uint32_t)addr, dwc_read_reg32(addr));
5950 +
5951 +       addr=&core_if->dev_if->dev_global_regs->deachint;
5952 +       DWC_PRINT("DEACHINT      @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
5953 +       addr=&core_if->dev_if->dev_global_regs->deachintmsk;
5954 +       DWC_PRINT("DEACHINTMSK   @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
5955 +
5956 +       for (i=0; i<= core_if->dev_if->num_in_eps; i++) {
5957 +               addr=&core_if->dev_if->dev_global_regs->diepeachintmsk[i];
5958 +               DWC_PRINT("DIEPEACHINTMSK[%d]    @0x%08X : 0x%08X\n", i, (uint32_t)addr, dwc_read_reg32(addr));
5959 +       }
5960 +
5961 +
5962 +       for (i=0; i<= core_if->dev_if->num_out_eps; i++) {
5963 +               addr=&core_if->dev_if->dev_global_regs->doepeachintmsk[i];
5964 +               DWC_PRINT("DOEPEACHINTMSK[%d]    @0x%08X : 0x%08X\n", i, (uint32_t)addr, dwc_read_reg32(addr));
5965 +       }
5966 +
5967 +       for (i=0; i<= core_if->dev_if->num_in_eps; i++) {
5968 +               DWC_PRINT("Device IN EP %d Registers\n", i);
5969 +               addr=&core_if->dev_if->in_ep_regs[i]->diepctl;
5970 +               DWC_PRINT("DIEPCTL       @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
5971 +               addr=&core_if->dev_if->in_ep_regs[i]->diepint;
5972 +               DWC_PRINT("DIEPINT       @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
5973 +               addr=&core_if->dev_if->in_ep_regs[i]->dieptsiz;
5974 +               DWC_PRINT("DIETSIZ       @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
5975 +               addr=&core_if->dev_if->in_ep_regs[i]->diepdma;
5976 +               DWC_PRINT("DIEPDMA       @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
5977 +               addr=&core_if->dev_if->in_ep_regs[i]->dtxfsts;
5978 +               DWC_PRINT("DTXFSTS       @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
5979 +               addr=&core_if->dev_if->in_ep_regs[i]->diepdmab;
5980 +               DWC_PRINT("DIEPDMAB      @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
5981 +       }
5982 +
5983 +
5984 +       for (i=0; i<= core_if->dev_if->num_out_eps; i++) {
5985 +               DWC_PRINT("Device OUT EP %d Registers\n", i);
5986 +               addr=&core_if->dev_if->out_ep_regs[i]->doepctl;
5987 +               DWC_PRINT("DOEPCTL       @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
5988 +               addr=&core_if->dev_if->out_ep_regs[i]->doepfn;
5989 +               DWC_PRINT("DOEPFN        @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
5990 +               addr=&core_if->dev_if->out_ep_regs[i]->doepint;
5991 +               DWC_PRINT("DOEPINT       @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
5992 +               addr=&core_if->dev_if->out_ep_regs[i]->doeptsiz;
5993 +               DWC_PRINT("DOETSIZ       @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
5994 +               addr=&core_if->dev_if->out_ep_regs[i]->doepdma;
5995 +               DWC_PRINT("DOEPDMA       @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
5996 +               addr=&core_if->dev_if->out_ep_regs[i]->doepdmab;
5997 +               DWC_PRINT("DOEPDMAB      @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
5998 +
5999 +       }
6000 +
6001 +
6002 +
6003 +       return;
6004 +}
6005 +
6006 +/**
6007 + * This functions reads the SPRAM and prints its content
6008 + *
6009 + * @param core_if Programming view of DWC_otg controller.
6010 + */
6011 +void dwc_otg_dump_spram(dwc_otg_core_if_t *core_if)
6012 +{
6013 +       volatile uint8_t *addr, *start_addr, *end_addr;
6014 +
6015 +       DWC_PRINT("SPRAM Data:\n");
6016 +       start_addr = (void*)core_if->core_global_regs;
6017 +       DWC_PRINT("Base Address: 0x%8X\n", (uint32_t)start_addr);
6018 +       start_addr += 0x00028000;
6019 +       end_addr=(void*)core_if->core_global_regs;
6020 +       end_addr += 0x000280e0;
6021 +
6022 +       for(addr = start_addr; addr < end_addr; addr+=16)
6023 +       {
6024 +               DWC_PRINT("0x%8X:\t%2X %2X %2X %2X %2X %2X %2X %2X %2X %2X %2X %2X %2X %2X %2X %2X\n", (uint32_t)addr,
6025 +                       addr[0],
6026 +                       addr[1],
6027 +                       addr[2],
6028 +                       addr[3],
6029 +                       addr[4],
6030 +                       addr[5],
6031 +                       addr[6],
6032 +                       addr[7],
6033 +                       addr[8],
6034 +                       addr[9],
6035 +                       addr[10],
6036 +                       addr[11],
6037 +                       addr[12],
6038 +                       addr[13],
6039 +                       addr[14],
6040 +                       addr[15]
6041 +                       );
6042 +       }
6043 +
6044 +       return;
6045 +}
6046 +/**
6047 + * This function reads the host registers and prints them
6048 + *
6049 + * @param core_if Programming view of DWC_otg controller.
6050 + */
6051 +void dwc_otg_dump_host_registers(dwc_otg_core_if_t *core_if)
6052 +{
6053 +       int i;
6054 +       volatile uint32_t *addr;
6055 +
6056 +       DWC_PRINT("Host Global Registers\n");
6057 +       addr=&core_if->host_if->host_global_regs->hcfg;
6058 +       DWC_PRINT("HCFG          @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
6059 +       addr=&core_if->host_if->host_global_regs->hfir;
6060 +       DWC_PRINT("HFIR          @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
6061 +       addr=&core_if->host_if->host_global_regs->hfnum;
6062 +       DWC_PRINT("HFNUM         @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
6063 +       addr=&core_if->host_if->host_global_regs->hptxsts;
6064 +       DWC_PRINT("HPTXSTS       @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
6065 +       addr=&core_if->host_if->host_global_regs->haint;
6066 +       DWC_PRINT("HAINT         @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
6067 +       addr=&core_if->host_if->host_global_regs->haintmsk;
6068 +       DWC_PRINT("HAINTMSK      @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
6069 +       addr=core_if->host_if->hprt0;
6070 +       DWC_PRINT("HPRT0         @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
6071 +
6072 +       for (i=0; i<core_if->core_params->host_channels; i++)
6073 +       {
6074 +               DWC_PRINT("Host Channel %d Specific Registers\n", i);
6075 +               addr=&core_if->host_if->hc_regs[i]->hcchar;
6076 +               DWC_PRINT("HCCHAR        @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
6077 +               addr=&core_if->host_if->hc_regs[i]->hcsplt;
6078 +               DWC_PRINT("HCSPLT        @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
6079 +               addr=&core_if->host_if->hc_regs[i]->hcint;
6080 +               DWC_PRINT("HCINT         @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
6081 +               addr=&core_if->host_if->hc_regs[i]->hcintmsk;
6082 +               DWC_PRINT("HCINTMSK      @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
6083 +               addr=&core_if->host_if->hc_regs[i]->hctsiz;
6084 +               DWC_PRINT("HCTSIZ        @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
6085 +               addr=&core_if->host_if->hc_regs[i]->hcdma;
6086 +               DWC_PRINT("HCDMA         @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
6087 +       }
6088 +       return;
6089 +}
6090 +
6091 +/**
6092 + * This function reads the core global registers and prints them
6093 + *
6094 + * @param core_if Programming view of DWC_otg controller.
6095 + */
6096 +void dwc_otg_dump_global_registers(dwc_otg_core_if_t *core_if)
6097 +{
6098 +       int i;
6099 +       volatile uint32_t *addr;
6100 +
6101 +       DWC_PRINT("Core Global Registers\n");
6102 +       addr=&core_if->core_global_regs->gotgctl;
6103 +       DWC_PRINT("GOTGCTL       @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
6104 +       addr=&core_if->core_global_regs->gotgint;
6105 +       DWC_PRINT("GOTGINT       @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
6106 +       addr=&core_if->core_global_regs->gahbcfg;
6107 +       DWC_PRINT("GAHBCFG       @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
6108 +       addr=&core_if->core_global_regs->gusbcfg;
6109 +       DWC_PRINT("GUSBCFG       @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
6110 +       addr=&core_if->core_global_regs->grstctl;
6111 +       DWC_PRINT("GRSTCTL       @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
6112 +       addr=&core_if->core_global_regs->gintsts;
6113 +       DWC_PRINT("GINTSTS       @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
6114 +       addr=&core_if->core_global_regs->gintmsk;
6115 +       DWC_PRINT("GINTMSK       @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
6116 +       addr=&core_if->core_global_regs->grxstsr;
6117 +       DWC_PRINT("GRXSTSR       @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
6118 +       //addr=&core_if->core_global_regs->grxstsp;
6119 +       //DWC_PRINT("GRXSTSP   @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
6120 +       addr=&core_if->core_global_regs->grxfsiz;
6121 +       DWC_PRINT("GRXFSIZ       @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
6122 +       addr=&core_if->core_global_regs->gnptxfsiz;
6123 +       DWC_PRINT("GNPTXFSIZ @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
6124 +       addr=&core_if->core_global_regs->gnptxsts;
6125 +       DWC_PRINT("GNPTXSTS      @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
6126 +       addr=&core_if->core_global_regs->gi2cctl;
6127 +       DWC_PRINT("GI2CCTL       @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
6128 +       addr=&core_if->core_global_regs->gpvndctl;
6129 +       DWC_PRINT("GPVNDCTL      @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
6130 +       addr=&core_if->core_global_regs->ggpio;
6131 +       DWC_PRINT("GGPIO         @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
6132 +       addr=&core_if->core_global_regs->guid;
6133 +       DWC_PRINT("GUID          @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
6134 +       addr=&core_if->core_global_regs->gsnpsid;
6135 +       DWC_PRINT("GSNPSID       @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
6136 +       addr=&core_if->core_global_regs->ghwcfg1;
6137 +       DWC_PRINT("GHWCFG1       @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
6138 +       addr=&core_if->core_global_regs->ghwcfg2;
6139 +       DWC_PRINT("GHWCFG2       @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
6140 +       addr=&core_if->core_global_regs->ghwcfg3;
6141 +       DWC_PRINT("GHWCFG3       @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
6142 +       addr=&core_if->core_global_regs->ghwcfg4;
6143 +       DWC_PRINT("GHWCFG4       @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
6144 +       addr=&core_if->core_global_regs->hptxfsiz;
6145 +       DWC_PRINT("HPTXFSIZ      @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
6146 +
6147 +       for (i=0; i<core_if->hwcfg4.b.num_dev_perio_in_ep; i++)
6148 +       {
6149 +               addr=&core_if->core_global_regs->dptxfsiz_dieptxf[i];
6150 +               DWC_PRINT("DPTXFSIZ[%d] @0x%08X : 0x%08X\n",i,(uint32_t)addr,dwc_read_reg32(addr));
6151 +       }
6152 +}
6153 +
6154 +/**
6155 + * Flush a Tx FIFO.
6156 + *
6157 + * @param core_if Programming view of DWC_otg controller.
6158 + * @param num Tx FIFO to flush.
6159 + */
6160 +void dwc_otg_flush_tx_fifo(dwc_otg_core_if_t *core_if,
6161 +                                          const int num)
6162 +{
6163 +       dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs;
6164 +       volatile grstctl_t greset = { .d32 = 0};
6165 +       int count = 0;
6166 +
6167 +       DWC_DEBUGPL((DBG_CIL|DBG_PCDV), "Flush Tx FIFO %d\n", num);
6168 +
6169 +       greset.b.txfflsh = 1;
6170 +       greset.b.txfnum = num;
6171 +       dwc_write_reg32(&global_regs->grstctl, greset.d32);
6172 +
6173 +       do {
6174 +               greset.d32 = dwc_read_reg32(&global_regs->grstctl);
6175 +               if (++count > 10000) {
6176 +                       DWC_WARN("%s() HANG! GRSTCTL=%0x GNPTXSTS=0x%08x\n",
6177 +                                         __func__, greset.d32,
6178 +                       dwc_read_reg32(&global_regs->gnptxsts));
6179 +                       break;
6180 +               }
6181 +       }
6182 +       while (greset.b.txfflsh == 1);
6183 +
6184 +       /* Wait for 3 PHY Clocks*/
6185 +       UDELAY(1);
6186 +}
6187 +
6188 +/**
6189 + * Flush Rx FIFO.
6190 + *
6191 + * @param core_if Programming view of DWC_otg controller.
6192 + */
6193 +void dwc_otg_flush_rx_fifo(dwc_otg_core_if_t *core_if)
6194 +{
6195 +       dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs;
6196 +       volatile grstctl_t greset = { .d32 = 0};
6197 +       int count = 0;
6198 +
6199 +       DWC_DEBUGPL((DBG_CIL|DBG_PCDV), "%s\n", __func__);
6200 +       /*
6201 +        *
6202 +        */
6203 +       greset.b.rxfflsh = 1;
6204 +       dwc_write_reg32(&global_regs->grstctl, greset.d32);
6205 +
6206 +       do {
6207 +               greset.d32 = dwc_read_reg32(&global_regs->grstctl);
6208 +               if (++count > 10000) {
6209 +                       DWC_WARN("%s() HANG! GRSTCTL=%0x\n", __func__,
6210 +                               greset.d32);
6211 +                       break;
6212 +               }
6213 +       }
6214 +       while (greset.b.rxfflsh == 1);
6215 +
6216 +       /* Wait for 3 PHY Clocks*/
6217 +       UDELAY(1);
6218 +}
6219 +
6220 +/**
6221 + * Do core a soft reset of the core.  Be careful with this because it
6222 + * resets all the internal state machines of the core.
6223 + */
6224 +void dwc_otg_core_reset(dwc_otg_core_if_t *core_if)
6225 +{
6226 +       dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs;
6227 +       volatile grstctl_t greset = { .d32 = 0};
6228 +       int count = 0;
6229 +
6230 +       DWC_DEBUGPL(DBG_CILV, "%s\n", __func__);
6231 +       /* Wait for AHB master IDLE state. */
6232 +       do {
6233 +               UDELAY(10);
6234 +               greset.d32 = dwc_read_reg32(&global_regs->grstctl);
6235 +               if (++count > 100000) {
6236 +                       DWC_WARN("%s() HANG! AHB Idle GRSTCTL=%0x\n", __func__,
6237 +                               greset.d32);
6238 +                       return;
6239 +               }
6240 +       }
6241 +       while (greset.b.ahbidle == 0);
6242 +
6243 +       /* Core Soft Reset */
6244 +       count = 0;
6245 +       greset.b.csftrst = 1;
6246 +       dwc_write_reg32(&global_regs->grstctl, greset.d32);
6247 +       do {
6248 +               greset.d32 = dwc_read_reg32(&global_regs->grstctl);
6249 +               if (++count > 10000) {
6250 +                       DWC_WARN("%s() HANG! Soft Reset GRSTCTL=%0x\n", __func__,
6251 +                               greset.d32);
6252 +                       break;
6253 +               }
6254 +       }
6255 +       while (greset.b.csftrst == 1);
6256 +
6257 +       /* Wait for 3 PHY Clocks*/
6258 +       MDELAY(100);
6259 +}
6260 +
6261 +
6262 +
6263 +/**
6264 + * Register HCD callbacks.     The callbacks are used to start and stop
6265 + * the HCD for interrupt processing.
6266 + *
6267 + * @param core_if Programming view of DWC_otg controller.
6268 + * @param cb the HCD callback structure.
6269 + * @param p pointer to be passed to callback function (usb_hcd*).
6270 + */
6271 +void dwc_otg_cil_register_hcd_callbacks(dwc_otg_core_if_t *core_if,
6272 +                                               dwc_otg_cil_callbacks_t *cb,
6273 +                                               void *p)
6274 +{
6275 +       core_if->hcd_cb = cb;
6276 +       cb->p = p;
6277 +}
6278 +
6279 +/**
6280 + * Register PCD callbacks.     The callbacks are used to start and stop
6281 + * the PCD for interrupt processing.
6282 + *
6283 + * @param core_if Programming view of DWC_otg controller.
6284 + * @param cb the PCD callback structure.
6285 + * @param p pointer to be passed to callback function (pcd*).
6286 + */
6287 +void dwc_otg_cil_register_pcd_callbacks(dwc_otg_core_if_t *core_if,
6288 +                                               dwc_otg_cil_callbacks_t *cb,
6289 +                                               void *p)
6290 +{
6291 +       core_if->pcd_cb = cb;
6292 +       cb->p = p;
6293 +}
6294 +
6295 +#ifdef DWC_EN_ISOC
6296 +
6297 +/**
6298 + * This function writes isoc data per 1 (micro)frame into tx fifo
6299 + *
6300 + * @param core_if Programming view of DWC_otg controller.
6301 + * @param ep The EP to start the transfer on.
6302 + *
6303 + */
6304 +void write_isoc_frame_data(dwc_otg_core_if_t *core_if, dwc_ep_t *ep)
6305 +{
6306 +       dwc_otg_dev_in_ep_regs_t *ep_regs;
6307 +       dtxfsts_data_t txstatus = {.d32 = 0};
6308 +       uint32_t len = 0;
6309 +       uint32_t dwords;
6310 +
6311 +       ep->xfer_len = ep->data_per_frame;
6312 +       ep->xfer_count = 0;
6313 +
6314 +       ep_regs = core_if->dev_if->in_ep_regs[ep->num];
6315 +
6316 +       len = ep->xfer_len - ep->xfer_count;
6317 +
6318 +       if (len > ep->maxpacket) {
6319 +               len = ep->maxpacket;
6320 +       }
6321 +
6322 +       dwords = (len + 3)/4;
6323 +
6324 +       /* While there is space in the queue and space in the FIFO and
6325 +        * More data to tranfer, Write packets to the Tx FIFO */
6326 +       txstatus.d32 = dwc_read_reg32(&core_if->dev_if->in_ep_regs[ep->num]->dtxfsts);
6327 +       DWC_DEBUGPL(DBG_PCDV, "b4 dtxfsts[%d]=0x%08x\n",ep->num,txstatus.d32);
6328 +
6329 +       while  (txstatus.b.txfspcavail > dwords &&
6330 +               ep->xfer_count < ep->xfer_len &&
6331 +               ep->xfer_len != 0) {
6332 +               /* Write the FIFO */
6333 +               dwc_otg_ep_write_packet(core_if, ep, 0);
6334 +
6335 +               len = ep->xfer_len - ep->xfer_count;
6336 +               if (len > ep->maxpacket) {
6337 +                       len = ep->maxpacket;
6338 +               }
6339 +
6340 +               dwords = (len + 3)/4;
6341 +               txstatus.d32 = dwc_read_reg32(&core_if->dev_if->in_ep_regs[ep->num]->dtxfsts);
6342 +               DWC_DEBUGPL(DBG_PCDV,"dtxfsts[%d]=0x%08x\n", ep->num, txstatus.d32);
6343 +       }
6344 +}
6345 +
6346 +
6347 +/**
6348 + * This function initializes a descriptor chain for Isochronous transfer
6349 + *
6350 + * @param core_if Programming view of DWC_otg controller.
6351 + * @param ep The EP to start the transfer on.
6352 + *
6353 + */
6354 +void dwc_otg_iso_ep_start_frm_transfer(dwc_otg_core_if_t *core_if, dwc_ep_t *ep)
6355 +{
6356 +       deptsiz_data_t          deptsiz = { .d32 = 0 };
6357 +       depctl_data_t           depctl = { .d32 = 0 };
6358 +       dsts_data_t             dsts = { .d32 = 0 };
6359 +       volatile uint32_t       *addr;
6360 +
6361 +       if(ep->is_in) {
6362 +               addr = &core_if->dev_if->in_ep_regs[ep->num]->diepctl;
6363 +       } else {
6364 +               addr = &core_if->dev_if->out_ep_regs[ep->num]->doepctl;
6365 +       }
6366 +
6367 +       ep->xfer_len = ep->data_per_frame;
6368 +       ep->xfer_count = 0;
6369 +       ep->xfer_buff = ep->cur_pkt_addr;
6370 +       ep->dma_addr = ep->cur_pkt_dma_addr;
6371 +
6372 +       if(ep->is_in) {
6373 +               /* Program the transfer size and packet count
6374 +                *      as follows: xfersize = N * maxpacket +
6375 +                *      short_packet pktcnt = N + (short_packet
6376 +                *      exist ? 1 : 0)
6377 +                */
6378 +               deptsiz.b.xfersize = ep->xfer_len;
6379 +               deptsiz.b.pktcnt =
6380 +                       (ep->xfer_len - 1 + ep->maxpacket) /
6381 +                       ep->maxpacket;
6382 +               deptsiz.b.mc = deptsiz.b.pktcnt;
6383 +               dwc_write_reg32(&core_if->dev_if->in_ep_regs[ep->num]->dieptsiz, deptsiz.d32);
6384 +
6385 +               /* Write the DMA register */
6386 +               if (core_if->dma_enable) {
6387 +                       dwc_write_reg32 (&(core_if->dev_if->in_ep_regs[ep->num]->diepdma), (uint32_t)ep->dma_addr);
6388 +               }
6389 +       } else {
6390 +               deptsiz.b.pktcnt =
6391 +                               (ep->xfer_len + (ep->maxpacket - 1)) /
6392 +                               ep->maxpacket;
6393 +               deptsiz.b.xfersize = deptsiz.b.pktcnt * ep->maxpacket;
6394 +
6395 +               dwc_write_reg32(&core_if->dev_if->out_ep_regs[ep->num]->doeptsiz, deptsiz.d32);
6396 +
6397 +               if (core_if->dma_enable) {
6398 +                               dwc_write_reg32 (&(core_if->dev_if->out_ep_regs[ep->num]->doepdma),
6399 +                                       (uint32_t)ep->dma_addr);
6400 +               }
6401 +       }
6402 +
6403 +
6404 +       /** Enable endpoint, clear nak  */
6405 +
6406 +       depctl.d32 = 0;
6407 +       if(ep->bInterval == 1) {
6408 +               dsts.d32 = dwc_read_reg32(&core_if->dev_if->dev_global_regs->dsts);
6409 +               ep->next_frame = dsts.b.soffn + ep->bInterval;
6410 +
6411 +               if(ep->next_frame & 0x1) {
6412 +                       depctl.b.setd1pid = 1;
6413 +               } else {
6414 +                       depctl.b.setd0pid = 1;
6415 +               }
6416 +       } else {
6417 +               ep->next_frame += ep->bInterval;
6418 +
6419 +               if(ep->next_frame & 0x1) {
6420 +                       depctl.b.setd1pid = 1;
6421 +               } else {
6422 +                       depctl.b.setd0pid = 1;
6423 +               }
6424 +       }
6425 +       depctl.b.epena = 1;
6426 +       depctl.b.cnak = 1;
6427 +
6428 +       dwc_modify_reg32(addr, 0, depctl.d32);
6429 +       depctl.d32 = dwc_read_reg32(addr);
6430 +
6431 +       if(ep->is_in && core_if->dma_enable == 0) {
6432 +               write_isoc_frame_data(core_if, ep);
6433 +       }
6434 +
6435 +}
6436 +
6437 +#endif //DWC_EN_ISOC
6438 --- /dev/null
6439 +++ b/drivers/usb/dwc_otg/dwc_otg_cil.h
6440 @@ -0,0 +1,1098 @@
6441 +/* ==========================================================================
6442 + * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_cil.h $
6443 + * $Revision: 1.2 $
6444 + * $Date: 2008-11-21 05:39:15 $
6445 + * $Change: 1099526 $
6446 + *
6447 + * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
6448 + * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
6449 + * otherwise expressly agreed to in writing between Synopsys and you.
6450 + *
6451 + * The Software IS NOT an item of Licensed Software or Licensed Product under
6452 + * any End User Software License Agreement or Agreement for Licensed Product
6453 + * with Synopsys or any supplement thereto. You are permitted to use and
6454 + * redistribute this Software in source and binary forms, with or without
6455 + * modification, provided that redistributions of source code must retain this
6456 + * notice. You may not view, use, disclose, copy or distribute this file or
6457 + * any information contained herein except pursuant to this license grant from
6458 + * Synopsys. If you do not agree with this notice, including the disclaimer
6459 + * below, then you are not authorized to use the Software.
6460 + *
6461 + * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
6462 + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
6463 + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
6464 + * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
6465 + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
6466 + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
6467 + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
6468 + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
6469 + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
6470 + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
6471 + * DAMAGE.
6472 + * ========================================================================== */
6473 +
6474 +#if !defined(__DWC_CIL_H__)
6475 +#define __DWC_CIL_H__
6476 +
6477 +#include <linux/workqueue.h>
6478 +#include <linux/version.h>
6479 +#include <asm/param.h>
6480 +
6481 +#include "linux/dwc_otg_plat.h"
6482 +#include "dwc_otg_regs.h"
6483 +#ifdef DEBUG
6484 +#include "linux/timer.h"
6485 +#endif
6486 +
6487 +/**
6488 + * @file
6489 + * This file contains the interface to the Core Interface Layer.
6490 + */
6491 +
6492 +
6493 +/** Macros defined for DWC OTG HW Release verison */
6494 +#define OTG_CORE_REV_2_00      0x4F542000
6495 +#define OTG_CORE_REV_2_60a     0x4F54260A
6496 +#define OTG_CORE_REV_2_71a     0x4F54271A
6497 +#define OTG_CORE_REV_2_72a     0x4F54272A
6498 +
6499 +/**
6500 +*/
6501 +typedef struct iso_pkt_info
6502 +{
6503 +       uint32_t        offset;
6504 +       uint32_t        length;
6505 +       int32_t         status;
6506 +} iso_pkt_info_t;
6507 +/**
6508 + * The <code>dwc_ep</code> structure represents the state of a single
6509 + * endpoint when acting in device mode. It contains the data items
6510 + * needed for an endpoint to be activated and transfer packets.
6511 + */
6512 +typedef struct dwc_ep
6513 +{
6514 +       /** EP number used for register address lookup */
6515 +       uint8_t  num;
6516 +       /** EP direction 0 = OUT */
6517 +       unsigned is_in : 1;
6518 +       /** EP active. */
6519 +       unsigned active : 1;
6520 +
6521 +       /** Periodic Tx FIFO # for IN EPs For INTR EP set to 0 to use non-periodic Tx FIFO
6522 +               If dedicated Tx FIFOs are enabled for all IN Eps - Tx FIFO # FOR IN EPs*/
6523 +       unsigned tx_fifo_num : 4;
6524 +       /** EP type: 0 - Control, 1 - ISOC,      2 - BULK,      3 - INTR */
6525 +       unsigned type : 2;
6526 +#define DWC_OTG_EP_TYPE_CONTROL           0
6527 +#define DWC_OTG_EP_TYPE_ISOC      1
6528 +#define DWC_OTG_EP_TYPE_BULK      2
6529 +#define DWC_OTG_EP_TYPE_INTR      3
6530 +
6531 +       /** DATA start PID for INTR and BULK EP */
6532 +       unsigned data_pid_start : 1;
6533 +       /** Frame (even/odd) for ISOC EP */
6534 +       unsigned even_odd_frame : 1;
6535 +       /** Max Packet bytes */
6536 +       unsigned maxpacket : 11;
6537 +
6538 +       /** Max Transfer size */
6539 +       unsigned maxxfer : 16;
6540 +
6541 +       /** @name Transfer state */
6542 +       /** @{ */
6543 +
6544 +       /**
6545 +        * Pointer to the beginning of the transfer buffer -- do not modify
6546 +        * during transfer.
6547 +        */
6548 +
6549 +       uint32_t dma_addr;
6550 +
6551 +       uint32_t dma_desc_addr;
6552 +       dwc_otg_dma_desc_t* desc_addr;
6553 +
6554 +
6555 +       uint8_t *start_xfer_buff;
6556 +       /** pointer to the transfer buffer */
6557 +       uint8_t *xfer_buff;
6558 +       /** Number of bytes to transfer */
6559 +       unsigned xfer_len : 19;
6560 +       /** Number of bytes transferred. */
6561 +       unsigned xfer_count : 19;
6562 +       /** Sent ZLP */
6563 +       unsigned sent_zlp : 1;
6564 +       /** Total len for control transfer */
6565 +       unsigned total_len : 19;
6566 +
6567 +       /** stall clear flag */
6568 +       unsigned stall_clear_flag : 1;
6569 +
6570 +       /** Allocated DMA Desc count */
6571 +       uint32_t        desc_cnt;
6572 +
6573 +#ifdef DWC_EN_ISOC
6574 +       /**
6575 +        * Variables specific for ISOC EPs
6576 +        *
6577 +        */
6578 +       /** DMA addresses of ISOC buffers */
6579 +       uint32_t        dma_addr0;
6580 +       uint32_t        dma_addr1;
6581 +
6582 +       uint32_t        iso_dma_desc_addr;
6583 +       dwc_otg_dma_desc_t* iso_desc_addr;
6584 +
6585 +       /** pointer to the transfer buffers */
6586 +       uint8_t         *xfer_buff0;
6587 +       uint8_t         *xfer_buff1;
6588 +
6589 +       /** number of ISOC Buffer is processing */
6590 +       uint32_t        proc_buf_num;
6591 +       /** Interval of ISOC Buffer processing */
6592 +       uint32_t        buf_proc_intrvl;
6593 +       /** Data size for regular frame */
6594 +       uint32_t        data_per_frame;
6595 +
6596 +       /* todo - pattern data support is to be implemented in the future */
6597 +       /** Data size for pattern frame */
6598 +       uint32_t        data_pattern_frame;
6599 +       /** Frame number of pattern data */
6600 +       uint32_t        sync_frame;
6601 +
6602 +       /** bInterval */
6603 +       uint32_t        bInterval;
6604 +       /** ISO Packet number per frame */
6605 +       uint32_t        pkt_per_frm;
6606 +       /** Next frame num for which will be setup DMA Desc */
6607 +       uint32_t        next_frame;
6608 +       /** Number of packets per buffer processing */
6609 +       uint32_t        pkt_cnt;
6610 +       /** Info for all isoc packets */
6611 +       iso_pkt_info_t  *pkt_info;
6612 +       /** current pkt number */
6613 +       uint32_t        cur_pkt;
6614 +       /** current pkt number */
6615 +       uint8_t         *cur_pkt_addr;
6616 +       /** current pkt number */
6617 +       uint32_t        cur_pkt_dma_addr;
6618 +#endif //DWC_EN_ISOC
6619 +/** @} */
6620 +} dwc_ep_t;
6621 +
6622 +/*
6623 + * Reasons for halting a host channel.
6624 + */
6625 +typedef enum dwc_otg_halt_status
6626 +{
6627 +       DWC_OTG_HC_XFER_NO_HALT_STATUS,
6628 +       DWC_OTG_HC_XFER_COMPLETE,
6629 +       DWC_OTG_HC_XFER_URB_COMPLETE,
6630 +       DWC_OTG_HC_XFER_ACK,
6631 +       DWC_OTG_HC_XFER_NAK,
6632 +       DWC_OTG_HC_XFER_NYET,
6633 +       DWC_OTG_HC_XFER_STALL,
6634 +       DWC_OTG_HC_XFER_XACT_ERR,
6635 +       DWC_OTG_HC_XFER_FRAME_OVERRUN,
6636 +       DWC_OTG_HC_XFER_BABBLE_ERR,
6637 +       DWC_OTG_HC_XFER_DATA_TOGGLE_ERR,
6638 +       DWC_OTG_HC_XFER_AHB_ERR,
6639 +       DWC_OTG_HC_XFER_PERIODIC_INCOMPLETE,
6640 +       DWC_OTG_HC_XFER_URB_DEQUEUE
6641 +} dwc_otg_halt_status_e;
6642 +
6643 +/**
6644 + * Host channel descriptor. This structure represents the state of a single
6645 + * host channel when acting in host mode. It contains the data items needed to
6646 + * transfer packets to an endpoint via a host channel.
6647 + */
6648 +typedef struct dwc_hc
6649 +{
6650 +       /** Host channel number used for register address lookup */
6651 +       uint8_t  hc_num;
6652 +
6653 +       /** Device to access */
6654 +       unsigned dev_addr : 7;
6655 +
6656 +       /** EP to access */
6657 +       unsigned ep_num : 4;
6658 +
6659 +       /** EP direction. 0: OUT, 1: IN */
6660 +       unsigned ep_is_in : 1;
6661 +
6662 +       /**
6663 +        * EP speed.
6664 +        * One of the following values:
6665 +        *      - DWC_OTG_EP_SPEED_LOW
6666 +        *      - DWC_OTG_EP_SPEED_FULL
6667 +        *      - DWC_OTG_EP_SPEED_HIGH
6668 +        */
6669 +       unsigned speed : 2;
6670 +#define DWC_OTG_EP_SPEED_LOW   0
6671 +#define DWC_OTG_EP_SPEED_FULL  1
6672 +#define DWC_OTG_EP_SPEED_HIGH  2
6673 +
6674 +       /**
6675 +        * Endpoint type.
6676 +        * One of the following values:
6677 +        *      - DWC_OTG_EP_TYPE_CONTROL: 0
6678 +        *      - DWC_OTG_EP_TYPE_ISOC: 1
6679 +        *      - DWC_OTG_EP_TYPE_BULK: 2
6680 +        *      - DWC_OTG_EP_TYPE_INTR: 3
6681 +        */
6682 +       unsigned ep_type : 2;
6683 +
6684 +       /** Max packet size in bytes */
6685 +       unsigned max_packet : 11;
6686 +
6687 +       /**
6688 +        * PID for initial transaction.
6689 +        * 0: DATA0,<br>
6690 +        * 1: DATA2,<br>
6691 +        * 2: DATA1,<br>
6692 +        * 3: MDATA (non-Control EP),
6693 +        *        SETUP (Control EP)
6694 +        */
6695 +       unsigned data_pid_start : 2;
6696 +#define DWC_OTG_HC_PID_DATA0 0
6697 +#define DWC_OTG_HC_PID_DATA2 1
6698 +#define DWC_OTG_HC_PID_DATA1 2
6699 +#define DWC_OTG_HC_PID_MDATA 3
6700 +#define DWC_OTG_HC_PID_SETUP 3
6701 +
6702 +       /** Number of periodic transactions per (micro)frame */
6703 +       unsigned multi_count: 2;
6704 +
6705 +       /** @name Transfer State */
6706 +       /** @{ */
6707 +
6708 +       /** Pointer to the current transfer buffer position. */
6709 +       uint8_t *xfer_buff;
6710 +       /** Total number of bytes to transfer. */
6711 +       uint32_t xfer_len;
6712 +       /** Number of bytes transferred so far. */
6713 +       uint32_t xfer_count;
6714 +       /** Packet count at start of transfer.*/
6715 +       uint16_t start_pkt_count;
6716 +
6717 +       /**
6718 +        * Flag to indicate whether the transfer has been started. Set to 1 if
6719 +        * it has been started, 0 otherwise.
6720 +        */
6721 +       uint8_t xfer_started;
6722 +
6723 +       /**
6724 +        * Set to 1 to indicate that a PING request should be issued on this
6725 +        * channel. If 0, process normally.
6726 +        */
6727 +       uint8_t do_ping;
6728 +
6729 +       /**
6730 +        * Set to 1 to indicate that the error count for this transaction is
6731 +        * non-zero. Set to 0 if the error count is 0.
6732 +        */
6733 +       uint8_t error_state;
6734 +
6735 +       /**
6736 +        * Set to 1 to indicate that this channel should be halted the next
6737 +        * time a request is queued for the channel. This is necessary in
6738 +        * slave mode if no request queue space is available when an attempt
6739 +        * is made to halt the channel.
6740 +        */
6741 +       uint8_t halt_on_queue;
6742 +
6743 +       /**
6744 +        * Set to 1 if the host channel has been halted, but the core is not
6745 +        * finished flushing queued requests. Otherwise 0.
6746 +        */
6747 +       uint8_t halt_pending;
6748 +
6749 +       /**
6750 +        * Reason for halting the host channel.
6751 +        */
6752 +       dwc_otg_halt_status_e   halt_status;
6753 +
6754 +       /*
6755 +        * Split settings for the host channel
6756 +        */
6757 +       uint8_t do_split;                  /**< Enable split for the channel */
6758 +       uint8_t complete_split;    /**< Enable complete split */
6759 +       uint8_t hub_addr;                  /**< Address of high speed hub */
6760 +
6761 +       uint8_t port_addr;                 /**< Port of the low/full speed device */
6762 +       /** Split transaction position
6763 +        * One of the following values:
6764 +        *        - DWC_HCSPLIT_XACTPOS_MID
6765 +        *        - DWC_HCSPLIT_XACTPOS_BEGIN
6766 +        *        - DWC_HCSPLIT_XACTPOS_END
6767 +        *        - DWC_HCSPLIT_XACTPOS_ALL */
6768 +       uint8_t xact_pos;
6769 +
6770 +       /** Set when the host channel does a short read. */
6771 +       uint8_t short_read;
6772 +
6773 +       /**
6774 +        * Number of requests issued for this channel since it was assigned to
6775 +        * the current transfer (not counting PINGs).
6776 +        */
6777 +       uint8_t requests;
6778 +
6779 +       /**
6780 +        * Queue Head for the transfer being processed by this channel.
6781 +        */
6782 +       struct dwc_otg_qh *qh;
6783 +
6784 +       /** @} */
6785 +
6786 +       /** Entry in list of host channels. */
6787 +       struct list_head        hc_list_entry;
6788 +} dwc_hc_t;
6789 +
6790 +/**
6791 + * The following parameters may be specified when starting the module. These
6792 + * parameters define how the DWC_otg controller should be configured.
6793 + * Parameter values are passed to the CIL initialization function
6794 + * dwc_otg_cil_init.
6795 + */
6796 +typedef struct dwc_otg_core_params
6797 +{
6798 +       int32_t opt;
6799 +#define dwc_param_opt_default 1
6800 +
6801 +       /**
6802 +        * Specifies the OTG capabilities. The driver will automatically
6803 +        * detect the value for this parameter if none is specified.
6804 +        * 0 - HNP and SRP capable (default)
6805 +        * 1 - SRP Only capable
6806 +        * 2 - No HNP/SRP capable
6807 +        */
6808 +       int32_t otg_cap;
6809 +#define DWC_OTG_CAP_PARAM_HNP_SRP_CAPABLE 0
6810 +#define DWC_OTG_CAP_PARAM_SRP_ONLY_CAPABLE 1
6811 +#define DWC_OTG_CAP_PARAM_NO_HNP_SRP_CAPABLE 2
6812 +#define dwc_param_otg_cap_default DWC_OTG_CAP_PARAM_HNP_SRP_CAPABLE
6813 +
6814 +       /**
6815 +        * Specifies whether to use slave or DMA mode for accessing the data
6816 +        * FIFOs. The driver will automatically detect the value for this
6817 +        * parameter if none is specified.
6818 +        * 0 - Slave
6819 +        * 1 - DMA (default, if available)
6820 +        */
6821 +       int32_t dma_enable;
6822 +#define dwc_param_dma_enable_default 1
6823 +
6824 +       /**
6825 +        * When DMA mode is enabled specifies whether to use address DMA or DMA Descritor mode for accessing the data
6826 +        * FIFOs in device mode. The driver will automatically detect the value for this
6827 +        * parameter if none is specified.
6828 +        * 0 - address DMA
6829 +        * 1 - DMA Descriptor(default, if available)
6830 +        */
6831 +       int32_t dma_desc_enable;
6832 +#define dwc_param_dma_desc_enable_default 0
6833 +       /** The DMA Burst size (applicable only for External DMA
6834 +        * Mode). 1, 4, 8 16, 32, 64, 128, 256 (default 32)
6835 +        */
6836 +       int32_t dma_burst_size;  /* Translate this to GAHBCFG values */
6837 +#define dwc_param_dma_burst_size_default 32
6838 +
6839 +       /**
6840 +        * Specifies the maximum speed of operation in host and device mode.
6841 +        * The actual speed depends on the speed of the attached device and
6842 +        * the value of phy_type. The actual speed depends on the speed of the
6843 +        * attached device.
6844 +        * 0 - High Speed (default)
6845 +        * 1 - Full Speed
6846 +        */
6847 +       int32_t speed;
6848 +#define dwc_param_speed_default 0
6849 +#define DWC_SPEED_PARAM_HIGH 0
6850 +#define DWC_SPEED_PARAM_FULL 1
6851 +
6852 +       /** Specifies whether low power mode is supported when attached
6853 +        *      to a Full Speed or Low Speed device in host mode.
6854 +        * 0 - Don't support low power mode (default)
6855 +        * 1 - Support low power mode
6856 +        */
6857 +       int32_t host_support_fs_ls_low_power;
6858 +#define dwc_param_host_support_fs_ls_low_power_default 0
6859 +
6860 +       /** Specifies the PHY clock rate in low power mode when connected to a
6861 +        * Low Speed device in host mode. This parameter is applicable only if
6862 +        * HOST_SUPPORT_FS_LS_LOW_POWER is enabled.      If PHY_TYPE is set to FS
6863 +        * then defaults to 6 MHZ otherwise 48 MHZ.
6864 +        *
6865 +        * 0 - 48 MHz
6866 +        * 1 - 6 MHz
6867 +        */
6868 +       int32_t host_ls_low_power_phy_clk;
6869 +#define dwc_param_host_ls_low_power_phy_clk_default 0
6870 +#define DWC_HOST_LS_LOW_POWER_PHY_CLK_PARAM_48MHZ 0
6871 +#define DWC_HOST_LS_LOW_POWER_PHY_CLK_PARAM_6MHZ 1
6872 +
6873 +       /**
6874 +        * 0 - Use cC FIFO size parameters
6875 +        * 1 - Allow dynamic FIFO sizing (default)
6876 +        */
6877 +       int32_t enable_dynamic_fifo;
6878 +#define dwc_param_enable_dynamic_fifo_default 1
6879 +
6880 +       /** Total number of 4-byte words in the data FIFO memory. This
6881 +        * memory includes the Rx FIFO, non-periodic Tx FIFO, and periodic
6882 +        * Tx FIFOs.
6883 +        * 32 to 32768 (default 8192)
6884 +        * Note: The total FIFO memory depth in the FPGA configuration is 8192.
6885 +        */
6886 +       int32_t data_fifo_size;
6887 +#define dwc_param_data_fifo_size_default 8192
6888 +
6889 +       /** Number of 4-byte words in the Rx FIFO in device mode when dynamic
6890 +        * FIFO sizing is enabled.
6891 +        * 16 to 32768 (default 1064)
6892 +        */
6893 +       int32_t dev_rx_fifo_size;
6894 +#define dwc_param_dev_rx_fifo_size_default  1064
6895 +
6896 +       /** Number of 4-byte words in the non-periodic Tx FIFO in device mode
6897 +        * when dynamic FIFO sizing is enabled.
6898 +        * 16 to 32768 (default 1024)
6899 +        */
6900 +       int32_t dev_nperio_tx_fifo_size;
6901 +#define dwc_param_dev_nperio_tx_fifo_size_default 1024
6902 +
6903 +       /** Number of 4-byte words in each of the periodic Tx FIFOs in device
6904 +        * mode when dynamic FIFO sizing is enabled.
6905 +        * 4 to 768 (default 256)
6906 +        */
6907 +       uint32_t dev_perio_tx_fifo_size[MAX_PERIO_FIFOS];
6908 +#define dwc_param_dev_perio_tx_fifo_size_default 256
6909 +
6910 +       /** Number of 4-byte words in the Rx FIFO in host mode when dynamic
6911 +        * FIFO sizing is enabled.
6912 +        * 16 to 32768 (default 1024)
6913 +        */
6914 +       int32_t host_rx_fifo_size;
6915 +#define dwc_param_host_rx_fifo_size_default 1024
6916 +
6917 +       /** Number of 4-byte words in the non-periodic Tx FIFO in host mode
6918 +        * when Dynamic FIFO sizing is enabled in the core.
6919 +        * 16 to 32768 (default 1024)
6920 +        */
6921 +       int32_t host_nperio_tx_fifo_size;
6922 +#define dwc_param_host_nperio_tx_fifo_size_default 1024
6923 +
6924 +       /** Number of 4-byte words in the host periodic Tx FIFO when dynamic
6925 +        * FIFO sizing is enabled.
6926 +        * 16 to 32768 (default 1024)
6927 +        */
6928 +       int32_t host_perio_tx_fifo_size;
6929 +#define dwc_param_host_perio_tx_fifo_size_default 1024
6930 +
6931 +       /** The maximum transfer size supported in bytes.
6932 +        * 2047 to 65,535  (default 65,535)
6933 +        */
6934 +       int32_t max_transfer_size;
6935 +#define dwc_param_max_transfer_size_default 65535
6936 +
6937 +       /** The maximum number of packets in a transfer.
6938 +        * 15 to 511  (default 511)
6939 +        */
6940 +       int32_t max_packet_count;
6941 +#define dwc_param_max_packet_count_default 511
6942 +
6943 +       /** The number of host channel registers to use.
6944 +        * 1 to 16 (default 12)
6945 +        * Note: The FPGA configuration supports a maximum of 12 host channels.
6946 +        */
6947 +       int32_t host_channels;
6948 +#define dwc_param_host_channels_default 12
6949 +
6950 +       /** The number of endpoints in addition to EP0 available for device
6951 +        * mode operations.
6952 +        * 1 to 15 (default 6 IN and OUT)
6953 +        * Note: The FPGA configuration supports a maximum of 6 IN and OUT
6954 +        * endpoints in addition to EP0.
6955 +        */
6956 +       int32_t dev_endpoints;
6957 +#define dwc_param_dev_endpoints_default 6
6958 +
6959 +               /**
6960 +                * Specifies the type of PHY interface to use. By default, the driver
6961 +                * will automatically detect the phy_type.
6962 +                *
6963 +                * 0 - Full Speed PHY
6964 +                * 1 - UTMI+ (default)
6965 +                * 2 - ULPI
6966 +                */
6967 +       int32_t phy_type;
6968 +#define DWC_PHY_TYPE_PARAM_FS 0
6969 +#define DWC_PHY_TYPE_PARAM_UTMI 1
6970 +#define DWC_PHY_TYPE_PARAM_ULPI 2
6971 +#define dwc_param_phy_type_default DWC_PHY_TYPE_PARAM_UTMI
6972 +
6973 +       /**
6974 +        * Specifies the UTMI+ Data Width.      This parameter is
6975 +        * applicable for a PHY_TYPE of UTMI+ or ULPI. (For a ULPI
6976 +        * PHY_TYPE, this parameter indicates the data width between
6977 +        * the MAC and the ULPI Wrapper.) Also, this parameter is
6978 +        * applicable only if the OTG_HSPHY_WIDTH cC parameter was set
6979 +        * to "8 and 16 bits", meaning that the core has been
6980 +        * configured to work at either data path width.
6981 +        *
6982 +        * 8 or 16 bits (default 16)
6983 +        */
6984 +       int32_t phy_utmi_width;
6985 +#define dwc_param_phy_utmi_width_default 16
6986 +
6987 +       /**
6988 +        * Specifies whether the ULPI operates at double or single
6989 +        * data rate. This parameter is only applicable if PHY_TYPE is
6990 +        * ULPI.
6991 +        *
6992 +        * 0 - single data rate ULPI interface with 8 bit wide data
6993 +        * bus (default)
6994 +        * 1 - double data rate ULPI interface with 4 bit wide data
6995 +        * bus
6996 +        */
6997 +       int32_t phy_ulpi_ddr;
6998 +#define dwc_param_phy_ulpi_ddr_default 0
6999 +
7000 +       /**
7001 +        * Specifies whether to use the internal or external supply to
7002 +        * drive the vbus with a ULPI phy.
7003 +        */
7004 +       int32_t phy_ulpi_ext_vbus;
7005 +#define DWC_PHY_ULPI_INTERNAL_VBUS 0
7006 +#define DWC_PHY_ULPI_EXTERNAL_VBUS 1
7007 +#define dwc_param_phy_ulpi_ext_vbus_default DWC_PHY_ULPI_INTERNAL_VBUS
7008 +
7009 +       /**
7010 +        * Specifies whether to use the I2Cinterface for full speed PHY. This
7011 +        * parameter is only applicable if PHY_TYPE is FS.
7012 +        * 0 - No (default)
7013 +        * 1 - Yes
7014 +        */
7015 +       int32_t i2c_enable;
7016 +#define dwc_param_i2c_enable_default 0
7017 +
7018 +       int32_t ulpi_fs_ls;
7019 +#define dwc_param_ulpi_fs_ls_default 0
7020 +
7021 +       int32_t ts_dline;
7022 +#define dwc_param_ts_dline_default 0
7023 +
7024 +       /**
7025 +        * Specifies whether dedicated transmit FIFOs are
7026 +        * enabled for non periodic IN endpoints in device mode
7027 +        * 0 - No
7028 +        * 1 - Yes
7029 +        */
7030 +        int32_t en_multiple_tx_fifo;
7031 +#define dwc_param_en_multiple_tx_fifo_default 1
7032 +
7033 +       /** Number of 4-byte words in each of the Tx FIFOs in device
7034 +        * mode when dynamic FIFO sizing is enabled.
7035 +        * 4 to 768 (default 256)
7036 +        */
7037 +       uint32_t dev_tx_fifo_size[MAX_TX_FIFOS];
7038 +#define dwc_param_dev_tx_fifo_size_default 256
7039 +
7040 +       /** Thresholding enable flag-
7041 +        * bit 0 - enable non-ISO Tx thresholding
7042 +        * bit 1 - enable ISO Tx thresholding
7043 +        * bit 2 - enable Rx thresholding
7044 +        */
7045 +       uint32_t thr_ctl;
7046 +#define dwc_param_thr_ctl_default 0
7047 +
7048 +       /** Thresholding length for Tx
7049 +        *      FIFOs in 32 bit DWORDs
7050 +        */
7051 +       uint32_t tx_thr_length;
7052 +#define dwc_param_tx_thr_length_default 64
7053 +
7054 +       /** Thresholding length for Rx
7055 +        *      FIFOs in 32 bit DWORDs
7056 +        */
7057 +       uint32_t rx_thr_length;
7058 +#define dwc_param_rx_thr_length_default 64
7059 +
7060 +       /** Per Transfer Interrupt
7061 +        *      mode enable flag
7062 +        * 1 - Enabled
7063 +        * 0 - Disabled
7064 +        */
7065 +       uint32_t pti_enable;
7066 +#define dwc_param_pti_enable_default 0
7067 +
7068 +       /** Molti Processor Interrupt
7069 +        *      mode enable flag
7070 +        * 1 - Enabled
7071 +        * 0 - Disabled
7072 +        */
7073 +       uint32_t mpi_enable;
7074 +#define dwc_param_mpi_enable_default 0
7075 +
7076 +} dwc_otg_core_params_t;
7077 +
7078 +#ifdef DEBUG
7079 +struct dwc_otg_core_if;
7080 +typedef struct hc_xfer_info
7081 +{
7082 +       struct dwc_otg_core_if  *core_if;
7083 +       dwc_hc_t                *hc;
7084 +} hc_xfer_info_t;
7085 +#endif
7086 +
7087 +/**
7088 + * The <code>dwc_otg_core_if</code> structure contains information needed to manage
7089 + * the DWC_otg controller acting in either host or device mode. It
7090 + * represents the programming view of the controller as a whole.
7091 + */
7092 +typedef struct dwc_otg_core_if
7093 +{
7094 +       /** Parameters that define how the core should be configured.*/
7095 +       dwc_otg_core_params_t      *core_params;
7096 +
7097 +       /** Core Global registers starting at offset 000h. */
7098 +       dwc_otg_core_global_regs_t *core_global_regs;
7099 +
7100 +       /** Device-specific information */
7101 +       dwc_otg_dev_if_t                   *dev_if;
7102 +       /** Host-specific information */
7103 +       dwc_otg_host_if_t                  *host_if;
7104 +
7105 +       /** Value from SNPSID register */
7106 +       uint32_t snpsid;
7107 +
7108 +       /*
7109 +        * Set to 1 if the core PHY interface bits in USBCFG have been
7110 +        * initialized.
7111 +        */
7112 +       uint8_t phy_init_done;
7113 +
7114 +       /*
7115 +        * SRP Success flag, set by srp success interrupt in FS I2C mode
7116 +        */
7117 +       uint8_t srp_success;
7118 +       uint8_t srp_timer_started;
7119 +
7120 +       /* Common configuration information */
7121 +       /** Power and Clock Gating Control Register */
7122 +       volatile uint32_t *pcgcctl;
7123 +#define DWC_OTG_PCGCCTL_OFFSET 0xE00
7124 +
7125 +       /** Push/pop addresses for endpoints or host channels.*/
7126 +       uint32_t *data_fifo[MAX_EPS_CHANNELS];
7127 +#define DWC_OTG_DATA_FIFO_OFFSET 0x1000
7128 +#define DWC_OTG_DATA_FIFO_SIZE 0x1000
7129 +
7130 +       /** Total RAM for FIFOs (Bytes) */
7131 +       uint16_t total_fifo_size;
7132 +       /** Size of Rx FIFO (Bytes) */
7133 +       uint16_t rx_fifo_size;
7134 +       /** Size of Non-periodic Tx FIFO (Bytes) */
7135 +       uint16_t nperio_tx_fifo_size;
7136 +
7137 +
7138 +       /** 1 if DMA is enabled, 0 otherwise. */
7139 +       uint8_t dma_enable;
7140 +
7141 +       /** 1 if Descriptor DMA mode is enabled, 0 otherwise. */
7142 +       uint8_t dma_desc_enable;
7143 +
7144 +       /** 1 if PTI Enhancement mode is enabled, 0 otherwise. */
7145 +       uint8_t pti_enh_enable;
7146 +
7147 +       /** 1 if MPI Enhancement mode is enabled, 0 otherwise. */
7148 +       uint8_t multiproc_int_enable;
7149 +
7150 +       /** 1 if dedicated Tx FIFOs are enabled, 0 otherwise. */
7151 +       uint8_t en_multiple_tx_fifo;
7152 +
7153 +       /** Set to 1 if multiple packets of a high-bandwidth transfer is in
7154 +        * process of being queued */
7155 +       uint8_t queuing_high_bandwidth;
7156 +
7157 +       /** Hardware Configuration -- stored here for convenience.*/
7158 +       hwcfg1_data_t hwcfg1;
7159 +       hwcfg2_data_t hwcfg2;
7160 +       hwcfg3_data_t hwcfg3;
7161 +       hwcfg4_data_t hwcfg4;
7162 +
7163 +       /** Host and Device Configuration -- stored here for convenience.*/
7164 +       hcfg_data_t hcfg;
7165 +       dcfg_data_t dcfg;
7166 +
7167 +       /** The operational State, during transations
7168 +        * (a_host>>a_peripherial and b_device=>b_host) this may not
7169 +        * match the core but allows the software to determine
7170 +        * transitions.
7171 +        */
7172 +       uint8_t op_state;
7173 +
7174 +       /**
7175 +        * Set to 1 if the HCD needs to be restarted on a session request
7176 +        * interrupt. This is required if no connector ID status change has
7177 +        * occurred since the HCD was last disconnected.
7178 +        */
7179 +       uint8_t restart_hcd_on_session_req;
7180 +
7181 +       /** HCD callbacks */
7182 +       /** A-Device is a_host */
7183 +#define A_HOST         (1)
7184 +       /** A-Device is a_suspend */
7185 +#define A_SUSPEND      (2)
7186 +       /** A-Device is a_peripherial */
7187 +#define A_PERIPHERAL   (3)
7188 +       /** B-Device is operating as a Peripheral. */
7189 +#define B_PERIPHERAL   (4)
7190 +       /** B-Device is operating as a Host. */
7191 +#define B_HOST         (5)
7192 +
7193 +       /** HCD callbacks */
7194 +       struct dwc_otg_cil_callbacks *hcd_cb;
7195 +       /** PCD callbacks */
7196 +       struct dwc_otg_cil_callbacks *pcd_cb;
7197 +
7198 +       /** Device mode Periodic Tx FIFO Mask */
7199 +       uint32_t p_tx_msk;
7200 +       /** Device mode Periodic Tx FIFO Mask */
7201 +       uint32_t tx_msk;
7202 +
7203 +       /** Workqueue object used for handling several interrupts */
7204 +       struct workqueue_struct *wq_otg;
7205 +
7206 +       /** Work object used for handling "Connector ID Status Change" Interrupt */
7207 +       struct work_struct      w_conn_id;
7208 +
7209 +       /** Work object used for handling "Wakeup Detected" Interrupt */
7210 +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,20)
7211 +       struct work_struct      w_wkp;
7212 +#else
7213 +       struct delayed_work     w_wkp;
7214 +#endif
7215 +
7216 +#ifdef DEBUG
7217 +       uint32_t                start_hcchar_val[MAX_EPS_CHANNELS];
7218 +
7219 +       hc_xfer_info_t          hc_xfer_info[MAX_EPS_CHANNELS];
7220 +       struct timer_list       hc_xfer_timer[MAX_EPS_CHANNELS];
7221 +
7222 +       uint32_t                hfnum_7_samples;
7223 +       uint64_t                hfnum_7_frrem_accum;
7224 +       uint32_t                hfnum_0_samples;
7225 +       uint64_t                hfnum_0_frrem_accum;
7226 +       uint32_t                hfnum_other_samples;
7227 +       uint64_t                hfnum_other_frrem_accum;
7228 +#endif
7229 +
7230 +
7231 +} dwc_otg_core_if_t;
7232 +
7233 +/*We must clear S3C24XX_EINTPEND external interrupt register
7234 + * because after clearing in this register trigerred IRQ from
7235 + * H/W core in kernel interrupt can be occured again before OTG
7236 + * handlers clear all IRQ sources of Core registers because of
7237 + * timing latencies and Low Level IRQ Type.
7238 + */
7239 +
7240 +#ifdef CONFIG_MACH_IPMATE
7241 +#define  S3C2410X_CLEAR_EINTPEND()   \
7242 +do { \
7243 +       if (!dwc_otg_read_core_intr(core_if)) { \
7244 +       __raw_writel(1UL << 11,S3C24XX_EINTPEND); \
7245 +       } \
7246 +} while (0)
7247 +#else
7248 +#define  S3C2410X_CLEAR_EINTPEND()   do { } while (0)
7249 +#endif
7250 +
7251 +/*
7252 + * The following functions are functions for works
7253 + * using during handling some interrupts
7254 + */
7255 +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,20)
7256 +
7257 +extern void w_conn_id_status_change(void *p);
7258 +extern void w_wakeup_detected(void *p);
7259 +
7260 +#else
7261 +
7262 +extern void w_conn_id_status_change(struct work_struct *p);
7263 +extern void w_wakeup_detected(struct work_struct *p);
7264 +
7265 +#endif
7266 +
7267 +
7268 +/*
7269 + * The following functions support initialization of the CIL driver component
7270 + * and the DWC_otg controller.
7271 + */
7272 +extern dwc_otg_core_if_t *dwc_otg_cil_init(const uint32_t *_reg_base_addr,
7273 +                                          dwc_otg_core_params_t *_core_params);
7274 +extern void dwc_otg_cil_remove(dwc_otg_core_if_t *_core_if);
7275 +extern void dwc_otg_core_init(dwc_otg_core_if_t *_core_if);
7276 +extern void dwc_otg_core_host_init(dwc_otg_core_if_t *_core_if);
7277 +extern void dwc_otg_core_dev_init(dwc_otg_core_if_t *_core_if);
7278 +extern void dwc_otg_enable_global_interrupts( dwc_otg_core_if_t *_core_if );
7279 +extern void dwc_otg_disable_global_interrupts( dwc_otg_core_if_t *_core_if );
7280 +
7281 +/** @name Device CIL Functions
7282 + * The following functions support managing the DWC_otg controller in device
7283 + * mode.
7284 + */
7285 +/**@{*/
7286 +extern void dwc_otg_wakeup(dwc_otg_core_if_t *_core_if);
7287 +extern void dwc_otg_read_setup_packet (dwc_otg_core_if_t *_core_if, uint32_t *_dest);
7288 +extern uint32_t dwc_otg_get_frame_number(dwc_otg_core_if_t *_core_if);
7289 +extern void dwc_otg_ep0_activate(dwc_otg_core_if_t *_core_if, dwc_ep_t *_ep);
7290 +extern void dwc_otg_ep_activate(dwc_otg_core_if_t *_core_if, dwc_ep_t *_ep);
7291 +extern void dwc_otg_ep_deactivate(dwc_otg_core_if_t *_core_if, dwc_ep_t *_ep);
7292 +extern void dwc_otg_ep_start_transfer(dwc_otg_core_if_t *_core_if, dwc_ep_t *_ep);
7293 +extern void dwc_otg_ep_start_zl_transfer(dwc_otg_core_if_t *_core_if, dwc_ep_t *_ep);
7294 +extern void dwc_otg_ep0_start_transfer(dwc_otg_core_if_t *_core_if, dwc_ep_t *_ep);
7295 +extern void dwc_otg_ep0_continue_transfer(dwc_otg_core_if_t *_core_if, dwc_ep_t *_ep);
7296 +extern void dwc_otg_ep_write_packet(dwc_otg_core_if_t *_core_if, dwc_ep_t *_ep, int _dma);
7297 +extern void dwc_otg_ep_set_stall(dwc_otg_core_if_t *_core_if, dwc_ep_t *_ep);
7298 +extern void dwc_otg_ep_clear_stall(dwc_otg_core_if_t *_core_if, dwc_ep_t *_ep);
7299 +extern void dwc_otg_enable_device_interrupts(dwc_otg_core_if_t *_core_if);
7300 +extern void dwc_otg_dump_dev_registers(dwc_otg_core_if_t *_core_if);
7301 +extern void dwc_otg_dump_spram(dwc_otg_core_if_t *_core_if);
7302 +#ifdef DWC_EN_ISOC
7303 +extern void dwc_otg_iso_ep_start_frm_transfer(dwc_otg_core_if_t *core_if, dwc_ep_t *ep);
7304 +extern void dwc_otg_iso_ep_start_buf_transfer(dwc_otg_core_if_t *core_if, dwc_ep_t *ep);
7305 +#endif //DWC_EN_ISOC
7306 +/**@}*/
7307 +
7308 +/** @name Host CIL Functions
7309 + * The following functions support managing the DWC_otg controller in host
7310 + * mode.
7311 + */
7312 +/**@{*/
7313 +extern void dwc_otg_hc_init(dwc_otg_core_if_t *_core_if, dwc_hc_t *_hc);
7314 +extern void dwc_otg_hc_halt(dwc_otg_core_if_t *_core_if,
7315 +                               dwc_hc_t *_hc,
7316 +                               dwc_otg_halt_status_e _halt_status);
7317 +extern void dwc_otg_hc_cleanup(dwc_otg_core_if_t *_core_if, dwc_hc_t *_hc);
7318 +extern void dwc_otg_hc_start_transfer(dwc_otg_core_if_t *_core_if, dwc_hc_t *_hc);
7319 +extern int dwc_otg_hc_continue_transfer(dwc_otg_core_if_t *_core_if, dwc_hc_t *_hc);
7320 +extern void dwc_otg_hc_do_ping(dwc_otg_core_if_t *_core_if, dwc_hc_t *_hc);
7321 +extern void dwc_otg_hc_write_packet(dwc_otg_core_if_t *_core_if, dwc_hc_t *_hc);
7322 +extern void dwc_otg_enable_host_interrupts(dwc_otg_core_if_t *_core_if);
7323 +extern void dwc_otg_disable_host_interrupts(dwc_otg_core_if_t *_core_if);
7324 +
7325 +/**
7326 + * This function Reads HPRT0 in preparation to modify. It keeps the
7327 + * WC bits 0 so that if they are read as 1, they won't clear when you
7328 + * write it back
7329 + */
7330 +static inline uint32_t dwc_otg_read_hprt0(dwc_otg_core_if_t *_core_if)
7331 +{
7332 +       hprt0_data_t hprt0;
7333 +       hprt0.d32 = dwc_read_reg32(_core_if->host_if->hprt0);
7334 +       hprt0.b.prtena = 0;
7335 +       hprt0.b.prtconndet = 0;
7336 +       hprt0.b.prtenchng = 0;
7337 +       hprt0.b.prtovrcurrchng = 0;
7338 +       return hprt0.d32;
7339 +}
7340 +
7341 +extern void dwc_otg_dump_host_registers(dwc_otg_core_if_t *_core_if);
7342 +/**@}*/
7343 +
7344 +/** @name Common CIL Functions
7345 + * The following functions support managing the DWC_otg controller in either
7346 + * device or host mode.
7347 + */
7348 +/**@{*/
7349 +
7350 +extern void dwc_otg_read_packet(dwc_otg_core_if_t *core_if,
7351 +                               uint8_t *dest,
7352 +                               uint16_t bytes);
7353 +
7354 +extern void dwc_otg_dump_global_registers(dwc_otg_core_if_t *_core_if);
7355 +
7356 +extern void dwc_otg_flush_tx_fifo( dwc_otg_core_if_t *_core_if,
7357 +                                                                  const int _num );
7358 +extern void dwc_otg_flush_rx_fifo( dwc_otg_core_if_t *_core_if );
7359 +extern void dwc_otg_core_reset( dwc_otg_core_if_t *_core_if );
7360 +
7361 +extern dwc_otg_dma_desc_t* dwc_otg_ep_alloc_desc_chain(uint32_t * dma_desc_addr, uint32_t count);
7362 +extern void dwc_otg_ep_free_desc_chain(dwc_otg_dma_desc_t* desc_addr, uint32_t dma_desc_addr, uint32_t count);
7363 +
7364 +/**
7365 + * This function returns the Core Interrupt register.
7366 + */
7367 +static inline uint32_t dwc_otg_read_core_intr(dwc_otg_core_if_t *_core_if)
7368 +{
7369 +       return (dwc_read_reg32(&_core_if->core_global_regs->gintsts) &
7370 +               dwc_read_reg32(&_core_if->core_global_regs->gintmsk));
7371 +}
7372 +
7373 +/**
7374 + * This function returns the OTG Interrupt register.
7375 + */
7376 +static inline uint32_t dwc_otg_read_otg_intr (dwc_otg_core_if_t *_core_if)
7377 +{
7378 +       return (dwc_read_reg32 (&_core_if->core_global_regs->gotgint));
7379 +}
7380 +
7381 +/**
7382 + * This function reads the Device All Endpoints Interrupt register and
7383 + * returns the IN endpoint interrupt bits.
7384 + */
7385 +static inline uint32_t dwc_otg_read_dev_all_in_ep_intr(dwc_otg_core_if_t *core_if)
7386 +{
7387 +       uint32_t v;
7388 +
7389 +       if(core_if->multiproc_int_enable) {
7390 +               v = dwc_read_reg32(&core_if->dev_if->dev_global_regs->deachint) &
7391 +                               dwc_read_reg32(&core_if->dev_if->dev_global_regs->deachintmsk);
7392 +       } else {
7393 +               v = dwc_read_reg32(&core_if->dev_if->dev_global_regs->daint) &
7394 +                               dwc_read_reg32(&core_if->dev_if->dev_global_regs->daintmsk);
7395 +       }
7396 +       return (v & 0xffff);
7397 +
7398 +}
7399 +
7400 +/**
7401 + * This function reads the Device All Endpoints Interrupt register and
7402 + * returns the OUT endpoint interrupt bits.
7403 + */
7404 +static inline uint32_t dwc_otg_read_dev_all_out_ep_intr(dwc_otg_core_if_t *core_if)
7405 +{
7406 +       uint32_t v;
7407 +
7408 +       if(core_if->multiproc_int_enable) {
7409 +               v = dwc_read_reg32(&core_if->dev_if->dev_global_regs->deachint) &
7410 +                               dwc_read_reg32(&core_if->dev_if->dev_global_regs->deachintmsk);
7411 +       } else {
7412 +               v = dwc_read_reg32(&core_if->dev_if->dev_global_regs->daint) &
7413 +                               dwc_read_reg32(&core_if->dev_if->dev_global_regs->daintmsk);
7414 +       }
7415 +
7416 +       return ((v & 0xffff0000) >> 16);
7417 +}
7418 +
7419 +/**
7420 + * This function returns the Device IN EP Interrupt register
7421 + */
7422 +static inline uint32_t dwc_otg_read_dev_in_ep_intr(dwc_otg_core_if_t *core_if,
7423 +                                                       dwc_ep_t *ep)
7424 +{
7425 +       dwc_otg_dev_if_t *dev_if = core_if->dev_if;
7426 +       uint32_t v, msk, emp;
7427 +
7428 +       if(core_if->multiproc_int_enable) {
7429 +               msk = dwc_read_reg32(&dev_if->dev_global_regs->diepeachintmsk[ep->num]);
7430 +               emp = dwc_read_reg32(&dev_if->dev_global_regs->dtknqr4_fifoemptymsk);
7431 +               msk |= ((emp >> ep->num) & 0x1) << 7;
7432 +               v = dwc_read_reg32(&dev_if->in_ep_regs[ep->num]->diepint) & msk;
7433 +       } else {
7434 +               msk = dwc_read_reg32(&dev_if->dev_global_regs->diepmsk);
7435 +               emp = dwc_read_reg32(&dev_if->dev_global_regs->dtknqr4_fifoemptymsk);
7436 +               msk |= ((emp >> ep->num) & 0x1) << 7;
7437 +               v = dwc_read_reg32(&dev_if->in_ep_regs[ep->num]->diepint) & msk;
7438 +       }
7439 +
7440 +
7441 +       return v;
7442 +}
7443 +/**
7444 + * This function returns the Device OUT EP Interrupt register
7445 + */
7446 +static inline uint32_t dwc_otg_read_dev_out_ep_intr(dwc_otg_core_if_t *_core_if,
7447 +                                                       dwc_ep_t *_ep)
7448 +{
7449 +       dwc_otg_dev_if_t *dev_if = _core_if->dev_if;
7450 +       uint32_t v;
7451 +       doepmsk_data_t msk = { .d32 = 0 };
7452 +
7453 +       if(_core_if->multiproc_int_enable) {
7454 +               msk.d32 = dwc_read_reg32(&dev_if->dev_global_regs->doepeachintmsk[_ep->num]);
7455 +               if(_core_if->pti_enh_enable) {
7456 +                       msk.b.pktdrpsts = 1;
7457 +               }
7458 +               v = dwc_read_reg32( &dev_if->out_ep_regs[_ep->num]->doepint) & msk.d32;
7459 +       } else {
7460 +               msk.d32 = dwc_read_reg32(&dev_if->dev_global_regs->doepmsk);
7461 +               if(_core_if->pti_enh_enable) {
7462 +                       msk.b.pktdrpsts = 1;
7463 +               }
7464 +               v = dwc_read_reg32( &dev_if->out_ep_regs[_ep->num]->doepint) & msk.d32;
7465 +       }
7466 +       return v;
7467 +}
7468 +
7469 +/**
7470 + * This function returns the Host All Channel Interrupt register
7471 + */
7472 +static inline uint32_t dwc_otg_read_host_all_channels_intr (dwc_otg_core_if_t *_core_if)
7473 +{
7474 +       return (dwc_read_reg32 (&_core_if->host_if->host_global_regs->haint));
7475 +}
7476 +
7477 +static inline uint32_t dwc_otg_read_host_channel_intr (dwc_otg_core_if_t *_core_if, dwc_hc_t *_hc)
7478 +{
7479 +       return (dwc_read_reg32 (&_core_if->host_if->hc_regs[_hc->hc_num]->hcint));
7480 +}
7481 +
7482 +
7483 +/**
7484 + * This function returns the mode of the operation, host or device.
7485 + *
7486 + * @return 0 - Device Mode, 1 - Host Mode
7487 + */
7488 +static inline uint32_t dwc_otg_mode(dwc_otg_core_if_t *_core_if)
7489 +{
7490 +       return (dwc_read_reg32( &_core_if->core_global_regs->gintsts ) & 0x1);
7491 +}
7492 +
7493 +static inline uint8_t dwc_otg_is_device_mode(dwc_otg_core_if_t *_core_if)
7494 +{
7495 +       return (dwc_otg_mode(_core_if) != DWC_HOST_MODE);
7496 +}
7497 +static inline uint8_t dwc_otg_is_host_mode(dwc_otg_core_if_t *_core_if)
7498 +{
7499 +       return (dwc_otg_mode(_core_if) == DWC_HOST_MODE);
7500 +}
7501 +
7502 +extern int32_t dwc_otg_handle_common_intr( dwc_otg_core_if_t *_core_if );
7503 +
7504 +
7505 +/**@}*/
7506 +
7507 +/**
7508 + * DWC_otg CIL callback structure.     This structure allows the HCD and
7509 + * PCD to register functions used for starting and stopping the PCD
7510 + * and HCD for role change on for a DRD.
7511 + */
7512 +typedef struct dwc_otg_cil_callbacks
7513 +{
7514 +       /** Start function for role change */
7515 +       int (*start) (void *_p);
7516 +       /** Stop Function for role change */
7517 +       int (*stop) (void *_p);
7518 +       /** Disconnect Function for role change */
7519 +       int (*disconnect) (void *_p);
7520 +       /** Resume/Remote wakeup Function */
7521 +       int (*resume_wakeup) (void *_p);
7522 +       /** Suspend function */
7523 +       int (*suspend) (void *_p);
7524 +       /** Session Start (SRP) */
7525 +       int (*session_start) (void *_p);
7526 +       /** Pointer passed to start() and stop() */
7527 +       void *p;
7528 +} dwc_otg_cil_callbacks_t;
7529 +
7530 +extern void dwc_otg_cil_register_pcd_callbacks( dwc_otg_core_if_t *_core_if,
7531 +                                               dwc_otg_cil_callbacks_t *_cb,
7532 +                                               void *_p);
7533 +extern void dwc_otg_cil_register_hcd_callbacks( dwc_otg_core_if_t *_core_if,
7534 +                                               dwc_otg_cil_callbacks_t *_cb,
7535 +                                               void *_p);
7536 +
7537 +#endif
7538 +
7539 --- /dev/null
7540 +++ b/drivers/usb/dwc_otg/dwc_otg_cil_intr.c
7541 @@ -0,0 +1,750 @@
7542 +/* ==========================================================================
7543 + * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_cil_intr.c $
7544 + * $Revision: 1.2 $
7545 + * $Date: 2008-11-21 05:39:15 $
7546 + * $Change: 1065567 $
7547 + *
7548 + * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
7549 + * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
7550 + * otherwise expressly agreed to in writing between Synopsys and you.
7551 + *
7552 + * The Software IS NOT an item of Licensed Software or Licensed Product under
7553 + * any End User Software License Agreement or Agreement for Licensed Product
7554 + * with Synopsys or any supplement thereto. You are permitted to use and
7555 + * redistribute this Software in source and binary forms, with or without
7556 + * modification, provided that redistributions of source code must retain this
7557 + * notice. You may not view, use, disclose, copy or distribute this file or
7558 + * any information contained herein except pursuant to this license grant from
7559 + * Synopsys. If you do not agree with this notice, including the disclaimer
7560 + * below, then you are not authorized to use the Software.
7561 + *
7562 + * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
7563 + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
7564 + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
7565 + * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
7566 + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
7567 + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
7568 + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
7569 + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
7570 + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
7571 + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
7572 + * DAMAGE.
7573 + * ========================================================================== */
7574 +
7575 +/** @file
7576 + *
7577 + * The Core Interface Layer provides basic services for accessing and
7578 + * managing the DWC_otg hardware. These services are used by both the
7579 + * Host Controller Driver and the Peripheral Controller Driver.
7580 + *
7581 + * This file contains the Common Interrupt handlers.
7582 + */
7583 +#include "linux/dwc_otg_plat.h"
7584 +#include "dwc_otg_regs.h"
7585 +#include "dwc_otg_cil.h"
7586 +
7587 +#ifdef DEBUG
7588 +inline const char *op_state_str(dwc_otg_core_if_t *core_if)
7589 +{
7590 +        return (core_if->op_state==A_HOST?"a_host":
7591 +                (core_if->op_state==A_SUSPEND?"a_suspend":
7592 +                 (core_if->op_state==A_PERIPHERAL?"a_peripheral":
7593 +                  (core_if->op_state==B_PERIPHERAL?"b_peripheral":
7594 +                   (core_if->op_state==B_HOST?"b_host":
7595 +                    "unknown")))));
7596 +}
7597 +#endif
7598 +
7599 +/** This function will log a debug message
7600 + *
7601 + * @param core_if Programming view of DWC_otg controller.
7602 + */
7603 +int32_t dwc_otg_handle_mode_mismatch_intr (dwc_otg_core_if_t *core_if)
7604 +{
7605 +       gintsts_data_t gintsts;
7606 +       DWC_WARN("Mode Mismatch Interrupt: currently in %s mode\n",
7607 +                dwc_otg_mode(core_if) ? "Host" : "Device");
7608 +
7609 +       /* Clear interrupt */
7610 +       gintsts.d32 = 0;
7611 +       gintsts.b.modemismatch = 1;
7612 +       dwc_write_reg32 (&core_if->core_global_regs->gintsts, gintsts.d32);
7613 +       return 1;
7614 +}
7615 +
7616 +/** Start the HCD.  Helper function for using the HCD callbacks.
7617 + *
7618 + * @param core_if Programming view of DWC_otg controller.
7619 + */
7620 +static inline void hcd_start(dwc_otg_core_if_t *core_if)
7621 +{
7622 +        if (core_if->hcd_cb && core_if->hcd_cb->start) {
7623 +                core_if->hcd_cb->start(core_if->hcd_cb->p);
7624 +        }
7625 +}
7626 +/** Stop the HCD.  Helper function for using the HCD callbacks.
7627 + *
7628 + * @param core_if Programming view of DWC_otg controller.
7629 + */
7630 +static inline void hcd_stop(dwc_otg_core_if_t *core_if)
7631 +{
7632 +        if (core_if->hcd_cb && core_if->hcd_cb->stop) {
7633 +                core_if->hcd_cb->stop(core_if->hcd_cb->p);
7634 +        }
7635 +}
7636 +/** Disconnect the HCD.  Helper function for using the HCD callbacks.
7637 + *
7638 + * @param core_if Programming view of DWC_otg controller.
7639 + */
7640 +static inline void hcd_disconnect(dwc_otg_core_if_t *core_if)
7641 +{
7642 +        if (core_if->hcd_cb && core_if->hcd_cb->disconnect) {
7643 +                core_if->hcd_cb->disconnect(core_if->hcd_cb->p);
7644 +        }
7645 +}
7646 +/** Inform the HCD the a New Session has begun.  Helper function for
7647 + * using the HCD callbacks.
7648 + *
7649 + * @param core_if Programming view of DWC_otg controller.
7650 + */
7651 +static inline void hcd_session_start(dwc_otg_core_if_t *core_if)
7652 +{
7653 +        if (core_if->hcd_cb && core_if->hcd_cb->session_start) {
7654 +                core_if->hcd_cb->session_start(core_if->hcd_cb->p);
7655 +        }
7656 +}
7657 +
7658 +/** Start the PCD.  Helper function for using the PCD callbacks.
7659 + *
7660 + * @param core_if Programming view of DWC_otg controller.
7661 + */
7662 +static inline void pcd_start(dwc_otg_core_if_t *core_if)
7663 +{
7664 +        if (core_if->pcd_cb && core_if->pcd_cb->start) {
7665 +                core_if->pcd_cb->start(core_if->pcd_cb->p);
7666 +        }
7667 +}
7668 +/** Stop the PCD.  Helper function for using the PCD callbacks.
7669 + *
7670 + * @param core_if Programming view of DWC_otg controller.
7671 + */
7672 +static inline void pcd_stop(dwc_otg_core_if_t *core_if)
7673 +{
7674 +        if (core_if->pcd_cb && core_if->pcd_cb->stop) {
7675 +                core_if->pcd_cb->stop(core_if->pcd_cb->p);
7676 +        }
7677 +}
7678 +/** Suspend the PCD.  Helper function for using the PCD callbacks.
7679 + *
7680 + * @param core_if Programming view of DWC_otg controller.
7681 + */
7682 +static inline void pcd_suspend(dwc_otg_core_if_t *core_if)
7683 +{
7684 +        if (core_if->pcd_cb && core_if->pcd_cb->suspend) {
7685 +                core_if->pcd_cb->suspend(core_if->pcd_cb->p);
7686 +        }
7687 +}
7688 +/** Resume the PCD.  Helper function for using the PCD callbacks.
7689 + *
7690 + * @param core_if Programming view of DWC_otg controller.
7691 + */
7692 +static inline void pcd_resume(dwc_otg_core_if_t *core_if)
7693 +{
7694 +        if (core_if->pcd_cb && core_if->pcd_cb->resume_wakeup) {
7695 +                core_if->pcd_cb->resume_wakeup(core_if->pcd_cb->p);
7696 +        }
7697 +}
7698 +
7699 +/**
7700 + * This function handles the OTG Interrupts. It reads the OTG
7701 + * Interrupt Register (GOTGINT) to determine what interrupt has
7702 + * occurred.
7703 + *
7704 + * @param core_if Programming view of DWC_otg controller.
7705 + */
7706 +int32_t dwc_otg_handle_otg_intr(dwc_otg_core_if_t *core_if)
7707 +{
7708 +        dwc_otg_core_global_regs_t *global_regs =
7709 +                core_if->core_global_regs;
7710 +       gotgint_data_t gotgint;
7711 +        gotgctl_data_t gotgctl;
7712 +       gintmsk_data_t gintmsk;
7713 +
7714 +       gotgint.d32 = dwc_read_reg32(&global_regs->gotgint);
7715 +        gotgctl.d32 = dwc_read_reg32(&global_regs->gotgctl);
7716 +        DWC_DEBUGPL(DBG_CIL, "gotgctl=%08x\n", gotgctl.d32);
7717 +
7718 +       if (gotgint.b.sesenddet) {
7719 +               DWC_DEBUGPL(DBG_ANY, "OTG Interrupt: "
7720 +                           "Session End Detected++ (%s)\n",
7721 +                            op_state_str(core_if));
7722 +                gotgctl.d32 = dwc_read_reg32(&global_regs->gotgctl);
7723 +
7724 +                if (core_if->op_state == B_HOST) {
7725 +                        pcd_start(core_if);
7726 +                        core_if->op_state = B_PERIPHERAL;
7727 +                } else {
7728 +                        /* If not B_HOST and Device HNP still set. HNP
7729 +                         * Did not succeed!*/
7730 +                        if (gotgctl.b.devhnpen) {
7731 +                                DWC_DEBUGPL(DBG_ANY, "Session End Detected\n");
7732 +                                DWC_ERROR("Device Not Connected/Responding!\n");
7733 +                        }
7734 +
7735 +                        /* If Session End Detected the B-Cable has
7736 +                         * been disconnected. */
7737 +                        /* Reset PCD and Gadget driver to a
7738 +                         * clean state. */
7739 +                        pcd_stop(core_if);
7740 +                }
7741 +                gotgctl.d32 = 0;
7742 +                gotgctl.b.devhnpen = 1;
7743 +                dwc_modify_reg32(&global_regs->gotgctl,
7744 +                                  gotgctl.d32, 0);
7745 +        }
7746 +       if (gotgint.b.sesreqsucstschng) {
7747 +               DWC_DEBUGPL(DBG_ANY, " OTG Interrupt: "
7748 +                           "Session Reqeust Success Status Change++\n");
7749 +                gotgctl.d32 = dwc_read_reg32(&global_regs->gotgctl);
7750 +                if (gotgctl.b.sesreqscs) {
7751 +                       if ((core_if->core_params->phy_type == DWC_PHY_TYPE_PARAM_FS) &&
7752 +                           (core_if->core_params->i2c_enable)) {
7753 +                               core_if->srp_success = 1;
7754 +                       }
7755 +                       else {
7756 +                               pcd_resume(core_if);
7757 +                               /* Clear Session Request */
7758 +                               gotgctl.d32 = 0;
7759 +                               gotgctl.b.sesreq = 1;
7760 +                               dwc_modify_reg32(&global_regs->gotgctl,
7761 +                                                 gotgctl.d32, 0);
7762 +                       }
7763 +                }
7764 +       }
7765 +       if (gotgint.b.hstnegsucstschng) {
7766 +                /* Print statements during the HNP interrupt handling
7767 +                 * can cause it to fail.*/
7768 +                gotgctl.d32 = dwc_read_reg32(&global_regs->gotgctl);
7769 +                if (gotgctl.b.hstnegscs) {
7770 +                        if (dwc_otg_is_host_mode(core_if)) {
7771 +                                core_if->op_state = B_HOST;
7772 +                               /*
7773 +                                * Need to disable SOF interrupt immediately.
7774 +                                * When switching from device to host, the PCD
7775 +                                * interrupt handler won't handle the
7776 +                                * interrupt if host mode is already set. The
7777 +                                * HCD interrupt handler won't get called if
7778 +                                * the HCD state is HALT. This means that the
7779 +                                * interrupt does not get handled and Linux
7780 +                                * complains loudly.
7781 +                                */
7782 +                               gintmsk.d32 = 0;
7783 +                               gintmsk.b.sofintr = 1;
7784 +                               dwc_modify_reg32(&global_regs->gintmsk,
7785 +                                                gintmsk.d32, 0);
7786 +                                pcd_stop(core_if);
7787 +                                /*
7788 +                                 * Initialize the Core for Host mode.
7789 +                                 */
7790 +                                hcd_start(core_if);
7791 +                                core_if->op_state = B_HOST;
7792 +                        }
7793 +                } else {
7794 +                        gotgctl.d32 = 0;
7795 +                        gotgctl.b.hnpreq = 1;
7796 +                        gotgctl.b.devhnpen = 1;
7797 +                        dwc_modify_reg32(&global_regs->gotgctl,
7798 +                                          gotgctl.d32, 0);
7799 +                        DWC_DEBUGPL(DBG_ANY, "HNP Failed\n");
7800 +                        DWC_ERROR("Device Not Connected/Responding\n");
7801 +                }
7802 +       }
7803 +       if (gotgint.b.hstnegdet) {
7804 +                /* The disconnect interrupt is set at the same time as
7805 +                * Host Negotiation Detected.  During the mode
7806 +                * switch all interrupts are cleared so the disconnect
7807 +                * interrupt handler will not get executed.
7808 +                 */
7809 +               DWC_DEBUGPL(DBG_ANY, " ++OTG Interrupt: "
7810 +                           "Host Negotiation Detected++ (%s)\n",
7811 +                            (dwc_otg_is_host_mode(core_if)?"Host":"Device"));
7812 +                if (dwc_otg_is_device_mode(core_if)){
7813 +                       DWC_DEBUGPL(DBG_ANY, "a_suspend->a_peripheral (%d)\n", core_if->op_state);
7814 +                        hcd_disconnect(core_if);
7815 +                        pcd_start(core_if);
7816 +                        core_if->op_state = A_PERIPHERAL;
7817 +                } else {
7818 +                       /*
7819 +                        * Need to disable SOF interrupt immediately. When
7820 +                        * switching from device to host, the PCD interrupt
7821 +                        * handler won't handle the interrupt if host mode is
7822 +                        * already set. The HCD interrupt handler won't get
7823 +                        * called if the HCD state is HALT. This means that
7824 +                        * the interrupt does not get handled and Linux
7825 +                        * complains loudly.
7826 +                        */
7827 +                       gintmsk.d32 = 0;
7828 +                       gintmsk.b.sofintr = 1;
7829 +                       dwc_modify_reg32(&global_regs->gintmsk,
7830 +                                        gintmsk.d32, 0);
7831 +                        pcd_stop(core_if);
7832 +                        hcd_start(core_if);
7833 +                        core_if->op_state = A_HOST;
7834 +                }
7835 +       }
7836 +       if (gotgint.b.adevtoutchng) {
7837 +               DWC_DEBUGPL(DBG_ANY, " ++OTG Interrupt: "
7838 +                           "A-Device Timeout Change++\n");
7839 +       }
7840 +       if (gotgint.b.debdone) {
7841 +               DWC_DEBUGPL(DBG_ANY, " ++OTG Interrupt: "
7842 +                           "Debounce Done++\n");
7843 +       }
7844 +
7845 +       /* Clear GOTGINT */
7846 +       dwc_write_reg32 (&core_if->core_global_regs->gotgint, gotgint.d32);
7847 +
7848 +       return 1;
7849 +}
7850 +
7851 +
7852 +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,20)
7853 +
7854 +void w_conn_id_status_change(void *p)
7855 +{
7856 +       dwc_otg_core_if_t *core_if = p;
7857 +
7858 +#else
7859 +
7860 +void w_conn_id_status_change(struct work_struct *p)
7861 +{
7862 +       dwc_otg_core_if_t *core_if = container_of(p, dwc_otg_core_if_t, w_conn_id);
7863 +
7864 +#endif
7865 +
7866 +
7867 +       uint32_t count = 0;
7868 +        gotgctl_data_t gotgctl = { .d32 = 0 };
7869 +
7870 +        gotgctl.d32 = dwc_read_reg32(&core_if->core_global_regs->gotgctl);
7871 +       DWC_DEBUGPL(DBG_CIL, "gotgctl=%0x\n", gotgctl.d32);
7872 +       DWC_DEBUGPL(DBG_CIL, "gotgctl.b.conidsts=%d\n", gotgctl.b.conidsts);
7873 +
7874 +        /* B-Device connector (Device Mode) */
7875 +        if (gotgctl.b.conidsts) {
7876 +                /* Wait for switch to device mode. */
7877 +                while (!dwc_otg_is_device_mode(core_if)){
7878 +                        DWC_PRINT("Waiting for Peripheral Mode, Mode=%s\n",
7879 +                                  (dwc_otg_is_host_mode(core_if)?"Host":"Peripheral"));
7880 +                        MDELAY(100);
7881 +                        if (++count > 10000) *(uint32_t*)NULL=0;
7882 +                }
7883 +                core_if->op_state = B_PERIPHERAL;
7884 +               dwc_otg_core_init(core_if);
7885 +               dwc_otg_enable_global_interrupts(core_if);
7886 +                pcd_start(core_if);
7887 +        } else {
7888 +                /* A-Device connector (Host Mode) */
7889 +                while (!dwc_otg_is_host_mode(core_if)) {
7890 +                        DWC_PRINT("Waiting for Host Mode, Mode=%s\n",
7891 +                                  (dwc_otg_is_host_mode(core_if)?"Host":"Peripheral"));
7892 +                        MDELAY(100);
7893 +                        if (++count > 10000) *(uint32_t*)NULL=0;
7894 +                }
7895 +                core_if->op_state = A_HOST;
7896 +                /*
7897 +                 * Initialize the Core for Host mode.
7898 +                 */
7899 +               dwc_otg_core_init(core_if);
7900 +               dwc_otg_enable_global_interrupts(core_if);
7901 +                hcd_start(core_if);
7902 +        }
7903 +}
7904 +
7905 +
7906 +/**
7907 + * This function handles the Connector ID Status Change Interrupt.  It
7908 + * reads the OTG Interrupt Register (GOTCTL) to determine whether this
7909 + * is a Device to Host Mode transition or a Host Mode to Device
7910 + * Transition.
7911 + *
7912 + * This only occurs when the cable is connected/removed from the PHY
7913 + * connector.
7914 + *
7915 + * @param core_if Programming view of DWC_otg controller.
7916 + */
7917 +int32_t dwc_otg_handle_conn_id_status_change_intr(dwc_otg_core_if_t *core_if)
7918 +{
7919 +
7920 +       /*
7921 +        * Need to disable SOF interrupt immediately. If switching from device
7922 +        * to host, the PCD interrupt handler won't handle the interrupt if
7923 +        * host mode is already set. The HCD interrupt handler won't get
7924 +        * called if the HCD state is HALT. This means that the interrupt does
7925 +        * not get handled and Linux complains loudly.
7926 +        */
7927 +       gintmsk_data_t gintmsk = { .d32 = 0 };
7928 +       gintsts_data_t gintsts = { .d32 = 0 };
7929 +
7930 +       gintmsk.b.sofintr = 1;
7931 +       dwc_modify_reg32(&core_if->core_global_regs->gintmsk, gintmsk.d32, 0);
7932 +
7933 +       DWC_DEBUGPL(DBG_CIL, " ++Connector ID Status Change Interrupt++  (%s)\n",
7934 +                    (dwc_otg_is_host_mode(core_if)?"Host":"Device"));
7935 +
7936 +       /*
7937 +        * Need to schedule a work, as there are possible DELAY function calls
7938 +       */
7939 +       queue_work(core_if->wq_otg, &core_if->w_conn_id);
7940 +
7941 +       /* Set flag and clear interrupt */
7942 +       gintsts.b.conidstschng = 1;
7943 +       dwc_write_reg32 (&core_if->core_global_regs->gintsts, gintsts.d32);
7944 +
7945 +       return 1;
7946 +}
7947 +
7948 +/**
7949 + * This interrupt indicates that a device is initiating the Session
7950 + * Request Protocol to request the host to turn on bus power so a new
7951 + * session can begin. The handler responds by turning on bus power. If
7952 + * the DWC_otg controller is in low power mode, the handler brings the
7953 + * controller out of low power mode before turning on bus power.
7954 + *
7955 + * @param core_if Programming view of DWC_otg controller.
7956 + */
7957 +int32_t dwc_otg_handle_session_req_intr(dwc_otg_core_if_t *core_if)
7958 +{
7959 +       gintsts_data_t gintsts;
7960 +
7961 +#ifndef DWC_HOST_ONLY
7962 +        hprt0_data_t hprt0;
7963 +       DWC_DEBUGPL(DBG_ANY, "++Session Request Interrupt++\n");
7964 +
7965 +        if (dwc_otg_is_device_mode(core_if)) {
7966 +                DWC_PRINT("SRP: Device mode\n");
7967 +        } else {
7968 +               DWC_PRINT("SRP: Host mode\n");
7969 +
7970 +               /* Turn on the port power bit. */
7971 +               hprt0.d32 = dwc_otg_read_hprt0(core_if);
7972 +               hprt0.b.prtpwr = 1;
7973 +               dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32);
7974 +
7975 +               /* Start the Connection timer. So a message can be displayed
7976 +                * if connect does not occur within 10 seconds. */
7977 +               hcd_session_start(core_if);
7978 +        }
7979 +#endif
7980 +
7981 +       /* Clear interrupt */
7982 +       gintsts.d32 = 0;
7983 +       gintsts.b.sessreqintr = 1;
7984 +       dwc_write_reg32 (&core_if->core_global_regs->gintsts, gintsts.d32);
7985 +
7986 +       return 1;
7987 +}
7988 +
7989 +
7990 +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,20)
7991 +void w_wakeup_detected(void *p)
7992 +{
7993 +       dwc_otg_core_if_t* core_if = p;
7994 +
7995 +#else
7996 +
7997 +void w_wakeup_detected(struct work_struct *p)
7998 +{
7999 +       struct delayed_work *dw = container_of(p, struct delayed_work, work);
8000 +       dwc_otg_core_if_t *core_if = container_of(dw, dwc_otg_core_if_t, w_wkp);
8001 +
8002 +#endif
8003 +        /*
8004 +        * Clear the Resume after 70ms. (Need 20 ms minimum. Use 70 ms
8005 +        * so that OPT tests pass with all PHYs).
8006 +        */
8007 +        hprt0_data_t hprt0 = {.d32=0};
8008 +#if 0
8009 +       pcgcctl_data_t pcgcctl = {.d32=0};
8010 +        /* Restart the Phy Clock */
8011 +        pcgcctl.b.stoppclk = 1;
8012 +        dwc_modify_reg32(core_if->pcgcctl, pcgcctl.d32, 0);
8013 +        UDELAY(10);
8014 +#endif //0
8015 +        hprt0.d32 = dwc_otg_read_hprt0(core_if);
8016 +        DWC_DEBUGPL(DBG_ANY,"Resume: HPRT0=%0x\n", hprt0.d32);
8017 +//      MDELAY(70);
8018 +        hprt0.b.prtres = 0; /* Resume */
8019 +        dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32);
8020 +        DWC_DEBUGPL(DBG_ANY,"Clear Resume: HPRT0=%0x\n", dwc_read_reg32(core_if->host_if->hprt0));
8021 +}
8022 +/**
8023 + * This interrupt indicates that the DWC_otg controller has detected a
8024 + * resume or remote wakeup sequence. If the DWC_otg controller is in
8025 + * low power mode, the handler must brings the controller out of low
8026 + * power mode. The controller automatically begins resume
8027 + * signaling. The handler schedules a time to stop resume signaling.
8028 + */
8029 +int32_t dwc_otg_handle_wakeup_detected_intr(dwc_otg_core_if_t *core_if)
8030 +{
8031 +       gintsts_data_t gintsts;
8032 +
8033 +       DWC_DEBUGPL(DBG_ANY, "++Resume and Remote Wakeup Detected Interrupt++\n");
8034 +
8035 +        if (dwc_otg_is_device_mode(core_if)) {
8036 +                dctl_data_t dctl = {.d32=0};
8037 +                DWC_DEBUGPL(DBG_PCD, "DSTS=0x%0x\n",
8038 +                            dwc_read_reg32(&core_if->dev_if->dev_global_regs->dsts));
8039 +#ifdef PARTIAL_POWER_DOWN
8040 +                if (core_if->hwcfg4.b.power_optimiz) {
8041 +                        pcgcctl_data_t power = {.d32=0};
8042 +
8043 +                        power.d32 = dwc_read_reg32(core_if->pcgcctl);
8044 +                        DWC_DEBUGPL(DBG_CIL, "PCGCCTL=%0x\n", power.d32);
8045 +
8046 +                        power.b.stoppclk = 0;
8047 +                        dwc_write_reg32(core_if->pcgcctl, power.d32);
8048 +
8049 +                        power.b.pwrclmp = 0;
8050 +                        dwc_write_reg32(core_if->pcgcctl, power.d32);
8051 +
8052 +                        power.b.rstpdwnmodule = 0;
8053 +                        dwc_write_reg32(core_if->pcgcctl, power.d32);
8054 +                }
8055 +#endif
8056 +                /* Clear the Remote Wakeup Signalling */
8057 +                dctl.b.rmtwkupsig = 1;
8058 +                dwc_modify_reg32(&core_if->dev_if->dev_global_regs->dctl,
8059 +                                  dctl.d32, 0);
8060 +
8061 +                if (core_if->pcd_cb && core_if->pcd_cb->resume_wakeup) {
8062 +                        core_if->pcd_cb->resume_wakeup(core_if->pcd_cb->p);
8063 +                }
8064 +
8065 +        } else {
8066 +               pcgcctl_data_t pcgcctl = {.d32=0};
8067 +
8068 +               /* Restart the Phy Clock */
8069 +               pcgcctl.b.stoppclk = 1;
8070 +               dwc_modify_reg32(core_if->pcgcctl, pcgcctl.d32, 0);
8071 +
8072 +               queue_delayed_work(core_if->wq_otg, &core_if->w_wkp, ((70 * HZ / 1000) + 1));
8073 +        }
8074 +
8075 +       /* Clear interrupt */
8076 +       gintsts.d32 = 0;
8077 +       gintsts.b.wkupintr = 1;
8078 +       dwc_write_reg32 (&core_if->core_global_regs->gintsts, gintsts.d32);
8079 +
8080 +       return 1;
8081 +}
8082 +
8083 +/**
8084 + * This interrupt indicates that a device has been disconnected from
8085 + * the root port.
8086 + */
8087 +int32_t dwc_otg_handle_disconnect_intr(dwc_otg_core_if_t *core_if)
8088 +{
8089 +       gintsts_data_t gintsts;
8090 +
8091 +       DWC_DEBUGPL(DBG_ANY, "++Disconnect Detected Interrupt++ (%s) %s\n",
8092 +                    (dwc_otg_is_host_mode(core_if)?"Host":"Device"),
8093 +                    op_state_str(core_if));
8094 +
8095 +/** @todo Consolidate this if statement. */
8096 +#ifndef DWC_HOST_ONLY
8097 +        if (core_if->op_state == B_HOST) {
8098 +                /* If in device mode Disconnect and stop the HCD, then
8099 +                 * start the PCD. */
8100 +                hcd_disconnect(core_if);
8101 +                pcd_start(core_if);
8102 +                core_if->op_state = B_PERIPHERAL;
8103 +        } else if (dwc_otg_is_device_mode(core_if)) {
8104 +                gotgctl_data_t gotgctl = { .d32 = 0 };
8105 +                gotgctl.d32 = dwc_read_reg32(&core_if->core_global_regs->gotgctl);
8106 +                if (gotgctl.b.hstsethnpen==1) {
8107 +                        /* Do nothing, if HNP in process the OTG
8108 +                         * interrupt "Host Negotiation Detected"
8109 +                         * interrupt will do the mode switch.
8110 +                         */
8111 +                } else if (gotgctl.b.devhnpen == 0) {
8112 +                        /* If in device mode Disconnect and stop the HCD, then
8113 +                         * start the PCD. */
8114 +                        hcd_disconnect(core_if);
8115 +                        pcd_start(core_if);
8116 +                        core_if->op_state = B_PERIPHERAL;
8117 +                } else {
8118 +                        DWC_DEBUGPL(DBG_ANY,"!a_peripheral && !devhnpen\n");
8119 +                }
8120 +        } else {
8121 +                if (core_if->op_state == A_HOST) {
8122 +                        /* A-Cable still connected but device disconnected. */
8123 +                        hcd_disconnect(core_if);
8124 +                }
8125 +        }
8126 +#endif
8127 +
8128 +       gintsts.d32 = 0;
8129 +       gintsts.b.disconnect = 1;
8130 +       dwc_write_reg32 (&core_if->core_global_regs->gintsts, gintsts.d32);
8131 +       return 1;
8132 +}
8133 +/**
8134 + * This interrupt indicates that SUSPEND state has been detected on
8135 + * the USB.
8136 + *
8137 + * For HNP the USB Suspend interrupt signals the change from
8138 + * "a_peripheral" to "a_host".
8139 + *
8140 + * When power management is enabled the core will be put in low power
8141 + * mode.
8142 + */
8143 +int32_t dwc_otg_handle_usb_suspend_intr(dwc_otg_core_if_t *core_if)
8144 +{
8145 +        dsts_data_t dsts;
8146 +        gintsts_data_t gintsts;
8147 +
8148 +        DWC_DEBUGPL(DBG_ANY,"USB SUSPEND\n");
8149 +
8150 +        if (dwc_otg_is_device_mode(core_if)) {
8151 +                /* Check the Device status register to determine if the Suspend
8152 +                 * state is active. */
8153 +                dsts.d32 = dwc_read_reg32(&core_if->dev_if->dev_global_regs->dsts);
8154 +                DWC_DEBUGPL(DBG_PCD, "DSTS=0x%0x\n", dsts.d32);
8155 +                DWC_DEBUGPL(DBG_PCD, "DSTS.Suspend Status=%d "
8156 +                            "HWCFG4.power Optimize=%d\n",
8157 +                            dsts.b.suspsts, core_if->hwcfg4.b.power_optimiz);
8158 +
8159 +
8160 +#ifdef PARTIAL_POWER_DOWN
8161 +/** @todo Add a module parameter for power management. */
8162 +
8163 +                if (dsts.b.suspsts && core_if->hwcfg4.b.power_optimiz) {
8164 +                        pcgcctl_data_t power = {.d32=0};
8165 +                        DWC_DEBUGPL(DBG_CIL, "suspend\n");
8166 +
8167 +                        power.b.pwrclmp = 1;
8168 +                        dwc_write_reg32(core_if->pcgcctl, power.d32);
8169 +
8170 +                        power.b.rstpdwnmodule = 1;
8171 +                        dwc_modify_reg32(core_if->pcgcctl, 0, power.d32);
8172 +
8173 +                        power.b.stoppclk = 1;
8174 +                        dwc_modify_reg32(core_if->pcgcctl, 0, power.d32);
8175 +
8176 +                } else {
8177 +                        DWC_DEBUGPL(DBG_ANY,"disconnect?\n");
8178 +                }
8179 +#endif
8180 +                /* PCD callback for suspend. */
8181 +                pcd_suspend(core_if);
8182 +        } else {
8183 +                if (core_if->op_state == A_PERIPHERAL) {
8184 +                        DWC_DEBUGPL(DBG_ANY,"a_peripheral->a_host\n");
8185 +                        /* Clear the a_peripheral flag, back to a_host. */
8186 +                        pcd_stop(core_if);
8187 +                        hcd_start(core_if);
8188 +                        core_if->op_state = A_HOST;
8189 +                }
8190 +        }
8191 +
8192 +       /* Clear interrupt */
8193 +       gintsts.d32 = 0;
8194 +       gintsts.b.usbsuspend = 1;
8195 +       dwc_write_reg32(&core_if->core_global_regs->gintsts, gintsts.d32);
8196 +
8197 +        return 1;
8198 +}
8199 +
8200 +
8201 +/**
8202 + * This function returns the Core Interrupt register.
8203 + */
8204 +static inline uint32_t dwc_otg_read_common_intr(dwc_otg_core_if_t *core_if)
8205 +{
8206 +        gintsts_data_t gintsts;
8207 +        gintmsk_data_t gintmsk;
8208 +        gintmsk_data_t gintmsk_common = {.d32=0};
8209 +       gintmsk_common.b.wkupintr = 1;
8210 +       gintmsk_common.b.sessreqintr = 1;
8211 +       gintmsk_common.b.conidstschng = 1;
8212 +       gintmsk_common.b.otgintr = 1;
8213 +       gintmsk_common.b.modemismatch = 1;
8214 +        gintmsk_common.b.disconnect = 1;
8215 +        gintmsk_common.b.usbsuspend = 1;
8216 +        /** @todo: The port interrupt occurs while in device
8217 +         * mode. Added code to CIL to clear the interrupt for now!
8218 +         */
8219 +        gintmsk_common.b.portintr = 1;
8220 +
8221 +        gintsts.d32 = dwc_read_reg32(&core_if->core_global_regs->gintsts);
8222 +        gintmsk.d32 = dwc_read_reg32(&core_if->core_global_regs->gintmsk);
8223 +#ifdef DEBUG
8224 +        /* if any common interrupts set */
8225 +        if (gintsts.d32 & gintmsk_common.d32) {
8226 +                DWC_DEBUGPL(DBG_ANY, "gintsts=%08x  gintmsk=%08x\n",
8227 +                            gintsts.d32, gintmsk.d32);
8228 +        }
8229 +#endif
8230 +
8231 +        return ((gintsts.d32 & gintmsk.d32) & gintmsk_common.d32);
8232 +
8233 +}
8234 +
8235 +/**
8236 + * Common interrupt handler.
8237 + *
8238 + * The common interrupts are those that occur in both Host and Device mode.
8239 + * This handler handles the following interrupts:
8240 + * - Mode Mismatch Interrupt
8241 + * - Disconnect Interrupt
8242 + * - OTG Interrupt
8243 + * - Connector ID Status Change Interrupt
8244 + * - Session Request Interrupt.
8245 + * - Resume / Remote Wakeup Detected Interrupt.
8246 + *
8247 + */
8248 +int32_t dwc_otg_handle_common_intr(dwc_otg_core_if_t *core_if)
8249 +{
8250 +       int retval = 0;
8251 +        gintsts_data_t gintsts;
8252 +
8253 +        gintsts.d32 = dwc_otg_read_common_intr(core_if);
8254 +
8255 +        if (gintsts.b.modemismatch) {
8256 +                retval |= dwc_otg_handle_mode_mismatch_intr(core_if);
8257 +        }
8258 +        if (gintsts.b.otgintr) {
8259 +                retval |= dwc_otg_handle_otg_intr(core_if);
8260 +        }
8261 +        if (gintsts.b.conidstschng) {
8262 +                retval |= dwc_otg_handle_conn_id_status_change_intr(core_if);
8263 +        }
8264 +        if (gintsts.b.disconnect) {
8265 +                retval |= dwc_otg_handle_disconnect_intr(core_if);
8266 +        }
8267 +        if (gintsts.b.sessreqintr) {
8268 +                retval |= dwc_otg_handle_session_req_intr(core_if);
8269 +        }
8270 +        if (gintsts.b.wkupintr) {
8271 +                retval |= dwc_otg_handle_wakeup_detected_intr(core_if);
8272 +        }
8273 +        if (gintsts.b.usbsuspend) {
8274 +                retval |= dwc_otg_handle_usb_suspend_intr(core_if);
8275 +        }
8276 +        if (gintsts.b.portintr && dwc_otg_is_device_mode(core_if)) {
8277 +                /* The port interrupt occurs while in device mode with HPRT0
8278 +                 * Port Enable/Disable.
8279 +                 */
8280 +                gintsts.d32 = 0;
8281 +                gintsts.b.portintr = 1;
8282 +                dwc_write_reg32(&core_if->core_global_regs->gintsts,
8283 +                                gintsts.d32);
8284 +                retval |= 1;
8285 +
8286 +        }
8287 +
8288 +       S3C2410X_CLEAR_EINTPEND();
8289 +
8290 +        return retval;
8291 +}
8292 --- /dev/null
8293 +++ b/drivers/usb/dwc_otg/dwc_otg_driver.c
8294 @@ -0,0 +1,1273 @@
8295 +/* ==========================================================================
8296 + * $File: //dwh/usb_iip/dev/software/otg_ipmate/linux/drivers/dwc_otg_driver.c $
8297 + * $Revision: 1.7 $
8298 + * $Date: 2008-11-21 05:39:15 $
8299 + * $Change: 791271 $
8300 + *
8301 + * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
8302 + * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
8303 + * otherwise expressly agreed to in writing between Synopsys and you.
8304 + *
8305 + * The Software IS NOT an item of Licensed Software or Licensed Product under
8306 + * any End User Software License Agreement or Agreement for Licensed Product
8307 + * with Synopsys or any supplement thereto. You are permitted to use and
8308 + * redistribute this Software in source and binary forms, with or without
8309 + * modification, provided that redistributions of source code must retain this
8310 + * notice. You may not view, use, disclose, copy or distribute this file or
8311 + * any information contained herein except pursuant to this license grant from
8312 + * Synopsys. If you do not agree with this notice, including the disclaimer
8313 + * below, then you are not authorized to use the Software.
8314 + *
8315 + * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
8316 + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
8317 + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
8318 + * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
8319 + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
8320 + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
8321 + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
8322 + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
8323 + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
8324 + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
8325 + * DAMAGE.
8326 + * ========================================================================== */
8327 +
8328 +/** @file
8329 + * The dwc_otg_driver module provides the initialization and cleanup entry
8330 + * points for the DWC_otg driver. This module will be dynamically installed
8331 + * after Linux is booted using the insmod command. When the module is
8332 + * installed, the dwc_otg_driver_init function is called. When the module is
8333 + * removed (using rmmod), the dwc_otg_driver_cleanup function is called.
8334 + *
8335 + * This module also defines a data structure for the dwc_otg_driver, which is
8336 + * used in conjunction with the standard ARM platform_device structure. These
8337 + * structures allow the OTG driver to comply with the standard Linux driver
8338 + * model in which devices and drivers are registered with a bus driver. This
8339 + * has the benefit that Linux can expose attributes of the driver and device
8340 + * in its special sysfs file system. Users can then read or write files in
8341 + * this file system to perform diagnostics on the driver components or the
8342 + * device.
8343 + */
8344 +
8345 +#include <linux/kernel.h>
8346 +#include <linux/module.h>
8347 +#include <linux/moduleparam.h>
8348 +#include <linux/init.h>
8349 +#include <linux/device.h>
8350 +#include <linux/errno.h>
8351 +#include <linux/types.h>
8352 +#include <linux/stat.h>         /* permission constants */
8353 +#include <linux/version.h>
8354 +#include <linux/platform_device.h>
8355 +
8356 +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20)
8357 +# include <linux/irq.h>
8358 +#endif
8359 +
8360 +#include <asm/io.h>
8361 +
8362 +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,20)
8363 +# include <asm/irq.h>
8364 +#endif
8365 +
8366 +#include "linux/dwc_otg_plat.h"
8367 +#include "dwc_otg_attr.h"
8368 +#include "dwc_otg_driver.h"
8369 +#include "dwc_otg_cil.h"
8370 +#include "dwc_otg_pcd.h"
8371 +#include "dwc_otg_hcd.h"
8372 +
8373 +#define DWC_DRIVER_VERSION     "2.72a 24-JUN-2008"
8374 +#define DWC_DRIVER_DESC                "HS OTG USB Controller driver"
8375 +
8376 +static const char dwc_driver_name[] = "dwc_otg";
8377 +
8378 +/*-------------------------------------------------------------------------*/
8379 +/* Encapsulate the module parameter settings */
8380 +
8381 +static dwc_otg_core_params_t dwc_otg_module_params = {
8382 +       .opt = -1,
8383 +       .otg_cap = -1,
8384 +       .dma_enable = -1,
8385 +       .dma_desc_enable = -1,
8386 +       .dma_burst_size = -1,
8387 +       .speed = -1,
8388 +       .host_support_fs_ls_low_power = -1,
8389 +       .host_ls_low_power_phy_clk = -1,
8390 +       .enable_dynamic_fifo = -1,
8391 +       .data_fifo_size = -1,
8392 +       .dev_rx_fifo_size = -1,
8393 +       .dev_nperio_tx_fifo_size = -1,
8394 +       .dev_perio_tx_fifo_size = {
8395 +               /* dev_perio_tx_fifo_size_1 */
8396 +               -1,
8397 +               -1,
8398 +               -1,
8399 +               -1,
8400 +               -1,
8401 +               -1,
8402 +               -1,
8403 +               -1,
8404 +               -1,
8405 +               -1,
8406 +               -1,
8407 +               -1,
8408 +               -1,
8409 +               -1,
8410 +               -1
8411 +               /* 15 */
8412 +       },
8413 +       .host_rx_fifo_size = -1,
8414 +       .host_nperio_tx_fifo_size = -1,
8415 +       .host_perio_tx_fifo_size = -1,
8416 +       .max_transfer_size = -1,
8417 +       .max_packet_count = -1,
8418 +       .host_channels = -1,
8419 +       .dev_endpoints = -1,
8420 +       .phy_type = -1,
8421 +       .phy_utmi_width = -1,
8422 +       .phy_ulpi_ddr = -1,
8423 +       .phy_ulpi_ext_vbus = -1,
8424 +       .i2c_enable = -1,
8425 +       .ulpi_fs_ls = -1,
8426 +       .ts_dline = -1,
8427 +       .en_multiple_tx_fifo = -1,
8428 +       .dev_tx_fifo_size = {
8429 +               /* dev_tx_fifo_size */
8430 +               -1,
8431 +               -1,
8432 +               -1,
8433 +               -1,
8434 +               -1,
8435 +               -1,
8436 +               -1,
8437 +               -1,
8438 +               -1,
8439 +               -1,
8440 +               -1,
8441 +               -1,
8442 +               -1,
8443 +               -1,
8444 +               -1
8445 +               /* 15 */
8446 +       },
8447 +       .thr_ctl = -1,
8448 +       .tx_thr_length = -1,
8449 +       .rx_thr_length = -1,
8450 +       .pti_enable = -1,
8451 +       .mpi_enable = -1,
8452 +};
8453 +
8454 +/**
8455 + * This function shows the Driver Version.
8456 + */
8457 +static ssize_t version_show(struct device_driver *dev, char *buf)
8458 +{
8459 +       return snprintf(buf, sizeof(DWC_DRIVER_VERSION)+2, "%s\n",
8460 +                       DWC_DRIVER_VERSION);
8461 +}
8462 +static DRIVER_ATTR(version, S_IRUGO, version_show, NULL);
8463 +
8464 +/**
8465 + * Global Debug Level Mask.
8466 + */
8467 +uint32_t g_dbg_lvl = 0; /* OFF */
8468 +
8469 +/**
8470 + * This function shows the driver Debug Level.
8471 + */
8472 +static ssize_t dbg_level_show(struct device_driver *drv, char *buf)
8473 +{
8474 +       return sprintf(buf, "0x%0x\n", g_dbg_lvl);
8475 +}
8476 +
8477 +/**
8478 + * This function stores the driver Debug Level.
8479 + */
8480 +static ssize_t dbg_level_store(struct device_driver *drv, const char *buf,
8481 +                              size_t count)
8482 +{
8483 +       g_dbg_lvl = simple_strtoul(buf, NULL, 16);
8484 +               return count;
8485 +}
8486 +static DRIVER_ATTR(debuglevel, S_IRUGO|S_IWUSR, dbg_level_show, dbg_level_store);
8487 +
8488 +/**
8489 + * This function is called during module intialization to verify that
8490 + * the module parameters are in a valid state.
8491 + */
8492 +static int check_parameters(dwc_otg_core_if_t *core_if)
8493 +{
8494 +       int i;
8495 +       int retval = 0;
8496 +
8497 +/* Checks if the parameter is outside of its valid range of values */
8498 +#define DWC_OTG_PARAM_TEST(_param_, _low_, _high_) \
8499 +               ((dwc_otg_module_params._param_ < (_low_)) || \
8500 +               (dwc_otg_module_params._param_ > (_high_)))
8501 +
8502 +/* If the parameter has been set by the user, check that the parameter value is
8503 + * within the value range of values.  If not, report a module error. */
8504 +#define DWC_OTG_PARAM_ERR(_param_, _low_, _high_, _string_) \
8505 +               do { \
8506 +                       if (dwc_otg_module_params._param_ != -1) { \
8507 +                               if (DWC_OTG_PARAM_TEST(_param_, (_low_), (_high_))) { \
8508 +                                       DWC_ERROR("`%d' invalid for parameter `%s'\n", \
8509 +                                                 dwc_otg_module_params._param_, _string_); \
8510 +                                       dwc_otg_module_params._param_ = dwc_param_##_param_##_default; \
8511 +                                       retval++; \
8512 +                               } \
8513 +                       } \
8514 +               } while (0)
8515 +
8516 +       DWC_OTG_PARAM_ERR(opt,0,1,"opt");
8517 +       DWC_OTG_PARAM_ERR(otg_cap,0,2,"otg_cap");
8518 +       DWC_OTG_PARAM_ERR(dma_enable,0,1,"dma_enable");
8519 +       DWC_OTG_PARAM_ERR(dma_desc_enable,0,1,"dma_desc_enable");
8520 +       DWC_OTG_PARAM_ERR(speed,0,1,"speed");
8521 +       DWC_OTG_PARAM_ERR(host_support_fs_ls_low_power,0,1,"host_support_fs_ls_low_power");
8522 +       DWC_OTG_PARAM_ERR(host_ls_low_power_phy_clk,0,1,"host_ls_low_power_phy_clk");
8523 +       DWC_OTG_PARAM_ERR(enable_dynamic_fifo,0,1,"enable_dynamic_fifo");
8524 +       DWC_OTG_PARAM_ERR(data_fifo_size,32,32768,"data_fifo_size");
8525 +       DWC_OTG_PARAM_ERR(dev_rx_fifo_size,16,32768,"dev_rx_fifo_size");
8526 +       DWC_OTG_PARAM_ERR(dev_nperio_tx_fifo_size,16,32768,"dev_nperio_tx_fifo_size");
8527 +       DWC_OTG_PARAM_ERR(host_rx_fifo_size,16,32768,"host_rx_fifo_size");
8528 +       DWC_OTG_PARAM_ERR(host_nperio_tx_fifo_size,16,32768,"host_nperio_tx_fifo_size");
8529 +       DWC_OTG_PARAM_ERR(host_perio_tx_fifo_size,16,32768,"host_perio_tx_fifo_size");
8530 +       DWC_OTG_PARAM_ERR(max_transfer_size,2047,524288,"max_transfer_size");
8531 +       DWC_OTG_PARAM_ERR(max_packet_count,15,511,"max_packet_count");
8532 +       DWC_OTG_PARAM_ERR(host_channels,1,16,"host_channels");
8533 +       DWC_OTG_PARAM_ERR(dev_endpoints,1,15,"dev_endpoints");
8534 +       DWC_OTG_PARAM_ERR(phy_type,0,2,"phy_type");
8535 +       DWC_OTG_PARAM_ERR(phy_ulpi_ddr,0,1,"phy_ulpi_ddr");
8536 +       DWC_OTG_PARAM_ERR(phy_ulpi_ext_vbus,0,1,"phy_ulpi_ext_vbus");
8537 +       DWC_OTG_PARAM_ERR(i2c_enable,0,1,"i2c_enable");
8538 +       DWC_OTG_PARAM_ERR(ulpi_fs_ls,0,1,"ulpi_fs_ls");
8539 +       DWC_OTG_PARAM_ERR(ts_dline,0,1,"ts_dline");
8540 +
8541 +       if (dwc_otg_module_params.dma_burst_size != -1) {
8542 +               if (DWC_OTG_PARAM_TEST(dma_burst_size,1,1) &&
8543 +                   DWC_OTG_PARAM_TEST(dma_burst_size,4,4) &&
8544 +                   DWC_OTG_PARAM_TEST(dma_burst_size,8,8) &&
8545 +                   DWC_OTG_PARAM_TEST(dma_burst_size,16,16) &&
8546 +                   DWC_OTG_PARAM_TEST(dma_burst_size,32,32) &&
8547 +                   DWC_OTG_PARAM_TEST(dma_burst_size,64,64) &&
8548 +                   DWC_OTG_PARAM_TEST(dma_burst_size,128,128) &&
8549 +                   DWC_OTG_PARAM_TEST(dma_burst_size,256,256)) {
8550 +                       DWC_ERROR("`%d' invalid for parameter `dma_burst_size'\n",
8551 +                                 dwc_otg_module_params.dma_burst_size);
8552 +                       dwc_otg_module_params.dma_burst_size = 32;
8553 +                       retval++;
8554 +               }
8555 +
8556 +               {
8557 +                       uint8_t brst_sz = 0;
8558 +                       while(dwc_otg_module_params.dma_burst_size > 1) {
8559 +                               brst_sz ++;
8560 +                               dwc_otg_module_params.dma_burst_size >>= 1;
8561 +                       }
8562 +                       dwc_otg_module_params.dma_burst_size = brst_sz;
8563 +               }
8564 +       }
8565 +
8566 +       if (dwc_otg_module_params.phy_utmi_width != -1) {
8567 +               if (DWC_OTG_PARAM_TEST(phy_utmi_width, 8, 8) &&
8568 +                   DWC_OTG_PARAM_TEST(phy_utmi_width, 16, 16)) {
8569 +                       DWC_ERROR("`%d' invalid for parameter `phy_utmi_width'\n",
8570 +                                 dwc_otg_module_params.phy_utmi_width);
8571 +                       dwc_otg_module_params.phy_utmi_width = 16;
8572 +                       retval++;
8573 +               }
8574 +       }
8575 +
8576 +       for (i = 0; i < 15; i++) {
8577 +               /** @todo should be like above */
8578 +               //DWC_OTG_PARAM_ERR(dev_perio_tx_fifo_size[i], 4, 768, "dev_perio_tx_fifo_size");
8579 +               if (dwc_otg_module_params.dev_perio_tx_fifo_size[i] != -1) {
8580 +                       if (DWC_OTG_PARAM_TEST(dev_perio_tx_fifo_size[i], 4, 768)) {
8581 +                               DWC_ERROR("`%d' invalid for parameter `%s_%d'\n",
8582 +                                         dwc_otg_module_params.dev_perio_tx_fifo_size[i], "dev_perio_tx_fifo_size", i);
8583 +                               dwc_otg_module_params.dev_perio_tx_fifo_size[i] = dwc_param_dev_perio_tx_fifo_size_default;
8584 +                               retval++;
8585 +                       }
8586 +               }
8587 +       }
8588 +
8589 +       DWC_OTG_PARAM_ERR(en_multiple_tx_fifo, 0, 1, "en_multiple_tx_fifo");
8590 +
8591 +       for (i = 0; i < 15; i++) {
8592 +               /** @todo should be like above */
8593 +               //DWC_OTG_PARAM_ERR(dev_tx_fifo_size[i], 4, 768, "dev_tx_fifo_size");
8594 +               if (dwc_otg_module_params.dev_tx_fifo_size[i] != -1) {
8595 +                       if (DWC_OTG_PARAM_TEST(dev_tx_fifo_size[i], 4, 768)) {
8596 +                               DWC_ERROR("`%d' invalid for parameter `%s_%d'\n",
8597 +                                         dwc_otg_module_params.dev_tx_fifo_size[i], "dev_tx_fifo_size", i);
8598 +                               dwc_otg_module_params.dev_tx_fifo_size[i] = dwc_param_dev_tx_fifo_size_default;
8599 +                               retval++;
8600 +                       }
8601 +               }
8602 +       }
8603 +
8604 +       DWC_OTG_PARAM_ERR(thr_ctl, 0, 7, "thr_ctl");
8605 +       DWC_OTG_PARAM_ERR(tx_thr_length, 8, 128, "tx_thr_length");
8606 +       DWC_OTG_PARAM_ERR(rx_thr_length, 8, 128, "rx_thr_length");
8607 +
8608 +       DWC_OTG_PARAM_ERR(pti_enable,0,1,"pti_enable");
8609 +       DWC_OTG_PARAM_ERR(mpi_enable,0,1,"mpi_enable");
8610 +
8611 +       /* At this point, all module parameters that have been set by the user
8612 +        * are valid, and those that have not are left unset.  Now set their
8613 +        * default values and/or check the parameters against the hardware
8614 +        * configurations of the OTG core. */
8615 +
8616 +/* This sets the parameter to the default value if it has not been set by the
8617 + * user */
8618 +#define DWC_OTG_PARAM_SET_DEFAULT(_param_) \
8619 +       ({ \
8620 +               int changed = 1; \
8621 +               if (dwc_otg_module_params._param_ == -1) { \
8622 +                       changed = 0; \
8623 +                       dwc_otg_module_params._param_ = dwc_param_##_param_##_default; \
8624 +               } \
8625 +               changed; \
8626 +       })
8627 +
8628 +/* This checks the macro agains the hardware configuration to see if it is
8629 + * valid.  It is possible that the default value could be invalid. In this
8630 + * case, it will report a module error if the user touched the parameter.
8631 + * Otherwise it will adjust the value without any error. */
8632 +#define DWC_OTG_PARAM_CHECK_VALID(_param_, _str_, _is_valid_, _set_valid_) \
8633 +       ({ \
8634 +               int changed = DWC_OTG_PARAM_SET_DEFAULT(_param_); \
8635 +               int error = 0; \
8636 +               if (!(_is_valid_)) { \
8637 +                       if (changed) { \
8638 +                               DWC_ERROR("`%d' invalid for parameter `%s'. Check HW configuration.\n", dwc_otg_module_params._param_, _str_); \
8639 +                               error = 1; \
8640 +                       } \
8641 +                       dwc_otg_module_params._param_ = (_set_valid_); \
8642 +               } \
8643 +               error; \
8644 +       })
8645 +
8646 +       /* OTG Cap */
8647 +       retval += DWC_OTG_PARAM_CHECK_VALID(otg_cap, "otg_cap",
8648 +                               ({
8649 +                                       int valid;
8650 +                                       valid = 1;
8651 +                                       switch (dwc_otg_module_params.otg_cap) {
8652 +                                       case DWC_OTG_CAP_PARAM_HNP_SRP_CAPABLE:
8653 +                                               if (core_if->hwcfg2.b.op_mode != DWC_HWCFG2_OP_MODE_HNP_SRP_CAPABLE_OTG)
8654 +                                                       valid = 0;
8655 +                                               break;
8656 +                                       case DWC_OTG_CAP_PARAM_SRP_ONLY_CAPABLE:
8657 +                                               if ((core_if->hwcfg2.b.op_mode != DWC_HWCFG2_OP_MODE_HNP_SRP_CAPABLE_OTG) &&
8658 +                                                   (core_if->hwcfg2.b.op_mode != DWC_HWCFG2_OP_MODE_SRP_ONLY_CAPABLE_OTG) &&
8659 +                                                   (core_if->hwcfg2.b.op_mode != DWC_HWCFG2_OP_MODE_SRP_CAPABLE_DEVICE) &&
8660 +                                                   (core_if->hwcfg2.b.op_mode != DWC_HWCFG2_OP_MODE_SRP_CAPABLE_HOST)) {
8661 +                                                       valid = 0;
8662 +                                               }
8663 +                                               break;
8664 +                                       case DWC_OTG_CAP_PARAM_NO_HNP_SRP_CAPABLE:
8665 +                                               /* always valid */
8666 +                                               break;
8667 +                                       }
8668 +                                       valid;
8669 +                               }),
8670 +                               (((core_if->hwcfg2.b.op_mode == DWC_HWCFG2_OP_MODE_HNP_SRP_CAPABLE_OTG) ||
8671 +                                 (core_if->hwcfg2.b.op_mode == DWC_HWCFG2_OP_MODE_SRP_ONLY_CAPABLE_OTG) ||
8672 +                                 (core_if->hwcfg2.b.op_mode == DWC_HWCFG2_OP_MODE_SRP_CAPABLE_DEVICE) ||
8673 +                                 (core_if->hwcfg2.b.op_mode == DWC_HWCFG2_OP_MODE_SRP_CAPABLE_HOST)) ?
8674 +                                DWC_OTG_CAP_PARAM_SRP_ONLY_CAPABLE :
8675 +                                DWC_OTG_CAP_PARAM_NO_HNP_SRP_CAPABLE));
8676 +
8677 +       retval += DWC_OTG_PARAM_CHECK_VALID(dma_enable, "dma_enable",
8678 +                               ((dwc_otg_module_params.dma_enable == 1) && (core_if->hwcfg2.b.architecture == 0)) ? 0 : 1,
8679 +                               0);
8680 +
8681 +       retval += DWC_OTG_PARAM_CHECK_VALID(dma_desc_enable, "dma_desc_enable",
8682 +                               ((dwc_otg_module_params.dma_desc_enable == 1) &&
8683 +                                ((dwc_otg_module_params.dma_enable == 0) || (core_if->hwcfg4.b.desc_dma == 0))) ? 0 : 1,
8684 +                               0);
8685 +
8686 +       retval += DWC_OTG_PARAM_CHECK_VALID(opt, "opt", 1, 0);
8687 +
8688 +       DWC_OTG_PARAM_SET_DEFAULT(dma_burst_size);
8689 +
8690 +       retval += DWC_OTG_PARAM_CHECK_VALID(host_support_fs_ls_low_power,
8691 +                               "host_support_fs_ls_low_power",
8692 +                               1, 0);
8693 +
8694 +       retval += DWC_OTG_PARAM_CHECK_VALID(enable_dynamic_fifo,
8695 +                                       "enable_dynamic_fifo",
8696 +                                       ((dwc_otg_module_params.enable_dynamic_fifo == 0) ||
8697 +                                       (core_if->hwcfg2.b.dynamic_fifo == 1)), 0);
8698 +
8699 +       retval += DWC_OTG_PARAM_CHECK_VALID(data_fifo_size,
8700 +                                       "data_fifo_size",
8701 +                                       (dwc_otg_module_params.data_fifo_size <= core_if->hwcfg3.b.dfifo_depth),
8702 +                                       core_if->hwcfg3.b.dfifo_depth);
8703 +
8704 +       retval += DWC_OTG_PARAM_CHECK_VALID(dev_rx_fifo_size,
8705 +                                       "dev_rx_fifo_size",
8706 +                                       (dwc_otg_module_params.dev_rx_fifo_size <= dwc_read_reg32(&core_if->core_global_regs->grxfsiz)),
8707 +                                       dwc_read_reg32(&core_if->core_global_regs->grxfsiz));
8708 +
8709 +       retval += DWC_OTG_PARAM_CHECK_VALID(dev_nperio_tx_fifo_size,
8710 +                                       "dev_nperio_tx_fifo_size",
8711 +                                       (dwc_otg_module_params.dev_nperio_tx_fifo_size <= (dwc_read_reg32(&core_if->core_global_regs->gnptxfsiz) >> 16)),
8712 +                                       (dwc_read_reg32(&core_if->core_global_regs->gnptxfsiz) >> 16));
8713 +
8714 +       retval += DWC_OTG_PARAM_CHECK_VALID(host_rx_fifo_size,
8715 +                                       "host_rx_fifo_size",
8716 +                                       (dwc_otg_module_params.host_rx_fifo_size <= dwc_read_reg32(&core_if->core_global_regs->grxfsiz)),
8717 +                                       dwc_read_reg32(&core_if->core_global_regs->grxfsiz));
8718 +
8719 +       retval += DWC_OTG_PARAM_CHECK_VALID(host_nperio_tx_fifo_size,
8720 +                                       "host_nperio_tx_fifo_size",
8721 +                                       (dwc_otg_module_params.host_nperio_tx_fifo_size <= (dwc_read_reg32(&core_if->core_global_regs->gnptxfsiz) >> 16)),
8722 +                                       (dwc_read_reg32(&core_if->core_global_regs->gnptxfsiz) >> 16));
8723 +
8724 +       retval += DWC_OTG_PARAM_CHECK_VALID(host_perio_tx_fifo_size,
8725 +                                       "host_perio_tx_fifo_size",
8726 +                                       (dwc_otg_module_params.host_perio_tx_fifo_size <= ((dwc_read_reg32(&core_if->core_global_regs->hptxfsiz) >> 16))),
8727 +                                       ((dwc_read_reg32(&core_if->core_global_regs->hptxfsiz) >> 16)));
8728 +
8729 +       retval += DWC_OTG_PARAM_CHECK_VALID(max_transfer_size,
8730 +                                       "max_transfer_size",
8731 +                                       (dwc_otg_module_params.max_transfer_size < (1 << (core_if->hwcfg3.b.xfer_size_cntr_width + 11))),
8732 +                                       ((1 << (core_if->hwcfg3.b.xfer_size_cntr_width + 11)) - 1));
8733 +
8734 +       retval += DWC_OTG_PARAM_CHECK_VALID(max_packet_count,
8735 +                                       "max_packet_count",
8736 +                                       (dwc_otg_module_params.max_packet_count < (1 << (core_if->hwcfg3.b.packet_size_cntr_width + 4))),
8737 +                                       ((1 << (core_if->hwcfg3.b.packet_size_cntr_width + 4)) - 1));
8738 +
8739 +       retval += DWC_OTG_PARAM_CHECK_VALID(host_channels,
8740 +                                       "host_channels",
8741 +                                       (dwc_otg_module_params.host_channels <= (core_if->hwcfg2.b.num_host_chan + 1)),
8742 +                                       (core_if->hwcfg2.b.num_host_chan + 1));
8743 +
8744 +       retval += DWC_OTG_PARAM_CHECK_VALID(dev_endpoints,
8745 +                                       "dev_endpoints",
8746 +                                       (dwc_otg_module_params.dev_endpoints <= (core_if->hwcfg2.b.num_dev_ep)),
8747 +                                       core_if->hwcfg2.b.num_dev_ep);
8748 +
8749 +/*
8750 + * Define the following to disable the FS PHY Hardware checking.  This is for
8751 + * internal testing only.
8752 + *
8753 + * #define NO_FS_PHY_HW_CHECKS
8754 + */
8755 +
8756 +#ifdef NO_FS_PHY_HW_CHECKS
8757 +       retval += DWC_OTG_PARAM_CHECK_VALID(phy_type,
8758 +                               "phy_type", 1, 0);
8759 +#else
8760 +       retval += DWC_OTG_PARAM_CHECK_VALID(phy_type,
8761 +                               "phy_type",
8762 +                               ({
8763 +                                       int valid = 0;
8764 +                                       if ((dwc_otg_module_params.phy_type == DWC_PHY_TYPE_PARAM_UTMI) &&
8765 +                                       ((core_if->hwcfg2.b.hs_phy_type == 1) ||
8766 +                                        (core_if->hwcfg2.b.hs_phy_type == 3))) {
8767 +                                               valid = 1;
8768 +                                       }
8769 +                                       else if ((dwc_otg_module_params.phy_type == DWC_PHY_TYPE_PARAM_ULPI) &&
8770 +                                                ((core_if->hwcfg2.b.hs_phy_type == 2) ||
8771 +                                                 (core_if->hwcfg2.b.hs_phy_type == 3))) {
8772 +                                               valid = 1;
8773 +                                       }
8774 +                                       else if ((dwc_otg_module_params.phy_type == DWC_PHY_TYPE_PARAM_FS) &&
8775 +                                                (core_if->hwcfg2.b.fs_phy_type == 1)) {
8776 +                                               valid = 1;
8777 +                                       }
8778 +                                       valid;
8779 +                               }),
8780 +                               ({
8781 +                                       int set = DWC_PHY_TYPE_PARAM_FS;
8782 +                                       if (core_if->hwcfg2.b.hs_phy_type) {
8783 +                                               if ((core_if->hwcfg2.b.hs_phy_type == 3) ||
8784 +                                               (core_if->hwcfg2.b.hs_phy_type == 1)) {
8785 +                                                       set = DWC_PHY_TYPE_PARAM_UTMI;
8786 +                                               }
8787 +                                               else {
8788 +                                                       set = DWC_PHY_TYPE_PARAM_ULPI;
8789 +                                               }
8790 +                                       }
8791 +                                       set;
8792 +                               }));
8793 +#endif
8794 +
8795 +       retval += DWC_OTG_PARAM_CHECK_VALID(speed, "speed",
8796 +                               (dwc_otg_module_params.speed == 0) && (dwc_otg_module_params.phy_type == DWC_PHY_TYPE_PARAM_FS) ? 0 : 1,
8797 +                               dwc_otg_module_params.phy_type == DWC_PHY_TYPE_PARAM_FS ? 1 : 0);
8798 +
8799 +       retval += DWC_OTG_PARAM_CHECK_VALID(host_ls_low_power_phy_clk,
8800 +                               "host_ls_low_power_phy_clk",
8801 +                               ((dwc_otg_module_params.host_ls_low_power_phy_clk == DWC_HOST_LS_LOW_POWER_PHY_CLK_PARAM_48MHZ) && (dwc_otg_module_params.phy_type == DWC_PHY_TYPE_PARAM_FS) ? 0 : 1),
8802 +                               ((dwc_otg_module_params.phy_type == DWC_PHY_TYPE_PARAM_FS) ? DWC_HOST_LS_LOW_POWER_PHY_CLK_PARAM_6MHZ : DWC_HOST_LS_LOW_POWER_PHY_CLK_PARAM_48MHZ));
8803 +
8804 +       DWC_OTG_PARAM_SET_DEFAULT(phy_ulpi_ddr);
8805 +       DWC_OTG_PARAM_SET_DEFAULT(phy_ulpi_ext_vbus);
8806 +       DWC_OTG_PARAM_SET_DEFAULT(phy_utmi_width);
8807 +       DWC_OTG_PARAM_SET_DEFAULT(ulpi_fs_ls);
8808 +       DWC_OTG_PARAM_SET_DEFAULT(ts_dline);
8809 +
8810 +#ifdef NO_FS_PHY_HW_CHECKS
8811 +       retval += DWC_OTG_PARAM_CHECK_VALID(i2c_enable, "i2c_enable", 1, 0);
8812 +#else
8813 +       retval += DWC_OTG_PARAM_CHECK_VALID(i2c_enable,
8814 +                               "i2c_enable",
8815 +                               (dwc_otg_module_params.i2c_enable == 1) && (core_if->hwcfg3.b.i2c == 0) ? 0 : 1,
8816 +                               0);
8817 +#endif
8818 +
8819 +       for (i = 0; i < 15; i++) {
8820 +               int changed = 1;
8821 +               int error = 0;
8822 +
8823 +               if (dwc_otg_module_params.dev_perio_tx_fifo_size[i] == -1) {
8824 +                       changed = 0;
8825 +                       dwc_otg_module_params.dev_perio_tx_fifo_size[i] = dwc_param_dev_perio_tx_fifo_size_default;
8826 +               }
8827 +               if (!(dwc_otg_module_params.dev_perio_tx_fifo_size[i] <= (dwc_read_reg32(&core_if->core_global_regs->dptxfsiz_dieptxf[i])))) {
8828 +                       if (changed) {
8829 +                               DWC_ERROR("`%d' invalid for parameter `dev_perio_fifo_size_%d'. Check HW configuration.\n", dwc_otg_module_params.dev_perio_tx_fifo_size[i], i);
8830 +                               error = 1;
8831 +                       }
8832 +                       dwc_otg_module_params.dev_perio_tx_fifo_size[i] = dwc_read_reg32(&core_if->core_global_regs->dptxfsiz_dieptxf[i]);
8833 +               }
8834 +               retval += error;
8835 +       }
8836 +
8837 +       retval += DWC_OTG_PARAM_CHECK_VALID(en_multiple_tx_fifo, "en_multiple_tx_fifo",
8838 +                                               ((dwc_otg_module_params.en_multiple_tx_fifo == 1) && (core_if->hwcfg4.b.ded_fifo_en == 0)) ? 0 : 1,
8839 +                                               0);
8840 +
8841 +       for (i = 0; i < 15; i++) {
8842 +               int changed = 1;
8843 +               int error = 0;
8844 +
8845 +               if (dwc_otg_module_params.dev_tx_fifo_size[i] == -1) {
8846 +                       changed = 0;
8847 +                       dwc_otg_module_params.dev_tx_fifo_size[i] = dwc_param_dev_tx_fifo_size_default;
8848 +               }
8849 +               if (!(dwc_otg_module_params.dev_tx_fifo_size[i] <= (dwc_read_reg32(&core_if->core_global_regs->dptxfsiz_dieptxf[i])))) {
8850 +                       if (changed) {
8851 +                               DWC_ERROR("%d' invalid for parameter `dev_perio_fifo_size_%d'. Check HW configuration.\n", dwc_otg_module_params.dev_tx_fifo_size[i], i);
8852 +                               error = 1;
8853 +                       }
8854 +                       dwc_otg_module_params.dev_tx_fifo_size[i] = dwc_read_reg32(&core_if->core_global_regs->dptxfsiz_dieptxf[i]);
8855 +               }
8856 +               retval += error;
8857 +       }
8858 +
8859 +       retval += DWC_OTG_PARAM_CHECK_VALID(thr_ctl, "thr_ctl",
8860 +                               ((dwc_otg_module_params.thr_ctl != 0) && ((dwc_otg_module_params.dma_enable == 0) || (core_if->hwcfg4.b.ded_fifo_en == 0))) ? 0 : 1,
8861 +                               0);
8862 +
8863 +       DWC_OTG_PARAM_SET_DEFAULT(tx_thr_length);
8864 +       DWC_OTG_PARAM_SET_DEFAULT(rx_thr_length);
8865 +
8866 +       retval += DWC_OTG_PARAM_CHECK_VALID(pti_enable, "pti_enable",
8867 +               ((dwc_otg_module_params.pti_enable == 0) || ((dwc_otg_module_params.pti_enable == 1) && (core_if->snpsid >= 0x4F54272A))) ? 1 : 0,
8868 +                       0);
8869 +
8870 +       retval += DWC_OTG_PARAM_CHECK_VALID(mpi_enable, "mpi_enable",
8871 +                       ((dwc_otg_module_params.mpi_enable == 0) || ((dwc_otg_module_params.mpi_enable == 1) && (core_if->hwcfg2.b.multi_proc_int == 1))) ? 1 : 0,
8872 +                       0);
8873 +       return retval;
8874 +}
8875 +
8876 +/**
8877 + * This function is the top level interrupt handler for the Common
8878 + * (Device and host modes) interrupts.
8879 + */
8880 +static irqreturn_t dwc_otg_common_irq(int irq, void *dev
8881 +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,19)
8882 +                                     , struct pt_regs *r
8883 +#endif
8884 +                                    )
8885 +{
8886 +       dwc_otg_device_t *otg_dev = dev;
8887 +       int32_t retval = IRQ_NONE;
8888 +
8889 +       retval = dwc_otg_handle_common_intr(otg_dev->core_if);
8890 +       return IRQ_RETVAL(retval);
8891 +}
8892 +
8893 +/**
8894 + * This function is called when a platform_device is unregistered with the
8895 + * dwc_otg_driver. This happens, for example, when the rmmod command is
8896 + * executed. The device may or may not be electrically present. If it is
8897 + * present, the driver stops device processing. Any resources used on behalf
8898 + * of this device are freed.
8899 + *
8900 + * @param[in] pdev
8901 + */
8902 +static int dwc_otg_driver_remove(struct platform_device *pdev)
8903 +{
8904 +       dwc_otg_device_t *otg_dev = platform_get_drvdata(pdev);
8905 +       DWC_DEBUGPL(DBG_ANY, "%s(%p)\n", __func__, pdev);
8906 +
8907 +       if (!otg_dev) {
8908 +               /* Memory allocation for the dwc_otg_device failed. */
8909 +               DWC_DEBUGPL(DBG_ANY, "%s: otg_dev NULL!\n", __func__);
8910 +               return 0;
8911 +       }
8912 +
8913 +       /*
8914 +        * Free the IRQ
8915 +        */
8916 +       if (otg_dev->common_irq_installed) {
8917 +               free_irq(otg_dev->irq, otg_dev);
8918 +       }
8919 +
8920 +#ifndef DWC_DEVICE_ONLY
8921 +       if (otg_dev->hcd) {
8922 +               dwc_otg_hcd_remove(&pdev->dev);
8923 +       } else {
8924 +               DWC_DEBUGPL(DBG_ANY, "%s: otg_dev->hcd NULL!\n", __func__);
8925 +               return 0;
8926 +       }
8927 +#endif
8928 +
8929 +#ifndef DWC_HOST_ONLY
8930 +       if (otg_dev->pcd) {
8931 +               dwc_otg_pcd_remove(&pdev->dev);
8932 +       }
8933 +#endif
8934 +       if (otg_dev->core_if) {
8935 +               dwc_otg_cil_remove(otg_dev->core_if);
8936 +       }
8937 +
8938 +       /*
8939 +        * Remove the device attributes
8940 +        */
8941 +       dwc_otg_attr_remove(otg_dev->parent);
8942 +
8943 +       /* Disable USB port */
8944 +       dwc_write_reg32((uint32_t *)((uint8_t *)otg_dev->base + 0xe00), 0xf);
8945 +
8946 +       /*
8947 +        * Return the memory.
8948 +        */
8949 +       if (otg_dev->base) {
8950 +               iounmap(otg_dev->base);
8951 +       }
8952 +
8953 +       if (otg_dev->phys_addr != 0) {
8954 +               release_mem_region(otg_dev->phys_addr, otg_dev->base_len);
8955 +       }
8956 +
8957 +       kfree(otg_dev);
8958 +
8959 +       /*
8960 +        * Clear the drvdata pointer.
8961 +        */
8962 +       platform_set_drvdata(pdev, NULL);
8963 +
8964 +       return 0;
8965 +}
8966 +
8967 +/**
8968 + * This function is called when an platform_device is bound to a
8969 + * dwc_otg_driver. It creates the driver components required to
8970 + * control the device (CIL, HCD, and PCD) and it initializes the
8971 + * device. The driver components are stored in a dwc_otg_device
8972 + * structure. A reference to the dwc_otg_device is saved in the
8973 + * platform_device. This allows the driver to access the dwc_otg_device
8974 + * structure on subsequent calls to driver methods for this device.
8975 + *
8976 + * @param[in] pdev  platform_device definition
8977 + */
8978 +static int dwc_otg_driver_probe(struct platform_device *pdev)
8979 +{
8980 +       int retval = 0;
8981 +       uint32_t snpsid;
8982 +       dwc_otg_device_t *otg_dev;
8983 +       struct resource *res;
8984 +
8985 +       dev_dbg(&pdev->dev, "dwc_otg_driver_probe(%p)\n", pdev);
8986 +
8987 +       otg_dev= kzalloc(sizeof(dwc_otg_device_t), GFP_KERNEL);
8988 +       if (!otg_dev) {
8989 +               dev_err(&pdev->dev, "kmalloc of dwc_otg_device failed\n");
8990 +               retval = -ENOMEM;
8991 +               goto fail;
8992 +       }
8993 +
8994 +       otg_dev->reg_offset = 0xFFFFFFFF;
8995 +
8996 +       /*
8997 +        * Retrieve the memory and IRQ resources.
8998 +        */
8999 +       otg_dev->irq = platform_get_irq(pdev, 0);
9000 +       if (otg_dev->irq <= 0) {
9001 +               dev_err(&pdev->dev, "no device irq\n");
9002 +               retval = -EINVAL;
9003 +               goto fail;
9004 +       }
9005 +
9006 +       res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
9007 +       if (res == NULL) {
9008 +               dev_err(&pdev->dev, "no CSR address\n");
9009 +               retval = -EINVAL;
9010 +               goto fail;
9011 +       }
9012 +
9013 +       otg_dev->parent = &pdev->dev;
9014 +       otg_dev->phys_addr = res->start;
9015 +       otg_dev->base_len = res->end - res->start + 1;
9016 +       if (request_mem_region(otg_dev->phys_addr,
9017 +                              otg_dev->base_len,
9018 +                              dwc_driver_name) == NULL) {
9019 +               dev_err(&pdev->dev, "request_mem_region failed\n");
9020 +               retval = -EBUSY;
9021 +               goto fail;
9022 +       }
9023 +
9024 +       /*
9025 +        * Map the DWC_otg Core memory into virtual address space.
9026 +        */
9027 +       otg_dev->base = ioremap(otg_dev->phys_addr, otg_dev->base_len);
9028 +       if (!otg_dev->base) {
9029 +               dev_err(&pdev->dev, "ioremap() failed\n");
9030 +               retval = -ENOMEM;
9031 +               goto fail;
9032 +       }
9033 +       dev_dbg(&pdev->dev, "mapped base=0x%08x\n", (unsigned) otg_dev->base);
9034 +
9035 +       /* Enable USB Port */
9036 +       dwc_write_reg32((uint32_t *)((uint8_t *)otg_dev->base + 0xe00), 0);
9037 +
9038 +       /*
9039 +        * Attempt to ensure this device is really a DWC_otg Controller.
9040 +        * Read and verify the SNPSID register contents. The value should be
9041 +        * 0x45F42XXX, which corresponds to "OT2", as in "OTG version 2.XX".
9042 +        */
9043 +       snpsid = dwc_read_reg32((uint32_t *)((uint8_t *)otg_dev->base + 0x40));
9044 +
9045 +       if ((snpsid & 0xFFFFF000) != OTG_CORE_REV_2_00) {
9046 +               dev_err(&pdev->dev, "Bad value for SNPSID: 0x%08x\n", snpsid);
9047 +               retval = -EINVAL;
9048 +               goto fail;
9049 +       }
9050 +
9051 +       DWC_PRINT("Core Release: %x.%x%x%x\n",
9052 +                       (snpsid >> 12 & 0xF),
9053 +                       (snpsid >> 8 & 0xF),
9054 +                       (snpsid >> 4 & 0xF),
9055 +                       (snpsid & 0xF));
9056 +
9057 +       /*
9058 +        * Initialize driver data to point to the global DWC_otg
9059 +        * Device structure.
9060 +        */
9061 +       platform_set_drvdata(pdev, otg_dev);
9062 +       dev_dbg(&pdev->dev, "dwc_otg_device=0x%p\n", otg_dev);
9063 +
9064 +
9065 +       otg_dev->core_if = dwc_otg_cil_init(otg_dev->base,
9066 +                                                  &dwc_otg_module_params);
9067 +
9068 +       otg_dev->core_if->snpsid = snpsid;
9069 +
9070 +       if (!otg_dev->core_if) {
9071 +               dev_err(&pdev->dev, "CIL initialization failed!\n");
9072 +               retval = -ENOMEM;
9073 +               goto fail;
9074 +       }
9075 +
9076 +       /*
9077 +        * Validate parameter values.
9078 +        */
9079 +       if (check_parameters(otg_dev->core_if)) {
9080 +               retval = -EINVAL;
9081 +               goto fail;
9082 +       }
9083 +
9084 +       /*
9085 +        * Create Device Attributes in sysfs
9086 +        */
9087 +       //dwc_otg_attr_create(&pdev->dev);
9088 +
9089 +       /*
9090 +        * Disable the global interrupt until all the interrupt
9091 +        * handlers are installed.
9092 +        */
9093 +       dwc_otg_disable_global_interrupts(otg_dev->core_if);
9094 +
9095 +       /*
9096 +        * Install the interrupt handler for the common interrupts before
9097 +        * enabling common interrupts in core_init below.
9098 +        */
9099 +       DWC_DEBUGPL(DBG_CIL, "registering (common) handler for irq%d\n",
9100 +                   otg_dev->irq);
9101 +       retval = request_irq(otg_dev->irq, dwc_otg_common_irq,
9102 +                            IRQF_SHARED, "dwc_otg", otg_dev);
9103 +       if (retval) {
9104 +               DWC_ERROR("request of irq%d failed\n", otg_dev->irq);
9105 +               retval = -EBUSY;
9106 +               goto fail;
9107 +       } else {
9108 +               otg_dev->common_irq_installed = 1;
9109 +       }
9110 +
9111 +       /*
9112 +        * Initialize the DWC_otg core.
9113 +        */
9114 +       dwc_otg_core_init(otg_dev->core_if);
9115 +
9116 +#ifndef DWC_HOST_ONLY
9117 +       /*
9118 +        * Initialize the PCD
9119 +        */
9120 +       retval = dwc_otg_pcd_init(&pdev->dev);
9121 +       if (retval != 0) {
9122 +               DWC_ERROR("dwc_otg_pcd_init failed\n");
9123 +               otg_dev->pcd = NULL;
9124 +               goto fail;
9125 +       }
9126 +#endif
9127 +#ifndef DWC_DEVICE_ONLY
9128 +       /*
9129 +        * Initialize the HCD
9130 +        */
9131 +       retval = dwc_otg_hcd_init(&pdev->dev);
9132 +       if (retval != 0) {
9133 +               DWC_ERROR("dwc_otg_hcd_init failed\n");
9134 +               otg_dev->hcd = NULL;
9135 +               goto fail;
9136 +       }
9137 +#endif
9138 +
9139 +       /*
9140 +        * Enable the global interrupt after all the interrupt
9141 +        * handlers are installed.
9142 +        */
9143 +       dwc_otg_enable_global_interrupts(otg_dev->core_if);
9144 +
9145 +       return 0;
9146 +
9147 + fail:
9148 +       dwc_otg_driver_remove(pdev);
9149 +       return retval;
9150 +}
9151 +
9152 +/**
9153 + * This structure defines the methods to be called by a bus driver
9154 + * during the lifecycle of a device on that bus. Both drivers and
9155 + * devices are registered with a bus driver. The bus driver matches
9156 + * devices to drivers based on information in the device and driver
9157 + * structures.
9158 + *
9159 + * The probe function is called when the bus driver matches a device
9160 + * to this driver. The remove function is called when a device is
9161 + * unregistered with the bus driver.
9162 + */
9163 +
9164 +static const struct of_device_id ralink_otg_match[] = {
9165 +       { .compatible = "ralink,rt3050-otg" },
9166 +       {},
9167 +};
9168 +MODULE_DEVICE_TABLE(of, ralink_otg_match);
9169 +
9170 +static struct platform_driver dwc_otg_driver = {
9171 +       .driver = {
9172 +               .name   = (char *)dwc_driver_name,
9173 +               .of_match_table = ralink_otg_match,
9174 +       },
9175 +       .probe          = dwc_otg_driver_probe,
9176 +       .remove         = dwc_otg_driver_remove,
9177 +};
9178 +
9179 +/**
9180 + * This function is called when the dwc_otg_driver is installed with the
9181 + * insmod command. It registers the dwc_otg_driver structure with the
9182 + * appropriate bus driver. This will cause the dwc_otg_driver_probe function
9183 + * to be called. In addition, the bus driver will automatically expose
9184 + * attributes defined for the device and driver in the special sysfs file
9185 + * system.
9186 + *
9187 + * @return
9188 + */
9189 +static int __init dwc_otg_driver_init(void)
9190 +{
9191 +       int retval = 0;
9192 +       int error;
9193 +
9194 +       printk(KERN_INFO "%s: version %s\n", dwc_driver_name, DWC_DRIVER_VERSION);
9195 +
9196 +       retval = platform_driver_register(&dwc_otg_driver);
9197 +       if (retval) {
9198 +               printk(KERN_ERR "%s retval=%d\n", __func__, retval);
9199 +               return retval;
9200 +       }
9201 +
9202 +       error = driver_create_file(&dwc_otg_driver.driver, &driver_attr_version);
9203 +       error = driver_create_file(&dwc_otg_driver.driver, &driver_attr_debuglevel);
9204 +
9205 +       return retval;
9206 +}
9207 +module_init(dwc_otg_driver_init);
9208 +
9209 +/**
9210 + * This function is called when the driver is removed from the kernel
9211 + * with the rmmod command. The driver unregisters itself with its bus
9212 + * driver.
9213 + *
9214 + */
9215 +static void __exit dwc_otg_driver_cleanup(void)
9216 +{
9217 +       printk(KERN_DEBUG "dwc_otg_driver_cleanup()\n");
9218 +
9219 +       driver_remove_file(&dwc_otg_driver.driver, &driver_attr_debuglevel);
9220 +       driver_remove_file(&dwc_otg_driver.driver, &driver_attr_version);
9221 +
9222 +       platform_driver_unregister(&dwc_otg_driver);
9223 +
9224 +       printk(KERN_INFO "%s module removed\n", dwc_driver_name);
9225 +}
9226 +module_exit(dwc_otg_driver_cleanup);
9227 +
9228 +MODULE_DESCRIPTION(DWC_DRIVER_DESC);
9229 +MODULE_AUTHOR("Synopsys Inc.");
9230 +MODULE_LICENSE("GPL");
9231 +
9232 +module_param_named(otg_cap, dwc_otg_module_params.otg_cap, int, 0444);
9233 +MODULE_PARM_DESC(otg_cap, "OTG Capabilities 0=HNP&SRP 1=SRP Only 2=None");
9234 +module_param_named(opt, dwc_otg_module_params.opt, int, 0444);
9235 +MODULE_PARM_DESC(opt, "OPT Mode");
9236 +module_param_named(dma_enable, dwc_otg_module_params.dma_enable, int, 0444);
9237 +MODULE_PARM_DESC(dma_enable, "DMA Mode 0=Slave 1=DMA enabled");
9238 +
9239 +module_param_named(dma_desc_enable, dwc_otg_module_params.dma_desc_enable, int, 0444);
9240 +MODULE_PARM_DESC(dma_desc_enable, "DMA Desc Mode 0=Address DMA 1=DMA Descriptor enabled");
9241 +
9242 +module_param_named(dma_burst_size, dwc_otg_module_params.dma_burst_size, int, 0444);
9243 +MODULE_PARM_DESC(dma_burst_size, "DMA Burst Size 1, 4, 8, 16, 32, 64, 128, 256");
9244 +module_param_named(speed, dwc_otg_module_params.speed, int, 0444);
9245 +MODULE_PARM_DESC(speed, "Speed 0=High Speed 1=Full Speed");
9246 +module_param_named(host_support_fs_ls_low_power, dwc_otg_module_params.host_support_fs_ls_low_power, int, 0444);
9247 +MODULE_PARM_DESC(host_support_fs_ls_low_power, "Support Low Power w/FS or LS 0=Support 1=Don't Support");
9248 +module_param_named(host_ls_low_power_phy_clk, dwc_otg_module_params.host_ls_low_power_phy_clk, int, 0444);
9249 +MODULE_PARM_DESC(host_ls_low_power_phy_clk, "Low Speed Low Power Clock 0=48Mhz 1=6Mhz");
9250 +module_param_named(enable_dynamic_fifo, dwc_otg_module_params.enable_dynamic_fifo, int, 0444);
9251 +MODULE_PARM_DESC(enable_dynamic_fifo, "0=cC Setting 1=Allow Dynamic Sizing");
9252 +module_param_named(data_fifo_size, dwc_otg_module_params.data_fifo_size, int, 0444);
9253 +MODULE_PARM_DESC(data_fifo_size, "Total number of words in the data FIFO memory 32-32768");
9254 +module_param_named(dev_rx_fifo_size, dwc_otg_module_params.dev_rx_fifo_size, int, 0444);
9255 +MODULE_PARM_DESC(dev_rx_fifo_size, "Number of words in the Rx FIFO 16-32768");
9256 +module_param_named(dev_nperio_tx_fifo_size, dwc_otg_module_params.dev_nperio_tx_fifo_size, int, 0444);
9257 +MODULE_PARM_DESC(dev_nperio_tx_fifo_size, "Number of words in the non-periodic Tx FIFO 16-32768");
9258 +module_param_named(dev_perio_tx_fifo_size_1, dwc_otg_module_params.dev_perio_tx_fifo_size[0], int, 0444);
9259 +MODULE_PARM_DESC(dev_perio_tx_fifo_size_1, "Number of words in the periodic Tx FIFO 4-768");
9260 +module_param_named(dev_perio_tx_fifo_size_2, dwc_otg_module_params.dev_perio_tx_fifo_size[1], int, 0444);
9261 +MODULE_PARM_DESC(dev_perio_tx_fifo_size_2, "Number of words in the periodic Tx FIFO 4-768");
9262 +module_param_named(dev_perio_tx_fifo_size_3, dwc_otg_module_params.dev_perio_tx_fifo_size[2], int, 0444);
9263 +MODULE_PARM_DESC(dev_perio_tx_fifo_size_3, "Number of words in the periodic Tx FIFO 4-768");
9264 +module_param_named(dev_perio_tx_fifo_size_4, dwc_otg_module_params.dev_perio_tx_fifo_size[3], int, 0444);
9265 +MODULE_PARM_DESC(dev_perio_tx_fifo_size_4, "Number of words in the periodic Tx FIFO 4-768");
9266 +module_param_named(dev_perio_tx_fifo_size_5, dwc_otg_module_params.dev_perio_tx_fifo_size[4], int, 0444);
9267 +MODULE_PARM_DESC(dev_perio_tx_fifo_size_5, "Number of words in the periodic Tx FIFO 4-768");
9268 +module_param_named(dev_perio_tx_fifo_size_6, dwc_otg_module_params.dev_perio_tx_fifo_size[5], int, 0444);
9269 +MODULE_PARM_DESC(dev_perio_tx_fifo_size_6, "Number of words in the periodic Tx FIFO 4-768");
9270 +module_param_named(dev_perio_tx_fifo_size_7, dwc_otg_module_params.dev_perio_tx_fifo_size[6], int, 0444);
9271 +MODULE_PARM_DESC(dev_perio_tx_fifo_size_7, "Number of words in the periodic Tx FIFO 4-768");
9272 +module_param_named(dev_perio_tx_fifo_size_8, dwc_otg_module_params.dev_perio_tx_fifo_size[7], int, 0444);
9273 +MODULE_PARM_DESC(dev_perio_tx_fifo_size_8, "Number of words in the periodic Tx FIFO 4-768");
9274 +module_param_named(dev_perio_tx_fifo_size_9, dwc_otg_module_params.dev_perio_tx_fifo_size[8], int, 0444);
9275 +MODULE_PARM_DESC(dev_perio_tx_fifo_size_9, "Number of words in the periodic Tx FIFO 4-768");
9276 +module_param_named(dev_perio_tx_fifo_size_10, dwc_otg_module_params.dev_perio_tx_fifo_size[9], int, 0444);
9277 +MODULE_PARM_DESC(dev_perio_tx_fifo_size_10, "Number of words in the periodic Tx FIFO 4-768");
9278 +module_param_named(dev_perio_tx_fifo_size_11, dwc_otg_module_params.dev_perio_tx_fifo_size[10], int, 0444);
9279 +MODULE_PARM_DESC(dev_perio_tx_fifo_size_11, "Number of words in the periodic Tx FIFO 4-768");
9280 +module_param_named(dev_perio_tx_fifo_size_12, dwc_otg_module_params.dev_perio_tx_fifo_size[11], int, 0444);
9281 +MODULE_PARM_DESC(dev_perio_tx_fifo_size_12, "Number of words in the periodic Tx FIFO 4-768");
9282 +module_param_named(dev_perio_tx_fifo_size_13, dwc_otg_module_params.dev_perio_tx_fifo_size[12], int, 0444);
9283 +MODULE_PARM_DESC(dev_perio_tx_fifo_size_13, "Number of words in the periodic Tx FIFO 4-768");
9284 +module_param_named(dev_perio_tx_fifo_size_14, dwc_otg_module_params.dev_perio_tx_fifo_size[13], int, 0444);
9285 +MODULE_PARM_DESC(dev_perio_tx_fifo_size_14, "Number of words in the periodic Tx FIFO 4-768");
9286 +module_param_named(dev_perio_tx_fifo_size_15, dwc_otg_module_params.dev_perio_tx_fifo_size[14], int, 0444);
9287 +MODULE_PARM_DESC(dev_perio_tx_fifo_size_15, "Number of words in the periodic Tx FIFO 4-768");
9288 +module_param_named(host_rx_fifo_size, dwc_otg_module_params.host_rx_fifo_size, int, 0444);
9289 +MODULE_PARM_DESC(host_rx_fifo_size, "Number of words in the Rx FIFO 16-32768");
9290 +module_param_named(host_nperio_tx_fifo_size, dwc_otg_module_params.host_nperio_tx_fifo_size, int, 0444);
9291 +MODULE_PARM_DESC(host_nperio_tx_fifo_size, "Number of words in the non-periodic Tx FIFO 16-32768");
9292 +module_param_named(host_perio_tx_fifo_size, dwc_otg_module_params.host_perio_tx_fifo_size, int, 0444);
9293 +MODULE_PARM_DESC(host_perio_tx_fifo_size, "Number of words in the host periodic Tx FIFO 16-32768");
9294 +module_param_named(max_transfer_size, dwc_otg_module_params.max_transfer_size, int, 0444);
9295 +/** @todo Set the max to 512K, modify checks */
9296 +MODULE_PARM_DESC(max_transfer_size, "The maximum transfer size supported in bytes 2047-65535");
9297 +module_param_named(max_packet_count, dwc_otg_module_params.max_packet_count, int, 0444);
9298 +MODULE_PARM_DESC(max_packet_count, "The maximum number of packets in a transfer 15-511");
9299 +module_param_named(host_channels, dwc_otg_module_params.host_channels, int, 0444);
9300 +MODULE_PARM_DESC(host_channels, "The number of host channel registers to use 1-16");
9301 +module_param_named(dev_endpoints, dwc_otg_module_params.dev_endpoints, int, 0444);
9302 +MODULE_PARM_DESC(dev_endpoints, "The number of endpoints in addition to EP0 available for device mode 1-15");
9303 +module_param_named(phy_type, dwc_otg_module_params.phy_type, int, 0444);
9304 +MODULE_PARM_DESC(phy_type, "0=Reserved 1=UTMI+ 2=ULPI");
9305 +module_param_named(phy_utmi_width, dwc_otg_module_params.phy_utmi_width, int, 0444);
9306 +MODULE_PARM_DESC(phy_utmi_width, "Specifies the UTMI+ Data Width 8 or 16 bits");
9307 +module_param_named(phy_ulpi_ddr, dwc_otg_module_params.phy_ulpi_ddr, int, 0444);
9308 +MODULE_PARM_DESC(phy_ulpi_ddr, "ULPI at double or single data rate 0=Single 1=Double");
9309 +module_param_named(phy_ulpi_ext_vbus, dwc_otg_module_params.phy_ulpi_ext_vbus, int, 0444);
9310 +MODULE_PARM_DESC(phy_ulpi_ext_vbus, "ULPI PHY using internal or external vbus 0=Internal");
9311 +module_param_named(i2c_enable, dwc_otg_module_params.i2c_enable, int, 0444);
9312 +MODULE_PARM_DESC(i2c_enable, "FS PHY Interface");
9313 +module_param_named(ulpi_fs_ls, dwc_otg_module_params.ulpi_fs_ls, int, 0444);
9314 +MODULE_PARM_DESC(ulpi_fs_ls, "ULPI PHY FS/LS mode only");
9315 +module_param_named(ts_dline, dwc_otg_module_params.ts_dline, int, 0444);
9316 +MODULE_PARM_DESC(ts_dline, "Term select Dline pulsing for all PHYs");
9317 +module_param_named(debug, g_dbg_lvl, int, 0444);
9318 +MODULE_PARM_DESC(debug, "");
9319 +
9320 +module_param_named(en_multiple_tx_fifo, dwc_otg_module_params.en_multiple_tx_fifo, int, 0444);
9321 +MODULE_PARM_DESC(en_multiple_tx_fifo, "Dedicated Non Periodic Tx FIFOs 0=disabled 1=enabled");
9322 +module_param_named(dev_tx_fifo_size_1, dwc_otg_module_params.dev_tx_fifo_size[0], int, 0444);
9323 +MODULE_PARM_DESC(dev_tx_fifo_size_1, "Number of words in the Tx FIFO 4-768");
9324 +module_param_named(dev_tx_fifo_size_2, dwc_otg_module_params.dev_tx_fifo_size[1], int, 0444);
9325 +MODULE_PARM_DESC(dev_tx_fifo_size_2, "Number of words in the Tx FIFO 4-768");
9326 +module_param_named(dev_tx_fifo_size_3, dwc_otg_module_params.dev_tx_fifo_size[2], int, 0444);
9327 +MODULE_PARM_DESC(dev_tx_fifo_size_3, "Number of words in the Tx FIFO 4-768");
9328 +module_param_named(dev_tx_fifo_size_4, dwc_otg_module_params.dev_tx_fifo_size[3], int, 0444);
9329 +MODULE_PARM_DESC(dev_tx_fifo_size_4, "Number of words in the Tx FIFO 4-768");
9330 +module_param_named(dev_tx_fifo_size_5, dwc_otg_module_params.dev_tx_fifo_size[4], int, 0444);
9331 +MODULE_PARM_DESC(dev_tx_fifo_size_5, "Number of words in the Tx FIFO 4-768");
9332 +module_param_named(dev_tx_fifo_size_6, dwc_otg_module_params.dev_tx_fifo_size[5], int, 0444);
9333 +MODULE_PARM_DESC(dev_tx_fifo_size_6, "Number of words in the Tx FIFO 4-768");
9334 +module_param_named(dev_tx_fifo_size_7, dwc_otg_module_params.dev_tx_fifo_size[6], int, 0444);
9335 +MODULE_PARM_DESC(dev_tx_fifo_size_7, "Number of words in the Tx FIFO 4-768");
9336 +module_param_named(dev_tx_fifo_size_8, dwc_otg_module_params.dev_tx_fifo_size[7], int, 0444);
9337 +MODULE_PARM_DESC(dev_tx_fifo_size_8, "Number of words in the Tx FIFO 4-768");
9338 +module_param_named(dev_tx_fifo_size_9, dwc_otg_module_params.dev_tx_fifo_size[8], int, 0444);
9339 +MODULE_PARM_DESC(dev_tx_fifo_size_9, "Number of words in the Tx FIFO 4-768");
9340 +module_param_named(dev_tx_fifo_size_10, dwc_otg_module_params.dev_tx_fifo_size[9], int, 0444);
9341 +MODULE_PARM_DESC(dev_tx_fifo_size_10, "Number of words in the Tx FIFO 4-768");
9342 +module_param_named(dev_tx_fifo_size_11, dwc_otg_module_params.dev_tx_fifo_size[10], int, 0444);
9343 +MODULE_PARM_DESC(dev_tx_fifo_size_11, "Number of words in the Tx FIFO 4-768");
9344 +module_param_named(dev_tx_fifo_size_12, dwc_otg_module_params.dev_tx_fifo_size[11], int, 0444);
9345 +MODULE_PARM_DESC(dev_tx_fifo_size_12, "Number of words in the Tx FIFO 4-768");
9346 +module_param_named(dev_tx_fifo_size_13, dwc_otg_module_params.dev_tx_fifo_size[12], int, 0444);
9347 +MODULE_PARM_DESC(dev_tx_fifo_size_13, "Number of words in the Tx FIFO 4-768");
9348 +module_param_named(dev_tx_fifo_size_14, dwc_otg_module_params.dev_tx_fifo_size[13], int, 0444);
9349 +MODULE_PARM_DESC(dev_tx_fifo_size_14, "Number of words in the Tx FIFO 4-768");
9350 +module_param_named(dev_tx_fifo_size_15, dwc_otg_module_params.dev_tx_fifo_size[14], int, 0444);
9351 +MODULE_PARM_DESC(dev_tx_fifo_size_15, "Number of words in the Tx FIFO 4-768");
9352 +
9353 +module_param_named(thr_ctl, dwc_otg_module_params.thr_ctl, int, 0444);
9354 +MODULE_PARM_DESC(thr_ctl, "Thresholding enable flag bit 0 - non ISO Tx thr., 1 - ISO Tx thr., 2 - Rx thr.- bit 0=disabled 1=enabled");
9355 +module_param_named(tx_thr_length, dwc_otg_module_params.tx_thr_length, int, 0444);
9356 +MODULE_PARM_DESC(tx_thr_length, "Tx Threshold length in 32 bit DWORDs");
9357 +module_param_named(rx_thr_length, dwc_otg_module_params.rx_thr_length, int, 0444);
9358 +MODULE_PARM_DESC(rx_thr_length, "Rx Threshold length in 32 bit DWORDs");
9359 +
9360 +module_param_named(pti_enable, dwc_otg_module_params.pti_enable, int, 0444);
9361 +MODULE_PARM_DESC(pti_enable, "Per Transfer Interrupt mode 0=disabled 1=enabled");
9362 +
9363 +module_param_named(mpi_enable, dwc_otg_module_params.mpi_enable, int, 0444);
9364 +MODULE_PARM_DESC(mpi_enable, "Multiprocessor Interrupt mode 0=disabled 1=enabled");
9365 +
9366 +/** @page "Module Parameters"
9367 + *
9368 + * The following parameters may be specified when starting the module.
9369 + * These parameters define how the DWC_otg controller should be
9370 + * configured. Parameter values are passed to the CIL initialization
9371 + * function dwc_otg_cil_init
9372 + *
9373 + * Example: <code>modprobe dwc_otg speed=1 otg_cap=1</code>
9374 + *
9375 +
9376 + <table>
9377 + <tr><td>Parameter Name</td><td>Meaning</td></tr>
9378 +
9379 + <tr>
9380 + <td>otg_cap</td>
9381 + <td>Specifies the OTG capabilities. The driver will automatically detect the
9382 + value for this parameter if none is specified.
9383 + - 0: HNP and SRP capable (default, if available)
9384 + - 1: SRP Only capable
9385 + - 2: No HNP/SRP capable
9386 + </td></tr>
9387 +
9388 + <tr>
9389 + <td>dma_enable</td>
9390 + <td>Specifies whether to use slave or DMA mode for accessing the data FIFOs.
9391 + The driver will automatically detect the value for this parameter if none is
9392 + specified.
9393 + - 0: Slave
9394 + - 1: DMA (default, if available)
9395 + </td></tr>
9396 +
9397 + <tr>
9398 + <td>dma_burst_size</td>
9399 + <td>The DMA Burst size (applicable only for External DMA Mode).
9400 + - Values: 1, 4, 8 16, 32, 64, 128, 256 (default 32)
9401 + </td></tr>
9402 +
9403 + <tr>
9404 + <td>speed</td>
9405 + <td>Specifies the maximum speed of operation in host and device mode. The
9406 + actual speed depends on the speed of the attached device and the value of
9407 + phy_type.
9408 + - 0: High Speed (default)
9409 + - 1: Full Speed
9410 + </td></tr>
9411 +
9412 + <tr>
9413 + <td>host_support_fs_ls_low_power</td>
9414 + <td>Specifies whether low power mode is supported when attached to a Full
9415 + Speed or Low Speed device in host mode.
9416 + - 0: Don't support low power mode (default)
9417 + - 1: Support low power mode
9418 + </td></tr>
9419 +
9420 + <tr>
9421 + <td>host_ls_low_power_phy_clk</td>
9422 + <td>Specifies the PHY clock rate in low power mode when connected to a Low
9423 + Speed device in host mode. This parameter is applicable only if
9424 + HOST_SUPPORT_FS_LS_LOW_POWER is enabled.
9425 + - 0: 48 MHz (default)
9426 + - 1: 6 MHz
9427 + </td></tr>
9428 +
9429 + <tr>
9430 + <td>enable_dynamic_fifo</td>
9431 + <td> Specifies whether FIFOs may be resized by the driver software.
9432 + - 0: Use cC FIFO size parameters
9433 + - 1: Allow dynamic FIFO sizing (default)
9434 + </td></tr>
9435 +
9436 + <tr>
9437 + <td>data_fifo_size</td>
9438 + <td>Total number of 4-byte words in the data FIFO memory. This memory
9439 + includes the Rx FIFO, non-periodic Tx FIFO, and periodic Tx FIFOs.
9440 + - Values: 32 to 32768 (default 8192)
9441 +
9442 + Note: The total FIFO memory depth in the FPGA configuration is 8192.
9443 + </td></tr>
9444 +
9445 + <tr>
9446 + <td>dev_rx_fifo_size</td>
9447 + <td>Number of 4-byte words in the Rx FIFO in device mode when dynamic
9448 + FIFO sizing is enabled.
9449 + - Values: 16 to 32768 (default 1064)
9450 + </td></tr>
9451 +
9452 + <tr>
9453 + <td>dev_nperio_tx_fifo_size</td>
9454 + <td>Number of 4-byte words in the non-periodic Tx FIFO in device mode when
9455 + dynamic FIFO sizing is enabled.
9456 + - Values: 16 to 32768 (default 1024)
9457 + </td></tr>
9458 +
9459 + <tr>
9460 + <td>dev_perio_tx_fifo_size_n (n = 1 to 15)</td>
9461 + <td>Number of 4-byte words in each of the periodic Tx FIFOs in device mode
9462 + when dynamic FIFO sizing is enabled.
9463 + - Values: 4 to 768 (default 256)
9464 + </td></tr>
9465 +
9466 + <tr>
9467 + <td>host_rx_fifo_size</td>
9468 + <td>Number of 4-byte words in the Rx FIFO in host mode when dynamic FIFO
9469 + sizing is enabled.
9470 + - Values: 16 to 32768 (default 1024)
9471 + </td></tr>
9472 +
9473 + <tr>
9474 + <td>host_nperio_tx_fifo_size</td>
9475 + <td>Number of 4-byte words in the non-periodic Tx FIFO in host mode when
9476 + dynamic FIFO sizing is enabled in the core.
9477 + - Values: 16 to 32768 (default 1024)
9478 + </td></tr>
9479 +
9480 + <tr>
9481 + <td>host_perio_tx_fifo_size</td>
9482 + <td>Number of 4-byte words in the host periodic Tx FIFO when dynamic FIFO
9483 + sizing is enabled.
9484 + - Values: 16 to 32768 (default 1024)
9485 + </td></tr>
9486 +
9487 + <tr>
9488 + <td>max_transfer_size</td>
9489 + <td>The maximum transfer size supported in bytes.
9490 + - Values: 2047 to 65,535 (default 65,535)
9491 + </td></tr>
9492 +
9493 + <tr>
9494 + <td>max_packet_count</td>
9495 + <td>The maximum number of packets in a transfer.
9496 + - Values: 15 to 511 (default 511)
9497 + </td></tr>
9498 +
9499 + <tr>
9500 + <td>host_channels</td>
9501 + <td>The number of host channel registers to use.
9502 + - Values: 1 to 16 (default 12)
9503 +
9504 + Note: The FPGA configuration supports a maximum of 12 host channels.
9505 + </td></tr>
9506 +
9507 + <tr>
9508 + <td>dev_endpoints</td>
9509 + <td>The number of endpoints in addition to EP0 available for device mode
9510 + operations.
9511 + - Values: 1 to 15 (default 6 IN and OUT)
9512 +
9513 + Note: The FPGA configuration supports a maximum of 6 IN and OUT endpoints in
9514 + addition to EP0.
9515 + </td></tr>
9516 +
9517 + <tr>
9518 + <td>phy_type</td>
9519 + <td>Specifies the type of PHY interface to use. By default, the driver will
9520 + automatically detect the phy_type.
9521 + - 0: Full Speed
9522 + - 1: UTMI+ (default, if available)
9523 + - 2: ULPI
9524 + </td></tr>
9525 +
9526 + <tr>
9527 + <td>phy_utmi_width</td>
9528 + <td>Specifies the UTMI+ Data Width. This parameter is applicable for a
9529 + phy_type of UTMI+. Also, this parameter is applicable only if the
9530 + OTG_HSPHY_WIDTH cC parameter was set to "8 and 16 bits", meaning that the
9531 + core has been configured to work at either data path width.
9532 + - Values: 8 or 16 bits (default 16)
9533 + </td></tr>
9534 +
9535 + <tr>
9536 + <td>phy_ulpi_ddr</td>
9537 + <td>Specifies whether the ULPI operates at double or single data rate. This
9538 + parameter is only applicable if phy_type is ULPI.
9539 + - 0: single data rate ULPI interface with 8 bit wide data bus (default)
9540 + - 1: double data rate ULPI interface with 4 bit wide data bus
9541 + </td></tr>
9542 +
9543 + <tr>
9544 + <td>i2c_enable</td>
9545 + <td>Specifies whether to use the I2C interface for full speed PHY. This
9546 + parameter is only applicable if PHY_TYPE is FS.
9547 + - 0: Disabled (default)
9548 + - 1: Enabled
9549 + </td></tr>
9550 +
9551 + <tr>
9552 + <td>otg_en_multiple_tx_fifo</td>
9553 + <td>Specifies whether dedicatedto tx fifos are enabled for non periodic IN EPs.
9554 + The driver will automatically detect the value for this parameter if none is
9555 + specified.
9556 + - 0: Disabled
9557 + - 1: Enabled (default, if available)
9558 + </td></tr>
9559 +
9560 + <tr>
9561 + <td>dev_tx_fifo_size_n (n = 1 to 15)</td>
9562 + <td>Number of 4-byte words in each of the Tx FIFOs in device mode
9563 + when dynamic FIFO sizing is enabled.
9564 + - Values: 4 to 768 (default 256)
9565 + </td></tr>
9566 +
9567 +*/
9568 --- /dev/null
9569 +++ b/drivers/usb/dwc_otg/dwc_otg_driver.h
9570 @@ -0,0 +1,83 @@
9571 +/* ==========================================================================
9572 + * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_driver.h $
9573 + * $Revision: 1.2 $
9574 + * $Date: 2008-11-21 05:39:15 $
9575 + * $Change: 1064918 $
9576 + *
9577 + * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
9578 + * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
9579 + * otherwise expressly agreed to in writing between Synopsys and you.
9580 + *
9581 + * The Software IS NOT an item of Licensed Software or Licensed Product under
9582 + * any End User Software License Agreement or Agreement for Licensed Product
9583 + * with Synopsys or any supplement thereto. You are permitted to use and
9584 + * redistribute this Software in source and binary forms, with or without
9585 + * modification, provided that redistributions of source code must retain this
9586 + * notice. You may not view, use, disclose, copy or distribute this file or
9587 + * any information contained herein except pursuant to this license grant from
9588 + * Synopsys. If you do not agree with this notice, including the disclaimer
9589 + * below, then you are not authorized to use the Software.
9590 + *
9591 + * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
9592 + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
9593 + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
9594 + * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
9595 + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
9596 + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
9597 + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
9598 + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
9599 + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
9600 + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
9601 + * DAMAGE.
9602 + * ========================================================================== */
9603 +
9604 +#ifndef __DWC_OTG_DRIVER_H__
9605 +#define __DWC_OTG_DRIVER_H__
9606 +
9607 +/** @file
9608 + * This file contains the interface to the Linux driver.
9609 + */
9610 +#include "dwc_otg_cil.h"
9611 +
9612 +/* Type declarations */
9613 +struct dwc_otg_pcd;
9614 +struct dwc_otg_hcd;
9615 +
9616 +/**
9617 + * This structure is a wrapper that encapsulates the driver components used to
9618 + * manage a single DWC_otg controller.
9619 + */
9620 +typedef struct dwc_otg_device {
9621 +       /** Base address returned from ioremap() */
9622 +       void *base;
9623 +
9624 +       struct device *parent;
9625 +
9626 +       /** Pointer to the core interface structure. */
9627 +       dwc_otg_core_if_t *core_if;
9628 +
9629 +       /** Register offset for Diagnostic API. */
9630 +       uint32_t reg_offset;
9631 +
9632 +       /** Pointer to the PCD structure. */
9633 +       struct dwc_otg_pcd *pcd;
9634 +
9635 +       /** Pointer to the HCD structure. */
9636 +       struct dwc_otg_hcd *hcd;
9637 +
9638 +       /** Flag to indicate whether the common IRQ handler is installed. */
9639 +       uint8_t common_irq_installed;
9640 +
9641 +       /* Interrupt request number. */
9642 +       unsigned int irq;
9643 +
9644 +       /* Physical address of Control and Status registers, used by
9645 +        * release_mem_region().
9646 +        */
9647 +       resource_size_t phys_addr;
9648 +
9649 +       /* Length of memory region, used by release_mem_region(). */
9650 +       unsigned long base_len;
9651 +} dwc_otg_device_t;
9652 +
9653 +#endif
9654 --- /dev/null
9655 +++ b/drivers/usb/dwc_otg/dwc_otg_hcd.c
9656 @@ -0,0 +1,2852 @@
9657 +/* ==========================================================================
9658 + * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_hcd.c $
9659 + * $Revision: 1.4 $
9660 + * $Date: 2008-11-21 05:39:15 $
9661 + * $Change: 1064940 $
9662 + *
9663 + * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
9664 + * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
9665 + * otherwise expressly agreed to in writing between Synopsys and you.
9666 + *
9667 + * The Software IS NOT an item of Licensed Software or Licensed Product under
9668 + * any End User Software License Agreement or Agreement for Licensed Product
9669 + * with Synopsys or any supplement thereto. You are permitted to use and
9670 + * redistribute this Software in source and binary forms, with or without
9671 + * modification, provided that redistributions of source code must retain this
9672 + * notice. You may not view, use, disclose, copy or distribute this file or
9673 + * any information contained herein except pursuant to this license grant from
9674 + * Synopsys. If you do not agree with this notice, including the disclaimer
9675 + * below, then you are not authorized to use the Software.
9676 + *
9677 + * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
9678 + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
9679 + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
9680 + * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
9681 + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
9682 + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
9683 + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
9684 + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
9685 + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
9686 + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
9687 + * DAMAGE.
9688 + * ========================================================================== */
9689 +#ifndef DWC_DEVICE_ONLY
9690 +
9691 +/**
9692 + * @file
9693 + *
9694 + * This file contains the implementation of the HCD. In Linux, the HCD
9695 + * implements the hc_driver API.
9696 + */
9697 +#include <linux/kernel.h>
9698 +#include <linux/module.h>
9699 +#include <linux/moduleparam.h>
9700 +#include <linux/init.h>
9701 +#include <linux/device.h>
9702 +#include <linux/errno.h>
9703 +#include <linux/list.h>
9704 +#include <linux/interrupt.h>
9705 +#include <linux/string.h>
9706 +#include <linux/dma-mapping.h>
9707 +#include <linux/version.h>
9708 +
9709 +#include "dwc_otg_driver.h"
9710 +#include "dwc_otg_hcd.h"
9711 +#include "dwc_otg_regs.h"
9712 +
9713 +static const char dwc_otg_hcd_name[] = "dwc_otg";
9714 +
9715 +static const struct hc_driver dwc_otg_hc_driver = {
9716 +
9717 +       .description =          dwc_otg_hcd_name,
9718 +       .product_desc =         "DWC OTG Controller",
9719 +       .hcd_priv_size =        sizeof(dwc_otg_hcd_t),
9720 +
9721 +       .irq =                  dwc_otg_hcd_irq,
9722 +
9723 +       .flags =                HCD_MEMORY | HCD_USB2,
9724 +
9725 +       //.reset =
9726 +       .start =                dwc_otg_hcd_start,
9727 +       //.suspend =
9728 +       //.resume =
9729 +       .stop =                 dwc_otg_hcd_stop,
9730 +
9731 +       .urb_enqueue =          dwc_otg_hcd_urb_enqueue,
9732 +       .urb_dequeue =          dwc_otg_hcd_urb_dequeue,
9733 +       .endpoint_disable =     dwc_otg_hcd_endpoint_disable,
9734 +
9735 +       .get_frame_number =     dwc_otg_hcd_get_frame_number,
9736 +
9737 +       .hub_status_data =      dwc_otg_hcd_hub_status_data,
9738 +       .hub_control =          dwc_otg_hcd_hub_control,
9739 +       //.hub_suspend =
9740 +       //.hub_resume =
9741 +};
9742 +
9743 +/**
9744 + * Work queue function for starting the HCD when A-Cable is connected.
9745 + * The dwc_otg_hcd_start() must be called in a process context.
9746 + */
9747 +static void hcd_start_func(
9748 +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,20)
9749 +                          void *_vp
9750 +#else
9751 +                          struct work_struct *_work
9752 +#endif
9753 +                         )
9754 +{
9755 +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,20)
9756 +       struct usb_hcd *usb_hcd = (struct usb_hcd *)_vp;
9757 +#else
9758 +       struct delayed_work *dw = container_of(_work, struct delayed_work, work);
9759 +       struct dwc_otg_hcd *otg_hcd = container_of(dw, struct dwc_otg_hcd, start_work);
9760 +       struct usb_hcd *usb_hcd = container_of((void *)otg_hcd, struct usb_hcd, hcd_priv);
9761 +#endif
9762 +       DWC_DEBUGPL(DBG_HCDV, "%s() %p\n", __func__, usb_hcd);
9763 +       if (usb_hcd) {
9764 +               dwc_otg_hcd_start(usb_hcd);
9765 +       }
9766 +}
9767 +
9768 +/**
9769 + * HCD Callback function for starting the HCD when A-Cable is
9770 + * connected.
9771 + *
9772 + * @param p void pointer to the <code>struct usb_hcd</code>
9773 + */
9774 +static int32_t dwc_otg_hcd_start_cb(void *p)
9775 +{
9776 +       dwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd(p);
9777 +       dwc_otg_core_if_t *core_if = dwc_otg_hcd->core_if;
9778 +       hprt0_data_t hprt0;
9779 +
9780 +       if (core_if->op_state == B_HOST) {
9781 +               /*
9782 +                * Reset the port.  During a HNP mode switch the reset
9783 +                * needs to occur within 1ms and have a duration of at
9784 +                * least 50ms.
9785 +                */
9786 +               hprt0.d32 = dwc_otg_read_hprt0(core_if);
9787 +               hprt0.b.prtrst = 1;
9788 +               dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32);
9789 +               ((struct usb_hcd *)p)->self.is_b_host = 1;
9790 +       } else {
9791 +               ((struct usb_hcd *)p)->self.is_b_host = 0;
9792 +       }
9793 +
9794 +       /* Need to start the HCD in a non-interrupt context. */
9795 +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,20)
9796 +       INIT_WORK(&dwc_otg_hcd->start_work, hcd_start_func, p);
9797 +//     INIT_DELAYED_WORK(&dwc_otg_hcd->start_work, hcd_start_func, p);
9798 +#else
9799 +//     INIT_WORK(&dwc_otg_hcd->start_work, hcd_start_func);
9800 +       INIT_DELAYED_WORK(&dwc_otg_hcd->start_work, hcd_start_func);
9801 +#endif
9802 +//     schedule_work(&dwc_otg_hcd->start_work);
9803 +       queue_delayed_work(core_if->wq_otg, &dwc_otg_hcd->start_work, 50 * HZ / 1000);
9804 +
9805 +       return 1;
9806 +}
9807 +
9808 +/**
9809 + * HCD Callback function for stopping the HCD.
9810 + *
9811 + * @param p void pointer to the <code>struct usb_hcd</code>
9812 + */
9813 +static int32_t dwc_otg_hcd_stop_cb(void *p)
9814 +{
9815 +       struct usb_hcd *usb_hcd = (struct usb_hcd *)p;
9816 +       DWC_DEBUGPL(DBG_HCDV, "%s(%p)\n", __func__, p);
9817 +       dwc_otg_hcd_stop(usb_hcd);
9818 +       return 1;
9819 +}
9820 +
9821 +static void del_xfer_timers(dwc_otg_hcd_t *hcd)
9822 +{
9823 +#ifdef DEBUG
9824 +       int i;
9825 +       int num_channels = hcd->core_if->core_params->host_channels;
9826 +       for (i = 0; i < num_channels; i++) {
9827 +               del_timer(&hcd->core_if->hc_xfer_timer[i]);
9828 +       }
9829 +#endif
9830 +}
9831 +
9832 +static void del_timers(dwc_otg_hcd_t *hcd)
9833 +{
9834 +       del_xfer_timers(hcd);
9835 +       del_timer(&hcd->conn_timer);
9836 +}
9837 +
9838 +/**
9839 + * Processes all the URBs in a single list of QHs. Completes them with
9840 + * -ETIMEDOUT and frees the QTD.
9841 + */
9842 +static void kill_urbs_in_qh_list(dwc_otg_hcd_t *hcd, struct list_head *qh_list)
9843 +{
9844 +       struct list_head        *qh_item;
9845 +       dwc_otg_qh_t            *qh;
9846 +       struct list_head        *qtd_item;
9847 +       dwc_otg_qtd_t           *qtd;
9848 +
9849 +       list_for_each(qh_item, qh_list) {
9850 +               qh = list_entry(qh_item, dwc_otg_qh_t, qh_list_entry);
9851 +               for (qtd_item = qh->qtd_list.next;
9852 +                    qtd_item != &qh->qtd_list;
9853 +                    qtd_item = qh->qtd_list.next) {
9854 +                       qtd = list_entry(qtd_item, dwc_otg_qtd_t, qtd_list_entry);
9855 +                       if (qtd->urb != NULL) {
9856 +                               dwc_otg_hcd_complete_urb(hcd, qtd->urb,
9857 +                                                        -ETIMEDOUT);
9858 +                       }
9859 +                       dwc_otg_hcd_qtd_remove_and_free(hcd, qtd);
9860 +               }
9861 +       }
9862 +}
9863 +
9864 +/**
9865 + * Responds with an error status of ETIMEDOUT to all URBs in the non-periodic
9866 + * and periodic schedules. The QTD associated with each URB is removed from
9867 + * the schedule and freed. This function may be called when a disconnect is
9868 + * detected or when the HCD is being stopped.
9869 + */
9870 +static void kill_all_urbs(dwc_otg_hcd_t *hcd)
9871 +{
9872 +       kill_urbs_in_qh_list(hcd, &hcd->non_periodic_sched_inactive);
9873 +       kill_urbs_in_qh_list(hcd, &hcd->non_periodic_sched_active);
9874 +       kill_urbs_in_qh_list(hcd, &hcd->periodic_sched_inactive);
9875 +       kill_urbs_in_qh_list(hcd, &hcd->periodic_sched_ready);
9876 +       kill_urbs_in_qh_list(hcd, &hcd->periodic_sched_assigned);
9877 +       kill_urbs_in_qh_list(hcd, &hcd->periodic_sched_queued);
9878 +}
9879 +
9880 +/**
9881 + * HCD Callback function for disconnect of the HCD.
9882 + *
9883 + * @param p void pointer to the <code>struct usb_hcd</code>
9884 + */
9885 +static int32_t dwc_otg_hcd_disconnect_cb(void *p)
9886 +{
9887 +       gintsts_data_t  intr;
9888 +       dwc_otg_hcd_t   *dwc_otg_hcd = hcd_to_dwc_otg_hcd(p);
9889 +
9890 +       //DWC_DEBUGPL(DBG_HCDV, "%s(%p)\n", __func__, p);
9891 +
9892 +       /*
9893 +        * Set status flags for the hub driver.
9894 +        */
9895 +       dwc_otg_hcd->flags.b.port_connect_status_change = 1;
9896 +       dwc_otg_hcd->flags.b.port_connect_status = 0;
9897 +
9898 +       /*
9899 +        * Shutdown any transfers in process by clearing the Tx FIFO Empty
9900 +        * interrupt mask and status bits and disabling subsequent host
9901 +        * channel interrupts.
9902 +        */
9903 +       intr.d32 = 0;
9904 +       intr.b.nptxfempty = 1;
9905 +       intr.b.ptxfempty = 1;
9906 +       intr.b.hcintr = 1;
9907 +       dwc_modify_reg32(&dwc_otg_hcd->core_if->core_global_regs->gintmsk, intr.d32, 0);
9908 +       dwc_modify_reg32(&dwc_otg_hcd->core_if->core_global_regs->gintsts, intr.d32, 0);
9909 +
9910 +       del_timers(dwc_otg_hcd);
9911 +
9912 +       /*
9913 +        * Turn off the vbus power only if the core has transitioned to device
9914 +        * mode. If still in host mode, need to keep power on to detect a
9915 +        * reconnection.
9916 +        */
9917 +       if (dwc_otg_is_device_mode(dwc_otg_hcd->core_if)) {
9918 +               if (dwc_otg_hcd->core_if->op_state != A_SUSPEND) {
9919 +                       hprt0_data_t hprt0 = { .d32=0 };
9920 +                       DWC_PRINT("Disconnect: PortPower off\n");
9921 +                       hprt0.b.prtpwr = 0;
9922 +                       dwc_write_reg32(dwc_otg_hcd->core_if->host_if->hprt0, hprt0.d32);
9923 +               }
9924 +
9925 +               dwc_otg_disable_host_interrupts(dwc_otg_hcd->core_if);
9926 +       }
9927 +
9928 +       /* Respond with an error status to all URBs in the schedule. */
9929 +       kill_all_urbs(dwc_otg_hcd);
9930 +
9931 +       if (dwc_otg_is_host_mode(dwc_otg_hcd->core_if)) {
9932 +               /* Clean up any host channels that were in use. */
9933 +               int                     num_channels;
9934 +               int                     i;
9935 +               dwc_hc_t                *channel;
9936 +               dwc_otg_hc_regs_t       *hc_regs;
9937 +               hcchar_data_t           hcchar;
9938 +
9939 +               num_channels = dwc_otg_hcd->core_if->core_params->host_channels;
9940 +
9941 +               if (!dwc_otg_hcd->core_if->dma_enable) {
9942 +                       /* Flush out any channel requests in slave mode. */
9943 +                       for (i = 0; i < num_channels; i++) {
9944 +                               channel = dwc_otg_hcd->hc_ptr_array[i];
9945 +                               if (list_empty(&channel->hc_list_entry)) {
9946 +                                       hc_regs = dwc_otg_hcd->core_if->host_if->hc_regs[i];
9947 +                                       hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
9948 +                                       if (hcchar.b.chen) {
9949 +                                               hcchar.b.chen = 0;
9950 +                                               hcchar.b.chdis = 1;
9951 +                                               hcchar.b.epdir = 0;
9952 +                                               dwc_write_reg32(&hc_regs->hcchar, hcchar.d32);
9953 +                                       }
9954 +                               }
9955 +                       }
9956 +               }
9957 +
9958 +               for (i = 0; i < num_channels; i++) {
9959 +                       channel = dwc_otg_hcd->hc_ptr_array[i];
9960 +                       if (list_empty(&channel->hc_list_entry)) {
9961 +                               hc_regs = dwc_otg_hcd->core_if->host_if->hc_regs[i];
9962 +                               hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
9963 +                               if (hcchar.b.chen) {
9964 +                                       /* Halt the channel. */
9965 +                                       hcchar.b.chdis = 1;
9966 +                                       dwc_write_reg32(&hc_regs->hcchar, hcchar.d32);
9967 +                               }
9968 +
9969 +                               dwc_otg_hc_cleanup(dwc_otg_hcd->core_if, channel);
9970 +                               list_add_tail(&channel->hc_list_entry,
9971 +                                             &dwc_otg_hcd->free_hc_list);
9972 +                       }
9973 +               }
9974 +       }
9975 +
9976 +       /* A disconnect will end the session so the B-Device is no
9977 +        * longer a B-host. */
9978 +       ((struct usb_hcd *)p)->self.is_b_host = 0;
9979 +       return 1;
9980 +}
9981 +
9982 +/**
9983 + * Connection timeout function.  An OTG host is required to display a
9984 + * message if the device does not connect within 10 seconds.
9985 + */
9986 +void dwc_otg_hcd_connect_timeout(unsigned long ptr)
9987 +{
9988 +       DWC_DEBUGPL(DBG_HCDV, "%s(%x)\n", __func__, (int)ptr);
9989 +       DWC_PRINT("Connect Timeout\n");
9990 +       DWC_ERROR("Device Not Connected/Responding\n");
9991 +}
9992 +
9993 +/**
9994 + * Start the connection timer.  An OTG host is required to display a
9995 + * message if the device does not connect within 10 seconds.  The
9996 + * timer is deleted if a port connect interrupt occurs before the
9997 + * timer expires.
9998 + */
9999 +static void dwc_otg_hcd_start_connect_timer(dwc_otg_hcd_t *hcd)
10000 +{
10001 +       init_timer(&hcd->conn_timer);
10002 +       hcd->conn_timer.function = dwc_otg_hcd_connect_timeout;
10003 +       hcd->conn_timer.data = 0;
10004 +       hcd->conn_timer.expires = jiffies + (HZ * 10);
10005 +       add_timer(&hcd->conn_timer);
10006 +}
10007 +
10008 +/**
10009 + * HCD Callback function for disconnect of the HCD.
10010 + *
10011 + * @param p void pointer to the <code>struct usb_hcd</code>
10012 + */
10013 +static int32_t dwc_otg_hcd_session_start_cb(void *p)
10014 +{
10015 +       dwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd(p);
10016 +       DWC_DEBUGPL(DBG_HCDV, "%s(%p)\n", __func__, p);
10017 +       dwc_otg_hcd_start_connect_timer(dwc_otg_hcd);
10018 +       return 1;
10019 +}
10020 +
10021 +/**
10022 + * HCD Callback structure for handling mode switching.
10023 + */
10024 +static dwc_otg_cil_callbacks_t hcd_cil_callbacks = {
10025 +       .start = dwc_otg_hcd_start_cb,
10026 +       .stop = dwc_otg_hcd_stop_cb,
10027 +       .disconnect = dwc_otg_hcd_disconnect_cb,
10028 +       .session_start = dwc_otg_hcd_session_start_cb,
10029 +       .p = 0,
10030 +};
10031 +
10032 +/**
10033 + * Reset tasklet function
10034 + */
10035 +static void reset_tasklet_func(unsigned long data)
10036 +{
10037 +       dwc_otg_hcd_t *dwc_otg_hcd = (dwc_otg_hcd_t *)data;
10038 +       dwc_otg_core_if_t *core_if = dwc_otg_hcd->core_if;
10039 +       hprt0_data_t hprt0;
10040 +
10041 +       DWC_DEBUGPL(DBG_HCDV, "USB RESET tasklet called\n");
10042 +
10043 +       hprt0.d32 = dwc_otg_read_hprt0(core_if);
10044 +       hprt0.b.prtrst = 1;
10045 +       dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32);
10046 +       mdelay(60);
10047 +
10048 +       hprt0.b.prtrst = 0;
10049 +       dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32);
10050 +       dwc_otg_hcd->flags.b.port_reset_change = 1;
10051 +}
10052 +
10053 +static struct tasklet_struct reset_tasklet = {
10054 +       .next = NULL,
10055 +       .state = 0,
10056 +       .count = ATOMIC_INIT(0),
10057 +       .func = reset_tasklet_func,
10058 +       .data = 0,
10059 +};
10060 +
10061 +/**
10062 + * Initializes the HCD. This function allocates memory for and initializes the
10063 + * static parts of the usb_hcd and dwc_otg_hcd structures. It also registers the
10064 + * USB bus with the core and calls the hc_driver->start() function. It returns
10065 + * a negative error on failure.
10066 + */
10067 +int dwc_otg_hcd_init(struct device *dev)
10068 +{
10069 +       dwc_otg_device_t *otg_dev = dev_get_drvdata(dev);
10070 +       struct usb_hcd *hcd = NULL;
10071 +       dwc_otg_hcd_t *dwc_otg_hcd = NULL;
10072 +
10073 +       int             num_channels;
10074 +       int             i;
10075 +       dwc_hc_t        *channel;
10076 +
10077 +       int retval = 0;
10078 +
10079 +       DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD INIT\n");
10080 +
10081 +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20)
10082 +       /* 2.6.20+ requires dev.dma_mask to be set prior to calling usb_create_hcd() */
10083 +
10084 +       /* Set device flags indicating whether the HCD supports DMA. */
10085 +       if (otg_dev->core_if->dma_enable) {
10086 +               DWC_PRINT("Using DMA mode\n");
10087 +               dev->dma_mask = (void *)~0;
10088 +               dev->coherent_dma_mask = ~0;
10089 +
10090 +               if (otg_dev->core_if->dma_desc_enable) {
10091 +                       DWC_PRINT("Device using Descriptor DMA mode\n");
10092 +               } else {
10093 +                       DWC_PRINT("Device using Buffer DMA mode\n");
10094 +               }
10095 +       } else {
10096 +               DWC_PRINT("Using Slave mode\n");
10097 +               dev->dma_mask = (void *)0;
10098 +               dev->coherent_dma_mask = 0;
10099 +       }
10100 +#endif
10101 +       /*
10102 +        * Allocate memory for the base HCD plus the DWC OTG HCD.
10103 +        * Initialize the base HCD.
10104 +        */
10105 +       hcd = usb_create_hcd(&dwc_otg_hc_driver, dev, dev_name(dev));
10106 +       if (!hcd) {
10107 +               retval = -ENOMEM;
10108 +               goto error1;
10109 +       }
10110 +
10111 +       dev_set_drvdata(dev, otg_dev);
10112 +       hcd->regs = otg_dev->base;
10113 +       hcd->rsrc_start = otg_dev->phys_addr;
10114 +       hcd->rsrc_len = otg_dev->base_len;
10115 +       hcd->self.otg_port = 1;
10116 +       hcd->has_tt = 1;
10117 +
10118 +       /* Initialize the DWC OTG HCD. */
10119 +       dwc_otg_hcd = hcd_to_dwc_otg_hcd(hcd);
10120 +       dwc_otg_hcd->core_if = otg_dev->core_if;
10121 +       otg_dev->hcd = dwc_otg_hcd;
10122 +
10123 +       /* */
10124 +       spin_lock_init(&dwc_otg_hcd->lock);
10125 +
10126 +       /* Register the HCD CIL Callbacks */
10127 +       dwc_otg_cil_register_hcd_callbacks(otg_dev->core_if,
10128 +                                          &hcd_cil_callbacks, hcd);
10129 +
10130 +       /* Initialize the non-periodic schedule. */
10131 +       INIT_LIST_HEAD(&dwc_otg_hcd->non_periodic_sched_inactive);
10132 +       INIT_LIST_HEAD(&dwc_otg_hcd->non_periodic_sched_active);
10133 +
10134 +       /* Initialize the periodic schedule. */
10135 +       INIT_LIST_HEAD(&dwc_otg_hcd->periodic_sched_inactive);
10136 +       INIT_LIST_HEAD(&dwc_otg_hcd->periodic_sched_ready);
10137 +       INIT_LIST_HEAD(&dwc_otg_hcd->periodic_sched_assigned);
10138 +       INIT_LIST_HEAD(&dwc_otg_hcd->periodic_sched_queued);
10139 +
10140 +       /*
10141 +        * Create a host channel descriptor for each host channel implemented
10142 +        * in the controller. Initialize the channel descriptor array.
10143 +        */
10144 +       INIT_LIST_HEAD(&dwc_otg_hcd->free_hc_list);
10145 +       num_channels = dwc_otg_hcd->core_if->core_params->host_channels;
10146 +       memset(dwc_otg_hcd->hc_ptr_array, 0, sizeof(dwc_otg_hcd->hc_ptr_array));
10147 +       for (i = 0; i < num_channels; i++) {
10148 +               channel = kmalloc(sizeof(dwc_hc_t), GFP_KERNEL);
10149 +               if (channel == NULL) {
10150 +                       retval = -ENOMEM;
10151 +                       DWC_ERROR("%s: host channel allocation failed\n", __func__);
10152 +                       goto error2;
10153 +               }
10154 +               memset(channel, 0, sizeof(dwc_hc_t));
10155 +               channel->hc_num = i;
10156 +               dwc_otg_hcd->hc_ptr_array[i] = channel;
10157 +#ifdef DEBUG
10158 +               init_timer(&dwc_otg_hcd->core_if->hc_xfer_timer[i]);
10159 +#endif
10160 +               DWC_DEBUGPL(DBG_HCDV, "HCD Added channel #%d, hc=%p\n", i, channel);
10161 +       }
10162 +
10163 +       /* Initialize the Connection timeout timer. */
10164 +       init_timer(&dwc_otg_hcd->conn_timer);
10165 +
10166 +       /* Initialize reset tasklet. */
10167 +       reset_tasklet.data = (unsigned long) dwc_otg_hcd;
10168 +       dwc_otg_hcd->reset_tasklet = &reset_tasklet;
10169 +
10170 +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,20)
10171 +       /* Set device flags indicating whether the HCD supports DMA. */
10172 +       if (otg_dev->core_if->dma_enable) {
10173 +               DWC_PRINT("Using DMA mode\n");
10174 +               dev->dma_mask = (void *)~0;
10175 +               dev->coherent_dma_mask = ~0;
10176 +
10177 +               if (otg_dev->core_if->dma_desc_enable){
10178 +                       DWC_PRINT("Device using Descriptor DMA mode\n");
10179 +               } else {
10180 +                       DWC_PRINT("Device using Buffer DMA mode\n");
10181 +               }
10182 +       } else {
10183 +               DWC_PRINT("Using Slave mode\n");
10184 +               dev->dma_mask = (void *)0;
10185 +               dev->dev.coherent_dma_mask = 0;
10186 +       }
10187 +#endif
10188 +       /*
10189 +        * Finish generic HCD initialization and start the HCD. This function
10190 +        * allocates the DMA buffer pool, registers the USB bus, requests the
10191 +        * IRQ line, and calls dwc_otg_hcd_start method.
10192 +        */
10193 +       retval = usb_add_hcd(hcd, otg_dev->irq, IRQF_SHARED);
10194 +       if (retval < 0) {
10195 +               goto error2;
10196 +       }
10197 +
10198 +       /*
10199 +        * Allocate space for storing data on status transactions. Normally no
10200 +        * data is sent, but this space acts as a bit bucket. This must be
10201 +        * done after usb_add_hcd since that function allocates the DMA buffer
10202 +        * pool.
10203 +        */
10204 +       if (otg_dev->core_if->dma_enable) {
10205 +               dwc_otg_hcd->status_buf =
10206 +                       dma_alloc_coherent(dev,
10207 +                                          DWC_OTG_HCD_STATUS_BUF_SIZE,
10208 +                                          &dwc_otg_hcd->status_buf_dma,
10209 +                                          GFP_KERNEL | GFP_DMA);
10210 +       } else {
10211 +               dwc_otg_hcd->status_buf = kmalloc(DWC_OTG_HCD_STATUS_BUF_SIZE,
10212 +                                                 GFP_KERNEL);
10213 +       }
10214 +       if (!dwc_otg_hcd->status_buf) {
10215 +               retval = -ENOMEM;
10216 +               DWC_ERROR("%s: status_buf allocation failed\n", __func__);
10217 +               goto error3;
10218 +       }
10219 +
10220 +       dwc_otg_hcd->otg_dev = otg_dev;
10221 +
10222 +       DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD Initialized HCD, bus=%s, usbbus=%d\n",
10223 +                   dev_name(dev), hcd->self.busnum);
10224 +
10225 +       return 0;
10226 +
10227 +       /* Error conditions */
10228 + error3:
10229 +       usb_remove_hcd(hcd);
10230 + error2:
10231 +       dwc_otg_hcd_free(hcd);
10232 +       usb_put_hcd(hcd);
10233 +
10234 +       /* FIXME: 2008/05/03 by Steven
10235 +        * write back to device:
10236 +        * dwc_otg_hcd has already been released by dwc_otg_hcd_free()
10237 +        */
10238 +       dev_set_drvdata(dev, otg_dev);
10239 +
10240 + error1:
10241 +       return retval;
10242 +}
10243 +
10244 +/**
10245 + * Removes the HCD.
10246 + * Frees memory and resources associated with the HCD and deregisters the bus.
10247 + */
10248 +void dwc_otg_hcd_remove(struct device *dev)
10249 +{
10250 +       dwc_otg_device_t *otg_dev = dev_get_drvdata(dev);
10251 +       dwc_otg_hcd_t *dwc_otg_hcd;
10252 +       struct usb_hcd *hcd;
10253 +
10254 +       DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD REMOVE\n");
10255 +
10256 +       if (!otg_dev) {
10257 +               DWC_DEBUGPL(DBG_ANY, "%s: otg_dev NULL!\n", __func__);
10258 +               return;
10259 +       }
10260 +
10261 +       dwc_otg_hcd = otg_dev->hcd;
10262 +
10263 +       if (!dwc_otg_hcd) {
10264 +               DWC_DEBUGPL(DBG_ANY, "%s: otg_dev->hcd NULL!\n", __func__);
10265 +               return;
10266 +       }
10267 +
10268 +       hcd = dwc_otg_hcd_to_hcd(dwc_otg_hcd);
10269 +
10270 +       if (!hcd) {
10271 +               DWC_DEBUGPL(DBG_ANY, "%s: dwc_otg_hcd_to_hcd(dwc_otg_hcd) NULL!\n", __func__);
10272 +               return;
10273 +       }
10274 +
10275 +       /* Turn off all interrupts */
10276 +       dwc_write_reg32(&dwc_otg_hcd->core_if->core_global_regs->gintmsk, 0);
10277 +       dwc_modify_reg32(&dwc_otg_hcd->core_if->core_global_regs->gahbcfg, 1, 0);
10278 +
10279 +       usb_remove_hcd(hcd);
10280 +       dwc_otg_hcd_free(hcd);
10281 +       usb_put_hcd(hcd);
10282 +}
10283 +
10284 +/* =========================================================================
10285 + *  Linux HC Driver Functions
10286 + * ========================================================================= */
10287 +
10288 +/**
10289 + * Initializes dynamic portions of the DWC_otg HCD state.
10290 + */
10291 +static void hcd_reinit(dwc_otg_hcd_t *hcd)
10292 +{
10293 +       struct list_head        *item;
10294 +       int                     num_channels;
10295 +       int                     i;
10296 +       dwc_hc_t                *channel;
10297 +
10298 +       hcd->flags.d32 = 0;
10299 +
10300 +       hcd->non_periodic_qh_ptr = &hcd->non_periodic_sched_active;
10301 +       hcd->non_periodic_channels = 0;
10302 +       hcd->periodic_channels = 0;
10303 +
10304 +       /*
10305 +        * Put all channels in the free channel list and clean up channel
10306 +        * states.
10307 +        */
10308 +       item = hcd->free_hc_list.next;
10309 +       while (item != &hcd->free_hc_list) {
10310 +               list_del(item);
10311 +               item = hcd->free_hc_list.next;
10312 +       }
10313 +       num_channels = hcd->core_if->core_params->host_channels;
10314 +       for (i = 0; i < num_channels; i++) {
10315 +               channel = hcd->hc_ptr_array[i];
10316 +               list_add_tail(&channel->hc_list_entry, &hcd->free_hc_list);
10317 +               dwc_otg_hc_cleanup(hcd->core_if, channel);
10318 +       }
10319 +
10320 +       /* Initialize the DWC core for host mode operation. */
10321 +       dwc_otg_core_host_init(hcd->core_if);
10322 +}
10323 +
10324 +/** Initializes the DWC_otg controller and its root hub and prepares it for host
10325 + * mode operation. Activates the root port. Returns 0 on success and a negative
10326 + * error code on failure. */
10327 +int dwc_otg_hcd_start(struct usb_hcd *hcd)
10328 +{
10329 +       dwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd(hcd);
10330 +       dwc_otg_core_if_t *core_if = dwc_otg_hcd->core_if;
10331 +       struct usb_bus *bus;
10332 +
10333 +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,20)
10334 +       struct usb_device *udev;
10335 +       int retval;
10336 +#endif
10337 +
10338 +       DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD START\n");
10339 +
10340 +       bus = hcd_to_bus(hcd);
10341 +
10342 +       /* Initialize the bus state.  If the core is in Device Mode
10343 +        * HALT the USB bus and return. */
10344 +       if (dwc_otg_is_device_mode(core_if)) {
10345 +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,20)
10346 +               hcd->state = HC_STATE_HALT;
10347 +#else
10348 +               hcd->state = HC_STATE_RUNNING;
10349 +#endif
10350 +               return 0;
10351 +       }
10352 +       hcd->state = HC_STATE_RUNNING;
10353 +
10354 +       /* Initialize and connect root hub if one is not already attached */
10355 +       if (bus->root_hub) {
10356 +               DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD Has Root Hub\n");
10357 +               /* Inform the HUB driver to resume. */
10358 +               usb_hcd_resume_root_hub(hcd);
10359 +       }
10360 +       else {
10361 +               DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD Does Not Have Root Hub\n");
10362 +
10363 +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,20)
10364 +               udev = usb_alloc_dev(NULL, bus, 0);
10365 +               udev->speed = USB_SPEED_HIGH;
10366 +               if (!udev) {
10367 +                       DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD Error udev alloc\n");
10368 +                       return -ENODEV;
10369 +               }
10370 +               if ((retval = usb_hcd_register_root_hub(udev, hcd)) != 0) {
10371 +                       DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD Error registering %d\n", retval);
10372 +                       return -ENODEV;
10373 +               }
10374 +#endif
10375 +       }
10376 +
10377 +       hcd_reinit(dwc_otg_hcd);
10378 +
10379 +       return 0;
10380 +}
10381 +
10382 +static void qh_list_free(dwc_otg_hcd_t *hcd, struct list_head *qh_list)
10383 +{
10384 +       struct list_head        *item;
10385 +       dwc_otg_qh_t            *qh;
10386 +
10387 +       if (!qh_list->next) {
10388 +               /* The list hasn't been initialized yet. */
10389 +               return;
10390 +       }
10391 +
10392 +       /* Ensure there are no QTDs or URBs left. */
10393 +       kill_urbs_in_qh_list(hcd, qh_list);
10394 +
10395 +       for (item = qh_list->next; item != qh_list; item = qh_list->next) {
10396 +               qh = list_entry(item, dwc_otg_qh_t, qh_list_entry);
10397 +               dwc_otg_hcd_qh_remove_and_free(hcd, qh);
10398 +       }
10399 +}
10400 +
10401 +/**
10402 + * Halts the DWC_otg host mode operations in a clean manner. USB transfers are
10403 + * stopped.
10404 + */
10405 +void dwc_otg_hcd_stop(struct usb_hcd *hcd)
10406 +{
10407 +       dwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd(hcd);
10408 +       hprt0_data_t hprt0 = { .d32=0 };
10409 +
10410 +       DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD STOP\n");
10411 +
10412 +       /* Turn off all host-specific interrupts. */
10413 +       dwc_otg_disable_host_interrupts(dwc_otg_hcd->core_if);
10414 +
10415 +       /*
10416 +        * The root hub should be disconnected before this function is called.
10417 +        * The disconnect will clear the QTD lists (via ..._hcd_urb_dequeue)
10418 +        * and the QH lists (via ..._hcd_endpoint_disable).
10419 +        */
10420 +
10421 +       /* Turn off the vbus power */
10422 +       DWC_PRINT("PortPower off\n");
10423 +       hprt0.b.prtpwr = 0;
10424 +       dwc_write_reg32(dwc_otg_hcd->core_if->host_if->hprt0, hprt0.d32);
10425 +}
10426 +
10427 +/** Returns the current frame number. */
10428 +int dwc_otg_hcd_get_frame_number(struct usb_hcd *hcd)
10429 +{
10430 +       dwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd(hcd);
10431 +       hfnum_data_t hfnum;
10432 +
10433 +       hfnum.d32 = dwc_read_reg32(&dwc_otg_hcd->core_if->
10434 +                                  host_if->host_global_regs->hfnum);
10435 +
10436 +#ifdef DEBUG_SOF
10437 +       DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD GET FRAME NUMBER %d\n", hfnum.b.frnum);
10438 +#endif
10439 +       return hfnum.b.frnum;
10440 +}
10441 +
10442 +/**
10443 + * Frees secondary storage associated with the dwc_otg_hcd structure contained
10444 + * in the struct usb_hcd field.
10445 + */
10446 +void dwc_otg_hcd_free(struct usb_hcd *hcd)
10447 +{
10448 +       dwc_otg_hcd_t   *dwc_otg_hcd = hcd_to_dwc_otg_hcd(hcd);
10449 +       int             i;
10450 +
10451 +       DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD FREE\n");
10452 +
10453 +       del_timers(dwc_otg_hcd);
10454 +
10455 +       /* Free memory for QH/QTD lists */
10456 +       qh_list_free(dwc_otg_hcd, &dwc_otg_hcd->non_periodic_sched_inactive);
10457 +       qh_list_free(dwc_otg_hcd, &dwc_otg_hcd->non_periodic_sched_active);
10458 +       qh_list_free(dwc_otg_hcd, &dwc_otg_hcd->periodic_sched_inactive);
10459 +       qh_list_free(dwc_otg_hcd, &dwc_otg_hcd->periodic_sched_ready);
10460 +       qh_list_free(dwc_otg_hcd, &dwc_otg_hcd->periodic_sched_assigned);
10461 +       qh_list_free(dwc_otg_hcd, &dwc_otg_hcd->periodic_sched_queued);
10462 +
10463 +       /* Free memory for the host channels. */
10464 +       for (i = 0; i < MAX_EPS_CHANNELS; i++) {
10465 +               dwc_hc_t *hc = dwc_otg_hcd->hc_ptr_array[i];
10466 +               if (hc != NULL) {
10467 +                       DWC_DEBUGPL(DBG_HCDV, "HCD Free channel #%i, hc=%p\n", i, hc);
10468 +                       kfree(hc);
10469 +               }
10470 +       }
10471 +
10472 +       if (dwc_otg_hcd->core_if->dma_enable) {
10473 +               if (dwc_otg_hcd->status_buf_dma) {
10474 +                       dma_free_coherent(hcd->self.controller,
10475 +                                         DWC_OTG_HCD_STATUS_BUF_SIZE,
10476 +                                         dwc_otg_hcd->status_buf,
10477 +                                         dwc_otg_hcd->status_buf_dma);
10478 +               }
10479 +       } else if (dwc_otg_hcd->status_buf != NULL) {
10480 +               kfree(dwc_otg_hcd->status_buf);
10481 +       }
10482 +}
10483 +
10484 +#ifdef DEBUG
10485 +static void dump_urb_info(struct urb *urb, char* fn_name)
10486 +{
10487 +       DWC_PRINT("%s, urb %p\n", fn_name, urb);
10488 +       DWC_PRINT("  Device address: %d\n", usb_pipedevice(urb->pipe));
10489 +       DWC_PRINT("  Endpoint: %d, %s\n", usb_pipeendpoint(urb->pipe),
10490 +                 (usb_pipein(urb->pipe) ? "IN" : "OUT"));
10491 +       DWC_PRINT("  Endpoint type: %s\n",
10492 +                 ({char *pipetype;
10493 +                   switch (usb_pipetype(urb->pipe)) {
10494 +                   case PIPE_CONTROL: pipetype = "CONTROL"; break;
10495 +                   case PIPE_BULK: pipetype = "BULK"; break;
10496 +                   case PIPE_INTERRUPT: pipetype = "INTERRUPT"; break;
10497 +                   case PIPE_ISOCHRONOUS: pipetype = "ISOCHRONOUS"; break;
10498 +                   default: pipetype = "UNKNOWN"; break;
10499 +                  }; pipetype;}));
10500 +       DWC_PRINT("  Speed: %s\n",
10501 +                 ({char *speed;
10502 +                   switch (urb->dev->speed) {
10503 +                   case USB_SPEED_HIGH: speed = "HIGH"; break;
10504 +                   case USB_SPEED_FULL: speed = "FULL"; break;
10505 +                   case USB_SPEED_LOW: speed = "LOW"; break;
10506 +                   default: speed = "UNKNOWN"; break;
10507 +                  }; speed;}));
10508 +       DWC_PRINT("  Max packet size: %d\n",
10509 +                 usb_maxpacket(urb->dev, urb->pipe, usb_pipeout(urb->pipe)));
10510 +       DWC_PRINT("  Data buffer length: %d\n", urb->transfer_buffer_length);
10511 +       DWC_PRINT("  Transfer buffer: %p, Transfer DMA: %p\n",
10512 +                 urb->transfer_buffer, (void *)urb->transfer_dma);
10513 +       DWC_PRINT("  Setup buffer: %p, Setup DMA: %p\n",
10514 +                 urb->setup_packet, (void *)urb->setup_dma);
10515 +       DWC_PRINT("  Interval: %d\n", urb->interval);
10516 +       if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) {
10517 +               int i;
10518 +               for (i = 0; i < urb->number_of_packets;  i++) {
10519 +                       DWC_PRINT("  ISO Desc %d:\n", i);
10520 +                       DWC_PRINT("    offset: %d, length %d\n",
10521 +                                 urb->iso_frame_desc[i].offset,
10522 +                                 urb->iso_frame_desc[i].length);
10523 +               }
10524 +       }
10525 +}
10526 +
10527 +static void dump_channel_info(dwc_otg_hcd_t *hcd,
10528 +                             dwc_otg_qh_t *qh)
10529 +{
10530 +       if (qh->channel != NULL) {
10531 +               dwc_hc_t *hc = qh->channel;
10532 +               struct list_head *item;
10533 +               dwc_otg_qh_t *qh_item;
10534 +               int num_channels = hcd->core_if->core_params->host_channels;
10535 +               int i;
10536 +
10537 +               dwc_otg_hc_regs_t *hc_regs;
10538 +               hcchar_data_t   hcchar;
10539 +               hcsplt_data_t   hcsplt;
10540 +               hctsiz_data_t   hctsiz;
10541 +               uint32_t        hcdma;
10542 +
10543 +               hc_regs = hcd->core_if->host_if->hc_regs[hc->hc_num];
10544 +               hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
10545 +               hcsplt.d32 = dwc_read_reg32(&hc_regs->hcsplt);
10546 +               hctsiz.d32 = dwc_read_reg32(&hc_regs->hctsiz);
10547 +               hcdma = dwc_read_reg32(&hc_regs->hcdma);
10548 +
10549 +               DWC_PRINT("  Assigned to channel %p:\n", hc);
10550 +               DWC_PRINT("    hcchar 0x%08x, hcsplt 0x%08x\n", hcchar.d32, hcsplt.d32);
10551 +               DWC_PRINT("    hctsiz 0x%08x, hcdma 0x%08x\n", hctsiz.d32, hcdma);
10552 +               DWC_PRINT("    dev_addr: %d, ep_num: %d, ep_is_in: %d\n",
10553 +                         hc->dev_addr, hc->ep_num, hc->ep_is_in);
10554 +               DWC_PRINT("    ep_type: %d\n", hc->ep_type);
10555 +               DWC_PRINT("    max_packet: %d\n", hc->max_packet);
10556 +               DWC_PRINT("    data_pid_start: %d\n", hc->data_pid_start);
10557 +               DWC_PRINT("    xfer_started: %d\n", hc->xfer_started);
10558 +               DWC_PRINT("    halt_status: %d\n", hc->halt_status);
10559 +               DWC_PRINT("    xfer_buff: %p\n", hc->xfer_buff);
10560 +               DWC_PRINT("    xfer_len: %d\n", hc->xfer_len);
10561 +               DWC_PRINT("    qh: %p\n", hc->qh);
10562 +               DWC_PRINT("  NP inactive sched:\n");
10563 +               list_for_each(item, &hcd->non_periodic_sched_inactive) {
10564 +                       qh_item = list_entry(item, dwc_otg_qh_t, qh_list_entry);
10565 +                       DWC_PRINT("    %p\n", qh_item);
10566 +               }
10567 +               DWC_PRINT("  NP active sched:\n");
10568 +               list_for_each(item, &hcd->non_periodic_sched_active) {
10569 +                       qh_item = list_entry(item, dwc_otg_qh_t, qh_list_entry);
10570 +                       DWC_PRINT("    %p\n", qh_item);
10571 +               }
10572 +               DWC_PRINT("  Channels: \n");
10573 +               for (i = 0; i < num_channels; i++) {
10574 +                       dwc_hc_t *hc = hcd->hc_ptr_array[i];
10575 +                       DWC_PRINT("    %2d: %p\n", i, hc);
10576 +               }
10577 +       }
10578 +}
10579 +#endif
10580 +
10581 +/** Starts processing a USB transfer request specified by a USB Request Block
10582 + * (URB). mem_flags indicates the type of memory allocation to use while
10583 + * processing this URB. */
10584 +int dwc_otg_hcd_urb_enqueue(struct usb_hcd *hcd,
10585 +                           struct urb *urb,
10586 +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,20)
10587 +                           int mem_flags
10588 +#else
10589 +                           gfp_t mem_flags
10590 +#endif
10591 +                         )
10592 +{
10593 +       int retval = 0;
10594 +       dwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd(hcd);
10595 +       dwc_otg_qtd_t *qtd;
10596 +
10597 +#ifdef DEBUG
10598 +       if (CHK_DEBUG_LEVEL(DBG_HCDV | DBG_HCD_URB)) {
10599 +               dump_urb_info(urb, "dwc_otg_hcd_urb_enqueue");
10600 +       }
10601 +#endif
10602 +       if (!dwc_otg_hcd->flags.b.port_connect_status) {
10603 +               /* No longer connected. */
10604 +               return -ENODEV;
10605 +       }
10606 +
10607 +       qtd = dwc_otg_hcd_qtd_create(urb);
10608 +       if (qtd == NULL) {
10609 +               DWC_ERROR("DWC OTG HCD URB Enqueue failed creating QTD\n");
10610 +               return -ENOMEM;
10611 +       }
10612 +
10613 +       retval = dwc_otg_hcd_qtd_add(qtd, dwc_otg_hcd);
10614 +       if (retval < 0) {
10615 +               DWC_ERROR("DWC OTG HCD URB Enqueue failed adding QTD. "
10616 +                         "Error status %d\n", retval);
10617 +               dwc_otg_hcd_qtd_free(qtd);
10618 +       }
10619 +
10620 +       return retval;
10621 +}
10622 +
10623 +/** Aborts/cancels a USB transfer request. Always returns 0 to indicate
10624 + * success.  */
10625 +int dwc_otg_hcd_urb_dequeue(struct usb_hcd *hcd,
10626 +                           struct urb *urb,
10627 +                           int status)
10628 +{
10629 +       unsigned long flags;
10630 +       dwc_otg_hcd_t *dwc_otg_hcd;
10631 +       dwc_otg_qtd_t *urb_qtd;
10632 +       dwc_otg_qh_t *qh;
10633 +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20)
10634 +       struct usb_host_endpoint *ep = dwc_urb_to_endpoint(urb);
10635 +#endif
10636 +
10637 +       DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD URB Dequeue\n");
10638 +
10639 +       dwc_otg_hcd = hcd_to_dwc_otg_hcd(hcd);
10640 +
10641 +       SPIN_LOCK_IRQSAVE(&dwc_otg_hcd->lock, flags);
10642 +
10643 +       urb_qtd = (dwc_otg_qtd_t *)urb->hcpriv;
10644 +       qh = (dwc_otg_qh_t *)ep->hcpriv;
10645 +
10646 +#ifdef DEBUG
10647 +       if (CHK_DEBUG_LEVEL(DBG_HCDV | DBG_HCD_URB)) {
10648 +               dump_urb_info(urb, "dwc_otg_hcd_urb_dequeue");
10649 +               if (urb_qtd == qh->qtd_in_process) {
10650 +                       dump_channel_info(dwc_otg_hcd, qh);
10651 +               }
10652 +       }
10653 +#endif
10654 +
10655 +       if (urb_qtd == qh->qtd_in_process) {
10656 +               /* The QTD is in process (it has been assigned to a channel). */
10657 +
10658 +               if (dwc_otg_hcd->flags.b.port_connect_status) {
10659 +                       /*
10660 +                        * If still connected (i.e. in host mode), halt the
10661 +                        * channel so it can be used for other transfers. If
10662 +                        * no longer connected, the host registers can't be
10663 +                        * written to halt the channel since the core is in
10664 +                        * device mode.
10665 +                        */
10666 +                       dwc_otg_hc_halt(dwc_otg_hcd->core_if, qh->channel,
10667 +                                       DWC_OTG_HC_XFER_URB_DEQUEUE);
10668 +               }
10669 +       }
10670 +
10671 +       /*
10672 +        * Free the QTD and clean up the associated QH. Leave the QH in the
10673 +        * schedule if it has any remaining QTDs.
10674 +        */
10675 +       dwc_otg_hcd_qtd_remove_and_free(dwc_otg_hcd, urb_qtd);
10676 +       if (urb_qtd == qh->qtd_in_process) {
10677 +               dwc_otg_hcd_qh_deactivate(dwc_otg_hcd, qh, 0);
10678 +               qh->channel = NULL;
10679 +               qh->qtd_in_process = NULL;
10680 +       } else if (list_empty(&qh->qtd_list)) {
10681 +               dwc_otg_hcd_qh_remove(dwc_otg_hcd, qh);
10682 +       }
10683 +
10684 +       SPIN_UNLOCK_IRQRESTORE(&dwc_otg_hcd->lock, flags);
10685 +
10686 +       urb->hcpriv = NULL;
10687 +
10688 +       /* Higher layer software sets URB status. */
10689 +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20)
10690 +       usb_hcd_giveback_urb(hcd, urb, status);
10691 +#else
10692 +       usb_hcd_giveback_urb(hcd, urb, NULL);
10693 +#endif
10694 +       if (CHK_DEBUG_LEVEL(DBG_HCDV | DBG_HCD_URB)) {
10695 +               DWC_PRINT("Called usb_hcd_giveback_urb()\n");
10696 +               DWC_PRINT("  urb->status = %d\n", urb->status);
10697 +       }
10698 +
10699 +       return 0;
10700 +}
10701 +
10702 +/** Frees resources in the DWC_otg controller related to a given endpoint. Also
10703 + * clears state in the HCD related to the endpoint. Any URBs for the endpoint
10704 + * must already be dequeued. */
10705 +void dwc_otg_hcd_endpoint_disable(struct usb_hcd *hcd,
10706 +                                 struct usb_host_endpoint *ep)
10707 +{
10708 +       dwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd(hcd);
10709 +       dwc_otg_qh_t *qh;
10710 +
10711 +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20)
10712 +       unsigned long flags;
10713 +       int retry = 0;
10714 +#endif
10715 +
10716 +       DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD EP DISABLE: _bEndpointAddress=0x%02x, "
10717 +                   "endpoint=%d\n", ep->desc.bEndpointAddress,
10718 +                   dwc_ep_addr_to_endpoint(ep->desc.bEndpointAddress));
10719 +
10720 +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20)
10721 +rescan:
10722 +       SPIN_LOCK_IRQSAVE(&dwc_otg_hcd->lock, flags);
10723 +       qh = (dwc_otg_qh_t *)(ep->hcpriv);
10724 +       if (!qh)
10725 +               goto done;
10726 +
10727 +       /** Check that the QTD list is really empty */
10728 +       if (!list_empty(&qh->qtd_list)) {
10729 +               if (retry++ < 250) {
10730 +                       SPIN_UNLOCK_IRQRESTORE(&dwc_otg_hcd->lock, flags);
10731 +                       schedule_timeout_uninterruptible(1);
10732 +                       goto rescan;
10733 +               }
10734 +
10735 +               DWC_WARN("DWC OTG HCD EP DISABLE:"
10736 +                        " QTD List for this endpoint is not empty\n");
10737 +       }
10738 +
10739 +       dwc_otg_hcd_qh_remove_and_free(dwc_otg_hcd, qh);
10740 +       ep->hcpriv = NULL;
10741 +done:
10742 +       SPIN_UNLOCK_IRQRESTORE(&dwc_otg_hcd->lock, flags);
10743 +
10744 +#else // LINUX_VERSION_CODE
10745 +
10746 +       qh = (dwc_otg_qh_t *)(ep->hcpriv);
10747 +       if (qh != NULL) {
10748 +#ifdef DEBUG
10749 +               /** Check that the QTD list is really empty */
10750 +               if (!list_empty(&qh->qtd_list)) {
10751 +                       DWC_WARN("DWC OTG HCD EP DISABLE:"
10752 +                                " QTD List for this endpoint is not empty\n");
10753 +               }
10754 +#endif
10755 +               dwc_otg_hcd_qh_remove_and_free(dwc_otg_hcd, qh);
10756 +               ep->hcpriv = NULL;
10757 +       }
10758 +#endif // LINUX_VERSION_CODE
10759 +}
10760 +
10761 +/** Handles host mode interrupts for the DWC_otg controller. Returns IRQ_NONE if
10762 + * there was no interrupt to handle. Returns IRQ_HANDLED if there was a valid
10763 + * interrupt.
10764 + *
10765 + * This function is called by the USB core when an interrupt occurs */
10766 +irqreturn_t dwc_otg_hcd_irq(struct usb_hcd *hcd
10767 +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,19)
10768 +                           , struct pt_regs *regs
10769 +#endif
10770 +                         )
10771 +{
10772 +       dwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd(hcd);
10773 +       return IRQ_RETVAL(dwc_otg_hcd_handle_intr(dwc_otg_hcd));
10774 +}
10775 +
10776 +/** Creates Status Change bitmap for the root hub and root port. The bitmap is
10777 + * returned in buf. Bit 0 is the status change indicator for the root hub. Bit 1
10778 + * is the status change indicator for the single root port. Returns 1 if either
10779 + * change indicator is 1, otherwise returns 0. */
10780 +int dwc_otg_hcd_hub_status_data(struct usb_hcd *hcd, char *buf)
10781 +{
10782 +       dwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd(hcd);
10783 +
10784 +       buf[0] = 0;
10785 +       buf[0] |= (dwc_otg_hcd->flags.b.port_connect_status_change ||
10786 +                   dwc_otg_hcd->flags.b.port_reset_change ||
10787 +                   dwc_otg_hcd->flags.b.port_enable_change ||
10788 +                   dwc_otg_hcd->flags.b.port_suspend_change ||
10789 +                   dwc_otg_hcd->flags.b.port_over_current_change) << 1;
10790 +
10791 +#ifdef DEBUG
10792 +       if (buf[0]) {
10793 +               DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB STATUS DATA:"
10794 +                           " Root port status changed\n");
10795 +               DWC_DEBUGPL(DBG_HCDV, "  port_connect_status_change: %d\n",
10796 +                           dwc_otg_hcd->flags.b.port_connect_status_change);
10797 +               DWC_DEBUGPL(DBG_HCDV, "  port_reset_change: %d\n",
10798 +                           dwc_otg_hcd->flags.b.port_reset_change);
10799 +               DWC_DEBUGPL(DBG_HCDV, "  port_enable_change: %d\n",
10800 +                           dwc_otg_hcd->flags.b.port_enable_change);
10801 +               DWC_DEBUGPL(DBG_HCDV, "  port_suspend_change: %d\n",
10802 +                           dwc_otg_hcd->flags.b.port_suspend_change);
10803 +               DWC_DEBUGPL(DBG_HCDV, "  port_over_current_change: %d\n",
10804 +                           dwc_otg_hcd->flags.b.port_over_current_change);
10805 +       }
10806 +#endif
10807 +       return (buf[0] != 0);
10808 +}
10809 +
10810 +#ifdef DWC_HS_ELECT_TST
10811 +/*
10812 + * Quick and dirty hack to implement the HS Electrical Test
10813 + * SINGLE_STEP_GET_DEVICE_DESCRIPTOR feature.
10814 + *
10815 + * This code was copied from our userspace app "hset". It sends a
10816 + * Get Device Descriptor control sequence in two parts, first the
10817 + * Setup packet by itself, followed some time later by the In and
10818 + * Ack packets. Rather than trying to figure out how to add this
10819 + * functionality to the normal driver code, we just hijack the
10820 + * hardware, using these two function to drive the hardware
10821 + * directly.
10822 + */
10823 +
10824 +dwc_otg_core_global_regs_t *global_regs;
10825 +dwc_otg_host_global_regs_t *hc_global_regs;
10826 +dwc_otg_hc_regs_t *hc_regs;
10827 +uint32_t *data_fifo;
10828 +
10829 +static void do_setup(void)
10830 +{
10831 +       gintsts_data_t gintsts;
10832 +       hctsiz_data_t hctsiz;
10833 +       hcchar_data_t hcchar;
10834 +       haint_data_t haint;
10835 +       hcint_data_t hcint;
10836 +
10837 +       /* Enable HAINTs */
10838 +       dwc_write_reg32(&hc_global_regs->haintmsk, 0x0001);
10839 +
10840 +       /* Enable HCINTs */
10841 +       dwc_write_reg32(&hc_regs->hcintmsk, 0x04a3);
10842 +
10843 +       /* Read GINTSTS */
10844 +       gintsts.d32 = dwc_read_reg32(&global_regs->gintsts);
10845 +       //fprintf(stderr, "GINTSTS: %08x\n", gintsts.d32);
10846 +
10847 +       /* Read HAINT */
10848 +       haint.d32 = dwc_read_reg32(&hc_global_regs->haint);
10849 +       //fprintf(stderr, "HAINT: %08x\n", haint.d32);
10850 +
10851 +       /* Read HCINT */
10852 +       hcint.d32 = dwc_read_reg32(&hc_regs->hcint);
10853 +       //fprintf(stderr, "HCINT: %08x\n", hcint.d32);
10854 +
10855 +       /* Read HCCHAR */
10856 +       hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
10857 +       //fprintf(stderr, "HCCHAR: %08x\n", hcchar.d32);
10858 +
10859 +       /* Clear HCINT */
10860 +       dwc_write_reg32(&hc_regs->hcint, hcint.d32);
10861 +
10862 +       /* Clear HAINT */
10863 +       dwc_write_reg32(&hc_global_regs->haint, haint.d32);
10864 +
10865 +       /* Clear GINTSTS */
10866 +       dwc_write_reg32(&global_regs->gintsts, gintsts.d32);
10867 +
10868 +       /* Read GINTSTS */
10869 +       gintsts.d32 = dwc_read_reg32(&global_regs->gintsts);
10870 +       //fprintf(stderr, "GINTSTS: %08x\n", gintsts.d32);
10871 +
10872 +       /*
10873 +        * Send Setup packet (Get Device Descriptor)
10874 +        */
10875 +
10876 +       /* Make sure channel is disabled */
10877 +       hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
10878 +       if (hcchar.b.chen) {
10879 +               //fprintf(stderr, "Channel already enabled 1, HCCHAR = %08x\n", hcchar.d32);
10880 +               hcchar.b.chdis = 1;
10881 +//             hcchar.b.chen = 1;
10882 +               dwc_write_reg32(&hc_regs->hcchar, hcchar.d32);
10883 +               //sleep(1);
10884 +               mdelay(1000);
10885 +
10886 +               /* Read GINTSTS */
10887 +               gintsts.d32 = dwc_read_reg32(&global_regs->gintsts);
10888 +               //fprintf(stderr, "GINTSTS: %08x\n", gintsts.d32);
10889 +
10890 +               /* Read HAINT */
10891 +               haint.d32 = dwc_read_reg32(&hc_global_regs->haint);
10892 +               //fprintf(stderr, "HAINT: %08x\n", haint.d32);
10893 +
10894 +               /* Read HCINT */
10895 +               hcint.d32 = dwc_read_reg32(&hc_regs->hcint);
10896 +               //fprintf(stderr, "HCINT: %08x\n", hcint.d32);
10897 +
10898 +               /* Read HCCHAR */
10899 +               hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
10900 +               //fprintf(stderr, "HCCHAR: %08x\n", hcchar.d32);
10901 +
10902 +               /* Clear HCINT */
10903 +               dwc_write_reg32(&hc_regs->hcint, hcint.d32);
10904 +
10905 +               /* Clear HAINT */
10906 +               dwc_write_reg32(&hc_global_regs->haint, haint.d32);
10907 +
10908 +               /* Clear GINTSTS */
10909 +               dwc_write_reg32(&global_regs->gintsts, gintsts.d32);
10910 +
10911 +               hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
10912 +               //if (hcchar.b.chen) {
10913 +               //      fprintf(stderr, "** Channel _still_ enabled 1, HCCHAR = %08x **\n", hcchar.d32);
10914 +               //}
10915 +       }
10916 +
10917 +       /* Set HCTSIZ */
10918 +       hctsiz.d32 = 0;
10919 +       hctsiz.b.xfersize = 8;
10920 +       hctsiz.b.pktcnt = 1;
10921 +       hctsiz.b.pid = DWC_OTG_HC_PID_SETUP;
10922 +       dwc_write_reg32(&hc_regs->hctsiz, hctsiz.d32);
10923 +
10924 +       /* Set HCCHAR */
10925 +       hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
10926 +       hcchar.b.eptype = DWC_OTG_EP_TYPE_CONTROL;
10927 +       hcchar.b.epdir = 0;
10928 +       hcchar.b.epnum = 0;
10929 +       hcchar.b.mps = 8;
10930 +       hcchar.b.chen = 1;
10931 +       dwc_write_reg32(&hc_regs->hcchar, hcchar.d32);
10932 +
10933 +       /* Fill FIFO with Setup data for Get Device Descriptor */
10934 +       data_fifo = (uint32_t *)((char *)global_regs + 0x1000);
10935 +       dwc_write_reg32(data_fifo++, 0x01000680);
10936 +       dwc_write_reg32(data_fifo++, 0x00080000);
10937 +
10938 +       gintsts.d32 = dwc_read_reg32(&global_regs->gintsts);
10939 +       //fprintf(stderr, "Waiting for HCINTR intr 1, GINTSTS = %08x\n", gintsts.d32);
10940 +
10941 +       /* Wait for host channel interrupt */
10942 +       do {
10943 +               gintsts.d32 = dwc_read_reg32(&global_regs->gintsts);
10944 +       } while (gintsts.b.hcintr == 0);
10945 +
10946 +       //fprintf(stderr, "Got HCINTR intr 1, GINTSTS = %08x\n", gintsts.d32);
10947 +
10948 +       /* Disable HCINTs */
10949 +       dwc_write_reg32(&hc_regs->hcintmsk, 0x0000);
10950 +
10951 +       /* Disable HAINTs */
10952 +       dwc_write_reg32(&hc_global_regs->haintmsk, 0x0000);
10953 +
10954 +       /* Read HAINT */
10955 +       haint.d32 = dwc_read_reg32(&hc_global_regs->haint);
10956 +       //fprintf(stderr, "HAINT: %08x\n", haint.d32);
10957 +
10958 +       /* Read HCINT */
10959 +       hcint.d32 = dwc_read_reg32(&hc_regs->hcint);
10960 +       //fprintf(stderr, "HCINT: %08x\n", hcint.d32);
10961 +
10962 +       /* Read HCCHAR */
10963 +       hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
10964 +       //fprintf(stderr, "HCCHAR: %08x\n", hcchar.d32);
10965 +
10966 +       /* Clear HCINT */
10967 +       dwc_write_reg32(&hc_regs->hcint, hcint.d32);
10968 +
10969 +       /* Clear HAINT */
10970 +       dwc_write_reg32(&hc_global_regs->haint, haint.d32);
10971 +
10972 +       /* Clear GINTSTS */
10973 +       dwc_write_reg32(&global_regs->gintsts, gintsts.d32);
10974 +
10975 +       /* Read GINTSTS */
10976 +       gintsts.d32 = dwc_read_reg32(&global_regs->gintsts);
10977 +       //fprintf(stderr, "GINTSTS: %08x\n", gintsts.d32);
10978 +}
10979 +
10980 +static void do_in_ack(void)
10981 +{
10982 +       gintsts_data_t gintsts;
10983 +       hctsiz_data_t hctsiz;
10984 +       hcchar_data_t hcchar;
10985 +       haint_data_t haint;
10986 +       hcint_data_t hcint;
10987 +       host_grxsts_data_t grxsts;
10988 +
10989 +       /* Enable HAINTs */
10990 +       dwc_write_reg32(&hc_global_regs->haintmsk, 0x0001);
10991 +
10992 +       /* Enable HCINTs */
10993 +       dwc_write_reg32(&hc_regs->hcintmsk, 0x04a3);
10994 +
10995 +       /* Read GINTSTS */
10996 +       gintsts.d32 = dwc_read_reg32(&global_regs->gintsts);
10997 +       //fprintf(stderr, "GINTSTS: %08x\n", gintsts.d32);
10998 +
10999 +       /* Read HAINT */
11000 +       haint.d32 = dwc_read_reg32(&hc_global_regs->haint);
11001 +       //fprintf(stderr, "HAINT: %08x\n", haint.d32);
11002 +
11003 +       /* Read HCINT */
11004 +       hcint.d32 = dwc_read_reg32(&hc_regs->hcint);
11005 +       //fprintf(stderr, "HCINT: %08x\n", hcint.d32);
11006 +
11007 +       /* Read HCCHAR */
11008 +       hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
11009 +       //fprintf(stderr, "HCCHAR: %08x\n", hcchar.d32);
11010 +
11011 +       /* Clear HCINT */
11012 +       dwc_write_reg32(&hc_regs->hcint, hcint.d32);
11013 +
11014 +       /* Clear HAINT */
11015 +       dwc_write_reg32(&hc_global_regs->haint, haint.d32);
11016 +
11017 +       /* Clear GINTSTS */
11018 +       dwc_write_reg32(&global_regs->gintsts, gintsts.d32);
11019 +
11020 +       /* Read GINTSTS */
11021 +       gintsts.d32 = dwc_read_reg32(&global_regs->gintsts);
11022 +       //fprintf(stderr, "GINTSTS: %08x\n", gintsts.d32);
11023 +
11024 +       /*
11025 +        * Receive Control In packet
11026 +        */
11027 +
11028 +       /* Make sure channel is disabled */
11029 +       hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
11030 +       if (hcchar.b.chen) {
11031 +               //fprintf(stderr, "Channel already enabled 2, HCCHAR = %08x\n", hcchar.d32);
11032 +               hcchar.b.chdis = 1;
11033 +               hcchar.b.chen = 1;
11034 +               dwc_write_reg32(&hc_regs->hcchar, hcchar.d32);
11035 +               //sleep(1);
11036 +               mdelay(1000);
11037 +
11038 +               /* Read GINTSTS */
11039 +               gintsts.d32 = dwc_read_reg32(&global_regs->gintsts);
11040 +               //fprintf(stderr, "GINTSTS: %08x\n", gintsts.d32);
11041 +
11042 +               /* Read HAINT */
11043 +               haint.d32 = dwc_read_reg32(&hc_global_regs->haint);
11044 +               //fprintf(stderr, "HAINT: %08x\n", haint.d32);
11045 +
11046 +               /* Read HCINT */
11047 +               hcint.d32 = dwc_read_reg32(&hc_regs->hcint);
11048 +               //fprintf(stderr, "HCINT: %08x\n", hcint.d32);
11049 +
11050 +               /* Read HCCHAR */
11051 +               hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
11052 +               //fprintf(stderr, "HCCHAR: %08x\n", hcchar.d32);
11053 +
11054 +               /* Clear HCINT */
11055 +               dwc_write_reg32(&hc_regs->hcint, hcint.d32);
11056 +
11057 +               /* Clear HAINT */
11058 +               dwc_write_reg32(&hc_global_regs->haint, haint.d32);
11059 +
11060 +               /* Clear GINTSTS */
11061 +               dwc_write_reg32(&global_regs->gintsts, gintsts.d32);
11062 +
11063 +               hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
11064 +               //if (hcchar.b.chen) {
11065 +               //      fprintf(stderr, "** Channel _still_ enabled 2, HCCHAR = %08x **\n", hcchar.d32);
11066 +               //}
11067 +       }
11068 +
11069 +       /* Set HCTSIZ */
11070 +       hctsiz.d32 = 0;
11071 +       hctsiz.b.xfersize = 8;
11072 +       hctsiz.b.pktcnt = 1;
11073 +       hctsiz.b.pid = DWC_OTG_HC_PID_DATA1;
11074 +       dwc_write_reg32(&hc_regs->hctsiz, hctsiz.d32);
11075 +
11076 +       /* Set HCCHAR */
11077 +       hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
11078 +       hcchar.b.eptype = DWC_OTG_EP_TYPE_CONTROL;
11079 +       hcchar.b.epdir = 1;
11080 +       hcchar.b.epnum = 0;
11081 +       hcchar.b.mps = 8;
11082 +       hcchar.b.chen = 1;
11083 +       dwc_write_reg32(&hc_regs->hcchar, hcchar.d32);
11084 +
11085 +       gintsts.d32 = dwc_read_reg32(&global_regs->gintsts);
11086 +       //fprintf(stderr, "Waiting for RXSTSQLVL intr 1, GINTSTS = %08x\n", gintsts.d32);
11087 +
11088 +       /* Wait for receive status queue interrupt */
11089 +       do {
11090 +               gintsts.d32 = dwc_read_reg32(&global_regs->gintsts);
11091 +       } while (gintsts.b.rxstsqlvl == 0);
11092 +
11093 +       //fprintf(stderr, "Got RXSTSQLVL intr 1, GINTSTS = %08x\n", gintsts.d32);
11094 +
11095 +       /* Read RXSTS */
11096 +       grxsts.d32 = dwc_read_reg32(&global_regs->grxstsp);
11097 +       //fprintf(stderr, "GRXSTS: %08x\n", grxsts.d32);
11098 +
11099 +       /* Clear RXSTSQLVL in GINTSTS */
11100 +       gintsts.d32 = 0;
11101 +       gintsts.b.rxstsqlvl = 1;
11102 +       dwc_write_reg32(&global_regs->gintsts, gintsts.d32);
11103 +
11104 +       switch (grxsts.b.pktsts) {
11105 +       case DWC_GRXSTS_PKTSTS_IN:
11106 +               /* Read the data into the host buffer */
11107 +               if (grxsts.b.bcnt > 0) {
11108 +                       int i;
11109 +                       int word_count = (grxsts.b.bcnt + 3) / 4;
11110 +
11111 +                       data_fifo = (uint32_t *)((char *)global_regs + 0x1000);
11112 +
11113 +                       for (i = 0; i < word_count; i++) {
11114 +                               (void)dwc_read_reg32(data_fifo++);
11115 +                       }
11116 +               }
11117 +
11118 +               //fprintf(stderr, "Received %u bytes\n", (unsigned)grxsts.b.bcnt);
11119 +       break;
11120 +
11121 +       default:
11122 +               //fprintf(stderr, "** Unexpected GRXSTS packet status 1 **\n");
11123 +       break;
11124 +       }
11125 +
11126 +       gintsts.d32 = dwc_read_reg32(&global_regs->gintsts);
11127 +       //fprintf(stderr, "Waiting for RXSTSQLVL intr 2, GINTSTS = %08x\n", gintsts.d32);
11128 +
11129 +       /* Wait for receive status queue interrupt */
11130 +       do {
11131 +               gintsts.d32 = dwc_read_reg32(&global_regs->gintsts);
11132 +       } while (gintsts.b.rxstsqlvl == 0);
11133 +
11134 +       //fprintf(stderr, "Got RXSTSQLVL intr 2, GINTSTS = %08x\n", gintsts.d32);
11135 +
11136 +       /* Read RXSTS */
11137 +       grxsts.d32 = dwc_read_reg32(&global_regs->grxstsp);
11138 +       //fprintf(stderr, "GRXSTS: %08x\n", grxsts.d32);
11139 +
11140 +       /* Clear RXSTSQLVL in GINTSTS */
11141 +       gintsts.d32 = 0;
11142 +       gintsts.b.rxstsqlvl = 1;
11143 +       dwc_write_reg32(&global_regs->gintsts, gintsts.d32);
11144 +
11145 +       switch (grxsts.b.pktsts) {
11146 +       case DWC_GRXSTS_PKTSTS_IN_XFER_COMP:
11147 +       break;
11148 +
11149 +       default:
11150 +               //fprintf(stderr, "** Unexpected GRXSTS packet status 2 **\n");
11151 +       break;
11152 +       }
11153 +
11154 +       gintsts.d32 = dwc_read_reg32(&global_regs->gintsts);
11155 +       //fprintf(stderr, "Waiting for HCINTR intr 2, GINTSTS = %08x\n", gintsts.d32);
11156 +
11157 +       /* Wait for host channel interrupt */
11158 +       do {
11159 +               gintsts.d32 = dwc_read_reg32(&global_regs->gintsts);
11160 +       } while (gintsts.b.hcintr == 0);
11161 +
11162 +       //fprintf(stderr, "Got HCINTR intr 2, GINTSTS = %08x\n", gintsts.d32);
11163 +
11164 +       /* Read HAINT */
11165 +       haint.d32 = dwc_read_reg32(&hc_global_regs->haint);
11166 +       //fprintf(stderr, "HAINT: %08x\n", haint.d32);
11167 +
11168 +       /* Read HCINT */
11169 +       hcint.d32 = dwc_read_reg32(&hc_regs->hcint);
11170 +       //fprintf(stderr, "HCINT: %08x\n", hcint.d32);
11171 +
11172 +       /* Read HCCHAR */
11173 +       hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
11174 +       //fprintf(stderr, "HCCHAR: %08x\n", hcchar.d32);
11175 +
11176 +       /* Clear HCINT */
11177 +       dwc_write_reg32(&hc_regs->hcint, hcint.d32);
11178 +
11179 +       /* Clear HAINT */
11180 +       dwc_write_reg32(&hc_global_regs->haint, haint.d32);
11181 +
11182 +       /* Clear GINTSTS */
11183 +       dwc_write_reg32(&global_regs->gintsts, gintsts.d32);
11184 +
11185 +       /* Read GINTSTS */
11186 +       gintsts.d32 = dwc_read_reg32(&global_regs->gintsts);
11187 +       //fprintf(stderr, "GINTSTS: %08x\n", gintsts.d32);
11188 +
11189 +//     usleep(100000);
11190 +//     mdelay(100);
11191 +       mdelay(1);
11192 +
11193 +       /*
11194 +        * Send handshake packet
11195 +        */
11196 +
11197 +       /* Read HAINT */
11198 +       haint.d32 = dwc_read_reg32(&hc_global_regs->haint);
11199 +       //fprintf(stderr, "HAINT: %08x\n", haint.d32);
11200 +
11201 +       /* Read HCINT */
11202 +       hcint.d32 = dwc_read_reg32(&hc_regs->hcint);
11203 +       //fprintf(stderr, "HCINT: %08x\n", hcint.d32);
11204 +
11205 +       /* Read HCCHAR */
11206 +       hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
11207 +       //fprintf(stderr, "HCCHAR: %08x\n", hcchar.d32);
11208 +
11209 +       /* Clear HCINT */
11210 +       dwc_write_reg32(&hc_regs->hcint, hcint.d32);
11211 +
11212 +       /* Clear HAINT */
11213 +       dwc_write_reg32(&hc_global_regs->haint, haint.d32);
11214 +
11215 +       /* Clear GINTSTS */
11216 +       dwc_write_reg32(&global_regs->gintsts, gintsts.d32);
11217 +
11218 +       /* Read GINTSTS */
11219 +       gintsts.d32 = dwc_read_reg32(&global_regs->gintsts);
11220 +       //fprintf(stderr, "GINTSTS: %08x\n", gintsts.d32);
11221 +
11222 +       /* Make sure channel is disabled */
11223 +       hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
11224 +       if (hcchar.b.chen) {
11225 +               //fprintf(stderr, "Channel already enabled 3, HCCHAR = %08x\n", hcchar.d32);
11226 +               hcchar.b.chdis = 1;
11227 +               hcchar.b.chen = 1;
11228 +               dwc_write_reg32(&hc_regs->hcchar, hcchar.d32);
11229 +               //sleep(1);
11230 +               mdelay(1000);
11231 +
11232 +               /* Read GINTSTS */
11233 +               gintsts.d32 = dwc_read_reg32(&global_regs->gintsts);
11234 +               //fprintf(stderr, "GINTSTS: %08x\n", gintsts.d32);
11235 +
11236 +               /* Read HAINT */
11237 +               haint.d32 = dwc_read_reg32(&hc_global_regs->haint);
11238 +               //fprintf(stderr, "HAINT: %08x\n", haint.d32);
11239 +
11240 +               /* Read HCINT */
11241 +               hcint.d32 = dwc_read_reg32(&hc_regs->hcint);
11242 +               //fprintf(stderr, "HCINT: %08x\n", hcint.d32);
11243 +
11244 +               /* Read HCCHAR */
11245 +               hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
11246 +               //fprintf(stderr, "HCCHAR: %08x\n", hcchar.d32);
11247 +
11248 +               /* Clear HCINT */
11249 +               dwc_write_reg32(&hc_regs->hcint, hcint.d32);
11250 +
11251 +               /* Clear HAINT */
11252 +               dwc_write_reg32(&hc_global_regs->haint, haint.d32);
11253 +
11254 +               /* Clear GINTSTS */
11255 +               dwc_write_reg32(&global_regs->gintsts, gintsts.d32);
11256 +
11257 +               hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
11258 +               //if (hcchar.b.chen) {
11259 +               //      fprintf(stderr, "** Channel _still_ enabled 3, HCCHAR = %08x **\n", hcchar.d32);
11260 +               //}
11261 +       }
11262 +
11263 +       /* Set HCTSIZ */
11264 +       hctsiz.d32 = 0;
11265 +       hctsiz.b.xfersize = 0;
11266 +       hctsiz.b.pktcnt = 1;
11267 +       hctsiz.b.pid = DWC_OTG_HC_PID_DATA1;
11268 +       dwc_write_reg32(&hc_regs->hctsiz, hctsiz.d32);
11269 +
11270 +       /* Set HCCHAR */
11271 +       hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
11272 +       hcchar.b.eptype = DWC_OTG_EP_TYPE_CONTROL;
11273 +       hcchar.b.epdir = 0;
11274 +       hcchar.b.epnum = 0;
11275 +       hcchar.b.mps = 8;
11276 +       hcchar.b.chen = 1;
11277 +       dwc_write_reg32(&hc_regs->hcchar, hcchar.d32);
11278 +
11279 +       gintsts.d32 = dwc_read_reg32(&global_regs->gintsts);
11280 +       //fprintf(stderr, "Waiting for HCINTR intr 3, GINTSTS = %08x\n", gintsts.d32);
11281 +
11282 +       /* Wait for host channel interrupt */
11283 +       do {
11284 +               gintsts.d32 = dwc_read_reg32(&global_regs->gintsts);
11285 +       } while (gintsts.b.hcintr == 0);
11286 +
11287 +       //fprintf(stderr, "Got HCINTR intr 3, GINTSTS = %08x\n", gintsts.d32);
11288 +
11289 +       /* Disable HCINTs */
11290 +       dwc_write_reg32(&hc_regs->hcintmsk, 0x0000);
11291 +
11292 +       /* Disable HAINTs */
11293 +       dwc_write_reg32(&hc_global_regs->haintmsk, 0x0000);
11294 +
11295 +       /* Read HAINT */
11296 +       haint.d32 = dwc_read_reg32(&hc_global_regs->haint);
11297 +       //fprintf(stderr, "HAINT: %08x\n", haint.d32);
11298 +
11299 +       /* Read HCINT */
11300 +       hcint.d32 = dwc_read_reg32(&hc_regs->hcint);
11301 +       //fprintf(stderr, "HCINT: %08x\n", hcint.d32);
11302 +
11303 +       /* Read HCCHAR */
11304 +       hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
11305 +       //fprintf(stderr, "HCCHAR: %08x\n", hcchar.d32);
11306 +
11307 +       /* Clear HCINT */
11308 +       dwc_write_reg32(&hc_regs->hcint, hcint.d32);
11309 +
11310 +       /* Clear HAINT */
11311 +       dwc_write_reg32(&hc_global_regs->haint, haint.d32);
11312 +
11313 +       /* Clear GINTSTS */
11314 +       dwc_write_reg32(&global_regs->gintsts, gintsts.d32);
11315 +
11316 +       /* Read GINTSTS */
11317 +       gintsts.d32 = dwc_read_reg32(&global_regs->gintsts);
11318 +       //fprintf(stderr, "GINTSTS: %08x\n", gintsts.d32);
11319 +}
11320 +#endif /* DWC_HS_ELECT_TST */
11321 +
11322 +/** Handles hub class-specific requests. */
11323 +int dwc_otg_hcd_hub_control(struct usb_hcd *hcd,
11324 +                           u16 typeReq,
11325 +                           u16 wValue,
11326 +                           u16 wIndex,
11327 +                           char *buf,
11328 +                           u16 wLength)
11329 +{
11330 +       int retval = 0;
11331 +
11332 +       dwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd(hcd);
11333 +       dwc_otg_core_if_t *core_if = hcd_to_dwc_otg_hcd(hcd)->core_if;
11334 +       struct usb_hub_descriptor *desc;
11335 +       hprt0_data_t hprt0 = {.d32 = 0};
11336 +
11337 +       uint32_t port_status;
11338 +
11339 +       switch (typeReq) {
11340 +       case ClearHubFeature:
11341 +               DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
11342 +                           "ClearHubFeature 0x%x\n", wValue);
11343 +               switch (wValue) {
11344 +               case C_HUB_LOCAL_POWER:
11345 +               case C_HUB_OVER_CURRENT:
11346 +                       /* Nothing required here */
11347 +                       break;
11348 +               default:
11349 +                       retval = -EINVAL;
11350 +                       DWC_ERROR("DWC OTG HCD - "
11351 +                                 "ClearHubFeature request %xh unknown\n", wValue);
11352 +               }
11353 +               break;
11354 +       case ClearPortFeature:
11355 +               if (!wIndex || wIndex > 1)
11356 +                       goto error;
11357 +
11358 +               switch (wValue) {
11359 +               case USB_PORT_FEAT_ENABLE:
11360 +                       DWC_DEBUGPL(DBG_ANY, "DWC OTG HCD HUB CONTROL - "
11361 +                                   "ClearPortFeature USB_PORT_FEAT_ENABLE\n");
11362 +                       hprt0.d32 = dwc_otg_read_hprt0(core_if);
11363 +                       hprt0.b.prtena = 1;
11364 +                       dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32);
11365 +                       break;
11366 +               case USB_PORT_FEAT_SUSPEND:
11367 +                       DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
11368 +                                   "ClearPortFeature USB_PORT_FEAT_SUSPEND\n");
11369 +                       hprt0.d32 = dwc_otg_read_hprt0(core_if);
11370 +                       hprt0.b.prtres = 1;
11371 +                       dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32);
11372 +                       /* Clear Resume bit */
11373 +                       mdelay(100);
11374 +                       hprt0.b.prtres = 0;
11375 +                       dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32);
11376 +                       break;
11377 +               case USB_PORT_FEAT_POWER:
11378 +                       DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
11379 +                                   "ClearPortFeature USB_PORT_FEAT_POWER\n");
11380 +                       hprt0.d32 = dwc_otg_read_hprt0(core_if);
11381 +                       hprt0.b.prtpwr = 0;
11382 +                       dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32);
11383 +                       break;
11384 +               case USB_PORT_FEAT_INDICATOR:
11385 +                       DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
11386 +                                   "ClearPortFeature USB_PORT_FEAT_INDICATOR\n");
11387 +                       /* Port inidicator not supported */
11388 +                       break;
11389 +               case USB_PORT_FEAT_C_CONNECTION:
11390 +                       /* Clears drivers internal connect status change
11391 +                        * flag */
11392 +                       DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
11393 +                                   "ClearPortFeature USB_PORT_FEAT_C_CONNECTION\n");
11394 +                       dwc_otg_hcd->flags.b.port_connect_status_change = 0;
11395 +                       break;
11396 +               case USB_PORT_FEAT_C_RESET:
11397 +                       /* Clears the driver's internal Port Reset Change
11398 +                        * flag */
11399 +                       DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
11400 +                                   "ClearPortFeature USB_PORT_FEAT_C_RESET\n");
11401 +                       dwc_otg_hcd->flags.b.port_reset_change = 0;
11402 +                       break;
11403 +               case USB_PORT_FEAT_C_ENABLE:
11404 +                       /* Clears the driver's internal Port
11405 +                        * Enable/Disable Change flag */
11406 +                       DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
11407 +                                   "ClearPortFeature USB_PORT_FEAT_C_ENABLE\n");
11408 +                       dwc_otg_hcd->flags.b.port_enable_change = 0;
11409 +                       break;
11410 +               case USB_PORT_FEAT_C_SUSPEND:
11411 +                       /* Clears the driver's internal Port Suspend
11412 +                        * Change flag, which is set when resume signaling on
11413 +                        * the host port is complete */
11414 +                       DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
11415 +                                   "ClearPortFeature USB_PORT_FEAT_C_SUSPEND\n");
11416 +                       dwc_otg_hcd->flags.b.port_suspend_change = 0;
11417 +                       break;
11418 +               case USB_PORT_FEAT_C_OVER_CURRENT:
11419 +                       DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
11420 +                                   "ClearPortFeature USB_PORT_FEAT_C_OVER_CURRENT\n");
11421 +                       dwc_otg_hcd->flags.b.port_over_current_change = 0;
11422 +                       break;
11423 +               default:
11424 +                       retval = -EINVAL;
11425 +                       DWC_ERROR("DWC OTG HCD - "
11426 +                                 "ClearPortFeature request %xh "
11427 +                                 "unknown or unsupported\n", wValue);
11428 +               }
11429 +               break;
11430 +       case GetHubDescriptor:
11431 +               DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
11432 +                           "GetHubDescriptor\n");
11433 +               desc = (struct usb_hub_descriptor *)buf;
11434 +               desc->bDescLength = 9;
11435 +               desc->bDescriptorType = 0x29;
11436 +               desc->bNbrPorts = 1;
11437 +               desc->wHubCharacteristics = 0x08;
11438 +               desc->bPwrOn2PwrGood = 1;
11439 +               desc->bHubContrCurrent = 0;
11440 +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,39)
11441 +               desc->u.hs.DeviceRemovable[0] = 0;
11442 +               desc->u.hs.DeviceRemovable[1] = 0xff;
11443 +#endif
11444 +               break;
11445 +       case GetHubStatus:
11446 +               DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
11447 +                           "GetHubStatus\n");
11448 +               memset(buf, 0, 4);
11449 +               break;
11450 +       case GetPortStatus:
11451 +               DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
11452 +                           "GetPortStatus\n");
11453 +
11454 +               if (!wIndex || wIndex > 1)
11455 +                       goto error;
11456 +
11457 +               port_status = 0;
11458 +
11459 +               if (dwc_otg_hcd->flags.b.port_connect_status_change)
11460 +                       port_status |= (1 << USB_PORT_FEAT_C_CONNECTION);
11461 +
11462 +               if (dwc_otg_hcd->flags.b.port_enable_change)
11463 +                       port_status |= (1 << USB_PORT_FEAT_C_ENABLE);
11464 +
11465 +               if (dwc_otg_hcd->flags.b.port_suspend_change)
11466 +                       port_status |= (1 << USB_PORT_FEAT_C_SUSPEND);
11467 +
11468 +               if (dwc_otg_hcd->flags.b.port_reset_change)
11469 +                       port_status |= (1 << USB_PORT_FEAT_C_RESET);
11470 +
11471 +               if (dwc_otg_hcd->flags.b.port_over_current_change) {
11472 +                       DWC_ERROR("Device Not Supported\n");
11473 +                       port_status |= (1 << USB_PORT_FEAT_C_OVER_CURRENT);
11474 +               }
11475 +
11476 +               if (!dwc_otg_hcd->flags.b.port_connect_status) {
11477 +                       /*
11478 +                        * The port is disconnected, which means the core is
11479 +                        * either in device mode or it soon will be. Just
11480 +                        * return 0's for the remainder of the port status
11481 +                        * since the port register can't be read if the core
11482 +                        * is in device mode.
11483 +                        */
11484 +                       *((__le32 *) buf) = cpu_to_le32(port_status);
11485 +                       break;
11486 +               }
11487 +
11488 +               hprt0.d32 = dwc_read_reg32(core_if->host_if->hprt0);
11489 +               DWC_DEBUGPL(DBG_HCDV, "  HPRT0: 0x%08x\n", hprt0.d32);
11490 +
11491 +               if (hprt0.b.prtconnsts)
11492 +                       port_status |= (1 << USB_PORT_FEAT_CONNECTION);
11493 +
11494 +               if (hprt0.b.prtena)
11495 +                       port_status |= (1 << USB_PORT_FEAT_ENABLE);
11496 +
11497 +               if (hprt0.b.prtsusp)
11498 +                       port_status |= (1 << USB_PORT_FEAT_SUSPEND);
11499 +
11500 +               if (hprt0.b.prtovrcurract)
11501 +                       port_status |= (1 << USB_PORT_FEAT_OVER_CURRENT);
11502 +
11503 +               if (hprt0.b.prtrst)
11504 +                       port_status |= (1 << USB_PORT_FEAT_RESET);
11505 +
11506 +               if (hprt0.b.prtpwr)
11507 +                       port_status |= (1 << USB_PORT_FEAT_POWER);
11508 +
11509 +               if (hprt0.b.prtspd == DWC_HPRT0_PRTSPD_HIGH_SPEED)
11510 +                       port_status |= USB_PORT_STAT_HIGH_SPEED;
11511 +               else if (hprt0.b.prtspd == DWC_HPRT0_PRTSPD_LOW_SPEED)
11512 +                       port_status |= USB_PORT_STAT_LOW_SPEED;
11513 +
11514 +               if (hprt0.b.prttstctl)
11515 +                       port_status |= (1 << USB_PORT_FEAT_TEST);
11516 +
11517 +               /* USB_PORT_FEAT_INDICATOR unsupported always 0 */
11518 +
11519 +               *((__le32 *) buf) = cpu_to_le32(port_status);
11520 +
11521 +               break;
11522 +       case SetHubFeature:
11523 +               DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
11524 +                           "SetHubFeature\n");
11525 +               /* No HUB features supported */
11526 +               break;
11527 +       case SetPortFeature:
11528 +               if (wValue != USB_PORT_FEAT_TEST && (!wIndex || wIndex > 1))
11529 +                       goto error;
11530 +
11531 +               if (!dwc_otg_hcd->flags.b.port_connect_status) {
11532 +                       /*
11533 +                        * The port is disconnected, which means the core is
11534 +                        * either in device mode or it soon will be. Just
11535 +                        * return without doing anything since the port
11536 +                        * register can't be written if the core is in device
11537 +                        * mode.
11538 +                        */
11539 +                       break;
11540 +               }
11541 +
11542 +               switch (wValue) {
11543 +               case USB_PORT_FEAT_SUSPEND:
11544 +                       DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
11545 +                                   "SetPortFeature - USB_PORT_FEAT_SUSPEND\n");
11546 +                       if (hcd->self.otg_port == wIndex &&
11547 +                           hcd->self.b_hnp_enable) {
11548 +                               gotgctl_data_t  gotgctl = {.d32=0};
11549 +                               gotgctl.b.hstsethnpen = 1;
11550 +                               dwc_modify_reg32(&core_if->core_global_regs->gotgctl,
11551 +                                                 0, gotgctl.d32);
11552 +                               core_if->op_state = A_SUSPEND;
11553 +                       }
11554 +                       hprt0.d32 = dwc_otg_read_hprt0(core_if);
11555 +                       hprt0.b.prtsusp = 1;
11556 +                       dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32);
11557 +                       //DWC_PRINT("SUSPEND: HPRT0=%0x\n", hprt0.d32);
11558 +                       /* Suspend the Phy Clock */
11559 +                       {
11560 +                               pcgcctl_data_t pcgcctl = {.d32=0};
11561 +                               pcgcctl.b.stoppclk = 1;
11562 +                               dwc_write_reg32(core_if->pcgcctl, pcgcctl.d32);
11563 +                       }
11564 +
11565 +                       /* For HNP the bus must be suspended for at least 200ms. */
11566 +                       if (hcd->self.b_hnp_enable) {
11567 +                               mdelay(200);
11568 +                               //DWC_PRINT("SUSPEND: wait complete! (%d)\n", _hcd->state);
11569 +                       }
11570 +                       break;
11571 +               case USB_PORT_FEAT_POWER:
11572 +                       DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
11573 +                                   "SetPortFeature - USB_PORT_FEAT_POWER\n");
11574 +                       hprt0.d32 = dwc_otg_read_hprt0(core_if);
11575 +                       hprt0.b.prtpwr = 1;
11576 +                       dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32);
11577 +                       break;
11578 +               case USB_PORT_FEAT_RESET:
11579 +                       DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
11580 +                                   "SetPortFeature - USB_PORT_FEAT_RESET\n");
11581 +                       hprt0.d32 = dwc_otg_read_hprt0(core_if);
11582 +                       /* When B-Host the Port reset bit is set in
11583 +                        * the Start HCD Callback function, so that
11584 +                        * the reset is started within 1ms of the HNP
11585 +                        * success interrupt. */
11586 +                       if (!hcd->self.is_b_host) {
11587 +                               hprt0.b.prtrst = 1;
11588 +                               dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32);
11589 +                       }
11590 +                       /* Clear reset bit in 10ms (FS/LS) or 50ms (HS) */
11591 +                       MDELAY(60);
11592 +                       hprt0.b.prtrst = 0;
11593 +                       dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32);
11594 +                       break;
11595 +
11596 +#ifdef DWC_HS_ELECT_TST
11597 +               case USB_PORT_FEAT_TEST:
11598 +               {
11599 +                       uint32_t t;
11600 +                       gintmsk_data_t gintmsk;
11601 +
11602 +                       t = (wIndex >> 8); /* MSB wIndex USB */
11603 +                       DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
11604 +                                   "SetPortFeature - USB_PORT_FEAT_TEST %d\n", t);
11605 +                       warn("USB_PORT_FEAT_TEST %d\n", t);
11606 +                       if (t < 6) {
11607 +                               hprt0.d32 = dwc_otg_read_hprt0(core_if);
11608 +                               hprt0.b.prttstctl = t;
11609 +                               dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32);
11610 +                       } else {
11611 +                               /* Setup global vars with reg addresses (quick and
11612 +                                * dirty hack, should be cleaned up)
11613 +                                */
11614 +                               global_regs = core_if->core_global_regs;
11615 +                               hc_global_regs = core_if->host_if->host_global_regs;
11616 +                               hc_regs = (dwc_otg_hc_regs_t *)((char *)global_regs + 0x500);
11617 +                               data_fifo = (uint32_t *)((char *)global_regs + 0x1000);
11618 +
11619 +                               if (t == 6) { /* HS_HOST_PORT_SUSPEND_RESUME */
11620 +                                       /* Save current interrupt mask */
11621 +                                       gintmsk.d32 = dwc_read_reg32(&global_regs->gintmsk);
11622 +
11623 +                                       /* Disable all interrupts while we muck with
11624 +                                        * the hardware directly
11625 +                                        */
11626 +                                       dwc_write_reg32(&global_regs->gintmsk, 0);
11627 +
11628 +                                       /* 15 second delay per the test spec */
11629 +                                       mdelay(15000);
11630 +
11631 +                                       /* Drive suspend on the root port */
11632 +                                       hprt0.d32 = dwc_otg_read_hprt0(core_if);
11633 +                                       hprt0.b.prtsusp = 1;
11634 +                                       hprt0.b.prtres = 0;
11635 +                                       dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32);
11636 +
11637 +                                       /* 15 second delay per the test spec */
11638 +                                       mdelay(15000);
11639 +
11640 +                                       /* Drive resume on the root port */
11641 +                                       hprt0.d32 = dwc_otg_read_hprt0(core_if);
11642 +                                       hprt0.b.prtsusp = 0;
11643 +                                       hprt0.b.prtres = 1;
11644 +                                       dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32);
11645 +                                       mdelay(100);
11646 +
11647 +                                       /* Clear the resume bit */
11648 +                                       hprt0.b.prtres = 0;
11649 +                                       dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32);
11650 +
11651 +                                       /* Restore interrupts */
11652 +                                       dwc_write_reg32(&global_regs->gintmsk, gintmsk.d32);
11653 +                               } else if (t == 7) { /* SINGLE_STEP_GET_DEVICE_DESCRIPTOR setup */
11654 +                                       /* Save current interrupt mask */
11655 +                                       gintmsk.d32 = dwc_read_reg32(&global_regs->gintmsk);
11656 +
11657 +                                       /* Disable all interrupts while we muck with
11658 +                                        * the hardware directly
11659 +                                        */
11660 +                                       dwc_write_reg32(&global_regs->gintmsk, 0);
11661 +
11662 +                                       /* 15 second delay per the test spec */
11663 +                                       mdelay(15000);
11664 +
11665 +                                       /* Send the Setup packet */
11666 +                                       do_setup();
11667 +
11668 +                                       /* 15 second delay so nothing else happens for awhile */
11669 +                                       mdelay(15000);
11670 +
11671 +                                       /* Restore interrupts */
11672 +                                       dwc_write_reg32(&global_regs->gintmsk, gintmsk.d32);
11673 +                               } else if (t == 8) { /* SINGLE_STEP_GET_DEVICE_DESCRIPTOR execute */
11674 +                                       /* Save current interrupt mask */
11675 +                                       gintmsk.d32 = dwc_read_reg32(&global_regs->gintmsk);
11676 +
11677 +                                       /* Disable all interrupts while we muck with
11678 +                                        * the hardware directly
11679 +                                        */
11680 +                                       dwc_write_reg32(&global_regs->gintmsk, 0);
11681 +
11682 +                                       /* Send the Setup packet */
11683 +                                       do_setup();
11684 +
11685 +                                       /* 15 second delay so nothing else happens for awhile */
11686 +                                       mdelay(15000);
11687 +
11688 +                                       /* Send the In and Ack packets */
11689 +                                       do_in_ack();
11690 +
11691 +                                       /* 15 second delay so nothing else happens for awhile */
11692 +                                       mdelay(15000);
11693 +
11694 +                                       /* Restore interrupts */
11695 +                                       dwc_write_reg32(&global_regs->gintmsk, gintmsk.d32);
11696 +                               }
11697 +                       }
11698 +                       break;
11699 +               }
11700 +#endif /* DWC_HS_ELECT_TST */
11701 +
11702 +               case USB_PORT_FEAT_INDICATOR:
11703 +                       DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
11704 +                                   "SetPortFeature - USB_PORT_FEAT_INDICATOR\n");
11705 +                       /* Not supported */
11706 +                       break;
11707 +               default:
11708 +                       retval = -EINVAL;
11709 +                       DWC_ERROR("DWC OTG HCD - "
11710 +                                 "SetPortFeature request %xh "
11711 +                                 "unknown or unsupported\n", wValue);
11712 +                       break;
11713 +               }
11714 +               break;
11715 +       default:
11716 +       error:
11717 +               retval = -EINVAL;
11718 +               DWC_WARN("DWC OTG HCD - "
11719 +                        "Unknown hub control request type or invalid typeReq: %xh wIndex: %xh wValue: %xh\n",
11720 +                        typeReq, wIndex, wValue);
11721 +               break;
11722 +       }
11723 +
11724 +       return retval;
11725 +}
11726 +
11727 +/**
11728 + * Assigns transactions from a QTD to a free host channel and initializes the
11729 + * host channel to perform the transactions. The host channel is removed from
11730 + * the free list.
11731 + *
11732 + * @param hcd The HCD state structure.
11733 + * @param qh Transactions from the first QTD for this QH are selected and
11734 + * assigned to a free host channel.
11735 + */
11736 +static void assign_and_init_hc(dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh)
11737 +{
11738 +       dwc_hc_t        *hc;
11739 +       dwc_otg_qtd_t   *qtd;
11740 +       struct urb      *urb;
11741 +
11742 +       DWC_DEBUGPL(DBG_HCDV, "%s(%p,%p)\n", __func__, hcd, qh);
11743 +
11744 +       hc = list_entry(hcd->free_hc_list.next, dwc_hc_t, hc_list_entry);
11745 +
11746 +       /* Remove the host channel from the free list. */
11747 +       list_del_init(&hc->hc_list_entry);
11748 +
11749 +       qtd = list_entry(qh->qtd_list.next, dwc_otg_qtd_t, qtd_list_entry);
11750 +       urb = qtd->urb;
11751 +       qh->channel = hc;
11752 +       qh->qtd_in_process = qtd;
11753 +
11754 +       /*
11755 +        * Use usb_pipedevice to determine device address. This address is
11756 +        * 0 before the SET_ADDRESS command and the correct address afterward.
11757 +        */
11758 +       hc->dev_addr = usb_pipedevice(urb->pipe);
11759 +       hc->ep_num = usb_pipeendpoint(urb->pipe);
11760 +
11761 +       if (urb->dev->speed == USB_SPEED_LOW) {
11762 +               hc->speed = DWC_OTG_EP_SPEED_LOW;
11763 +       } else if (urb->dev->speed == USB_SPEED_FULL) {
11764 +               hc->speed = DWC_OTG_EP_SPEED_FULL;
11765 +       } else {
11766 +               hc->speed = DWC_OTG_EP_SPEED_HIGH;
11767 +       }
11768 +
11769 +       hc->max_packet = dwc_max_packet(qh->maxp);
11770 +
11771 +       hc->xfer_started = 0;
11772 +       hc->halt_status = DWC_OTG_HC_XFER_NO_HALT_STATUS;
11773 +       hc->error_state = (qtd->error_count > 0);
11774 +       hc->halt_on_queue = 0;
11775 +       hc->halt_pending = 0;
11776 +       hc->requests = 0;
11777 +
11778 +       /*
11779 +        * The following values may be modified in the transfer type section
11780 +        * below. The xfer_len value may be reduced when the transfer is
11781 +        * started to accommodate the max widths of the XferSize and PktCnt
11782 +        * fields in the HCTSIZn register.
11783 +        */
11784 +       hc->do_ping = qh->ping_state;
11785 +       hc->ep_is_in = (usb_pipein(urb->pipe) != 0);
11786 +       hc->data_pid_start = qh->data_toggle;
11787 +       hc->multi_count = 1;
11788 +
11789 +       if (hcd->core_if->dma_enable) {
11790 +               hc->xfer_buff = (uint8_t *)urb->transfer_dma + urb->actual_length;
11791 +       } else {
11792 +               hc->xfer_buff = (uint8_t *)urb->transfer_buffer + urb->actual_length;
11793 +       }
11794 +       hc->xfer_len = urb->transfer_buffer_length - urb->actual_length;
11795 +       hc->xfer_count = 0;
11796 +
11797 +       /*
11798 +        * Set the split attributes
11799 +        */
11800 +       hc->do_split = 0;
11801 +       if (qh->do_split) {
11802 +               hc->do_split = 1;
11803 +               hc->xact_pos = qtd->isoc_split_pos;
11804 +               hc->complete_split = qtd->complete_split;
11805 +               hc->hub_addr = urb->dev->tt->hub->devnum;
11806 +               hc->port_addr = urb->dev->ttport;
11807 +       }
11808 +
11809 +       switch (usb_pipetype(urb->pipe)) {
11810 +       case PIPE_CONTROL:
11811 +               hc->ep_type = DWC_OTG_EP_TYPE_CONTROL;
11812 +               switch (qtd->control_phase) {
11813 +               case DWC_OTG_CONTROL_SETUP:
11814 +                       DWC_DEBUGPL(DBG_HCDV, "  Control setup transaction\n");
11815 +                       hc->do_ping = 0;
11816 +                       hc->ep_is_in = 0;
11817 +                       hc->data_pid_start = DWC_OTG_HC_PID_SETUP;
11818 +                       if (hcd->core_if->dma_enable) {
11819 +                               hc->xfer_buff = (uint8_t *)urb->setup_dma;
11820 +                       } else {
11821 +                               hc->xfer_buff = (uint8_t *)urb->setup_packet;
11822 +                       }
11823 +                       hc->xfer_len = 8;
11824 +                       break;
11825 +               case DWC_OTG_CONTROL_DATA:
11826 +                       DWC_DEBUGPL(DBG_HCDV, "  Control data transaction\n");
11827 +                       hc->data_pid_start = qtd->data_toggle;
11828 +                       break;
11829 +               case DWC_OTG_CONTROL_STATUS:
11830 +                       /*
11831 +                        * Direction is opposite of data direction or IN if no
11832 +                        * data.
11833 +                        */
11834 +                       DWC_DEBUGPL(DBG_HCDV, "  Control status transaction\n");
11835 +                       if (urb->transfer_buffer_length == 0) {
11836 +                               hc->ep_is_in = 1;
11837 +                       } else {
11838 +                               hc->ep_is_in = (usb_pipein(urb->pipe) != USB_DIR_IN);
11839 +                       }
11840 +                       if (hc->ep_is_in) {
11841 +                               hc->do_ping = 0;
11842 +                       }
11843 +                       hc->data_pid_start = DWC_OTG_HC_PID_DATA1;
11844 +                       hc->xfer_len = 0;
11845 +                       if (hcd->core_if->dma_enable) {
11846 +                               hc->xfer_buff = (uint8_t *)hcd->status_buf_dma;
11847 +                       } else {
11848 +                               hc->xfer_buff = (uint8_t *)hcd->status_buf;
11849 +                       }
11850 +                       break;
11851 +               }
11852 +               break;
11853 +       case PIPE_BULK:
11854 +               hc->ep_type = DWC_OTG_EP_TYPE_BULK;
11855 +               break;
11856 +       case PIPE_INTERRUPT:
11857 +               hc->ep_type = DWC_OTG_EP_TYPE_INTR;
11858 +               break;
11859 +       case PIPE_ISOCHRONOUS:
11860 +               {
11861 +                       struct usb_iso_packet_descriptor *frame_desc;
11862 +                       frame_desc = &urb->iso_frame_desc[qtd->isoc_frame_index];
11863 +                       hc->ep_type = DWC_OTG_EP_TYPE_ISOC;
11864 +                       if (hcd->core_if->dma_enable) {
11865 +                               hc->xfer_buff = (uint8_t *)urb->transfer_dma;
11866 +                       } else {
11867 +                               hc->xfer_buff = (uint8_t *)urb->transfer_buffer;
11868 +                       }
11869 +                       hc->xfer_buff += frame_desc->offset + qtd->isoc_split_offset;
11870 +                       hc->xfer_len = frame_desc->length - qtd->isoc_split_offset;
11871 +
11872 +                       if (hc->xact_pos == DWC_HCSPLIT_XACTPOS_ALL) {
11873 +                               if (hc->xfer_len <= 188) {
11874 +                                       hc->xact_pos = DWC_HCSPLIT_XACTPOS_ALL;
11875 +                               }
11876 +                               else {
11877 +                                       hc->xact_pos = DWC_HCSPLIT_XACTPOS_BEGIN;
11878 +                               }
11879 +                       }
11880 +               }
11881 +               break;
11882 +       }
11883 +
11884 +       if (hc->ep_type == DWC_OTG_EP_TYPE_INTR ||
11885 +           hc->ep_type == DWC_OTG_EP_TYPE_ISOC) {
11886 +               /*
11887 +                * This value may be modified when the transfer is started to
11888 +                * reflect the actual transfer length.
11889 +                */
11890 +               hc->multi_count = dwc_hb_mult(qh->maxp);
11891 +       }
11892 +
11893 +       dwc_otg_hc_init(hcd->core_if, hc);
11894 +       hc->qh = qh;
11895 +}
11896 +
11897 +/**
11898 + * This function selects transactions from the HCD transfer schedule and
11899 + * assigns them to available host channels. It is called from HCD interrupt
11900 + * handler functions.
11901 + *
11902 + * @param hcd The HCD state structure.
11903 + *
11904 + * @return The types of new transactions that were assigned to host channels.
11905 + */
11906 +dwc_otg_transaction_type_e dwc_otg_hcd_select_transactions(dwc_otg_hcd_t *hcd)
11907 +{
11908 +       struct list_head                *qh_ptr;
11909 +       dwc_otg_qh_t                    *qh;
11910 +       int                             num_channels;
11911 +       dwc_otg_transaction_type_e      ret_val = DWC_OTG_TRANSACTION_NONE;
11912 +
11913 +#ifdef DEBUG_SOF
11914 +       DWC_DEBUGPL(DBG_HCD, "  Select Transactions\n");
11915 +#endif
11916 +
11917 +       /* Process entries in the periodic ready list. */
11918 +       qh_ptr = hcd->periodic_sched_ready.next;
11919 +       while (qh_ptr != &hcd->periodic_sched_ready &&
11920 +              !list_empty(&hcd->free_hc_list)) {
11921 +
11922 +               qh = list_entry(qh_ptr, dwc_otg_qh_t, qh_list_entry);
11923 +               assign_and_init_hc(hcd, qh);
11924 +
11925 +               /*
11926 +                * Move the QH from the periodic ready schedule to the
11927 +                * periodic assigned schedule.
11928 +                */
11929 +               qh_ptr = qh_ptr->next;
11930 +               list_move(&qh->qh_list_entry, &hcd->periodic_sched_assigned);
11931 +
11932 +               ret_val = DWC_OTG_TRANSACTION_PERIODIC;
11933 +       }
11934 +
11935 +       /*
11936 +        * Process entries in the inactive portion of the non-periodic
11937 +        * schedule. Some free host channels may not be used if they are
11938 +        * reserved for periodic transfers.
11939 +        */
11940 +       qh_ptr = hcd->non_periodic_sched_inactive.next;
11941 +       num_channels = hcd->core_if->core_params->host_channels;
11942 +       while (qh_ptr != &hcd->non_periodic_sched_inactive &&
11943 +              (hcd->non_periodic_channels <
11944 +               num_channels - hcd->periodic_channels) &&
11945 +              !list_empty(&hcd->free_hc_list)) {
11946 +
11947 +               qh = list_entry(qh_ptr, dwc_otg_qh_t, qh_list_entry);
11948 +               assign_and_init_hc(hcd, qh);
11949 +
11950 +               /*
11951 +                * Move the QH from the non-periodic inactive schedule to the
11952 +                * non-periodic active schedule.
11953 +                */
11954 +               qh_ptr = qh_ptr->next;
11955 +               list_move(&qh->qh_list_entry, &hcd->non_periodic_sched_active);
11956 +
11957 +               if (ret_val == DWC_OTG_TRANSACTION_NONE) {
11958 +                       ret_val = DWC_OTG_TRANSACTION_NON_PERIODIC;
11959 +               } else {
11960 +                       ret_val = DWC_OTG_TRANSACTION_ALL;
11961 +               }
11962 +
11963 +               hcd->non_periodic_channels++;
11964 +       }
11965 +
11966 +       return ret_val;
11967 +}
11968 +
11969 +/**
11970 + * Attempts to queue a single transaction request for a host channel
11971 + * associated with either a periodic or non-periodic transfer. This function
11972 + * assumes that there is space available in the appropriate request queue. For
11973 + * an OUT transfer or SETUP transaction in Slave mode, it checks whether space
11974 + * is available in the appropriate Tx FIFO.
11975 + *
11976 + * @param hcd The HCD state structure.
11977 + * @param hc Host channel descriptor associated with either a periodic or
11978 + * non-periodic transfer.
11979 + * @param fifo_dwords_avail Number of DWORDs available in the periodic Tx
11980 + * FIFO for periodic transfers or the non-periodic Tx FIFO for non-periodic
11981 + * transfers.
11982 + *
11983 + * @return 1 if a request is queued and more requests may be needed to
11984 + * complete the transfer, 0 if no more requests are required for this
11985 + * transfer, -1 if there is insufficient space in the Tx FIFO.
11986 + */
11987 +static int queue_transaction(dwc_otg_hcd_t *hcd,
11988 +                            dwc_hc_t *hc,
11989 +                            uint16_t fifo_dwords_avail)
11990 +{
11991 +       int retval;
11992 +
11993 +       if (hcd->core_if->dma_enable) {
11994 +               if (!hc->xfer_started) {
11995 +                       dwc_otg_hc_start_transfer(hcd->core_if, hc);
11996 +                       hc->qh->ping_state = 0;
11997 +               }
11998 +               retval = 0;
11999 +       } else if (hc->halt_pending) {
12000 +               /* Don't queue a request if the channel has been halted. */
12001 +               retval = 0;
12002 +       } else if (hc->halt_on_queue) {
12003 +               dwc_otg_hc_halt(hcd->core_if, hc, hc->halt_status);
12004 +               retval = 0;
12005 +       } else if (hc->do_ping) {
12006 +               if (!hc->xfer_started) {
12007 +                       dwc_otg_hc_start_transfer(hcd->core_if, hc);
12008 +               }
12009 +               retval = 0;
12010 +       } else if (!hc->ep_is_in ||
12011 +                  hc->data_pid_start == DWC_OTG_HC_PID_SETUP) {
12012 +               if ((fifo_dwords_avail * 4) >= hc->max_packet) {
12013 +                       if (!hc->xfer_started) {
12014 +                               dwc_otg_hc_start_transfer(hcd->core_if, hc);
12015 +                               retval = 1;
12016 +                       } else {
12017 +                               retval = dwc_otg_hc_continue_transfer(hcd->core_if, hc);
12018 +                       }
12019 +               } else {
12020 +                       retval = -1;
12021 +               }
12022 +       } else {
12023 +               if (!hc->xfer_started) {
12024 +                       dwc_otg_hc_start_transfer(hcd->core_if, hc);
12025 +                       retval = 1;
12026 +               } else {
12027 +                       retval = dwc_otg_hc_continue_transfer(hcd->core_if, hc);
12028 +               }
12029 +       }
12030 +
12031 +       return retval;
12032 +}
12033 +
12034 +/**
12035 + * Processes active non-periodic channels and queues transactions for these
12036 + * channels to the DWC_otg controller. After queueing transactions, the NP Tx
12037 + * FIFO Empty interrupt is enabled if there are more transactions to queue as
12038 + * NP Tx FIFO or request queue space becomes available. Otherwise, the NP Tx
12039 + * FIFO Empty interrupt is disabled.
12040 + */
12041 +static void process_non_periodic_channels(dwc_otg_hcd_t *hcd)
12042 +{
12043 +       gnptxsts_data_t         tx_status;
12044 +       struct list_head        *orig_qh_ptr;
12045 +       dwc_otg_qh_t            *qh;
12046 +       int                     status;
12047 +       int                     no_queue_space = 0;
12048 +       int                     no_fifo_space = 0;
12049 +       int                     more_to_do = 0;
12050 +
12051 +       dwc_otg_core_global_regs_t *global_regs = hcd->core_if->core_global_regs;
12052 +
12053 +       DWC_DEBUGPL(DBG_HCDV, "Queue non-periodic transactions\n");
12054 +#ifdef DEBUG
12055 +       tx_status.d32 = dwc_read_reg32(&global_regs->gnptxsts);
12056 +       DWC_DEBUGPL(DBG_HCDV, "  NP Tx Req Queue Space Avail (before queue): %d\n",
12057 +                   tx_status.b.nptxqspcavail);
12058 +       DWC_DEBUGPL(DBG_HCDV, "  NP Tx FIFO Space Avail (before queue): %d\n",
12059 +                   tx_status.b.nptxfspcavail);
12060 +#endif
12061 +       /*
12062 +        * Keep track of the starting point. Skip over the start-of-list
12063 +        * entry.
12064 +        */
12065 +       if (hcd->non_periodic_qh_ptr == &hcd->non_periodic_sched_active) {
12066 +               hcd->non_periodic_qh_ptr = hcd->non_periodic_qh_ptr->next;
12067 +       }
12068 +       orig_qh_ptr = hcd->non_periodic_qh_ptr;
12069 +
12070 +       /*
12071 +        * Process once through the active list or until no more space is
12072 +        * available in the request queue or the Tx FIFO.
12073 +        */
12074 +       do {
12075 +               tx_status.d32 = dwc_read_reg32(&global_regs->gnptxsts);
12076 +               if (!hcd->core_if->dma_enable && tx_status.b.nptxqspcavail == 0) {
12077 +                       no_queue_space = 1;
12078 +                       break;
12079 +               }
12080 +
12081 +               qh = list_entry(hcd->non_periodic_qh_ptr, dwc_otg_qh_t, qh_list_entry);
12082 +               status = queue_transaction(hcd, qh->channel, tx_status.b.nptxfspcavail);
12083 +
12084 +               if (status > 0) {
12085 +                       more_to_do = 1;
12086 +               } else if (status < 0) {
12087 +                       no_fifo_space = 1;
12088 +                       break;
12089 +               }
12090 +
12091 +               /* Advance to next QH, skipping start-of-list entry. */
12092 +               hcd->non_periodic_qh_ptr = hcd->non_periodic_qh_ptr->next;
12093 +               if (hcd->non_periodic_qh_ptr == &hcd->non_periodic_sched_active) {
12094 +                       hcd->non_periodic_qh_ptr = hcd->non_periodic_qh_ptr->next;
12095 +               }
12096 +
12097 +       } while (hcd->non_periodic_qh_ptr != orig_qh_ptr);
12098 +
12099 +       if (!hcd->core_if->dma_enable) {
12100 +               gintmsk_data_t intr_mask = {.d32 = 0};
12101 +               intr_mask.b.nptxfempty = 1;
12102 +
12103 +#ifdef DEBUG
12104 +               tx_status.d32 = dwc_read_reg32(&global_regs->gnptxsts);
12105 +               DWC_DEBUGPL(DBG_HCDV, "  NP Tx Req Queue Space Avail (after queue): %d\n",
12106 +                           tx_status.b.nptxqspcavail);
12107 +               DWC_DEBUGPL(DBG_HCDV, "  NP Tx FIFO Space Avail (after queue): %d\n",
12108 +                           tx_status.b.nptxfspcavail);
12109 +#endif
12110 +               if (more_to_do || no_queue_space || no_fifo_space) {
12111 +                       /*
12112 +                        * May need to queue more transactions as the request
12113 +                        * queue or Tx FIFO empties. Enable the non-periodic
12114 +                        * Tx FIFO empty interrupt. (Always use the half-empty
12115 +                        * level to ensure that new requests are loaded as
12116 +                        * soon as possible.)
12117 +                        */
12118 +                       dwc_modify_reg32(&global_regs->gintmsk, 0, intr_mask.d32);
12119 +               } else {
12120 +                       /*
12121 +                        * Disable the Tx FIFO empty interrupt since there are
12122 +                        * no more transactions that need to be queued right
12123 +                        * now. This function is called from interrupt
12124 +                        * handlers to queue more transactions as transfer
12125 +                        * states change.
12126 +                        */
12127 +                       dwc_modify_reg32(&global_regs->gintmsk, intr_mask.d32, 0);
12128 +               }
12129 +       }
12130 +}
12131 +
12132 +/**
12133 + * Processes periodic channels for the next frame and queues transactions for
12134 + * these channels to the DWC_otg controller. After queueing transactions, the
12135 + * Periodic Tx FIFO Empty interrupt is enabled if there are more transactions
12136 + * to queue as Periodic Tx FIFO or request queue space becomes available.
12137 + * Otherwise, the Periodic Tx FIFO Empty interrupt is disabled.
12138 + */
12139 +static void process_periodic_channels(dwc_otg_hcd_t *hcd)
12140 +{
12141 +       hptxsts_data_t          tx_status;
12142 +       struct list_head        *qh_ptr;
12143 +       dwc_otg_qh_t            *qh;
12144 +       int                     status;
12145 +       int                     no_queue_space = 0;
12146 +       int                     no_fifo_space = 0;
12147 +
12148 +       dwc_otg_host_global_regs_t *host_regs;
12149 +       host_regs = hcd->core_if->host_if->host_global_regs;
12150 +
12151 +       DWC_DEBUGPL(DBG_HCDV, "Queue periodic transactions\n");
12152 +#ifdef DEBUG
12153 +       tx_status.d32 = dwc_read_reg32(&host_regs->hptxsts);
12154 +       DWC_DEBUGPL(DBG_HCDV, "  P Tx Req Queue Space Avail (before queue): %d\n",
12155 +                   tx_status.b.ptxqspcavail);
12156 +       DWC_DEBUGPL(DBG_HCDV, "  P Tx FIFO Space Avail (before queue): %d\n",
12157 +                   tx_status.b.ptxfspcavail);
12158 +#endif
12159 +
12160 +       qh_ptr = hcd->periodic_sched_assigned.next;
12161 +       while (qh_ptr != &hcd->periodic_sched_assigned) {
12162 +               tx_status.d32 = dwc_read_reg32(&host_regs->hptxsts);
12163 +               if (tx_status.b.ptxqspcavail == 0) {
12164 +                       no_queue_space = 1;
12165 +                       break;
12166 +               }
12167 +
12168 +               qh = list_entry(qh_ptr, dwc_otg_qh_t, qh_list_entry);
12169 +
12170 +               /*
12171 +                * Set a flag if we're queuing high-bandwidth in slave mode.
12172 +                * The flag prevents any halts to get into the request queue in
12173 +                * the middle of multiple high-bandwidth packets getting queued.
12174 +                */
12175 +               if (!hcd->core_if->dma_enable &&
12176 +                   qh->channel->multi_count > 1)
12177 +               {
12178 +                       hcd->core_if->queuing_high_bandwidth = 1;
12179 +               }
12180 +
12181 +               status = queue_transaction(hcd, qh->channel, tx_status.b.ptxfspcavail);
12182 +               if (status < 0) {
12183 +                       no_fifo_space = 1;
12184 +                       break;
12185 +               }
12186 +
12187 +               /*
12188 +                * In Slave mode, stay on the current transfer until there is
12189 +                * nothing more to do or the high-bandwidth request count is
12190 +                * reached. In DMA mode, only need to queue one request. The
12191 +                * controller automatically handles multiple packets for
12192 +                * high-bandwidth transfers.
12193 +                */
12194 +               if (hcd->core_if->dma_enable || status == 0 ||
12195 +                   qh->channel->requests == qh->channel->multi_count) {
12196 +                       qh_ptr = qh_ptr->next;
12197 +                       /*
12198 +                        * Move the QH from the periodic assigned schedule to
12199 +                        * the periodic queued schedule.
12200 +                        */
12201 +                       list_move(&qh->qh_list_entry, &hcd->periodic_sched_queued);
12202 +
12203 +                       /* done queuing high bandwidth */
12204 +                       hcd->core_if->queuing_high_bandwidth = 0;
12205 +               }
12206 +       }
12207 +
12208 +       if (!hcd->core_if->dma_enable) {
12209 +               dwc_otg_core_global_regs_t *global_regs;
12210 +               gintmsk_data_t intr_mask = {.d32 = 0};
12211 +
12212 +               global_regs = hcd->core_if->core_global_regs;
12213 +               intr_mask.b.ptxfempty = 1;
12214 +#ifdef DEBUG
12215 +               tx_status.d32 = dwc_read_reg32(&host_regs->hptxsts);
12216 +               DWC_DEBUGPL(DBG_HCDV, "  P Tx Req Queue Space Avail (after queue): %d\n",
12217 +                           tx_status.b.ptxqspcavail);
12218 +               DWC_DEBUGPL(DBG_HCDV, "  P Tx FIFO Space Avail (after queue): %d\n",
12219 +                           tx_status.b.ptxfspcavail);
12220 +#endif
12221 +               if (!list_empty(&hcd->periodic_sched_assigned) ||
12222 +                   no_queue_space || no_fifo_space) {
12223 +                       /*
12224 +                        * May need to queue more transactions as the request
12225 +                        * queue or Tx FIFO empties. Enable the periodic Tx
12226 +                        * FIFO empty interrupt. (Always use the half-empty
12227 +                        * level to ensure that new requests are loaded as
12228 +                        * soon as possible.)
12229 +                        */
12230 +                       dwc_modify_reg32(&global_regs->gintmsk, 0, intr_mask.d32);
12231 +               } else {
12232 +                       /*
12233 +                        * Disable the Tx FIFO empty interrupt since there are
12234 +                        * no more transactions that need to be queued right
12235 +                        * now. This function is called from interrupt
12236 +                        * handlers to queue more transactions as transfer
12237 +                        * states change.
12238 +                        */
12239 +                       dwc_modify_reg32(&global_regs->gintmsk, intr_mask.d32, 0);
12240 +               }
12241 +       }
12242 +}
12243 +
12244 +/**
12245 + * This function processes the currently active host channels and queues
12246 + * transactions for these channels to the DWC_otg controller. It is called
12247 + * from HCD interrupt handler functions.
12248 + *
12249 + * @param hcd The HCD state structure.
12250 + * @param tr_type The type(s) of transactions to queue (non-periodic,
12251 + * periodic, or both).
12252 + */
12253 +void dwc_otg_hcd_queue_transactions(dwc_otg_hcd_t *hcd,
12254 +                                   dwc_otg_transaction_type_e tr_type)
12255 +{
12256 +#ifdef DEBUG_SOF
12257 +       DWC_DEBUGPL(DBG_HCD, "Queue Transactions\n");
12258 +#endif
12259 +       /* Process host channels associated with periodic transfers. */
12260 +       if ((tr_type == DWC_OTG_TRANSACTION_PERIODIC ||
12261 +            tr_type == DWC_OTG_TRANSACTION_ALL) &&
12262 +           !list_empty(&hcd->periodic_sched_assigned)) {
12263 +
12264 +               process_periodic_channels(hcd);
12265 +       }
12266 +
12267 +       /* Process host channels associated with non-periodic transfers. */
12268 +       if (tr_type == DWC_OTG_TRANSACTION_NON_PERIODIC ||
12269 +           tr_type == DWC_OTG_TRANSACTION_ALL) {
12270 +               if (!list_empty(&hcd->non_periodic_sched_active)) {
12271 +                       process_non_periodic_channels(hcd);
12272 +               } else {
12273 +                       /*
12274 +                        * Ensure NP Tx FIFO empty interrupt is disabled when
12275 +                        * there are no non-periodic transfers to process.
12276 +                        */
12277 +                       gintmsk_data_t gintmsk = {.d32 = 0};
12278 +                       gintmsk.b.nptxfempty = 1;
12279 +                       dwc_modify_reg32(&hcd->core_if->core_global_regs->gintmsk,
12280 +                                        gintmsk.d32, 0);
12281 +               }
12282 +       }
12283 +}
12284 +
12285 +/**
12286 + * Sets the final status of an URB and returns it to the device driver. Any
12287 + * required cleanup of the URB is performed.
12288 + */
12289 +void dwc_otg_hcd_complete_urb(dwc_otg_hcd_t *hcd, struct urb *urb, int status)
12290 +{
12291 +#ifdef DEBUG
12292 +       if (CHK_DEBUG_LEVEL(DBG_HCDV | DBG_HCD_URB)) {
12293 +               DWC_PRINT("%s: urb %p, device %d, ep %d %s, status=%d\n",
12294 +                         __func__, urb, usb_pipedevice(urb->pipe),
12295 +                         usb_pipeendpoint(urb->pipe),
12296 +                         usb_pipein(urb->pipe) ? "IN" : "OUT", status);
12297 +               if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) {
12298 +                       int i;
12299 +                       for (i = 0; i < urb->number_of_packets; i++) {
12300 +                               DWC_PRINT("  ISO Desc %d status: %d\n",
12301 +                                         i, urb->iso_frame_desc[i].status);
12302 +                       }
12303 +               }
12304 +       }
12305 +#endif
12306 +
12307 +       urb->status = status;
12308 +       urb->hcpriv = NULL;
12309 +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20)
12310 +       usb_hcd_giveback_urb(dwc_otg_hcd_to_hcd(hcd), urb, status);
12311 +#else
12312 +       usb_hcd_giveback_urb(dwc_otg_hcd_to_hcd(hcd), urb, NULL);
12313 +#endif
12314 +}
12315 +
12316 +/*
12317 + * Returns the Queue Head for an URB.
12318 + */
12319 +dwc_otg_qh_t *dwc_urb_to_qh(struct urb *urb)
12320 +{
12321 +       struct usb_host_endpoint *ep = dwc_urb_to_endpoint(urb);
12322 +       return (dwc_otg_qh_t *)ep->hcpriv;
12323 +}
12324 +
12325 +#ifdef DEBUG
12326 +void dwc_print_setup_data(uint8_t *setup)
12327 +{
12328 +       int i;
12329 +       if (CHK_DEBUG_LEVEL(DBG_HCD)){
12330 +               DWC_PRINT("Setup Data = MSB ");
12331 +               for (i = 7; i >= 0; i--) DWC_PRINT("%02x ", setup[i]);
12332 +               DWC_PRINT("\n");
12333 +               DWC_PRINT("  bmRequestType Tranfer = %s\n", (setup[0] & 0x80) ? "Device-to-Host" : "Host-to-Device");
12334 +               DWC_PRINT("  bmRequestType Type = ");
12335 +               switch ((setup[0] & 0x60) >> 5) {
12336 +               case 0: DWC_PRINT("Standard\n"); break;
12337 +               case 1: DWC_PRINT("Class\n"); break;
12338 +               case 2: DWC_PRINT("Vendor\n"); break;
12339 +               case 3: DWC_PRINT("Reserved\n"); break;
12340 +               }
12341 +               DWC_PRINT("  bmRequestType Recipient = ");
12342 +               switch (setup[0] & 0x1f) {
12343 +               case 0: DWC_PRINT("Device\n"); break;
12344 +               case 1: DWC_PRINT("Interface\n"); break;
12345 +               case 2: DWC_PRINT("Endpoint\n"); break;
12346 +               case 3: DWC_PRINT("Other\n"); break;
12347 +               default: DWC_PRINT("Reserved\n"); break;
12348 +               }
12349 +               DWC_PRINT("  bRequest = 0x%0x\n", setup[1]);
12350 +               DWC_PRINT("  wValue = 0x%0x\n", *((uint16_t *)&setup[2]));
12351 +               DWC_PRINT("  wIndex = 0x%0x\n", *((uint16_t *)&setup[4]));
12352 +               DWC_PRINT("  wLength = 0x%0x\n\n", *((uint16_t *)&setup[6]));
12353 +       }
12354 +}
12355 +#endif
12356 +
12357 +void dwc_otg_hcd_dump_frrem(dwc_otg_hcd_t *hcd) {
12358 +#if defined(DEBUG) && LINUX_VERSION_CODE < KERNEL_VERSION(2,6,20)
12359 +       DWC_PRINT("Frame remaining at SOF:\n");
12360 +       DWC_PRINT("  samples %u, accum %llu, avg %llu\n",
12361 +                 hcd->frrem_samples, hcd->frrem_accum,
12362 +                 (hcd->frrem_samples > 0) ?
12363 +                 hcd->frrem_accum/hcd->frrem_samples : 0);
12364 +
12365 +       DWC_PRINT("\n");
12366 +       DWC_PRINT("Frame remaining at start_transfer (uframe 7):\n");
12367 +       DWC_PRINT("  samples %u, accum %llu, avg %llu\n",
12368 +                 hcd->core_if->hfnum_7_samples, hcd->core_if->hfnum_7_frrem_accum,
12369 +                 (hcd->core_if->hfnum_7_samples > 0) ?
12370 +                 hcd->core_if->hfnum_7_frrem_accum/hcd->core_if->hfnum_7_samples : 0);
12371 +       DWC_PRINT("Frame remaining at start_transfer (uframe 0):\n");
12372 +       DWC_PRINT("  samples %u, accum %llu, avg %llu\n",
12373 +                 hcd->core_if->hfnum_0_samples, hcd->core_if->hfnum_0_frrem_accum,
12374 +                 (hcd->core_if->hfnum_0_samples > 0) ?
12375 +                 hcd->core_if->hfnum_0_frrem_accum/hcd->core_if->hfnum_0_samples : 0);
12376 +       DWC_PRINT("Frame remaining at start_transfer (uframe 1-6):\n");
12377 +       DWC_PRINT("  samples %u, accum %llu, avg %llu\n",
12378 +                 hcd->core_if->hfnum_other_samples, hcd->core_if->hfnum_other_frrem_accum,
12379 +                 (hcd->core_if->hfnum_other_samples > 0) ?
12380 +                 hcd->core_if->hfnum_other_frrem_accum/hcd->core_if->hfnum_other_samples : 0);
12381 +
12382 +       DWC_PRINT("\n");
12383 +       DWC_PRINT("Frame remaining at sample point A (uframe 7):\n");
12384 +       DWC_PRINT("  samples %u, accum %llu, avg %llu\n",
12385 +                 hcd->hfnum_7_samples_a, hcd->hfnum_7_frrem_accum_a,
12386 +                 (hcd->hfnum_7_samples_a > 0) ?
12387 +                 hcd->hfnum_7_frrem_accum_a/hcd->hfnum_7_samples_a : 0);
12388 +       DWC_PRINT("Frame remaining at sample point A (uframe 0):\n");
12389 +       DWC_PRINT("  samples %u, accum %llu, avg %llu\n",
12390 +                 hcd->hfnum_0_samples_a, hcd->hfnum_0_frrem_accum_a,
12391 +                 (hcd->hfnum_0_samples_a > 0) ?
12392 +                 hcd->hfnum_0_frrem_accum_a/hcd->hfnum_0_samples_a : 0);
12393 +       DWC_PRINT("Frame remaining at sample point A (uframe 1-6):\n");
12394 +       DWC_PRINT("  samples %u, accum %llu, avg %llu\n",
12395 +                 hcd->hfnum_other_samples_a, hcd->hfnum_other_frrem_accum_a,
12396 +                 (hcd->hfnum_other_samples_a > 0) ?
12397 +                 hcd->hfnum_other_frrem_accum_a/hcd->hfnum_other_samples_a : 0);
12398 +
12399 +       DWC_PRINT("\n");
12400 +       DWC_PRINT("Frame remaining at sample point B (uframe 7):\n");
12401 +       DWC_PRINT("  samples %u, accum %llu, avg %llu\n",
12402 +                 hcd->hfnum_7_samples_b, hcd->hfnum_7_frrem_accum_b,
12403 +                 (hcd->hfnum_7_samples_b > 0) ?
12404 +                 hcd->hfnum_7_frrem_accum_b/hcd->hfnum_7_samples_b : 0);
12405 +       DWC_PRINT("Frame remaining at sample point B (uframe 0):\n");
12406 +       DWC_PRINT("  samples %u, accum %llu, avg %llu\n",
12407 +                 hcd->hfnum_0_samples_b, hcd->hfnum_0_frrem_accum_b,
12408 +                 (hcd->hfnum_0_samples_b > 0) ?
12409 +                 hcd->hfnum_0_frrem_accum_b/hcd->hfnum_0_samples_b : 0);
12410 +       DWC_PRINT("Frame remaining at sample point B (uframe 1-6):\n");
12411 +       DWC_PRINT("  samples %u, accum %llu, avg %llu\n",
12412 +                 hcd->hfnum_other_samples_b, hcd->hfnum_other_frrem_accum_b,
12413 +                 (hcd->hfnum_other_samples_b > 0) ?
12414 +                 hcd->hfnum_other_frrem_accum_b/hcd->hfnum_other_samples_b : 0);
12415 +#endif
12416 +}
12417 +
12418 +void dwc_otg_hcd_dump_state(dwc_otg_hcd_t *hcd)
12419 +{
12420 +#ifdef DEBUG
12421 +       int num_channels;
12422 +       int i;
12423 +       gnptxsts_data_t np_tx_status;
12424 +       hptxsts_data_t p_tx_status;
12425 +
12426 +       num_channels = hcd->core_if->core_params->host_channels;
12427 +       DWC_PRINT("\n");
12428 +       DWC_PRINT("************************************************************\n");
12429 +       DWC_PRINT("HCD State:\n");
12430 +       DWC_PRINT("  Num channels: %d\n", num_channels);
12431 +       for (i = 0; i < num_channels; i++) {
12432 +               dwc_hc_t *hc = hcd->hc_ptr_array[i];
12433 +               DWC_PRINT("  Channel %d:\n", i);
12434 +               DWC_PRINT("    dev_addr: %d, ep_num: %d, ep_is_in: %d\n",
12435 +                         hc->dev_addr, hc->ep_num, hc->ep_is_in);
12436 +               DWC_PRINT("    speed: %d\n", hc->speed);
12437 +               DWC_PRINT("    ep_type: %d\n", hc->ep_type);
12438 +               DWC_PRINT("    max_packet: %d\n", hc->max_packet);
12439 +               DWC_PRINT("    data_pid_start: %d\n", hc->data_pid_start);
12440 +               DWC_PRINT("    multi_count: %d\n", hc->multi_count);
12441 +               DWC_PRINT("    xfer_started: %d\n", hc->xfer_started);
12442 +               DWC_PRINT("    xfer_buff: %p\n", hc->xfer_buff);
12443 +               DWC_PRINT("    xfer_len: %d\n", hc->xfer_len);
12444 +               DWC_PRINT("    xfer_count: %d\n", hc->xfer_count);
12445 +               DWC_PRINT("    halt_on_queue: %d\n", hc->halt_on_queue);
12446 +               DWC_PRINT("    halt_pending: %d\n", hc->halt_pending);
12447 +               DWC_PRINT("    halt_status: %d\n", hc->halt_status);
12448 +               DWC_PRINT("    do_split: %d\n", hc->do_split);
12449 +               DWC_PRINT("    complete_split: %d\n", hc->complete_split);
12450 +               DWC_PRINT("    hub_addr: %d\n", hc->hub_addr);
12451 +               DWC_PRINT("    port_addr: %d\n", hc->port_addr);
12452 +               DWC_PRINT("    xact_pos: %d\n", hc->xact_pos);
12453 +               DWC_PRINT("    requests: %d\n", hc->requests);
12454 +               DWC_PRINT("    qh: %p\n", hc->qh);
12455 +               if (hc->xfer_started) {
12456 +                       hfnum_data_t hfnum;
12457 +                       hcchar_data_t hcchar;
12458 +                       hctsiz_data_t hctsiz;
12459 +                       hcint_data_t hcint;
12460 +                       hcintmsk_data_t hcintmsk;
12461 +                       hfnum.d32 = dwc_read_reg32(&hcd->core_if->host_if->host_global_regs->hfnum);
12462 +                       hcchar.d32 = dwc_read_reg32(&hcd->core_if->host_if->hc_regs[i]->hcchar);
12463 +                       hctsiz.d32 = dwc_read_reg32(&hcd->core_if->host_if->hc_regs[i]->hctsiz);
12464 +                       hcint.d32 = dwc_read_reg32(&hcd->core_if->host_if->hc_regs[i]->hcint);
12465 +                       hcintmsk.d32 = dwc_read_reg32(&hcd->core_if->host_if->hc_regs[i]->hcintmsk);
12466 +                       DWC_PRINT("    hfnum: 0x%08x\n", hfnum.d32);
12467 +                       DWC_PRINT("    hcchar: 0x%08x\n", hcchar.d32);
12468 +                       DWC_PRINT("    hctsiz: 0x%08x\n", hctsiz.d32);
12469 +                       DWC_PRINT("    hcint: 0x%08x\n", hcint.d32);
12470 +                       DWC_PRINT("    hcintmsk: 0x%08x\n", hcintmsk.d32);
12471 +               }
12472 +               if (hc->xfer_started && hc->qh && hc->qh->qtd_in_process) {
12473 +                       dwc_otg_qtd_t *qtd;
12474 +                       struct urb *urb;
12475 +                       qtd = hc->qh->qtd_in_process;
12476 +                       urb = qtd->urb;
12477 +                       DWC_PRINT("    URB Info:\n");
12478 +                       DWC_PRINT("      qtd: %p, urb: %p\n", qtd, urb);
12479 +                       if (urb) {
12480 +                               DWC_PRINT("      Dev: %d, EP: %d %s\n",
12481 +                                         usb_pipedevice(urb->pipe), usb_pipeendpoint(urb->pipe),
12482 +                                         usb_pipein(urb->pipe) ? "IN" : "OUT");
12483 +                               DWC_PRINT("      Max packet size: %d\n",
12484 +                                         usb_maxpacket(urb->dev, urb->pipe, usb_pipeout(urb->pipe)));
12485 +                               DWC_PRINT("      transfer_buffer: %p\n", urb->transfer_buffer);
12486 +                               DWC_PRINT("      transfer_dma: %p\n", (void *)urb->transfer_dma);
12487 +                               DWC_PRINT("      transfer_buffer_length: %d\n", urb->transfer_buffer_length);
12488 +                               DWC_PRINT("      actual_length: %d\n", urb->actual_length);
12489 +                       }
12490 +               }
12491 +       }
12492 +       DWC_PRINT("  non_periodic_channels: %d\n", hcd->non_periodic_channels);
12493 +       DWC_PRINT("  periodic_channels: %d\n", hcd->periodic_channels);
12494 +       DWC_PRINT("  periodic_usecs: %d\n", hcd->periodic_usecs);
12495 +       np_tx_status.d32 = dwc_read_reg32(&hcd->core_if->core_global_regs->gnptxsts);
12496 +       DWC_PRINT("  NP Tx Req Queue Space Avail: %d\n", np_tx_status.b.nptxqspcavail);
12497 +       DWC_PRINT("  NP Tx FIFO Space Avail: %d\n", np_tx_status.b.nptxfspcavail);
12498 +       p_tx_status.d32 = dwc_read_reg32(&hcd->core_if->host_if->host_global_regs->hptxsts);
12499 +       DWC_PRINT("  P Tx Req Queue Space Avail: %d\n", p_tx_status.b.ptxqspcavail);
12500 +       DWC_PRINT("  P Tx FIFO Space Avail: %d\n", p_tx_status.b.ptxfspcavail);
12501 +       dwc_otg_hcd_dump_frrem(hcd);
12502 +       dwc_otg_dump_global_registers(hcd->core_if);
12503 +       dwc_otg_dump_host_registers(hcd->core_if);
12504 +       DWC_PRINT("************************************************************\n");
12505 +       DWC_PRINT("\n");
12506 +#endif
12507 +}
12508 +#endif /* DWC_DEVICE_ONLY */
12509 --- /dev/null
12510 +++ b/drivers/usb/dwc_otg/dwc_otg_hcd.h
12511 @@ -0,0 +1,668 @@
12512 +/* ==========================================================================
12513 + * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_hcd.h $
12514 + * $Revision: 1.3 $
12515 + * $Date: 2008-12-15 06:51:32 $
12516 + * $Change: 1064918 $
12517 + *
12518 + * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
12519 + * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
12520 + * otherwise expressly agreed to in writing between Synopsys and you.
12521 + *
12522 + * The Software IS NOT an item of Licensed Software or Licensed Product under
12523 + * any End User Software License Agreement or Agreement for Licensed Product
12524 + * with Synopsys or any supplement thereto. You are permitted to use and
12525 + * redistribute this Software in source and binary forms, with or without
12526 + * modification, provided that redistributions of source code must retain this
12527 + * notice. You may not view, use, disclose, copy or distribute this file or
12528 + * any information contained herein except pursuant to this license grant from
12529 + * Synopsys. If you do not agree with this notice, including the disclaimer
12530 + * below, then you are not authorized to use the Software.
12531 + *
12532 + * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
12533 + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
12534 + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
12535 + * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
12536 + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
12537 + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
12538 + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
12539 + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
12540 + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
12541 + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
12542 + * DAMAGE.
12543 + * ========================================================================== */
12544 +#ifndef DWC_DEVICE_ONLY
12545 +#ifndef __DWC_HCD_H__
12546 +#define __DWC_HCD_H__
12547 +
12548 +#include <linux/list.h>
12549 +#include <linux/usb.h>
12550 +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,35)
12551 +#include <linux/usb/hcd.h>
12552 +#else
12553 +#include <../drivers/usb/core/hcd.h>
12554 +#endif
12555 +
12556 +struct dwc_otg_device;
12557 +
12558 +#include "dwc_otg_cil.h"
12559 +
12560 +/**
12561 + * @file
12562 + *
12563 + * This file contains the structures, constants, and interfaces for
12564 + * the Host Contoller Driver (HCD).
12565 + *
12566 + * The Host Controller Driver (HCD) is responsible for translating requests
12567 + * from the USB Driver into the appropriate actions on the DWC_otg controller.
12568 + * It isolates the USBD from the specifics of the controller by providing an
12569 + * API to the USBD.
12570 + */
12571 +
12572 +/**
12573 + * Phases for control transfers.
12574 + */
12575 +typedef enum dwc_otg_control_phase {
12576 +       DWC_OTG_CONTROL_SETUP,
12577 +       DWC_OTG_CONTROL_DATA,
12578 +       DWC_OTG_CONTROL_STATUS
12579 +} dwc_otg_control_phase_e;
12580 +
12581 +/** Transaction types. */
12582 +typedef enum dwc_otg_transaction_type {
12583 +       DWC_OTG_TRANSACTION_NONE,
12584 +       DWC_OTG_TRANSACTION_PERIODIC,
12585 +       DWC_OTG_TRANSACTION_NON_PERIODIC,
12586 +       DWC_OTG_TRANSACTION_ALL
12587 +} dwc_otg_transaction_type_e;
12588 +
12589 +/**
12590 + * A Queue Transfer Descriptor (QTD) holds the state of a bulk, control,
12591 + * interrupt, or isochronous transfer. A single QTD is created for each URB
12592 + * (of one of these types) submitted to the HCD. The transfer associated with
12593 + * a QTD may require one or multiple transactions.
12594 + *
12595 + * A QTD is linked to a Queue Head, which is entered in either the
12596 + * non-periodic or periodic schedule for execution. When a QTD is chosen for
12597 + * execution, some or all of its transactions may be executed. After
12598 + * execution, the state of the QTD is updated. The QTD may be retired if all
12599 + * its transactions are complete or if an error occurred. Otherwise, it
12600 + * remains in the schedule so more transactions can be executed later.
12601 + */
12602 +typedef struct dwc_otg_qtd {
12603 +       /**
12604 +        * Determines the PID of the next data packet for the data phase of
12605 +        * control transfers. Ignored for other transfer types.<br>
12606 +        * One of the following values:
12607 +        *      - DWC_OTG_HC_PID_DATA0
12608 +        *      - DWC_OTG_HC_PID_DATA1
12609 +        */
12610 +       uint8_t                 data_toggle;
12611 +
12612 +       /** Current phase for control transfers (Setup, Data, or Status). */
12613 +       dwc_otg_control_phase_e control_phase;
12614 +
12615 +       /** Keep track of the current split type
12616 +        * for FS/LS endpoints on a HS Hub */
12617 +       uint8_t                 complete_split;
12618 +
12619 +       /** How many bytes transferred during SSPLIT OUT */
12620 +       uint32_t                ssplit_out_xfer_count;
12621 +
12622 +       /**
12623 +        * Holds the number of bus errors that have occurred for a transaction
12624 +        * within this transfer.
12625 +        */
12626 +       uint8_t                 error_count;
12627 +
12628 +       /**
12629 +        * Index of the next frame descriptor for an isochronous transfer. A
12630 +        * frame descriptor describes the buffer position and length of the
12631 +        * data to be transferred in the next scheduled (micro)frame of an
12632 +        * isochronous transfer. It also holds status for that transaction.
12633 +        * The frame index starts at 0.
12634 +        */
12635 +       int                     isoc_frame_index;
12636 +
12637 +       /** Position of the ISOC split on full/low speed */
12638 +       uint8_t                 isoc_split_pos;
12639 +
12640 +       /** Position of the ISOC split in the buffer for the current frame */
12641 +       uint16_t                isoc_split_offset;
12642 +
12643 +       /** URB for this transfer */
12644 +       struct urb              *urb;
12645 +
12646 +       /** This list of QTDs */
12647 +       struct list_head        qtd_list_entry;
12648 +
12649 +} dwc_otg_qtd_t;
12650 +
12651 +/**
12652 + * A Queue Head (QH) holds the static characteristics of an endpoint and
12653 + * maintains a list of transfers (QTDs) for that endpoint. A QH structure may
12654 + * be entered in either the non-periodic or periodic schedule.
12655 + */
12656 +typedef struct dwc_otg_qh {
12657 +       /**
12658 +        * Endpoint type.
12659 +        * One of the following values:
12660 +        *      - USB_ENDPOINT_XFER_CONTROL
12661 +        *      - USB_ENDPOINT_XFER_ISOC
12662 +        *      - USB_ENDPOINT_XFER_BULK
12663 +        *      - USB_ENDPOINT_XFER_INT
12664 +        */
12665 +       uint8_t                 ep_type;
12666 +       uint8_t                 ep_is_in;
12667 +
12668 +       /** wMaxPacketSize Field of Endpoint Descriptor. */
12669 +       uint16_t                maxp;
12670 +
12671 +       /**
12672 +        * Determines the PID of the next data packet for non-control
12673 +        * transfers. Ignored for control transfers.<br>
12674 +        * One of the following values:
12675 +        *      - DWC_OTG_HC_PID_DATA0
12676 +        *      - DWC_OTG_HC_PID_DATA1
12677 +        */
12678 +       uint8_t                 data_toggle;
12679 +
12680 +       /** Ping state if 1. */
12681 +       uint8_t                 ping_state;
12682 +
12683 +       /**
12684 +        * List of QTDs for this QH.
12685 +        */
12686 +       struct list_head        qtd_list;
12687 +
12688 +       /** Host channel currently processing transfers for this QH. */
12689 +       dwc_hc_t                *channel;
12690 +
12691 +       /** QTD currently assigned to a host channel for this QH. */
12692 +       dwc_otg_qtd_t           *qtd_in_process;
12693 +
12694 +       /** Full/low speed endpoint on high-speed hub requires split. */
12695 +       uint8_t                 do_split;
12696 +
12697 +       /** @name Periodic schedule information */
12698 +       /** @{ */
12699 +
12700 +       /** Bandwidth in microseconds per (micro)frame. */
12701 +       uint8_t                 usecs;
12702 +
12703 +       /** Interval between transfers in (micro)frames. */
12704 +       uint16_t                interval;
12705 +
12706 +       /**
12707 +        * (micro)frame to initialize a periodic transfer. The transfer
12708 +        * executes in the following (micro)frame.
12709 +        */
12710 +       uint16_t                sched_frame;
12711 +
12712 +       /** (micro)frame at which last start split was initialized. */
12713 +       uint16_t                start_split_frame;
12714 +
12715 +       /** @} */
12716 +
12717 +       /** Entry for QH in either the periodic or non-periodic schedule. */
12718 +       struct list_head        qh_list_entry;
12719 +
12720 +       /* For non-dword aligned buffer support */
12721 +       uint8_t                 *dw_align_buf;
12722 +       dma_addr_t              dw_align_buf_dma;
12723 +} dwc_otg_qh_t;
12724 +
12725 +/**
12726 + * This structure holds the state of the HCD, including the non-periodic and
12727 + * periodic schedules.
12728 + */
12729 +typedef struct dwc_otg_hcd {
12730 +       /** The DWC otg device pointer */
12731 +       struct dwc_otg_device   *otg_dev;
12732 +
12733 +       /** DWC OTG Core Interface Layer */
12734 +       dwc_otg_core_if_t       *core_if;
12735 +
12736 +       /** Internal DWC HCD Flags */
12737 +       volatile union dwc_otg_hcd_internal_flags {
12738 +               uint32_t d32;
12739 +               struct {
12740 +                       unsigned port_connect_status_change : 1;
12741 +                       unsigned port_connect_status : 1;
12742 +                       unsigned port_reset_change : 1;
12743 +                       unsigned port_enable_change : 1;
12744 +                       unsigned port_suspend_change : 1;
12745 +                       unsigned port_over_current_change : 1;
12746 +                       unsigned reserved : 27;
12747 +               } b;
12748 +       } flags;
12749 +
12750 +       /**
12751 +        * Inactive items in the non-periodic schedule. This is a list of
12752 +        * Queue Heads. Transfers associated with these Queue Heads are not
12753 +        * currently assigned to a host channel.
12754 +        */
12755 +       struct list_head        non_periodic_sched_inactive;
12756 +
12757 +       /**
12758 +        * Active items in the non-periodic schedule. This is a list of
12759 +        * Queue Heads. Transfers associated with these Queue Heads are
12760 +        * currently assigned to a host channel.
12761 +        */
12762 +       struct list_head        non_periodic_sched_active;
12763 +
12764 +       /**
12765 +        * Pointer to the next Queue Head to process in the active
12766 +        * non-periodic schedule.
12767 +        */
12768 +       struct list_head        *non_periodic_qh_ptr;
12769 +
12770 +       /**
12771 +        * Inactive items in the periodic schedule. This is a list of QHs for
12772 +        * periodic transfers that are _not_ scheduled for the next frame.
12773 +        * Each QH in the list has an interval counter that determines when it
12774 +        * needs to be scheduled for execution. This scheduling mechanism
12775 +        * allows only a simple calculation for periodic bandwidth used (i.e.
12776 +        * must assume that all periodic transfers may need to execute in the
12777 +        * same frame). However, it greatly simplifies scheduling and should
12778 +        * be sufficient for the vast majority of OTG hosts, which need to
12779 +        * connect to a small number of peripherals at one time.
12780 +        *
12781 +        * Items move from this list to periodic_sched_ready when the QH
12782 +        * interval counter is 0 at SOF.
12783 +        */
12784 +       struct list_head        periodic_sched_inactive;
12785 +
12786 +       /**
12787 +        * List of periodic QHs that are ready for execution in the next
12788 +        * frame, but have not yet been assigned to host channels.
12789 +        *
12790 +        * Items move from this list to periodic_sched_assigned as host
12791 +        * channels become available during the current frame.
12792 +        */
12793 +       struct list_head        periodic_sched_ready;
12794 +
12795 +       /**
12796 +        * List of periodic QHs to be executed in the next frame that are
12797 +        * assigned to host channels.
12798 +        *
12799 +        * Items move from this list to periodic_sched_queued as the
12800 +        * transactions for the QH are queued to the DWC_otg controller.
12801 +        */
12802 +       struct list_head        periodic_sched_assigned;
12803 +
12804 +       /**
12805 +        * List of periodic QHs that have been queued for execution.
12806 +        *
12807 +        * Items move from this list to either periodic_sched_inactive or
12808 +        * periodic_sched_ready when the channel associated with the transfer
12809 +        * is released. If the interval for the QH is 1, the item moves to
12810 +        * periodic_sched_ready because it must be rescheduled for the next
12811 +        * frame. Otherwise, the item moves to periodic_sched_inactive.
12812 +        */
12813 +       struct list_head        periodic_sched_queued;
12814 +
12815 +       /**
12816 +        * Total bandwidth claimed so far for periodic transfers. This value
12817 +        * is in microseconds per (micro)frame. The assumption is that all
12818 +        * periodic transfers may occur in the same (micro)frame.
12819 +        */
12820 +       uint16_t                periodic_usecs;
12821 +
12822 +       /**
12823 +        * Frame number read from the core at SOF. The value ranges from 0 to
12824 +        * DWC_HFNUM_MAX_FRNUM.
12825 +        */
12826 +       uint16_t                frame_number;
12827 +
12828 +       /**
12829 +        * Free host channels in the controller. This is a list of
12830 +        * dwc_hc_t items.
12831 +        */
12832 +       struct list_head        free_hc_list;
12833 +
12834 +       /**
12835 +        * Number of host channels assigned to periodic transfers. Currently
12836 +        * assuming that there is a dedicated host channel for each periodic
12837 +        * transaction and at least one host channel available for
12838 +        * non-periodic transactions.
12839 +        */
12840 +       int                     periodic_channels;
12841 +
12842 +       /**
12843 +        * Number of host channels assigned to non-periodic transfers.
12844 +        */
12845 +       int                     non_periodic_channels;
12846 +
12847 +       /**
12848 +        * Array of pointers to the host channel descriptors. Allows accessing
12849 +        * a host channel descriptor given the host channel number. This is
12850 +        * useful in interrupt handlers.
12851 +        */
12852 +       dwc_hc_t                *hc_ptr_array[MAX_EPS_CHANNELS];
12853 +
12854 +       /**
12855 +        * Buffer to use for any data received during the status phase of a
12856 +        * control transfer. Normally no data is transferred during the status
12857 +        * phase. This buffer is used as a bit bucket.
12858 +        */
12859 +       uint8_t                 *status_buf;
12860 +
12861 +       /**
12862 +        * DMA address for status_buf.
12863 +        */
12864 +       dma_addr_t              status_buf_dma;
12865 +#define DWC_OTG_HCD_STATUS_BUF_SIZE 64
12866 +
12867 +       /**
12868 +        * Structure to allow starting the HCD in a non-interrupt context
12869 +        * during an OTG role change.
12870 +        */
12871 +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,20)
12872 +       struct work_struct      start_work;
12873 +#else
12874 +       struct delayed_work     start_work;
12875 +#endif
12876 +
12877 +       /**
12878 +        * Connection timer. An OTG host must display a message if the device
12879 +        * does not connect. Started when the VBus power is turned on via
12880 +        * sysfs attribute "buspower".
12881 +        */
12882 +       struct timer_list       conn_timer;
12883 +
12884 +       /* Tasket to do a reset */
12885 +       struct tasklet_struct   *reset_tasklet;
12886 +
12887 +       /*  */
12888 +       spinlock_t lock;
12889 +
12890 +#ifdef DEBUG
12891 +       uint32_t                frrem_samples;
12892 +       uint64_t                frrem_accum;
12893 +
12894 +       uint32_t                hfnum_7_samples_a;
12895 +       uint64_t                hfnum_7_frrem_accum_a;
12896 +       uint32_t                hfnum_0_samples_a;
12897 +       uint64_t                hfnum_0_frrem_accum_a;
12898 +       uint32_t                hfnum_other_samples_a;
12899 +       uint64_t                hfnum_other_frrem_accum_a;
12900 +
12901 +       uint32_t                hfnum_7_samples_b;
12902 +       uint64_t                hfnum_7_frrem_accum_b;
12903 +       uint32_t                hfnum_0_samples_b;
12904 +       uint64_t                hfnum_0_frrem_accum_b;
12905 +       uint32_t                hfnum_other_samples_b;
12906 +       uint64_t                hfnum_other_frrem_accum_b;
12907 +#endif
12908 +} dwc_otg_hcd_t;
12909 +
12910 +/** Gets the dwc_otg_hcd from a struct usb_hcd */
12911 +static inline dwc_otg_hcd_t *hcd_to_dwc_otg_hcd(struct usb_hcd *hcd)
12912 +{
12913 +       return (dwc_otg_hcd_t *)(hcd->hcd_priv);
12914 +}
12915 +
12916 +/** Gets the struct usb_hcd that contains a dwc_otg_hcd_t. */
12917 +static inline struct usb_hcd *dwc_otg_hcd_to_hcd(dwc_otg_hcd_t *dwc_otg_hcd)
12918 +{
12919 +       return container_of((void *)dwc_otg_hcd, struct usb_hcd, hcd_priv);
12920 +}
12921 +
12922 +/** @name HCD Create/Destroy Functions */
12923 +/** @{ */
12924 +extern int dwc_otg_hcd_init(struct device *dev);
12925 +extern void dwc_otg_hcd_remove(struct device *dev);
12926 +/** @} */
12927 +
12928 +/** @name Linux HC Driver API Functions */
12929 +/** @{ */
12930 +
12931 +extern int dwc_otg_hcd_start(struct usb_hcd *hcd);
12932 +extern void dwc_otg_hcd_stop(struct usb_hcd *hcd);
12933 +extern int dwc_otg_hcd_get_frame_number(struct usb_hcd *hcd);
12934 +extern void dwc_otg_hcd_free(struct usb_hcd *hcd);
12935 +extern int dwc_otg_hcd_urb_enqueue(struct usb_hcd *hcd,
12936 +                                  struct urb *urb,
12937 +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,20)
12938 +                                  int mem_flags
12939 +#else
12940 +                                  gfp_t mem_flags
12941 +#endif
12942 +                                 );
12943 +extern int dwc_otg_hcd_urb_dequeue(struct usb_hcd *hcd,
12944 +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,20)
12945 +#endif
12946 +                                  struct urb *urb, int status);
12947 +extern void dwc_otg_hcd_endpoint_disable(struct usb_hcd *hcd,
12948 +                                        struct usb_host_endpoint *ep);
12949 +extern irqreturn_t dwc_otg_hcd_irq(struct usb_hcd *hcd
12950 +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,20)
12951 +                                  , struct pt_regs *regs
12952 +#endif
12953 +                                 );
12954 +extern int dwc_otg_hcd_hub_status_data(struct usb_hcd *hcd,
12955 +                                      char *buf);
12956 +extern int dwc_otg_hcd_hub_control(struct usb_hcd *hcd,
12957 +                                  u16 typeReq,
12958 +                                  u16 wValue,
12959 +                                  u16 wIndex,
12960 +                                  char *buf,
12961 +                                  u16 wLength);
12962 +
12963 +/** @} */
12964 +
12965 +/** @name Transaction Execution Functions */
12966 +/** @{ */
12967 +extern dwc_otg_transaction_type_e dwc_otg_hcd_select_transactions(dwc_otg_hcd_t *hcd);
12968 +extern void dwc_otg_hcd_queue_transactions(dwc_otg_hcd_t *hcd,
12969 +                                          dwc_otg_transaction_type_e tr_type);
12970 +extern void dwc_otg_hcd_complete_urb(dwc_otg_hcd_t *_hcd, struct urb *urb,
12971 +                                    int status);
12972 +/** @} */
12973 +
12974 +/** @name Interrupt Handler Functions */
12975 +/** @{ */
12976 +extern int32_t dwc_otg_hcd_handle_intr(dwc_otg_hcd_t *dwc_otg_hcd);
12977 +extern int32_t dwc_otg_hcd_handle_sof_intr(dwc_otg_hcd_t *dwc_otg_hcd);
12978 +extern int32_t dwc_otg_hcd_handle_rx_status_q_level_intr(dwc_otg_hcd_t *dwc_otg_hcd);
12979 +extern int32_t dwc_otg_hcd_handle_np_tx_fifo_empty_intr(dwc_otg_hcd_t *dwc_otg_hcd);
12980 +extern int32_t dwc_otg_hcd_handle_perio_tx_fifo_empty_intr(dwc_otg_hcd_t *dwc_otg_hcd);
12981 +extern int32_t dwc_otg_hcd_handle_incomplete_periodic_intr(dwc_otg_hcd_t *dwc_otg_hcd);
12982 +extern int32_t dwc_otg_hcd_handle_port_intr(dwc_otg_hcd_t *dwc_otg_hcd);
12983 +extern int32_t dwc_otg_hcd_handle_conn_id_status_change_intr(dwc_otg_hcd_t *dwc_otg_hcd);
12984 +extern int32_t dwc_otg_hcd_handle_disconnect_intr(dwc_otg_hcd_t *dwc_otg_hcd);
12985 +extern int32_t dwc_otg_hcd_handle_hc_intr(dwc_otg_hcd_t *dwc_otg_hcd);
12986 +extern int32_t dwc_otg_hcd_handle_hc_n_intr(dwc_otg_hcd_t *dwc_otg_hcd, uint32_t num);
12987 +extern int32_t dwc_otg_hcd_handle_session_req_intr(dwc_otg_hcd_t *dwc_otg_hcd);
12988 +extern int32_t dwc_otg_hcd_handle_wakeup_detected_intr(dwc_otg_hcd_t *dwc_otg_hcd);
12989 +/** @} */
12990 +
12991 +
12992 +/** @name Schedule Queue Functions */
12993 +/** @{ */
12994 +
12995 +/* Implemented in dwc_otg_hcd_queue.c */
12996 +extern dwc_otg_qh_t *dwc_otg_hcd_qh_create(dwc_otg_hcd_t *hcd, struct urb *urb);
12997 +extern void dwc_otg_hcd_qh_init(dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh, struct urb *urb);
12998 +extern void dwc_otg_hcd_qh_free(dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh);
12999 +extern int dwc_otg_hcd_qh_add(dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh);
13000 +extern void dwc_otg_hcd_qh_remove(dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh);
13001 +extern void dwc_otg_hcd_qh_deactivate(dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh, int sched_csplit);
13002 +
13003 +/** Remove and free a QH */
13004 +static inline void dwc_otg_hcd_qh_remove_and_free(dwc_otg_hcd_t *hcd,
13005 +                                                 dwc_otg_qh_t *qh)
13006 +{
13007 +       dwc_otg_hcd_qh_remove(hcd, qh);
13008 +       dwc_otg_hcd_qh_free(hcd, qh);
13009 +}
13010 +
13011 +/** Allocates memory for a QH structure.
13012 + * @return Returns the memory allocate or NULL on error. */
13013 +static inline dwc_otg_qh_t *dwc_otg_hcd_qh_alloc(void)
13014 +{
13015 +       return (dwc_otg_qh_t *) kmalloc(sizeof(dwc_otg_qh_t), GFP_KERNEL);
13016 +}
13017 +
13018 +extern dwc_otg_qtd_t *dwc_otg_hcd_qtd_create(struct urb *urb);
13019 +extern void dwc_otg_hcd_qtd_init(dwc_otg_qtd_t *qtd, struct urb *urb);
13020 +extern int dwc_otg_hcd_qtd_add(dwc_otg_qtd_t *qtd, dwc_otg_hcd_t *dwc_otg_hcd);
13021 +
13022 +/** Allocates memory for a QTD structure.
13023 + * @return Returns the memory allocate or NULL on error. */
13024 +static inline dwc_otg_qtd_t *dwc_otg_hcd_qtd_alloc(void)
13025 +{
13026 +       return (dwc_otg_qtd_t *) kmalloc(sizeof(dwc_otg_qtd_t), GFP_KERNEL);
13027 +}
13028 +
13029 +/** Frees the memory for a QTD structure.  QTD should already be removed from
13030 + * list.
13031 + * @param[in] qtd QTD to free.*/
13032 +static inline void dwc_otg_hcd_qtd_free(dwc_otg_qtd_t *qtd)
13033 +{
13034 +       kfree(qtd);
13035 +}
13036 +
13037 +/** Removes a QTD from list.
13038 + * @param[in] hcd HCD instance.
13039 + * @param[in] qtd QTD to remove from list. */
13040 +static inline void dwc_otg_hcd_qtd_remove(dwc_otg_hcd_t *hcd, dwc_otg_qtd_t *qtd)
13041 +{
13042 +       unsigned long flags;
13043 +       SPIN_LOCK_IRQSAVE(&hcd->lock, flags);
13044 +       list_del(&qtd->qtd_list_entry);
13045 +       SPIN_UNLOCK_IRQRESTORE(&hcd->lock, flags);
13046 +}
13047 +
13048 +/** Remove and free a QTD */
13049 +static inline void dwc_otg_hcd_qtd_remove_and_free(dwc_otg_hcd_t *hcd, dwc_otg_qtd_t *qtd)
13050 +{
13051 +       dwc_otg_hcd_qtd_remove(hcd, qtd);
13052 +       dwc_otg_hcd_qtd_free(qtd);
13053 +}
13054 +
13055 +/** @} */
13056 +
13057 +
13058 +/** @name Internal Functions */
13059 +/** @{ */
13060 +dwc_otg_qh_t *dwc_urb_to_qh(struct urb *urb);
13061 +void dwc_otg_hcd_dump_frrem(dwc_otg_hcd_t *hcd);
13062 +void dwc_otg_hcd_dump_state(dwc_otg_hcd_t *hcd);
13063 +/** @} */
13064 +
13065 +/** Gets the usb_host_endpoint associated with an URB. */
13066 +static inline struct usb_host_endpoint *dwc_urb_to_endpoint(struct urb *urb)
13067 +{
13068 +       struct usb_device *dev = urb->dev;
13069 +       int ep_num = usb_pipeendpoint(urb->pipe);
13070 +
13071 +       if (usb_pipein(urb->pipe))
13072 +               return dev->ep_in[ep_num];
13073 +       else
13074 +               return dev->ep_out[ep_num];
13075 +}
13076 +
13077 +/**
13078 + * Gets the endpoint number from a _bEndpointAddress argument. The endpoint is
13079 + * qualified with its direction (possible 32 endpoints per device).
13080 + */
13081 +#define dwc_ep_addr_to_endpoint(_bEndpointAddress_) ((_bEndpointAddress_ & USB_ENDPOINT_NUMBER_MASK) | \
13082 +                                                    ((_bEndpointAddress_ & USB_DIR_IN) != 0) << 4)
13083 +
13084 +/** Gets the QH that contains the list_head */
13085 +#define dwc_list_to_qh(_list_head_ptr_) container_of(_list_head_ptr_, dwc_otg_qh_t, qh_list_entry)
13086 +
13087 +/** Gets the QTD that contains the list_head */
13088 +#define dwc_list_to_qtd(_list_head_ptr_) container_of(_list_head_ptr_, dwc_otg_qtd_t, qtd_list_entry)
13089 +
13090 +/** Check if QH is non-periodic  */
13091 +#define dwc_qh_is_non_per(_qh_ptr_) ((_qh_ptr_->ep_type == USB_ENDPOINT_XFER_BULK) || \
13092 +                                    (_qh_ptr_->ep_type == USB_ENDPOINT_XFER_CONTROL))
13093 +
13094 +/** High bandwidth multiplier as encoded in highspeed endpoint descriptors */
13095 +#define dwc_hb_mult(wMaxPacketSize) (1 + (((wMaxPacketSize) >> 11) & 0x03))
13096 +
13097 +/** Packet size for any kind of endpoint descriptor */
13098 +#define dwc_max_packet(wMaxPacketSize) ((wMaxPacketSize) & 0x07ff)
13099 +
13100 +/**
13101 + * Returns true if _frame1 is less than or equal to _frame2. The comparison is
13102 + * done modulo DWC_HFNUM_MAX_FRNUM. This accounts for the rollover of the
13103 + * frame number when the max frame number is reached.
13104 + */
13105 +static inline int dwc_frame_num_le(uint16_t frame1, uint16_t frame2)
13106 +{
13107 +       return ((frame2 - frame1) & DWC_HFNUM_MAX_FRNUM) <=
13108 +               (DWC_HFNUM_MAX_FRNUM >> 1);
13109 +}
13110 +
13111 +/**
13112 + * Returns true if _frame1 is greater than _frame2. The comparison is done
13113 + * modulo DWC_HFNUM_MAX_FRNUM. This accounts for the rollover of the frame
13114 + * number when the max frame number is reached.
13115 + */
13116 +static inline int dwc_frame_num_gt(uint16_t frame1, uint16_t frame2)
13117 +{
13118 +       return (frame1 != frame2) &&
13119 +               (((frame1 - frame2) & DWC_HFNUM_MAX_FRNUM) <
13120 +                (DWC_HFNUM_MAX_FRNUM >> 1));
13121 +}
13122 +
13123 +/**
13124 + * Increments _frame by the amount specified by _inc. The addition is done
13125 + * modulo DWC_HFNUM_MAX_FRNUM. Returns the incremented value.
13126 + */
13127 +static inline uint16_t dwc_frame_num_inc(uint16_t frame, uint16_t inc)
13128 +{
13129 +       return (frame + inc) & DWC_HFNUM_MAX_FRNUM;
13130 +}
13131 +
13132 +static inline uint16_t dwc_full_frame_num(uint16_t frame)
13133 +{
13134 +       return (frame & DWC_HFNUM_MAX_FRNUM) >> 3;
13135 +}
13136 +
13137 +static inline uint16_t dwc_micro_frame_num(uint16_t frame)
13138 +{
13139 +       return frame & 0x7;
13140 +}
13141 +
13142 +#ifdef DEBUG
13143 +/**
13144 + * Macro to sample the remaining PHY clocks left in the current frame. This
13145 + * may be used during debugging to determine the average time it takes to
13146 + * execute sections of code. There are two possible sample points, "a" and
13147 + * "b", so the _letter argument must be one of these values.
13148 + *
13149 + * To dump the average sample times, read the "hcd_frrem" sysfs attribute. For
13150 + * example, "cat /sys/devices/lm0/hcd_frrem".
13151 + */
13152 +#define dwc_sample_frrem(_hcd, _qh, _letter) \
13153 +{ \
13154 +       hfnum_data_t hfnum; \
13155 +       dwc_otg_qtd_t *qtd; \
13156 +       qtd = list_entry(_qh->qtd_list.next, dwc_otg_qtd_t, qtd_list_entry); \
13157 +       if (usb_pipeint(qtd->urb->pipe) && _qh->start_split_frame != 0 && !qtd->complete_split) { \
13158 +               hfnum.d32 = dwc_read_reg32(&_hcd->core_if->host_if->host_global_regs->hfnum); \
13159 +               switch (hfnum.b.frnum & 0x7) { \
13160 +               case 7: \
13161 +                       _hcd->hfnum_7_samples_##_letter++; \
13162 +                       _hcd->hfnum_7_frrem_accum_##_letter += hfnum.b.frrem; \
13163 +                       break; \
13164 +               case 0: \
13165 +                       _hcd->hfnum_0_samples_##_letter++; \
13166 +                       _hcd->hfnum_0_frrem_accum_##_letter += hfnum.b.frrem; \
13167 +                       break; \
13168 +               default: \
13169 +                       _hcd->hfnum_other_samples_##_letter++; \
13170 +                       _hcd->hfnum_other_frrem_accum_##_letter += hfnum.b.frrem; \
13171 +                       break; \
13172 +               } \
13173 +       } \
13174 +}
13175 +#else
13176 +#define dwc_sample_frrem(_hcd, _qh, _letter)
13177 +#endif
13178 +#endif
13179 +#endif /* DWC_DEVICE_ONLY */
13180 --- /dev/null
13181 +++ b/drivers/usb/dwc_otg/dwc_otg_hcd_intr.c
13182 @@ -0,0 +1,1873 @@
13183 +/* ==========================================================================
13184 + * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_hcd_intr.c $
13185 + * $Revision: 1.6.2.1 $
13186 + * $Date: 2009-04-22 03:48:22 $
13187 + * $Change: 1117667 $
13188 + *
13189 + * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
13190 + * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
13191 + * otherwise expressly agreed to in writing between Synopsys and you.
13192 + *
13193 + * The Software IS NOT an item of Licensed Software or Licensed Product under
13194 + * any End User Software License Agreement or Agreement for Licensed Product
13195 + * with Synopsys or any supplement thereto. You are permitted to use and
13196 + * redistribute this Software in source and binary forms, with or without
13197 + * modification, provided that redistributions of source code must retain this
13198 + * notice. You may not view, use, disclose, copy or distribute this file or
13199 + * any information contained herein except pursuant to this license grant from
13200 + * Synopsys. If you do not agree with this notice, including the disclaimer
13201 + * below, then you are not authorized to use the Software.
13202 + *
13203 + * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
13204 + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
13205 + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
13206 + * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
13207 + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
13208 + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
13209 + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
13210 + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
13211 + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
13212 + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
13213 + * DAMAGE.
13214 + * ========================================================================== */
13215 +#ifndef DWC_DEVICE_ONLY
13216 +
13217 +#include <linux/version.h>
13218 +
13219 +#include "dwc_otg_driver.h"
13220 +#include "dwc_otg_hcd.h"
13221 +#include "dwc_otg_regs.h"
13222 +
13223 +/** @file
13224 + * This file contains the implementation of the HCD Interrupt handlers.
13225 + */
13226 +
13227 +/** This function handles interrupts for the HCD. */
13228 +int32_t dwc_otg_hcd_handle_intr(dwc_otg_hcd_t *dwc_otg_hcd)
13229 +{
13230 +       int retval = 0;
13231 +
13232 +       dwc_otg_core_if_t *core_if = dwc_otg_hcd->core_if;
13233 +       gintsts_data_t gintsts;
13234 +#ifdef DEBUG
13235 +       dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs;
13236 +#endif
13237 +
13238 +       /* Check if HOST Mode */
13239 +       if (dwc_otg_is_host_mode(core_if)) {
13240 +               gintsts.d32 = dwc_otg_read_core_intr(core_if);
13241 +               if (!gintsts.d32) {
13242 +                       return 0;
13243 +               }
13244 +
13245 +#ifdef DEBUG
13246 +               /* Don't print debug message in the interrupt handler on SOF */
13247 +# ifndef DEBUG_SOF
13248 +               if (gintsts.d32 != DWC_SOF_INTR_MASK)
13249 +# endif
13250 +                       DWC_DEBUGPL(DBG_HCD, "\n");
13251 +#endif
13252 +
13253 +#ifdef DEBUG
13254 +# ifndef DEBUG_SOF
13255 +               if (gintsts.d32 != DWC_SOF_INTR_MASK)
13256 +# endif
13257 +                       DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD Interrupt Detected gintsts&gintmsk=0x%08x\n", gintsts.d32);
13258 +#endif
13259 +               if (gintsts.b.usbreset) {
13260 +                       DWC_PRINT("Usb Reset In Host Mode\n");
13261 +               }
13262 +
13263 +
13264 +               if (gintsts.b.sofintr) {
13265 +                       retval |= dwc_otg_hcd_handle_sof_intr(dwc_otg_hcd);
13266 +               }
13267 +               if (gintsts.b.rxstsqlvl) {
13268 +                       retval |= dwc_otg_hcd_handle_rx_status_q_level_intr(dwc_otg_hcd);
13269 +               }
13270 +               if (gintsts.b.nptxfempty) {
13271 +                       retval |= dwc_otg_hcd_handle_np_tx_fifo_empty_intr(dwc_otg_hcd);
13272 +               }
13273 +               if (gintsts.b.i2cintr) {
13274 +                       /** @todo Implement i2cintr handler. */
13275 +               }
13276 +               if (gintsts.b.portintr) {
13277 +                       retval |= dwc_otg_hcd_handle_port_intr(dwc_otg_hcd);
13278 +               }
13279 +               if (gintsts.b.hcintr) {
13280 +                       retval |= dwc_otg_hcd_handle_hc_intr(dwc_otg_hcd);
13281 +               }
13282 +               if (gintsts.b.ptxfempty) {
13283 +                       retval |= dwc_otg_hcd_handle_perio_tx_fifo_empty_intr(dwc_otg_hcd);
13284 +               }
13285 +#ifdef DEBUG
13286 +# ifndef DEBUG_SOF
13287 +               if (gintsts.d32 != DWC_SOF_INTR_MASK)
13288 +# endif
13289 +               {
13290 +                       DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD Finished Servicing Interrupts\n");
13291 +                       DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD gintsts=0x%08x\n",
13292 +                                   dwc_read_reg32(&global_regs->gintsts));
13293 +                       DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD gintmsk=0x%08x\n",
13294 +                                   dwc_read_reg32(&global_regs->gintmsk));
13295 +               }
13296 +#endif
13297 +
13298 +#ifdef DEBUG
13299 +# ifndef DEBUG_SOF
13300 +       if (gintsts.d32 != DWC_SOF_INTR_MASK)
13301 +# endif
13302 +               DWC_DEBUGPL(DBG_HCD, "\n");
13303 +#endif
13304 +
13305 +       }
13306 +
13307 +       S3C2410X_CLEAR_EINTPEND();
13308 +
13309 +       return retval;
13310 +}
13311 +
13312 +#ifdef DWC_TRACK_MISSED_SOFS
13313 +#warning Compiling code to track missed SOFs
13314 +#define FRAME_NUM_ARRAY_SIZE 1000
13315 +/**
13316 + * This function is for debug only.
13317 + */
13318 +static inline void track_missed_sofs(uint16_t curr_frame_number)
13319 +{
13320 +       static uint16_t         frame_num_array[FRAME_NUM_ARRAY_SIZE];
13321 +       static uint16_t         last_frame_num_array[FRAME_NUM_ARRAY_SIZE];
13322 +       static int              frame_num_idx = 0;
13323 +       static uint16_t         last_frame_num = DWC_HFNUM_MAX_FRNUM;
13324 +       static int              dumped_frame_num_array = 0;
13325 +
13326 +       if (frame_num_idx < FRAME_NUM_ARRAY_SIZE) {
13327 +               if (((last_frame_num + 1) & DWC_HFNUM_MAX_FRNUM) != curr_frame_number) {
13328 +                       frame_num_array[frame_num_idx] = curr_frame_number;
13329 +                       last_frame_num_array[frame_num_idx++] = last_frame_num;
13330 +               }
13331 +       } else if (!dumped_frame_num_array) {
13332 +               int i;
13333 +               printk(KERN_EMERG USB_DWC "Frame     Last Frame\n");
13334 +               printk(KERN_EMERG USB_DWC "-----     ----------\n");
13335 +               for (i = 0; i < FRAME_NUM_ARRAY_SIZE; i++) {
13336 +                       printk(KERN_EMERG USB_DWC "0x%04x    0x%04x\n",
13337 +                              frame_num_array[i], last_frame_num_array[i]);
13338 +               }
13339 +               dumped_frame_num_array = 1;
13340 +       }
13341 +       last_frame_num = curr_frame_number;
13342 +}
13343 +#endif
13344 +
13345 +/**
13346 + * Handles the start-of-frame interrupt in host mode. Non-periodic
13347 + * transactions may be queued to the DWC_otg controller for the current
13348 + * (micro)frame. Periodic transactions may be queued to the controller for the
13349 + * next (micro)frame.
13350 + */
13351 +int32_t dwc_otg_hcd_handle_sof_intr(dwc_otg_hcd_t *hcd)
13352 +{
13353 +       hfnum_data_t            hfnum;
13354 +       struct list_head        *qh_entry;
13355 +       dwc_otg_qh_t            *qh;
13356 +       dwc_otg_transaction_type_e tr_type;
13357 +       gintsts_data_t gintsts = {.d32 = 0};
13358 +
13359 +       hfnum.d32 = dwc_read_reg32(&hcd->core_if->host_if->host_global_regs->hfnum);
13360 +
13361 +#ifdef DEBUG_SOF
13362 +       DWC_DEBUGPL(DBG_HCD, "--Start of Frame Interrupt--\n");
13363 +#endif
13364 +       hcd->frame_number = hfnum.b.frnum;
13365 +
13366 +#ifdef DEBUG
13367 +       hcd->frrem_accum += hfnum.b.frrem;
13368 +       hcd->frrem_samples++;
13369 +#endif
13370 +
13371 +#ifdef DWC_TRACK_MISSED_SOFS
13372 +       track_missed_sofs(hcd->frame_number);
13373 +#endif
13374 +
13375 +       /* Determine whether any periodic QHs should be executed. */
13376 +       qh_entry = hcd->periodic_sched_inactive.next;
13377 +       while (qh_entry != &hcd->periodic_sched_inactive) {
13378 +               qh = list_entry(qh_entry, dwc_otg_qh_t, qh_list_entry);
13379 +               qh_entry = qh_entry->next;
13380 +               if (dwc_frame_num_le(qh->sched_frame, hcd->frame_number)) {
13381 +                       /*
13382 +                        * Move QH to the ready list to be executed next
13383 +                        * (micro)frame.
13384 +                        */
13385 +                       list_move(&qh->qh_list_entry, &hcd->periodic_sched_ready);
13386 +               }
13387 +       }
13388 +
13389 +       tr_type = dwc_otg_hcd_select_transactions(hcd);
13390 +       if (tr_type != DWC_OTG_TRANSACTION_NONE) {
13391 +               dwc_otg_hcd_queue_transactions(hcd, tr_type);
13392 +       }
13393 +
13394 +       /* Clear interrupt */
13395 +       gintsts.b.sofintr = 1;
13396 +       dwc_write_reg32(&hcd->core_if->core_global_regs->gintsts, gintsts.d32);
13397 +
13398 +       return 1;
13399 +}
13400 +
13401 +/** Handles the Rx Status Queue Level Interrupt, which indicates that there is at
13402 + * least one packet in the Rx FIFO.  The packets are moved from the FIFO to
13403 + * memory if the DWC_otg controller is operating in Slave mode. */
13404 +int32_t dwc_otg_hcd_handle_rx_status_q_level_intr(dwc_otg_hcd_t *dwc_otg_hcd)
13405 +{
13406 +       host_grxsts_data_t grxsts;
13407 +       dwc_hc_t *hc = NULL;
13408 +
13409 +       DWC_DEBUGPL(DBG_HCD, "--RxStsQ Level Interrupt--\n");
13410 +
13411 +       grxsts.d32 = dwc_read_reg32(&dwc_otg_hcd->core_if->core_global_regs->grxstsp);
13412 +
13413 +       hc = dwc_otg_hcd->hc_ptr_array[grxsts.b.chnum];
13414 +
13415 +       /* Packet Status */
13416 +       DWC_DEBUGPL(DBG_HCDV, "    Ch num = %d\n", grxsts.b.chnum);
13417 +       DWC_DEBUGPL(DBG_HCDV, "    Count = %d\n", grxsts.b.bcnt);
13418 +       DWC_DEBUGPL(DBG_HCDV, "    DPID = %d, hc.dpid = %d\n", grxsts.b.dpid, hc->data_pid_start);
13419 +       DWC_DEBUGPL(DBG_HCDV, "    PStatus = %d\n", grxsts.b.pktsts);
13420 +
13421 +       switch (grxsts.b.pktsts) {
13422 +       case DWC_GRXSTS_PKTSTS_IN:
13423 +               /* Read the data into the host buffer. */
13424 +               if (grxsts.b.bcnt > 0) {
13425 +                       dwc_otg_read_packet(dwc_otg_hcd->core_if,
13426 +                                           hc->xfer_buff,
13427 +                                           grxsts.b.bcnt);
13428 +
13429 +                       /* Update the HC fields for the next packet received. */
13430 +                       hc->xfer_count += grxsts.b.bcnt;
13431 +                       hc->xfer_buff += grxsts.b.bcnt;
13432 +               }
13433 +
13434 +       case DWC_GRXSTS_PKTSTS_IN_XFER_COMP:
13435 +       case DWC_GRXSTS_PKTSTS_DATA_TOGGLE_ERR:
13436 +       case DWC_GRXSTS_PKTSTS_CH_HALTED:
13437 +               /* Handled in interrupt, just ignore data */
13438 +               break;
13439 +       default:
13440 +               DWC_ERROR("RX_STS_Q Interrupt: Unknown status %d\n", grxsts.b.pktsts);
13441 +               break;
13442 +       }
13443 +
13444 +       return 1;
13445 +}
13446 +
13447 +/** This interrupt occurs when the non-periodic Tx FIFO is half-empty. More
13448 + * data packets may be written to the FIFO for OUT transfers. More requests
13449 + * may be written to the non-periodic request queue for IN transfers. This
13450 + * interrupt is enabled only in Slave mode. */
13451 +int32_t dwc_otg_hcd_handle_np_tx_fifo_empty_intr(dwc_otg_hcd_t *dwc_otg_hcd)
13452 +{
13453 +       DWC_DEBUGPL(DBG_HCD, "--Non-Periodic TxFIFO Empty Interrupt--\n");
13454 +       dwc_otg_hcd_queue_transactions(dwc_otg_hcd,
13455 +                                      DWC_OTG_TRANSACTION_NON_PERIODIC);
13456 +       return 1;
13457 +}
13458 +
13459 +/** This interrupt occurs when the periodic Tx FIFO is half-empty. More data
13460 + * packets may be written to the FIFO for OUT transfers. More requests may be
13461 + * written to the periodic request queue for IN transfers. This interrupt is
13462 + * enabled only in Slave mode. */
13463 +int32_t dwc_otg_hcd_handle_perio_tx_fifo_empty_intr(dwc_otg_hcd_t *dwc_otg_hcd)
13464 +{
13465 +       DWC_DEBUGPL(DBG_HCD, "--Periodic TxFIFO Empty Interrupt--\n");
13466 +       dwc_otg_hcd_queue_transactions(dwc_otg_hcd,
13467 +                                      DWC_OTG_TRANSACTION_PERIODIC);
13468 +       return 1;
13469 +}
13470 +
13471 +/** There are multiple conditions that can cause a port interrupt. This function
13472 + * determines which interrupt conditions have occurred and handles them
13473 + * appropriately. */
13474 +int32_t dwc_otg_hcd_handle_port_intr(dwc_otg_hcd_t *dwc_otg_hcd)
13475 +{
13476 +       int retval = 0;
13477 +       hprt0_data_t hprt0;
13478 +       hprt0_data_t hprt0_modify;
13479 +
13480 +       hprt0.d32 = dwc_read_reg32(dwc_otg_hcd->core_if->host_if->hprt0);
13481 +       hprt0_modify.d32 = dwc_read_reg32(dwc_otg_hcd->core_if->host_if->hprt0);
13482 +
13483 +       /* Clear appropriate bits in HPRT0 to clear the interrupt bit in
13484 +        * GINTSTS */
13485 +
13486 +       hprt0_modify.b.prtena = 0;
13487 +       hprt0_modify.b.prtconndet = 0;
13488 +       hprt0_modify.b.prtenchng = 0;
13489 +       hprt0_modify.b.prtovrcurrchng = 0;
13490 +
13491 +       /* Port Connect Detected
13492 +        * Set flag and clear if detected */
13493 +       if (hprt0.b.prtconndet) {
13494 +               DWC_DEBUGPL(DBG_HCD, "--Port Interrupt HPRT0=0x%08x "
13495 +                           "Port Connect Detected--\n", hprt0.d32);
13496 +               dwc_otg_hcd->flags.b.port_connect_status_change = 1;
13497 +               dwc_otg_hcd->flags.b.port_connect_status = 1;
13498 +               hprt0_modify.b.prtconndet = 1;
13499 +
13500 +               /* B-Device has connected, Delete the connection timer. */
13501 +               del_timer( &dwc_otg_hcd->conn_timer );
13502 +
13503 +               /* The Hub driver asserts a reset when it sees port connect
13504 +                * status change flag */
13505 +               retval |= 1;
13506 +       }
13507 +
13508 +       /* Port Enable Changed
13509 +        * Clear if detected - Set internal flag if disabled */
13510 +       if (hprt0.b.prtenchng) {
13511 +               DWC_DEBUGPL(DBG_HCD, "  --Port Interrupt HPRT0=0x%08x "
13512 +                           "Port Enable Changed--\n", hprt0.d32);
13513 +               hprt0_modify.b.prtenchng = 1;
13514 +               if (hprt0.b.prtena == 1) {
13515 +                       int do_reset = 0;
13516 +                       dwc_otg_core_params_t *params = dwc_otg_hcd->core_if->core_params;
13517 +                       dwc_otg_core_global_regs_t *global_regs = dwc_otg_hcd->core_if->core_global_regs;
13518 +                       dwc_otg_host_if_t *host_if = dwc_otg_hcd->core_if->host_if;
13519 +
13520 +                       /* Check if we need to adjust the PHY clock speed for
13521 +                        * low power and adjust it */
13522 +                       if (params->host_support_fs_ls_low_power) {
13523 +                               gusbcfg_data_t usbcfg;
13524 +
13525 +                               usbcfg.d32 = dwc_read_reg32(&global_regs->gusbcfg);
13526 +
13527 +                               if (hprt0.b.prtspd == DWC_HPRT0_PRTSPD_LOW_SPEED ||
13528 +                                   hprt0.b.prtspd == DWC_HPRT0_PRTSPD_FULL_SPEED) {
13529 +                                       /*
13530 +                                        * Low power
13531 +                                        */
13532 +                                       hcfg_data_t hcfg;
13533 +                                       if (usbcfg.b.phylpwrclksel == 0) {
13534 +                                               /* Set PHY low power clock select for FS/LS devices */
13535 +                                               usbcfg.b.phylpwrclksel = 1;
13536 +                                               dwc_write_reg32(&global_regs->gusbcfg, usbcfg.d32);
13537 +                                               do_reset = 1;
13538 +                                       }
13539 +
13540 +                                       hcfg.d32 = dwc_read_reg32(&host_if->host_global_regs->hcfg);
13541 +
13542 +                                       if (hprt0.b.prtspd == DWC_HPRT0_PRTSPD_LOW_SPEED &&
13543 +                                           params->host_ls_low_power_phy_clk ==
13544 +                                            DWC_HOST_LS_LOW_POWER_PHY_CLK_PARAM_6MHZ) {
13545 +                                               /* 6 MHZ */
13546 +                                               DWC_DEBUGPL(DBG_CIL, "FS_PHY programming HCFG to 6 MHz (Low Power)\n");
13547 +                                               if (hcfg.b.fslspclksel != DWC_HCFG_6_MHZ) {
13548 +                                                       hcfg.b.fslspclksel = DWC_HCFG_6_MHZ;
13549 +                                                       dwc_write_reg32(&host_if->host_global_regs->hcfg,
13550 +                                                                       hcfg.d32);
13551 +                                                       do_reset = 1;
13552 +                                               }
13553 +                                       } else {
13554 +                                               /* 48 MHZ */
13555 +                                               DWC_DEBUGPL(DBG_CIL, "FS_PHY programming HCFG to 48 MHz ()\n");
13556 +                                               if (hcfg.b.fslspclksel != DWC_HCFG_48_MHZ) {
13557 +                                                       hcfg.b.fslspclksel = DWC_HCFG_48_MHZ;
13558 +                                                       dwc_write_reg32(&host_if->host_global_regs->hcfg,
13559 +                                                                       hcfg.d32);
13560 +                                                       do_reset = 1;
13561 +                                               }
13562 +                                       }
13563 +                               } else {
13564 +                                       /*
13565 +                                        * Not low power
13566 +                                        */
13567 +                                       if (usbcfg.b.phylpwrclksel == 1) {
13568 +                                               usbcfg.b.phylpwrclksel = 0;
13569 +                                               dwc_write_reg32(&global_regs->gusbcfg, usbcfg.d32);
13570 +                                               do_reset = 1;
13571 +                                       }
13572 +                               }
13573 +
13574 +                               if (do_reset) {
13575 +                                       tasklet_schedule(dwc_otg_hcd->reset_tasklet);
13576 +                               }
13577 +                       }
13578 +
13579 +                       if (!do_reset) {
13580 +                               /* Port has been enabled set the reset change flag */
13581 +                               dwc_otg_hcd->flags.b.port_reset_change = 1;
13582 +                       }
13583 +               } else {
13584 +                       dwc_otg_hcd->flags.b.port_enable_change = 1;
13585 +               }
13586 +               retval |= 1;
13587 +       }
13588 +
13589 +       /** Overcurrent Change Interrupt */
13590 +       if (hprt0.b.prtovrcurrchng) {
13591 +               DWC_DEBUGPL(DBG_HCD, "  --Port Interrupt HPRT0=0x%08x "
13592 +                           "Port Overcurrent Changed--\n", hprt0.d32);
13593 +               dwc_otg_hcd->flags.b.port_over_current_change = 1;
13594 +               hprt0_modify.b.prtovrcurrchng = 1;
13595 +               retval |= 1;
13596 +       }
13597 +
13598 +       /* Clear Port Interrupts */
13599 +       dwc_write_reg32(dwc_otg_hcd->core_if->host_if->hprt0, hprt0_modify.d32);
13600 +
13601 +       return retval;
13602 +}
13603 +
13604 +/** This interrupt indicates that one or more host channels has a pending
13605 + * interrupt. There are multiple conditions that can cause each host channel
13606 + * interrupt. This function determines which conditions have occurred for each
13607 + * host channel interrupt and handles them appropriately. */
13608 +int32_t dwc_otg_hcd_handle_hc_intr(dwc_otg_hcd_t *dwc_otg_hcd)
13609 +{
13610 +       int i;
13611 +       int retval = 0;
13612 +       haint_data_t haint;
13613 +
13614 +       /* Clear appropriate bits in HCINTn to clear the interrupt bit in
13615 +        * GINTSTS */
13616 +
13617 +       haint.d32 = dwc_otg_read_host_all_channels_intr(dwc_otg_hcd->core_if);
13618 +
13619 +       for (i = 0; i < dwc_otg_hcd->core_if->core_params->host_channels; i++) {
13620 +               if (haint.b2.chint & (1 << i)) {
13621 +                       retval |= dwc_otg_hcd_handle_hc_n_intr(dwc_otg_hcd, i);
13622 +               }
13623 +       }
13624 +
13625 +       return retval;
13626 +}
13627 +
13628 +/* Macro used to clear one channel interrupt */
13629 +#define clear_hc_int(_hc_regs_, _intr_) \
13630 +do { \
13631 +       hcint_data_t hcint_clear = {.d32 = 0}; \
13632 +       hcint_clear.b._intr_ = 1; \
13633 +       dwc_write_reg32(&(_hc_regs_)->hcint, hcint_clear.d32); \
13634 +} while (0)
13635 +
13636 +/*
13637 + * Macro used to disable one channel interrupt. Channel interrupts are
13638 + * disabled when the channel is halted or released by the interrupt handler.
13639 + * There is no need to handle further interrupts of that type until the
13640 + * channel is re-assigned. In fact, subsequent handling may cause crashes
13641 + * because the channel structures are cleaned up when the channel is released.
13642 + */
13643 +#define disable_hc_int(_hc_regs_, _intr_) \
13644 +do { \
13645 +       hcintmsk_data_t hcintmsk = {.d32 = 0}; \
13646 +       hcintmsk.b._intr_ = 1; \
13647 +       dwc_modify_reg32(&(_hc_regs_)->hcintmsk, hcintmsk.d32, 0); \
13648 +} while (0)
13649 +
13650 +/**
13651 + * Gets the actual length of a transfer after the transfer halts. _halt_status
13652 + * holds the reason for the halt.
13653 + *
13654 + * For IN transfers where halt_status is DWC_OTG_HC_XFER_COMPLETE,
13655 + * *short_read is set to 1 upon return if less than the requested
13656 + * number of bytes were transferred. Otherwise, *short_read is set to 0 upon
13657 + * return. short_read may also be NULL on entry, in which case it remains
13658 + * unchanged.
13659 + */
13660 +static uint32_t get_actual_xfer_length(dwc_hc_t *hc,
13661 +                                      dwc_otg_hc_regs_t *hc_regs,
13662 +                                      dwc_otg_qtd_t *qtd,
13663 +                                      dwc_otg_halt_status_e halt_status,
13664 +                                      int *short_read)
13665 +{
13666 +       hctsiz_data_t   hctsiz;
13667 +       uint32_t        length;
13668 +
13669 +       if (short_read != NULL) {
13670 +               *short_read = 0;
13671 +       }
13672 +       hctsiz.d32 = dwc_read_reg32(&hc_regs->hctsiz);
13673 +
13674 +       if (halt_status == DWC_OTG_HC_XFER_COMPLETE) {
13675 +               if (hc->ep_is_in) {
13676 +                       length = hc->xfer_len - hctsiz.b.xfersize;
13677 +                       if (short_read != NULL) {
13678 +                               *short_read = (hctsiz.b.xfersize != 0);
13679 +                       }
13680 +               } else if (hc->qh->do_split) {
13681 +                       length = qtd->ssplit_out_xfer_count;
13682 +               } else {
13683 +                       length = hc->xfer_len;
13684 +               }
13685 +       } else {
13686 +               /*
13687 +                * Must use the hctsiz.pktcnt field to determine how much data
13688 +                * has been transferred. This field reflects the number of
13689 +                * packets that have been transferred via the USB. This is
13690 +                * always an integral number of packets if the transfer was
13691 +                * halted before its normal completion. (Can't use the
13692 +                * hctsiz.xfersize field because that reflects the number of
13693 +                * bytes transferred via the AHB, not the USB).
13694 +                */
13695 +               length = (hc->start_pkt_count - hctsiz.b.pktcnt) * hc->max_packet;
13696 +       }
13697 +
13698 +       return length;
13699 +}
13700 +
13701 +/**
13702 + * Updates the state of the URB after a Transfer Complete interrupt on the
13703 + * host channel. Updates the actual_length field of the URB based on the
13704 + * number of bytes transferred via the host channel. Sets the URB status
13705 + * if the data transfer is finished.
13706 + *
13707 + * @return 1 if the data transfer specified by the URB is completely finished,
13708 + * 0 otherwise.
13709 + */
13710 +static int update_urb_state_xfer_comp(dwc_hc_t *hc,
13711 +                                     dwc_otg_hc_regs_t *hc_regs,
13712 +                                     struct urb *urb,
13713 +                                     dwc_otg_qtd_t *qtd)
13714 +{
13715 +       int             xfer_done = 0;
13716 +       int             short_read = 0;
13717 +       int             overflow_read=0;
13718 +       uint32_t        len = 0;
13719 +       int             max_packet;
13720 +
13721 +       len = get_actual_xfer_length(hc, hc_regs, qtd,
13722 +                                    DWC_OTG_HC_XFER_COMPLETE,
13723 +                                    &short_read);
13724 +
13725 +       /* Data overflow case: by Steven */
13726 +       if (len > urb->transfer_buffer_length) {
13727 +           len = urb->transfer_buffer_length;
13728 +           overflow_read = 1;
13729 +       }
13730 +
13731 +       /* non DWORD-aligned buffer case handling. */
13732 +       if (((uint32_t)hc->xfer_buff & 0x3) && len && hc->qh->dw_align_buf && hc->ep_is_in) {
13733 +               memcpy(urb->transfer_buffer + urb->actual_length, hc->qh->dw_align_buf, len);
13734 +       }
13735 +       urb->actual_length +=len;
13736 +
13737 +       max_packet = usb_maxpacket(urb->dev, urb->pipe, !usb_pipein(urb->pipe));
13738 +       if((len) && usb_pipebulk(urb->pipe) &&
13739 +          (urb->transfer_flags & URB_ZERO_PACKET) &&
13740 +          (urb->actual_length == urb->transfer_buffer_length) &&
13741 +          (!(urb->transfer_buffer_length % max_packet))) {
13742 +       } else if (short_read || urb->actual_length == urb->transfer_buffer_length) {
13743 +               xfer_done = 1;
13744 +               if (short_read && (urb->transfer_flags & URB_SHORT_NOT_OK)) {
13745 +                       urb->status = -EREMOTEIO;
13746 +               } else if (overflow_read) {
13747 +                       urb->status = -EOVERFLOW;
13748 +               } else {
13749 +                       urb->status = 0;
13750 +               }
13751 +       }
13752 +
13753 +#ifdef DEBUG
13754 +       {
13755 +               hctsiz_data_t   hctsiz;
13756 +               hctsiz.d32 = dwc_read_reg32(&hc_regs->hctsiz);
13757 +               DWC_DEBUGPL(DBG_HCDV, "DWC_otg: %s: %s, channel %d\n",
13758 +                           __func__, (hc->ep_is_in ? "IN" : "OUT"), hc->hc_num);
13759 +               DWC_DEBUGPL(DBG_HCDV, "  hc->xfer_len %d\n", hc->xfer_len);
13760 +               DWC_DEBUGPL(DBG_HCDV, "  hctsiz.xfersize %d\n", hctsiz.b.xfersize);
13761 +               DWC_DEBUGPL(DBG_HCDV, "  urb->transfer_buffer_length %d\n",
13762 +                           urb->transfer_buffer_length);
13763 +               DWC_DEBUGPL(DBG_HCDV, "  urb->actual_length %d\n", urb->actual_length);
13764 +               DWC_DEBUGPL(DBG_HCDV, "  short_read %d, xfer_done %d\n",
13765 +                           short_read, xfer_done);
13766 +       }
13767 +#endif
13768 +
13769 +       return xfer_done;
13770 +}
13771 +
13772 +/*
13773 + * Save the starting data toggle for the next transfer. The data toggle is
13774 + * saved in the QH for non-control transfers and it's saved in the QTD for
13775 + * control transfers.
13776 + */
13777 +static void save_data_toggle(dwc_hc_t *hc,
13778 +                            dwc_otg_hc_regs_t *hc_regs,
13779 +                            dwc_otg_qtd_t *qtd)
13780 +{
13781 +       hctsiz_data_t hctsiz;
13782 +       hctsiz.d32 = dwc_read_reg32(&hc_regs->hctsiz);
13783 +
13784 +       if (hc->ep_type != DWC_OTG_EP_TYPE_CONTROL) {
13785 +               dwc_otg_qh_t *qh = hc->qh;
13786 +               if (hctsiz.b.pid == DWC_HCTSIZ_DATA0) {
13787 +                       qh->data_toggle = DWC_OTG_HC_PID_DATA0;
13788 +               } else {
13789 +                       qh->data_toggle = DWC_OTG_HC_PID_DATA1;
13790 +               }
13791 +       } else {
13792 +               if (hctsiz.b.pid == DWC_HCTSIZ_DATA0) {
13793 +                       qtd->data_toggle = DWC_OTG_HC_PID_DATA0;
13794 +               } else {
13795 +                       qtd->data_toggle = DWC_OTG_HC_PID_DATA1;
13796 +               }
13797 +       }
13798 +}
13799 +
13800 +/**
13801 + * Frees the first QTD in the QH's list if free_qtd is 1. For non-periodic
13802 + * QHs, removes the QH from the active non-periodic schedule. If any QTDs are
13803 + * still linked to the QH, the QH is added to the end of the inactive
13804 + * non-periodic schedule. For periodic QHs, removes the QH from the periodic
13805 + * schedule if no more QTDs are linked to the QH.
13806 + */
13807 +static void deactivate_qh(dwc_otg_hcd_t *hcd,
13808 +                         dwc_otg_qh_t *qh,
13809 +                         int free_qtd)
13810 +{
13811 +       int continue_split = 0;
13812 +       dwc_otg_qtd_t *qtd;
13813 +
13814 +       DWC_DEBUGPL(DBG_HCDV, "  %s(%p,%p,%d)\n", __func__, hcd, qh, free_qtd);
13815 +
13816 +       qtd = list_entry(qh->qtd_list.next, dwc_otg_qtd_t, qtd_list_entry);
13817 +
13818 +       if (qtd->complete_split) {
13819 +               continue_split = 1;
13820 +       } else if (qtd->isoc_split_pos == DWC_HCSPLIT_XACTPOS_MID ||
13821 +                  qtd->isoc_split_pos == DWC_HCSPLIT_XACTPOS_END) {
13822 +               continue_split = 1;
13823 +       }
13824 +
13825 +       if (free_qtd) {
13826 +               dwc_otg_hcd_qtd_remove_and_free(hcd, qtd);
13827 +               continue_split = 0;
13828 +       }
13829 +
13830 +       qh->channel = NULL;
13831 +       qh->qtd_in_process = NULL;
13832 +       dwc_otg_hcd_qh_deactivate(hcd, qh, continue_split);
13833 +}
13834 +
13835 +/**
13836 + * Updates the state of an Isochronous URB when the transfer is stopped for
13837 + * any reason. The fields of the current entry in the frame descriptor array
13838 + * are set based on the transfer state and the input _halt_status. Completes
13839 + * the Isochronous URB if all the URB frames have been completed.
13840 + *
13841 + * @return DWC_OTG_HC_XFER_COMPLETE if there are more frames remaining to be
13842 + * transferred in the URB. Otherwise return DWC_OTG_HC_XFER_URB_COMPLETE.
13843 + */
13844 +static dwc_otg_halt_status_e
13845 +update_isoc_urb_state(dwc_otg_hcd_t *hcd,
13846 +                     dwc_hc_t *hc,
13847 +                     dwc_otg_hc_regs_t *hc_regs,
13848 +                     dwc_otg_qtd_t *qtd,
13849 +                     dwc_otg_halt_status_e halt_status)
13850 +{
13851 +       struct urb *urb = qtd->urb;
13852 +       dwc_otg_halt_status_e ret_val = halt_status;
13853 +       struct usb_iso_packet_descriptor *frame_desc;
13854 +
13855 +       frame_desc = &urb->iso_frame_desc[qtd->isoc_frame_index];
13856 +       switch (halt_status) {
13857 +       case DWC_OTG_HC_XFER_COMPLETE:
13858 +               frame_desc->status = 0;
13859 +               frame_desc->actual_length =
13860 +                       get_actual_xfer_length(hc, hc_regs, qtd,
13861 +                                              halt_status, NULL);
13862 +
13863 +               /* non DWORD-aligned buffer case handling. */
13864 +               if (frame_desc->actual_length && ((uint32_t)hc->xfer_buff & 0x3) &&
13865 +                               hc->qh->dw_align_buf && hc->ep_is_in) {
13866 +                       memcpy(urb->transfer_buffer + frame_desc->offset + qtd->isoc_split_offset,
13867 +                               hc->qh->dw_align_buf, frame_desc->actual_length);
13868 +
13869 +               }
13870 +
13871 +               break;
13872 +       case DWC_OTG_HC_XFER_FRAME_OVERRUN:
13873 +               printk("DWC_OTG_HC_XFER_FRAME_OVERRUN: %d\n", halt_status);
13874 +               urb->error_count++;
13875 +               if (hc->ep_is_in) {
13876 +                       frame_desc->status = -ENOSR;
13877 +               } else {
13878 +                       frame_desc->status = -ECOMM;
13879 +               }
13880 +               frame_desc->actual_length = 0;
13881 +               break;
13882 +       case DWC_OTG_HC_XFER_BABBLE_ERR:
13883 +               printk("DWC_OTG_HC_XFER_BABBLE_ERR: %d\n", halt_status);
13884 +               urb->error_count++;
13885 +               frame_desc->status = -EOVERFLOW;
13886 +               /* Don't need to update actual_length in this case. */
13887 +               break;
13888 +       case DWC_OTG_HC_XFER_XACT_ERR:
13889 +               printk("DWC_OTG_HC_XFER_XACT_ERR: %d\n", halt_status);
13890 +               urb->error_count++;
13891 +               frame_desc->status = -EPROTO;
13892 +               frame_desc->actual_length =
13893 +                       get_actual_xfer_length(hc, hc_regs, qtd,
13894 +                                              halt_status, NULL);
13895 +
13896 +               /* non DWORD-aligned buffer case handling. */
13897 +               if (frame_desc->actual_length && ((uint32_t)hc->xfer_buff & 0x3) &&
13898 +                               hc->qh->dw_align_buf && hc->ep_is_in) {
13899 +                       memcpy(urb->transfer_buffer + frame_desc->offset + qtd->isoc_split_offset,
13900 +                               hc->qh->dw_align_buf, frame_desc->actual_length);
13901 +
13902 +               }
13903 +               break;
13904 +       default:
13905 +
13906 +               DWC_ERROR("%s: Unhandled _halt_status (%d)\n", __func__,
13907 +                         halt_status);
13908 +               BUG();
13909 +               break;
13910 +       }
13911 +
13912 +       if (++qtd->isoc_frame_index == urb->number_of_packets) {
13913 +               /*
13914 +                * urb->status is not used for isoc transfers.
13915 +                * The individual frame_desc statuses are used instead.
13916 +                */
13917 +               dwc_otg_hcd_complete_urb(hcd, urb, 0);
13918 +               ret_val = DWC_OTG_HC_XFER_URB_COMPLETE;
13919 +       } else {
13920 +               ret_val = DWC_OTG_HC_XFER_COMPLETE;
13921 +       }
13922 +
13923 +       return ret_val;
13924 +}
13925 +
13926 +/**
13927 + * Releases a host channel for use by other transfers. Attempts to select and
13928 + * queue more transactions since at least one host channel is available.
13929 + *
13930 + * @param hcd The HCD state structure.
13931 + * @param hc The host channel to release.
13932 + * @param qtd The QTD associated with the host channel. This QTD may be freed
13933 + * if the transfer is complete or an error has occurred.
13934 + * @param halt_status Reason the channel is being released. This status
13935 + * determines the actions taken by this function.
13936 + */
13937 +static void release_channel(dwc_otg_hcd_t *hcd,
13938 +                           dwc_hc_t *hc,
13939 +                           dwc_otg_qtd_t *qtd,
13940 +                           dwc_otg_halt_status_e halt_status)
13941 +{
13942 +       dwc_otg_transaction_type_e tr_type;
13943 +       int free_qtd;
13944 +
13945 +       DWC_DEBUGPL(DBG_HCDV, "  %s: channel %d, halt_status %d\n",
13946 +                   __func__, hc->hc_num, halt_status);
13947 +
13948 +       switch (halt_status) {
13949 +       case DWC_OTG_HC_XFER_URB_COMPLETE:
13950 +               free_qtd = 1;
13951 +               break;
13952 +       case DWC_OTG_HC_XFER_AHB_ERR:
13953 +       case DWC_OTG_HC_XFER_STALL:
13954 +       case DWC_OTG_HC_XFER_BABBLE_ERR:
13955 +               free_qtd = 1;
13956 +               break;
13957 +       case DWC_OTG_HC_XFER_XACT_ERR:
13958 +               if (qtd->error_count >= 3) {
13959 +                       DWC_DEBUGPL(DBG_HCDV, "  Complete URB with transaction error\n");
13960 +                       free_qtd = 1;
13961 +                       qtd->urb->status = -EPROTO;
13962 +                       dwc_otg_hcd_complete_urb(hcd, qtd->urb, -EPROTO);
13963 +               } else {
13964 +                       free_qtd = 0;
13965 +               }
13966 +               break;
13967 +       case DWC_OTG_HC_XFER_URB_DEQUEUE:
13968 +               /*
13969 +                * The QTD has already been removed and the QH has been
13970 +                * deactivated. Don't want to do anything except release the
13971 +                * host channel and try to queue more transfers.
13972 +                */
13973 +               goto cleanup;
13974 +       case DWC_OTG_HC_XFER_NO_HALT_STATUS:
13975 +               DWC_ERROR("%s: No halt_status, channel %d\n", __func__, hc->hc_num);
13976 +               free_qtd = 0;
13977 +               break;
13978 +       default:
13979 +               free_qtd = 0;
13980 +               break;
13981 +       }
13982 +
13983 +       deactivate_qh(hcd, hc->qh, free_qtd);
13984 +
13985 + cleanup:
13986 +       /*
13987 +        * Release the host channel for use by other transfers. The cleanup
13988 +        * function clears the channel interrupt enables and conditions, so
13989 +        * there's no need to clear the Channel Halted interrupt separately.
13990 +        */
13991 +       dwc_otg_hc_cleanup(hcd->core_if, hc);
13992 +       list_add_tail(&hc->hc_list_entry, &hcd->free_hc_list);
13993 +
13994 +       switch (hc->ep_type) {
13995 +       case DWC_OTG_EP_TYPE_CONTROL:
13996 +       case DWC_OTG_EP_TYPE_BULK:
13997 +               hcd->non_periodic_channels--;
13998 +               break;
13999 +
14000 +       default:
14001 +               /*
14002 +                * Don't release reservations for periodic channels here.
14003 +                * That's done when a periodic transfer is descheduled (i.e.
14004 +                * when the QH is removed from the periodic schedule).
14005 +                */
14006 +               break;
14007 +       }
14008 +
14009 +       /* Try to queue more transfers now that there's a free channel. */
14010 +       tr_type = dwc_otg_hcd_select_transactions(hcd);
14011 +       if (tr_type != DWC_OTG_TRANSACTION_NONE) {
14012 +               dwc_otg_hcd_queue_transactions(hcd, tr_type);
14013 +       }
14014 +}
14015 +
14016 +/**
14017 + * Halts a host channel. If the channel cannot be halted immediately because
14018 + * the request queue is full, this function ensures that the FIFO empty
14019 + * interrupt for the appropriate queue is enabled so that the halt request can
14020 + * be queued when there is space in the request queue.
14021 + *
14022 + * This function may also be called in DMA mode. In that case, the channel is
14023 + * simply released since the core always halts the channel automatically in
14024 + * DMA mode.
14025 + */
14026 +static void halt_channel(dwc_otg_hcd_t *hcd,
14027 +                        dwc_hc_t *hc,
14028 +                        dwc_otg_qtd_t *qtd,
14029 +                        dwc_otg_halt_status_e halt_status)
14030 +{
14031 +       if (hcd->core_if->dma_enable) {
14032 +               release_channel(hcd, hc, qtd, halt_status);
14033 +               return;
14034 +       }
14035 +
14036 +       /* Slave mode processing... */
14037 +       dwc_otg_hc_halt(hcd->core_if, hc, halt_status);
14038 +
14039 +       if (hc->halt_on_queue) {
14040 +               gintmsk_data_t gintmsk = {.d32 = 0};
14041 +               dwc_otg_core_global_regs_t *global_regs;
14042 +               global_regs = hcd->core_if->core_global_regs;
14043 +
14044 +               if (hc->ep_type == DWC_OTG_EP_TYPE_CONTROL ||
14045 +                   hc->ep_type == DWC_OTG_EP_TYPE_BULK) {
14046 +                       /*
14047 +                        * Make sure the Non-periodic Tx FIFO empty interrupt
14048 +                        * is enabled so that the non-periodic schedule will
14049 +                        * be processed.
14050 +                        */
14051 +                       gintmsk.b.nptxfempty = 1;
14052 +                       dwc_modify_reg32(&global_regs->gintmsk, 0, gintmsk.d32);
14053 +               } else {
14054 +                       /*
14055 +                        * Move the QH from the periodic queued schedule to
14056 +                        * the periodic assigned schedule. This allows the
14057 +                        * halt to be queued when the periodic schedule is
14058 +                        * processed.
14059 +                        */
14060 +                       list_move(&hc->qh->qh_list_entry,
14061 +                                 &hcd->periodic_sched_assigned);
14062 +
14063 +                       /*
14064 +                        * Make sure the Periodic Tx FIFO Empty interrupt is
14065 +                        * enabled so that the periodic schedule will be
14066 +                        * processed.
14067 +                        */
14068 +                       gintmsk.b.ptxfempty = 1;
14069 +                       dwc_modify_reg32(&global_regs->gintmsk, 0, gintmsk.d32);
14070 +               }
14071 +       }
14072 +}
14073 +
14074 +/**
14075 + * Performs common cleanup for non-periodic transfers after a Transfer
14076 + * Complete interrupt. This function should be called after any endpoint type
14077 + * specific handling is finished to release the host channel.
14078 + */
14079 +static void complete_non_periodic_xfer(dwc_otg_hcd_t *hcd,
14080 +                                      dwc_hc_t *hc,
14081 +                                      dwc_otg_hc_regs_t *hc_regs,
14082 +                                      dwc_otg_qtd_t *qtd,
14083 +                                      dwc_otg_halt_status_e halt_status)
14084 +{
14085 +       hcint_data_t hcint;
14086 +
14087 +       qtd->error_count = 0;
14088 +
14089 +       hcint.d32 = dwc_read_reg32(&hc_regs->hcint);
14090 +       if (hcint.b.nyet) {
14091 +               /*
14092 +                * Got a NYET on the last transaction of the transfer. This
14093 +                * means that the endpoint should be in the PING state at the
14094 +                * beginning of the next transfer.
14095 +                */
14096 +               hc->qh->ping_state = 1;
14097 +               clear_hc_int(hc_regs, nyet);
14098 +       }
14099 +
14100 +       /*
14101 +        * Always halt and release the host channel to make it available for
14102 +        * more transfers. There may still be more phases for a control
14103 +        * transfer or more data packets for a bulk transfer at this point,
14104 +        * but the host channel is still halted. A channel will be reassigned
14105 +        * to the transfer when the non-periodic schedule is processed after
14106 +        * the channel is released. This allows transactions to be queued
14107 +        * properly via dwc_otg_hcd_queue_transactions, which also enables the
14108 +        * Tx FIFO Empty interrupt if necessary.
14109 +        */
14110 +       if (hc->ep_is_in) {
14111 +               /*
14112 +                * IN transfers in Slave mode require an explicit disable to
14113 +                * halt the channel. (In DMA mode, this call simply releases
14114 +                * the channel.)
14115 +                */
14116 +               halt_channel(hcd, hc, qtd, halt_status);
14117 +       } else {
14118 +               /*
14119 +                * The channel is automatically disabled by the core for OUT
14120 +                * transfers in Slave mode.
14121 +                */
14122 +               release_channel(hcd, hc, qtd, halt_status);
14123 +       }
14124 +}
14125 +
14126 +/**
14127 + * Performs common cleanup for periodic transfers after a Transfer Complete
14128 + * interrupt. This function should be called after any endpoint type specific
14129 + * handling is finished to release the host channel.
14130 + */
14131 +static void complete_periodic_xfer(dwc_otg_hcd_t *hcd,
14132 +                                  dwc_hc_t *hc,
14133 +                                  dwc_otg_hc_regs_t *hc_regs,
14134 +                                  dwc_otg_qtd_t *qtd,
14135 +                                  dwc_otg_halt_status_e halt_status)
14136 +{
14137 +       hctsiz_data_t hctsiz;
14138 +       qtd->error_count = 0;
14139 +
14140 +       hctsiz.d32 = dwc_read_reg32(&hc_regs->hctsiz);
14141 +       if (!hc->ep_is_in || hctsiz.b.pktcnt == 0) {
14142 +               /* Core halts channel in these cases. */
14143 +               release_channel(hcd, hc, qtd, halt_status);
14144 +       } else {
14145 +               /* Flush any outstanding requests from the Tx queue. */
14146 +               halt_channel(hcd, hc, qtd, halt_status);
14147 +       }
14148 +}
14149 +
14150 +/**
14151 + * Handles a host channel Transfer Complete interrupt. This handler may be
14152 + * called in either DMA mode or Slave mode.
14153 + */
14154 +static int32_t handle_hc_xfercomp_intr(dwc_otg_hcd_t *hcd,
14155 +                                      dwc_hc_t *hc,
14156 +                                      dwc_otg_hc_regs_t *hc_regs,
14157 +                                      dwc_otg_qtd_t *qtd)
14158 +{
14159 +       int                     urb_xfer_done;
14160 +       dwc_otg_halt_status_e   halt_status = DWC_OTG_HC_XFER_COMPLETE;
14161 +       struct urb              *urb = qtd->urb;
14162 +       int                     pipe_type = usb_pipetype(urb->pipe);
14163 +
14164 +       DWC_DEBUGPL(DBG_HCD, "--Host Channel %d Interrupt: "
14165 +                   "Transfer Complete--\n", hc->hc_num);
14166 +
14167 +       /*
14168 +        * Handle xfer complete on CSPLIT.
14169 +        */
14170 +       if (hc->qh->do_split) {
14171 +               qtd->complete_split = 0;
14172 +       }
14173 +
14174 +       /* Update the QTD and URB states. */
14175 +       switch (pipe_type) {
14176 +       case PIPE_CONTROL:
14177 +               switch (qtd->control_phase) {
14178 +               case DWC_OTG_CONTROL_SETUP:
14179 +                       if (urb->transfer_buffer_length > 0) {
14180 +                               qtd->control_phase = DWC_OTG_CONTROL_DATA;
14181 +                       } else {
14182 +                               qtd->control_phase = DWC_OTG_CONTROL_STATUS;
14183 +                       }
14184 +                       DWC_DEBUGPL(DBG_HCDV, "  Control setup transaction done\n");
14185 +                       halt_status = DWC_OTG_HC_XFER_COMPLETE;
14186 +                       break;
14187 +               case DWC_OTG_CONTROL_DATA: {
14188 +                       urb_xfer_done = update_urb_state_xfer_comp(hc, hc_regs, urb, qtd);
14189 +                       if (urb_xfer_done) {
14190 +                               qtd->control_phase = DWC_OTG_CONTROL_STATUS;
14191 +                               DWC_DEBUGPL(DBG_HCDV, "  Control data transfer done\n");
14192 +                       } else {
14193 +                               save_data_toggle(hc, hc_regs, qtd);
14194 +                       }
14195 +                       halt_status = DWC_OTG_HC_XFER_COMPLETE;
14196 +                       break;
14197 +               }
14198 +               case DWC_OTG_CONTROL_STATUS:
14199 +                       DWC_DEBUGPL(DBG_HCDV, "  Control transfer complete\n");
14200 +                       if (urb->status == -EINPROGRESS) {
14201 +                               urb->status = 0;
14202 +                       }
14203 +                       dwc_otg_hcd_complete_urb(hcd, urb, urb->status);
14204 +                       halt_status = DWC_OTG_HC_XFER_URB_COMPLETE;
14205 +                       break;
14206 +               }
14207 +
14208 +               complete_non_periodic_xfer(hcd, hc, hc_regs, qtd, halt_status);
14209 +               break;
14210 +       case PIPE_BULK:
14211 +               DWC_DEBUGPL(DBG_HCDV, "  Bulk transfer complete\n");
14212 +               urb_xfer_done = update_urb_state_xfer_comp(hc, hc_regs, urb, qtd);
14213 +               if (urb_xfer_done) {
14214 +                       dwc_otg_hcd_complete_urb(hcd, urb, urb->status);
14215 +                       halt_status = DWC_OTG_HC_XFER_URB_COMPLETE;
14216 +               } else {
14217 +                       halt_status = DWC_OTG_HC_XFER_COMPLETE;
14218 +               }
14219 +
14220 +               save_data_toggle(hc, hc_regs, qtd);
14221 +               complete_non_periodic_xfer(hcd, hc, hc_regs, qtd, halt_status);
14222 +               break;
14223 +       case PIPE_INTERRUPT:
14224 +               DWC_DEBUGPL(DBG_HCDV, "  Interrupt transfer complete\n");
14225 +               update_urb_state_xfer_comp(hc, hc_regs, urb, qtd);
14226 +
14227 +               /*
14228 +                * Interrupt URB is done on the first transfer complete
14229 +                * interrupt.
14230 +                */
14231 +               dwc_otg_hcd_complete_urb(hcd, urb, urb->status);
14232 +               save_data_toggle(hc, hc_regs, qtd);
14233 +               complete_periodic_xfer(hcd, hc, hc_regs, qtd,
14234 +                                      DWC_OTG_HC_XFER_URB_COMPLETE);
14235 +               break;
14236 +       case PIPE_ISOCHRONOUS:
14237 +               DWC_DEBUGPL(DBG_HCDV,  "  Isochronous transfer complete\n");
14238 +               if (qtd->isoc_split_pos == DWC_HCSPLIT_XACTPOS_ALL) {
14239 +                       halt_status = update_isoc_urb_state(hcd, hc, hc_regs, qtd,
14240 +                                                           DWC_OTG_HC_XFER_COMPLETE);
14241 +               }
14242 +               complete_periodic_xfer(hcd, hc, hc_regs, qtd, halt_status);
14243 +               break;
14244 +       }
14245 +
14246 +       disable_hc_int(hc_regs, xfercompl);
14247 +
14248 +       return 1;
14249 +}
14250 +
14251 +/**
14252 + * Handles a host channel STALL interrupt. This handler may be called in
14253 + * either DMA mode or Slave mode.
14254 + */
14255 +static int32_t handle_hc_stall_intr(dwc_otg_hcd_t *hcd,
14256 +                                   dwc_hc_t *hc,
14257 +                                   dwc_otg_hc_regs_t *hc_regs,
14258 +                                   dwc_otg_qtd_t *qtd)
14259 +{
14260 +       struct urb *urb = qtd->urb;
14261 +       int pipe_type = usb_pipetype(urb->pipe);
14262 +
14263 +       DWC_DEBUGPL(DBG_HCD, "--Host Channel %d Interrupt: "
14264 +                   "STALL Received--\n", hc->hc_num);
14265 +
14266 +       if (pipe_type == PIPE_CONTROL) {
14267 +               dwc_otg_hcd_complete_urb(hcd, urb, -EPIPE);
14268 +       }
14269 +
14270 +       if (pipe_type == PIPE_BULK || pipe_type == PIPE_INTERRUPT) {
14271 +               dwc_otg_hcd_complete_urb(hcd, urb, -EPIPE);
14272 +               /*
14273 +                * USB protocol requires resetting the data toggle for bulk
14274 +                * and interrupt endpoints when a CLEAR_FEATURE(ENDPOINT_HALT)
14275 +                * setup command is issued to the endpoint. Anticipate the
14276 +                * CLEAR_FEATURE command since a STALL has occurred and reset
14277 +                * the data toggle now.
14278 +                */
14279 +               hc->qh->data_toggle = 0;
14280 +       }
14281 +
14282 +       halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_STALL);
14283 +
14284 +       disable_hc_int(hc_regs, stall);
14285 +
14286 +       return 1;
14287 +}
14288 +
14289 +/*
14290 + * Updates the state of the URB when a transfer has been stopped due to an
14291 + * abnormal condition before the transfer completes. Modifies the
14292 + * actual_length field of the URB to reflect the number of bytes that have
14293 + * actually been transferred via the host channel.
14294 + */
14295 +static void update_urb_state_xfer_intr(dwc_hc_t *hc,
14296 +                                      dwc_otg_hc_regs_t *hc_regs,
14297 +                                      struct urb *urb,
14298 +                                      dwc_otg_qtd_t *qtd,
14299 +                                      dwc_otg_halt_status_e halt_status)
14300 +{
14301 +       uint32_t bytes_transferred = get_actual_xfer_length(hc, hc_regs, qtd,
14302 +                                                           halt_status, NULL);
14303 +       urb->actual_length += bytes_transferred;
14304 +
14305 +#ifdef DEBUG
14306 +       {
14307 +               hctsiz_data_t   hctsiz;
14308 +               hctsiz.d32 = dwc_read_reg32(&hc_regs->hctsiz);
14309 +               DWC_DEBUGPL(DBG_HCDV, "DWC_otg: %s: %s, channel %d\n",
14310 +                           __func__, (hc->ep_is_in ? "IN" : "OUT"), hc->hc_num);
14311 +               DWC_DEBUGPL(DBG_HCDV, "  hc->start_pkt_count %d\n", hc->start_pkt_count);
14312 +               DWC_DEBUGPL(DBG_HCDV, "  hctsiz.pktcnt %d\n", hctsiz.b.pktcnt);
14313 +               DWC_DEBUGPL(DBG_HCDV, "  hc->max_packet %d\n", hc->max_packet);
14314 +               DWC_DEBUGPL(DBG_HCDV, "  bytes_transferred %d\n", bytes_transferred);
14315 +               DWC_DEBUGPL(DBG_HCDV, "  urb->actual_length %d\n", urb->actual_length);
14316 +               DWC_DEBUGPL(DBG_HCDV, "  urb->transfer_buffer_length %d\n",
14317 +                           urb->transfer_buffer_length);
14318 +       }
14319 +#endif
14320 +}
14321 +
14322 +/**
14323 + * Handles a host channel NAK interrupt. This handler may be called in either
14324 + * DMA mode or Slave mode.
14325 + */
14326 +static int32_t handle_hc_nak_intr(dwc_otg_hcd_t *hcd,
14327 +                                 dwc_hc_t *hc,
14328 +                                 dwc_otg_hc_regs_t *hc_regs,
14329 +                                 dwc_otg_qtd_t *qtd)
14330 +{
14331 +       DWC_DEBUGPL(DBG_HCD, "--Host Channel %d Interrupt: "
14332 +                   "NAK Received--\n", hc->hc_num);
14333 +
14334 +       /*
14335 +        * Handle NAK for IN/OUT SSPLIT/CSPLIT transfers, bulk, control, and
14336 +        * interrupt.  Re-start the SSPLIT transfer.
14337 +        */
14338 +       if (hc->do_split) {
14339 +               if (hc->complete_split) {
14340 +                       qtd->error_count = 0;
14341 +               }
14342 +               qtd->complete_split = 0;
14343 +               halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_NAK);
14344 +               goto handle_nak_done;
14345 +       }
14346 +
14347 +       switch (usb_pipetype(qtd->urb->pipe)) {
14348 +       case PIPE_CONTROL:
14349 +       case PIPE_BULK:
14350 +               if (hcd->core_if->dma_enable && hc->ep_is_in) {
14351 +                       /*
14352 +                        * NAK interrupts are enabled on bulk/control IN
14353 +                        * transfers in DMA mode for the sole purpose of
14354 +                        * resetting the error count after a transaction error
14355 +                        * occurs. The core will continue transferring data.
14356 +                        */
14357 +                       qtd->error_count = 0;
14358 +                       goto handle_nak_done;
14359 +               }
14360 +
14361 +               /*
14362 +                * NAK interrupts normally occur during OUT transfers in DMA
14363 +                * or Slave mode. For IN transfers, more requests will be
14364 +                * queued as request queue space is available.
14365 +                */
14366 +               qtd->error_count = 0;
14367 +
14368 +               if (!hc->qh->ping_state) {
14369 +                       update_urb_state_xfer_intr(hc, hc_regs, qtd->urb,
14370 +                                                  qtd, DWC_OTG_HC_XFER_NAK);
14371 +                       save_data_toggle(hc, hc_regs, qtd);
14372 +                       if (qtd->urb->dev->speed == USB_SPEED_HIGH) {
14373 +                               hc->qh->ping_state = 1;
14374 +                       }
14375 +               }
14376 +
14377 +               /*
14378 +                * Halt the channel so the transfer can be re-started from
14379 +                * the appropriate point or the PING protocol will
14380 +                * start/continue.
14381 +                */
14382 +               halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_NAK);
14383 +               break;
14384 +       case PIPE_INTERRUPT:
14385 +               qtd->error_count = 0;
14386 +               halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_NAK);
14387 +               break;
14388 +       case PIPE_ISOCHRONOUS:
14389 +               /* Should never get called for isochronous transfers. */
14390 +               BUG();
14391 +               break;
14392 +       }
14393 +
14394 + handle_nak_done:
14395 +       disable_hc_int(hc_regs, nak);
14396 +
14397 +       return 1;
14398 +}
14399 +
14400 +/**
14401 + * Handles a host channel ACK interrupt. This interrupt is enabled when
14402 + * performing the PING protocol in Slave mode, when errors occur during
14403 + * either Slave mode or DMA mode, and during Start Split transactions.
14404 + */
14405 +static int32_t handle_hc_ack_intr(dwc_otg_hcd_t *hcd,
14406 +                                 dwc_hc_t *hc,
14407 +                                 dwc_otg_hc_regs_t *hc_regs,
14408 +                                 dwc_otg_qtd_t *qtd)
14409 +{
14410 +       DWC_DEBUGPL(DBG_HCD, "--Host Channel %d Interrupt: "
14411 +                   "ACK Received--\n", hc->hc_num);
14412 +
14413 +       if (hc->do_split) {
14414 +               /*
14415 +                * Handle ACK on SSPLIT.
14416 +                * ACK should not occur in CSPLIT.
14417 +                */
14418 +               if (!hc->ep_is_in && hc->data_pid_start != DWC_OTG_HC_PID_SETUP) {
14419 +                       qtd->ssplit_out_xfer_count = hc->xfer_len;
14420 +               }
14421 +               if (!(hc->ep_type == DWC_OTG_EP_TYPE_ISOC && !hc->ep_is_in)) {
14422 +                       /* Don't need complete for isochronous out transfers. */
14423 +                       qtd->complete_split = 1;
14424 +               }
14425 +
14426 +               /* ISOC OUT */
14427 +               if (hc->ep_type == DWC_OTG_EP_TYPE_ISOC && !hc->ep_is_in) {
14428 +                       switch (hc->xact_pos) {
14429 +                       case DWC_HCSPLIT_XACTPOS_ALL:
14430 +                               break;
14431 +                       case DWC_HCSPLIT_XACTPOS_END:
14432 +                               qtd->isoc_split_pos = DWC_HCSPLIT_XACTPOS_ALL;
14433 +                               qtd->isoc_split_offset = 0;
14434 +                               break;
14435 +                       case DWC_HCSPLIT_XACTPOS_BEGIN:
14436 +                       case DWC_HCSPLIT_XACTPOS_MID:
14437 +                               /*
14438 +                                * For BEGIN or MID, calculate the length for
14439 +                                * the next microframe to determine the correct
14440 +                                * SSPLIT token, either MID or END.
14441 +                                */
14442 +                               {
14443 +                                       struct usb_iso_packet_descriptor *frame_desc;
14444 +
14445 +                                       frame_desc = &qtd->urb->iso_frame_desc[qtd->isoc_frame_index];
14446 +                                       qtd->isoc_split_offset += 188;
14447 +
14448 +                                       if ((frame_desc->length - qtd->isoc_split_offset) <= 188) {
14449 +                                               qtd->isoc_split_pos = DWC_HCSPLIT_XACTPOS_END;
14450 +                                       } else {
14451 +                                               qtd->isoc_split_pos = DWC_HCSPLIT_XACTPOS_MID;
14452 +                                       }
14453 +
14454 +                               }
14455 +                               break;
14456 +                       }
14457 +               } else {
14458 +                       halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_ACK);
14459 +               }
14460 +       } else {
14461 +               qtd->error_count = 0;
14462 +
14463 +               if (hc->qh->ping_state) {
14464 +                       hc->qh->ping_state = 0;
14465 +                       /*
14466 +                        * Halt the channel so the transfer can be re-started
14467 +                        * from the appropriate point. This only happens in
14468 +                        * Slave mode. In DMA mode, the ping_state is cleared
14469 +                        * when the transfer is started because the core
14470 +                        * automatically executes the PING, then the transfer.
14471 +                        */
14472 +                       halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_ACK);
14473 +               }
14474 +       }
14475 +
14476 +       /*
14477 +        * If the ACK occurred when _not_ in the PING state, let the channel
14478 +        * continue transferring data after clearing the error count.
14479 +        */
14480 +
14481 +       disable_hc_int(hc_regs, ack);
14482 +
14483 +       return 1;
14484 +}
14485 +
14486 +/**
14487 + * Handles a host channel NYET interrupt. This interrupt should only occur on
14488 + * Bulk and Control OUT endpoints and for complete split transactions. If a
14489 + * NYET occurs at the same time as a Transfer Complete interrupt, it is
14490 + * handled in the xfercomp interrupt handler, not here. This handler may be
14491 + * called in either DMA mode or Slave mode.
14492 + */
14493 +static int32_t handle_hc_nyet_intr(dwc_otg_hcd_t *hcd,
14494 +                                  dwc_hc_t *hc,
14495 +                                  dwc_otg_hc_regs_t *hc_regs,
14496 +                                  dwc_otg_qtd_t *qtd)
14497 +{
14498 +       DWC_DEBUGPL(DBG_HCD, "--Host Channel %d Interrupt: "
14499 +                   "NYET Received--\n", hc->hc_num);
14500 +
14501 +       /*
14502 +        * NYET on CSPLIT
14503 +        * re-do the CSPLIT immediately on non-periodic
14504 +        */
14505 +       if (hc->do_split && hc->complete_split) {
14506 +               if (hc->ep_type == DWC_OTG_EP_TYPE_INTR ||
14507 +                   hc->ep_type == DWC_OTG_EP_TYPE_ISOC) {
14508 +                       int frnum = dwc_otg_hcd_get_frame_number(dwc_otg_hcd_to_hcd(hcd));
14509 +
14510 +                       if (dwc_full_frame_num(frnum) !=
14511 +                           dwc_full_frame_num(hc->qh->sched_frame)) {
14512 +                               /*
14513 +                                * No longer in the same full speed frame.
14514 +                                * Treat this as a transaction error.
14515 +                                */
14516 +#if 0
14517 +                               /** @todo Fix system performance so this can
14518 +                                * be treated as an error. Right now complete
14519 +                                * splits cannot be scheduled precisely enough
14520 +                                * due to other system activity, so this error
14521 +                                * occurs regularly in Slave mode.
14522 +                                */
14523 +                               qtd->error_count++;
14524 +#endif
14525 +                               qtd->complete_split = 0;
14526 +                               halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_XACT_ERR);
14527 +                               /** @todo add support for isoc release */
14528 +                               goto handle_nyet_done;
14529 +                       }
14530 +               }
14531 +
14532 +               halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_NYET);
14533 +               goto handle_nyet_done;
14534 +       }
14535 +
14536 +       hc->qh->ping_state = 1;
14537 +       qtd->error_count = 0;
14538 +
14539 +       update_urb_state_xfer_intr(hc, hc_regs, qtd->urb, qtd,
14540 +                                  DWC_OTG_HC_XFER_NYET);
14541 +       save_data_toggle(hc, hc_regs, qtd);
14542 +
14543 +       /*
14544 +        * Halt the channel and re-start the transfer so the PING
14545 +        * protocol will start.
14546 +        */
14547 +       halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_NYET);
14548 +
14549 +handle_nyet_done:
14550 +       disable_hc_int(hc_regs, nyet);
14551 +       return 1;
14552 +}
14553 +
14554 +/**
14555 + * Handles a host channel babble interrupt. This handler may be called in
14556 + * either DMA mode or Slave mode.
14557 + */
14558 +static int32_t handle_hc_babble_intr(dwc_otg_hcd_t *hcd,
14559 +                                    dwc_hc_t *hc,
14560 +                                    dwc_otg_hc_regs_t *hc_regs,
14561 +                                    dwc_otg_qtd_t *qtd)
14562 +{
14563 +       DWC_DEBUGPL(DBG_HCD, "--Host Channel %d Interrupt: "
14564 +                   "Babble Error--\n", hc->hc_num);
14565 +       if (hc->ep_type != DWC_OTG_EP_TYPE_ISOC) {
14566 +               dwc_otg_hcd_complete_urb(hcd, qtd->urb, -EOVERFLOW);
14567 +               halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_BABBLE_ERR);
14568 +       } else {
14569 +               dwc_otg_halt_status_e halt_status;
14570 +               halt_status = update_isoc_urb_state(hcd, hc, hc_regs, qtd,
14571 +                                                   DWC_OTG_HC_XFER_BABBLE_ERR);
14572 +               halt_channel(hcd, hc, qtd, halt_status);
14573 +       }
14574 +       disable_hc_int(hc_regs, bblerr);
14575 +       return 1;
14576 +}
14577 +
14578 +/**
14579 + * Handles a host channel AHB error interrupt. This handler is only called in
14580 + * DMA mode.
14581 + */
14582 +static int32_t handle_hc_ahberr_intr(dwc_otg_hcd_t *hcd,
14583 +                                    dwc_hc_t *hc,
14584 +                                    dwc_otg_hc_regs_t *hc_regs,
14585 +                                    dwc_otg_qtd_t *qtd)
14586 +{
14587 +       hcchar_data_t   hcchar;
14588 +       hcsplt_data_t   hcsplt;
14589 +       hctsiz_data_t   hctsiz;
14590 +       uint32_t        hcdma;
14591 +       struct urb      *urb = qtd->urb;
14592 +
14593 +       DWC_DEBUGPL(DBG_HCD, "--Host Channel %d Interrupt: "
14594 +                   "AHB Error--\n", hc->hc_num);
14595 +
14596 +       hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
14597 +       hcsplt.d32 = dwc_read_reg32(&hc_regs->hcsplt);
14598 +       hctsiz.d32 = dwc_read_reg32(&hc_regs->hctsiz);
14599 +       hcdma = dwc_read_reg32(&hc_regs->hcdma);
14600 +
14601 +       DWC_ERROR("AHB ERROR, Channel %d\n", hc->hc_num);
14602 +       DWC_ERROR("  hcchar 0x%08x, hcsplt 0x%08x\n", hcchar.d32, hcsplt.d32);
14603 +       DWC_ERROR("  hctsiz 0x%08x, hcdma 0x%08x\n", hctsiz.d32, hcdma);
14604 +                 DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD URB Enqueue\n");
14605 +       DWC_ERROR("  Device address: %d\n", usb_pipedevice(urb->pipe));
14606 +       DWC_ERROR("  Endpoint: %d, %s\n", usb_pipeendpoint(urb->pipe),
14607 +                 (usb_pipein(urb->pipe) ? "IN" : "OUT"));
14608 +       DWC_ERROR("  Endpoint type: %s\n",
14609 +                 ({char *pipetype;
14610 +                   switch (usb_pipetype(urb->pipe)) {
14611 +                   case PIPE_CONTROL: pipetype = "CONTROL"; break;
14612 +                   case PIPE_BULK: pipetype = "BULK"; break;
14613 +                   case PIPE_INTERRUPT: pipetype = "INTERRUPT"; break;
14614 +                   case PIPE_ISOCHRONOUS: pipetype = "ISOCHRONOUS"; break;
14615 +                   default: pipetype = "UNKNOWN"; break;
14616 +                  }; pipetype;}));
14617 +       DWC_ERROR("  Speed: %s\n",
14618 +                 ({char *speed;
14619 +                   switch (urb->dev->speed) {
14620 +                   case USB_SPEED_HIGH: speed = "HIGH"; break;
14621 +                   case USB_SPEED_FULL: speed = "FULL"; break;
14622 +                   case USB_SPEED_LOW: speed = "LOW"; break;
14623 +                   default: speed = "UNKNOWN"; break;
14624 +                  }; speed;}));
14625 +       DWC_ERROR("  Max packet size: %d\n",
14626 +                 usb_maxpacket(urb->dev, urb->pipe, usb_pipeout(urb->pipe)));
14627 +       DWC_ERROR("  Data buffer length: %d\n", urb->transfer_buffer_length);
14628 +       DWC_ERROR("  Transfer buffer: %p, Transfer DMA: %p\n",
14629 +                 urb->transfer_buffer, (void *)urb->transfer_dma);
14630 +       DWC_ERROR("  Setup buffer: %p, Setup DMA: %p\n",
14631 +                 urb->setup_packet, (void *)urb->setup_dma);
14632 +       DWC_ERROR("  Interval: %d\n", urb->interval);
14633 +
14634 +       dwc_otg_hcd_complete_urb(hcd, urb, -EIO);
14635 +
14636 +       /*
14637 +        * Force a channel halt. Don't call halt_channel because that won't
14638 +        * write to the HCCHARn register in DMA mode to force the halt.
14639 +        */
14640 +       dwc_otg_hc_halt(hcd->core_if, hc, DWC_OTG_HC_XFER_AHB_ERR);
14641 +
14642 +       disable_hc_int(hc_regs, ahberr);
14643 +       return 1;
14644 +}
14645 +
14646 +/**
14647 + * Handles a host channel transaction error interrupt. This handler may be
14648 + * called in either DMA mode or Slave mode.
14649 + */
14650 +static int32_t handle_hc_xacterr_intr(dwc_otg_hcd_t *hcd,
14651 +                                     dwc_hc_t *hc,
14652 +                                     dwc_otg_hc_regs_t *hc_regs,
14653 +                                     dwc_otg_qtd_t *qtd)
14654 +{
14655 +       DWC_DEBUGPL(DBG_HCD, "--Host Channel %d Interrupt: "
14656 +                   "Transaction Error--\n", hc->hc_num);
14657 +
14658 +       switch (usb_pipetype(qtd->urb->pipe)) {
14659 +       case PIPE_CONTROL:
14660 +       case PIPE_BULK:
14661 +               qtd->error_count++;
14662 +               if (!hc->qh->ping_state) {
14663 +                       update_urb_state_xfer_intr(hc, hc_regs, qtd->urb,
14664 +                                                  qtd, DWC_OTG_HC_XFER_XACT_ERR);
14665 +                       save_data_toggle(hc, hc_regs, qtd);
14666 +                       if (!hc->ep_is_in && qtd->urb->dev->speed == USB_SPEED_HIGH) {
14667 +                               hc->qh->ping_state = 1;
14668 +                       }
14669 +               }
14670 +
14671 +               /*
14672 +                * Halt the channel so the transfer can be re-started from
14673 +                * the appropriate point or the PING protocol will start.
14674 +                */
14675 +               halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_XACT_ERR);
14676 +               break;
14677 +       case PIPE_INTERRUPT:
14678 +               qtd->error_count++;
14679 +               if (hc->do_split && hc->complete_split) {
14680 +                       qtd->complete_split = 0;
14681 +               }
14682 +               halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_XACT_ERR);
14683 +               break;
14684 +       case PIPE_ISOCHRONOUS:
14685 +               {
14686 +                       dwc_otg_halt_status_e halt_status;
14687 +                       halt_status = update_isoc_urb_state(hcd, hc, hc_regs, qtd,
14688 +                                                           DWC_OTG_HC_XFER_XACT_ERR);
14689 +
14690 +                       halt_channel(hcd, hc, qtd, halt_status);
14691 +               }
14692 +               break;
14693 +       }
14694 +
14695 +       disable_hc_int(hc_regs, xacterr);
14696 +
14697 +       return 1;
14698 +}
14699 +
14700 +/**
14701 + * Handles a host channel frame overrun interrupt. This handler may be called
14702 + * in either DMA mode or Slave mode.
14703 + */
14704 +static int32_t handle_hc_frmovrun_intr(dwc_otg_hcd_t *hcd,
14705 +                                      dwc_hc_t *hc,
14706 +                                      dwc_otg_hc_regs_t *hc_regs,
14707 +                                      dwc_otg_qtd_t *qtd)
14708 +{
14709 +       DWC_DEBUGPL(DBG_HCD, "--Host Channel %d Interrupt: "
14710 +                   "Frame Overrun--\n", hc->hc_num);
14711 +
14712 +       switch (usb_pipetype(qtd->urb->pipe)) {
14713 +       case PIPE_CONTROL:
14714 +       case PIPE_BULK:
14715 +               break;
14716 +       case PIPE_INTERRUPT:
14717 +               halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_FRAME_OVERRUN);
14718 +               break;
14719 +       case PIPE_ISOCHRONOUS:
14720 +               {
14721 +                       dwc_otg_halt_status_e halt_status;
14722 +                       halt_status = update_isoc_urb_state(hcd, hc, hc_regs, qtd,
14723 +                                                           DWC_OTG_HC_XFER_FRAME_OVERRUN);
14724 +
14725 +                       halt_channel(hcd, hc, qtd, halt_status);
14726 +               }
14727 +               break;
14728 +       }
14729 +
14730 +       disable_hc_int(hc_regs, frmovrun);
14731 +
14732 +       return 1;
14733 +}
14734 +
14735 +/**
14736 + * Handles a host channel data toggle error interrupt. This handler may be
14737 + * called in either DMA mode or Slave mode.
14738 + */
14739 +static int32_t handle_hc_datatglerr_intr(dwc_otg_hcd_t *hcd,
14740 +                                        dwc_hc_t *hc,
14741 +                                        dwc_otg_hc_regs_t *hc_regs,
14742 +                                        dwc_otg_qtd_t *qtd)
14743 +{
14744 +       DWC_DEBUGPL(DBG_HCD, "--Host Channel %d Interrupt: "
14745 +                   "Data Toggle Error--\n", hc->hc_num);
14746 +
14747 +       if (hc->ep_is_in) {
14748 +               qtd->error_count = 0;
14749 +       } else {
14750 +               DWC_ERROR("Data Toggle Error on OUT transfer,"
14751 +                         "channel %d\n", hc->hc_num);
14752 +       }
14753 +
14754 +       disable_hc_int(hc_regs, datatglerr);
14755 +
14756 +       return 1;
14757 +}
14758 +
14759 +#ifdef DEBUG
14760 +/**
14761 + * This function is for debug only. It checks that a valid halt status is set
14762 + * and that HCCHARn.chdis is clear. If there's a problem, corrective action is
14763 + * taken and a warning is issued.
14764 + * @return 1 if halt status is ok, 0 otherwise.
14765 + */
14766 +static inline int halt_status_ok(dwc_otg_hcd_t *hcd,
14767 +                                dwc_hc_t *hc,
14768 +                                dwc_otg_hc_regs_t *hc_regs,
14769 +                                dwc_otg_qtd_t *qtd)
14770 +{
14771 +       hcchar_data_t hcchar;
14772 +       hctsiz_data_t hctsiz;
14773 +       hcint_data_t hcint;
14774 +       hcintmsk_data_t hcintmsk;
14775 +       hcsplt_data_t hcsplt;
14776 +
14777 +       if (hc->halt_status == DWC_OTG_HC_XFER_NO_HALT_STATUS) {
14778 +               /*
14779 +                * This code is here only as a check. This condition should
14780 +                * never happen. Ignore the halt if it does occur.
14781 +                */
14782 +               hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
14783 +               hctsiz.d32 = dwc_read_reg32(&hc_regs->hctsiz);
14784 +               hcint.d32 = dwc_read_reg32(&hc_regs->hcint);
14785 +               hcintmsk.d32 = dwc_read_reg32(&hc_regs->hcintmsk);
14786 +               hcsplt.d32 = dwc_read_reg32(&hc_regs->hcsplt);
14787 +               DWC_WARN("%s: hc->halt_status == DWC_OTG"
14788 +                        "channel %d, hcchar 0x%08x, hctsiz 0x%08x, "
14789 +                        "hcint 0x%08x, hcintmsk 0x%08x, "
14790 +                        "hcsplt 0x%08x, qtd->complete_split %d\n",
14791 +                        __func__, hc->hc_num, hcchar.d32, hctsiz.d32,
14792 +                        hcint.d32, hcintmsk.d32,
14793 +                        hcsplt.d32, qtd->complete_split);
14794 +
14795 +               DWC_WARN("%s: no halt status, channel %d, ignoring interrupt\n",
14796 +                        __func__, hc->hc_num);
14797 +               DWC_WARN("\n");
14798 +               clear_hc_int(hc_regs, chhltd);
14799 +               return 0;
14800 +       }
14801 +
14802 +       /*
14803 +        * This code is here only as a check. hcchar.chdis should
14804 +        * never be set when the halt interrupt occurs. Halt the
14805 +        * channel again if it does occur.
14806 +        */
14807 +       hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
14808 +       if (hcchar.b.chdis) {
14809 +               DWC_WARN("%s: hcchar.chdis set unexpectedly, "
14810 +                        "hcchar 0x%08x, trying to halt again\n",
14811 +                        __func__, hcchar.d32);
14812 +               clear_hc_int(hc_regs, chhltd);
14813 +               hc->halt_pending = 0;
14814 +               halt_channel(hcd, hc, qtd, hc->halt_status);
14815 +               return 0;
14816 +       }
14817 +
14818 +       return 1;
14819 +}
14820 +#endif
14821 +
14822 +/**
14823 + * Handles a host Channel Halted interrupt in DMA mode. This handler
14824 + * determines the reason the channel halted and proceeds accordingly.
14825 + */
14826 +static void handle_hc_chhltd_intr_dma(dwc_otg_hcd_t *hcd,
14827 +                                     dwc_hc_t *hc,
14828 +                                     dwc_otg_hc_regs_t *hc_regs,
14829 +                                     dwc_otg_qtd_t *qtd)
14830 +{
14831 +       hcint_data_t hcint;
14832 +       hcintmsk_data_t hcintmsk;
14833 +       int out_nak_enh = 0;
14834 +
14835 +       /* For core with OUT NAK enhancement, the flow for high-
14836 +        * speed CONTROL/BULK OUT is handled a little differently.
14837 +        */
14838 +       if (hcd->core_if->snpsid >= 0x4F54271A) {
14839 +               if (hc->speed == DWC_OTG_EP_SPEED_HIGH && !hc->ep_is_in &&
14840 +                   (hc->ep_type == DWC_OTG_EP_TYPE_CONTROL ||
14841 +                    hc->ep_type == DWC_OTG_EP_TYPE_BULK)) {
14842 +                       printk(KERN_DEBUG "OUT NAK enhancement enabled\n");
14843 +                       out_nak_enh = 1;
14844 +               } else {
14845 +                       printk(KERN_DEBUG "OUT NAK enhancement disabled, not HS Ctrl/Bulk OUT EP\n");
14846 +               }
14847 +       } else {
14848 +//             printk(KERN_DEBUG "OUT NAK enhancement disabled, no core support\n");
14849 +       }
14850 +
14851 +       if (hc->halt_status == DWC_OTG_HC_XFER_URB_DEQUEUE ||
14852 +           hc->halt_status == DWC_OTG_HC_XFER_AHB_ERR) {
14853 +               /*
14854 +                * Just release the channel. A dequeue can happen on a
14855 +                * transfer timeout. In the case of an AHB Error, the channel
14856 +                * was forced to halt because there's no way to gracefully
14857 +                * recover.
14858 +                */
14859 +               release_channel(hcd, hc, qtd, hc->halt_status);
14860 +               return;
14861 +       }
14862 +
14863 +       /* Read the HCINTn register to determine the cause for the halt. */
14864 +       hcint.d32 = dwc_read_reg32(&hc_regs->hcint);
14865 +       hcintmsk.d32 = dwc_read_reg32(&hc_regs->hcintmsk);
14866 +
14867 +       if (hcint.b.xfercomp) {
14868 +               /** @todo This is here because of a possible hardware bug.  Spec
14869 +                * says that on SPLIT-ISOC OUT transfers in DMA mode that a HALT
14870 +                * interrupt w/ACK bit set should occur, but I only see the
14871 +                * XFERCOMP bit, even with it masked out.  This is a workaround
14872 +                * for that behavior.  Should fix this when hardware is fixed.
14873 +                */
14874 +               if (hc->ep_type == DWC_OTG_EP_TYPE_ISOC && !hc->ep_is_in) {
14875 +                       handle_hc_ack_intr(hcd, hc, hc_regs, qtd);
14876 +               }
14877 +               handle_hc_xfercomp_intr(hcd, hc, hc_regs, qtd);
14878 +       } else if (hcint.b.stall) {
14879 +               handle_hc_stall_intr(hcd, hc, hc_regs, qtd);
14880 +       } else if (hcint.b.xacterr) {
14881 +               if (out_nak_enh) {
14882 +                       if (hcint.b.nyet || hcint.b.nak || hcint.b.ack) {
14883 +                               printk(KERN_DEBUG "XactErr with NYET/NAK/ACK\n");
14884 +                               qtd->error_count = 0;
14885 +                       } else {
14886 +                               printk(KERN_DEBUG "XactErr without NYET/NAK/ACK\n");
14887 +                       }
14888 +               }
14889 +
14890 +               /*
14891 +                * Must handle xacterr before nak or ack. Could get a xacterr
14892 +                * at the same time as either of these on a BULK/CONTROL OUT
14893 +                * that started with a PING. The xacterr takes precedence.
14894 +                */
14895 +               handle_hc_xacterr_intr(hcd, hc, hc_regs, qtd);
14896 +       } else if (!out_nak_enh) {
14897 +               if (hcint.b.nyet) {
14898 +                       /*
14899 +                        * Must handle nyet before nak or ack. Could get a nyet at the
14900 +                        * same time as either of those on a BULK/CONTROL OUT that
14901 +                        * started with a PING. The nyet takes precedence.
14902 +                        */
14903 +                       handle_hc_nyet_intr(hcd, hc, hc_regs, qtd);
14904 +               } else if (hcint.b.bblerr) {
14905 +                       handle_hc_babble_intr(hcd, hc, hc_regs, qtd);
14906 +               } else if (hcint.b.frmovrun) {
14907 +                       handle_hc_frmovrun_intr(hcd, hc, hc_regs, qtd);
14908 +               } else if (hcint.b.nak && !hcintmsk.b.nak) {
14909 +                       /*
14910 +                        * If nak is not masked, it's because a non-split IN transfer
14911 +                        * is in an error state. In that case, the nak is handled by
14912 +                        * the nak interrupt handler, not here. Handle nak here for
14913 +                        * BULK/CONTROL OUT transfers, which halt on a NAK to allow
14914 +                        * rewinding the buffer pointer.
14915 +                        */
14916 +                       handle_hc_nak_intr(hcd, hc, hc_regs, qtd);
14917 +               } else if (hcint.b.ack && !hcintmsk.b.ack) {
14918 +                       /*
14919 +                        * If ack is not masked, it's because a non-split IN transfer
14920 +                        * is in an error state. In that case, the ack is handled by
14921 +                        * the ack interrupt handler, not here. Handle ack here for
14922 +                        * split transfers. Start splits halt on ACK.
14923 +                        */
14924 +                       handle_hc_ack_intr(hcd, hc, hc_regs, qtd);
14925 +               } else {
14926 +                       if (hc->ep_type == DWC_OTG_EP_TYPE_INTR ||
14927 +                           hc->ep_type == DWC_OTG_EP_TYPE_ISOC) {
14928 +                               /*
14929 +                                * A periodic transfer halted with no other channel
14930 +                                * interrupts set. Assume it was halted by the core
14931 +                                * because it could not be completed in its scheduled
14932 +                                * (micro)frame.
14933 +                                */
14934 +#ifdef DEBUG
14935 +                               DWC_PRINT("%s: Halt channel %d (assume incomplete periodic transfer)\n",
14936 +                                         __func__, hc->hc_num);
14937 +#endif
14938 +                               halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_PERIODIC_INCOMPLETE);
14939 +                       } else {
14940 +                               DWC_ERROR("%s: Channel %d, DMA Mode -- ChHltd set, but reason "
14941 +                                         "for halting is unknown, hcint 0x%08x, intsts 0x%08x\n",
14942 +                                         __func__, hc->hc_num, hcint.d32,
14943 +                                         dwc_read_reg32(&hcd->core_if->core_global_regs->gintsts));
14944 +                       }
14945 +               }
14946 +       } else {
14947 +               printk(KERN_DEBUG "NYET/NAK/ACK/other in non-error case, 0x%08x\n", hcint.d32);
14948 +       }
14949 +}
14950 +
14951 +/**
14952 + * Handles a host channel Channel Halted interrupt.
14953 + *
14954 + * In slave mode, this handler is called only when the driver specifically
14955 + * requests a halt. This occurs during handling other host channel interrupts
14956 + * (e.g. nak, xacterr, stall, nyet, etc.).
14957 + *
14958 + * In DMA mode, this is the interrupt that occurs when the core has finished
14959 + * processing a transfer on a channel. Other host channel interrupts (except
14960 + * ahberr) are disabled in DMA mode.
14961 + */
14962 +static int32_t handle_hc_chhltd_intr(dwc_otg_hcd_t *hcd,
14963 +                                    dwc_hc_t *hc,
14964 +                                    dwc_otg_hc_regs_t *hc_regs,
14965 +                                    dwc_otg_qtd_t *qtd)
14966 +{
14967 +       DWC_DEBUGPL(DBG_HCD, "--Host Channel %d Interrupt: "
14968 +                   "Channel Halted--\n", hc->hc_num);
14969 +
14970 +       if (hcd->core_if->dma_enable) {
14971 +               handle_hc_chhltd_intr_dma(hcd, hc, hc_regs, qtd);
14972 +       } else {
14973 +#ifdef DEBUG
14974 +               if (!halt_status_ok(hcd, hc, hc_regs, qtd)) {
14975 +                       return 1;
14976 +               }
14977 +#endif
14978 +               release_channel(hcd, hc, qtd, hc->halt_status);
14979 +       }
14980 +
14981 +       return 1;
14982 +}
14983 +
14984 +/** Handles interrupt for a specific Host Channel */
14985 +int32_t dwc_otg_hcd_handle_hc_n_intr(dwc_otg_hcd_t *dwc_otg_hcd, uint32_t num)
14986 +{
14987 +       int retval = 0;
14988 +       hcint_data_t hcint;
14989 +       hcintmsk_data_t hcintmsk;
14990 +       dwc_hc_t *hc;
14991 +       dwc_otg_hc_regs_t *hc_regs;
14992 +       dwc_otg_qtd_t *qtd;
14993 +
14994 +       DWC_DEBUGPL(DBG_HCDV, "--Host Channel Interrupt--, Channel %d\n", num);
14995 +
14996 +       hc = dwc_otg_hcd->hc_ptr_array[num];
14997 +       hc_regs = dwc_otg_hcd->core_if->host_if->hc_regs[num];
14998 +       qtd = list_entry(hc->qh->qtd_list.next, dwc_otg_qtd_t, qtd_list_entry);
14999 +
15000 +       hcint.d32 = dwc_read_reg32(&hc_regs->hcint);
15001 +       hcintmsk.d32 = dwc_read_reg32(&hc_regs->hcintmsk);
15002 +       DWC_DEBUGPL(DBG_HCDV, "  hcint 0x%08x, hcintmsk 0x%08x, hcint&hcintmsk 0x%08x\n",
15003 +                   hcint.d32, hcintmsk.d32, (hcint.d32 & hcintmsk.d32));
15004 +       hcint.d32 = hcint.d32 & hcintmsk.d32;
15005 +
15006 +       if (!dwc_otg_hcd->core_if->dma_enable) {
15007 +               if (hcint.b.chhltd && hcint.d32 != 0x2) {
15008 +                       hcint.b.chhltd = 0;
15009 +               }
15010 +       }
15011 +
15012 +       if (hcint.b.xfercomp) {
15013 +               retval |= handle_hc_xfercomp_intr(dwc_otg_hcd, hc, hc_regs, qtd);
15014 +               /*
15015 +                * If NYET occurred at same time as Xfer Complete, the NYET is
15016 +                * handled by the Xfer Complete interrupt handler. Don't want
15017 +                * to call the NYET interrupt handler in this case.
15018 +                */
15019 +               hcint.b.nyet = 0;
15020 +       }
15021 +       if (hcint.b.chhltd) {
15022 +               retval |= handle_hc_chhltd_intr(dwc_otg_hcd, hc, hc_regs, qtd);
15023 +       }
15024 +       if (hcint.b.ahberr) {
15025 +               retval |= handle_hc_ahberr_intr(dwc_otg_hcd, hc, hc_regs, qtd);
15026 +       }
15027 +       if (hcint.b.stall) {
15028 +               retval |= handle_hc_stall_intr(dwc_otg_hcd, hc, hc_regs, qtd);
15029 +       }
15030 +       if (hcint.b.nak) {
15031 +               retval |= handle_hc_nak_intr(dwc_otg_hcd, hc, hc_regs, qtd);
15032 +       }
15033 +       if (hcint.b.ack) {
15034 +               retval |= handle_hc_ack_intr(dwc_otg_hcd, hc, hc_regs, qtd);
15035 +       }
15036 +       if (hcint.b.nyet) {
15037 +               retval |= handle_hc_nyet_intr(dwc_otg_hcd, hc, hc_regs, qtd);
15038 +       }
15039 +       if (hcint.b.xacterr) {
15040 +               retval |= handle_hc_xacterr_intr(dwc_otg_hcd, hc, hc_regs, qtd);
15041 +       }
15042 +       if (hcint.b.bblerr) {
15043 +               retval |= handle_hc_babble_intr(dwc_otg_hcd, hc, hc_regs, qtd);
15044 +       }
15045 +       if (hcint.b.frmovrun) {
15046 +               retval |= handle_hc_frmovrun_intr(dwc_otg_hcd, hc, hc_regs, qtd);
15047 +       }
15048 +       if (hcint.b.datatglerr) {
15049 +               retval |= handle_hc_datatglerr_intr(dwc_otg_hcd, hc, hc_regs, qtd);
15050 +       }
15051 +
15052 +       return retval;
15053 +}
15054 +
15055 +#endif /* DWC_DEVICE_ONLY */
15056 --- /dev/null
15057 +++ b/drivers/usb/dwc_otg/dwc_otg_hcd_queue.c
15058 @@ -0,0 +1,684 @@
15059 +/* ==========================================================================
15060 + * $File: //dwh/usb_iip/dev/software/otg_ipmate/linux/drivers/dwc_otg_hcd_queue.c $
15061 + * $Revision: 1.5 $
15062 + * $Date: 2008-12-15 06:51:32 $
15063 + * $Change: 537387 $
15064 + *
15065 + * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
15066 + * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
15067 + * otherwise expressly agreed to in writing between Synopsys and you.
15068 + *
15069 + * The Software IS NOT an item of Licensed Software or Licensed Product under
15070 + * any End User Software License Agreement or Agreement for Licensed Product
15071 + * with Synopsys or any supplement thereto. You are permitted to use and
15072 + * redistribute this Software in source and binary forms, with or without
15073 + * modification, provided that redistributions of source code must retain this
15074 + * notice. You may not view, use, disclose, copy or distribute this file or
15075 + * any information contained herein except pursuant to this license grant from
15076 + * Synopsys. If you do not agree with this notice, including the disclaimer
15077 + * below, then you are not authorized to use the Software.
15078 + *
15079 + * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
15080 + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
15081 + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
15082 + * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
15083 + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
15084 + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
15085 + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
15086 + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
15087 + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
15088 + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
15089 + * DAMAGE.
15090 + * ========================================================================== */
15091 +#ifndef DWC_DEVICE_ONLY
15092 +
15093 +/**
15094 + * @file
15095 + *
15096 + * This file contains the functions to manage Queue Heads and Queue
15097 + * Transfer Descriptors.
15098 + */
15099 +#include <linux/kernel.h>
15100 +#include <linux/module.h>
15101 +#include <linux/moduleparam.h>
15102 +#include <linux/init.h>
15103 +#include <linux/device.h>
15104 +#include <linux/errno.h>
15105 +#include <linux/list.h>
15106 +#include <linux/interrupt.h>
15107 +#include <linux/string.h>
15108 +#include <linux/dma-mapping.h>
15109 +
15110 +#include "dwc_otg_driver.h"
15111 +#include "dwc_otg_hcd.h"
15112 +#include "dwc_otg_regs.h"
15113 +
15114 +/**
15115 + * This function allocates and initializes a QH.
15116 + *
15117 + * @param hcd The HCD state structure for the DWC OTG controller.
15118 + * @param[in] urb Holds the information about the device/endpoint that we need
15119 + * to initialize the QH.
15120 + *
15121 + * @return Returns pointer to the newly allocated QH, or NULL on error. */
15122 +dwc_otg_qh_t *dwc_otg_hcd_qh_create (dwc_otg_hcd_t *hcd, struct urb *urb)
15123 +{
15124 +       dwc_otg_qh_t *qh;
15125 +
15126 +       /* Allocate memory */
15127 +       /** @todo add memflags argument */
15128 +       qh = dwc_otg_hcd_qh_alloc ();
15129 +       if (qh == NULL) {
15130 +               return NULL;
15131 +       }
15132 +
15133 +       dwc_otg_hcd_qh_init (hcd, qh, urb);
15134 +       return qh;
15135 +}
15136 +
15137 +/** Free each QTD in the QH's QTD-list then free the QH.  QH should already be
15138 + * removed from a list.  QTD list should already be empty if called from URB
15139 + * Dequeue.
15140 + *
15141 + * @param[in] hcd HCD instance.
15142 + * @param[in] qh The QH to free.
15143 + */
15144 +void dwc_otg_hcd_qh_free (dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh)
15145 +{
15146 +       dwc_otg_qtd_t *qtd;
15147 +       struct list_head *pos;
15148 +       unsigned long flags;
15149 +
15150 +       /* Free each QTD in the QTD list */
15151 +       SPIN_LOCK_IRQSAVE(&hcd->lock, flags)
15152 +       for (pos = qh->qtd_list.next;
15153 +            pos != &qh->qtd_list;
15154 +            pos = qh->qtd_list.next)
15155 +       {
15156 +               list_del (pos);
15157 +               qtd = dwc_list_to_qtd (pos);
15158 +               dwc_otg_hcd_qtd_free (qtd);
15159 +       }
15160 +       SPIN_UNLOCK_IRQRESTORE(&hcd->lock, flags)
15161 +
15162 +       if (qh->dw_align_buf) {
15163 +               dma_free_coherent((dwc_otg_hcd_to_hcd(hcd))->self.controller,
15164 +                                 hcd->core_if->core_params->max_transfer_size,
15165 +                                 qh->dw_align_buf,
15166 +                                 qh->dw_align_buf_dma);
15167 +       }
15168 +
15169 +       kfree (qh);
15170 +       return;
15171 +}
15172 +
15173 +/** Initializes a QH structure.
15174 + *
15175 + * @param[in] hcd The HCD state structure for the DWC OTG controller.
15176 + * @param[in] qh The QH to init.
15177 + * @param[in] urb Holds the information about the device/endpoint that we need
15178 + * to initialize the QH. */
15179 +#define SCHEDULE_SLOP 10
15180 +void dwc_otg_hcd_qh_init(dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh, struct urb *urb)
15181 +{
15182 +       char *speed, *type;
15183 +       memset (qh, 0, sizeof (dwc_otg_qh_t));
15184 +
15185 +       /* Initialize QH */
15186 +       switch (usb_pipetype(urb->pipe)) {
15187 +       case PIPE_CONTROL:
15188 +               qh->ep_type = USB_ENDPOINT_XFER_CONTROL;
15189 +               break;
15190 +       case PIPE_BULK:
15191 +               qh->ep_type = USB_ENDPOINT_XFER_BULK;
15192 +               break;
15193 +       case PIPE_ISOCHRONOUS:
15194 +               qh->ep_type = USB_ENDPOINT_XFER_ISOC;
15195 +               break;
15196 +       case PIPE_INTERRUPT:
15197 +               qh->ep_type = USB_ENDPOINT_XFER_INT;
15198 +               break;
15199 +       }
15200 +
15201 +       qh->ep_is_in = usb_pipein(urb->pipe) ? 1 : 0;
15202 +
15203 +       qh->data_toggle = DWC_OTG_HC_PID_DATA0;
15204 +       qh->maxp = usb_maxpacket(urb->dev, urb->pipe, !(usb_pipein(urb->pipe)));
15205 +       INIT_LIST_HEAD(&qh->qtd_list);
15206 +       INIT_LIST_HEAD(&qh->qh_list_entry);
15207 +       qh->channel = NULL;
15208 +
15209 +       /* FS/LS Enpoint on HS Hub
15210 +        * NOT virtual root hub */
15211 +       qh->do_split = 0;
15212 +       if (((urb->dev->speed == USB_SPEED_LOW) ||
15213 +            (urb->dev->speed == USB_SPEED_FULL)) &&
15214 +            (urb->dev->tt) && (urb->dev->tt->hub) && (urb->dev->tt->hub->devnum != 1))
15215 +       {
15216 +               DWC_DEBUGPL(DBG_HCD, "QH init: EP %d: TT found at hub addr %d, for port %d\n",
15217 +                          usb_pipeendpoint(urb->pipe), urb->dev->tt->hub->devnum,
15218 +                          urb->dev->ttport);
15219 +               qh->do_split = 1;
15220 +       }
15221 +
15222 +       if (qh->ep_type == USB_ENDPOINT_XFER_INT ||
15223 +           qh->ep_type == USB_ENDPOINT_XFER_ISOC) {
15224 +               /* Compute scheduling parameters once and save them. */
15225 +               hprt0_data_t hprt;
15226 +
15227 +               /** @todo Account for split transfers in the bus time. */
15228 +               int bytecount = dwc_hb_mult(qh->maxp) * dwc_max_packet(qh->maxp);
15229 +
15230 +               /* FIXME: work-around patch by Steven */
15231 +               qh->usecs = NS_TO_US(usb_calc_bus_time(urb->dev->speed,
15232 +                                              usb_pipein(urb->pipe),
15233 +                                              (qh->ep_type == USB_ENDPOINT_XFER_ISOC),
15234 +                                              bytecount));
15235 +
15236 +               /* Start in a slightly future (micro)frame. */
15237 +               qh->sched_frame = dwc_frame_num_inc(hcd->frame_number,
15238 +                                                    SCHEDULE_SLOP);
15239 +               qh->interval = urb->interval;
15240 +#if 0
15241 +               /* Increase interrupt polling rate for debugging. */
15242 +               if (qh->ep_type == USB_ENDPOINT_XFER_INT) {
15243 +                       qh->interval = 8;
15244 +               }
15245 +#endif
15246 +               hprt.d32 = dwc_read_reg32(hcd->core_if->host_if->hprt0);
15247 +               if ((hprt.b.prtspd == DWC_HPRT0_PRTSPD_HIGH_SPEED) &&
15248 +                   ((urb->dev->speed == USB_SPEED_LOW) ||
15249 +                    (urb->dev->speed == USB_SPEED_FULL))) {
15250 +                       qh->interval *= 8;
15251 +                       qh->sched_frame |= 0x7;
15252 +                       qh->start_split_frame = qh->sched_frame;
15253 +               }
15254 +
15255 +       }
15256 +
15257 +       DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD QH Initialized\n");
15258 +       DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD QH  - qh = %p\n", qh);
15259 +       DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD QH  - Device Address = %d\n",
15260 +                   urb->dev->devnum);
15261 +       DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD QH  - Endpoint %d, %s\n",
15262 +                   usb_pipeendpoint(urb->pipe),
15263 +                   usb_pipein(urb->pipe) == USB_DIR_IN ? "IN" : "OUT");
15264 +
15265 +       switch(urb->dev->speed) {
15266 +       case USB_SPEED_LOW:
15267 +               speed = "low";
15268 +               break;
15269 +       case USB_SPEED_FULL:
15270 +               speed = "full";
15271 +               break;
15272 +       case USB_SPEED_HIGH:
15273 +               speed = "high";
15274 +               break;
15275 +       default:
15276 +               speed = "?";
15277 +               break;
15278 +       }
15279 +       DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD QH  - Speed = %s\n", speed);
15280 +
15281 +       switch (qh->ep_type) {
15282 +       case USB_ENDPOINT_XFER_ISOC:
15283 +               type = "isochronous";
15284 +               break;
15285 +       case USB_ENDPOINT_XFER_INT:
15286 +               type = "interrupt";
15287 +               break;
15288 +       case USB_ENDPOINT_XFER_CONTROL:
15289 +               type = "control";
15290 +               break;
15291 +       case USB_ENDPOINT_XFER_BULK:
15292 +               type = "bulk";
15293 +               break;
15294 +       default:
15295 +               type = "?";
15296 +               break;
15297 +       }
15298 +       DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD QH  - Type = %s\n",type);
15299 +
15300 +#ifdef DEBUG
15301 +       if (qh->ep_type == USB_ENDPOINT_XFER_INT) {
15302 +               DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD QH - usecs = %d\n",
15303 +                           qh->usecs);
15304 +               DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD QH - interval = %d\n",
15305 +                           qh->interval);
15306 +       }
15307 +#endif
15308 +       qh->dw_align_buf = NULL;
15309 +       return;
15310 +}
15311 +
15312 +/**
15313 + * Checks that a channel is available for a periodic transfer.
15314 + *
15315 + * @return 0 if successful, negative error code otherise.
15316 + */
15317 +static int periodic_channel_available(dwc_otg_hcd_t *hcd)
15318 +{
15319 +       /*
15320 +        * Currently assuming that there is a dedicated host channnel for each
15321 +        * periodic transaction plus at least one host channel for
15322 +        * non-periodic transactions.
15323 +        */
15324 +       int status;
15325 +       int num_channels;
15326 +
15327 +       num_channels = hcd->core_if->core_params->host_channels;
15328 +       if ((hcd->periodic_channels + hcd->non_periodic_channels < num_channels) &&
15329 +           (hcd->periodic_channels < num_channels - 1)) {
15330 +               status = 0;
15331 +       }
15332 +       else {
15333 +               DWC_NOTICE("%s: Total channels: %d, Periodic: %d, Non-periodic: %d\n",
15334 +                          __func__, num_channels, hcd->periodic_channels,
15335 +                          hcd->non_periodic_channels);
15336 +               status = -ENOSPC;
15337 +       }
15338 +
15339 +       return status;
15340 +}
15341 +
15342 +/**
15343 + * Checks that there is sufficient bandwidth for the specified QH in the
15344 + * periodic schedule. For simplicity, this calculation assumes that all the
15345 + * transfers in the periodic schedule may occur in the same (micro)frame.
15346 + *
15347 + * @param hcd The HCD state structure for the DWC OTG controller.
15348 + * @param qh QH containing periodic bandwidth required.
15349 + *
15350 + * @return 0 if successful, negative error code otherwise.
15351 + */
15352 +static int check_periodic_bandwidth(dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh)
15353 +{
15354 +       int             status;
15355 +       uint16_t        max_claimed_usecs;
15356 +
15357 +       status = 0;
15358 +
15359 +       if (hcd->core_if->core_params->speed == DWC_SPEED_PARAM_HIGH) {
15360 +               /*
15361 +                * High speed mode.
15362 +                * Max periodic usecs is 80% x 125 usec = 100 usec.
15363 +                */
15364 +               max_claimed_usecs = 100 - qh->usecs;
15365 +       } else {
15366 +               /*
15367 +                * Full speed mode.
15368 +                * Max periodic usecs is 90% x 1000 usec = 900 usec.
15369 +                */
15370 +               max_claimed_usecs = 900 - qh->usecs;
15371 +       }
15372 +
15373 +       if (hcd->periodic_usecs > max_claimed_usecs) {
15374 +               DWC_NOTICE("%s: already claimed usecs %d, required usecs %d\n",
15375 +                          __func__, hcd->periodic_usecs, qh->usecs);
15376 +               status = -ENOSPC;
15377 +       }
15378 +
15379 +       return status;
15380 +}
15381 +
15382 +/**
15383 + * Checks that the max transfer size allowed in a host channel is large enough
15384 + * to handle the maximum data transfer in a single (micro)frame for a periodic
15385 + * transfer.
15386 + *
15387 + * @param hcd The HCD state structure for the DWC OTG controller.
15388 + * @param qh QH for a periodic endpoint.
15389 + *
15390 + * @return 0 if successful, negative error code otherwise.
15391 + */
15392 +static int check_max_xfer_size(dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh)
15393 +{
15394 +       int             status;
15395 +       uint32_t        max_xfer_size;
15396 +       uint32_t        max_channel_xfer_size;
15397 +
15398 +       status = 0;
15399 +
15400 +       max_xfer_size = dwc_max_packet(qh->maxp) * dwc_hb_mult(qh->maxp);
15401 +       max_channel_xfer_size = hcd->core_if->core_params->max_transfer_size;
15402 +
15403 +       if (max_xfer_size > max_channel_xfer_size) {
15404 +               DWC_NOTICE("%s: Periodic xfer length %d > "
15405 +                           "max xfer length for channel %d\n",
15406 +                           __func__, max_xfer_size, max_channel_xfer_size);
15407 +               status = -ENOSPC;
15408 +       }
15409 +
15410 +       return status;
15411 +}
15412 +
15413 +/**
15414 + * Schedules an interrupt or isochronous transfer in the periodic schedule.
15415 + *
15416 + * @param hcd The HCD state structure for the DWC OTG controller.
15417 + * @param qh QH for the periodic transfer. The QH should already contain the
15418 + * scheduling information.
15419 + *
15420 + * @return 0 if successful, negative error code otherwise.
15421 + */
15422 +static int schedule_periodic(dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh)
15423 +{
15424 +       int status = 0;
15425 +
15426 +       status = periodic_channel_available(hcd);
15427 +       if (status) {
15428 +               DWC_NOTICE("%s: No host channel available for periodic "
15429 +                          "transfer.\n", __func__);
15430 +               return status;
15431 +       }
15432 +
15433 +       status = check_periodic_bandwidth(hcd, qh);
15434 +       if (status) {
15435 +               DWC_NOTICE("%s: Insufficient periodic bandwidth for "
15436 +                          "periodic transfer.\n", __func__);
15437 +               return status;
15438 +       }
15439 +
15440 +       status = check_max_xfer_size(hcd, qh);
15441 +       if (status) {
15442 +               DWC_NOTICE("%s: Channel max transfer size too small "
15443 +                           "for periodic transfer.\n", __func__);
15444 +               return status;
15445 +       }
15446 +
15447 +       /* Always start in the inactive schedule. */
15448 +       list_add_tail(&qh->qh_list_entry, &hcd->periodic_sched_inactive);
15449 +
15450 +       /* Reserve the periodic channel. */
15451 +       hcd->periodic_channels++;
15452 +
15453 +       /* Update claimed usecs per (micro)frame. */
15454 +       hcd->periodic_usecs += qh->usecs;
15455 +
15456 +       /* Update average periodic bandwidth claimed and # periodic reqs for usbfs. */
15457 +       hcd_to_bus(dwc_otg_hcd_to_hcd(hcd))->bandwidth_allocated += qh->usecs / qh->interval;
15458 +       if (qh->ep_type == USB_ENDPOINT_XFER_INT) {
15459 +               hcd_to_bus(dwc_otg_hcd_to_hcd(hcd))->bandwidth_int_reqs++;
15460 +               DWC_DEBUGPL(DBG_HCD, "Scheduled intr: qh %p, usecs %d, period %d\n",
15461 +                           qh, qh->usecs, qh->interval);
15462 +       } else {
15463 +               hcd_to_bus(dwc_otg_hcd_to_hcd(hcd))->bandwidth_isoc_reqs++;
15464 +               DWC_DEBUGPL(DBG_HCD, "Scheduled isoc: qh %p, usecs %d, period %d\n",
15465 +                           qh, qh->usecs, qh->interval);
15466 +       }
15467 +
15468 +       return status;
15469 +}
15470 +
15471 +/**
15472 + * This function adds a QH to either the non periodic or periodic schedule if
15473 + * it is not already in the schedule. If the QH is already in the schedule, no
15474 + * action is taken.
15475 + *
15476 + * @return 0 if successful, negative error code otherwise.
15477 + */
15478 +int dwc_otg_hcd_qh_add (dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh)
15479 +{
15480 +       unsigned long flags;
15481 +       int status = 0;
15482 +
15483 +       SPIN_LOCK_IRQSAVE(&hcd->lock, flags)
15484 +
15485 +       if (!list_empty(&qh->qh_list_entry)) {
15486 +               /* QH already in a schedule. */
15487 +               goto done;
15488 +       }
15489 +
15490 +       /* Add the new QH to the appropriate schedule */
15491 +       if (dwc_qh_is_non_per(qh)) {
15492 +               /* Always start in the inactive schedule. */
15493 +               list_add_tail(&qh->qh_list_entry, &hcd->non_periodic_sched_inactive);
15494 +       } else {
15495 +               status = schedule_periodic(hcd, qh);
15496 +       }
15497 +
15498 + done:
15499 +       SPIN_UNLOCK_IRQRESTORE(&hcd->lock, flags)
15500 +
15501 +       return status;
15502 +}
15503 +
15504 +/**
15505 + * Removes an interrupt or isochronous transfer from the periodic schedule.
15506 + *
15507 + * @param hcd The HCD state structure for the DWC OTG controller.
15508 + * @param qh QH for the periodic transfer.
15509 + */
15510 +static void deschedule_periodic(dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh)
15511 +{
15512 +       list_del_init(&qh->qh_list_entry);
15513 +
15514 +       /* Release the periodic channel reservation. */
15515 +       hcd->periodic_channels--;
15516 +
15517 +       /* Update claimed usecs per (micro)frame. */
15518 +       hcd->periodic_usecs -= qh->usecs;
15519 +
15520 +       /* Update average periodic bandwidth claimed and # periodic reqs for usbfs. */
15521 +       hcd_to_bus(dwc_otg_hcd_to_hcd(hcd))->bandwidth_allocated -= qh->usecs / qh->interval;
15522 +
15523 +       if (qh->ep_type == USB_ENDPOINT_XFER_INT) {
15524 +               hcd_to_bus(dwc_otg_hcd_to_hcd(hcd))->bandwidth_int_reqs--;
15525 +               DWC_DEBUGPL(DBG_HCD, "Descheduled intr: qh %p, usecs %d, period %d\n",
15526 +                           qh, qh->usecs, qh->interval);
15527 +       } else {
15528 +               hcd_to_bus(dwc_otg_hcd_to_hcd(hcd))->bandwidth_isoc_reqs--;
15529 +               DWC_DEBUGPL(DBG_HCD, "Descheduled isoc: qh %p, usecs %d, period %d\n",
15530 +                           qh, qh->usecs, qh->interval);
15531 +       }
15532 +}
15533 +
15534 +/**
15535 + * Removes a QH from either the non-periodic or periodic schedule.  Memory is
15536 + * not freed.
15537 + *
15538 + * @param[in] hcd The HCD state structure.
15539 + * @param[in] qh QH to remove from schedule. */
15540 +void dwc_otg_hcd_qh_remove (dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh)
15541 +{
15542 +       unsigned long flags;
15543 +
15544 +       SPIN_LOCK_IRQSAVE(&hcd->lock, flags);
15545 +
15546 +       if (list_empty(&qh->qh_list_entry)) {
15547 +               /* QH is not in a schedule. */
15548 +               goto done;
15549 +       }
15550 +
15551 +       if (dwc_qh_is_non_per(qh)) {
15552 +               if (hcd->non_periodic_qh_ptr == &qh->qh_list_entry) {
15553 +                       hcd->non_periodic_qh_ptr = hcd->non_periodic_qh_ptr->next;
15554 +               }
15555 +               list_del_init(&qh->qh_list_entry);
15556 +       } else {
15557 +               deschedule_periodic(hcd, qh);
15558 +       }
15559 +
15560 + done:
15561 +       SPIN_UNLOCK_IRQRESTORE(&hcd->lock, flags)
15562 +}
15563 +
15564 +/**
15565 + * Deactivates a QH. For non-periodic QHs, removes the QH from the active
15566 + * non-periodic schedule. The QH is added to the inactive non-periodic
15567 + * schedule if any QTDs are still attached to the QH.
15568 + *
15569 + * For periodic QHs, the QH is removed from the periodic queued schedule. If
15570 + * there are any QTDs still attached to the QH, the QH is added to either the
15571 + * periodic inactive schedule or the periodic ready schedule and its next
15572 + * scheduled frame is calculated. The QH is placed in the ready schedule if
15573 + * the scheduled frame has been reached already. Otherwise it's placed in the
15574 + * inactive schedule. If there are no QTDs attached to the QH, the QH is
15575 + * completely removed from the periodic schedule.
15576 + */
15577 +void dwc_otg_hcd_qh_deactivate(dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh, int sched_next_periodic_split)
15578 +{
15579 +       unsigned long flags;
15580 +       SPIN_LOCK_IRQSAVE(&hcd->lock, flags);
15581 +
15582 +       if (dwc_qh_is_non_per(qh)) {
15583 +               dwc_otg_hcd_qh_remove(hcd, qh);
15584 +               if (!list_empty(&qh->qtd_list)) {
15585 +                       /* Add back to inactive non-periodic schedule. */
15586 +                       dwc_otg_hcd_qh_add(hcd, qh);
15587 +               }
15588 +       } else {
15589 +               uint16_t frame_number = dwc_otg_hcd_get_frame_number(dwc_otg_hcd_to_hcd(hcd));
15590 +
15591 +               if (qh->do_split) {
15592 +                       /* Schedule the next continuing periodic split transfer */
15593 +                       if (sched_next_periodic_split) {
15594 +
15595 +                               qh->sched_frame = frame_number;
15596 +                               if (dwc_frame_num_le(frame_number,
15597 +                                                    dwc_frame_num_inc(qh->start_split_frame, 1))) {
15598 +                                       /*
15599 +                                        * Allow one frame to elapse after start
15600 +                                        * split microframe before scheduling
15601 +                                        * complete split, but DONT if we are
15602 +                                        * doing the next start split in the
15603 +                                        * same frame for an ISOC out.
15604 +                                        */
15605 +                                       if ((qh->ep_type != USB_ENDPOINT_XFER_ISOC) || (qh->ep_is_in != 0)) {
15606 +                                               qh->sched_frame = dwc_frame_num_inc(qh->sched_frame, 1);
15607 +                                       }
15608 +                               }
15609 +                       } else {
15610 +                               qh->sched_frame = dwc_frame_num_inc(qh->start_split_frame,
15611 +                                                                    qh->interval);
15612 +                               if (dwc_frame_num_le(qh->sched_frame, frame_number)) {
15613 +                                       qh->sched_frame = frame_number;
15614 +                               }
15615 +                               qh->sched_frame |= 0x7;
15616 +                               qh->start_split_frame = qh->sched_frame;
15617 +                       }
15618 +               } else {
15619 +                       qh->sched_frame = dwc_frame_num_inc(qh->sched_frame, qh->interval);
15620 +                       if (dwc_frame_num_le(qh->sched_frame, frame_number)) {
15621 +                               qh->sched_frame = frame_number;
15622 +                       }
15623 +               }
15624 +
15625 +               if (list_empty(&qh->qtd_list)) {
15626 +                       dwc_otg_hcd_qh_remove(hcd, qh);
15627 +               } else {
15628 +                       /*
15629 +                        * Remove from periodic_sched_queued and move to
15630 +                        * appropriate queue.
15631 +                        */
15632 +                       if (qh->sched_frame == frame_number) {
15633 +                               list_move(&qh->qh_list_entry,
15634 +                                         &hcd->periodic_sched_ready);
15635 +                       } else {
15636 +                               list_move(&qh->qh_list_entry,
15637 +                                         &hcd->periodic_sched_inactive);
15638 +                       }
15639 +               }
15640 +       }
15641 +
15642 +       SPIN_UNLOCK_IRQRESTORE(&hcd->lock, flags);
15643 +}
15644 +
15645 +/**
15646 + * This function allocates and initializes a QTD.
15647 + *
15648 + * @param[in] urb The URB to create a QTD from.  Each URB-QTD pair will end up
15649 + * pointing to each other so each pair should have a unique correlation.
15650 + *
15651 + * @return Returns pointer to the newly allocated QTD, or NULL on error. */
15652 +dwc_otg_qtd_t *dwc_otg_hcd_qtd_create (struct urb *urb)
15653 +{
15654 +       dwc_otg_qtd_t *qtd;
15655 +
15656 +       qtd = dwc_otg_hcd_qtd_alloc ();
15657 +       if (qtd == NULL) {
15658 +               return NULL;
15659 +       }
15660 +
15661 +       dwc_otg_hcd_qtd_init (qtd, urb);
15662 +       return qtd;
15663 +}
15664 +
15665 +/**
15666 + * Initializes a QTD structure.
15667 + *
15668 + * @param[in] qtd The QTD to initialize.
15669 + * @param[in] urb The URB to use for initialization.  */
15670 +void dwc_otg_hcd_qtd_init (dwc_otg_qtd_t *qtd, struct urb *urb)
15671 +{
15672 +       memset (qtd, 0, sizeof (dwc_otg_qtd_t));
15673 +       qtd->urb = urb;
15674 +       if (usb_pipecontrol(urb->pipe)) {
15675 +               /*
15676 +                * The only time the QTD data toggle is used is on the data
15677 +                * phase of control transfers. This phase always starts with
15678 +                * DATA1.
15679 +                */
15680 +               qtd->data_toggle = DWC_OTG_HC_PID_DATA1;
15681 +               qtd->control_phase = DWC_OTG_CONTROL_SETUP;
15682 +       }
15683 +
15684 +       /* start split */
15685 +       qtd->complete_split = 0;
15686 +       qtd->isoc_split_pos = DWC_HCSPLIT_XACTPOS_ALL;
15687 +       qtd->isoc_split_offset = 0;
15688 +
15689 +       /* Store the qtd ptr in the urb to reference what QTD. */
15690 +       urb->hcpriv = qtd;
15691 +       return;
15692 +}
15693 +
15694 +/**
15695 + * This function adds a QTD to the QTD-list of a QH.  It will find the correct
15696 + * QH to place the QTD into.  If it does not find a QH, then it will create a
15697 + * new QH. If the QH to which the QTD is added is not currently scheduled, it
15698 + * is placed into the proper schedule based on its EP type.
15699 + *
15700 + * @param[in] qtd The QTD to add
15701 + * @param[in] dwc_otg_hcd The DWC HCD structure
15702 + *
15703 + * @return 0 if successful, negative error code otherwise.
15704 + */
15705 +int dwc_otg_hcd_qtd_add (dwc_otg_qtd_t *qtd,
15706 +                        dwc_otg_hcd_t *dwc_otg_hcd)
15707 +{
15708 +       struct usb_host_endpoint *ep;
15709 +       dwc_otg_qh_t *qh;
15710 +       unsigned long flags;
15711 +       int retval = 0;
15712 +
15713 +       struct urb *urb = qtd->urb;
15714 +
15715 +       SPIN_LOCK_IRQSAVE(&dwc_otg_hcd->lock, flags);
15716 +
15717 +       /*
15718 +        * Get the QH which holds the QTD-list to insert to. Create QH if it
15719 +        * doesn't exist.
15720 +        */
15721 +       ep = dwc_urb_to_endpoint(urb);
15722 +       qh = (dwc_otg_qh_t *)ep->hcpriv;
15723 +       if (qh == NULL) {
15724 +               qh = dwc_otg_hcd_qh_create (dwc_otg_hcd, urb);
15725 +               if (qh == NULL) {
15726 +                       goto done;
15727 +               }
15728 +               ep->hcpriv = qh;
15729 +       }
15730 +
15731 +       retval = dwc_otg_hcd_qh_add(dwc_otg_hcd, qh);
15732 +       if (retval == 0) {
15733 +               list_add_tail(&qtd->qtd_list_entry, &qh->qtd_list);
15734 +       }
15735 +
15736 + done:
15737 +       SPIN_UNLOCK_IRQRESTORE(&dwc_otg_hcd->lock, flags);
15738 +
15739 +       return retval;
15740 +}
15741 +
15742 +#endif /* DWC_DEVICE_ONLY */
15743 --- /dev/null
15744 +++ b/drivers/usb/dwc_otg/dwc_otg_pcd.c
15745 @@ -0,0 +1,2523 @@
15746 +/* ==========================================================================
15747 + * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_pcd.c $
15748 + * $Revision: 1.5 $
15749 + * $Date: 2008-11-27 09:21:25 $
15750 + * $Change: 1115682 $
15751 + *
15752 + * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
15753 + * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
15754 + * otherwise expressly agreed to in writing between Synopsys and you.
15755 + *
15756 + * The Software IS NOT an item of Licensed Software or Licensed Product under
15757 + * any End User Software License Agreement or Agreement for Licensed Product
15758 + * with Synopsys or any supplement thereto. You are permitted to use and
15759 + * redistribute this Software in source and binary forms, with or without
15760 + * modification, provided that redistributions of source code must retain this
15761 + * notice. You may not view, use, disclose, copy or distribute this file or
15762 + * any information contained herein except pursuant to this license grant from
15763 + * Synopsys. If you do not agree with this notice, including the disclaimer
15764 + * below, then you are not authorized to use the Software.
15765 + *
15766 + * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
15767 + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
15768 + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
15769 + * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
15770 + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
15771 + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
15772 + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
15773 + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
15774 + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
15775 + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
15776 + * DAMAGE.
15777 + * ========================================================================== */
15778 +#ifndef DWC_HOST_ONLY
15779 +
15780 +/** @file
15781 + * This file implements the Peripheral Controller Driver.
15782 + *
15783 + * The Peripheral Controller Driver (PCD) is responsible for
15784 + * translating requests from the Function Driver into the appropriate
15785 + * actions on the DWC_otg controller. It isolates the Function Driver
15786 + * from the specifics of the controller by providing an API to the
15787 + * Function Driver.
15788 + *
15789 + * The Peripheral Controller Driver for Linux will implement the
15790 + * Gadget API, so that the existing Gadget drivers can be used.
15791 + * (Gadget Driver is the Linux terminology for a Function Driver.)
15792 + *
15793 + * The Linux Gadget API is defined in the header file
15794 + * <code><linux/usb_gadget.h></code>.  The USB EP operations API is
15795 + * defined in the structure <code>usb_ep_ops</code> and the USB
15796 + * Controller API is defined in the structure
15797 + * <code>usb_gadget_ops</code>.
15798 + *
15799 + * An important function of the PCD is managing interrupts generated
15800 + * by the DWC_otg controller. The implementation of the DWC_otg device
15801 + * mode interrupt service routines is in dwc_otg_pcd_intr.c.
15802 + *
15803 + * @todo Add Device Mode test modes (Test J mode, Test K mode, etc).
15804 + * @todo Does it work when the request size is greater than DEPTSIZ
15805 + * transfer size
15806 + *
15807 + */
15808 +
15809 +
15810 +#include <linux/kernel.h>
15811 +#include <linux/module.h>
15812 +#include <linux/moduleparam.h>
15813 +#include <linux/init.h>
15814 +#include <linux/device.h>
15815 +#include <linux/errno.h>
15816 +#include <linux/list.h>
15817 +#include <linux/interrupt.h>
15818 +#include <linux/string.h>
15819 +#include <linux/dma-mapping.h>
15820 +#include <linux/version.h>
15821 +
15822 +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,21)
15823 +# include <linux/usb/ch9.h>
15824 +#else
15825 +# include <linux/usb_ch9.h>
15826 +#endif
15827 +
15828 +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,24)
15829 +#include <linux/usb/gadget.h>
15830 +#else
15831 +#include <linux/usb_gadget.h>
15832 +#endif
15833 +
15834 +#include "dwc_otg_driver.h"
15835 +#include "dwc_otg_pcd.h"
15836 +
15837 +
15838 +/**
15839 + * Static PCD pointer for use in usb_gadget_register_driver and
15840 + * usb_gadget_unregister_driver.  Initialized in dwc_otg_pcd_init.
15841 + */
15842 +static  dwc_otg_pcd_t *s_pcd = 0;
15843 +
15844 +
15845 +/* Display the contents of the buffer */
15846 +extern void dump_msg(const u8 *buf, unsigned int length);
15847 +
15848 +
15849 +/**
15850 + * This function completes a request.  It call's the request call back.
15851 + */
15852 +void dwc_otg_request_done(dwc_otg_pcd_ep_t *ep, dwc_otg_pcd_request_t *req,
15853 +                                 int status)
15854 +{
15855 +       unsigned stopped = ep->stopped;
15856 +
15857 +       DWC_DEBUGPL(DBG_PCDV, "%s(%p)\n", __func__, ep);
15858 +       list_del_init(&req->queue);
15859 +
15860 +       if (req->req.status == -EINPROGRESS) {
15861 +               req->req.status = status;
15862 +       } else {
15863 +               status = req->req.status;
15864 +       }
15865 +
15866 +       /* don't modify queue heads during completion callback */
15867 +       ep->stopped = 1;
15868 +       SPIN_UNLOCK(&ep->pcd->lock);
15869 +       req->req.complete(&ep->ep, &req->req);
15870 +       SPIN_LOCK(&ep->pcd->lock);
15871 +
15872 +       if (ep->pcd->request_pending > 0) {
15873 +               --ep->pcd->request_pending;
15874 +       }
15875 +
15876 +       ep->stopped = stopped;
15877 +}
15878 +
15879 +/**
15880 + * This function terminates all the requsts in the EP request queue.
15881 + */
15882 +void dwc_otg_request_nuke(dwc_otg_pcd_ep_t *ep)
15883 +{
15884 +       dwc_otg_pcd_request_t *req;
15885 +
15886 +       ep->stopped = 1;
15887 +
15888 +       /* called with irqs blocked?? */
15889 +       while (!list_empty(&ep->queue)) {
15890 +               req = list_entry(ep->queue.next, dwc_otg_pcd_request_t,
15891 +                                queue);
15892 +               dwc_otg_request_done(ep, req, -ESHUTDOWN);
15893 +       }
15894 +}
15895 +
15896 +/* USB Endpoint Operations */
15897 +/*
15898 + * The following sections briefly describe the behavior of the Gadget
15899 + * API endpoint operations implemented in the DWC_otg driver
15900 + * software. Detailed descriptions of the generic behavior of each of
15901 + * these functions can be found in the Linux header file
15902 + * include/linux/usb_gadget.h.
15903 + *
15904 + * The Gadget API provides wrapper functions for each of the function
15905 + * pointers defined in usb_ep_ops. The Gadget Driver calls the wrapper
15906 + * function, which then calls the underlying PCD function. The
15907 + * following sections are named according to the wrapper
15908 + * functions. Within each section, the corresponding DWC_otg PCD
15909 + * function name is specified.
15910 + *
15911 + */
15912 +
15913 +/**
15914 + * This function assigns periodic Tx FIFO to an periodic EP
15915 + * in shared Tx FIFO mode
15916 + */
15917 +static uint32_t assign_perio_tx_fifo(dwc_otg_core_if_t *core_if)
15918 +{
15919 +       uint32_t PerTxMsk = 1;
15920 +       int i;
15921 +       for(i = 0; i < core_if->hwcfg4.b.num_dev_perio_in_ep; ++i)
15922 +       {
15923 +               if((PerTxMsk & core_if->p_tx_msk) == 0) {
15924 +                       core_if->p_tx_msk |= PerTxMsk;
15925 +                       return i + 1;
15926 +               }
15927 +               PerTxMsk <<= 1;
15928 +       }
15929 +       return 0;
15930 +}
15931 +/**
15932 + * This function releases periodic Tx FIFO
15933 + * in shared Tx FIFO mode
15934 + */
15935 +static void release_perio_tx_fifo(dwc_otg_core_if_t *core_if, uint32_t fifo_num)
15936 +{
15937 +       core_if->p_tx_msk = (core_if->p_tx_msk & (1 << (fifo_num - 1))) ^ core_if->p_tx_msk;
15938 +}
15939 +/**
15940 + * This function assigns periodic Tx FIFO to an periodic EP
15941 + * in shared Tx FIFO mode
15942 + */
15943 +static uint32_t assign_tx_fifo(dwc_otg_core_if_t *core_if)
15944 +{
15945 +       uint32_t TxMsk = 1;
15946 +       int i;
15947 +
15948 +       for(i = 0; i < core_if->hwcfg4.b.num_in_eps; ++i)
15949 +       {
15950 +               if((TxMsk & core_if->tx_msk) == 0) {
15951 +                       core_if->tx_msk |= TxMsk;
15952 +                       return i + 1;
15953 +               }
15954 +               TxMsk <<= 1;
15955 +       }
15956 +       return 0;
15957 +}
15958 +/**
15959 + * This function releases periodic Tx FIFO
15960 + * in shared Tx FIFO mode
15961 + */
15962 +static void release_tx_fifo(dwc_otg_core_if_t  *core_if, uint32_t fifo_num)
15963 +{
15964 +       core_if->tx_msk = (core_if->tx_msk & (1 << (fifo_num - 1))) ^ core_if->tx_msk;
15965 +}
15966 +
15967 +/**
15968 + * This function is called by the Gadget Driver for each EP to be
15969 + * configured for the current configuration (SET_CONFIGURATION).
15970 + *
15971 + * This function initializes the dwc_otg_ep_t data structure, and then
15972 + * calls dwc_otg_ep_activate.
15973 + */
15974 +static int dwc_otg_pcd_ep_enable(struct usb_ep *usb_ep,
15975 +                                const struct usb_endpoint_descriptor *ep_desc)
15976 +{
15977 +       dwc_otg_pcd_ep_t *ep = 0;
15978 +       dwc_otg_pcd_t *pcd = 0;
15979 +       unsigned long flags;
15980 +
15981 +       DWC_DEBUGPL(DBG_PCDV,"%s(%p,%p)\n", __func__, usb_ep, ep_desc);
15982 +
15983 +       ep = container_of(usb_ep, dwc_otg_pcd_ep_t, ep);
15984 +       if (!usb_ep || !ep_desc || ep->desc ||
15985 +                       ep_desc->bDescriptorType != USB_DT_ENDPOINT) {
15986 +               DWC_WARN("%s, bad ep or descriptor\n", __func__);
15987 +               return -EINVAL;
15988 +       }
15989 +       if (ep == &ep->pcd->ep0) {
15990 +               DWC_WARN("%s, bad ep(0)\n", __func__);
15991 +               return -EINVAL;
15992 +       }
15993 +
15994 +       /* Check FIFO size? */
15995 +       if (!ep_desc->wMaxPacketSize) {
15996 +               DWC_WARN("%s, bad %s maxpacket\n", __func__, usb_ep->name);
15997 +               return -ERANGE;
15998 +       }
15999 +
16000 +       pcd = ep->pcd;
16001 +       if (!pcd->driver || pcd->gadget.speed == USB_SPEED_UNKNOWN) {
16002 +               DWC_WARN("%s, bogus device state\n", __func__);
16003 +               return -ESHUTDOWN;
16004 +       }
16005 +
16006 +       SPIN_LOCK_IRQSAVE(&pcd->lock, flags);
16007 +
16008 +       ep->desc = ep_desc;
16009 +       ep->ep.maxpacket = le16_to_cpu (ep_desc->wMaxPacketSize);
16010 +
16011 +       /*
16012 +        * Activate the EP
16013 +        */
16014 +       ep->stopped = 0;
16015 +
16016 +       ep->dwc_ep.is_in = (USB_DIR_IN & ep_desc->bEndpointAddress) != 0;
16017 +       ep->dwc_ep.maxpacket = ep->ep.maxpacket;
16018 +
16019 +       ep->dwc_ep.type = ep_desc->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK;
16020 +
16021 +       if(ep->dwc_ep.is_in) {
16022 +               if(!pcd->otg_dev->core_if->en_multiple_tx_fifo) {
16023 +                       ep->dwc_ep.tx_fifo_num = 0;
16024 +
16025 +                       if (ep->dwc_ep.type == USB_ENDPOINT_XFER_ISOC) {
16026 +                               /*
16027 +                                * if ISOC EP then assign a Periodic Tx FIFO.
16028 +                                */
16029 +                               ep->dwc_ep.tx_fifo_num = assign_perio_tx_fifo(pcd->otg_dev->core_if);
16030 +                        }
16031 +               } else {
16032 +                       /*
16033 +                        * if Dedicated FIFOs mode is on then assign a Tx FIFO.
16034 +                        */
16035 +                       ep->dwc_ep.tx_fifo_num = assign_tx_fifo(pcd->otg_dev->core_if);
16036 +
16037 +               }
16038 +       }
16039 +       /* Set initial data PID. */
16040 +       if (ep->dwc_ep.type == USB_ENDPOINT_XFER_BULK) {
16041 +               ep->dwc_ep.data_pid_start = 0;
16042 +       }
16043 +
16044 +       DWC_DEBUGPL(DBG_PCD, "Activate %s-%s: type=%d, mps=%d desc=%p\n",
16045 +                                       ep->ep.name, (ep->dwc_ep.is_in ?"IN":"OUT"),
16046 +                                       ep->dwc_ep.type, ep->dwc_ep.maxpacket, ep->desc);
16047 +
16048 +       if(ep->dwc_ep.type != USB_ENDPOINT_XFER_ISOC) {
16049 +               ep->dwc_ep.desc_addr = dwc_otg_ep_alloc_desc_chain(&ep->dwc_ep.dma_desc_addr, MAX_DMA_DESC_CNT);
16050 +       }
16051 +
16052 +       dwc_otg_ep_activate(GET_CORE_IF(pcd), &ep->dwc_ep);
16053 +       SPIN_UNLOCK_IRQRESTORE(&pcd->lock, flags);
16054 +
16055 +       return 0;
16056 +}
16057 +
16058 +/**
16059 + * This function is called when an EP is disabled due to disconnect or
16060 + * change in configuration. Any pending requests will terminate with a
16061 + * status of -ESHUTDOWN.
16062 + *
16063 + * This function modifies the dwc_otg_ep_t data structure for this EP,
16064 + * and then calls dwc_otg_ep_deactivate.
16065 + */
16066 +static int dwc_otg_pcd_ep_disable(struct usb_ep *usb_ep)
16067 +{
16068 +       dwc_otg_pcd_ep_t *ep;
16069 +       dwc_otg_pcd_t *pcd = 0;
16070 +       unsigned long flags;
16071 +
16072 +       DWC_DEBUGPL(DBG_PCDV,"%s(%p)\n", __func__, usb_ep);
16073 +       ep = container_of(usb_ep, dwc_otg_pcd_ep_t, ep);
16074 +       if (!usb_ep || !ep->desc) {
16075 +               DWC_DEBUGPL(DBG_PCD, "%s, %s not enabled\n", __func__,
16076 +                       usb_ep ? ep->ep.name : NULL);
16077 +               return -EINVAL;
16078 +       }
16079 +
16080 +       SPIN_LOCK_IRQSAVE(&ep->pcd->lock, flags);
16081 +
16082 +       dwc_otg_request_nuke(ep);
16083 +
16084 +       dwc_otg_ep_deactivate(GET_CORE_IF(ep->pcd), &ep->dwc_ep);
16085 +       ep->desc = 0;
16086 +       ep->stopped = 1;
16087 +
16088 +       if(ep->dwc_ep.is_in) {
16089 +               dwc_otg_flush_tx_fifo(GET_CORE_IF(ep->pcd), ep->dwc_ep.tx_fifo_num);
16090 +               release_perio_tx_fifo(GET_CORE_IF(ep->pcd), ep->dwc_ep.tx_fifo_num);
16091 +               release_tx_fifo(GET_CORE_IF(ep->pcd), ep->dwc_ep.tx_fifo_num);
16092 +       }
16093 +
16094 +       /* Free DMA Descriptors */
16095 +       pcd = ep->pcd;
16096 +
16097 +       SPIN_UNLOCK_IRQRESTORE(&ep->pcd->lock, flags);
16098 +
16099 +       if(ep->dwc_ep.type != USB_ENDPOINT_XFER_ISOC && ep->dwc_ep.desc_addr) {
16100 +               dwc_otg_ep_free_desc_chain(ep->dwc_ep.desc_addr, ep->dwc_ep.dma_desc_addr, MAX_DMA_DESC_CNT);
16101 +       }
16102 +
16103 +       DWC_DEBUGPL(DBG_PCD, "%s disabled\n", usb_ep->name);
16104 +       return 0;
16105 +}
16106 +
16107 +
16108 +/**
16109 + * This function allocates a request object to use with the specified
16110 + * endpoint.
16111 + *
16112 + * @param ep The endpoint to be used with with the request
16113 + * @param gfp_flags the GFP_* flags to use.
16114 + */
16115 +static struct usb_request *dwc_otg_pcd_alloc_request(struct usb_ep *ep,
16116 +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,20)
16117 +                                                    int gfp_flags
16118 +#else
16119 +                                                    gfp_t gfp_flags
16120 +#endif
16121 +                                                  )
16122 +{
16123 +       dwc_otg_pcd_request_t *req;
16124 +
16125 +       DWC_DEBUGPL(DBG_PCDV,"%s(%p,%d)\n", __func__, ep, gfp_flags);
16126 +       if (0 == ep) {
16127 +               DWC_WARN("%s() %s\n", __func__, "Invalid EP!\n");
16128 +               return 0;
16129 +       }
16130 +       req = kmalloc(sizeof(dwc_otg_pcd_request_t), gfp_flags);
16131 +       if (0 == req) {
16132 +               DWC_WARN("%s() %s\n", __func__,
16133 +                                "request allocation failed!\n");
16134 +               return 0;
16135 +       }
16136 +       memset(req, 0, sizeof(dwc_otg_pcd_request_t));
16137 +       req->req.dma = DMA_ADDR_INVALID;
16138 +       INIT_LIST_HEAD(&req->queue);
16139 +       return &req->req;
16140 +}
16141 +
16142 +/**
16143 + * This function frees a request object.
16144 + *
16145 + * @param ep The endpoint associated with the request
16146 + * @param req The request being freed
16147 + */
16148 +static void dwc_otg_pcd_free_request(struct usb_ep *ep,
16149 +                                        struct usb_request *req)
16150 +{
16151 +       dwc_otg_pcd_request_t *request;
16152 +       DWC_DEBUGPL(DBG_PCDV,"%s(%p,%p)\n", __func__, ep, req);
16153 +
16154 +       if (0 == ep || 0 == req) {
16155 +               DWC_WARN("%s() %s\n", __func__,
16156 +                                "Invalid ep or req argument!\n");
16157 +               return;
16158 +       }
16159 +
16160 +       request = container_of(req, dwc_otg_pcd_request_t, req);
16161 +       kfree(request);
16162 +}
16163 +
16164 +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,23)
16165 +/**
16166 + * This function allocates an I/O buffer to be used for a transfer
16167 + * to/from the specified endpoint.
16168 + *
16169 + * @param usb_ep The endpoint to be used with with the request
16170 + * @param bytes The desired number of bytes for the buffer
16171 + * @param dma Pointer to the buffer's DMA address; must be valid
16172 + * @param gfp_flags the GFP_* flags to use.
16173 + * @return address of a new buffer or null is buffer could not be allocated.
16174 + */
16175 +static void *dwc_otg_pcd_alloc_buffer(struct usb_ep *usb_ep, unsigned bytes,
16176 +                                     dma_addr_t *dma,
16177 +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,20)
16178 +                                     int gfp_flags
16179 +#else
16180 +                                     gfp_t gfp_flags
16181 +#endif
16182 +                                   )
16183 +{
16184 +       void *buf;
16185 +       dwc_otg_pcd_ep_t *ep;
16186 +       dwc_otg_pcd_t *pcd = 0;
16187 +
16188 +       ep = container_of(usb_ep, dwc_otg_pcd_ep_t, ep);
16189 +       pcd = ep->pcd;
16190 +
16191 +       DWC_DEBUGPL(DBG_PCDV,"%s(%p,%d,%p,%0x)\n", __func__, usb_ep, bytes,
16192 +                               dma, gfp_flags);
16193 +
16194 +       /* Check dword alignment */
16195 +       if ((bytes & 0x3UL) != 0) {
16196 +               DWC_WARN("%s() Buffer size is not a multiple of"
16197 +                                "DWORD size (%d)",__func__, bytes);
16198 +       }
16199 +
16200 +       if (GET_CORE_IF(pcd)->dma_enable) {
16201 +               buf = dma_alloc_coherent (NULL, bytes, dma, gfp_flags);
16202 +       }
16203 +       else {
16204 +               buf = kmalloc(bytes, gfp_flags);
16205 +       }
16206 +
16207 +       /* Check dword alignment */
16208 +       if (((int)buf & 0x3UL) != 0) {
16209 +               DWC_WARN("%s() Buffer is not DWORD aligned (%p)",
16210 +                                       __func__, buf);
16211 +       }
16212 +
16213 +       return buf;
16214 +}
16215 +
16216 +/**
16217 + * This function frees an I/O buffer that was allocated by alloc_buffer.
16218 + *
16219 + * @param usb_ep the endpoint associated with the buffer
16220 + * @param buf address of the buffer
16221 + * @param dma The buffer's DMA address
16222 + * @param bytes The number of bytes of the buffer
16223 + */
16224 +static void dwc_otg_pcd_free_buffer(struct usb_ep *usb_ep, void *buf,
16225 +                                       dma_addr_t dma, unsigned bytes)
16226 +{
16227 +       dwc_otg_pcd_ep_t *ep;
16228 +       dwc_otg_pcd_t *pcd = 0;
16229 +
16230 +       ep = container_of(usb_ep, dwc_otg_pcd_ep_t, ep);
16231 +       pcd = ep->pcd;
16232 +
16233 +       DWC_DEBUGPL(DBG_PCDV,"%s(%p,%p,%0x,%d)\n", __func__, ep, buf, dma, bytes);
16234 +
16235 +       if (GET_CORE_IF(pcd)->dma_enable) {
16236 +               dma_free_coherent (NULL, bytes, buf, dma);
16237 +       }
16238 +       else {
16239 +               kfree(buf);
16240 +       }
16241 +}
16242 +#endif
16243 +
16244 +
16245 +/**
16246 + * This function is used to submit an I/O Request to an EP.
16247 + *
16248 + *     - When the request completes the request's completion callback
16249 + *       is called to return the request to the driver.
16250 + *     - An EP, except control EPs, may have multiple requests
16251 + *       pending.
16252 + *     - Once submitted the request cannot be examined or modified.
16253 + *     - Each request is turned into one or more packets.
16254 + *     - A BULK EP can queue any amount of data; the transfer is
16255 + *       packetized.
16256 + *     - Zero length Packets are specified with the request 'zero'
16257 + *       flag.
16258 + */
16259 +static int dwc_otg_pcd_ep_queue(struct usb_ep *usb_ep,
16260 +                               struct usb_request *usb_req,
16261 +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,20)
16262 +                               int gfp_flags
16263 +#else
16264 +                               gfp_t gfp_flags
16265 +#endif
16266 +                             )
16267 +{
16268 +       int prevented = 0;
16269 +       dwc_otg_pcd_request_t *req;
16270 +       dwc_otg_pcd_ep_t *ep;
16271 +       dwc_otg_pcd_t   *pcd;
16272 +       unsigned long flags = 0;
16273 +       dwc_otg_core_if_t *_core_if;
16274 +
16275 +       DWC_DEBUGPL(DBG_PCDV,"%s(%p,%p,%d)\n",
16276 +                       __func__, usb_ep, usb_req, gfp_flags);
16277 +
16278 +       req = container_of(usb_req, dwc_otg_pcd_request_t, req);
16279 +       if (!usb_req || !usb_req->complete || !usb_req->buf ||
16280 +                       !list_empty(&req->queue)) {
16281 +               DWC_WARN("%s, bad params\n", __func__);
16282 +               return -EINVAL;
16283 +       }
16284 +
16285 +       ep = container_of(usb_ep, dwc_otg_pcd_ep_t, ep);
16286 +       if (!usb_ep || (!ep->desc && ep->dwc_ep.num != 0)/* || ep->stopped != 0*/) {
16287 +               DWC_WARN("%s, bad ep\n", __func__);
16288 +               return -EINVAL;
16289 +       }
16290 +
16291 +       pcd = ep->pcd;
16292 +       if (!pcd->driver || pcd->gadget.speed == USB_SPEED_UNKNOWN) {
16293 +               DWC_DEBUGPL(DBG_PCDV, "gadget.speed=%d\n", pcd->gadget.speed);
16294 +               DWC_WARN("%s, bogus device state\n", __func__);
16295 +               return -ESHUTDOWN;
16296 +       }
16297 +
16298 +
16299 +       DWC_DEBUGPL(DBG_PCD, "%s queue req %p, len %d buf %p\n",
16300 +                          usb_ep->name, usb_req, usb_req->length, usb_req->buf);
16301 +
16302 +       if (!GET_CORE_IF(pcd)->core_params->opt) {
16303 +               if (ep->dwc_ep.num != 0) {
16304 +                       DWC_ERROR("%s queue req %p, len %d buf %p\n",
16305 +                                         usb_ep->name, usb_req, usb_req->length, usb_req->buf);
16306 +               }
16307 +       }
16308 +
16309 +       SPIN_LOCK_IRQSAVE(&ep->pcd->lock, flags);
16310 +
16311 +
16312 +       /**************************************************
16313 +         New add by kaiker ,for DMA mode bug
16314 +       ************************************************/
16315 +       //by kaiker ,for RT3052 USB OTG device mode
16316 +
16317 +       _core_if = GET_CORE_IF(pcd);
16318 +
16319 +       if (_core_if->dma_enable)
16320 +       {
16321 +                usb_req->dma = virt_to_phys((void *)usb_req->buf);
16322 +
16323 +               if(ep->dwc_ep.is_in)
16324 +               {
16325 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,24)) || defined(CONFIG_MIPS)
16326 +                       if(usb_req->length)
16327 +                               dma_cache_wback_inv((unsigned long)usb_req->buf, usb_req->length + 2);
16328 +#endif
16329 +               }
16330 +       }
16331 +
16332 +
16333 +
16334 +#if defined(DEBUG) & defined(VERBOSE)
16335 +       dump_msg(usb_req->buf, usb_req->length);
16336 +#endif
16337 +
16338 +       usb_req->status = -EINPROGRESS;
16339 +       usb_req->actual = 0;
16340 +
16341 +       /*
16342 +        * For EP0 IN without premature status, zlp is required?
16343 +        */
16344 +       if (ep->dwc_ep.num == 0 && ep->dwc_ep.is_in) {
16345 +               DWC_DEBUGPL(DBG_PCDV, "%s-OUT ZLP\n", usb_ep->name);
16346 +               //_req->zero = 1;
16347 +       }
16348 +
16349 +       /* Start the transfer */
16350 +       if (list_empty(&ep->queue) && !ep->stopped) {
16351 +               /* EP0 Transfer? */
16352 +               if (ep->dwc_ep.num == 0) {
16353 +                       switch (pcd->ep0state) {
16354 +                       case EP0_IN_DATA_PHASE:
16355 +                               DWC_DEBUGPL(DBG_PCD,
16356 +                                               "%s ep0: EP0_IN_DATA_PHASE\n",
16357 +                                               __func__);
16358 +                               break;
16359 +
16360 +                       case EP0_OUT_DATA_PHASE:
16361 +                               DWC_DEBUGPL(DBG_PCD,
16362 +                                               "%s ep0: EP0_OUT_DATA_PHASE\n",
16363 +                                               __func__);
16364 +                               if (pcd->request_config) {
16365 +                                       /* Complete STATUS PHASE */
16366 +                                       ep->dwc_ep.is_in = 1;
16367 +                                       pcd->ep0state = EP0_IN_STATUS_PHASE;
16368 +                               }
16369 +                               break;
16370 +
16371 +                       case EP0_IN_STATUS_PHASE:
16372 +                               DWC_DEBUGPL(DBG_PCD,
16373 +                                               "%s ep0: EP0_IN_STATUS_PHASE\n",
16374 +                                               __func__);
16375 +                               break;
16376 +
16377 +                       default:
16378 +                               DWC_DEBUGPL(DBG_ANY, "ep0: odd state %d\n",
16379 +                                               pcd->ep0state);
16380 +                               SPIN_UNLOCK_IRQRESTORE(&pcd->lock, flags);
16381 +                               return -EL2HLT;
16382 +                       }
16383 +                       ep->dwc_ep.dma_addr = usb_req->dma;
16384 +                       ep->dwc_ep.start_xfer_buff = usb_req->buf;
16385 +                       ep->dwc_ep.xfer_buff = usb_req->buf;
16386 +                       ep->dwc_ep.xfer_len = usb_req->length;
16387 +                       ep->dwc_ep.xfer_count = 0;
16388 +                       ep->dwc_ep.sent_zlp = 0;
16389 +                       ep->dwc_ep.total_len = ep->dwc_ep.xfer_len;
16390 +
16391 +                       if(usb_req->zero) {
16392 +                               if((ep->dwc_ep.xfer_len % ep->dwc_ep.maxpacket == 0)
16393 +                                               && (ep->dwc_ep.xfer_len != 0)) {
16394 +                                       ep->dwc_ep.sent_zlp = 1;
16395 +                               }
16396 +
16397 +                       }
16398 +
16399 +                       dwc_otg_ep0_start_transfer(GET_CORE_IF(pcd), &ep->dwc_ep);
16400 +               }
16401 +               else {
16402 +
16403 +                       uint32_t max_transfer = GET_CORE_IF(ep->pcd)->core_params->max_transfer_size;
16404 +
16405 +                       /* Setup and start the Transfer */
16406 +                       ep->dwc_ep.dma_addr = usb_req->dma;
16407 +                       ep->dwc_ep.start_xfer_buff = usb_req->buf;
16408 +                       ep->dwc_ep.xfer_buff = usb_req->buf;
16409 +                       ep->dwc_ep.sent_zlp = 0;
16410 +                       ep->dwc_ep.total_len = usb_req->length;
16411 +                       ep->dwc_ep.xfer_len = 0;
16412 +                       ep->dwc_ep.xfer_count = 0;
16413 +
16414 +                       if(max_transfer > MAX_TRANSFER_SIZE) {
16415 +                               ep->dwc_ep.maxxfer = max_transfer - (max_transfer % ep->dwc_ep.maxpacket);
16416 +                       } else {
16417 +                               ep->dwc_ep.maxxfer = max_transfer;
16418 +                       }
16419 +
16420 +                       if(usb_req->zero) {
16421 +                               if((ep->dwc_ep.total_len % ep->dwc_ep.maxpacket == 0)
16422 +                                               && (ep->dwc_ep.total_len != 0)) {
16423 +                                       ep->dwc_ep.sent_zlp = 1;
16424 +                               }
16425 +
16426 +                       }
16427 +                       dwc_otg_ep_start_transfer(GET_CORE_IF(pcd), &ep->dwc_ep);
16428 +               }
16429 +       }
16430 +
16431 +       if ((req != 0) || prevented) {
16432 +               ++pcd->request_pending;
16433 +               list_add_tail(&req->queue, &ep->queue);
16434 +               if (ep->dwc_ep.is_in && ep->stopped && !(GET_CORE_IF(pcd)->dma_enable)) {
16435 +                       /** @todo NGS Create a function for this. */
16436 +                       diepmsk_data_t diepmsk = { .d32 = 0};
16437 +                       diepmsk.b.intktxfemp = 1;
16438 +                       if(&GET_CORE_IF(pcd)->multiproc_int_enable) {
16439 +                               dwc_modify_reg32(&GET_CORE_IF(pcd)->dev_if->dev_global_regs->diepeachintmsk[ep->dwc_ep.num],
16440 +                                                       0, diepmsk.d32);
16441 +                       } else {
16442 +                               dwc_modify_reg32(&GET_CORE_IF(pcd)->dev_if->dev_global_regs->diepmsk, 0, diepmsk.d32);
16443 +                       }
16444 +               }
16445 +       }
16446 +
16447 +       SPIN_UNLOCK_IRQRESTORE(&pcd->lock, flags);
16448 +       return 0;
16449 +}
16450 +
16451 +/**
16452 + * This function cancels an I/O request from an EP.
16453 + */
16454 +static int dwc_otg_pcd_ep_dequeue(struct usb_ep *usb_ep,
16455 +                                 struct usb_request *usb_req)
16456 +{
16457 +       dwc_otg_pcd_request_t *req;
16458 +       dwc_otg_pcd_ep_t *ep;
16459 +       dwc_otg_pcd_t   *pcd;
16460 +       unsigned long flags;
16461 +
16462 +       DWC_DEBUGPL(DBG_PCDV,"%s(%p,%p)\n", __func__, usb_ep, usb_req);
16463 +
16464 +       ep = container_of(usb_ep, dwc_otg_pcd_ep_t, ep);
16465 +       if (!usb_ep || !usb_req || (!ep->desc && ep->dwc_ep.num != 0)) {
16466 +               DWC_WARN("%s, bad argument\n", __func__);
16467 +               return -EINVAL;
16468 +       }
16469 +       pcd = ep->pcd;
16470 +       if (!pcd->driver || pcd->gadget.speed == USB_SPEED_UNKNOWN) {
16471 +               DWC_WARN("%s, bogus device state\n", __func__);
16472 +               return -ESHUTDOWN;
16473 +       }
16474 +
16475 +       SPIN_LOCK_IRQSAVE(&pcd->lock, flags);
16476 +       DWC_DEBUGPL(DBG_PCDV, "%s %s %s %p\n", __func__, usb_ep->name,
16477 +                                       ep->dwc_ep.is_in ? "IN" : "OUT",
16478 +                                       usb_req);
16479 +
16480 +       /* make sure it's actually queued on this endpoint */
16481 +       list_for_each_entry(req, &ep->queue, queue)
16482 +       {
16483 +               if (&req->req == usb_req) {
16484 +                       break;
16485 +               }
16486 +       }
16487 +
16488 +       if (&req->req != usb_req) {
16489 +               SPIN_UNLOCK_IRQRESTORE(&pcd->lock, flags);
16490 +               return -EINVAL;
16491 +       }
16492 +
16493 +       if (!list_empty(&req->queue)) {
16494 +               dwc_otg_request_done(ep, req, -ECONNRESET);
16495 +       }
16496 +       else {
16497 +               req = 0;
16498 +       }
16499 +
16500 +       SPIN_UNLOCK_IRQRESTORE(&pcd->lock, flags);
16501 +
16502 +       return req ? 0 : -EOPNOTSUPP;
16503 +}
16504 +
16505 +/**
16506 + * usb_ep_set_halt stalls an endpoint.
16507 + *
16508 + * usb_ep_clear_halt clears an endpoint halt and resets its data
16509 + * toggle.
16510 + *
16511 + * Both of these functions are implemented with the same underlying
16512 + * function. The behavior depends on the value argument.
16513 + *
16514 + * @param[in] usb_ep the Endpoint to halt or clear halt.
16515 + * @param[in] value
16516 + *     - 0 means clear_halt.
16517 + *     - 1 means set_halt,
16518 + *     - 2 means clear stall lock flag.
16519 + *     - 3 means set  stall lock flag.
16520 + */
16521 +static int dwc_otg_pcd_ep_set_halt(struct usb_ep *usb_ep, int value)
16522 +{
16523 +       int retval = 0;
16524 +       unsigned long flags;
16525 +       dwc_otg_pcd_ep_t *ep = 0;
16526 +
16527 +
16528 +       DWC_DEBUGPL(DBG_PCD,"HALT %s %d\n", usb_ep->name, value);
16529 +
16530 +       ep = container_of(usb_ep, dwc_otg_pcd_ep_t, ep);
16531 +
16532 +       if (!usb_ep || (!ep->desc && ep != &ep->pcd->ep0) ||
16533 +                       ep->desc->bmAttributes == USB_ENDPOINT_XFER_ISOC) {
16534 +               DWC_WARN("%s, bad ep\n", __func__);
16535 +               return -EINVAL;
16536 +       }
16537 +
16538 +       SPIN_LOCK_IRQSAVE(&ep->pcd->lock, flags);
16539 +       if (!list_empty(&ep->queue)) {
16540 +               DWC_WARN("%s() %s XFer In process\n", __func__, usb_ep->name);
16541 +               retval = -EAGAIN;
16542 +       }
16543 +       else if (value == 0) {
16544 +               dwc_otg_ep_clear_stall(ep->pcd->otg_dev->core_if,
16545 +                                       &ep->dwc_ep);
16546 +       }
16547 +       else if(value == 1) {
16548 +               if (ep->dwc_ep.is_in == 1 && ep->pcd->otg_dev->core_if->dma_desc_enable) {
16549 +                       dtxfsts_data_t txstatus;
16550 +                       fifosize_data_t txfifosize;
16551 +
16552 +                       txfifosize.d32 = dwc_read_reg32(&ep->pcd->otg_dev->core_if->core_global_regs->dptxfsiz_dieptxf[ep->dwc_ep.tx_fifo_num]);
16553 +                       txstatus.d32 = dwc_read_reg32(&ep->pcd->otg_dev->core_if->dev_if->in_ep_regs[ep->dwc_ep.num]->dtxfsts);
16554 +
16555 +                       if(txstatus.b.txfspcavail < txfifosize.b.depth) {
16556 +                               DWC_WARN("%s() %s Data In Tx Fifo\n", __func__, usb_ep->name);
16557 +                               retval = -EAGAIN;
16558 +                       }
16559 +                       else {
16560 +                               if (ep->dwc_ep.num == 0) {
16561 +                                       ep->pcd->ep0state = EP0_STALL;
16562 +                               }
16563 +
16564 +                               ep->stopped = 1;
16565 +                               dwc_otg_ep_set_stall(ep->pcd->otg_dev->core_if,
16566 +                                                       &ep->dwc_ep);
16567 +                       }
16568 +               }
16569 +               else {
16570 +                       if (ep->dwc_ep.num == 0) {
16571 +                               ep->pcd->ep0state = EP0_STALL;
16572 +                       }
16573 +
16574 +                       ep->stopped = 1;
16575 +                       dwc_otg_ep_set_stall(ep->pcd->otg_dev->core_if,
16576 +                                               &ep->dwc_ep);
16577 +               }
16578 +       }
16579 +       else if (value == 2) {
16580 +               ep->dwc_ep.stall_clear_flag = 0;
16581 +       }
16582 +       else if (value == 3) {
16583 +               ep->dwc_ep.stall_clear_flag = 1;
16584 +       }
16585 +
16586 +       SPIN_UNLOCK_IRQRESTORE(&ep->pcd->lock, flags);
16587 +       return retval;
16588 +}
16589 +
16590 +/**
16591 + * This function allocates a DMA Descriptor chain for the Endpoint
16592 + * buffer to be used for a transfer to/from the specified endpoint.
16593 + */
16594 +dwc_otg_dma_desc_t* dwc_otg_ep_alloc_desc_chain(uint32_t * dma_desc_addr, uint32_t count)
16595 +{
16596 +
16597 +       return dma_alloc_coherent(NULL, count * sizeof(dwc_otg_dma_desc_t), dma_desc_addr, GFP_KERNEL);
16598 +}
16599 +
16600 +/**
16601 + * This function frees a DMA Descriptor chain that was allocated by ep_alloc_desc.
16602 + */
16603 +void dwc_otg_ep_free_desc_chain(dwc_otg_dma_desc_t* desc_addr, uint32_t dma_desc_addr, uint32_t count)
16604 +{
16605 +       dma_free_coherent(NULL, count * sizeof(dwc_otg_dma_desc_t), desc_addr, dma_desc_addr);
16606 +}
16607 +
16608 +#ifdef DWC_EN_ISOC
16609 +
16610 +/**
16611 + * This function initializes a descriptor chain for Isochronous transfer
16612 + *
16613 + * @param core_if Programming view of DWC_otg controller.
16614 + * @param dwc_ep The EP to start the transfer on.
16615 + *
16616 + */
16617 +void dwc_otg_iso_ep_start_ddma_transfer(dwc_otg_core_if_t *core_if, dwc_ep_t *dwc_ep)
16618 +{
16619 +
16620 +       dsts_data_t             dsts = { .d32 = 0};
16621 +       depctl_data_t           depctl = { .d32 = 0 };
16622 +       volatile uint32_t       *addr;
16623 +       int                     i, j;
16624 +
16625 +       if(dwc_ep->is_in)
16626 +               dwc_ep->desc_cnt = dwc_ep->buf_proc_intrvl / dwc_ep->bInterval;
16627 +       else
16628 +               dwc_ep->desc_cnt = dwc_ep->buf_proc_intrvl * dwc_ep->pkt_per_frm / dwc_ep->bInterval;
16629 +
16630 +
16631 +       /** Allocate descriptors for double buffering */
16632 +       dwc_ep->iso_desc_addr = dwc_otg_ep_alloc_desc_chain(&dwc_ep->iso_dma_desc_addr,dwc_ep->desc_cnt*2);
16633 +       if(dwc_ep->desc_addr) {
16634 +               DWC_WARN("%s, can't allocate DMA descriptor chain\n", __func__);
16635 +               return;
16636 +       }
16637 +
16638 +       dsts.d32 = dwc_read_reg32(&core_if->dev_if->dev_global_regs->dsts);
16639 +
16640 +       /** ISO OUT EP */
16641 +       if(dwc_ep->is_in == 0) {
16642 +               desc_sts_data_t sts = { .d32 =0 };
16643 +               dwc_otg_dma_desc_t* dma_desc = dwc_ep->iso_desc_addr;
16644 +               dma_addr_t dma_ad;
16645 +               uint32_t data_per_desc;
16646 +               dwc_otg_dev_out_ep_regs_t *out_regs =
16647 +                       core_if->dev_if->out_ep_regs[dwc_ep->num];
16648 +               int     offset;
16649 +
16650 +               addr = &core_if->dev_if->out_ep_regs[dwc_ep->num]->doepctl;
16651 +               dma_ad = (dma_addr_t)dwc_read_reg32(&(out_regs->doepdma));
16652 +
16653 +               /** Buffer 0 descriptors setup */
16654 +               dma_ad = dwc_ep->dma_addr0;
16655 +
16656 +               sts.b_iso_out.bs = BS_HOST_READY;
16657 +               sts.b_iso_out.rxsts = 0;
16658 +               sts.b_iso_out.l = 0;
16659 +               sts.b_iso_out.sp = 0;
16660 +               sts.b_iso_out.ioc = 0;
16661 +               sts.b_iso_out.pid = 0;
16662 +               sts.b_iso_out.framenum = 0;
16663 +
16664 +               offset = 0;
16665 +               for(i = 0; i < dwc_ep->desc_cnt - dwc_ep->pkt_per_frm; i+= dwc_ep->pkt_per_frm)
16666 +               {
16667 +
16668 +                       for(j = 0; j < dwc_ep->pkt_per_frm; ++j)
16669 +                       {
16670 +                               data_per_desc = ((j + 1) * dwc_ep->maxpacket > dwc_ep->data_per_frame) ?
16671 +                                       dwc_ep->data_per_frame - j * dwc_ep->maxpacket : dwc_ep->maxpacket;
16672 +
16673 +                               data_per_desc += (data_per_desc % 4) ? (4 - data_per_desc % 4):0;
16674 +                               sts.b_iso_out.rxbytes = data_per_desc;
16675 +                               writel((uint32_t)dma_ad, &dma_desc->buf);
16676 +                               writel(sts.d32, &dma_desc->status);
16677 +
16678 +                               offset += data_per_desc;
16679 +                               dma_desc ++;
16680 +                               (uint32_t)dma_ad += data_per_desc;
16681 +                       }
16682 +               }
16683 +
16684 +               for(j = 0; j < dwc_ep->pkt_per_frm - 1; ++j)
16685 +               {
16686 +                       data_per_desc = ((j + 1) * dwc_ep->maxpacket > dwc_ep->data_per_frame) ?
16687 +                               dwc_ep->data_per_frame - j * dwc_ep->maxpacket : dwc_ep->maxpacket;
16688 +                       data_per_desc += (data_per_desc % 4) ? (4 - data_per_desc % 4):0;
16689 +                       sts.b_iso_out.rxbytes = data_per_desc;
16690 +                       writel((uint32_t)dma_ad, &dma_desc->buf);
16691 +                       writel(sts.d32, &dma_desc->status);
16692 +
16693 +                       offset += data_per_desc;
16694 +                       dma_desc ++;
16695 +                       (uint32_t)dma_ad += data_per_desc;
16696 +               }
16697 +
16698 +               sts.b_iso_out.ioc = 1;
16699 +               data_per_desc = ((j + 1) * dwc_ep->maxpacket > dwc_ep->data_per_frame) ?
16700 +                       dwc_ep->data_per_frame - j * dwc_ep->maxpacket : dwc_ep->maxpacket;
16701 +               data_per_desc += (data_per_desc % 4) ? (4 - data_per_desc % 4):0;
16702 +               sts.b_iso_out.rxbytes = data_per_desc;
16703 +
16704 +               writel((uint32_t)dma_ad, &dma_desc->buf);
16705 +               writel(sts.d32, &dma_desc->status);
16706 +               dma_desc ++;
16707 +
16708 +               /** Buffer 1 descriptors setup */
16709 +               sts.b_iso_out.ioc = 0;
16710 +               dma_ad = dwc_ep->dma_addr1;
16711 +
16712 +               offset = 0;
16713 +               for(i = 0; i < dwc_ep->desc_cnt - dwc_ep->pkt_per_frm; i+= dwc_ep->pkt_per_frm)
16714 +               {
16715 +                       for(j = 0; j < dwc_ep->pkt_per_frm; ++j)
16716 +                       {
16717 +                               data_per_desc = ((j + 1) * dwc_ep->maxpacket > dwc_ep->data_per_frame) ?
16718 +                                       dwc_ep->data_per_frame - j * dwc_ep->maxpacket : dwc_ep->maxpacket;
16719 +                               data_per_desc += (data_per_desc % 4) ? (4 - data_per_desc % 4):0;
16720 +                               sts.b_iso_out.rxbytes = data_per_desc;
16721 +                               writel((uint32_t)dma_ad, &dma_desc->buf);
16722 +                               writel(sts.d32, &dma_desc->status);
16723 +
16724 +                               offset += data_per_desc;
16725 +                               dma_desc ++;
16726 +                               (uint32_t)dma_ad += data_per_desc;
16727 +                       }
16728 +               }
16729 +               for(j = 0; j < dwc_ep->pkt_per_frm - 1; ++j)
16730 +               {
16731 +                       data_per_desc = ((j + 1) * dwc_ep->maxpacket > dwc_ep->data_per_frame) ?
16732 +                               dwc_ep->data_per_frame - j * dwc_ep->maxpacket : dwc_ep->maxpacket;
16733 +                       data_per_desc += (data_per_desc % 4) ? (4 - data_per_desc % 4):0;
16734 +                       sts.b_iso_out.rxbytes = data_per_desc;
16735 +                       writel((uint32_t)dma_ad, &dma_desc->buf);
16736 +                       writel(sts.d32, &dma_desc->status);
16737 +
16738 +                       offset += data_per_desc;
16739 +                       dma_desc ++;
16740 +                       (uint32_t)dma_ad += data_per_desc;
16741 +               }
16742 +
16743 +               sts.b_iso_out.ioc = 1;
16744 +               sts.b_iso_out.l = 1;
16745 +               data_per_desc = ((j + 1) * dwc_ep->maxpacket > dwc_ep->data_per_frame) ?
16746 +                       dwc_ep->data_per_frame - j * dwc_ep->maxpacket : dwc_ep->maxpacket;
16747 +               data_per_desc += (data_per_desc % 4) ? (4 - data_per_desc % 4):0;
16748 +               sts.b_iso_out.rxbytes = data_per_desc;
16749 +
16750 +               writel((uint32_t)dma_ad, &dma_desc->buf);
16751 +               writel(sts.d32, &dma_desc->status);
16752 +
16753 +               dwc_ep->next_frame = 0;
16754 +
16755 +               /** Write dma_ad into DOEPDMA register */
16756 +               dwc_write_reg32(&(out_regs->doepdma),(uint32_t)dwc_ep->iso_dma_desc_addr);
16757 +
16758 +       }
16759 +       /** ISO IN EP */
16760 +       else {
16761 +               desc_sts_data_t sts = { .d32 =0 };
16762 +               dwc_otg_dma_desc_t* dma_desc = dwc_ep->iso_desc_addr;
16763 +               dma_addr_t dma_ad;
16764 +               dwc_otg_dev_in_ep_regs_t *in_regs =
16765 +                       core_if->dev_if->in_ep_regs[dwc_ep->num];
16766 +               unsigned int               frmnumber;
16767 +               fifosize_data_t         txfifosize,rxfifosize;
16768 +
16769 +               txfifosize.d32 = dwc_read_reg32(&core_if->dev_if->in_ep_regs[dwc_ep->num]->dtxfsts);
16770 +               rxfifosize.d32 = dwc_read_reg32(&core_if->core_global_regs->grxfsiz);
16771 +
16772 +
16773 +               addr = &core_if->dev_if->in_ep_regs[dwc_ep->num]->diepctl;
16774 +
16775 +               dma_ad = dwc_ep->dma_addr0;
16776 +
16777 +               dsts.d32 = dwc_read_reg32(&core_if->dev_if->dev_global_regs->dsts);
16778 +
16779 +               sts.b_iso_in.bs = BS_HOST_READY;
16780 +               sts.b_iso_in.txsts = 0;
16781 +               sts.b_iso_in.sp = (dwc_ep->data_per_frame % dwc_ep->maxpacket)? 1 : 0;
16782 +               sts.b_iso_in.ioc = 0;
16783 +               sts.b_iso_in.pid = dwc_ep->pkt_per_frm;
16784 +
16785 +
16786 +               frmnumber = dwc_ep->next_frame;
16787 +
16788 +               sts.b_iso_in.framenum = frmnumber;
16789 +               sts.b_iso_in.txbytes = dwc_ep->data_per_frame;
16790 +               sts.b_iso_in.l = 0;
16791 +
16792 +               /** Buffer 0 descriptors setup */
16793 +               for(i = 0; i < dwc_ep->desc_cnt - 1; i++)
16794 +               {
16795 +                       writel((uint32_t)dma_ad, &dma_desc->buf);
16796 +                       writel(sts.d32, &dma_desc->status);
16797 +                       dma_desc ++;
16798 +
16799 +                       (uint32_t)dma_ad += dwc_ep->data_per_frame;
16800 +                       sts.b_iso_in.framenum += dwc_ep->bInterval;
16801 +               }
16802 +
16803 +               sts.b_iso_in.ioc = 1;
16804 +               writel((uint32_t)dma_ad, &dma_desc->buf);
16805 +               writel(sts.d32, &dma_desc->status);
16806 +               ++dma_desc;
16807 +
16808 +               /** Buffer 1 descriptors setup */
16809 +               sts.b_iso_in.ioc = 0;
16810 +               dma_ad = dwc_ep->dma_addr1;
16811 +
16812 +               for(i = 0; i < dwc_ep->desc_cnt - dwc_ep->pkt_per_frm; i+= dwc_ep->pkt_per_frm)
16813 +               {
16814 +                       writel((uint32_t)dma_ad, &dma_desc->buf);
16815 +                       writel(sts.d32, &dma_desc->status);
16816 +                       dma_desc ++;
16817 +
16818 +                       (uint32_t)dma_ad += dwc_ep->data_per_frame;
16819 +                       sts.b_iso_in.framenum += dwc_ep->bInterval;
16820 +
16821 +                       sts.b_iso_in.ioc = 0;
16822 +               }
16823 +               sts.b_iso_in.ioc = 1;
16824 +               sts.b_iso_in.l = 1;
16825 +
16826 +               writel((uint32_t)dma_ad, &dma_desc->buf);
16827 +               writel(sts.d32, &dma_desc->status);
16828 +
16829 +               dwc_ep->next_frame = sts.b_iso_in.framenum + dwc_ep->bInterval;
16830 +
16831 +               /** Write dma_ad into diepdma register */
16832 +               dwc_write_reg32(&(in_regs->diepdma),(uint32_t)dwc_ep->iso_dma_desc_addr);
16833 +       }
16834 +       /** Enable endpoint, clear nak  */
16835 +       depctl.d32 = 0;
16836 +       depctl.b.epena = 1;
16837 +       depctl.b.usbactep = 1;
16838 +       depctl.b.cnak = 1;
16839 +
16840 +       dwc_modify_reg32(addr, depctl.d32,depctl.d32);
16841 +       depctl.d32 = dwc_read_reg32(addr);
16842 +}
16843 +
16844 +/**
16845 + * This function initializes a descriptor chain for Isochronous transfer
16846 + *
16847 + * @param core_if Programming view of DWC_otg controller.
16848 + * @param ep The EP to start the transfer on.
16849 + *
16850 + */
16851 +
16852 +void dwc_otg_iso_ep_start_buf_transfer(dwc_otg_core_if_t *core_if, dwc_ep_t *ep)
16853 +{
16854 +       depctl_data_t           depctl = { .d32 = 0 };
16855 +       volatile uint32_t       *addr;
16856 +
16857 +
16858 +       if(ep->is_in) {
16859 +               addr = &core_if->dev_if->in_ep_regs[ep->num]->diepctl;
16860 +       } else {
16861 +               addr = &core_if->dev_if->out_ep_regs[ep->num]->doepctl;
16862 +       }
16863 +
16864 +
16865 +       if(core_if->dma_enable == 0 || core_if->dma_desc_enable!= 0) {
16866 +               return;
16867 +       } else {
16868 +               deptsiz_data_t          deptsiz = { .d32 = 0 };
16869 +
16870 +               ep->xfer_len = ep->data_per_frame * ep->buf_proc_intrvl / ep->bInterval;
16871 +               ep->pkt_cnt = (ep->xfer_len - 1 + ep->maxpacket) /
16872 +                               ep->maxpacket;
16873 +               ep->xfer_count = 0;
16874 +               ep->xfer_buff = (ep->proc_buf_num) ? ep->xfer_buff1 : ep->xfer_buff0;
16875 +               ep->dma_addr = (ep->proc_buf_num) ? ep->dma_addr1 : ep->dma_addr0;
16876 +
16877 +               if(ep->is_in) {
16878 +                       /* Program the transfer size and packet count
16879 +                        *      as follows: xfersize = N * maxpacket +
16880 +                        *      short_packet pktcnt = N + (short_packet
16881 +                        *      exist ? 1 : 0)
16882 +                        */
16883 +                       deptsiz.b.mc = ep->pkt_per_frm;
16884 +                       deptsiz.b.xfersize = ep->xfer_len;
16885 +                       deptsiz.b.pktcnt =
16886 +                               (ep->xfer_len - 1 + ep->maxpacket) /
16887 +                               ep->maxpacket;
16888 +                       dwc_write_reg32(&core_if->dev_if->in_ep_regs[ep->num]->dieptsiz, deptsiz.d32);
16889 +
16890 +                       /* Write the DMA register */
16891 +                       dwc_write_reg32 (&(core_if->dev_if->in_ep_regs[ep->num]->diepdma), (uint32_t)ep->dma_addr);
16892 +
16893 +               } else {
16894 +                       deptsiz.b.pktcnt =
16895 +                                       (ep->xfer_len + (ep->maxpacket - 1)) /
16896 +                                       ep->maxpacket;
16897 +                       deptsiz.b.xfersize = deptsiz.b.pktcnt * ep->maxpacket;
16898 +
16899 +                       dwc_write_reg32(&core_if->dev_if->out_ep_regs[ep->num]->doeptsiz, deptsiz.d32);
16900 +
16901 +                       /* Write the DMA register */
16902 +                       dwc_write_reg32 (&(core_if->dev_if->out_ep_regs[ep->num]->doepdma), (uint32_t)ep->dma_addr);
16903 +
16904 +               }
16905 +               /** Enable endpoint, clear nak  */
16906 +               depctl.d32 = 0;
16907 +               dwc_modify_reg32(addr, depctl.d32,depctl.d32);
16908 +
16909 +               depctl.b.epena = 1;
16910 +               depctl.b.cnak = 1;
16911 +
16912 +               dwc_modify_reg32(addr, depctl.d32,depctl.d32);
16913 +       }
16914 +}
16915 +
16916 +
16917 +/**
16918 + * This function does the setup for a data transfer for an EP and
16919 + * starts the transfer.         For an IN transfer, the packets will be
16920 + * loaded into the appropriate Tx FIFO in the ISR. For OUT transfers,
16921 + * the packets are unloaded from the Rx FIFO in the ISR.  the ISR.
16922 + *
16923 + * @param core_if Programming view of DWC_otg controller.
16924 + * @param ep The EP to start the transfer on.
16925 + */
16926 +
16927 +void dwc_otg_iso_ep_start_transfer(dwc_otg_core_if_t *core_if, dwc_ep_t *ep)
16928 +{
16929 +       if(core_if->dma_enable) {
16930 +               if(core_if->dma_desc_enable) {
16931 +                       if(ep->is_in) {
16932 +                               ep->desc_cnt = ep->pkt_cnt / ep->pkt_per_frm;
16933 +                       } else {
16934 +                               ep->desc_cnt = ep->pkt_cnt;
16935 +                       }
16936 +                       dwc_otg_iso_ep_start_ddma_transfer(core_if, ep);
16937 +               } else {
16938 +                       if(core_if->pti_enh_enable) {
16939 +                               dwc_otg_iso_ep_start_buf_transfer(core_if, ep);
16940 +                       } else {
16941 +                               ep->cur_pkt_addr = (ep->proc_buf_num) ? ep->xfer_buff1 : ep->xfer_buff0;
16942 +                               ep->cur_pkt_dma_addr = (ep->proc_buf_num) ? ep->dma_addr1 : ep->dma_addr0;
16943 +                               dwc_otg_iso_ep_start_frm_transfer(core_if, ep);
16944 +                       }
16945 +               }
16946 +       } else {
16947 +               ep->cur_pkt_addr = (ep->proc_buf_num) ? ep->xfer_buff1 : ep->xfer_buff0;
16948 +               ep->cur_pkt_dma_addr = (ep->proc_buf_num) ? ep->dma_addr1 : ep->dma_addr0;
16949 +               dwc_otg_iso_ep_start_frm_transfer(core_if, ep);
16950 +       }
16951 +}
16952 +
16953 +/**
16954 + * This function does the setup for a data transfer for an EP and
16955 + * starts the transfer.         For an IN transfer, the packets will be
16956 + * loaded into the appropriate Tx FIFO in the ISR. For OUT transfers,
16957 + * the packets are unloaded from the Rx FIFO in the ISR.  the ISR.
16958 + *
16959 + * @param core_if Programming view of DWC_otg controller.
16960 + * @param ep The EP to start the transfer on.
16961 + */
16962 +
16963 +void dwc_otg_iso_ep_stop_transfer(dwc_otg_core_if_t *core_if, dwc_ep_t *ep)
16964 +{
16965 +       depctl_data_t depctl = { .d32 = 0 };
16966 +       volatile uint32_t *addr;
16967 +
16968 +       if(ep->is_in == 1) {
16969 +               addr = &core_if->dev_if->in_ep_regs[ep->num]->diepctl;
16970 +       }
16971 +       else {
16972 +               addr = &core_if->dev_if->out_ep_regs[ep->num]->doepctl;
16973 +       }
16974 +
16975 +       /* disable the ep */
16976 +       depctl.d32 = dwc_read_reg32(addr);
16977 +
16978 +       depctl.b.epdis = 1;
16979 +       depctl.b.snak = 1;
16980 +
16981 +       dwc_write_reg32(addr, depctl.d32);
16982 +
16983 +       if(core_if->dma_desc_enable &&
16984 +               ep->iso_desc_addr && ep->iso_dma_desc_addr) {
16985 +               dwc_otg_ep_free_desc_chain(ep->iso_desc_addr,ep->iso_dma_desc_addr,ep->desc_cnt * 2);
16986 +       }
16987 +
16988 +       /* reset varibales */
16989 +       ep->dma_addr0 = 0;
16990 +       ep->dma_addr1 = 0;
16991 +       ep->xfer_buff0 = 0;
16992 +       ep->xfer_buff1 = 0;
16993 +       ep->data_per_frame = 0;
16994 +       ep->data_pattern_frame = 0;
16995 +       ep->sync_frame = 0;
16996 +       ep->buf_proc_intrvl = 0;
16997 +       ep->bInterval = 0;
16998 +       ep->proc_buf_num = 0;
16999 +       ep->pkt_per_frm = 0;
17000 +       ep->pkt_per_frm = 0;
17001 +       ep->desc_cnt =  0;
17002 +       ep->iso_desc_addr = 0;
17003 +       ep->iso_dma_desc_addr = 0;
17004 +}
17005 +
17006 +
17007 +/**
17008 + * This function is used to submit an ISOC Transfer Request to an EP.
17009 + *
17010 + *     - Every time a sync period completes the request's completion callback
17011 + *       is called to provide data to the gadget driver.
17012 + *     - Once submitted the request cannot be modified.
17013 + *     - Each request is turned into periodic data packets untill ISO
17014 + *       Transfer is stopped..
17015 + */
17016 +static int dwc_otg_pcd_iso_ep_start(struct usb_ep *usb_ep, struct usb_iso_request *req,
17017 +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,20)
17018 +                               int gfp_flags
17019 +#else
17020 +                               gfp_t gfp_flags
17021 +#endif
17022 +)
17023 +{
17024 +       dwc_otg_pcd_ep_t        *ep;
17025 +       dwc_otg_pcd_t           *pcd;
17026 +       dwc_ep_t                *dwc_ep;
17027 +       unsigned long           flags = 0;
17028 +       int32_t                 frm_data;
17029 +       dwc_otg_core_if_t       *core_if;
17030 +       dcfg_data_t             dcfg;
17031 +       dsts_data_t             dsts;
17032 +
17033 +
17034 +       if (!req || !req->process_buffer || !req->buf0 || !req->buf1) {
17035 +               DWC_WARN("%s, bad params\n", __func__);
17036 +               return -EINVAL;
17037 +       }
17038 +
17039 +       ep = container_of(usb_ep, dwc_otg_pcd_ep_t, ep);
17040 +
17041 +       if (!usb_ep || !ep->desc || ep->dwc_ep.num == 0) {
17042 +               DWC_WARN("%s, bad ep\n", __func__);
17043 +               return -EINVAL;
17044 +       }
17045 +
17046 +       pcd = ep->pcd;
17047 +       core_if = GET_CORE_IF(pcd);
17048 +
17049 +       dcfg.d32 = dwc_read_reg32(&core_if->dev_if->dev_global_regs->dcfg);
17050 +
17051 +       if (!pcd->driver || pcd->gadget.speed == USB_SPEED_UNKNOWN) {
17052 +               DWC_DEBUGPL(DBG_PCDV, "gadget.speed=%d\n", pcd->gadget.speed);
17053 +               DWC_WARN("%s, bogus device state\n", __func__);
17054 +               return -ESHUTDOWN;
17055 +       }
17056 +
17057 +       SPIN_LOCK_IRQSAVE(&ep->pcd->lock, flags);
17058 +
17059 +       dwc_ep = &ep->dwc_ep;
17060 +
17061 +       if(ep->iso_req) {
17062 +               DWC_WARN("%s, iso request in progress\n", __func__);
17063 +       }
17064 +       req->status = -EINPROGRESS;
17065 +
17066 +       dwc_ep->dma_addr0 = req->dma0;
17067 +       dwc_ep->dma_addr1 = req->dma1;
17068 +
17069 +       dwc_ep->xfer_buff0 = req->buf0;
17070 +       dwc_ep->xfer_buff1 = req->buf1;
17071 +
17072 +       ep->iso_req = req;
17073 +
17074 +       dwc_ep->data_per_frame = req->data_per_frame;
17075 +
17076 +       /** @todo - pattern data support is to be implemented in the future */
17077 +       dwc_ep->data_pattern_frame = req->data_pattern_frame;
17078 +       dwc_ep->sync_frame = req->sync_frame;
17079 +
17080 +       dwc_ep->buf_proc_intrvl = req->buf_proc_intrvl;
17081 +
17082 +       dwc_ep->bInterval = 1 << (ep->desc->bInterval - 1);
17083 +
17084 +       dwc_ep->proc_buf_num = 0;
17085 +
17086 +       dwc_ep->pkt_per_frm = 0;
17087 +       frm_data = ep->dwc_ep.data_per_frame;
17088 +       while(frm_data > 0) {
17089 +               dwc_ep->pkt_per_frm++;
17090 +               frm_data -= ep->dwc_ep.maxpacket;
17091 +       }
17092 +
17093 +       dsts.d32 = dwc_read_reg32(&core_if->dev_if->dev_global_regs->dsts);
17094 +
17095 +       if(req->flags & USB_REQ_ISO_ASAP) {
17096 +               dwc_ep->next_frame = dsts.b.soffn + 1;
17097 +               if(dwc_ep->bInterval != 1){
17098 +                       dwc_ep->next_frame = dwc_ep->next_frame + (dwc_ep->bInterval - 1 - dwc_ep->next_frame % dwc_ep->bInterval);
17099 +               }
17100 +       } else {
17101 +               dwc_ep->next_frame = req->start_frame;
17102 +       }
17103 +
17104 +
17105 +       if(!core_if->pti_enh_enable) {
17106 +               dwc_ep->pkt_cnt = dwc_ep->buf_proc_intrvl * dwc_ep->pkt_per_frm / dwc_ep->bInterval;
17107 +       } else {
17108 +               dwc_ep->pkt_cnt =
17109 +                       (dwc_ep->data_per_frame * (dwc_ep->buf_proc_intrvl / dwc_ep->bInterval)
17110 +                       - 1 + dwc_ep->maxpacket) / dwc_ep->maxpacket;
17111 +       }
17112 +
17113 +       if(core_if->dma_desc_enable) {
17114 +               dwc_ep->desc_cnt =
17115 +                       dwc_ep->buf_proc_intrvl * dwc_ep->pkt_per_frm / dwc_ep->bInterval;
17116 +       }
17117 +
17118 +       dwc_ep->pkt_info = kmalloc(sizeof(iso_pkt_info_t) * dwc_ep->pkt_cnt, GFP_KERNEL);
17119 +       if(!dwc_ep->pkt_info) {
17120 +               return -ENOMEM;
17121 +       }
17122 +       if(core_if->pti_enh_enable) {
17123 +               memset(dwc_ep->pkt_info, 0, sizeof(iso_pkt_info_t) * dwc_ep->pkt_cnt);
17124 +       }
17125 +
17126 +       dwc_ep->cur_pkt = 0;
17127 +
17128 +       SPIN_UNLOCK_IRQRESTORE(&pcd->lock, flags);
17129 +
17130 +       dwc_otg_iso_ep_start_transfer(core_if, dwc_ep);
17131 +
17132 +       return 0;
17133 +}
17134 +
17135 +/**
17136 + * This function stops ISO EP Periodic Data Transfer.
17137 + */
17138 +static int dwc_otg_pcd_iso_ep_stop(struct usb_ep *usb_ep, struct usb_iso_request *req)
17139 +{
17140 +       dwc_otg_pcd_ep_t *ep;
17141 +       dwc_otg_pcd_t   *pcd;
17142 +       dwc_ep_t *dwc_ep;
17143 +       unsigned long flags;
17144 +
17145 +       ep = container_of(usb_ep, dwc_otg_pcd_ep_t, ep);
17146 +
17147 +       if (!usb_ep || !ep->desc || ep->dwc_ep.num == 0) {
17148 +               DWC_WARN("%s, bad ep\n", __func__);
17149 +               return -EINVAL;
17150 +       }
17151 +
17152 +       pcd = ep->pcd;
17153 +
17154 +       if (!pcd->driver || pcd->gadget.speed == USB_SPEED_UNKNOWN) {
17155 +               DWC_DEBUGPL(DBG_PCDV, "gadget.speed=%d\n", pcd->gadget.speed);
17156 +               DWC_WARN("%s, bogus device state\n", __func__);
17157 +               return -ESHUTDOWN;
17158 +       }
17159 +
17160 +       dwc_ep = &ep->dwc_ep;
17161 +
17162 +       dwc_otg_iso_ep_stop_transfer(GET_CORE_IF(pcd), dwc_ep);
17163 +
17164 +       kfree(dwc_ep->pkt_info);
17165 +
17166 +       SPIN_LOCK_IRQSAVE(&pcd->lock, flags);
17167 +
17168 +       if(ep->iso_req != req) {
17169 +               return -EINVAL;
17170 +       }
17171 +
17172 +       req->status = -ECONNRESET;
17173 +
17174 +       SPIN_UNLOCK_IRQRESTORE(&pcd->lock, flags);
17175 +
17176 +
17177 +       ep->iso_req = 0;
17178 +
17179 +       return 0;
17180 +}
17181 +
17182 +/**
17183 + * This function is used for perodical data exchnage between PCD and gadget drivers.
17184 + * for Isochronous EPs
17185 + *
17186 + *     - Every time a sync period completes this function is called to
17187 + *       perform data exchange between PCD and gadget
17188 + */
17189 +void dwc_otg_iso_buffer_done(dwc_otg_pcd_ep_t *ep, dwc_otg_pcd_iso_request_t *req)
17190 +{
17191 +       int i;
17192 +       struct usb_gadget_iso_packet_descriptor *iso_packet;
17193 +       dwc_ep_t *dwc_ep;
17194 +
17195 +       dwc_ep = &ep->dwc_ep;
17196 +
17197 +       if(ep->iso_req->status == -ECONNRESET) {
17198 +               DWC_PRINT("Device has already disconnected\n");
17199 +               /*Device has been disconnected*/
17200 +               return;
17201 +       }
17202 +
17203 +       if(dwc_ep->proc_buf_num != 0) {
17204 +               iso_packet = ep->iso_req->iso_packet_desc0;
17205 +       }
17206 +
17207 +       else {
17208 +               iso_packet = ep->iso_req->iso_packet_desc1;
17209 +       }
17210 +
17211 +       /* Fill in ISOC packets descriptors & pass to gadget driver*/
17212 +
17213 +       for(i = 0; i < dwc_ep->pkt_cnt; ++i) {
17214 +               iso_packet[i].status = dwc_ep->pkt_info[i].status;
17215 +               iso_packet[i].offset = dwc_ep->pkt_info[i].offset;
17216 +               iso_packet[i].actual_length = dwc_ep->pkt_info[i].length;
17217 +               dwc_ep->pkt_info[i].status = 0;
17218 +               dwc_ep->pkt_info[i].offset = 0;
17219 +               dwc_ep->pkt_info[i].length = 0;
17220 +       }
17221 +
17222 +       /* Call callback function to process data buffer */
17223 +       ep->iso_req->status = 0;/* success */
17224 +
17225 +       SPIN_UNLOCK(&ep->pcd->lock);
17226 +       ep->iso_req->process_buffer(&ep->ep, ep->iso_req);
17227 +       SPIN_LOCK(&ep->pcd->lock);
17228 +}
17229 +
17230 +
17231 +static struct usb_iso_request *dwc_otg_pcd_alloc_iso_request(struct usb_ep *ep,int packets,
17232 +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,20)
17233 +                               int gfp_flags
17234 +#else
17235 +                               gfp_t gfp_flags
17236 +#endif
17237 +)
17238 +{
17239 +       struct usb_iso_request  *pReq = NULL;
17240 +       uint32_t                req_size;
17241 +
17242 +
17243 +       req_size = sizeof(struct usb_iso_request);
17244 +       req_size += (2 * packets * (sizeof(struct usb_gadget_iso_packet_descriptor)));
17245 +
17246 +
17247 +       pReq = kmalloc(req_size, gfp_flags);
17248 +       if (!pReq) {
17249 +               DWC_WARN("%s, can't allocate Iso Request\n", __func__);
17250 +               return 0;
17251 +       }
17252 +       pReq->iso_packet_desc0 = (void*) (pReq +  1);
17253 +
17254 +       pReq->iso_packet_desc1 = pReq->iso_packet_desc0 + packets;
17255 +
17256 +       return pReq;
17257 +}
17258 +
17259 +static void dwc_otg_pcd_free_iso_request(struct usb_ep *ep, struct usb_iso_request *req)
17260 +{
17261 +       kfree(req);
17262 +}
17263 +
17264 +static struct usb_isoc_ep_ops dwc_otg_pcd_ep_ops =
17265 +{
17266 +       .ep_ops =
17267 +       {
17268 +               .enable         = dwc_otg_pcd_ep_enable,
17269 +               .disable        = dwc_otg_pcd_ep_disable,
17270 +
17271 +               .alloc_request  = dwc_otg_pcd_alloc_request,
17272 +               .free_request   = dwc_otg_pcd_free_request,
17273 +
17274 +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,23)
17275 +               .alloc_buffer   = dwc_otg_pcd_alloc_buffer,
17276 +               .free_buffer    = dwc_otg_pcd_free_buffer,
17277 +#endif
17278 +
17279 +               .queue          = dwc_otg_pcd_ep_queue,
17280 +               .dequeue        = dwc_otg_pcd_ep_dequeue,
17281 +
17282 +               .set_halt       = dwc_otg_pcd_ep_set_halt,
17283 +               .fifo_status    = 0,
17284 +               .fifo_flush = 0,
17285 +       },
17286 +       .iso_ep_start           = dwc_otg_pcd_iso_ep_start,
17287 +       .iso_ep_stop            = dwc_otg_pcd_iso_ep_stop,
17288 +       .alloc_iso_request      = dwc_otg_pcd_alloc_iso_request,
17289 +       .free_iso_request       = dwc_otg_pcd_free_iso_request,
17290 +};
17291 +
17292 +#else
17293 +
17294 +
17295 +static struct usb_ep_ops dwc_otg_pcd_ep_ops =
17296 +{
17297 +       .enable         = dwc_otg_pcd_ep_enable,
17298 +       .disable        = dwc_otg_pcd_ep_disable,
17299 +
17300 +       .alloc_request  = dwc_otg_pcd_alloc_request,
17301 +       .free_request   = dwc_otg_pcd_free_request,
17302 +
17303 +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,23)
17304 +       .alloc_buffer   = dwc_otg_pcd_alloc_buffer,
17305 +       .free_buffer    = dwc_otg_pcd_free_buffer,
17306 +#endif
17307 +
17308 +       .queue          = dwc_otg_pcd_ep_queue,
17309 +       .dequeue        = dwc_otg_pcd_ep_dequeue,
17310 +
17311 +       .set_halt       = dwc_otg_pcd_ep_set_halt,
17312 +       .fifo_status    = 0,
17313 +       .fifo_flush = 0,
17314 +
17315 +
17316 +};
17317 +
17318 +#endif /* DWC_EN_ISOC */
17319 +/*     Gadget Operations */
17320 +/**
17321 + * The following gadget operations will be implemented in the DWC_otg
17322 + * PCD. Functions in the API that are not described below are not
17323 + * implemented.
17324 + *
17325 + * The Gadget API provides wrapper functions for each of the function
17326 + * pointers defined in usb_gadget_ops. The Gadget Driver calls the
17327 + * wrapper function, which then calls the underlying PCD function. The
17328 + * following sections are named according to the wrapper functions
17329 + * (except for ioctl, which doesn't have a wrapper function). Within
17330 + * each section, the corresponding DWC_otg PCD function name is
17331 + * specified.
17332 + *
17333 + */
17334 +
17335 +/**
17336 + *Gets the USB Frame number of the last SOF.
17337 + */
17338 +static int dwc_otg_pcd_get_frame(struct usb_gadget *gadget)
17339 +{
17340 +       dwc_otg_pcd_t *pcd;
17341 +
17342 +       DWC_DEBUGPL(DBG_PCDV,"%s(%p)\n", __func__, gadget);
17343 +
17344 +       if (gadget == 0) {
17345 +               return -ENODEV;
17346 +       }
17347 +       else {
17348 +               pcd = container_of(gadget, dwc_otg_pcd_t, gadget);
17349 +               dwc_otg_get_frame_number(GET_CORE_IF(pcd));
17350 +       }
17351 +
17352 +       return 0;
17353 +}
17354 +
17355 +void dwc_otg_pcd_initiate_srp(dwc_otg_pcd_t *pcd)
17356 +{
17357 +       uint32_t *addr = (uint32_t *)&(GET_CORE_IF(pcd)->core_global_regs->gotgctl);
17358 +       gotgctl_data_t mem;
17359 +       gotgctl_data_t val;
17360 +
17361 +       val.d32 = dwc_read_reg32(addr);
17362 +       if (val.b.sesreq) {
17363 +               DWC_ERROR("Session Request Already active!\n");
17364 +                       return;
17365 +       }
17366 +
17367 +       DWC_NOTICE("Session Request Initated\n");
17368 +       mem.d32 = dwc_read_reg32(addr);
17369 +       mem.b.sesreq = 1;
17370 +       dwc_write_reg32(addr, mem.d32);
17371 +
17372 +       /* Start the SRP timer */
17373 +       dwc_otg_pcd_start_srp_timer(pcd);
17374 +       return;
17375 +}
17376 +
17377 +void dwc_otg_pcd_remote_wakeup(dwc_otg_pcd_t *pcd, int set)
17378 +{
17379 +       dctl_data_t dctl = {.d32=0};
17380 +       volatile uint32_t *addr = &(GET_CORE_IF(pcd)->dev_if->dev_global_regs->dctl);
17381 +
17382 +       if (dwc_otg_is_device_mode(GET_CORE_IF(pcd))) {
17383 +               if (pcd->remote_wakeup_enable) {
17384 +                       if (set) {
17385 +                               dctl.b.rmtwkupsig = 1;
17386 +                               dwc_modify_reg32(addr, 0, dctl.d32);
17387 +                               DWC_DEBUGPL(DBG_PCD, "Set Remote Wakeup\n");
17388 +                               mdelay(1);
17389 +                               dwc_modify_reg32(addr, dctl.d32, 0);
17390 +                               DWC_DEBUGPL(DBG_PCD, "Clear Remote Wakeup\n");
17391 +                       }
17392 +                       else {
17393 +                       }
17394 +               }
17395 +               else {
17396 +                       DWC_DEBUGPL(DBG_PCD, "Remote Wakeup is disabled\n");
17397 +               }
17398 +       }
17399 +       return;
17400 +}
17401 +
17402 +/**
17403 + * Initiates Session Request Protocol (SRP) to wakeup the host if no
17404 + * session is in progress. If a session is already in progress, but
17405 + * the device is suspended, remote wakeup signaling is started.
17406 + *
17407 + */
17408 +static int dwc_otg_pcd_wakeup(struct usb_gadget *gadget)
17409 +{
17410 +       unsigned long flags;
17411 +       dwc_otg_pcd_t *pcd;
17412 +       dsts_data_t             dsts;
17413 +       gotgctl_data_t  gotgctl;
17414 +
17415 +       DWC_DEBUGPL(DBG_PCDV,"%s(%p)\n", __func__, gadget);
17416 +
17417 +       if (gadget == 0) {
17418 +               return -ENODEV;
17419 +       }
17420 +       else {
17421 +               pcd = container_of(gadget, dwc_otg_pcd_t, gadget);
17422 +       }
17423 +       SPIN_LOCK_IRQSAVE(&pcd->lock, flags);
17424 +
17425 +       /*
17426 +        * This function starts the Protocol if no session is in progress. If
17427 +        * a session is already in progress, but the device is suspended,
17428 +        * remote wakeup signaling is started.
17429 +        */
17430 +
17431 +       /* Check if valid session */
17432 +       gotgctl.d32 = dwc_read_reg32(&(GET_CORE_IF(pcd)->core_global_regs->gotgctl));
17433 +       if (gotgctl.b.bsesvld) {
17434 +               /* Check if suspend state */
17435 +               dsts.d32 = dwc_read_reg32(&(GET_CORE_IF(pcd)->dev_if->dev_global_regs->dsts));
17436 +               if (dsts.b.suspsts) {
17437 +                       dwc_otg_pcd_remote_wakeup(pcd, 1);
17438 +               }
17439 +       }
17440 +       else {
17441 +               dwc_otg_pcd_initiate_srp(pcd);
17442 +       }
17443 +
17444 +       SPIN_UNLOCK_IRQRESTORE(&pcd->lock, flags);
17445 +       return 0;
17446 +}
17447 +
17448 +static const struct usb_gadget_ops dwc_otg_pcd_ops =
17449 +{
17450 +       .get_frame       = dwc_otg_pcd_get_frame,
17451 +       .wakeup          = dwc_otg_pcd_wakeup,
17452 +       // current versions must always be self-powered
17453 +};
17454 +
17455 +/**
17456 + * This function updates the otg values in the gadget structure.
17457 + */
17458 +void dwc_otg_pcd_update_otg(dwc_otg_pcd_t *pcd, const unsigned reset)
17459 +{
17460 +
17461 +       if (!pcd->gadget.is_otg)
17462 +               return;
17463 +
17464 +       if (reset) {
17465 +               pcd->b_hnp_enable = 0;
17466 +               pcd->a_hnp_support = 0;
17467 +               pcd->a_alt_hnp_support = 0;
17468 +       }
17469 +
17470 +       pcd->gadget.b_hnp_enable = pcd->b_hnp_enable;
17471 +       pcd->gadget.a_hnp_support =  pcd->a_hnp_support;
17472 +       pcd->gadget.a_alt_hnp_support = pcd->a_alt_hnp_support;
17473 +}
17474 +
17475 +/**
17476 + * This function is the top level PCD interrupt handler.
17477 + */
17478 +static irqreturn_t dwc_otg_pcd_irq(int irq, void *dev
17479 +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,19)
17480 +                                  , struct pt_regs *r
17481 +#endif
17482 +                                )
17483 +{
17484 +       dwc_otg_pcd_t *pcd = dev;
17485 +       int32_t retval = IRQ_NONE;
17486 +
17487 +       retval = dwc_otg_pcd_handle_intr(pcd);
17488 +       return IRQ_RETVAL(retval);
17489 +}
17490 +
17491 +/**
17492 + * PCD Callback function for initializing the PCD when switching to
17493 + * device mode.
17494 + *
17495 + * @param p void pointer to the <code>dwc_otg_pcd_t</code>
17496 + */
17497 +static int32_t dwc_otg_pcd_start_cb(void *p)
17498 +{
17499 +       dwc_otg_pcd_t *pcd = (dwc_otg_pcd_t *)p;
17500 +
17501 +       /*
17502 +        * Initialized the Core for Device mode.
17503 +        */
17504 +       if (dwc_otg_is_device_mode(GET_CORE_IF(pcd))) {
17505 +               dwc_otg_core_dev_init(GET_CORE_IF(pcd));
17506 +       }
17507 +       return 1;
17508 +}
17509 +
17510 +/**
17511 + * PCD Callback function for stopping the PCD when switching to Host
17512 + * mode.
17513 + *
17514 + * @param p void pointer to the <code>dwc_otg_pcd_t</code>
17515 + */
17516 +static int32_t dwc_otg_pcd_stop_cb(void *p)
17517 +{
17518 +       dwc_otg_pcd_t *pcd = (dwc_otg_pcd_t *)p;
17519 +       extern void dwc_otg_pcd_stop(dwc_otg_pcd_t *_pcd);
17520 +
17521 +       dwc_otg_pcd_stop(pcd);
17522 +       return 1;
17523 +}
17524 +
17525 +
17526 +/**
17527 + * PCD Callback function for notifying the PCD when resuming from
17528 + * suspend.
17529 + *
17530 + * @param p void pointer to the <code>dwc_otg_pcd_t</code>
17531 + */
17532 +static int32_t dwc_otg_pcd_suspend_cb(void *p)
17533 +{
17534 +       dwc_otg_pcd_t *pcd = (dwc_otg_pcd_t *)p;
17535 +
17536 +       if (pcd->driver && pcd->driver->resume) {
17537 +               SPIN_UNLOCK(&pcd->lock);
17538 +               pcd->driver->suspend(&pcd->gadget);
17539 +               SPIN_LOCK(&pcd->lock);
17540 +       }
17541 +
17542 +       return 1;
17543 +}
17544 +
17545 +
17546 +/**
17547 + * PCD Callback function for notifying the PCD when resuming from
17548 + * suspend.
17549 + *
17550 + * @param p void pointer to the <code>dwc_otg_pcd_t</code>
17551 + */
17552 +static int32_t dwc_otg_pcd_resume_cb(void *p)
17553 +{
17554 +       dwc_otg_pcd_t *pcd = (dwc_otg_pcd_t *)p;
17555 +
17556 +       if (pcd->driver && pcd->driver->resume) {
17557 +                       SPIN_UNLOCK(&pcd->lock);
17558 +                       pcd->driver->resume(&pcd->gadget);
17559 +                       SPIN_LOCK(&pcd->lock);
17560 +       }
17561 +
17562 +       /* Stop the SRP timeout timer. */
17563 +       if ((GET_CORE_IF(pcd)->core_params->phy_type != DWC_PHY_TYPE_PARAM_FS) ||
17564 +               (!GET_CORE_IF(pcd)->core_params->i2c_enable)) {
17565 +               if (GET_CORE_IF(pcd)->srp_timer_started) {
17566 +                       GET_CORE_IF(pcd)->srp_timer_started = 0;
17567 +                       del_timer(&pcd->srp_timer);
17568 +               }
17569 +       }
17570 +       return 1;
17571 +}
17572 +
17573 +
17574 +/**
17575 + * PCD Callback structure for handling mode switching.
17576 + */
17577 +static dwc_otg_cil_callbacks_t pcd_callbacks =
17578 +{
17579 +       .start = dwc_otg_pcd_start_cb,
17580 +       .stop = dwc_otg_pcd_stop_cb,
17581 +       .suspend = dwc_otg_pcd_suspend_cb,
17582 +       .resume_wakeup = dwc_otg_pcd_resume_cb,
17583 +       .p = 0, /* Set at registration */
17584 +};
17585 +
17586 +/**
17587 + * This function is called when the SRP timer expires. The SRP should
17588 + * complete within 6 seconds.
17589 + */
17590 +static void srp_timeout(unsigned long ptr)
17591 +{
17592 +       gotgctl_data_t gotgctl;
17593 +       dwc_otg_core_if_t *core_if = (dwc_otg_core_if_t *)ptr;
17594 +       volatile uint32_t *addr = &core_if->core_global_regs->gotgctl;
17595 +
17596 +       gotgctl.d32 = dwc_read_reg32(addr);
17597 +
17598 +       core_if->srp_timer_started = 0;
17599 +
17600 +       if ((core_if->core_params->phy_type == DWC_PHY_TYPE_PARAM_FS) &&
17601 +               (core_if->core_params->i2c_enable)) {
17602 +               DWC_PRINT("SRP Timeout\n");
17603 +
17604 +               if ((core_if->srp_success) &&
17605 +                       (gotgctl.b.bsesvld)) {
17606 +                       if (core_if->pcd_cb && core_if->pcd_cb->resume_wakeup) {
17607 +                               core_if->pcd_cb->resume_wakeup(core_if->pcd_cb->p);
17608 +                       }
17609 +
17610 +                       /* Clear Session Request */
17611 +                       gotgctl.d32 = 0;
17612 +                       gotgctl.b.sesreq = 1;
17613 +                       dwc_modify_reg32(&core_if->core_global_regs->gotgctl,
17614 +                                         gotgctl.d32, 0);
17615 +
17616 +                       core_if->srp_success = 0;
17617 +               }
17618 +               else {
17619 +                       DWC_ERROR("Device not connected/responding\n");
17620 +                       gotgctl.b.sesreq = 0;
17621 +                       dwc_write_reg32(addr, gotgctl.d32);
17622 +               }
17623 +       }
17624 +       else if (gotgctl.b.sesreq) {
17625 +               DWC_PRINT("SRP Timeout\n");
17626 +
17627 +               DWC_ERROR("Device not connected/responding\n");
17628 +               gotgctl.b.sesreq = 0;
17629 +               dwc_write_reg32(addr, gotgctl.d32);
17630 +       }
17631 +       else {
17632 +               DWC_PRINT(" SRP GOTGCTL=%0x\n", gotgctl.d32);
17633 +       }
17634 +}
17635 +
17636 +/**
17637 + * Start the SRP timer to detect when the SRP does not complete within
17638 + * 6 seconds.
17639 + *
17640 + * @param pcd the pcd structure.
17641 + */
17642 +void dwc_otg_pcd_start_srp_timer(dwc_otg_pcd_t *pcd)
17643 +{
17644 +       struct timer_list *srp_timer = &pcd->srp_timer;
17645 +       GET_CORE_IF(pcd)->srp_timer_started = 1;
17646 +       init_timer(srp_timer);
17647 +       srp_timer->function = srp_timeout;
17648 +       srp_timer->data = (unsigned long)GET_CORE_IF(pcd);
17649 +       srp_timer->expires = jiffies + (HZ*6);
17650 +       add_timer(srp_timer);
17651 +}
17652 +
17653 +/**
17654 + * Tasklet
17655 + *
17656 + */
17657 +extern void start_next_request(dwc_otg_pcd_ep_t *ep);
17658 +
17659 +static void start_xfer_tasklet_func (unsigned long data)
17660 +{
17661 +       dwc_otg_pcd_t *pcd = (dwc_otg_pcd_t*)data;
17662 +       dwc_otg_core_if_t *core_if = pcd->otg_dev->core_if;
17663 +
17664 +       int i;
17665 +       depctl_data_t diepctl;
17666 +
17667 +       DWC_DEBUGPL(DBG_PCDV, "Start xfer tasklet\n");
17668 +
17669 +       diepctl.d32 = dwc_read_reg32(&core_if->dev_if->in_ep_regs[0]->diepctl);
17670 +
17671 +       if (pcd->ep0.queue_sof) {
17672 +               pcd->ep0.queue_sof = 0;
17673 +               start_next_request (&pcd->ep0);
17674 +               // break;
17675 +       }
17676 +
17677 +       for (i=0; i<core_if->dev_if->num_in_eps; i++)
17678 +       {
17679 +               depctl_data_t diepctl;
17680 +               diepctl.d32 = dwc_read_reg32(&core_if->dev_if->in_ep_regs[i]->diepctl);
17681 +
17682 +               if (pcd->in_ep[i].queue_sof) {
17683 +                       pcd->in_ep[i].queue_sof = 0;
17684 +                       start_next_request (&pcd->in_ep[i]);
17685 +                       // break;
17686 +               }
17687 +       }
17688 +
17689 +       return;
17690 +}
17691 +
17692 +
17693 +
17694 +
17695 +
17696 +
17697 +
17698 +static struct tasklet_struct start_xfer_tasklet = {
17699 +       .next = NULL,
17700 +       .state = 0,
17701 +       .count = ATOMIC_INIT(0),
17702 +       .func = start_xfer_tasklet_func,
17703 +       .data = 0,
17704 +};
17705 +/**
17706 + * This function initialized the pcd Dp structures to there default
17707 + * state.
17708 + *
17709 + * @param pcd the pcd structure.
17710 + */
17711 +void dwc_otg_pcd_reinit(dwc_otg_pcd_t *pcd)
17712 +{
17713 +       static const char * names[] =
17714 +               {
17715 +
17716 +                       "ep0",
17717 +                       "ep1in",
17718 +                       "ep2in",
17719 +                       "ep3in",
17720 +                       "ep4in",
17721 +                       "ep5in",
17722 +                       "ep6in",
17723 +                       "ep7in",
17724 +                       "ep8in",
17725 +                       "ep9in",
17726 +                       "ep10in",
17727 +                       "ep11in",
17728 +                       "ep12in",
17729 +                       "ep13in",
17730 +                       "ep14in",
17731 +                       "ep15in",
17732 +                       "ep1out",
17733 +                       "ep2out",
17734 +                       "ep3out",
17735 +                       "ep4out",
17736 +                       "ep5out",
17737 +                       "ep6out",
17738 +                       "ep7out",
17739 +                       "ep8out",
17740 +                       "ep9out",
17741 +                       "ep10out",
17742 +                       "ep11out",
17743 +                       "ep12out",
17744 +                       "ep13out",
17745 +                       "ep14out",
17746 +                       "ep15out"
17747 +
17748 +       };
17749 +
17750 +       int i;
17751 +       int in_ep_cntr, out_ep_cntr;
17752 +       uint32_t hwcfg1;
17753 +       uint32_t num_in_eps = (GET_CORE_IF(pcd))->dev_if->num_in_eps;
17754 +       uint32_t num_out_eps = (GET_CORE_IF(pcd))->dev_if->num_out_eps;
17755 +       dwc_otg_pcd_ep_t *ep;
17756 +
17757 +       DWC_DEBUGPL(DBG_PCDV, "%s(%p)\n", __func__, pcd);
17758 +
17759 +       INIT_LIST_HEAD (&pcd->gadget.ep_list);
17760 +       pcd->gadget.ep0 = &pcd->ep0.ep;
17761 +       pcd->gadget.speed = USB_SPEED_UNKNOWN;
17762 +
17763 +       INIT_LIST_HEAD (&pcd->gadget.ep0->ep_list);
17764 +
17765 +       /**
17766 +        * Initialize the EP0 structure.
17767 +        */
17768 +       ep = &pcd->ep0;
17769 +
17770 +       /* Init EP structure */
17771 +       ep->desc = 0;
17772 +       ep->pcd = pcd;
17773 +       ep->stopped = 1;
17774 +
17775 +       /* Init DWC ep structure */
17776 +       ep->dwc_ep.num = 0;
17777 +       ep->dwc_ep.active = 0;
17778 +       ep->dwc_ep.tx_fifo_num = 0;
17779 +       /* Control until ep is actvated */
17780 +       ep->dwc_ep.type = DWC_OTG_EP_TYPE_CONTROL;
17781 +       ep->dwc_ep.maxpacket = MAX_PACKET_SIZE;
17782 +       ep->dwc_ep.dma_addr = 0;
17783 +       ep->dwc_ep.start_xfer_buff = 0;
17784 +       ep->dwc_ep.xfer_buff = 0;
17785 +       ep->dwc_ep.xfer_len = 0;
17786 +       ep->dwc_ep.xfer_count = 0;
17787 +       ep->dwc_ep.sent_zlp = 0;
17788 +       ep->dwc_ep.total_len = 0;
17789 +       ep->queue_sof = 0;
17790 +       ep->dwc_ep.desc_addr = 0;
17791 +       ep->dwc_ep.dma_desc_addr = 0;
17792 +
17793 +
17794 +       /* Init the usb_ep structure. */
17795 +       ep->ep.name = names[0];
17796 +       ep->ep.ops = (struct usb_ep_ops*)&dwc_otg_pcd_ep_ops;
17797 +
17798 +       /**
17799 +        * @todo NGS: What should the max packet size be set to
17800 +        * here?  Before EP type is set?
17801 +        */
17802 +       ep->ep.maxpacket = MAX_PACKET_SIZE;
17803 +
17804 +       list_add_tail (&ep->ep.ep_list, &pcd->gadget.ep_list);
17805 +
17806 +       INIT_LIST_HEAD (&ep->queue);
17807 +       /**
17808 +        * Initialize the EP structures.
17809 +        */
17810 +       in_ep_cntr = 0;
17811 +       hwcfg1 = (GET_CORE_IF(pcd))->hwcfg1.d32 >> 3;
17812 +
17813 +       for (i = 1; in_ep_cntr < num_in_eps; i++)
17814 +       {
17815 +               if((hwcfg1 & 0x1) == 0) {
17816 +                       dwc_otg_pcd_ep_t *ep = &pcd->in_ep[in_ep_cntr];
17817 +                       in_ep_cntr ++;
17818 +
17819 +                       /* Init EP structure */
17820 +                       ep->desc = 0;
17821 +                       ep->pcd = pcd;
17822 +                       ep->stopped = 1;
17823 +
17824 +                       /* Init DWC ep structure */
17825 +                       ep->dwc_ep.is_in = 1;
17826 +                       ep->dwc_ep.num = i;
17827 +                       ep->dwc_ep.active = 0;
17828 +                       ep->dwc_ep.tx_fifo_num = 0;
17829 +
17830 +                       /* Control until ep is actvated */
17831 +                       ep->dwc_ep.type = DWC_OTG_EP_TYPE_CONTROL;
17832 +                       ep->dwc_ep.maxpacket = MAX_PACKET_SIZE;
17833 +                       ep->dwc_ep.dma_addr = 0;
17834 +                       ep->dwc_ep.start_xfer_buff = 0;
17835 +                       ep->dwc_ep.xfer_buff = 0;
17836 +                       ep->dwc_ep.xfer_len = 0;
17837 +                       ep->dwc_ep.xfer_count = 0;
17838 +                       ep->dwc_ep.sent_zlp = 0;
17839 +                       ep->dwc_ep.total_len = 0;
17840 +                       ep->queue_sof = 0;
17841 +                       ep->dwc_ep.desc_addr = 0;
17842 +                       ep->dwc_ep.dma_desc_addr = 0;
17843 +
17844 +                       /* Init the usb_ep structure. */
17845 +                       ep->ep.name = names[i];
17846 +                       ep->ep.ops = (struct usb_ep_ops*)&dwc_otg_pcd_ep_ops;
17847 +
17848 +                       /**
17849 +                        * @todo NGS: What should the max packet size be set to
17850 +                        * here?  Before EP type is set?
17851 +                        */
17852 +                       ep->ep.maxpacket = MAX_PACKET_SIZE;
17853 +
17854 +                       list_add_tail (&ep->ep.ep_list, &pcd->gadget.ep_list);
17855 +
17856 +                       INIT_LIST_HEAD (&ep->queue);
17857 +               }
17858 +               hwcfg1 >>= 2;
17859 +       }
17860 +
17861 +       out_ep_cntr = 0;
17862 +       hwcfg1 = (GET_CORE_IF(pcd))->hwcfg1.d32 >> 2;
17863 +
17864 +       for (i = 1; out_ep_cntr < num_out_eps; i++)
17865 +       {
17866 +               if((hwcfg1 & 0x1) == 0) {
17867 +                       dwc_otg_pcd_ep_t *ep = &pcd->out_ep[out_ep_cntr];
17868 +                       out_ep_cntr++;
17869 +
17870 +                       /* Init EP structure */
17871 +                       ep->desc = 0;
17872 +                       ep->pcd = pcd;
17873 +                       ep->stopped = 1;
17874 +
17875 +                       /* Init DWC ep structure */
17876 +                       ep->dwc_ep.is_in = 0;
17877 +                       ep->dwc_ep.num = i;
17878 +                       ep->dwc_ep.active = 0;
17879 +                       ep->dwc_ep.tx_fifo_num = 0;
17880 +                       /* Control until ep is actvated */
17881 +                       ep->dwc_ep.type = DWC_OTG_EP_TYPE_CONTROL;
17882 +                       ep->dwc_ep.maxpacket = MAX_PACKET_SIZE;
17883 +                       ep->dwc_ep.dma_addr = 0;
17884 +                       ep->dwc_ep.start_xfer_buff = 0;
17885 +                       ep->dwc_ep.xfer_buff = 0;
17886 +                       ep->dwc_ep.xfer_len = 0;
17887 +                       ep->dwc_ep.xfer_count = 0;
17888 +                       ep->dwc_ep.sent_zlp = 0;
17889 +                       ep->dwc_ep.total_len = 0;
17890 +                       ep->queue_sof = 0;
17891 +
17892 +                       /* Init the usb_ep structure. */
17893 +                       ep->ep.name = names[15 + i];
17894 +                       ep->ep.ops = (struct usb_ep_ops*)&dwc_otg_pcd_ep_ops;
17895 +                       /**
17896 +                        * @todo NGS: What should the max packet size be set to
17897 +                        * here?  Before EP type is set?
17898 +                        */
17899 +                       ep->ep.maxpacket = MAX_PACKET_SIZE;
17900 +
17901 +                       list_add_tail (&ep->ep.ep_list, &pcd->gadget.ep_list);
17902 +
17903 +                       INIT_LIST_HEAD (&ep->queue);
17904 +               }
17905 +               hwcfg1 >>= 2;
17906 +       }
17907 +
17908 +       /* remove ep0 from the list.  There is a ep0 pointer.*/
17909 +       list_del_init (&pcd->ep0.ep.ep_list);
17910 +
17911 +       pcd->ep0state = EP0_DISCONNECT;
17912 +       pcd->ep0.ep.maxpacket = MAX_EP0_SIZE;
17913 +       pcd->ep0.dwc_ep.maxpacket = MAX_EP0_SIZE;
17914 +       pcd->ep0.dwc_ep.type = DWC_OTG_EP_TYPE_CONTROL;
17915 +}
17916 +
17917 +/**
17918 + * This function releases the Gadget device.
17919 + * required by device_unregister().
17920 + *
17921 + * @todo Should this do something?     Should it free the PCD?
17922 + */
17923 +static void dwc_otg_pcd_gadget_release(struct device *dev)
17924 +{
17925 +       DWC_DEBUGPL(DBG_PCDV,"%s(%p)\n", __func__, dev);
17926 +}
17927 +
17928 +
17929 +
17930 +/**
17931 + * This function initialized the PCD portion of the driver.
17932 + *
17933 + */
17934 +
17935 +int dwc_otg_pcd_init(struct device *dev)
17936 +{
17937 +       static char pcd_name[] = "dwc_otg_pcd";
17938 +       dwc_otg_pcd_t *pcd;
17939 +       dwc_otg_core_if_t* core_if;
17940 +       dwc_otg_dev_if_t* dev_if;
17941 +       dwc_otg_device_t *otg_dev = dev_get_drvdata(dev);
17942 +       int retval = 0;
17943 +
17944 +
17945 +       DWC_DEBUGPL(DBG_PCDV,"%s(%p)\n",__func__, dev);
17946 +       /*
17947 +        * Allocate PCD structure
17948 +        */
17949 +       pcd = kmalloc(sizeof(dwc_otg_pcd_t), GFP_KERNEL);
17950 +
17951 +       if (pcd == 0) {
17952 +               return -ENOMEM;
17953 +       }
17954 +
17955 +       memset(pcd, 0, sizeof(dwc_otg_pcd_t));
17956 +       spin_lock_init(&pcd->lock);
17957 +
17958 +       otg_dev->pcd = pcd;
17959 +       s_pcd = pcd;
17960 +       pcd->gadget.name = pcd_name;
17961 +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,30)
17962 +       strcpy(pcd->gadget.dev.bus_id, "gadget");
17963 +#else
17964 +       dev_set_name(&pcd->gadget.dev, "%s", "gadget");
17965 +#endif
17966 +
17967 +       pcd->otg_dev = dev_get_drvdata(dev);
17968 +
17969 +       pcd->gadget.dev.parent = dev;
17970 +       pcd->gadget.dev.release = dwc_otg_pcd_gadget_release;
17971 +       pcd->gadget.ops = &dwc_otg_pcd_ops;
17972 +
17973 +       core_if = GET_CORE_IF(pcd);
17974 +       dev_if = core_if->dev_if;
17975 +
17976 +       if(core_if->hwcfg4.b.ded_fifo_en) {
17977 +               DWC_PRINT("Dedicated Tx FIFOs mode\n");
17978 +       }
17979 +       else {
17980 +               DWC_PRINT("Shared Tx FIFO mode\n");
17981 +       }
17982 +
17983 +       /* If the module is set to FS or if the PHY_TYPE is FS then the gadget
17984 +        * should not report as dual-speed capable.      replace the following line
17985 +        * with the block of code below it once the software is debugged for
17986 +        * this.  If is_dualspeed = 0 then the gadget driver should not report
17987 +        * a device qualifier descriptor when queried. */
17988 +       if ((GET_CORE_IF(pcd)->core_params->speed == DWC_SPEED_PARAM_FULL) ||
17989 +               ((GET_CORE_IF(pcd)->hwcfg2.b.hs_phy_type == 2) &&
17990 +                (GET_CORE_IF(pcd)->hwcfg2.b.fs_phy_type == 1) &&
17991 +                (GET_CORE_IF(pcd)->core_params->ulpi_fs_ls))) {
17992 +               pcd->gadget.is_dualspeed = 0;
17993 +       }
17994 +       else {
17995 +               pcd->gadget.is_dualspeed = 1;
17996 +       }
17997 +
17998 +       if ((otg_dev->core_if->hwcfg2.b.op_mode == DWC_HWCFG2_OP_MODE_NO_SRP_CAPABLE_DEVICE) ||
17999 +       (otg_dev->core_if->hwcfg2.b.op_mode == DWC_HWCFG2_OP_MODE_NO_SRP_CAPABLE_HOST) ||
18000 +       (otg_dev->core_if->hwcfg2.b.op_mode == DWC_HWCFG2_OP_MODE_SRP_CAPABLE_DEVICE) ||
18001 +       (otg_dev->core_if->hwcfg2.b.op_mode == DWC_HWCFG2_OP_MODE_SRP_CAPABLE_HOST)) {
18002 +               pcd->gadget.is_otg = 0;
18003 +       }
18004 +       else {
18005 +               pcd->gadget.is_otg = 1;
18006 +       }
18007 +
18008 +
18009 +       pcd->driver = 0;
18010 +       /* Register the gadget device */
18011 +       retval = device_register(&pcd->gadget.dev);
18012 +       if (retval != 0) {
18013 +               kfree (pcd);
18014 +               return retval;
18015 +       }
18016 +
18017 +
18018 +       /*
18019 +        * Initialized the Core for Device mode.
18020 +        */
18021 +       if (dwc_otg_is_device_mode(core_if)) {
18022 +               dwc_otg_core_dev_init(core_if);
18023 +       }
18024 +
18025 +       /*
18026 +        * Initialize EP structures
18027 +        */
18028 +       dwc_otg_pcd_reinit(pcd);
18029 +
18030 +       /*
18031 +        * Register the PCD Callbacks.
18032 +        */
18033 +       dwc_otg_cil_register_pcd_callbacks(otg_dev->core_if, &pcd_callbacks,
18034 +                                               pcd);
18035 +       /*
18036 +        * Setup interupt handler
18037 +        */
18038 +       DWC_DEBUGPL(DBG_ANY, "registering handler for irq%d\n", otg_dev->irq);
18039 +       retval = request_irq(otg_dev->irq, dwc_otg_pcd_irq,
18040 +                               IRQF_SHARED, pcd->gadget.name, pcd);
18041 +       if (retval != 0) {
18042 +               DWC_ERROR("request of irq%d failed\n", otg_dev->irq);
18043 +               device_unregister(&pcd->gadget.dev);
18044 +               kfree (pcd);
18045 +               return -EBUSY;
18046 +       }
18047 +
18048 +       /*
18049 +        * Initialize the DMA buffer for SETUP packets
18050 +        */
18051 +       if (GET_CORE_IF(pcd)->dma_enable) {
18052 +               pcd->setup_pkt = dma_alloc_coherent (NULL, sizeof (*pcd->setup_pkt) * 5, &pcd->setup_pkt_dma_handle, 0);
18053 +               if (pcd->setup_pkt == 0) {
18054 +                       free_irq(otg_dev->irq, pcd);
18055 +                       device_unregister(&pcd->gadget.dev);
18056 +                       kfree (pcd);
18057 +                       return -ENOMEM;
18058 +               }
18059 +
18060 +               pcd->status_buf = dma_alloc_coherent (NULL, sizeof (uint16_t), &pcd->status_buf_dma_handle, 0);
18061 +               if (pcd->status_buf == 0) {
18062 +                       dma_free_coherent(NULL, sizeof(*pcd->setup_pkt), pcd->setup_pkt, pcd->setup_pkt_dma_handle);
18063 +                       free_irq(otg_dev->irq, pcd);
18064 +                       device_unregister(&pcd->gadget.dev);
18065 +                       kfree (pcd);
18066 +                       return -ENOMEM;
18067 +               }
18068 +
18069 +               if (GET_CORE_IF(pcd)->dma_desc_enable) {
18070 +                       dev_if->setup_desc_addr[0] = dwc_otg_ep_alloc_desc_chain(&dev_if->dma_setup_desc_addr[0], 1);
18071 +                       dev_if->setup_desc_addr[1] = dwc_otg_ep_alloc_desc_chain(&dev_if->dma_setup_desc_addr[1], 1);
18072 +                       dev_if->in_desc_addr = dwc_otg_ep_alloc_desc_chain(&dev_if->dma_in_desc_addr, 1);
18073 +                       dev_if->out_desc_addr = dwc_otg_ep_alloc_desc_chain(&dev_if->dma_out_desc_addr, 1);
18074 +
18075 +                       if(dev_if->setup_desc_addr[0] == 0
18076 +                       || dev_if->setup_desc_addr[1] == 0
18077 +                       || dev_if->in_desc_addr == 0
18078 +                       || dev_if->out_desc_addr == 0 ) {
18079 +
18080 +                               if(dev_if->out_desc_addr)
18081 +                                       dwc_otg_ep_free_desc_chain(dev_if->out_desc_addr, dev_if->dma_out_desc_addr, 1);
18082 +                               if(dev_if->in_desc_addr)
18083 +                                       dwc_otg_ep_free_desc_chain(dev_if->in_desc_addr, dev_if->dma_in_desc_addr, 1);
18084 +                               if(dev_if->setup_desc_addr[1])
18085 +                                       dwc_otg_ep_free_desc_chain(dev_if->setup_desc_addr[1], dev_if->dma_setup_desc_addr[1], 1);
18086 +                               if(dev_if->setup_desc_addr[0])
18087 +                                       dwc_otg_ep_free_desc_chain(dev_if->setup_desc_addr[0], dev_if->dma_setup_desc_addr[0], 1);
18088 +
18089 +
18090 +                               dma_free_coherent(NULL, sizeof(*pcd->status_buf), pcd->status_buf, pcd->setup_pkt_dma_handle);
18091 +                               dma_free_coherent(NULL, sizeof(*pcd->setup_pkt), pcd->setup_pkt, pcd->setup_pkt_dma_handle);
18092 +
18093 +                               free_irq(otg_dev->irq, pcd);
18094 +                               device_unregister(&pcd->gadget.dev);
18095 +                               kfree (pcd);
18096 +
18097 +                               return -ENOMEM;
18098 +                       }
18099 +               }
18100 +       }
18101 +       else {
18102 +               pcd->setup_pkt = kmalloc (sizeof (*pcd->setup_pkt) * 5, GFP_KERNEL);
18103 +               if (pcd->setup_pkt == 0) {
18104 +                       free_irq(otg_dev->irq, pcd);
18105 +                       device_unregister(&pcd->gadget.dev);
18106 +                       kfree (pcd);
18107 +                       return -ENOMEM;
18108 +               }
18109 +
18110 +               pcd->status_buf = kmalloc (sizeof (uint16_t), GFP_KERNEL);
18111 +               if (pcd->status_buf == 0) {
18112 +                       kfree(pcd->setup_pkt);
18113 +                       free_irq(otg_dev->irq, pcd);
18114 +                       device_unregister(&pcd->gadget.dev);
18115 +                       kfree (pcd);
18116 +                       return -ENOMEM;
18117 +               }
18118 +       }
18119 +
18120 +
18121 +       /* Initialize tasklet */
18122 +       start_xfer_tasklet.data = (unsigned long)pcd;
18123 +       pcd->start_xfer_tasklet = &start_xfer_tasklet;
18124 +
18125 +       return 0;
18126 +}
18127 +
18128 +/**
18129 + * Cleanup the PCD.
18130 + */
18131 +void dwc_otg_pcd_remove(struct device *dev)
18132 +{
18133 +       dwc_otg_device_t *otg_dev = dev_get_drvdata(dev);
18134 +       dwc_otg_pcd_t *pcd = otg_dev->pcd;
18135 +       dwc_otg_dev_if_t* dev_if = GET_CORE_IF(pcd)->dev_if;
18136 +
18137 +       DWC_DEBUGPL(DBG_PCDV, "%s(%p)\n", __func__, dev);
18138 +
18139 +       /*
18140 +        * Free the IRQ
18141 +        */
18142 +       free_irq(otg_dev->irq, pcd);
18143 +
18144 +        /* start with the driver above us */
18145 +       if (pcd->driver) {
18146 +               /* should have been done already by driver model core */
18147 +               DWC_WARN("driver '%s' is still registered\n",
18148 +                                pcd->driver->driver.name);
18149 +               usb_gadget_unregister_driver(pcd->driver);
18150 +       }
18151 +       device_unregister(&pcd->gadget.dev);
18152 +
18153 +       if (GET_CORE_IF(pcd)->dma_enable) {
18154 +               dma_free_coherent (NULL, sizeof (*pcd->setup_pkt) * 5, pcd->setup_pkt, pcd->setup_pkt_dma_handle);
18155 +               dma_free_coherent (NULL, sizeof (uint16_t), pcd->status_buf, pcd->status_buf_dma_handle);
18156 +               if (GET_CORE_IF(pcd)->dma_desc_enable) {
18157 +                       dwc_otg_ep_free_desc_chain(dev_if->setup_desc_addr[0], dev_if->dma_setup_desc_addr[0], 1);
18158 +                       dwc_otg_ep_free_desc_chain(dev_if->setup_desc_addr[1], dev_if->dma_setup_desc_addr[1], 1);
18159 +                       dwc_otg_ep_free_desc_chain(dev_if->in_desc_addr, dev_if->dma_in_desc_addr, 1);
18160 +                       dwc_otg_ep_free_desc_chain(dev_if->out_desc_addr, dev_if->dma_out_desc_addr, 1);
18161 +               }
18162 +       }
18163 +       else {
18164 +               kfree (pcd->setup_pkt);
18165 +               kfree (pcd->status_buf);
18166 +       }
18167 +
18168 +       kfree(pcd);
18169 +       otg_dev->pcd = 0;
18170 +}
18171 +
18172 +/**
18173 + * This function registers a gadget driver with the PCD.
18174 + *
18175 + * When a driver is successfully registered, it will receive control
18176 + * requests including set_configuration(), which enables non-control
18177 + * requests.  then usb traffic follows until a disconnect is reported.
18178 + * then a host may connect again, or the driver might get unbound.
18179 + *
18180 + * @param driver The driver being registered
18181 + */
18182 +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,37)
18183 +int usb_gadget_probe_driver(struct usb_gadget_driver *driver, int (*bind)(struct usb_gadget *))
18184 +#else
18185 +int usb_gadget_register_driver(struct usb_gadget_driver *driver)
18186 +#endif
18187 +{
18188 +       int retval;
18189 +       int (*d_bind)(struct usb_gadget *);
18190 +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,37)
18191 +       d_bind = bind;
18192 +#else
18193 +       d_bind = driver->bind;
18194 +#endif
18195 +
18196 +       DWC_DEBUGPL(DBG_PCD, "registering gadget driver '%s'\n", driver->driver.name);
18197 +
18198 +       if (!driver || driver->speed == USB_SPEED_UNKNOWN ||
18199 +               !d_bind ||
18200 +               !driver->unbind ||
18201 +               !driver->disconnect ||
18202 +               !driver->setup) {
18203 +               DWC_DEBUGPL(DBG_PCDV,"EINVAL\n");
18204 +               return -EINVAL;
18205 +       }
18206 +       if (s_pcd == 0) {
18207 +               DWC_DEBUGPL(DBG_PCDV,"ENODEV\n");
18208 +               return -ENODEV;
18209 +       }
18210 +       if (s_pcd->driver != 0) {
18211 +               DWC_DEBUGPL(DBG_PCDV,"EBUSY (%p)\n", s_pcd->driver);
18212 +               return -EBUSY;
18213 +       }
18214 +
18215 +       /* hook up the driver */
18216 +       s_pcd->driver = driver;
18217 +       s_pcd->gadget.dev.driver = &driver->driver;
18218 +
18219 +       DWC_DEBUGPL(DBG_PCD, "bind to driver %s\n", driver->driver.name);
18220 +       retval = d_bind(&s_pcd->gadget);
18221 +       if (retval) {
18222 +               DWC_ERROR("bind to driver %s --> error %d\n",
18223 +                                       driver->driver.name, retval);
18224 +               s_pcd->driver = 0;
18225 +               s_pcd->gadget.dev.driver = 0;
18226 +               return retval;
18227 +       }
18228 +       DWC_DEBUGPL(DBG_ANY, "registered gadget driver '%s'\n",
18229 +                                       driver->driver.name);
18230 +       return 0;
18231 +}
18232 +
18233 +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,37)
18234 +EXPORT_SYMBOL(usb_gadget_probe_driver);
18235 +#else
18236 +EXPORT_SYMBOL(usb_gadget_register_driver);
18237 +#endif
18238 +
18239 +/**
18240 + * This function unregisters a gadget driver
18241 + *
18242 + * @param driver The driver being unregistered
18243 + */
18244 +int usb_gadget_unregister_driver(struct usb_gadget_driver *driver)
18245 +{
18246 +       //DWC_DEBUGPL(DBG_PCDV,"%s(%p)\n", __func__, _driver);
18247 +
18248 +       if (s_pcd == 0) {
18249 +               DWC_DEBUGPL(DBG_ANY, "%s Return(%d): s_pcd==0\n", __func__,
18250 +                               -ENODEV);
18251 +               return -ENODEV;
18252 +       }
18253 +       if (driver == 0 || driver != s_pcd->driver) {
18254 +               DWC_DEBUGPL(DBG_ANY, "%s Return(%d): driver?\n", __func__,
18255 +                               -EINVAL);
18256 +               return -EINVAL;
18257 +       }
18258 +
18259 +       driver->unbind(&s_pcd->gadget);
18260 +       s_pcd->driver = 0;
18261 +
18262 +       DWC_DEBUGPL(DBG_ANY, "unregistered driver '%s'\n",
18263 +                       driver->driver.name);
18264 +       return 0;
18265 +}
18266 +EXPORT_SYMBOL(usb_gadget_unregister_driver);
18267 +
18268 +#endif /* DWC_HOST_ONLY */
18269 --- /dev/null
18270 +++ b/drivers/usb/dwc_otg/dwc_otg_pcd.h
18271 @@ -0,0 +1,248 @@
18272 +/* ==========================================================================
18273 + * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_pcd.h $
18274 + * $Revision: 1.2 $
18275 + * $Date: 2008-11-21 05:39:15 $
18276 + * $Change: 1103515 $
18277 + *
18278 + * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
18279 + * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
18280 + * otherwise expressly agreed to in writing between Synopsys and you.
18281 + *
18282 + * The Software IS NOT an item of Licensed Software or Licensed Product under
18283 + * any End User Software License Agreement or Agreement for Licensed Product
18284 + * with Synopsys or any supplement thereto. You are permitted to use and
18285 + * redistribute this Software in source and binary forms, with or without
18286 + * modification, provided that redistributions of source code must retain this
18287 + * notice. You may not view, use, disclose, copy or distribute this file or
18288 + * any information contained herein except pursuant to this license grant from
18289 + * Synopsys. If you do not agree with this notice, including the disclaimer
18290 + * below, then you are not authorized to use the Software.
18291 + *
18292 + * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
18293 + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18294 + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18295 + * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
18296 + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
18297 + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
18298 + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
18299 + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
18300 + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
18301 + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
18302 + * DAMAGE.
18303 + * ========================================================================== */
18304 +#ifndef DWC_HOST_ONLY
18305 +#if !defined(__DWC_PCD_H__)
18306 +#define __DWC_PCD_H__
18307 +
18308 +#include <linux/types.h>
18309 +#include <linux/list.h>
18310 +#include <linux/errno.h>
18311 +#include <linux/device.h>
18312 +
18313 +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,21)
18314 +# include <linux/usb/ch9.h>
18315 +#else
18316 +# include <linux/usb_ch9.h>
18317 +#endif
18318 +
18319 +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,24)
18320 +#include <linux/usb/gadget.h>
18321 +#else
18322 +#include <linux/usb_gadget.h>
18323 +#endif
18324 +#include <linux/interrupt.h>
18325 +#include <linux/dma-mapping.h>
18326 +
18327 +struct dwc_otg_device;
18328 +
18329 +#include "dwc_otg_cil.h"
18330 +
18331 +/**
18332 + * @file
18333 + *
18334 + * This file contains the structures, constants, and interfaces for
18335 + * the Perpherial Contoller Driver (PCD).
18336 + *
18337 + * The Peripheral Controller Driver (PCD) for Linux will implement the
18338 + * Gadget API, so that the existing Gadget drivers can be used.         For
18339 + * the Mass Storage Function driver the File-backed USB Storage Gadget
18340 + * (FBS) driver will be used.  The FBS driver supports the
18341 + * Control-Bulk (CB), Control-Bulk-Interrupt (CBI), and Bulk-Only
18342 + * transports.
18343 + *
18344 + */
18345 +
18346 +/** Invalid DMA Address */
18347 +#define DMA_ADDR_INVALID       (~(dma_addr_t)0)
18348 +/** Maxpacket size for EP0 */
18349 +#define MAX_EP0_SIZE   64
18350 +/** Maxpacket size for any EP */
18351 +#define MAX_PACKET_SIZE 1024
18352 +
18353 +/** Max Transfer size for any EP */
18354 +#define MAX_TRANSFER_SIZE 65535
18355 +
18356 +/** Max DMA Descriptor count for any EP */
18357 +#define MAX_DMA_DESC_CNT 64
18358 +
18359 +/**
18360 + * Get the pointer to the core_if from the pcd pointer.
18361 + */
18362 +#define GET_CORE_IF( _pcd ) (_pcd->otg_dev->core_if)
18363 +
18364 +/**
18365 + * States of EP0.
18366 + */
18367 +typedef enum ep0_state
18368 +{
18369 +       EP0_DISCONNECT,         /* no host */
18370 +       EP0_IDLE,
18371 +       EP0_IN_DATA_PHASE,
18372 +       EP0_OUT_DATA_PHASE,
18373 +       EP0_IN_STATUS_PHASE,
18374 +       EP0_OUT_STATUS_PHASE,
18375 +       EP0_STALL,
18376 +} ep0state_e;
18377 +
18378 +/** Fordward declaration.*/
18379 +struct dwc_otg_pcd;
18380 +
18381 +/** DWC_otg iso request structure.
18382 + *
18383 + */
18384 +typedef struct usb_iso_request  dwc_otg_pcd_iso_request_t;
18385 +
18386 +/**      PCD EP structure.
18387 + * This structure describes an EP, there is an array of EPs in the PCD
18388 + * structure.
18389 + */
18390 +typedef struct dwc_otg_pcd_ep
18391 +{
18392 +       /** USB EP data */
18393 +       struct usb_ep           ep;
18394 +       /** USB EP Descriptor */
18395 +       const struct usb_endpoint_descriptor    *desc;
18396 +
18397 +       /** queue of dwc_otg_pcd_requests. */
18398 +       struct list_head        queue;
18399 +       unsigned stopped : 1;
18400 +       unsigned disabling : 1;
18401 +       unsigned dma : 1;
18402 +       unsigned queue_sof : 1;
18403 +
18404 +#ifdef DWC_EN_ISOC
18405 +       /** DWC_otg Isochronous Transfer */
18406 +       struct usb_iso_request* iso_req;
18407 +#endif //DWC_EN_ISOC
18408 +
18409 +       /** DWC_otg ep data. */
18410 +       dwc_ep_t dwc_ep;
18411 +
18412 +       /** Pointer to PCD */
18413 +       struct dwc_otg_pcd *pcd;
18414 +}dwc_otg_pcd_ep_t;
18415 +
18416 +
18417 +
18418 +/** DWC_otg PCD Structure.
18419 + * This structure encapsulates the data for the dwc_otg PCD.
18420 + */
18421 +typedef struct dwc_otg_pcd
18422 +{
18423 +       /** USB gadget */
18424 +       struct usb_gadget gadget;
18425 +       /** USB gadget driver pointer*/
18426 +       struct usb_gadget_driver *driver;
18427 +       /** The DWC otg device pointer. */
18428 +       struct dwc_otg_device *otg_dev;
18429 +
18430 +       /** State of EP0 */
18431 +       ep0state_e      ep0state;
18432 +       /** EP0 Request is pending */
18433 +       unsigned        ep0_pending : 1;
18434 +       /** Indicates when SET CONFIGURATION Request is in process */
18435 +       unsigned        request_config : 1;
18436 +       /** The state of the Remote Wakeup Enable. */
18437 +       unsigned        remote_wakeup_enable : 1;
18438 +       /** The state of the B-Device HNP Enable. */
18439 +       unsigned        b_hnp_enable : 1;
18440 +       /** The state of A-Device HNP Support. */
18441 +       unsigned        a_hnp_support : 1;
18442 +       /** The state of the A-Device Alt HNP support. */
18443 +       unsigned        a_alt_hnp_support : 1;
18444 +       /** Count of pending Requests */
18445 +       unsigned        request_pending;
18446 +
18447 +               /** SETUP packet for EP0
18448 +        * This structure is allocated as a DMA buffer on PCD initialization
18449 +        * with enough space for up to 3 setup packets.
18450 +        */
18451 +       union
18452 +       {
18453 +                       struct usb_ctrlrequest  req;
18454 +                       uint32_t        d32[2];
18455 +       } *setup_pkt;
18456 +
18457 +       dma_addr_t setup_pkt_dma_handle;
18458 +
18459 +       /** 2-byte dma buffer used to return status from GET_STATUS */
18460 +       uint16_t *status_buf;
18461 +       dma_addr_t status_buf_dma_handle;
18462 +
18463 +       /** EP0 */
18464 +       dwc_otg_pcd_ep_t ep0;
18465 +
18466 +       /** Array of IN EPs. */
18467 +       dwc_otg_pcd_ep_t in_ep[ MAX_EPS_CHANNELS - 1];
18468 +       /** Array of OUT EPs. */
18469 +       dwc_otg_pcd_ep_t out_ep[ MAX_EPS_CHANNELS - 1];
18470 +       /** number of valid EPs in the above array. */
18471 +//       unsigned      num_eps : 4;
18472 +       spinlock_t      lock;
18473 +       /** Timer for SRP.      If it expires before SRP is successful
18474 +        * clear the SRP. */
18475 +       struct timer_list srp_timer;
18476 +
18477 +       /** Tasklet to defer starting of TEST mode transmissions until
18478 +        *      Status Phase has been completed.
18479 +        */
18480 +       struct tasklet_struct test_mode_tasklet;
18481 +
18482 +       /** Tasklet to delay starting of xfer in DMA mode */
18483 +       struct tasklet_struct *start_xfer_tasklet;
18484 +
18485 +       /** The test mode to enter when the tasklet is executed. */
18486 +       unsigned test_mode;
18487 +
18488 +} dwc_otg_pcd_t;
18489 +
18490 +
18491 +/** DWC_otg request structure.
18492 + * This structure is a list of requests.
18493 + */
18494 +typedef struct
18495 +{
18496 +       struct usb_request      req; /**< USB Request. */
18497 +       struct list_head        queue;  /**< queue of these requests. */
18498 +} dwc_otg_pcd_request_t;
18499 +
18500 +
18501 +extern int dwc_otg_pcd_init(struct device *dev);
18502 +
18503 +//extern void dwc_otg_pcd_remove( struct dwc_otg_device *_otg_dev );
18504 +extern void dwc_otg_pcd_remove( struct device *dev);
18505 +extern int32_t dwc_otg_pcd_handle_intr( dwc_otg_pcd_t *pcd );
18506 +extern void dwc_otg_pcd_start_srp_timer(dwc_otg_pcd_t *pcd );
18507 +
18508 +extern void dwc_otg_pcd_initiate_srp(dwc_otg_pcd_t *pcd);
18509 +extern void dwc_otg_pcd_remote_wakeup(dwc_otg_pcd_t *pcd, int set);
18510 +
18511 +extern void dwc_otg_iso_buffer_done(dwc_otg_pcd_ep_t *ep, dwc_otg_pcd_iso_request_t *req);
18512 +extern void dwc_otg_request_done(dwc_otg_pcd_ep_t *_ep, dwc_otg_pcd_request_t *req,
18513 +                               int status);
18514 +extern void dwc_otg_request_nuke(dwc_otg_pcd_ep_t *_ep);
18515 +extern void dwc_otg_pcd_update_otg(dwc_otg_pcd_t *_pcd,
18516 +                                       const unsigned reset);
18517 +
18518 +#endif
18519 +#endif /* DWC_HOST_ONLY */
18520 --- /dev/null
18521 +++ b/drivers/usb/dwc_otg/dwc_otg_pcd_intr.c
18522 @@ -0,0 +1,3654 @@
18523 +/* ==========================================================================
18524 + * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_pcd_intr.c $
18525 + * $Revision: 1.2 $
18526 + * $Date: 2008-11-21 05:39:15 $
18527 + * $Change: 1115682 $
18528 + *
18529 + * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
18530 + * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
18531 + * otherwise expressly agreed to in writing between Synopsys and you.
18532 + *
18533 + * The Software IS NOT an item of Licensed Software or Licensed Product under
18534 + * any End User Software License Agreement or Agreement for Licensed Product
18535 + * with Synopsys or any supplement thereto. You are permitted to use and
18536 + * redistribute this Software in source and binary forms, with or without
18537 + * modification, provided that redistributions of source code must retain this
18538 + * notice. You may not view, use, disclose, copy or distribute this file or
18539 + * any information contained herein except pursuant to this license grant from
18540 + * Synopsys. If you do not agree with this notice, including the disclaimer
18541 + * below, then you are not authorized to use the Software.
18542 + *
18543 + * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
18544 + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18545 + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18546 + * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
18547 + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
18548 + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
18549 + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
18550 + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
18551 + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
18552 + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
18553 + * DAMAGE.
18554 + * ========================================================================== */
18555 +#ifndef DWC_HOST_ONLY
18556 +#include <linux/interrupt.h>
18557 +#include <linux/dma-mapping.h>
18558 +#include <linux/version.h>
18559 +
18560 +#include "dwc_otg_driver.h"
18561 +#include "dwc_otg_pcd.h"
18562 +
18563 +
18564 +#define DEBUG_EP0
18565 +
18566 +/* request functions defined in "dwc_otg_pcd.c" */
18567 +
18568 +/** @file
18569 + * This file contains the implementation of the PCD Interrupt handlers.
18570 + *
18571 + * The PCD handles the device interrupts.  Many conditions can cause a
18572 + * device interrupt. When an interrupt occurs, the device interrupt
18573 + * service routine determines the cause of the interrupt and
18574 + * dispatches handling to the appropriate function. These interrupt
18575 + * handling functions are described below.
18576 + * All interrupt registers are processed from LSB to MSB.
18577 + */
18578 +
18579 +
18580 +/**
18581 + * This function prints the ep0 state for debug purposes.
18582 + */
18583 +static inline void print_ep0_state(dwc_otg_pcd_t *pcd)
18584 +{
18585 +#ifdef DEBUG
18586 +       char str[40];
18587 +
18588 +       switch (pcd->ep0state) {
18589 +       case EP0_DISCONNECT:
18590 +               strcpy(str, "EP0_DISCONNECT");
18591 +               break;
18592 +       case EP0_IDLE:
18593 +               strcpy(str, "EP0_IDLE");
18594 +               break;
18595 +       case EP0_IN_DATA_PHASE:
18596 +               strcpy(str, "EP0_IN_DATA_PHASE");
18597 +               break;
18598 +       case EP0_OUT_DATA_PHASE:
18599 +               strcpy(str, "EP0_OUT_DATA_PHASE");
18600 +               break;
18601 +       case EP0_IN_STATUS_PHASE:
18602 +               strcpy(str,"EP0_IN_STATUS_PHASE");
18603 +               break;
18604 +       case EP0_OUT_STATUS_PHASE:
18605 +               strcpy(str,"EP0_OUT_STATUS_PHASE");
18606 +               break;
18607 +       case EP0_STALL:
18608 +               strcpy(str,"EP0_STALL");
18609 +               break;
18610 +       default:
18611 +               strcpy(str,"EP0_INVALID");
18612 +       }
18613 +
18614 +       DWC_DEBUGPL(DBG_ANY, "%s(%d)\n", str, pcd->ep0state);
18615 +#endif
18616 +}
18617 +
18618 +/**
18619 + * This function returns pointer to in ep struct with number ep_num
18620 + */
18621 +static inline dwc_otg_pcd_ep_t* get_in_ep(dwc_otg_pcd_t *pcd, uint32_t ep_num)
18622 +{
18623 +       int i;
18624 +       int num_in_eps = GET_CORE_IF(pcd)->dev_if->num_in_eps;
18625 +       if(ep_num == 0) {
18626 +               return &pcd->ep0;
18627 +       }
18628 +       else {
18629 +               for(i = 0; i < num_in_eps; ++i)
18630 +               {
18631 +                       if(pcd->in_ep[i].dwc_ep.num == ep_num)
18632 +                               return &pcd->in_ep[i];
18633 +               }
18634 +               return 0;
18635 +       }
18636 +}
18637 +/**
18638 + * This function returns pointer to out ep struct with number ep_num
18639 + */
18640 +static inline dwc_otg_pcd_ep_t* get_out_ep(dwc_otg_pcd_t *pcd, uint32_t ep_num)
18641 +{
18642 +       int i;
18643 +       int num_out_eps = GET_CORE_IF(pcd)->dev_if->num_out_eps;
18644 +       if(ep_num == 0) {
18645 +               return &pcd->ep0;
18646 +       }
18647 +       else {
18648 +               for(i = 0; i < num_out_eps; ++i)
18649 +               {
18650 +                       if(pcd->out_ep[i].dwc_ep.num == ep_num)
18651 +                               return &pcd->out_ep[i];
18652 +               }
18653 +               return 0;
18654 +       }
18655 +}
18656 +/**
18657 + * This functions gets a pointer to an EP from the wIndex address
18658 + * value of the control request.
18659 + */
18660 +static dwc_otg_pcd_ep_t *get_ep_by_addr (dwc_otg_pcd_t *pcd, u16 wIndex)
18661 +{
18662 +       dwc_otg_pcd_ep_t        *ep;
18663 +
18664 +       if ((wIndex & USB_ENDPOINT_NUMBER_MASK) == 0)
18665 +               return &pcd->ep0;
18666 +       list_for_each_entry(ep, &pcd->gadget.ep_list, ep.ep_list)
18667 +       {
18668 +               u8      bEndpointAddress;
18669 +
18670 +               if (!ep->desc)
18671 +                       continue;
18672 +
18673 +               bEndpointAddress = ep->desc->bEndpointAddress;
18674 +               if((wIndex & (USB_DIR_IN | USB_ENDPOINT_NUMBER_MASK))
18675 +                       == (bEndpointAddress & (USB_DIR_IN | USB_ENDPOINT_NUMBER_MASK)))
18676 +                       return ep;
18677 +       }
18678 +       return NULL;
18679 +}
18680 +
18681 +/**
18682 + * This function checks the EP request queue, if the queue is not
18683 + * empty the next request is started.
18684 + */
18685 +void start_next_request(dwc_otg_pcd_ep_t *ep)
18686 +{
18687 +       dwc_otg_pcd_request_t *req = 0;
18688 +       uint32_t max_transfer = GET_CORE_IF(ep->pcd)->core_params->max_transfer_size;
18689 +
18690 +       if (!list_empty(&ep->queue)) {
18691 +               req = list_entry(ep->queue.next,
18692 +                          dwc_otg_pcd_request_t, queue);
18693 +
18694 +               /* Setup and start the Transfer */
18695 +               ep->dwc_ep.dma_addr = req->req.dma;
18696 +               ep->dwc_ep.start_xfer_buff = req->req.buf;
18697 +               ep->dwc_ep.xfer_buff = req->req.buf;
18698 +               ep->dwc_ep.sent_zlp = 0;
18699 +               ep->dwc_ep.total_len = req->req.length;
18700 +               ep->dwc_ep.xfer_len = 0;
18701 +               ep->dwc_ep.xfer_count = 0;
18702 +
18703 +               if(max_transfer > MAX_TRANSFER_SIZE) {
18704 +                       ep->dwc_ep.maxxfer = max_transfer - (max_transfer % ep->dwc_ep.maxpacket);
18705 +               } else {
18706 +                       ep->dwc_ep.maxxfer = max_transfer;
18707 +               }
18708 +
18709 +               if(req->req.zero) {
18710 +                       if((ep->dwc_ep.total_len % ep->dwc_ep.maxpacket == 0)
18711 +                                       && (ep->dwc_ep.total_len != 0)) {
18712 +                               ep->dwc_ep.sent_zlp = 1;
18713 +                       }
18714 +
18715 +               }
18716 +
18717 +               dwc_otg_ep_start_transfer(GET_CORE_IF(ep->pcd), &ep->dwc_ep);
18718 +       }
18719 +}
18720 +
18721 +/**
18722 + * This function handles the SOF Interrupts. At this time the SOF
18723 + * Interrupt is disabled.
18724 + */
18725 +int32_t dwc_otg_pcd_handle_sof_intr(dwc_otg_pcd_t *pcd)
18726 +{
18727 +       dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
18728 +
18729 +       gintsts_data_t gintsts;
18730 +
18731 +       DWC_DEBUGPL(DBG_PCD, "SOF\n");
18732 +
18733 +       /* Clear interrupt */
18734 +       gintsts.d32 = 0;
18735 +       gintsts.b.sofintr = 1;
18736 +       dwc_write_reg32 (&core_if->core_global_regs->gintsts, gintsts.d32);
18737 +
18738 +       return 1;
18739 +}
18740 +
18741 +
18742 +/**
18743 + * This function handles the Rx Status Queue Level Interrupt, which
18744 + * indicates that there is a least one packet in the Rx FIFO.  The
18745 + * packets are moved from the FIFO to memory, where they will be
18746 + * processed when the Endpoint Interrupt Register indicates Transfer
18747 + * Complete or SETUP Phase Done.
18748 + *
18749 + * Repeat the following until the Rx Status Queue is empty:
18750 + *      -# Read the Receive Status Pop Register (GRXSTSP) to get Packet
18751 + *             info
18752 + *      -# If Receive FIFO is empty then skip to step Clear the interrupt
18753 + *             and exit
18754 + *      -# If SETUP Packet call dwc_otg_read_setup_packet to copy the
18755 + *             SETUP data to the buffer
18756 + *      -# If OUT Data Packet call dwc_otg_read_packet to copy the data
18757 + *             to the destination buffer
18758 + */
18759 +int32_t dwc_otg_pcd_handle_rx_status_q_level_intr(dwc_otg_pcd_t *pcd)
18760 +{
18761 +       dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
18762 +       dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs;
18763 +       gintmsk_data_t gintmask = {.d32=0};
18764 +       device_grxsts_data_t status;
18765 +       dwc_otg_pcd_ep_t *ep;
18766 +       gintsts_data_t gintsts;
18767 +#ifdef DEBUG
18768 +       static char *dpid_str[] ={ "D0", "D2", "D1", "MDATA" };
18769 +#endif
18770 +
18771 +       //DWC_DEBUGPL(DBG_PCDV, "%s(%p)\n", __func__, _pcd);
18772 +       /* Disable the Rx Status Queue Level interrupt */
18773 +       gintmask.b.rxstsqlvl= 1;
18774 +       dwc_modify_reg32(&global_regs->gintmsk, gintmask.d32, 0);
18775 +
18776 +       /* Get the Status from the top of the FIFO */
18777 +       status.d32 = dwc_read_reg32(&global_regs->grxstsp);
18778 +
18779 +       DWC_DEBUGPL(DBG_PCD, "EP:%d BCnt:%d DPID:%s "
18780 +                                       "pktsts:%x Frame:%d(0x%0x)\n",
18781 +                                       status.b.epnum, status.b.bcnt,
18782 +                                       dpid_str[status.b.dpid],
18783 +                                       status.b.pktsts, status.b.fn, status.b.fn);
18784 +       /* Get pointer to EP structure */
18785 +       ep = get_out_ep(pcd, status.b.epnum);
18786 +
18787 +       switch (status.b.pktsts) {
18788 +       case DWC_DSTS_GOUT_NAK:
18789 +               DWC_DEBUGPL(DBG_PCDV, "Global OUT NAK\n");
18790 +               break;
18791 +       case DWC_STS_DATA_UPDT:
18792 +               DWC_DEBUGPL(DBG_PCDV, "OUT Data Packet\n");
18793 +               if (status.b.bcnt && ep->dwc_ep.xfer_buff) {
18794 +                       /** @todo NGS Check for buffer overflow? */
18795 +                       dwc_otg_read_packet(core_if,
18796 +                                                ep->dwc_ep.xfer_buff,
18797 +                                                status.b.bcnt);
18798 +                       ep->dwc_ep.xfer_count += status.b.bcnt;
18799 +                       ep->dwc_ep.xfer_buff += status.b.bcnt;
18800 +               }
18801 +               break;
18802 +       case DWC_STS_XFER_COMP:
18803 +               DWC_DEBUGPL(DBG_PCDV, "OUT Complete\n");
18804 +               break;
18805 +       case DWC_DSTS_SETUP_COMP:
18806 +#ifdef DEBUG_EP0
18807 +               DWC_DEBUGPL(DBG_PCDV, "Setup Complete\n");
18808 +#endif
18809 +               break;
18810 +case DWC_DSTS_SETUP_UPDT:
18811 +               dwc_otg_read_setup_packet(core_if, pcd->setup_pkt->d32);
18812 +#ifdef DEBUG_EP0
18813 +               DWC_DEBUGPL(DBG_PCD,
18814 +                               "SETUP PKT: %02x.%02x v%04x i%04x l%04x\n",
18815 +                               pcd->setup_pkt->req.bRequestType,
18816 +                               pcd->setup_pkt->req.bRequest,
18817 +                               pcd->setup_pkt->req.wValue,
18818 +                               pcd->setup_pkt->req.wIndex,
18819 +                               pcd->setup_pkt->req.wLength);
18820 +#endif
18821 +               ep->dwc_ep.xfer_count += status.b.bcnt;
18822 +               break;
18823 +       default:
18824 +               DWC_DEBUGPL(DBG_PCDV, "Invalid Packet Status (0x%0x)\n",
18825 +                               status.b.pktsts);
18826 +               break;
18827 +       }
18828 +
18829 +       /* Enable the Rx Status Queue Level interrupt */
18830 +       dwc_modify_reg32(&global_regs->gintmsk, 0, gintmask.d32);
18831 +       /* Clear interrupt */
18832 +       gintsts.d32 = 0;
18833 +       gintsts.b.rxstsqlvl = 1;
18834 +       dwc_write_reg32 (&global_regs->gintsts, gintsts.d32);
18835 +
18836 +       //DWC_DEBUGPL(DBG_PCDV, "EXIT: %s\n", __func__);
18837 +       return 1;
18838 +}
18839 +/**
18840 + * This function examines the Device IN Token Learning Queue to
18841 + * determine the EP number of the last IN token received.  This
18842 + * implementation is for the Mass Storage device where there are only
18843 + * 2 IN EPs (Control-IN and BULK-IN).
18844 + *
18845 + * The EP numbers for the first six IN Tokens are in DTKNQR1 and there
18846 + * are 8 EP Numbers in each of the other possible DTKNQ Registers.
18847 + *
18848 + * @param core_if Programming view of DWC_otg controller.
18849 + *
18850 + */
18851 +static inline int get_ep_of_last_in_token(dwc_otg_core_if_t *core_if)
18852 +{
18853 +       dwc_otg_device_global_regs_t *dev_global_regs =
18854 +                       core_if->dev_if->dev_global_regs;
18855 +       const uint32_t TOKEN_Q_DEPTH = core_if->hwcfg2.b.dev_token_q_depth;
18856 +       /* Number of Token Queue Registers */
18857 +       const int DTKNQ_REG_CNT = (TOKEN_Q_DEPTH + 7) / 8;
18858 +       dtknq1_data_t dtknqr1;
18859 +       uint32_t in_tkn_epnums[4];
18860 +       int ndx = 0;
18861 +       int i = 0;
18862 +       volatile uint32_t *addr = &dev_global_regs->dtknqr1;
18863 +       int epnum = 0;
18864 +
18865 +       //DWC_DEBUGPL(DBG_PCD,"dev_token_q_depth=%d\n",TOKEN_Q_DEPTH);
18866 +
18867 +
18868 +       /* Read the DTKNQ Registers */
18869 +       for (i = 0; i < DTKNQ_REG_CNT; i++)
18870 +       {
18871 +               in_tkn_epnums[ i ] = dwc_read_reg32(addr);
18872 +               DWC_DEBUGPL(DBG_PCDV, "DTKNQR%d=0x%08x\n", i+1,
18873 +                               in_tkn_epnums[i]);
18874 +               if (addr == &dev_global_regs->dvbusdis) {
18875 +                       addr = &dev_global_regs->dtknqr3_dthrctl;
18876 +               }
18877 +               else {
18878 +                       ++addr;
18879 +               }
18880 +
18881 +       }
18882 +
18883 +       /* Copy the DTKNQR1 data to the bit field. */
18884 +       dtknqr1.d32 = in_tkn_epnums[0];
18885 +       /* Get the EP numbers */
18886 +       in_tkn_epnums[0] = dtknqr1.b.epnums0_5;
18887 +       ndx = dtknqr1.b.intknwptr - 1;
18888 +
18889 +       //DWC_DEBUGPL(DBG_PCDV,"ndx=%d\n",ndx);
18890 +       if (ndx == -1) {
18891 +               /** @todo Find a simpler way to calculate the max
18892 +                * queue position.*/
18893 +               int cnt = TOKEN_Q_DEPTH;
18894 +               if (TOKEN_Q_DEPTH <= 6) {
18895 +                       cnt = TOKEN_Q_DEPTH - 1;
18896 +               }
18897 +               else if (TOKEN_Q_DEPTH <= 14) {
18898 +                       cnt = TOKEN_Q_DEPTH - 7;
18899 +               }
18900 +               else if (TOKEN_Q_DEPTH <= 22) {
18901 +                       cnt = TOKEN_Q_DEPTH - 15;
18902 +               }
18903 +               else {
18904 +                       cnt = TOKEN_Q_DEPTH - 23;
18905 +               }
18906 +               epnum = (in_tkn_epnums[ DTKNQ_REG_CNT - 1 ] >> (cnt * 4)) & 0xF;
18907 +       }
18908 +       else {
18909 +               if (ndx <= 5) {
18910 +                       epnum = (in_tkn_epnums[0] >> (ndx * 4)) & 0xF;
18911 +               }
18912 +               else if (ndx <= 13) {
18913 +                       ndx -= 6;
18914 +                       epnum = (in_tkn_epnums[1] >> (ndx * 4)) & 0xF;
18915 +               }
18916 +               else if (ndx <= 21) {
18917 +                       ndx -= 14;
18918 +                       epnum = (in_tkn_epnums[2] >> (ndx * 4)) & 0xF;
18919 +               }
18920 +               else if (ndx <= 29) {
18921 +                       ndx -= 22;
18922 +                       epnum = (in_tkn_epnums[3] >> (ndx * 4)) & 0xF;
18923 +               }
18924 +       }
18925 +       //DWC_DEBUGPL(DBG_PCD,"epnum=%d\n",epnum);
18926 +       return epnum;
18927 +}
18928 +
18929 +/**
18930 + * This interrupt occurs when the non-periodic Tx FIFO is half-empty.
18931 + * The active request is checked for the next packet to be loaded into
18932 + * the non-periodic Tx FIFO.
18933 + */
18934 +int32_t dwc_otg_pcd_handle_np_tx_fifo_empty_intr(dwc_otg_pcd_t *pcd)
18935 +{
18936 +       dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
18937 +       dwc_otg_core_global_regs_t *global_regs =
18938 +                       core_if->core_global_regs;
18939 +       dwc_otg_dev_in_ep_regs_t *ep_regs;
18940 +       gnptxsts_data_t txstatus = {.d32 = 0};
18941 +       gintsts_data_t gintsts;
18942 +
18943 +       int epnum = 0;
18944 +       dwc_otg_pcd_ep_t *ep = 0;
18945 +       uint32_t len = 0;
18946 +       int dwords;
18947 +
18948 +       /* Get the epnum from the IN Token Learning Queue. */
18949 +       epnum = get_ep_of_last_in_token(core_if);
18950 +       ep = get_in_ep(pcd, epnum);
18951 +
18952 +       DWC_DEBUGPL(DBG_PCD, "NP TxFifo Empty: %s(%d) \n", ep->ep.name, epnum);
18953 +       ep_regs = core_if->dev_if->in_ep_regs[epnum];
18954 +
18955 +       len = ep->dwc_ep.xfer_len - ep->dwc_ep.xfer_count;
18956 +       if (len > ep->dwc_ep.maxpacket) {
18957 +               len = ep->dwc_ep.maxpacket;
18958 +       }
18959 +       dwords = (len + 3)/4;
18960 +
18961 +
18962 +       /* While there is space in the queue and space in the FIFO and
18963 +       * More data to tranfer, Write packets to the Tx FIFO */
18964 +       txstatus.d32 = dwc_read_reg32(&global_regs->gnptxsts);
18965 +       DWC_DEBUGPL(DBG_PCDV, "b4 GNPTXSTS=0x%08x\n",txstatus.d32);
18966 +
18967 +       while  (txstatus.b.nptxqspcavail > 0 &&
18968 +               txstatus.b.nptxfspcavail > dwords &&
18969 +               ep->dwc_ep.xfer_count < ep->dwc_ep.xfer_len) {
18970 +               /* Write the FIFO */
18971 +               dwc_otg_ep_write_packet(core_if, &ep->dwc_ep, 0);
18972 +               len = ep->dwc_ep.xfer_len - ep->dwc_ep.xfer_count;
18973 +
18974 +               if (len > ep->dwc_ep.maxpacket) {
18975 +                       len = ep->dwc_ep.maxpacket;
18976 +               }
18977 +
18978 +               dwords = (len + 3)/4;
18979 +               txstatus.d32 = dwc_read_reg32(&global_regs->gnptxsts);
18980 +               DWC_DEBUGPL(DBG_PCDV,"GNPTXSTS=0x%08x\n",txstatus.d32);
18981 +       }
18982 +
18983 +       DWC_DEBUGPL(DBG_PCDV, "GNPTXSTS=0x%08x\n",
18984 +                       dwc_read_reg32(&global_regs->gnptxsts));
18985 +
18986 +       /* Clear interrupt */
18987 +       gintsts.d32 = 0;
18988 +       gintsts.b.nptxfempty = 1;
18989 +       dwc_write_reg32 (&global_regs->gintsts, gintsts.d32);
18990 +
18991 +       return 1;
18992 +}
18993 +
18994 +/**
18995 + * This function is called when dedicated Tx FIFO Empty interrupt occurs.
18996 + * The active request is checked for the next packet to be loaded into
18997 + * apropriate Tx FIFO.
18998 + */
18999 +static int32_t write_empty_tx_fifo(dwc_otg_pcd_t *pcd, uint32_t epnum)
19000 +{
19001 +       dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
19002 +       dwc_otg_dev_if_t* dev_if = core_if->dev_if;
19003 +       dwc_otg_dev_in_ep_regs_t *ep_regs;
19004 +       dtxfsts_data_t txstatus = {.d32 = 0};
19005 +       dwc_otg_pcd_ep_t *ep = 0;
19006 +       uint32_t len = 0;
19007 +       int dwords;
19008 +
19009 +       ep = get_in_ep(pcd, epnum);
19010 +
19011 +       DWC_DEBUGPL(DBG_PCD, "Dedicated TxFifo Empty: %s(%d) \n", ep->ep.name, epnum);
19012 +
19013 +       ep_regs = core_if->dev_if->in_ep_regs[epnum];
19014 +
19015 +       len = ep->dwc_ep.xfer_len - ep->dwc_ep.xfer_count;
19016 +
19017 +       if (len > ep->dwc_ep.maxpacket) {
19018 +               len = ep->dwc_ep.maxpacket;
19019 +       }
19020 +
19021 +       dwords = (len + 3)/4;
19022 +
19023 +       /* While there is space in the queue and space in the FIFO and
19024 +        * More data to tranfer, Write packets to the Tx FIFO */
19025 +       txstatus.d32 = dwc_read_reg32(&dev_if->in_ep_regs[epnum]->dtxfsts);
19026 +       DWC_DEBUGPL(DBG_PCDV, "b4 dtxfsts[%d]=0x%08x\n",epnum,txstatus.d32);
19027 +
19028 +       while  (txstatus.b.txfspcavail > dwords &&
19029 +               ep->dwc_ep.xfer_count < ep->dwc_ep.xfer_len &&
19030 +               ep->dwc_ep.xfer_len != 0) {
19031 +               /* Write the FIFO */
19032 +               dwc_otg_ep_write_packet(core_if, &ep->dwc_ep, 0);
19033 +
19034 +               len = ep->dwc_ep.xfer_len - ep->dwc_ep.xfer_count;
19035 +               if (len > ep->dwc_ep.maxpacket) {
19036 +                       len = ep->dwc_ep.maxpacket;
19037 +               }
19038 +
19039 +               dwords = (len + 3)/4;
19040 +               txstatus.d32 = dwc_read_reg32(&dev_if->in_ep_regs[epnum]->dtxfsts);
19041 +               DWC_DEBUGPL(DBG_PCDV,"dtxfsts[%d]=0x%08x\n", epnum, txstatus.d32);
19042 +       }
19043 +
19044 +       DWC_DEBUGPL(DBG_PCDV, "b4 dtxfsts[%d]=0x%08x\n",epnum,dwc_read_reg32(&dev_if->in_ep_regs[epnum]->dtxfsts));
19045 +
19046 +       return 1;
19047 +}
19048 +
19049 +
19050 +/**
19051 + * This function is called when the Device is disconnected. It stops
19052 + * any active requests and informs the Gadget driver of the
19053 + * disconnect.
19054 + */
19055 +void dwc_otg_pcd_stop(dwc_otg_pcd_t *pcd)
19056 +{
19057 +       int i, num_in_eps, num_out_eps;
19058 +       dwc_otg_pcd_ep_t *ep;
19059 +
19060 +       gintmsk_data_t intr_mask = {.d32 = 0};
19061 +
19062 +       num_in_eps = GET_CORE_IF(pcd)->dev_if->num_in_eps;
19063 +       num_out_eps = GET_CORE_IF(pcd)->dev_if->num_out_eps;
19064 +
19065 +       DWC_DEBUGPL(DBG_PCDV, "%s() \n", __func__);
19066 +       /* don't disconnect drivers more than once */
19067 +       if (pcd->ep0state == EP0_DISCONNECT) {
19068 +               DWC_DEBUGPL(DBG_ANY, "%s() Already Disconnected\n", __func__);
19069 +               return;
19070 +       }
19071 +       pcd->ep0state = EP0_DISCONNECT;
19072 +
19073 +       /* Reset the OTG state. */
19074 +       dwc_otg_pcd_update_otg(pcd, 1);
19075 +
19076 +       /* Disable the NP Tx Fifo Empty Interrupt. */
19077 +       intr_mask.b.nptxfempty = 1;
19078 +       dwc_modify_reg32(&GET_CORE_IF(pcd)->core_global_regs->gintmsk,
19079 +                                        intr_mask.d32, 0);
19080 +
19081 +       /* Flush the FIFOs */
19082 +       /**@todo NGS Flush Periodic FIFOs */
19083 +       dwc_otg_flush_tx_fifo(GET_CORE_IF(pcd), 0x10);
19084 +       dwc_otg_flush_rx_fifo(GET_CORE_IF(pcd));
19085 +
19086 +       /* prevent new request submissions, kill any outstanding requests  */
19087 +       ep = &pcd->ep0;
19088 +       dwc_otg_request_nuke(ep);
19089 +       /* prevent new request submissions, kill any outstanding requests  */
19090 +       for (i = 0; i < num_in_eps; i++)
19091 +       {
19092 +               dwc_otg_pcd_ep_t *ep = &pcd->in_ep[i];
19093 +               dwc_otg_request_nuke(ep);
19094 +       }
19095 +       /* prevent new request submissions, kill any outstanding requests  */
19096 +       for (i = 0; i < num_out_eps; i++)
19097 +       {
19098 +               dwc_otg_pcd_ep_t *ep = &pcd->out_ep[i];
19099 +               dwc_otg_request_nuke(ep);
19100 +       }
19101 +
19102 +       /* report disconnect; the driver is already quiesced */
19103 +       if (pcd->driver && pcd->driver->disconnect) {
19104 +               SPIN_UNLOCK(&pcd->lock);
19105 +               pcd->driver->disconnect(&pcd->gadget);
19106 +               SPIN_LOCK(&pcd->lock);
19107 +       }
19108 +}
19109 +
19110 +/**
19111 + * This interrupt indicates that ...
19112 + */
19113 +int32_t dwc_otg_pcd_handle_i2c_intr(dwc_otg_pcd_t *pcd)
19114 +{
19115 +       gintmsk_data_t intr_mask = { .d32 = 0};
19116 +       gintsts_data_t gintsts;
19117 +
19118 +       DWC_PRINT("INTERRUPT Handler not implemented for %s\n", "i2cintr");
19119 +       intr_mask.b.i2cintr = 1;
19120 +       dwc_modify_reg32(&GET_CORE_IF(pcd)->core_global_regs->gintmsk,
19121 +                               intr_mask.d32, 0);
19122 +
19123 +       /* Clear interrupt */
19124 +       gintsts.d32 = 0;
19125 +       gintsts.b.i2cintr = 1;
19126 +       dwc_write_reg32 (&GET_CORE_IF(pcd)->core_global_regs->gintsts,
19127 +                                                gintsts.d32);
19128 +       return 1;
19129 +}
19130 +
19131 +
19132 +/**
19133 + * This interrupt indicates that ...
19134 + */
19135 +int32_t dwc_otg_pcd_handle_early_suspend_intr(dwc_otg_pcd_t *pcd)
19136 +{
19137 +       gintsts_data_t gintsts;
19138 +#if defined(VERBOSE)
19139 +       DWC_PRINT("Early Suspend Detected\n");
19140 +#endif
19141 +       /* Clear interrupt */
19142 +       gintsts.d32 = 0;
19143 +       gintsts.b.erlysuspend = 1;
19144 +       dwc_write_reg32(&GET_CORE_IF(pcd)->core_global_regs->gintsts,
19145 +                               gintsts.d32);
19146 +       return 1;
19147 +}
19148 +
19149 +/**
19150 + * This function configures EPO to receive SETUP packets.
19151 + *
19152 + * @todo NGS: Update the comments from the HW FS.
19153 + *
19154 + *     -# Program the following fields in the endpoint specific registers
19155 + *     for Control OUT EP 0, in order to receive a setup packet
19156 + *     - DOEPTSIZ0.Packet Count = 3 (To receive up to 3 back to back
19157 + *       setup packets)
19158 + *     - DOEPTSIZE0.Transfer Size = 24 Bytes (To receive up to 3 back
19159 + *       to back setup packets)
19160 + *             - In DMA mode, DOEPDMA0 Register with a memory address to
19161 + *               store any setup packets received
19162 + *
19163 + * @param core_if Programming view of DWC_otg controller.
19164 + * @param pcd    Programming view of the PCD.
19165 + */
19166 +static inline void ep0_out_start(dwc_otg_core_if_t *core_if, dwc_otg_pcd_t *pcd)
19167 +{
19168 +       dwc_otg_dev_if_t *dev_if = core_if->dev_if;
19169 +       deptsiz0_data_t doeptsize0 = { .d32 = 0};
19170 +       dwc_otg_dma_desc_t* dma_desc;
19171 +       depctl_data_t doepctl = { .d32 = 0 };
19172 +
19173 +#ifdef VERBOSE
19174 +       DWC_DEBUGPL(DBG_PCDV,"%s() doepctl0=%0x\n", __func__,
19175 +                               dwc_read_reg32(&dev_if->out_ep_regs[0]->doepctl));
19176 +#endif
19177 +
19178 +       doeptsize0.b.supcnt = 3;
19179 +       doeptsize0.b.pktcnt = 1;
19180 +       doeptsize0.b.xfersize = 8*3;
19181 +
19182 +
19183 +       if (core_if->dma_enable) {
19184 +               if (!core_if->dma_desc_enable) {
19185 +                       /** put here as for Hermes mode deptisz register should not be written */
19186 +                       dwc_write_reg32(&dev_if->out_ep_regs[0]->doeptsiz,
19187 +                        doeptsize0.d32);
19188 +
19189 +                       /** @todo dma needs to handle multiple setup packets (up to 3) */
19190 +                       dwc_write_reg32(&dev_if->out_ep_regs[0]->doepdma,
19191 +                       pcd->setup_pkt_dma_handle);
19192 +               } else {
19193 +                       dev_if->setup_desc_index = (dev_if->setup_desc_index + 1) & 1;
19194 +                       dma_desc = dev_if->setup_desc_addr[dev_if->setup_desc_index];
19195 +
19196 +                       /** DMA Descriptor Setup */
19197 +                       dma_desc->status.b.bs = BS_HOST_BUSY;
19198 +                       dma_desc->status.b.l = 1;
19199 +                       dma_desc->status.b.ioc = 1;
19200 +                       dma_desc->status.b.bytes = pcd->ep0.dwc_ep.maxpacket;
19201 +                       dma_desc->buf = pcd->setup_pkt_dma_handle;
19202 +                       dma_desc->status.b.bs = BS_HOST_READY;
19203 +
19204 +                       /** DOEPDMA0 Register write */
19205 +                       dwc_write_reg32(&dev_if->out_ep_regs[0]->doepdma, dev_if->dma_setup_desc_addr[dev_if->setup_desc_index]);
19206 +               }
19207 +
19208 +       } else {
19209 +               /** put here as for Hermes mode deptisz register should not be written */
19210 +               dwc_write_reg32(&dev_if->out_ep_regs[0]->doeptsiz,
19211 +                                        doeptsize0.d32);
19212 +       }
19213 +
19214 +       /** DOEPCTL0 Register write */
19215 +       doepctl.b.epena = 1;
19216 +       doepctl.b.cnak = 1;
19217 +       dwc_write_reg32(&dev_if->out_ep_regs[0]->doepctl, doepctl.d32);
19218 +
19219 +#ifdef VERBOSE
19220 +       DWC_DEBUGPL(DBG_PCDV,"doepctl0=%0x\n",
19221 +                               dwc_read_reg32(&dev_if->out_ep_regs[0]->doepctl));
19222 +       DWC_DEBUGPL(DBG_PCDV,"diepctl0=%0x\n",
19223 +                               dwc_read_reg32(&dev_if->in_ep_regs[0]->diepctl));
19224 +#endif
19225 +}
19226 +
19227 +
19228 +/**
19229 + * This interrupt occurs when a USB Reset is detected. When the USB
19230 + * Reset Interrupt occurs the device state is set to DEFAULT and the
19231 + * EP0 state is set to IDLE.
19232 + *     -#      Set the NAK bit for all OUT endpoints (DOEPCTLn.SNAK = 1)
19233 + *     -#      Unmask the following interrupt bits
19234 + *             - DAINTMSK.INEP0 = 1 (Control 0 IN endpoint)
19235 + *     - DAINTMSK.OUTEP0 = 1 (Control 0 OUT endpoint)
19236 + *     - DOEPMSK.SETUP = 1
19237 + *     - DOEPMSK.XferCompl = 1
19238 + *     - DIEPMSK.XferCompl = 1
19239 + *     - DIEPMSK.TimeOut = 1
19240 + *     -# Program the following fields in the endpoint specific registers
19241 + *     for Control OUT EP 0, in order to receive a setup packet
19242 + *     - DOEPTSIZ0.Packet Count = 3 (To receive up to 3 back to back
19243 + *       setup packets)
19244 + *     - DOEPTSIZE0.Transfer Size = 24 Bytes (To receive up to 3 back
19245 + *       to back setup packets)
19246 + *             - In DMA mode, DOEPDMA0 Register with a memory address to
19247 + *               store any setup packets received
19248 + * At this point, all the required initialization, except for enabling
19249 + * the control 0 OUT endpoint is done, for receiving SETUP packets.
19250 + */
19251 +int32_t dwc_otg_pcd_handle_usb_reset_intr(dwc_otg_pcd_t * pcd)
19252 +{
19253 +       dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
19254 +       dwc_otg_dev_if_t *dev_if = core_if->dev_if;
19255 +       depctl_data_t doepctl = { .d32 = 0};
19256 +
19257 +       daint_data_t daintmsk = { .d32 = 0};
19258 +       doepmsk_data_t doepmsk = { .d32 = 0};
19259 +       diepmsk_data_t diepmsk = { .d32 = 0};
19260 +
19261 +       dcfg_data_t dcfg = { .d32=0 };
19262 +       grstctl_t resetctl = { .d32=0 };
19263 +       dctl_data_t dctl = {.d32=0};
19264 +       int i = 0;
19265 +       gintsts_data_t gintsts;
19266 +
19267 +       DWC_PRINT("USB RESET\n");
19268 +#ifdef DWC_EN_ISOC
19269 +       for(i = 1;i < 16; ++i)
19270 +       {
19271 +               dwc_otg_pcd_ep_t *ep;
19272 +               dwc_ep_t *dwc_ep;
19273 +               ep = get_in_ep(pcd,i);
19274 +               if(ep != 0){
19275 +                       dwc_ep = &ep->dwc_ep;
19276 +                       dwc_ep->next_frame = 0xffffffff;
19277 +               }
19278 +       }
19279 +#endif /* DWC_EN_ISOC  */
19280 +
19281 +       /* reset the HNP settings */
19282 +       dwc_otg_pcd_update_otg(pcd, 1);
19283 +
19284 +       /* Clear the Remote Wakeup Signalling */
19285 +       dctl.b.rmtwkupsig = 1;
19286 +       dwc_modify_reg32(&core_if->dev_if->dev_global_regs->dctl,
19287 +                                         dctl.d32, 0);
19288 +
19289 +       /* Set NAK for all OUT EPs */
19290 +       doepctl.b.snak = 1;
19291 +       for (i=0; i <= dev_if->num_out_eps; i++)
19292 +       {
19293 +               dwc_write_reg32(&dev_if->out_ep_regs[i]->doepctl,
19294 +                                                doepctl.d32);
19295 +       }
19296 +
19297 +       /* Flush the NP Tx FIFO */
19298 +       dwc_otg_flush_tx_fifo(core_if, 0x10);
19299 +       /* Flush the Learning Queue */
19300 +       resetctl.b.intknqflsh = 1;
19301 +       dwc_write_reg32(&core_if->core_global_regs->grstctl, resetctl.d32);
19302 +
19303 +       if(core_if->multiproc_int_enable) {
19304 +               daintmsk.b.inep0 = 1;
19305 +               daintmsk.b.outep0 = 1;
19306 +               dwc_write_reg32(&dev_if->dev_global_regs->deachintmsk, daintmsk.d32);
19307 +
19308 +               doepmsk.b.setup = 1;
19309 +               doepmsk.b.xfercompl = 1;
19310 +               doepmsk.b.ahberr = 1;
19311 +               doepmsk.b.epdisabled = 1;
19312 +
19313 +               if(core_if->dma_desc_enable) {
19314 +                       doepmsk.b.stsphsercvd = 1;
19315 +                       doepmsk.b.bna = 1;
19316 +               }
19317 +/*
19318 +               doepmsk.b.babble = 1;
19319 +               doepmsk.b.nyet = 1;
19320 +
19321 +               if(core_if->dma_enable) {
19322 +                       doepmsk.b.nak = 1;
19323 +               }
19324 +*/
19325 +               dwc_write_reg32(&dev_if->dev_global_regs->doepeachintmsk[0], doepmsk.d32);
19326 +
19327 +               diepmsk.b.xfercompl = 1;
19328 +               diepmsk.b.timeout = 1;
19329 +               diepmsk.b.epdisabled = 1;
19330 +               diepmsk.b.ahberr = 1;
19331 +               diepmsk.b.intknepmis = 1;
19332 +
19333 +               if(core_if->dma_desc_enable) {
19334 +                       diepmsk.b.bna = 1;
19335 +               }
19336 +/*
19337 +               if(core_if->dma_enable) {
19338 +                       diepmsk.b.nak = 1;
19339 +               }
19340 +*/
19341 +               dwc_write_reg32(&dev_if->dev_global_regs->diepeachintmsk[0], diepmsk.d32);
19342 +       } else{
19343 +               daintmsk.b.inep0 = 1;
19344 +               daintmsk.b.outep0 = 1;
19345 +               dwc_write_reg32(&dev_if->dev_global_regs->daintmsk, daintmsk.d32);
19346 +
19347 +               doepmsk.b.setup = 1;
19348 +               doepmsk.b.xfercompl = 1;
19349 +               doepmsk.b.ahberr = 1;
19350 +               doepmsk.b.epdisabled = 1;
19351 +
19352 +               if(core_if->dma_desc_enable) {
19353 +                       doepmsk.b.stsphsercvd = 1;
19354 +                       doepmsk.b.bna = 1;
19355 +               }
19356 +/*
19357 +               doepmsk.b.babble = 1;
19358 +               doepmsk.b.nyet = 1;
19359 +               doepmsk.b.nak = 1;
19360 +*/
19361 +               dwc_write_reg32(&dev_if->dev_global_regs->doepmsk, doepmsk.d32);
19362 +
19363 +               diepmsk.b.xfercompl = 1;
19364 +               diepmsk.b.timeout = 1;
19365 +               diepmsk.b.epdisabled = 1;
19366 +               diepmsk.b.ahberr = 1;
19367 +               diepmsk.b.intknepmis = 1;
19368 +
19369 +               if(core_if->dma_desc_enable) {
19370 +                       diepmsk.b.bna = 1;
19371 +               }
19372 +
19373 +//             diepmsk.b.nak = 1;
19374 +
19375 +               dwc_write_reg32(&dev_if->dev_global_regs->diepmsk, diepmsk.d32);
19376 +       }
19377 +
19378 +       /* Reset Device Address */
19379 +       dcfg.d32 = dwc_read_reg32(&dev_if->dev_global_regs->dcfg);
19380 +       dcfg.b.devaddr = 0;
19381 +       dwc_write_reg32(&dev_if->dev_global_regs->dcfg, dcfg.d32);
19382 +
19383 +       /* setup EP0 to receive SETUP packets */
19384 +       ep0_out_start(core_if, pcd);
19385 +
19386 +       /* Clear interrupt */
19387 +       gintsts.d32 = 0;
19388 +       gintsts.b.usbreset = 1;
19389 +       dwc_write_reg32 (&core_if->core_global_regs->gintsts, gintsts.d32);
19390 +
19391 +       return 1;
19392 +}
19393 +
19394 +/**
19395 + * Get the device speed from the device status register and convert it
19396 + * to USB speed constant.
19397 + *
19398 + * @param core_if Programming view of DWC_otg controller.
19399 + */
19400 +static int get_device_speed(dwc_otg_core_if_t *core_if)
19401 +{
19402 +       dsts_data_t dsts;
19403 +       enum usb_device_speed speed = USB_SPEED_UNKNOWN;
19404 +       dsts.d32 = dwc_read_reg32(&core_if->dev_if->dev_global_regs->dsts);
19405 +
19406 +       switch (dsts.b.enumspd) {
19407 +       case DWC_DSTS_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ:
19408 +               speed = USB_SPEED_HIGH;
19409 +               break;
19410 +       case DWC_DSTS_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ:
19411 +       case DWC_DSTS_ENUMSPD_FS_PHY_48MHZ:
19412 +               speed = USB_SPEED_FULL;
19413 +               break;
19414 +
19415 +       case DWC_DSTS_ENUMSPD_LS_PHY_6MHZ:
19416 +               speed = USB_SPEED_LOW;
19417 +               break;
19418 +       }
19419 +
19420 +       return speed;
19421 +}
19422 +
19423 +/**
19424 + * Read the device status register and set the device speed in the
19425 + * data structure.
19426 + * Set up EP0 to receive SETUP packets by calling dwc_ep0_activate.
19427 + */
19428 +int32_t dwc_otg_pcd_handle_enum_done_intr(dwc_otg_pcd_t *pcd)
19429 +{
19430 +       dwc_otg_pcd_ep_t *ep0 = &pcd->ep0;
19431 +       gintsts_data_t gintsts;
19432 +       gusbcfg_data_t gusbcfg;
19433 +       dwc_otg_core_global_regs_t *global_regs =
19434 +               GET_CORE_IF(pcd)->core_global_regs;
19435 +       uint8_t utmi16b, utmi8b;
19436 +       DWC_DEBUGPL(DBG_PCD, "SPEED ENUM\n");
19437 +
19438 +       if (GET_CORE_IF(pcd)->snpsid >= 0x4F54260A) {
19439 +               utmi16b = 6;
19440 +               utmi8b = 9;
19441 +       } else {
19442 +               utmi16b = 4;
19443 +               utmi8b = 8;
19444 +       }
19445 +       dwc_otg_ep0_activate(GET_CORE_IF(pcd), &ep0->dwc_ep);
19446 +
19447 +#ifdef DEBUG_EP0
19448 +       print_ep0_state(pcd);
19449 +#endif
19450 +
19451 +       if (pcd->ep0state == EP0_DISCONNECT) {
19452 +               pcd->ep0state = EP0_IDLE;
19453 +       }
19454 +       else if (pcd->ep0state == EP0_STALL) {
19455 +               pcd->ep0state = EP0_IDLE;
19456 +       }
19457 +
19458 +       pcd->ep0state = EP0_IDLE;
19459 +
19460 +       ep0->stopped = 0;
19461 +
19462 +       pcd->gadget.speed = get_device_speed(GET_CORE_IF(pcd));
19463 +
19464 +       /* Set USB turnaround time based on device speed and PHY interface. */
19465 +       gusbcfg.d32 = dwc_read_reg32(&global_regs->gusbcfg);
19466 +       if (pcd->gadget.speed == USB_SPEED_HIGH) {
19467 +               if (GET_CORE_IF(pcd)->hwcfg2.b.hs_phy_type == DWC_HWCFG2_HS_PHY_TYPE_ULPI) {
19468 +                       /* ULPI interface */
19469 +                       gusbcfg.b.usbtrdtim = 9;
19470 +               }
19471 +               if (GET_CORE_IF(pcd)->hwcfg2.b.hs_phy_type == DWC_HWCFG2_HS_PHY_TYPE_UTMI) {
19472 +                       /* UTMI+ interface */
19473 +                       if (GET_CORE_IF(pcd)->hwcfg4.b.utmi_phy_data_width == 0) {
19474 +                               gusbcfg.b.usbtrdtim = utmi8b;
19475 +                       }
19476 +                       else if (GET_CORE_IF(pcd)->hwcfg4.b.utmi_phy_data_width == 1) {
19477 +                               gusbcfg.b.usbtrdtim = utmi16b;
19478 +                       }
19479 +                       else if (GET_CORE_IF(pcd)->core_params->phy_utmi_width == 8) {
19480 +                               gusbcfg.b.usbtrdtim = utmi8b;
19481 +                       }
19482 +                       else {
19483 +                               gusbcfg.b.usbtrdtim = utmi16b;
19484 +                       }
19485 +               }
19486 +               if (GET_CORE_IF(pcd)->hwcfg2.b.hs_phy_type == DWC_HWCFG2_HS_PHY_TYPE_UTMI_ULPI) {
19487 +                       /* UTMI+  OR  ULPI interface */
19488 +                       if (gusbcfg.b.ulpi_utmi_sel == 1) {
19489 +                               /* ULPI interface */
19490 +                               gusbcfg.b.usbtrdtim = 9;
19491 +                       }
19492 +                       else {
19493 +                               /* UTMI+ interface */
19494 +                               if (GET_CORE_IF(pcd)->core_params->phy_utmi_width == 16) {
19495 +                                       gusbcfg.b.usbtrdtim = utmi16b;
19496 +                               }
19497 +                               else {
19498 +                                       gusbcfg.b.usbtrdtim = utmi8b;
19499 +                               }
19500 +                       }
19501 +               }
19502 +       }
19503 +       else {
19504 +               /* Full or low speed */
19505 +               gusbcfg.b.usbtrdtim = 9;
19506 +       }
19507 +       dwc_write_reg32(&global_regs->gusbcfg, gusbcfg.d32);
19508 +
19509 +       /* Clear interrupt */
19510 +       gintsts.d32 = 0;
19511 +       gintsts.b.enumdone = 1;
19512 +       dwc_write_reg32(&GET_CORE_IF(pcd)->core_global_regs->gintsts,
19513 +                        gintsts.d32);
19514 +       return 1;
19515 +}
19516 +
19517 +/**
19518 + * This interrupt indicates that the ISO OUT Packet was dropped due to
19519 + * Rx FIFO full or Rx Status Queue Full.  If this interrupt occurs
19520 + * read all the data from the Rx FIFO.
19521 + */
19522 +int32_t dwc_otg_pcd_handle_isoc_out_packet_dropped_intr(dwc_otg_pcd_t *pcd)
19523 +{
19524 +       gintmsk_data_t intr_mask = { .d32 = 0};
19525 +       gintsts_data_t gintsts;
19526 +
19527 +       DWC_PRINT("INTERRUPT Handler not implemented for %s\n",
19528 +                         "ISOC Out Dropped");
19529 +
19530 +       intr_mask.b.isooutdrop = 1;
19531 +       dwc_modify_reg32(&GET_CORE_IF(pcd)->core_global_regs->gintmsk,
19532 +                         intr_mask.d32, 0);
19533 +
19534 +       /* Clear interrupt */
19535 +
19536 +       gintsts.d32 = 0;
19537 +       gintsts.b.isooutdrop = 1;
19538 +       dwc_write_reg32(&GET_CORE_IF(pcd)->core_global_regs->gintsts,
19539 +                        gintsts.d32);
19540 +
19541 +       return 1;
19542 +}
19543 +
19544 +/**
19545 + * This interrupt indicates the end of the portion of the micro-frame
19546 + * for periodic transactions.  If there is a periodic transaction for
19547 + * the next frame, load the packets into the EP periodic Tx FIFO.
19548 + */
19549 +int32_t dwc_otg_pcd_handle_end_periodic_frame_intr(dwc_otg_pcd_t *pcd)
19550 +{
19551 +       gintmsk_data_t intr_mask = { .d32 = 0};
19552 +       gintsts_data_t gintsts;
19553 +       DWC_PRINT("INTERRUPT Handler not implemented for %s\n", "EOP");
19554 +
19555 +       intr_mask.b.eopframe = 1;
19556 +       dwc_modify_reg32(&GET_CORE_IF(pcd)->core_global_regs->gintmsk,
19557 +                                         intr_mask.d32, 0);
19558 +
19559 +       /* Clear interrupt */
19560 +       gintsts.d32 = 0;
19561 +       gintsts.b.eopframe = 1;
19562 +       dwc_write_reg32(&GET_CORE_IF(pcd)->core_global_regs->gintsts, gintsts.d32);
19563 +
19564 +       return 1;
19565 +}
19566 +
19567 +/**
19568 + * This interrupt indicates that EP of the packet on the top of the
19569 + * non-periodic Tx FIFO does not match EP of the IN Token received.
19570 + *
19571 + * The "Device IN Token Queue" Registers are read to determine the
19572 + * order the IN Tokens have been received.     The non-periodic Tx FIFO
19573 + * is flushed, so it can be reloaded in the order seen in the IN Token
19574 + * Queue.
19575 + */
19576 +int32_t dwc_otg_pcd_handle_ep_mismatch_intr(dwc_otg_core_if_t *core_if)
19577 +{
19578 +       gintsts_data_t gintsts;
19579 +       DWC_DEBUGPL(DBG_PCDV, "%s(%p)\n", __func__, core_if);
19580 +
19581 +       /* Clear interrupt */
19582 +       gintsts.d32 = 0;
19583 +       gintsts.b.epmismatch = 1;
19584 +       dwc_write_reg32 (&core_if->core_global_regs->gintsts, gintsts.d32);
19585 +
19586 +       return 1;
19587 +}
19588 +
19589 +/**
19590 + * This funcion stalls EP0.
19591 + */
19592 +static inline void ep0_do_stall(dwc_otg_pcd_t *pcd, const int err_val)
19593 +{
19594 +       dwc_otg_pcd_ep_t *ep0 = &pcd->ep0;
19595 +       struct usb_ctrlrequest  *ctrl = &pcd->setup_pkt->req;
19596 +       DWC_WARN("req %02x.%02x protocol STALL; err %d\n",
19597 +                        ctrl->bRequestType, ctrl->bRequest, err_val);
19598 +
19599 +       ep0->dwc_ep.is_in = 1;
19600 +       dwc_otg_ep_set_stall(pcd->otg_dev->core_if, &ep0->dwc_ep);
19601 +       pcd->ep0.stopped = 1;
19602 +       pcd->ep0state = EP0_IDLE;
19603 +       ep0_out_start(GET_CORE_IF(pcd), pcd);
19604 +}
19605 +
19606 +/**
19607 + * This functions delegates the setup command to the gadget driver.
19608 + */
19609 +static inline void do_gadget_setup(dwc_otg_pcd_t *pcd,
19610 +                                       struct usb_ctrlrequest * ctrl)
19611 +{
19612 +       int ret = 0;
19613 +       if (pcd->driver && pcd->driver->setup) {
19614 +               SPIN_UNLOCK(&pcd->lock);
19615 +               ret = pcd->driver->setup(&pcd->gadget, ctrl);
19616 +               SPIN_LOCK(&pcd->lock);
19617 +               if (ret < 0) {
19618 +                       ep0_do_stall(pcd, ret);
19619 +               }
19620 +
19621 +               /** @todo This is a g_file_storage gadget driver specific
19622 +                * workaround: a DELAYED_STATUS result from the fsg_setup
19623 +                * routine will result in the gadget queueing a EP0 IN status
19624 +                * phase for a two-stage control transfer.      Exactly the same as
19625 +                * a SET_CONFIGURATION/SET_INTERFACE except that this is a class
19626 +                * specific request.  Need a generic way to know when the gadget
19627 +                * driver will queue the status phase.  Can we assume when we
19628 +                * call the gadget driver setup() function that it will always
19629 +                * queue and require the following flag?  Need to look into
19630 +                * this.
19631 +                */
19632 +
19633 +               if (ret == 256 + 999) {
19634 +                       pcd->request_config = 1;
19635 +               }
19636 +       }
19637 +}
19638 +
19639 +/**
19640 + * This function starts the Zero-Length Packet for the IN status phase
19641 + * of a 2 stage control transfer.
19642 + */
19643 +static inline void do_setup_in_status_phase(dwc_otg_pcd_t *pcd)
19644 +{
19645 +       dwc_otg_pcd_ep_t *ep0 = &pcd->ep0;
19646 +       if (pcd->ep0state == EP0_STALL) {
19647 +               return;
19648 +       }
19649 +
19650 +       pcd->ep0state = EP0_IN_STATUS_PHASE;
19651 +
19652 +       /* Prepare for more SETUP Packets */
19653 +       DWC_DEBUGPL(DBG_PCD, "EP0 IN ZLP\n");
19654 +       ep0->dwc_ep.xfer_len = 0;
19655 +       ep0->dwc_ep.xfer_count = 0;
19656 +       ep0->dwc_ep.is_in = 1;
19657 +       ep0->dwc_ep.dma_addr = pcd->setup_pkt_dma_handle;
19658 +       dwc_otg_ep0_start_transfer(GET_CORE_IF(pcd), &ep0->dwc_ep);
19659 +
19660 +       /* Prepare for more SETUP Packets */
19661 +//     if(GET_CORE_IF(pcd)->dma_enable == 0) ep0_out_start(GET_CORE_IF(pcd), pcd);
19662 +}
19663 +
19664 +/**
19665 + * This function starts the Zero-Length Packet for the OUT status phase
19666 + * of a 2 stage control transfer.
19667 + */
19668 +static inline void do_setup_out_status_phase(dwc_otg_pcd_t *pcd)
19669 +{
19670 +       dwc_otg_pcd_ep_t *ep0 = &pcd->ep0;
19671 +       if (pcd->ep0state == EP0_STALL) {
19672 +               DWC_DEBUGPL(DBG_PCD, "EP0 STALLED\n");
19673 +               return;
19674 +       }
19675 +       pcd->ep0state = EP0_OUT_STATUS_PHASE;
19676 +
19677 +       DWC_DEBUGPL(DBG_PCD, "EP0 OUT ZLP\n");
19678 +       ep0->dwc_ep.xfer_len = 0;
19679 +       ep0->dwc_ep.xfer_count = 0;
19680 +       ep0->dwc_ep.is_in = 0;
19681 +       ep0->dwc_ep.dma_addr = pcd->setup_pkt_dma_handle;
19682 +       dwc_otg_ep0_start_transfer(GET_CORE_IF(pcd), &ep0->dwc_ep);
19683 +
19684 +       /* Prepare for more SETUP Packets */
19685 +       if(GET_CORE_IF(pcd)->dma_enable == 0) {
19686 +                       ep0_out_start(GET_CORE_IF(pcd), pcd);
19687 +       }
19688 +}
19689 +
19690 +/**
19691 + * Clear the EP halt (STALL) and if pending requests start the
19692 + * transfer.
19693 + */
19694 +static inline void pcd_clear_halt(dwc_otg_pcd_t *pcd, dwc_otg_pcd_ep_t *ep)
19695 +{
19696 +       if(ep->dwc_ep.stall_clear_flag == 0)
19697 +               dwc_otg_ep_clear_stall(GET_CORE_IF(pcd), &ep->dwc_ep);
19698 +
19699 +       /* Reactive the EP */
19700 +       dwc_otg_ep_activate(GET_CORE_IF(pcd), &ep->dwc_ep);
19701 +       if (ep->stopped) {
19702 +               ep->stopped = 0;
19703 +               /* If there is a request in the EP queue start it */
19704 +
19705 +               /** @todo FIXME: this causes an EP mismatch in DMA mode.
19706 +                * epmismatch not yet implemented. */
19707 +
19708 +               /*
19709 +                * Above fixme is solved by implmenting a tasklet to call the
19710 +                * start_next_request(), outside of interrupt context at some
19711 +                * time after the current time, after a clear-halt setup packet.
19712 +                * Still need to implement ep mismatch in the future if a gadget
19713 +                * ever uses more than one endpoint at once
19714 +                */
19715 +               ep->queue_sof = 1;
19716 +               tasklet_schedule (pcd->start_xfer_tasklet);
19717 +       }
19718 +       /* Start Control Status Phase */
19719 +       do_setup_in_status_phase(pcd);
19720 +}
19721 +
19722 +/**
19723 + * This function is called when the SET_FEATURE TEST_MODE Setup packet
19724 + * is sent from the host.  The Device Control register is written with
19725 + * the Test Mode bits set to the specified Test Mode.  This is done as
19726 + * a tasklet so that the "Status" phase of the control transfer
19727 + * completes before transmitting the TEST packets.
19728 + *
19729 + * @todo This has not been tested since the tasklet struct was put
19730 + * into the PCD struct!
19731 + *
19732 + */
19733 +static void do_test_mode(unsigned long data)
19734 +{
19735 +       dctl_data_t             dctl;
19736 +       dwc_otg_pcd_t *pcd = (dwc_otg_pcd_t *)data;
19737 +       dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
19738 +       int test_mode = pcd->test_mode;
19739 +
19740 +
19741 +//       DWC_WARN("%s() has not been tested since being rewritten!\n", __func__);
19742 +
19743 +       dctl.d32 = dwc_read_reg32(&core_if->dev_if->dev_global_regs->dctl);
19744 +       switch (test_mode) {
19745 +       case 1: // TEST_J
19746 +               dctl.b.tstctl = 1;
19747 +               break;
19748 +
19749 +       case 2: // TEST_K
19750 +               dctl.b.tstctl = 2;
19751 +               break;
19752 +
19753 +       case 3: // TEST_SE0_NAK
19754 +               dctl.b.tstctl = 3;
19755 +               break;
19756 +
19757 +       case 4: // TEST_PACKET
19758 +               dctl.b.tstctl = 4;
19759 +               break;
19760 +
19761 +       case 5: // TEST_FORCE_ENABLE
19762 +               dctl.b.tstctl = 5;
19763 +               break;
19764 +       }
19765 +       dwc_write_reg32(&core_if->dev_if->dev_global_regs->dctl, dctl.d32);
19766 +}
19767 +
19768 +/**
19769 + * This function process the GET_STATUS Setup Commands.
19770 + */
19771 +static inline void do_get_status(dwc_otg_pcd_t *pcd)
19772 +{
19773 +       struct usb_ctrlrequest  ctrl = pcd->setup_pkt->req;
19774 +       dwc_otg_pcd_ep_t        *ep;
19775 +       dwc_otg_pcd_ep_t        *ep0 = &pcd->ep0;
19776 +       uint16_t                *status = pcd->status_buf;
19777 +
19778 +#ifdef DEBUG_EP0
19779 +       DWC_DEBUGPL(DBG_PCD,
19780 +                       "GET_STATUS %02x.%02x v%04x i%04x l%04x\n",
19781 +                       ctrl.bRequestType, ctrl.bRequest,
19782 +                       ctrl.wValue, ctrl.wIndex, ctrl.wLength);
19783 +#endif
19784 +
19785 +       switch (ctrl.bRequestType & USB_RECIP_MASK) {
19786 +       case USB_RECIP_DEVICE:
19787 +               *status = 0x1; /* Self powered */
19788 +               *status |= pcd->remote_wakeup_enable << 1;
19789 +               break;
19790 +
19791 +       case USB_RECIP_INTERFACE:
19792 +               *status = 0;
19793 +               break;
19794 +
19795 +       case USB_RECIP_ENDPOINT:
19796 +               ep = get_ep_by_addr(pcd, ctrl.wIndex);
19797 +               if (ep == 0 || ctrl.wLength > 2) {
19798 +                       ep0_do_stall(pcd, -EOPNOTSUPP);
19799 +                       return;
19800 +               }
19801 +               /** @todo check for EP stall */
19802 +               *status = ep->stopped;
19803 +               break;
19804 +       }
19805 +       pcd->ep0_pending = 1;
19806 +       ep0->dwc_ep.start_xfer_buff = (uint8_t *)status;
19807 +       ep0->dwc_ep.xfer_buff = (uint8_t *)status;
19808 +       ep0->dwc_ep.dma_addr = pcd->status_buf_dma_handle;
19809 +       ep0->dwc_ep.xfer_len = 2;
19810 +       ep0->dwc_ep.xfer_count = 0;
19811 +       ep0->dwc_ep.total_len = ep0->dwc_ep.xfer_len;
19812 +       dwc_otg_ep0_start_transfer(GET_CORE_IF(pcd), &ep0->dwc_ep);
19813 +}
19814 +/**
19815 + * This function process the SET_FEATURE Setup Commands.
19816 + */
19817 +static inline void do_set_feature(dwc_otg_pcd_t *pcd)
19818 +{
19819 +       dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
19820 +       dwc_otg_core_global_regs_t *global_regs =
19821 +                       core_if->core_global_regs;
19822 +       struct usb_ctrlrequest  ctrl = pcd->setup_pkt->req;
19823 +       dwc_otg_pcd_ep_t        *ep = 0;
19824 +       int32_t otg_cap_param = core_if->core_params->otg_cap;
19825 +       gotgctl_data_t gotgctl = { .d32 = 0 };
19826 +
19827 +       DWC_DEBUGPL(DBG_PCD, "SET_FEATURE:%02x.%02x v%04x i%04x l%04x\n",
19828 +                       ctrl.bRequestType, ctrl.bRequest,
19829 +                       ctrl.wValue, ctrl.wIndex, ctrl.wLength);
19830 +       DWC_DEBUGPL(DBG_PCD,"otg_cap=%d\n", otg_cap_param);
19831 +
19832 +
19833 +       switch (ctrl.bRequestType & USB_RECIP_MASK) {
19834 +       case USB_RECIP_DEVICE:
19835 +               switch (ctrl.wValue) {
19836 +               case USB_DEVICE_REMOTE_WAKEUP:
19837 +                       pcd->remote_wakeup_enable = 1;
19838 +                       break;
19839 +
19840 +               case USB_DEVICE_TEST_MODE:
19841 +                       /* Setup the Test Mode tasklet to do the Test
19842 +                        * Packet generation after the SETUP Status
19843 +                        * phase has completed. */
19844 +
19845 +                       /** @todo This has not been tested since the
19846 +                        * tasklet struct was put into the PCD
19847 +                        * struct! */
19848 +                       pcd->test_mode_tasklet.next = 0;
19849 +                       pcd->test_mode_tasklet.state = 0;
19850 +                       atomic_set(&pcd->test_mode_tasklet.count, 0);
19851 +                       pcd->test_mode_tasklet.func = do_test_mode;
19852 +                       pcd->test_mode_tasklet.data = (unsigned long)pcd;
19853 +                       pcd->test_mode = ctrl.wIndex >> 8;
19854 +                       tasklet_schedule(&pcd->test_mode_tasklet);
19855 +                       break;
19856 +
19857 +               case USB_DEVICE_B_HNP_ENABLE:
19858 +                       DWC_DEBUGPL(DBG_PCDV, "SET_FEATURE: USB_DEVICE_B_HNP_ENABLE\n");
19859 +
19860 +                       /* dev may initiate HNP */
19861 +                       if (otg_cap_param == DWC_OTG_CAP_PARAM_HNP_SRP_CAPABLE) {
19862 +                               pcd->b_hnp_enable = 1;
19863 +                               dwc_otg_pcd_update_otg(pcd, 0);
19864 +                               DWC_DEBUGPL(DBG_PCD, "Request B HNP\n");
19865 +                               /**@todo Is the gotgctl.devhnpen cleared
19866 +                                * by a USB Reset? */
19867 +                               gotgctl.b.devhnpen = 1;
19868 +                               gotgctl.b.hnpreq = 1;
19869 +                               dwc_write_reg32(&global_regs->gotgctl, gotgctl.d32);
19870 +                       }
19871 +                       else {
19872 +                               ep0_do_stall(pcd, -EOPNOTSUPP);
19873 +                       }
19874 +                       break;
19875 +
19876 +               case USB_DEVICE_A_HNP_SUPPORT:
19877 +                       /* RH port supports HNP */
19878 +                       DWC_DEBUGPL(DBG_PCDV, "SET_FEATURE: USB_DEVICE_A_HNP_SUPPORT\n");
19879 +                       if (otg_cap_param == DWC_OTG_CAP_PARAM_HNP_SRP_CAPABLE) {
19880 +                               pcd->a_hnp_support = 1;
19881 +                               dwc_otg_pcd_update_otg(pcd, 0);
19882 +                       }
19883 +                       else {
19884 +                               ep0_do_stall(pcd, -EOPNOTSUPP);
19885 +                       }
19886 +                       break;
19887 +
19888 +               case USB_DEVICE_A_ALT_HNP_SUPPORT:
19889 +                       /* other RH port does */
19890 +                       DWC_DEBUGPL(DBG_PCDV, "SET_FEATURE: USB_DEVICE_A_ALT_HNP_SUPPORT\n");
19891 +                       if (otg_cap_param == DWC_OTG_CAP_PARAM_HNP_SRP_CAPABLE) {
19892 +                               pcd->a_alt_hnp_support = 1;
19893 +                               dwc_otg_pcd_update_otg(pcd, 0);
19894 +                       }
19895 +                       else {
19896 +                               ep0_do_stall(pcd, -EOPNOTSUPP);
19897 +                       }
19898 +                       break;
19899 +               }
19900 +               do_setup_in_status_phase(pcd);
19901 +               break;
19902 +
19903 +       case USB_RECIP_INTERFACE:
19904 +               do_gadget_setup(pcd, &ctrl);
19905 +               break;
19906 +
19907 +       case USB_RECIP_ENDPOINT:
19908 +               if (ctrl.wValue == USB_ENDPOINT_HALT) {
19909 +                       ep = get_ep_by_addr(pcd, ctrl.wIndex);
19910 +                       if (ep == 0) {
19911 +                               ep0_do_stall(pcd, -EOPNOTSUPP);
19912 +                               return;
19913 +                       }
19914 +                       ep->stopped = 1;
19915 +                       dwc_otg_ep_set_stall(core_if, &ep->dwc_ep);
19916 +               }
19917 +               do_setup_in_status_phase(pcd);
19918 +               break;
19919 +       }
19920 +}
19921 +
19922 +/**
19923 + * This function process the CLEAR_FEATURE Setup Commands.
19924 + */
19925 +static inline void do_clear_feature(dwc_otg_pcd_t *pcd)
19926 +{
19927 +       struct usb_ctrlrequest  ctrl = pcd->setup_pkt->req;
19928 +       dwc_otg_pcd_ep_t        *ep = 0;
19929 +
19930 +       DWC_DEBUGPL(DBG_PCD,
19931 +                               "CLEAR_FEATURE:%02x.%02x v%04x i%04x l%04x\n",
19932 +                               ctrl.bRequestType, ctrl.bRequest,
19933 +                               ctrl.wValue, ctrl.wIndex, ctrl.wLength);
19934 +
19935 +       switch (ctrl.bRequestType & USB_RECIP_MASK) {
19936 +       case USB_RECIP_DEVICE:
19937 +               switch (ctrl.wValue) {
19938 +               case USB_DEVICE_REMOTE_WAKEUP:
19939 +                       pcd->remote_wakeup_enable = 0;
19940 +                       break;
19941 +
19942 +               case USB_DEVICE_TEST_MODE:
19943 +                       /** @todo Add CLEAR_FEATURE for TEST modes. */
19944 +                       break;
19945 +               }
19946 +               do_setup_in_status_phase(pcd);
19947 +               break;
19948 +
19949 +       case USB_RECIP_ENDPOINT:
19950 +               ep = get_ep_by_addr(pcd, ctrl.wIndex);
19951 +               if (ep == 0) {
19952 +                       ep0_do_stall(pcd, -EOPNOTSUPP);
19953 +                       return;
19954 +               }
19955 +
19956 +               pcd_clear_halt(pcd, ep);
19957 +
19958 +               break;
19959 +       }
19960 +}
19961 +
19962 +/**
19963 + * This function process the SET_ADDRESS Setup Commands.
19964 + */
19965 +static inline void do_set_address(dwc_otg_pcd_t *pcd)
19966 +{
19967 +       dwc_otg_dev_if_t *dev_if = GET_CORE_IF(pcd)->dev_if;
19968 +       struct usb_ctrlrequest  ctrl = pcd->setup_pkt->req;
19969 +
19970 +       if (ctrl.bRequestType == USB_RECIP_DEVICE) {
19971 +               dcfg_data_t dcfg = {.d32=0};
19972 +
19973 +#ifdef DEBUG_EP0
19974 +//                     DWC_DEBUGPL(DBG_PCDV, "SET_ADDRESS:%d\n", ctrl.wValue);
19975 +#endif
19976 +               dcfg.b.devaddr = ctrl.wValue;
19977 +               dwc_modify_reg32(&dev_if->dev_global_regs->dcfg, 0, dcfg.d32);
19978 +               do_setup_in_status_phase(pcd);
19979 +       }
19980 +}
19981 +
19982 +/**
19983 + *     This function processes SETUP commands.  In Linux, the USB Command
19984 + *     processing is done in two places - the first being the PCD and the
19985 + *     second in the Gadget Driver (for example, the File-Backed Storage
19986 + *     Gadget Driver).
19987 + *
19988 + * <table>
19989 + * <tr><td>Command     </td><td>Driver </td><td>Description</td></tr>
19990 + *
19991 + * <tr><td>GET_STATUS </td><td>PCD </td><td>Command is processed as
19992 + * defined in chapter 9 of the USB 2.0 Specification chapter 9
19993 + * </td></tr>
19994 + *
19995 + * <tr><td>CLEAR_FEATURE </td><td>PCD </td><td>The Device and Endpoint
19996 + * requests are the ENDPOINT_HALT feature is procesed, all others the
19997 + * interface requests are ignored.</td></tr>
19998 + *
19999 + * <tr><td>SET_FEATURE </td><td>PCD </td><td>The Device and Endpoint
20000 + * requests are processed by the PCD.  Interface requests are passed
20001 + * to the Gadget Driver.</td></tr>
20002 + *
20003 + * <tr><td>SET_ADDRESS </td><td>PCD </td><td>Program the DCFG reg,
20004 + * with device address received </td></tr>
20005 + *
20006 + * <tr><td>GET_DESCRIPTOR </td><td>Gadget Driver </td><td>Return the
20007 + * requested descriptor</td></tr>
20008 + *
20009 + * <tr><td>SET_DESCRIPTOR </td><td>Gadget Driver </td><td>Optional -
20010 + * not implemented by any of the existing Gadget Drivers.</td></tr>
20011 + *
20012 + * <tr><td>SET_CONFIGURATION </td><td>Gadget Driver </td><td>Disable
20013 + * all EPs and enable EPs for new configuration.</td></tr>
20014 + *
20015 + * <tr><td>GET_CONFIGURATION </td><td>Gadget Driver </td><td>Return
20016 + * the current configuration</td></tr>
20017 + *
20018 + * <tr><td>SET_INTERFACE </td><td>Gadget Driver </td><td>Disable all
20019 + * EPs and enable EPs for new configuration.</td></tr>
20020 + *
20021 + * <tr><td>GET_INTERFACE </td><td>Gadget Driver </td><td>Return the
20022 + * current interface.</td></tr>
20023 + *
20024 + * <tr><td>SYNC_FRAME </td><td>PCD </td><td>Display debug
20025 + * message.</td></tr>
20026 + * </table>
20027 + *
20028 + * When the SETUP Phase Done interrupt occurs, the PCD SETUP commands are
20029 + * processed by pcd_setup. Calling the Function Driver's setup function from
20030 + * pcd_setup processes the gadget SETUP commands.
20031 + */
20032 +static inline void pcd_setup(dwc_otg_pcd_t *pcd)
20033 +{
20034 +       dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
20035 +       dwc_otg_dev_if_t *dev_if = core_if->dev_if;
20036 +       struct usb_ctrlrequest  ctrl = pcd->setup_pkt->req;
20037 +       dwc_otg_pcd_ep_t        *ep0 = &pcd->ep0;
20038 +
20039 +       deptsiz0_data_t doeptsize0 = { .d32 = 0};
20040 +
20041 +#ifdef DEBUG_EP0
20042 +       DWC_DEBUGPL(DBG_PCD, "SETUP %02x.%02x v%04x i%04x l%04x\n",
20043 +                       ctrl.bRequestType, ctrl.bRequest,
20044 +                       ctrl.wValue, ctrl.wIndex, ctrl.wLength);
20045 +#endif
20046 +
20047 +       doeptsize0.d32 = dwc_read_reg32(&dev_if->out_ep_regs[0]->doeptsiz);
20048 +
20049 +       /** @todo handle > 1 setup packet , assert error for now */
20050 +
20051 +       if (core_if->dma_enable && core_if->dma_desc_enable == 0 && (doeptsize0.b.supcnt < 2)) {
20052 +               DWC_ERROR ("\n\n-----------      CANNOT handle > 1 setup packet in DMA mode\n\n");
20053 +       }
20054 +
20055 +       /* Clean up the request queue */
20056 +       dwc_otg_request_nuke(ep0);
20057 +       ep0->stopped = 0;
20058 +
20059 +       if (ctrl.bRequestType & USB_DIR_IN) {
20060 +               ep0->dwc_ep.is_in = 1;
20061 +               pcd->ep0state = EP0_IN_DATA_PHASE;
20062 +       }
20063 +       else {
20064 +               ep0->dwc_ep.is_in = 0;
20065 +               pcd->ep0state = EP0_OUT_DATA_PHASE;
20066 +       }
20067 +
20068 +       if(ctrl.wLength == 0) {
20069 +               ep0->dwc_ep.is_in = 1;
20070 +               pcd->ep0state = EP0_IN_STATUS_PHASE;
20071 +       }
20072 +
20073 +       if ((ctrl.bRequestType & USB_TYPE_MASK) != USB_TYPE_STANDARD) {
20074 +               /* handle non-standard (class/vendor) requests in the gadget driver */
20075 +               do_gadget_setup(pcd, &ctrl);
20076 +               return;
20077 +       }
20078 +
20079 +       /** @todo NGS: Handle bad setup packet? */
20080 +
20081 +///////////////////////////////////////////
20082 +//// --- Standard Request handling --- ////
20083 +
20084 +       switch (ctrl.bRequest) {
20085 +               case USB_REQ_GET_STATUS:
20086 +               do_get_status(pcd);
20087 +               break;
20088 +
20089 +       case USB_REQ_CLEAR_FEATURE:
20090 +               do_clear_feature(pcd);
20091 +               break;
20092 +
20093 +       case USB_REQ_SET_FEATURE:
20094 +               do_set_feature(pcd);
20095 +               break;
20096 +
20097 +       case USB_REQ_SET_ADDRESS:
20098 +               do_set_address(pcd);
20099 +               break;
20100 +
20101 +       case USB_REQ_SET_INTERFACE:
20102 +       case USB_REQ_SET_CONFIGURATION:
20103 +//             _pcd->request_config = 1;       /* Configuration changed */
20104 +               do_gadget_setup(pcd, &ctrl);
20105 +               break;
20106 +
20107 +       case USB_REQ_SYNCH_FRAME:
20108 +               do_gadget_setup(pcd, &ctrl);
20109 +               break;
20110 +
20111 +       default:
20112 +               /* Call the Gadget Driver's setup functions */
20113 +               do_gadget_setup(pcd, &ctrl);
20114 +               break;
20115 +       }
20116 +}
20117 +
20118 +/**
20119 + * This function completes the ep0 control transfer.
20120 + */
20121 +static int32_t ep0_complete_request(dwc_otg_pcd_ep_t *ep)
20122 +{
20123 +       dwc_otg_core_if_t *core_if = GET_CORE_IF(ep->pcd);
20124 +       dwc_otg_dev_if_t *dev_if = core_if->dev_if;
20125 +       dwc_otg_dev_in_ep_regs_t *in_ep_regs =
20126 +       dev_if->in_ep_regs[ep->dwc_ep.num];
20127 +#ifdef DEBUG_EP0
20128 +       dwc_otg_dev_out_ep_regs_t *out_ep_regs =
20129 +                       dev_if->out_ep_regs[ep->dwc_ep.num];
20130 +#endif
20131 +       deptsiz0_data_t deptsiz;
20132 +       desc_sts_data_t desc_sts;
20133 +       dwc_otg_pcd_request_t *req;
20134 +       int is_last = 0;
20135 +       dwc_otg_pcd_t *pcd = ep->pcd;
20136 +
20137 +       //DWC_DEBUGPL(DBG_PCDV, "%s() %s\n", __func__, _ep->ep.name);
20138 +
20139 +       if (pcd->ep0_pending && list_empty(&ep->queue)) {
20140 +               if (ep->dwc_ep.is_in) {
20141 +#ifdef DEBUG_EP0
20142 +                       DWC_DEBUGPL(DBG_PCDV, "Do setup OUT status phase\n");
20143 +#endif
20144 +                       do_setup_out_status_phase(pcd);
20145 +               }
20146 +               else {
20147 +#ifdef DEBUG_EP0
20148 +                       DWC_DEBUGPL(DBG_PCDV, "Do setup IN status phase\n");
20149 +#endif
20150 +                       do_setup_in_status_phase(pcd);
20151 +               }
20152 +               pcd->ep0_pending = 0;
20153 +               return 1;
20154 +       }
20155 +
20156 +       if (list_empty(&ep->queue)) {
20157 +               return 0;
20158 +       }
20159 +       req = list_entry(ep->queue.next, dwc_otg_pcd_request_t, queue);
20160 +
20161 +
20162 +       if (pcd->ep0state == EP0_OUT_STATUS_PHASE || pcd->ep0state == EP0_IN_STATUS_PHASE) {
20163 +               is_last = 1;
20164 +       }
20165 +       else if (ep->dwc_ep.is_in) {
20166 +               deptsiz.d32 = dwc_read_reg32(&in_ep_regs->dieptsiz);
20167 +               if(core_if->dma_desc_enable != 0)
20168 +                       desc_sts.d32 = readl(dev_if->in_desc_addr);
20169 +#ifdef DEBUG_EP0
20170 +               DWC_DEBUGPL(DBG_PCDV, "%s len=%d  xfersize=%d pktcnt=%d\n",
20171 +                               ep->ep.name, ep->dwc_ep.xfer_len,
20172 +                               deptsiz.b.xfersize, deptsiz.b.pktcnt);
20173 +#endif
20174 +
20175 +               if (((core_if->dma_desc_enable == 0) && (deptsiz.b.xfersize == 0)) ||
20176 +                       ((core_if->dma_desc_enable != 0) && (desc_sts.b.bytes == 0))) {
20177 +                       req->req.actual = ep->dwc_ep.xfer_count;
20178 +                       /* Is a Zero Len Packet needed? */
20179 +                       if (req->req.zero) {
20180 +#ifdef DEBUG_EP0
20181 +                               DWC_DEBUGPL(DBG_PCD, "Setup Rx ZLP\n");
20182 +#endif
20183 +                           req->req.zero = 0;
20184 +                       }
20185 +                       do_setup_out_status_phase(pcd);
20186 +               }
20187 +       }
20188 +       else {
20189 +               /* ep0-OUT */
20190 +#ifdef DEBUG_EP0
20191 +               deptsiz.d32 = dwc_read_reg32(&out_ep_regs->doeptsiz);
20192 +               DWC_DEBUGPL(DBG_PCDV, "%s len=%d xsize=%d pktcnt=%d\n",
20193 +                               ep->ep.name, ep->dwc_ep.xfer_len,
20194 +                               deptsiz.b.xfersize,
20195 +                               deptsiz.b.pktcnt);
20196 +#endif
20197 +               req->req.actual = ep->dwc_ep.xfer_count;
20198 +               /* Is a Zero Len Packet needed? */
20199 +               if (req->req.zero) {
20200 +#ifdef DEBUG_EP0
20201 +                       DWC_DEBUGPL(DBG_PCDV, "Setup Tx ZLP\n");
20202 +#endif
20203 +                       req->req.zero = 0;
20204 +               }
20205 +               if(core_if->dma_desc_enable == 0)
20206 +                       do_setup_in_status_phase(pcd);
20207 +       }
20208 +
20209 +       /* Complete the request */
20210 +       if (is_last) {
20211 +               dwc_otg_request_done(ep, req, 0);
20212 +               ep->dwc_ep.start_xfer_buff = 0;
20213 +               ep->dwc_ep.xfer_buff = 0;
20214 +               ep->dwc_ep.xfer_len = 0;
20215 +               return 1;
20216 +       }
20217 +       return 0;
20218 +}
20219 +
20220 +/**
20221 + * This function completes the request for the EP.     If there are
20222 + * additional requests for the EP in the queue they will be started.
20223 + */
20224 +static void complete_ep(dwc_otg_pcd_ep_t *ep)
20225 +{
20226 +       dwc_otg_core_if_t *core_if = GET_CORE_IF(ep->pcd);
20227 +       dwc_otg_dev_if_t *dev_if = core_if->dev_if;
20228 +       dwc_otg_dev_in_ep_regs_t *in_ep_regs =
20229 +       dev_if->in_ep_regs[ep->dwc_ep.num];
20230 +       deptsiz_data_t deptsiz;
20231 +       desc_sts_data_t desc_sts;
20232 +       dwc_otg_pcd_request_t *req = 0;
20233 +       dwc_otg_dma_desc_t* dma_desc;
20234 +       uint32_t byte_count = 0;
20235 +       int is_last = 0;
20236 +       int i;
20237 +
20238 +       DWC_DEBUGPL(DBG_PCDV,"%s() %s-%s\n", __func__, ep->ep.name,
20239 +                                       (ep->dwc_ep.is_in?"IN":"OUT"));
20240 +
20241 +       /* Get any pending requests */
20242 +       if (!list_empty(&ep->queue)) {
20243 +               req = list_entry(ep->queue.next, dwc_otg_pcd_request_t,
20244 +                                queue);
20245 +               if (!req) {
20246 +                       printk("complete_ep 0x%p, req = NULL!\n", ep);
20247 +                       return;
20248 +               }
20249 +       }
20250 +       else {
20251 +               printk("complete_ep 0x%p, ep->queue empty!\n", ep);
20252 +               return;
20253 +       }
20254 +       DWC_DEBUGPL(DBG_PCD, "Requests %d\n", ep->pcd->request_pending);
20255 +
20256 +       if (ep->dwc_ep.is_in) {
20257 +               deptsiz.d32 = dwc_read_reg32(&in_ep_regs->dieptsiz);
20258 +
20259 +               if (core_if->dma_enable) {
20260 +                       if(core_if->dma_desc_enable == 0) {
20261 +                               if (deptsiz.b.xfersize == 0 && deptsiz.b.pktcnt == 0) {
20262 +                                       byte_count = ep->dwc_ep.xfer_len - ep->dwc_ep.xfer_count;
20263 +
20264 +                                       ep->dwc_ep.xfer_buff += byte_count;
20265 +                                       ep->dwc_ep.dma_addr += byte_count;
20266 +                                       ep->dwc_ep.xfer_count += byte_count;
20267 +
20268 +                               DWC_DEBUGPL(DBG_PCDV, "%s len=%d  xfersize=%d pktcnt=%d\n",
20269 +                                               ep->ep.name, ep->dwc_ep.xfer_len,
20270 +                                               deptsiz.b.xfersize, deptsiz.b.pktcnt);
20271 +
20272 +
20273 +                                       if(ep->dwc_ep.xfer_len < ep->dwc_ep.total_len) {
20274 +                                               dwc_otg_ep_start_transfer(core_if, &ep->dwc_ep);
20275 +                                       } else if(ep->dwc_ep.sent_zlp) {
20276 +                                               /*
20277 +                                                * This fragment of code should initiate 0
20278 +                                                * length trasfer in case if it is queued
20279 +                                                * a trasfer with size divisible to EPs max
20280 +                                                * packet size and with usb_request zero field
20281 +                                                * is set, which means that after data is transfered,
20282 +                                                * it is also should be transfered
20283 +                                                * a 0 length packet at the end. For Slave and
20284 +                                                * Buffer DMA modes in this case SW has
20285 +                                                * to initiate 2 transfers one with transfer size,
20286 +                                                * and the second with 0 size. For Desriptor
20287 +                                                * DMA mode SW is able to initiate a transfer,
20288 +                                                * which will handle all the packets including
20289 +                                                * the last  0 legth.
20290 +                                                */
20291 +                                               ep->dwc_ep.sent_zlp = 0;
20292 +                                               dwc_otg_ep_start_zl_transfer(core_if, &ep->dwc_ep);
20293 +                                       } else {
20294 +                                               is_last = 1;
20295 +                                       }
20296 +                               } else {
20297 +                                       DWC_WARN("Incomplete transfer (%s-%s [siz=%d pkt=%d])\n",
20298 +                                                        ep->ep.name, (ep->dwc_ep.is_in?"IN":"OUT"),
20299 +                                                        deptsiz.b.xfersize, deptsiz.b.pktcnt);
20300 +                               }
20301 +                       } else {
20302 +                               dma_desc = ep->dwc_ep.desc_addr;
20303 +                               byte_count = 0;
20304 +                               ep->dwc_ep.sent_zlp = 0;
20305 +
20306 +                               for(i = 0; i < ep->dwc_ep.desc_cnt; ++i) {
20307 +                                       desc_sts.d32 = readl(dma_desc);
20308 +                                       byte_count += desc_sts.b.bytes;
20309 +                                       dma_desc++;
20310 +                               }
20311 +
20312 +                               if(byte_count == 0) {
20313 +                                       ep->dwc_ep.xfer_count = ep->dwc_ep.total_len;
20314 +                                       is_last = 1;
20315 +                               } else {
20316 +                                       DWC_WARN("Incomplete transfer\n");
20317 +                               }
20318 +                       }
20319 +               } else {
20320 +                       if (deptsiz.b.xfersize == 0 && deptsiz.b.pktcnt == 0) {
20321 +                               /*      Check if the whole transfer was completed,
20322 +                                *      if no, setup transfer for next portion of data
20323 +                                */
20324 +                       DWC_DEBUGPL(DBG_PCDV, "%s len=%d  xfersize=%d pktcnt=%d\n",
20325 +                                       ep->ep.name, ep->dwc_ep.xfer_len,
20326 +                                       deptsiz.b.xfersize, deptsiz.b.pktcnt);
20327 +                               if(ep->dwc_ep.xfer_len < ep->dwc_ep.total_len) {
20328 +                                       dwc_otg_ep_start_transfer(core_if, &ep->dwc_ep);
20329 +                               } else if(ep->dwc_ep.sent_zlp) {
20330 +                                       /*
20331 +                                        * This fragment of code should initiate 0
20332 +                                        * length trasfer in case if it is queued
20333 +                                        * a trasfer with size divisible to EPs max
20334 +                                        * packet size and with usb_request zero field
20335 +                                        * is set, which means that after data is transfered,
20336 +                                        * it is also should be transfered
20337 +                                        * a 0 length packet at the end. For Slave and
20338 +                                        * Buffer DMA modes in this case SW has
20339 +                                        * to initiate 2 transfers one with transfer size,
20340 +                                        * and the second with 0 size. For Desriptor
20341 +                                        * DMA mode SW is able to initiate a transfer,
20342 +                                        * which will handle all the packets including
20343 +                                        * the last  0 legth.
20344 +                                        */
20345 +                                       ep->dwc_ep.sent_zlp = 0;
20346 +                                       dwc_otg_ep_start_zl_transfer(core_if, &ep->dwc_ep);
20347 +                               } else {
20348 +                                       is_last = 1;
20349 +                               }
20350 +                       }
20351 +                       else {
20352 +                               DWC_WARN("Incomplete transfer (%s-%s [siz=%d pkt=%d])\n",
20353 +                                               ep->ep.name, (ep->dwc_ep.is_in?"IN":"OUT"),
20354 +                                               deptsiz.b.xfersize, deptsiz.b.pktcnt);
20355 +                       }
20356 +               }
20357 +       } else {
20358 +               dwc_otg_dev_out_ep_regs_t *out_ep_regs =
20359 +                               dev_if->out_ep_regs[ep->dwc_ep.num];
20360 +               desc_sts.d32 = 0;
20361 +               if(core_if->dma_enable) {
20362 +                       if(core_if->dma_desc_enable) {
20363 +                               dma_desc = ep->dwc_ep.desc_addr;
20364 +                               byte_count = 0;
20365 +                               ep->dwc_ep.sent_zlp = 0;
20366 +                               for(i = 0; i < ep->dwc_ep.desc_cnt; ++i) {
20367 +                                       desc_sts.d32 = readl(dma_desc);
20368 +                                       byte_count += desc_sts.b.bytes;
20369 +                                       dma_desc++;
20370 +                               }
20371 +
20372 +                               ep->dwc_ep.xfer_count = ep->dwc_ep.total_len
20373 +                                               - byte_count + ((4 - (ep->dwc_ep.total_len & 0x3)) & 0x3);
20374 +                               is_last = 1;
20375 +                       } else {
20376 +                               deptsiz.d32 = 0;
20377 +                               deptsiz.d32 = dwc_read_reg32(&out_ep_regs->doeptsiz);
20378 +
20379 +                               byte_count = (ep->dwc_ep.xfer_len -
20380 +                                                        ep->dwc_ep.xfer_count - deptsiz.b.xfersize);
20381 +                               ep->dwc_ep.xfer_buff += byte_count;
20382 +                               ep->dwc_ep.dma_addr += byte_count;
20383 +                               ep->dwc_ep.xfer_count += byte_count;
20384 +
20385 +                               /*      Check if the whole transfer was completed,
20386 +                                *      if no, setup transfer for next portion of data
20387 +                                */
20388 +                               if(ep->dwc_ep.xfer_len < ep->dwc_ep.total_len) {
20389 +                                       dwc_otg_ep_start_transfer(core_if, &ep->dwc_ep);
20390 +                               }
20391 +                               else if(ep->dwc_ep.sent_zlp) {
20392 +                                       /*
20393 +                                        * This fragment of code should initiate 0
20394 +                                        * length trasfer in case if it is queued
20395 +                                        * a trasfer with size divisible to EPs max
20396 +                                        * packet size and with usb_request zero field
20397 +                                        * is set, which means that after data is transfered,
20398 +                                        * it is also should be transfered
20399 +                                        * a 0 length packet at the end. For Slave and
20400 +                                        * Buffer DMA modes in this case SW has
20401 +                                        * to initiate 2 transfers one with transfer size,
20402 +                                        * and the second with 0 size. For Desriptor
20403 +                                        * DMA mode SW is able to initiate a transfer,
20404 +                                        * which will handle all the packets including
20405 +                                        * the last  0 legth.
20406 +                                        */
20407 +                                       ep->dwc_ep.sent_zlp = 0;
20408 +                                       dwc_otg_ep_start_zl_transfer(core_if, &ep->dwc_ep);
20409 +                               } else {
20410 +                                       is_last = 1;
20411 +                               }
20412 +                       }
20413 +               } else {
20414 +                       /*      Check if the whole transfer was completed,
20415 +                        *      if no, setup transfer for next portion of data
20416 +                        */
20417 +                       if(ep->dwc_ep.xfer_len < ep->dwc_ep.total_len) {
20418 +                               dwc_otg_ep_start_transfer(core_if, &ep->dwc_ep);
20419 +                       }
20420 +                       else if(ep->dwc_ep.sent_zlp) {
20421 +                               /*
20422 +                                * This fragment of code should initiate 0
20423 +                                * length trasfer in case if it is queued
20424 +                                * a trasfer with size divisible to EPs max
20425 +                                * packet size and with usb_request zero field
20426 +                                * is set, which means that after data is transfered,
20427 +                                * it is also should be transfered
20428 +                                * a 0 length packet at the end. For Slave and
20429 +                                * Buffer DMA modes in this case SW has
20430 +                                * to initiate 2 transfers one with transfer size,
20431 +                                * and the second with 0 size. For Desriptor
20432 +                                * DMA mode SW is able to initiate a transfer,
20433 +                                * which will handle all the packets including
20434 +                                * the last  0 legth.
20435 +                                */
20436 +                               ep->dwc_ep.sent_zlp = 0;
20437 +                               dwc_otg_ep_start_zl_transfer(core_if, &ep->dwc_ep);
20438 +                       } else {
20439 +                               is_last = 1;
20440 +                       }
20441 +               }
20442 +
20443 +#ifdef DEBUG
20444 +
20445 +               DWC_DEBUGPL(DBG_PCDV, "addr %p,  %s len=%d cnt=%d xsize=%d pktcnt=%d\n",
20446 +                               &out_ep_regs->doeptsiz, ep->ep.name, ep->dwc_ep.xfer_len,
20447 +                               ep->dwc_ep.xfer_count,
20448 +                               deptsiz.b.xfersize,
20449 +                               deptsiz.b.pktcnt);
20450 +#endif
20451 +       }
20452 +
20453 +       /* Complete the request */
20454 +       if (is_last) {
20455 +               req->req.actual = ep->dwc_ep.xfer_count;
20456 +
20457 +               dwc_otg_request_done(ep, req, 0);
20458 +
20459 +               ep->dwc_ep.start_xfer_buff = 0;
20460 +               ep->dwc_ep.xfer_buff = 0;
20461 +               ep->dwc_ep.xfer_len = 0;
20462 +
20463 +               /* If there is a request in the queue start it.*/
20464 +               start_next_request(ep);
20465 +       }
20466 +}
20467 +
20468 +
20469 +#ifdef DWC_EN_ISOC
20470 +
20471 +/**
20472 + * This function BNA interrupt for Isochronous EPs
20473 + *
20474 + */
20475 +static void dwc_otg_pcd_handle_iso_bna(dwc_otg_pcd_ep_t *ep)
20476 +{
20477 +       dwc_ep_t                *dwc_ep = &ep->dwc_ep;
20478 +       volatile uint32_t       *addr;
20479 +       depctl_data_t           depctl = {.d32 = 0};
20480 +       dwc_otg_pcd_t           *pcd = ep->pcd;
20481 +       dwc_otg_dma_desc_t      *dma_desc;
20482 +       int     i;
20483 +
20484 +       dma_desc = dwc_ep->iso_desc_addr + dwc_ep->desc_cnt * (dwc_ep->proc_buf_num);
20485 +
20486 +       if(dwc_ep->is_in) {
20487 +               desc_sts_data_t sts = {.d32 = 0};
20488 +               for(i = 0;i < dwc_ep->desc_cnt; ++i, ++dma_desc)
20489 +               {
20490 +                       sts.d32 = readl(&dma_desc->status);
20491 +                       sts.b_iso_in.bs = BS_HOST_READY;
20492 +                       writel(sts.d32,&dma_desc->status);
20493 +               }
20494 +       }
20495 +       else {
20496 +               desc_sts_data_t sts = {.d32 = 0};
20497 +               for(i = 0;i < dwc_ep->desc_cnt; ++i, ++dma_desc)
20498 +               {
20499 +                       sts.d32 = readl(&dma_desc->status);
20500 +                       sts.b_iso_out.bs = BS_HOST_READY;
20501 +                       writel(sts.d32,&dma_desc->status);
20502 +               }
20503 +       }
20504 +
20505 +       if(dwc_ep->is_in == 0){
20506 +               addr = &GET_CORE_IF(pcd)->dev_if->out_ep_regs[dwc_ep->num]->doepctl;
20507 +       }
20508 +       else{
20509 +               addr = &GET_CORE_IF(pcd)->dev_if->in_ep_regs[dwc_ep->num]->diepctl;
20510 +       }
20511 +       depctl.b.epena = 1;
20512 +       dwc_modify_reg32(addr,depctl.d32,depctl.d32);
20513 +}
20514 +
20515 +/**
20516 + * This function sets latest iso packet information(non-PTI mode)
20517 + *
20518 + * @param core_if Programming view of DWC_otg controller.
20519 + * @param ep The EP to start the transfer on.
20520 + *
20521 + */
20522 +void set_current_pkt_info(dwc_otg_core_if_t *core_if, dwc_ep_t *ep)
20523 +{
20524 +       deptsiz_data_t          deptsiz = { .d32 = 0 };
20525 +       dma_addr_t              dma_addr;
20526 +       uint32_t                offset;
20527 +
20528 +       if(ep->proc_buf_num)
20529 +               dma_addr = ep->dma_addr1;
20530 +       else
20531 +               dma_addr = ep->dma_addr0;
20532 +
20533 +
20534 +       if(ep->is_in) {
20535 +               deptsiz.d32 = dwc_read_reg32(&core_if->dev_if->in_ep_regs[ep->num]->dieptsiz);
20536 +               offset = ep->data_per_frame;
20537 +       } else {
20538 +               deptsiz.d32 = dwc_read_reg32(&core_if->dev_if->out_ep_regs[ep->num]->doeptsiz);
20539 +               offset = ep->data_per_frame + (0x4 & (0x4 - (ep->data_per_frame & 0x3)));
20540 +       }
20541 +
20542 +       if(!deptsiz.b.xfersize) {
20543 +               ep->pkt_info[ep->cur_pkt].length = ep->data_per_frame;
20544 +               ep->pkt_info[ep->cur_pkt].offset = ep->cur_pkt_dma_addr - dma_addr;
20545 +               ep->pkt_info[ep->cur_pkt].status = 0;
20546 +       } else {
20547 +               ep->pkt_info[ep->cur_pkt].length = ep->data_per_frame;
20548 +               ep->pkt_info[ep->cur_pkt].offset = ep->cur_pkt_dma_addr - dma_addr;
20549 +               ep->pkt_info[ep->cur_pkt].status = -ENODATA;
20550 +       }
20551 +       ep->cur_pkt_addr += offset;
20552 +       ep->cur_pkt_dma_addr += offset;
20553 +       ep->cur_pkt++;
20554 +}
20555 +
20556 +/**
20557 + * This function sets latest iso packet information(DDMA mode)
20558 + *
20559 + * @param core_if Programming view of DWC_otg controller.
20560 + * @param dwc_ep The EP to start the transfer on.
20561 + *
20562 + */
20563 +static void set_ddma_iso_pkts_info(dwc_otg_core_if_t *core_if, dwc_ep_t *dwc_ep)
20564 +{
20565 +       dwc_otg_dma_desc_t* dma_desc;
20566 +       desc_sts_data_t sts = {.d32 = 0};
20567 +       iso_pkt_info_t *iso_packet;
20568 +       uint32_t data_per_desc;
20569 +       uint32_t offset;
20570 +       int i, j;
20571 +
20572 +       iso_packet = dwc_ep->pkt_info;
20573 +
20574 +       /** Reinit closed DMA Descriptors*/
20575 +       /** ISO OUT EP */
20576 +       if(dwc_ep->is_in == 0) {
20577 +               dma_desc = dwc_ep->iso_desc_addr + dwc_ep->desc_cnt * dwc_ep->proc_buf_num;
20578 +               offset = 0;
20579 +
20580 +               for(i = 0; i < dwc_ep->desc_cnt - dwc_ep->pkt_per_frm; i+= dwc_ep->pkt_per_frm)
20581 +               {
20582 +                       for(j = 0; j < dwc_ep->pkt_per_frm; ++j)
20583 +                       {
20584 +                               data_per_desc = ((j + 1) * dwc_ep->maxpacket > dwc_ep->data_per_frame) ?
20585 +                                       dwc_ep->data_per_frame - j * dwc_ep->maxpacket : dwc_ep->maxpacket;
20586 +                               data_per_desc += (data_per_desc % 4) ? (4 - data_per_desc % 4):0;
20587 +
20588 +                               sts.d32 = readl(&dma_desc->status);
20589 +
20590 +                               /* Write status in iso_packet_decsriptor  */
20591 +                               iso_packet->status = sts.b_iso_out.rxsts + (sts.b_iso_out.bs^BS_DMA_DONE);
20592 +                               if(iso_packet->status) {
20593 +                                       iso_packet->status = -ENODATA;
20594 +                               }
20595 +
20596 +                               /* Received data length */
20597 +                               if(!sts.b_iso_out.rxbytes){
20598 +                                       iso_packet->length = data_per_desc - sts.b_iso_out.rxbytes;
20599 +                               } else {
20600 +                                       iso_packet->length = data_per_desc - sts.b_iso_out.rxbytes +
20601 +                                                               (4 - dwc_ep->data_per_frame % 4);
20602 +                               }
20603 +
20604 +                               iso_packet->offset = offset;
20605 +
20606 +                               offset += data_per_desc;
20607 +                               dma_desc ++;
20608 +                               iso_packet ++;
20609 +                       }
20610 +               }
20611 +
20612 +               for(j = 0; j < dwc_ep->pkt_per_frm - 1; ++j)
20613 +               {
20614 +                       data_per_desc = ((j + 1) * dwc_ep->maxpacket > dwc_ep->data_per_frame) ?
20615 +                               dwc_ep->data_per_frame - j * dwc_ep->maxpacket : dwc_ep->maxpacket;
20616 +                       data_per_desc += (data_per_desc % 4) ? (4 - data_per_desc % 4):0;
20617 +
20618 +                       sts.d32 = readl(&dma_desc->status);
20619 +
20620 +                       /* Write status in iso_packet_decsriptor  */
20621 +                       iso_packet->status = sts.b_iso_out.rxsts + (sts.b_iso_out.bs^BS_DMA_DONE);
20622 +                       if(iso_packet->status) {
20623 +                               iso_packet->status = -ENODATA;
20624 +                       }
20625 +
20626 +                       /* Received data length */
20627 +                       iso_packet->length = dwc_ep->data_per_frame - sts.b_iso_out.rxbytes;
20628 +
20629 +                       iso_packet->offset = offset;
20630 +
20631 +                       offset += data_per_desc;
20632 +                       iso_packet++;
20633 +                       dma_desc++;
20634 +               }
20635 +
20636 +               sts.d32 = readl(&dma_desc->status);
20637 +
20638 +               /* Write status in iso_packet_decsriptor  */
20639 +               iso_packet->status = sts.b_iso_out.rxsts + (sts.b_iso_out.bs^BS_DMA_DONE);
20640 +               if(iso_packet->status) {
20641 +                       iso_packet->status = -ENODATA;
20642 +               }
20643 +               /* Received data length */
20644 +               if(!sts.b_iso_out.rxbytes){
20645 +               iso_packet->length = dwc_ep->data_per_frame - sts.b_iso_out.rxbytes;
20646 +               } else {
20647 +                       iso_packet->length = dwc_ep->data_per_frame - sts.b_iso_out.rxbytes +
20648 +                                                       (4 - dwc_ep->data_per_frame % 4);
20649 +               }
20650 +
20651 +               iso_packet->offset = offset;
20652 +       }
20653 +       else /** ISO IN EP */
20654 +       {
20655 +               dma_desc = dwc_ep->iso_desc_addr + dwc_ep->desc_cnt * dwc_ep->proc_buf_num;
20656 +
20657 +               for(i = 0; i < dwc_ep->desc_cnt - 1; i++)
20658 +               {
20659 +                       sts.d32 = readl(&dma_desc->status);
20660 +
20661 +                       /* Write status in iso packet descriptor */
20662 +                       iso_packet->status = sts.b_iso_in.txsts + (sts.b_iso_in.bs^BS_DMA_DONE);
20663 +                       if(iso_packet->status != 0) {
20664 +                               iso_packet->status = -ENODATA;
20665 +
20666 +                       }
20667 +                       /* Bytes has been transfered */
20668 +                       iso_packet->length = dwc_ep->data_per_frame - sts.b_iso_in.txbytes;
20669 +
20670 +                       dma_desc ++;
20671 +                       iso_packet++;
20672 +               }
20673 +
20674 +               sts.d32 = readl(&dma_desc->status);
20675 +               while(sts.b_iso_in.bs == BS_DMA_BUSY) {
20676 +                       sts.d32 = readl(&dma_desc->status);
20677 +               }
20678 +
20679 +               /* Write status in iso packet descriptor ??? do be done with ERROR codes*/
20680 +               iso_packet->status = sts.b_iso_in.txsts + (sts.b_iso_in.bs^BS_DMA_DONE);
20681 +               if(iso_packet->status != 0) {
20682 +                       iso_packet->status = -ENODATA;
20683 +               }
20684 +
20685 +               /* Bytes has been transfered */
20686 +               iso_packet->length = dwc_ep->data_per_frame - sts.b_iso_in.txbytes;
20687 +       }
20688 +}
20689 +
20690 +/**
20691 + * This function reinitialize DMA Descriptors for Isochronous transfer
20692 + *
20693 + * @param core_if Programming view of DWC_otg controller.
20694 + * @param dwc_ep The EP to start the transfer on.
20695 + *
20696 + */
20697 +static void reinit_ddma_iso_xfer(dwc_otg_core_if_t *core_if, dwc_ep_t *dwc_ep)
20698 +{
20699 +       int i, j;
20700 +       dwc_otg_dma_desc_t* dma_desc;
20701 +       dma_addr_t dma_ad;
20702 +       volatile uint32_t       *addr;
20703 +       desc_sts_data_t sts = { .d32 =0 };
20704 +       uint32_t data_per_desc;
20705 +
20706 +       if(dwc_ep->is_in == 0) {
20707 +               addr = &core_if->dev_if->out_ep_regs[dwc_ep->num]->doepctl;
20708 +       }
20709 +       else {
20710 +               addr = &core_if->dev_if->in_ep_regs[dwc_ep->num]->diepctl;
20711 +       }
20712 +
20713 +
20714 +       if(dwc_ep->proc_buf_num == 0) {
20715 +               /** Buffer 0 descriptors setup */
20716 +               dma_ad = dwc_ep->dma_addr0;
20717 +       }
20718 +       else {
20719 +               /** Buffer 1 descriptors setup */
20720 +               dma_ad = dwc_ep->dma_addr1;
20721 +       }
20722 +
20723 +
20724 +       /** Reinit closed DMA Descriptors*/
20725 +       /** ISO OUT EP */
20726 +       if(dwc_ep->is_in == 0) {
20727 +               dma_desc = dwc_ep->iso_desc_addr + dwc_ep->desc_cnt * dwc_ep->proc_buf_num;
20728 +
20729 +               sts.b_iso_out.bs = BS_HOST_READY;
20730 +               sts.b_iso_out.rxsts = 0;
20731 +               sts.b_iso_out.l = 0;
20732 +               sts.b_iso_out.sp = 0;
20733 +               sts.b_iso_out.ioc = 0;
20734 +               sts.b_iso_out.pid = 0;
20735 +               sts.b_iso_out.framenum = 0;
20736 +
20737 +               for(i = 0; i < dwc_ep->desc_cnt - dwc_ep->pkt_per_frm; i+= dwc_ep->pkt_per_frm)
20738 +               {
20739 +                       for(j = 0; j < dwc_ep->pkt_per_frm; ++j)
20740 +                       {
20741 +                               data_per_desc = ((j + 1) * dwc_ep->maxpacket > dwc_ep->data_per_frame) ?
20742 +                                       dwc_ep->data_per_frame - j * dwc_ep->maxpacket : dwc_ep->maxpacket;
20743 +                               data_per_desc += (data_per_desc % 4) ? (4 - data_per_desc % 4):0;
20744 +                               sts.b_iso_out.rxbytes = data_per_desc;
20745 +                               writel((uint32_t)dma_ad, &dma_desc->buf);
20746 +                               writel(sts.d32, &dma_desc->status);
20747 +
20748 +                               (uint32_t)dma_ad += data_per_desc;
20749 +                               dma_desc ++;
20750 +                       }
20751 +               }
20752 +
20753 +               for(j = 0; j < dwc_ep->pkt_per_frm - 1; ++j)
20754 +               {
20755 +
20756 +                       data_per_desc = ((j + 1) * dwc_ep->maxpacket > dwc_ep->data_per_frame) ?
20757 +                               dwc_ep->data_per_frame - j * dwc_ep->maxpacket : dwc_ep->maxpacket;
20758 +                       data_per_desc += (data_per_desc % 4) ? (4 - data_per_desc % 4):0;
20759 +                       sts.b_iso_out.rxbytes = data_per_desc;
20760 +
20761 +                       writel((uint32_t)dma_ad, &dma_desc->buf);
20762 +                       writel(sts.d32, &dma_desc->status);
20763 +
20764 +                       dma_desc++;
20765 +                       (uint32_t)dma_ad += data_per_desc;
20766 +               }
20767 +
20768 +               sts.b_iso_out.ioc = 1;
20769 +               sts.b_iso_out.l = dwc_ep->proc_buf_num;
20770 +
20771 +               data_per_desc = ((j + 1) * dwc_ep->maxpacket > dwc_ep->data_per_frame) ?
20772 +                       dwc_ep->data_per_frame - j * dwc_ep->maxpacket : dwc_ep->maxpacket;
20773 +               data_per_desc += (data_per_desc % 4) ? (4 - data_per_desc % 4):0;
20774 +               sts.b_iso_out.rxbytes = data_per_desc;
20775 +
20776 +               writel((uint32_t)dma_ad, &dma_desc->buf);
20777 +               writel(sts.d32, &dma_desc->status);
20778 +       }
20779 +       else /** ISO IN EP */
20780 +       {
20781 +               dma_desc = dwc_ep->iso_desc_addr + dwc_ep->desc_cnt * dwc_ep->proc_buf_num;
20782 +
20783 +               sts.b_iso_in.bs = BS_HOST_READY;
20784 +               sts.b_iso_in.txsts = 0;
20785 +               sts.b_iso_in.sp = 0;
20786 +               sts.b_iso_in.ioc = 0;
20787 +               sts.b_iso_in.pid = dwc_ep->pkt_per_frm;
20788 +               sts.b_iso_in.framenum = dwc_ep->next_frame;
20789 +               sts.b_iso_in.txbytes = dwc_ep->data_per_frame;
20790 +               sts.b_iso_in.l = 0;
20791 +
20792 +               for(i = 0; i < dwc_ep->desc_cnt - 1; i++)
20793 +               {
20794 +                       writel((uint32_t)dma_ad, &dma_desc->buf);
20795 +                       writel(sts.d32, &dma_desc->status);
20796 +
20797 +                       sts.b_iso_in.framenum  += dwc_ep->bInterval;
20798 +                       (uint32_t)dma_ad += dwc_ep->data_per_frame;
20799 +                       dma_desc ++;
20800 +               }
20801 +
20802 +               sts.b_iso_in.ioc = 1;
20803 +               sts.b_iso_in.l = dwc_ep->proc_buf_num;
20804 +
20805 +               writel((uint32_t)dma_ad, &dma_desc->buf);
20806 +               writel(sts.d32, &dma_desc->status);
20807 +
20808 +               dwc_ep->next_frame = sts.b_iso_in.framenum + dwc_ep->bInterval * 1;
20809 +       }
20810 +       dwc_ep->proc_buf_num = (dwc_ep->proc_buf_num ^ 1) & 0x1;
20811 +}
20812 +
20813 +
20814 +/**
20815 + * This function is to handle Iso EP transfer complete interrupt
20816 + * in case Iso out packet was dropped
20817 + *
20818 + * @param core_if Programming view of DWC_otg controller.
20819 + * @param dwc_ep The EP for wihich transfer complete was asserted
20820 + *
20821 + */
20822 +static uint32_t handle_iso_out_pkt_dropped(dwc_otg_core_if_t *core_if, dwc_ep_t *dwc_ep)
20823 +{
20824 +       uint32_t dma_addr;
20825 +       uint32_t drp_pkt;
20826 +       uint32_t drp_pkt_cnt;
20827 +       deptsiz_data_t deptsiz = { .d32 = 0 };
20828 +       depctl_data_t depctl  = { .d32 = 0 };
20829 +       int i;
20830 +
20831 +       deptsiz.d32 = dwc_read_reg32(&core_if->dev_if->out_ep_regs[dwc_ep->num]->doeptsiz);
20832 +
20833 +       drp_pkt = dwc_ep->pkt_cnt - deptsiz.b.pktcnt;
20834 +       drp_pkt_cnt = dwc_ep->pkt_per_frm - (drp_pkt % dwc_ep->pkt_per_frm);
20835 +
20836 +       /* Setting dropped packets status */
20837 +       for(i = 0; i < drp_pkt_cnt; ++i) {
20838 +               dwc_ep->pkt_info[drp_pkt].status = -ENODATA;
20839 +               drp_pkt ++;
20840 +               deptsiz.b.pktcnt--;
20841 +       }
20842 +
20843 +
20844 +       if(deptsiz.b.pktcnt > 0) {
20845 +               deptsiz.b.xfersize = dwc_ep->xfer_len - (dwc_ep->pkt_cnt - deptsiz.b.pktcnt) * dwc_ep->maxpacket;
20846 +       } else {
20847 +               deptsiz.b.xfersize = 0;
20848 +               deptsiz.b.pktcnt = 0;
20849 +       }
20850 +
20851 +       dwc_write_reg32(&core_if->dev_if->out_ep_regs[dwc_ep->num]->doeptsiz, deptsiz.d32);
20852 +
20853 +       if(deptsiz.b.pktcnt > 0) {
20854 +               if(dwc_ep->proc_buf_num) {
20855 +                       dma_addr = dwc_ep->dma_addr1 + dwc_ep->xfer_len - deptsiz.b.xfersize;
20856 +               } else {
20857 +                       dma_addr = dwc_ep->dma_addr0 + dwc_ep->xfer_len - deptsiz.b.xfersize;;
20858 +               }
20859 +
20860 +               dwc_write_reg32(&core_if->dev_if->out_ep_regs[dwc_ep->num]->doepdma, dma_addr);
20861 +
20862 +               /** Re-enable endpoint, clear nak  */
20863 +               depctl.d32 = 0;
20864 +               depctl.b.epena = 1;
20865 +               depctl.b.cnak = 1;
20866 +
20867 +               dwc_modify_reg32(&core_if->dev_if->out_ep_regs[dwc_ep->num]->doepctl,
20868 +                               depctl.d32,depctl.d32);
20869 +               return 0;
20870 +       } else {
20871 +               return 1;
20872 +       }
20873 +}
20874 +
20875 +/**
20876 + * This function sets iso packets information(PTI mode)
20877 + *
20878 + * @param core_if Programming view of DWC_otg controller.
20879 + * @param ep The EP to start the transfer on.
20880 + *
20881 + */
20882 +static uint32_t set_iso_pkts_info(dwc_otg_core_if_t *core_if, dwc_ep_t *ep)
20883 +{
20884 +       int i, j;
20885 +       dma_addr_t dma_ad;
20886 +       iso_pkt_info_t *packet_info = ep->pkt_info;
20887 +       uint32_t offset;
20888 +       uint32_t frame_data;
20889 +       deptsiz_data_t deptsiz;
20890 +
20891 +       if(ep->proc_buf_num == 0) {
20892 +               /** Buffer 0 descriptors setup */
20893 +               dma_ad = ep->dma_addr0;
20894 +       }
20895 +       else {
20896 +               /** Buffer 1 descriptors setup */
20897 +               dma_ad = ep->dma_addr1;
20898 +       }
20899 +
20900 +
20901 +       if(ep->is_in) {
20902 +               deptsiz.d32 = dwc_read_reg32(&core_if->dev_if->in_ep_regs[ep->num]->dieptsiz);
20903 +       } else {
20904 +               deptsiz.d32 = dwc_read_reg32(&core_if->dev_if->out_ep_regs[ep->num]->doeptsiz);
20905 +       }
20906 +
20907 +       if(!deptsiz.b.xfersize) {
20908 +               offset = 0;
20909 +               for(i = 0; i < ep->pkt_cnt; i += ep->pkt_per_frm)
20910 +               {
20911 +                       frame_data = ep->data_per_frame;
20912 +                       for(j = 0; j < ep->pkt_per_frm; ++j) {
20913 +
20914 +                               /* Packet status - is not set as initially
20915 +                                * it is set to 0 and if packet was sent
20916 +                                successfully, status field will remain 0*/
20917 +
20918 +
20919 +                               /* Bytes has been transfered */
20920 +                               packet_info->length = (ep->maxpacket < frame_data) ?
20921 +                                                       ep->maxpacket : frame_data;
20922 +
20923 +                               /* Received packet offset */
20924 +                               packet_info->offset = offset;
20925 +                               offset += packet_info->length;
20926 +                               frame_data -= packet_info->length;
20927 +
20928 +                               packet_info ++;
20929 +                       }
20930 +               }
20931 +               return 1;
20932 +       } else {
20933 +               /* This is a workaround for in case of Transfer Complete with
20934 +                * PktDrpSts interrupts merging - in this case Transfer complete
20935 +                * interrupt for Isoc Out Endpoint is asserted without PktDrpSts
20936 +                * set and with DOEPTSIZ register non zero. Investigations showed,
20937 +                * that this happens when Out packet is dropped, but because of
20938 +                * interrupts merging during first interrupt handling PktDrpSts
20939 +                * bit is cleared and for next merged interrupts it is not reset.
20940 +                * In this case SW hadles the interrupt as if PktDrpSts bit is set.
20941 +                */
20942 +               if(ep->is_in) {
20943 +                       return 1;
20944 +               } else {
20945 +                       return handle_iso_out_pkt_dropped(core_if, ep);
20946 +               }
20947 +       }
20948 +}
20949 +
20950 +/**
20951 + * This function is to handle Iso EP transfer complete interrupt
20952 + *
20953 + * @param ep The EP for which transfer complete was asserted
20954 + *
20955 + */
20956 +static void complete_iso_ep(dwc_otg_pcd_ep_t *ep)
20957 +{
20958 +       dwc_otg_core_if_t *core_if = GET_CORE_IF(ep->pcd);
20959 +       dwc_ep_t *dwc_ep = &ep->dwc_ep;
20960 +       uint8_t is_last = 0;
20961 +
20962 +       if(core_if->dma_enable) {
20963 +               if(core_if->dma_desc_enable) {
20964 +                       set_ddma_iso_pkts_info(core_if, dwc_ep);
20965 +                       reinit_ddma_iso_xfer(core_if, dwc_ep);
20966 +                       is_last = 1;
20967 +               } else {
20968 +                       if(core_if->pti_enh_enable) {
20969 +                               if(set_iso_pkts_info(core_if, dwc_ep)) {
20970 +                                       dwc_ep->proc_buf_num = (dwc_ep->proc_buf_num ^ 1) & 0x1;
20971 +                                       dwc_otg_iso_ep_start_buf_transfer(core_if, dwc_ep);
20972 +                                       is_last = 1;
20973 +                               }
20974 +                       } else {
20975 +                               set_current_pkt_info(core_if, dwc_ep);
20976 +                               if(dwc_ep->cur_pkt >= dwc_ep->pkt_cnt) {
20977 +                                       is_last = 1;
20978 +                                       dwc_ep->cur_pkt = 0;
20979 +                                       dwc_ep->proc_buf_num = (dwc_ep->proc_buf_num ^ 1) & 0x1;
20980 +                                       if(dwc_ep->proc_buf_num) {
20981 +                                               dwc_ep->cur_pkt_addr = dwc_ep->xfer_buff1;
20982 +                                               dwc_ep->cur_pkt_dma_addr = dwc_ep->dma_addr1;
20983 +                                       } else {
20984 +                                               dwc_ep->cur_pkt_addr = dwc_ep->xfer_buff0;
20985 +                                               dwc_ep->cur_pkt_dma_addr = dwc_ep->dma_addr0;
20986 +                                       }
20987 +
20988 +                               }
20989 +                               dwc_otg_iso_ep_start_frm_transfer(core_if, dwc_ep);
20990 +                       }
20991 +               }
20992 +       } else {
20993 +               set_current_pkt_info(core_if, dwc_ep);
20994 +               if(dwc_ep->cur_pkt >= dwc_ep->pkt_cnt) {
20995 +                       is_last = 1;
20996 +                       dwc_ep->cur_pkt = 0;
20997 +                       dwc_ep->proc_buf_num = (dwc_ep->proc_buf_num ^ 1) & 0x1;
20998 +                       if(dwc_ep->proc_buf_num) {
20999 +                               dwc_ep->cur_pkt_addr = dwc_ep->xfer_buff1;
21000 +                               dwc_ep->cur_pkt_dma_addr = dwc_ep->dma_addr1;
21001 +                       } else {
21002 +                               dwc_ep->cur_pkt_addr = dwc_ep->xfer_buff0;
21003 +                               dwc_ep->cur_pkt_dma_addr = dwc_ep->dma_addr0;
21004 +                       }
21005 +
21006 +               }
21007 +               dwc_otg_iso_ep_start_frm_transfer(core_if, dwc_ep);
21008 +       }
21009 +       if(is_last)
21010 +               dwc_otg_iso_buffer_done(ep, ep->iso_req);
21011 +}
21012 +
21013 +#endif  //DWC_EN_ISOC
21014 +
21015 +
21016 +/**
21017 + * This function handles EP0 Control transfers.
21018 + *
21019 + * The state of the control tranfers are tracked in
21020 + * <code>ep0state</code>.
21021 + */
21022 +static void handle_ep0(dwc_otg_pcd_t *pcd)
21023 +{
21024 +       dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
21025 +       dwc_otg_pcd_ep_t *ep0 = &pcd->ep0;
21026 +       desc_sts_data_t desc_sts;
21027 +       deptsiz0_data_t deptsiz;
21028 +       uint32_t byte_count;
21029 +
21030 +#ifdef DEBUG_EP0
21031 +       DWC_DEBUGPL(DBG_PCDV, "%s()\n", __func__);
21032 +       print_ep0_state(pcd);
21033 +#endif
21034 +
21035 +       switch (pcd->ep0state) {
21036 +       case EP0_DISCONNECT:
21037 +               break;
21038 +
21039 +       case EP0_IDLE:
21040 +               pcd->request_config = 0;
21041 +
21042 +               pcd_setup(pcd);
21043 +               break;
21044 +
21045 +       case EP0_IN_DATA_PHASE:
21046 +#ifdef DEBUG_EP0
21047 +               DWC_DEBUGPL(DBG_PCD, "DATA_IN EP%d-%s: type=%d, mps=%d\n",
21048 +                               ep0->dwc_ep.num, (ep0->dwc_ep.is_in ?"IN":"OUT"),
21049 +                               ep0->dwc_ep.type, ep0->dwc_ep.maxpacket);
21050 +#endif
21051 +
21052 +               if (core_if->dma_enable != 0) {
21053 +                       /*
21054 +                        * For EP0 we can only program 1 packet at a time so we
21055 +                        * need to do the make calculations after each complete.
21056 +                        * Call write_packet to make the calculations, as in
21057 +                        * slave mode, and use those values to determine if we
21058 +                        * can complete.
21059 +                        */
21060 +                       if(core_if->dma_desc_enable == 0) {
21061 +                               deptsiz.d32 = dwc_read_reg32(&core_if->dev_if->in_ep_regs[0]->dieptsiz);
21062 +                               byte_count = ep0->dwc_ep.xfer_len - deptsiz.b.xfersize;
21063 +                       }
21064 +                       else {
21065 +                               desc_sts.d32 = readl(core_if->dev_if->in_desc_addr);
21066 +                               byte_count = ep0->dwc_ep.xfer_len - desc_sts.b.bytes;
21067 +                       }
21068 +                       ep0->dwc_ep.xfer_count += byte_count;
21069 +                       ep0->dwc_ep.xfer_buff += byte_count;
21070 +                       ep0->dwc_ep.dma_addr += byte_count;
21071 +               }
21072 +               if (ep0->dwc_ep.xfer_count < ep0->dwc_ep.total_len) {
21073 +                       dwc_otg_ep0_continue_transfer (GET_CORE_IF(pcd), &ep0->dwc_ep);
21074 +                       DWC_DEBUGPL(DBG_PCD, "CONTINUE TRANSFER\n");
21075 +               }
21076 +               else if(ep0->dwc_ep.sent_zlp) {
21077 +                       dwc_otg_ep0_continue_transfer (GET_CORE_IF(pcd), &ep0->dwc_ep);
21078 +                       ep0->dwc_ep.sent_zlp = 0;
21079 +                       DWC_DEBUGPL(DBG_PCD, "CONTINUE TRANSFER\n");
21080 +               }
21081 +               else {
21082 +                       ep0_complete_request(ep0);
21083 +                       DWC_DEBUGPL(DBG_PCD, "COMPLETE TRANSFER\n");
21084 +               }
21085 +               break;
21086 +       case EP0_OUT_DATA_PHASE:
21087 +#ifdef DEBUG_EP0
21088 +               DWC_DEBUGPL(DBG_PCD, "DATA_OUT EP%d-%s: type=%d, mps=%d\n",
21089 +                               ep0->dwc_ep.num, (ep0->dwc_ep.is_in ?"IN":"OUT"),
21090 +                               ep0->dwc_ep.type, ep0->dwc_ep.maxpacket);
21091 +#endif
21092 +               if (core_if->dma_enable != 0) {
21093 +                       if(core_if->dma_desc_enable == 0) {
21094 +                               deptsiz.d32 = dwc_read_reg32(&core_if->dev_if->out_ep_regs[0]->doeptsiz);
21095 +                               byte_count = ep0->dwc_ep.maxpacket - deptsiz.b.xfersize;
21096 +                       }
21097 +                       else {
21098 +                               desc_sts.d32 = readl(core_if->dev_if->out_desc_addr);
21099 +                               byte_count = ep0->dwc_ep.maxpacket - desc_sts.b.bytes;
21100 +                       }
21101 +                       ep0->dwc_ep.xfer_count += byte_count;
21102 +                       ep0->dwc_ep.xfer_buff += byte_count;
21103 +                       ep0->dwc_ep.dma_addr += byte_count;
21104 +               }
21105 +               if (ep0->dwc_ep.xfer_count < ep0->dwc_ep.total_len) {
21106 +                       dwc_otg_ep0_continue_transfer (GET_CORE_IF(pcd), &ep0->dwc_ep);
21107 +                       DWC_DEBUGPL(DBG_PCD, "CONTINUE TRANSFER\n");
21108 +               }
21109 +               else if(ep0->dwc_ep.sent_zlp) {
21110 +                       dwc_otg_ep0_continue_transfer (GET_CORE_IF(pcd), &ep0->dwc_ep);
21111 +                       ep0->dwc_ep.sent_zlp = 0;
21112 +                       DWC_DEBUGPL(DBG_PCD, "CONTINUE TRANSFER\n");
21113 +       }
21114 +               else {
21115 +                       ep0_complete_request(ep0);
21116 +                       DWC_DEBUGPL(DBG_PCD, "COMPLETE TRANSFER\n");
21117 +               }
21118 +               break;
21119 +
21120 +
21121 +       case EP0_IN_STATUS_PHASE:
21122 +       case EP0_OUT_STATUS_PHASE:
21123 +               DWC_DEBUGPL(DBG_PCD, "CASE: EP0_STATUS\n");
21124 +                               ep0_complete_request(ep0);
21125 +                               pcd->ep0state = EP0_IDLE;
21126 +                               ep0->stopped = 1;
21127 +                               ep0->dwc_ep.is_in = 0;  /* OUT for next SETUP */
21128 +
21129 +               /* Prepare for more SETUP Packets */
21130 +               if(core_if->dma_enable) {
21131 +                       ep0_out_start(core_if, pcd);
21132 +               }
21133 +               break;
21134 +
21135 +       case EP0_STALL:
21136 +               DWC_ERROR("EP0 STALLed, should not get here pcd_setup()\n");
21137 +               break;
21138 +       }
21139 +#ifdef DEBUG_EP0
21140 +       print_ep0_state(pcd);
21141 +#endif
21142 +}
21143 +
21144 +
21145 +/**
21146 + * Restart transfer
21147 + */
21148 +static void restart_transfer(dwc_otg_pcd_t *pcd, const uint32_t epnum)
21149 +{
21150 +       dwc_otg_core_if_t *core_if;
21151 +       dwc_otg_dev_if_t *dev_if;
21152 +       deptsiz_data_t dieptsiz = {.d32=0};
21153 +       dwc_otg_pcd_ep_t *ep;
21154 +
21155 +       ep = get_in_ep(pcd, epnum);
21156 +
21157 +#ifdef DWC_EN_ISOC
21158 +       if(ep->dwc_ep.type == DWC_OTG_EP_TYPE_ISOC) {
21159 +               return;
21160 +       }
21161 +#endif /* DWC_EN_ISOC  */
21162 +
21163 +       core_if = GET_CORE_IF(pcd);
21164 +       dev_if = core_if->dev_if;
21165 +
21166 +       dieptsiz.d32 = dwc_read_reg32(&dev_if->in_ep_regs[epnum]->dieptsiz);
21167 +
21168 +       DWC_DEBUGPL(DBG_PCD,"xfer_buff=%p xfer_count=%0x xfer_len=%0x"
21169 +                       " stopped=%d\n", ep->dwc_ep.xfer_buff,
21170 +                       ep->dwc_ep.xfer_count, ep->dwc_ep.xfer_len ,
21171 +                       ep->stopped);
21172 +       /*
21173 +        * If xfersize is 0 and pktcnt in not 0, resend the last packet.
21174 +        */
21175 +       if (dieptsiz.b.pktcnt && dieptsiz.b.xfersize == 0 &&
21176 +                ep->dwc_ep.start_xfer_buff != 0) {
21177 +               if (ep->dwc_ep.total_len <= ep->dwc_ep.maxpacket) {
21178 +                       ep->dwc_ep.xfer_count = 0;
21179 +                       ep->dwc_ep.xfer_buff = ep->dwc_ep.start_xfer_buff;
21180 +                       ep->dwc_ep.xfer_len = ep->dwc_ep.xfer_count;
21181 +               }
21182 +               else {
21183 +                       ep->dwc_ep.xfer_count -= ep->dwc_ep.maxpacket;
21184 +                       /* convert packet size to dwords. */
21185 +                       ep->dwc_ep.xfer_buff -= ep->dwc_ep.maxpacket;
21186 +                       ep->dwc_ep.xfer_len = ep->dwc_ep.xfer_count;
21187 +               }
21188 +               ep->stopped = 0;
21189 +               DWC_DEBUGPL(DBG_PCD,"xfer_buff=%p xfer_count=%0x "
21190 +                                       "xfer_len=%0x stopped=%d\n",
21191 +                                       ep->dwc_ep.xfer_buff,
21192 +                                       ep->dwc_ep.xfer_count, ep->dwc_ep.xfer_len ,
21193 +                                       ep->stopped
21194 +                                       );
21195 +               if (epnum == 0) {
21196 +                       dwc_otg_ep0_start_transfer(core_if, &ep->dwc_ep);
21197 +               }
21198 +               else {
21199 +                       dwc_otg_ep_start_transfer(core_if, &ep->dwc_ep);
21200 +               }
21201 +       }
21202 +}
21203 +
21204 +
21205 +/**
21206 + * handle the IN EP disable interrupt.
21207 + */
21208 +static inline void handle_in_ep_disable_intr(dwc_otg_pcd_t *pcd,
21209 +                                                const uint32_t epnum)
21210 +{
21211 +       dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
21212 +       dwc_otg_dev_if_t *dev_if = core_if->dev_if;
21213 +       deptsiz_data_t dieptsiz = {.d32=0};
21214 +       dctl_data_t dctl = {.d32=0};
21215 +       dwc_otg_pcd_ep_t *ep;
21216 +       dwc_ep_t *dwc_ep;
21217 +
21218 +       ep = get_in_ep(pcd, epnum);
21219 +       dwc_ep = &ep->dwc_ep;
21220 +
21221 +       if(dwc_ep->type == DWC_OTG_EP_TYPE_ISOC) {
21222 +               dwc_otg_flush_tx_fifo(core_if, dwc_ep->tx_fifo_num);
21223 +               return;
21224 +       }
21225 +
21226 +       DWC_DEBUGPL(DBG_PCD,"diepctl%d=%0x\n", epnum,
21227 +                       dwc_read_reg32(&dev_if->in_ep_regs[epnum]->diepctl));
21228 +       dieptsiz.d32 = dwc_read_reg32(&dev_if->in_ep_regs[epnum]->dieptsiz);
21229 +
21230 +       DWC_DEBUGPL(DBG_ANY, "pktcnt=%d size=%d\n",
21231 +                       dieptsiz.b.pktcnt,
21232 +                       dieptsiz.b.xfersize);
21233 +
21234 +       if (ep->stopped) {
21235 +               /* Flush the Tx FIFO */
21236 +               dwc_otg_flush_tx_fifo(core_if, dwc_ep->tx_fifo_num);
21237 +               /* Clear the Global IN NP NAK */
21238 +               dctl.d32 = 0;
21239 +               dctl.b.cgnpinnak = 1;
21240 +               dwc_modify_reg32(&dev_if->dev_global_regs->dctl,
21241 +                                        dctl.d32, 0);
21242 +               /* Restart the transaction */
21243 +               if (dieptsiz.b.pktcnt != 0 ||
21244 +                       dieptsiz.b.xfersize != 0) {
21245 +                       restart_transfer(pcd, epnum);
21246 +               }
21247 +       }
21248 +       else {
21249 +               /* Restart the transaction */
21250 +               if (dieptsiz.b.pktcnt != 0 ||
21251 +                       dieptsiz.b.xfersize != 0) {
21252 +                       restart_transfer(pcd, epnum);
21253 +               }
21254 +               DWC_DEBUGPL(DBG_ANY, "STOPPED!!!\n");
21255 +       }
21256 +}
21257 +
21258 +/**
21259 + * Handler for the IN EP timeout handshake interrupt.
21260 + */
21261 +static inline void handle_in_ep_timeout_intr(dwc_otg_pcd_t *pcd,
21262 +                                               const uint32_t epnum)
21263 +{
21264 +       dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
21265 +       dwc_otg_dev_if_t *dev_if = core_if->dev_if;
21266 +
21267 +#ifdef DEBUG
21268 +       deptsiz_data_t dieptsiz = {.d32=0};
21269 +       uint32_t num = 0;
21270 +#endif
21271 +       dctl_data_t dctl = {.d32=0};
21272 +       dwc_otg_pcd_ep_t *ep;
21273 +
21274 +       gintmsk_data_t intr_mask = {.d32 = 0};
21275 +
21276 +       ep = get_in_ep(pcd, epnum);
21277 +
21278 +       /* Disable the NP Tx Fifo Empty Interrrupt */
21279 +       if (!core_if->dma_enable) {
21280 +               intr_mask.b.nptxfempty = 1;
21281 +               dwc_modify_reg32(&core_if->core_global_regs->gintmsk, intr_mask.d32, 0);
21282 +       }
21283 +       /** @todo NGS Check EP type.
21284 +        * Implement for Periodic EPs */
21285 +       /*
21286 +        * Non-periodic EP
21287 +        */
21288 +       /* Enable the Global IN NAK Effective Interrupt */
21289 +       intr_mask.b.ginnakeff = 1;
21290 +       dwc_modify_reg32(&core_if->core_global_regs->gintmsk,
21291 +                                         0, intr_mask.d32);
21292 +
21293 +       /* Set Global IN NAK */
21294 +       dctl.b.sgnpinnak = 1;
21295 +       dwc_modify_reg32(&dev_if->dev_global_regs->dctl,
21296 +                                        dctl.d32, dctl.d32);
21297 +
21298 +       ep->stopped = 1;
21299 +
21300 +#ifdef DEBUG
21301 +       dieptsiz.d32 = dwc_read_reg32(&dev_if->in_ep_regs[num]->dieptsiz);
21302 +       DWC_DEBUGPL(DBG_ANY, "pktcnt=%d size=%d\n",
21303 +                       dieptsiz.b.pktcnt,
21304 +                       dieptsiz.b.xfersize);
21305 +#endif
21306 +
21307 +#ifdef DISABLE_PERIODIC_EP
21308 +       /*
21309 +        * Set the NAK bit for this EP to
21310 +        * start the disable process.
21311 +        */
21312 +       diepctl.d32 = 0;
21313 +       diepctl.b.snak = 1;
21314 +       dwc_modify_reg32(&dev_if->in_ep_regs[num]->diepctl, diepctl.d32, diepctl.d32);
21315 +       ep->disabling = 1;
21316 +       ep->stopped = 1;
21317 +#endif
21318 +}
21319 +
21320 +/**
21321 + * Handler for the IN EP NAK interrupt.
21322 + */
21323 +static inline int32_t handle_in_ep_nak_intr(dwc_otg_pcd_t *pcd,
21324 +                                               const uint32_t epnum)
21325 +{
21326 +        /** @todo implement ISR */
21327 +        dwc_otg_core_if_t* core_if;
21328 +       diepmsk_data_t intr_mask = { .d32 = 0};
21329 +
21330 +       DWC_PRINT("INTERRUPT Handler not implemented for %s\n", "IN EP NAK");
21331 +       core_if = GET_CORE_IF(pcd);
21332 +       intr_mask.b.nak = 1;
21333 +
21334 +       if(core_if->multiproc_int_enable) {
21335 +               dwc_modify_reg32(&core_if->dev_if->dev_global_regs->diepeachintmsk[epnum],
21336 +                                         intr_mask.d32, 0);
21337 +       } else {
21338 +               dwc_modify_reg32(&core_if->dev_if->dev_global_regs->diepmsk,
21339 +                                         intr_mask.d32, 0);
21340 +       }
21341 +
21342 +       return 1;
21343 +}
21344 +
21345 +/**
21346 + * Handler for the OUT EP Babble interrupt.
21347 + */
21348 +static inline int32_t handle_out_ep_babble_intr(dwc_otg_pcd_t *pcd,
21349 +                                               const uint32_t epnum)
21350 +{
21351 +        /** @todo implement ISR */
21352 +        dwc_otg_core_if_t* core_if;
21353 +       doepmsk_data_t intr_mask = { .d32 = 0};
21354 +
21355 +       DWC_PRINT("INTERRUPT Handler not implemented for %s\n", "OUT EP Babble");
21356 +       core_if = GET_CORE_IF(pcd);
21357 +       intr_mask.b.babble = 1;
21358 +
21359 +       if(core_if->multiproc_int_enable) {
21360 +               dwc_modify_reg32(&core_if->dev_if->dev_global_regs->doepeachintmsk[epnum],
21361 +                                         intr_mask.d32, 0);
21362 +       } else {
21363 +               dwc_modify_reg32(&core_if->dev_if->dev_global_regs->doepmsk,
21364 +                                         intr_mask.d32, 0);
21365 +       }
21366 +
21367 +       return 1;
21368 +}
21369 +
21370 +/**
21371 + * Handler for the OUT EP NAK interrupt.
21372 + */
21373 +static inline int32_t handle_out_ep_nak_intr(dwc_otg_pcd_t *pcd,
21374 +                                               const uint32_t epnum)
21375 +{
21376 +        /** @todo implement ISR */
21377 +        dwc_otg_core_if_t* core_if;
21378 +       doepmsk_data_t intr_mask = { .d32 = 0};
21379 +
21380 +       DWC_PRINT("INTERRUPT Handler not implemented for %s\n", "OUT EP NAK");
21381 +       core_if = GET_CORE_IF(pcd);
21382 +       intr_mask.b.nak = 1;
21383 +
21384 +       if(core_if->multiproc_int_enable) {
21385 +               dwc_modify_reg32(&core_if->dev_if->dev_global_regs->doepeachintmsk[epnum],
21386 +                                         intr_mask.d32, 0);
21387 +       } else {
21388 +               dwc_modify_reg32(&core_if->dev_if->dev_global_regs->doepmsk,
21389 +                                         intr_mask.d32, 0);
21390 +       }
21391 +
21392 +       return 1;
21393 +}
21394 +
21395 +/**
21396 + * Handler for the OUT EP NYET interrupt.
21397 + */
21398 +static inline int32_t handle_out_ep_nyet_intr(dwc_otg_pcd_t *pcd,
21399 +                                               const uint32_t epnum)
21400 +{
21401 +        /** @todo implement ISR */
21402 +        dwc_otg_core_if_t* core_if;
21403 +       doepmsk_data_t intr_mask = { .d32 = 0};
21404 +
21405 +       DWC_PRINT("INTERRUPT Handler not implemented for %s\n", "OUT EP NYET");
21406 +       core_if = GET_CORE_IF(pcd);
21407 +       intr_mask.b.nyet = 1;
21408 +
21409 +       if(core_if->multiproc_int_enable) {
21410 +               dwc_modify_reg32(&core_if->dev_if->dev_global_regs->doepeachintmsk[epnum],
21411 +                                         intr_mask.d32, 0);
21412 +       } else {
21413 +               dwc_modify_reg32(&core_if->dev_if->dev_global_regs->doepmsk,
21414 +                                         intr_mask.d32, 0);
21415 +       }
21416 +
21417 +       return 1;
21418 +}
21419 +
21420 +/**
21421 + * This interrupt indicates that an IN EP has a pending Interrupt.
21422 + * The sequence for handling the IN EP interrupt is shown below:
21423 + * -#  Read the Device All Endpoint Interrupt register
21424 + * -#  Repeat the following for each IN EP interrupt bit set (from
21425 + *             LSB to MSB).
21426 + * -#  Read the Device Endpoint Interrupt (DIEPINTn) register
21427 + * -#  If "Transfer Complete" call the request complete function
21428 + * -#  If "Endpoint Disabled" complete the EP disable procedure.
21429 + * -#  If "AHB Error Interrupt" log error
21430 + * -#  If "Time-out Handshake" log error
21431 + * -#  If "IN Token Received when TxFIFO Empty" write packet to Tx
21432 + *             FIFO.
21433 + * -#  If "IN Token EP Mismatch" (disable, this is handled by EP
21434 + *             Mismatch Interrupt)
21435 + */
21436 +static int32_t dwc_otg_pcd_handle_in_ep_intr(dwc_otg_pcd_t *pcd)
21437 +{
21438 +#define CLEAR_IN_EP_INTR(__core_if,__epnum,__intr) \
21439 +do { \
21440 +               diepint_data_t diepint = {.d32=0}; \
21441 +               diepint.b.__intr = 1; \
21442 +               dwc_write_reg32(&__core_if->dev_if->in_ep_regs[__epnum]->diepint, \
21443 +               diepint.d32); \
21444 +} while (0)
21445 +
21446 +       dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
21447 +       dwc_otg_dev_if_t *dev_if = core_if->dev_if;
21448 +       diepint_data_t diepint = {.d32=0};
21449 +       dctl_data_t dctl = {.d32=0};
21450 +       depctl_data_t depctl = {.d32=0};
21451 +       uint32_t ep_intr;
21452 +       uint32_t epnum = 0;
21453 +       dwc_otg_pcd_ep_t *ep;
21454 +       dwc_ep_t *dwc_ep;
21455 +       gintmsk_data_t intr_mask = {.d32 = 0};
21456 +
21457 +
21458 +
21459 +       DWC_DEBUGPL(DBG_PCDV, "%s(%p)\n", __func__, pcd);
21460 +
21461 +       /* Read in the device interrupt bits */
21462 +       ep_intr = dwc_otg_read_dev_all_in_ep_intr(core_if);
21463 +
21464 +       /* Service the Device IN interrupts for each endpoint */
21465 +       while(ep_intr) {
21466 +               if (ep_intr&0x1) {
21467 +                       uint32_t empty_msk;
21468 +                       /* Get EP pointer */
21469 +                       ep = get_in_ep(pcd, epnum);
21470 +                       dwc_ep = &ep->dwc_ep;
21471 +
21472 +                       depctl.d32 = dwc_read_reg32(&dev_if->in_ep_regs[epnum]->diepctl);
21473 +                       empty_msk = dwc_read_reg32(&dev_if->dev_global_regs->dtknqr4_fifoemptymsk);
21474 +
21475 +                       DWC_DEBUGPL(DBG_PCDV,
21476 +                                       "IN EP INTERRUPT - %d\nepmty_msk - %8x  diepctl - %8x\n",
21477 +                                       epnum,
21478 +                                       empty_msk,
21479 +                                       depctl.d32);
21480 +
21481 +                       DWC_DEBUGPL(DBG_PCD,
21482 +                                       "EP%d-%s: type=%d, mps=%d\n",
21483 +                                       dwc_ep->num, (dwc_ep->is_in ?"IN":"OUT"),
21484 +                                       dwc_ep->type, dwc_ep->maxpacket);
21485 +
21486 +                       diepint.d32 = dwc_otg_read_dev_in_ep_intr(core_if, dwc_ep);
21487 +
21488 +                       DWC_DEBUGPL(DBG_PCDV, "EP %d Interrupt Register - 0x%x\n", epnum, diepint.d32);
21489 +                       /* Transfer complete */
21490 +                       if (diepint.b.xfercompl) {
21491 +                               /* Disable the NP Tx FIFO Empty
21492 +                                * Interrrupt */
21493 +                                       if(core_if->en_multiple_tx_fifo == 0) {
21494 +                                       intr_mask.b.nptxfempty = 1;
21495 +                                       dwc_modify_reg32(&core_if->core_global_regs->gintmsk, intr_mask.d32, 0);
21496 +                               }
21497 +                               else {
21498 +                                       /* Disable the Tx FIFO Empty Interrupt for this EP */
21499 +                                       uint32_t fifoemptymsk = 0x1 << dwc_ep->num;
21500 +                                       dwc_modify_reg32(&core_if->dev_if->dev_global_regs->dtknqr4_fifoemptymsk,
21501 +                                       fifoemptymsk, 0);
21502 +                               }
21503 +                               /* Clear the bit in DIEPINTn for this interrupt */
21504 +                               CLEAR_IN_EP_INTR(core_if,epnum,xfercompl);
21505 +
21506 +                               /* Complete the transfer */
21507 +                               if (epnum == 0) {
21508 +                                       handle_ep0(pcd);
21509 +                               }
21510 +#ifdef DWC_EN_ISOC
21511 +                               else if(dwc_ep->type == DWC_OTG_EP_TYPE_ISOC) {
21512 +                                       if(!ep->stopped)
21513 +                                               complete_iso_ep(ep);
21514 +                               }
21515 +#endif //DWC_EN_ISOC
21516 +                               else {
21517 +
21518 +                                       complete_ep(ep);
21519 +                               }
21520 +                       }
21521 +                       /* Endpoint disable      */
21522 +                       if (diepint.b.epdisabled) {
21523 +                               DWC_DEBUGPL(DBG_ANY,"EP%d IN disabled\n", epnum);
21524 +                               handle_in_ep_disable_intr(pcd, epnum);
21525 +
21526 +                               /* Clear the bit in DIEPINTn for this interrupt */
21527 +                               CLEAR_IN_EP_INTR(core_if,epnum,epdisabled);
21528 +                       }
21529 +                       /* AHB Error */
21530 +                       if (diepint.b.ahberr) {
21531 +                               DWC_DEBUGPL(DBG_ANY,"EP%d IN AHB Error\n", epnum);
21532 +                               /* Clear the bit in DIEPINTn for this interrupt */
21533 +                               CLEAR_IN_EP_INTR(core_if,epnum,ahberr);
21534 +                       }
21535 +                       /* TimeOUT Handshake (non-ISOC IN EPs) */
21536 +                       if (diepint.b.timeout) {
21537 +                               DWC_DEBUGPL(DBG_ANY,"EP%d IN Time-out\n", epnum);
21538 +                               handle_in_ep_timeout_intr(pcd, epnum);
21539 +
21540 +                               CLEAR_IN_EP_INTR(core_if,epnum,timeout);
21541 +                       }
21542 +                       /** IN Token received with TxF Empty */
21543 +                       if (diepint.b.intktxfemp) {
21544 +                               DWC_DEBUGPL(DBG_ANY,"EP%d IN TKN TxFifo Empty\n",
21545 +                                                               epnum);
21546 +                               if (!ep->stopped && epnum != 0) {
21547 +
21548 +                                       diepmsk_data_t diepmsk = { .d32 = 0};
21549 +                                       diepmsk.b.intktxfemp = 1;
21550 +
21551 +                                       if(core_if->multiproc_int_enable) {
21552 +                                               dwc_modify_reg32(&dev_if->dev_global_regs->diepeachintmsk[epnum],
21553 +                                                       diepmsk.d32, 0);
21554 +                                       } else {
21555 +                                               dwc_modify_reg32(&dev_if->dev_global_regs->diepmsk, diepmsk.d32, 0);
21556 +                                       }
21557 +                                       start_next_request(ep);
21558 +                               }
21559 +                               else if(core_if->dma_desc_enable && epnum == 0 &&
21560 +                                               pcd->ep0state == EP0_OUT_STATUS_PHASE) {
21561 +                                       // EP0 IN set STALL
21562 +                                       depctl.d32 = dwc_read_reg32(&dev_if->in_ep_regs[epnum]->diepctl);
21563 +
21564 +                                       /* set the disable and stall bits */
21565 +                                       if (depctl.b.epena) {
21566 +                                               depctl.b.epdis = 1;
21567 +                                       }
21568 +                                       depctl.b.stall = 1;
21569 +                                       dwc_write_reg32(&dev_if->in_ep_regs[epnum]->diepctl, depctl.d32);
21570 +                               }
21571 +                               CLEAR_IN_EP_INTR(core_if,epnum,intktxfemp);
21572 +                       }
21573 +                       /** IN Token Received with EP mismatch */
21574 +                       if (diepint.b.intknepmis) {
21575 +                               DWC_DEBUGPL(DBG_ANY,"EP%d IN TKN EP Mismatch\n", epnum);
21576 +                               CLEAR_IN_EP_INTR(core_if,epnum,intknepmis);
21577 +                       }
21578 +                       /** IN Endpoint NAK Effective */
21579 +                       if (diepint.b.inepnakeff) {
21580 +                               DWC_DEBUGPL(DBG_ANY,"EP%d IN EP NAK Effective\n", epnum);
21581 +                               /* Periodic EP */
21582 +                               if (ep->disabling) {
21583 +                                       depctl.d32 = 0;
21584 +                                       depctl.b.snak = 1;
21585 +                                       depctl.b.epdis = 1;
21586 +                                       dwc_modify_reg32(&dev_if->in_ep_regs[epnum]->diepctl, depctl.d32, depctl.d32);
21587 +                               }
21588 +                               CLEAR_IN_EP_INTR(core_if,epnum,inepnakeff);
21589 +
21590 +                       }
21591 +
21592 +                       /** IN EP Tx FIFO Empty Intr */
21593 +                       if (diepint.b.emptyintr) {
21594 +                               DWC_DEBUGPL(DBG_ANY,"EP%d Tx FIFO Empty Intr \n", epnum);
21595 +                               write_empty_tx_fifo(pcd, epnum);
21596 +
21597 +                               CLEAR_IN_EP_INTR(core_if,epnum,emptyintr);
21598 +
21599 +                       }
21600 +
21601 +                       /** IN EP BNA Intr */
21602 +                       if (diepint.b.bna) {
21603 +                               CLEAR_IN_EP_INTR(core_if,epnum,bna);
21604 +                               if(core_if->dma_desc_enable) {
21605 +#ifdef DWC_EN_ISOC
21606 +                                       if(dwc_ep->type == DWC_OTG_EP_TYPE_ISOC) {
21607 +                                               /*
21608 +                                                * This checking is performed to prevent first "false" BNA
21609 +                                                * handling occuring right after reconnect
21610 +                                                */
21611 +                                               if(dwc_ep->next_frame != 0xffffffff)
21612 +                                                       dwc_otg_pcd_handle_iso_bna(ep);
21613 +                                       }
21614 +                                       else
21615 +#endif //DWC_EN_ISOC
21616 +                                       {
21617 +                                               dctl.d32 = dwc_read_reg32(&dev_if->dev_global_regs->dctl);
21618 +
21619 +                                               /* If Global Continue on BNA is disabled - disable EP */
21620 +                                               if(!dctl.b.gcontbna)                                            {
21621 +                                                       depctl.d32 = 0;
21622 +                                                       depctl.b.snak = 1;
21623 +                                                       depctl.b.epdis = 1;
21624 +                                                       dwc_modify_reg32(&dev_if->in_ep_regs[epnum]->diepctl, depctl.d32, depctl.d32);
21625 +                                               } else {
21626 +                                                       start_next_request(ep);
21627 +                                               }
21628 +                                       }
21629 +                               }
21630 +                       }
21631 +                       /* NAK Interrutp */
21632 +                       if (diepint.b.nak) {
21633 +                               DWC_DEBUGPL(DBG_ANY,"EP%d IN NAK Interrupt\n", epnum);
21634 +                               handle_in_ep_nak_intr(pcd, epnum);
21635 +
21636 +                               CLEAR_IN_EP_INTR(core_if,epnum,nak);
21637 +                       }
21638 +               }
21639 +               epnum++;
21640 +               ep_intr >>=1;
21641 +       }
21642 +
21643 +       return 1;
21644 +#undef CLEAR_IN_EP_INTR
21645 +}
21646 +
21647 +/**
21648 + * This interrupt indicates that an OUT EP has a pending Interrupt.
21649 + * The sequence for handling the OUT EP interrupt is shown below:
21650 + * -#  Read the Device All Endpoint Interrupt register
21651 + * -#  Repeat the following for each OUT EP interrupt bit set (from
21652 + *             LSB to MSB).
21653 + * -#  Read the Device Endpoint Interrupt (DOEPINTn) register
21654 + * -#  If "Transfer Complete" call the request complete function
21655 + * -#  If "Endpoint Disabled" complete the EP disable procedure.
21656 + * -#  If "AHB Error Interrupt" log error
21657 + * -#  If "Setup Phase Done" process Setup Packet (See Standard USB
21658 + *             Command Processing)
21659 + */
21660 +static int32_t dwc_otg_pcd_handle_out_ep_intr(dwc_otg_pcd_t *pcd)
21661 +{
21662 +#define CLEAR_OUT_EP_INTR(__core_if,__epnum,__intr) \
21663 +do { \
21664 +               doepint_data_t doepint = {.d32=0}; \
21665 +               doepint.b.__intr = 1; \
21666 +               dwc_write_reg32(&__core_if->dev_if->out_ep_regs[__epnum]->doepint, \
21667 +               doepint.d32); \
21668 +} while (0)
21669 +
21670 +       dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
21671 +       dwc_otg_dev_if_t *dev_if = core_if->dev_if;
21672 +       uint32_t ep_intr;
21673 +       doepint_data_t doepint = {.d32=0};
21674 +       dctl_data_t dctl = {.d32=0};
21675 +       depctl_data_t doepctl = {.d32=0};
21676 +       uint32_t epnum = 0;
21677 +       dwc_otg_pcd_ep_t *ep;
21678 +       dwc_ep_t *dwc_ep;
21679 +
21680 +       DWC_DEBUGPL(DBG_PCDV, "%s()\n", __func__);
21681 +
21682 +       /* Read in the device interrupt bits */
21683 +       ep_intr = dwc_otg_read_dev_all_out_ep_intr(core_if);
21684 +
21685 +       while(ep_intr) {
21686 +               if (ep_intr&0x1) {
21687 +                       /* Get EP pointer */
21688 +                       ep = get_out_ep(pcd, epnum);
21689 +                       dwc_ep = &ep->dwc_ep;
21690 +
21691 +#ifdef VERBOSE
21692 +                       DWC_DEBUGPL(DBG_PCDV,
21693 +                                       "EP%d-%s: type=%d, mps=%d\n",
21694 +                                       dwc_ep->num, (dwc_ep->is_in ?"IN":"OUT"),
21695 +                                       dwc_ep->type, dwc_ep->maxpacket);
21696 +#endif
21697 +                       doepint.d32 = dwc_otg_read_dev_out_ep_intr(core_if, dwc_ep);
21698 +
21699 +                       /* Transfer complete */
21700 +                       if (doepint.b.xfercompl) {
21701 +
21702 +                               if (epnum == 0) {
21703 +                                       /* Clear the bit in DOEPINTn for this interrupt */
21704 +                                       CLEAR_OUT_EP_INTR(core_if,epnum,xfercompl);
21705 +                                       if(core_if->dma_desc_enable == 0 || pcd->ep0state != EP0_IDLE)
21706 +                                               handle_ep0(pcd);
21707 +#ifdef DWC_EN_ISOC
21708 +                               } else if(dwc_ep->type == DWC_OTG_EP_TYPE_ISOC) {
21709 +                                       if (doepint.b.pktdrpsts == 0) {
21710 +                                               /* Clear the bit in DOEPINTn for this interrupt */
21711 +                                               CLEAR_OUT_EP_INTR(core_if,epnum,xfercompl);
21712 +                                               complete_iso_ep(ep);
21713 +                                       } else {
21714 +
21715 +                                               doepint_data_t doepint = {.d32=0};
21716 +                                               doepint.b.xfercompl = 1;
21717 +                                               doepint.b.pktdrpsts = 1;
21718 +                                               dwc_write_reg32(&core_if->dev_if->out_ep_regs[epnum]->doepint,
21719 +                                                       doepint.d32);
21720 +                                               if(handle_iso_out_pkt_dropped(core_if,dwc_ep)) {
21721 +                                                       complete_iso_ep(ep);
21722 +                                               }
21723 +                                       }
21724 +#endif //DWC_EN_ISOC
21725 +                               } else {
21726 +                                       /* Clear the bit in DOEPINTn for this interrupt */
21727 +                                       CLEAR_OUT_EP_INTR(core_if,epnum,xfercompl);
21728 +                                       complete_ep(ep);
21729 +                               }
21730 +
21731 +                       }
21732 +
21733 +                       /* Endpoint disable      */
21734 +                       if (doepint.b.epdisabled) {
21735 +
21736 +                               /* Clear the bit in DOEPINTn for this interrupt */
21737 +                               CLEAR_OUT_EP_INTR(core_if,epnum,epdisabled);
21738 +                       }
21739 +                       /* AHB Error */
21740 +                       if (doepint.b.ahberr) {
21741 +                               DWC_DEBUGPL(DBG_PCD,"EP%d OUT AHB Error\n", epnum);
21742 +                               DWC_DEBUGPL(DBG_PCD,"EP DMA REG  %d \n", core_if->dev_if->out_ep_regs[epnum]->doepdma);
21743 +                               CLEAR_OUT_EP_INTR(core_if,epnum,ahberr);
21744 +                       }
21745 +                       /* Setup Phase Done (contorl EPs) */
21746 +                       if (doepint.b.setup) {
21747 +#ifdef DEBUG_EP0
21748 +                               DWC_DEBUGPL(DBG_PCD,"EP%d SETUP Done\n",
21749 +                                                       epnum);
21750 +#endif
21751 +                               CLEAR_OUT_EP_INTR(core_if,epnum,setup);
21752 +
21753 +                               handle_ep0(pcd);
21754 +                       }
21755 +
21756 +                       /** OUT EP BNA Intr */
21757 +                       if (doepint.b.bna) {
21758 +                               CLEAR_OUT_EP_INTR(core_if,epnum,bna);
21759 +                               if(core_if->dma_desc_enable) {
21760 +#ifdef DWC_EN_ISOC
21761 +                                       if(dwc_ep->type == DWC_OTG_EP_TYPE_ISOC) {
21762 +                                               /*
21763 +                                                * This checking is performed to prevent first "false" BNA
21764 +                                                * handling occuring right after reconnect
21765 +                                                */
21766 +                                               if(dwc_ep->next_frame != 0xffffffff)
21767 +                                                       dwc_otg_pcd_handle_iso_bna(ep);
21768 +                                       }
21769 +                                       else
21770 +#endif //DWC_EN_ISOC
21771 +                                       {
21772 +                                               dctl.d32 = dwc_read_reg32(&dev_if->dev_global_regs->dctl);
21773 +
21774 +                                               /* If Global Continue on BNA is disabled - disable EP*/
21775 +                                               if(!dctl.b.gcontbna) {
21776 +                                                       doepctl.d32 = 0;
21777 +                                                       doepctl.b.snak = 1;
21778 +                                                       doepctl.b.epdis = 1;
21779 +                                                       dwc_modify_reg32(&dev_if->out_ep_regs[epnum]->doepctl, doepctl.d32, doepctl.d32);
21780 +                                               } else {
21781 +                                                       start_next_request(ep);
21782 +                                               }
21783 +                                       }
21784 +                               }
21785 +                       }
21786 +                       if (doepint.b.stsphsercvd) {
21787 +                               CLEAR_OUT_EP_INTR(core_if,epnum,stsphsercvd);
21788 +                               if(core_if->dma_desc_enable) {
21789 +                                       do_setup_in_status_phase(pcd);
21790 +                               }
21791 +                       }
21792 +                       /* Babble Interrutp */
21793 +                       if (doepint.b.babble) {
21794 +                               DWC_DEBUGPL(DBG_ANY,"EP%d OUT Babble\n", epnum);
21795 +                               handle_out_ep_babble_intr(pcd, epnum);
21796 +
21797 +                               CLEAR_OUT_EP_INTR(core_if,epnum,babble);
21798 +                       }
21799 +                       /* NAK Interrutp */
21800 +                       if (doepint.b.nak) {
21801 +                               DWC_DEBUGPL(DBG_ANY,"EP%d OUT NAK\n", epnum);
21802 +                               handle_out_ep_nak_intr(pcd, epnum);
21803 +
21804 +                               CLEAR_OUT_EP_INTR(core_if,epnum,nak);
21805 +                       }
21806 +                       /* NYET Interrutp */
21807 +                       if (doepint.b.nyet) {
21808 +                               DWC_DEBUGPL(DBG_ANY,"EP%d OUT NYET\n", epnum);
21809 +                               handle_out_ep_nyet_intr(pcd, epnum);
21810 +
21811 +                               CLEAR_OUT_EP_INTR(core_if,epnum,nyet);
21812 +                       }
21813 +               }
21814 +
21815 +               epnum++;
21816 +               ep_intr >>=1;
21817 +       }
21818 +
21819 +       return 1;
21820 +
21821 +#undef CLEAR_OUT_EP_INTR
21822 +}
21823 +
21824 +
21825 +/**
21826 + * Incomplete ISO IN Transfer Interrupt.
21827 + * This interrupt indicates one of the following conditions occurred
21828 + * while transmitting an ISOC transaction.
21829 + * - Corrupted IN Token for ISOC EP.
21830 + * - Packet not complete in FIFO.
21831 + * The follow actions will be taken:
21832 + *     -#      Determine the EP
21833 + *     -#      Set incomplete flag in dwc_ep structure
21834 + *     -#      Disable EP; when "Endpoint Disabled" interrupt is received
21835 + *             Flush FIFO
21836 + */
21837 +int32_t dwc_otg_pcd_handle_incomplete_isoc_in_intr(dwc_otg_pcd_t *pcd)
21838 +{
21839 +       gintsts_data_t          gintsts;
21840 +
21841 +
21842 +#ifdef DWC_EN_ISOC
21843 +       dwc_otg_dev_if_t        *dev_if;
21844 +       deptsiz_data_t          deptsiz = { .d32 = 0};
21845 +       depctl_data_t           depctl = { .d32 = 0};
21846 +       dsts_data_t             dsts = { .d32 = 0};
21847 +       dwc_ep_t                *dwc_ep;
21848 +       int i;
21849 +
21850 +       dev_if = GET_CORE_IF(pcd)->dev_if;
21851 +
21852 +       for(i = 1; i <= dev_if->num_in_eps; ++i) {
21853 +               dwc_ep = &pcd->in_ep[i].dwc_ep;
21854 +               if(dwc_ep->active &&
21855 +                       dwc_ep->type == USB_ENDPOINT_XFER_ISOC)
21856 +               {
21857 +                       deptsiz.d32 = dwc_read_reg32(&dev_if->in_ep_regs[i]->dieptsiz);
21858 +                       depctl.d32 = dwc_read_reg32(&dev_if->in_ep_regs[i]->diepctl);
21859 +
21860 +                       if(depctl.b.epdis && deptsiz.d32) {
21861 +                               set_current_pkt_info(GET_CORE_IF(pcd), dwc_ep);
21862 +                               if(dwc_ep->cur_pkt >= dwc_ep->pkt_cnt) {
21863 +                                       dwc_ep->cur_pkt = 0;
21864 +                                       dwc_ep->proc_buf_num = (dwc_ep->proc_buf_num ^ 1) & 0x1;
21865 +
21866 +                                       if(dwc_ep->proc_buf_num) {
21867 +                                               dwc_ep->cur_pkt_addr = dwc_ep->xfer_buff1;
21868 +                                               dwc_ep->cur_pkt_dma_addr = dwc_ep->dma_addr1;
21869 +                                       } else {
21870 +                                               dwc_ep->cur_pkt_addr = dwc_ep->xfer_buff0;
21871 +                                               dwc_ep->cur_pkt_dma_addr = dwc_ep->dma_addr0;
21872 +                                       }
21873 +
21874 +                               }
21875 +
21876 +                               dsts.d32 = dwc_read_reg32(&GET_CORE_IF(pcd)->dev_if->dev_global_regs->dsts);
21877 +                               dwc_ep->next_frame = dsts.b.soffn;
21878 +
21879 +                               dwc_otg_iso_ep_start_frm_transfer(GET_CORE_IF(pcd), dwc_ep);
21880 +                       }
21881 +               }
21882 +       }
21883 +
21884 +#else
21885 +        gintmsk_data_t intr_mask = { .d32 = 0};
21886 +        DWC_PRINT("INTERRUPT Handler not implemented for %s\n",
21887 +                          "IN ISOC Incomplete");
21888 +
21889 +        intr_mask.b.incomplisoin = 1;
21890 +        dwc_modify_reg32(&GET_CORE_IF(pcd)->core_global_regs->gintmsk,
21891 +                                intr_mask.d32, 0);
21892 +#endif //DWC_EN_ISOC
21893 +
21894 +       /* Clear interrupt */
21895 +       gintsts.d32 = 0;
21896 +       gintsts.b.incomplisoin = 1;
21897 +       dwc_write_reg32 (&GET_CORE_IF(pcd)->core_global_regs->gintsts,
21898 +                               gintsts.d32);
21899 +
21900 +       return 1;
21901 +}
21902 +
21903 +/**
21904 + * Incomplete ISO OUT Transfer Interrupt.
21905 + *
21906 + * This interrupt indicates that the core has dropped an ISO OUT
21907 + * packet.     The following conditions can be the cause:
21908 + * - FIFO Full, the entire packet would not fit in the FIFO.
21909 + * - CRC Error
21910 + * - Corrupted Token
21911 + * The follow actions will be taken:
21912 + *     -#      Determine the EP
21913 + *     -#      Set incomplete flag in dwc_ep structure
21914 + *     -#      Read any data from the FIFO
21915 + *     -#      Disable EP.      when "Endpoint Disabled" interrupt is received
21916 + *             re-enable EP.
21917 + */
21918 +int32_t dwc_otg_pcd_handle_incomplete_isoc_out_intr(dwc_otg_pcd_t *pcd)
21919 +{
21920 +       /* @todo implement ISR */
21921 +       gintsts_data_t gintsts;
21922 +
21923 +#ifdef DWC_EN_ISOC
21924 +       dwc_otg_dev_if_t        *dev_if;
21925 +       deptsiz_data_t          deptsiz = { .d32 = 0};
21926 +       depctl_data_t           depctl = { .d32 = 0};
21927 +       dsts_data_t             dsts = { .d32 = 0};
21928 +       dwc_ep_t                *dwc_ep;
21929 +       int i;
21930 +
21931 +       dev_if = GET_CORE_IF(pcd)->dev_if;
21932 +
21933 +       for(i = 1; i <= dev_if->num_out_eps; ++i) {
21934 +               dwc_ep = &pcd->in_ep[i].dwc_ep;
21935 +               if(pcd->out_ep[i].dwc_ep.active &&
21936 +                       pcd->out_ep[i].dwc_ep.type == USB_ENDPOINT_XFER_ISOC)
21937 +               {
21938 +                       deptsiz.d32 = dwc_read_reg32(&dev_if->out_ep_regs[i]->doeptsiz);
21939 +                       depctl.d32 = dwc_read_reg32(&dev_if->out_ep_regs[i]->doepctl);
21940 +
21941 +                       if(depctl.b.epdis && deptsiz.d32) {
21942 +                               set_current_pkt_info(GET_CORE_IF(pcd), &pcd->out_ep[i].dwc_ep);
21943 +                               if(dwc_ep->cur_pkt >= dwc_ep->pkt_cnt) {
21944 +                                       dwc_ep->cur_pkt = 0;
21945 +                                       dwc_ep->proc_buf_num = (dwc_ep->proc_buf_num ^ 1) & 0x1;
21946 +
21947 +                                       if(dwc_ep->proc_buf_num) {
21948 +                                               dwc_ep->cur_pkt_addr = dwc_ep->xfer_buff1;
21949 +                                               dwc_ep->cur_pkt_dma_addr = dwc_ep->dma_addr1;
21950 +                                       } else {
21951 +                                               dwc_ep->cur_pkt_addr = dwc_ep->xfer_buff0;
21952 +                                               dwc_ep->cur_pkt_dma_addr = dwc_ep->dma_addr0;
21953 +                                       }
21954 +
21955 +                               }
21956 +
21957 +                               dsts.d32 = dwc_read_reg32(&GET_CORE_IF(pcd)->dev_if->dev_global_regs->dsts);
21958 +                               dwc_ep->next_frame = dsts.b.soffn;
21959 +
21960 +                               dwc_otg_iso_ep_start_frm_transfer(GET_CORE_IF(pcd), dwc_ep);
21961 +                       }
21962 +               }
21963 +       }
21964 +#else
21965 +        /** @todo implement ISR */
21966 +        gintmsk_data_t intr_mask = { .d32 = 0};
21967 +
21968 +        DWC_PRINT("INTERRUPT Handler not implemented for %s\n",
21969 +                          "OUT ISOC Incomplete");
21970 +
21971 +        intr_mask.b.incomplisoout = 1;
21972 +        dwc_modify_reg32(&GET_CORE_IF(pcd)->core_global_regs->gintmsk,
21973 +                                intr_mask.d32, 0);
21974 +
21975 +#endif // DWC_EN_ISOC
21976 +
21977 +       /* Clear interrupt */
21978 +       gintsts.d32 = 0;
21979 +       gintsts.b.incomplisoout = 1;
21980 +       dwc_write_reg32 (&GET_CORE_IF(pcd)->core_global_regs->gintsts,
21981 +                               gintsts.d32);
21982 +
21983 +       return 1;
21984 +}
21985 +
21986 +/**
21987 + * This function handles the Global IN NAK Effective interrupt.
21988 + *
21989 + */
21990 +int32_t dwc_otg_pcd_handle_in_nak_effective(dwc_otg_pcd_t *pcd)
21991 +{
21992 +       dwc_otg_dev_if_t *dev_if = GET_CORE_IF(pcd)->dev_if;
21993 +       depctl_data_t diepctl = { .d32 = 0};
21994 +       depctl_data_t diepctl_rd = { .d32 = 0};
21995 +       gintmsk_data_t intr_mask = { .d32 = 0};
21996 +       gintsts_data_t gintsts;
21997 +       int i;
21998 +
21999 +       DWC_DEBUGPL(DBG_PCD, "Global IN NAK Effective\n");
22000 +
22001 +       /* Disable all active IN EPs */
22002 +       diepctl.b.epdis = 1;
22003 +       diepctl.b.snak = 1;
22004 +
22005 +       for (i=0; i <= dev_if->num_in_eps; i++)
22006 +       {
22007 +               diepctl_rd.d32 = dwc_read_reg32(&dev_if->in_ep_regs[i]->diepctl);
22008 +               if (diepctl_rd.b.epena) {
22009 +                       dwc_write_reg32(&dev_if->in_ep_regs[i]->diepctl,
22010 +                                               diepctl.d32);
22011 +               }
22012 +       }
22013 +       /* Disable the Global IN NAK Effective Interrupt */
22014 +       intr_mask.b.ginnakeff = 1;
22015 +       dwc_modify_reg32(&GET_CORE_IF(pcd)->core_global_regs->gintmsk,
22016 +                                         intr_mask.d32, 0);
22017 +
22018 +       /* Clear interrupt */
22019 +       gintsts.d32 = 0;
22020 +       gintsts.b.ginnakeff = 1;
22021 +       dwc_write_reg32(&GET_CORE_IF(pcd)->core_global_regs->gintsts,
22022 +                                                gintsts.d32);
22023 +
22024 +       return 1;
22025 +}
22026 +
22027 +/**
22028 + * OUT NAK Effective.
22029 + *
22030 + */
22031 +int32_t dwc_otg_pcd_handle_out_nak_effective(dwc_otg_pcd_t *pcd)
22032 +{
22033 +       gintmsk_data_t intr_mask = { .d32 = 0};
22034 +       gintsts_data_t gintsts;
22035 +
22036 +       DWC_PRINT("INTERRUPT Handler not implemented for %s\n",
22037 +                         "Global IN NAK Effective\n");
22038 +       /* Disable the Global IN NAK Effective Interrupt */
22039 +       intr_mask.b.goutnakeff = 1;
22040 +       dwc_modify_reg32(&GET_CORE_IF(pcd)->core_global_regs->gintmsk,
22041 +                                         intr_mask.d32, 0);
22042 +
22043 +       /* Clear interrupt */
22044 +       gintsts.d32 = 0;
22045 +       gintsts.b.goutnakeff = 1;
22046 +       dwc_write_reg32 (&GET_CORE_IF(pcd)->core_global_regs->gintsts,
22047 +                                                gintsts.d32);
22048 +
22049 +       return 1;
22050 +}
22051 +
22052 +
22053 +/**
22054 + * PCD interrupt handler.
22055 + *
22056 + * The PCD handles the device interrupts.  Many conditions can cause a
22057 + * device interrupt. When an interrupt occurs, the device interrupt
22058 + * service routine determines the cause of the interrupt and
22059 + * dispatches handling to the appropriate function. These interrupt
22060 + * handling functions are described below.
22061 + *
22062 + * All interrupt registers are processed from LSB to MSB.
22063 + *
22064 + */
22065 +int32_t dwc_otg_pcd_handle_intr(dwc_otg_pcd_t *pcd)
22066 +{
22067 +       dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
22068 +#ifdef VERBOSE
22069 +       dwc_otg_core_global_regs_t *global_regs =
22070 +                       core_if->core_global_regs;
22071 +#endif
22072 +       gintsts_data_t gintr_status;
22073 +       int32_t retval = 0;
22074 +
22075 +
22076 +#ifdef VERBOSE
22077 +       DWC_DEBUGPL(DBG_ANY, "%s() gintsts=%08x  gintmsk=%08x\n",
22078 +                               __func__,
22079 +                               dwc_read_reg32(&global_regs->gintsts),
22080 +                               dwc_read_reg32(&global_regs->gintmsk));
22081 +#endif
22082 +
22083 +       if (dwc_otg_is_device_mode(core_if)) {
22084 +               SPIN_LOCK(&pcd->lock);
22085 +#ifdef VERBOSE
22086 +               DWC_DEBUGPL(DBG_PCDV, "%s() gintsts=%08x  gintmsk=%08x\n",
22087 +                                               __func__,
22088 +                                               dwc_read_reg32(&global_regs->gintsts),
22089 +                                               dwc_read_reg32(&global_regs->gintmsk));
22090 +#endif
22091 +
22092 +               gintr_status.d32 = dwc_otg_read_core_intr(core_if);
22093 +
22094 +/*
22095 +               if (!gintr_status.d32) {
22096 +                       SPIN_UNLOCK(&pcd->lock);
22097 +                       return 0;
22098 +               }
22099 +*/
22100 +               DWC_DEBUGPL(DBG_PCDV, "%s: gintsts&gintmsk=%08x\n",
22101 +                                       __func__, gintr_status.d32);
22102 +
22103 +               if (gintr_status.b.sofintr) {
22104 +                       retval |= dwc_otg_pcd_handle_sof_intr(pcd);
22105 +               }
22106 +               if (gintr_status.b.rxstsqlvl) {
22107 +                       retval |= dwc_otg_pcd_handle_rx_status_q_level_intr(pcd);
22108 +               }
22109 +               if (gintr_status.b.nptxfempty) {
22110 +                       retval |= dwc_otg_pcd_handle_np_tx_fifo_empty_intr(pcd);
22111 +               }
22112 +               if (gintr_status.b.ginnakeff) {
22113 +                       retval |= dwc_otg_pcd_handle_in_nak_effective(pcd);
22114 +               }
22115 +               if (gintr_status.b.goutnakeff) {
22116 +                       retval |= dwc_otg_pcd_handle_out_nak_effective(pcd);
22117 +               }
22118 +               if (gintr_status.b.i2cintr) {
22119 +                       retval |= dwc_otg_pcd_handle_i2c_intr(pcd);
22120 +               }
22121 +               if (gintr_status.b.erlysuspend) {
22122 +                       retval |= dwc_otg_pcd_handle_early_suspend_intr(pcd);
22123 +               }
22124 +               if (gintr_status.b.usbreset) {
22125 +                       retval |= dwc_otg_pcd_handle_usb_reset_intr(pcd);
22126 +               }
22127 +               if (gintr_status.b.enumdone) {
22128 +                       retval |= dwc_otg_pcd_handle_enum_done_intr(pcd);
22129 +               }
22130 +               if (gintr_status.b.isooutdrop) {
22131 +                       retval |= dwc_otg_pcd_handle_isoc_out_packet_dropped_intr(pcd);
22132 +               }
22133 +               if (gintr_status.b.eopframe) {
22134 +                       retval |= dwc_otg_pcd_handle_end_periodic_frame_intr(pcd);
22135 +               }
22136 +               if (gintr_status.b.epmismatch) {
22137 +                       retval |= dwc_otg_pcd_handle_ep_mismatch_intr(core_if);
22138 +               }
22139 +               if (gintr_status.b.inepint) {
22140 +                       if(!core_if->multiproc_int_enable) {
22141 +                               retval |= dwc_otg_pcd_handle_in_ep_intr(pcd);
22142 +                       }
22143 +               }
22144 +               if (gintr_status.b.outepintr) {
22145 +                       if(!core_if->multiproc_int_enable) {
22146 +                               retval |= dwc_otg_pcd_handle_out_ep_intr(pcd);
22147 +                       }
22148 +               }
22149 +               if (gintr_status.b.incomplisoin) {
22150 +                       retval |= dwc_otg_pcd_handle_incomplete_isoc_in_intr(pcd);
22151 +               }
22152 +               if (gintr_status.b.incomplisoout) {
22153 +                       retval |= dwc_otg_pcd_handle_incomplete_isoc_out_intr(pcd);
22154 +               }
22155 +
22156 +               /* In MPI mode De vice Endpoints intterrupts are asserted
22157 +                * without setting outepintr and inepint bits set, so these
22158 +                * Interrupt handlers are called without checking these bit-fields
22159 +                */
22160 +               if(core_if->multiproc_int_enable) {
22161 +                       retval |= dwc_otg_pcd_handle_in_ep_intr(pcd);
22162 +                       retval |= dwc_otg_pcd_handle_out_ep_intr(pcd);
22163 +               }
22164 +#ifdef VERBOSE
22165 +               DWC_DEBUGPL(DBG_PCDV, "%s() gintsts=%0x\n", __func__,
22166 +                                               dwc_read_reg32(&global_regs->gintsts));
22167 +#endif
22168 +               SPIN_UNLOCK(&pcd->lock);
22169 +       }
22170 +
22171 +       S3C2410X_CLEAR_EINTPEND();
22172 +
22173 +       return retval;
22174 +}
22175 +
22176 +#endif /* DWC_HOST_ONLY */
22177 --- /dev/null
22178 +++ b/drivers/usb/dwc_otg/dwc_otg_regs.h
22179 @@ -0,0 +1,2075 @@
22180 +/* ==========================================================================
22181 + * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_regs.h $
22182 + * $Revision: 1.2 $
22183 + * $Date: 2008-11-21 05:39:15 $
22184 + * $Change: 1099526 $
22185 + *
22186 + * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
22187 + * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
22188 + * otherwise expressly agreed to in writing between Synopsys and you.
22189 + *
22190 + * The Software IS NOT an item of Licensed Software or Licensed Product under
22191 + * any End User Software License Agreement or Agreement for Licensed Product
22192 + * with Synopsys or any supplement thereto. You are permitted to use and
22193 + * redistribute this Software in source and binary forms, with or without
22194 + * modification, provided that redistributions of source code must retain this
22195 + * notice. You may not view, use, disclose, copy or distribute this file or
22196 + * any information contained herein except pursuant to this license grant from
22197 + * Synopsys. If you do not agree with this notice, including the disclaimer
22198 + * below, then you are not authorized to use the Software.
22199 + *
22200 + * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
22201 + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22202 + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22203 + * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
22204 + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
22205 + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
22206 + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
22207 + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22208 + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
22209 + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
22210 + * DAMAGE.
22211 + * ========================================================================== */
22212 +
22213 +#ifndef __DWC_OTG_REGS_H__
22214 +#define __DWC_OTG_REGS_H__
22215 +
22216 +/**
22217 + * @file
22218 + *
22219 + * This file contains the data structures for accessing the DWC_otg core registers.
22220 + *
22221 + * The application interfaces with the HS OTG core by reading from and
22222 + * writing to the Control and Status Register (CSR) space through the
22223 + * AHB Slave interface. These registers are 32 bits wide, and the
22224 + * addresses are 32-bit-block aligned.
22225 + * CSRs are classified as follows:
22226 + * - Core Global Registers
22227 + * - Device Mode Registers
22228 + * - Device Global Registers
22229 + * - Device Endpoint Specific Registers
22230 + * - Host Mode Registers
22231 + * - Host Global Registers
22232 + * - Host Port CSRs
22233 + * - Host Channel Specific Registers
22234 + *
22235 + * Only the Core Global registers can be accessed in both Device and
22236 + * Host modes. When the HS OTG core is operating in one mode, either
22237 + * Device or Host, the application must not access registers from the
22238 + * other mode. When the core switches from one mode to another, the
22239 + * registers in the new mode of operation must be reprogrammed as they
22240 + * would be after a power-on reset.
22241 + */
22242 +
22243 +/** Maximum number of Periodic FIFOs */
22244 +#define MAX_PERIO_FIFOS 15
22245 +/** Maximum number of Transmit FIFOs */
22246 +#define MAX_TX_FIFOS 15
22247 +
22248 +/** Maximum number of Endpoints/HostChannels */
22249 +#define MAX_EPS_CHANNELS 16
22250 +
22251 +/****************************************************************************/
22252 +/** DWC_otg Core registers .
22253 + * The dwc_otg_core_global_regs structure defines the size
22254 + * and relative field offsets for the Core Global registers.
22255 + */
22256 +typedef struct dwc_otg_core_global_regs
22257 +{
22258 +       /** OTG Control and Status Register.  <i>Offset: 000h</i> */
22259 +       volatile uint32_t gotgctl;
22260 +       /** OTG Interrupt Register.      <i>Offset: 004h</i> */
22261 +       volatile uint32_t gotgint;
22262 +       /**Core AHB Configuration Register.      <i>Offset: 008h</i> */
22263 +       volatile uint32_t gahbcfg;
22264 +
22265 +#define DWC_GLBINTRMASK                0x0001
22266 +#define DWC_DMAENABLE          0x0020
22267 +#define DWC_NPTXEMPTYLVL_EMPTY 0x0080
22268 +#define DWC_NPTXEMPTYLVL_HALFEMPTY     0x0000
22269 +#define DWC_PTXEMPTYLVL_EMPTY  0x0100
22270 +#define DWC_PTXEMPTYLVL_HALFEMPTY      0x0000
22271 +
22272 +       /**Core USB Configuration Register.      <i>Offset: 00Ch</i> */
22273 +       volatile uint32_t gusbcfg;
22274 +       /**Core Reset Register.  <i>Offset: 010h</i> */
22275 +       volatile uint32_t grstctl;
22276 +       /**Core Interrupt Register.      <i>Offset: 014h</i> */
22277 +       volatile uint32_t gintsts;
22278 +       /**Core Interrupt Mask Register.  <i>Offset: 018h</i> */
22279 +       volatile uint32_t gintmsk;
22280 +       /**Receive Status Queue Read Register (Read Only).      <i>Offset: 01Ch</i> */
22281 +       volatile uint32_t grxstsr;
22282 +       /**Receive Status Queue Read & POP Register (Read Only).  <i>Offset: 020h</i>*/
22283 +       volatile uint32_t grxstsp;
22284 +       /**Receive FIFO Size Register.  <i>Offset: 024h</i> */
22285 +       volatile uint32_t grxfsiz;
22286 +       /**Non Periodic Transmit FIFO Size Register.  <i>Offset: 028h</i> */
22287 +       volatile uint32_t gnptxfsiz;
22288 +       /**Non Periodic Transmit FIFO/Queue Status Register (Read
22289 +        * Only). <i>Offset: 02Ch</i> */
22290 +       volatile uint32_t gnptxsts;
22291 +       /**I2C Access Register.  <i>Offset: 030h</i> */
22292 +       volatile uint32_t gi2cctl;
22293 +       /**PHY Vendor Control Register.  <i>Offset: 034h</i> */
22294 +       volatile uint32_t gpvndctl;
22295 +       /**General Purpose Input/Output Register.  <i>Offset: 038h</i> */
22296 +       volatile uint32_t ggpio;
22297 +       /**User ID Register.  <i>Offset: 03Ch</i> */
22298 +       volatile uint32_t guid;
22299 +       /**Synopsys ID Register (Read Only).  <i>Offset: 040h</i> */
22300 +       volatile uint32_t gsnpsid;
22301 +       /**User HW Config1 Register (Read Only).  <i>Offset: 044h</i> */
22302 +       volatile uint32_t ghwcfg1;
22303 +       /**User HW Config2 Register (Read Only).  <i>Offset: 048h</i> */
22304 +       volatile uint32_t ghwcfg2;
22305 +#define DWC_SLAVE_ONLY_ARCH 0
22306 +#define DWC_EXT_DMA_ARCH 1
22307 +#define DWC_INT_DMA_ARCH 2
22308 +
22309 +#define DWC_MODE_HNP_SRP_CAPABLE       0
22310 +#define DWC_MODE_SRP_ONLY_CAPABLE      1
22311 +#define DWC_MODE_NO_HNP_SRP_CAPABLE            2
22312 +#define DWC_MODE_SRP_CAPABLE_DEVICE            3
22313 +#define DWC_MODE_NO_SRP_CAPABLE_DEVICE 4
22314 +#define DWC_MODE_SRP_CAPABLE_HOST      5
22315 +#define DWC_MODE_NO_SRP_CAPABLE_HOST   6
22316 +
22317 +       /**User HW Config3 Register (Read Only).  <i>Offset: 04Ch</i> */
22318 +       volatile uint32_t ghwcfg3;
22319 +       /**User HW Config4 Register (Read Only).  <i>Offset: 050h</i>*/
22320 +       volatile uint32_t ghwcfg4;
22321 +       /** Reserved  <i>Offset: 054h-0FFh</i> */
22322 +       volatile uint32_t reserved[43];
22323 +       /** Host Periodic Transmit FIFO Size Register. <i>Offset: 100h</i> */
22324 +       volatile uint32_t hptxfsiz;
22325 +       /** Device Periodic Transmit FIFO#n Register if dedicated fifos are disabled,
22326 +               otherwise Device Transmit FIFO#n Register.
22327 +        * <i>Offset: 104h + (FIFO_Number-1)*04h, 1 <= FIFO Number <= 15 (1<=n<=15).</i> */
22328 +       volatile uint32_t dptxfsiz_dieptxf[15];
22329 +} dwc_otg_core_global_regs_t;
22330 +
22331 +/**
22332 + * This union represents the bit fields of the Core OTG Control
22333 + * and Status Register (GOTGCTL).  Set the bits using the bit
22334 + * fields then write the <i>d32</i> value to the register.
22335 + */
22336 +typedef union gotgctl_data
22337 +{
22338 +       /** raw register data */
22339 +       uint32_t d32;
22340 +       /** register bits */
22341 +       struct
22342 +       {
22343 +               unsigned sesreqscs : 1;
22344 +               unsigned sesreq : 1;
22345 +               unsigned reserved2_7 : 6;
22346 +               unsigned hstnegscs : 1;
22347 +               unsigned hnpreq : 1;
22348 +               unsigned hstsethnpen : 1;
22349 +               unsigned devhnpen : 1;
22350 +               unsigned reserved12_15 : 4;
22351 +               unsigned conidsts : 1;
22352 +               unsigned reserved17 : 1;
22353 +               unsigned asesvld : 1;
22354 +               unsigned bsesvld : 1;
22355 +               unsigned currmod : 1;
22356 +               unsigned reserved21_31 : 11;
22357 +       } b;
22358 +} gotgctl_data_t;
22359 +
22360 +/**
22361 + * This union represents the bit fields of the Core OTG Interrupt Register
22362 + * (GOTGINT).  Set/clear the bits using the bit fields then write the <i>d32</i>
22363 + * value to the register.
22364 + */
22365 +typedef union gotgint_data
22366 +{
22367 +       /** raw register data */
22368 +       uint32_t d32;
22369 +       /** register bits */
22370 +       struct
22371 +       {
22372 +               /** Current Mode */
22373 +               unsigned reserved0_1 : 2;
22374 +
22375 +               /** Session End Detected */
22376 +               unsigned sesenddet : 1;
22377 +
22378 +               unsigned reserved3_7 : 5;
22379 +
22380 +               /** Session Request Success Status Change */
22381 +               unsigned sesreqsucstschng : 1;
22382 +               /** Host Negotiation Success Status Change */
22383 +               unsigned hstnegsucstschng : 1;
22384 +
22385 +               unsigned reserver10_16 : 7;
22386 +
22387 +               /** Host Negotiation Detected */
22388 +               unsigned hstnegdet : 1;
22389 +               /** A-Device Timeout Change */
22390 +               unsigned adevtoutchng : 1;
22391 +               /** Debounce Done */
22392 +               unsigned debdone : 1;
22393 +
22394 +               unsigned reserved31_20 : 12;
22395 +
22396 +       } b;
22397 +} gotgint_data_t;
22398 +
22399 +
22400 +/**
22401 + * This union represents the bit fields of the Core AHB Configuration
22402 + * Register (GAHBCFG). Set/clear the bits using the bit fields then
22403 + * write the <i>d32</i> value to the register.
22404 + */
22405 +typedef union gahbcfg_data
22406 +{
22407 +       /** raw register data */
22408 +       uint32_t d32;
22409 +       /** register bits */
22410 +       struct
22411 +       {
22412 +               unsigned glblintrmsk : 1;
22413 +#define DWC_GAHBCFG_GLBINT_ENABLE              1
22414 +
22415 +               unsigned hburstlen : 4;
22416 +#define DWC_GAHBCFG_INT_DMA_BURST_SINGLE       0
22417 +#define DWC_GAHBCFG_INT_DMA_BURST_INCR         1
22418 +#define DWC_GAHBCFG_INT_DMA_BURST_INCR4                3
22419 +#define DWC_GAHBCFG_INT_DMA_BURST_INCR8                5
22420 +#define DWC_GAHBCFG_INT_DMA_BURST_INCR16       7
22421 +
22422 +               unsigned dmaenable : 1;
22423 +#define DWC_GAHBCFG_DMAENABLE                  1
22424 +               unsigned reserved : 1;
22425 +               unsigned nptxfemplvl_txfemplvl : 1;
22426 +               unsigned ptxfemplvl : 1;
22427 +#define DWC_GAHBCFG_TXFEMPTYLVL_EMPTY          1
22428 +#define DWC_GAHBCFG_TXFEMPTYLVL_HALFEMPTY      0
22429 +               unsigned reserved9_31 : 23;
22430 +       } b;
22431 +} gahbcfg_data_t;
22432 +
22433 +/**
22434 + * This union represents the bit fields of the Core USB Configuration
22435 + * Register (GUSBCFG). Set the bits using the bit fields then write
22436 + * the <i>d32</i> value to the register.
22437 + */
22438 +typedef union gusbcfg_data
22439 +{
22440 +       /** raw register data */
22441 +       uint32_t d32;
22442 +       /** register bits */
22443 +       struct
22444 +       {
22445 +               unsigned toutcal : 3;
22446 +               unsigned phyif : 1;
22447 +               unsigned ulpi_utmi_sel : 1;
22448 +               unsigned fsintf : 1;
22449 +               unsigned physel : 1;
22450 +               unsigned ddrsel : 1;
22451 +               unsigned srpcap : 1;
22452 +               unsigned hnpcap : 1;
22453 +               unsigned usbtrdtim : 4;
22454 +               unsigned nptxfrwnden : 1;
22455 +               unsigned phylpwrclksel : 1;
22456 +               unsigned otgutmifssel : 1;
22457 +               unsigned ulpi_fsls : 1;
22458 +               unsigned ulpi_auto_res : 1;
22459 +               unsigned ulpi_clk_sus_m : 1;
22460 +               unsigned ulpi_ext_vbus_drv : 1;
22461 +               unsigned ulpi_int_vbus_indicator : 1;
22462 +               unsigned term_sel_dl_pulse : 1;
22463 +               unsigned reserved23_27 : 5;
22464 +               unsigned tx_end_delay : 1;
22465 +               unsigned reserved29_31 : 3;
22466 +       } b;
22467 +} gusbcfg_data_t;
22468 +
22469 +/**
22470 + * This union represents the bit fields of the Core Reset Register
22471 + * (GRSTCTL).  Set/clear the bits using the bit fields then write the
22472 + * <i>d32</i> value to the register.
22473 + */
22474 +typedef union grstctl_data
22475 +{
22476 +       /** raw register data */
22477 +       uint32_t d32;
22478 +       /** register bits */
22479 +       struct
22480 +       {
22481 +               /** Core Soft Reset (CSftRst) (Device and Host)
22482 +                *
22483 +                * The application can flush the control logic in the
22484 +                * entire core using this bit. This bit resets the
22485 +                * pipelines in the AHB Clock domain as well as the
22486 +                * PHY Clock domain.
22487 +                *
22488 +                * The state machines are reset to an IDLE state, the
22489 +                * control bits in the CSRs are cleared, all the
22490 +                * transmit FIFOs and the receive FIFO are flushed.
22491 +                *
22492 +                * The status mask bits that control the generation of
22493 +                * the interrupt, are cleared, to clear the
22494 +                * interrupt. The interrupt status bits are not
22495 +                * cleared, so the application can get the status of
22496 +                * any events that occurred in the core after it has
22497 +                * set this bit.
22498 +                *
22499 +                * Any transactions on the AHB are terminated as soon
22500 +                * as possible following the protocol. Any
22501 +                * transactions on the USB are terminated immediately.
22502 +                *
22503 +                * The configuration settings in the CSRs are
22504 +                * unchanged, so the software doesn't have to
22505 +                * reprogram these registers (Device
22506 +                * Configuration/Host Configuration/Core System
22507 +                * Configuration/Core PHY Configuration).
22508 +                *
22509 +                * The application can write to this bit, any time it
22510 +                * wants to reset the core. This is a self clearing
22511 +                * bit and the core clears this bit after all the
22512 +                * necessary logic is reset in the core, which may
22513 +                * take several clocks, depending on the current state
22514 +                * of the core.
22515 +                */
22516 +               unsigned csftrst : 1;
22517 +               /** Hclk Soft Reset
22518 +                *
22519 +                * The application uses this bit to reset the control logic in
22520 +                * the AHB clock domain. Only AHB clock domain pipelines are
22521 +                * reset.
22522 +                */
22523 +               unsigned hsftrst : 1;
22524 +               /** Host Frame Counter Reset (Host Only)<br>
22525 +                *
22526 +                * The application can reset the (micro)frame number
22527 +                * counter inside the core, using this bit. When the
22528 +                * (micro)frame counter is reset, the subsequent SOF
22529 +                * sent out by the core, will have a (micro)frame
22530 +                * number of 0.
22531 +                */
22532 +               unsigned hstfrm : 1;
22533 +               /** In Token Sequence Learning Queue Flush
22534 +                * (INTknQFlsh) (Device Only)
22535 +                */
22536 +               unsigned intknqflsh : 1;
22537 +               /** RxFIFO Flush (RxFFlsh) (Device and Host)
22538 +                *
22539 +                * The application can flush the entire Receive FIFO
22540 +                * using this bit.      <p>The application must first
22541 +                * ensure that the core is not in the middle of a
22542 +                * transaction.  <p>The application should write into
22543 +                * this bit, only after making sure that neither the
22544 +                * DMA engine is reading from the RxFIFO nor the MAC
22545 +                * is writing the data in to the FIFO.  <p>The
22546 +                * application should wait until the bit is cleared
22547 +                * before performing any other operations. This bit
22548 +                * will takes 8 clocks (slowest of PHY or AHB clock)
22549 +                * to clear.
22550 +                */
22551 +               unsigned rxfflsh : 1;
22552 +               /** TxFIFO Flush (TxFFlsh) (Device and Host).
22553 +                *
22554 +                * This bit is used to selectively flush a single or
22555 +                * all transmit FIFOs.  The application must first
22556 +                * ensure that the core is not in the middle of a
22557 +                * transaction.  <p>The application should write into
22558 +                * this bit, only after making sure that neither the
22559 +                * DMA engine is writing into the TxFIFO nor the MAC
22560 +                * is reading the data out of the FIFO.  <p>The
22561 +                * application should wait until the core clears this
22562 +                * bit, before performing any operations. This bit
22563 +                * will takes 8 clocks (slowest of PHY or AHB clock)
22564 +                * to clear.
22565 +                */
22566 +               unsigned txfflsh : 1;
22567 +
22568 +               /** TxFIFO Number (TxFNum) (Device and Host).
22569 +                *
22570 +                * This is the FIFO number which needs to be flushed,
22571 +                * using the TxFIFO Flush bit. This field should not
22572 +                * be changed until the TxFIFO Flush bit is cleared by
22573 +                * the core.
22574 +                *       - 0x0 : Non Periodic TxFIFO Flush
22575 +                *       - 0x1 : Periodic TxFIFO #1 Flush in device mode
22576 +                *         or Periodic TxFIFO in host mode
22577 +                *       - 0x2 : Periodic TxFIFO #2 Flush in device mode.
22578 +                *       - ...
22579 +                *       - 0xF : Periodic TxFIFO #15 Flush in device mode
22580 +                *       - 0x10: Flush all the Transmit NonPeriodic and
22581 +                *         Transmit Periodic FIFOs in the core
22582 +                */
22583 +               unsigned txfnum : 5;
22584 +               /** Reserved */
22585 +               unsigned reserved11_29 : 19;
22586 +               /** DMA Request Signal.  Indicated DMA request is in
22587 +                * probress.  Used for debug purpose. */
22588 +               unsigned dmareq : 1;
22589 +               /** AHB Master Idle.  Indicates the AHB Master State
22590 +                * Machine is in IDLE condition. */
22591 +               unsigned ahbidle : 1;
22592 +       } b;
22593 +} grstctl_t;
22594 +
22595 +
22596 +/**
22597 + * This union represents the bit fields of the Core Interrupt Mask
22598 + * Register (GINTMSK). Set/clear the bits using the bit fields then
22599 + * write the <i>d32</i> value to the register.
22600 + */
22601 +typedef union gintmsk_data
22602 +{
22603 +       /** raw register data */
22604 +       uint32_t d32;
22605 +       /** register bits */
22606 +       struct
22607 +       {
22608 +               unsigned reserved0 : 1;
22609 +               unsigned modemismatch : 1;
22610 +               unsigned otgintr : 1;
22611 +               unsigned sofintr : 1;
22612 +               unsigned rxstsqlvl : 1;
22613 +               unsigned nptxfempty : 1;
22614 +               unsigned ginnakeff : 1;
22615 +               unsigned goutnakeff : 1;
22616 +               unsigned reserved8 : 1;
22617 +               unsigned i2cintr : 1;
22618 +               unsigned erlysuspend : 1;
22619 +               unsigned usbsuspend : 1;
22620 +               unsigned usbreset : 1;
22621 +               unsigned enumdone : 1;
22622 +               unsigned isooutdrop : 1;
22623 +               unsigned eopframe : 1;
22624 +               unsigned reserved16 : 1;
22625 +               unsigned epmismatch : 1;
22626 +               unsigned inepintr : 1;
22627 +               unsigned outepintr : 1;
22628 +               unsigned incomplisoin : 1;
22629 +               unsigned incomplisoout : 1;
22630 +               unsigned reserved22_23 : 2;
22631 +               unsigned portintr : 1;
22632 +               unsigned hcintr : 1;
22633 +               unsigned ptxfempty : 1;
22634 +               unsigned reserved27 : 1;
22635 +               unsigned conidstschng : 1;
22636 +               unsigned disconnect : 1;
22637 +               unsigned sessreqintr : 1;
22638 +               unsigned wkupintr : 1;
22639 +       } b;
22640 +} gintmsk_data_t;
22641 +/**
22642 + * This union represents the bit fields of the Core Interrupt Register
22643 + * (GINTSTS).  Set/clear the bits using the bit fields then write the
22644 + * <i>d32</i> value to the register.
22645 + */
22646 +typedef union gintsts_data
22647 +{
22648 +       /** raw register data */
22649 +       uint32_t d32;
22650 +#define DWC_SOF_INTR_MASK 0x0008
22651 +       /** register bits */
22652 +       struct
22653 +       {
22654 +#define DWC_HOST_MODE 1
22655 +               unsigned curmode : 1;
22656 +               unsigned modemismatch : 1;
22657 +               unsigned otgintr : 1;
22658 +               unsigned sofintr : 1;
22659 +               unsigned rxstsqlvl : 1;
22660 +               unsigned nptxfempty : 1;
22661 +               unsigned ginnakeff : 1;
22662 +               unsigned goutnakeff : 1;
22663 +               unsigned reserved8 : 1;
22664 +               unsigned i2cintr : 1;
22665 +               unsigned erlysuspend : 1;
22666 +               unsigned usbsuspend : 1;
22667 +               unsigned usbreset : 1;
22668 +               unsigned enumdone : 1;
22669 +               unsigned isooutdrop : 1;
22670 +               unsigned eopframe : 1;
22671 +               unsigned intokenrx : 1;
22672 +               unsigned epmismatch : 1;
22673 +               unsigned inepint: 1;
22674 +               unsigned outepintr : 1;
22675 +               unsigned incomplisoin : 1;
22676 +               unsigned incomplisoout : 1;
22677 +               unsigned reserved22_23 : 2;
22678 +               unsigned portintr : 1;
22679 +               unsigned hcintr : 1;
22680 +               unsigned ptxfempty : 1;
22681 +               unsigned reserved27 : 1;
22682 +               unsigned conidstschng : 1;
22683 +               unsigned disconnect : 1;
22684 +               unsigned sessreqintr : 1;
22685 +               unsigned wkupintr : 1;
22686 +       } b;
22687 +} gintsts_data_t;
22688 +
22689 +
22690 +/**
22691 + * This union represents the bit fields in the Device Receive Status Read and
22692 + * Pop Registers (GRXSTSR, GRXSTSP) Read the register into the <i>d32</i>
22693 + * element then read out the bits using the <i>b</i>it elements.
22694 + */
22695 +typedef union device_grxsts_data
22696 +{
22697 +       /** raw register data */
22698 +       uint32_t d32;
22699 +       /** register bits */
22700 +       struct
22701 +       {
22702 +               unsigned epnum : 4;
22703 +               unsigned bcnt : 11;
22704 +               unsigned dpid : 2;
22705 +
22706 +#define DWC_STS_DATA_UPDT              0x2                               // OUT Data Packet
22707 +#define DWC_STS_XFER_COMP              0x3                               // OUT Data Transfer Complete
22708 +
22709 +#define DWC_DSTS_GOUT_NAK              0x1                               // Global OUT NAK
22710 +#define DWC_DSTS_SETUP_COMP            0x4                               // Setup Phase Complete
22711 +#define DWC_DSTS_SETUP_UPDT 0x6                                  // SETUP Packet
22712 +               unsigned pktsts : 4;
22713 +               unsigned fn : 4;
22714 +               unsigned reserved : 7;
22715 +       } b;
22716 +} device_grxsts_data_t;
22717 +
22718 +/**
22719 + * This union represents the bit fields in the Host Receive Status Read and
22720 + * Pop Registers (GRXSTSR, GRXSTSP) Read the register into the <i>d32</i>
22721 + * element then read out the bits using the <i>b</i>it elements.
22722 + */
22723 +typedef union host_grxsts_data
22724 +{
22725 +       /** raw register data */
22726 +       uint32_t d32;
22727 +       /** register bits */
22728 +       struct
22729 +       {
22730 +               unsigned chnum : 4;
22731 +               unsigned bcnt : 11;
22732 +               unsigned dpid : 2;
22733 +
22734 +               unsigned pktsts : 4;
22735 +#define DWC_GRXSTS_PKTSTS_IN                     0x2
22736 +#define DWC_GRXSTS_PKTSTS_IN_XFER_COMP   0x3
22737 +#define DWC_GRXSTS_PKTSTS_DATA_TOGGLE_ERR 0x5
22738 +#define DWC_GRXSTS_PKTSTS_CH_HALTED              0x7
22739 +
22740 +               unsigned reserved : 11;
22741 +       } b;
22742 +} host_grxsts_data_t;
22743 +
22744 +/**
22745 + * This union represents the bit fields in the FIFO Size Registers (HPTXFSIZ,
22746 + * GNPTXFSIZ, DPTXFSIZn, DIEPTXFn). Read the register into the <i>d32</i> element then
22747 + * read out the bits using the <i>b</i>it elements.
22748 + */
22749 +typedef union fifosize_data
22750 +{
22751 +       /** raw register data */
22752 +       uint32_t d32;
22753 +       /** register bits */
22754 +       struct
22755 +       {
22756 +               unsigned startaddr : 16;
22757 +               unsigned depth : 16;
22758 +       } b;
22759 +} fifosize_data_t;
22760 +
22761 +/**
22762 + * This union represents the bit fields in the Non-Periodic Transmit
22763 + * FIFO/Queue Status Register (GNPTXSTS). Read the register into the
22764 + * <i>d32</i> element then read out the bits using the <i>b</i>it
22765 + * elements.
22766 + */
22767 +typedef union gnptxsts_data
22768 +{
22769 +       /** raw register data */
22770 +       uint32_t d32;
22771 +       /** register bits */
22772 +       struct
22773 +       {
22774 +               unsigned nptxfspcavail : 16;
22775 +               unsigned nptxqspcavail : 8;
22776 +               /** Top of the Non-Periodic Transmit Request Queue
22777 +                *      - bit 24 - Terminate (Last entry for the selected
22778 +                *        channel/EP)
22779 +                *      - bits 26:25 - Token Type
22780 +                *        - 2'b00 - IN/OUT
22781 +                *        - 2'b01 - Zero Length OUT
22782 +                *        - 2'b10 - PING/Complete Split
22783 +                *        - 2'b11 - Channel Halt
22784 +                *      - bits 30:27 - Channel/EP Number
22785 +                */
22786 +               unsigned nptxqtop_terminate : 1;
22787 +               unsigned nptxqtop_token : 2;
22788 +               unsigned nptxqtop_chnep : 4;
22789 +               unsigned reserved : 1;
22790 +       } b;
22791 +} gnptxsts_data_t;
22792 +
22793 +/**
22794 + * This union represents the bit fields in the Transmit
22795 + * FIFO Status Register (DTXFSTS). Read the register into the
22796 + * <i>d32</i> element then read out the bits using the <i>b</i>it
22797 + * elements.
22798 + */
22799 +typedef union dtxfsts_data
22800 +{
22801 +       /** raw register data */
22802 +       uint32_t d32;
22803 +       /** register bits */
22804 +       struct
22805 +       {
22806 +               unsigned txfspcavail : 16;
22807 +               unsigned reserved : 16;
22808 +       } b;
22809 +} dtxfsts_data_t;
22810 +
22811 +/**
22812 + * This union represents the bit fields in the I2C Control Register
22813 + * (I2CCTL). Read the register into the <i>d32</i> element then read out the
22814 + * bits using the <i>b</i>it elements.
22815 + */
22816 +typedef union gi2cctl_data
22817 +{
22818 +       /** raw register data */
22819 +       uint32_t d32;
22820 +       /** register bits */
22821 +       struct
22822 +       {
22823 +               unsigned rwdata : 8;
22824 +               unsigned regaddr : 8;
22825 +               unsigned addr : 7;
22826 +               unsigned i2cen : 1;
22827 +               unsigned ack : 1;
22828 +               unsigned i2csuspctl : 1;
22829 +               unsigned i2cdevaddr : 2;
22830 +               unsigned reserved : 2;
22831 +               unsigned rw : 1;
22832 +               unsigned bsydne : 1;
22833 +       } b;
22834 +} gi2cctl_data_t;
22835 +
22836 +/**
22837 + * This union represents the bit fields in the User HW Config1
22838 + * Register.  Read the register into the <i>d32</i> element then read
22839 + * out the bits using the <i>b</i>it elements.
22840 + */
22841 +typedef union hwcfg1_data
22842 +{
22843 +       /** raw register data */
22844 +       uint32_t d32;
22845 +       /** register bits */
22846 +       struct
22847 +       {
22848 +               unsigned ep_dir0 : 2;
22849 +               unsigned ep_dir1 : 2;
22850 +               unsigned ep_dir2 : 2;
22851 +               unsigned ep_dir3 : 2;
22852 +               unsigned ep_dir4 : 2;
22853 +               unsigned ep_dir5 : 2;
22854 +               unsigned ep_dir6 : 2;
22855 +               unsigned ep_dir7 : 2;
22856 +               unsigned ep_dir8 : 2;
22857 +               unsigned ep_dir9 : 2;
22858 +               unsigned ep_dir10 : 2;
22859 +               unsigned ep_dir11 : 2;
22860 +               unsigned ep_dir12 : 2;
22861 +               unsigned ep_dir13 : 2;
22862 +               unsigned ep_dir14 : 2;
22863 +               unsigned ep_dir15 : 2;
22864 +       } b;
22865 +} hwcfg1_data_t;
22866 +
22867 +/**
22868 + * This union represents the bit fields in the User HW Config2
22869 + * Register.  Read the register into the <i>d32</i> element then read
22870 + * out the bits using the <i>b</i>it elements.
22871 + */
22872 +typedef union hwcfg2_data
22873 +{
22874 +       /** raw register data */
22875 +       uint32_t d32;
22876 +       /** register bits */
22877 +       struct
22878 +       {
22879 +               /* GHWCFG2 */
22880 +               unsigned op_mode : 3;
22881 +#define DWC_HWCFG2_OP_MODE_HNP_SRP_CAPABLE_OTG 0
22882 +#define DWC_HWCFG2_OP_MODE_SRP_ONLY_CAPABLE_OTG 1
22883 +#define DWC_HWCFG2_OP_MODE_NO_HNP_SRP_CAPABLE_OTG 2
22884 +#define DWC_HWCFG2_OP_MODE_SRP_CAPABLE_DEVICE 3
22885 +#define DWC_HWCFG2_OP_MODE_NO_SRP_CAPABLE_DEVICE 4
22886 +#define DWC_HWCFG2_OP_MODE_SRP_CAPABLE_HOST 5
22887 +#define DWC_HWCFG2_OP_MODE_NO_SRP_CAPABLE_HOST 6
22888 +
22889 +               unsigned architecture : 2;
22890 +               unsigned point2point : 1;
22891 +               unsigned hs_phy_type : 2;
22892 +#define DWC_HWCFG2_HS_PHY_TYPE_NOT_SUPPORTED 0
22893 +#define DWC_HWCFG2_HS_PHY_TYPE_UTMI 1
22894 +#define DWC_HWCFG2_HS_PHY_TYPE_ULPI 2
22895 +#define DWC_HWCFG2_HS_PHY_TYPE_UTMI_ULPI 3
22896 +
22897 +               unsigned fs_phy_type : 2;
22898 +               unsigned num_dev_ep : 4;
22899 +               unsigned num_host_chan : 4;
22900 +               unsigned perio_ep_supported : 1;
22901 +               unsigned dynamic_fifo : 1;
22902 +               unsigned multi_proc_int : 1;
22903 +               unsigned reserved21 : 1;
22904 +               unsigned nonperio_tx_q_depth : 2;
22905 +               unsigned host_perio_tx_q_depth : 2;
22906 +               unsigned dev_token_q_depth : 5;
22907 +               unsigned reserved31 : 1;
22908 +       } b;
22909 +} hwcfg2_data_t;
22910 +
22911 +/**
22912 + * This union represents the bit fields in the User HW Config3
22913 + * Register.  Read the register into the <i>d32</i> element then read
22914 + * out the bits using the <i>b</i>it elements.
22915 + */
22916 +typedef union hwcfg3_data
22917 +{
22918 +       /** raw register data */
22919 +       uint32_t d32;
22920 +       /** register bits */
22921 +       struct
22922 +       {
22923 +               /* GHWCFG3 */
22924 +               unsigned xfer_size_cntr_width : 4;
22925 +               unsigned packet_size_cntr_width : 3;
22926 +               unsigned otg_func : 1;
22927 +               unsigned i2c : 1;
22928 +               unsigned vendor_ctrl_if : 1;
22929 +               unsigned optional_features : 1;
22930 +               unsigned synch_reset_type : 1;
22931 +               unsigned ahb_phy_clock_synch : 1;
22932 +               unsigned reserved15_13 : 3;
22933 +               unsigned dfifo_depth : 16;
22934 +       } b;
22935 +} hwcfg3_data_t;
22936 +
22937 +/**
22938 + * This union represents the bit fields in the User HW Config4
22939 + * Register.  Read the register into the <i>d32</i> element then read
22940 + * out the bits using the <i>b</i>it elements.
22941 + */
22942 +typedef union hwcfg4_data
22943 +{
22944 +       /** raw register data */
22945 +       uint32_t d32;
22946 +       /** register bits */
22947 +       struct
22948 +       {
22949 +               unsigned num_dev_perio_in_ep : 4;
22950 +               unsigned power_optimiz : 1;
22951 +               unsigned min_ahb_freq : 9;
22952 +               unsigned utmi_phy_data_width : 2;
22953 +               unsigned num_dev_mode_ctrl_ep : 4;
22954 +               unsigned iddig_filt_en : 1;
22955 +               unsigned vbus_valid_filt_en : 1;
22956 +               unsigned a_valid_filt_en : 1;
22957 +               unsigned b_valid_filt_en : 1;
22958 +               unsigned session_end_filt_en : 1;
22959 +               unsigned ded_fifo_en : 1;
22960 +               unsigned num_in_eps : 4;
22961 +               unsigned desc_dma : 1;
22962 +               unsigned desc_dma_dyn : 1;
22963 +       } b;
22964 +} hwcfg4_data_t;
22965 +
22966 +////////////////////////////////////////////
22967 +// Device Registers
22968 +/**
22969 + * Device Global Registers. <i>Offsets 800h-BFFh</i>
22970 + *
22971 + * The following structures define the size and relative field offsets
22972 + * for the Device Mode Registers.
22973 + *
22974 + * <i>These registers are visible only in Device mode and must not be
22975 + * accessed in Host mode, as the results are unknown.</i>
22976 + */
22977 +typedef struct dwc_otg_dev_global_regs
22978 +{
22979 +       /** Device Configuration Register. <i>Offset 800h</i> */
22980 +       volatile uint32_t dcfg;
22981 +       /** Device Control Register. <i>Offset: 804h</i> */
22982 +       volatile uint32_t dctl;
22983 +       /** Device Status Register (Read Only). <i>Offset: 808h</i> */
22984 +       volatile uint32_t dsts;
22985 +       /** Reserved. <i>Offset: 80Ch</i> */
22986 +       uint32_t unused;
22987 +       /** Device IN Endpoint Common Interrupt Mask
22988 +        * Register. <i>Offset: 810h</i> */
22989 +       volatile uint32_t diepmsk;
22990 +       /** Device OUT Endpoint Common Interrupt Mask
22991 +        * Register. <i>Offset: 814h</i> */
22992 +       volatile uint32_t doepmsk;
22993 +       /** Device All Endpoints Interrupt Register.  <i>Offset: 818h</i> */
22994 +       volatile uint32_t daint;
22995 +       /** Device All Endpoints Interrupt Mask Register.  <i>Offset:
22996 +        * 81Ch</i> */
22997 +       volatile uint32_t daintmsk;
22998 +       /** Device IN Token Queue Read Register-1 (Read Only).
22999 +        * <i>Offset: 820h</i> */
23000 +       volatile uint32_t dtknqr1;
23001 +       /** Device IN Token Queue Read Register-2 (Read Only).
23002 +        * <i>Offset: 824h</i> */
23003 +       volatile uint32_t dtknqr2;
23004 +       /** Device VBUS  discharge Register.  <i>Offset: 828h</i> */
23005 +       volatile uint32_t dvbusdis;
23006 +       /** Device VBUS Pulse Register.  <i>Offset: 82Ch</i> */
23007 +       volatile uint32_t dvbuspulse;
23008 +       /** Device IN Token Queue Read Register-3 (Read Only). /
23009 +        *      Device Thresholding control register (Read/Write)
23010 +        * <i>Offset: 830h</i> */
23011 +       volatile uint32_t dtknqr3_dthrctl;
23012 +       /** Device IN Token Queue Read Register-4 (Read Only). /
23013 +        *      Device IN EPs empty Inr. Mask Register (Read/Write)
23014 +        * <i>Offset: 834h</i> */
23015 +       volatile uint32_t dtknqr4_fifoemptymsk;
23016 +       /** Device Each Endpoint Interrupt Register (Read Only). /
23017 +        * <i>Offset: 838h</i> */
23018 +       volatile uint32_t deachint;
23019 +       /** Device Each Endpoint Interrupt mask Register (Read/Write). /
23020 +        * <i>Offset: 83Ch</i> */
23021 +       volatile uint32_t deachintmsk;
23022 +       /** Device Each In Endpoint Interrupt mask Register (Read/Write). /
23023 +        * <i>Offset: 840h</i> */
23024 +       volatile uint32_t diepeachintmsk[MAX_EPS_CHANNELS];
23025 +       /** Device Each Out Endpoint Interrupt mask Register (Read/Write). /
23026 +        * <i>Offset: 880h</i> */
23027 +       volatile uint32_t doepeachintmsk[MAX_EPS_CHANNELS];
23028 +} dwc_otg_device_global_regs_t;
23029 +
23030 +/**
23031 + * This union represents the bit fields in the Device Configuration
23032 + * Register.  Read the register into the <i>d32</i> member then
23033 + * set/clear the bits using the <i>b</i>it elements.  Write the
23034 + * <i>d32</i> member to the dcfg register.
23035 + */
23036 +typedef union dcfg_data
23037 +{
23038 +       /** raw register data */
23039 +       uint32_t d32;
23040 +       /** register bits */
23041 +       struct
23042 +       {
23043 +               /** Device Speed */
23044 +               unsigned devspd : 2;
23045 +               /** Non Zero Length Status OUT Handshake */
23046 +               unsigned nzstsouthshk : 1;
23047 +#define DWC_DCFG_SEND_STALL 1
23048 +
23049 +               unsigned reserved3 : 1;
23050 +               /** Device Addresses */
23051 +               unsigned devaddr : 7;
23052 +               /** Periodic Frame Interval */
23053 +               unsigned perfrint : 2;
23054 +#define DWC_DCFG_FRAME_INTERVAL_80 0
23055 +#define DWC_DCFG_FRAME_INTERVAL_85 1
23056 +#define DWC_DCFG_FRAME_INTERVAL_90 2
23057 +#define DWC_DCFG_FRAME_INTERVAL_95 3
23058 +
23059 +               unsigned reserved13_17 : 5;
23060 +               /** In Endpoint Mis-match count */
23061 +               unsigned epmscnt : 5;
23062 +               /** Enable Descriptor DMA in Device mode */
23063 +               unsigned descdma : 1;
23064 +       } b;
23065 +} dcfg_data_t;
23066 +
23067 +/**
23068 + * This union represents the bit fields in the Device Control
23069 + * Register.  Read the register into the <i>d32</i> member then
23070 + * set/clear the bits using the <i>b</i>it elements.
23071 + */
23072 +typedef union dctl_data
23073 +{
23074 +       /** raw register data */
23075 +       uint32_t d32;
23076 +       /** register bits */
23077 +       struct
23078 +       {
23079 +               /** Remote Wakeup */
23080 +               unsigned rmtwkupsig : 1;
23081 +               /** Soft Disconnect */
23082 +               unsigned sftdiscon : 1;
23083 +               /** Global Non-Periodic IN NAK Status */
23084 +               unsigned gnpinnaksts : 1;
23085 +               /** Global OUT NAK Status */
23086 +               unsigned goutnaksts : 1;
23087 +               /** Test Control */
23088 +               unsigned tstctl : 3;
23089 +               /** Set Global Non-Periodic IN NAK */
23090 +               unsigned sgnpinnak : 1;
23091 +               /** Clear Global Non-Periodic IN NAK */
23092 +               unsigned cgnpinnak : 1;
23093 +               /** Set Global OUT NAK */
23094 +               unsigned sgoutnak : 1;
23095 +               /** Clear Global OUT NAK */
23096 +               unsigned cgoutnak : 1;
23097 +
23098 +               /** Power-On Programming Done */
23099 +               unsigned pwronprgdone : 1;
23100 +               /** Global Continue on BNA */
23101 +               unsigned gcontbna : 1;
23102 +               /** Global Multi Count */
23103 +               unsigned gmc : 2;
23104 +               /** Ignore Frame Number for ISOC EPs */
23105 +               unsigned ifrmnum : 1;
23106 +               /** NAK on Babble */
23107 +               unsigned nakonbble : 1;
23108 +
23109 +               unsigned reserved16_31 : 16;
23110 +       } b;
23111 +} dctl_data_t;
23112 +
23113 +/**
23114 + * This union represents the bit fields in the Device Status
23115 + * Register.  Read the register into the <i>d32</i> member then
23116 + * set/clear the bits using the <i>b</i>it elements.
23117 + */
23118 +typedef union dsts_data
23119 +{
23120 +       /** raw register data */
23121 +       uint32_t d32;
23122 +       /** register bits */
23123 +       struct
23124 +       {
23125 +               /** Suspend Status */
23126 +               unsigned suspsts : 1;
23127 +               /** Enumerated Speed */
23128 +               unsigned enumspd : 2;
23129 +#define DWC_DSTS_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ 0
23130 +#define DWC_DSTS_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ 1
23131 +#define DWC_DSTS_ENUMSPD_LS_PHY_6MHZ              2
23132 +#define DWC_DSTS_ENUMSPD_FS_PHY_48MHZ             3
23133 +               /** Erratic Error */
23134 +               unsigned errticerr : 1;
23135 +               unsigned reserved4_7: 4;
23136 +               /** Frame or Microframe Number of the received SOF */
23137 +               unsigned soffn : 14;
23138 +               unsigned reserved22_31 : 10;
23139 +       } b;
23140 +} dsts_data_t;
23141 +
23142 +
23143 +/**
23144 + * This union represents the bit fields in the Device IN EP Interrupt
23145 + * Register and the Device IN EP Common Mask Register.
23146 + *
23147 + * - Read the register into the <i>d32</i> member then set/clear the
23148 + *      bits using the <i>b</i>it elements.
23149 + */
23150 +typedef union diepint_data
23151 +{
23152 +       /** raw register data */
23153 +       uint32_t d32;
23154 +       /** register bits */
23155 +       struct
23156 +       {
23157 +               /** Transfer complete mask */
23158 +               unsigned xfercompl : 1;
23159 +               /** Endpoint disable mask */
23160 +               unsigned epdisabled : 1;
23161 +               /** AHB Error mask */
23162 +               unsigned ahberr : 1;
23163 +               /** TimeOUT Handshake mask (non-ISOC EPs) */
23164 +               unsigned timeout : 1;
23165 +               /** IN Token received with TxF Empty mask */
23166 +               unsigned intktxfemp : 1;
23167 +               /** IN Token Received with EP mismatch mask */
23168 +               unsigned intknepmis : 1;
23169 +               /** IN Endpoint HAK Effective mask */
23170 +               unsigned inepnakeff : 1;
23171 +               /** IN Endpoint HAK Effective mask */
23172 +               unsigned emptyintr : 1;
23173 +
23174 +               unsigned txfifoundrn : 1;
23175 +
23176 +               /** BNA Interrupt mask */
23177 +               unsigned bna : 1;
23178 +
23179 +               unsigned reserved10_12 : 3;
23180 +               /** BNA Interrupt mask */
23181 +               unsigned nak : 1;
23182 +
23183 +               unsigned reserved14_31 : 18;
23184 +               } b;
23185 +} diepint_data_t;
23186 +
23187 +/**
23188 + * This union represents the bit fields in the Device IN EP
23189 + * Common/Dedicated Interrupt Mask Register.
23190 + */
23191 +typedef union diepint_data diepmsk_data_t;
23192 +
23193 +/**
23194 + * This union represents the bit fields in the Device OUT EP Interrupt
23195 + * Registerand Device OUT EP Common Interrupt Mask Register.
23196 + *
23197 + * - Read the register into the <i>d32</i> member then set/clear the
23198 + *      bits using the <i>b</i>it elements.
23199 + */
23200 +typedef union doepint_data
23201 +{
23202 +       /** raw register data */
23203 +       uint32_t d32;
23204 +       /** register bits */
23205 +       struct
23206 +       {
23207 +               /** Transfer complete */
23208 +               unsigned xfercompl : 1;
23209 +               /** Endpoint disable  */
23210 +               unsigned epdisabled : 1;
23211 +               /** AHB Error */
23212 +               unsigned ahberr : 1;
23213 +               /** Setup Phase Done (contorl EPs) */
23214 +               unsigned setup : 1;
23215 +               /** OUT Token Received when Endpoint Disabled */
23216 +               unsigned outtknepdis : 1;
23217 +
23218 +               unsigned stsphsercvd : 1;
23219 +               /** Back-to-Back SETUP Packets Received */
23220 +               unsigned back2backsetup : 1;
23221 +
23222 +               unsigned reserved7 : 1;
23223 +               /** OUT packet Error */
23224 +               unsigned outpkterr : 1;
23225 +               /** BNA Interrupt */
23226 +               unsigned bna : 1;
23227 +
23228 +               unsigned reserved10 : 1;
23229 +               /** Packet Drop Status */
23230 +               unsigned pktdrpsts : 1;
23231 +               /** Babble Interrupt */
23232 +               unsigned babble : 1;
23233 +               /** NAK Interrupt */
23234 +               unsigned nak : 1;
23235 +               /** NYET Interrupt */
23236 +               unsigned nyet : 1;
23237 +
23238 +               unsigned reserved15_31 : 17;
23239 +       } b;
23240 +} doepint_data_t;
23241 +
23242 +/**
23243 + * This union represents the bit fields in the Device OUT EP
23244 + * Common/Dedicated Interrupt Mask Register.
23245 + */
23246 +typedef union doepint_data doepmsk_data_t;
23247 +
23248 +/**
23249 + * This union represents the bit fields in the Device All EP Interrupt
23250 + * and Mask Registers.
23251 + * - Read the register into the <i>d32</i> member then set/clear the
23252 + *      bits using the <i>b</i>it elements.
23253 + */
23254 +typedef union daint_data
23255 +{
23256 +       /** raw register data */
23257 +       uint32_t d32;
23258 +       /** register bits */
23259 +       struct
23260 +       {
23261 +               /** IN Endpoint bits */
23262 +               unsigned in : 16;
23263 +               /** OUT Endpoint bits */
23264 +               unsigned out : 16;
23265 +       } ep;
23266 +       struct
23267 +       {
23268 +               /** IN Endpoint bits */
23269 +               unsigned inep0  : 1;
23270 +               unsigned inep1  : 1;
23271 +               unsigned inep2  : 1;
23272 +               unsigned inep3  : 1;
23273 +               unsigned inep4  : 1;
23274 +               unsigned inep5  : 1;
23275 +               unsigned inep6  : 1;
23276 +               unsigned inep7  : 1;
23277 +               unsigned inep8  : 1;
23278 +               unsigned inep9  : 1;
23279 +               unsigned inep10 : 1;
23280 +               unsigned inep11 : 1;
23281 +               unsigned inep12 : 1;
23282 +               unsigned inep13 : 1;
23283 +               unsigned inep14 : 1;
23284 +               unsigned inep15 : 1;
23285 +               /** OUT Endpoint bits */
23286 +               unsigned outep0  : 1;
23287 +               unsigned outep1  : 1;
23288 +               unsigned outep2  : 1;
23289 +               unsigned outep3  : 1;
23290 +               unsigned outep4  : 1;
23291 +               unsigned outep5  : 1;
23292 +               unsigned outep6  : 1;
23293 +               unsigned outep7  : 1;
23294 +               unsigned outep8  : 1;
23295 +               unsigned outep9  : 1;
23296 +               unsigned outep10 : 1;
23297 +               unsigned outep11 : 1;
23298 +               unsigned outep12 : 1;
23299 +               unsigned outep13 : 1;
23300 +               unsigned outep14 : 1;
23301 +               unsigned outep15 : 1;
23302 +       } b;
23303 +} daint_data_t;
23304 +
23305 +/**
23306 + * This union represents the bit fields in the Device IN Token Queue
23307 + * Read Registers.
23308 + * - Read the register into the <i>d32</i> member.
23309 + * - READ-ONLY Register
23310 + */
23311 +typedef union dtknq1_data
23312 +{
23313 +       /** raw register data */
23314 +       uint32_t d32;
23315 +       /** register bits */
23316 +       struct
23317 +       {
23318 +               /** In Token Queue Write Pointer */
23319 +               unsigned intknwptr : 5;
23320 +               /** Reserved */
23321 +               unsigned reserved05_06 : 2;
23322 +               /** write pointer has wrapped. */
23323 +               unsigned wrap_bit : 1;
23324 +               /** EP Numbers of IN Tokens 0 ... 4 */
23325 +               unsigned epnums0_5 : 24;
23326 +       }b;
23327 +} dtknq1_data_t;
23328 +
23329 +/**
23330 + * This union represents Threshold control Register
23331 + * - Read and write the register into the <i>d32</i> member.
23332 + * - READ-WRITABLE Register
23333 + */
23334 +typedef union dthrctl_data
23335 +{
23336 +       /** raw register data */
23337 +       uint32_t d32;
23338 +       /** register bits */
23339 +       struct
23340 +       {
23341 +               /** non ISO Tx Thr. Enable */
23342 +               unsigned non_iso_thr_en : 1;
23343 +               /** ISO Tx Thr. Enable */
23344 +               unsigned iso_thr_en : 1;
23345 +               /** Tx Thr. Length */
23346 +               unsigned tx_thr_len : 9;
23347 +               /** Reserved */
23348 +               unsigned reserved11_15 : 5;
23349 +               /** Rx Thr. Enable */
23350 +               unsigned rx_thr_en : 1;
23351 +               /** Rx Thr. Length */
23352 +               unsigned rx_thr_len : 9;
23353 +               /** Reserved */
23354 +               unsigned reserved26_31 : 6;
23355 +       }b;
23356 +} dthrctl_data_t;
23357 +
23358 +
23359 +/**
23360 + * Device Logical IN Endpoint-Specific Registers. <i>Offsets
23361 + * 900h-AFCh</i>
23362 + *
23363 + * There will be one set of endpoint registers per logical endpoint
23364 + * implemented.
23365 + *
23366 + * <i>These registers are visible only in Device mode and must not be
23367 + * accessed in Host mode, as the results are unknown.</i>
23368 + */
23369 +typedef struct dwc_otg_dev_in_ep_regs
23370 +{
23371 +       /** Device IN Endpoint Control Register. <i>Offset:900h +
23372 +        * (ep_num * 20h) + 00h</i> */
23373 +       volatile uint32_t diepctl;
23374 +       /** Reserved. <i>Offset:900h + (ep_num * 20h) + 04h</i> */
23375 +       uint32_t reserved04;
23376 +       /** Device IN Endpoint Interrupt Register. <i>Offset:900h +
23377 +        * (ep_num * 20h) + 08h</i> */
23378 +       volatile uint32_t diepint;
23379 +       /** Reserved. <i>Offset:900h + (ep_num * 20h) + 0Ch</i> */
23380 +       uint32_t reserved0C;
23381 +       /** Device IN Endpoint Transfer Size
23382 +        * Register. <i>Offset:900h + (ep_num * 20h) + 10h</i> */
23383 +       volatile uint32_t dieptsiz;
23384 +       /** Device IN Endpoint DMA Address Register. <i>Offset:900h +
23385 +        * (ep_num * 20h) + 14h</i> */
23386 +       volatile uint32_t diepdma;
23387 +       /** Device IN Endpoint Transmit FIFO Status Register. <i>Offset:900h +
23388 +        * (ep_num * 20h) + 18h</i> */
23389 +       volatile uint32_t dtxfsts;
23390 +       /** Device IN Endpoint DMA Buffer Register. <i>Offset:900h +
23391 +        * (ep_num * 20h) + 1Ch</i> */
23392 +       volatile uint32_t diepdmab;
23393 +} dwc_otg_dev_in_ep_regs_t;
23394 +
23395 +/**
23396 + * Device Logical OUT Endpoint-Specific Registers. <i>Offsets:
23397 + * B00h-CFCh</i>
23398 + *
23399 + * There will be one set of endpoint registers per logical endpoint
23400 + * implemented.
23401 + *
23402 + * <i>These registers are visible only in Device mode and must not be
23403 + * accessed in Host mode, as the results are unknown.</i>
23404 + */
23405 +typedef struct dwc_otg_dev_out_ep_regs
23406 +{
23407 +       /** Device OUT Endpoint Control Register. <i>Offset:B00h +
23408 +        * (ep_num * 20h) + 00h</i> */
23409 +       volatile uint32_t doepctl;
23410 +       /** Device OUT Endpoint Frame number Register.  <i>Offset:
23411 +        * B00h + (ep_num * 20h) + 04h</i> */
23412 +       volatile uint32_t doepfn;
23413 +       /** Device OUT Endpoint Interrupt Register. <i>Offset:B00h +
23414 +        * (ep_num * 20h) + 08h</i> */
23415 +       volatile uint32_t doepint;
23416 +       /** Reserved. <i>Offset:B00h + (ep_num * 20h) + 0Ch</i> */
23417 +       uint32_t reserved0C;
23418 +       /** Device OUT Endpoint Transfer Size Register. <i>Offset:
23419 +        * B00h + (ep_num * 20h) + 10h</i> */
23420 +       volatile uint32_t doeptsiz;
23421 +       /** Device OUT Endpoint DMA Address Register. <i>Offset:B00h
23422 +        * + (ep_num * 20h) + 14h</i> */
23423 +       volatile uint32_t doepdma;
23424 +       /** Reserved. <i>Offset:B00h +   * (ep_num * 20h) + 1Ch</i> */
23425 +       uint32_t unused;
23426 +       /** Device OUT Endpoint DMA Buffer Register. <i>Offset:B00h
23427 +        * + (ep_num * 20h) + 1Ch</i> */
23428 +       uint32_t doepdmab;
23429 +} dwc_otg_dev_out_ep_regs_t;
23430 +
23431 +/**
23432 + * This union represents the bit fields in the Device EP Control
23433 + * Register.  Read the register into the <i>d32</i> member then
23434 + * set/clear the bits using the <i>b</i>it elements.
23435 + */
23436 +typedef union depctl_data
23437 +{
23438 +       /** raw register data */
23439 +       uint32_t d32;
23440 +       /** register bits */
23441 +       struct
23442 +       {
23443 +               /** Maximum Packet Size
23444 +                * IN/OUT EPn
23445 +                * IN/OUT EP0 - 2 bits
23446 +                *       2'b00: 64 Bytes
23447 +                *       2'b01: 32
23448 +                *       2'b10: 16
23449 +                *       2'b11: 8 */
23450 +               unsigned mps : 11;
23451 +#define DWC_DEP0CTL_MPS_64      0
23452 +#define DWC_DEP0CTL_MPS_32      1
23453 +#define DWC_DEP0CTL_MPS_16      2
23454 +#define DWC_DEP0CTL_MPS_8       3
23455 +
23456 +               /** Next Endpoint
23457 +                * IN EPn/IN EP0
23458 +                * OUT EPn/OUT EP0 - reserved */
23459 +               unsigned nextep : 4;
23460 +
23461 +               /** USB Active Endpoint */
23462 +               unsigned usbactep : 1;
23463 +
23464 +               /** Endpoint DPID (INTR/Bulk IN and OUT endpoints)
23465 +                * This field contains the PID of the packet going to
23466 +                * be received or transmitted on this endpoint. The
23467 +                * application should program the PID of the first
23468 +                * packet going to be received or transmitted on this
23469 +                * endpoint , after the endpoint is
23470 +                * activated. Application use the SetD1PID and
23471 +                * SetD0PID fields of this register to program either
23472 +                * D0 or D1 PID.
23473 +                *
23474 +                * The encoding for this field is
23475 +                *       - 0: D0
23476 +                *       - 1: D1
23477 +                */
23478 +               unsigned dpid : 1;
23479 +
23480 +               /** NAK Status */
23481 +               unsigned naksts : 1;
23482 +
23483 +               /** Endpoint Type
23484 +                *      2'b00: Control
23485 +                *      2'b01: Isochronous
23486 +                *      2'b10: Bulk
23487 +                *      2'b11: Interrupt */
23488 +               unsigned eptype : 2;
23489 +
23490 +               /** Snoop Mode
23491 +                * OUT EPn/OUT EP0
23492 +                * IN EPn/IN EP0 - reserved */
23493 +               unsigned snp : 1;
23494 +
23495 +               /** Stall Handshake */
23496 +               unsigned stall : 1;
23497 +
23498 +               /** Tx Fifo Number
23499 +                * IN EPn/IN EP0
23500 +                * OUT EPn/OUT EP0 - reserved */
23501 +               unsigned txfnum : 4;
23502 +
23503 +               /** Clear NAK */
23504 +               unsigned cnak : 1;
23505 +               /** Set NAK */
23506 +               unsigned snak : 1;
23507 +               /** Set DATA0 PID (INTR/Bulk IN and OUT endpoints)
23508 +                * Writing to this field sets the Endpoint DPID (DPID)
23509 +                * field in this register to DATA0. Set Even
23510 +                * (micro)frame (SetEvenFr) (ISO IN and OUT Endpoints)
23511 +                * Writing to this field sets the Even/Odd
23512 +                * (micro)frame (EO_FrNum) field to even (micro)
23513 +                * frame.
23514 +                */
23515 +               unsigned setd0pid : 1;
23516 +               /** Set DATA1 PID (INTR/Bulk IN and OUT endpoints)
23517 +                * Writing to this field sets the Endpoint DPID (DPID)
23518 +                * field in this register to DATA1 Set Odd
23519 +                * (micro)frame (SetOddFr) (ISO IN and OUT Endpoints)
23520 +                * Writing to this field sets the Even/Odd
23521 +                * (micro)frame (EO_FrNum) field to odd (micro) frame.
23522 +                */
23523 +               unsigned setd1pid : 1;
23524 +
23525 +               /** Endpoint Disable */
23526 +               unsigned epdis : 1;
23527 +               /** Endpoint Enable */
23528 +               unsigned epena : 1;
23529 +               } b;
23530 +} depctl_data_t;
23531 +
23532 +/**
23533 + * This union represents the bit fields in the Device EP Transfer
23534 + * Size Register.  Read the register into the <i>d32</i> member then
23535 + * set/clear the bits using the <i>b</i>it elements.
23536 + */
23537 +typedef union deptsiz_data
23538 +{
23539 +               /** raw register data */
23540 +               uint32_t d32;
23541 +               /** register bits */
23542 +               struct {
23543 +               /** Transfer size */
23544 +               unsigned xfersize : 19;
23545 +               /** Packet Count */
23546 +               unsigned pktcnt : 10;
23547 +               /** Multi Count - Periodic IN endpoints */
23548 +               unsigned mc : 2;
23549 +               unsigned reserved : 1;
23550 +               } b;
23551 +} deptsiz_data_t;
23552 +
23553 +/**
23554 + * This union represents the bit fields in the Device EP 0 Transfer
23555 + * Size Register.  Read the register into the <i>d32</i> member then
23556 + * set/clear the bits using the <i>b</i>it elements.
23557 + */
23558 +typedef union deptsiz0_data
23559 +{
23560 +               /** raw register data */
23561 +               uint32_t d32;
23562 +               /** register bits */
23563 +               struct {
23564 +               /** Transfer size */
23565 +               unsigned xfersize : 7;
23566 +                               /** Reserved */
23567 +                               unsigned reserved7_18 : 12;
23568 +               /** Packet Count */
23569 +               unsigned pktcnt : 1;
23570 +                               /** Reserved */
23571 +               unsigned reserved20_28 : 9;
23572 +                               /**Setup Packet Count (DOEPTSIZ0 Only) */
23573 +                               unsigned supcnt : 2;
23574 +                               unsigned reserved31;
23575 +               } b;
23576 +} deptsiz0_data_t;
23577 +
23578 +
23579 +/////////////////////////////////////////////////
23580 +// DMA Descriptor Specific Structures
23581 +//
23582 +
23583 +/** Buffer status definitions */
23584 +
23585 +#define BS_HOST_READY  0x0
23586 +#define BS_DMA_BUSY            0x1
23587 +#define BS_DMA_DONE            0x2
23588 +#define BS_HOST_BUSY   0x3
23589 +
23590 +/** Receive/Transmit status definitions */
23591 +
23592 +#define RTS_SUCCESS            0x0
23593 +#define RTS_BUFFLUSH   0x1
23594 +#define RTS_RESERVED   0x2
23595 +#define RTS_BUFERR             0x3
23596 +
23597 +
23598 +/**
23599 + * This union represents the bit fields in the DMA Descriptor
23600 + * status quadlet. Read the quadlet into the <i>d32</i> member then
23601 + * set/clear the bits using the <i>b</i>it, <i>b_iso_out</i> and
23602 + * <i>b_iso_in</i> elements.
23603 + */
23604 +typedef union desc_sts_data
23605 +{
23606 +               /** raw register data */
23607 +               uint32_t d32;
23608 +               /** quadlet bits */
23609 +               struct {
23610 +               /** Received number of bytes */
23611 +               unsigned bytes : 16;
23612 +
23613 +               unsigned reserved16_22 : 7;
23614 +               /** Multiple Transfer - only for OUT EPs */
23615 +               unsigned mtrf : 1;
23616 +               /** Setup Packet received - only for OUT EPs */
23617 +               unsigned sr : 1;
23618 +               /** Interrupt On Complete */
23619 +               unsigned ioc : 1;
23620 +               /** Short Packet */
23621 +               unsigned sp : 1;
23622 +               /** Last */
23623 +               unsigned l : 1;
23624 +               /** Receive Status */
23625 +               unsigned sts : 2;
23626 +               /** Buffer Status */
23627 +               unsigned bs : 2;
23628 +               } b;
23629 +
23630 +#ifdef DWC_EN_ISOC
23631 +               /** iso out quadlet bits */
23632 +               struct {
23633 +               /** Received number of bytes */
23634 +               unsigned rxbytes : 11;
23635 +
23636 +               unsigned reserved11 : 1;
23637 +               /** Frame Number */
23638 +               unsigned framenum : 11;
23639 +               /** Received ISO Data PID */
23640 +               unsigned pid : 2;
23641 +               /** Interrupt On Complete */
23642 +               unsigned ioc : 1;
23643 +               /** Short Packet */
23644 +               unsigned sp : 1;
23645 +               /** Last */
23646 +               unsigned l : 1;
23647 +               /** Receive Status */
23648 +               unsigned rxsts : 2;
23649 +               /** Buffer Status */
23650 +               unsigned bs : 2;
23651 +               } b_iso_out;
23652 +
23653 +               /** iso in quadlet bits */
23654 +               struct {
23655 +               /** Transmited number of bytes */
23656 +               unsigned txbytes : 12;
23657 +               /** Frame Number */
23658 +               unsigned framenum : 11;
23659 +               /** Transmited ISO Data PID */
23660 +               unsigned pid : 2;
23661 +               /** Interrupt On Complete */
23662 +               unsigned ioc : 1;
23663 +               /** Short Packet */
23664 +               unsigned sp : 1;
23665 +               /** Last */
23666 +               unsigned l : 1;
23667 +               /** Transmit Status */
23668 +               unsigned txsts : 2;
23669 +               /** Buffer Status */
23670 +               unsigned bs : 2;
23671 +               } b_iso_in;
23672 +#endif //DWC_EN_ISOC
23673 +} desc_sts_data_t;
23674 +
23675 +/**
23676 + * DMA Descriptor structure
23677 + *
23678 + * DMA Descriptor structure contains two quadlets:
23679 + * Status quadlet and Data buffer pointer.
23680 + */
23681 +typedef struct dwc_otg_dma_desc
23682 +{
23683 +       /** DMA Descriptor status quadlet */
23684 +       desc_sts_data_t status;
23685 +       /** DMA Descriptor data buffer pointer */
23686 +       dma_addr_t      buf;
23687 +} dwc_otg_dma_desc_t;
23688 +
23689 +/**
23690 + * The dwc_otg_dev_if structure contains information needed to manage
23691 + * the DWC_otg controller acting in device mode. It represents the
23692 + * programming view of the device-specific aspects of the controller.
23693 + */
23694 +typedef struct dwc_otg_dev_if
23695 +{
23696 +       /** Pointer to device Global registers.
23697 +        * Device Global Registers starting at offset 800h
23698 +        */
23699 +       dwc_otg_device_global_regs_t *dev_global_regs;
23700 +#define DWC_DEV_GLOBAL_REG_OFFSET 0x800
23701 +
23702 +       /**
23703 +        * Device Logical IN Endpoint-Specific Registers 900h-AFCh
23704 +        */
23705 +       dwc_otg_dev_in_ep_regs_t         *in_ep_regs[MAX_EPS_CHANNELS];
23706 +#define DWC_DEV_IN_EP_REG_OFFSET 0x900
23707 +#define DWC_EP_REG_OFFSET 0x20
23708 +
23709 +       /** Device Logical OUT Endpoint-Specific Registers B00h-CFCh */
23710 +       dwc_otg_dev_out_ep_regs_t        *out_ep_regs[MAX_EPS_CHANNELS];
23711 +#define DWC_DEV_OUT_EP_REG_OFFSET 0xB00
23712 +
23713 +       /* Device configuration information*/
23714 +       uint8_t  speed;                          /**< Device Speed      0: Unknown, 1: LS, 2:FS, 3: HS */
23715 +       uint8_t  num_in_eps;             /**< Number # of Tx EP range: 0-15 exept ep0 */
23716 +       uint8_t  num_out_eps;            /**< Number # of Rx EP range: 0-15 exept ep 0*/
23717 +
23718 +       /** Size of periodic FIFOs (Bytes) */
23719 +       uint16_t perio_tx_fifo_size[MAX_PERIO_FIFOS];
23720 +
23721 +       /** Size of Tx FIFOs (Bytes) */
23722 +       uint16_t tx_fifo_size[MAX_TX_FIFOS];
23723 +
23724 +       /** Thresholding enable flags and length varaiables **/
23725 +       uint16_t rx_thr_en;
23726 +       uint16_t iso_tx_thr_en;
23727 +       uint16_t non_iso_tx_thr_en;
23728 +
23729 +       uint16_t rx_thr_length;
23730 +       uint16_t tx_thr_length;
23731 +
23732 +       /**
23733 +        * Pointers to the DMA Descriptors for EP0 Control
23734 +        * transfers (virtual and physical)
23735 +        */
23736 +
23737 +       /** 2 descriptors for SETUP packets */
23738 +       uint32_t dma_setup_desc_addr[2];
23739 +       dwc_otg_dma_desc_t* setup_desc_addr[2];
23740 +
23741 +       /** Pointer to Descriptor with latest SETUP packet */
23742 +       dwc_otg_dma_desc_t* psetup;
23743 +
23744 +       /** Index of current SETUP handler descriptor */
23745 +       uint32_t setup_desc_index;
23746 +
23747 +       /** Descriptor for Data In or Status In phases */
23748 +       uint32_t dma_in_desc_addr;
23749 +       dwc_otg_dma_desc_t* in_desc_addr;;
23750 +
23751 +       /** Descriptor for Data Out or Status Out phases */
23752 +       uint32_t dma_out_desc_addr;
23753 +       dwc_otg_dma_desc_t* out_desc_addr;
23754 +
23755 +} dwc_otg_dev_if_t;
23756 +
23757 +
23758 +
23759 +
23760 +/////////////////////////////////////////////////
23761 +// Host Mode Register Structures
23762 +//
23763 +/**
23764 + * The Host Global Registers structure defines the size and relative
23765 + * field offsets for the Host Mode Global Registers.  Host Global
23766 + * Registers offsets 400h-7FFh.
23767 +*/
23768 +typedef struct dwc_otg_host_global_regs
23769 +{
23770 +       /** Host Configuration Register.   <i>Offset: 400h</i> */
23771 +       volatile uint32_t hcfg;
23772 +       /** Host Frame Interval Register.       <i>Offset: 404h</i> */
23773 +       volatile uint32_t hfir;
23774 +       /** Host Frame Number / Frame Remaining Register. <i>Offset: 408h</i> */
23775 +       volatile uint32_t hfnum;
23776 +       /** Reserved.   <i>Offset: 40Ch</i> */
23777 +       uint32_t reserved40C;
23778 +       /** Host Periodic Transmit FIFO/ Queue Status Register. <i>Offset: 410h</i> */
23779 +       volatile uint32_t hptxsts;
23780 +       /** Host All Channels Interrupt Register. <i>Offset: 414h</i> */
23781 +       volatile uint32_t haint;
23782 +       /** Host All Channels Interrupt Mask Register. <i>Offset: 418h</i> */
23783 +       volatile uint32_t haintmsk;
23784 +} dwc_otg_host_global_regs_t;
23785 +
23786 +/**
23787 + * This union represents the bit fields in the Host Configuration Register.
23788 + * Read the register into the <i>d32</i> member then set/clear the bits using
23789 + * the <i>b</i>it elements. Write the <i>d32</i> member to the hcfg register.
23790 + */
23791 +typedef union hcfg_data
23792 +{
23793 +       /** raw register data */
23794 +       uint32_t d32;
23795 +
23796 +       /** register bits */
23797 +       struct
23798 +       {
23799 +               /** FS/LS Phy Clock Select */
23800 +               unsigned fslspclksel : 2;
23801 +#define DWC_HCFG_30_60_MHZ 0
23802 +#define DWC_HCFG_48_MHZ           1
23803 +#define DWC_HCFG_6_MHZ    2
23804 +
23805 +               /** FS/LS Only Support */
23806 +               unsigned fslssupp : 1;
23807 +               } b;
23808 +} hcfg_data_t;
23809 +
23810 +/**
23811 + * This union represents the bit fields in the Host Frame Remaing/Number
23812 + * Register.
23813 + */
23814 +typedef union hfir_data
23815 +{
23816 +       /** raw register data */
23817 +       uint32_t d32;
23818 +
23819 +       /** register bits */
23820 +       struct
23821 +       {
23822 +               unsigned frint : 16;
23823 +               unsigned reserved : 16;
23824 +       } b;
23825 +} hfir_data_t;
23826 +
23827 +/**
23828 + * This union represents the bit fields in the Host Frame Remaing/Number
23829 + * Register.
23830 + */
23831 +typedef union hfnum_data
23832 +{
23833 +       /** raw register data */
23834 +       uint32_t d32;
23835 +
23836 +       /** register bits */
23837 +       struct
23838 +       {
23839 +               unsigned frnum : 16;
23840 +#define DWC_HFNUM_MAX_FRNUM 0x3FFF
23841 +               unsigned frrem : 16;
23842 +       } b;
23843 +} hfnum_data_t;
23844 +
23845 +typedef union hptxsts_data
23846 +{
23847 +       /** raw register data */
23848 +       uint32_t d32;
23849 +
23850 +       /** register bits */
23851 +       struct
23852 +       {
23853 +               unsigned ptxfspcavail : 16;
23854 +               unsigned ptxqspcavail : 8;
23855 +               /** Top of the Periodic Transmit Request Queue
23856 +                *      - bit 24 - Terminate (last entry for the selected channel)
23857 +                *      - bits 26:25 - Token Type
23858 +                *        - 2'b00 - Zero length
23859 +                *        - 2'b01 - Ping
23860 +                *        - 2'b10 - Disable
23861 +                *      - bits 30:27 - Channel Number
23862 +                *      - bit 31 - Odd/even microframe
23863 +                */
23864 +               unsigned ptxqtop_terminate : 1;
23865 +               unsigned ptxqtop_token : 2;
23866 +               unsigned ptxqtop_chnum : 4;
23867 +               unsigned ptxqtop_odd : 1;
23868 +       } b;
23869 +} hptxsts_data_t;
23870 +
23871 +/**
23872 + * This union represents the bit fields in the Host Port Control and Status
23873 + * Register. Read the register into the <i>d32</i> member then set/clear the
23874 + * bits using the <i>b</i>it elements. Write the <i>d32</i> member to the
23875 + * hprt0 register.
23876 + */
23877 +typedef union hprt0_data
23878 +{
23879 +       /** raw register data */
23880 +       uint32_t d32;
23881 +       /** register bits */
23882 +       struct
23883 +       {
23884 +               unsigned prtconnsts : 1;
23885 +               unsigned prtconndet : 1;
23886 +               unsigned prtena : 1;
23887 +               unsigned prtenchng : 1;
23888 +               unsigned prtovrcurract : 1;
23889 +               unsigned prtovrcurrchng : 1;
23890 +               unsigned prtres : 1;
23891 +               unsigned prtsusp : 1;
23892 +               unsigned prtrst : 1;
23893 +               unsigned reserved9 : 1;
23894 +               unsigned prtlnsts : 2;
23895 +               unsigned prtpwr : 1;
23896 +               unsigned prttstctl : 4;
23897 +               unsigned prtspd : 2;
23898 +#define DWC_HPRT0_PRTSPD_HIGH_SPEED 0
23899 +#define DWC_HPRT0_PRTSPD_FULL_SPEED 1
23900 +#define DWC_HPRT0_PRTSPD_LOW_SPEED     2
23901 +               unsigned reserved19_31 : 13;
23902 +       } b;
23903 +} hprt0_data_t;
23904 +
23905 +/**
23906 + * This union represents the bit fields in the Host All Interrupt
23907 + * Register.
23908 + */
23909 +typedef union haint_data
23910 +{
23911 +       /** raw register data */
23912 +       uint32_t d32;
23913 +       /** register bits */
23914 +       struct
23915 +       {
23916 +               unsigned ch0 : 1;
23917 +               unsigned ch1 : 1;
23918 +               unsigned ch2 : 1;
23919 +               unsigned ch3 : 1;
23920 +               unsigned ch4 : 1;
23921 +               unsigned ch5 : 1;
23922 +               unsigned ch6 : 1;
23923 +               unsigned ch7 : 1;
23924 +               unsigned ch8 : 1;
23925 +               unsigned ch9 : 1;
23926 +               unsigned ch10 : 1;
23927 +               unsigned ch11 : 1;
23928 +               unsigned ch12 : 1;
23929 +               unsigned ch13 : 1;
23930 +               unsigned ch14 : 1;
23931 +               unsigned ch15 : 1;
23932 +               unsigned reserved : 16;
23933 +       } b;
23934 +
23935 +       struct
23936 +       {
23937 +               unsigned chint : 16;
23938 +               unsigned reserved : 16;
23939 +       } b2;
23940 +} haint_data_t;
23941 +
23942 +/**
23943 + * This union represents the bit fields in the Host All Interrupt
23944 + * Register.
23945 + */
23946 +typedef union haintmsk_data
23947 +{
23948 +       /** raw register data */
23949 +       uint32_t d32;
23950 +       /** register bits */
23951 +       struct
23952 +       {
23953 +               unsigned ch0 : 1;
23954 +               unsigned ch1 : 1;
23955 +               unsigned ch2 : 1;
23956 +               unsigned ch3 : 1;
23957 +               unsigned ch4 : 1;
23958 +               unsigned ch5 : 1;
23959 +               unsigned ch6 : 1;
23960 +               unsigned ch7 : 1;
23961 +               unsigned ch8 : 1;
23962 +               unsigned ch9 : 1;
23963 +               unsigned ch10 : 1;
23964 +               unsigned ch11 : 1;
23965 +               unsigned ch12 : 1;
23966 +               unsigned ch13 : 1;
23967 +               unsigned ch14 : 1;
23968 +               unsigned ch15 : 1;
23969 +               unsigned reserved : 16;
23970 +       } b;
23971 +
23972 +       struct
23973 +       {
23974 +               unsigned chint : 16;
23975 +               unsigned reserved : 16;
23976 +       } b2;
23977 +} haintmsk_data_t;
23978 +
23979 +/**
23980 + * Host Channel Specific Registers. <i>500h-5FCh</i>
23981 + */
23982 +typedef struct dwc_otg_hc_regs
23983 +{
23984 +       /** Host Channel 0 Characteristic Register. <i>Offset: 500h + (chan_num * 20h) + 00h</i> */
23985 +       volatile uint32_t hcchar;
23986 +       /** Host Channel 0 Split Control Register. <i>Offset: 500h + (chan_num * 20h) + 04h</i> */
23987 +       volatile uint32_t hcsplt;
23988 +       /** Host Channel 0 Interrupt Register. <i>Offset: 500h + (chan_num * 20h) + 08h</i> */
23989 +       volatile uint32_t hcint;
23990 +       /** Host Channel 0 Interrupt Mask Register. <i>Offset: 500h + (chan_num * 20h) + 0Ch</i> */
23991 +       volatile uint32_t hcintmsk;
23992 +       /** Host Channel 0 Transfer Size Register. <i>Offset: 500h + (chan_num * 20h) + 10h</i> */
23993 +       volatile uint32_t hctsiz;
23994 +       /** Host Channel 0 DMA Address Register. <i>Offset: 500h + (chan_num * 20h) + 14h</i> */
23995 +       volatile uint32_t hcdma;
23996 +       /** Reserved.  <i>Offset: 500h + (chan_num * 20h) + 18h - 500h + (chan_num * 20h) + 1Ch</i> */
23997 +       uint32_t reserved[2];
23998 +} dwc_otg_hc_regs_t;
23999 +
24000 +/**
24001 + * This union represents the bit fields in the Host Channel Characteristics
24002 + * Register. Read the register into the <i>d32</i> member then set/clear the
24003 + * bits using the <i>b</i>it elements. Write the <i>d32</i> member to the
24004 + * hcchar register.
24005 + */
24006 +typedef union hcchar_data
24007 +{
24008 +       /** raw register data */
24009 +       uint32_t d32;
24010 +
24011 +       /** register bits */
24012 +       struct
24013 +       {
24014 +               /** Maximum packet size in bytes */
24015 +               unsigned mps : 11;
24016 +
24017 +               /** Endpoint number */
24018 +               unsigned epnum : 4;
24019 +
24020 +               /** 0: OUT, 1: IN */
24021 +               unsigned epdir : 1;
24022 +
24023 +               unsigned reserved : 1;
24024 +
24025 +               /** 0: Full/high speed device, 1: Low speed device */
24026 +               unsigned lspddev : 1;
24027 +
24028 +               /** 0: Control, 1: Isoc, 2: Bulk, 3: Intr */
24029 +               unsigned eptype : 2;
24030 +
24031 +               /** Packets per frame for periodic transfers. 0 is reserved. */
24032 +               unsigned multicnt : 2;
24033 +
24034 +               /** Device address */
24035 +               unsigned devaddr : 7;
24036 +
24037 +               /**
24038 +                * Frame to transmit periodic transaction.
24039 +                * 0: even, 1: odd
24040 +                */
24041 +               unsigned oddfrm : 1;
24042 +
24043 +               /** Channel disable */
24044 +               unsigned chdis : 1;
24045 +
24046 +               /** Channel enable */
24047 +               unsigned chen : 1;
24048 +       } b;
24049 +} hcchar_data_t;
24050 +
24051 +typedef union hcsplt_data
24052 +{
24053 +       /** raw register data */
24054 +       uint32_t d32;
24055 +
24056 +       /** register bits */
24057 +       struct
24058 +       {
24059 +               /** Port Address */
24060 +               unsigned prtaddr : 7;
24061 +
24062 +               /** Hub Address */
24063 +               unsigned hubaddr : 7;
24064 +
24065 +               /** Transaction Position */
24066 +               unsigned xactpos : 2;
24067 +#define DWC_HCSPLIT_XACTPOS_MID 0
24068 +#define DWC_HCSPLIT_XACTPOS_END 1
24069 +#define DWC_HCSPLIT_XACTPOS_BEGIN 2
24070 +#define DWC_HCSPLIT_XACTPOS_ALL 3
24071 +
24072 +               /** Do Complete Split */
24073 +               unsigned compsplt : 1;
24074 +
24075 +               /** Reserved */
24076 +               unsigned reserved : 14;
24077 +
24078 +               /** Split Enble */
24079 +               unsigned spltena : 1;
24080 +       } b;
24081 +} hcsplt_data_t;
24082 +
24083 +
24084 +/**
24085 + * This union represents the bit fields in the Host All Interrupt
24086 + * Register.
24087 + */
24088 +typedef union hcint_data
24089 +{
24090 +       /** raw register data */
24091 +       uint32_t d32;
24092 +       /** register bits */
24093 +       struct
24094 +       {
24095 +               /** Transfer Complete */
24096 +               unsigned xfercomp : 1;
24097 +               /** Channel Halted */
24098 +               unsigned chhltd : 1;
24099 +               /** AHB Error */
24100 +               unsigned ahberr : 1;
24101 +               /** STALL Response Received */
24102 +               unsigned stall : 1;
24103 +               /** NAK Response Received */
24104 +               unsigned nak : 1;
24105 +               /** ACK Response Received */
24106 +               unsigned ack : 1;
24107 +               /** NYET Response Received */
24108 +               unsigned nyet : 1;
24109 +               /** Transaction Err */
24110 +               unsigned xacterr : 1;
24111 +               /** Babble Error */
24112 +               unsigned bblerr : 1;
24113 +               /** Frame Overrun */
24114 +               unsigned frmovrun : 1;
24115 +               /** Data Toggle Error */
24116 +               unsigned datatglerr : 1;
24117 +               /** Reserved */
24118 +               unsigned reserved : 21;
24119 +       } b;
24120 +} hcint_data_t;
24121 +
24122 +/**
24123 + * This union represents the bit fields in the Host Channel Transfer Size
24124 + * Register. Read the register into the <i>d32</i> member then set/clear the
24125 + * bits using the <i>b</i>it elements. Write the <i>d32</i> member to the
24126 + * hcchar register.
24127 + */
24128 +typedef union hctsiz_data
24129 +{
24130 +       /** raw register data */
24131 +       uint32_t d32;
24132 +
24133 +       /** register bits */
24134 +       struct
24135 +       {
24136 +               /** Total transfer size in bytes */
24137 +               unsigned xfersize : 19;
24138 +
24139 +               /** Data packets to transfer */
24140 +               unsigned pktcnt : 10;
24141 +
24142 +               /**
24143 +                * Packet ID for next data packet
24144 +                * 0: DATA0
24145 +                * 1: DATA2
24146 +                * 2: DATA1
24147 +                * 3: MDATA (non-Control), SETUP (Control)
24148 +                */
24149 +               unsigned pid : 2;
24150 +#define DWC_HCTSIZ_DATA0 0
24151 +#define DWC_HCTSIZ_DATA1 2
24152 +#define DWC_HCTSIZ_DATA2 1
24153 +#define DWC_HCTSIZ_MDATA 3
24154 +#define DWC_HCTSIZ_SETUP 3
24155 +
24156 +               /** Do PING protocol when 1 */
24157 +               unsigned dopng : 1;
24158 +       } b;
24159 +} hctsiz_data_t;
24160 +
24161 +/**
24162 + * This union represents the bit fields in the Host Channel Interrupt Mask
24163 + * Register. Read the register into the <i>d32</i> member then set/clear the
24164 + * bits using the <i>b</i>it elements. Write the <i>d32</i> member to the
24165 + * hcintmsk register.
24166 + */
24167 +typedef union hcintmsk_data
24168 +{
24169 +       /** raw register data */
24170 +       uint32_t d32;
24171 +
24172 +       /** register bits */
24173 +       struct
24174 +       {
24175 +               unsigned xfercompl : 1;
24176 +               unsigned chhltd : 1;
24177 +               unsigned ahberr : 1;
24178 +               unsigned stall : 1;
24179 +               unsigned nak : 1;
24180 +               unsigned ack : 1;
24181 +               unsigned nyet : 1;
24182 +               unsigned xacterr : 1;
24183 +               unsigned bblerr : 1;
24184 +               unsigned frmovrun : 1;
24185 +               unsigned datatglerr : 1;
24186 +               unsigned reserved : 21;
24187 +       } b;
24188 +} hcintmsk_data_t;
24189 +
24190 +/** OTG Host Interface Structure.
24191 + *
24192 + * The OTG Host Interface Structure structure contains information
24193 + * needed to manage the DWC_otg controller acting in host mode. It
24194 + * represents the programming view of the host-specific aspects of the
24195 + * controller.
24196 + */
24197 +typedef struct dwc_otg_host_if
24198 +{
24199 +       /** Host Global Registers starting at offset 400h.*/
24200 +       dwc_otg_host_global_regs_t *host_global_regs;
24201 +#define DWC_OTG_HOST_GLOBAL_REG_OFFSET 0x400
24202 +
24203 +       /** Host Port 0 Control and Status Register */
24204 +       volatile uint32_t *hprt0;
24205 +#define DWC_OTG_HOST_PORT_REGS_OFFSET 0x440
24206 +
24207 +
24208 +       /** Host Channel Specific Registers at offsets 500h-5FCh. */
24209 +       dwc_otg_hc_regs_t *hc_regs[MAX_EPS_CHANNELS];
24210 +#define DWC_OTG_HOST_CHAN_REGS_OFFSET 0x500
24211 +#define DWC_OTG_CHAN_REGS_OFFSET 0x20
24212 +
24213 +
24214 +       /* Host configuration information */
24215 +       /** Number of Host Channels (range: 1-16) */
24216 +       uint8_t  num_host_channels;
24217 +       /** Periodic EPs supported (0: no, 1: yes) */
24218 +       uint8_t  perio_eps_supported;
24219 +       /** Periodic Tx FIFO Size (Only 1 host periodic Tx FIFO) */
24220 +       uint16_t perio_tx_fifo_size;
24221 +
24222 +} dwc_otg_host_if_t;
24223 +
24224 +
24225 +/**
24226 + * This union represents the bit fields in the Power and Clock Gating Control
24227 + * Register. Read the register into the <i>d32</i> member then set/clear the
24228 + * bits using the <i>b</i>it elements.
24229 + */
24230 +typedef union pcgcctl_data
24231 +{
24232 +       /** raw register data */
24233 +       uint32_t d32;
24234 +
24235 +       /** register bits */
24236 +       struct
24237 +       {
24238 +               /** Stop Pclk */
24239 +               unsigned stoppclk : 1;
24240 +               /** Gate Hclk */
24241 +               unsigned gatehclk : 1;
24242 +               /** Power Clamp */
24243 +               unsigned pwrclmp : 1;
24244 +               /** Reset Power Down Modules */
24245 +               unsigned rstpdwnmodule : 1;
24246 +               /** PHY Suspended */
24247 +               unsigned physuspended : 1;
24248 +
24249 +               unsigned reserved : 27;
24250 +       } b;
24251 +} pcgcctl_data_t;
24252 +
24253 +
24254 +#endif
24255 --- /dev/null
24256 +++ b/drivers/usb/dwc_otg/linux/dwc_otg_plat.h
24257 @@ -0,0 +1,260 @@
24258 +/* ==========================================================================
24259 + * $File: //dwh/usb_iip/dev/software/otg/linux/platform/dwc_otg_plat.h $
24260 + * $Revision: 1.2 $
24261 + * $Date: 2008-11-21 05:39:16 $
24262 + * $Change: 1064915 $
24263 + *
24264 + * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
24265 + * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
24266 + * otherwise expressly agreed to in writing between Synopsys and you.
24267 + *
24268 + * The Software IS NOT an item of Licensed Software or Licensed Product under
24269 + * any End User Software License Agreement or Agreement for Licensed Product
24270 + * with Synopsys or any supplement thereto. You are permitted to use and
24271 + * redistribute this Software in source and binary forms, with or without
24272 + * modification, provided that redistributions of source code must retain this
24273 + * notice. You may not view, use, disclose, copy or distribute this file or
24274 + * any information contained herein except pursuant to this license grant from
24275 + * Synopsys. If you do not agree with this notice, including the disclaimer
24276 + * below, then you are not authorized to use the Software.
24277 + *
24278 + * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
24279 + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
24280 + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24281 + * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
24282 + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
24283 + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
24284 + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
24285 + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24286 + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24287 + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
24288 + * DAMAGE.
24289 + * ========================================================================== */
24290 +
24291 +#if !defined(__DWC_OTG_PLAT_H__)
24292 +#define __DWC_OTG_PLAT_H__
24293 +
24294 +#include <linux/types.h>
24295 +#include <linux/slab.h>
24296 +#include <linux/list.h>
24297 +#include <linux/delay.h>
24298 +#include <asm/io.h>
24299 +
24300 +/**
24301 + * @file
24302 + *
24303 + * This file contains the Platform Specific constants, interfaces
24304 + * (functions and macros) for Linux.
24305 + *
24306 + */
24307 +//#if !defined(__LINUX_ARM_ARCH__)
24308 +//#error "The contents of this file is Linux specific!!!"
24309 +//#endif
24310 +
24311 +/**
24312 + * Reads the content of a register.
24313 + *
24314 + * @param reg address of register to read.
24315 + * @return contents of the register.
24316 + *
24317 +
24318 + * Usage:<br>
24319 + * <code>uint32_t dev_ctl = dwc_read_reg32(&dev_regs->dctl);</code>
24320 + */
24321 +static __inline__ uint32_t dwc_read_reg32( volatile uint32_t *reg)
24322 +{
24323 +        return readl(reg);
24324 +};
24325 +
24326 +/**
24327 + * Writes a register with a 32 bit value.
24328 + *
24329 + * @param reg address of register to read.
24330 + * @param value to write to _reg.
24331 + *
24332 + * Usage:<br>
24333 + * <code>dwc_write_reg32(&dev_regs->dctl, 0); </code>
24334 + */
24335 +static __inline__ void dwc_write_reg32( volatile uint32_t *reg, const uint32_t value)
24336 +{
24337 +        writel( value, reg );
24338 +};
24339 +
24340 +/**
24341 + * This function modifies bit values in a register.  Using the
24342 + * algorithm: (reg_contents & ~clear_mask) | set_mask.
24343 + *
24344 + * @param reg address of register to read.
24345 + * @param clear_mask bit mask to be cleared.
24346 + * @param set_mask bit mask to be set.
24347 + *
24348 + * Usage:<br>
24349 + * <code> // Clear the SOF Interrupt Mask bit and <br>
24350 + * // set the OTG Interrupt mask bit, leaving all others as they were.
24351 + *    dwc_modify_reg32(&dev_regs->gintmsk, DWC_SOF_INT, DWC_OTG_INT);</code>
24352 + */
24353 +static __inline__
24354 + void dwc_modify_reg32( volatile uint32_t *reg, const uint32_t clear_mask, const uint32_t set_mask)
24355 +{
24356 +        writel( (readl(reg) & ~clear_mask) | set_mask, reg );
24357 +};
24358 +
24359 +
24360 +/**
24361 + * Wrapper for the OS micro-second delay function.
24362 + * @param[in] usecs Microseconds of delay
24363 + */
24364 +static __inline__ void UDELAY( const uint32_t usecs )
24365 +{
24366 +        udelay( usecs );
24367 +}
24368 +
24369 +/**
24370 + * Wrapper for the OS milli-second delay function.
24371 + * @param[in] msecs milliseconds of delay
24372 + */
24373 +static __inline__ void MDELAY( const uint32_t msecs )
24374 +{
24375 +        mdelay( msecs );
24376 +}
24377 +
24378 +/**
24379 + * Wrapper for the Linux spin_lock.  On the ARM (Integrator)
24380 + * spin_lock() is a nop.
24381 + *
24382 + * @param lock Pointer to the spinlock.
24383 + */
24384 +static __inline__ void SPIN_LOCK( spinlock_t *lock )
24385 +{
24386 +        spin_lock(lock);
24387 +}
24388 +
24389 +/**
24390 + * Wrapper for the Linux spin_unlock.  On the ARM (Integrator)
24391 + * spin_lock() is a nop.
24392 + *
24393 + * @param lock Pointer to the spinlock.
24394 + */
24395 +static __inline__ void SPIN_UNLOCK( spinlock_t *lock )
24396 +{
24397 +        spin_unlock(lock);
24398 +}
24399 +
24400 +/**
24401 + * Wrapper (macro) for the Linux spin_lock_irqsave.  On the ARM
24402 + * (Integrator) spin_lock() is a nop.
24403 + *
24404 + * @param l Pointer to the spinlock.
24405 + * @param f unsigned long for irq flags storage.
24406 + */
24407 +#define SPIN_LOCK_IRQSAVE( l, f )  spin_lock_irqsave(l,f);
24408 +
24409 +/**
24410 + * Wrapper (macro) for the Linux spin_unlock_irqrestore.  On the ARM
24411 + * (Integrator) spin_lock() is a nop.
24412 + *
24413 + * @param l Pointer to the spinlock.
24414 + * @param f unsigned long for irq flags storage.
24415 + */
24416 +#define SPIN_UNLOCK_IRQRESTORE( l,f ) spin_unlock_irqrestore(l,f);
24417 +
24418 +/*
24419 + * Debugging support vanishes in non-debug builds.
24420 + */
24421 +
24422 +
24423 +/**
24424 + * The Debug Level bit-mask variable.
24425 + */
24426 +extern uint32_t g_dbg_lvl;
24427 +/**
24428 + * Set the Debug Level variable.
24429 + */
24430 +static inline uint32_t SET_DEBUG_LEVEL( const uint32_t new )
24431 +{
24432 +        uint32_t old = g_dbg_lvl;
24433 +        g_dbg_lvl = new;
24434 +        return old;
24435 +}
24436 +
24437 +/** When debug level has the DBG_CIL bit set, display CIL Debug messages. */
24438 +#define DBG_CIL                (0x2)
24439 +/** When debug level has the DBG_CILV bit set, display CIL Verbose debug
24440 + * messages */
24441 +#define DBG_CILV       (0x20)
24442 +/**  When debug level has the DBG_PCD bit set, display PCD (Device) debug
24443 + *  messages */
24444 +#define DBG_PCD                (0x4)
24445 +/** When debug level has the DBG_PCDV set, display PCD (Device) Verbose debug
24446 + * messages */
24447 +#define DBG_PCDV       (0x40)
24448 +/** When debug level has the DBG_HCD bit set, display Host debug messages */
24449 +#define DBG_HCD                (0x8)
24450 +/** When debug level has the DBG_HCDV bit set, display Verbose Host debug
24451 + * messages */
24452 +#define DBG_HCDV       (0x80)
24453 +/** When debug level has the DBG_HCD_URB bit set, display enqueued URBs in host
24454 + *  mode. */
24455 +#define DBG_HCD_URB    (0x800)
24456 +
24457 +/** When debug level has any bit set, display debug messages */
24458 +#define DBG_ANY                (0xFF)
24459 +
24460 +/** All debug messages off */
24461 +#define DBG_OFF                0
24462 +
24463 +/** Prefix string for DWC_DEBUG print macros. */
24464 +#define USB_DWC "dwc_otg: "
24465 +
24466 +/**
24467 + * Print a debug message when the Global debug level variable contains
24468 + * the bit defined in <code>lvl</code>.
24469 + *
24470 + * @param[in] lvl - Debug level, use one of the DBG_ constants above.
24471 + * @param[in] x - like printf
24472 + *
24473 + *    Example:<p>
24474 + * <code>
24475 + *      DWC_DEBUGPL( DBG_ANY, "%s(%p)\n", __func__, _reg_base_addr);
24476 + * </code>
24477 + * <br>
24478 + * results in:<br>
24479 + * <code>
24480 + * usb-DWC_otg: dwc_otg_cil_init(ca867000)
24481 + * </code>
24482 + */
24483 +#ifdef DEBUG
24484 +
24485 +# define DWC_DEBUGPL(lvl, x...) do{ if ((lvl)&g_dbg_lvl)printk( KERN_DEBUG USB_DWC x ); }while(0)
24486 +# define DWC_DEBUGP(x...)      DWC_DEBUGPL(DBG_ANY, x )
24487 +
24488 +# define CHK_DEBUG_LEVEL(level) ((level) & g_dbg_lvl)
24489 +
24490 +#else
24491 +
24492 +# define DWC_DEBUGPL(lvl, x...) do{}while(0)
24493 +# define DWC_DEBUGP(x...)
24494 +
24495 +# define CHK_DEBUG_LEVEL(level) (0)
24496 +
24497 +#endif /*DEBUG*/
24498 +
24499 +/**
24500 + * Print an Error message.
24501 + */
24502 +#define DWC_ERROR(x...) printk( KERN_ERR USB_DWC x )
24503 +/**
24504 + * Print a Warning message.
24505 + */
24506 +#define DWC_WARN(x...) printk( KERN_WARNING USB_DWC x )
24507 +/**
24508 + * Print a notice (normal but significant message).
24509 + */
24510 +#define DWC_NOTICE(x...) printk( KERN_NOTICE USB_DWC x )
24511 +/**
24512 + *  Basic message printing.
24513 + */
24514 +#define DWC_PRINT(x...) printk( KERN_INFO USB_DWC x )
24515 +
24516 +#endif
24517 +