target/linux/generic/files/drivers/net/phy/ar8216.c

   1 /*
   2  * ar8216.c: AR8216 switch driver
   3  *
   4  * Copyright (C) 2009 Felix Fietkau <nbd@openwrt.org>
   5  * Copyright (C) 2011-2012 Gabor Juhos <juhosg@openwrt.org>
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License
   9  * as published by the Free Software Foundation; either version 2
  10  * of the License, or (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  */
  17
  18 #include <linux/if.h>
  19 #include <linux/module.h>
  20 #include <linux/init.h>
  21 #include <linux/list.h>
  22 #include <linux/if_ether.h>
  23 #include <linux/skbuff.h>
  24 #include <linux/netdevice.h>
  25 #include <linux/netlink.h>
  26 #include <linux/bitops.h>
  27 #include <net/genetlink.h>
  28 #include <linux/switch.h>
  29 #include <linux/delay.h>
  30 #include <linux/phy.h>
  31 #include <linux/netdevice.h>
  32 #include <linux/etherdevice.h>
  33 #include <linux/lockdep.h>
  34 #include <linux/ar8216_platform.h>
  35 #include <linux/workqueue.h>
  36 #include <linux/version.h>
  37
  38 #include "ar8216.h"
  39
  40 extern const struct ar8xxx_chip ar8327_chip;
  41 extern const struct ar8xxx_chip ar8337_chip;
  42
  43 #define AR8XXX_MIB_WORK_DELAY   2000 /* msecs */
  44
  45 #define MIB_DESC(_s , _o, _n)   \
  46         {                       \
  47                 .size = (_s),   \
  48                 .offset = (_o), \
  49                 .name = (_n),   \
  50         }
  51
  52 static const struct ar8xxx_mib_desc ar8216_mibs[] = {
  53         MIB_DESC(1, AR8216_STATS_RXBROAD, "RxBroad"),
  54         MIB_DESC(1, AR8216_STATS_RXPAUSE, "RxPause"),
  55         MIB_DESC(1, AR8216_STATS_RXMULTI, "RxMulti"),
  56         MIB_DESC(1, AR8216_STATS_RXFCSERR, "RxFcsErr"),
  57         MIB_DESC(1, AR8216_STATS_RXALIGNERR, "RxAlignErr"),
  58         MIB_DESC(1, AR8216_STATS_RXRUNT, "RxRunt"),
  59         MIB_DESC(1, AR8216_STATS_RXFRAGMENT, "RxFragment"),
  60         MIB_DESC(1, AR8216_STATS_RX64BYTE, "Rx64Byte"),
  61         MIB_DESC(1, AR8216_STATS_RX128BYTE, "Rx128Byte"),
  62         MIB_DESC(1, AR8216_STATS_RX256BYTE, "Rx256Byte"),
  63         MIB_DESC(1, AR8216_STATS_RX512BYTE, "Rx512Byte"),
  64         MIB_DESC(1, AR8216_STATS_RX1024BYTE, "Rx1024Byte"),
  65         MIB_DESC(1, AR8216_STATS_RXMAXBYTE, "RxMaxByte"),
  66         MIB_DESC(1, AR8216_STATS_RXTOOLONG, "RxTooLong"),
  67         MIB_DESC(2, AR8216_STATS_RXGOODBYTE, "RxGoodByte"),
  68         MIB_DESC(2, AR8216_STATS_RXBADBYTE, "RxBadByte"),
  69         MIB_DESC(1, AR8216_STATS_RXOVERFLOW, "RxOverFlow"),
  70         MIB_DESC(1, AR8216_STATS_FILTERED, "Filtered"),
  71         MIB_DESC(1, AR8216_STATS_TXBROAD, "TxBroad"),
  72         MIB_DESC(1, AR8216_STATS_TXPAUSE, "TxPause"),
  73         MIB_DESC(1, AR8216_STATS_TXMULTI, "TxMulti"),
  74         MIB_DESC(1, AR8216_STATS_TXUNDERRUN, "TxUnderRun"),
  75         MIB_DESC(1, AR8216_STATS_TX64BYTE, "Tx64Byte"),
  76         MIB_DESC(1, AR8216_STATS_TX128BYTE, "Tx128Byte"),
  77         MIB_DESC(1, AR8216_STATS_TX256BYTE, "Tx256Byte"),
  78         MIB_DESC(1, AR8216_STATS_TX512BYTE, "Tx512Byte"),
  79         MIB_DESC(1, AR8216_STATS_TX1024BYTE, "Tx1024Byte"),
  80         MIB_DESC(1, AR8216_STATS_TXMAXBYTE, "TxMaxByte"),
  81         MIB_DESC(1, AR8216_STATS_TXOVERSIZE, "TxOverSize"),
  82         MIB_DESC(2, AR8216_STATS_TXBYTE, "TxByte"),
  83         MIB_DESC(1, AR8216_STATS_TXCOLLISION, "TxCollision"),
  84         MIB_DESC(1, AR8216_STATS_TXABORTCOL, "TxAbortCol"),
  85         MIB_DESC(1, AR8216_STATS_TXMULTICOL, "TxMultiCol"),
  86         MIB_DESC(1, AR8216_STATS_TXSINGLECOL, "TxSingleCol"),
  87         MIB_DESC(1, AR8216_STATS_TXEXCDEFER, "TxExcDefer"),
  88         MIB_DESC(1, AR8216_STATS_TXDEFER, "TxDefer"),
  89         MIB_DESC(1, AR8216_STATS_TXLATECOL, "TxLateCol"),
  90 };
  91
  92 const struct ar8xxx_mib_desc ar8236_mibs[39] = {
  93         MIB_DESC(1, AR8236_STATS_RXBROAD, "RxBroad"),
  94         MIB_DESC(1, AR8236_STATS_RXPAUSE, "RxPause"),
  95         MIB_DESC(1, AR8236_STATS_RXMULTI, "RxMulti"),
  96         MIB_DESC(1, AR8236_STATS_RXFCSERR, "RxFcsErr"),
  97         MIB_DESC(1, AR8236_STATS_RXALIGNERR, "RxAlignErr"),
  98         MIB_DESC(1, AR8236_STATS_RXRUNT, "RxRunt"),
  99         MIB_DESC(1, AR8236_STATS_RXFRAGMENT, "RxFragment"),
 100         MIB_DESC(1, AR8236_STATS_RX64BYTE, "Rx64Byte"),
 101         MIB_DESC(1, AR8236_STATS_RX128BYTE, "Rx128Byte"),
 102         MIB_DESC(1, AR8236_STATS_RX256BYTE, "Rx256Byte"),
 103         MIB_DESC(1, AR8236_STATS_RX512BYTE, "Rx512Byte"),
 104         MIB_DESC(1, AR8236_STATS_RX1024BYTE, "Rx1024Byte"),
 105         MIB_DESC(1, AR8236_STATS_RX1518BYTE, "Rx1518Byte"),
 106         MIB_DESC(1, AR8236_STATS_RXMAXBYTE, "RxMaxByte"),
 107         MIB_DESC(1, AR8236_STATS_RXTOOLONG, "RxTooLong"),
 108         MIB_DESC(2, AR8236_STATS_RXGOODBYTE, "RxGoodByte"),
 109         MIB_DESC(2, AR8236_STATS_RXBADBYTE, "RxBadByte"),
 110         MIB_DESC(1, AR8236_STATS_RXOVERFLOW, "RxOverFlow"),
 111         MIB_DESC(1, AR8236_STATS_FILTERED, "Filtered"),
 112         MIB_DESC(1, AR8236_STATS_TXBROAD, "TxBroad"),
 113         MIB_DESC(1, AR8236_STATS_TXPAUSE, "TxPause"),
 114         MIB_DESC(1, AR8236_STATS_TXMULTI, "TxMulti"),
 115         MIB_DESC(1, AR8236_STATS_TXUNDERRUN, "TxUnderRun"),
 116         MIB_DESC(1, AR8236_STATS_TX64BYTE, "Tx64Byte"),
 117         MIB_DESC(1, AR8236_STATS_TX128BYTE, "Tx128Byte"),
 118         MIB_DESC(1, AR8236_STATS_TX256BYTE, "Tx256Byte"),
 119         MIB_DESC(1, AR8236_STATS_TX512BYTE, "Tx512Byte"),
 120         MIB_DESC(1, AR8236_STATS_TX1024BYTE, "Tx1024Byte"),
 121         MIB_DESC(1, AR8236_STATS_TX1518BYTE, "Tx1518Byte"),
 122         MIB_DESC(1, AR8236_STATS_TXMAXBYTE, "TxMaxByte"),
 123         MIB_DESC(1, AR8236_STATS_TXOVERSIZE, "TxOverSize"),
 124         MIB_DESC(2, AR8236_STATS_TXBYTE, "TxByte"),
 125         MIB_DESC(1, AR8236_STATS_TXCOLLISION, "TxCollision"),
 126         MIB_DESC(1, AR8236_STATS_TXABORTCOL, "TxAbortCol"),
 127         MIB_DESC(1, AR8236_STATS_TXMULTICOL, "TxMultiCol"),
 128         MIB_DESC(1, AR8236_STATS_TXSINGLECOL, "TxSingleCol"),
 129         MIB_DESC(1, AR8236_STATS_TXEXCDEFER, "TxExcDefer"),
 130         MIB_DESC(1, AR8236_STATS_TXDEFER, "TxDefer"),
 131         MIB_DESC(1, AR8236_STATS_TXLATECOL, "TxLateCol"),
 132 };
 133
 134 static DEFINE_MUTEX(ar8xxx_dev_list_lock);
 135 static LIST_HEAD(ar8xxx_dev_list);
 136
 137 static inline void
 138 split_addr(u32 regaddr, u16 *r1, u16 *r2, u16 *page)
 139 {
 140         regaddr >>= 1;
 141         *r1 = regaddr & 0x1e;
 142
 143         regaddr >>= 5;
 144         *r2 = regaddr & 0x7;
 145
 146         regaddr >>= 3;
 147         *page = regaddr & 0x1ff;
 148 }
 149
 150 /* inspired by phy_poll_reset in drivers/net/phy/phy_device.c */
 151 static int
 152 ar8xxx_phy_poll_reset(struct mii_bus *bus)
 153 {
 154         unsigned int sleep_msecs = 20;
 155         int ret, elapsed, i;
 156
 157         for (elapsed = sleep_msecs; elapsed <= 600;
 158              elapsed += sleep_msecs) {
 159                 msleep(sleep_msecs);
 160                 for (i = 0; i < AR8XXX_NUM_PHYS; i++) {
 161                         ret = mdiobus_read(bus, i, MII_BMCR);
 162                         if (ret < 0)
 163                                 return ret;
 164                         if (ret & BMCR_RESET)
 165                                 break;
 166                         if (i == AR8XXX_NUM_PHYS - 1) {
 167                                 usleep_range(1000, 2000);
 168                                 return 0;
 169                         }
 170                 }
 171         }
 172         return -ETIMEDOUT;
 173 }
 174
 175 static int
 176 ar8xxx_phy_check_aneg(struct phy_device *phydev)
 177 {
 178         int ret;
 179
 180         if (phydev->autoneg != AUTONEG_ENABLE)
 181                 return 0;
 182         /*
 183          * BMCR_ANENABLE might have been cleared
 184          * by phy_init_hw in certain kernel versions
 185          * therefore check for it
 186          */
 187         ret = phy_read(phydev, MII_BMCR);
 188         if (ret < 0)
 189                 return ret;
 190         if (ret & BMCR_ANENABLE)
 191                 return 0;
 192
 193         dev_info(&phydev->dev, "ANEG disabled, re-enabling ...\n");
 194         ret |= BMCR_ANENABLE | BMCR_ANRESTART;
 195         return phy_write(phydev, MII_BMCR, ret);
 196 }
 197
 198 void
 199 ar8xxx_phy_init(struct ar8xxx_priv *priv)
 200 {
 201         int i;
 202         struct mii_bus *bus;
 203
 204         bus = priv->mii_bus;
 205         for (i = 0; i < AR8XXX_NUM_PHYS; i++) {
 206                 if (priv->chip->phy_fixup)
 207                         priv->chip->phy_fixup(priv, i);
 208
 209                 /* initialize the port itself */
 210                 mdiobus_write(bus, i, MII_ADVERTISE,
 211                         ADVERTISE_ALL | ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
 212                 if (ar8xxx_has_gige(priv))
 213                         mdiobus_write(bus, i, MII_CTRL1000, ADVERTISE_1000FULL);
 214                 mdiobus_write(bus, i, MII_BMCR, BMCR_RESET | BMCR_ANENABLE);
 215         }
 216
 217         ar8xxx_phy_poll_reset(bus);
 218 }
 219
 220 static u32
 221 mii_read32(struct ar8xxx_priv *priv, int phy_id, int regnum)
 222 {
 223         struct mii_bus *bus = priv->mii_bus;
 224         u16 lo, hi;
 225
 226         lo = bus->read(bus, phy_id, regnum);
 227         hi = bus->read(bus, phy_id, regnum + 1);
 228
 229         return (hi << 16) | lo;
 230 }
 231
 232 static void
 233 mii_write32(struct ar8xxx_priv *priv, int phy_id, int regnum, u32 val)
 234 {
 235         struct mii_bus *bus = priv->mii_bus;
 236         u16 lo, hi;
 237
 238         lo = val & 0xffff;
 239         hi = (u16) (val >> 16);
 240
 241         if (priv->chip->mii_lo_first)
 242         {
 243                 bus->write(bus, phy_id, regnum, lo);
 244                 bus->write(bus, phy_id, regnum + 1, hi);
 245         } else {
 246                 bus->write(bus, phy_id, regnum + 1, hi);
 247                 bus->write(bus, phy_id, regnum, lo);
 248         }
 249 }
 250
 251 u32
 252 ar8xxx_read(struct ar8xxx_priv *priv, int reg)
 253 {
 254         struct mii_bus *bus = priv->mii_bus;
 255         u16 r1, r2, page;
 256         u32 val;
 257
 258         split_addr((u32) reg, &r1, &r2, &page);
 259
 260         mutex_lock(&bus->mdio_lock);
 261
 262         bus->write(bus, 0x18, 0, page);
 263         usleep_range(1000, 2000); /* wait for the page switch to propagate */
 264         val = mii_read32(priv, 0x10 | r2, r1);
 265
 266         mutex_unlock(&bus->mdio_lock);
 267
 268         return val;
 269 }
 270
 271 void
 272 ar8xxx_write(struct ar8xxx_priv *priv, int reg, u32 val)
 273 {
 274         struct mii_bus *bus = priv->mii_bus;
 275         u16 r1, r2, page;
 276
 277         split_addr((u32) reg, &r1, &r2, &page);
 278
 279         mutex_lock(&bus->mdio_lock);
 280
 281         bus->write(bus, 0x18, 0, page);
 282         usleep_range(1000, 2000); /* wait for the page switch to propagate */
 283         mii_write32(priv, 0x10 | r2, r1, val);
 284
 285         mutex_unlock(&bus->mdio_lock);
 286 }
 287
 288 u32
 289 ar8xxx_rmw(struct ar8xxx_priv *priv, int reg, u32 mask, u32 val)
 290 {
 291         struct mii_bus *bus = priv->mii_bus;
 292         u16 r1, r2, page;
 293         u32 ret;
 294
 295         split_addr((u32) reg, &r1, &r2, &page);
 296
 297         mutex_lock(&bus->mdio_lock);
 298
 299         bus->write(bus, 0x18, 0, page);
 300         usleep_range(1000, 2000); /* wait for the page switch to propagate */
 301
 302         ret = mii_read32(priv, 0x10 | r2, r1);
 303         ret &= ~mask;
 304         ret |= val;
 305         mii_write32(priv, 0x10 | r2, r1, ret);
 306
 307         mutex_unlock(&bus->mdio_lock);
 308
 309         return ret;
 310 }
 311
 312 void
 313 ar8xxx_phy_dbg_write(struct ar8xxx_priv *priv, int phy_addr,
 314                      u16 dbg_addr, u16 dbg_data)
 315 {
 316         struct mii_bus *bus = priv->mii_bus;
 317
 318         mutex_lock(&bus->mdio_lock);
 319         bus->write(bus, phy_addr, MII_ATH_DBG_ADDR, dbg_addr);
 320         bus->write(bus, phy_addr, MII_ATH_DBG_DATA, dbg_data);
 321         mutex_unlock(&bus->mdio_lock);
 322 }
 323
 324 void
 325 ar8xxx_phy_mmd_write(struct ar8xxx_priv *priv, int phy_addr, u16 addr, u16 data)
 326 {
 327         struct mii_bus *bus = priv->mii_bus;
 328
 329         mutex_lock(&bus->mdio_lock);
 330         bus->write(bus, phy_addr, MII_ATH_MMD_ADDR, addr);
 331         bus->write(bus, phy_addr, MII_ATH_MMD_DATA, data);
 332         mutex_unlock(&bus->mdio_lock);
 333 }
 334
 335 u16
 336 ar8xxx_phy_mmd_read(struct ar8xxx_priv *priv, int phy_addr, u16 addr)
 337 {
 338         struct mii_bus *bus = priv->mii_bus;
 339         u16 data;
 340
 341         mutex_lock(&bus->mdio_lock);
 342         bus->write(bus, phy_addr, MII_ATH_MMD_ADDR, addr);
 343         data = bus->read(bus, phy_addr, MII_ATH_MMD_DATA);
 344         mutex_unlock(&bus->mdio_lock);
 345
 346         return data;
 347 }
 348
 349 static int
 350 ar8xxx_reg_wait(struct ar8xxx_priv *priv, u32 reg, u32 mask, u32 val,
 351                 unsigned timeout)
 352 {
 353         int i;
 354
 355         for (i = 0; i < timeout; i++) {
 356                 u32 t;
 357
 358                 t = ar8xxx_read(priv, reg);
 359                 if ((t & mask) == val)
 360                         return 0;
 361
 362                 usleep_range(1000, 2000);
 363         }
 364
 365         return -ETIMEDOUT;
 366 }
 367
 368 static int
 369 ar8xxx_mib_op(struct ar8xxx_priv *priv, u32 op)
 370 {
 371         unsigned mib_func = priv->chip->mib_func;
 372         int ret;
 373
 374         lockdep_assert_held(&priv->mib_lock);
 375
 376         /* Capture the hardware statistics for all ports */
 377         ar8xxx_rmw(priv, mib_func, AR8216_MIB_FUNC, (op << AR8216_MIB_FUNC_S));
 378
 379         /* Wait for the capturing to complete. */
 380         ret = ar8xxx_reg_wait(priv, mib_func, AR8216_MIB_BUSY, 0, 10);
 381         if (ret)
 382                 goto out;
 383
 384         ret = 0;
 385
 386 out:
 387         return ret;
 388 }
 389
 390 static int
 391 ar8xxx_mib_capture(struct ar8xxx_priv *priv)
 392 {
 393         return ar8xxx_mib_op(priv, AR8216_MIB_FUNC_CAPTURE);
 394 }
 395
 396 static int
 397 ar8xxx_mib_flush(struct ar8xxx_priv *priv)
 398 {
 399         return ar8xxx_mib_op(priv, AR8216_MIB_FUNC_FLUSH);
 400 }
 401
 402 static void
 403 ar8xxx_mib_fetch_port_stat(struct ar8xxx_priv *priv, int port, bool flush)
 404 {
 405         unsigned int base;
 406         u64 *mib_stats;
 407         int i;
 408
 409         WARN_ON(port >= priv->dev.ports);
 410
 411         lockdep_assert_held(&priv->mib_lock);
 412
 413         base = priv->chip->reg_port_stats_start +
 414                priv->chip->reg_port_stats_length * port;
 415
 416         mib_stats = &priv->mib_stats[port * priv->chip->num_mibs];
 417         for (i = 0; i < priv->chip->num_mibs; i++) {
 418                 const struct ar8xxx_mib_desc *mib;
 419                 u64 t;
 420
 421                 mib = &priv->chip->mib_decs[i];
 422                 t = ar8xxx_read(priv, base + mib->offset);
 423                 if (mib->size == 2) {
 424                         u64 hi;
 425
 426                         hi = ar8xxx_read(priv, base + mib->offset + 4);
 427                         t |= hi << 32;
 428                 }
 429
 430                 if (flush)
 431                         mib_stats[i] = 0;
 432                 else
 433                         mib_stats[i] += t;
 434         }
 435 }
 436
 437 static void
 438 ar8216_read_port_link(struct ar8xxx_priv *priv, int port,
 439                       struct switch_port_link *link)
 440 {
 441         u32 status;
 442         u32 speed;
 443
 444         memset(link, '\0', sizeof(*link));
 445
 446         status = priv->chip->read_port_status(priv, port);
 447
 448         link->aneg = !!(status & AR8216_PORT_STATUS_LINK_AUTO);
 449         if (link->aneg) {
 450                 link->link = !!(status & AR8216_PORT_STATUS_LINK_UP);
 451         } else {
 452                 link->link = true;
 453
 454                 if (priv->get_port_link) {
 455                         int err;
 456
 457                         err = priv->get_port_link(port);
 458                         if (err >= 0)
 459                                 link->link = !!err;
 460                 }
 461         }
 462
 463         if (!link->link)
 464                 return;
 465
 466         link->duplex = !!(status & AR8216_PORT_STATUS_DUPLEX);
 467         link->tx_flow = !!(status & AR8216_PORT_STATUS_TXFLOW);
 468         link->rx_flow = !!(status & AR8216_PORT_STATUS_RXFLOW);
 469
 470         if (link->aneg && link->duplex && priv->chip->read_port_eee_status)
 471                 link->eee = priv->chip->read_port_eee_status(priv, port);
 472
 473         speed = (status & AR8216_PORT_STATUS_SPEED) >>
 474                  AR8216_PORT_STATUS_SPEED_S;
 475
 476         switch (speed) {
 477         case AR8216_PORT_SPEED_10M:
 478                 link->speed = SWITCH_PORT_SPEED_10;
 479                 break;
 480         case AR8216_PORT_SPEED_100M:
 481                 link->speed = SWITCH_PORT_SPEED_100;
 482                 break;
 483         case AR8216_PORT_SPEED_1000M:
 484                 link->speed = SWITCH_PORT_SPEED_1000;
 485                 break;
 486         default:
 487                 link->speed = SWITCH_PORT_SPEED_UNKNOWN;
 488                 break;
 489         }
 490 }
 491
 492 static struct sk_buff *
 493 ar8216_mangle_tx(struct net_device *dev, struct sk_buff *skb)
 494 {
 495         struct ar8xxx_priv *priv = dev->phy_ptr;
 496         unsigned char *buf;
 497
 498         if (unlikely(!priv))
 499                 goto error;
 500
 501         if (!priv->vlan)
 502                 goto send;
 503
 504         if (unlikely(skb_headroom(skb) < 2)) {
 505                 if (pskb_expand_head(skb, 2, 0, GFP_ATOMIC) < 0)
 506                         goto error;
 507         }
 508
 509         buf = skb_push(skb, 2);
 510         buf[0] = 0x10;
 511         buf[1] = 0x80;
 512
 513 send:
 514         return skb;
 515
 516 error:
 517         dev_kfree_skb_any(skb);
 518         return NULL;
 519 }
 520
 521 static void
 522 ar8216_mangle_rx(struct net_device *dev, struct sk_buff *skb)
 523 {
 524         struct ar8xxx_priv *priv;
 525         unsigned char *buf;
 526         int port, vlan;
 527
 528         priv = dev->phy_ptr;
 529         if (!priv)
 530                 return;
 531
 532         /* don't strip the header if vlan mode is disabled */
 533         if (!priv->vlan)
 534                 return;
 535
 536         /* strip header, get vlan id */
 537         buf = skb->data;
 538         skb_pull(skb, 2);
 539
 540         /* check for vlan header presence */
 541         if ((buf[12 + 2] != 0x81) || (buf[13 + 2] != 0x00))
 542                 return;
 543
 544         port = buf[0] & 0xf;
 545
 546         /* no need to fix up packets coming from a tagged source */
 547         if (priv->vlan_tagged & (1 << port))
 548                 return;
 549
 550         /* lookup port vid from local table, the switch passes an invalid vlan id */
 551         vlan = priv->vlan_id[priv->pvid[port]];
 552
 553         buf[14 + 2] &= 0xf0;
 554         buf[14 + 2] |= vlan >> 8;
 555         buf[15 + 2] = vlan & 0xff;
 556 }
 557
 558 int
 559 ar8216_wait_bit(struct ar8xxx_priv *priv, int reg, u32 mask, u32 val)
 560 {
 561         int timeout = 20;
 562         u32 t = 0;
 563
 564         while (1) {
 565                 t = ar8xxx_read(priv, reg);
 566                 if ((t & mask) == val)
 567                         return 0;
 568
 569                 if (timeout-- <= 0)
 570                         break;
 571
 572                 udelay(10);
 573         }
 574
 575         pr_err("ar8216: timeout on reg %08x: %08x & %08x != %08x\n",
 576                (unsigned int) reg, t, mask, val);
 577         return -ETIMEDOUT;
 578 }
 579
 580 static void
 581 ar8216_vtu_op(struct ar8xxx_priv *priv, u32 op, u32 val)
 582 {
 583         if (ar8216_wait_bit(priv, AR8216_REG_VTU, AR8216_VTU_ACTIVE, 0))
 584                 return;
 585         if ((op & AR8216_VTU_OP) == AR8216_VTU_OP_LOAD) {
 586                 val &= AR8216_VTUDATA_MEMBER;
 587                 val |= AR8216_VTUDATA_VALID;
 588                 ar8xxx_write(priv, AR8216_REG_VTU_DATA, val);
 589         }
 590         op |= AR8216_VTU_ACTIVE;
 591         ar8xxx_write(priv, AR8216_REG_VTU, op);
 592 }
 593
 594 static void
 595 ar8216_vtu_flush(struct ar8xxx_priv *priv)
 596 {
 597         ar8216_vtu_op(priv, AR8216_VTU_OP_FLUSH, 0);
 598 }
 599
 600 static void
 601 ar8216_vtu_load_vlan(struct ar8xxx_priv *priv, u32 vid, u32 port_mask)
 602 {
 603         u32 op;
 604
 605         op = AR8216_VTU_OP_LOAD | (vid << AR8216_VTU_VID_S);
 606         ar8216_vtu_op(priv, op, port_mask);
 607 }
 608
 609 static int
 610 ar8216_atu_flush(struct ar8xxx_priv *priv)
 611 {
 612         int ret;
 613
 614         ret = ar8216_wait_bit(priv, AR8216_REG_ATU, AR8216_ATU_ACTIVE, 0);
 615         if (!ret)
 616                 ar8xxx_write(priv, AR8216_REG_ATU, AR8216_ATU_OP_FLUSH |
 617                                                    AR8216_ATU_ACTIVE);
 618
 619         return ret;
 620 }
 621
 622 static u32
 623 ar8216_read_port_status(struct ar8xxx_priv *priv, int port)
 624 {
 625         return ar8xxx_read(priv, AR8216_REG_PORT_STATUS(port));
 626 }
 627
 628 static void
 629 ar8216_setup_port(struct ar8xxx_priv *priv, int port, u32 members)
 630 {
 631         u32 header;
 632         u32 egress, ingress;
 633         u32 pvid;
 634
 635         if (priv->vlan) {
 636                 pvid = priv->vlan_id[priv->pvid[port]];
 637                 if (priv->vlan_tagged & (1 << port))
 638                         egress = AR8216_OUT_ADD_VLAN;
 639                 else
 640                         egress = AR8216_OUT_STRIP_VLAN;
 641                 ingress = AR8216_IN_SECURE;
 642         } else {
 643                 pvid = port;
 644                 egress = AR8216_OUT_KEEP;
 645                 ingress = AR8216_IN_PORT_ONLY;
 646         }
 647
 648         if (chip_is_ar8216(priv) && priv->vlan && port == AR8216_PORT_CPU)
 649                 header = AR8216_PORT_CTRL_HEADER;
 650         else
 651                 header = 0;
 652
 653         ar8xxx_rmw(priv, AR8216_REG_PORT_CTRL(port),
 654                    AR8216_PORT_CTRL_LEARN | AR8216_PORT_CTRL_VLAN_MODE |
 655                    AR8216_PORT_CTRL_SINGLE_VLAN | AR8216_PORT_CTRL_STATE |
 656                    AR8216_PORT_CTRL_HEADER | AR8216_PORT_CTRL_LEARN_LOCK,
 657                    AR8216_PORT_CTRL_LEARN | header |
 658                    (egress << AR8216_PORT_CTRL_VLAN_MODE_S) |
 659                    (AR8216_PORT_STATE_FORWARD << AR8216_PORT_CTRL_STATE_S));
 660
 661         ar8xxx_rmw(priv, AR8216_REG_PORT_VLAN(port),
 662                    AR8216_PORT_VLAN_DEST_PORTS | AR8216_PORT_VLAN_MODE |
 663                    AR8216_PORT_VLAN_DEFAULT_ID,
 664                    (members << AR8216_PORT_VLAN_DEST_PORTS_S) |
 665                    (ingress << AR8216_PORT_VLAN_MODE_S) |
 666                    (pvid << AR8216_PORT_VLAN_DEFAULT_ID_S));
 667 }
 668
 669 static int
 670 ar8216_hw_init(struct ar8xxx_priv *priv)
 671 {
 672         if (priv->initialized)
 673                 return 0;
 674
 675         ar8xxx_phy_init(priv);
 676
 677         priv->initialized = true;
 678         return 0;
 679 }
 680
 681 static void
 682 ar8216_init_globals(struct ar8xxx_priv *priv)
 683 {
 684         /* standard atheros magic */
 685         ar8xxx_write(priv, 0x38, 0xc000050e);
 686
 687         ar8xxx_rmw(priv, AR8216_REG_GLOBAL_CTRL,
 688                    AR8216_GCTRL_MTU, 1518 + 8 + 2);
 689 }
 690
 691 static void
 692 ar8216_init_port(struct ar8xxx_priv *priv, int port)
 693 {
 694         /* Enable port learning and tx */
 695         ar8xxx_write(priv, AR8216_REG_PORT_CTRL(port),
 696                 AR8216_PORT_CTRL_LEARN |
 697                 (4 << AR8216_PORT_CTRL_STATE_S));
 698
 699         ar8xxx_write(priv, AR8216_REG_PORT_VLAN(port), 0);
 700
 701         if (port == AR8216_PORT_CPU) {
 702                 ar8xxx_write(priv, AR8216_REG_PORT_STATUS(port),
 703                         AR8216_PORT_STATUS_LINK_UP |
 704                         (ar8xxx_has_gige(priv) ?
 705                                 AR8216_PORT_SPEED_1000M : AR8216_PORT_SPEED_100M) |
 706                         AR8216_PORT_STATUS_TXMAC |
 707                         AR8216_PORT_STATUS_RXMAC |
 708                         (chip_is_ar8316(priv) ? AR8216_PORT_STATUS_RXFLOW : 0) |
 709                         (chip_is_ar8316(priv) ? AR8216_PORT_STATUS_TXFLOW : 0) |
 710                         AR8216_PORT_STATUS_DUPLEX);
 711         } else {
 712                 ar8xxx_write(priv, AR8216_REG_PORT_STATUS(port),
 713                         AR8216_PORT_STATUS_LINK_AUTO);
 714         }
 715 }
 716
 717 static void
 718 ar8236_setup_port(struct ar8xxx_priv *priv, int port, u32 members)
 719 {
 720         u32 egress, ingress;
 721         u32 pvid;
 722
 723         if (priv->vlan) {
 724                 pvid = priv->vlan_id[priv->pvid[port]];
 725                 if (priv->vlan_tagged & (1 << port))
 726                         egress = AR8216_OUT_ADD_VLAN;
 727                 else
 728                         egress = AR8216_OUT_STRIP_VLAN;
 729                 ingress = AR8216_IN_SECURE;
 730         } else {
 731                 pvid = port;
 732                 egress = AR8216_OUT_KEEP;
 733                 ingress = AR8216_IN_PORT_ONLY;
 734         }
 735
 736         ar8xxx_rmw(priv, AR8216_REG_PORT_CTRL(port),
 737                    AR8216_PORT_CTRL_LEARN | AR8216_PORT_CTRL_VLAN_MODE |
 738                    AR8216_PORT_CTRL_SINGLE_VLAN | AR8216_PORT_CTRL_STATE |
 739                    AR8216_PORT_CTRL_HEADER | AR8216_PORT_CTRL_LEARN_LOCK,
 740                    AR8216_PORT_CTRL_LEARN |
 741                    (egress << AR8216_PORT_CTRL_VLAN_MODE_S) |
 742                    (AR8216_PORT_STATE_FORWARD << AR8216_PORT_CTRL_STATE_S));
 743
 744         ar8xxx_rmw(priv, AR8236_REG_PORT_VLAN(port),
 745                    AR8236_PORT_VLAN_DEFAULT_ID,
 746                    (pvid << AR8236_PORT_VLAN_DEFAULT_ID_S));
 747
 748         ar8xxx_rmw(priv, AR8236_REG_PORT_VLAN2(port),
 749                    AR8236_PORT_VLAN2_VLAN_MODE |
 750                    AR8236_PORT_VLAN2_MEMBER,
 751                    (ingress << AR8236_PORT_VLAN2_VLAN_MODE_S) |
 752                    (members << AR8236_PORT_VLAN2_MEMBER_S));
 753 }
 754
 755 static void
 756 ar8236_init_globals(struct ar8xxx_priv *priv)
 757 {
 758         /* enable jumbo frames */
 759         ar8xxx_rmw(priv, AR8216_REG_GLOBAL_CTRL,
 760                    AR8316_GCTRL_MTU, 9018 + 8 + 2);
 761
 762         /* enable cpu port to receive arp frames */
 763         ar8xxx_reg_set(priv, AR8216_REG_ATU_CTRL,
 764                    AR8236_ATU_CTRL_RES);
 765
 766         /* enable cpu port to receive multicast and broadcast frames */
 767         ar8xxx_reg_set(priv, AR8216_REG_FLOOD_MASK,
 768                    AR8236_FM_CPU_BROADCAST_EN | AR8236_FM_CPU_BCAST_FWD_EN);
 769
 770         /* Enable MIB counters */
 771         ar8xxx_rmw(priv, AR8216_REG_MIB_FUNC, AR8216_MIB_FUNC | AR8236_MIB_EN,
 772                    (AR8216_MIB_FUNC_NO_OP << AR8216_MIB_FUNC_S) |
 773                    AR8236_MIB_EN);
 774 }
 775
 776 static int
 777 ar8316_hw_init(struct ar8xxx_priv *priv)
 778 {
 779         u32 val, newval;
 780
 781         val = ar8xxx_read(priv, AR8316_REG_POSTRIP);
 782
 783         if (priv->phy->interface == PHY_INTERFACE_MODE_RGMII) {
 784                 if (priv->port4_phy) {
 785                         /* value taken from Ubiquiti RouterStation Pro */
 786                         newval = 0x81461bea;
 787                         pr_info("ar8316: Using port 4 as PHY\n");
 788                 } else {
 789                         newval = 0x01261be2;
 790                         pr_info("ar8316: Using port 4 as switch port\n");
 791                 }
 792         } else if (priv->phy->interface == PHY_INTERFACE_MODE_GMII) {
 793                 /* value taken from AVM Fritz!Box 7390 sources */
 794                 newval = 0x010e5b71;
 795         } else {
 796                 /* no known value for phy interface */
 797                 pr_err("ar8316: unsupported mii mode: %d.\n",
 798                        priv->phy->interface);
 799                 return -EINVAL;
 800         }
 801
 802         if (val == newval)
 803                 goto out;
 804
 805         ar8xxx_write(priv, AR8316_REG_POSTRIP, newval);
 806
 807         if (priv->port4_phy &&
 808             priv->phy->interface == PHY_INTERFACE_MODE_RGMII) {
 809                 /* work around for phy4 rgmii mode */
 810                 ar8xxx_phy_dbg_write(priv, 4, 0x12, 0x480c);
 811                 /* rx delay */
 812                 ar8xxx_phy_dbg_write(priv, 4, 0x0, 0x824e);
 813                 /* tx delay */
 814                 ar8xxx_phy_dbg_write(priv, 4, 0x5, 0x3d47);
 815                 msleep(1000);
 816         }
 817
 818         ar8xxx_phy_init(priv);
 819
 820 out:
 821         priv->initialized = true;
 822         return 0;
 823 }
 824
 825 static void
 826 ar8316_init_globals(struct ar8xxx_priv *priv)
 827 {
 828         /* standard atheros magic */
 829         ar8xxx_write(priv, 0x38, 0xc000050e);
 830
 831         /* enable cpu port to receive multicast and broadcast frames */
 832         ar8xxx_write(priv, AR8216_REG_FLOOD_MASK, 0x003f003f);
 833
 834         /* enable jumbo frames */
 835         ar8xxx_rmw(priv, AR8216_REG_GLOBAL_CTRL,
 836                    AR8316_GCTRL_MTU, 9018 + 8 + 2);
 837
 838         /* Enable MIB counters */
 839         ar8xxx_rmw(priv, AR8216_REG_MIB_FUNC, AR8216_MIB_FUNC | AR8236_MIB_EN,
 840                    (AR8216_MIB_FUNC_NO_OP << AR8216_MIB_FUNC_S) |
 841                    AR8236_MIB_EN);
 842 }
 843
 844 int
 845 ar8xxx_sw_set_vlan(struct switch_dev *dev, const struct switch_attr *attr,
 846                    struct switch_val *val)
 847 {
 848         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
 849         priv->vlan = !!val->value.i;
 850         return 0;
 851 }
 852
 853 int
 854 ar8xxx_sw_get_vlan(struct switch_dev *dev, const struct switch_attr *attr,
 855                    struct switch_val *val)
 856 {
 857         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
 858         val->value.i = priv->vlan;
 859         return 0;
 860 }
 861
 862
 863 int
 864 ar8xxx_sw_set_pvid(struct switch_dev *dev, int port, int vlan)
 865 {
 866         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
 867
 868         /* make sure no invalid PVIDs get set */
 869
 870         if (vlan >= dev->vlans)
 871                 return -EINVAL;
 872
 873         priv->pvid[port] = vlan;
 874         return 0;
 875 }
 876
 877 int
 878 ar8xxx_sw_get_pvid(struct switch_dev *dev, int port, int *vlan)
 879 {
 880         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
 881         *vlan = priv->pvid[port];
 882         return 0;
 883 }
 884
 885 static int
 886 ar8xxx_sw_set_vid(struct switch_dev *dev, const struct switch_attr *attr,
 887                   struct switch_val *val)
 888 {
 889         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
 890         priv->vlan_id[val->port_vlan] = val->value.i;
 891         return 0;
 892 }
 893
 894 static int
 895 ar8xxx_sw_get_vid(struct switch_dev *dev, const struct switch_attr *attr,
 896                   struct switch_val *val)
 897 {
 898         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
 899         val->value.i = priv->vlan_id[val->port_vlan];
 900         return 0;
 901 }
 902
 903 int
 904 ar8xxx_sw_get_port_link(struct switch_dev *dev, int port,
 905                         struct switch_port_link *link)
 906 {
 907         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
 908
 909         ar8216_read_port_link(priv, port, link);
 910         return 0;
 911 }
 912
 913 static int
 914 ar8xxx_sw_get_ports(struct switch_dev *dev, struct switch_val *val)
 915 {
 916         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
 917         u8 ports = priv->vlan_table[val->port_vlan];
 918         int i;
 919
 920         val->len = 0;
 921         for (i = 0; i < dev->ports; i++) {
 922                 struct switch_port *p;
 923
 924                 if (!(ports & (1 << i)))
 925                         continue;
 926
 927                 p = &val->value.ports[val->len++];
 928                 p->id = i;
 929                 if (priv->vlan_tagged & (1 << i))
 930                         p->flags = (1 << SWITCH_PORT_FLAG_TAGGED);
 931                 else
 932                         p->flags = 0;
 933         }
 934         return 0;
 935 }
 936
 937 static int
 938 ar8xxx_sw_set_ports(struct switch_dev *dev, struct switch_val *val)
 939 {
 940         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
 941         u8 *vt = &priv->vlan_table[val->port_vlan];
 942         int i, j;
 943
 944         *vt = 0;
 945         for (i = 0; i < val->len; i++) {
 946                 struct switch_port *p = &val->value.ports[i];
 947
 948                 if (p->flags & (1 << SWITCH_PORT_FLAG_TAGGED)) {
 949                         priv->vlan_tagged |= (1 << p->id);
 950                 } else {
 951                         priv->vlan_tagged &= ~(1 << p->id);
 952                         priv->pvid[p->id] = val->port_vlan;
 953
 954                         /* make sure that an untagged port does not
 955                          * appear in other vlans */
 956                         for (j = 0; j < AR8X16_MAX_VLANS; j++) {
 957                                 if (j == val->port_vlan)
 958                                         continue;
 959                                 priv->vlan_table[j] &= ~(1 << p->id);
 960                         }
 961                 }
 962
 963                 *vt |= 1 << p->id;
 964         }
 965         return 0;
 966 }
 967
 968 static void
 969 ar8216_set_mirror_regs(struct ar8xxx_priv *priv)
 970 {
 971         int port;
 972
 973         /* reset all mirror registers */
 974         ar8xxx_rmw(priv, AR8216_REG_GLOBAL_CPUPORT,
 975                    AR8216_GLOBAL_CPUPORT_MIRROR_PORT,
 976                    (0xF << AR8216_GLOBAL_CPUPORT_MIRROR_PORT_S));
 977         for (port = 0; port < AR8216_NUM_PORTS; port++) {
 978                 ar8xxx_reg_clear(priv, AR8216_REG_PORT_CTRL(port),
 979                            AR8216_PORT_CTRL_MIRROR_RX);
 980
 981                 ar8xxx_reg_clear(priv, AR8216_REG_PORT_CTRL(port),
 982                            AR8216_PORT_CTRL_MIRROR_TX);
 983         }
 984
 985         /* now enable mirroring if necessary */
 986         if (priv->source_port >= AR8216_NUM_PORTS ||
 987             priv->monitor_port >= AR8216_NUM_PORTS ||
 988             priv->source_port == priv->monitor_port) {
 989                 return;
 990         }
 991
 992         ar8xxx_rmw(priv, AR8216_REG_GLOBAL_CPUPORT,
 993                    AR8216_GLOBAL_CPUPORT_MIRROR_PORT,
 994                    (priv->monitor_port << AR8216_GLOBAL_CPUPORT_MIRROR_PORT_S));
 995
 996         if (priv->mirror_rx)
 997                 ar8xxx_reg_set(priv, AR8216_REG_PORT_CTRL(priv->source_port),
 998                            AR8216_PORT_CTRL_MIRROR_RX);
 999
1000         if (priv->mirror_tx)
1001                 ar8xxx_reg_set(priv, AR8216_REG_PORT_CTRL(priv->source_port),
1002                            AR8216_PORT_CTRL_MIRROR_TX);
1003 }
1004
1005 int
1006 ar8xxx_sw_hw_apply(struct switch_dev *dev)
1007 {
1008         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1009         u8 portmask[AR8X16_MAX_PORTS];
1010         int i, j;
1011
1012         mutex_lock(&priv->reg_mutex);
1013         /* flush all vlan translation unit entries */
1014         priv->chip->vtu_flush(priv);
1015
1016         memset(portmask, 0, sizeof(portmask));
1017         if (!priv->init) {
1018                 /* calculate the port destination masks and load vlans
1019                  * into the vlan translation unit */
1020                 for (j = 0; j < AR8X16_MAX_VLANS; j++) {
1021                         u8 vp = priv->vlan_table[j];
1022
1023                         if (!vp)
1024                                 continue;
1025
1026                         for (i = 0; i < dev->ports; i++) {
1027                                 u8 mask = (1 << i);
1028                                 if (vp & mask)
1029                                         portmask[i] |= vp & ~mask;
1030                         }
1031
1032                         priv->chip->vtu_load_vlan(priv, priv->vlan_id[j],
1033                                                  priv->vlan_table[j]);
1034                 }
1035         } else {
1036                 /* vlan disabled:
1037                  * isolate all ports, but connect them to the cpu port */
1038                 for (i = 0; i < dev->ports; i++) {
1039                         if (i == AR8216_PORT_CPU)
1040                                 continue;
1041
1042                         portmask[i] = 1 << AR8216_PORT_CPU;
1043                         portmask[AR8216_PORT_CPU] |= (1 << i);
1044                 }
1045         }
1046
1047         /* update the port destination mask registers and tag settings */
1048         for (i = 0; i < dev->ports; i++) {
1049                 priv->chip->setup_port(priv, i, portmask[i]);
1050         }
1051
1052         priv->chip->set_mirror_regs(priv);
1053
1054         mutex_unlock(&priv->reg_mutex);
1055         return 0;
1056 }
1057
1058 int
1059 ar8xxx_sw_reset_switch(struct switch_dev *dev)
1060 {
1061         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1062         const struct ar8xxx_chip *chip = priv->chip;
1063         int i;
1064
1065         mutex_lock(&priv->reg_mutex);
1066         memset(&priv->vlan, 0, sizeof(struct ar8xxx_priv) -
1067                 offsetof(struct ar8xxx_priv, vlan));
1068
1069         for (i = 0; i < AR8X16_MAX_VLANS; i++)
1070                 priv->vlan_id[i] = i;
1071
1072         /* Configure all ports */
1073         for (i = 0; i < dev->ports; i++)
1074                 chip->init_port(priv, i);
1075
1076         priv->mirror_rx = false;
1077         priv->mirror_tx = false;
1078         priv->source_port = 0;
1079         priv->monitor_port = 0;
1080
1081         chip->init_globals(priv);
1082
1083         mutex_unlock(&priv->reg_mutex);
1084
1085         return chip->sw_hw_apply(dev);
1086 }
1087
1088 int
1089 ar8xxx_sw_set_reset_mibs(struct switch_dev *dev,
1090                          const struct switch_attr *attr,
1091                          struct switch_val *val)
1092 {
1093         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1094         unsigned int len;
1095         int ret;
1096
1097         if (!ar8xxx_has_mib_counters(priv))
1098                 return -EOPNOTSUPP;
1099
1100         mutex_lock(&priv->mib_lock);
1101
1102         len = priv->dev.ports * priv->chip->num_mibs *
1103               sizeof(*priv->mib_stats);
1104         memset(priv->mib_stats, '\0', len);
1105         ret = ar8xxx_mib_flush(priv);
1106         if (ret)
1107                 goto unlock;
1108
1109         ret = 0;
1110
1111 unlock:
1112         mutex_unlock(&priv->mib_lock);
1113         return ret;
1114 }
1115
1116 int
1117 ar8xxx_sw_set_mirror_rx_enable(struct switch_dev *dev,
1118                                const struct switch_attr *attr,
1119                                struct switch_val *val)
1120 {
1121         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1122
1123         mutex_lock(&priv->reg_mutex);
1124         priv->mirror_rx = !!val->value.i;
1125         priv->chip->set_mirror_regs(priv);
1126         mutex_unlock(&priv->reg_mutex);
1127
1128         return 0;
1129 }
1130
1131 int
1132 ar8xxx_sw_get_mirror_rx_enable(struct switch_dev *dev,
1133                                const struct switch_attr *attr,
1134                                struct switch_val *val)
1135 {
1136         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1137         val->value.i = priv->mirror_rx;
1138         return 0;
1139 }
1140
1141 int
1142 ar8xxx_sw_set_mirror_tx_enable(struct switch_dev *dev,
1143                                const struct switch_attr *attr,
1144                                struct switch_val *val)
1145 {
1146         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1147
1148         mutex_lock(&priv->reg_mutex);
1149         priv->mirror_tx = !!val->value.i;
1150         priv->chip->set_mirror_regs(priv);
1151         mutex_unlock(&priv->reg_mutex);
1152
1153         return 0;
1154 }
1155
1156 int
1157 ar8xxx_sw_get_mirror_tx_enable(struct switch_dev *dev,
1158                                const struct switch_attr *attr,
1159                                struct switch_val *val)
1160 {
1161         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1162         val->value.i = priv->mirror_tx;
1163         return 0;
1164 }
1165
1166 int
1167 ar8xxx_sw_set_mirror_monitor_port(struct switch_dev *dev,
1168                                   const struct switch_attr *attr,
1169                                   struct switch_val *val)
1170 {
1171         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1172
1173         mutex_lock(&priv->reg_mutex);
1174         priv->monitor_port = val->value.i;
1175         priv->chip->set_mirror_regs(priv);
1176         mutex_unlock(&priv->reg_mutex);
1177
1178         return 0;
1179 }
1180
1181 int
1182 ar8xxx_sw_get_mirror_monitor_port(struct switch_dev *dev,
1183                                   const struct switch_attr *attr,
1184                                   struct switch_val *val)
1185 {
1186         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1187         val->value.i = priv->monitor_port;
1188         return 0;
1189 }
1190
1191 int
1192 ar8xxx_sw_set_mirror_source_port(struct switch_dev *dev,
1193                                  const struct switch_attr *attr,
1194                                  struct switch_val *val)
1195 {
1196         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1197
1198         mutex_lock(&priv->reg_mutex);
1199         priv->source_port = val->value.i;
1200         priv->chip->set_mirror_regs(priv);
1201         mutex_unlock(&priv->reg_mutex);
1202
1203         return 0;
1204 }
1205
1206 int
1207 ar8xxx_sw_get_mirror_source_port(struct switch_dev *dev,
1208                                  const struct switch_attr *attr,
1209                                  struct switch_val *val)
1210 {
1211         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1212         val->value.i = priv->source_port;
1213         return 0;
1214 }
1215
1216 int
1217 ar8xxx_sw_set_port_reset_mib(struct switch_dev *dev,
1218                              const struct switch_attr *attr,
1219                              struct switch_val *val)
1220 {
1221         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1222         int port;
1223         int ret;
1224
1225         if (!ar8xxx_has_mib_counters(priv))
1226                 return -EOPNOTSUPP;
1227
1228         port = val->port_vlan;
1229         if (port >= dev->ports)
1230                 return -EINVAL;
1231
1232         mutex_lock(&priv->mib_lock);
1233         ret = ar8xxx_mib_capture(priv);
1234         if (ret)
1235                 goto unlock;
1236
1237         ar8xxx_mib_fetch_port_stat(priv, port, true);
1238
1239         ret = 0;
1240
1241 unlock:
1242         mutex_unlock(&priv->mib_lock);
1243         return ret;
1244 }
1245
1246 int
1247 ar8xxx_sw_get_port_mib(struct switch_dev *dev,
1248                        const struct switch_attr *attr,
1249                        struct switch_val *val)
1250 {
1251         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1252         const struct ar8xxx_chip *chip = priv->chip;
1253         u64 *mib_stats;
1254         int port;
1255         int ret;
1256         char *buf = priv->buf;
1257         int i, len = 0;
1258
1259         if (!ar8xxx_has_mib_counters(priv))
1260                 return -EOPNOTSUPP;
1261
1262         port = val->port_vlan;
1263         if (port >= dev->ports)
1264                 return -EINVAL;
1265
1266         mutex_lock(&priv->mib_lock);
1267         ret = ar8xxx_mib_capture(priv);
1268         if (ret)
1269                 goto unlock;
1270
1271         ar8xxx_mib_fetch_port_stat(priv, port, false);
1272
1273         len += snprintf(buf + len, sizeof(priv->buf) - len,
1274                         "Port %d MIB counters\n",
1275                         port);
1276
1277         mib_stats = &priv->mib_stats[port * chip->num_mibs];
1278         for (i = 0; i < chip->num_mibs; i++)
1279                 len += snprintf(buf + len, sizeof(priv->buf) - len,
1280                                 "%-12s: %llu\n",
1281                                 chip->mib_decs[i].name,
1282                                 mib_stats[i]);
1283
1284         val->value.s = buf;
1285         val->len = len;
1286
1287         ret = 0;
1288
1289 unlock:
1290         mutex_unlock(&priv->mib_lock);
1291         return ret;
1292 }
1293
1294 static const struct switch_attr ar8xxx_sw_attr_globals[] = {
1295         {
1296                 .type = SWITCH_TYPE_INT,
1297                 .name = "enable_vlan",
1298                 .description = "Enable VLAN mode",
1299                 .set = ar8xxx_sw_set_vlan,
1300                 .get = ar8xxx_sw_get_vlan,
1301                 .max = 1
1302         },
1303         {
1304                 .type = SWITCH_TYPE_NOVAL,
1305                 .name = "reset_mibs",
1306                 .description = "Reset all MIB counters",
1307                 .set = ar8xxx_sw_set_reset_mibs,
1308         },
1309         {
1310                 .type = SWITCH_TYPE_INT,
1311                 .name = "enable_mirror_rx",
1312                 .description = "Enable mirroring of RX packets",
1313                 .set = ar8xxx_sw_set_mirror_rx_enable,
1314                 .get = ar8xxx_sw_get_mirror_rx_enable,
1315                 .max = 1
1316         },
1317         {
1318                 .type = SWITCH_TYPE_INT,
1319                 .name = "enable_mirror_tx",
1320                 .description = "Enable mirroring of TX packets",
1321                 .set = ar8xxx_sw_set_mirror_tx_enable,
1322                 .get = ar8xxx_sw_get_mirror_tx_enable,
1323                 .max = 1
1324         },
1325         {
1326                 .type = SWITCH_TYPE_INT,
1327                 .name = "mirror_monitor_port",
1328                 .description = "Mirror monitor port",
1329                 .set = ar8xxx_sw_set_mirror_monitor_port,
1330                 .get = ar8xxx_sw_get_mirror_monitor_port,
1331                 .max = AR8216_NUM_PORTS - 1
1332         },
1333         {
1334                 .type = SWITCH_TYPE_INT,
1335                 .name = "mirror_source_port",
1336                 .description = "Mirror source port",
1337                 .set = ar8xxx_sw_set_mirror_source_port,
1338                 .get = ar8xxx_sw_get_mirror_source_port,
1339                 .max = AR8216_NUM_PORTS - 1
1340         },
1341 };
1342
1343 const struct switch_attr ar8xxx_sw_attr_port[2] = {
1344         {
1345                 .type = SWITCH_TYPE_NOVAL,
1346                 .name = "reset_mib",
1347                 .description = "Reset single port MIB counters",
1348                 .set = ar8xxx_sw_set_port_reset_mib,
1349         },
1350         {
1351                 .type = SWITCH_TYPE_STRING,
1352                 .name = "mib",
1353                 .description = "Get port's MIB counters",
1354                 .set = NULL,
1355                 .get = ar8xxx_sw_get_port_mib,
1356         },
1357 };
1358
1359 const struct switch_attr ar8xxx_sw_attr_vlan[1] = {
1360         {
1361                 .type = SWITCH_TYPE_INT,
1362                 .name = "vid",
1363                 .description = "VLAN ID (0-4094)",
1364                 .set = ar8xxx_sw_set_vid,
1365                 .get = ar8xxx_sw_get_vid,
1366                 .max = 4094,
1367         },
1368 };
1369
1370 static const struct switch_dev_ops ar8xxx_sw_ops = {
1371         .attr_global = {
1372                 .attr = ar8xxx_sw_attr_globals,
1373                 .n_attr = ARRAY_SIZE(ar8xxx_sw_attr_globals),
1374         },
1375         .attr_port = {
1376                 .attr = ar8xxx_sw_attr_port,
1377                 .n_attr = ARRAY_SIZE(ar8xxx_sw_attr_port),
1378         },
1379         .attr_vlan = {
1380                 .attr = ar8xxx_sw_attr_vlan,
1381                 .n_attr = ARRAY_SIZE(ar8xxx_sw_attr_vlan),
1382         },
1383         .get_port_pvid = ar8xxx_sw_get_pvid,
1384         .set_port_pvid = ar8xxx_sw_set_pvid,
1385         .get_vlan_ports = ar8xxx_sw_get_ports,
1386         .set_vlan_ports = ar8xxx_sw_set_ports,
1387         .apply_config = ar8xxx_sw_hw_apply,
1388         .reset_switch = ar8xxx_sw_reset_switch,
1389         .get_port_link = ar8xxx_sw_get_port_link,
1390 };
1391
1392 static const struct ar8xxx_chip ar8216_chip = {
1393         .caps = AR8XXX_CAP_MIB_COUNTERS,
1394
1395         .reg_port_stats_start = 0x19000,
1396         .reg_port_stats_length = 0xa0,
1397
1398         .name = "Atheros AR8216",
1399         .ports = AR8216_NUM_PORTS,
1400         .vlans = AR8216_NUM_VLANS,
1401         .swops = &ar8xxx_sw_ops,
1402
1403         .hw_init = ar8216_hw_init,
1404         .init_globals = ar8216_init_globals,
1405         .init_port = ar8216_init_port,
1406         .setup_port = ar8216_setup_port,
1407         .read_port_status = ar8216_read_port_status,
1408         .atu_flush = ar8216_atu_flush,
1409         .vtu_flush = ar8216_vtu_flush,
1410         .vtu_load_vlan = ar8216_vtu_load_vlan,
1411         .set_mirror_regs = ar8216_set_mirror_regs,
1412         .sw_hw_apply = ar8xxx_sw_hw_apply,
1413
1414         .num_mibs = ARRAY_SIZE(ar8216_mibs),
1415         .mib_decs = ar8216_mibs,
1416         .mib_func = AR8216_REG_MIB_FUNC
1417 };
1418
1419 static const struct ar8xxx_chip ar8236_chip = {
1420         .caps = AR8XXX_CAP_MIB_COUNTERS,
1421
1422         .reg_port_stats_start = 0x20000,
1423         .reg_port_stats_length = 0x100,
1424
1425         .name = "Atheros AR8236",
1426         .ports = AR8216_NUM_PORTS,
1427         .vlans = AR8216_NUM_VLANS,
1428         .swops = &ar8xxx_sw_ops,
1429
1430         .hw_init = ar8216_hw_init,
1431         .init_globals = ar8236_init_globals,
1432         .init_port = ar8216_init_port,
1433         .setup_port = ar8236_setup_port,
1434         .read_port_status = ar8216_read_port_status,
1435         .atu_flush = ar8216_atu_flush,
1436         .vtu_flush = ar8216_vtu_flush,
1437         .vtu_load_vlan = ar8216_vtu_load_vlan,
1438         .set_mirror_regs = ar8216_set_mirror_regs,
1439         .sw_hw_apply = ar8xxx_sw_hw_apply,
1440
1441         .num_mibs = ARRAY_SIZE(ar8236_mibs),
1442         .mib_decs = ar8236_mibs,
1443         .mib_func = AR8216_REG_MIB_FUNC
1444 };
1445
1446 static const struct ar8xxx_chip ar8316_chip = {
1447         .caps = AR8XXX_CAP_GIGE | AR8XXX_CAP_MIB_COUNTERS,
1448
1449         .reg_port_stats_start = 0x20000,
1450         .reg_port_stats_length = 0x100,
1451
1452         .name = "Atheros AR8316",
1453         .ports = AR8216_NUM_PORTS,
1454         .vlans = AR8X16_MAX_VLANS,
1455         .swops = &ar8xxx_sw_ops,
1456
1457         .hw_init = ar8316_hw_init,
1458         .init_globals = ar8316_init_globals,
1459         .init_port = ar8216_init_port,
1460         .setup_port = ar8216_setup_port,
1461         .read_port_status = ar8216_read_port_status,
1462         .atu_flush = ar8216_atu_flush,
1463         .vtu_flush = ar8216_vtu_flush,
1464         .vtu_load_vlan = ar8216_vtu_load_vlan,
1465         .set_mirror_regs = ar8216_set_mirror_regs,
1466         .sw_hw_apply = ar8xxx_sw_hw_apply,
1467
1468         .num_mibs = ARRAY_SIZE(ar8236_mibs),
1469         .mib_decs = ar8236_mibs,
1470         .mib_func = AR8216_REG_MIB_FUNC
1471 };
1472
1473 static int
1474 ar8xxx_id_chip(struct ar8xxx_priv *priv)
1475 {
1476         u32 val;
1477         u16 id;
1478         int i;
1479
1480         val = ar8xxx_read(priv, AR8216_REG_CTRL);
1481         if (val == ~0)
1482                 return -ENODEV;
1483
1484         id = val & (AR8216_CTRL_REVISION | AR8216_CTRL_VERSION);
1485         for (i = 0; i < AR8X16_PROBE_RETRIES; i++) {
1486                 u16 t;
1487
1488                 val = ar8xxx_read(priv, AR8216_REG_CTRL);
1489                 if (val == ~0)
1490                         return -ENODEV;
1491
1492                 t = val & (AR8216_CTRL_REVISION | AR8216_CTRL_VERSION);
1493                 if (t != id)
1494                         return -ENODEV;
1495         }
1496
1497         priv->chip_ver = (id & AR8216_CTRL_VERSION) >> AR8216_CTRL_VERSION_S;
1498         priv->chip_rev = (id & AR8216_CTRL_REVISION);
1499
1500         switch (priv->chip_ver) {
1501         case AR8XXX_VER_AR8216:
1502                 priv->chip = &ar8216_chip;
1503                 break;
1504         case AR8XXX_VER_AR8236:
1505                 priv->chip = &ar8236_chip;
1506                 break;
1507         case AR8XXX_VER_AR8316:
1508                 priv->chip = &ar8316_chip;
1509                 break;
1510         case AR8XXX_VER_AR8327:
1511                 priv->chip = &ar8327_chip;
1512                 break;
1513         case AR8XXX_VER_AR8337:
1514                 priv->chip = &ar8337_chip;
1515                 break;
1516         default:
1517                 pr_err("ar8216: Unknown Atheros device [ver=%d, rev=%d]\n",
1518                        priv->chip_ver, priv->chip_rev);
1519
1520                 return -ENODEV;
1521         }
1522
1523         return 0;
1524 }
1525
1526 static void
1527 ar8xxx_mib_work_func(struct work_struct *work)
1528 {
1529         struct ar8xxx_priv *priv;
1530         int err;
1531
1532         priv = container_of(work, struct ar8xxx_priv, mib_work.work);
1533
1534         mutex_lock(&priv->mib_lock);
1535
1536         err = ar8xxx_mib_capture(priv);
1537         if (err)
1538                 goto next_port;
1539
1540         ar8xxx_mib_fetch_port_stat(priv, priv->mib_next_port, false);
1541
1542 next_port:
1543         priv->mib_next_port++;
1544         if (priv->mib_next_port >= priv->dev.ports)
1545                 priv->mib_next_port = 0;
1546
1547         mutex_unlock(&priv->mib_lock);
1548         schedule_delayed_work(&priv->mib_work,
1549                               msecs_to_jiffies(AR8XXX_MIB_WORK_DELAY));
1550 }
1551
1552 static int
1553 ar8xxx_mib_init(struct ar8xxx_priv *priv)
1554 {
1555         unsigned int len;
1556
1557         if (!ar8xxx_has_mib_counters(priv))
1558                 return 0;
1559
1560         BUG_ON(!priv->chip->mib_decs || !priv->chip->num_mibs);
1561
1562         len = priv->dev.ports * priv->chip->num_mibs *
1563               sizeof(*priv->mib_stats);
1564         priv->mib_stats = kzalloc(len, GFP_KERNEL);
1565
1566         if (!priv->mib_stats)
1567                 return -ENOMEM;
1568
1569         return 0;
1570 }
1571
1572 static void
1573 ar8xxx_mib_start(struct ar8xxx_priv *priv)
1574 {
1575         if (!ar8xxx_has_mib_counters(priv))
1576                 return;
1577
1578         schedule_delayed_work(&priv->mib_work,
1579                               msecs_to_jiffies(AR8XXX_MIB_WORK_DELAY));
1580 }
1581
1582 static void
1583 ar8xxx_mib_stop(struct ar8xxx_priv *priv)
1584 {
1585         if (!ar8xxx_has_mib_counters(priv))
1586                 return;
1587
1588         cancel_delayed_work(&priv->mib_work);
1589 }
1590
1591 static struct ar8xxx_priv *
1592 ar8xxx_create(void)
1593 {
1594         struct ar8xxx_priv *priv;
1595
1596         priv = kzalloc(sizeof(struct ar8xxx_priv), GFP_KERNEL);
1597         if (priv == NULL)
1598                 return NULL;
1599
1600         mutex_init(&priv->reg_mutex);
1601         mutex_init(&priv->mib_lock);
1602         INIT_DELAYED_WORK(&priv->mib_work, ar8xxx_mib_work_func);
1603
1604         return priv;
1605 }
1606
1607 static void
1608 ar8xxx_free(struct ar8xxx_priv *priv)
1609 {
1610         if (priv->chip && priv->chip->cleanup)
1611                 priv->chip->cleanup(priv);
1612
1613         kfree(priv->chip_data);
1614         kfree(priv->mib_stats);
1615         kfree(priv);
1616 }
1617
1618 static int
1619 ar8xxx_probe_switch(struct ar8xxx_priv *priv)
1620 {
1621         const struct ar8xxx_chip *chip;
1622         struct switch_dev *swdev;
1623         int ret;
1624
1625         ret = ar8xxx_id_chip(priv);
1626         if (ret)
1627                 return ret;
1628
1629         chip = priv->chip;
1630
1631         swdev = &priv->dev;
1632         swdev->cpu_port = AR8216_PORT_CPU;
1633         swdev->name = chip->name;
1634         swdev->vlans = chip->vlans;
1635         swdev->ports = chip->ports;
1636         swdev->ops = chip->swops;
1637
1638         ret = ar8xxx_mib_init(priv);
1639         if (ret)
1640                 return ret;
1641
1642         return 0;
1643 }
1644
1645 static int
1646 ar8xxx_start(struct ar8xxx_priv *priv)
1647 {
1648         int ret;
1649
1650         priv->init = true;
1651
1652         ret = priv->chip->hw_init(priv);
1653         if (ret)
1654                 return ret;
1655
1656         ret = ar8xxx_sw_reset_switch(&priv->dev);
1657         if (ret)
1658                 return ret;
1659
1660         priv->init = false;
1661
1662         ar8xxx_mib_start(priv);
1663
1664         return 0;
1665 }
1666
1667 static int
1668 ar8xxx_phy_config_init(struct phy_device *phydev)
1669 {
1670         struct ar8xxx_priv *priv = phydev->priv;
1671         struct net_device *dev = phydev->attached_dev;
1672         int ret;
1673
1674         if (WARN_ON(!priv))
1675                 return -ENODEV;
1676
1677         if (priv->chip->config_at_probe)
1678                 return ar8xxx_phy_check_aneg(phydev);
1679
1680         priv->phy = phydev;
1681
1682         if (phydev->addr != 0) {
1683                 if (chip_is_ar8316(priv)) {
1684                         /* switch device has been initialized, reinit */
1685                         priv->dev.ports = (AR8216_NUM_PORTS - 1);
1686                         priv->initialized = false;
1687                         priv->port4_phy = true;
1688                         ar8316_hw_init(priv);
1689                         return 0;
1690                 }
1691
1692                 return 0;
1693         }
1694
1695         ret = ar8xxx_start(priv);
1696         if (ret)
1697                 return ret;
1698
1699         /* VID fixup only needed on ar8216 */
1700         if (chip_is_ar8216(priv)) {
1701                 dev->phy_ptr = priv;
1702                 dev->priv_flags |= IFF_NO_IP_ALIGN;
1703                 dev->eth_mangle_rx = ar8216_mangle_rx;
1704                 dev->eth_mangle_tx = ar8216_mangle_tx;
1705         }
1706
1707         return 0;
1708 }
1709
1710 static int
1711 ar8xxx_phy_read_status(struct phy_device *phydev)
1712 {
1713         struct ar8xxx_priv *priv = phydev->priv;
1714         struct switch_port_link link;
1715
1716         if (phydev->addr != 0)
1717                 return genphy_read_status(phydev);
1718
1719         ar8216_read_port_link(priv, phydev->addr, &link);
1720         phydev->link = !!link.link;
1721         if (!phydev->link)
1722                 return 0;
1723
1724         switch (link.speed) {
1725         case SWITCH_PORT_SPEED_10:
1726                 phydev->speed = SPEED_10;
1727                 break;
1728         case SWITCH_PORT_SPEED_100:
1729                 phydev->speed = SPEED_100;
1730                 break;
1731         case SWITCH_PORT_SPEED_1000:
1732                 phydev->speed = SPEED_1000;
1733                 break;
1734         default:
1735                 phydev->speed = 0;
1736         }
1737         phydev->duplex = link.duplex ? DUPLEX_FULL : DUPLEX_HALF;
1738
1739         phydev->state = PHY_RUNNING;
1740         netif_carrier_on(phydev->attached_dev);
1741         phydev->adjust_link(phydev->attached_dev);
1742
1743         return 0;
1744 }
1745
1746 static int
1747 ar8xxx_phy_config_aneg(struct phy_device *phydev)
1748 {
1749         if (phydev->addr == 0)
1750                 return 0;
1751
1752         return genphy_config_aneg(phydev);
1753 }
1754
1755 static const u32 ar8xxx_phy_ids[] = {
1756         0x004dd033,
1757         0x004dd034, /* AR8327 */
1758         0x004dd036, /* AR8337 */
1759         0x004dd041,
1760         0x004dd042,
1761         0x004dd043, /* AR8236 */
1762 };
1763
1764 static bool
1765 ar8xxx_phy_match(u32 phy_id)
1766 {
1767         int i;
1768
1769         for (i = 0; i < ARRAY_SIZE(ar8xxx_phy_ids); i++)
1770                 if (phy_id == ar8xxx_phy_ids[i])
1771                         return true;
1772
1773         return false;
1774 }
1775
1776 static bool
1777 ar8xxx_is_possible(struct mii_bus *bus)
1778 {
1779         unsigned i;
1780
1781         for (i = 0; i < 4; i++) {
1782                 u32 phy_id;
1783
1784                 phy_id = mdiobus_read(bus, i, MII_PHYSID1) << 16;
1785                 phy_id |= mdiobus_read(bus, i, MII_PHYSID2);
1786                 if (!ar8xxx_phy_match(phy_id)) {
1787                         pr_debug("ar8xxx: unknown PHY at %s:%02x id:%08x\n",
1788                                  dev_name(&bus->dev), i, phy_id);
1789                         return false;
1790                 }
1791         }
1792
1793         return true;
1794 }
1795
1796 static int
1797 ar8xxx_phy_probe(struct phy_device *phydev)
1798 {
1799         struct ar8xxx_priv *priv;
1800         struct switch_dev *swdev;
1801         int ret;
1802
1803         /* skip PHYs at unused adresses */
1804         if (phydev->addr != 0 && phydev->addr != 4)
1805                 return -ENODEV;
1806
1807         if (!ar8xxx_is_possible(phydev->bus))
1808                 return -ENODEV;
1809
1810         mutex_lock(&ar8xxx_dev_list_lock);
1811         list_for_each_entry(priv, &ar8xxx_dev_list, list)
1812                 if (priv->mii_bus == phydev->bus)
1813                         goto found;
1814
1815         priv = ar8xxx_create();
1816         if (priv == NULL) {
1817                 ret = -ENOMEM;
1818                 goto unlock;
1819         }
1820
1821         priv->mii_bus = phydev->bus;
1822
1823         ret = ar8xxx_probe_switch(priv);
1824         if (ret)
1825                 goto free_priv;
1826
1827         swdev = &priv->dev;
1828         swdev->alias = dev_name(&priv->mii_bus->dev);
1829         ret = register_switch(swdev, NULL);
1830         if (ret)
1831                 goto free_priv;
1832
1833         pr_info("%s: %s rev. %u switch registered on %s\n",
1834                 swdev->devname, swdev->name, priv->chip_rev,
1835                 dev_name(&priv->mii_bus->dev));
1836
1837 found:
1838         priv->use_count++;
1839
1840         if (phydev->addr == 0) {
1841                 if (ar8xxx_has_gige(priv)) {
1842                         phydev->supported = SUPPORTED_1000baseT_Full;
1843                         phydev->advertising = ADVERTISED_1000baseT_Full;
1844                 } else {
1845                         phydev->supported = SUPPORTED_100baseT_Full;
1846                         phydev->advertising = ADVERTISED_100baseT_Full;
1847                 }
1848
1849                 if (priv->chip->config_at_probe) {
1850                         priv->phy = phydev;
1851
1852                         ret = ar8xxx_start(priv);
1853                         if (ret)
1854                                 goto err_unregister_switch;
1855                 }
1856         } else {
1857                 if (ar8xxx_has_gige(priv)) {
1858                         phydev->supported |= SUPPORTED_1000baseT_Full;
1859                         phydev->advertising |= ADVERTISED_1000baseT_Full;
1860                 }
1861         }
1862
1863         phydev->priv = priv;
1864
1865         list_add(&priv->list, &ar8xxx_dev_list);
1866
1867         mutex_unlock(&ar8xxx_dev_list_lock);
1868
1869         return 0;
1870
1871 err_unregister_switch:
1872         if (--priv->use_count)
1873                 goto unlock;
1874
1875         unregister_switch(&priv->dev);
1876
1877 free_priv:
1878         ar8xxx_free(priv);
1879 unlock:
1880         mutex_unlock(&ar8xxx_dev_list_lock);
1881         return ret;
1882 }
1883
1884 static void
1885 ar8xxx_phy_detach(struct phy_device *phydev)
1886 {
1887         struct net_device *dev = phydev->attached_dev;
1888
1889         if (!dev)
1890                 return;
1891
1892         dev->phy_ptr = NULL;
1893         dev->priv_flags &= ~IFF_NO_IP_ALIGN;
1894         dev->eth_mangle_rx = NULL;
1895         dev->eth_mangle_tx = NULL;
1896 }
1897
1898 static void
1899 ar8xxx_phy_remove(struct phy_device *phydev)
1900 {
1901         struct ar8xxx_priv *priv = phydev->priv;
1902
1903         if (WARN_ON(!priv))
1904                 return;
1905
1906         phydev->priv = NULL;
1907         if (--priv->use_count > 0)
1908                 return;
1909
1910         mutex_lock(&ar8xxx_dev_list_lock);
1911         list_del(&priv->list);
1912         mutex_unlock(&ar8xxx_dev_list_lock);
1913
1914         unregister_switch(&priv->dev);
1915         ar8xxx_mib_stop(priv);
1916         ar8xxx_free(priv);
1917 }
1918
1919 #if LINUX_VERSION_CODE >= KERNEL_VERSION(3,14,0)
1920 static int
1921 ar8xxx_phy_soft_reset(struct phy_device *phydev)
1922 {
1923         /* we don't need an extra reset */
1924         return 0;
1925 }
1926 #endif
1927
1928 static struct phy_driver ar8xxx_phy_driver = {
1929         .phy_id         = 0x004d0000,
1930         .name           = "Atheros AR8216/AR8236/AR8316",
1931         .phy_id_mask    = 0xffff0000,
1932         .features       = PHY_BASIC_FEATURES,
1933         .probe          = ar8xxx_phy_probe,
1934         .remove         = ar8xxx_phy_remove,
1935         .detach         = ar8xxx_phy_detach,
1936         .config_init    = ar8xxx_phy_config_init,
1937         .config_aneg    = ar8xxx_phy_config_aneg,
1938         .read_status    = ar8xxx_phy_read_status,
1939 #if LINUX_VERSION_CODE >= KERNEL_VERSION(3,14,0)
1940         .soft_reset     = ar8xxx_phy_soft_reset,
1941 #endif
1942         .driver         = { .owner = THIS_MODULE },
1943 };
1944
1945 int __init
1946 ar8xxx_init(void)
1947 {
1948         return phy_driver_register(&ar8xxx_phy_driver);
1949 }
1950
1951 void __exit
1952 ar8xxx_exit(void)
1953 {
1954         phy_driver_unregister(&ar8xxx_phy_driver);
1955 }
1956
1957 module_init(ar8xxx_init);
1958 module_exit(ar8xxx_exit);
1959 MODULE_LICENSE("GPL");
1960