target/linux/generic/files/drivers/net/phy/ar8216.c

   1 /*
   2  * ar8216.c: AR8216 switch driver
   3  *
   4  * Copyright (C) 2009 Felix Fietkau <nbd@nbd.name>
   5  * Copyright (C) 2011-2012 Gabor Juhos <juhosg@openwrt.org>
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License
   9  * as published by the Free Software Foundation; either version 2
  10  * of the License, or (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  */
  17
  18 #include <linux/if.h>
  19 #include <linux/module.h>
  20 #include <linux/init.h>
  21 #include <linux/list.h>
  22 #include <linux/if_ether.h>
  23 #include <linux/skbuff.h>
  24 #include <linux/netdevice.h>
  25 #include <linux/netlink.h>
  26 #include <linux/bitops.h>
  27 #include <net/genetlink.h>
  28 #include <linux/switch.h>
  29 #include <linux/delay.h>
  30 #include <linux/phy.h>
  31 #include <linux/netdevice.h>
  32 #include <linux/etherdevice.h>
  33 #include <linux/lockdep.h>
  34 #include <linux/ar8216_platform.h>
  35 #include <linux/workqueue.h>
  36 #include <linux/version.h>
  37
  38 #include "ar8216.h"
  39
  40 extern const struct ar8xxx_chip ar8327_chip;
  41 extern const struct ar8xxx_chip ar8337_chip;
  42
  43 #define AR8XXX_MIB_WORK_DELAY   2000 /* msecs */
  44
  45 #define MIB_DESC(_s , _o, _n)   \
  46         {                       \
  47                 .size = (_s),   \
  48                 .offset = (_o), \
  49                 .name = (_n),   \
  50         }
  51
  52 static const struct ar8xxx_mib_desc ar8216_mibs[] = {
  53         MIB_DESC(1, AR8216_STATS_RXBROAD, "RxBroad"),
  54         MIB_DESC(1, AR8216_STATS_RXPAUSE, "RxPause"),
  55         MIB_DESC(1, AR8216_STATS_RXMULTI, "RxMulti"),
  56         MIB_DESC(1, AR8216_STATS_RXFCSERR, "RxFcsErr"),
  57         MIB_DESC(1, AR8216_STATS_RXALIGNERR, "RxAlignErr"),
  58         MIB_DESC(1, AR8216_STATS_RXRUNT, "RxRunt"),
  59         MIB_DESC(1, AR8216_STATS_RXFRAGMENT, "RxFragment"),
  60         MIB_DESC(1, AR8216_STATS_RX64BYTE, "Rx64Byte"),
  61         MIB_DESC(1, AR8216_STATS_RX128BYTE, "Rx128Byte"),
  62         MIB_DESC(1, AR8216_STATS_RX256BYTE, "Rx256Byte"),
  63         MIB_DESC(1, AR8216_STATS_RX512BYTE, "Rx512Byte"),
  64         MIB_DESC(1, AR8216_STATS_RX1024BYTE, "Rx1024Byte"),
  65         MIB_DESC(1, AR8216_STATS_RXMAXBYTE, "RxMaxByte"),
  66         MIB_DESC(1, AR8216_STATS_RXTOOLONG, "RxTooLong"),
  67         MIB_DESC(2, AR8216_STATS_RXGOODBYTE, "RxGoodByte"),
  68         MIB_DESC(2, AR8216_STATS_RXBADBYTE, "RxBadByte"),
  69         MIB_DESC(1, AR8216_STATS_RXOVERFLOW, "RxOverFlow"),
  70         MIB_DESC(1, AR8216_STATS_FILTERED, "Filtered"),
  71         MIB_DESC(1, AR8216_STATS_TXBROAD, "TxBroad"),
  72         MIB_DESC(1, AR8216_STATS_TXPAUSE, "TxPause"),
  73         MIB_DESC(1, AR8216_STATS_TXMULTI, "TxMulti"),
  74         MIB_DESC(1, AR8216_STATS_TXUNDERRUN, "TxUnderRun"),
  75         MIB_DESC(1, AR8216_STATS_TX64BYTE, "Tx64Byte"),
  76         MIB_DESC(1, AR8216_STATS_TX128BYTE, "Tx128Byte"),
  77         MIB_DESC(1, AR8216_STATS_TX256BYTE, "Tx256Byte"),
  78         MIB_DESC(1, AR8216_STATS_TX512BYTE, "Tx512Byte"),
  79         MIB_DESC(1, AR8216_STATS_TX1024BYTE, "Tx1024Byte"),
  80         MIB_DESC(1, AR8216_STATS_TXMAXBYTE, "TxMaxByte"),
  81         MIB_DESC(1, AR8216_STATS_TXOVERSIZE, "TxOverSize"),
  82         MIB_DESC(2, AR8216_STATS_TXBYTE, "TxByte"),
  83         MIB_DESC(1, AR8216_STATS_TXCOLLISION, "TxCollision"),
  84         MIB_DESC(1, AR8216_STATS_TXABORTCOL, "TxAbortCol"),
  85         MIB_DESC(1, AR8216_STATS_TXMULTICOL, "TxMultiCol"),
  86         MIB_DESC(1, AR8216_STATS_TXSINGLECOL, "TxSingleCol"),
  87         MIB_DESC(1, AR8216_STATS_TXEXCDEFER, "TxExcDefer"),
  88         MIB_DESC(1, AR8216_STATS_TXDEFER, "TxDefer"),
  89         MIB_DESC(1, AR8216_STATS_TXLATECOL, "TxLateCol"),
  90 };
  91
  92 const struct ar8xxx_mib_desc ar8236_mibs[39] = {
  93         MIB_DESC(1, AR8236_STATS_RXBROAD, "RxBroad"),
  94         MIB_DESC(1, AR8236_STATS_RXPAUSE, "RxPause"),
  95         MIB_DESC(1, AR8236_STATS_RXMULTI, "RxMulti"),
  96         MIB_DESC(1, AR8236_STATS_RXFCSERR, "RxFcsErr"),
  97         MIB_DESC(1, AR8236_STATS_RXALIGNERR, "RxAlignErr"),
  98         MIB_DESC(1, AR8236_STATS_RXRUNT, "RxRunt"),
  99         MIB_DESC(1, AR8236_STATS_RXFRAGMENT, "RxFragment"),
 100         MIB_DESC(1, AR8236_STATS_RX64BYTE, "Rx64Byte"),
 101         MIB_DESC(1, AR8236_STATS_RX128BYTE, "Rx128Byte"),
 102         MIB_DESC(1, AR8236_STATS_RX256BYTE, "Rx256Byte"),
 103         MIB_DESC(1, AR8236_STATS_RX512BYTE, "Rx512Byte"),
 104         MIB_DESC(1, AR8236_STATS_RX1024BYTE, "Rx1024Byte"),
 105         MIB_DESC(1, AR8236_STATS_RX1518BYTE, "Rx1518Byte"),
 106         MIB_DESC(1, AR8236_STATS_RXMAXBYTE, "RxMaxByte"),
 107         MIB_DESC(1, AR8236_STATS_RXTOOLONG, "RxTooLong"),
 108         MIB_DESC(2, AR8236_STATS_RXGOODBYTE, "RxGoodByte"),
 109         MIB_DESC(2, AR8236_STATS_RXBADBYTE, "RxBadByte"),
 110         MIB_DESC(1, AR8236_STATS_RXOVERFLOW, "RxOverFlow"),
 111         MIB_DESC(1, AR8236_STATS_FILTERED, "Filtered"),
 112         MIB_DESC(1, AR8236_STATS_TXBROAD, "TxBroad"),
 113         MIB_DESC(1, AR8236_STATS_TXPAUSE, "TxPause"),
 114         MIB_DESC(1, AR8236_STATS_TXMULTI, "TxMulti"),
 115         MIB_DESC(1, AR8236_STATS_TXUNDERRUN, "TxUnderRun"),
 116         MIB_DESC(1, AR8236_STATS_TX64BYTE, "Tx64Byte"),
 117         MIB_DESC(1, AR8236_STATS_TX128BYTE, "Tx128Byte"),
 118         MIB_DESC(1, AR8236_STATS_TX256BYTE, "Tx256Byte"),
 119         MIB_DESC(1, AR8236_STATS_TX512BYTE, "Tx512Byte"),
 120         MIB_DESC(1, AR8236_STATS_TX1024BYTE, "Tx1024Byte"),
 121         MIB_DESC(1, AR8236_STATS_TX1518BYTE, "Tx1518Byte"),
 122         MIB_DESC(1, AR8236_STATS_TXMAXBYTE, "TxMaxByte"),
 123         MIB_DESC(1, AR8236_STATS_TXOVERSIZE, "TxOverSize"),
 124         MIB_DESC(2, AR8236_STATS_TXBYTE, "TxByte"),
 125         MIB_DESC(1, AR8236_STATS_TXCOLLISION, "TxCollision"),
 126         MIB_DESC(1, AR8236_STATS_TXABORTCOL, "TxAbortCol"),
 127         MIB_DESC(1, AR8236_STATS_TXMULTICOL, "TxMultiCol"),
 128         MIB_DESC(1, AR8236_STATS_TXSINGLECOL, "TxSingleCol"),
 129         MIB_DESC(1, AR8236_STATS_TXEXCDEFER, "TxExcDefer"),
 130         MIB_DESC(1, AR8236_STATS_TXDEFER, "TxDefer"),
 131         MIB_DESC(1, AR8236_STATS_TXLATECOL, "TxLateCol"),
 132 };
 133
 134 static DEFINE_MUTEX(ar8xxx_dev_list_lock);
 135 static LIST_HEAD(ar8xxx_dev_list);
 136
 137 /* inspired by phy_poll_reset in drivers/net/phy/phy_device.c */
 138 static int
 139 ar8xxx_phy_poll_reset(struct mii_bus *bus)
 140 {
 141         unsigned int sleep_msecs = 20;
 142         int ret, elapsed, i;
 143
 144         for (elapsed = sleep_msecs; elapsed <= 600;
 145              elapsed += sleep_msecs) {
 146                 msleep(sleep_msecs);
 147                 for (i = 0; i < AR8XXX_NUM_PHYS; i++) {
 148                         ret = mdiobus_read(bus, i, MII_BMCR);
 149                         if (ret < 0)
 150                                 return ret;
 151                         if (ret & BMCR_RESET)
 152                                 break;
 153                         if (i == AR8XXX_NUM_PHYS - 1) {
 154                                 usleep_range(1000, 2000);
 155                                 return 0;
 156                         }
 157                 }
 158         }
 159         return -ETIMEDOUT;
 160 }
 161
 162 static int
 163 ar8xxx_phy_check_aneg(struct phy_device *phydev)
 164 {
 165         int ret;
 166
 167         if (phydev->autoneg != AUTONEG_ENABLE)
 168                 return 0;
 169         /*
 170          * BMCR_ANENABLE might have been cleared
 171          * by phy_init_hw in certain kernel versions
 172          * therefore check for it
 173          */
 174         ret = phy_read(phydev, MII_BMCR);
 175         if (ret < 0)
 176                 return ret;
 177         if (ret & BMCR_ANENABLE)
 178                 return 0;
 179
 180         dev_info(&phydev->dev, "ANEG disabled, re-enabling ...\n");
 181         ret |= BMCR_ANENABLE | BMCR_ANRESTART;
 182         return phy_write(phydev, MII_BMCR, ret);
 183 }
 184
 185 void
 186 ar8xxx_phy_init(struct ar8xxx_priv *priv)
 187 {
 188         int i;
 189         struct mii_bus *bus;
 190
 191         bus = priv->mii_bus;
 192         for (i = 0; i < AR8XXX_NUM_PHYS; i++) {
 193                 if (priv->chip->phy_fixup)
 194                         priv->chip->phy_fixup(priv, i);
 195
 196                 /* initialize the port itself */
 197                 mdiobus_write(bus, i, MII_ADVERTISE,
 198                         ADVERTISE_ALL | ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
 199                 if (ar8xxx_has_gige(priv))
 200                         mdiobus_write(bus, i, MII_CTRL1000, ADVERTISE_1000FULL);
 201                 mdiobus_write(bus, i, MII_BMCR, BMCR_RESET | BMCR_ANENABLE);
 202         }
 203
 204         ar8xxx_phy_poll_reset(bus);
 205 }
 206
 207 u32
 208 ar8xxx_mii_read32(struct ar8xxx_priv *priv, int phy_id, int regnum)
 209 {
 210         struct mii_bus *bus = priv->mii_bus;
 211         u16 lo, hi;
 212
 213         lo = bus->read(bus, phy_id, regnum);
 214         hi = bus->read(bus, phy_id, regnum + 1);
 215
 216         return (hi << 16) | lo;
 217 }
 218
 219 void
 220 ar8xxx_mii_write32(struct ar8xxx_priv *priv, int phy_id, int regnum, u32 val)
 221 {
 222         struct mii_bus *bus = priv->mii_bus;
 223         u16 lo, hi;
 224
 225         lo = val & 0xffff;
 226         hi = (u16) (val >> 16);
 227
 228         if (priv->chip->mii_lo_first)
 229         {
 230                 bus->write(bus, phy_id, regnum, lo);
 231                 bus->write(bus, phy_id, regnum + 1, hi);
 232         } else {
 233                 bus->write(bus, phy_id, regnum + 1, hi);
 234                 bus->write(bus, phy_id, regnum, lo);
 235         }
 236 }
 237
 238 u32
 239 ar8xxx_read(struct ar8xxx_priv *priv, int reg)
 240 {
 241         struct mii_bus *bus = priv->mii_bus;
 242         u16 r1, r2, page;
 243         u32 val;
 244
 245         split_addr((u32) reg, &r1, &r2, &page);
 246
 247         mutex_lock(&bus->mdio_lock);
 248
 249         bus->write(bus, 0x18, 0, page);
 250         wait_for_page_switch();
 251         val = ar8xxx_mii_read32(priv, 0x10 | r2, r1);
 252
 253         mutex_unlock(&bus->mdio_lock);
 254
 255         return val;
 256 }
 257
 258 void
 259 ar8xxx_write(struct ar8xxx_priv *priv, int reg, u32 val)
 260 {
 261         struct mii_bus *bus = priv->mii_bus;
 262         u16 r1, r2, page;
 263
 264         split_addr((u32) reg, &r1, &r2, &page);
 265
 266         mutex_lock(&bus->mdio_lock);
 267
 268         bus->write(bus, 0x18, 0, page);
 269         wait_for_page_switch();
 270         ar8xxx_mii_write32(priv, 0x10 | r2, r1, val);
 271
 272         mutex_unlock(&bus->mdio_lock);
 273 }
 274
 275 u32
 276 ar8xxx_rmw(struct ar8xxx_priv *priv, int reg, u32 mask, u32 val)
 277 {
 278         struct mii_bus *bus = priv->mii_bus;
 279         u16 r1, r2, page;
 280         u32 ret;
 281
 282         split_addr((u32) reg, &r1, &r2, &page);
 283
 284         mutex_lock(&bus->mdio_lock);
 285
 286         bus->write(bus, 0x18, 0, page);
 287         wait_for_page_switch();
 288
 289         ret = ar8xxx_mii_read32(priv, 0x10 | r2, r1);
 290         ret &= ~mask;
 291         ret |= val;
 292         ar8xxx_mii_write32(priv, 0x10 | r2, r1, ret);
 293
 294         mutex_unlock(&bus->mdio_lock);
 295
 296         return ret;
 297 }
 298
 299 void
 300 ar8xxx_phy_dbg_write(struct ar8xxx_priv *priv, int phy_addr,
 301                      u16 dbg_addr, u16 dbg_data)
 302 {
 303         struct mii_bus *bus = priv->mii_bus;
 304
 305         mutex_lock(&bus->mdio_lock);
 306         bus->write(bus, phy_addr, MII_ATH_DBG_ADDR, dbg_addr);
 307         bus->write(bus, phy_addr, MII_ATH_DBG_DATA, dbg_data);
 308         mutex_unlock(&bus->mdio_lock);
 309 }
 310
 311 static inline void
 312 ar8xxx_phy_mmd_prep(struct mii_bus *bus, int phy_addr, u16 addr, u16 reg)
 313 {
 314         bus->write(bus, phy_addr, MII_ATH_MMD_ADDR, addr);
 315         bus->write(bus, phy_addr, MII_ATH_MMD_DATA, reg);
 316         bus->write(bus, phy_addr, MII_ATH_MMD_ADDR, addr | 0x4000);
 317 }
 318
 319 void
 320 ar8xxx_phy_mmd_write(struct ar8xxx_priv *priv, int phy_addr, u16 addr, u16 reg, u16 data)
 321 {
 322         struct mii_bus *bus = priv->mii_bus;
 323
 324         mutex_lock(&bus->mdio_lock);
 325         ar8xxx_phy_mmd_prep(bus, phy_addr, addr, reg);
 326         bus->write(bus, phy_addr, MII_ATH_MMD_DATA, data);
 327         mutex_unlock(&bus->mdio_lock);
 328 }
 329
 330 u16
 331 ar8xxx_phy_mmd_read(struct ar8xxx_priv *priv, int phy_addr, u16 addr, u16 reg)
 332 {
 333         struct mii_bus *bus = priv->mii_bus;
 334         u16 data;
 335
 336         mutex_lock(&bus->mdio_lock);
 337         ar8xxx_phy_mmd_prep(bus, phy_addr, addr, reg);
 338         data = bus->read(bus, phy_addr, MII_ATH_MMD_DATA);
 339         mutex_unlock(&bus->mdio_lock);
 340
 341         return data;
 342 }
 343
 344 static int
 345 ar8xxx_reg_wait(struct ar8xxx_priv *priv, u32 reg, u32 mask, u32 val,
 346                 unsigned timeout)
 347 {
 348         int i;
 349
 350         for (i = 0; i < timeout; i++) {
 351                 u32 t;
 352
 353                 t = ar8xxx_read(priv, reg);
 354                 if ((t & mask) == val)
 355                         return 0;
 356
 357                 usleep_range(1000, 2000);
 358         }
 359
 360         return -ETIMEDOUT;
 361 }
 362
 363 static int
 364 ar8xxx_mib_op(struct ar8xxx_priv *priv, u32 op)
 365 {
 366         unsigned mib_func = priv->chip->mib_func;
 367         int ret;
 368
 369         lockdep_assert_held(&priv->mib_lock);
 370
 371         /* Capture the hardware statistics for all ports */
 372         ar8xxx_rmw(priv, mib_func, AR8216_MIB_FUNC, (op << AR8216_MIB_FUNC_S));
 373
 374         /* Wait for the capturing to complete. */
 375         ret = ar8xxx_reg_wait(priv, mib_func, AR8216_MIB_BUSY, 0, 10);
 376         if (ret)
 377                 goto out;
 378
 379         ret = 0;
 380
 381 out:
 382         return ret;
 383 }
 384
 385 static int
 386 ar8xxx_mib_capture(struct ar8xxx_priv *priv)
 387 {
 388         return ar8xxx_mib_op(priv, AR8216_MIB_FUNC_CAPTURE);
 389 }
 390
 391 static int
 392 ar8xxx_mib_flush(struct ar8xxx_priv *priv)
 393 {
 394         return ar8xxx_mib_op(priv, AR8216_MIB_FUNC_FLUSH);
 395 }
 396
 397 static void
 398 ar8xxx_mib_fetch_port_stat(struct ar8xxx_priv *priv, int port, bool flush)
 399 {
 400         unsigned int base;
 401         u64 *mib_stats;
 402         int i;
 403
 404         WARN_ON(port >= priv->dev.ports);
 405
 406         lockdep_assert_held(&priv->mib_lock);
 407
 408         base = priv->chip->reg_port_stats_start +
 409                priv->chip->reg_port_stats_length * port;
 410
 411         mib_stats = &priv->mib_stats[port * priv->chip->num_mibs];
 412         for (i = 0; i < priv->chip->num_mibs; i++) {
 413                 const struct ar8xxx_mib_desc *mib;
 414                 u64 t;
 415
 416                 mib = &priv->chip->mib_decs[i];
 417                 t = ar8xxx_read(priv, base + mib->offset);
 418                 if (mib->size == 2) {
 419                         u64 hi;
 420
 421                         hi = ar8xxx_read(priv, base + mib->offset + 4);
 422                         t |= hi << 32;
 423                 }
 424
 425                 if (flush)
 426                         mib_stats[i] = 0;
 427                 else
 428                         mib_stats[i] += t;
 429         }
 430 }
 431
 432 static void
 433 ar8216_read_port_link(struct ar8xxx_priv *priv, int port,
 434                       struct switch_port_link *link)
 435 {
 436         u32 status;
 437         u32 speed;
 438
 439         memset(link, '\0', sizeof(*link));
 440
 441         status = priv->chip->read_port_status(priv, port);
 442
 443         link->aneg = !!(status & AR8216_PORT_STATUS_LINK_AUTO);
 444         if (link->aneg) {
 445                 link->link = !!(status & AR8216_PORT_STATUS_LINK_UP);
 446         } else {
 447                 link->link = true;
 448
 449                 if (priv->get_port_link) {
 450                         int err;
 451
 452                         err = priv->get_port_link(port);
 453                         if (err >= 0)
 454                                 link->link = !!err;
 455                 }
 456         }
 457
 458         if (!link->link)
 459                 return;
 460
 461         link->duplex = !!(status & AR8216_PORT_STATUS_DUPLEX);
 462         link->tx_flow = !!(status & AR8216_PORT_STATUS_TXFLOW);
 463         link->rx_flow = !!(status & AR8216_PORT_STATUS_RXFLOW);
 464
 465         if (link->aneg && link->duplex && priv->chip->read_port_eee_status)
 466                 link->eee = priv->chip->read_port_eee_status(priv, port);
 467
 468         speed = (status & AR8216_PORT_STATUS_SPEED) >>
 469                  AR8216_PORT_STATUS_SPEED_S;
 470
 471         switch (speed) {
 472         case AR8216_PORT_SPEED_10M:
 473                 link->speed = SWITCH_PORT_SPEED_10;
 474                 break;
 475         case AR8216_PORT_SPEED_100M:
 476                 link->speed = SWITCH_PORT_SPEED_100;
 477                 break;
 478         case AR8216_PORT_SPEED_1000M:
 479                 link->speed = SWITCH_PORT_SPEED_1000;
 480                 break;
 481         default:
 482                 link->speed = SWITCH_PORT_SPEED_UNKNOWN;
 483                 break;
 484         }
 485 }
 486
 487 static struct sk_buff *
 488 ar8216_mangle_tx(struct net_device *dev, struct sk_buff *skb)
 489 {
 490         struct ar8xxx_priv *priv = dev->phy_ptr;
 491         unsigned char *buf;
 492
 493         if (unlikely(!priv))
 494                 goto error;
 495
 496         if (!priv->vlan)
 497                 goto send;
 498
 499         if (unlikely(skb_headroom(skb) < 2)) {
 500                 if (pskb_expand_head(skb, 2, 0, GFP_ATOMIC) < 0)
 501                         goto error;
 502         }
 503
 504         buf = skb_push(skb, 2);
 505         buf[0] = 0x10;
 506         buf[1] = 0x80;
 507
 508 send:
 509         return skb;
 510
 511 error:
 512         dev_kfree_skb_any(skb);
 513         return NULL;
 514 }
 515
 516 static void
 517 ar8216_mangle_rx(struct net_device *dev, struct sk_buff *skb)
 518 {
 519         struct ar8xxx_priv *priv;
 520         unsigned char *buf;
 521         int port, vlan;
 522
 523         priv = dev->phy_ptr;
 524         if (!priv)
 525                 return;
 526
 527         /* don't strip the header if vlan mode is disabled */
 528         if (!priv->vlan)
 529                 return;
 530
 531         /* strip header, get vlan id */
 532         buf = skb->data;
 533         skb_pull(skb, 2);
 534
 535         /* check for vlan header presence */
 536         if ((buf[12 + 2] != 0x81) || (buf[13 + 2] != 0x00))
 537                 return;
 538
 539         port = buf[0] & 0xf;
 540
 541         /* no need to fix up packets coming from a tagged source */
 542         if (priv->vlan_tagged & (1 << port))
 543                 return;
 544
 545         /* lookup port vid from local table, the switch passes an invalid vlan id */
 546         vlan = priv->vlan_id[priv->pvid[port]];
 547
 548         buf[14 + 2] &= 0xf0;
 549         buf[14 + 2] |= vlan >> 8;
 550         buf[15 + 2] = vlan & 0xff;
 551 }
 552
 553 int
 554 ar8216_wait_bit(struct ar8xxx_priv *priv, int reg, u32 mask, u32 val)
 555 {
 556         int timeout = 20;
 557         u32 t = 0;
 558
 559         while (1) {
 560                 t = ar8xxx_read(priv, reg);
 561                 if ((t & mask) == val)
 562                         return 0;
 563
 564                 if (timeout-- <= 0)
 565                         break;
 566
 567                 udelay(10);
 568         }
 569
 570         pr_err("ar8216: timeout on reg %08x: %08x & %08x != %08x\n",
 571                (unsigned int) reg, t, mask, val);
 572         return -ETIMEDOUT;
 573 }
 574
 575 static void
 576 ar8216_vtu_op(struct ar8xxx_priv *priv, u32 op, u32 val)
 577 {
 578         if (ar8216_wait_bit(priv, AR8216_REG_VTU, AR8216_VTU_ACTIVE, 0))
 579                 return;
 580         if ((op & AR8216_VTU_OP) == AR8216_VTU_OP_LOAD) {
 581                 val &= AR8216_VTUDATA_MEMBER;
 582                 val |= AR8216_VTUDATA_VALID;
 583                 ar8xxx_write(priv, AR8216_REG_VTU_DATA, val);
 584         }
 585         op |= AR8216_VTU_ACTIVE;
 586         ar8xxx_write(priv, AR8216_REG_VTU, op);
 587 }
 588
 589 static void
 590 ar8216_vtu_flush(struct ar8xxx_priv *priv)
 591 {
 592         ar8216_vtu_op(priv, AR8216_VTU_OP_FLUSH, 0);
 593 }
 594
 595 static void
 596 ar8216_vtu_load_vlan(struct ar8xxx_priv *priv, u32 vid, u32 port_mask)
 597 {
 598         u32 op;
 599
 600         op = AR8216_VTU_OP_LOAD | (vid << AR8216_VTU_VID_S);
 601         ar8216_vtu_op(priv, op, port_mask);
 602 }
 603
 604 static int
 605 ar8216_atu_flush(struct ar8xxx_priv *priv)
 606 {
 607         int ret;
 608
 609         ret = ar8216_wait_bit(priv, AR8216_REG_ATU_FUNC0, AR8216_ATU_ACTIVE, 0);
 610         if (!ret)
 611                 ar8xxx_write(priv, AR8216_REG_ATU_FUNC0, AR8216_ATU_OP_FLUSH |
 612                                                          AR8216_ATU_ACTIVE);
 613
 614         return ret;
 615 }
 616
 617 static int
 618 ar8216_atu_flush_port(struct ar8xxx_priv *priv, int port)
 619 {
 620         u32 t;
 621         int ret;
 622
 623         ret = ar8216_wait_bit(priv, AR8216_REG_ATU_FUNC0, AR8216_ATU_ACTIVE, 0);
 624         if (!ret) {
 625                 t = (port << AR8216_ATU_PORT_NUM_S) | AR8216_ATU_OP_FLUSH_PORT;
 626                 t |= AR8216_ATU_ACTIVE;
 627                 ar8xxx_write(priv, AR8216_REG_ATU_FUNC0, t);
 628         }
 629
 630         return ret;
 631 }
 632
 633 static u32
 634 ar8216_read_port_status(struct ar8xxx_priv *priv, int port)
 635 {
 636         return ar8xxx_read(priv, AR8216_REG_PORT_STATUS(port));
 637 }
 638
 639 static void
 640 ar8216_setup_port(struct ar8xxx_priv *priv, int port, u32 members)
 641 {
 642         u32 header;
 643         u32 egress, ingress;
 644         u32 pvid;
 645
 646         if (priv->vlan) {
 647                 pvid = priv->vlan_id[priv->pvid[port]];
 648                 if (priv->vlan_tagged & (1 << port))
 649                         egress = AR8216_OUT_ADD_VLAN;
 650                 else
 651                         egress = AR8216_OUT_STRIP_VLAN;
 652                 ingress = AR8216_IN_SECURE;
 653         } else {
 654                 pvid = port;
 655                 egress = AR8216_OUT_KEEP;
 656                 ingress = AR8216_IN_PORT_ONLY;
 657         }
 658
 659         if (chip_is_ar8216(priv) && priv->vlan && port == AR8216_PORT_CPU)
 660                 header = AR8216_PORT_CTRL_HEADER;
 661         else
 662                 header = 0;
 663
 664         ar8xxx_rmw(priv, AR8216_REG_PORT_CTRL(port),
 665                    AR8216_PORT_CTRL_LEARN | AR8216_PORT_CTRL_VLAN_MODE |
 666                    AR8216_PORT_CTRL_SINGLE_VLAN | AR8216_PORT_CTRL_STATE |
 667                    AR8216_PORT_CTRL_HEADER | AR8216_PORT_CTRL_LEARN_LOCK,
 668                    AR8216_PORT_CTRL_LEARN | header |
 669                    (egress << AR8216_PORT_CTRL_VLAN_MODE_S) |
 670                    (AR8216_PORT_STATE_FORWARD << AR8216_PORT_CTRL_STATE_S));
 671
 672         ar8xxx_rmw(priv, AR8216_REG_PORT_VLAN(port),
 673                    AR8216_PORT_VLAN_DEST_PORTS | AR8216_PORT_VLAN_MODE |
 674                    AR8216_PORT_VLAN_DEFAULT_ID,
 675                    (members << AR8216_PORT_VLAN_DEST_PORTS_S) |
 676                    (ingress << AR8216_PORT_VLAN_MODE_S) |
 677                    (pvid << AR8216_PORT_VLAN_DEFAULT_ID_S));
 678 }
 679
 680 static int
 681 ar8216_hw_init(struct ar8xxx_priv *priv)
 682 {
 683         if (priv->initialized)
 684                 return 0;
 685
 686         ar8xxx_phy_init(priv);
 687
 688         priv->initialized = true;
 689         return 0;
 690 }
 691
 692 static void
 693 ar8216_init_globals(struct ar8xxx_priv *priv)
 694 {
 695         /* standard atheros magic */
 696         ar8xxx_write(priv, 0x38, 0xc000050e);
 697
 698         ar8xxx_rmw(priv, AR8216_REG_GLOBAL_CTRL,
 699                    AR8216_GCTRL_MTU, 1518 + 8 + 2);
 700 }
 701
 702 static void
 703 ar8216_init_port(struct ar8xxx_priv *priv, int port)
 704 {
 705         /* Enable port learning and tx */
 706         ar8xxx_write(priv, AR8216_REG_PORT_CTRL(port),
 707                 AR8216_PORT_CTRL_LEARN |
 708                 (4 << AR8216_PORT_CTRL_STATE_S));
 709
 710         ar8xxx_write(priv, AR8216_REG_PORT_VLAN(port), 0);
 711
 712         if (port == AR8216_PORT_CPU) {
 713                 ar8xxx_write(priv, AR8216_REG_PORT_STATUS(port),
 714                         AR8216_PORT_STATUS_LINK_UP |
 715                         (ar8xxx_has_gige(priv) ?
 716                                 AR8216_PORT_SPEED_1000M : AR8216_PORT_SPEED_100M) |
 717                         AR8216_PORT_STATUS_TXMAC |
 718                         AR8216_PORT_STATUS_RXMAC |
 719                         (chip_is_ar8316(priv) ? AR8216_PORT_STATUS_RXFLOW : 0) |
 720                         (chip_is_ar8316(priv) ? AR8216_PORT_STATUS_TXFLOW : 0) |
 721                         AR8216_PORT_STATUS_DUPLEX);
 722         } else {
 723                 ar8xxx_write(priv, AR8216_REG_PORT_STATUS(port),
 724                         AR8216_PORT_STATUS_LINK_AUTO);
 725         }
 726 }
 727
 728 static void
 729 ar8216_wait_atu_ready(struct ar8xxx_priv *priv, u16 r2, u16 r1)
 730 {
 731         int timeout = 20;
 732
 733         while (ar8xxx_mii_read32(priv, r2, r1) & AR8216_ATU_ACTIVE && --timeout)
 734                 udelay(10);
 735
 736         if (!timeout)
 737                 pr_err("ar8216: timeout waiting for atu to become ready\n");
 738 }
 739
 740 static void ar8216_get_arl_entry(struct ar8xxx_priv *priv,
 741                                  struct arl_entry *a, u32 *status, enum arl_op op)
 742 {
 743         struct mii_bus *bus = priv->mii_bus;
 744         u16 r2, page;
 745         u16 r1_func0, r1_func1, r1_func2;
 746         u32 t, val0, val1, val2;
 747         int i;
 748
 749         split_addr(AR8216_REG_ATU_FUNC0, &r1_func0, &r2, &page);
 750         r2 |= 0x10;
 751
 752         r1_func1 = (AR8216_REG_ATU_FUNC1 >> 1) & 0x1e;
 753         r1_func2 = (AR8216_REG_ATU_FUNC2 >> 1) & 0x1e;
 754
 755         switch (op) {
 756         case AR8XXX_ARL_INITIALIZE:
 757                 /* all ATU registers are on the same page
 758                 * therefore set page only once
 759                 */
 760                 bus->write(bus, 0x18, 0, page);
 761                 wait_for_page_switch();
 762
 763                 ar8216_wait_atu_ready(priv, r2, r1_func0);
 764
 765                 ar8xxx_mii_write32(priv, r2, r1_func0, AR8216_ATU_OP_GET_NEXT);
 766                 ar8xxx_mii_write32(priv, r2, r1_func1, 0);
 767                 ar8xxx_mii_write32(priv, r2, r1_func2, 0);
 768                 break;
 769         case AR8XXX_ARL_GET_NEXT:
 770                 t = ar8xxx_mii_read32(priv, r2, r1_func0);
 771                 t |= AR8216_ATU_ACTIVE;
 772                 ar8xxx_mii_write32(priv, r2, r1_func0, t);
 773                 ar8216_wait_atu_ready(priv, r2, r1_func0);
 774
 775                 val0 = ar8xxx_mii_read32(priv, r2, r1_func0);
 776                 val1 = ar8xxx_mii_read32(priv, r2, r1_func1);
 777                 val2 = ar8xxx_mii_read32(priv, r2, r1_func2);
 778
 779                 *status = (val2 & AR8216_ATU_STATUS) >> AR8216_ATU_STATUS_S;
 780                 if (!*status)
 781                         break;
 782
 783                 i = 0;
 784                 t = AR8216_ATU_PORT0;
 785                 while (!(val2 & t) && ++i < priv->dev.ports)
 786                         t <<= 1;
 787
 788                 a->port = i;
 789                 a->mac[0] = (val0 & AR8216_ATU_ADDR5) >> AR8216_ATU_ADDR5_S;
 790                 a->mac[1] = (val0 & AR8216_ATU_ADDR4) >> AR8216_ATU_ADDR4_S;
 791                 a->mac[2] = (val1 & AR8216_ATU_ADDR3) >> AR8216_ATU_ADDR3_S;
 792                 a->mac[3] = (val1 & AR8216_ATU_ADDR2) >> AR8216_ATU_ADDR2_S;
 793                 a->mac[4] = (val1 & AR8216_ATU_ADDR1) >> AR8216_ATU_ADDR1_S;
 794                 a->mac[5] = (val1 & AR8216_ATU_ADDR0) >> AR8216_ATU_ADDR0_S;
 795                 break;
 796         }
 797 }
 798
 799 static void
 800 ar8236_setup_port(struct ar8xxx_priv *priv, int port, u32 members)
 801 {
 802         u32 egress, ingress;
 803         u32 pvid;
 804
 805         if (priv->vlan) {
 806                 pvid = priv->vlan_id[priv->pvid[port]];
 807                 if (priv->vlan_tagged & (1 << port))
 808                         egress = AR8216_OUT_ADD_VLAN;
 809                 else
 810                         egress = AR8216_OUT_STRIP_VLAN;
 811                 ingress = AR8216_IN_SECURE;
 812         } else {
 813                 pvid = port;
 814                 egress = AR8216_OUT_KEEP;
 815                 ingress = AR8216_IN_PORT_ONLY;
 816         }
 817
 818         ar8xxx_rmw(priv, AR8216_REG_PORT_CTRL(port),
 819                    AR8216_PORT_CTRL_LEARN | AR8216_PORT_CTRL_VLAN_MODE |
 820                    AR8216_PORT_CTRL_SINGLE_VLAN | AR8216_PORT_CTRL_STATE |
 821                    AR8216_PORT_CTRL_HEADER | AR8216_PORT_CTRL_LEARN_LOCK,
 822                    AR8216_PORT_CTRL_LEARN |
 823                    (egress << AR8216_PORT_CTRL_VLAN_MODE_S) |
 824                    (AR8216_PORT_STATE_FORWARD << AR8216_PORT_CTRL_STATE_S));
 825
 826         ar8xxx_rmw(priv, AR8236_REG_PORT_VLAN(port),
 827                    AR8236_PORT_VLAN_DEFAULT_ID,
 828                    (pvid << AR8236_PORT_VLAN_DEFAULT_ID_S));
 829
 830         ar8xxx_rmw(priv, AR8236_REG_PORT_VLAN2(port),
 831                    AR8236_PORT_VLAN2_VLAN_MODE |
 832                    AR8236_PORT_VLAN2_MEMBER,
 833                    (ingress << AR8236_PORT_VLAN2_VLAN_MODE_S) |
 834                    (members << AR8236_PORT_VLAN2_MEMBER_S));
 835 }
 836
 837 static void
 838 ar8236_init_globals(struct ar8xxx_priv *priv)
 839 {
 840         /* enable jumbo frames */
 841         ar8xxx_rmw(priv, AR8216_REG_GLOBAL_CTRL,
 842                    AR8316_GCTRL_MTU, 9018 + 8 + 2);
 843
 844         /* enable cpu port to receive arp frames */
 845         ar8xxx_reg_set(priv, AR8216_REG_ATU_CTRL,
 846                    AR8236_ATU_CTRL_RES);
 847
 848         /* enable cpu port to receive multicast and broadcast frames */
 849         ar8xxx_reg_set(priv, AR8216_REG_FLOOD_MASK,
 850                    AR8236_FM_CPU_BROADCAST_EN | AR8236_FM_CPU_BCAST_FWD_EN);
 851
 852         /* Enable MIB counters */
 853         ar8xxx_rmw(priv, AR8216_REG_MIB_FUNC, AR8216_MIB_FUNC | AR8236_MIB_EN,
 854                    (AR8216_MIB_FUNC_NO_OP << AR8216_MIB_FUNC_S) |
 855                    AR8236_MIB_EN);
 856 }
 857
 858 static int
 859 ar8316_hw_init(struct ar8xxx_priv *priv)
 860 {
 861         u32 val, newval;
 862
 863         val = ar8xxx_read(priv, AR8316_REG_POSTRIP);
 864
 865         if (priv->phy->interface == PHY_INTERFACE_MODE_RGMII) {
 866                 if (priv->port4_phy) {
 867                         /* value taken from Ubiquiti RouterStation Pro */
 868                         newval = 0x81461bea;
 869                         pr_info("ar8316: Using port 4 as PHY\n");
 870                 } else {
 871                         newval = 0x01261be2;
 872                         pr_info("ar8316: Using port 4 as switch port\n");
 873                 }
 874         } else if (priv->phy->interface == PHY_INTERFACE_MODE_GMII) {
 875                 /* value taken from AVM Fritz!Box 7390 sources */
 876                 newval = 0x010e5b71;
 877         } else {
 878                 /* no known value for phy interface */
 879                 pr_err("ar8316: unsupported mii mode: %d.\n",
 880                        priv->phy->interface);
 881                 return -EINVAL;
 882         }
 883
 884         if (val == newval)
 885                 goto out;
 886
 887         ar8xxx_write(priv, AR8316_REG_POSTRIP, newval);
 888
 889         if (priv->port4_phy &&
 890             priv->phy->interface == PHY_INTERFACE_MODE_RGMII) {
 891                 /* work around for phy4 rgmii mode */
 892                 ar8xxx_phy_dbg_write(priv, 4, 0x12, 0x480c);
 893                 /* rx delay */
 894                 ar8xxx_phy_dbg_write(priv, 4, 0x0, 0x824e);
 895                 /* tx delay */
 896                 ar8xxx_phy_dbg_write(priv, 4, 0x5, 0x3d47);
 897                 msleep(1000);
 898         }
 899
 900         ar8xxx_phy_init(priv);
 901
 902 out:
 903         priv->initialized = true;
 904         return 0;
 905 }
 906
 907 static void
 908 ar8316_init_globals(struct ar8xxx_priv *priv)
 909 {
 910         /* standard atheros magic */
 911         ar8xxx_write(priv, 0x38, 0xc000050e);
 912
 913         /* enable cpu port to receive multicast and broadcast frames */
 914         ar8xxx_write(priv, AR8216_REG_FLOOD_MASK, 0x003f003f);
 915
 916         /* enable jumbo frames */
 917         ar8xxx_rmw(priv, AR8216_REG_GLOBAL_CTRL,
 918                    AR8316_GCTRL_MTU, 9018 + 8 + 2);
 919
 920         /* Enable MIB counters */
 921         ar8xxx_rmw(priv, AR8216_REG_MIB_FUNC, AR8216_MIB_FUNC | AR8236_MIB_EN,
 922                    (AR8216_MIB_FUNC_NO_OP << AR8216_MIB_FUNC_S) |
 923                    AR8236_MIB_EN);
 924 }
 925
 926 int
 927 ar8xxx_sw_set_vlan(struct switch_dev *dev, const struct switch_attr *attr,
 928                    struct switch_val *val)
 929 {
 930         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
 931         priv->vlan = !!val->value.i;
 932         return 0;
 933 }
 934
 935 int
 936 ar8xxx_sw_get_vlan(struct switch_dev *dev, const struct switch_attr *attr,
 937                    struct switch_val *val)
 938 {
 939         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
 940         val->value.i = priv->vlan;
 941         return 0;
 942 }
 943
 944
 945 int
 946 ar8xxx_sw_set_pvid(struct switch_dev *dev, int port, int vlan)
 947 {
 948         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
 949
 950         /* make sure no invalid PVIDs get set */
 951
 952         if (vlan >= dev->vlans)
 953                 return -EINVAL;
 954
 955         priv->pvid[port] = vlan;
 956         return 0;
 957 }
 958
 959 int
 960 ar8xxx_sw_get_pvid(struct switch_dev *dev, int port, int *vlan)
 961 {
 962         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
 963         *vlan = priv->pvid[port];
 964         return 0;
 965 }
 966
 967 static int
 968 ar8xxx_sw_set_vid(struct switch_dev *dev, const struct switch_attr *attr,
 969                   struct switch_val *val)
 970 {
 971         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
 972         priv->vlan_id[val->port_vlan] = val->value.i;
 973         return 0;
 974 }
 975
 976 static int
 977 ar8xxx_sw_get_vid(struct switch_dev *dev, const struct switch_attr *attr,
 978                   struct switch_val *val)
 979 {
 980         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
 981         val->value.i = priv->vlan_id[val->port_vlan];
 982         return 0;
 983 }
 984
 985 int
 986 ar8xxx_sw_get_port_link(struct switch_dev *dev, int port,
 987                         struct switch_port_link *link)
 988 {
 989         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
 990
 991         ar8216_read_port_link(priv, port, link);
 992         return 0;
 993 }
 994
 995 static int
 996 ar8xxx_sw_get_ports(struct switch_dev *dev, struct switch_val *val)
 997 {
 998         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
 999         u8 ports = priv->vlan_table[val->port_vlan];
1000         int i;
1001
1002         val->len = 0;
1003         for (i = 0; i < dev->ports; i++) {
1004                 struct switch_port *p;
1005
1006                 if (!(ports & (1 << i)))
1007                         continue;
1008
1009                 p = &val->value.ports[val->len++];
1010                 p->id = i;
1011                 if (priv->vlan_tagged & (1 << i))
1012                         p->flags = (1 << SWITCH_PORT_FLAG_TAGGED);
1013                 else
1014                         p->flags = 0;
1015         }
1016         return 0;
1017 }
1018
1019 static int
1020 ar8xxx_sw_set_ports(struct switch_dev *dev, struct switch_val *val)
1021 {
1022         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1023         u8 *vt = &priv->vlan_table[val->port_vlan];
1024         int i, j;
1025
1026         *vt = 0;
1027         for (i = 0; i < val->len; i++) {
1028                 struct switch_port *p = &val->value.ports[i];
1029
1030                 if (p->flags & (1 << SWITCH_PORT_FLAG_TAGGED)) {
1031                         priv->vlan_tagged |= (1 << p->id);
1032                 } else {
1033                         priv->vlan_tagged &= ~(1 << p->id);
1034                         priv->pvid[p->id] = val->port_vlan;
1035
1036                         /* make sure that an untagged port does not
1037                          * appear in other vlans */
1038                         for (j = 0; j < AR8X16_MAX_VLANS; j++) {
1039                                 if (j == val->port_vlan)
1040                                         continue;
1041                                 priv->vlan_table[j] &= ~(1 << p->id);
1042                         }
1043                 }
1044
1045                 *vt |= 1 << p->id;
1046         }
1047         return 0;
1048 }
1049
1050 static void
1051 ar8216_set_mirror_regs(struct ar8xxx_priv *priv)
1052 {
1053         int port;
1054
1055         /* reset all mirror registers */
1056         ar8xxx_rmw(priv, AR8216_REG_GLOBAL_CPUPORT,
1057                    AR8216_GLOBAL_CPUPORT_MIRROR_PORT,
1058                    (0xF << AR8216_GLOBAL_CPUPORT_MIRROR_PORT_S));
1059         for (port = 0; port < AR8216_NUM_PORTS; port++) {
1060                 ar8xxx_reg_clear(priv, AR8216_REG_PORT_CTRL(port),
1061                            AR8216_PORT_CTRL_MIRROR_RX);
1062
1063                 ar8xxx_reg_clear(priv, AR8216_REG_PORT_CTRL(port),
1064                            AR8216_PORT_CTRL_MIRROR_TX);
1065         }
1066
1067         /* now enable mirroring if necessary */
1068         if (priv->source_port >= AR8216_NUM_PORTS ||
1069             priv->monitor_port >= AR8216_NUM_PORTS ||
1070             priv->source_port == priv->monitor_port) {
1071                 return;
1072         }
1073
1074         ar8xxx_rmw(priv, AR8216_REG_GLOBAL_CPUPORT,
1075                    AR8216_GLOBAL_CPUPORT_MIRROR_PORT,
1076                    (priv->monitor_port << AR8216_GLOBAL_CPUPORT_MIRROR_PORT_S));
1077
1078         if (priv->mirror_rx)
1079                 ar8xxx_reg_set(priv, AR8216_REG_PORT_CTRL(priv->source_port),
1080                            AR8216_PORT_CTRL_MIRROR_RX);
1081
1082         if (priv->mirror_tx)
1083                 ar8xxx_reg_set(priv, AR8216_REG_PORT_CTRL(priv->source_port),
1084                            AR8216_PORT_CTRL_MIRROR_TX);
1085 }
1086
1087 static inline u32
1088 ar8xxx_age_time_val(int age_time)
1089 {
1090         return (age_time + AR8XXX_REG_ARL_CTRL_AGE_TIME_SECS / 2) /
1091                AR8XXX_REG_ARL_CTRL_AGE_TIME_SECS;
1092 }
1093
1094 static inline void
1095 ar8xxx_set_age_time(struct ar8xxx_priv *priv, int reg)
1096 {
1097         u32 age_time = ar8xxx_age_time_val(priv->arl_age_time);
1098         ar8xxx_rmw(priv, reg, AR8216_ATU_CTRL_AGE_TIME, age_time << AR8216_ATU_CTRL_AGE_TIME_S);
1099 }
1100
1101 int
1102 ar8xxx_sw_hw_apply(struct switch_dev *dev)
1103 {
1104         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1105         const struct ar8xxx_chip *chip = priv->chip;
1106         u8 portmask[AR8X16_MAX_PORTS];
1107         int i, j;
1108
1109         mutex_lock(&priv->reg_mutex);
1110         /* flush all vlan translation unit entries */
1111         priv->chip->vtu_flush(priv);
1112
1113         memset(portmask, 0, sizeof(portmask));
1114         if (!priv->init) {
1115                 /* calculate the port destination masks and load vlans
1116                  * into the vlan translation unit */
1117                 for (j = 0; j < AR8X16_MAX_VLANS; j++) {
1118                         u8 vp = priv->vlan_table[j];
1119
1120                         if (!vp)
1121                                 continue;
1122
1123                         for (i = 0; i < dev->ports; i++) {
1124                                 u8 mask = (1 << i);
1125                                 if (vp & mask)
1126                                         portmask[i] |= vp & ~mask;
1127                         }
1128
1129                         chip->vtu_load_vlan(priv, priv->vlan_id[j],
1130                                             priv->vlan_table[j]);
1131                 }
1132         } else {
1133                 /* vlan disabled:
1134                  * isolate all ports, but connect them to the cpu port */
1135                 for (i = 0; i < dev->ports; i++) {
1136                         if (i == AR8216_PORT_CPU)
1137                                 continue;
1138
1139                         portmask[i] = 1 << AR8216_PORT_CPU;
1140                         portmask[AR8216_PORT_CPU] |= (1 << i);
1141                 }
1142         }
1143
1144         /* update the port destination mask registers and tag settings */
1145         for (i = 0; i < dev->ports; i++) {
1146                 chip->setup_port(priv, i, portmask[i]);
1147         }
1148
1149         chip->set_mirror_regs(priv);
1150
1151         /* set age time */
1152         if (chip->reg_arl_ctrl)
1153                 ar8xxx_set_age_time(priv, chip->reg_arl_ctrl);
1154
1155         mutex_unlock(&priv->reg_mutex);
1156         return 0;
1157 }
1158
1159 int
1160 ar8xxx_sw_reset_switch(struct switch_dev *dev)
1161 {
1162         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1163         const struct ar8xxx_chip *chip = priv->chip;
1164         int i;
1165
1166         mutex_lock(&priv->reg_mutex);
1167         memset(&priv->vlan, 0, sizeof(struct ar8xxx_priv) -
1168                 offsetof(struct ar8xxx_priv, vlan));
1169
1170         for (i = 0; i < AR8X16_MAX_VLANS; i++)
1171                 priv->vlan_id[i] = i;
1172
1173         /* Configure all ports */
1174         for (i = 0; i < dev->ports; i++)
1175                 chip->init_port(priv, i);
1176
1177         priv->mirror_rx = false;
1178         priv->mirror_tx = false;
1179         priv->source_port = 0;
1180         priv->monitor_port = 0;
1181         priv->arl_age_time = AR8XXX_DEFAULT_ARL_AGE_TIME;
1182
1183         chip->init_globals(priv);
1184
1185         mutex_unlock(&priv->reg_mutex);
1186
1187         return chip->sw_hw_apply(dev);
1188 }
1189
1190 int
1191 ar8xxx_sw_set_reset_mibs(struct switch_dev *dev,
1192                          const struct switch_attr *attr,
1193                          struct switch_val *val)
1194 {
1195         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1196         unsigned int len;
1197         int ret;
1198
1199         if (!ar8xxx_has_mib_counters(priv))
1200                 return -EOPNOTSUPP;
1201
1202         mutex_lock(&priv->mib_lock);
1203
1204         len = priv->dev.ports * priv->chip->num_mibs *
1205               sizeof(*priv->mib_stats);
1206         memset(priv->mib_stats, '\0', len);
1207         ret = ar8xxx_mib_flush(priv);
1208         if (ret)
1209                 goto unlock;
1210
1211         ret = 0;
1212
1213 unlock:
1214         mutex_unlock(&priv->mib_lock);
1215         return ret;
1216 }
1217
1218 int
1219 ar8xxx_sw_set_mirror_rx_enable(struct switch_dev *dev,
1220                                const struct switch_attr *attr,
1221                                struct switch_val *val)
1222 {
1223         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1224
1225         mutex_lock(&priv->reg_mutex);
1226         priv->mirror_rx = !!val->value.i;
1227         priv->chip->set_mirror_regs(priv);
1228         mutex_unlock(&priv->reg_mutex);
1229
1230         return 0;
1231 }
1232
1233 int
1234 ar8xxx_sw_get_mirror_rx_enable(struct switch_dev *dev,
1235                                const struct switch_attr *attr,
1236                                struct switch_val *val)
1237 {
1238         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1239         val->value.i = priv->mirror_rx;
1240         return 0;
1241 }
1242
1243 int
1244 ar8xxx_sw_set_mirror_tx_enable(struct switch_dev *dev,
1245                                const struct switch_attr *attr,
1246                                struct switch_val *val)
1247 {
1248         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1249
1250         mutex_lock(&priv->reg_mutex);
1251         priv->mirror_tx = !!val->value.i;
1252         priv->chip->set_mirror_regs(priv);
1253         mutex_unlock(&priv->reg_mutex);
1254
1255         return 0;
1256 }
1257
1258 int
1259 ar8xxx_sw_get_mirror_tx_enable(struct switch_dev *dev,
1260                                const struct switch_attr *attr,
1261                                struct switch_val *val)
1262 {
1263         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1264         val->value.i = priv->mirror_tx;
1265         return 0;
1266 }
1267
1268 int
1269 ar8xxx_sw_set_mirror_monitor_port(struct switch_dev *dev,
1270                                   const struct switch_attr *attr,
1271                                   struct switch_val *val)
1272 {
1273         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1274
1275         mutex_lock(&priv->reg_mutex);
1276         priv->monitor_port = val->value.i;
1277         priv->chip->set_mirror_regs(priv);
1278         mutex_unlock(&priv->reg_mutex);
1279
1280         return 0;
1281 }
1282
1283 int
1284 ar8xxx_sw_get_mirror_monitor_port(struct switch_dev *dev,
1285                                   const struct switch_attr *attr,
1286                                   struct switch_val *val)
1287 {
1288         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1289         val->value.i = priv->monitor_port;
1290         return 0;
1291 }
1292
1293 int
1294 ar8xxx_sw_set_mirror_source_port(struct switch_dev *dev,
1295                                  const struct switch_attr *attr,
1296                                  struct switch_val *val)
1297 {
1298         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1299
1300         mutex_lock(&priv->reg_mutex);
1301         priv->source_port = val->value.i;
1302         priv->chip->set_mirror_regs(priv);
1303         mutex_unlock(&priv->reg_mutex);
1304
1305         return 0;
1306 }
1307
1308 int
1309 ar8xxx_sw_get_mirror_source_port(struct switch_dev *dev,
1310                                  const struct switch_attr *attr,
1311                                  struct switch_val *val)
1312 {
1313         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1314         val->value.i = priv->source_port;
1315         return 0;
1316 }
1317
1318 int
1319 ar8xxx_sw_set_port_reset_mib(struct switch_dev *dev,
1320                              const struct switch_attr *attr,
1321                              struct switch_val *val)
1322 {
1323         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1324         int port;
1325         int ret;
1326
1327         if (!ar8xxx_has_mib_counters(priv))
1328                 return -EOPNOTSUPP;
1329
1330         port = val->port_vlan;
1331         if (port >= dev->ports)
1332                 return -EINVAL;
1333
1334         mutex_lock(&priv->mib_lock);
1335         ret = ar8xxx_mib_capture(priv);
1336         if (ret)
1337                 goto unlock;
1338
1339         ar8xxx_mib_fetch_port_stat(priv, port, true);
1340
1341         ret = 0;
1342
1343 unlock:
1344         mutex_unlock(&priv->mib_lock);
1345         return ret;
1346 }
1347
1348 static void
1349 ar8xxx_byte_to_str(char *buf, int len, u64 byte)
1350 {
1351         unsigned long b;
1352         const char *unit;
1353
1354         if (byte >= 0x40000000) { /* 1 GiB */
1355                 b = byte * 10 / 0x40000000;
1356                 unit = "GiB";
1357         } else if (byte >= 0x100000) { /* 1 MiB */
1358                 b = byte * 10 / 0x100000;
1359                 unit = "MiB";
1360         } else if (byte >= 0x400) { /* 1 KiB */
1361                 b = byte * 10 / 0x400;
1362                 unit = "KiB";
1363         } else {
1364                 b = byte;
1365                 unit = "Byte";
1366         }
1367         if (strcmp(unit, "Byte"))
1368                 snprintf(buf, len, "%lu.%lu %s", b / 10, b % 10, unit);
1369         else
1370                 snprintf(buf, len, "%lu %s", b, unit);
1371 }
1372
1373 int
1374 ar8xxx_sw_get_port_mib(struct switch_dev *dev,
1375                        const struct switch_attr *attr,
1376                        struct switch_val *val)
1377 {
1378         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1379         const struct ar8xxx_chip *chip = priv->chip;
1380         u64 *mib_stats, mib_data;
1381         int port;
1382         int ret;
1383         char *buf = priv->buf;
1384         char buf1[64];
1385         const char *mib_name;
1386         int i, len = 0;
1387         bool mib_stats_empty = true;
1388
1389         if (!ar8xxx_has_mib_counters(priv))
1390                 return -EOPNOTSUPP;
1391
1392         port = val->port_vlan;
1393         if (port >= dev->ports)
1394                 return -EINVAL;
1395
1396         mutex_lock(&priv->mib_lock);
1397         ret = ar8xxx_mib_capture(priv);
1398         if (ret)
1399                 goto unlock;
1400
1401         ar8xxx_mib_fetch_port_stat(priv, port, false);
1402
1403         len += snprintf(buf + len, sizeof(priv->buf) - len,
1404                         "MIB counters\n");
1405
1406         mib_stats = &priv->mib_stats[port * chip->num_mibs];
1407         for (i = 0; i < chip->num_mibs; i++) {
1408                 mib_name = chip->mib_decs[i].name;
1409                 mib_data = mib_stats[i];
1410                 len += snprintf(buf + len, sizeof(priv->buf) - len,
1411                                 "%-12s: %llu\n", mib_name, mib_data);
1412                 if ((!strcmp(mib_name, "TxByte") ||
1413                     !strcmp(mib_name, "RxGoodByte")) &&
1414                     mib_data >= 1024) {
1415                         ar8xxx_byte_to_str(buf1, sizeof(buf1), mib_data);
1416                         --len; /* discard newline at the end of buf */
1417                         len += snprintf(buf + len, sizeof(priv->buf) - len,
1418                                         " (%s)\n", buf1);
1419                 }
1420                 if (mib_stats_empty && mib_data)
1421                         mib_stats_empty = false;
1422         }
1423
1424         if (mib_stats_empty)
1425                 len = snprintf(buf, sizeof(priv->buf), "No MIB data");
1426
1427         val->value.s = buf;
1428         val->len = len;
1429
1430         ret = 0;
1431
1432 unlock:
1433         mutex_unlock(&priv->mib_lock);
1434         return ret;
1435 }
1436
1437 int
1438 ar8xxx_sw_set_arl_age_time(struct switch_dev *dev, const struct switch_attr *attr,
1439                            struct switch_val *val)
1440 {
1441         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1442         int age_time = val->value.i;
1443         u32 age_time_val;
1444
1445         if (age_time < 0)
1446                 return -EINVAL;
1447
1448         age_time_val = ar8xxx_age_time_val(age_time);
1449         if (age_time_val == 0 || age_time_val > 0xffff)
1450                 return -EINVAL;
1451
1452         priv->arl_age_time = age_time;
1453         return 0;
1454 }
1455
1456 int
1457 ar8xxx_sw_get_arl_age_time(struct switch_dev *dev, const struct switch_attr *attr,
1458                    struct switch_val *val)
1459 {
1460         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1461         val->value.i = priv->arl_age_time;
1462         return 0;
1463 }
1464
1465 int
1466 ar8xxx_sw_get_arl_table(struct switch_dev *dev,
1467                         const struct switch_attr *attr,
1468                         struct switch_val *val)
1469 {
1470         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1471         struct mii_bus *bus = priv->mii_bus;
1472         const struct ar8xxx_chip *chip = priv->chip;
1473         char *buf = priv->arl_buf;
1474         int i, j, k, len = 0;
1475         struct arl_entry *a, *a1;
1476         u32 status;
1477
1478         if (!chip->get_arl_entry)
1479                 return -EOPNOTSUPP;
1480
1481         mutex_lock(&priv->reg_mutex);
1482         mutex_lock(&bus->mdio_lock);
1483
1484         chip->get_arl_entry(priv, NULL, NULL, AR8XXX_ARL_INITIALIZE);
1485
1486         for(i = 0; i < AR8XXX_NUM_ARL_RECORDS; ++i) {
1487                 a = &priv->arl_table[i];
1488                 duplicate:
1489                 chip->get_arl_entry(priv, a, &status, AR8XXX_ARL_GET_NEXT);
1490
1491                 if (!status)
1492                         break;
1493
1494                 /* avoid duplicates
1495                  * ARL table can include multiple valid entries
1496                  * per MAC, just with differing status codes
1497                  */
1498                 for (j = 0; j < i; ++j) {
1499                         a1 = &priv->arl_table[j];
1500                         if (a->port == a1->port && !memcmp(a->mac, a1->mac, sizeof(a->mac)))
1501                                 goto duplicate;
1502                 }
1503         }
1504
1505         mutex_unlock(&bus->mdio_lock);
1506
1507         len += snprintf(buf + len, sizeof(priv->arl_buf) - len,
1508                         "address resolution table\n");
1509
1510         if (i == AR8XXX_NUM_ARL_RECORDS)
1511                 len += snprintf(buf + len, sizeof(priv->arl_buf) - len,
1512                                 "Too many entries found, displaying the first %d only!\n",
1513                                 AR8XXX_NUM_ARL_RECORDS);
1514
1515         for (j = 0; j < priv->dev.ports; ++j) {
1516                 for (k = 0; k < i; ++k) {
1517                         a = &priv->arl_table[k];
1518                         if (a->port != j)
1519                                 continue;
1520                         len += snprintf(buf + len, sizeof(priv->arl_buf) - len,
1521                                         "Port %d: MAC %02x:%02x:%02x:%02x:%02x:%02x\n",
1522                                         j,
1523                                         a->mac[5], a->mac[4], a->mac[3],
1524                                         a->mac[2], a->mac[1], a->mac[0]);
1525                 }
1526         }
1527
1528         val->value.s = buf;
1529         val->len = len;
1530
1531         mutex_unlock(&priv->reg_mutex);
1532
1533         return 0;
1534 }
1535
1536 int
1537 ar8xxx_sw_set_flush_arl_table(struct switch_dev *dev,
1538                               const struct switch_attr *attr,
1539                               struct switch_val *val)
1540 {
1541         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1542         int ret;
1543
1544         mutex_lock(&priv->reg_mutex);
1545         ret = priv->chip->atu_flush(priv);
1546         mutex_unlock(&priv->reg_mutex);
1547
1548         return ret;
1549 }
1550
1551 int
1552 ar8xxx_sw_set_flush_port_arl_table(struct switch_dev *dev,
1553                                    const struct switch_attr *attr,
1554                                    struct switch_val *val)
1555 {
1556         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1557         int port, ret;
1558
1559         port = val->port_vlan;
1560         if (port >= dev->ports)
1561                 return -EINVAL;
1562
1563         mutex_lock(&priv->reg_mutex);
1564         ret = priv->chip->atu_flush_port(priv, port);
1565         mutex_unlock(&priv->reg_mutex);
1566
1567         return ret;
1568 }
1569
1570 static const struct switch_attr ar8xxx_sw_attr_globals[] = {
1571         {
1572                 .type = SWITCH_TYPE_INT,
1573                 .name = "enable_vlan",
1574                 .description = "Enable VLAN mode",
1575                 .set = ar8xxx_sw_set_vlan,
1576                 .get = ar8xxx_sw_get_vlan,
1577                 .max = 1
1578         },
1579         {
1580                 .type = SWITCH_TYPE_NOVAL,
1581                 .name = "reset_mibs",
1582                 .description = "Reset all MIB counters",
1583                 .set = ar8xxx_sw_set_reset_mibs,
1584         },
1585         {
1586                 .type = SWITCH_TYPE_INT,
1587                 .name = "enable_mirror_rx",
1588                 .description = "Enable mirroring of RX packets",
1589                 .set = ar8xxx_sw_set_mirror_rx_enable,
1590                 .get = ar8xxx_sw_get_mirror_rx_enable,
1591                 .max = 1
1592         },
1593         {
1594                 .type = SWITCH_TYPE_INT,
1595                 .name = "enable_mirror_tx",
1596                 .description = "Enable mirroring of TX packets",
1597                 .set = ar8xxx_sw_set_mirror_tx_enable,
1598                 .get = ar8xxx_sw_get_mirror_tx_enable,
1599                 .max = 1
1600         },
1601         {
1602                 .type = SWITCH_TYPE_INT,
1603                 .name = "mirror_monitor_port",
1604                 .description = "Mirror monitor port",
1605                 .set = ar8xxx_sw_set_mirror_monitor_port,
1606                 .get = ar8xxx_sw_get_mirror_monitor_port,
1607                 .max = AR8216_NUM_PORTS - 1
1608         },
1609         {
1610                 .type = SWITCH_TYPE_INT,
1611                 .name = "mirror_source_port",
1612                 .description = "Mirror source port",
1613                 .set = ar8xxx_sw_set_mirror_source_port,
1614                 .get = ar8xxx_sw_get_mirror_source_port,
1615                 .max = AR8216_NUM_PORTS - 1
1616         },
1617         {
1618                 .type = SWITCH_TYPE_STRING,
1619                 .name = "arl_table",
1620                 .description = "Get ARL table",
1621                 .set = NULL,
1622                 .get = ar8xxx_sw_get_arl_table,
1623         },
1624         {
1625                 .type = SWITCH_TYPE_NOVAL,
1626                 .name = "flush_arl_table",
1627                 .description = "Flush ARL table",
1628                 .set = ar8xxx_sw_set_flush_arl_table,
1629         },
1630 };
1631
1632 const struct switch_attr ar8xxx_sw_attr_port[] = {
1633         {
1634                 .type = SWITCH_TYPE_NOVAL,
1635                 .name = "reset_mib",
1636                 .description = "Reset single port MIB counters",
1637                 .set = ar8xxx_sw_set_port_reset_mib,
1638         },
1639         {
1640                 .type = SWITCH_TYPE_STRING,
1641                 .name = "mib",
1642                 .description = "Get port's MIB counters",
1643                 .set = NULL,
1644                 .get = ar8xxx_sw_get_port_mib,
1645         },
1646         {
1647                 .type = SWITCH_TYPE_NOVAL,
1648                 .name = "flush_arl_table",
1649                 .description = "Flush port's ARL table entries",
1650                 .set = ar8xxx_sw_set_flush_port_arl_table,
1651         },
1652 };
1653
1654 const struct switch_attr ar8xxx_sw_attr_vlan[1] = {
1655         {
1656                 .type = SWITCH_TYPE_INT,
1657                 .name = "vid",
1658                 .description = "VLAN ID (0-4094)",
1659                 .set = ar8xxx_sw_set_vid,
1660                 .get = ar8xxx_sw_get_vid,
1661                 .max = 4094,
1662         },
1663 };
1664
1665 static const struct switch_dev_ops ar8xxx_sw_ops = {
1666         .attr_global = {
1667                 .attr = ar8xxx_sw_attr_globals,
1668                 .n_attr = ARRAY_SIZE(ar8xxx_sw_attr_globals),
1669         },
1670         .attr_port = {
1671                 .attr = ar8xxx_sw_attr_port,
1672                 .n_attr = ARRAY_SIZE(ar8xxx_sw_attr_port),
1673         },
1674         .attr_vlan = {
1675                 .attr = ar8xxx_sw_attr_vlan,
1676                 .n_attr = ARRAY_SIZE(ar8xxx_sw_attr_vlan),
1677         },
1678         .get_port_pvid = ar8xxx_sw_get_pvid,
1679         .set_port_pvid = ar8xxx_sw_set_pvid,
1680         .get_vlan_ports = ar8xxx_sw_get_ports,
1681         .set_vlan_ports = ar8xxx_sw_set_ports,
1682         .apply_config = ar8xxx_sw_hw_apply,
1683         .reset_switch = ar8xxx_sw_reset_switch,
1684         .get_port_link = ar8xxx_sw_get_port_link,
1685 };
1686
1687 static const struct ar8xxx_chip ar8216_chip = {
1688         .caps = AR8XXX_CAP_MIB_COUNTERS,
1689
1690         .reg_port_stats_start = 0x19000,
1691         .reg_port_stats_length = 0xa0,
1692         .reg_arl_ctrl = AR8216_REG_ATU_CTRL,
1693
1694         .name = "Atheros AR8216",
1695         .ports = AR8216_NUM_PORTS,
1696         .vlans = AR8216_NUM_VLANS,
1697         .swops = &ar8xxx_sw_ops,
1698
1699         .hw_init = ar8216_hw_init,
1700         .init_globals = ar8216_init_globals,
1701         .init_port = ar8216_init_port,
1702         .setup_port = ar8216_setup_port,
1703         .read_port_status = ar8216_read_port_status,
1704         .atu_flush = ar8216_atu_flush,
1705         .atu_flush_port = ar8216_atu_flush_port,
1706         .vtu_flush = ar8216_vtu_flush,
1707         .vtu_load_vlan = ar8216_vtu_load_vlan,
1708         .set_mirror_regs = ar8216_set_mirror_regs,
1709         .get_arl_entry = ar8216_get_arl_entry,
1710         .sw_hw_apply = ar8xxx_sw_hw_apply,
1711
1712         .num_mibs = ARRAY_SIZE(ar8216_mibs),
1713         .mib_decs = ar8216_mibs,
1714         .mib_func = AR8216_REG_MIB_FUNC
1715 };
1716
1717 static const struct ar8xxx_chip ar8236_chip = {
1718         .caps = AR8XXX_CAP_MIB_COUNTERS,
1719
1720         .reg_port_stats_start = 0x20000,
1721         .reg_port_stats_length = 0x100,
1722         .reg_arl_ctrl = AR8216_REG_ATU_CTRL,
1723
1724         .name = "Atheros AR8236",
1725         .ports = AR8216_NUM_PORTS,
1726         .vlans = AR8216_NUM_VLANS,
1727         .swops = &ar8xxx_sw_ops,
1728
1729         .hw_init = ar8216_hw_init,
1730         .init_globals = ar8236_init_globals,
1731         .init_port = ar8216_init_port,
1732         .setup_port = ar8236_setup_port,
1733         .read_port_status = ar8216_read_port_status,
1734         .atu_flush = ar8216_atu_flush,
1735         .atu_flush_port = ar8216_atu_flush_port,
1736         .vtu_flush = ar8216_vtu_flush,
1737         .vtu_load_vlan = ar8216_vtu_load_vlan,
1738         .set_mirror_regs = ar8216_set_mirror_regs,
1739         .get_arl_entry = ar8216_get_arl_entry,
1740         .sw_hw_apply = ar8xxx_sw_hw_apply,
1741
1742         .num_mibs = ARRAY_SIZE(ar8236_mibs),
1743         .mib_decs = ar8236_mibs,
1744         .mib_func = AR8216_REG_MIB_FUNC
1745 };
1746
1747 static const struct ar8xxx_chip ar8316_chip = {
1748         .caps = AR8XXX_CAP_GIGE | AR8XXX_CAP_MIB_COUNTERS,
1749
1750         .reg_port_stats_start = 0x20000,
1751         .reg_port_stats_length = 0x100,
1752         .reg_arl_ctrl = AR8216_REG_ATU_CTRL,
1753
1754         .name = "Atheros AR8316",
1755         .ports = AR8216_NUM_PORTS,
1756         .vlans = AR8X16_MAX_VLANS,
1757         .swops = &ar8xxx_sw_ops,
1758
1759         .hw_init = ar8316_hw_init,
1760         .init_globals = ar8316_init_globals,
1761         .init_port = ar8216_init_port,
1762         .setup_port = ar8216_setup_port,
1763         .read_port_status = ar8216_read_port_status,
1764         .atu_flush = ar8216_atu_flush,
1765         .atu_flush_port = ar8216_atu_flush_port,
1766         .vtu_flush = ar8216_vtu_flush,
1767         .vtu_load_vlan = ar8216_vtu_load_vlan,
1768         .set_mirror_regs = ar8216_set_mirror_regs,
1769         .get_arl_entry = ar8216_get_arl_entry,
1770         .sw_hw_apply = ar8xxx_sw_hw_apply,
1771
1772         .num_mibs = ARRAY_SIZE(ar8236_mibs),
1773         .mib_decs = ar8236_mibs,
1774         .mib_func = AR8216_REG_MIB_FUNC
1775 };
1776
1777 static int
1778 ar8xxx_id_chip(struct ar8xxx_priv *priv)
1779 {
1780         u32 val;
1781         u16 id;
1782         int i;
1783
1784         val = ar8xxx_read(priv, AR8216_REG_CTRL);
1785         if (val == ~0)
1786                 return -ENODEV;
1787
1788         id = val & (AR8216_CTRL_REVISION | AR8216_CTRL_VERSION);
1789         for (i = 0; i < AR8X16_PROBE_RETRIES; i++) {
1790                 u16 t;
1791
1792                 val = ar8xxx_read(priv, AR8216_REG_CTRL);
1793                 if (val == ~0)
1794                         return -ENODEV;
1795
1796                 t = val & (AR8216_CTRL_REVISION | AR8216_CTRL_VERSION);
1797                 if (t != id)
1798                         return -ENODEV;
1799         }
1800
1801         priv->chip_ver = (id & AR8216_CTRL_VERSION) >> AR8216_CTRL_VERSION_S;
1802         priv->chip_rev = (id & AR8216_CTRL_REVISION);
1803
1804         switch (priv->chip_ver) {
1805         case AR8XXX_VER_AR8216:
1806                 priv->chip = &ar8216_chip;
1807                 break;
1808         case AR8XXX_VER_AR8236:
1809                 priv->chip = &ar8236_chip;
1810                 break;
1811         case AR8XXX_VER_AR8316:
1812                 priv->chip = &ar8316_chip;
1813                 break;
1814         case AR8XXX_VER_AR8327:
1815                 priv->chip = &ar8327_chip;
1816                 break;
1817         case AR8XXX_VER_AR8337:
1818                 priv->chip = &ar8337_chip;
1819                 break;
1820         default:
1821                 pr_err("ar8216: Unknown Atheros device [ver=%d, rev=%d]\n",
1822                        priv->chip_ver, priv->chip_rev);
1823
1824                 return -ENODEV;
1825         }
1826
1827         return 0;
1828 }
1829
1830 static void
1831 ar8xxx_mib_work_func(struct work_struct *work)
1832 {
1833         struct ar8xxx_priv *priv;
1834         int err;
1835
1836         priv = container_of(work, struct ar8xxx_priv, mib_work.work);
1837
1838         mutex_lock(&priv->mib_lock);
1839
1840         err = ar8xxx_mib_capture(priv);
1841         if (err)
1842                 goto next_port;
1843
1844         ar8xxx_mib_fetch_port_stat(priv, priv->mib_next_port, false);
1845
1846 next_port:
1847         priv->mib_next_port++;
1848         if (priv->mib_next_port >= priv->dev.ports)
1849                 priv->mib_next_port = 0;
1850
1851         mutex_unlock(&priv->mib_lock);
1852         schedule_delayed_work(&priv->mib_work,
1853                               msecs_to_jiffies(AR8XXX_MIB_WORK_DELAY));
1854 }
1855
1856 static int
1857 ar8xxx_mib_init(struct ar8xxx_priv *priv)
1858 {
1859         unsigned int len;
1860
1861         if (!ar8xxx_has_mib_counters(priv))
1862                 return 0;
1863
1864         BUG_ON(!priv->chip->mib_decs || !priv->chip->num_mibs);
1865
1866         len = priv->dev.ports * priv->chip->num_mibs *
1867               sizeof(*priv->mib_stats);
1868         priv->mib_stats = kzalloc(len, GFP_KERNEL);
1869
1870         if (!priv->mib_stats)
1871                 return -ENOMEM;
1872
1873         return 0;
1874 }
1875
1876 static void
1877 ar8xxx_mib_start(struct ar8xxx_priv *priv)
1878 {
1879         if (!ar8xxx_has_mib_counters(priv))
1880                 return;
1881
1882         schedule_delayed_work(&priv->mib_work,
1883                               msecs_to_jiffies(AR8XXX_MIB_WORK_DELAY));
1884 }
1885
1886 static void
1887 ar8xxx_mib_stop(struct ar8xxx_priv *priv)
1888 {
1889         if (!ar8xxx_has_mib_counters(priv))
1890                 return;
1891
1892         cancel_delayed_work(&priv->mib_work);
1893 }
1894
1895 static struct ar8xxx_priv *
1896 ar8xxx_create(void)
1897 {
1898         struct ar8xxx_priv *priv;
1899
1900         priv = kzalloc(sizeof(struct ar8xxx_priv), GFP_KERNEL);
1901         if (priv == NULL)
1902                 return NULL;
1903
1904         mutex_init(&priv->reg_mutex);
1905         mutex_init(&priv->mib_lock);
1906         INIT_DELAYED_WORK(&priv->mib_work, ar8xxx_mib_work_func);
1907
1908         return priv;
1909 }
1910
1911 static void
1912 ar8xxx_free(struct ar8xxx_priv *priv)
1913 {
1914         if (priv->chip && priv->chip->cleanup)
1915                 priv->chip->cleanup(priv);
1916
1917         kfree(priv->chip_data);
1918         kfree(priv->mib_stats);
1919         kfree(priv);
1920 }
1921
1922 static int
1923 ar8xxx_probe_switch(struct ar8xxx_priv *priv)
1924 {
1925         const struct ar8xxx_chip *chip;
1926         struct switch_dev *swdev;
1927         int ret;
1928
1929         ret = ar8xxx_id_chip(priv);
1930         if (ret)
1931                 return ret;
1932
1933         chip = priv->chip;
1934
1935         swdev = &priv->dev;
1936         swdev->cpu_port = AR8216_PORT_CPU;
1937         swdev->name = chip->name;
1938         swdev->vlans = chip->vlans;
1939         swdev->ports = chip->ports;
1940         swdev->ops = chip->swops;
1941
1942         ret = ar8xxx_mib_init(priv);
1943         if (ret)
1944                 return ret;
1945
1946         return 0;
1947 }
1948
1949 static int
1950 ar8xxx_start(struct ar8xxx_priv *priv)
1951 {
1952         int ret;
1953
1954         priv->init = true;
1955
1956         ret = priv->chip->hw_init(priv);
1957         if (ret)
1958                 return ret;
1959
1960         ret = ar8xxx_sw_reset_switch(&priv->dev);
1961         if (ret)
1962                 return ret;
1963
1964         priv->init = false;
1965
1966         ar8xxx_mib_start(priv);
1967
1968         return 0;
1969 }
1970
1971 static int
1972 ar8xxx_phy_config_init(struct phy_device *phydev)
1973 {
1974         struct ar8xxx_priv *priv = phydev->priv;
1975         struct net_device *dev = phydev->attached_dev;
1976         int ret;
1977
1978         if (WARN_ON(!priv))
1979                 return -ENODEV;
1980
1981         if (priv->chip->config_at_probe)
1982                 return ar8xxx_phy_check_aneg(phydev);
1983
1984         priv->phy = phydev;
1985
1986         if (phydev->addr != 0) {
1987                 if (chip_is_ar8316(priv)) {
1988                         /* switch device has been initialized, reinit */
1989                         priv->dev.ports = (AR8216_NUM_PORTS - 1);
1990                         priv->initialized = false;
1991                         priv->port4_phy = true;
1992                         ar8316_hw_init(priv);
1993                         return 0;
1994                 }
1995
1996                 return 0;
1997         }
1998
1999         ret = ar8xxx_start(priv);
2000         if (ret)
2001                 return ret;
2002
2003         /* VID fixup only needed on ar8216 */
2004         if (chip_is_ar8216(priv)) {
2005                 dev->phy_ptr = priv;
2006                 dev->priv_flags |= IFF_NO_IP_ALIGN;
2007                 dev->eth_mangle_rx = ar8216_mangle_rx;
2008                 dev->eth_mangle_tx = ar8216_mangle_tx;
2009         }
2010
2011         return 0;
2012 }
2013
2014 static bool
2015 ar8xxx_check_link_states(struct ar8xxx_priv *priv)
2016 {
2017         bool link_new, changed = false;
2018         u32 status;
2019         int i;
2020
2021         mutex_lock(&priv->reg_mutex);
2022
2023         for (i = 0; i < priv->dev.ports; i++) {
2024                 status = priv->chip->read_port_status(priv, i);
2025                 link_new = !!(status & AR8216_PORT_STATUS_LINK_UP);
2026                 if (link_new == priv->link_up[i])
2027                         continue;
2028
2029                 priv->link_up[i] = link_new;
2030                 changed = true;
2031                 /* flush ARL entries for this port if it went down*/
2032                 if (!link_new)
2033                         priv->chip->atu_flush_port(priv, i);
2034                 dev_info(&priv->phy->dev, "Port %d is %s\n",
2035                          i, link_new ? "up" : "down");
2036         }
2037
2038         mutex_unlock(&priv->reg_mutex);
2039
2040         return changed;
2041 }
2042
2043 static int
2044 ar8xxx_phy_read_status(struct phy_device *phydev)
2045 {
2046         struct ar8xxx_priv *priv = phydev->priv;
2047         struct switch_port_link link;
2048
2049         /* check for switch port link changes */
2050         if (phydev->state == PHY_CHANGELINK)
2051                 ar8xxx_check_link_states(priv);
2052
2053         if (phydev->addr != 0)
2054                 return genphy_read_status(phydev);
2055
2056         ar8216_read_port_link(priv, phydev->addr, &link);
2057         phydev->link = !!link.link;
2058         if (!phydev->link)
2059                 return 0;
2060
2061         switch (link.speed) {
2062         case SWITCH_PORT_SPEED_10:
2063                 phydev->speed = SPEED_10;
2064                 break;
2065         case SWITCH_PORT_SPEED_100:
2066                 phydev->speed = SPEED_100;
2067                 break;
2068         case SWITCH_PORT_SPEED_1000:
2069                 phydev->speed = SPEED_1000;
2070                 break;
2071         default:
2072                 phydev->speed = 0;
2073         }
2074         phydev->duplex = link.duplex ? DUPLEX_FULL : DUPLEX_HALF;
2075
2076         phydev->state = PHY_RUNNING;
2077         netif_carrier_on(phydev->attached_dev);
2078         phydev->adjust_link(phydev->attached_dev);
2079
2080         return 0;
2081 }
2082
2083 static int
2084 ar8xxx_phy_config_aneg(struct phy_device *phydev)
2085 {
2086         if (phydev->addr == 0)
2087                 return 0;
2088
2089         return genphy_config_aneg(phydev);
2090 }
2091
2092 static const u32 ar8xxx_phy_ids[] = {
2093         0x004dd033,
2094         0x004dd034, /* AR8327 */
2095         0x004dd036, /* AR8337 */
2096         0x004dd041,
2097         0x004dd042,
2098         0x004dd043, /* AR8236 */
2099 };
2100
2101 static bool
2102 ar8xxx_phy_match(u32 phy_id)
2103 {
2104         int i;
2105
2106         for (i = 0; i < ARRAY_SIZE(ar8xxx_phy_ids); i++)
2107                 if (phy_id == ar8xxx_phy_ids[i])
2108                         return true;
2109
2110         return false;
2111 }
2112
2113 static bool
2114 ar8xxx_is_possible(struct mii_bus *bus)
2115 {
2116         unsigned i;
2117
2118         for (i = 0; i < 4; i++) {
2119                 u32 phy_id;
2120
2121                 phy_id = mdiobus_read(bus, i, MII_PHYSID1) << 16;
2122                 phy_id |= mdiobus_read(bus, i, MII_PHYSID2);
2123                 if (!ar8xxx_phy_match(phy_id)) {
2124                         pr_debug("ar8xxx: unknown PHY at %s:%02x id:%08x\n",
2125                                  dev_name(&bus->dev), i, phy_id);
2126                         return false;
2127                 }
2128         }
2129
2130         return true;
2131 }
2132
2133 static int
2134 ar8xxx_phy_probe(struct phy_device *phydev)
2135 {
2136         struct ar8xxx_priv *priv;
2137         struct switch_dev *swdev;
2138         int ret;
2139
2140         /* skip PHYs at unused adresses */
2141         if (phydev->addr != 0 && phydev->addr != 4)
2142                 return -ENODEV;
2143
2144         if (!ar8xxx_is_possible(phydev->bus))
2145                 return -ENODEV;
2146
2147         mutex_lock(&ar8xxx_dev_list_lock);
2148         list_for_each_entry(priv, &ar8xxx_dev_list, list)
2149                 if (priv->mii_bus == phydev->bus)
2150                         goto found;
2151
2152         priv = ar8xxx_create();
2153         if (priv == NULL) {
2154                 ret = -ENOMEM;
2155                 goto unlock;
2156         }
2157
2158         priv->mii_bus = phydev->bus;
2159
2160         ret = ar8xxx_probe_switch(priv);
2161         if (ret)
2162                 goto free_priv;
2163
2164         swdev = &priv->dev;
2165         swdev->alias = dev_name(&priv->mii_bus->dev);
2166         ret = register_switch(swdev, NULL);
2167         if (ret)
2168                 goto free_priv;
2169
2170         pr_info("%s: %s rev. %u switch registered on %s\n",
2171                 swdev->devname, swdev->name, priv->chip_rev,
2172                 dev_name(&priv->mii_bus->dev));
2173
2174 found:
2175         priv->use_count++;
2176
2177         if (phydev->addr == 0) {
2178                 if (ar8xxx_has_gige(priv)) {
2179                         phydev->supported = SUPPORTED_1000baseT_Full;
2180                         phydev->advertising = ADVERTISED_1000baseT_Full;
2181                 } else {
2182                         phydev->supported = SUPPORTED_100baseT_Full;
2183                         phydev->advertising = ADVERTISED_100baseT_Full;
2184                 }
2185
2186                 if (priv->chip->config_at_probe) {
2187                         priv->phy = phydev;
2188
2189                         ret = ar8xxx_start(priv);
2190                         if (ret)
2191                                 goto err_unregister_switch;
2192                 }
2193         } else {
2194                 if (ar8xxx_has_gige(priv)) {
2195                         phydev->supported |= SUPPORTED_1000baseT_Full;
2196                         phydev->advertising |= ADVERTISED_1000baseT_Full;
2197                 }
2198         }
2199
2200         phydev->priv = priv;
2201
2202         list_add(&priv->list, &ar8xxx_dev_list);
2203
2204         mutex_unlock(&ar8xxx_dev_list_lock);
2205
2206         return 0;
2207
2208 err_unregister_switch:
2209         if (--priv->use_count)
2210                 goto unlock;
2211
2212         unregister_switch(&priv->dev);
2213
2214 free_priv:
2215         ar8xxx_free(priv);
2216 unlock:
2217         mutex_unlock(&ar8xxx_dev_list_lock);
2218         return ret;
2219 }
2220
2221 static void
2222 ar8xxx_phy_detach(struct phy_device *phydev)
2223 {
2224         struct net_device *dev = phydev->attached_dev;
2225
2226         if (!dev)
2227                 return;
2228
2229         dev->phy_ptr = NULL;
2230         dev->priv_flags &= ~IFF_NO_IP_ALIGN;
2231         dev->eth_mangle_rx = NULL;
2232         dev->eth_mangle_tx = NULL;
2233 }
2234
2235 static void
2236 ar8xxx_phy_remove(struct phy_device *phydev)
2237 {
2238         struct ar8xxx_priv *priv = phydev->priv;
2239
2240         if (WARN_ON(!priv))
2241                 return;
2242
2243         phydev->priv = NULL;
2244         if (--priv->use_count > 0)
2245                 return;
2246
2247         mutex_lock(&ar8xxx_dev_list_lock);
2248         list_del(&priv->list);
2249         mutex_unlock(&ar8xxx_dev_list_lock);
2250
2251         unregister_switch(&priv->dev);
2252         ar8xxx_mib_stop(priv);
2253         ar8xxx_free(priv);
2254 }
2255
2256 #if LINUX_VERSION_CODE >= KERNEL_VERSION(3,14,0)
2257 static int
2258 ar8xxx_phy_soft_reset(struct phy_device *phydev)
2259 {
2260         /* we don't need an extra reset */
2261         return 0;
2262 }
2263 #endif
2264
2265 static struct phy_driver ar8xxx_phy_driver = {
2266         .phy_id         = 0x004d0000,
2267         .name           = "Atheros AR8216/AR8236/AR8316",
2268         .phy_id_mask    = 0xffff0000,
2269         .features       = PHY_BASIC_FEATURES,
2270         .probe          = ar8xxx_phy_probe,
2271         .remove         = ar8xxx_phy_remove,
2272         .detach         = ar8xxx_phy_detach,
2273         .config_init    = ar8xxx_phy_config_init,
2274         .config_aneg    = ar8xxx_phy_config_aneg,
2275         .read_status    = ar8xxx_phy_read_status,
2276 #if LINUX_VERSION_CODE >= KERNEL_VERSION(3,14,0)
2277         .soft_reset     = ar8xxx_phy_soft_reset,
2278 #endif
2279         .driver         = { .owner = THIS_MODULE },
2280 };
2281
2282 int __init
2283 ar8xxx_init(void)
2284 {
2285         return phy_driver_register(&ar8xxx_phy_driver);
2286 }
2287
2288 void __exit
2289 ar8xxx_exit(void)
2290 {
2291         phy_driver_unregister(&ar8xxx_phy_driver);
2292 }
2293
2294 module_init(ar8xxx_init);
2295 module_exit(ar8xxx_exit);
2296 MODULE_LICENSE("GPL");
2297