target/linux/ar71xx/files/arch/mips/ath79/mach-rb4xx.c

   1 /*
   2  *  MikroTik RouterBOARD 4xx series support
   3  *
   4  *  Copyright (C) 2008-2012 Gabor Juhos <juhosg@openwrt.org>
   5  *  Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
   6  *
   7  *  This program is free software; you can redistribute it and/or modify it
   8  *  under the terms of the GNU General Public License version 2 as published
   9  *  by the Free Software Foundation.
  10  */
  11
  12 #include <linux/platform_device.h>
  13 #include <linux/irq.h>
  14 #if LINUX_VERSION_CODE < KERNEL_VERSION(4,4,0)
  15 #include <linux/mdio-gpio.h>
  16 #else
  17 #include <linux/platform_data/mdio-gpio.h>
  18 #endif
  19 #include <linux/mmc/host.h>
  20 #include <linux/spi/spi.h>
  21 #include <linux/spi/flash.h>
  22 #include <linux/spi/mmc_spi.h>
  23 #include <linux/mtd/mtd.h>
  24 #include <linux/mtd/partitions.h>
  25
  26 #include <asm/mach-ath79/ar71xx_regs.h>
  27 #include <asm/mach-ath79/ath79.h>
  28 #include <asm/mach-ath79/rb4xx_cpld.h>
  29
  30 #include "common.h"
  31 #include "dev-eth.h"
  32 #include "dev-gpio-buttons.h"
  33 #include "dev-leds-gpio.h"
  34 #include "dev-usb.h"
  35 #include "machtypes.h"
  36 #include "pci.h"
  37
  38 #define RB4XX_GPIO_USER_LED     4
  39 #define RB4XX_GPIO_RESET_SWITCH 7
  40
  41 #define RB4XX_GPIO_CPLD_BASE    32
  42 #define RB4XX_GPIO_CPLD_LED1    (RB4XX_GPIO_CPLD_BASE + CPLD_GPIO_nLED1)
  43 #define RB4XX_GPIO_CPLD_LED2    (RB4XX_GPIO_CPLD_BASE + CPLD_GPIO_nLED2)
  44 #define RB4XX_GPIO_CPLD_LED3    (RB4XX_GPIO_CPLD_BASE + CPLD_GPIO_nLED3)
  45 #define RB4XX_GPIO_CPLD_LED4    (RB4XX_GPIO_CPLD_BASE + CPLD_GPIO_nLED4)
  46 #define RB4XX_GPIO_CPLD_LED5    (RB4XX_GPIO_CPLD_BASE + CPLD_GPIO_nLED5)
  47
  48 #define RB4XX_KEYS_POLL_INTERVAL        20      /* msecs */
  49 #define RB4XX_KEYS_DEBOUNCE_INTERVAL    (3 * RB4XX_KEYS_POLL_INTERVAL)
  50
  51 static struct gpio_led rb4xx_leds_gpio[] __initdata = {
  52         {
  53                 .name           = "rb4xx:yellow:user",
  54                 .gpio           = RB4XX_GPIO_USER_LED,
  55                 .active_low     = 0,
  56         }, {
  57                 .name           = "rb4xx:green:led1",
  58                 .gpio           = RB4XX_GPIO_CPLD_LED1,
  59                 .active_low     = 1,
  60         }, {
  61                 .name           = "rb4xx:green:led2",
  62                 .gpio           = RB4XX_GPIO_CPLD_LED2,
  63                 .active_low     = 1,
  64         }, {
  65                 .name           = "rb4xx:green:led3",
  66                 .gpio           = RB4XX_GPIO_CPLD_LED3,
  67                 .active_low     = 1,
  68         }, {
  69                 .name           = "rb4xx:green:led4",
  70                 .gpio           = RB4XX_GPIO_CPLD_LED4,
  71                 .active_low     = 1,
  72         }, {
  73                 .name           = "rb4xx:green:led5",
  74                 .gpio           = RB4XX_GPIO_CPLD_LED5,
  75                 .active_low     = 0,
  76         },
  77 };
  78
  79 static struct gpio_keys_button rb4xx_gpio_keys[] __initdata = {
  80         {
  81                 .desc           = "reset_switch",
  82                 .type           = EV_KEY,
  83                 .code           = KEY_RESTART,
  84                 .debounce_interval = RB4XX_KEYS_DEBOUNCE_INTERVAL,
  85                 .gpio           = RB4XX_GPIO_RESET_SWITCH,
  86                 .active_low     = 1,
  87         }
  88 };
  89
  90 static struct platform_device rb4xx_nand_device = {
  91         .name   = "rb4xx-nand",
  92         .id     = -1,
  93 };
  94
  95 static struct ath79_pci_irq rb4xx_pci_irqs[] __initdata = {
  96         {
  97                 .slot   = 17,
  98                 .pin    = 1,
  99                 .irq    = ATH79_PCI_IRQ(2),
 100         }, {
 101                 .slot   = 18,
 102                 .pin    = 1,
 103                 .irq    = ATH79_PCI_IRQ(0),
 104         }, {
 105                 .slot   = 18,
 106                 .pin    = 2,
 107                 .irq    = ATH79_PCI_IRQ(1),
 108         }, {
 109                 .slot   = 19,
 110                 .pin    = 1,
 111                 .irq    = ATH79_PCI_IRQ(1),
 112         }, {
 113                 .slot   = 19,
 114                 .pin    = 2,
 115                 .irq    = ATH79_PCI_IRQ(2),
 116         }, {
 117                 .slot   = 20,
 118                 .pin    = 1,
 119                 .irq    = ATH79_PCI_IRQ(2),
 120         }, {
 121                 .slot   = 20,
 122                 .pin    = 2,
 123                 .irq    = ATH79_PCI_IRQ(0),
 124         }, {
 125                 .slot   = 21,
 126                 .pin    = 1,
 127                 .irq    = ATH79_PCI_IRQ(0),
 128         }, {
 129                 .slot   = 22,
 130                 .pin    = 1,
 131                 .irq    = ATH79_PCI_IRQ(1),
 132         }, {
 133                 .slot   = 22,
 134                 .pin    = 2,
 135                 .irq    = ATH79_PCI_IRQ(2),
 136         }, {
 137                 .slot   = 23,
 138                 .pin    = 1,
 139                 .irq    = ATH79_PCI_IRQ(2),
 140         }, {
 141                 .slot   = 23,
 142                 .pin    = 2,
 143                 .irq    = ATH79_PCI_IRQ(0),
 144         }
 145 };
 146
 147 static struct mtd_partition rb4xx_partitions[] = {
 148         {
 149                 .name           = "routerboot",
 150                 .offset         = 0,
 151                 .size           = 0x0b000,
 152                 .mask_flags     = MTD_WRITEABLE,
 153         }, {
 154                 .name           = "hard_config",
 155                 .offset         = 0x0b000,
 156                 .size           = 0x01000,
 157                 .mask_flags     = MTD_WRITEABLE,
 158         }, {
 159                 .name           = "bios",
 160                 .offset         = 0x0d000,
 161                 .size           = 0x02000,
 162                 .mask_flags     = MTD_WRITEABLE,
 163         }, {
 164                 .name           = "soft_config",
 165                 .offset         = 0x0f000,
 166                 .size           = 0x01000,
 167         }
 168 };
 169
 170 static struct flash_platform_data rb4xx_flash_data = {
 171         .type           = "pm25lv512",
 172         .parts          = rb4xx_partitions,
 173         .nr_parts       = ARRAY_SIZE(rb4xx_partitions),
 174 };
 175
 176 static struct rb4xx_cpld_platform_data rb4xx_cpld_data = {
 177         .gpio_base      = RB4XX_GPIO_CPLD_BASE,
 178 };
 179
 180 static struct mmc_spi_platform_data rb4xx_mmc_data = {
 181         .ocr_mask       = MMC_VDD_32_33 | MMC_VDD_33_34,
 182 };
 183
 184 static struct spi_board_info rb4xx_spi_info[] = {
 185         {
 186                 .bus_num        = 0,
 187                 .chip_select    = 0,
 188                 .max_speed_hz   = 25000000,
 189                 .modalias       = "m25p80",
 190                 .platform_data  = &rb4xx_flash_data,
 191         }, {
 192                 .bus_num        = 0,
 193                 .chip_select    = 1,
 194                 .max_speed_hz   = 25000000,
 195                 .modalias       = "spi-rb4xx-cpld",
 196                 .platform_data  = &rb4xx_cpld_data,
 197         }
 198 };
 199
 200 static struct spi_board_info rb4xx_microsd_info[] = {
 201         {
 202                 .bus_num        = 0,
 203                 .chip_select    = 2,
 204                 .max_speed_hz   = 25000000,
 205                 .modalias       = "mmc_spi",
 206                 .platform_data  = &rb4xx_mmc_data,
 207         }
 208 };
 209
 210
 211 static struct resource rb4xx_spi_resources[] = {
 212         {
 213                 .start  = AR71XX_SPI_BASE,
 214                 .end    = AR71XX_SPI_BASE + AR71XX_SPI_SIZE - 1,
 215                 .flags  = IORESOURCE_MEM,
 216         },
 217 };
 218
 219 static struct platform_device rb4xx_spi_device = {
 220         .name           = "rb4xx-spi",
 221         .id             = -1,
 222         .resource       = rb4xx_spi_resources,
 223         .num_resources  = ARRAY_SIZE(rb4xx_spi_resources),
 224 };
 225
 226 static void __init rb4xx_generic_setup(void)
 227 {
 228         ath79_gpio_function_enable(AR71XX_GPIO_FUNC_SPI_CS1_EN |
 229                                    AR71XX_GPIO_FUNC_SPI_CS2_EN);
 230
 231         ath79_register_leds_gpio(-1, ARRAY_SIZE(rb4xx_leds_gpio),
 232                                         rb4xx_leds_gpio);
 233
 234         ath79_register_gpio_keys_polled(-1, RB4XX_KEYS_POLL_INTERVAL,
 235                                         ARRAY_SIZE(rb4xx_gpio_keys),
 236                                         rb4xx_gpio_keys);
 237
 238         spi_register_board_info(rb4xx_spi_info, ARRAY_SIZE(rb4xx_spi_info));
 239         platform_device_register(&rb4xx_spi_device);
 240         platform_device_register(&rb4xx_nand_device);
 241 }
 242
 243 static void __init rb411_setup(void)
 244 {
 245         rb4xx_generic_setup();
 246         spi_register_board_info(rb4xx_microsd_info,
 247                                 ARRAY_SIZE(rb4xx_microsd_info));
 248
 249         ath79_register_mdio(0, 0xfffffffc);
 250
 251         ath79_init_mac(ath79_eth0_data.mac_addr, ath79_mac_base, 0);
 252         ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_MII;
 253         ath79_eth0_data.phy_mask = 0x00000003;
 254
 255         ath79_register_eth(0);
 256
 257         ath79_pci_set_irq_map(ARRAY_SIZE(rb4xx_pci_irqs), rb4xx_pci_irqs);
 258         ath79_register_pci();
 259 }
 260
 261 MIPS_MACHINE(ATH79_MACH_RB_411, "411", "MikroTik RouterBOARD 411/A/AH",
 262              rb411_setup);
 263
 264 static void __init rb411u_setup(void)
 265 {
 266         rb411_setup();
 267         ath79_register_usb();
 268 }
 269
 270 MIPS_MACHINE(ATH79_MACH_RB_411U, "411U", "MikroTik RouterBOARD 411U",
 271              rb411u_setup);
 272
 273 #define RB433_LAN_PHYMASK       BIT(0)
 274 #define RB433_WAN_PHYMASK       BIT(4)
 275 #define RB433_MDIO_PHYMASK      (RB433_LAN_PHYMASK | RB433_WAN_PHYMASK)
 276
 277 static void __init rb433_setup(void)
 278 {
 279         rb4xx_generic_setup();
 280         spi_register_board_info(rb4xx_microsd_info,
 281                                 ARRAY_SIZE(rb4xx_microsd_info));
 282
 283         ath79_register_mdio(0, ~RB433_MDIO_PHYMASK);
 284
 285         ath79_init_mac(ath79_eth0_data.mac_addr, ath79_mac_base, 1);
 286         ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_MII;
 287         ath79_eth0_data.phy_mask = RB433_LAN_PHYMASK;
 288
 289         ath79_init_mac(ath79_eth1_data.mac_addr, ath79_mac_base, 0);
 290         ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_RMII;
 291         ath79_eth1_data.phy_mask = RB433_WAN_PHYMASK;
 292
 293         ath79_register_eth(1);
 294         ath79_register_eth(0);
 295
 296         ath79_pci_set_irq_map(ARRAY_SIZE(rb4xx_pci_irqs), rb4xx_pci_irqs);
 297         ath79_register_pci();
 298 }
 299
 300 MIPS_MACHINE(ATH79_MACH_RB_433, "433", "MikroTik RouterBOARD 433/AH",
 301              rb433_setup);
 302
 303 static void __init rb433u_setup(void)
 304 {
 305         rb433_setup();
 306         ath79_register_usb();
 307 }
 308
 309 MIPS_MACHINE(ATH79_MACH_RB_433U, "433U", "MikroTik RouterBOARD 433UAH",
 310              rb433u_setup);
 311
 312 static void __init rb435g_setup(void)
 313 {
 314         rb4xx_generic_setup();
 315
 316         spi_register_board_info(rb4xx_microsd_info,
 317                                 ARRAY_SIZE(rb4xx_microsd_info));
 318
 319         ath79_register_mdio(0, ~RB433_MDIO_PHYMASK);
 320
 321         ath79_init_mac(ath79_eth0_data.mac_addr, ath79_mac_base, 1);
 322         ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
 323         ath79_eth0_data.phy_mask = RB433_LAN_PHYMASK;
 324
 325         ath79_init_mac(ath79_eth1_data.mac_addr, ath79_mac_base, 0);
 326         ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
 327         ath79_eth1_data.phy_mask = RB433_WAN_PHYMASK;
 328
 329         ath79_register_eth(1);
 330         ath79_register_eth(0);
 331
 332         ath79_pci_set_irq_map(ARRAY_SIZE(rb4xx_pci_irqs), rb4xx_pci_irqs);
 333         ath79_register_pci();
 334
 335         ath79_register_usb();
 336 }
 337
 338 MIPS_MACHINE(ATH79_MACH_RB_435G, "435G", "MikroTik RouterBOARD 435G",
 339              rb435g_setup);
 340
 341 #define RB450_LAN_PHYMASK       BIT(0)
 342 #define RB450_WAN_PHYMASK       BIT(4)
 343 #define RB450_MDIO_PHYMASK      (RB450_LAN_PHYMASK | RB450_WAN_PHYMASK)
 344
 345 static void __init rb450_generic_setup(int gige)
 346 {
 347         rb4xx_generic_setup();
 348         ath79_register_mdio(0, ~RB450_MDIO_PHYMASK);
 349
 350         ath79_init_mac(ath79_eth0_data.mac_addr, ath79_mac_base, 1);
 351         ath79_eth0_data.phy_if_mode = (gige) ?
 352                 PHY_INTERFACE_MODE_RGMII : PHY_INTERFACE_MODE_MII;
 353         ath79_eth0_data.phy_mask = RB450_LAN_PHYMASK;
 354
 355         ath79_init_mac(ath79_eth1_data.mac_addr, ath79_mac_base, 0);
 356         ath79_eth1_data.phy_if_mode = (gige) ?
 357                 PHY_INTERFACE_MODE_RGMII : PHY_INTERFACE_MODE_RMII;
 358         ath79_eth1_data.phy_mask = RB450_WAN_PHYMASK;
 359
 360         ath79_register_eth(1);
 361         ath79_register_eth(0);
 362 }
 363
 364 static void __init rb450_setup(void)
 365 {
 366         rb450_generic_setup(0);
 367 }
 368
 369 MIPS_MACHINE(ATH79_MACH_RB_450, "450", "MikroTik RouterBOARD 450",
 370              rb450_setup);
 371
 372 static void __init rb450g_setup(void)
 373 {
 374         rb450_generic_setup(1);
 375         spi_register_board_info(rb4xx_microsd_info,
 376                                 ARRAY_SIZE(rb4xx_microsd_info));
 377 }
 378
 379 MIPS_MACHINE(ATH79_MACH_RB_450G, "450G", "MikroTik RouterBOARD 450G",
 380              rb450g_setup);
 381
 382 static void __init rb493_setup(void)
 383 {
 384         rb4xx_generic_setup();
 385
 386         ath79_register_mdio(0, 0x3fffff00);
 387
 388         ath79_init_mac(ath79_eth0_data.mac_addr, ath79_mac_base, 0);
 389         ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_MII;
 390         ath79_eth0_data.speed = SPEED_100;
 391         ath79_eth0_data.duplex = DUPLEX_FULL;
 392
 393         ath79_init_mac(ath79_eth1_data.mac_addr, ath79_mac_base, 1);
 394         ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_RMII;
 395         ath79_eth1_data.phy_mask = 0x00000001;
 396
 397         ath79_register_eth(0);
 398         ath79_register_eth(1);
 399
 400         ath79_pci_set_irq_map(ARRAY_SIZE(rb4xx_pci_irqs), rb4xx_pci_irqs);
 401         ath79_register_pci();
 402 }
 403
 404 MIPS_MACHINE(ATH79_MACH_RB_493, "493", "MikroTik RouterBOARD 493/AH",
 405              rb493_setup);
 406
 407 #define RB493G_GPIO_MDIO_MDC            7
 408 #define RB493G_GPIO_MDIO_DATA           8
 409
 410 #define RB493G_MDIO_PHYMASK             BIT(0)
 411
 412 static struct mdio_gpio_platform_data rb493g_mdio_data = {
 413         .mdc            = RB493G_GPIO_MDIO_MDC,
 414         .mdio           = RB493G_GPIO_MDIO_DATA,
 415
 416         .phy_mask       = ~RB493G_MDIO_PHYMASK,
 417 };
 418
 419 static struct platform_device rb493g_mdio_device = {
 420         .name           = "mdio-gpio",
 421         .id             = -1,
 422         .dev            = {
 423                 .platform_data  = &rb493g_mdio_data,
 424         },
 425 };
 426
 427 static void __init rb493g_setup(void)
 428 {
 429         ath79_gpio_function_enable(AR71XX_GPIO_FUNC_SPI_CS1_EN |
 430                                     AR71XX_GPIO_FUNC_SPI_CS2_EN);
 431
 432         ath79_register_leds_gpio(-1, ARRAY_SIZE(rb4xx_leds_gpio),
 433                                     rb4xx_leds_gpio);
 434
 435         spi_register_board_info(rb4xx_spi_info, ARRAY_SIZE(rb4xx_spi_info));
 436         spi_register_board_info(rb4xx_microsd_info,
 437                                 ARRAY_SIZE(rb4xx_microsd_info));
 438
 439         platform_device_register(&rb4xx_spi_device);
 440         platform_device_register(&rb4xx_nand_device);
 441
 442         ath79_register_mdio(0, ~RB493G_MDIO_PHYMASK);
 443
 444         ath79_init_mac(ath79_eth0_data.mac_addr, ath79_mac_base, 0);
 445         ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
 446         ath79_eth0_data.phy_mask = RB493G_MDIO_PHYMASK;
 447         ath79_eth0_data.speed = SPEED_1000;
 448         ath79_eth0_data.duplex = DUPLEX_FULL;
 449
 450         ath79_init_mac(ath79_eth1_data.mac_addr, ath79_mac_base, 1);
 451         ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
 452         ath79_eth1_data.mii_bus_dev = &rb493g_mdio_device.dev;
 453         ath79_eth1_data.phy_mask = RB493G_MDIO_PHYMASK;
 454         ath79_eth1_data.speed = SPEED_1000;
 455         ath79_eth1_data.duplex = DUPLEX_FULL;
 456
 457         platform_device_register(&rb493g_mdio_device);
 458
 459         ath79_register_eth(1);
 460         ath79_register_eth(0);
 461
 462         ath79_register_usb();
 463
 464         ath79_pci_set_irq_map(ARRAY_SIZE(rb4xx_pci_irqs), rb4xx_pci_irqs);
 465         ath79_register_pci();
 466 }
 467
 468 MIPS_MACHINE(ATH79_MACH_RB_493G, "493G", "MikroTik RouterBOARD 493G",
 469              rb493g_setup);