target/linux/ar71xx/files/arch/mips/ath79/mach-rb4xx.c

   1 /*
   2  *  MikroTik RouterBOARD 4xx series support
   3  *
   4  *  Copyright (C) 2008-2012 Gabor Juhos <juhosg@openwrt.org>
   5  *  Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
   6  *
   7  *  This program is free software; you can redistribute it and/or modify it
   8  *  under the terms of the GNU General Public License version 2 as published
   9  *  by the Free Software Foundation.
  10  */
  11
  12 #include <linux/platform_device.h>
  13 #include <linux/irq.h>
  14 #include <linux/version.h>
  15 #if LINUX_VERSION_CODE < KERNEL_VERSION(4,4,0)
  16 #include <linux/mdio-gpio.h>
  17 #else
  18 #include <linux/platform_data/mdio-gpio.h>
  19 #endif
  20 #include <linux/mmc/host.h>
  21 #include <linux/spi/spi.h>
  22 #include <linux/spi/flash.h>
  23 #include <linux/spi/mmc_spi.h>
  24 #include <linux/mtd/mtd.h>
  25 #include <linux/mtd/partitions.h>
  26
  27 #include <asm/mach-ath79/ar71xx_regs.h>
  28 #include <asm/mach-ath79/ath79.h>
  29 #include <asm/mach-ath79/rb4xx_cpld.h>
  30
  31 #include "common.h"
  32 #include "dev-eth.h"
  33 #include "dev-gpio-buttons.h"
  34 #include "dev-leds-gpio.h"
  35 #include "dev-usb.h"
  36 #include "machtypes.h"
  37 #include "pci.h"
  38
  39 #define RB4XX_GPIO_USER_LED     4
  40 #define RB4XX_GPIO_RESET_SWITCH 7
  41
  42 #define RB4XX_GPIO_CPLD_BASE    32
  43 #define RB4XX_GPIO_CPLD_LED1    (RB4XX_GPIO_CPLD_BASE + CPLD_GPIO_nLED1)
  44 #define RB4XX_GPIO_CPLD_LED2    (RB4XX_GPIO_CPLD_BASE + CPLD_GPIO_nLED2)
  45 #define RB4XX_GPIO_CPLD_LED3    (RB4XX_GPIO_CPLD_BASE + CPLD_GPIO_nLED3)
  46 #define RB4XX_GPIO_CPLD_LED4    (RB4XX_GPIO_CPLD_BASE + CPLD_GPIO_nLED4)
  47 #define RB4XX_GPIO_CPLD_LED5    (RB4XX_GPIO_CPLD_BASE + CPLD_GPIO_nLED5)
  48
  49 #define RB4XX_KEYS_POLL_INTERVAL        20      /* msecs */
  50 #define RB4XX_KEYS_DEBOUNCE_INTERVAL    (3 * RB4XX_KEYS_POLL_INTERVAL)
  51
  52 static struct gpio_led rb4xx_leds_gpio[] __initdata = {
  53         {
  54                 .name           = "rb4xx:yellow:user",
  55                 .gpio           = RB4XX_GPIO_USER_LED,
  56                 .active_low     = 0,
  57         }, {
  58                 .name           = "rb4xx:green:led1",
  59                 .gpio           = RB4XX_GPIO_CPLD_LED1,
  60                 .active_low     = 1,
  61         }, {
  62                 .name           = "rb4xx:green:led2",
  63                 .gpio           = RB4XX_GPIO_CPLD_LED2,
  64                 .active_low     = 1,
  65         }, {
  66                 .name           = "rb4xx:green:led3",
  67                 .gpio           = RB4XX_GPIO_CPLD_LED3,
  68                 .active_low     = 1,
  69         }, {
  70                 .name           = "rb4xx:green:led4",
  71                 .gpio           = RB4XX_GPIO_CPLD_LED4,
  72                 .active_low     = 1,
  73         }, {
  74                 .name           = "rb4xx:green:led5",
  75                 .gpio           = RB4XX_GPIO_CPLD_LED5,
  76                 .active_low     = 0,
  77         },
  78 };
  79
  80 static struct gpio_keys_button rb4xx_gpio_keys[] __initdata = {
  81         {
  82                 .desc           = "reset_switch",
  83                 .type           = EV_KEY,
  84                 .code           = KEY_RESTART,
  85                 .debounce_interval = RB4XX_KEYS_DEBOUNCE_INTERVAL,
  86                 .gpio           = RB4XX_GPIO_RESET_SWITCH,
  87                 .active_low     = 1,
  88         }
  89 };
  90
  91 static struct platform_device rb4xx_nand_device = {
  92         .name   = "rb4xx-nand",
  93         .id     = -1,
  94 };
  95
  96 static struct ath79_pci_irq rb4xx_pci_irqs[] __initdata = {
  97         {
  98                 .slot   = 17,
  99                 .pin    = 1,
 100                 .irq    = ATH79_PCI_IRQ(2),
 101         }, {
 102                 .slot   = 18,
 103                 .pin    = 1,
 104                 .irq    = ATH79_PCI_IRQ(0),
 105         }, {
 106                 .slot   = 18,
 107                 .pin    = 2,
 108                 .irq    = ATH79_PCI_IRQ(1),
 109         }, {
 110                 .slot   = 19,
 111                 .pin    = 1,
 112                 .irq    = ATH79_PCI_IRQ(1),
 113         }, {
 114                 .slot   = 19,
 115                 .pin    = 2,
 116                 .irq    = ATH79_PCI_IRQ(2),
 117         }, {
 118                 .slot   = 20,
 119                 .pin    = 1,
 120                 .irq    = ATH79_PCI_IRQ(2),
 121         }, {
 122                 .slot   = 20,
 123                 .pin    = 2,
 124                 .irq    = ATH79_PCI_IRQ(0),
 125         }, {
 126                 .slot   = 21,
 127                 .pin    = 1,
 128                 .irq    = ATH79_PCI_IRQ(0),
 129         }, {
 130                 .slot   = 22,
 131                 .pin    = 1,
 132                 .irq    = ATH79_PCI_IRQ(1),
 133         }, {
 134                 .slot   = 22,
 135                 .pin    = 2,
 136                 .irq    = ATH79_PCI_IRQ(2),
 137         }, {
 138                 .slot   = 23,
 139                 .pin    = 1,
 140                 .irq    = ATH79_PCI_IRQ(2),
 141         }, {
 142                 .slot   = 23,
 143                 .pin    = 2,
 144                 .irq    = ATH79_PCI_IRQ(0),
 145         }
 146 };
 147
 148 static struct mtd_partition rb4xx_partitions[] = {
 149         {
 150                 .name           = "routerboot",
 151                 .offset         = 0,
 152                 .size           = 0x0b000,
 153                 .mask_flags     = MTD_WRITEABLE,
 154         }, {
 155                 .name           = "hard_config",
 156                 .offset         = 0x0b000,
 157                 .size           = 0x01000,
 158                 .mask_flags     = MTD_WRITEABLE,
 159         }, {
 160                 .name           = "bios",
 161                 .offset         = 0x0d000,
 162                 .size           = 0x02000,
 163                 .mask_flags     = MTD_WRITEABLE,
 164         }, {
 165                 .name           = "soft_config",
 166                 .offset         = 0x0f000,
 167                 .size           = 0x01000,
 168         }
 169 };
 170
 171 static struct flash_platform_data rb4xx_flash_data = {
 172         .type           = "pm25lv512",
 173         .parts          = rb4xx_partitions,
 174         .nr_parts       = ARRAY_SIZE(rb4xx_partitions),
 175 };
 176
 177 static struct rb4xx_cpld_platform_data rb4xx_cpld_data = {
 178         .gpio_base      = RB4XX_GPIO_CPLD_BASE,
 179 };
 180
 181 static struct mmc_spi_platform_data rb4xx_mmc_data = {
 182         .ocr_mask       = MMC_VDD_32_33 | MMC_VDD_33_34,
 183 };
 184
 185 static struct spi_board_info rb4xx_spi_info[] = {
 186         {
 187                 .bus_num        = 0,
 188                 .chip_select    = 0,
 189                 .max_speed_hz   = 25000000,
 190                 .modalias       = "m25p80",
 191                 .platform_data  = &rb4xx_flash_data,
 192         }, {
 193                 .bus_num        = 0,
 194                 .chip_select    = 1,
 195                 .max_speed_hz   = 25000000,
 196                 .modalias       = "spi-rb4xx-cpld",
 197                 .platform_data  = &rb4xx_cpld_data,
 198         }
 199 };
 200
 201 static struct spi_board_info rb4xx_microsd_info[] = {
 202         {
 203                 .bus_num        = 0,
 204                 .chip_select    = 2,
 205                 .max_speed_hz   = 25000000,
 206                 .modalias       = "mmc_spi",
 207                 .platform_data  = &rb4xx_mmc_data,
 208         }
 209 };
 210
 211
 212 static struct resource rb4xx_spi_resources[] = {
 213         {
 214                 .start  = AR71XX_SPI_BASE,
 215                 .end    = AR71XX_SPI_BASE + AR71XX_SPI_SIZE - 1,
 216                 .flags  = IORESOURCE_MEM,
 217         },
 218 };
 219
 220 static struct platform_device rb4xx_spi_device = {
 221         .name           = "rb4xx-spi",
 222         .id             = -1,
 223         .resource       = rb4xx_spi_resources,
 224         .num_resources  = ARRAY_SIZE(rb4xx_spi_resources),
 225 };
 226
 227 static void __init rb4xx_generic_setup(void)
 228 {
 229         ath79_gpio_function_enable(AR71XX_GPIO_FUNC_SPI_CS1_EN |
 230                                    AR71XX_GPIO_FUNC_SPI_CS2_EN);
 231
 232         ath79_register_leds_gpio(-1, ARRAY_SIZE(rb4xx_leds_gpio),
 233                                         rb4xx_leds_gpio);
 234
 235         ath79_register_gpio_keys_polled(-1, RB4XX_KEYS_POLL_INTERVAL,
 236                                         ARRAY_SIZE(rb4xx_gpio_keys),
 237                                         rb4xx_gpio_keys);
 238
 239         spi_register_board_info(rb4xx_spi_info, ARRAY_SIZE(rb4xx_spi_info));
 240         platform_device_register(&rb4xx_spi_device);
 241         platform_device_register(&rb4xx_nand_device);
 242 }
 243
 244 static void __init rb411_setup(void)
 245 {
 246         rb4xx_generic_setup();
 247         spi_register_board_info(rb4xx_microsd_info,
 248                                 ARRAY_SIZE(rb4xx_microsd_info));
 249
 250         ath79_register_mdio(0, 0xfffffffc);
 251
 252         ath79_init_mac(ath79_eth0_data.mac_addr, ath79_mac_base, 0);
 253         ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_MII;
 254         ath79_eth0_data.phy_mask = 0x00000003;
 255
 256         ath79_register_eth(0);
 257
 258         ath79_pci_set_irq_map(ARRAY_SIZE(rb4xx_pci_irqs), rb4xx_pci_irqs);
 259         ath79_register_pci();
 260 }
 261
 262 MIPS_MACHINE(ATH79_MACH_RB_411, "411", "MikroTik RouterBOARD 411/A/AH",
 263              rb411_setup);
 264
 265 static void __init rb411u_setup(void)
 266 {
 267         rb411_setup();
 268         ath79_register_usb();
 269 }
 270
 271 MIPS_MACHINE(ATH79_MACH_RB_411U, "411U", "MikroTik RouterBOARD 411U",
 272              rb411u_setup);
 273
 274 #define RB433_LAN_PHYMASK       BIT(0)
 275 #define RB433_WAN_PHYMASK       BIT(4)
 276 #define RB433_MDIO_PHYMASK      (RB433_LAN_PHYMASK | RB433_WAN_PHYMASK)
 277
 278 static void __init rb433_setup(void)
 279 {
 280         rb4xx_generic_setup();
 281         spi_register_board_info(rb4xx_microsd_info,
 282                                 ARRAY_SIZE(rb4xx_microsd_info));
 283
 284         ath79_register_mdio(0, ~RB433_MDIO_PHYMASK);
 285
 286         ath79_init_mac(ath79_eth0_data.mac_addr, ath79_mac_base, 1);
 287         ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_MII;
 288         ath79_eth0_data.phy_mask = RB433_LAN_PHYMASK;
 289
 290         ath79_init_mac(ath79_eth1_data.mac_addr, ath79_mac_base, 0);
 291         ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_RMII;
 292         ath79_eth1_data.phy_mask = RB433_WAN_PHYMASK;
 293
 294         ath79_register_eth(1);
 295         ath79_register_eth(0);
 296
 297         ath79_pci_set_irq_map(ARRAY_SIZE(rb4xx_pci_irqs), rb4xx_pci_irqs);
 298         ath79_register_pci();
 299 }
 300
 301 MIPS_MACHINE(ATH79_MACH_RB_433, "433", "MikroTik RouterBOARD 433/AH",
 302              rb433_setup);
 303
 304 static void __init rb433u_setup(void)
 305 {
 306         rb433_setup();
 307         ath79_register_usb();
 308 }
 309
 310 MIPS_MACHINE(ATH79_MACH_RB_433U, "433U", "MikroTik RouterBOARD 433UAH",
 311              rb433u_setup);
 312
 313 static void __init rb435g_setup(void)
 314 {
 315         rb4xx_generic_setup();
 316
 317         spi_register_board_info(rb4xx_microsd_info,
 318                                 ARRAY_SIZE(rb4xx_microsd_info));
 319
 320         ath79_register_mdio(0, ~RB433_MDIO_PHYMASK);
 321
 322         ath79_init_mac(ath79_eth0_data.mac_addr, ath79_mac_base, 1);
 323         ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
 324         ath79_eth0_data.phy_mask = RB433_LAN_PHYMASK;
 325
 326         ath79_init_mac(ath79_eth1_data.mac_addr, ath79_mac_base, 0);
 327         ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
 328         ath79_eth1_data.phy_mask = RB433_WAN_PHYMASK;
 329
 330         ath79_register_eth(1);
 331         ath79_register_eth(0);
 332
 333         ath79_pci_set_irq_map(ARRAY_SIZE(rb4xx_pci_irqs), rb4xx_pci_irqs);
 334         ath79_register_pci();
 335
 336         ath79_register_usb();
 337 }
 338
 339 MIPS_MACHINE(ATH79_MACH_RB_435G, "435G", "MikroTik RouterBOARD 435G",
 340              rb435g_setup);
 341
 342 #define RB450_LAN_PHYMASK       BIT(0)
 343 #define RB450_WAN_PHYMASK       BIT(4)
 344 #define RB450_MDIO_PHYMASK      (RB450_LAN_PHYMASK | RB450_WAN_PHYMASK)
 345
 346 static void __init rb450_generic_setup(int gige)
 347 {
 348         rb4xx_generic_setup();
 349         ath79_register_mdio(0, ~RB450_MDIO_PHYMASK);
 350
 351         ath79_init_mac(ath79_eth0_data.mac_addr, ath79_mac_base, 1);
 352         ath79_eth0_data.phy_if_mode = (gige) ?
 353                 PHY_INTERFACE_MODE_RGMII : PHY_INTERFACE_MODE_MII;
 354         ath79_eth0_data.phy_mask = RB450_LAN_PHYMASK;
 355
 356         ath79_init_mac(ath79_eth1_data.mac_addr, ath79_mac_base, 0);
 357         ath79_eth1_data.phy_if_mode = (gige) ?
 358                 PHY_INTERFACE_MODE_RGMII : PHY_INTERFACE_MODE_RMII;
 359         ath79_eth1_data.phy_mask = RB450_WAN_PHYMASK;
 360
 361         ath79_register_eth(1);
 362         ath79_register_eth(0);
 363 }
 364
 365 static void __init rb450_setup(void)
 366 {
 367         rb450_generic_setup(0);
 368 }
 369
 370 MIPS_MACHINE(ATH79_MACH_RB_450, "450", "MikroTik RouterBOARD 450",
 371              rb450_setup);
 372
 373 static void __init rb450g_setup(void)
 374 {
 375         rb450_generic_setup(1);
 376         spi_register_board_info(rb4xx_microsd_info,
 377                                 ARRAY_SIZE(rb4xx_microsd_info));
 378 }
 379
 380 MIPS_MACHINE(ATH79_MACH_RB_450G, "450G", "MikroTik RouterBOARD 450G",
 381              rb450g_setup);
 382
 383 static void __init rb493_setup(void)
 384 {
 385         rb4xx_generic_setup();
 386
 387         ath79_register_mdio(0, 0x3fffff00);
 388
 389         ath79_init_mac(ath79_eth0_data.mac_addr, ath79_mac_base, 0);
 390         ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_MII;
 391         ath79_eth0_data.speed = SPEED_100;
 392         ath79_eth0_data.duplex = DUPLEX_FULL;
 393
 394         ath79_init_mac(ath79_eth1_data.mac_addr, ath79_mac_base, 1);
 395         ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_RMII;
 396         ath79_eth1_data.phy_mask = 0x00000001;
 397
 398         ath79_register_eth(0);
 399         ath79_register_eth(1);
 400
 401         ath79_pci_set_irq_map(ARRAY_SIZE(rb4xx_pci_irqs), rb4xx_pci_irqs);
 402         ath79_register_pci();
 403 }
 404
 405 MIPS_MACHINE(ATH79_MACH_RB_493, "493", "MikroTik RouterBOARD 493/AH",
 406              rb493_setup);
 407
 408 #define RB493G_GPIO_MDIO_MDC            7
 409 #define RB493G_GPIO_MDIO_DATA           8
 410
 411 #define RB493G_MDIO_PHYMASK             BIT(0)
 412
 413 static struct mdio_gpio_platform_data rb493g_mdio_data = {
 414         .mdc            = RB493G_GPIO_MDIO_MDC,
 415         .mdio           = RB493G_GPIO_MDIO_DATA,
 416
 417         .phy_mask       = ~RB493G_MDIO_PHYMASK,
 418 };
 419
 420 static struct platform_device rb493g_mdio_device = {
 421         .name           = "mdio-gpio",
 422         .id             = -1,
 423         .dev            = {
 424                 .platform_data  = &rb493g_mdio_data,
 425         },
 426 };
 427
 428 static void __init rb493g_setup(void)
 429 {
 430         ath79_gpio_function_enable(AR71XX_GPIO_FUNC_SPI_CS1_EN |
 431                                     AR71XX_GPIO_FUNC_SPI_CS2_EN);
 432
 433         ath79_register_leds_gpio(-1, ARRAY_SIZE(rb4xx_leds_gpio),
 434                                     rb4xx_leds_gpio);
 435
 436         spi_register_board_info(rb4xx_spi_info, ARRAY_SIZE(rb4xx_spi_info));
 437         spi_register_board_info(rb4xx_microsd_info,
 438                                 ARRAY_SIZE(rb4xx_microsd_info));
 439
 440         platform_device_register(&rb4xx_spi_device);
 441         platform_device_register(&rb4xx_nand_device);
 442
 443         ath79_register_mdio(0, ~RB493G_MDIO_PHYMASK);
 444
 445         ath79_init_mac(ath79_eth0_data.mac_addr, ath79_mac_base, 0);
 446         ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
 447         ath79_eth0_data.phy_mask = RB493G_MDIO_PHYMASK;
 448         ath79_eth0_data.speed = SPEED_1000;
 449         ath79_eth0_data.duplex = DUPLEX_FULL;
 450
 451         ath79_init_mac(ath79_eth1_data.mac_addr, ath79_mac_base, 1);
 452         ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
 453         ath79_eth1_data.mii_bus_dev = &rb493g_mdio_device.dev;
 454         ath79_eth1_data.phy_mask = RB493G_MDIO_PHYMASK;
 455         ath79_eth1_data.speed = SPEED_1000;
 456         ath79_eth1_data.duplex = DUPLEX_FULL;
 457
 458         platform_device_register(&rb493g_mdio_device);
 459
 460         ath79_register_eth(1);
 461         ath79_register_eth(0);
 462
 463         ath79_register_usb();
 464
 465         ath79_pci_set_irq_map(ARRAY_SIZE(rb4xx_pci_irqs), rb4xx_pci_irqs);
 466         ath79_register_pci();
 467 }
 468
 469 MIPS_MACHINE(ATH79_MACH_RB_493G, "493G", "MikroTik RouterBOARD 493G",
 470              rb493g_setup);