target/linux/sunxi/patches-4.1/165-asoc-add-sunxi-codec.patch

   1 From 97dcb50623db12f13c9c9a8b68dca61901b7f030 Mon Sep 17 00:00:00 2001
   2 From: =?UTF-8?q?Emilio=20L=C3=B3pez?= <emilio@elopez.com.ar>
   3 Date: Mon, 14 Jul 2014 20:25:23 -0300
   4 Subject: [PATCH] ASoC: sunxi: add support for the on-chip codec on early
   5  Allwinner SoCs
   6
   7 The sun4i, sun5i and sun7i SoC families have a built-in codec, capable
   8 of both audio capture and playback. This memory-mapped device can be fed
   9 with audio data via the Allwinner DMA controller.
  10
  11 Signed-off-by: Hans de Goede <hdegoede@redhat.com>
  12 ---
  13  sound/soc/Kconfig             |   1 +
  14  sound/soc/Makefile            |   1 +
  15  sound/soc/sunxi/Kconfig       |  10 +
  16  sound/soc/sunxi/Makefile      |   2 +
  17  sound/soc/sunxi/sunxi-codec.c | 802 ++++++++++++++++++++++++++++++++++++++++++
  18  5 files changed, 816 insertions(+)
  19  create mode 100644 sound/soc/sunxi/Kconfig
  20  create mode 100644 sound/soc/sunxi/Makefile
  21  create mode 100644 sound/soc/sunxi/sunxi-codec.c
  22
  23 --- a/sound/soc/Kconfig
  24 +++ b/sound/soc/Kconfig
  25 @@ -53,6 +53,7 @@ source "sound/soc/samsung/Kconfig"
  26  source "sound/soc/sh/Kconfig"
  27  source "sound/soc/sirf/Kconfig"
  28  source "sound/soc/spear/Kconfig"
  29 +source "sound/soc/sunxi/Kconfig"
  30  source "sound/soc/tegra/Kconfig"
  31  source "sound/soc/txx9/Kconfig"
  32  source "sound/soc/ux500/Kconfig"
  33 --- a/sound/soc/Makefile
  34 +++ b/sound/soc/Makefile
  35 @@ -34,6 +34,7 @@ obj-$(CONFIG_SND_SOC) += samsung/
  36  obj-$(CONFIG_SND_SOC)  += sh/
  37  obj-$(CONFIG_SND_SOC)  += sirf/
  38  obj-$(CONFIG_SND_SOC)  += spear/
  39 +obj-$(CONFIG_SND_SOC)  += sunxi/
  40  obj-$(CONFIG_SND_SOC)  += tegra/
  41  obj-$(CONFIG_SND_SOC)  += txx9/
  42  obj-$(CONFIG_SND_SOC)  += ux500/
  43 --- /dev/null
  44 +++ b/sound/soc/sunxi/Kconfig
  45 @@ -0,0 +1,10 @@
  46 +menu "SoC Audio support for Allwinner SoCs"
  47 +        depends on ARCH_SUNXI
  48 +
  49 +config SND_SUNXI_SOC_CODEC
  50 +       tristate "APB on-chip sun4i/sun5i/sun7i CODEC"
  51 +       select SND_SOC_GENERIC_DMAENGINE_PCM
  52 +       select REGMAP_MMIO
  53 +       default y
  54 +
  55 +endmenu
  56 --- /dev/null
  57 +++ b/sound/soc/sunxi/Makefile
  58 @@ -0,0 +1,2 @@
  59 +obj-$(CONFIG_SND_SUNXI_SOC_CODEC) += sunxi-codec.o
  60 +
  61 --- /dev/null
  62 +++ b/sound/soc/sunxi/sunxi-codec.c
  63 @@ -0,0 +1,802 @@
  64 +/*
  65 + * Copyright 2014 Emilio López <emilio@elopez.com.ar>
  66 + * Copyright 2014 Jon Smirl <jonsmirl@gmail.com>
  67 + *
  68 + * Based on the Allwinner SDK driver, released under the GPL.
  69 + *
  70 + * This program is free software; you can redistribute it and/or modify
  71 + * it under the terms of the GNU General Public License as published by
  72 + * the Free Software Foundation; either version 2 of the License, or
  73 + * (at your option) any later version.
  74 + *
  75 + * This program is distributed in the hope that it will be useful,
  76 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
  77 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  78 + * GNU General Public License for more details.
  79 + */
  80 +
  81 +#include <linux/init.h>
  82 +#include <linux/kernel.h>
  83 +#include <linux/module.h>
  84 +#include <linux/platform_device.h>
  85 +#include <linux/delay.h>
  86 +#include <linux/slab.h>
  87 +#include <linux/of.h>
  88 +#include <linux/of_platform.h>
  89 +#include <linux/of_address.h>
  90 +#include <linux/clk.h>
  91 +#include <linux/regmap.h>
  92 +
  93 +#include <sound/core.h>
  94 +#include <sound/pcm.h>
  95 +#include <sound/pcm_params.h>
  96 +#include <sound/soc.h>
  97 +#include <sound/tlv.h>
  98 +#include <sound/initval.h>
  99 +#include <sound/dmaengine_pcm.h>
 100 +
 101 +/* Codec DAC register offsets and bit fields */
 102 +#define SUNXI_DAC_DPC                  (0x00)
 103 +#define SUNXI_DAC_DPC_EN_DA                    (31)
 104 +#define SUNXI_DAC_DPC_DVOL                     (12)
 105 +#define SUNXI_DAC_FIFOC                        (0x04)
 106 +#define SUNXI_DAC_FIFOC_DAC_FS                 (29)
 107 +#define SUNXI_DAC_FIFOC_FIR_VERSION            (28)
 108 +#define SUNXI_DAC_FIFOC_SEND_LASAT             (26)
 109 +#define SUNXI_DAC_FIFOC_TX_FIFO_MODE           (24)
 110 +#define SUNXI_DAC_FIFOC_DRQ_CLR_CNT            (21)
 111 +#define SUNXI_DAC_FIFOC_TX_TRIG_LEVEL          (8)
 112 +#define SUNXI_DAC_FIFOC_MONO_EN                        (6)
 113 +#define SUNXI_DAC_FIFOC_TX_SAMPLE_BITS         (5)
 114 +#define SUNXI_DAC_FIFOC_DAC_DRQ_EN             (4)
 115 +#define SUNXI_DAC_FIFOC_FIFO_FLUSH             (0)
 116 +#define SUNXI_DAC_FIFOS                        (0x08)
 117 +#define SUNXI_DAC_TXDATA               (0x0c)
 118 +#define SUNXI_DAC_ACTL                 (0x10)
 119 +#define SUNXI_DAC_ACTL_DACAENR                 (31)
 120 +#define SUNXI_DAC_ACTL_DACAENL                 (30)
 121 +#define SUNXI_DAC_ACTL_MIXEN                   (29)
 122 +#define SUNXI_DAC_ACTL_LDACLMIXS               (15)
 123 +#define SUNXI_DAC_ACTL_RDACRMIXS               (14)
 124 +#define SUNXI_DAC_ACTL_LDACRMIXS               (13)
 125 +#define SUNXI_DAC_ACTL_DACPAS                  (8)
 126 +#define SUNXI_DAC_ACTL_MIXPAS                  (7)
 127 +#define SUNXI_DAC_ACTL_PA_MUTE                 (6)
 128 +#define SUNXI_DAC_ACTL_PA_VOL                  (0)
 129 +#define SUNXI_DAC_TUNE                 (0x14)
 130 +#define SUNXI_DAC_DEBUG                        (0x18)
 131 +
 132 +/* Codec ADC register offsets and bit fields */
 133 +#define SUNXI_ADC_FIFOC                        (0x1c)
 134 +#define SUNXI_ADC_FIFOC_EN_AD                  (28)
 135 +#define SUNXI_ADC_FIFOC_RX_FIFO_MODE           (24)
 136 +#define SUNXI_ADC_FIFOC_RX_TRIG_LEVEL          (8)
 137 +#define SUNXI_ADC_FIFOC_MONO_EN                        (7)
 138 +#define SUNXI_ADC_FIFOC_RX_SAMPLE_BITS         (6)
 139 +#define SUNXI_ADC_FIFOC_ADC_DRQ_EN             (4)
 140 +#define SUNXI_ADC_FIFOC_FIFO_FLUSH             (0)
 141 +#define SUNXI_ADC_FIFOS                        (0x20)
 142 +#define SUNXI_ADC_RXDATA               (0x24)
 143 +#define SUNXI_ADC_ACTL                 (0x28)
 144 +#define SUNXI_ADC_ACTL_ADCREN                  (31)
 145 +#define SUNXI_ADC_ACTL_ADCLEN                  (30)
 146 +#define SUNXI_ADC_ACTL_PREG1EN                 (29)
 147 +#define SUNXI_ADC_ACTL_PREG2EN                 (28)
 148 +#define SUNXI_ADC_ACTL_VMICEN                  (27)
 149 +#define SUNXI_ADC_ACTL_VADCG                   (20)
 150 +#define SUNXI_ADC_ACTL_ADCIS                   (17)
 151 +#define SUNXI_ADC_ACTL_PA_EN                   (4)
 152 +#define SUNXI_ADC_ACTL_DDE                     (3)
 153 +#define SUNXI_ADC_DEBUG                        (0x2c)
 154 +
 155 +/* Other various ADC registers */
 156 +#define SUNXI_DAC_TXCNT                        (0x30)
 157 +#define SUNXI_ADC_RXCNT                        (0x34)
 158 +#define SUNXI_AC_SYS_VERI              (0x38)
 159 +#define SUNXI_AC_MIC_PHONE_CAL         (0x3c)
 160 +
 161 +/* Supported SoC families - used for quirks */
 162 +enum sunxi_soc_family {
 163 +       SUN4IA, /* A10 SoC - revision A */
 164 +       SUN4I,  /* A10 SoC - later revisions */
 165 +       SUN5I,  /* A10S/A13 SoCs */
 166 +       SUN7I,  /* A20 SoC */
 167 +};
 168 +
 169 +struct sunxi_priv {
 170 +       struct regmap *regmap;
 171 +       struct clk *clk_apb, *clk_module;
 172 +
 173 +       enum sunxi_soc_family revision;
 174 +
 175 +       struct snd_dmaengine_dai_dma_data playback_dma_data;
 176 +       struct snd_dmaengine_dai_dma_data capture_dma_data;
 177 +};
 178 +
 179 +static void sunxi_codec_play_start(struct sunxi_priv *priv)
 180 +{
 181 +       /* TODO: see if we need to drive PA GPIO high */
 182 +
 183 +       /* flush TX FIFO */
 184 +       regmap_update_bits(priv->regmap, SUNXI_DAC_FIFOC, 0x1 << SUNXI_DAC_FIFOC_FIFO_FLUSH, 0x1 << SUNXI_DAC_FIFOC_FIFO_FLUSH);
 185 +
 186 +       /* enable DAC DRQ */
 187 +       regmap_update_bits(priv->regmap, SUNXI_DAC_FIFOC, 0x1 << SUNXI_DAC_FIFOC_DAC_DRQ_EN, 0x1 << SUNXI_DAC_FIFOC_DAC_DRQ_EN);
 188 +}
 189 +
 190 +static void sunxi_codec_play_stop(struct sunxi_priv *priv)
 191 +{
 192 +       /* TODO: see if we need to drive PA GPIO low */
 193 +
 194 +       /* disable DAC DRQ */
 195 +       regmap_update_bits(priv->regmap, SUNXI_DAC_FIFOC, 0x1 << SUNXI_DAC_FIFOC_DAC_DRQ_EN, 0x0 << SUNXI_DAC_FIFOC_DAC_DRQ_EN);
 196 +}
 197 +
 198 +static void sunxi_codec_capture_start(struct sunxi_priv *priv)
 199 +{
 200 +       /* TODO: see if we need to drive PA GPIO high */
 201 +
 202 +       /* enable ADC DRQ */
 203 +       regmap_update_bits(priv->regmap, SUNXI_ADC_FIFOC, 0x1 << SUNXI_ADC_FIFOC_ADC_DRQ_EN, 0x1 << SUNXI_ADC_FIFOC_ADC_DRQ_EN);
 204 +}
 205 +
 206 +static void sunxi_codec_capture_stop(struct sunxi_priv *priv)
 207 +{
 208 +       /* disable ADC DRQ */
 209 +       regmap_update_bits(priv->regmap, SUNXI_ADC_FIFOC, 0x1 << SUNXI_ADC_FIFOC_ADC_DRQ_EN, 0x0 << SUNXI_ADC_FIFOC_ADC_DRQ_EN);
 210 +
 211 +       /* enable mic1 PA */
 212 +       regmap_update_bits(priv->regmap, SUNXI_ADC_ACTL, 0x1 << SUNXI_ADC_ACTL_PREG1EN, 0x0 << SUNXI_ADC_ACTL_PREG1EN);
 213 +
 214 +       /* enable VMIC */
 215 +       regmap_update_bits(priv->regmap, SUNXI_ADC_ACTL, 0x1 << SUNXI_ADC_ACTL_VMICEN, 0x0 << SUNXI_ADC_ACTL_VMICEN);
 216 +       if (priv->revision == SUN7I) {
 217 +               /* TODO: undocumented */
 218 +               regmap_update_bits(priv->regmap, SUNXI_DAC_TUNE, 0x3 << 8, 0x0 << 8);
 219 +       }
 220 +
 221 +       /* enable ADC digital */
 222 +       regmap_update_bits(priv->regmap, SUNXI_ADC_FIFOC, 0x1 << SUNXI_ADC_FIFOC_EN_AD, 0x0 << SUNXI_ADC_FIFOC_EN_AD);
 223 +
 224 +       /* set RX FIFO mode */
 225 +       regmap_update_bits(priv->regmap, SUNXI_ADC_FIFOC, 0x1 << SUNXI_ADC_FIFOC_RX_FIFO_MODE, 0x0 << SUNXI_ADC_FIFOC_RX_FIFO_MODE);
 226 +
 227 +       /* flush RX FIFO */
 228 +       regmap_update_bits(priv->regmap, SUNXI_ADC_FIFOC, 0x1 << SUNXI_ADC_FIFOC_FIFO_FLUSH, 0x0 << SUNXI_ADC_FIFOC_FIFO_FLUSH);
 229 +
 230 +       /* enable adc1 analog */
 231 +       regmap_update_bits(priv->regmap, SUNXI_ADC_ACTL, 0x3 << SUNXI_ADC_ACTL_ADCLEN, 0x0 << SUNXI_ADC_ACTL_ADCLEN);
 232 +}
 233 +
 234 +static int sunxi_codec_trigger(struct snd_pcm_substream *substream, int cmd,
 235 +                              struct snd_soc_dai *dai)
 236 +{
 237 +       struct snd_soc_pcm_runtime *rtd = substream->private_data;
 238 +       struct sunxi_priv *priv = snd_soc_card_get_drvdata(rtd->card);
 239 +
 240 +       switch (cmd) {
 241 +       case SNDRV_PCM_TRIGGER_START:
 242 +       case SNDRV_PCM_TRIGGER_RESUME:
 243 +       case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
 244 +               if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
 245 +                       sunxi_codec_capture_start(priv);
 246 +               else
 247 +                       sunxi_codec_play_start(priv);
 248 +               break;
 249 +       case SNDRV_PCM_TRIGGER_STOP:
 250 +       case SNDRV_PCM_TRIGGER_SUSPEND:
 251 +       case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
 252 +               if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
 253 +                       sunxi_codec_capture_stop(priv);
 254 +               else
 255 +                       sunxi_codec_play_stop(priv);
 256 +               break;
 257 +       default:
 258 +               return -EINVAL;
 259 +       }
 260 +
 261 +       return 0;
 262 +}
 263 +
 264 +static int sunxi_codec_prepare(struct snd_pcm_substream *substream,
 265 +                              struct snd_soc_dai *dai)
 266 +{
 267 +       struct snd_soc_pcm_runtime *rtd = substream->private_data;
 268 +       struct sunxi_priv *priv = snd_soc_card_get_drvdata(rtd->card);
 269 +
 270 +       if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
 271 +               regmap_update_bits(priv->regmap, SUNXI_DAC_FIFOC, 0x1 << SUNXI_DAC_FIFOC_FIFO_FLUSH, 0x1 << SUNXI_DAC_FIFOC_FIFO_FLUSH);
 272 +
 273 +               /* set TX FIFO send DRQ level */
 274 +               regmap_update_bits(priv->regmap, SUNXI_DAC_FIFOC, 0x3f << SUNXI_DAC_FIFOC_TX_TRIG_LEVEL, 0xf << SUNXI_DAC_FIFOC_TX_TRIG_LEVEL);
 275 +               if (substream->runtime->rate > 32000) {
 276 +                       regmap_update_bits(priv->regmap, SUNXI_DAC_FIFOC, 0x1 << SUNXI_DAC_FIFOC_FIR_VERSION, 0x0 << SUNXI_DAC_FIFOC_FIR_VERSION);
 277 +               } else {
 278 +                       regmap_update_bits(priv->regmap, SUNXI_DAC_FIFOC, 0x1 << SUNXI_DAC_FIFOC_FIR_VERSION, 0x1 << SUNXI_DAC_FIFOC_FIR_VERSION);
 279 +               }
 280 +
 281 +               /* set TX FIFO MODE - 0 works for both 16 and 24 bits */
 282 +               regmap_update_bits(priv->regmap, SUNXI_DAC_FIFOC, 0x1 << SUNXI_DAC_FIFOC_TX_FIFO_MODE, 0x0 << SUNXI_DAC_FIFOC_TX_FIFO_MODE);
 283 +
 284 +               /* send last sample when DAC FIFO under run */
 285 +               regmap_update_bits(priv->regmap, SUNXI_DAC_FIFOC, 0x1 << SUNXI_DAC_FIFOC_SEND_LASAT, 0x0 << SUNXI_DAC_FIFOC_SEND_LASAT);
 286 +       } else {
 287 +               /* enable mic1 PA */
 288 +               regmap_update_bits(priv->regmap, SUNXI_ADC_ACTL, 0x1 << SUNXI_ADC_ACTL_PREG1EN, 0x1 << SUNXI_ADC_ACTL_PREG1EN);
 289 +
 290 +               /* mic1 gain 32dB */  /* FIXME - makes no sense */
 291 +               regmap_update_bits(priv->regmap, SUNXI_ADC_ACTL, 0x3 << 25, 0x1 << 25);
 292 +
 293 +               /* enable VMIC */
 294 +               regmap_update_bits(priv->regmap, SUNXI_ADC_ACTL, 0x1 << SUNXI_ADC_ACTL_VMICEN, 0x1 << SUNXI_ADC_ACTL_VMICEN);
 295 +
 296 +               if (priv->revision == SUN7I) {
 297 +                       /* boost up record effect */
 298 +                       regmap_update_bits(priv->regmap, SUNXI_DAC_TUNE, 0x3 << 8, 0x1 << 8);
 299 +               }
 300 +
 301 +               /* enable ADC digital */
 302 +               regmap_update_bits(priv->regmap, SUNXI_ADC_FIFOC, 0x1 << SUNXI_ADC_FIFOC_EN_AD, 0x1 << SUNXI_ADC_FIFOC_EN_AD);
 303 +
 304 +               /* set RX FIFO mode */
 305 +               regmap_update_bits(priv->regmap, SUNXI_ADC_FIFOC, 0x1 << SUNXI_ADC_FIFOC_RX_FIFO_MODE, 0x1 << SUNXI_ADC_FIFOC_RX_FIFO_MODE);
 306 +
 307 +               /* flush RX FIFO */
 308 +               regmap_update_bits(priv->regmap, SUNXI_ADC_FIFOC, 0x1 << SUNXI_ADC_FIFOC_FIFO_FLUSH, 0x1 << SUNXI_ADC_FIFOC_FIFO_FLUSH);
 309 +
 310 +               /* set RX FIFO rec drq level */
 311 +               regmap_update_bits(priv->regmap, SUNXI_ADC_FIFOC, 0xf << SUNXI_ADC_FIFOC_RX_TRIG_LEVEL, 0x7 << SUNXI_ADC_FIFOC_RX_TRIG_LEVEL);
 312 +
 313 +               /* enable adc1 analog */
 314 +               regmap_update_bits(priv->regmap, SUNXI_ADC_ACTL, 0x3 << SUNXI_ADC_ACTL_ADCLEN, 0x3 << SUNXI_ADC_ACTL_ADCLEN);
 315 +       }
 316 +
 317 +       return 0;
 318 +}
 319 +
 320 +static int sunxi_codec_hw_params(struct snd_pcm_substream *substream,
 321 +                                struct snd_pcm_hw_params *params,
 322 +                                struct snd_soc_dai *dai)
 323 +{
 324 +       struct snd_soc_pcm_runtime *rtd = substream->private_data;
 325 +       struct sunxi_priv *priv = snd_soc_card_get_drvdata(rtd->card);
 326 +       int is_mono = !!(params_channels(params) == 1);
 327 +       int is_24bit = !!(hw_param_interval(params, SNDRV_PCM_HW_PARAM_SAMPLE_BITS)->min == 32);
 328 +       unsigned int rate = params_rate(params);
 329 +       unsigned int hwrate;
 330 +
 331 +       switch (rate) {
 332 +       case 176400:
 333 +       case 88200:
 334 +       case 44100:
 335 +       case 33075:
 336 +       case 22050:
 337 +       case 14700:
 338 +       case 11025:
 339 +       case 7350:
 340 +       default:
 341 +               clk_set_rate(priv->clk_module, 22579200);
 342 +               break;
 343 +       case 192000:
 344 +       case 96000:
 345 +       case 48000:
 346 +       case 32000:
 347 +       case 24000:
 348 +       case 16000:
 349 +       case 12000:
 350 +       case 8000:
 351 +               clk_set_rate(priv->clk_module, 24576000);
 352 +               break;
 353 +       }
 354 +
 355 +       switch (rate) {
 356 +       case 192000:
 357 +       case 176400:
 358 +               hwrate = 6;
 359 +               break;
 360 +       case 96000:
 361 +       case 88200:
 362 +               hwrate = 7;
 363 +               break;
 364 +       default:
 365 +       case 48000:
 366 +       case 44100:
 367 +               hwrate = 0;
 368 +               break;
 369 +       case 32000:
 370 +       case 33075:
 371 +               hwrate = 1;
 372 +               break;
 373 +       case 24000:
 374 +       case 22050:
 375 +               hwrate = 2;
 376 +               break;
 377 +       case 16000:
 378 +       case 14700:
 379 +               hwrate = 3;
 380 +               break;
 381 +       case 12000:
 382 +       case 11025:
 383 +               hwrate = 4;
 384 +               break;
 385 +       case 8000:
 386 +       case 7350:
 387 +               hwrate = 5;
 388 +               break;
 389 +       }
 390 +
 391 +       if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
 392 +               regmap_update_bits(priv->regmap, SUNXI_DAC_FIFOC, 7 << SUNXI_DAC_FIFOC_DAC_FS, hwrate << SUNXI_DAC_FIFOC_DAC_FS);
 393 +               regmap_update_bits(priv->regmap, SUNXI_DAC_FIFOC, 1 << SUNXI_DAC_FIFOC_MONO_EN, is_mono << SUNXI_DAC_FIFOC_MONO_EN);
 394 +               regmap_update_bits(priv->regmap, SUNXI_DAC_FIFOC, 1 << SUNXI_DAC_FIFOC_TX_SAMPLE_BITS, is_24bit << SUNXI_DAC_FIFOC_TX_SAMPLE_BITS);
 395 +               if (is_24bit)
 396 +                       priv->playback_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
 397 +               else
 398 +                       priv->playback_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
 399 +       } else  {
 400 +               regmap_update_bits(priv->regmap, SUNXI_ADC_FIFOC, 7 << SUNXI_DAC_FIFOC_DAC_FS, hwrate << SUNXI_DAC_FIFOC_DAC_FS);
 401 +               regmap_update_bits(priv->regmap, SUNXI_ADC_FIFOC, 1 << SUNXI_ADC_FIFOC_MONO_EN, is_mono << SUNXI_ADC_FIFOC_MONO_EN);
 402 +       }
 403 +
 404 +       return 0;
 405 +}
 406 +
 407 +static const struct snd_kcontrol_new sun7i_dac_ctls[] = {
 408 +       /*SUNXI_DAC_ACTL = 0x10,PAVOL*/
 409 +       SOC_SINGLE("Master Playback Volume", SUNXI_DAC_ACTL, 0, 0x3f, 0),
 410 +       SOC_SINGLE("Playback Switch", SUNXI_DAC_ACTL, 6, 1, 0), /* Global output switch */
 411 +       SOC_SINGLE("FmL Switch", SUNXI_DAC_ACTL, 17, 1, 0), /* FM left switch */
 412 +       SOC_SINGLE("FmR Switch", SUNXI_DAC_ACTL, 16, 1, 0), /* FM right switch */
 413 +       SOC_SINGLE("LineL Switch", SUNXI_DAC_ACTL, 19, 1, 0), /* Line left switch */
 414 +       SOC_SINGLE("LineR Switch", SUNXI_DAC_ACTL, 18, 1, 0), /* Line right switch */
 415 +       SOC_SINGLE("Ldac Left Mixer", SUNXI_DAC_ACTL, 15, 1, 0),
 416 +       SOC_SINGLE("Rdac Right Mixer", SUNXI_DAC_ACTL, 14, 1, 0),
 417 +       SOC_SINGLE("Ldac Right Mixer", SUNXI_DAC_ACTL, 13, 1, 0),
 418 +       SOC_SINGLE("Mic Input Mux", SUNXI_DAC_ACTL, 9, 15, 0), /* from bit 9 to bit 12. Microphone input mute */
 419 +       SOC_SINGLE("MIC output volume", SUNXI_DAC_ACTL, 20, 7, 0),
 420 +       /*      FM Input to output mixer Gain Control
 421 +       *       From -4.5db to 6db,1.5db/step,default is 0db
 422 +       *       -4.5db:0x0,-3.0db:0x1,-1.5db:0x2,0db:0x3
 423 +       *       1.5db:0x4,3.0db:0x5,4.5db:0x6,6db:0x7
 424 +       */
 425 +       SOC_SINGLE("Fm output Volume", SUNXI_DAC_ACTL, 23, 7, 0),
 426 +       /*      Line-in gain stage to output mixer Gain Control
 427 +       *       0:-1.5db,1:0db
 428 +       */
 429 +       SOC_SINGLE("Line output Volume", SUNXI_DAC_ACTL, 26, 1, 0),
 430 +
 431 +       SOC_SINGLE("Master Capture Mute", SUNXI_ADC_ACTL, 4, 1, 0),
 432 +       SOC_SINGLE("Right Capture Mute", SUNXI_ADC_ACTL, 31, 1, 0),
 433 +       SOC_SINGLE("Left Capture Mute", SUNXI_ADC_ACTL, 30, 1, 0),
 434 +       SOC_SINGLE("Linein Pre-AMP", SUNXI_ADC_ACTL, 13, 7, 0),
 435 +       SOC_SINGLE("LINEIN APM Volume", SUNXI_AC_MIC_PHONE_CAL, 13, 0x7, 0),
 436 +       /* ADC Input Gain Control, capture volume
 437 +       * 000:-4.5db,001:-3db,010:-1.5db,011:0db,100:1.5db,101:3db,110:4.5db,111:6db
 438 +       */
 439 +       SOC_SINGLE("Capture Volume", SUNXI_ADC_ACTL, 20, 7, 0),
 440 +       /*
 441 +       *       MIC2 pre-amplifier Gain Control
 442 +       *       00:0db,01:35db,10:38db,11:41db
 443 +       */
 444 +       SOC_SINGLE("MicL Volume", SUNXI_ADC_ACTL, 25, 3, 0), /* Microphone left volume */
 445 +       SOC_SINGLE("MicR Volume", SUNXI_ADC_ACTL, 23, 3, 0), /* Microphone right volume */
 446 +       SOC_SINGLE("Mic2 Boost", SUNXI_ADC_ACTL, 29, 1, 0),
 447 +       SOC_SINGLE("Mic1 Boost", SUNXI_ADC_ACTL, 28, 1, 0),
 448 +       SOC_SINGLE("Mic Power", SUNXI_ADC_ACTL, 27, 1, 0),
 449 +       SOC_SINGLE("ADC Input Mux", SUNXI_ADC_ACTL, 17, 7, 0), /* ADC input mute */
 450 +       SOC_SINGLE("Mic2 gain Volume", SUNXI_AC_MIC_PHONE_CAL, 26, 7, 0),
 451 +       /*
 452 +       *       MIC1 pre-amplifier Gain Control
 453 +       *       00:0db,01:35db,10:38db,11:41db
 454 +       */
 455 +       SOC_SINGLE("Mic1 gain Volume", SUNXI_AC_MIC_PHONE_CAL, 29, 3, 0),
 456 +};
 457 +
 458 +static int sunxi_codec_dai_probe(struct snd_soc_dai *dai)
 459 +{
 460 +       struct snd_soc_card *card = snd_soc_dai_get_drvdata(dai);
 461 +       struct sunxi_priv *priv = snd_soc_card_get_drvdata(card);
 462 +
 463 +       snd_soc_dai_init_dma_data(dai, &priv->playback_dma_data, &priv->capture_dma_data);
 464 +
 465 +       return 0;
 466 +}
 467 +
 468 +static void sunxi_codec_init(struct sunxi_priv *priv)
 469 +{
 470 +       regmap_update_bits(priv->regmap, SUNXI_DAC_FIFOC, 1 << SUNXI_DAC_FIFOC_FIR_VERSION, 1 << SUNXI_DAC_FIFOC_FIR_VERSION);
 471 +
 472 +       /* set digital volume to maximum */
 473 +       if (priv->revision == SUN4IA)
 474 +               regmap_update_bits(priv->regmap, SUNXI_DAC_DPC, 0x3F << SUNXI_DAC_DPC_DVOL, 0 << SUNXI_DAC_DPC_DVOL);
 475 +
 476 +       regmap_update_bits(priv->regmap, SUNXI_DAC_FIFOC, 3 << SUNXI_DAC_FIFOC_DRQ_CLR_CNT, 3 << SUNXI_DAC_FIFOC_DRQ_CLR_CNT);
 477 +
 478 +       /* set volume */ /* TODO: is A10A inverted? */
 479 +       if (priv->revision == SUN4IA)
 480 +               regmap_update_bits(priv->regmap, SUNXI_DAC_ACTL, 0x3f << SUNXI_DAC_ACTL_PA_VOL, 1 << SUNXI_DAC_ACTL_PA_VOL);
 481 +       else
 482 +               regmap_update_bits(priv->regmap, SUNXI_DAC_ACTL, 0x3f << SUNXI_DAC_ACTL_PA_VOL, 0x3b << SUNXI_DAC_ACTL_PA_VOL);
 483 +}
 484 +
 485 +static int sunxi_codec_startup(struct snd_pcm_substream *substream,
 486 +                              struct snd_soc_dai *dai)
 487 +{
 488 +       struct snd_soc_pcm_runtime *rtd = substream->private_data;
 489 +       struct sunxi_priv *priv = snd_soc_card_get_drvdata(rtd->card);
 490 +
 491 +       sunxi_codec_init(priv);
 492 +
 493 +       return clk_prepare_enable(priv->clk_module);
 494 +}
 495 +
 496 +static void sunxi_codec_shutdown(struct snd_pcm_substream *substream,
 497 +                                struct snd_soc_dai *dai)
 498 +{
 499 +       struct snd_soc_pcm_runtime *rtd = substream->private_data;
 500 +       struct sunxi_priv *priv = snd_soc_card_get_drvdata(rtd->card);
 501 +
 502 +       clk_disable_unprepare(priv->clk_module);
 503 +}
 504 +
 505 +/*** Codec DAI ***/
 506 +
 507 +static const struct snd_soc_dai_ops sunxi_codec_dai_ops = {
 508 +       .startup = sunxi_codec_startup,
 509 +       .shutdown = sunxi_codec_shutdown,
 510 +       .trigger = sunxi_codec_trigger,
 511 +       .hw_params = sunxi_codec_hw_params,
 512 +       .prepare = sunxi_codec_prepare,
 513 +};
 514 +
 515 +static struct snd_soc_dai_driver sunxi_codec_dai = {
 516 +       .name = "Codec",
 517 +       .playback = {
 518 +               .stream_name = "Codec Playback",
 519 +               .channels_min = 1,
 520 +               .channels_max = 2,
 521 +               .rate_min = 8000,
 522 +               .rate_max = 192000,
 523 +               .rates = (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_11025 |\
 524 +                        SNDRV_PCM_RATE_22050| SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 |\
 525 +                        SNDRV_PCM_RATE_48000 |SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_192000 |\
 526 +                        SNDRV_PCM_RATE_KNOT),
 527 +               .formats = (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE),
 528 +               .sig_bits = 24,
 529 +       },
 530 +       .capture = {
 531 +               .stream_name = "Codec Capture",
 532 +               .channels_min = 1,
 533 +               .channels_max = 2,
 534 +               .rate_min = 8000,
 535 +               .rate_max = 192000,
 536 +               .rates = (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_11025 |\
 537 +                        SNDRV_PCM_RATE_22050| SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 |\
 538 +                        SNDRV_PCM_RATE_48000 |SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_192000 |\
 539 +                        SNDRV_PCM_RATE_KNOT),
 540 +               .formats = (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE),
 541 +               .sig_bits = 24,
 542 +       },
 543 +       .ops = &sunxi_codec_dai_ops,
 544 +};
 545 +
 546 +/*** Codec ***/
 547 +
 548 +static const struct snd_kcontrol_new sunxi_pa =
 549 +       SOC_DAPM_SINGLE("PA Switch", SUNXI_ADC_ACTL, SUNXI_ADC_ACTL_PA_EN, 1, 0);
 550 +
 551 +static const struct snd_kcontrol_new sunxi_pa_mute =
 552 +       SOC_DAPM_SINGLE("PA Mute Switch", SUNXI_DAC_ACTL, SUNXI_DAC_ACTL_PA_MUTE, 1, 0);
 553 +
 554 +static DECLARE_TLV_DB_SCALE(sunxi_pa_volume_scale, -6300, 100, 1);
 555 +
 556 +static const struct snd_kcontrol_new sunxi_codec_widgets[] = {
 557 +       SOC_SINGLE_TLV("PA Volume", SUNXI_DAC_ACTL, SUNXI_DAC_ACTL_PA_VOL,
 558 +                      0x3F, 0, sunxi_pa_volume_scale),
 559 +};
 560 +
 561 +static const char *right_output_mixer_text[] = { "Disabled", "Left", "Right" };
 562 +static const unsigned int right_output_mixer_values[] = { 0x0, 0x1, 0x2 };
 563 +static SOC_VALUE_ENUM_SINGLE_DECL(right_output_mixer, SUNXI_DAC_ACTL,
 564 +                                 SUNXI_DAC_ACTL_LDACRMIXS, 0x3,
 565 +                                 right_output_mixer_text,
 566 +                                 right_output_mixer_values);
 567 +
 568 +static const char *left_output_mixer_text[] = { "Disabled", "Left" };
 569 +static const unsigned int left_output_mixer_values[] = { 0x0, 0x1 };
 570 +static SOC_VALUE_ENUM_SINGLE_DECL(left_output_mixer, SUNXI_DAC_ACTL,
 571 +                                 SUNXI_DAC_ACTL_LDACLMIXS, 0x1,
 572 +                                 left_output_mixer_text,
 573 +                                 left_output_mixer_values);
 574 +
 575 +static const struct snd_kcontrol_new right_mixer =
 576 +       SOC_DAPM_ENUM("Right Mixer", right_output_mixer);
 577 +
 578 +static const struct snd_kcontrol_new left_mixer =
 579 +       SOC_DAPM_ENUM("Left Mixer", left_output_mixer);
 580 +
 581 +static const struct snd_kcontrol_new sunxi_mixer =
 582 +       SOC_DAPM_SINGLE("Mixer Switch", SUNXI_DAC_ACTL, SUNXI_DAC_ACTL_MIXEN, 1, 0);
 583 +
 584 +static const char *sunxi_dac_output_text[] = { "Muted", "Mixed", "Direct" };
 585 +static const unsigned int sunxi_dac_output_values[] = { 0x0, 0x1, 0x2 };
 586 +static SOC_VALUE_ENUM_SINGLE_DECL(dac_output_mux, SUNXI_DAC_ACTL,
 587 +                                 SUNXI_DAC_ACTL_MIXPAS, 0x3,
 588 +                                 sunxi_dac_output_text,
 589 +                                 sunxi_dac_output_values);
 590 +
 591 +static const struct snd_kcontrol_new sunxi_dac_output =
 592 +       SOC_DAPM_ENUM("DAC Output", dac_output_mux);
 593 +
 594 +static const struct snd_soc_dapm_widget codec_dapm_widgets[] = {
 595 +       /* Digital parts of the DACs */
 596 +       SND_SOC_DAPM_SUPPLY("DAC", SUNXI_DAC_DPC, SUNXI_DAC_DPC_EN_DA, 0, NULL, 0),
 597 +
 598 +       /* Analog parts of the DACs */
 599 +       SND_SOC_DAPM_DAC("Left DAC", NULL, SUNXI_DAC_ACTL, SUNXI_DAC_ACTL_DACAENL, 0),
 600 +       SND_SOC_DAPM_DAC("Right DAC", NULL, SUNXI_DAC_ACTL, SUNXI_DAC_ACTL_DACAENR, 0),
 601 +
 602 +       SND_SOC_DAPM_SWITCH("PA", SUNXI_ADC_ACTL, SUNXI_ADC_ACTL_PA_EN, 0, &sunxi_pa),
 603 +       SND_SOC_DAPM_SWITCH("PA Mute", SUNXI_DAC_ACTL, SUNXI_DAC_ACTL_PA_MUTE, 0, &sunxi_pa_mute),
 604 +
 605 +       SND_SOC_DAPM_MUX("Right Mixer", SUNXI_DAC_ACTL, SUNXI_DAC_ACTL_LDACRMIXS, 0, &right_mixer),
 606 +       SND_SOC_DAPM_MUX("Left Mixer", SUNXI_DAC_ACTL, SUNXI_DAC_ACTL_LDACLMIXS, 0, &left_mixer),
 607 +       SND_SOC_DAPM_SWITCH("Mixer", SUNXI_DAC_ACTL, SUNXI_DAC_ACTL_MIXEN, 0, &sunxi_mixer),
 608 +
 609 +       SND_SOC_DAPM_MUX("DAC Output", SUNXI_DAC_ACTL, SUNXI_DAC_ACTL_MIXPAS, 0, &sunxi_dac_output),
 610 +
 611 +       SND_SOC_DAPM_OUTPUT("Mic Bias"),
 612 +       SND_SOC_DAPM_OUTPUT("HP Right"),
 613 +       SND_SOC_DAPM_OUTPUT("HP Left"),
 614 +       SND_SOC_DAPM_INPUT("MIC_IN"),
 615 +       SND_SOC_DAPM_INPUT("LINE_IN"),
 616 +};
 617 +
 618 +static const struct snd_soc_dapm_route codec_dapm_routes[] = {
 619 +       /* DAC block */
 620 +       { "Left DAC", NULL, "Codec Playback" },
 621 +       { "Right DAC", NULL, "Codec Playback" },
 622 +       { "Left DAC", NULL, "DAC" },
 623 +       { "Right DAC", NULL, "DAC" },
 624 +
 625 +       /* DAC -> PA path */
 626 +       { "DAC Output", "Direct", "Left DAC" },
 627 +       { "DAC Output", "Direct", "Right DAC" },
 628 +       { "PA", NULL, "DAC Output"},
 629 +
 630 +       /* DAC -> MIX -> PA path */
 631 +       { "Left Mixer", "Left", "Left DAC" },
 632 +       { "Right Mixer", "Right", "Right DAC" },
 633 +       { "Mixer", NULL, "Left Mixer" },
 634 +       { "Mixer", NULL, "Right Mixer" },
 635 +       { "DAC Output", "Mixed", "Mixer" },
 636 +       { "PA", NULL, "DAC Output" },
 637 +
 638 +       /* PA -> HP path */
 639 +       { "PA Mute", NULL, "PA" },
 640 +       { "HP Right", NULL, "PA Mute" },
 641 +       { "HP Left", NULL, "PA Mute" },
 642 +};
 643 +
 644 +static struct snd_soc_codec_driver sunxi_codec = {
 645 +       .controls = sunxi_codec_widgets,
 646 +       .num_controls = ARRAY_SIZE(sunxi_codec_widgets),
 647 +       .dapm_widgets = codec_dapm_widgets,
 648 +       .num_dapm_widgets = ARRAY_SIZE(codec_dapm_widgets),
 649 +       .dapm_routes = codec_dapm_routes,
 650 +       .num_dapm_routes = ARRAY_SIZE(codec_dapm_routes),
 651 +};
 652 +
 653 +/*** Board routing ***/
 654 +/* TODO: do this with DT */
 655 +
 656 +static const struct snd_soc_dapm_widget sunxi_board_dapm_widgets[] = {
 657 +       SND_SOC_DAPM_HP("Headphone Jack", NULL),
 658 +};
 659 +
 660 +static const struct snd_soc_dapm_route sunxi_board_routing[] = {
 661 +       { "Headphone Jack",     NULL,   "HP Right" },
 662 +       { "Headphone Jack",     NULL,   "HP Left" },
 663 +};
 664 +
 665 +/*** Card and DAI Link ***/
 666 +
 667 +static struct snd_soc_dai_link cdc_dai = {
 668 +       .name = "cdc",
 669 +
 670 +       .stream_name = "CDC PCM",
 671 +       .codec_dai_name = "Codec",
 672 +       .cpu_dai_name = "1c22c00.codec",
 673 +       .codec_name = "1c22c00.codec",
 674 +       .platform_name = "1c22c00.codec",
 675 +       .dai_fmt = SND_SOC_DAIFMT_I2S,
 676 +};
 677 +
 678 +static struct snd_soc_card snd_soc_sunxi_codec = {
 679 +       .name = "sunxi-codec",
 680 +       .owner = THIS_MODULE,
 681 +       .dai_link = &cdc_dai,
 682 +       .num_links = 1,
 683 +       .dapm_widgets = sunxi_board_dapm_widgets,
 684 +       .num_dapm_widgets = ARRAY_SIZE(sunxi_board_dapm_widgets),
 685 +       .dapm_routes = sunxi_board_routing,
 686 +       .num_dapm_routes = ARRAY_SIZE(sunxi_board_routing),
 687 +};
 688 +
 689 +/*** CPU DAI ***/
 690 +
 691 +static const struct snd_soc_component_driver sunxi_codec_component = {
 692 +       .name = "sunxi-codec",
 693 +};
 694 +
 695 +#define SUNXI_RATES    SNDRV_PCM_RATE_8000_192000
 696 +#define SUNXI_FORMATS  (SNDRV_PCM_FMTBIT_S16_LE | \
 697 +                       SNDRV_PCM_FMTBIT_S32_LE)
 698 +
 699 +static struct snd_soc_dai_driver dummy_cpu_dai = {
 700 +       .name = "sunxi-cpu-dai",
 701 +       .probe = sunxi_codec_dai_probe,
 702 +       .playback = {
 703 +               .stream_name    = "Playback",
 704 +               .channels_min   = 1,
 705 +               .channels_max   = 2,
 706 +               .rates          = SUNXI_RATES,
 707 +               .formats        = SUNXI_FORMATS,
 708 +               .sig_bits       = 24,
 709 +       },
 710 +       .capture = {
 711 +               .stream_name    = "Capture",
 712 +               .channels_min   = 1,
 713 +               .channels_max   = 2,
 714 +               .rates          = SUNXI_RATES,
 715 +               .formats        = SUNXI_FORMATS,
 716 +               .sig_bits       = 24,
 717 +        },
 718 +};
 719 +
 720 +static const struct regmap_config sunxi_codec_regmap_config = {
 721 +       .reg_bits = 32,
 722 +       .reg_stride = 4,
 723 +       .val_bits = 32,
 724 +       .max_register = SUNXI_AC_MIC_PHONE_CAL,
 725 +};
 726 +
 727 +static const struct of_device_id sunxi_codec_of_match[] = {
 728 +       { .compatible = "allwinner,sun4i-a10a-codec", .data = (void *)SUN4IA},
 729 +       { .compatible = "allwinner,sun4i-a10-codec", .data = (void *)SUN4I},
 730 +       { .compatible = "allwinner,sun5i-a13-codec", .data = (void *)SUN5I},
 731 +       { .compatible = "allwinner,sun7i-a20-codec", .data = (void *)SUN7I},
 732 +       {}
 733 +};
 734 +MODULE_DEVICE_TABLE(of, sunxi_codec_of_match);
 735 +
 736 +static int sunxi_codec_probe(struct platform_device *pdev)
 737 +{
 738 +       struct device_node *np = pdev->dev.of_node;
 739 +       struct snd_soc_card *card = &snd_soc_sunxi_codec;
 740 +       const struct of_device_id *of_id;
 741 +       struct device *dev = &pdev->dev;
 742 +       struct sunxi_priv *priv;
 743 +       struct resource *res;
 744 +       void __iomem *base;
 745 +       int ret;
 746 +
 747 +       if (!of_device_is_available(np))
 748 +               return -ENODEV;
 749 +
 750 +       of_id = of_match_device(sunxi_codec_of_match, dev);
 751 +       if (!of_id)
 752 +               return -EINVAL;
 753 +
 754 +       priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
 755 +       if (!priv)
 756 +               return -ENOMEM;
 757 +
 758 +       card->dev = &pdev->dev;
 759 +       platform_set_drvdata(pdev, card);
 760 +       snd_soc_card_set_drvdata(card, priv);
 761 +
 762 +       priv->revision = (enum sunxi_soc_family)of_id->data;
 763 +
 764 +       res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 765 +       base = devm_ioremap_resource(&pdev->dev, res);
 766 +       if (IS_ERR(base))
 767 +               return PTR_ERR(base);
 768 +
 769 +       priv->regmap = devm_regmap_init_mmio(&pdev->dev, base,
 770 +                                            &sunxi_codec_regmap_config);
 771 +       if (IS_ERR(priv->regmap))
 772 +               return PTR_ERR(priv->regmap);
 773 +
 774 +       /* Get the clocks from the DT */
 775 +       priv->clk_apb = devm_clk_get(dev, "apb");
 776 +       if (IS_ERR(priv->clk_apb)) {
 777 +               dev_err(dev, "failed to get apb clock\n");
 778 +               return PTR_ERR(priv->clk_apb);
 779 +       }
 780 +       priv->clk_module = devm_clk_get(dev, "codec");
 781 +       if (IS_ERR(priv->clk_module)) {
 782 +               dev_err(dev, "failed to get codec clock\n");
 783 +               return PTR_ERR(priv->clk_module);
 784 +       }
 785 +
 786 +       /* Enable the clock on a basic rate */
 787 +       ret = clk_set_rate(priv->clk_module, 24576000);
 788 +       if (ret) {
 789 +               dev_err(dev, "failed to set codec base clock rate\n");
 790 +               return ret;
 791 +       }
 792 +
 793 +       /* Enable the bus clock */
 794 +       if (clk_prepare_enable(priv->clk_apb)) {
 795 +               dev_err(dev, "failed to enable apb clock\n");
 796 +               clk_disable_unprepare(priv->clk_module);
 797 +               return -EINVAL;
 798 +       }
 799 +
 800 +       /* DMA configuration for TX FIFO */
 801 +       priv->playback_dma_data.addr = res->start + SUNXI_DAC_TXDATA;
 802 +       priv->playback_dma_data.maxburst = 4;
 803 +       priv->playback_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
 804 +
 805 +       /* DMA configuration for RX FIFO */
 806 +       priv->capture_dma_data.addr = res->start + SUNXI_ADC_RXDATA;
 807 +       priv->capture_dma_data.maxburst = 4;
 808 +       priv->capture_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
 809 +
 810 +       ret = snd_soc_register_codec(&pdev->dev, &sunxi_codec, &sunxi_codec_dai, 1);
 811 +
 812 +       ret = devm_snd_soc_register_component(&pdev->dev, &sunxi_codec_component, &dummy_cpu_dai, 1);
 813 +       if (ret)
 814 +               goto err_clk_disable;
 815 +
 816 +       ret = devm_snd_dmaengine_pcm_register(&pdev->dev, NULL, 0);
 817 +       if (ret)
 818 +               goto err_clk_disable;
 819 +
 820 +       sunxi_codec_init(priv);
 821 +
 822 +       ret = snd_soc_register_card(card);
 823 +       if (ret) {
 824 +               dev_err(&pdev->dev, "snd_soc_register_card failed (%d)\n", ret);
 825 +               goto err_fini_utils;
 826 +       }
 827 +
 828 +       ret = snd_soc_of_parse_audio_routing(card, "routing");
 829 +       if (ret)
 830 +               goto err;
 831 +
 832 +       return 0;
 833 +
 834 +err_fini_utils:
 835 +err:
 836 +err_clk_disable:
 837 +       clk_disable_unprepare(priv->clk_apb);
 838 +       return ret;
 839 +}
 840 +
 841 +static int sunxi_codec_remove(struct platform_device *pdev)
 842 +{
 843 +       struct sunxi_priv *priv = platform_get_drvdata(pdev);
 844 +
 845 +       clk_disable_unprepare(priv->clk_apb);
 846 +       clk_disable_unprepare(priv->clk_module);
 847 +
 848 +       return 0;
 849 +}
 850 +
 851 +static struct platform_driver sunxi_codec_driver = {
 852 +       .driver = {
 853 +               .name = "sunxi-codec",
 854 +               .owner = THIS_MODULE,
 855 +               .of_match_table = sunxi_codec_of_match,
 856 +       },
 857 +       .probe = sunxi_codec_probe,
 858 +       .remove = sunxi_codec_remove,
 859 +};
 860 +module_platform_driver(sunxi_codec_driver);
 861 +
 862 +MODULE_DESCRIPTION("sunxi codec ASoC driver");
 863 +MODULE_AUTHOR("Emilio López <emilio@elopez.com.ar>");
 864 +MODULE_AUTHOR("Jon Smirl <jonsmirl@gmail.com>");
 865 +MODULE_LICENSE("GPL");