kernel: update 4.1 to 4.1.5
[openwrt.git] / target / linux / sunxi / patches-4.1 / 122-mtd-nand-sunxi-add-partition-support.patch
1 From 5cb31780791d0f6b68e3712f1b35f1a28c47add0 Mon Sep 17 00:00:00 2001
2 From: Boris Brezillon <boris.brezillon@free-electrons.com>
3 Date: Tue, 21 Oct 2014 14:37:15 +0200
4 Subject: [PATCH] mtd: nand: sunxi: Add NAND partition support
5
6 Add NAND partition support to the sunxi_nand driver.
7
8 Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
9 Signed-off-by: Hans de Goede <hdegoede@redhat.com>
10 ---
11  drivers/mtd/nand/Kconfig      |  1 +
12  drivers/mtd/nand/sunxi_nand.c | 73 +++++++++++++++++++++++++++++++++++++------
13  2 files changed, 65 insertions(+), 9 deletions(-)
14
15 --- a/drivers/mtd/nand/Kconfig
16 +++ b/drivers/mtd/nand/Kconfig
17 @@ -525,6 +525,7 @@ config MTD_NAND_XWAY
18  config MTD_NAND_SUNXI
19         tristate "Support for NAND on Allwinner SoCs"
20         depends on ARCH_SUNXI
21 +       select MTD_OF_NAND_PARTS
22         help
23           Enables support for NAND Flash chips on Allwinner SoCs.
24  
25 --- a/drivers/mtd/nand/sunxi_nand.c
26 +++ b/drivers/mtd/nand/sunxi_nand.c
27 @@ -202,6 +202,23 @@ struct sunxi_nand_hw_ecc {
28  };
29  
30  /*
31 + * sunxi NAND partition structure: stores NAND partitions information
32 + *
33 + * @part: base paritition structure
34 + * @ecc: per-partition ECC info
35 + */
36 +struct sunxi_nand_part {
37 +       struct nand_part part;
38 +       struct nand_ecc_ctrl ecc;
39 +};
40 +
41 +static inline struct sunxi_nand_part *
42 +to_sunxi_nand_part(struct nand_part *part)
43 +{
44 +       return container_of(part, struct sunxi_nand_part, part);
45 +}
46 +
47 +/*
48   * NAND chip structure: stores NAND chip device related information
49   *
50   * @node:              used to store NAND chips into a list
51 @@ -521,7 +538,7 @@ static int sunxi_nfc_hw_ecc_read_page(st
52                                       int oob_required, int page)
53  {
54         struct sunxi_nfc *nfc = to_sunxi_nfc(chip->controller);
55 -       struct nand_ecc_ctrl *ecc = &chip->ecc;
56 +       struct nand_ecc_ctrl *ecc = chip->cur_ecc;
57         struct nand_ecclayout *layout = ecc->layout;
58         struct sunxi_nand_hw_ecc *data = ecc->priv;
59         unsigned int max_bitflips = 0;
60 @@ -607,7 +624,7 @@ static int sunxi_nfc_hw_ecc_write_page(s
61                                        const uint8_t *buf, int oob_required)
62  {
63         struct sunxi_nfc *nfc = to_sunxi_nfc(chip->controller);
64 -       struct nand_ecc_ctrl *ecc = &chip->ecc;
65 +       struct nand_ecc_ctrl *ecc = chip->cur_ecc;
66         struct nand_ecclayout *layout = ecc->layout;
67         struct sunxi_nand_hw_ecc *data = ecc->priv;
68         int offset;
69 @@ -681,7 +698,7 @@ static int sunxi_nfc_hw_syndrome_ecc_rea
70                                                int page)
71  {
72         struct sunxi_nfc *nfc = to_sunxi_nfc(chip->controller);
73 -       struct nand_ecc_ctrl *ecc = &chip->ecc;
74 +       struct nand_ecc_ctrl *ecc = chip->cur_ecc;
75         struct sunxi_nand_hw_ecc *data = ecc->priv;
76         unsigned int max_bitflips = 0;
77         uint8_t *oob = chip->oob_poi;
78 @@ -749,7 +766,7 @@ static int sunxi_nfc_hw_syndrome_ecc_wri
79                                                 int oob_required)
80  {
81         struct sunxi_nfc *nfc = to_sunxi_nfc(chip->controller);
82 -       struct nand_ecc_ctrl *ecc = &chip->ecc;
83 +       struct nand_ecc_ctrl *ecc = chip->cur_ecc;
84         struct sunxi_nand_hw_ecc *data = ecc->priv;
85         uint8_t *oob = chip->oob_poi;
86         int offset = 0;
87 @@ -1099,8 +1116,13 @@ static int sunxi_nand_ecc_init(struct mt
88                 ecc->strength = nand->ecc_strength_ds;
89         }
90  
91 -       if (!ecc->size || !ecc->strength)
92 -               return -EINVAL;
93 +       if (!ecc->size || !ecc->strength) {
94 +               if (ecc == &nand->ecc)
95 +                       return -EINVAL;
96 +
97 +               ecc->size = nand->ecc.size;
98 +               ecc->strength = nand->ecc.strength;
99 +       }
100  
101         ecc->mode = NAND_ECC_HW;
102  
103 @@ -1135,12 +1157,39 @@ static int sunxi_nand_ecc_init(struct mt
104         return 0;
105  }
106  
107 +static void sunxi_nand_part_release(struct nand_part *part)
108 +{
109 +       kfree(to_sunxi_nand_part(part));
110 +}
111 +
112 +struct nand_part *sunxi_ofnandpart_parse(void *priv, struct mtd_info *master,
113 +                                        struct device_node *pp)
114 +{
115 +       struct sunxi_nand_part *part;
116 +       int ret;
117 +
118 +       part = kzalloc(sizeof(*part), GFP_KERNEL);
119 +       part->part.release = sunxi_nand_part_release;
120 +
121 +       ret = sunxi_nand_ecc_init(master, &part->ecc, pp);
122 +       if (ret)
123 +               goto err;
124 +
125 +       part->part.ecc = &part->ecc;
126 +
127 +       return &part->part;
128 +
129 +err:
130 +       kfree(part);
131 +       return ERR_PTR(ret);
132 +}
133 +
134  static int sunxi_nand_chip_init(struct device *dev, struct sunxi_nfc *nfc,
135                                 struct device_node *np)
136  {
137         const struct nand_sdr_timings *timings;
138         struct sunxi_nand_chip *chip;
139 -       struct mtd_part_parser_data ppdata;
140 +       struct ofnandpart_data ppdata;
141         struct mtd_info *mtd;
142         struct nand_chip *nand;
143         int nsels;
144 @@ -1269,8 +1318,14 @@ static int sunxi_nand_chip_init(struct d
145                 return ret;
146         }
147  
148 -       ppdata.of_node = np;
149 -       ret = mtd_device_parse_register(mtd, NULL, &ppdata, NULL, 0);
150 +       ppdata.node = np;
151 +       ppdata.parse = sunxi_ofnandpart_parse;
152 +       ret = ofnandpart_parse(mtd, &ppdata);
153 +       if (!ret)
154 +               ret = mtd_device_register(mtd, NULL, 0);
155 +       else if (ret > 0)
156 +               ret = 0;
157 +
158         if (ret) {
159                 dev_err(dev, "failed to register mtd device: %d\n", ret);
160                 nand_release(mtd);