target/linux/ramips/files/arch/mips/ralink/rt288x/irq.c

   1 /*
   2  *  Ralink RT288x SoC specific interrupt handling
   3  *
   4  *  Copyright (C) 2008-2009 Gabor Juhos <juhosg@openwrt.org>
   5  *  Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
   6  *
   7  *  This program is free software; you can redistribute it and/or modify it
   8  *  under the terms of the GNU General Public License version 2 as published
   9  *  by the Free Software Foundation.
  10  */
  11
  12 #include <linux/kernel.h>
  13 #include <linux/init.h>
  14 #include <linux/interrupt.h>
  15 #include <linux/irq.h>
  16
  17 #include <asm/irq_cpu.h>
  18 #include <asm/mipsregs.h>
  19
  20 #include <asm/mach-ralink/rt288x.h>
  21 #include <asm/mach-ralink/rt288x_regs.h>
  22
  23 static void rt288x_intc_irq_dispatch(void)
  24 {
  25         u32 pending;
  26
  27         pending = rt288x_intc_rr(INTC_REG_STATUS0);
  28
  29         if (pending & RT2880_INTC_INT_TIMER0)
  30                 do_IRQ(RT2880_INTC_IRQ_TIMER0);
  31
  32         else if (pending & RT2880_INTC_INT_TIMER1)
  33                 do_IRQ(RT2880_INTC_IRQ_TIMER1);
  34
  35         else if (pending & RT2880_INTC_INT_UART0)
  36                 do_IRQ(RT2880_INTC_IRQ_UART0);
  37
  38         else if (pending & RT2880_INTC_INT_PCM)
  39                 do_IRQ(RT2880_INTC_IRQ_PCM);
  40
  41         else if (pending & RT2880_INTC_INT_UART1)
  42                 do_IRQ(RT2880_INTC_IRQ_UART1);
  43
  44         /* TODO: handle PIO interrupts as well */
  45
  46         else
  47                 spurious_interrupt();
  48 }
  49
  50 static void rt288x_intc_irq_unmask(unsigned int irq)
  51 {
  52         irq -= RT288X_INTC_IRQ_BASE;
  53         rt288x_intc_wr((1 << irq), INTC_REG_ENABLE);
  54 }
  55
  56 static void rt288x_intc_irq_mask(unsigned int irq)
  57 {
  58         irq -= RT288X_INTC_IRQ_BASE;
  59         rt288x_intc_wr((1 << irq), INTC_REG_DISABLE);
  60 }
  61
  62 struct irq_chip rt288x_intc_irq_chip = {
  63         .name           = "RT288X INTC",
  64         .unmask         = rt288x_intc_irq_unmask,
  65         .mask           = rt288x_intc_irq_mask,
  66         .mask_ack       = rt288x_intc_irq_mask,
  67 };
  68
  69 static struct irqaction rt288x_intc_irqaction = {
  70         .handler        = no_action,
  71         .name           = "cascade [RT288X INTC]",
  72 };
  73
  74 static void __init rt288x_intc_irq_init(void)
  75 {
  76         int i;
  77
  78         /* disable all interrupts */
  79         rt288x_intc_wr(~0, INTC_REG_DISABLE);
  80
  81         /* route all INTC interrupts to MIPS HW0 interrupt */
  82         rt288x_intc_wr(0, INTC_REG_TYPE);
  83
  84         for (i = RT288X_INTC_IRQ_BASE;
  85              i < RT288X_INTC_IRQ_BASE + RT288X_INTC_IRQ_COUNT; i++) {
  86                 irq_desc[i].status = IRQ_DISABLED;
  87                 set_irq_chip_and_handler(i, &rt288x_intc_irq_chip,
  88                                          handle_level_irq);
  89         }
  90
  91         setup_irq(RT288X_CPU_IRQ_INTC, &rt288x_intc_irqaction);
  92
  93         rt288x_intc_wr(RT2880_INTC_INT_GLOBAL, INTC_REG_ENABLE);
  94 }
  95
  96 asmlinkage void plat_irq_dispatch(void)
  97 {
  98         unsigned long pending;
  99
 100         pending = read_c0_status() & read_c0_cause() & ST0_IM;
 101
 102         if (pending & STATUSF_IP7)
 103                 do_IRQ(RT288X_CPU_IRQ_COUNTER);
 104
 105         else if (pending & STATUSF_IP4)
 106                 do_IRQ(RT288X_CPU_IRQ_PCI);
 107
 108         else if (pending & STATUSF_IP5)
 109                 do_IRQ(RT288X_CPU_IRQ_FE);
 110
 111         else if (pending & STATUSF_IP6)
 112                 do_IRQ(RT288X_CPU_IRQ_WNIC);
 113
 114         else if (pending & STATUSF_IP2)
 115                 rt288x_intc_irq_dispatch();
 116
 117         else
 118                 spurious_interrupt();
 119 }
 120
 121 void __init arch_init_irq(void)
 122 {
 123         mips_cpu_irq_init();
 124         rt288x_intc_irq_init();
 125 }