target/linux/mediatek/patches-4.4/0024-dt-bindings-add-MediaTek-PCIe-binding-documentation.patch

   1 From 97478bae3a11b5e87d61b88267e915f7c5ddf4e9 Mon Sep 17 00:00:00 2001
   2 From: John Crispin <blogic@openwrt.org>
   3 Date: Wed, 6 Jan 2016 21:55:10 +0100
   4 Subject: [PATCH 24/81] dt-bindings: add MediaTek PCIe binding documentation
   5
   6 Signed-off-by: John Crispin <blogic@openwrt.org>
   7 ---
   8  .../devicetree/bindings/pci/mediatek-pcie.txt      |  140 ++++++++++++++++++++
   9  arch/arm/boot/dts/mt7623.dtsi                      |   12 ++
  10  2 files changed, 152 insertions(+)
  11  create mode 100644 Documentation/devicetree/bindings/pci/mediatek-pcie.txt
  12
  13 diff --git a/Documentation/devicetree/bindings/pci/mediatek-pcie.txt b/Documentation/devicetree/bindings/pci/mediatek-pcie.txt
  14 new file mode 100644
  15 index 0000000..8fea3ed
  16 --- /dev/null
  17 +++ b/Documentation/devicetree/bindings/pci/mediatek-pcie.txt
  18 @@ -0,0 +1,140 @@
  19 +Mediatek PCIe controller
  20 +
  21 +Required properties:
  22 +- compatible: Should be one of:
  23 +       - "mediatek,mt2701-pcie"
  24 +       - "mediatek,mt7623-pcie"
  25 +- device_type: Must be "pci"
  26 +- reg: A list of physical base address and length for each set of controller
  27 +  registers. A list of register ranges to use. Must contain an
  28 +    entry for each entry in the reg-names property.
  29 +- reg-names: Must include the following entries:
  30 +  "pcie": PCIe registers
  31 +  "pcie phy0": PCIe PHY0 registers
  32 +  "pcie phy1": PCIe PHY0 registers
  33 +  "pcie phy2": PCIe PHY0 registers
  34 +- interrupts: A list of interrupt outputs of the controller. Must contain an
  35 +  entry for each entry in the interrupt-names property.
  36 +- interrupt-names: Must include the following entries:
  37 +  "pcie0": The interrupt that is asserted for port0
  38 +  "pcie1": The interrupt that is asserted for port1
  39 +  "pcie2": The interrupt that is asserted for port2
  40 +- bus-range: Range of bus numbers associated with this controller
  41 +- #address-cells: Address representation for root ports (must be 3)
  42 +- #size-cells: Size representation for root ports (must be 2)
  43 +- ranges: Describes the translation of addresses for root ports and standard
  44 +  PCI regions. The entries must be 6 cells each.
  45 +  Please refer to the standard PCI bus binding document for a more detailed
  46 +  explanation.
  47 +- #interrupt-cells: Size representation for interrupts (must be 1)
  48 +- clocks: Must contain an entry for each entry in clock-names.
  49 +  See ../clocks/clock-bindings.txt for details.
  50 +- clock-names: Must include the following entries:
  51 +  - pcie0
  52 +  - pcie1
  53 +  - pcie2
  54 +- resets: Must contain an entry for each entry in reset-names.
  55 +  See ../reset/reset.txt for details.
  56 +- reset-names: Must include the following entries:
  57 +  - pcie0
  58 +  - pcie1
  59 +  - pcie2
  60 +- mediatek,hifsys: Must contain a phandle to the HIFSYS syscon range.
  61 +Root ports are defined as subnodes of the PCIe controller node.
  62 +
  63 +Required properties:
  64 +- device_type: Must be "pci"
  65 +- assigned-addresses: Address and size of the port configuration registers
  66 +- reg: PCI bus address of the root port
  67 +- #address-cells: Must be 3
  68 +- #size-cells: Must be 2
  69 +- ranges: Sub-ranges distributed from the PCIe controller node. An empty
  70 +  property is sufficient.
  71 +
  72 +Example:
  73 +
  74 +SoC DTSI:
  75 +
  76 +       hifsys: clock-controller@1a000000 {
  77 +               compatible = "mediatek,mt7623-hifsys",
  78 +                            "mediatek,mt2701-hifsys",
  79 +                            "syscon";
  80 +               reg = <0 0x1a000000 0 0x1000>;
  81 +               #clock-cells = <1>;
  82 +               #reset-cells = <1>;
  83 +       };
  84 +
  85 +       pcie-controller@1a140000 {
  86 +               compatible = "mediatek,mt7623-pcie";
  87 +               device_type = "pci";
  88 +               reg = <0 0x1a140000 0 0x8000>, /* PCI-Express registers */
  89 +                     <0 0x1a149000 0 0x1000>, /* PCI-Express PHY0 */
  90 +                     <0 0x1a14a000 0 0x1000>, /* PCI-Express PHY1 */
  91 +                     <0 0x1a244000 0 0x1000>; /* PCI-Express PHY2 */
  92 +               reg-names = "pcie", "pcie phy0", "pcie phy1", "pcie phy2";
  93 +               interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_LOW>,
  94 +                            <GIC_SPI 194 IRQ_TYPE_LEVEL_LOW>,
  95 +                            <GIC_SPI 195 IRQ_TYPE_LEVEL_LOW>;
  96 +               interrupt-names = "pcie0", "pcie1", "pcie2";
  97 +               clocks = <&topckgen CLK_TOP_ETHIF_SEL>;
  98 +               clock-names = "pcie";
  99 +               power-domains = <&scpsys MT2701_POWER_DOMAIN_HIF>;
 100 +               resets = <&hifsys MT2701_HIFSYS_PCIE0_RST>,
 101 +                        <&hifsys MT2701_HIFSYS_PCIE1_RST>,
 102 +                        <&hifsys MT2701_HIFSYS_PCIE2_RST>;
 103 +               reset-names = "pcie0", "pice1", "pcie2";
 104 +
 105 +               bus-range = <0x00 0xff>;
 106 +               #address-cells = <3>;
 107 +               #size-cells = <2>;
 108 +
 109 +                mediatek,hifsys = <&hifsys>;
 110 +
 111 +               ranges = <0x81000000 0 0x1a160000 0 0x1a160000 0 0x00010000 /* io space */
 112 +                         0x83000000 0 0x60000000 0 0x60000000 0 0x10000000>; /* pci memory */
 113 +
 114 +               status = "disabled";
 115 +
 116 +               pcie@1,0 {
 117 +                       device_type = "pci";
 118 +                       reg = <0x0800 0 0 0 0>;
 119 +
 120 +                       #address-cells = <3>;
 121 +                       #size-cells = <2>;
 122 +                       ranges;
 123 +
 124 +                       status = "disabled";
 125 +               };
 126 +
 127 +               pcie@2,0{
 128 +                       device_type = "pci";
 129 +                       reg = <0x1000 0 0 0 0>;
 130 +
 131 +                       #address-cells = <3>;
 132 +                       #size-cells = <2>;
 133 +                       ranges;
 134 +
 135 +                       status = "disabled";
 136 +               };
 137 +
 138 +               pcie@3,0{
 139 +                       device_type = "pci";
 140 +                       reg = <0x1800 0 0 0 0>;
 141 +
 142 +                       #address-cells = <3>;
 143 +                       #size-cells = <2>;
 144 +                       ranges;
 145 +
 146 +                       status = "disabled";
 147 +               };
 148 +       };
 149 +
 150 +Board DTS:
 151 +
 152 +       pcie-controller {
 153 +               status = "okay";
 154 +
 155 +               pci@1,0 {
 156 +                       status = "okay";
 157 +               };
 158 +       };
 159 diff --git a/arch/arm/boot/dts/mt7623.dtsi b/arch/arm/boot/dts/mt7623.dtsi
 160 index c53c10d..c8c802d 100644
 161 --- a/arch/arm/boot/dts/mt7623.dtsi
 162 +++ b/arch/arm/boot/dts/mt7623.dtsi
 163 @@ -292,6 +292,18 @@
 164                 status = "disabled";
 165         };
 166
 167 +       nand: nfi@1100d000 {
 168 +               compatible = "mediatek,mt2701-nfc";
 169 +               reg = <0 0x1100d000 0 0x1000>, <0 0x1100e000 0 0x1000>;
 170 +               interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_LOW>,
 171 +                            <GIC_SPI 55 IRQ_TYPE_LEVEL_LOW>;
 172 +               clocks = <&pericfg CLK_PERI_NFI>, <&pericfg CLK_PERI_NFI_ECC>,
 173 +                        <&pericfg CLK_PERI_NFI_PAD>;
 174 +               clock-names = "nfi_clk", "nfiecc_clk", "pad_clk";
 175 +               nand-on-flash-bbt;
 176 +               status = "disabled";
 177 +       };
 178 +
 179         mmc0: mmc@11230000 {
 180                 compatible = "mediatek,mt7623-mmc",
 181                              "mediatek,mt8135-mmc";
 182 --
 183 1.7.10.4
 184