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treewide: fix replace nbd@openwrt.org with nbd@nbd.name
[openwrt.git] / target / linux / mediatek / patches-4.4 / 0023-ARM-dts-mediatek-add-MT7623-basic-support.patch
1 From 83ef9fb21a896ac03c3a78bc3ae0b21f3b0a43a3 Mon Sep 17 00:00:00 2001
2 From: John Crispin <blogic@openwrt.org>
3 Date: Tue, 5 Jan 2016 12:16:17 +0100
4 Subject: [PATCH 23/91] ARM: dts: mediatek: add MT7623 basic support
5
6 This adds basic chip support for Mediatek MT7623.
7
8 Signed-off-by: John Crispin <blogic@openwrt.org>
9 ---
10  arch/arm/boot/dts/Makefile        |    1 +
11  arch/arm/boot/dts/mt7623-evb.dts  |  474 +++++++++++++++++++++++++++++
12  arch/arm/boot/dts/mt7623.dtsi     |  593 +++++++++++++++++++++++++++++++++++++
13  arch/arm/mach-mediatek/Kconfig    |    4 +
14  arch/arm/mach-mediatek/mediatek.c |    1 +
15  5 files changed, 1073 insertions(+)
16  create mode 100644 arch/arm/boot/dts/mt7623-evb.dts
17  create mode 100644 arch/arm/boot/dts/mt7623.dtsi
18
19 diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
20 index 30bbc37..2bce370 100644
21 --- a/arch/arm/boot/dts/Makefile
22 +++ b/arch/arm/boot/dts/Makefile
23 @@ -774,6 +774,7 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += \
24         mt6580-evbp1.dtb \
25         mt6589-aquaris5.dtb \
26         mt6592-evb.dtb \
27 +       mt7623-evb.dtb \
28         mt8127-moose.dtb \
29         mt8135-evbp1.dtb
30  dtb-$(CONFIG_ARCH_ZX) += zx296702-ad1.dtb
31 diff --git a/arch/arm/boot/dts/mt7623-evb.dts b/arch/arm/boot/dts/mt7623-evb.dts
32 new file mode 100644
33 index 0000000..70b92a4
34 --- /dev/null
35 +++ b/arch/arm/boot/dts/mt7623-evb.dts
36 @@ -0,0 +1,474 @@
37 +/*
38 + * Copyright (c) 2016 MediaTek Inc.
39 + * Author: John Crispin <blogic@openwrt.org>
40 + *
41 + * This program is free software; you can redistribute it and/or modify
42 + * it under the terms of the GNU General Public License version 2 as
43 + * published by the Free Software Foundation.
44 + *
45 + * This program is distributed in the hope that it will be useful,
46 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
47 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
48 + * GNU General Public License for more details.
49 + */
50 +
51 +/dts-v1/;
52 +
53 +#include "mt7623.dtsi"
54 +#include <dt-bindings/gpio/gpio.h>
55 +
56 +/ {
57 +       model = "MediaTek MT7623 evaluation board";
58 +       compatible = "mediatek,mt7623-evb", "mediatek,mt7623";
59 +
60 +       chosen {
61 +               stdout-path = &uart2;
62 +       };
63 +
64 +       memory {
65 +               reg = <0 0x80000000 0 0x20000000>;
66 +       };
67 +
68 +       usb_p1_vbus: regulator@0 {
69 +               compatible = "regulator-fixed";
70 +               regulator-name = "usb_vbus";
71 +               regulator-min-microvolt = <5000000>;
72 +               regulator-max-microvolt = <5000000>;
73 +               gpio = <&pio 135 GPIO_ACTIVE_HIGH>;
74 +               enable-active-high;
75 +       };
76 +};
77 +
78 +&cpu0 {
79 +       proc-supply = <&mt6323_vproc_reg>;
80 +};
81 +
82 +&cpu1 {
83 +       proc-supply = <&mt6323_vproc_reg>;
84 +};
85 +
86 +&cpu2 {
87 +       proc-supply = <&mt6323_vproc_reg>;
88 +};
89 +
90 +&cpu3 {
91 +       proc-supply = <&mt6323_vproc_reg>;
92 +};
93 +
94 +&pwrap {
95 +       pmic: mt6323 {
96 +               compatible = "mediatek,mt6323";
97 +               interrupt-parent = <&pio>;
98 +               interrupts = <150 IRQ_TYPE_LEVEL_HIGH>;
99 +               interrupt-controller;
100 +               #interrupt-cells = <2>;
101 +
102 +               mt6323regulator: mt6323regulator{
103 +                       compatible = "mediatek,mt6323-regulator";
104 +
105 +                       mt6323_vproc_reg: buck_vproc{
106 +                               regulator-name = "vproc";
107 +                               regulator-min-microvolt = < 700000>;
108 +                               regulator-max-microvolt = <1350000>;
109 +                               regulator-ramp-delay = <12500>;
110 +                               regulator-always-on;
111 +                               regulator-boot-on;
112 +                       };
113 +
114 +                       mt6323_vsys_reg: buck_vsys{
115 +                               regulator-name = "vsys";
116 +                               regulator-min-microvolt = <1400000>;
117 +                               regulator-max-microvolt = <2987500>;
118 +                               regulator-ramp-delay = <25000>;
119 +                               regulator-always-on;
120 +                               regulator-boot-on;
121 +                       };
122 +
123 +                       mt6323_vpa_reg: buck_vpa{
124 +                               regulator-name = "vpa";
125 +                               regulator-min-microvolt = < 500000>;
126 +                               regulator-max-microvolt = <3650000>;
127 +                       };
128 +
129 +                       mt6323_vtcxo_reg: ldo_vtcxo{
130 +                               regulator-name = "vtcxo";
131 +                               regulator-min-microvolt = <2800000>;
132 +                               regulator-max-microvolt = <2800000>;
133 +                               regulator-enable-ramp-delay = <90>;
134 +                               regulator-always-on;
135 +                               regulator-boot-on;
136 +                       };
137 +
138 +                       mt6323_vcn28_reg: ldo_vcn28{
139 +                               regulator-name = "vcn28";
140 +                               regulator-min-microvolt = <2800000>;
141 +                               regulator-max-microvolt = <2800000>;
142 +                               regulator-enable-ramp-delay = <185>;
143 +                       };
144 +
145 +                       mt6323_vcn33_bt_reg: ldo_vcn33_bt{
146 +                               regulator-name = "vcn33_bt";
147 +                               regulator-min-microvolt = <3300000>;
148 +                               regulator-max-microvolt = <3600000>;
149 +                               regulator-enable-ramp-delay = <185>;
150 +                       };
151 +
152 +                       mt6323_vcn33_wifi_reg: ldo_vcn33_wifi{
153 +                               regulator-name = "vcn33_wifi";
154 +                               regulator-min-microvolt = <3300000>;
155 +                               regulator-max-microvolt = <3600000>;
156 +                               regulator-enable-ramp-delay = <185>;
157 +                       };
158 +
159 +                       mt6323_va_reg: ldo_va{
160 +                               regulator-name = "va";
161 +                               regulator-min-microvolt = <2800000>;
162 +                               regulator-max-microvolt = <2800000>;
163 +                               regulator-enable-ramp-delay = <216>;
164 +                               regulator-always-on;
165 +                               regulator-boot-on;
166 +                       };
167 +
168 +                       mt6323_vcama_reg: ldo_vcama{
169 +                               regulator-name = "vcama";
170 +                               regulator-min-microvolt = <1500000>;
171 +                               regulator-max-microvolt = <2800000>;
172 +                               regulator-enable-ramp-delay = <216>;
173 +                       };
174 +
175 +                       mt6323_vio28_reg: ldo_vio28{
176 +                               regulator-name = "vio28";
177 +                               regulator-min-microvolt = <2800000>;
178 +                               regulator-max-microvolt = <2800000>;
179 +                               regulator-enable-ramp-delay = <216>;
180 +                               regulator-always-on;
181 +                               regulator-boot-on;
182 +                       };
183 +
184 +                       mt6323_vusb_reg: ldo_vusb{
185 +                               regulator-name = "vusb";
186 +                               regulator-min-microvolt = <3300000>;
187 +                               regulator-max-microvolt = <3300000>;
188 +                               regulator-enable-ramp-delay = <216>;
189 +                               regulator-boot-on;
190 +                       };
191 +
192 +                       mt6323_vmc_reg: ldo_vmc{
193 +                               regulator-name = "vmc";
194 +                               regulator-min-microvolt = <1800000>;
195 +                               regulator-max-microvolt = <3300000>;
196 +                               regulator-enable-ramp-delay = <36>;
197 +                               regulator-boot-on;
198 +                       };
199 +
200 +                       mt6323_vmch_reg: ldo_vmch{
201 +                               regulator-name = "vmch";
202 +                               regulator-min-microvolt = <3000000>;
203 +                               regulator-max-microvolt = <3300000>;
204 +                               regulator-enable-ramp-delay = <36>;
205 +                               regulator-boot-on;
206 +                       };
207 +
208 +                       mt6323_vemc3v3_reg: ldo_vemc3v3{
209 +                               regulator-name = "vemc3v3";
210 +                               regulator-min-microvolt = <3000000>;
211 +                               regulator-max-microvolt = <3300000>;
212 +                               regulator-enable-ramp-delay = <36>;
213 +                               regulator-boot-on;
214 +                       };
215 +
216 +                       mt6323_vgp1_reg: ldo_vgp1{
217 +                               regulator-name = "vgp1";
218 +                               regulator-min-microvolt = <1200000>;
219 +                               regulator-max-microvolt = <3300000>;
220 +                               regulator-enable-ramp-delay = <216>;
221 +                       };
222 +
223 +                       mt6323_vgp2_reg: ldo_vgp2{
224 +                               regulator-name = "vgp2";
225 +                               regulator-min-microvolt = <1200000>;
226 +                               regulator-max-microvolt = <3000000>;
227 +                               regulator-enable-ramp-delay = <216>;
228 +                       };
229 +
230 +                       mt6323_vgp3_reg: ldo_vgp3{
231 +                               regulator-name = "vgp3";
232 +                               regulator-min-microvolt = <1200000>;
233 +                               regulator-max-microvolt = <1800000>;
234 +                               regulator-enable-ramp-delay = <216>;
235 +                       };
236 +
237 +                       mt6323_vcn18_reg: ldo_vcn18{
238 +                               regulator-name = "vcn18";
239 +                               regulator-min-microvolt = <1800000>;
240 +                               regulator-max-microvolt = <1800000>;
241 +                               regulator-enable-ramp-delay = <216>;
242 +                       };
243 +
244 +                       mt6323_vsim1_reg: ldo_vsim1{
245 +                               regulator-name = "vsim1";
246 +                               regulator-min-microvolt = <1800000>;
247 +                               regulator-max-microvolt = <3000000>;
248 +                               regulator-enable-ramp-delay = <216>;
249 +                       };
250 +
251 +                       mt6323_vsim2_reg: ldo_vsim2{
252 +                               regulator-name = "vsim2";
253 +                               regulator-min-microvolt = <1800000>;
254 +                               regulator-max-microvolt = <3000000>;
255 +                               regulator-enable-ramp-delay = <216>;
256 +                       };
257 +
258 +                       mt6323_vrtc_reg: ldo_vrtc{
259 +                               regulator-name = "vrtc";
260 +                               regulator-min-microvolt = <2800000>;
261 +                               regulator-max-microvolt = <2800000>;
262 +                               regulator-always-on;
263 +                               regulator-boot-on;
264 +                       };
265 +
266 +                       mt6323_vcamaf_reg: ldo_vcamaf{
267 +                               regulator-name = "vcamaf";
268 +                               regulator-min-microvolt = <1200000>;
269 +                               regulator-max-microvolt = <3300000>;
270 +                               regulator-enable-ramp-delay = <216>;
271 +                       };
272 +
273 +                       mt6323_vibr_reg: ldo_vibr{
274 +                               regulator-name = "vibr";
275 +                               regulator-min-microvolt = <1200000>;
276 +                               regulator-max-microvolt = <3300000>;
277 +                               regulator-enable-ramp-delay = <36>;
278 +                       };
279 +
280 +                       mt6323_vrf18_reg: ldo_vrf18{
281 +                               regulator-name = "vrf18";
282 +                               regulator-min-microvolt = <1825000>;
283 +                               regulator-max-microvolt = <1825000>;
284 +                               regulator-enable-ramp-delay = <187>;
285 +                       };
286 +
287 +                       mt6323_vm_reg: ldo_vm{
288 +                               regulator-name = "vm";
289 +                               regulator-min-microvolt = <1200000>;
290 +                               regulator-max-microvolt = <1800000>;
291 +                               regulator-enable-ramp-delay = <216>;
292 +                               regulator-always-on;
293 +                               regulator-boot-on;
294 +                       };
295 +
296 +                       mt6323_vio18_reg: ldo_vio18{
297 +                               regulator-name = "vio18";
298 +                               regulator-min-microvolt = <1800000>;
299 +                               regulator-max-microvolt = <1800000>;
300 +                               regulator-enable-ramp-delay = <216>;
301 +                               regulator-always-on;
302 +                               regulator-boot-on;
303 +                       };
304 +
305 +                       mt6323_vcamd_reg: ldo_vcamd{
306 +                               regulator-name = "vcamd";
307 +                               regulator-min-microvolt = <1200000>;
308 +                               regulator-max-microvolt = <1800000>;
309 +                               regulator-enable-ramp-delay = <216>;
310 +                       };
311 +
312 +                       mt6323_vcamio_reg: ldo_vcamio{
313 +                               regulator-name = "vcamio";
314 +                               regulator-min-microvolt = <1800000>;
315 +                               regulator-max-microvolt = <1800000>;
316 +                               regulator-enable-ramp-delay = <216>;
317 +                       };
318 +               };
319 +       };
320 +};
321 +
322 +&uart2 {
323 +       status = "okay";
324 +};
325 +
326 +&mmc0 {
327 +       status = "okay";
328 +       pinctrl-names = "default", "state_uhs";
329 +       pinctrl-0 = <&mmc0_pins_default>;
330 +       pinctrl-1 = <&mmc0_pins_uhs>;
331 +       bus-width = <8>;
332 +       max-frequency = <50000000>;
333 +       cap-mmc-highspeed;
334 +       vmmc-supply = <&mt6323_vemc3v3_reg>;
335 +       vqmmc-supply = <&mt6323_vio18_reg>;
336 +       non-removable;
337 +};
338 +
339 +&mmc1 {
340 +       status = "okay";
341 +       pinctrl-names = "default", "state_uhs";
342 +       pinctrl-0 = <&mmc1_pins_default>;
343 +       pinctrl-1 = <&mmc1_pins_uhs>;
344 +       bus-width = <4>;
345 +       max-frequency = <50000000>;
346 +       cap-sd-highspeed;
347 +       sd-uhs-sdr25;
348 +//     cd-gpios = <&pio 132 0>;
349 +       vmmc-supply = <&mt6323_vmch_reg>;
350 +       vqmmc-supply = <&mt6323_vmc_reg>;
351 +};
352 +
353 +&pio {
354 +       mmc0_pins_default: mmc0default {
355 +               pins_cmd_dat {
356 +                       pinmux = <MT7623_PIN_111_MSDC0_DAT7_FUNC_MSDC0_DAT7>,
357 +                                <MT7623_PIN_112_MSDC0_DAT6_FUNC_MSDC0_DAT6>,
358 +                                <MT7623_PIN_113_MSDC0_DAT5_FUNC_MSDC0_DAT5>,
359 +                                <MT7623_PIN_114_MSDC0_DAT4_FUNC_MSDC0_DAT4>,
360 +                                <MT7623_PIN_118_MSDC0_DAT3_FUNC_MSDC0_DAT3>,
361 +                                <MT7623_PIN_119_MSDC0_DAT2_FUNC_MSDC0_DAT2>,
362 +                                <MT7623_PIN_120_MSDC0_DAT1_FUNC_MSDC0_DAT1>,
363 +                                <MT7623_PIN_121_MSDC0_DAT0_FUNC_MSDC0_DAT0>,
364 +                                <MT7623_PIN_116_MSDC0_CMD_FUNC_MSDC0_CMD>;
365 +                       input-enable;
366 +                       bias-pull-up;
367 +               };
368 +
369 +               pins_clk {
370 +                       pinmux = <MT7623_PIN_117_MSDC0_CLK_FUNC_MSDC0_CLK>;
371 +                       bias-pull-down;
372 +               };
373 +
374 +               pins_rst {
375 +                       pinmux = <MT7623_PIN_115_MSDC0_RSTB_FUNC_MSDC0_RSTB>;
376 +                       bias-pull-up;
377 +               };
378 +       };
379 +
380 +       mmc0_pins_uhs: mmc0 {
381 +               pins_cmd_dat {
382 +                       pinmux = <MT7623_PIN_111_MSDC0_DAT7_FUNC_MSDC0_DAT7>,
383 +                                <MT7623_PIN_112_MSDC0_DAT6_FUNC_MSDC0_DAT6>,
384 +                                <MT7623_PIN_113_MSDC0_DAT5_FUNC_MSDC0_DAT5>,
385 +                                <MT7623_PIN_114_MSDC0_DAT4_FUNC_MSDC0_DAT4>,
386 +                                <MT7623_PIN_118_MSDC0_DAT3_FUNC_MSDC0_DAT3>,
387 +                                <MT7623_PIN_119_MSDC0_DAT2_FUNC_MSDC0_DAT2>,
388 +                                <MT7623_PIN_120_MSDC0_DAT1_FUNC_MSDC0_DAT1>,
389 +                                <MT7623_PIN_121_MSDC0_DAT0_FUNC_MSDC0_DAT0>,
390 +                                <MT7623_PIN_116_MSDC0_CMD_FUNC_MSDC0_CMD>;
391 +                       input-enable;
392 +                       drive-strength = <MTK_DRIVE_2mA>;
393 +                       bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
394 +               };
395 +
396 +               pins_clk {
397 +                       pinmux = <MT7623_PIN_117_MSDC0_CLK_FUNC_MSDC0_CLK>;
398 +                       drive-strength = <MTK_DRIVE_2mA>;
399 +                       bias-pull-down = <MTK_PUPD_SET_R1R0_01>;
400 +               };
401 +
402 +               pins_rst {
403 +                       pinmux = <MT7623_PIN_115_MSDC0_RSTB_FUNC_MSDC0_RSTB>;
404 +                       bias-pull-up;
405 +               };
406 +       };
407 +
408 +       mmc1_pins_default: mmc1default {
409 +               pins_cmd_dat {
410 +                       pinmux = <MT7623_PIN_107_MSDC1_DAT0_FUNC_MSDC1_DAT0>,
411 +                                <MT7623_PIN_108_MSDC1_DAT1_FUNC_MSDC1_DAT1>,
412 +                                <MT7623_PIN_109_MSDC1_DAT2_FUNC_MSDC1_DAT2>,
413 +                                <MT7623_PIN_110_MSDC1_DAT3_FUNC_MSDC1_DAT3>,
414 +                                <MT7623_PIN_105_MSDC1_CMD_FUNC_MSDC1_CMD>;
415 +                       input-enable;
416 +                       drive-strength = <MTK_DRIVE_4mA>;
417 +                       bias-pull-up = <MTK_PUPD_SET_R1R0_10>;
418 +               };
419 +
420 +               pins_clk {
421 +                       pinmux = <MT7623_PIN_106_MSDC1_CLK_FUNC_MSDC1_CLK>;
422 +                       bias-pull-down;
423 +                       drive-strength = <MTK_DRIVE_4mA>;
424 +               };
425 +
426 +//             pins_insert {
427 +//                     pinmux = <MT8173_PIN_132_I2S0_DATA1_FUNC_GPIO132>;
428 +//                     bias-pull-up;
429 +//             };
430 +       };
431 +
432 +       mmc1_pins_uhs: mmc1 {
433 +               pins_cmd_dat {
434 +                       pinmux = <MT7623_PIN_107_MSDC1_DAT0_FUNC_MSDC1_DAT0>,
435 +                                <MT7623_PIN_108_MSDC1_DAT1_FUNC_MSDC1_DAT1>,
436 +                                <MT7623_PIN_109_MSDC1_DAT2_FUNC_MSDC1_DAT2>,
437 +                                <MT7623_PIN_110_MSDC1_DAT3_FUNC_MSDC1_DAT3>,
438 +                                <MT7623_PIN_105_MSDC1_CMD_FUNC_MSDC1_CMD>;
439 +                       input-enable;
440 +                       drive-strength = <MTK_DRIVE_4mA>;
441 +                       bias-pull-up = <MTK_PUPD_SET_R1R0_10>;
442 +               };
443 +
444 +               pins_clk {
445 +                       pinmux = <MT7623_PIN_106_MSDC1_CLK_FUNC_MSDC1_CLK>;
446 +                       drive-strength = <MTK_DRIVE_4mA>;
447 +                       bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
448 +               };
449 +       };
450 +
451 +       eth_default: eth {
452 +               pins_eth {
453 +                       pinmux = <MT7623_PIN_275_G2_MDC_FUNC_MDC>,
454 +                                <MT7623_PIN_276_G2_MDIO_FUNC_MDIO>,
455 +                                <MT7623_PIN_262_G2_TXEN_FUNC_G2_TXEN>,
456 +                                <MT7623_PIN_263_G2_TXD3_FUNC_G2_TXD3>,
457 +                                <MT7623_PIN_264_G2_TXD2_FUNC_G2_TXD2>,
458 +                                <MT7623_PIN_265_G2_TXD1_FUNC_G2_TXD1>,
459 +                                <MT7623_PIN_266_G2_TXD0_FUNC_G2_TXD0>,
460 +                                <MT7623_PIN_267_G2_TXCLK_FUNC_G2_TXC>,
461 +                                <MT7623_PIN_268_G2_RXCLK_FUNC_G2_RXC>,
462 +                                <MT7623_PIN_269_G2_RXD0_FUNC_G2_RXD0>,
463 +                                <MT7623_PIN_270_G2_RXD1_FUNC_G2_RXD1>,
464 +                                <MT7623_PIN_271_G2_RXD2_FUNC_G2_RXD2>,
465 +                                <MT7623_PIN_272_G2_RXD3_FUNC_G2_RXD3>,
466 +                                <MT7623_PIN_273_ESW_INT_FUNC_ESW_INT>,
467 +                                <MT7623_PIN_274_G2_RXDV_FUNC_G2_RXDV>;
468 +               };
469 +               
470 +               pins_eth_rst {
471 +                       pinmux = <MT7623_PIN_15_GPIO15_FUNC_GPIO15>;
472 +                       output-low;
473 +               };
474 +       };
475 +};
476 +
477 +&usb1 {
478 +       vusb33-supply = <&mt6323_vusb_reg>;
479 +       vbus-supply = <&usb_p1_vbus>;
480 +       status = "okay";
481 +};
482 +
483 +&u3phy1 {
484 +       status = "okay";
485 +};
486 +
487 +&pcie {
488 +       status = "okay";
489 +};
490 +
491 +&eth {
492 +       status = "okay";
493 +};
494 +
495 +&gmac1 {
496 +       mac-address = [00 11 22 33 44 56];
497 +       status = "okay";
498 +};
499 +
500 +&gmac2 {
501 +       mac-address = [00 11 22 33 44 55];
502 +       status = "okay";
503 +};
504 +
505 +&gsw {
506 +       pinctrl-names = "default";
507 +       pinctrl-0 = <&eth_default>;
508 +       mediatek,reset-pin = <&pio 15 0>;
509 +       status = "okay";
510 +};
511 diff --git a/arch/arm/boot/dts/mt7623.dtsi b/arch/arm/boot/dts/mt7623.dtsi
512 new file mode 100644
513 index 0000000..80c1ab8
514 --- /dev/null
515 +++ b/arch/arm/boot/dts/mt7623.dtsi
516 @@ -0,0 +1,593 @@
517 +/*
518 + * Copyright (c) 2016 MediaTek Inc.
519 + * Author: John Crispin <blogic@openwrt.org>
520 + *
521 + * This program is free software; you can redistribute it and/or modify
522 + * it under the terms of the GNU General Public License version 2 as
523 + * published by the Free Software Foundation.
524 + *
525 + * This program is distributed in the hope that it will be useful,
526 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
527 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
528 + * GNU General Public License for more details.
529 + */
530 +
531 +#include <dt-bindings/interrupt-controller/irq.h>
532 +#include <dt-bindings/interrupt-controller/arm-gic.h>
533 +#include <dt-bindings/clock/mt2701-clk.h>
534 +#include <dt-bindings/power/mt2701-power.h>
535 +#include <dt-bindings/phy/phy.h>
536 +#include <dt-bindings/reset-controller/mt2701-resets.h>
537 +#include <dt-bindings/pinctrl/mt7623-pinfunc.h>
538 +#include "skeleton64.dtsi"
539 +
540 +
541 +/ {
542 +       compatible = "mediatek,mt7623";
543 +       interrupt-parent = <&sysirq>;
544 +
545 +       cpus {
546 +               #address-cells = <1>;
547 +               #size-cells = <0>;
548 +               enable-method = "mediatek,mt6589-smp";
549 +
550 +               cpu0: cpu@0 {
551 +                       device_type = "cpu";
552 +                       compatible = "arm,cortex-a7";
553 +                       reg = <0x0>;
554 +                       clocks = <&infracfg CLK_INFRA_CPUSEL>,
555 +                                <&apmixedsys CLK_APMIXED_MAINPLL>;
556 +                       clock-names = "cpu", "intermediate";
557 +                       operating-points = <
558 +                               598000 1150000
559 +                               747500 1150000
560 +                               1040000 1150000
561 +                               1196000 1200000
562 +                               1300000 1300000
563 +                       >;
564 +               };
565 +               cpu1: cpu@1 {
566 +                       device_type = "cpu";
567 +                       compatible = "arm,cortex-a7";
568 +                       reg = <0x1>;
569 +                       clocks = <&infracfg CLK_INFRA_CPUSEL>,
570 +                                <&apmixedsys CLK_APMIXED_MAINPLL>;
571 +                       clock-names = "cpu", "intermediate";
572 +                       operating-points = <
573 +                               598000 1150000
574 +                               747500 1150000
575 +                               1040000 1150000
576 +                               1196000 1200000
577 +                               1300000 1300000
578 +                       >;
579 +               };
580 +               cpu2: cpu@2 {
581 +                       device_type = "cpu";
582 +                       compatible = "arm,cortex-a7";
583 +                       reg = <0x2>;
584 +                       clocks = <&infracfg CLK_INFRA_CPUSEL>,
585 +                                <&apmixedsys CLK_APMIXED_MAINPLL>;
586 +                       clock-names = "cpu", "intermediate";
587 +                       operating-points = <
588 +                               598000 1150000
589 +                               747500 1150000
590 +                               1040000 1150000
591 +                               1196000 1200000
592 +                               1300000 1300000
593 +                       >;
594 +               };
595 +               cpu3: cpu@3 {
596 +                       device_type = "cpu";
597 +                       compatible = "arm,cortex-a7";
598 +                       reg = <0x3>;
599 +                       clocks = <&infracfg CLK_INFRA_CPUSEL>,
600 +                                <&apmixedsys CLK_APMIXED_MAINPLL>;
601 +                       clock-names = "cpu", "intermediate";
602 +                       operating-points = <
603 +                               598000 1150000
604 +                               747500 1150000
605 +                               1040000 1150000
606 +                               1196000 1200000
607 +                               1300000 1300000
608 +                       >;
609 +               };
610 +       };
611 +
612 +       system_clk: dummy13m {
613 +               compatible = "fixed-clock";
614 +               clock-frequency = <13000000>;
615 +               #clock-cells = <0>;
616 +       };
617 +
618 +       rtc_clk: dummy32k {
619 +               compatible = "fixed-clock";
620 +               clock-frequency = <32000>;
621 +               #clock-cells = <0>;
622 +               clock-output-names = "clk32k";
623 +       };
624 +
625 +       clk26m: dummy26m {
626 +               compatible = "fixed-clock";
627 +               clock-frequency = <26000000>;
628 +               #clock-cells = <0>;
629 +               clock-output-names = "clk26m";
630 +       };
631 +
632 +       timer {
633 +               compatible = "arm,armv7-timer";
634 +               interrupt-parent = <&gic>;
635 +               interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
636 +                            <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
637 +                            <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
638 +                            <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
639 +               clock-frequency = <13000000>;
640 +               arm,cpu-registers-not-fw-configured;
641 +       };
642 +
643 +       topckgen: power-controller@10000000 {
644 +               compatible = "mediatek,mt7623-topckgen",
645 +                            "mediatek,mt2701-topckgen",
646 +                            "syscon";
647 +               reg = <0 0x10000000 0 0x1000>;
648 +               #clock-cells = <1>;
649 +       };
650 +
651 +       infracfg: power-controller@10001000 {
652 +               compatible = "mediatek,mt7623-infracfg",
653 +                            "mediatek,mt2701-infracfg",
654 +                            "syscon";
655 +               reg = <0 0x10001000 0 0x1000>;
656 +               #clock-cells = <1>;
657 +               #reset-cells = <1>;
658 +       };
659 +
660 +       pericfg: pericfg@10003000 {
661 +               compatible = "mediatek,mt7623-pericfg",
662 +                            "mediatek,mt2701-pericfg",
663 +                            "syscon";
664 +               reg = <0 0x10003000 0 0x1000>;
665 +               #clock-cells = <1>;
666 +               #reset-cells = <1>;
667 +       };
668 +
669 +       pio: pinctrl@10005000 {
670 +               compatible = "mediatek,mt7623-pinctrl";
671 +               reg = <0 0x1000b000 0 0x1000>;
672 +               mediatek,pctl-regmap = <&syscfg_pctl_a>;
673 +               pins-are-numbered;
674 +               gpio-controller;
675 +               #gpio-cells = <2>;
676 +               interrupt-controller;
677 +               interrupt-parent = <&gic>;
678 +               #interrupt-cells = <2>;
679 +               interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
680 +                            <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
681 +       };
682 +
683 +       syscfg_pctl_a: syscfg@10005000 {
684 +               compatible = "mediatek,mt7623-pctl-a-syscfg", "syscon";
685 +               reg = <0 0x10005000 0 0x1000>;
686 +       };
687 +
688 +       scpsys: scpsys@10006000 {
689 +               #power-domain-cells = <1>;
690 +               compatible = "mediatek,mt7623-scpsys",
691 +                            "mediatek,mt2701-scpsys";
692 +               reg = <0 0x10006000 0 0x1000>;
693 +               infracfg = <&infracfg>;
694 +               clocks = <&clk26m>,
695 +                        <&topckgen CLK_TOP_MM_SEL>;
696 +               clock-names = "mfg", "mm";
697 +       };
698 +
699 +       watchdog: watchdog@10007000 {
700 +               compatible = "mediatek,mt7623-wdt",
701 +                            "mediatek,mt6589-wdt";
702 +               reg = <0 0x10007000 0 0x100>;
703 +       };
704 +
705 +       timer: timer@10008000 {
706 +               compatible = "mediatek,mt7623-timer",
707 +                            "mediatek,mt6577-timer";
708 +               reg = <0 0x10008000 0 0x80>;
709 +               interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_LOW>;
710 +               clocks = <&system_clk>, <&rtc_clk>;
711 +               clock-names = "system-clk", "rtc-clk";
712 +       };
713 +
714 +       pwrap: pwrap@1000d000 {
715 +               compatible = "mediatek,mt7623-pwrap",
716 +                            "mediatek,mt2701-pwrap";
717 +               reg = <0 0x1000d000 0 0x1000>;
718 +               reg-names = "pwrap";
719 +               interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
720 +               resets = <&infracfg MT2701_INFRA_PMIC_WRAP_RST>;
721 +               reset-names = "pwrap";
722 +               clocks = <&infracfg CLK_INFRA_PMICSPI>,
723 +                        <&infracfg CLK_INFRA_PMICWRAP>;
724 +               clock-names = "spi", "wrap";
725 +       };
726 +
727 +       sysirq: interrupt-controller@10200100 {
728 +               compatible = "mediatek,mt7623-sysirq",
729 +                            "mediatek,mt6577-sysirq";
730 +               interrupt-controller;
731 +               #interrupt-cells = <3>;
732 +               interrupt-parent = <&gic>;
733 +               reg = <0 0x10200100 0 0x1c>;
734 +       };
735 +
736 +       apmixedsys: apmixedsys@10209000 {
737 +               compatible = "mediatek,mt7623-apmixedsys",
738 +                            "mediatek,mt2701-apmixedsys";
739 +               reg = <0 0x10209000 0 0x1000>;
740 +               #clock-cells = <1>;
741 +       };
742 +
743 +       gic: interrupt-controller@10211000 {
744 +               compatible = "arm,cortex-a7-gic";
745 +               interrupt-controller;
746 +               #interrupt-cells = <3>;
747 +               interrupt-parent = <&gic>;
748 +               reg = <0 0x10211000 0 0x1000>,
749 +                     <0 0x10212000 0 0x1000>,
750 +                     <0 0x10214000 0 0x2000>,
751 +                     <0 0x10216000 0 0x2000>;
752 +       };
753 +
754 +       i2c0: i2c@11007000 {
755 +               compatible = "mediatek,mt7623-i2c",
756 +                            "mediatek,mt6577-i2c";
757 +               reg = <0 0x11007000 0 0x70>,
758 +                     <0 0x11000200 0 0x80>;
759 +               interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_LOW>;
760 +               clock-div = <16>;
761 +               clocks = <&pericfg CLK_PERI_I2C0>,
762 +                        <&pericfg CLK_PERI_AP_DMA>;
763 +               clock-names = "main", "dma";
764 +               #address-cells = <1>;
765 +               #size-cells = <0>;
766 +               status = "disabled";
767 +       };
768 +
769 +       i2c1: i2c@11008000 {
770 +               compatible = "mediatek,mt7623-i2c",
771 +                            "mediatek,mt6577-i2c";
772 +               reg = <0 0x11008000 0 0x70>,
773 +                     <0 0x11000280 0 0x80>;
774 +               interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_LOW>;
775 +               clock-div = <16>;
776 +               clocks = <&pericfg CLK_PERI_I2C1>,
777 +                        <&pericfg CLK_PERI_AP_DMA>;
778 +               clock-names = "main", "dma";
779 +               #address-cells = <1>;
780 +               #size-cells = <0>;
781 +               status = "disabled";
782 +       };
783 +
784 +       i2c2: i2c@11009000 {
785 +               compatible = "mediatek,mt7623-i2c",
786 +                            "mediatek,mt6577-i2c";
787 +               reg = <0 0x11009000 0 0x70>,
788 +                     <0 0x11000300 0 0x80>;
789 +               interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_LOW>;
790 +               clock-div = <16>;
791 +               clocks = <&pericfg CLK_PERI_I2C2>,
792 +                        <&pericfg CLK_PERI_AP_DMA>;
793 +               clock-names = "main", "dma";
794 +               #address-cells = <1>;
795 +               #size-cells = <0>;
796 +               status = "disabled";
797 +       };
798 +
799 +       uart0: serial@11002000 {
800 +               compatible = "mediatek,mt7623-uart",
801 +                            "mediatek,mt6577-uart";
802 +               reg = <0 0x11002000 0 0x400>;
803 +               interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_LOW>;
804 +               clocks = <&pericfg CLK_PERI_UART0_SEL>,
805 +                        <&pericfg CLK_PERI_UART0>;
806 +               clock-names = "baud", "bus";
807 +               status = "disabled";
808 +       };
809 +
810 +       uart1: serial@11003000 {
811 +               compatible = "mediatek,mt7623-uart",
812 +                            "mediatek,mt6577-uart";
813 +               reg = <0 0x11003000 0 0x400>;
814 +               interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_LOW>;
815 +               clocks = <&pericfg CLK_PERI_UART1_SEL>,
816 +                        <&pericfg CLK_PERI_UART1>;
817 +               clock-names = "baud", "bus";
818 +               status = "disabled";
819 +       };
820 +
821 +       uart2: serial@11004000 {
822 +               compatible = "mediatek,mt7623-uart",
823 +                            "mediatek,mt6577-uart";
824 +               reg = <0 0x11004000 0 0x400>;
825 +               interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_LOW>;
826 +               clocks = <&pericfg CLK_PERI_UART2_SEL>,
827 +                        <&pericfg CLK_PERI_UART2>;
828 +               clock-names = "baud", "bus";
829 +               status = "disabled";
830 +       };
831 +
832 +       uart3: serial@11005000 {
833 +               compatible = "mediatek,mt7623-uart",
834 +                            "mediatek,mt6577-uart";
835 +               reg = <0 0x11005000 0 0x400>;
836 +               interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_LOW>;
837 +               clocks = <&pericfg CLK_PERI_UART3_SEL>,
838 +                        <&pericfg CLK_PERI_UART3>;
839 +               clock-names = "baud", "bus";
840 +               status = "disabled";
841 +       };
842 +
843 +       spi: spi@1100a000 {
844 +               compatible = "mediatek,mt7623-spi", "mediatek,mt6589-spi";
845 +               reg = <0 0x1100a000 0 0x1000>;
846 +               interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_LOW>;
847 +               clocks = <&pericfg CLK_PERI_SPI0>;
848 +               clock-names = "main";
849 +
850 +               status = "disabled";
851 +       };
852 +
853 +       nandc: nfi@1100d000 {
854 +               compatible = "mediatek,mt2701-nfc";
855 +               reg = <0 0x1100d000 0 0x1000>;
856 +               interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_LOW>;
857 +               clocks = <&pericfg CLK_PERI_NFI>,
858 +                        <&pericfg CLK_PERI_NFI_PAD>;
859 +               clock-names = "nfi_clk", "pad_clk";
860 +               status = "disabled";
861 +               ecc-engine = <&bch>;
862 +               #address-cells = <1>;
863 +               #size-cells = <0>;
864 +       };
865 +
866 +       bch: ecc@1100e000 {
867 +               compatible = "mediatek,mt2701-ecc";
868 +               reg = <0 0x1100e000 0 0x1000>;
869 +               interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_LOW>;
870 +               clocks = <&pericfg CLK_PERI_NFI_ECC>;
871 +               clock-names = "nfiecc_clk";
872 +               status = "disabled";
873 +       };
874 +
875 +       mmc0: mmc@11230000 {
876 +               compatible = "mediatek,mt7623-mmc",
877 +                            "mediatek,mt8135-mmc";
878 +               reg = <0 0x11230000 0 0x1000>;
879 +               interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_LOW>;
880 +               clocks = <&pericfg CLK_PERI_MSDC30_0>,
881 +                        <&topckgen CLK_TOP_MSDC30_0_SEL>;
882 +               clock-names = "source", "hclk";
883 +               status = "disabled";
884 +       };
885 +
886 +       mmc1: mmc@11240000 {
887 +               compatible = "mediatek,mt7623-mmc",
888 +                            "mediatek,mt8135-mmc";
889 +               reg = <0 0x11240000 0 0x1000>;
890 +               interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_LOW>;
891 +               clocks = <&pericfg CLK_PERI_MSDC30_1>,
892 +                        <&topckgen CLK_TOP_MSDC30_1_SEL>;
893 +               clock-names = "source", "hclk";
894 +               status = "disabled";
895 +       };
896 +
897 +       usb1: usb@1a1c0000 {
898 +               compatible = "mediatek,mt2701-xhci",
899 +                            "mediatek,mt8173-xhci";
900 +               reg = <0 0x1a1c0000 0 0x1000>,
901 +                     <0 0x1a1c4700 0 0x0100>;
902 +               interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_LOW>;
903 +               clocks = <&hifsys CLK_HIFSYS_USB0PHY>,
904 +                        <&topckgen CLK_TOP_ETHIF_SEL>;
905 +               clock-names = "sys_ck", "ethif";
906 +               power-domains = <&scpsys MT2701_POWER_DOMAIN_HIF>;
907 +               phys = <&phy_port0 PHY_TYPE_USB3>;
908 +               status = "disabled";
909 +       };
910 +
911 +       u3phy1: usb-phy@1a1c4000 {
912 +               compatible = "mediatek,mt2701-u3phy",
913 +                            "mediatek,mt8173-u3phy";
914 +               reg = <0 0x1a1c4000 0 0x0700>;
915 +               clocks = <&clk26m>;
916 +               clock-names = "u3phya_ref";
917 +               #phy-cells = <1>;
918 +               #address-cells = <2>;
919 +               #size-cells = <2>;
920 +               ranges;
921 +               status = "disabled";
922 +
923 +               phy_port0: phy_port0: port@1a1c4800 {
924 +                       reg = <0 0x1a1c4800 0 0x800>;
925 +                       #phy-cells = <1>;
926 +                       status = "okay";
927 +               };
928 +       };
929 +
930 +       usb2: usb@1a240000 {
931 +               compatible = "mediatek,mt2701-xhci",
932 +                            "mediatek,mt8173-xhci";
933 +               reg = <0 0x1a240000 0 0x1000>,
934 +                     <0 0x1a244700 0 0x0100>;
935 +               interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_LOW>;
936 +               clocks = <&hifsys CLK_HIFSYS_USB1PHY>,
937 +                        <&topckgen CLK_TOP_ETHIF_SEL>;
938 +               clock-names = "sys_ck", "ethif";
939 +               power-domains = <&scpsys MT2701_POWER_DOMAIN_HIF>;
940 +               phys = <&u3phy2 0>;
941 +               status = "disabled";
942 +       };
943 +
944 +       u3phy2: usb-phy@1a244000 {
945 +               compatible = "mediatek,mt2701-u3phy",
946 +                            "mediatek,mt8173-u3phy";
947 +               reg = <0 0x1a244000 0 0x0700>,
948 +                     <0 0x1a244800 0 0x0800>;
949 +               clocks = <&clk26m>;
950 +               clock-names = "u3phya_ref";
951 +               #phy-cells = <1>;
952 +               status = "disabled";
953 +       };
954 +
955 +       hifsys: clock-controller@1a000000 {
956 +               compatible = "mediatek,mt7623-hifsys",
957 +                            "mediatek,mt2701-hifsys",
958 +                            "syscon";
959 +               reg = <0 0x1a000000 0 0x1000>;
960 +               #clock-cells = <1>;
961 +               #reset-cells = <1>;
962 +       };
963 +
964 +       pcie: pcie@1a140000 {
965 +               compatible = "mediatek,mt7623-pcie";
966 +               device_type = "pci";
967 +               reg = <0 0x1a140000 0 0x8000>, /* PCI-Express registers */
968 +                     <0 0x1a149000 0 0x1000>, /* PCI-Express PHY0 */
969 +                     <0 0x1a14a000 0 0x1000>, /* PCI-Express PHY1 */
970 +                     <0 0x1a244000 0 0x1000>; /* PCI-Express PHY2 */
971 +               reg-names = "pcie", "pcie phy0", "pcie phy1", "pcie phy2";
972 +               interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_LOW>,
973 +                            <GIC_SPI 194 IRQ_TYPE_LEVEL_LOW>,
974 +                            <GIC_SPI 195 IRQ_TYPE_LEVEL_LOW>;
975 +               interrupt-names = "pcie0", "pcie1", "pcie2";
976 +               clocks = <&topckgen CLK_TOP_ETHIF_SEL>;
977 +               clock-names = "pcie";
978 +               power-domains = <&scpsys MT2701_POWER_DOMAIN_HIF>;
979 +               resets = <&hifsys MT2701_HIFSYS_PCIE0_RST>,
980 +                        <&hifsys MT2701_HIFSYS_PCIE1_RST>,
981 +                        <&hifsys MT2701_HIFSYS_PCIE2_RST>;
982 +               reset-names = "pcie0", "pcie1", "pcie2";
983 +
984 +               mediatek,hifsys = <&hifsys>;
985 +
986 +               bus-range = <0x00 0xff>;
987 +               #address-cells = <3>;
988 +               #size-cells = <2>;
989 +
990 +               ranges = <0x81000000 0 0x1a160000 0 0x1a160000 0 0x00010000 /* io space */
991 +                         0x83000000 0 0x60000000 0 0x60000000 0 0x10000000>; /* pci memory */
992 +
993 +               status = "disabled";
994 +
995 +               pcie@1,0 {
996 +                       device_type = "pci";
997 +                       reg = <0x0800 0 0 0 0>;
998 +
999 +                       #address-cells = <3>;
1000 +                       #size-cells = <2>;
1001 +                       ranges;
1002 +               };
1003 +
1004 +               pcie@2,0{
1005 +                       device_type = "pci";
1006 +                       reg = <0x1000 0 0 0 0>;
1007 +
1008 +                       #address-cells = <3>;
1009 +                       #size-cells = <2>;
1010 +                       ranges;
1011 +               };
1012 +
1013 +               pcie@3,0{
1014 +                       device_type = "pci";
1015 +                       reg = <0x1800 0 0 0 0>;
1016 +
1017 +                       #address-cells = <3>;
1018 +                       #size-cells = <2>;
1019 +                       ranges;
1020 +               };
1021 +       };
1022 +
1023 +       ethsys: syscon@1b000000 {
1024 +               compatible = "mediatek,mt2701-ethsys", "syscon";
1025 +               reg = <0 0x1b000000 0 0x1000>;
1026 +               #reset-cells = <1>;
1027 +               #clock-cells = <1>;
1028 +       };
1029 +
1030 +       eth: ethernet@1b100000 {
1031 +               compatible = "mediatek,mt7623-eth";
1032 +               reg = <0 0x1b100000 0 0x20000>;
1033 +       
1034 +               clocks = <&topckgen CLK_TOP_ETHIF_SEL>,
1035 +                        <&ethsys CLK_ETHSYS_ESW>,
1036 +                        <&ethsys CLK_ETHSYS_GP2>,
1037 +                        <&ethsys CLK_ETHSYS_GP1>;
1038 +               clock-names = "ethif", "esw", "gp2", "gp1";
1039 +               interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_LOW
1040 +                             GIC_SPI 199 IRQ_TYPE_LEVEL_LOW
1041 +                             GIC_SPI 198 IRQ_TYPE_LEVEL_LOW>;
1042 +               power-domains = <&scpsys MT2701_POWER_DOMAIN_ETH>;
1043 +
1044 +               resets = <&ethsys 6>;
1045 +               reset-names = "eth";
1046 +
1047 +               mediatek,ethsys = <&ethsys>;
1048 +               mediatek,pctl = <&syscfg_pctl_a>;
1049 +
1050 +               mediatek,switch = <&gsw>;
1051 +
1052 +               #address-cells = <1>;
1053 +               #size-cells = <0>;
1054 +       
1055 +               status = "disabled";
1056 +
1057 +               gmac1: mac@0 {
1058 +                       compatible = "mediatek,eth-mac";
1059 +                       reg = <0>;
1060 +
1061 +                       status = "disabled";
1062 +                       
1063 +                       phy-mode = "rgmii";
1064 +                       
1065 +                       fixed-link {
1066 +                               speed = <1000>;
1067 +                               full-duplex;
1068 +                               pause;
1069 +                       };
1070 +               };
1071 +
1072 +               gmac2: mac@1 {
1073 +                       compatible = "mediatek,eth-mac";
1074 +                       reg = <1>;
1075 +
1076 +                       phy-handle = <&phy5>;
1077 +                       status = "disabled";
1078 +               };
1079 +       
1080 +               mdio-bus {
1081 +                       #address-cells = <1>;
1082 +                       #size-cells = <0>;
1083 +
1084 +                       phy5: ethernet-phy@5 {
1085 +                               reg = <5>;
1086 +                               phy-mode = "rgmii-rxid";
1087 +                       };
1088 +
1089 +                       phy1f: ethernet-phy@1f {
1090 +                               reg = <0x1f>;
1091 +                               phy-mode = "rgmii";
1092 +                       };
1093 +               };
1094 +       };
1095 +
1096 +       gsw: switch@1b100000 {
1097 +               compatible = "mediatek,mt7623-gsw";
1098 +               interrupt-parent = <&pio>;
1099 +               interrupts = <168 IRQ_TYPE_EDGE_RISING>;
1100 +               resets = <&ethsys 2>;
1101 +               reset-names = "eth";
1102 +               clocks = <&apmixedsys CLK_APMIXED_TRGPLL>;
1103 +               clock-names = "trgpll";
1104 +               mt7530-supply = <&mt6323_vpa_reg>;
1105 +               mediatek,pctl-regmap = <&syscfg_pctl_a>;
1106 +               mediatek,ethsys = <&ethsys>;
1107 +               status = "disabled";
1108 +       };
1109 +};
1110 diff --git a/arch/arm/mach-mediatek/Kconfig b/arch/arm/mach-mediatek/Kconfig
1111 index 37dd438..7fb605e 100644
1112 --- a/arch/arm/mach-mediatek/Kconfig
1113 +++ b/arch/arm/mach-mediatek/Kconfig
1114 @@ -21,6 +21,10 @@ config MACH_MT6592
1115         bool "MediaTek MT6592 SoCs support"
1116         default ARCH_MEDIATEK
1117  
1118 +config MACH_MT7623
1119 +       bool "MediaTek MT7623 SoCs support"
1120 +       default ARCH_MEDIATEK
1121 +
1122  config MACH_MT8127
1123         bool "MediaTek MT8127 SoCs support"
1124         default ARCH_MEDIATEK
1125 diff --git a/arch/arm/mach-mediatek/mediatek.c b/arch/arm/mach-mediatek/mediatek.c
1126 index d019a08..bcfca37 100644
1127 --- a/arch/arm/mach-mediatek/mediatek.c
1128 +++ b/arch/arm/mach-mediatek/mediatek.c
1129 @@ -46,6 +46,7 @@ static void __init mediatek_timer_init(void)
1130  static const char * const mediatek_board_dt_compat[] = {
1131         "mediatek,mt6589",
1132         "mediatek,mt6592",
1133 +       "mediatek,mt7623",
1134         "mediatek,mt8127",
1135         "mediatek,mt8135",
1136         NULL,
1137 -- 
1138 1.7.10.4
1139
OpenWrt main development branch