target/linux/lantiq/patches/104-board_xway.patch

   1
   2 --- /dev/null
   3 +++ b/arch/mips/lantiq/xway/Kconfig
   4 @@ -0,0 +1,19 @@
   5 +if SOC_LANTIQ_XWAY
   6 +
   7 +menu "Mips Machine"
   8 +
   9 +config LANTIQ_MACH_EASY50812
  10 +       bool "Easy50812"
  11 +       default y
  12 +
  13 +config LANTIQ_MACH_EASY50712
  14 +       bool "Easy50712"
  15 +       default y
  16 +
  17 +config LANTIQ_MACH_EASY4010
  18 +       bool "Easy4010"
  19 +       default y
  20 +
  21 +endmenu
  22 +
  23 +endif
  24 --- /dev/null
  25 +++ b/arch/mips/lantiq/xway/gpio_ebu.c
  26 @@ -0,0 +1,116 @@
  27 +/*
  28 + *  This program is free software; you can redistribute it and/or modify it
  29 + *  under the terms of the GNU General Public License version 2 as published
  30 + *  by the Free Software Foundation.
  31 + *
  32 + *  Copyright (C) 2010 John Crispin <blogic@openwrt.org>
  33 + */
  34 +
  35 +#include <linux/init.h>
  36 +#include <linux/module.h>
  37 +#include <linux/types.h>
  38 +#include <linux/platform_device.h>
  39 +#include <linux/mutex.h>
  40 +#include <linux/gpio.h>
  41 +
  42 +#include <xway.h>
  43 +
  44 +#define LQ_EBU_BUSCON  0x1e7ff
  45 +#define LQ_EBU_WP              0x80000000
  46 +
  47 +static int shadow = 0x0000;
  48 +static void __iomem *virt;
  49 +
  50 +static int
  51 +lq_ebu_direction_output(struct gpio_chip *chip, unsigned offset, int value)
  52 +{
  53 +       return 0;
  54 +}
  55 +
  56 +static void
  57 +lq_ebu_apply(void)
  58 +{
  59 +       unsigned long flags;
  60 +       spin_lock_irqsave(&ebu_lock, flags);
  61 +       lq_w32(LQ_EBU_BUSCON, LQ_EBU_BUSCON1);
  62 +       *((__u16*)virt) = shadow;
  63 +       lq_w32(LQ_EBU_BUSCON | LQ_EBU_WP, LQ_EBU_BUSCON1);
  64 +       spin_unlock_irqrestore(&ebu_lock, flags);
  65 +}
  66 +
  67 +static void
  68 +lq_ebu_set(struct gpio_chip *chip, unsigned offset, int value)
  69 +{
  70 +       if(value)
  71 +               shadow |= (1 << offset);
  72 +       else
  73 +               shadow &= ~(1 << offset);
  74 +       lq_ebu_apply();
  75 +}
  76 +
  77 +static struct gpio_chip
  78 +lq_ebu_chip =
  79 +{
  80 +       .label = "lq_ebu",
  81 +       .direction_output = lq_ebu_direction_output,
  82 +       .set = lq_ebu_set,
  83 +       .base = 32,
  84 +       .ngpio = 16,
  85 +       .can_sleep = 1,
  86 +       .owner = THIS_MODULE,
  87 +};
  88 +
  89 +static int __devinit
  90 +lq_ebu_probe(struct platform_device *pdev)
  91 +{
  92 +       struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  93 +       int ret = 0;
  94 +       if (!res)
  95 +               return -ENOENT;
  96 +       res = request_mem_region(res->start, resource_size(res),
  97 +               dev_name(&pdev->dev));
  98 +       if (!res)
  99 +               return -EBUSY;
 100 +
 101 +       /* tell the ebu controller which mem addr we will be using */
 102 +       lq_w32(pdev->resource->start | 0x1, LQ_EBU_ADDRSEL1);
 103 +       lq_w32(LQ_EBU_BUSCON | LQ_EBU_WP, LQ_EBU_BUSCON1);
 104 +
 105 +       virt = ioremap_nocache(res->start, resource_size(res));
 106 +       if (!virt)
 107 +       {
 108 +               dev_err(&pdev->dev, "Failed to ioremap mem region\n");
 109 +               ret = -ENOMEM;
 110 +               goto err_release_mem_region;
 111 +       }
 112 +       /* grab the default settings passed form the platform code */
 113 +       shadow = (unsigned int) pdev->dev.platform_data;
 114 +
 115 +       ret = gpiochip_add(&lq_ebu_chip);
 116 +       if (!ret)
 117 +       {
 118 +               lq_ebu_apply();
 119 +               return 0;
 120 +       }
 121 +
 122 +err_release_mem_region:
 123 +       release_mem_region(res->start, resource_size(res));
 124 +       return ret;
 125 +}
 126 +
 127 +static struct platform_driver
 128 +lq_ebu_driver = {
 129 +       .probe = lq_ebu_probe,
 130 +       .driver = {
 131 +               .name = "lq_ebu",
 132 +               .owner = THIS_MODULE,
 133 +       },
 134 +};
 135 +
 136 +static int __init
 137 +init_lq_ebu(void)
 138 +{
 139 +       return platform_driver_register(&lq_ebu_driver);
 140 +}
 141 +
 142 +postcore_initcall(init_lq_ebu);
 143 --- /dev/null
 144 +++ b/arch/mips/lantiq/xway/gpio_leds.c
 145 @@ -0,0 +1,161 @@
 146 +/*
 147 + *  This program is free software; you can redistribute it and/or modify it
 148 + *  under the terms of the GNU General Public License version 2 as published
 149 + *  by the Free Software Foundation.
 150 + *
 151 + *  Copyright (C) 2007 John Crispin <blogic@openwrt.org>
 152 + *
 153 + */
 154 +
 155 +#include <linux/slab.h>
 156 +#include <linux/init.h>
 157 +#include <linux/module.h>
 158 +#include <linux/types.h>
 159 +#include <linux/platform_device.h>
 160 +#include <linux/mutex.h>
 161 +#include <linux/gpio.h>
 162 +
 163 +#include <xway.h>
 164 +
 165 +#define LQ_STP_BASE                    0x1E100BB0
 166 +#define LQ_STP_SIZE                    0x40
 167 +
 168 +#define LQ_STP_CON0                    0x00
 169 +#define LQ_STP_CON1                    0x04
 170 +#define LQ_STP_CPU0                    0x08
 171 +#define LQ_STP_CPU1                    0x0C
 172 +#define LQ_STP_AR                      0x10
 173 +
 174 +#define STP_CON0_SWU           (1 << 31)
 175 +
 176 +#define LQ_STP_2HZ                     (0)
 177 +#define LQ_STP_4HZ                     (1 << 23)
 178 +#define LQ_STP_8HZ                     (2 << 23)
 179 +#define LQ_STP_10HZ                    (3 << 23)
 180 +#define LQ_STP_MASK                    (0xf << 23)
 181 +
 182 +#define LQ_STP_UPD_SRC_FPI     (1 << 31)
 183 +#define LQ_STP_UPD_MASK                (3 << 30)
 184 +#define LQ_STP_ADSL_SRC                (3 << 24)
 185 +
 186 +#define LQ_STP_GROUP0          (1 << 0)
 187 +
 188 +#define LQ_STP_RISING          0
 189 +#define LQ_STP_FALLING         (1 << 26)
 190 +#define LQ_STP_EDGE_MASK       (1 << 26)
 191 +
 192 +#define lq_stp_r32(reg)                                __raw_readl(virt + reg)
 193 +#define lq_stp_w32(val, reg)           __raw_writel(val, virt + reg)
 194 +#define lq_stp_w32_mask(clear, set, reg) \
 195 +        lq_w32((lq_r32(virt + reg) & ~clear) | set, virt + reg)
 196 +
 197 +static int shadow = 0xffff;
 198 +static void __iomem *virt;
 199 +
 200 +static int
 201 +lq_stp_direction_output(struct gpio_chip *chip, unsigned offset, int value)
 202 +{
 203 +       return 0;
 204 +}
 205 +
 206 +static void
 207 +lq_stp_set(struct gpio_chip *chip, unsigned offset, int value)
 208 +{
 209 +       if(value)
 210 +               shadow |= (1 << offset);
 211 +       else
 212 +               shadow &= ~(1 << offset);
 213 +       lq_stp_w32(shadow, LQ_STP_CPU0);
 214 +}
 215 +
 216 +static struct gpio_chip lq_stp_chip =
 217 +{
 218 +       .label = "lq_stp",
 219 +       .direction_output = lq_stp_direction_output,
 220 +       .set = lq_stp_set,
 221 +       .base = 48,
 222 +       .ngpio = 24,
 223 +       .can_sleep = 1,
 224 +       .owner = THIS_MODULE,
 225 +};
 226 +
 227 +static int
 228 +lq_stp_hw_init(void)
 229 +{
 230 +       /* the 3 pins used to control the external stp */
 231 +       lq_gpio_request(4, 1, 0, 1, "stp-st");
 232 +       lq_gpio_request(5, 1, 0, 1, "stp-d");
 233 +       lq_gpio_request(6, 1, 0, 1, "stp-sh");
 234 +
 235 +       /* sane defaults */
 236 +       lq_stp_w32(0, LQ_STP_AR);
 237 +       lq_stp_w32(0, LQ_STP_CPU0);
 238 +       lq_stp_w32(0, LQ_STP_CPU1);
 239 +       lq_stp_w32(STP_CON0_SWU, LQ_STP_CON0);
 240 +       lq_stp_w32(0, LQ_STP_CON1);
 241 +
 242 +       /* rising or falling edge */
 243 +       lq_stp_w32_mask(LQ_STP_EDGE_MASK, LQ_STP_FALLING, LQ_STP_CON0);
 244 +
 245 +       /* per default stp 15-0 are set */
 246 +       lq_stp_w32_mask(0, LQ_STP_GROUP0, LQ_STP_CON1);
 247 +
 248 +       /* stp are update periodically by the FPID */
 249 +       lq_stp_w32_mask(LQ_STP_UPD_MASK, LQ_STP_UPD_SRC_FPI, LQ_STP_CON1);
 250 +
 251 +       /* set stp update speed */
 252 +       lq_stp_w32_mask(LQ_STP_MASK, LQ_STP_8HZ, LQ_STP_CON1);
 253 +
 254 +       /* adsl 0 and 1 stp are updated by the arc */
 255 +       lq_stp_w32_mask(0, LQ_STP_ADSL_SRC, LQ_STP_CON0);
 256 +
 257 +       lq_pmu_enable(PMU_LED);
 258 +       return 0;
 259 +}
 260 +
 261 +static int
 262 +lq_stp_probe(struct platform_device *pdev)
 263 +{
 264 +       struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 265 +       int ret = 0;
 266 +       if (!res)
 267 +               return -ENOENT;
 268 +       res = request_mem_region(res->start, resource_size(res),
 269 +               dev_name(&pdev->dev));
 270 +       if (!res)
 271 +               return -EBUSY;
 272 +       virt = ioremap_nocache(res->start, resource_size(res));
 273 +       if(!virt)
 274 +       {
 275 +               ret = -ENOMEM;
 276 +               goto err_release_mem_region;
 277 +       }
 278 +       ret = gpiochip_add(&lq_stp_chip);
 279 +       if(!ret)
 280 +               return lq_stp_hw_init();
 281 +
 282 +       iounmap(virt);
 283 +err_release_mem_region:
 284 +       release_mem_region(res->start, resource_size(res));
 285 +       return ret;
 286 +}
 287 +
 288 +static struct platform_driver lq_stp_driver = {
 289 +       .probe = lq_stp_probe,
 290 +       .driver = {
 291 +               .name = "lq_stp",
 292 +               .owner = THIS_MODULE,
 293 +       },
 294 +};
 295 +
 296 +int __init
 297 +init_lq_stp(void)
 298 +{
 299 +       int ret = platform_driver_register(&lq_stp_driver);
 300 +       if (ret)
 301 +               printk(KERN_INFO
 302 +                       "lq_stp: error registering platfom driver");
 303 +       return ret;
 304 +}
 305 +
 306 +postcore_initcall(init_lq_stp);
 307 --- /dev/null
 308 +++ b/arch/mips/lantiq/xway/mach-easy4010.c
 309 @@ -0,0 +1,82 @@
 310 +/*
 311 + *  This program is free software; you can redistribute it and/or modify it
 312 + *  under the terms of the GNU General Public License version 2 as published
 313 + *  by the Free Software Foundation.
 314 + *
 315 + *  Copyright (C) 2010 John Crispin <blogic@openwrt.org>
 316 + */
 317 +
 318 +#include <linux/init.h>
 319 +#include <linux/platform_device.h>
 320 +#include <linux/leds.h>
 321 +#include <linux/gpio.h>
 322 +#include <linux/gpio_buttons.h>
 323 +#include <linux/mtd/mtd.h>
 324 +#include <linux/mtd/partitions.h>
 325 +#include <linux/mtd/physmap.h>
 326 +#include <linux/input.h>
 327 +
 328 +#include <machine.h>
 329 +
 330 +#include <xway.h>
 331 +#include <lantiq_platform.h>
 332 +
 333 +#include "devices.h"
 334 +
 335 +#ifdef CONFIG_MTD_PARTITIONS
 336 +static struct mtd_partition easy4010_partitions[] =
 337 +{
 338 +       {
 339 +               .name   = "uboot",
 340 +               .offset = 0x0,
 341 +               .size   = 0x20000,
 342 +       },
 343 +       {
 344 +               .name   = "uboot_env",
 345 +               .offset = 0x20000,
 346 +               .size   = 0x10000,
 347 +       },
 348 +       {
 349 +               .name   = "linux",
 350 +               .offset = 0x30000,
 351 +               .size   = 0x3D0000,
 352 +       },
 353 +};
 354 +#endif
 355 +
 356 +static struct physmap_flash_data easy4010_flash_data = {
 357 +#ifdef CONFIG_MTD_PARTITIONS
 358 +       .nr_parts       = ARRAY_SIZE(easy4010_partitions),
 359 +       .parts          = easy4010_partitions,
 360 +#endif
 361 +};
 362 +
 363 +static struct lq_pci_data lq_pci_data = {
 364 +       .clock      = PCI_CLOCK_INT,
 365 +       .gpio   = PCI_GNT1 | PCI_REQ1,
 366 +       .irq    = {
 367 +               [14] = INT_NUM_IM0_IRL0 + 22,
 368 +       },
 369 +};
 370 +
 371 +static struct lq_eth_data lq_eth_data = {
 372 +       .mii_mode = REV_MII_MODE,
 373 +};
 374 +
 375 +static void __init
 376 +easy4010_init(void)
 377 +{
 378 +       lq_register_gpio();
 379 +       lq_register_gpio_stp();
 380 +       lq_register_asc(0);
 381 +       lq_register_asc(1);
 382 +       lq_register_nor(&easy4010_flash_data);
 383 +       lq_register_wdt();
 384 +       lq_register_pci(&lq_pci_data);
 385 +       lq_register_ethernet(&lq_eth_data);
 386 +}
 387 +
 388 +MIPS_MACHINE(LANTIQ_MACH_EASY4010,
 389 +                       "EASY4010",
 390 +                       "EASY4010 Eval Board",
 391 +                       easy4010_init);
 392 --- /dev/null
 393 +++ b/arch/mips/lantiq/xway/mach-easy50712.c
 394 @@ -0,0 +1,82 @@
 395 +/*
 396 + *  This program is free software; you can redistribute it and/or modify it
 397 + *  under the terms of the GNU General Public License version 2 as published
 398 + *  by the Free Software Foundation.
 399 + *
 400 + *  Copyright (C) 2010 John Crispin <blogic@openwrt.org>
 401 + */
 402 +
 403 +#include <linux/init.h>
 404 +#include <linux/platform_device.h>
 405 +#include <linux/leds.h>
 406 +#include <linux/gpio.h>
 407 +#include <linux/gpio_buttons.h>
 408 +#include <linux/mtd/mtd.h>
 409 +#include <linux/mtd/partitions.h>
 410 +#include <linux/mtd/physmap.h>
 411 +#include <linux/input.h>
 412 +
 413 +#include <machine.h>
 414 +
 415 +#include <xway.h>
 416 +#include <lantiq_platform.h>
 417 +
 418 +#include "devices.h"
 419 +
 420 +#ifdef CONFIG_MTD_PARTITIONS
 421 +static struct mtd_partition easy50712_partitions[] =
 422 +{
 423 +       {
 424 +               .name   = "uboot",
 425 +               .offset = 0x0,
 426 +               .size   = 0x20000,
 427 +       },
 428 +       {
 429 +               .name   = "uboot_env",
 430 +               .offset = 0x20000,
 431 +               .size   = 0x10000,
 432 +       },
 433 +       {
 434 +               .name   = "linux",
 435 +               .offset = 0x30000,
 436 +               .size   = 0x3D0000,
 437 +       },
 438 +};
 439 +#endif
 440 +
 441 +static struct physmap_flash_data easy50712_flash_data = {
 442 +#ifdef CONFIG_MTD_PARTITIONS
 443 +       .nr_parts       = ARRAY_SIZE(easy50712_partitions),
 444 +       .parts          = easy50712_partitions,
 445 +#endif
 446 +};
 447 +
 448 +static struct lq_pci_data lq_pci_data = {
 449 +       .clock      = PCI_CLOCK_INT,
 450 +       .gpio   = PCI_GNT1 | PCI_REQ1,
 451 +       .irq    = {
 452 +               [14] = INT_NUM_IM0_IRL0 + 22,
 453 +       },
 454 +};
 455 +
 456 +static struct lq_eth_data lq_eth_data = {
 457 +       .mii_mode = REV_MII_MODE,
 458 +};
 459 +
 460 +static void __init
 461 +easy50712_init(void)
 462 +{
 463 +       lq_register_asc(0);
 464 +       lq_register_asc(1);
 465 +       lq_register_gpio();
 466 +       lq_register_gpio_stp();
 467 +       lq_register_nor(&easy50712_flash_data);
 468 +       lq_register_wdt();
 469 +       lq_register_pci(&lq_pci_data);
 470 +       lq_register_ethernet(&lq_eth_data);
 471 +}
 472 +
 473 +MIPS_MACHINE(LANTIQ_MACH_EASY50712,
 474 +                       "EASY50712",
 475 +                       "EASY50712 Eval Board",
 476 +                       easy50712_init);
 477 --- /dev/null
 478 +++ b/arch/mips/lantiq/xway/mach-easy50812.c
 479 @@ -0,0 +1,81 @@
 480 +/*
 481 + *  This program is free software; you can redistribute it and/or modify it
 482 + *  under the terms of the GNU General Public License version 2 as published
 483 + *  by the Free Software Foundation.
 484 + *
 485 + *  Copyright (C) 2010 John Crispin <blogic@openwrt.org>
 486 + */
 487 +
 488 +#include <linux/init.h>
 489 +#include <linux/platform_device.h>
 490 +#include <linux/leds.h>
 491 +#include <linux/gpio.h>
 492 +#include <linux/gpio_buttons.h>
 493 +#include <linux/mtd/mtd.h>
 494 +#include <linux/mtd/partitions.h>
 495 +#include <linux/mtd/physmap.h>
 496 +#include <linux/input.h>
 497 +
 498 +#include <machine.h>
 499 +
 500 +#include <xway.h>
 501 +#include <lantiq_platform.h>
 502 +
 503 +#include "devices.h"
 504 +
 505 +#ifdef CONFIG_MTD_PARTITIONS
 506 +static struct mtd_partition easy50812_partitions[] =
 507 +{
 508 +       {
 509 +               .name   = "uboot",
 510 +               .offset = 0x0,
 511 +               .size   = 0x40000,
 512 +       },
 513 +       {
 514 +               .name   = "uboot_env",
 515 +               .offset = 0x40000,
 516 +               .size   = 0x10000,
 517 +       },
 518 +       {
 519 +               .name   = "linux",
 520 +               .offset = 0x50000,
 521 +               .size   = 0x3B0000,
 522 +       },
 523 +};
 524 +#endif
 525 +
 526 +static struct physmap_flash_data easy50812_flash_data = {
 527 +#ifdef CONFIG_MTD_PARTITIONS
 528 +       .nr_parts       = ARRAY_SIZE(easy50812_partitions),
 529 +       .parts          = easy50812_partitions,
 530 +#endif
 531 +};
 532 +
 533 +static struct lq_pci_data lq_pci_data = {
 534 +       .clock      = PCI_CLOCK_INT,
 535 +       .gpio   = PCI_GNT1 | PCI_REQ1,
 536 +       .irq    = {
 537 +               [14] = INT_NUM_IM0_IRL0 + 22,
 538 +       },
 539 +};
 540 +
 541 +static struct lq_eth_data lq_eth_data = {
 542 +       .mii_mode = REV_MII_MODE,
 543 +};
 544 +
 545 +static void __init
 546 +easy50812_init(void)
 547 +{
 548 +       lq_register_gpio();
 549 +       lq_register_asc(0);
 550 +       lq_register_asc(1);
 551 +       lq_register_nor(&easy50812_flash_data);
 552 +       lq_register_wdt();
 553 +       lq_register_pci(&lq_pci_data);
 554 +       lq_register_ethernet(&lq_eth_data);
 555 +}
 556 +
 557 +MIPS_MACHINE(LANTIQ_MACH_EASY50812,
 558 +                       "EASY50812",
 559 +                       "EASY50812 Eval Board",
 560 +                       easy50812_init);
 561 --- /dev/null
 562 +++ b/arch/mips/lantiq/xway/prom.c
 563 @@ -0,0 +1,52 @@
 564 +/*
 565 + *  This program is free software; you can redistribute it and/or modify it
 566 + *  under the terms of the GNU General Public License version 2 as published
 567 + *  by the Free Software Foundation.
 568 + *
 569 + *  Copyright (C) 2010 John Crispin <blogic@openwrt.org>
 570 + */
 571 +
 572 +#include <linux/module.h>
 573 +#include <linux/clk.h>
 574 +#include <asm/bootinfo.h>
 575 +#include <asm/time.h>
 576 +
 577 +#include <xway.h>
 578 +
 579 +#include "../prom.h"
 580 +
 581 +#define SOC_DANUBE             "Danube"
 582 +#define SOC_TWINPASS   "Twinpass"
 583 +#define SOC_AR9                        "AR9"
 584 +
 585 +void __init
 586 +lq_soc_detect(struct lq_soc_info *i)
 587 +{
 588 +       i->partnum = (lq_r32(LQ_MPS_CHIPID) & 0x0FFFFFFF) >> 12;
 589 +       i->rev = (lq_r32(LQ_MPS_CHIPID) & 0xF0000000) >> 28;
 590 +       switch (i->partnum)
 591 +       {
 592 +       case SOC_ID_DANUBE1:
 593 +       case SOC_ID_DANUBE2:
 594 +               i->name = SOC_DANUBE;
 595 +               i->type = SOC_TYPE_DANUBE;
 596 +               break;
 597 +
 598 +       case SOC_ID_TWINPASS:
 599 +               i->name = SOC_TWINPASS;
 600 +               i->type = SOC_TYPE_DANUBE;
 601 +               break;
 602 +
 603 +       case SOC_ID_ARX188:
 604 +       case SOC_ID_ARX168:
 605 +       case SOC_ID_ARX182:
 606 +               i->name = SOC_AR9;
 607 +               i->type = SOC_TYPE_AR9;
 608 +               break;
 609 +
 610 +       default:
 611 +               printk(KERN_ERR "unknown chiprev : 0x%08X\n", i->partnum);
 612 +               while(1) {      };
 613 +               break;
 614 +       }
 615 +}
 616 --- /dev/null
 617 +++ b/arch/mips/lantiq/xway/devices.c
 618 @@ -0,0 +1,336 @@
 619 +/*
 620 + *  This program is free software; you can redistribute it and/or modify it
 621 + *  under the terms of the GNU General Public License version 2 as published
 622 + *  by the Free Software Foundation.
 623 + *
 624 + *  Copyright (C) 2010 John Crispin <blogic@openwrt.org>
 625 + */
 626 +
 627 +#include <linux/init.h>
 628 +#include <linux/module.h>
 629 +#include <linux/types.h>
 630 +#include <linux/string.h>
 631 +#include <linux/mtd/physmap.h>
 632 +#include <linux/kernel.h>
 633 +#include <linux/reboot.h>
 634 +#include <linux/platform_device.h>
 635 +#include <linux/leds.h>
 636 +#include <linux/etherdevice.h>
 637 +#include <linux/reboot.h>
 638 +#include <linux/time.h>
 639 +#include <linux/io.h>
 640 +#include <linux/gpio.h>
 641 +#include <linux/gpio_buttons.h>
 642 +#include <linux/leds.h>
 643 +
 644 +#include <asm/bootinfo.h>
 645 +#include <asm/irq.h>
 646 +
 647 +#include <xway.h>
 648 +#include <xway_irq.h>
 649 +#include <lantiq_platform.h>
 650 +
 651 +#define IRQ_RES(resname,irq) {.name=#resname,.start=(irq),.flags=IORESOURCE_IRQ}
 652 +
 653 +/* gpio leds */
 654 +static struct gpio_led_platform_data lq_gpio_led_data;
 655 +
 656 +static struct platform_device lq_gpio_leds =
 657 +{
 658 +       .name = "leds-gpio",
 659 +       .dev = {
 660 +               .platform_data = (void *) &lq_gpio_led_data,
 661 +       }
 662 +};
 663 +
 664 +void __init
 665 +lq_register_gpio_leds(struct gpio_led *leds, int cnt)
 666 +{
 667 +       lq_gpio_led_data.leds = leds;
 668 +       lq_gpio_led_data.num_leds = cnt;
 669 +       platform_device_register(&lq_gpio_leds);
 670 +}
 671 +
 672 +/* gpio buttons */
 673 +static struct gpio_buttons_platform_data lq_gpio_buttons_platform_data;
 674 +
 675 +static struct platform_device lq_gpio_buttons_platform_device =
 676 +{
 677 +       .name = "gpio-buttons",
 678 +       .id = 0,
 679 +       .dev = {
 680 +               .platform_data = (void *) &lq_gpio_buttons_platform_data,
 681 +       },
 682 +};
 683 +
 684 +void __init
 685 +lq_register_gpio_buttons(struct gpio_button *buttons, int cnt)
 686 +{
 687 +       lq_gpio_buttons_platform_data.buttons = buttons;
 688 +       lq_gpio_buttons_platform_data.nbuttons = cnt;
 689 +       platform_device_register(&lq_gpio_buttons_platform_device);
 690 +}
 691 +
 692 +/* serial to parallel conversion */
 693 +static struct resource lq_stp_resource =
 694 +{
 695 +       .name   = "stp",
 696 +       .start  = LQ_STP_BASE,
 697 +       .end    = LQ_STP_BASE + LQ_STP_SIZE - 1,
 698 +       .flags  = IORESOURCE_MEM,
 699 +};
 700 +
 701 +void __init
 702 +lq_register_gpio_stp(void)
 703 +{
 704 +       platform_device_register_simple("lq_stp", 0, &lq_stp_resource, 1);
 705 +}
 706 +
 707 +/* nor flash */
 708 +static struct resource lq_nor_resource =
 709 +{
 710 +       .name   = "nor",
 711 +       .start  = LQ_FLASH_START,
 712 +       .end    = LQ_FLASH_START + LQ_FLASH_MAX - 1,
 713 +       .flags  = IORESOURCE_MEM,
 714 +};
 715 +
 716 +static struct platform_device lq_nor =
 717 +{
 718 +       .name                   = "lq_nor",
 719 +       .resource               = &lq_nor_resource,
 720 +       .num_resources  = 1,
 721 +};
 722 +
 723 +void __init
 724 +lq_register_nor(struct physmap_flash_data *data)
 725 +{
 726 +       lq_nor.dev.platform_data = data;
 727 +       platform_device_register(&lq_nor);
 728 +}
 729 +
 730 +/* watchdog */
 731 +static struct resource lq_wdt_resource =
 732 +{
 733 +       .name   = "watchdog",
 734 +       .start  = LQ_WDT_BASE,
 735 +       .end    = LQ_WDT_BASE + LQ_WDT_SIZE - 1,
 736 +       .flags  = IORESOURCE_MEM,
 737 +};
 738 +
 739 +void __init
 740 +lq_register_wdt(void)
 741 +{
 742 +       platform_device_register_simple("lq_wdt", 0, &lq_wdt_resource, 1);
 743 +}
 744 +
 745 +/* gpio */
 746 +static struct resource lq_gpio_resource[] = {
 747 +       {
 748 +               .name   = "gpio0",
 749 +               .start  = LQ_GPIO0_BASE_ADDR,
 750 +               .end    = LQ_GPIO0_BASE_ADDR + LQ_GPIO_SIZE - 1,
 751 +               .flags  = IORESOURCE_MEM,
 752 +       }, {
 753 +               .name   = "gpio1",
 754 +               .start  = LQ_GPIO1_BASE_ADDR,
 755 +               .end    = LQ_GPIO1_BASE_ADDR + LQ_GPIO_SIZE - 1,
 756 +               .flags  = IORESOURCE_MEM,
 757 +       }
 758 +};
 759 +
 760 +void __init
 761 +lq_register_gpio(void)
 762 +{
 763 +       platform_device_register_simple("lq_gpio", 0, &lq_gpio_resource[0], 1);
 764 +       platform_device_register_simple("lq_gpio", 1, &lq_gpio_resource[1], 1);
 765 +}
 766 +
 767 +/* pci */
 768 +static struct platform_device lq_pci =
 769 +{
 770 +       .name                   = "lq_pci",
 771 +       .num_resources  = 0,
 772 +};
 773 +
 774 +void __init
 775 +lq_register_pci(struct lq_pci_data *data)
 776 +{
 777 +       lq_pci.dev.platform_data = data;
 778 +       platform_device_register(&lq_pci);
 779 +}
 780 +
 781 +/* ebu */
 782 +static struct resource lq_ebu_resource =
 783 +{
 784 +       .name   = "gpio_ebu",
 785 +       .start  = LQ_EBU_GPIO_START,
 786 +       .end    = LQ_EBU_GPIO_START + LQ_EBU_GPIO_SIZE - 1,
 787 +       .flags  = IORESOURCE_MEM,
 788 +};
 789 +
 790 +static struct platform_device lq_ebu =
 791 +{
 792 +       .name           = "lq_ebu",
 793 +       .resource       = &lq_ebu_resource,
 794 +       .num_resources  = 1,
 795 +};
 796 +
 797 +void __init
 798 +lq_register_gpio_ebu(unsigned int value)
 799 +{
 800 +       lq_ebu.dev.platform_data = (void*) value;
 801 +       platform_device_register(&lq_ebu);
 802 +}
 803 +
 804 +/* ethernet */
 805 +unsigned char lq_ethaddr[6] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
 806 +
 807 +static int __init
 808 +lq_set_ethaddr(char *str)
 809 +{
 810 +       sscanf(&str[8], "0%02hhx:0%02hhx:0%02hhx:0%02hhx:0%02hhx:0%02hhx",
 811 +               &lq_ethaddr[0], &lq_ethaddr[1], &lq_ethaddr[2],
 812 +               &lq_ethaddr[3], &lq_ethaddr[4], &lq_ethaddr[5]);
 813 +       return 0;
 814 +}
 815 +__setup("ethaddr=", lq_set_ethaddr);
 816 +
 817 +static struct resource lq_ethernet_resources =
 818 +{
 819 +       .name   = "etop",
 820 +       .start  = LQ_PPE32_BASE_ADDR,
 821 +       .end    = LQ_PPE32_BASE_ADDR + LQ_PPE32_SIZE - 1,
 822 +       .flags  = IORESOURCE_MEM,
 823 +};
 824 +
 825 +static struct platform_device lq_ethernet =
 826 +{
 827 +       .name                   = "lq_etop",
 828 +       .resource               = &lq_ethernet_resources,
 829 +       .num_resources  = 1,
 830 +};
 831 +
 832 +void __init
 833 +lq_register_ethernet(struct lq_eth_data *eth)
 834 +{
 835 +       if(!eth)
 836 +               return;
 837 +       if(!eth->mac)
 838 +               eth->mac = lq_ethaddr;
 839 +       if(!is_valid_ether_addr(eth->mac))
 840 +               random_ether_addr(eth->mac);
 841 +       lq_ethernet.dev.platform_data = eth;
 842 +       platform_device_register(&lq_ethernet);
 843 +}
 844 +
 845 +/* tapi */
 846 +static struct resource mps_resources[] = {
 847 +       {
 848 +               .name = "voice-mem",
 849 +               .flags = IORESOURCE_MEM,
 850 +               .start = 0x1f107000,
 851 +               .end =   0x1f1073ff,
 852 +       },
 853 +       {
 854 +               .name = "voice-mailbox",
 855 +               .flags = IORESOURCE_MEM,
 856 +               .start = 0x1f200000,
 857 +               .end =   0x1f2007ff,
 858 +       },
 859 +};
 860 +
 861 +static struct platform_device mps_device = {
 862 +       .name = "mps",
 863 +       .resource = mps_resources,
 864 +       .num_resources = ARRAY_SIZE(mps_resources),
 865 +};
 866 +
 867 +static struct platform_device vmmc_device = {
 868 +       .name = "vmmc",
 869 +       .dev = {
 870 +               .parent = &mps_device.dev,
 871 +       },
 872 +};
 873 +
 874 +static unsigned int *cp1_base;
 875 +unsigned int*
 876 +lq_get_cp1_base(void)
 877 +{
 878 +       return cp1_base;
 879 +}
 880 +EXPORT_SYMBOL(lq_get_cp1_base);
 881 +
 882 +void __init
 883 +lq_register_tapi(void)
 884 +{
 885 +#define CP1_SIZE       (1 << 20)
 886 +       dma_addr_t dma;
 887 +       mps_device.dev.platform_data =
 888 +       cp1_base =
 889 +               (void*)CPHYSADDR(dma_alloc_coherent(NULL, CP1_SIZE, &dma, GFP_ATOMIC));
 890 +       mps_device.dev.platform_data = cp1_base;
 891 +       platform_device_register(&mps_device);
 892 +       platform_device_register(&vmmc_device);
 893 +}
 894 +
 895 +/* asc ports */
 896 +static struct resource lq_asc0_resources[] =
 897 +{
 898 +       {
 899 +               .start  = LQ_ASC0_BASE,
 900 +               .end    = LQ_ASC0_BASE + LQ_ASC_SIZE - 1,
 901 +               .flags  = IORESOURCE_MEM,
 902 +       },
 903 +       IRQ_RES(tx, INT_NUM_IM3_IRL0),
 904 +       IRQ_RES(rx, INT_NUM_IM3_IRL0 + 1),
 905 +       IRQ_RES(err, INT_NUM_IM3_IRL0 + 2),
 906 +};
 907 +
 908 +static struct resource lq_asc1_resources[] =
 909 +{
 910 +       {
 911 +               .start  = LQ_ASC1_BASE,
 912 +               .end    = LQ_ASC1_BASE + LQ_ASC_SIZE - 1,
 913 +               .flags  = IORESOURCE_MEM,
 914 +       },
 915 +       IRQ_RES(tx, INT_NUM_IM3_IRL0 + 8),
 916 +       IRQ_RES(rx, INT_NUM_IM3_IRL0 + 9),
 917 +       IRQ_RES(err, INT_NUM_IM3_IRL0 + 10),
 918 +};
 919 +
 920 +void __init
 921 +lq_register_asc(int port)
 922 +{
 923 +       switch (port) {
 924 +       case 0:
 925 +               platform_device_register_simple("lq_asc", 0,
 926 +                       lq_asc0_resources, ARRAY_SIZE(lq_asc0_resources));
 927 +               break;
 928 +       case 1:
 929 +               platform_device_register_simple("lq_asc", 1,
 930 +                       lq_asc1_resources, ARRAY_SIZE(lq_asc1_resources));
 931 +               break;
 932 +       default:
 933 +               break;
 934 +       }
 935 +}
 936 +
 937 +void __init
 938 +lq_register_crypto(const char *name)
 939 +{
 940 +       platform_device_register_simple(name, 0, 0, 0);
 941 +}
 942 +
 943 +/* madwifi */
 944 +int lantiq_emulate_madwifi_eep = 0;
 945 +EXPORT_SYMBOL(lantiq_emulate_madwifi_eep);
 946 +
 947 +void __init
 948 +lq_register_madwifi_eep(void)
 949 +{
 950 +       lantiq_emulate_madwifi_eep = 1;
 951 +}
 952 +
 953 +
 954 +
 955 --- /dev/null
 956 +++ b/arch/mips/lantiq/xway/devices.h
 957 @@ -0,0 +1,28 @@
 958 +/*
 959 + *  This program is free software; you can redistribute it and/or modify it
 960 + *  under the terms of the GNU General Public License version 2 as published
 961 + *  by the Free Software Foundation.
 962 + *
 963 + *  Copyright (C) 2010 John Crispin <blogic@openwrt.org>
 964 + */
 965 +
 966 +#ifndef _LQ_DEVICES_H__
 967 +#define _LQ_DEVICES_H__
 968 +
 969 +#include <lantiq_platform.h>
 970 +#include <xway_irq.h>
 971 +
 972 +extern void __init lq_register_gpio(void);
 973 +extern void __init lq_register_gpio_stp(void);
 974 +extern void __init lq_register_gpio_ebu(unsigned int value);
 975 +extern void __init lq_register_gpio_leds(struct gpio_led *leds, int cnt);
 976 +extern void __init lq_register_pci(struct lq_pci_data *data);
 977 +extern void __init lq_register_nor(struct physmap_flash_data *data);
 978 +extern void __init lq_register_tapi(void);
 979 +extern void __init lq_register_madwifi_eep(void);
 980 +extern void __init lq_register_wdt(void);
 981 +extern void __init lq_register_ethernet(struct lq_eth_data *eth);
 982 +extern void __init lq_register_asc(int port);
 983 +extern void __init lq_register_gpio_buttons(struct gpio_button *buttons, int cnt);
 984 +
 985 +#endif
 986 --- /dev/null
 987 +++ b/arch/mips/lantiq/xway/dma.c
 988 @@ -0,0 +1,701 @@
 989 +#include <linux/module.h>
 990 +#include <linux/init.h>
 991 +#include <linux/sched.h>
 992 +#include <linux/kernel.h>
 993 +#include <linux/slab.h>
 994 +#include <linux/string.h>
 995 +#include <linux/timer.h>
 996 +#include <linux/fs.h>
 997 +#include <linux/errno.h>
 998 +#include <linux/stat.h>
 999 +#include <linux/mm.h>
1000 +#include <linux/tty.h>
1001 +#include <linux/selection.h>
1002 +#include <linux/kmod.h>
1003 +#include <linux/vmalloc.h>
1004 +#include <linux/interrupt.h>
1005 +#include <linux/delay.h>
1006 +#include <linux/uaccess.h>
1007 +#include <linux/errno.h>
1008 +#include <linux/io.h>
1009 +
1010 +#include <xway.h>
1011 +#include <xway_irq.h>
1012 +#include <xway_dma.h>
1013 +
1014 +#define LQ_DMA_CS                      ((u32 *)(LQ_DMA_BASE_ADDR + 0x18))
1015 +#define LQ_DMA_CIE                     ((u32 *)(LQ_DMA_BASE_ADDR + 0x2C))
1016 +#define LQ_DMA_IRNEN           ((u32 *)(LQ_DMA_BASE_ADDR + 0xf4))
1017 +#define LQ_DMA_CCTRL           ((u32 *)(LQ_DMA_BASE_ADDR + 0x1C))
1018 +#define LQ_DMA_CIS                     ((u32 *)(LQ_DMA_BASE_ADDR + 0x28))
1019 +#define LQ_DMA_CDLEN           ((u32 *)(LQ_DMA_BASE_ADDR + 0x24))
1020 +#define LQ_DMA_PS                      ((u32 *)(LQ_DMA_BASE_ADDR + 0x40))
1021 +#define LQ_DMA_PCTRL           ((u32 *)(LQ_DMA_BASE_ADDR + 0x44))
1022 +#define LQ_DMA_CTRL            ((u32 *)(LQ_DMA_BASE_ADDR + 0x10))
1023 +#define LQ_DMA_CPOLL           ((u32 *)(LQ_DMA_BASE_ADDR + 0x14))
1024 +#define LQ_DMA_CDBA            ((u32 *)(LQ_DMA_BASE_ADDR + 0x20))
1025 +
1026 +/*25 descriptors for each dma channel,4096/8/20=25.xx*/
1027 +#define LQ_DMA_DESCRIPTOR_OFFSET 25
1028 +
1029 +#define MAX_DMA_DEVICE_NUM  6  /*max ports connecting to dma */
1030 +#define MAX_DMA_CHANNEL_NUM 20 /*max dma channels */
1031 +#define DMA_INT_BUDGET      100        /*budget for interrupt handling */
1032 +#define DMA_POLL_COUNTER    4  /*fix me, set the correct counter value here! */
1033 +
1034 +extern void lq_mask_and_ack_irq(unsigned int irq_nr);
1035 +extern void lq_enable_irq(unsigned int irq_nr);
1036 +extern void lq_disable_irq(unsigned int irq_nr);
1037 +
1038 +u64 *g_desc_list;
1039 +struct dma_device_info dma_devs[MAX_DMA_DEVICE_NUM];
1040 +struct dma_channel_info dma_chan[MAX_DMA_CHANNEL_NUM];
1041 +
1042 +static const char *global_device_name[MAX_DMA_DEVICE_NUM] =
1043 +       { "PPE", "DEU", "SPI", "SDIO", "MCTRL0", "MCTRL1" };
1044 +
1045 +struct dma_chan_map default_dma_map[MAX_DMA_CHANNEL_NUM] = {
1046 +       {"PPE", LQ_DMA_RX, 0, LQ_DMA_CH0_INT, 0},
1047 +       {"PPE", LQ_DMA_TX, 0, LQ_DMA_CH1_INT, 0},
1048 +       {"PPE", LQ_DMA_RX, 1, LQ_DMA_CH2_INT, 1},
1049 +       {"PPE", LQ_DMA_TX, 1, LQ_DMA_CH3_INT, 1},
1050 +       {"PPE", LQ_DMA_RX, 2, LQ_DMA_CH4_INT, 2},
1051 +       {"PPE", LQ_DMA_TX, 2, LQ_DMA_CH5_INT, 2},
1052 +       {"PPE", LQ_DMA_RX, 3, LQ_DMA_CH6_INT, 3},
1053 +       {"PPE", LQ_DMA_TX, 3, LQ_DMA_CH7_INT, 3},
1054 +       {"DEU", LQ_DMA_RX, 0, LQ_DMA_CH8_INT, 0},
1055 +       {"DEU", LQ_DMA_TX, 0, LQ_DMA_CH9_INT, 0},
1056 +       {"DEU", LQ_DMA_RX, 1, LQ_DMA_CH10_INT, 1},
1057 +       {"DEU", LQ_DMA_TX, 1, LQ_DMA_CH11_INT, 1},
1058 +       {"SPI", LQ_DMA_RX, 0, LQ_DMA_CH12_INT, 0},
1059 +       {"SPI", LQ_DMA_TX, 0, LQ_DMA_CH13_INT, 0},
1060 +       {"SDIO", LQ_DMA_RX, 0, LQ_DMA_CH14_INT, 0},
1061 +       {"SDIO", LQ_DMA_TX, 0, LQ_DMA_CH15_INT, 0},
1062 +       {"MCTRL0", LQ_DMA_RX, 0, LQ_DMA_CH16_INT, 0},
1063 +       {"MCTRL0", LQ_DMA_TX, 0, LQ_DMA_CH17_INT, 0},
1064 +       {"MCTRL1", LQ_DMA_RX, 1, LQ_DMA_CH18_INT, 1},
1065 +       {"MCTRL1", LQ_DMA_TX, 1, LQ_DMA_CH19_INT, 1}
1066 +};
1067 +
1068 +struct dma_chan_map *chan_map = default_dma_map;
1069 +volatile u32 g_lq_dma_int_status;
1070 +volatile int g_lq_dma_in_process; /* 0=not in process, 1=in process */
1071 +
1072 +void do_dma_tasklet(unsigned long);
1073 +DECLARE_TASKLET(dma_tasklet, do_dma_tasklet, 0);
1074 +
1075 +u8 *common_buffer_alloc(int len, int *byte_offset, void **opt)
1076 +{
1077 +       u8 *buffer = kmalloc(len * sizeof(u8), GFP_KERNEL);
1078 +
1079 +       *byte_offset = 0;
1080 +
1081 +       return buffer;
1082 +}
1083 +
1084 +void common_buffer_free(u8 *dataptr, void *opt)
1085 +{
1086 +       kfree(dataptr);
1087 +}
1088 +
1089 +void enable_ch_irq(struct dma_channel_info *pCh)
1090 +{
1091 +       int chan_no = (int)(pCh - dma_chan);
1092 +       unsigned long flag;
1093 +
1094 +       local_irq_save(flag);
1095 +       lq_w32(chan_no, LQ_DMA_CS);
1096 +       lq_w32(0x4a, LQ_DMA_CIE);
1097 +       lq_w32(lq_r32(LQ_DMA_IRNEN) | (1 << chan_no), LQ_DMA_IRNEN);
1098 +       local_irq_restore(flag);
1099 +       lq_enable_irq(pCh->irq);
1100 +}
1101 +
1102 +void disable_ch_irq(struct dma_channel_info *pCh)
1103 +{
1104 +       unsigned long flag;
1105 +       int chan_no = (int) (pCh - dma_chan);
1106 +
1107 +       local_irq_save(flag);
1108 +       g_lq_dma_int_status &= ~(1 << chan_no);
1109 +       lq_w32(chan_no, LQ_DMA_CS);
1110 +       lq_w32(0, LQ_DMA_CIE);
1111 +       lq_w32(lq_r32(LQ_DMA_IRNEN) & ~(1 << chan_no), LQ_DMA_IRNEN);
1112 +       local_irq_restore(flag);
1113 +       lq_mask_and_ack_irq(pCh->irq);
1114 +}
1115 +
1116 +void open_chan(struct dma_channel_info *pCh)
1117 +{
1118 +       unsigned long flag;
1119 +       int chan_no = (int)(pCh - dma_chan);
1120 +
1121 +       local_irq_save(flag);
1122 +       lq_w32(chan_no, LQ_DMA_CS);
1123 +       lq_w32(lq_r32(LQ_DMA_CCTRL) | 1, LQ_DMA_CCTRL);
1124 +       if (pCh->dir == LQ_DMA_RX)
1125 +               enable_ch_irq(pCh);
1126 +       local_irq_restore(flag);
1127 +}
1128 +
1129 +void close_chan(struct dma_channel_info *pCh)
1130 +{
1131 +       unsigned long flag;
1132 +       int chan_no = (int) (pCh - dma_chan);
1133 +
1134 +       local_irq_save(flag);
1135 +       lq_w32(chan_no, LQ_DMA_CS);
1136 +       lq_w32(lq_r32(LQ_DMA_CCTRL) & ~1, LQ_DMA_CCTRL);
1137 +       disable_ch_irq(pCh);
1138 +       local_irq_restore(flag);
1139 +}
1140 +
1141 +void reset_chan(struct dma_channel_info *pCh)
1142 +{
1143 +       int chan_no = (int) (pCh - dma_chan);
1144 +
1145 +       lq_w32(chan_no, LQ_DMA_CS);
1146 +       lq_w32(lq_r32(LQ_DMA_CCTRL) | 2, LQ_DMA_CCTRL);
1147 +}
1148 +
1149 +void rx_chan_intr_handler(int chan_no)
1150 +{
1151 +       struct dma_device_info *pDev = (struct dma_device_info *)dma_chan[chan_no].dma_dev;
1152 +       struct dma_channel_info *pCh = &dma_chan[chan_no];
1153 +       struct rx_desc *rx_desc_p;
1154 +       int tmp;
1155 +       unsigned long flag;
1156 +
1157 +       /*handle command complete interrupt */
1158 +       rx_desc_p = (struct rx_desc *)pCh->desc_base + pCh->curr_desc;
1159 +       if (rx_desc_p->status.field.OWN == CPU_OWN
1160 +           && rx_desc_p->status.field.C
1161 +           && rx_desc_p->status.field.data_length < 1536){
1162 +               /* Every thing is correct, then we inform the upper layer */
1163 +               pDev->current_rx_chan = pCh->rel_chan_no;
1164 +               if (pDev->intr_handler)
1165 +                       pDev->intr_handler(pDev, RCV_INT);
1166 +               pCh->weight--;
1167 +       } else {
1168 +               local_irq_save(flag);
1169 +               tmp = lq_r32(LQ_DMA_CS);
1170 +               lq_w32(chan_no, LQ_DMA_CS);
1171 +               lq_w32(lq_r32(LQ_DMA_CIS) | 0x7e, LQ_DMA_CIS);
1172 +               lq_w32(tmp, LQ_DMA_CS);
1173 +               g_lq_dma_int_status &= ~(1 << chan_no);
1174 +               local_irq_restore(flag);
1175 +               lq_enable_irq(dma_chan[chan_no].irq);
1176 +       }
1177 +}
1178 +
1179 +inline void tx_chan_intr_handler(int chan_no)
1180 +{
1181 +       struct dma_device_info *pDev = (struct dma_device_info *)dma_chan[chan_no].dma_dev;
1182 +       struct dma_channel_info *pCh = &dma_chan[chan_no];
1183 +       int tmp;
1184 +       unsigned long flag;
1185 +
1186 +       local_irq_save(flag);
1187 +       tmp = lq_r32(LQ_DMA_CS);
1188 +       lq_w32(chan_no, LQ_DMA_CS);
1189 +       lq_w32(lq_r32(LQ_DMA_CIS) | 0x7e, LQ_DMA_CIS);
1190 +       lq_w32(tmp, LQ_DMA_CS);
1191 +       g_lq_dma_int_status &= ~(1 << chan_no);
1192 +       local_irq_restore(flag);
1193 +       pDev->current_tx_chan = pCh->rel_chan_no;
1194 +       if (pDev->intr_handler)
1195 +               pDev->intr_handler(pDev, TRANSMIT_CPT_INT);
1196 +}
1197 +
1198 +void do_dma_tasklet(unsigned long unused)
1199 +{
1200 +       int i;
1201 +       int chan_no = 0;
1202 +       int budget = DMA_INT_BUDGET;
1203 +       int weight = 0;
1204 +       unsigned long flag;
1205 +
1206 +       while (g_lq_dma_int_status) {
1207 +               if (budget-- < 0) {
1208 +                       tasklet_schedule(&dma_tasklet);
1209 +                       return;
1210 +               }
1211 +               chan_no = -1;
1212 +               weight = 0;
1213 +               for (i = 0; i < MAX_DMA_CHANNEL_NUM; i++) {
1214 +                       if ((g_lq_dma_int_status & (1 << i)) && dma_chan[i].weight > 0) {
1215 +                               if (dma_chan[i].weight > weight) {
1216 +                                       chan_no = i;
1217 +                                       weight = dma_chan[chan_no].weight;
1218 +                               }
1219 +                       }
1220 +               }
1221 +
1222 +               if (chan_no >= 0) {
1223 +                       if (chan_map[chan_no].dir == LQ_DMA_RX)
1224 +                               rx_chan_intr_handler(chan_no);
1225 +                       else
1226 +                               tx_chan_intr_handler(chan_no);
1227 +               } else {
1228 +                       for (i = 0; i < MAX_DMA_CHANNEL_NUM; i++)
1229 +                               dma_chan[i].weight = dma_chan[i].default_weight;
1230 +               }
1231 +       }
1232 +
1233 +       local_irq_save(flag);
1234 +       g_lq_dma_in_process = 0;
1235 +       if (g_lq_dma_int_status) {
1236 +               g_lq_dma_in_process = 1;
1237 +               tasklet_schedule(&dma_tasklet);
1238 +       }
1239 +       local_irq_restore(flag);
1240 +}
1241 +
1242 +irqreturn_t dma_interrupt(int irq, void *dev_id)
1243 +{
1244 +       struct dma_channel_info *pCh;
1245 +       int chan_no = 0;
1246 +       int tmp;
1247 +
1248 +       pCh = (struct dma_channel_info *)dev_id;
1249 +       chan_no = (int)(pCh - dma_chan);
1250 +       if (chan_no < 0 || chan_no > 19)
1251 +               BUG();
1252 +
1253 +       tmp = lq_r32(LQ_DMA_IRNEN);
1254 +       lq_w32(0, LQ_DMA_IRNEN);
1255 +       g_lq_dma_int_status |= 1 << chan_no;
1256 +       lq_w32(tmp, LQ_DMA_IRNEN);
1257 +       lq_mask_and_ack_irq(irq);
1258 +
1259 +       if (!g_lq_dma_in_process) {
1260 +               g_lq_dma_in_process = 1;
1261 +               tasklet_schedule(&dma_tasklet);
1262 +       }
1263 +
1264 +       return IRQ_HANDLED;
1265 +}
1266 +
1267 +struct dma_device_info *dma_device_reserve(char *dev_name)
1268 +{
1269 +       int i;
1270 +
1271 +       for (i = 0; i < MAX_DMA_DEVICE_NUM; i++) {
1272 +               if (strcmp(dev_name, dma_devs[i].device_name) == 0) {
1273 +                       if (dma_devs[i].reserved)
1274 +                               return NULL;
1275 +                       dma_devs[i].reserved = 1;
1276 +                       break;
1277 +               }
1278 +       }
1279 +
1280 +       return &dma_devs[i];
1281 +}
1282 +EXPORT_SYMBOL(dma_device_reserve);
1283 +
1284 +void dma_device_release(struct dma_device_info *dev)
1285 +{
1286 +       dev->reserved = 0;
1287 +}
1288 +EXPORT_SYMBOL(dma_device_release);
1289 +
1290 +void dma_device_register(struct dma_device_info *dev)
1291 +{
1292 +       int i, j;
1293 +       int chan_no = 0;
1294 +       u8 *buffer;
1295 +       int byte_offset;
1296 +       unsigned long flag;
1297 +       struct dma_device_info *pDev;
1298 +       struct dma_channel_info *pCh;
1299 +       struct rx_desc *rx_desc_p;
1300 +       struct tx_desc *tx_desc_p;
1301 +
1302 +       for (i = 0; i < dev->max_tx_chan_num; i++) {
1303 +               pCh = dev->tx_chan[i];
1304 +               if (pCh->control == LQ_DMA_CH_ON) {
1305 +                       chan_no = (int)(pCh - dma_chan);
1306 +                       for (j = 0; j < pCh->desc_len; j++) {
1307 +                               tx_desc_p = (struct tx_desc *)pCh->desc_base + j;
1308 +                               memset(tx_desc_p, 0, sizeof(struct tx_desc));
1309 +                       }
1310 +                       local_irq_save(flag);
1311 +                       lq_w32(chan_no, LQ_DMA_CS);
1312 +                       /* check if the descriptor length is changed */
1313 +                       if (lq_r32(LQ_DMA_CDLEN) != pCh->desc_len)
1314 +                               lq_w32(pCh->desc_len, LQ_DMA_CDLEN);
1315 +
1316 +                       lq_w32(lq_r32(LQ_DMA_CCTRL) & ~1, LQ_DMA_CCTRL);
1317 +                       lq_w32(lq_r32(LQ_DMA_CCTRL) | 2, LQ_DMA_CCTRL);
1318 +                       while (lq_r32(LQ_DMA_CCTRL) & 2)
1319 +                               ;
1320 +                       lq_w32(lq_r32(LQ_DMA_IRNEN) | (1 << chan_no), LQ_DMA_IRNEN);
1321 +                       lq_w32(0x30100, LQ_DMA_CCTRL); /* reset and enable channel,enable channel later */
1322 +                       local_irq_restore(flag);
1323 +               }
1324 +       }
1325 +
1326 +       for (i = 0; i < dev->max_rx_chan_num; i++) {
1327 +               pCh = dev->rx_chan[i];
1328 +               if (pCh->control == LQ_DMA_CH_ON) {
1329 +                       chan_no = (int)(pCh - dma_chan);
1330 +
1331 +                       for (j = 0; j < pCh->desc_len; j++) {
1332 +                               rx_desc_p = (struct rx_desc *)pCh->desc_base + j;
1333 +                               pDev = (struct dma_device_info *)(pCh->dma_dev);
1334 +                               buffer = pDev->buffer_alloc(pCh->packet_size, &byte_offset, (void *)&(pCh->opt[j]));
1335 +                               if (!buffer)
1336 +                                       break;
1337 +
1338 +                               dma_cache_inv((unsigned long) buffer, pCh->packet_size);
1339 +
1340 +                               rx_desc_p->Data_Pointer = (u32)CPHYSADDR((u32)buffer);
1341 +                               rx_desc_p->status.word = 0;
1342 +                               rx_desc_p->status.field.byte_offset = byte_offset;
1343 +                               rx_desc_p->status.field.OWN = DMA_OWN;
1344 +                               rx_desc_p->status.field.data_length = pCh->packet_size;
1345 +                       }
1346 +
1347 +                       local_irq_save(flag);
1348 +                       lq_w32(chan_no, LQ_DMA_CS);
1349 +                       /* check if the descriptor length is changed */
1350 +                       if (lq_r32(LQ_DMA_CDLEN) != pCh->desc_len)
1351 +                               lq_w32(pCh->desc_len, LQ_DMA_CDLEN);
1352 +                       lq_w32(lq_r32(LQ_DMA_CCTRL) & ~1, LQ_DMA_CCTRL);
1353 +                       lq_w32(lq_r32(LQ_DMA_CCTRL) | 2, LQ_DMA_CCTRL);
1354 +                       while (lq_r32(LQ_DMA_CCTRL) & 2)
1355 +                               ;
1356 +                       lq_w32(0x0a, LQ_DMA_CIE); /* fix me, should enable all the interrupts here? */
1357 +                       lq_w32(lq_r32(LQ_DMA_IRNEN) | (1 << chan_no), LQ_DMA_IRNEN);
1358 +                       lq_w32(0x30000, LQ_DMA_CCTRL);
1359 +                       local_irq_restore(flag);
1360 +                       lq_enable_irq(dma_chan[chan_no].irq);
1361 +               }
1362 +       }
1363 +}
1364 +EXPORT_SYMBOL(dma_device_register);
1365 +
1366 +void dma_device_unregister(struct dma_device_info *dev)
1367 +{
1368 +       int i, j;
1369 +       int chan_no;
1370 +       struct dma_channel_info *pCh;
1371 +       struct rx_desc *rx_desc_p;
1372 +       struct tx_desc *tx_desc_p;
1373 +       unsigned long flag;
1374 +
1375 +       for (i = 0; i < dev->max_tx_chan_num; i++) {
1376 +               pCh = dev->tx_chan[i];
1377 +               if (pCh->control == LQ_DMA_CH_ON) {
1378 +                       chan_no = (int)(dev->tx_chan[i] - dma_chan);
1379 +                       local_irq_save(flag);
1380 +                       lq_w32(chan_no, LQ_DMA_CS);
1381 +                       pCh->curr_desc = 0;
1382 +                       pCh->prev_desc = 0;
1383 +                       pCh->control = LQ_DMA_CH_OFF;
1384 +                       lq_w32(0, LQ_DMA_CIE); /* fix me, should disable all the interrupts here? */
1385 +                       lq_w32(lq_r32(LQ_DMA_IRNEN) & ~(1 << chan_no), LQ_DMA_IRNEN); /* disable interrupts */
1386 +                       lq_w32(lq_r32(LQ_DMA_CCTRL) & ~1, LQ_DMA_CCTRL);
1387 +                       while (lq_r32(LQ_DMA_CCTRL) & 1)
1388 +                               ;
1389 +                       local_irq_restore(flag);
1390 +
1391 +                       for (j = 0; j < pCh->desc_len; j++) {
1392 +                               tx_desc_p = (struct tx_desc *)pCh->desc_base + j;
1393 +                               if ((tx_desc_p->status.field.OWN == CPU_OWN && tx_desc_p->status.field.C)
1394 +                                               || (tx_desc_p->status.field.OWN == DMA_OWN && tx_desc_p->status.field.data_length > 0)) {
1395 +                                       dev->buffer_free((u8 *) __va(tx_desc_p->Data_Pointer), (void *)pCh->opt[j]);
1396 +                               }
1397 +                               tx_desc_p->status.field.OWN = CPU_OWN;
1398 +                               memset(tx_desc_p, 0, sizeof(struct tx_desc));
1399 +                       }
1400 +                       /* TODO should free buffer that is not transferred by dma */
1401 +               }
1402 +       }
1403 +
1404 +       for (i = 0; i < dev->max_rx_chan_num; i++) {
1405 +               pCh = dev->rx_chan[i];
1406 +               chan_no = (int)(dev->rx_chan[i] - dma_chan);
1407 +               lq_disable_irq(pCh->irq);
1408 +
1409 +               local_irq_save(flag);
1410 +               g_lq_dma_int_status &= ~(1 << chan_no);
1411 +               pCh->curr_desc = 0;
1412 +               pCh->prev_desc = 0;
1413 +               pCh->control = LQ_DMA_CH_OFF;
1414 +
1415 +               lq_w32(chan_no, LQ_DMA_CS);
1416 +               lq_w32(0, LQ_DMA_CIE); /* fix me, should disable all the interrupts here? */
1417 +               lq_w32(lq_r32(LQ_DMA_IRNEN) & ~(1 << chan_no), LQ_DMA_IRNEN); /* disable interrupts */
1418 +               lq_w32(lq_r32(LQ_DMA_CCTRL) & ~1, LQ_DMA_CCTRL);
1419 +               while (lq_r32(LQ_DMA_CCTRL) & 1)
1420 +                       ;
1421 +
1422 +               local_irq_restore(flag);
1423 +               for (j = 0; j < pCh->desc_len; j++) {
1424 +                       rx_desc_p = (struct rx_desc *) pCh->desc_base + j;
1425 +                       if ((rx_desc_p->status.field.OWN == CPU_OWN
1426 +                            && rx_desc_p->status.field.C)
1427 +                           || (rx_desc_p->status.field.OWN == DMA_OWN
1428 +                               && rx_desc_p->status.field.data_length > 0)) {
1429 +                               dev->buffer_free((u8 *)
1430 +                                                __va(rx_desc_p->Data_Pointer),
1431 +                                                (void *) pCh->opt[j]);
1432 +                       }
1433 +               }
1434 +       }
1435 +}
1436 +EXPORT_SYMBOL(dma_device_unregister);
1437 +
1438 +int dma_device_read(struct dma_device_info *dma_dev, u8 **dataptr, void **opt)
1439 +{
1440 +       u8 *buf;
1441 +       int len;
1442 +       int byte_offset = 0;
1443 +       void *p = NULL;
1444 +       struct dma_channel_info *pCh = dma_dev->rx_chan[dma_dev->current_rx_chan];
1445 +       struct rx_desc *rx_desc_p;
1446 +
1447 +       /* get the rx data first */
1448 +       rx_desc_p = (struct rx_desc *) pCh->desc_base + pCh->curr_desc;
1449 +       if (!(rx_desc_p->status.field.OWN == CPU_OWN && rx_desc_p->status.field.C))
1450 +               return 0;
1451 +
1452 +       buf = (u8 *) __va(rx_desc_p->Data_Pointer);
1453 +       *(u32 *)dataptr = (u32)buf;
1454 +       len = rx_desc_p->status.field.data_length;
1455 +
1456 +       if (opt)
1457 +               *(int *)opt = (int)pCh->opt[pCh->curr_desc];
1458 +
1459 +       /* replace with a new allocated buffer */
1460 +       buf = dma_dev->buffer_alloc(pCh->packet_size, &byte_offset, &p);
1461 +
1462 +       if (buf) {
1463 +               dma_cache_inv((unsigned long) buf, pCh->packet_size);
1464 +               pCh->opt[pCh->curr_desc] = p;
1465 +               wmb();
1466 +
1467 +               rx_desc_p->Data_Pointer = (u32) CPHYSADDR((u32) buf);
1468 +               rx_desc_p->status.word = (DMA_OWN << 31) | ((byte_offset) << 23) | pCh->packet_size;
1469 +               wmb();
1470 +       } else {
1471 +               *(u32 *) dataptr = 0;
1472 +               if (opt)
1473 +                       *(int *) opt = 0;
1474 +               len = 0;
1475 +       }
1476 +
1477 +       /* increase the curr_desc pointer */
1478 +       pCh->curr_desc++;
1479 +       if (pCh->curr_desc == pCh->desc_len)
1480 +               pCh->curr_desc = 0;
1481 +
1482 +       return len;
1483 +}
1484 +EXPORT_SYMBOL(dma_device_read);
1485 +
1486 +int dma_device_write(struct dma_device_info *dma_dev, u8 *dataptr, int len, void *opt)
1487 +{
1488 +       unsigned long flag;
1489 +       u32 tmp, byte_offset;
1490 +       struct dma_channel_info *pCh;
1491 +       int chan_no;
1492 +       struct tx_desc *tx_desc_p;
1493 +       local_irq_save(flag);
1494 +
1495 +       pCh = dma_dev->tx_chan[dma_dev->current_tx_chan];
1496 +       chan_no = (int)(pCh - (struct dma_channel_info *) dma_chan);
1497 +
1498 +       tx_desc_p = (struct tx_desc *)pCh->desc_base + pCh->prev_desc;
1499 +       while (tx_desc_p->status.field.OWN == CPU_OWN && tx_desc_p->status.field.C) {
1500 +               dma_dev->buffer_free((u8 *) __va(tx_desc_p->Data_Pointer), pCh->opt[pCh->prev_desc]);
1501 +               memset(tx_desc_p, 0, sizeof(struct tx_desc));
1502 +               pCh->prev_desc = (pCh->prev_desc + 1) % (pCh->desc_len);
1503 +               tx_desc_p = (struct tx_desc *)pCh->desc_base + pCh->prev_desc;
1504 +       }
1505 +       tx_desc_p = (struct tx_desc *)pCh->desc_base + pCh->curr_desc;
1506 +       /* Check whether this descriptor is available */
1507 +       if (tx_desc_p->status.field.OWN == DMA_OWN || tx_desc_p->status.field.C) {
1508 +               /* if not, the tell the upper layer device */
1509 +               dma_dev->intr_handler (dma_dev, TX_BUF_FULL_INT);
1510 +               local_irq_restore(flag);
1511 +               printk(KERN_INFO "%s %d: failed to write!\n", __func__, __LINE__);
1512 +
1513 +               return 0;
1514 +       }
1515 +       pCh->opt[pCh->curr_desc] = opt;
1516 +       /* byte offset----to adjust the starting address of the data buffer, should be multiple of the burst length. */
1517 +       byte_offset = ((u32) CPHYSADDR((u32) dataptr)) % ((dma_dev->tx_burst_len) * 4);
1518 +       dma_cache_wback((unsigned long) dataptr, len);
1519 +       wmb();
1520 +       tx_desc_p->Data_Pointer = (u32) CPHYSADDR((u32) dataptr) - byte_offset;
1521 +       wmb();
1522 +       tx_desc_p->status.word = (DMA_OWN << 31) | DMA_DESC_SOP_SET | DMA_DESC_EOP_SET | ((byte_offset) << 23) | len;
1523 +       wmb();
1524 +
1525 +       pCh->curr_desc++;
1526 +       if (pCh->curr_desc == pCh->desc_len)
1527 +               pCh->curr_desc = 0;
1528 +
1529 +       /*Check whether this descriptor is available */
1530 +       tx_desc_p = (struct tx_desc *) pCh->desc_base + pCh->curr_desc;
1531 +       if (tx_desc_p->status.field.OWN == DMA_OWN) {
1532 +               /*if not , the tell the upper layer device */
1533 +               dma_dev->intr_handler (dma_dev, TX_BUF_FULL_INT);
1534 +       }
1535 +
1536 +       lq_w32(chan_no, LQ_DMA_CS);
1537 +       tmp = lq_r32(LQ_DMA_CCTRL);
1538 +
1539 +       if (!(tmp & 1))
1540 +               pCh->open(pCh);
1541 +
1542 +       local_irq_restore(flag);
1543 +
1544 +       return len;
1545 +}
1546 +EXPORT_SYMBOL(dma_device_write);
1547 +
1548 +int map_dma_chan(struct dma_chan_map *map)
1549 +{
1550 +       int i, j;
1551 +       int result;
1552 +
1553 +       for (i = 0; i < MAX_DMA_DEVICE_NUM; i++)
1554 +               strcpy(dma_devs[i].device_name, global_device_name[i]);
1555 +
1556 +       for (i = 0; i < MAX_DMA_CHANNEL_NUM; i++) {
1557 +               dma_chan[i].irq = map[i].irq;
1558 +               result = request_irq(dma_chan[i].irq, dma_interrupt, IRQF_DISABLED, map[i].dev_name, (void *)&dma_chan[i]);
1559 +               if (result) {
1560 +                       printk(KERN_WARNING "error, cannot get dma_irq!\n");
1561 +                       free_irq(dma_chan[i].irq, (void *) &dma_interrupt);
1562 +
1563 +                       return -EFAULT;
1564 +               }
1565 +       }
1566 +
1567 +       for (i = 0; i < MAX_DMA_DEVICE_NUM; i++) {
1568 +               dma_devs[i].num_tx_chan = 0;    /*set default tx channel number to be one */
1569 +               dma_devs[i].num_rx_chan = 0;    /*set default rx channel number to be one */
1570 +               dma_devs[i].max_rx_chan_num = 0;
1571 +               dma_devs[i].max_tx_chan_num = 0;
1572 +               dma_devs[i].buffer_alloc = &common_buffer_alloc;
1573 +               dma_devs[i].buffer_free = &common_buffer_free;
1574 +               dma_devs[i].intr_handler = NULL;
1575 +               dma_devs[i].tx_burst_len = 4;
1576 +               dma_devs[i].rx_burst_len = 4;
1577 +               if (i == 0) {
1578 +                       lq_w32(0, LQ_DMA_PS);
1579 +                       lq_w32(lq_r32(LQ_DMA_PCTRL) | ((0xf << 8) | (1 << 6)), LQ_DMA_PCTRL);   /*enable dma drop */
1580 +               }
1581 +
1582 +               if (i == 1) {
1583 +                       lq_w32(1, LQ_DMA_PS);
1584 +                       lq_w32(0x14, LQ_DMA_PCTRL);     /*deu port setting */
1585 +               }
1586 +
1587 +               for (j = 0; j < MAX_DMA_CHANNEL_NUM; j++) {
1588 +                       dma_chan[j].byte_offset = 0;
1589 +                       dma_chan[j].open = &open_chan;
1590 +                       dma_chan[j].close = &close_chan;
1591 +                       dma_chan[j].reset = &reset_chan;
1592 +                       dma_chan[j].enable_irq = &enable_ch_irq;
1593 +                       dma_chan[j].disable_irq = &disable_ch_irq;
1594 +                       dma_chan[j].rel_chan_no = map[j].rel_chan_no;
1595 +                       dma_chan[j].control = LQ_DMA_CH_OFF;
1596 +                       dma_chan[j].default_weight = LQ_DMA_CH_DEFAULT_WEIGHT;
1597 +                       dma_chan[j].weight = dma_chan[j].default_weight;
1598 +                       dma_chan[j].curr_desc = 0;
1599 +                       dma_chan[j].prev_desc = 0;
1600 +               }
1601 +
1602 +               for (j = 0; j < MAX_DMA_CHANNEL_NUM; j++) {
1603 +                       if (strcmp(dma_devs[i].device_name, map[j].dev_name) == 0) {
1604 +                               if (map[j].dir == LQ_DMA_RX) {
1605 +                                       dma_chan[j].dir = LQ_DMA_RX;
1606 +                                       dma_devs[i].max_rx_chan_num++;
1607 +                                       dma_devs[i].rx_chan[dma_devs[i].max_rx_chan_num - 1] = &dma_chan[j];
1608 +                                       dma_devs[i].rx_chan[dma_devs[i].max_rx_chan_num - 1]->pri = map[j].pri;
1609 +                                       dma_chan[j].dma_dev = (void *)&dma_devs[i];
1610 +                               } else if (map[j].dir == LQ_DMA_TX) {
1611 +                                       /*TX direction */
1612 +                                       dma_chan[j].dir = LQ_DMA_TX;
1613 +                                       dma_devs[i].max_tx_chan_num++;
1614 +                                       dma_devs[i].tx_chan[dma_devs[i].max_tx_chan_num - 1] = &dma_chan[j];
1615 +                                       dma_devs[i].tx_chan[dma_devs[i].max_tx_chan_num - 1]->pri = map[j].pri;
1616 +                                       dma_chan[j].dma_dev = (void *)&dma_devs[i];
1617 +                               } else {
1618 +                                       printk(KERN_WARNING "WRONG DMA MAP!\n");
1619 +                               }
1620 +                       }
1621 +               }
1622 +       }
1623 +
1624 +       return 0;
1625 +}
1626 +
1627 +void dma_chip_init(void)
1628 +{
1629 +       int i;
1630 +
1631 +       /* enable DMA from PMU */
1632 +       lq_pmu_enable(PMU_DMA);
1633 +
1634 +       /* reset DMA */
1635 +       lq_w32(lq_r32(LQ_DMA_CTRL) | 1, LQ_DMA_CTRL);
1636 +
1637 +       /* disable all interrupts */
1638 +       lq_w32(0, LQ_DMA_IRNEN);
1639 +
1640 +       for (i = 0; i < MAX_DMA_CHANNEL_NUM; i++) {
1641 +               lq_w32(i, LQ_DMA_CS);
1642 +               lq_w32(0x2, LQ_DMA_CCTRL);
1643 +               lq_w32(0x80000040, LQ_DMA_CPOLL);
1644 +               lq_w32(lq_r32(LQ_DMA_CCTRL) & ~0x1, LQ_DMA_CCTRL);
1645 +       }
1646 +}
1647 +
1648 +int lq_dma_init(void)
1649 +{
1650 +       int i;
1651 +
1652 +       dma_chip_init();
1653 +
1654 +       if (map_dma_chan(default_dma_map))
1655 +               BUG();
1656 +
1657 +       g_desc_list = (u64 *)KSEG1ADDR(__get_free_page(GFP_DMA));
1658 +
1659 +       if (g_desc_list == NULL) {
1660 +               printk(KERN_WARNING "no memory for desriptor\n");
1661 +               return -ENOMEM;
1662 +       }
1663 +
1664 +       memset(g_desc_list, 0, PAGE_SIZE);
1665 +
1666 +       for (i = 0; i < MAX_DMA_CHANNEL_NUM; i++) {
1667 +               dma_chan[i].desc_base = (u32)g_desc_list + i * LQ_DMA_DESCRIPTOR_OFFSET * 8;
1668 +               dma_chan[i].curr_desc = 0;
1669 +               dma_chan[i].desc_len = LQ_DMA_DESCRIPTOR_OFFSET;
1670 +
1671 +               lq_w32(i, LQ_DMA_CS);
1672 +               lq_w32((u32)CPHYSADDR(dma_chan[i].desc_base), LQ_DMA_CDBA);
1673 +               lq_w32(dma_chan[i].desc_len, LQ_DMA_CDLEN);
1674 +       }
1675 +       return 0;
1676 +}
1677 +
1678 +arch_initcall(lq_dma_init);
1679 +
1680 +void dma_cleanup(void)
1681 +{
1682 +       int i;
1683 +
1684 +       free_page(KSEG0ADDR((unsigned long) g_desc_list));
1685 +       for (i = 0; i < MAX_DMA_CHANNEL_NUM; i++)
1686 +               free_irq(dma_chan[i].irq, (void  *)&dma_interrupt);
1687 +}
1688 +
1689 +MODULE_LICENSE("GPL");
1690 --- /dev/null
1691 +++ b/arch/mips/lantiq/xway/pmu.c
1692 @@ -0,0 +1,36 @@
1693 +/*
1694 + *  This program is free software; you can redistribute it and/or modify it
1695 + *  under the terms of the GNU General Public License version 2 as published
1696 + *  by the Free Software Foundation.
1697 + *
1698 + *  Copyright (C) 2010 John Crispin <blogic@openwrt.org>
1699 + */
1700 +
1701 +#include <linux/kernel.h>
1702 +#include <linux/module.h>
1703 +#include <linux/version.h>
1704 +
1705 +#include <xway.h>
1706 +
1707 +#define LQ_PMU_PWDCR        ((u32 *)(LQ_PMU_BASE_ADDR + 0x001C))
1708 +#define LQ_PMU_PWDSR        ((u32 *)(LQ_PMU_BASE_ADDR + 0x0020))
1709 +
1710 +void
1711 +lq_pmu_enable(unsigned int module)
1712 +{
1713 +       int err = 1000000;
1714 +
1715 +       lq_w32(lq_r32(LQ_PMU_PWDCR) & ~module, LQ_PMU_PWDCR);
1716 +       while (--err && (lq_r32(LQ_PMU_PWDSR) & module));
1717 +
1718 +       if (!err)
1719 +               panic("activating PMU module failed!");
1720 +}
1721 +EXPORT_SYMBOL(lq_pmu_enable);
1722 +
1723 +void
1724 +lq_pmu_disable(unsigned int module)
1725 +{
1726 +       lq_w32(lq_r32(LQ_PMU_PWDCR) | module, LQ_PMU_PWDCR);
1727 +}
1728 +EXPORT_SYMBOL(lq_pmu_disable);
1729 --- /dev/null
1730 +++ b/arch/mips/lantiq/xway/timer.c
1731 @@ -0,0 +1,828 @@
1732 +#include <linux/kernel.h>
1733 +#include <linux/module.h>
1734 +#include <linux/version.h>
1735 +#include <linux/types.h>
1736 +#include <linux/fs.h>
1737 +#include <linux/miscdevice.h>
1738 +#include <linux/init.h>
1739 +#include <linux/uaccess.h>
1740 +#include <linux/unistd.h>
1741 +#include <linux/errno.h>
1742 +#include <linux/interrupt.h>
1743 +#include <linux/sched.h>
1744 +
1745 +#include <asm/irq.h>
1746 +#include <asm/div64.h>
1747 +
1748 +#include <xway.h>
1749 +#include <xway_irq.h>
1750 +#include <lantiq_timer.h>
1751 +
1752 +#define MAX_NUM_OF_32BIT_TIMER_BLOCKS  6
1753 +
1754 +#ifdef TIMER1A
1755 +#define FIRST_TIMER                    TIMER1A
1756 +#else
1757 +#define FIRST_TIMER                    2
1758 +#endif
1759 +
1760 +/*
1761 + *  GPTC divider is set or not.
1762 + */
1763 +#define GPTU_CLC_RMC_IS_SET            0
1764 +
1765 +/*
1766 + *  Timer Interrupt (IRQ)
1767 + */
1768 +/*  Must be adjusted when ICU driver is available */
1769 +#define TIMER_INTERRUPT                        (INT_NUM_IM3_IRL0 + 22)
1770 +
1771 +/*
1772 + *  Bits Operation
1773 + */
1774 +#define GET_BITS(x, msb, lsb)          \
1775 +       (((x) & ((1 << ((msb) + 1)) - 1)) >> (lsb))
1776 +#define SET_BITS(x, msb, lsb, value)   \
1777 +       (((x) & ~(((1 << ((msb) + 1)) - 1) ^ ((1 << (lsb)) - 1))) | \
1778 +       (((value) & ((1 << (1 + (msb) - (lsb))) - 1)) << (lsb)))
1779 +
1780 +/*
1781 + *  GPTU Register Mapping
1782 + */
1783 +#define LQ_GPTU                        (KSEG1 + 0x1E100A00)
1784 +#define LQ_GPTU_CLC            ((volatile u32 *)(LQ_GPTU + 0x0000))
1785 +#define LQ_GPTU_ID                     ((volatile u32 *)(LQ_GPTU + 0x0008))
1786 +#define LQ_GPTU_CON(n, X)              ((volatile u32 *)(LQ_GPTU + 0x0010 + ((X) * 4) + ((n) - 1) * 0x0020))   /* X must be either A or B */
1787 +#define LQ_GPTU_RUN(n, X)              ((volatile u32 *)(LQ_GPTU + 0x0018 + ((X) * 4) + ((n) - 1) * 0x0020))   /* X must be either A or B */
1788 +#define LQ_GPTU_RELOAD(n, X)   ((volatile u32 *)(LQ_GPTU + 0x0020 + ((X) * 4) + ((n) - 1) * 0x0020))   /* X must be either A or B */
1789 +#define LQ_GPTU_COUNT(n, X)    ((volatile u32 *)(LQ_GPTU + 0x0028 + ((X) * 4) + ((n) - 1) * 0x0020))   /* X must be either A or B */
1790 +#define LQ_GPTU_IRNEN          ((volatile u32 *)(LQ_GPTU + 0x00F4))
1791 +#define LQ_GPTU_IRNICR         ((volatile u32 *)(LQ_GPTU + 0x00F8))
1792 +#define LQ_GPTU_IRNCR          ((volatile u32 *)(LQ_GPTU + 0x00FC))
1793 +
1794 +/*
1795 + *  Clock Control Register
1796 + */
1797 +#define GPTU_CLC_SMC                   GET_BITS(*LQ_GPTU_CLC, 23, 16)
1798 +#define GPTU_CLC_RMC                   GET_BITS(*LQ_GPTU_CLC, 15, 8)
1799 +#define GPTU_CLC_FSOE                  (*LQ_GPTU_CLC & (1 << 5))
1800 +#define GPTU_CLC_EDIS                  (*LQ_GPTU_CLC & (1 << 3))
1801 +#define GPTU_CLC_SPEN                  (*LQ_GPTU_CLC & (1 << 2))
1802 +#define GPTU_CLC_DISS                  (*LQ_GPTU_CLC & (1 << 1))
1803 +#define GPTU_CLC_DISR                  (*LQ_GPTU_CLC & (1 << 0))
1804 +
1805 +#define GPTU_CLC_SMC_SET(value)                SET_BITS(0, 23, 16, (value))
1806 +#define GPTU_CLC_RMC_SET(value)                SET_BITS(0, 15, 8, (value))
1807 +#define GPTU_CLC_FSOE_SET(value)       ((value) ? (1 << 5) : 0)
1808 +#define GPTU_CLC_SBWE_SET(value)       ((value) ? (1 << 4) : 0)
1809 +#define GPTU_CLC_EDIS_SET(value)       ((value) ? (1 << 3) : 0)
1810 +#define GPTU_CLC_SPEN_SET(value)       ((value) ? (1 << 2) : 0)
1811 +#define GPTU_CLC_DISR_SET(value)       ((value) ? (1 << 0) : 0)
1812 +
1813 +/*
1814 + *  ID Register
1815 + */
1816 +#define GPTU_ID_ID                     GET_BITS(*LQ_GPTU_ID, 15, 8)
1817 +#define GPTU_ID_CFG                    GET_BITS(*LQ_GPTU_ID, 7, 5)
1818 +#define GPTU_ID_REV                    GET_BITS(*LQ_GPTU_ID, 4, 0)
1819 +
1820 +/*
1821 + *  Control Register of Timer/Counter nX
1822 + *    n is the index of block (1 based index)
1823 + *    X is either A or B
1824 + */
1825 +#define GPTU_CON_SRC_EG(n, X)          (*LQ_GPTU_CON(n, X) & (1 << 10))
1826 +#define GPTU_CON_SRC_EXT(n, X)         (*LQ_GPTU_CON(n, X) & (1 << 9))
1827 +#define GPTU_CON_SYNC(n, X)            (*LQ_GPTU_CON(n, X) & (1 << 8))
1828 +#define GPTU_CON_EDGE(n, X)            GET_BITS(*LQ_GPTU_CON(n, X), 7, 6)
1829 +#define GPTU_CON_INV(n, X)             (*LQ_GPTU_CON(n, X) & (1 << 5))
1830 +#define GPTU_CON_EXT(n, X)             (*LQ_GPTU_CON(n, A) & (1 << 4)) /* Timer/Counter B does not have this bit */
1831 +#define GPTU_CON_STP(n, X)             (*LQ_GPTU_CON(n, X) & (1 << 3))
1832 +#define GPTU_CON_CNT(n, X)             (*LQ_GPTU_CON(n, X) & (1 << 2))
1833 +#define GPTU_CON_DIR(n, X)             (*LQ_GPTU_CON(n, X) & (1 << 1))
1834 +#define GPTU_CON_EN(n, X)              (*LQ_GPTU_CON(n, X) & (1 << 0))
1835 +
1836 +#define GPTU_CON_SRC_EG_SET(value)     ((value) ? 0 : (1 << 10))
1837 +#define GPTU_CON_SRC_EXT_SET(value)    ((value) ? (1 << 9) : 0)
1838 +#define GPTU_CON_SYNC_SET(value)       ((value) ? (1 << 8) : 0)
1839 +#define GPTU_CON_EDGE_SET(value)       SET_BITS(0, 7, 6, (value))
1840 +#define GPTU_CON_INV_SET(value)                ((value) ? (1 << 5) : 0)
1841 +#define GPTU_CON_EXT_SET(value)                ((value) ? (1 << 4) : 0)
1842 +#define GPTU_CON_STP_SET(value)                ((value) ? (1 << 3) : 0)
1843 +#define GPTU_CON_CNT_SET(value)                ((value) ? (1 << 2) : 0)
1844 +#define GPTU_CON_DIR_SET(value)                ((value) ? (1 << 1) : 0)
1845 +
1846 +#define GPTU_RUN_RL_SET(value)         ((value) ? (1 << 2) : 0)
1847 +#define GPTU_RUN_CEN_SET(value)                ((value) ? (1 << 1) : 0)
1848 +#define GPTU_RUN_SEN_SET(value)                ((value) ? (1 << 0) : 0)
1849 +
1850 +#define GPTU_IRNEN_TC_SET(n, X, value) ((value) ? (1 << (((n) - 1) * 2 + (X))) : 0)
1851 +#define GPTU_IRNCR_TC_SET(n, X, value) ((value) ? (1 << (((n) - 1) * 2 + (X))) : 0)
1852 +
1853 +#define TIMER_FLAG_MASK_SIZE(x)                (x & 0x0001)
1854 +#define TIMER_FLAG_MASK_TYPE(x)                (x & 0x0002)
1855 +#define TIMER_FLAG_MASK_STOP(x)                (x & 0x0004)
1856 +#define TIMER_FLAG_MASK_DIR(x)         (x & 0x0008)
1857 +#define TIMER_FLAG_NONE_EDGE           0x0000
1858 +#define TIMER_FLAG_MASK_EDGE(x)                (x & 0x0030)
1859 +#define TIMER_FLAG_REAL                        0x0000
1860 +#define TIMER_FLAG_INVERT              0x0040
1861 +#define TIMER_FLAG_MASK_INVERT(x)      (x & 0x0040)
1862 +#define TIMER_FLAG_MASK_TRIGGER(x)     (x & 0x0070)
1863 +#define TIMER_FLAG_MASK_SYNC(x)                (x & 0x0080)
1864 +#define TIMER_FLAG_CALLBACK_IN_HB      0x0200
1865 +#define TIMER_FLAG_MASK_HANDLE(x)      (x & 0x0300)
1866 +#define TIMER_FLAG_MASK_SRC(x)         (x & 0x1000)
1867 +
1868 +struct timer_dev_timer {
1869 +       unsigned int f_irq_on;
1870 +       unsigned int irq;
1871 +       unsigned int flag;
1872 +       unsigned long arg1;
1873 +       unsigned long arg2;
1874 +};
1875 +
1876 +struct timer_dev {
1877 +       struct mutex gptu_mutex;
1878 +       unsigned int number_of_timers;
1879 +       unsigned int occupation;
1880 +       unsigned int f_gptu_on;
1881 +       struct timer_dev_timer timer[MAX_NUM_OF_32BIT_TIMER_BLOCKS * 2];
1882 +};
1883 +
1884 +static long gptu_ioctl(struct file *, unsigned int, unsigned long);
1885 +static int gptu_open(struct inode *, struct file *);
1886 +static int gptu_release(struct inode *, struct file *);
1887 +
1888 +static struct file_operations gptu_fops = {
1889 +       .owner = THIS_MODULE,
1890 +       .unlocked_ioctl = gptu_ioctl,
1891 +       .open = gptu_open,
1892 +       .release = gptu_release
1893 +};
1894 +
1895 +static struct miscdevice gptu_miscdev = {
1896 +       .minor = MISC_DYNAMIC_MINOR,
1897 +       .name = "gptu",
1898 +       .fops = &gptu_fops,
1899 +};
1900 +
1901 +static struct timer_dev timer_dev;
1902 +
1903 +static irqreturn_t timer_irq_handler(int irq, void *p)
1904 +{
1905 +       unsigned int timer;
1906 +       unsigned int flag;
1907 +       struct timer_dev_timer *dev_timer = (struct timer_dev_timer *)p;
1908 +
1909 +       timer = irq - TIMER_INTERRUPT;
1910 +       if (timer < timer_dev.number_of_timers
1911 +               && dev_timer == &timer_dev.timer[timer]) {
1912 +               /*  Clear interrupt.    */
1913 +               lq_w32(1 << timer, LQ_GPTU_IRNCR);
1914 +
1915 +               /*  Call user hanler or signal. */
1916 +               flag = dev_timer->flag;
1917 +               if (!(timer & 0x01)
1918 +                       || TIMER_FLAG_MASK_SIZE(flag) == TIMER_FLAG_16BIT) {
1919 +                       /* 16-bit timer or timer A of 32-bit timer  */
1920 +                       switch (TIMER_FLAG_MASK_HANDLE(flag)) {
1921 +                       case TIMER_FLAG_CALLBACK_IN_IRQ:
1922 +                       case TIMER_FLAG_CALLBACK_IN_HB:
1923 +                               if (dev_timer->arg1)
1924 +                                       (*(timer_callback)dev_timer->arg1)(dev_timer->arg2);
1925 +                               break;
1926 +                       case TIMER_FLAG_SIGNAL:
1927 +                               send_sig((int)dev_timer->arg2, (struct task_struct *)dev_timer->arg1, 0);
1928 +                               break;
1929 +                       }
1930 +               }
1931 +       }
1932 +       return IRQ_HANDLED;
1933 +}
1934 +
1935 +static inline void lq_enable_gptu(void)
1936 +{
1937 +       lq_pmu_enable(PMU_GPT);
1938 +
1939 +       /*  Set divider as 1, disable write protection for SPEN, enable module. */
1940 +       *LQ_GPTU_CLC =
1941 +               GPTU_CLC_SMC_SET(0x00) |
1942 +               GPTU_CLC_RMC_SET(0x01) |
1943 +               GPTU_CLC_FSOE_SET(0) |
1944 +               GPTU_CLC_SBWE_SET(1) |
1945 +               GPTU_CLC_EDIS_SET(0) |
1946 +               GPTU_CLC_SPEN_SET(0) |
1947 +               GPTU_CLC_DISR_SET(0);
1948 +}
1949 +
1950 +static inline void lq_disable_gptu(void)
1951 +{
1952 +       lq_w32(0x00, LQ_GPTU_IRNEN);
1953 +       lq_w32(0xfff, LQ_GPTU_IRNCR);
1954 +
1955 +       /*  Set divider as 0, enable write protection for SPEN, disable module. */
1956 +       *LQ_GPTU_CLC =
1957 +               GPTU_CLC_SMC_SET(0x00) |
1958 +               GPTU_CLC_RMC_SET(0x00) |
1959 +               GPTU_CLC_FSOE_SET(0) |
1960 +               GPTU_CLC_SBWE_SET(0) |
1961 +               GPTU_CLC_EDIS_SET(0) |
1962 +               GPTU_CLC_SPEN_SET(0) |
1963 +               GPTU_CLC_DISR_SET(1);
1964 +
1965 +       lq_pmu_disable(PMU_GPT);
1966 +}
1967 +
1968 +int lq_request_timer(unsigned int timer, unsigned int flag,
1969 +       unsigned long value, unsigned long arg1, unsigned long arg2)
1970 +{
1971 +       int ret = 0;
1972 +       unsigned int con_reg, irnen_reg;
1973 +       int n, X;
1974 +
1975 +       if (timer >= FIRST_TIMER + timer_dev.number_of_timers)
1976 +               return -EINVAL;
1977 +
1978 +       printk(KERN_INFO "request_timer(%d, 0x%08X, %lu)...",
1979 +               timer, flag, value);
1980 +
1981 +       if (TIMER_FLAG_MASK_SIZE(flag) == TIMER_FLAG_16BIT)
1982 +               value &= 0xFFFF;
1983 +       else
1984 +               timer &= ~0x01;
1985 +
1986 +       mutex_lock(&timer_dev.gptu_mutex);
1987 +
1988 +       /*
1989 +        *  Allocate timer.
1990 +        */
1991 +       if (timer < FIRST_TIMER) {
1992 +               unsigned int mask;
1993 +               unsigned int shift;
1994 +               /* This takes care of TIMER1B which is the only choice for Voice TAPI system */
1995 +               unsigned int offset = TIMER2A;
1996 +
1997 +               /*
1998 +                *  Pick up a free timer.
1999 +                */
2000 +               if (TIMER_FLAG_MASK_SIZE(flag) == TIMER_FLAG_16BIT) {
2001 +                       mask = 1 << offset;
2002 +                       shift = 1;
2003 +               } else {
2004 +                       mask = 3 << offset;
2005 +                       shift = 2;
2006 +               }
2007 +               for (timer = offset;
2008 +                    timer < offset + timer_dev.number_of_timers;
2009 +                    timer += shift, mask <<= shift)
2010 +                       if (!(timer_dev.occupation & mask)) {
2011 +                               timer_dev.occupation |= mask;
2012 +                               break;
2013 +                       }
2014 +               if (timer >= offset + timer_dev.number_of_timers) {
2015 +                       printk("failed![%d]\n", __LINE__);
2016 +                       mutex_unlock(&timer_dev.gptu_mutex);
2017 +                       return -EINVAL;
2018 +               } else
2019 +                       ret = timer;
2020 +       } else {
2021 +               register unsigned int mask;
2022 +
2023 +               /*
2024 +                *  Check if the requested timer is free.
2025 +                */
2026 +               mask = (TIMER_FLAG_MASK_SIZE(flag) == TIMER_FLAG_16BIT ? 1 : 3) << timer;
2027 +               if ((timer_dev.occupation & mask)) {
2028 +                       printk("failed![%d] mask %#x, timer_dev.occupation %#x\n",
2029 +                               __LINE__, mask, timer_dev.occupation);
2030 +                       mutex_unlock(&timer_dev.gptu_mutex);
2031 +                       return -EBUSY;
2032 +               } else {
2033 +                       timer_dev.occupation |= mask;
2034 +                       ret = 0;
2035 +               }
2036 +       }
2037 +
2038 +       /*
2039 +        *  Prepare control register value.
2040 +        */
2041 +       switch (TIMER_FLAG_MASK_EDGE(flag)) {
2042 +       default:
2043 +       case TIMER_FLAG_NONE_EDGE:
2044 +               con_reg = GPTU_CON_EDGE_SET(0x00);
2045 +               break;
2046 +       case TIMER_FLAG_RISE_EDGE:
2047 +               con_reg = GPTU_CON_EDGE_SET(0x01);
2048 +               break;
2049 +       case TIMER_FLAG_FALL_EDGE:
2050 +               con_reg = GPTU_CON_EDGE_SET(0x02);
2051 +               break;
2052 +       case TIMER_FLAG_ANY_EDGE:
2053 +               con_reg = GPTU_CON_EDGE_SET(0x03);
2054 +               break;
2055 +       }
2056 +       if (TIMER_FLAG_MASK_TYPE(flag) == TIMER_FLAG_TIMER)
2057 +               con_reg |=
2058 +                       TIMER_FLAG_MASK_SRC(flag) ==
2059 +                       TIMER_FLAG_EXT_SRC ? GPTU_CON_SRC_EXT_SET(1) :
2060 +                       GPTU_CON_SRC_EXT_SET(0);
2061 +       else
2062 +               con_reg |=
2063 +                       TIMER_FLAG_MASK_SRC(flag) ==
2064 +                       TIMER_FLAG_EXT_SRC ? GPTU_CON_SRC_EG_SET(1) :
2065 +                       GPTU_CON_SRC_EG_SET(0);
2066 +       con_reg |=
2067 +               TIMER_FLAG_MASK_SYNC(flag) ==
2068 +               TIMER_FLAG_UNSYNC ? GPTU_CON_SYNC_SET(0) :
2069 +               GPTU_CON_SYNC_SET(1);
2070 +       con_reg |=
2071 +               TIMER_FLAG_MASK_INVERT(flag) ==
2072 +               TIMER_FLAG_REAL ? GPTU_CON_INV_SET(0) : GPTU_CON_INV_SET(1);
2073 +       con_reg |=
2074 +               TIMER_FLAG_MASK_SIZE(flag) ==
2075 +               TIMER_FLAG_16BIT ? GPTU_CON_EXT_SET(0) :
2076 +               GPTU_CON_EXT_SET(1);
2077 +       con_reg |=
2078 +               TIMER_FLAG_MASK_STOP(flag) ==
2079 +               TIMER_FLAG_ONCE ? GPTU_CON_STP_SET(1) : GPTU_CON_STP_SET(0);
2080 +       con_reg |=
2081 +               TIMER_FLAG_MASK_TYPE(flag) ==
2082 +               TIMER_FLAG_TIMER ? GPTU_CON_CNT_SET(0) :
2083 +               GPTU_CON_CNT_SET(1);
2084 +       con_reg |=
2085 +               TIMER_FLAG_MASK_DIR(flag) ==
2086 +               TIMER_FLAG_UP ? GPTU_CON_DIR_SET(1) : GPTU_CON_DIR_SET(0);
2087 +
2088 +       /*
2089 +        *  Fill up running data.
2090 +        */
2091 +       timer_dev.timer[timer - FIRST_TIMER].flag = flag;
2092 +       timer_dev.timer[timer - FIRST_TIMER].arg1 = arg1;
2093 +       timer_dev.timer[timer - FIRST_TIMER].arg2 = arg2;
2094 +       if (TIMER_FLAG_MASK_SIZE(flag) != TIMER_FLAG_16BIT)
2095 +               timer_dev.timer[timer - FIRST_TIMER + 1].flag = flag;
2096 +
2097 +       /*
2098 +        *  Enable GPTU module.
2099 +        */
2100 +       if (!timer_dev.f_gptu_on) {
2101 +               lq_enable_gptu();
2102 +               timer_dev.f_gptu_on = 1;
2103 +       }
2104 +
2105 +       /*
2106 +        *  Enable IRQ.
2107 +        */
2108 +       if (TIMER_FLAG_MASK_HANDLE(flag) != TIMER_FLAG_NO_HANDLE) {
2109 +               if (TIMER_FLAG_MASK_HANDLE(flag) == TIMER_FLAG_SIGNAL)
2110 +                       timer_dev.timer[timer - FIRST_TIMER].arg1 =
2111 +                               (unsigned long) find_task_by_vpid((int) arg1);
2112 +
2113 +               irnen_reg = 1 << (timer - FIRST_TIMER);
2114 +
2115 +               if (TIMER_FLAG_MASK_HANDLE(flag) == TIMER_FLAG_SIGNAL
2116 +                   || (TIMER_FLAG_MASK_HANDLE(flag) ==
2117 +                       TIMER_FLAG_CALLBACK_IN_IRQ
2118 +                       && timer_dev.timer[timer - FIRST_TIMER].arg1)) {
2119 +                       enable_irq(timer_dev.timer[timer - FIRST_TIMER].irq);
2120 +                       timer_dev.timer[timer - FIRST_TIMER].f_irq_on = 1;
2121 +               }
2122 +       } else
2123 +               irnen_reg = 0;
2124 +
2125 +       /*
2126 +        *  Write config register, reload value and enable interrupt.
2127 +        */
2128 +       n = timer >> 1;
2129 +       X = timer & 0x01;
2130 +       *LQ_GPTU_CON(n, X) = con_reg;
2131 +       *LQ_GPTU_RELOAD(n, X) = value;
2132 +       /* printk("reload value = %d\n", (u32)value); */
2133 +       *LQ_GPTU_IRNEN |= irnen_reg;
2134 +
2135 +       mutex_unlock(&timer_dev.gptu_mutex);
2136 +       printk("successful!\n");
2137 +       return ret;
2138 +}
2139 +EXPORT_SYMBOL(lq_request_timer);
2140 +
2141 +int lq_free_timer(unsigned int timer)
2142 +{
2143 +       unsigned int flag;
2144 +       unsigned int mask;
2145 +       int n, X;
2146 +
2147 +       if (!timer_dev.f_gptu_on)
2148 +               return -EINVAL;
2149 +
2150 +       if (timer < FIRST_TIMER || timer >= FIRST_TIMER + timer_dev.number_of_timers)
2151 +               return -EINVAL;
2152 +
2153 +       mutex_lock(&timer_dev.gptu_mutex);
2154 +
2155 +       flag = timer_dev.timer[timer - FIRST_TIMER].flag;
2156 +       if (TIMER_FLAG_MASK_SIZE(flag) != TIMER_FLAG_16BIT)
2157 +               timer &= ~0x01;
2158 +
2159 +       mask = (TIMER_FLAG_MASK_SIZE(flag) == TIMER_FLAG_16BIT ? 1 : 3) << timer;
2160 +       if (((timer_dev.occupation & mask) ^ mask)) {
2161 +               mutex_unlock(&timer_dev.gptu_mutex);
2162 +               return -EINVAL;
2163 +       }
2164 +
2165 +       n = timer >> 1;
2166 +       X = timer & 0x01;
2167 +
2168 +       if (GPTU_CON_EN(n, X))
2169 +               *LQ_GPTU_RUN(n, X) = GPTU_RUN_CEN_SET(1);
2170 +
2171 +       *LQ_GPTU_IRNEN &= ~GPTU_IRNEN_TC_SET(n, X, 1);
2172 +       *LQ_GPTU_IRNCR |= GPTU_IRNCR_TC_SET(n, X, 1);
2173 +
2174 +       if (timer_dev.timer[timer - FIRST_TIMER].f_irq_on) {
2175 +               disable_irq(timer_dev.timer[timer - FIRST_TIMER].irq);
2176 +               timer_dev.timer[timer - FIRST_TIMER].f_irq_on = 0;
2177 +       }
2178 +
2179 +       timer_dev.occupation &= ~mask;
2180 +       if (!timer_dev.occupation && timer_dev.f_gptu_on) {
2181 +               lq_disable_gptu();
2182 +               timer_dev.f_gptu_on = 0;
2183 +       }
2184 +
2185 +       mutex_unlock(&timer_dev.gptu_mutex);
2186 +
2187 +       return 0;
2188 +}
2189 +EXPORT_SYMBOL(lq_free_timer);
2190 +
2191 +int lq_start_timer(unsigned int timer, int is_resume)
2192 +{
2193 +       unsigned int flag;
2194 +       unsigned int mask;
2195 +       int n, X;
2196 +
2197 +       if (!timer_dev.f_gptu_on)
2198 +               return -EINVAL;
2199 +
2200 +       if (timer < FIRST_TIMER || timer >= FIRST_TIMER + timer_dev.number_of_timers)
2201 +               return -EINVAL;
2202 +
2203 +       mutex_lock(&timer_dev.gptu_mutex);
2204 +
2205 +       flag = timer_dev.timer[timer - FIRST_TIMER].flag;
2206 +       if (TIMER_FLAG_MASK_SIZE(flag) != TIMER_FLAG_16BIT)
2207 +               timer &= ~0x01;
2208 +
2209 +       mask = (TIMER_FLAG_MASK_SIZE(flag) ==
2210 +       TIMER_FLAG_16BIT ? 1 : 3) << timer;
2211 +       if (((timer_dev.occupation & mask) ^ mask)) {
2212 +               mutex_unlock(&timer_dev.gptu_mutex);
2213 +               return -EINVAL;
2214 +       }
2215 +
2216 +       n = timer >> 1;
2217 +       X = timer & 0x01;
2218 +
2219 +       *LQ_GPTU_RUN(n, X) = GPTU_RUN_RL_SET(!is_resume) | GPTU_RUN_SEN_SET(1);
2220 +
2221 +       mutex_unlock(&timer_dev.gptu_mutex);
2222 +
2223 +       return 0;
2224 +}
2225 +EXPORT_SYMBOL(lq_start_timer);
2226 +
2227 +int lq_stop_timer(unsigned int timer)
2228 +{
2229 +       unsigned int flag;
2230 +       unsigned int mask;
2231 +       int n, X;
2232 +
2233 +       if (!timer_dev.f_gptu_on)
2234 +               return -EINVAL;
2235 +
2236 +       if (timer < FIRST_TIMER
2237 +           || timer >= FIRST_TIMER + timer_dev.number_of_timers)
2238 +               return -EINVAL;
2239 +
2240 +       mutex_lock(&timer_dev.gptu_mutex);
2241 +
2242 +       flag = timer_dev.timer[timer - FIRST_TIMER].flag;
2243 +       if (TIMER_FLAG_MASK_SIZE(flag) != TIMER_FLAG_16BIT)
2244 +               timer &= ~0x01;
2245 +
2246 +       mask = (TIMER_FLAG_MASK_SIZE(flag) == TIMER_FLAG_16BIT ? 1 : 3) << timer;
2247 +       if (((timer_dev.occupation & mask) ^ mask)) {
2248 +               mutex_unlock(&timer_dev.gptu_mutex);
2249 +               return -EINVAL;
2250 +       }
2251 +
2252 +       n = timer >> 1;
2253 +       X = timer & 0x01;
2254 +
2255 +       *LQ_GPTU_RUN(n, X) = GPTU_RUN_CEN_SET(1);
2256 +
2257 +       mutex_unlock(&timer_dev.gptu_mutex);
2258 +
2259 +       return 0;
2260 +}
2261 +EXPORT_SYMBOL(lq_stop_timer);
2262 +
2263 +int lq_reset_counter_flags(u32 timer, u32 flags)
2264 +{
2265 +       unsigned int oflag;
2266 +       unsigned int mask, con_reg;
2267 +       int n, X;
2268 +
2269 +       if (!timer_dev.f_gptu_on)
2270 +               return -EINVAL;
2271 +
2272 +       if (timer < FIRST_TIMER || timer >= FIRST_TIMER + timer_dev.number_of_timers)
2273 +               return -EINVAL;
2274 +
2275 +       mutex_lock(&timer_dev.gptu_mutex);
2276 +
2277 +       oflag = timer_dev.timer[timer - FIRST_TIMER].flag;
2278 +       if (TIMER_FLAG_MASK_SIZE(oflag) != TIMER_FLAG_16BIT)
2279 +               timer &= ~0x01;
2280 +
2281 +       mask = (TIMER_FLAG_MASK_SIZE(oflag) == TIMER_FLAG_16BIT ? 1 : 3) << timer;
2282 +       if (((timer_dev.occupation & mask) ^ mask)) {
2283 +               mutex_unlock(&timer_dev.gptu_mutex);
2284 +               return -EINVAL;
2285 +       }
2286 +
2287 +       switch (TIMER_FLAG_MASK_EDGE(flags)) {
2288 +       default:
2289 +       case TIMER_FLAG_NONE_EDGE:
2290 +               con_reg = GPTU_CON_EDGE_SET(0x00);
2291 +               break;
2292 +       case TIMER_FLAG_RISE_EDGE:
2293 +               con_reg = GPTU_CON_EDGE_SET(0x01);
2294 +               break;
2295 +       case TIMER_FLAG_FALL_EDGE:
2296 +               con_reg = GPTU_CON_EDGE_SET(0x02);
2297 +               break;
2298 +       case TIMER_FLAG_ANY_EDGE:
2299 +               con_reg = GPTU_CON_EDGE_SET(0x03);
2300 +               break;
2301 +       }
2302 +       if (TIMER_FLAG_MASK_TYPE(flags) == TIMER_FLAG_TIMER)
2303 +               con_reg |= TIMER_FLAG_MASK_SRC(flags) == TIMER_FLAG_EXT_SRC ? GPTU_CON_SRC_EXT_SET(1) : GPTU_CON_SRC_EXT_SET(0);
2304 +       else
2305 +               con_reg |= TIMER_FLAG_MASK_SRC(flags) == TIMER_FLAG_EXT_SRC ? GPTU_CON_SRC_EG_SET(1) : GPTU_CON_SRC_EG_SET(0);
2306 +       con_reg |= TIMER_FLAG_MASK_SYNC(flags) == TIMER_FLAG_UNSYNC ? GPTU_CON_SYNC_SET(0) : GPTU_CON_SYNC_SET(1);
2307 +       con_reg |= TIMER_FLAG_MASK_INVERT(flags) == TIMER_FLAG_REAL ? GPTU_CON_INV_SET(0) : GPTU_CON_INV_SET(1);
2308 +       con_reg |= TIMER_FLAG_MASK_SIZE(flags) == TIMER_FLAG_16BIT ? GPTU_CON_EXT_SET(0) : GPTU_CON_EXT_SET(1);
2309 +       con_reg |= TIMER_FLAG_MASK_STOP(flags) == TIMER_FLAG_ONCE ? GPTU_CON_STP_SET(1) : GPTU_CON_STP_SET(0);
2310 +       con_reg |= TIMER_FLAG_MASK_TYPE(flags) == TIMER_FLAG_TIMER ? GPTU_CON_CNT_SET(0) : GPTU_CON_CNT_SET(1);
2311 +       con_reg |= TIMER_FLAG_MASK_DIR(flags) == TIMER_FLAG_UP ? GPTU_CON_DIR_SET(1) : GPTU_CON_DIR_SET(0);
2312 +
2313 +       timer_dev.timer[timer - FIRST_TIMER].flag = flags;
2314 +       if (TIMER_FLAG_MASK_SIZE(flags) != TIMER_FLAG_16BIT)
2315 +               timer_dev.timer[timer - FIRST_TIMER + 1].flag = flags;
2316 +
2317 +       n = timer >> 1;
2318 +       X = timer & 0x01;
2319 +
2320 +       *LQ_GPTU_CON(n, X) = con_reg;
2321 +       smp_wmb();
2322 +       printk(KERN_INFO "[%s]: counter%d oflags %#x, nflags %#x, GPTU_CON %#x\n", __func__, timer, oflag, flags, *LQ_GPTU_CON(n, X));
2323 +       mutex_unlock(&timer_dev.gptu_mutex);
2324 +       return 0;
2325 +}
2326 +EXPORT_SYMBOL(lq_reset_counter_flags);
2327 +
2328 +int lq_get_count_value(unsigned int timer, unsigned long *value)
2329 +{
2330 +       unsigned int flag;
2331 +       unsigned int mask;
2332 +       int n, X;
2333 +
2334 +       if (!timer_dev.f_gptu_on)
2335 +               return -EINVAL;
2336 +
2337 +       if (timer < FIRST_TIMER
2338 +           || timer >= FIRST_TIMER + timer_dev.number_of_timers)
2339 +               return -EINVAL;
2340 +
2341 +       mutex_lock(&timer_dev.gptu_mutex);
2342 +
2343 +       flag = timer_dev.timer[timer - FIRST_TIMER].flag;
2344 +       if (TIMER_FLAG_MASK_SIZE(flag) != TIMER_FLAG_16BIT)
2345 +               timer &= ~0x01;
2346 +
2347 +       mask = (TIMER_FLAG_MASK_SIZE(flag) == TIMER_FLAG_16BIT ? 1 : 3) << timer;
2348 +       if (((timer_dev.occupation & mask) ^ mask)) {
2349 +               mutex_unlock(&timer_dev.gptu_mutex);
2350 +               return -EINVAL;
2351 +       }
2352 +
2353 +       n = timer >> 1;
2354 +       X = timer & 0x01;
2355 +
2356 +       *value = *LQ_GPTU_COUNT(n, X);
2357 +
2358 +       mutex_unlock(&timer_dev.gptu_mutex);
2359 +
2360 +       return 0;
2361 +}
2362 +EXPORT_SYMBOL(lq_get_count_value);
2363 +
2364 +u32 lq_cal_divider(unsigned long freq)
2365 +{
2366 +       u64 module_freq, fpi = lq_get_fpi_bus_clock(2);
2367 +       u32 clock_divider = 1;
2368 +       module_freq = fpi * 1000;
2369 +       do_div(module_freq, clock_divider * freq);
2370 +       return module_freq;
2371 +}
2372 +EXPORT_SYMBOL(lq_cal_divider);
2373 +
2374 +int lq_set_timer(unsigned int timer, unsigned int freq, int is_cyclic,
2375 +       int is_ext_src, unsigned int handle_flag, unsigned long arg1,
2376 +       unsigned long arg2)
2377 +{
2378 +       unsigned long divider;
2379 +       unsigned int flag;
2380 +
2381 +       divider = lq_cal_divider(freq);
2382 +       if (divider == 0)
2383 +               return -EINVAL;
2384 +       flag = ((divider & ~0xFFFF) ? TIMER_FLAG_32BIT : TIMER_FLAG_16BIT)
2385 +               | (is_cyclic ? TIMER_FLAG_CYCLIC : TIMER_FLAG_ONCE)
2386 +               | (is_ext_src ? TIMER_FLAG_EXT_SRC : TIMER_FLAG_INT_SRC)
2387 +               | TIMER_FLAG_TIMER | TIMER_FLAG_DOWN
2388 +               | TIMER_FLAG_MASK_HANDLE(handle_flag);
2389 +
2390 +       printk(KERN_INFO "lq_set_timer(%d, %d), divider = %lu\n",
2391 +               timer, freq, divider);
2392 +       return lq_request_timer(timer, flag, divider, arg1, arg2);
2393 +}
2394 +EXPORT_SYMBOL(lq_set_timer);
2395 +
2396 +int lq_set_counter(unsigned int timer, unsigned int flag, u32 reload,
2397 +       unsigned long arg1, unsigned long arg2)
2398 +{
2399 +       printk(KERN_INFO "lq_set_counter(%d, %#x, %d)\n", timer, flag, reload);
2400 +       return lq_request_timer(timer, flag, reload, arg1, arg2);
2401 +}
2402 +EXPORT_SYMBOL(lq_set_counter);
2403 +
2404 +static long gptu_ioctl(struct file *file, unsigned int cmd,
2405 +       unsigned long arg)
2406 +{
2407 +       int ret;
2408 +       struct gptu_ioctl_param param;
2409 +
2410 +       if (!access_ok(VERIFY_READ, arg, sizeof(struct gptu_ioctl_param)))
2411 +               return -EFAULT;
2412 +       copy_from_user(&param, (void *) arg, sizeof(param));
2413 +
2414 +       if ((((cmd == GPTU_REQUEST_TIMER || cmd == GPTU_SET_TIMER
2415 +              || GPTU_SET_COUNTER) && param.timer < 2)
2416 +            || cmd == GPTU_GET_COUNT_VALUE || cmd == GPTU_CALCULATE_DIVIDER)
2417 +           && !access_ok(VERIFY_WRITE, arg,
2418 +                          sizeof(struct gptu_ioctl_param)))
2419 +               return -EFAULT;
2420 +
2421 +       switch (cmd) {
2422 +       case GPTU_REQUEST_TIMER:
2423 +               ret = lq_request_timer(param.timer, param.flag, param.value,
2424 +                                    (unsigned long) param.pid,
2425 +                                    (unsigned long) param.sig);
2426 +               if (ret > 0) {
2427 +                       copy_to_user(&((struct gptu_ioctl_param *) arg)->
2428 +                                     timer, &ret, sizeof(&ret));
2429 +                       ret = 0;
2430 +               }
2431 +               break;
2432 +       case GPTU_FREE_TIMER:
2433 +               ret = lq_free_timer(param.timer);
2434 +               break;
2435 +       case GPTU_START_TIMER:
2436 +               ret = lq_start_timer(param.timer, param.flag);
2437 +               break;
2438 +       case GPTU_STOP_TIMER:
2439 +               ret = lq_stop_timer(param.timer);
2440 +               break;
2441 +       case GPTU_GET_COUNT_VALUE:
2442 +               ret = lq_get_count_value(param.timer, &param.value);
2443 +               if (!ret)
2444 +                       copy_to_user(&((struct gptu_ioctl_param *) arg)->
2445 +                                     value, &param.value,
2446 +                                     sizeof(param.value));
2447 +               break;
2448 +       case GPTU_CALCULATE_DIVIDER:
2449 +               param.value = lq_cal_divider(param.value);
2450 +               if (param.value == 0)
2451 +                       ret = -EINVAL;
2452 +               else {
2453 +                       copy_to_user(&((struct gptu_ioctl_param *) arg)->
2454 +                                     value, &param.value,
2455 +                                     sizeof(param.value));
2456 +                       ret = 0;
2457 +               }
2458 +               break;
2459 +       case GPTU_SET_TIMER:
2460 +               ret = lq_set_timer(param.timer, param.value,
2461 +                                TIMER_FLAG_MASK_STOP(param.flag) !=
2462 +                                TIMER_FLAG_ONCE ? 1 : 0,
2463 +                                TIMER_FLAG_MASK_SRC(param.flag) ==
2464 +                                TIMER_FLAG_EXT_SRC ? 1 : 0,
2465 +                                TIMER_FLAG_MASK_HANDLE(param.flag) ==
2466 +                                TIMER_FLAG_SIGNAL ? TIMER_FLAG_SIGNAL :
2467 +                                TIMER_FLAG_NO_HANDLE,
2468 +                                (unsigned long) param.pid,
2469 +                                (unsigned long) param.sig);
2470 +               if (ret > 0) {
2471 +                       copy_to_user(&((struct gptu_ioctl_param *) arg)->
2472 +                                     timer, &ret, sizeof(&ret));
2473 +                       ret = 0;
2474 +               }
2475 +               break;
2476 +       case GPTU_SET_COUNTER:
2477 +               lq_set_counter(param.timer, param.flag, param.value, 0, 0);
2478 +               if (ret > 0) {
2479 +                       copy_to_user(&((struct gptu_ioctl_param *) arg)->
2480 +                                     timer, &ret, sizeof(&ret));
2481 +                       ret = 0;
2482 +               }
2483 +               break;
2484 +       default:
2485 +               ret = -ENOTTY;
2486 +       }
2487 +
2488 +       return ret;
2489 +}
2490 +
2491 +static int gptu_open(struct inode *inode, struct file *file)
2492 +{
2493 +       return 0;
2494 +}
2495 +
2496 +static int gptu_release(struct inode *inode, struct file *file)
2497 +{
2498 +       return 0;
2499 +}
2500 +
2501 +int __init lq_gptu_init(void)
2502 +{
2503 +       int ret;
2504 +       unsigned int i;
2505 +
2506 +       lq_w32(0, LQ_GPTU_IRNEN);
2507 +       lq_w32(0xfff, LQ_GPTU_IRNCR);
2508 +
2509 +       memset(&timer_dev, 0, sizeof(timer_dev));
2510 +       mutex_init(&timer_dev.gptu_mutex);
2511 +
2512 +       lq_enable_gptu();
2513 +       timer_dev.number_of_timers = GPTU_ID_CFG * 2;
2514 +       lq_disable_gptu();
2515 +       if (timer_dev.number_of_timers > MAX_NUM_OF_32BIT_TIMER_BLOCKS * 2)
2516 +               timer_dev.number_of_timers = MAX_NUM_OF_32BIT_TIMER_BLOCKS * 2;
2517 +       printk(KERN_INFO "gptu: totally %d 16-bit timers/counters\n", timer_dev.number_of_timers);
2518 +
2519 +       ret = misc_register(&gptu_miscdev);
2520 +       if (ret) {
2521 +               printk(KERN_ERR "gptu: can't misc_register, get error %d\n", -ret);
2522 +               return ret;
2523 +       } else {
2524 +               printk(KERN_INFO "gptu: misc_register on minor %d\n", gptu_miscdev.minor);
2525 +       }
2526 +
2527 +       for (i = 0; i < timer_dev.number_of_timers; i++) {
2528 +               ret = request_irq(TIMER_INTERRUPT + i, timer_irq_handler, IRQF_TIMER, gptu_miscdev.name, &timer_dev.timer[i]);
2529 +               if (ret) {
2530 +                       for (; i >= 0; i--)
2531 +                               free_irq(TIMER_INTERRUPT + i, &timer_dev.timer[i]);
2532 +                       misc_deregister(&gptu_miscdev);
2533 +                       printk(KERN_ERR "gptu: failed in requesting irq (%d), get error %d\n", i, -ret);
2534 +                       return ret;
2535 +               } else {
2536 +                       timer_dev.timer[i].irq = TIMER_INTERRUPT + i;
2537 +                       disable_irq(timer_dev.timer[i].irq);
2538 +                       printk(KERN_INFO "gptu: succeeded to request irq %d\n", timer_dev.timer[i].irq);
2539 +               }
2540 +       }
2541 +
2542 +       return 0;
2543 +}
2544 +
2545 +void __exit lq_gptu_exit(void)
2546 +{
2547 +       unsigned int i;
2548 +
2549 +       for (i = 0; i < timer_dev.number_of_timers; i++) {
2550 +               if (timer_dev.timer[i].f_irq_on)
2551 +                       disable_irq(timer_dev.timer[i].irq);
2552 +               free_irq(timer_dev.timer[i].irq, &timer_dev.timer[i]);
2553 +       }
2554 +       lq_disable_gptu();
2555 +       misc_deregister(&gptu_miscdev);
2556 +}
2557 +
2558 +module_init(lq_gptu_init);
2559 +module_exit(lq_gptu_exit);
2560 --- /dev/null
2561 +++ b/arch/mips/lantiq/xway/timer.h
2562 @@ -0,0 +1,155 @@
2563 +#ifndef __DANUBE_GPTU_DEV_H__2005_07_26__10_19__
2564 +#define __DANUBE_GPTU_DEV_H__2005_07_26__10_19__
2565 +
2566 +
2567 +/******************************************************************************
2568 +       Copyright (c) 2002, Infineon Technologies.  All rights reserved.
2569 +
2570 +                               No Warranty
2571 +   Because the program is licensed free of charge, there is no warranty for
2572 +   the program, to the extent permitted by applicable law.  Except when
2573 +   otherwise stated in writing the copyright holders and/or other parties
2574 +   provide the program "as is" without warranty of any kind, either
2575 +   expressed or implied, including, but not limited to, the implied
2576 +   warranties of merchantability and fitness for a particular purpose. The
2577 +   entire risk as to the quality and performance of the program is with
2578 +   you.  should the program prove defective, you assume the cost of all
2579 +   necessary servicing, repair or correction.
2580 +
2581 +   In no event unless required by applicable law or agreed to in writing
2582 +   will any copyright holder, or any other party who may modify and/or
2583 +   redistribute the program as permitted above, be liable to you for
2584 +   damages, including any general, special, incidental or consequential
2585 +   damages arising out of the use or inability to use the program
2586 +   (including but not limited to loss of data or data being rendered
2587 +   inaccurate or losses sustained by you or third parties or a failure of
2588 +   the program to operate with any other programs), even if such holder or
2589 +   other party has been advised of the possibility of such damages.
2590 +******************************************************************************/
2591 +
2592 +
2593 +/*
2594 + * ####################################
2595 + *              Definition
2596 + * ####################################
2597 + */
2598 +
2599 +/*
2600 + *  Available Timer/Counter Index
2601 + */
2602 +#define TIMER(n, X)                     (n * 2 + (X ? 1 : 0))
2603 +#define TIMER_ANY                       0x00
2604 +#define TIMER1A                         TIMER(1, 0)
2605 +#define TIMER1B                         TIMER(1, 1)
2606 +#define TIMER2A                         TIMER(2, 0)
2607 +#define TIMER2B                         TIMER(2, 1)
2608 +#define TIMER3A                         TIMER(3, 0)
2609 +#define TIMER3B                         TIMER(3, 1)
2610 +
2611 +/*
2612 + *  Flag of Timer/Counter
2613 + *  These flags specify the way in which timer is configured.
2614 + */
2615 +/*  Bit size of timer/counter.                      */
2616 +#define TIMER_FLAG_16BIT                0x0000
2617 +#define TIMER_FLAG_32BIT                0x0001
2618 +/*  Switch between timer and counter.               */
2619 +#define TIMER_FLAG_TIMER                0x0000
2620 +#define TIMER_FLAG_COUNTER              0x0002
2621 +/*  Stop or continue when overflowing/underflowing. */
2622 +#define TIMER_FLAG_ONCE                 0x0000
2623 +#define TIMER_FLAG_CYCLIC               0x0004
2624 +/*  Count up or counter down.                       */
2625 +#define TIMER_FLAG_UP                   0x0000
2626 +#define TIMER_FLAG_DOWN                 0x0008
2627 +/*  Count on specific level or edge.                */
2628 +#define TIMER_FLAG_HIGH_LEVEL_SENSITIVE 0x0000
2629 +#define TIMER_FLAG_LOW_LEVEL_SENSITIVE  0x0040
2630 +#define TIMER_FLAG_RISE_EDGE            0x0010
2631 +#define TIMER_FLAG_FALL_EDGE            0x0020
2632 +#define TIMER_FLAG_ANY_EDGE             0x0030
2633 +/*  Signal is syncronous to module clock or not.    */
2634 +#define TIMER_FLAG_UNSYNC               0x0000
2635 +#define TIMER_FLAG_SYNC                 0x0080
2636 +/*  Different interrupt handle type.                */
2637 +#define TIMER_FLAG_NO_HANDLE            0x0000
2638 +#if defined(__KERNEL__)
2639 +    #define TIMER_FLAG_CALLBACK_IN_IRQ  0x0100
2640 +#endif  //  defined(__KERNEL__)
2641 +#define TIMER_FLAG_SIGNAL               0x0300
2642 +/*  Internal clock source or external clock source  */
2643 +#define TIMER_FLAG_INT_SRC              0x0000
2644 +#define TIMER_FLAG_EXT_SRC              0x1000
2645 +
2646 +
2647 +/*
2648 + *  ioctl Command
2649 + */
2650 +#define GPTU_REQUEST_TIMER              0x01    /*  General method to setup timer/counter.  */
2651 +#define GPTU_FREE_TIMER                 0x02    /*  Free timer/counter.                     */
2652 +#define GPTU_START_TIMER                0x03    /*  Start or resume timer/counter.          */
2653 +#define GPTU_STOP_TIMER                 0x04    /*  Suspend timer/counter.                  */
2654 +#define GPTU_GET_COUNT_VALUE            0x05    /*  Get current count value.                */
2655 +#define GPTU_CALCULATE_DIVIDER          0x06    /*  Calculate timer divider from given freq.*/
2656 +#define GPTU_SET_TIMER                  0x07    /*  Simplified method to setup timer.       */
2657 +#define GPTU_SET_COUNTER                0x08    /*  Simplified method to setup counter.     */
2658 +
2659 +/*
2660 + *  Data Type Used to Call ioctl
2661 + */
2662 +struct gptu_ioctl_param {
2663 +    unsigned int                        timer;  /*  In command GPTU_REQUEST_TIMER, GPTU_SET_TIMER, and  *
2664 +                                                 *  GPTU_SET_COUNTER, this field is ID of expected      *
2665 +                                                 *  timer/counter. If it's zero, a timer/counter would  *
2666 +                                                 *  be dynamically allocated and ID would be stored in  *
2667 +                                                 *  this field.                                         *
2668 +                                                 *  In command GPTU_GET_COUNT_VALUE, this field is      *
2669 +                                                 *  ignored.                                            *
2670 +                                                 *  In other command, this field is ID of timer/counter *
2671 +                                                 *  allocated.                                          */
2672 +    unsigned int                        flag;   /*  In command GPTU_REQUEST_TIMER, GPTU_SET_TIMER, and  *
2673 +                                                 *  GPTU_SET_COUNTER, this field contains flags to      *
2674 +                                                 *  specify how to configure timer/counter.             *
2675 +                                                 *  In command GPTU_START_TIMER, zero indicate start    *
2676 +                                                 *  and non-zero indicate resume timer/counter.         *
2677 +                                                 *  In other command, this field is ignored.            */
2678 +    unsigned long                       value;  /*  In command GPTU_REQUEST_TIMER, this field contains  *
2679 +                                                 *  init/reload value.                                  *
2680 +                                                 *  In command GPTU_SET_TIMER, this field contains      *
2681 +                                                 *  frequency (0.001Hz) of timer.                       *
2682 +                                                 *  In command GPTU_GET_COUNT_VALUE, current count      *
2683 +                                                 *  value would be stored in this field.                *
2684 +                                                 *  In command GPTU_CALCULATE_DIVIDER, this field       *
2685 +                                                 *  contains frequency wanted, and after calculation,   *
2686 +                                                 *  divider would be stored in this field to overwrite  *
2687 +                                                 *  the frequency.                                      *
2688 +                                                 *  In other command, this field is ignored.            */
2689 +    int                                 pid;    /*  In command GPTU_REQUEST_TIMER and GPTU_SET_TIMER,   *
2690 +                                                 *  if signal is required, this field contains process  *
2691 +                                                 *  ID to which signal would be sent.                   *
2692 +                                                 *  In other command, this field is ignored.            */
2693 +    int                                 sig;    /*  In command GPTU_REQUEST_TIMER and GPTU_SET_TIMER,   *
2694 +                                                 *  if signal is required, this field contains signal   *
2695 +                                                 *  number which would be sent.                         *
2696 +                                                 *  In other command, this field is ignored.            */
2697 +};
2698 +
2699 +/*
2700 + * ####################################
2701 + *              Data Type
2702 + * ####################################
2703 + */
2704 +typedef void (*timer_callback)(unsigned long arg);
2705 +
2706 +extern int ifxmips_request_timer(unsigned int, unsigned int, unsigned long, unsigned long, unsigned long);
2707 +extern int ifxmips_free_timer(unsigned int);
2708 +extern int ifxmips_start_timer(unsigned int, int);
2709 +extern int ifxmips_stop_timer(unsigned int);
2710 +extern int ifxmips_reset_counter_flags(u32 timer, u32 flags);
2711 +extern int ifxmips_get_count_value(unsigned int, unsigned long *);
2712 +extern u32 ifxmips_cal_divider(unsigned long);
2713 +extern int ifxmips_set_timer(unsigned int, unsigned int, int, int, unsigned int, unsigned long, unsigned long);
2714 +extern int ifxmips_set_counter(unsigned int timer, unsigned int flag,
2715 +       u32 reload, unsigned long arg1, unsigned long arg2);
2716 +
2717 +#endif /* __DANUBE_GPTU_DEV_H__2005_07_26__10_19__ */
2718 --- /dev/null
2719 +++ b/arch/mips/lantiq/xway/Makefile
2720 @@ -0,0 +1,5 @@
2721 +obj-y := pmu.o prom.o dma.o timer.o reset.o clk-xway.o
2722 +obj-y += gpio.o gpio_ebu.o gpio_leds.o devices.o
2723 +obj-$(CONFIG_LANTIQ_MACH_EASY50812) += mach-easy50812.o
2724 +obj-$(CONFIG_LANTIQ_MACH_EASY50712) += mach-easy50712.o
2725 +obj-$(CONFIG_LANTIQ_MACH_EASY4010) += mach-easy4010.o
2726 --- /dev/null
2727 +++ b/arch/mips/lantiq/xway/clk-xway.c
2728 @@ -0,0 +1,219 @@
2729 +/*
2730 + *  This program is free software; you can redistribute it and/or modify it
2731 + *  under the terms of the GNU General Public License version 2 as published
2732 + *  by the Free Software Foundation.
2733 + *
2734 + *  Copyright (C) 2007 Xu Liang, infineon
2735 + *  Copyright (C) 2010 John Crispin <blogic@openwrt.org>
2736 + */
2737 +
2738 +#include <linux/io.h>
2739 +#include <linux/module.h>
2740 +#include <linux/init.h>
2741 +#include <linux/clk.h>
2742 +
2743 +#include <asm/time.h>
2744 +#include <asm/irq.h>
2745 +#include <asm/div64.h>
2746 +
2747 +#include <xway.h>
2748 +
2749 +static unsigned int lq_ram_clocks[] = {CLOCK_167M, CLOCK_133M, CLOCK_111M, CLOCK_83M };
2750 +#define DDR_HZ lq_ram_clocks[lq_r32(LQ_CGU_SYS) & 0x3]
2751 +
2752 +#define BASIC_FREQUENCY_1      35328000
2753 +#define BASIC_FREQUENCY_2      36000000
2754 +#define BASIS_REQUENCY_USB     12000000
2755 +
2756 +#define GET_BITS(x, msb, lsb)           (((x) & ((1 << ((msb) + 1)) - 1)) >> (lsb))
2757 +
2758 +#define CGU_PLL0_PHASE_DIVIDER_ENABLE   (lq_r32(LQ_CGU_PLL0_CFG) & (1 << 31))
2759 +#define CGU_PLL0_BYPASS                 (lq_r32(LQ_CGU_PLL0_CFG) & (1 << 30))
2760 +#define CGU_PLL0_CFG_DSMSEL             (lq_r32(LQ_CGU_PLL0_CFG) & (1 << 28))
2761 +#define CGU_PLL0_CFG_FRAC_EN            (lq_r32(LQ_CGU_PLL0_CFG) & (1 << 27))
2762 +#define CGU_PLL1_SRC                    (lq_r32(LQ_CGU_PLL1_CFG) & (1 << 31))
2763 +#define CGU_PLL2_PHASE_DIVIDER_ENABLE   (lq_r32(LQ_CGU_PLL2_CFG) & (1 << 20))
2764 +#define CGU_SYS_FPI_SEL                 (1 << 6)
2765 +#define CGU_SYS_DDR_SEL                 0x3
2766 +#define CGU_PLL0_SRC                    (1 << 29)
2767 +
2768 +#define CGU_PLL0_CFG_PLLK               GET_BITS(*LQ_CGU_PLL0_CFG, 26, 17)
2769 +#define CGU_PLL0_CFG_PLLN               GET_BITS(*LQ_CGU_PLL0_CFG, 12, 6)
2770 +#define CGU_PLL0_CFG_PLLM               GET_BITS(*LQ_CGU_PLL0_CFG, 5, 2)
2771 +#define CGU_PLL2_SRC                    GET_BITS(*LQ_CGU_PLL2_CFG, 18, 17)
2772 +#define CGU_PLL2_CFG_INPUT_DIV          GET_BITS(*LQ_CGU_PLL2_CFG, 16, 13)
2773 +
2774 +#define LQ_GPTU_GPT_CLC                ((u32 *)(LQ_GPTU_BASE_ADDR + 0x0000))
2775 +#define LQ_CGU_PLL0_CFG                ((u32 *)(LQ_CGU_BASE_ADDR + 0x0004))
2776 +#define LQ_CGU_PLL1_CFG                ((u32 *)(LQ_CGU_BASE_ADDR + 0x0008))
2777 +#define LQ_CGU_PLL2_CFG                ((u32 *)(LQ_CGU_BASE_ADDR + 0x000C))
2778 +#define LQ_CGU_SYS                     ((u32 *)(LQ_CGU_BASE_ADDR + 0x0010))
2779 +#define LQ_CGU_UPDATE          ((u32 *)(LQ_CGU_BASE_ADDR + 0x0014))
2780 +#define LQ_CGU_IF_CLK          ((u32 *)(LQ_CGU_BASE_ADDR + 0x0018))
2781 +#define LQ_CGU_OSC_CON         ((u32 *)(LQ_CGU_BASE_ADDR + 0x001C))
2782 +#define LQ_CGU_SMD                     ((u32 *)(LQ_CGU_BASE_ADDR + 0x0020))
2783 +#define LQ_CGU_CT1SR           ((u32 *)(LQ_CGU_BASE_ADDR + 0x0028))
2784 +#define LQ_CGU_CT2SR           ((u32 *)(LQ_CGU_BASE_ADDR + 0x002C))
2785 +#define LQ_CGU_PCMCR           ((u32 *)(LQ_CGU_BASE_ADDR + 0x0030))
2786 +#define LQ_CGU_PCI_CR          ((u32 *)(LQ_CGU_BASE_ADDR + 0x0034))
2787 +#define LQ_CGU_PD_PC           ((u32 *)(LQ_CGU_BASE_ADDR + 0x0038))
2788 +#define LQ_CGU_FMR                     ((u32 *)(LQ_CGU_BASE_ADDR + 0x003C))
2789 +
2790 +static unsigned int lq_get_pll0_fdiv(void);
2791 +
2792 +static inline unsigned int
2793 +get_input_clock(int pll)
2794 +{
2795 +       switch (pll) {
2796 +       case 0:
2797 +               if (lq_r32(LQ_CGU_PLL0_CFG) & CGU_PLL0_SRC)
2798 +                       return BASIS_REQUENCY_USB;
2799 +               else if (CGU_PLL0_PHASE_DIVIDER_ENABLE)
2800 +                       return BASIC_FREQUENCY_1;
2801 +               else
2802 +                       return BASIC_FREQUENCY_2;
2803 +       case 1:
2804 +               if (CGU_PLL1_SRC)
2805 +                       return BASIS_REQUENCY_USB;
2806 +               else if (CGU_PLL0_PHASE_DIVIDER_ENABLE)
2807 +                       return BASIC_FREQUENCY_1;
2808 +               else
2809 +                       return BASIC_FREQUENCY_2;
2810 +       case 2:
2811 +               switch (CGU_PLL2_SRC) {
2812 +               case 0:
2813 +                       return lq_get_pll0_fdiv();
2814 +               case 1:
2815 +                       return CGU_PLL2_PHASE_DIVIDER_ENABLE ?
2816 +                               BASIC_FREQUENCY_1 :
2817 +                               BASIC_FREQUENCY_2;
2818 +               case 2:
2819 +                       return BASIS_REQUENCY_USB;
2820 +               }
2821 +       default:
2822 +               return 0;
2823 +       }
2824 +}
2825 +
2826 +static inline unsigned int
2827 +cal_dsm(int pll, unsigned int num, unsigned int den)
2828 +{
2829 +       u64 res, clock = get_input_clock(pll);
2830 +       res = num * clock;
2831 +       do_div(res, den);
2832 +       return res;
2833 +}
2834 +
2835 +static inline unsigned int
2836 +mash_dsm(int pll, unsigned int M, unsigned int N, unsigned int K)
2837 +{
2838 +       unsigned int num = ((N + 1) << 10) + K;
2839 +       unsigned int den = (M + 1) << 10;
2840 +       return cal_dsm(pll, num, den);
2841 +}
2842 +
2843 +static inline unsigned int
2844 +ssff_dsm_1(int pll, unsigned int M, unsigned int N,    unsigned int K)
2845 +{
2846 +       unsigned int num = ((N + 1) << 11) + K + 512;
2847 +       unsigned int den = (M + 1) << 11;
2848 +       return cal_dsm(pll, num, den);
2849 +}
2850 +
2851 +static inline unsigned int
2852 +ssff_dsm_2(int pll, unsigned int M, unsigned int N, unsigned int K)
2853 +{
2854 +       unsigned int num = K >= 512 ?
2855 +               ((N + 1) << 12) + K - 512 : ((N + 1) << 12) + K + 3584;
2856 +       unsigned int den = (M + 1) << 12;
2857 +       return cal_dsm(pll, num, den);
2858 +}
2859 +
2860 +static inline unsigned int
2861 +dsm(int pll, unsigned int M, unsigned int N, unsigned int K,
2862 +       unsigned int dsmsel, unsigned int phase_div_en)
2863 +{
2864 +       if (!dsmsel)
2865 +               return mash_dsm(pll, M, N, K);
2866 +       else if (!phase_div_en)
2867 +               return mash_dsm(pll, M, N, K);
2868 +       else
2869 +               return ssff_dsm_2(pll, M, N, K);
2870 +}
2871 +
2872 +static inline unsigned int
2873 +lq_get_pll0_fosc(void)
2874 +{
2875 +       if (CGU_PLL0_BYPASS)
2876 +               return get_input_clock(0);
2877 +       else
2878 +               return !CGU_PLL0_CFG_FRAC_EN
2879 +                       ? dsm(0, CGU_PLL0_CFG_PLLM, CGU_PLL0_CFG_PLLN, 0, CGU_PLL0_CFG_DSMSEL,
2880 +                               CGU_PLL0_PHASE_DIVIDER_ENABLE)
2881 +                       : dsm(0, CGU_PLL0_CFG_PLLM, CGU_PLL0_CFG_PLLN, CGU_PLL0_CFG_PLLK,
2882 +                               CGU_PLL0_CFG_DSMSEL, CGU_PLL0_PHASE_DIVIDER_ENABLE);
2883 +}
2884 +
2885 +static unsigned int
2886 +lq_get_pll0_fdiv(void)
2887 +{
2888 +       unsigned int div = CGU_PLL2_CFG_INPUT_DIV + 1;
2889 +       return (lq_get_pll0_fosc() + (div >> 1)) / div;
2890 +}
2891 +
2892 +unsigned int
2893 +lq_get_io_region_clock(void)
2894 +{
2895 +       unsigned int ret = lq_get_pll0_fosc();
2896 +       switch (lq_r32(LQ_CGU_PLL2_CFG) & CGU_SYS_DDR_SEL) {
2897 +       default:
2898 +       case 0:
2899 +               return (ret + 1) / 2;
2900 +       case 1:
2901 +               return (ret * 2 + 2) / 5;
2902 +       case 2:
2903 +               return (ret + 1) / 3;
2904 +       case 3:
2905 +               return (ret + 2) / 4;
2906 +       }
2907 +}
2908 +EXPORT_SYMBOL(lq_get_io_region_clock);
2909 +
2910 +unsigned int
2911 +lq_get_fpi_bus_clock(int fpi)
2912 +{
2913 +       unsigned int ret = lq_get_io_region_clock();
2914 +       if ((fpi == 2) && (lq_r32(LQ_CGU_SYS) & CGU_SYS_FPI_SEL))
2915 +               ret >>= 1;
2916 +       return ret;
2917 +}
2918 +EXPORT_SYMBOL(lq_get_fpi_bus_clock);
2919 +
2920 +unsigned int
2921 +lq_get_cpu_hz(void)
2922 +{
2923 +       switch (lq_r32(LQ_CGU_SYS) & 0xc)
2924 +       {
2925 +       case 0:
2926 +               return CLOCK_333M;
2927 +       case 4:
2928 +               return DDR_HZ;
2929 +       case 8:
2930 +               return DDR_HZ << 1;
2931 +       default:
2932 +               return DDR_HZ >> 1;
2933 +       }
2934 +}
2935 +EXPORT_SYMBOL(lq_get_cpu_hz);
2936 +
2937 +unsigned int
2938 +lq_get_fpi_hz(void)
2939 +{
2940 +       unsigned int ddr_clock = DDR_HZ;
2941 +       if (lq_r32(LQ_CGU_SYS) & 0x40)
2942 +               return ddr_clock >> 1;
2943 +       return ddr_clock;
2944 +}
2945 +EXPORT_SYMBOL(lq_get_fpi_hz);
2946 +
2947 +
2948 --- /dev/null
2949 +++ b/arch/mips/lantiq/xway/gpio.c
2950 @@ -0,0 +1,206 @@
2951 +/*
2952 + *  This program is free software; you can redistribute it and/or modify it
2953 + *  under the terms of the GNU General Public License version 2 as published
2954 + *  by the Free Software Foundation.
2955 + *
2956 + *  Copyright (C) 2010 John Crispin <blogic@openwrt.org>
2957 + */
2958 +
2959 +#include <linux/slab.h>
2960 +#include <linux/module.h>
2961 +#include <linux/platform_device.h>
2962 +#include <linux/gpio.h>
2963 +
2964 +#include <lantiq.h>
2965 +
2966 +#define LQ_GPIO0_BASE_ADDR     0x1E100B10
2967 +#define LQ_GPIO1_BASE_ADDR     0x1E100B40
2968 +#define LQ_GPIO_SIZE           0x30
2969 +
2970 +#define LQ_GPIO_OUT                    0x00
2971 +#define LQ_GPIO_IN                     0x04
2972 +#define LQ_GPIO_DIR                    0x08
2973 +#define LQ_GPIO_ALTSEL0                0x0C
2974 +#define LQ_GPIO_ALTSEL1                0x10
2975 +#define LQ_GPIO_OD                     0x14
2976 +
2977 +#define PINS_PER_PORT          16
2978 +
2979 +#define lq_gpio_getbit(m, r, p)                !!(lq_r32(m + r) & (1 << p))
2980 +#define lq_gpio_setbit(m, r, p)                lq_w32_mask(0, (1 << p), m + r)
2981 +#define lq_gpio_clearbit(m, r, p)      lq_w32_mask((1 << p), 0, m + r)
2982 +
2983 +struct lq_gpio
2984 +{
2985 +       void __iomem *membase;
2986 +       struct gpio_chip chip;
2987 +};
2988 +
2989 +int
2990 +gpio_to_irq(unsigned int gpio)
2991 +{
2992 +       return -EINVAL;
2993 +}
2994 +EXPORT_SYMBOL(gpio_to_irq);
2995 +
2996 +int
2997 +lq_gpio_setconfig(unsigned int pin, unsigned int reg, unsigned int val)
2998 +{
2999 +       void __iomem *membase = (void*)KSEG1ADDR(LQ_GPIO0_BASE_ADDR);
3000 +       if(pin >= (2 * PINS_PER_PORT))
3001 +               return -EINVAL;
3002 +       if(pin >= PINS_PER_PORT)
3003 +       {
3004 +               pin -= PINS_PER_PORT;
3005 +               membase += LQ_GPIO_SIZE;
3006 +       }
3007 +       if(val)
3008 +               lq_w32_mask(0, (1 << pin), membase + reg);
3009 +       else
3010 +               lq_w32_mask((1 << pin), 0, membase + reg);
3011 +       return 0;
3012 +}
3013 +EXPORT_SYMBOL(lq_gpio_setconfig);
3014 +
3015 +int
3016 +lq_gpio_request(unsigned int pin, unsigned int alt0,
3017 +       unsigned int alt1, unsigned int dir, const char *name)
3018 +{
3019 +       void __iomem *membase = (void*)KSEG1ADDR(LQ_GPIO0_BASE_ADDR);
3020 +       if(pin >= (2 * PINS_PER_PORT))
3021 +               return -EINVAL;
3022 +       if(gpio_request(pin, name))
3023 +       {
3024 +               printk("failed to register %s gpio\n", name);
3025 +               return -EBUSY;
3026 +       }
3027 +       if(dir)
3028 +               gpio_direction_output(pin, 1);
3029 +       else
3030 +               gpio_direction_input(pin);
3031 +       if(pin >= PINS_PER_PORT)
3032 +       {
3033 +               pin -= PINS_PER_PORT;
3034 +               membase += LQ_GPIO_SIZE;
3035 +       }
3036 +       if(alt0)
3037 +               lq_gpio_setbit(membase, LQ_GPIO_ALTSEL0, pin);
3038 +       else
3039 +               lq_gpio_clearbit(membase, LQ_GPIO_ALTSEL0, pin);
3040 +       if(alt1)
3041 +               lq_gpio_setbit(membase, LQ_GPIO_ALTSEL1, pin);
3042 +       else
3043 +               lq_gpio_clearbit(membase, LQ_GPIO_ALTSEL1, pin);
3044 +       return 0;
3045 +}
3046 +EXPORT_SYMBOL(lq_gpio_request);
3047 +
3048 +static void
3049 +lq_gpio_set(struct gpio_chip *chip, unsigned int offset, int value)
3050 +{
3051 +       struct lq_gpio *lq_gpio = container_of(chip, struct lq_gpio, chip);
3052 +       if(value)
3053 +               lq_gpio_setbit(lq_gpio->membase, LQ_GPIO_OUT, offset);
3054 +       else
3055 +               lq_gpio_clearbit(lq_gpio->membase, LQ_GPIO_OUT, offset);
3056 +}
3057 +
3058 +static int
3059 +lq_gpio_get(struct gpio_chip *chip, unsigned int offset)
3060 +{
3061 +       struct lq_gpio *lq_gpio = container_of(chip, struct lq_gpio, chip);
3062 +       return lq_gpio_getbit(lq_gpio->membase, LQ_GPIO_IN, offset);
3063 +}
3064 +
3065 +static int
3066 +lq_gpio_direction_input(struct gpio_chip *chip, unsigned int offset)
3067 +{
3068 +       struct lq_gpio *lq_gpio = container_of(chip, struct lq_gpio, chip);
3069 +       lq_gpio_clearbit(lq_gpio->membase, LQ_GPIO_OD, offset);
3070 +       lq_gpio_clearbit(lq_gpio->membase, LQ_GPIO_DIR, offset);
3071 +       return 0;
3072 +}
3073 +
3074 +static int
3075 +lq_gpio_direction_output(struct gpio_chip *chip, unsigned int offset, int value)
3076 +{
3077 +       struct lq_gpio *lq_gpio = container_of(chip, struct lq_gpio, chip);
3078 +       lq_gpio_setbit(lq_gpio->membase, LQ_GPIO_OD, offset);
3079 +       lq_gpio_setbit(lq_gpio->membase, LQ_GPIO_DIR, offset);
3080 +       lq_gpio_set(chip, offset, value);
3081 +       return 0;
3082 +}
3083 +
3084 +static int
3085 +lq_gpio_req(struct gpio_chip *chip, unsigned offset)
3086 +{
3087 +       struct lq_gpio *lq_gpio = container_of(chip, struct lq_gpio, chip);
3088 +       lq_gpio_clearbit(lq_gpio->membase, LQ_GPIO_ALTSEL0, offset);
3089 +       lq_gpio_clearbit(lq_gpio->membase, LQ_GPIO_ALTSEL1, offset);
3090 +       return 0;
3091 +}
3092 +
3093 +static int
3094 +lq_gpio_probe(struct platform_device *pdev)
3095 +{
3096 +       struct lq_gpio *lq_gpio = kzalloc(sizeof(struct lq_gpio), GFP_KERNEL);
3097 +       struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
3098 +       int ret = 0;
3099 +       if(!res)
3100 +       {
3101 +               ret = -ENOENT;
3102 +               goto err_free;
3103 +       }
3104 +       res = request_mem_region(res->start, resource_size(res),
3105 +               dev_name(&pdev->dev));
3106 +       if(!res)
3107 +       {
3108 +               ret = -EBUSY;
3109 +               goto err_free;
3110 +       }
3111 +       lq_gpio->membase = ioremap_nocache(res->start, resource_size(res));
3112 +       if(!lq_gpio->membase)
3113 +       {
3114 +               ret = -ENOMEM;
3115 +               goto err_release_mem_region;
3116 +       }
3117 +       lq_gpio->chip.label = "lq_gpio";
3118 +       lq_gpio->chip.direction_input = lq_gpio_direction_input;
3119 +       lq_gpio->chip.direction_output = lq_gpio_direction_output;
3120 +       lq_gpio->chip.get = lq_gpio_get;
3121 +       lq_gpio->chip.set = lq_gpio_set;
3122 +       lq_gpio->chip.request = lq_gpio_req;
3123 +       lq_gpio->chip.base = PINS_PER_PORT * pdev->id;
3124 +       lq_gpio->chip.ngpio = PINS_PER_PORT;
3125 +       platform_set_drvdata(pdev, lq_gpio);
3126 +       ret = gpiochip_add(&lq_gpio->chip);
3127 +       if(!ret)
3128 +               return 0;
3129 +
3130 +       iounmap(lq_gpio->membase);
3131 +err_release_mem_region:
3132 +       release_mem_region(res->start, resource_size(res));
3133 +err_free:
3134 +    kfree(lq_gpio);
3135 +       return ret;
3136 +}
3137 +
3138 +static struct platform_driver
3139 +lq_gpio_driver = {
3140 +       .probe = lq_gpio_probe,
3141 +       .driver = {
3142 +               .name = "lq_gpio",
3143 +               .owner = THIS_MODULE,
3144 +       },
3145 +};
3146 +
3147 +int __init
3148 +lq_gpio_init(void)
3149 +{
3150 +       int ret = platform_driver_register(&lq_gpio_driver);
3151 +       if(ret)
3152 +               printk(KERN_INFO "lq_gpio : Error registering platfom driver!");
3153 +       return ret;
3154 +}
3155 +
3156 +postcore_initcall(lq_gpio_init);
3157 --- /dev/null
3158 +++ b/arch/mips/lantiq/xway/reset.c
3159 @@ -0,0 +1,53 @@
3160 +/*
3161 + *  This program is free software; you can redistribute it and/or modify it
3162 + *  under the terms of the GNU General Public License version 2 as published
3163 + *  by the Free Software Foundation.
3164 + *
3165 + *  Copyright (C) 2010 John Crispin <blogic@openwrt.org>
3166 + */
3167 +
3168 +#include <linux/init.h>
3169 +#include <linux/io.h>
3170 +#include <linux/pm.h>
3171 +#include <asm/reboot.h>
3172 +
3173 +#include <xway.h>
3174 +
3175 +#define LQ_RCU_RST                     ((u32 *)(LQ_RCU_BASE_ADDR + 0x0010))
3176 +#define LQ_RCU_RST_ALL         0x40000000
3177 +
3178 +static void
3179 +lq_machine_restart(char *command)
3180 +{
3181 +       printk(KERN_NOTICE "System restart\n");
3182 +       local_irq_disable();
3183 +       lq_w32(lq_r32(LQ_RCU_RST) | LQ_RCU_RST_ALL,     LQ_RCU_RST);
3184 +       for(;;);
3185 +}
3186 +
3187 +static void
3188 +lq_machine_halt(void)
3189 +{
3190 +       printk(KERN_NOTICE "System halted.\n");
3191 +       local_irq_disable();
3192 +       for(;;);
3193 +}
3194 +
3195 +static void
3196 +lq_machine_power_off(void)
3197 +{
3198 +       printk(KERN_NOTICE "Please turn off the power now.\n");
3199 +       local_irq_disable();
3200 +       for(;;);
3201 +}
3202 +
3203 +static int __init
3204 +mips_reboot_setup(void)
3205 +{
3206 +       _machine_restart = lq_machine_restart;
3207 +       _machine_halt = lq_machine_halt;
3208 +       pm_power_off = lq_machine_power_off;
3209 +       return 0;
3210 +}
3211 +
3212 +arch_initcall(mips_reboot_setup);