target/linux/lantiq/patches-3.3/0037-MIPS-lantiq-add-xway-nand-driver.patch

   1 From 50a9d37efdfa502fafe48a1de604cd5d84a0d5e9 Mon Sep 17 00:00:00 2001
   2 From: John Crispin <blogic@openwrt.org>
   3 Date: Sat, 27 Aug 2011 20:08:14 +0200
   4 Subject: [PATCH 37/70] MIPS: lantiq: add xway nand driver
   5
   6 This patch adds a nand driver for XWAY SoCs. The patch makes use of the
   7 plat_nand driver. As with the EBU NOR driver merged in 3.0, we have the
   8 endianess swap problem on read. To workaround this problem we make the
   9 read_byte() callback available via the plat_nand driver causing the nand
  10 layer to do byte reads.
  11
  12 Signed-off-by: John Crispin <blogic@openwrt.org>
  13
  14 TODO : memory ranges
  15        cs lines
  16        plat dev
  17        ebu2 and not ebu1 ?
  18 ---
  19  .../mips/include/asm/mach-lantiq/xway/lantiq_soc.h |    2 +
  20  arch/mips/lantiq/xway/Makefile                     |    2 +-
  21  arch/mips/lantiq/xway/devices.h                    |    1 +
  22  arch/mips/lantiq/xway/nand.c                       |  216 ++++++++++++++++++++
  23  drivers/mtd/nand/plat_nand.c                       |    1 +
  24  include/linux/mtd/nand.h                           |    1 +
  25  6 files changed, 222 insertions(+), 1 deletions(-)
  26  create mode 100644 arch/mips/lantiq/xway/nand.c
  27
  28 --- a/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h
  29 +++ b/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h
  30 @@ -145,6 +145,8 @@
  31  /* register access macros for EBU and CGU */
  32  #define ltq_ebu_w32(x, y)      ltq_w32((x), ltq_ebu_membase + (y))
  33  #define ltq_ebu_r32(x)         ltq_r32(ltq_ebu_membase + (x))
  34 +#define ltq_ebu_w32_mask(x, y, z) \
  35 +       ltq_w32_mask(x, y, ltq_ebu_membase + (z))
  36  #define ltq_cgu_w32(x, y)      ltq_w32((x), ltq_cgu_membase + (y))
  37  #define ltq_cgu_r32(x)         ltq_r32(ltq_cgu_membase + (x))
  38
  39 --- a/arch/mips/lantiq/xway/Makefile
  40 +++ b/arch/mips/lantiq/xway/Makefile
  41 @@ -1,4 +1,4 @@
  42 -obj-y := sysctrl.o reset.o gpio.o gpio_stp.o gpio_ebu.o devices.o dma.o clk.o prom.o
  43 +obj-y := sysctrl.o reset.o gpio.o gpio_stp.o gpio_ebu.o devices.o dma.o clk.o prom.o nand.o
  44
  45  obj-$(CONFIG_LANTIQ_MACH_EASY50712) += mach-easy50712.o
  46  obj-$(CONFIG_LANTIQ_MACH_EASY50601) += mach-easy50601.o
  47 --- a/arch/mips/lantiq/xway/devices.h
  48 +++ b/arch/mips/lantiq/xway/devices.h
  49 @@ -16,5 +16,6 @@ extern void ltq_register_gpio(void);
  50  extern void ltq_register_gpio_stp(void);
  51  extern void ltq_register_ase_asc(void);
  52  extern void ltq_register_etop(struct ltq_eth_data *eth);
  53 +extern void xway_register_nand(struct mtd_partition *parts, int count);
  54
  55  #endif
  56 --- /dev/null
  57 +++ b/arch/mips/lantiq/xway/nand.c
  58 @@ -0,0 +1,216 @@
  59 +/*
  60 + *  This program is free software; you can redistribute it and/or modify it
  61 + *  under the terms of the GNU General Public License version 2 as published
  62 + *  by the Free Software Foundation.
  63 + *
  64 + *  Copyright (C) 2010 John Crispin <blogic@openwrt.org>
  65 + */
  66 +
  67 +#include <linux/mtd/physmap.h>
  68 +#include <linux/mtd/nand.h>
  69 +#include <linux/platform_device.h>
  70 +#include <linux/io.h>
  71 +
  72 +#include <lantiq_soc.h>
  73 +#include <lantiq_irq.h>
  74 +#include <lantiq_platform.h>
  75 +
  76 +#include "devices.h"
  77 +
  78 +/* nand registers */
  79 +#define LTQ_EBU_NAND_WAIT      0xB4
  80 +#define LTQ_EBU_NAND_ECC0      0xB8
  81 +#define LTQ_EBU_NAND_ECC_AC    0xBC
  82 +#define LTQ_EBU_NAND_CON       0xB0
  83 +#define LTQ_EBU_ADDSEL1                0x24
  84 +
  85 +/* gpio definitions */
  86 +#define PIN_ALE                        13
  87 +#define PIN_CLE                        24
  88 +#define PIN_CS1                        23
  89 +#define PIN_RDY                        48  /* NFLASH_READY */
  90 +#define PIN_RD                 49  /* NFLASH_READ_N */
  91 +
  92 +#define NAND_CMD_ALE           (1 << 2)
  93 +#define NAND_CMD_CLE           (1 << 3)
  94 +#define NAND_CMD_CS            (1 << 4)
  95 +#define NAND_WRITE_CMD_RESET   0xff
  96 +#define NAND_WRITE_CMD         (NAND_CMD_CS | NAND_CMD_CLE)
  97 +#define NAND_WRITE_ADDR                (NAND_CMD_CS | NAND_CMD_ALE)
  98 +#define NAND_WRITE_DATA                (NAND_CMD_CS)
  99 +#define NAND_READ_DATA         (NAND_CMD_CS)
 100 +#define NAND_WAIT_WR_C         (1 << 3)
 101 +#define NAND_WAIT_RD           (0x1)
 102 +
 103 +#define ADDSEL1_MASK(x)                (x << 4)
 104 +#define ADDSEL1_REGEN          1
 105 +#define BUSCON1_SETUP          (1 << 22)
 106 +#define BUSCON1_BCGEN_RES      (0x3 << 12)
 107 +#define BUSCON1_WAITWRC2       (2 << 8)
 108 +#define BUSCON1_WAITRDC2       (2 << 6)
 109 +#define BUSCON1_HOLDC1         (1 << 4)
 110 +#define BUSCON1_RECOVC1                (1 << 2)
 111 +#define BUSCON1_CMULT4         1
 112 +#define NAND_CON_NANDM         1
 113 +#define NAND_CON_CSMUX         (1 << 1)
 114 +#define NAND_CON_CS_P          (1 << 4)
 115 +#define NAND_CON_SE_P          (1 << 5)
 116 +#define NAND_CON_WP_P          (1 << 6)
 117 +#define NAND_CON_PRE_P         (1 << 7)
 118 +#define NAND_CON_IN_CS0                0
 119 +#define NAND_CON_OUT_CS0       0
 120 +#define NAND_CON_IN_CS1                (1 << 8)
 121 +#define NAND_CON_OUT_CS1       (1 << 10)
 122 +#define NAND_CON_CE            (1 << 20)
 123 +
 124 +#define NAND_BASE_ADDRESS      (KSEG1 | 0x14000000)
 125 +
 126 +static const char *part_probes[] = { "cmdlinepart", NULL };
 127 +
 128 +static void xway_select_chip(struct mtd_info *mtd, int chip)
 129 +{
 130 +       switch (chip) {
 131 +       case -1:
 132 +               ltq_ebu_w32_mask(NAND_CON_CE, 0, LTQ_EBU_NAND_CON);
 133 +               ltq_ebu_w32_mask(NAND_CON_NANDM, 0, LTQ_EBU_NAND_CON);
 134 +               break;
 135 +       case 0:
 136 +               ltq_ebu_w32_mask(0, NAND_CON_NANDM, LTQ_EBU_NAND_CON);
 137 +               ltq_ebu_w32_mask(0, NAND_CON_CE, LTQ_EBU_NAND_CON);
 138 +               /* reset the nand chip */
 139 +               while ((ltq_ebu_r32(LTQ_EBU_NAND_WAIT) & NAND_WAIT_WR_C) == 0)
 140 +                       ;
 141 +               ltq_w32(NAND_WRITE_CMD_RESET,
 142 +                       ((u32 *) (NAND_BASE_ADDRESS | NAND_WRITE_CMD)));
 143 +               break;
 144 +       default:
 145 +               BUG();
 146 +       }
 147 +}
 148 +
 149 +static void xway_cmd_ctrl(struct mtd_info *mtd, int data, unsigned int ctrl)
 150 +{
 151 +       struct nand_chip *this = mtd->priv;
 152 +
 153 +       if (ctrl & NAND_CTRL_CHANGE) {
 154 +               if (ctrl & NAND_CLE)
 155 +                       this->IO_ADDR_W = (void __iomem *)
 156 +                                       (NAND_BASE_ADDRESS | NAND_WRITE_CMD);
 157 +               else if (ctrl & NAND_ALE)
 158 +                       this->IO_ADDR_W = (void __iomem *)
 159 +                                       (NAND_BASE_ADDRESS | NAND_WRITE_ADDR);
 160 +       }
 161 +
 162 +       if (data != NAND_CMD_NONE) {
 163 +               *(volatile u8*) ((u32) this->IO_ADDR_W) = data;
 164 +               while ((ltq_ebu_r32(LTQ_EBU_NAND_WAIT) & NAND_WAIT_WR_C) == 0)
 165 +                       ;
 166 +       }
 167 +}
 168 +
 169 +static int xway_dev_ready(struct mtd_info *mtd)
 170 +{
 171 +       return ltq_ebu_r32(LTQ_EBU_NAND_WAIT) & NAND_WAIT_RD;
 172 +}
 173 +
 174 +void nand_write(unsigned int addr, unsigned int val)
 175 +{
 176 +       ltq_w32(val, ((u32 *) (NAND_BASE_ADDRESS | addr)));
 177 +       while ((ltq_ebu_r32(LTQ_EBU_NAND_WAIT) & NAND_WAIT_WR_C) == 0)
 178 +               ;
 179 +}
 180 +
 181 +unsigned char xway_read_byte(struct mtd_info *mtd)
 182 +{
 183 +       return ltq_r8((void __iomem *)(NAND_BASE_ADDRESS | (NAND_READ_DATA)));
 184 +}
 185 +
 186 +static void xway_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
 187 +{
 188 +       int i;
 189 +
 190 +       for (i = 0; i < len; i++)
 191 +       {
 192 +               unsigned char res8 =  ltq_r8((void __iomem *)(NAND_BASE_ADDRESS | (NAND_READ_DATA)));
 193 +               buf[i] = res8;
 194 +       }
 195 +}
 196 +
 197 +static void xway_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
 198 +{
 199 +       int i;
 200 +
 201 +       for (i = 0; i < len; i++)
 202 +       {
 203 +               ltq_w8(buf[i], ((u32*)(NAND_BASE_ADDRESS | (NAND_WRITE_DATA))));
 204 +               while((ltq_ebu_r32(LTQ_EBU_NAND_WAIT) & NAND_WAIT_WR_C) == 0);
 205 +       }
 206 +}
 207 +
 208 +int xway_probe(struct platform_device *pdev)
 209 +{
 210 +       /* might need this later ?
 211 +       ltq_gpio_request(PIN_CS1, 2, 1, "NAND_CS1");
 212 +       */
 213 +       ltq_gpio_request(&pdev->dev, PIN_CLE, 2, 1, "NAND_CLE");
 214 +       ltq_gpio_request(&pdev->dev, PIN_ALE, 2, 1, "NAND_ALE");
 215 +       if (ltq_is_ar9() || ltq_is_vr9()) {
 216 +               ltq_gpio_request(&pdev->dev, PIN_RDY, 2, 0, "NAND_BSY");
 217 +               ltq_gpio_request(&pdev->dev, PIN_RD, 2, 1, "NAND_RD");
 218 +       }
 219 +
 220 +       ltq_ebu_w32((NAND_BASE_ADDRESS & 0x1fffff00)
 221 +               | ADDSEL1_MASK(3) | ADDSEL1_REGEN, LTQ_EBU_ADDSEL1);
 222 +
 223 +       ltq_ebu_w32(BUSCON1_SETUP | BUSCON1_BCGEN_RES | BUSCON1_WAITWRC2
 224 +               | BUSCON1_WAITRDC2 | BUSCON1_HOLDC1 | BUSCON1_RECOVC1
 225 +               | BUSCON1_CMULT4, LTQ_EBU_BUSCON1);
 226 +
 227 +       ltq_ebu_w32(NAND_CON_NANDM | NAND_CON_CSMUX | NAND_CON_CS_P
 228 +               | NAND_CON_SE_P | NAND_CON_WP_P | NAND_CON_PRE_P
 229 +               | NAND_CON_IN_CS0 | NAND_CON_OUT_CS0, LTQ_EBU_NAND_CON);
 230 +
 231 +       ltq_w32(NAND_WRITE_CMD_RESET,
 232 +               ((u32 *) (NAND_BASE_ADDRESS | NAND_WRITE_CMD)));
 233 +       while ((ltq_ebu_r32(LTQ_EBU_NAND_WAIT) & NAND_WAIT_WR_C) == 0)
 234 +               ;
 235 +
 236 +       return 0;
 237 +}
 238 +
 239 +static struct platform_nand_data falcon_flash_nand_data = {
 240 +       .chip = {
 241 +               .nr_chips               = 1,
 242 +               .chip_delay             = 30,
 243 +               .part_probe_types       = part_probes,
 244 +       },
 245 +       .ctrl = {
 246 +               .probe          = xway_probe,
 247 +               .cmd_ctrl       = xway_cmd_ctrl,
 248 +               .dev_ready      = xway_dev_ready,
 249 +               .select_chip    = xway_select_chip,
 250 +               .read_byte      = xway_read_byte,
 251 +               .read_buf       = xway_read_buf,
 252 +               .write_buf      = xway_write_buf,
 253 +       }
 254 +};
 255 +
 256 +static struct resource ltq_nand_res =
 257 +       MEM_RES("nand", 0x14000000, 0x7ffffff);
 258 +
 259 +static struct platform_device ltq_flash_nand = {
 260 +       .name           = "gen_nand",
 261 +       .id             = -1,
 262 +       .num_resources  = 1,
 263 +       .resource       = &ltq_nand_res,
 264 +       .dev            = {
 265 +               .platform_data = &falcon_flash_nand_data,
 266 +       },
 267 +};
 268 +
 269 +void __init xway_register_nand(struct mtd_partition *parts, int count)
 270 +{
 271 +       falcon_flash_nand_data.chip.partitions = parts;
 272 +       falcon_flash_nand_data.chip.nr_partitions = count;
 273 +       platform_device_register(&ltq_flash_nand);
 274 +}
 275 --- a/drivers/mtd/nand/plat_nand.c
 276 +++ b/drivers/mtd/nand/plat_nand.c
 277 @@ -75,6 +75,7 @@ static int __devinit plat_nand_probe(str
 278         data->chip.select_chip = pdata->ctrl.select_chip;
 279         data->chip.write_buf = pdata->ctrl.write_buf;
 280         data->chip.read_buf = pdata->ctrl.read_buf;
 281 +       data->chip.read_byte = pdata->ctrl.read_byte;
 282         data->chip.chip_delay = pdata->chip.chip_delay;
 283         data->chip.options |= pdata->chip.options;
 284         data->chip.bbt_options |= pdata->chip.bbt_options;
 285 --- a/include/linux/mtd/nand.h
 286 +++ b/include/linux/mtd/nand.h
 287 @@ -652,6 +652,7 @@ struct platform_nand_ctrl {
 288         void (*cmd_ctrl)(struct mtd_info *mtd, int dat, unsigned int ctrl);
 289         void (*write_buf)(struct mtd_info *mtd, const uint8_t *buf, int len);
 290         void (*read_buf)(struct mtd_info *mtd, uint8_t *buf, int len);
 291 +       unsigned char (*read_byte)(struct mtd_info *mtd);
 292         void *priv;
 293  };
 294