1 /* ==========================================================================
2 * $File: //dwh/usb_iip/dev/software/otg_ipmate/linux/drivers/dwc_otg_hcd_queue.c $
4 * $Date: 2009-04-17 06:15:34 $
7 * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
8 * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
9 * otherwise expressly agreed to in writing between Synopsys and you.
11 * The Software IS NOT an item of Licensed Software or Licensed Product under
12 * any End User Software License Agreement or Agreement for Licensed Product
13 * with Synopsys or any supplement thereto. You are permitted to use and
14 * redistribute this Software in source and binary forms, with or without
15 * modification, provided that redistributions of source code must retain this
16 * notice. You may not view, use, disclose, copy or distribute this file or
17 * any information contained herein except pursuant to this license grant from
18 * Synopsys. If you do not agree with this notice, including the disclaimer
19 * below, then you are not authorized to use the Software.
21 * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
22 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
25 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
26 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
27 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
28 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
29 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
30 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
32 * ========================================================================== */
33 #ifndef DWC_DEVICE_ONLY
38 * This file contains the functions to manage Queue Heads and Queue
39 * Transfer Descriptors.
41 #include <linux/kernel.h>
42 #include <linux/module.h>
43 #include <linux/moduleparam.h>
44 #include <linux/init.h>
45 #include <linux/device.h>
46 #include <linux/errno.h>
47 #include <linux/list.h>
48 #include <linux/interrupt.h>
49 #include <linux/string.h>
51 #include "dwc_otg_driver.h"
52 #include "dwc_otg_hcd.h"
53 #include "dwc_otg_regs.h"
56 * This function allocates and initializes a QH.
58 * @param _hcd The HCD state structure for the DWC OTG controller.
59 * @param[in] _urb Holds the information about the device/endpoint that we need
60 * to initialize the QH.
62 * @return Returns pointer to the newly allocated QH, or NULL on error. */
63 dwc_otg_qh_t *dwc_otg_hcd_qh_create (dwc_otg_hcd_t *_hcd, struct urb *_urb)
68 /** @todo add memflags argument */
69 qh = dwc_otg_hcd_qh_alloc ();
74 dwc_otg_hcd_qh_init (_hcd, qh, _urb);
78 /** Free each QTD in the QH's QTD-list then free the QH. QH should already be
79 * removed from a list. QTD list should already be empty if called from URB
82 * @param[in] _qh The QH to free.
84 void dwc_otg_hcd_qh_free (dwc_otg_qh_t *_qh)
87 struct list_head *pos;
90 /* Free each QTD in the QTD list */
91 local_irq_save (flags);
92 for (pos = _qh->qtd_list.next;
93 pos != &_qh->qtd_list;
94 pos = _qh->qtd_list.next)
97 qtd = dwc_list_to_qtd (pos);
98 dwc_otg_hcd_qtd_free (qtd);
100 local_irq_restore (flags);
106 /** Initializes a QH structure.
108 * @param[in] _hcd The HCD state structure for the DWC OTG controller.
109 * @param[in] _qh The QH to init.
110 * @param[in] _urb Holds the information about the device/endpoint that we need
111 * to initialize the QH. */
112 #define SCHEDULE_SLOP 10
113 void dwc_otg_hcd_qh_init(dwc_otg_hcd_t *_hcd, dwc_otg_qh_t *_qh, struct urb *_urb)
115 memset (_qh, 0, sizeof (dwc_otg_qh_t));
118 switch (usb_pipetype(_urb->pipe)) {
120 _qh->ep_type = USB_ENDPOINT_XFER_CONTROL;
123 _qh->ep_type = USB_ENDPOINT_XFER_BULK;
125 case PIPE_ISOCHRONOUS:
126 _qh->ep_type = USB_ENDPOINT_XFER_ISOC;
129 _qh->ep_type = USB_ENDPOINT_XFER_INT;
133 _qh->ep_is_in = usb_pipein(_urb->pipe) ? 1 : 0;
135 _qh->data_toggle = DWC_OTG_HC_PID_DATA0;
136 _qh->maxp = usb_maxpacket(_urb->dev, _urb->pipe, !(usb_pipein(_urb->pipe)));
137 INIT_LIST_HEAD(&_qh->qtd_list);
138 INIT_LIST_HEAD(&_qh->qh_list_entry);
141 /* FS/LS Enpoint on HS Hub
142 * NOT virtual root hub */
144 _qh->speed = _urb->dev->speed;
145 if (((_urb->dev->speed == USB_SPEED_LOW) ||
146 (_urb->dev->speed == USB_SPEED_FULL)) &&
147 (_urb->dev->tt) && (_urb->dev->tt->hub) && (_urb->dev->tt->hub->devnum != 1)) {
148 DWC_DEBUGPL(DBG_HCD, "QH init: EP %d: TT found at hub addr %d, for port %d\n",
149 usb_pipeendpoint(_urb->pipe), _urb->dev->tt->hub->devnum,
154 if (_qh->ep_type == USB_ENDPOINT_XFER_INT ||
155 _qh->ep_type == USB_ENDPOINT_XFER_ISOC) {
156 /* Compute scheduling parameters once and save them. */
159 /** @todo Account for split transfers in the bus time. */
160 int bytecount = dwc_hb_mult(_qh->maxp) * dwc_max_packet(_qh->maxp);
161 _qh->usecs = NS_TO_US(usb_calc_bus_time(_urb->dev->speed,
162 usb_pipein(_urb->pipe),
163 (_qh->ep_type == USB_ENDPOINT_XFER_ISOC),bytecount));
165 /* Start in a slightly future (micro)frame. */
166 _qh->sched_frame = dwc_frame_num_inc(_hcd->frame_number, SCHEDULE_SLOP);
167 _qh->interval = _urb->interval;
169 /* Increase interrupt polling rate for debugging. */
170 if (_qh->ep_type == USB_ENDPOINT_XFER_INT) {
174 hprt.d32 = dwc_read_reg32(_hcd->core_if->host_if->hprt0);
175 if ((hprt.b.prtspd == DWC_HPRT0_PRTSPD_HIGH_SPEED) &&
176 ((_urb->dev->speed == USB_SPEED_LOW) ||
177 (_urb->dev->speed == USB_SPEED_FULL)))
180 _qh->sched_frame |= 0x7;
181 _qh->start_split_frame = _qh->sched_frame;
185 DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD QH Initialized\n");
186 DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD QH - qh = %p\n", _qh);
187 DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD QH - Device Address = %d\n",
189 DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD QH - Endpoint %d, %s\n",
190 usb_pipeendpoint(_urb->pipe),
191 usb_pipein(_urb->pipe) == USB_DIR_IN ? "IN" : "OUT");
192 DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD QH - Speed = %s\n",
193 ({ char *speed; switch (_urb->dev->speed) {
194 case USB_SPEED_LOW: speed = "low"; break;
195 case USB_SPEED_FULL: speed = "full"; break;
196 case USB_SPEED_HIGH: speed = "high"; break;
197 default: speed = "?"; break;
199 DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD QH - Type = %s\n",
200 ({ char *type; switch (_qh->ep_type) {
201 case USB_ENDPOINT_XFER_ISOC: type = "isochronous"; break;
202 case USB_ENDPOINT_XFER_INT: type = "interrupt"; break;
203 case USB_ENDPOINT_XFER_CONTROL: type = "control"; break;
204 case USB_ENDPOINT_XFER_BULK: type = "bulk"; break;
205 default: type = "?"; break;
208 if (_qh->ep_type == USB_ENDPOINT_XFER_INT) {
209 DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD QH - usecs = %d\n",
211 DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD QH - interval = %d\n",
220 * Microframe scheduler
221 * track the total use in hcd->frame_usecs
222 * keep each qh use in qh->frame_usecs
223 * when surrendering the qh then donate the time back
225 const unsigned short max_uframe_usecs[]={ 100, 100, 100, 100, 100, 100, 30, 0 };
228 * called from dwc_otg_hcd.c:dwc_otg_hcd_init
230 int init_hcd_usecs(dwc_otg_hcd_t *_hcd)
233 for (i=0; i<8; i++) {
234 _hcd->frame_usecs[i] = max_uframe_usecs[i];
239 static int find_single_uframe(dwc_otg_hcd_t * _hcd, dwc_otg_qh_t * _qh)
242 unsigned short utime;
253 /* At the start _hcd->frame_usecs[i] = max_uframe_usecs[i]; */
254 if (utime <= _hcd->frame_usecs[i]) {
255 _hcd->frame_usecs[i] -= utime;
256 _qh->frame_usecs[i] += utime;
273 * use this for FS apps that can span multiple uframes
275 static int find_multi_uframe(dwc_otg_hcd_t * _hcd, dwc_otg_qh_t * _qh)
279 unsigned short utime;
283 unsigned short xtime;
292 if(_hcd->frame_usecs[i] <= 0) {
302 * we need n consequtive slots
303 * so use j as a start slot j plus j+1 must be enough time (for now)
305 xtime= _hcd->frame_usecs[i];
306 for (j = i+1 ; j < 8 ; j++ ) {
308 * if we add this frame remaining time to xtime we may
309 * be OK, if not we need to test j for a complete frame
311 if ((xtime+_hcd->frame_usecs[j]) < utime) {
312 if (_hcd->frame_usecs[j] < max_uframe_usecs[j]) {
318 if (xtime >= utime) {
320 j = 8; /* stop loop with a good value ret */
323 /* add the frame time to x time */
324 xtime += _hcd->frame_usecs[j];
325 /* we must have a fully available next frame or break */
327 && (_hcd->frame_usecs[j] == max_uframe_usecs[j])) {
329 j = 8; /* stop loop with a bad value ret */
335 for (j = i; (t_left>0) && (j < 8); j++ ) {
336 t_left -= _hcd->frame_usecs[j];
338 _qh->frame_usecs[j] += _hcd->frame_usecs[j] + t_left;
339 _hcd->frame_usecs[j]= -t_left;
343 _qh->frame_usecs[j] += _hcd->frame_usecs[j];
344 _hcd->frame_usecs[j] = 0;
358 static int find_uframe(dwc_otg_hcd_t * _hcd, dwc_otg_qh_t * _qh)
363 if (_qh->speed == USB_SPEED_HIGH) {
364 /* if this is a hs transaction we need a full frame */
365 ret = find_single_uframe(_hcd, _qh);
367 /* if this is a fs transaction we may need a sequence of frames */
368 ret = find_multi_uframe(_hcd, _qh);
374 * Checks that the max transfer size allowed in a host channel is large enough
375 * to handle the maximum data transfer in a single (micro)frame for a periodic
378 * @param _hcd The HCD state structure for the DWC OTG controller.
379 * @param _qh QH for a periodic endpoint.
381 * @return 0 if successful, negative error code otherwise.
383 static int check_max_xfer_size(dwc_otg_hcd_t *_hcd, dwc_otg_qh_t *_qh)
386 uint32_t max_xfer_size;
387 uint32_t max_channel_xfer_size;
391 max_xfer_size = dwc_max_packet(_qh->maxp) * dwc_hb_mult(_qh->maxp);
392 max_channel_xfer_size = _hcd->core_if->core_params->max_transfer_size;
394 if (max_xfer_size > max_channel_xfer_size) {
395 DWC_NOTICE("%s: Periodic xfer length %d > "
396 "max xfer length for channel %d\n",
397 __func__, max_xfer_size, max_channel_xfer_size);
405 * Schedules an interrupt or isochronous transfer in the periodic schedule.
407 * @param _hcd The HCD state structure for the DWC OTG controller.
408 * @param _qh QH for the periodic transfer. The QH should already contain the
409 * scheduling information.
411 * @return 0 if successful, negative error code otherwise.
413 static int schedule_periodic(dwc_otg_hcd_t *_hcd, dwc_otg_qh_t *_qh)
418 status = find_uframe(_hcd, _qh);
427 /* Set the new frame up */
429 _qh->sched_frame &= ~0x7;
430 _qh->sched_frame |= (frame & 7);
436 DWC_NOTICE("%s: Insufficient periodic bandwidth for "
437 "periodic transfer.\n", __func__);
441 status = check_max_xfer_size(_hcd, _qh);
443 DWC_NOTICE("%s: Channel max transfer size too small "
444 "for periodic transfer.\n", __func__);
448 /* Always start in the inactive schedule. */
449 list_add_tail(&_qh->qh_list_entry, &_hcd->periodic_sched_inactive);
452 /* Update claimed usecs per (micro)frame. */
453 _hcd->periodic_usecs += _qh->usecs;
455 /* Update average periodic bandwidth claimed and # periodic reqs for usbfs. */
456 hcd_to_bus(dwc_otg_hcd_to_hcd(_hcd))->bandwidth_allocated += _qh->usecs / _qh->interval;
457 if (_qh->ep_type == USB_ENDPOINT_XFER_INT) {
458 hcd_to_bus(dwc_otg_hcd_to_hcd(_hcd))->bandwidth_int_reqs++;
459 DWC_DEBUGPL(DBG_HCD, "Scheduled intr: qh %p, usecs %d, period %d\n",
460 _qh, _qh->usecs, _qh->interval);
462 hcd_to_bus(dwc_otg_hcd_to_hcd(_hcd))->bandwidth_isoc_reqs++;
463 DWC_DEBUGPL(DBG_HCD, "Scheduled isoc: qh %p, usecs %d, period %d\n",
464 _qh, _qh->usecs, _qh->interval);
471 * This function adds a QH to either the non periodic or periodic schedule if
472 * it is not already in the schedule. If the QH is already in the schedule, no
475 * @return 0 if successful, negative error code otherwise.
477 int dwc_otg_hcd_qh_add (dwc_otg_hcd_t *_hcd, dwc_otg_qh_t *_qh)
482 local_irq_save(flags);
484 if (!list_empty(&_qh->qh_list_entry)) {
485 /* QH already in a schedule. */
489 /* Add the new QH to the appropriate schedule */
490 if (dwc_qh_is_non_per(_qh)) {
491 /* Always start in the inactive schedule. */
492 list_add_tail(&_qh->qh_list_entry, &_hcd->non_periodic_sched_inactive);
494 status = schedule_periodic(_hcd, _qh);
498 local_irq_restore(flags);
504 * This function adds a QH to the non periodic deferred schedule.
506 * @return 0 if successful, negative error code otherwise.
508 int dwc_otg_hcd_qh_add_deferred(dwc_otg_hcd_t * _hcd, dwc_otg_qh_t * _qh)
511 local_irq_save(flags);
512 if (!list_empty(&_qh->qh_list_entry)) {
513 /* QH already in a schedule. */
517 /* Add the new QH to the non periodic deferred schedule */
518 if (dwc_qh_is_non_per(_qh)) {
519 list_add_tail(&_qh->qh_list_entry,
520 &_hcd->non_periodic_sched_deferred);
523 local_irq_restore(flags);
528 * Removes an interrupt or isochronous transfer from the periodic schedule.
530 * @param _hcd The HCD state structure for the DWC OTG controller.
531 * @param _qh QH for the periodic transfer.
533 static void deschedule_periodic(dwc_otg_hcd_t *_hcd, dwc_otg_qh_t *_qh)
536 list_del_init(&_qh->qh_list_entry);
539 /* Update claimed usecs per (micro)frame. */
540 _hcd->periodic_usecs -= _qh->usecs;
542 for (i = 0; i < 8; i++) {
543 _hcd->frame_usecs[i] += _qh->frame_usecs[i];
544 _qh->frame_usecs[i] = 0;
546 /* Update average periodic bandwidth claimed and # periodic reqs for usbfs. */
547 hcd_to_bus(dwc_otg_hcd_to_hcd(_hcd))->bandwidth_allocated -= _qh->usecs / _qh->interval;
549 if (_qh->ep_type == USB_ENDPOINT_XFER_INT) {
550 hcd_to_bus(dwc_otg_hcd_to_hcd(_hcd))->bandwidth_int_reqs--;
551 DWC_DEBUGPL(DBG_HCD, "Descheduled intr: qh %p, usecs %d, period %d\n",
552 _qh, _qh->usecs, _qh->interval);
554 hcd_to_bus(dwc_otg_hcd_to_hcd(_hcd))->bandwidth_isoc_reqs--;
555 DWC_DEBUGPL(DBG_HCD, "Descheduled isoc: qh %p, usecs %d, period %d\n",
556 _qh, _qh->usecs, _qh->interval);
561 * Removes a QH from either the non-periodic or periodic schedule. Memory is
564 * @param[in] _hcd The HCD state structure.
565 * @param[in] _qh QH to remove from schedule. */
566 void dwc_otg_hcd_qh_remove (dwc_otg_hcd_t *_hcd, dwc_otg_qh_t *_qh)
570 local_irq_save(flags);
572 if (list_empty(&_qh->qh_list_entry)) {
573 /* QH is not in a schedule. */
577 if (dwc_qh_is_non_per(_qh)) {
578 if (_hcd->non_periodic_qh_ptr == &_qh->qh_list_entry) {
579 _hcd->non_periodic_qh_ptr = _hcd->non_periodic_qh_ptr->next;
581 list_del_init(&_qh->qh_list_entry);
583 deschedule_periodic(_hcd, _qh);
587 local_irq_restore(flags);
591 * Defers a QH. For non-periodic QHs, removes the QH from the active
592 * non-periodic schedule. The QH is added to the deferred non-periodic
593 * schedule if any QTDs are still attached to the QH.
595 int dwc_otg_hcd_qh_deferr(dwc_otg_hcd_t * _hcd, dwc_otg_qh_t * _qh, int delay)
599 local_irq_save(flags);
600 if (dwc_qh_is_non_per(_qh)) {
602 dwc_frame_num_inc(_hcd->frame_number,
605 _qh->qtd_in_process = NULL;
607 dwc_otg_hcd_qh_remove(_hcd, _qh);
608 if (!list_empty(&_qh->qtd_list)) {
609 /* Add back to deferred non-periodic schedule. */
610 dwc_otg_hcd_qh_add_deferred(_hcd, _qh);
613 local_irq_restore(flags);
618 * Deactivates a QH. For non-periodic QHs, removes the QH from the active
619 * non-periodic schedule. The QH is added to the inactive non-periodic
620 * schedule if any QTDs are still attached to the QH.
622 * For periodic QHs, the QH is removed from the periodic queued schedule. If
623 * there are any QTDs still attached to the QH, the QH is added to either the
624 * periodic inactive schedule or the periodic ready schedule and its next
625 * scheduled frame is calculated. The QH is placed in the ready schedule if
626 * the scheduled frame has been reached already. Otherwise it's placed in the
627 * inactive schedule. If there are no QTDs attached to the QH, the QH is
628 * completely removed from the periodic schedule.
630 void dwc_otg_hcd_qh_deactivate(dwc_otg_hcd_t *_hcd, dwc_otg_qh_t *_qh, int sched_next_periodic_split)
633 local_irq_save(flags);
635 if (dwc_qh_is_non_per(_qh)) {
636 dwc_otg_hcd_qh_remove(_hcd, _qh);
637 if (!list_empty(&_qh->qtd_list)) {
638 /* Add back to inactive non-periodic schedule. */
639 dwc_otg_hcd_qh_add(_hcd, _qh);
642 uint16_t frame_number = dwc_otg_hcd_get_frame_number(dwc_otg_hcd_to_hcd(_hcd));
645 /* Schedule the next continuing periodic split transfer */
646 if (sched_next_periodic_split) {
648 _qh->sched_frame = frame_number;
649 if (dwc_frame_num_le(frame_number,
650 dwc_frame_num_inc(_qh->start_split_frame, 1))) {
652 * Allow one frame to elapse after start
653 * split microframe before scheduling
654 * complete split, but DONT if we are
655 * doing the next start split in the
656 * same frame for an ISOC out.
658 if ((_qh->ep_type != USB_ENDPOINT_XFER_ISOC) || (_qh->ep_is_in != 0)) {
659 _qh->sched_frame = dwc_frame_num_inc(_qh->sched_frame, 1);
663 _qh->sched_frame = dwc_frame_num_inc(_qh->start_split_frame,
665 if (dwc_frame_num_le(_qh->sched_frame, frame_number)) {
666 _qh->sched_frame = frame_number;
668 _qh->sched_frame |= 0x7;
669 _qh->start_split_frame = _qh->sched_frame;
672 _qh->sched_frame = dwc_frame_num_inc(_qh->sched_frame, _qh->interval);
673 if (dwc_frame_num_le(_qh->sched_frame, frame_number)) {
674 _qh->sched_frame = frame_number;
678 if (list_empty(&_qh->qtd_list)) {
679 dwc_otg_hcd_qh_remove(_hcd, _qh);
682 * Remove from periodic_sched_queued and move to
685 if (dwc_frame_num_le(_qh->sched_frame, frame_number)) {
686 list_move(&_qh->qh_list_entry,
687 &_hcd->periodic_sched_ready);
689 list_move(&_qh->qh_list_entry,
690 &_hcd->periodic_sched_inactive);
695 local_irq_restore(flags);
699 * This function allocates and initializes a QTD.
701 * @param[in] _urb The URB to create a QTD from. Each URB-QTD pair will end up
702 * pointing to each other so each pair should have a unique correlation.
704 * @return Returns pointer to the newly allocated QTD, or NULL on error. */
705 dwc_otg_qtd_t *dwc_otg_hcd_qtd_create (struct urb *_urb)
709 qtd = dwc_otg_hcd_qtd_alloc ();
714 dwc_otg_hcd_qtd_init (qtd, _urb);
719 * Initializes a QTD structure.
721 * @param[in] _qtd The QTD to initialize.
722 * @param[in] _urb The URB to use for initialization. */
723 void dwc_otg_hcd_qtd_init (dwc_otg_qtd_t *_qtd, struct urb *_urb)
725 memset (_qtd, 0, sizeof (dwc_otg_qtd_t));
727 if (usb_pipecontrol(_urb->pipe)) {
729 * The only time the QTD data toggle is used is on the data
730 * phase of control transfers. This phase always starts with
733 _qtd->data_toggle = DWC_OTG_HC_PID_DATA1;
734 _qtd->control_phase = DWC_OTG_CONTROL_SETUP;
738 _qtd->complete_split = 0;
739 _qtd->isoc_split_pos = DWC_HCSPLIT_XACTPOS_ALL;
740 _qtd->isoc_split_offset = 0;
742 /* Store the qtd ptr in the urb to reference what QTD. */
748 * This function adds a QTD to the QTD-list of a QH. It will find the correct
749 * QH to place the QTD into. If it does not find a QH, then it will create a
750 * new QH. If the QH to which the QTD is added is not currently scheduled, it
751 * is placed into the proper schedule based on its EP type.
753 * @param[in] _qtd The QTD to add
754 * @param[in] _dwc_otg_hcd The DWC HCD structure
756 * @return 0 if successful, negative error code otherwise.
758 int dwc_otg_hcd_qtd_add(dwc_otg_qtd_t * _qtd, dwc_otg_hcd_t * _dwc_otg_hcd)
760 struct usb_host_endpoint *ep;
764 struct urb *urb = _qtd->urb;
766 local_irq_save(flags);
769 * Get the QH which holds the QTD-list to insert to. Create QH if it
772 ep = dwc_urb_to_endpoint(urb);
773 qh = (dwc_otg_qh_t *)ep->hcpriv;
775 qh = dwc_otg_hcd_qh_create (_dwc_otg_hcd, urb);
783 _qtd->qtd_qh_ptr = qh;
784 retval = dwc_otg_hcd_qh_add(_dwc_otg_hcd, qh);
786 list_add_tail(&_qtd->qtd_list_entry, &qh->qtd_list);
790 local_irq_restore(flags);
794 #endif /* DWC_DEVICE_ONLY */