2 * This program is free software; you can redistribute it and/or modify it
3 * under the terms of the GNU General Public License version 2 as published
4 * by the Free Software Foundation.
6 * This program is distributed in the hope that it will be useful,
7 * but WITHOUT ANY WARRANTY; without even the implied warranty of
8 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
9 * GNU General Public License for more details.
11 * You should have received a copy of the GNU General Public License
12 * along with this program; if not, write to the Free Software
13 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
15 * Copyright (C) 2011 John Crispin <blogic@openwrt.org>
18 #include <linux/kernel.h>
19 #include <linux/slab.h>
20 #include <linux/errno.h>
21 #include <linux/types.h>
22 #include <linux/interrupt.h>
23 #include <linux/uaccess.h>
25 #include <linux/netdevice.h>
26 #include <linux/etherdevice.h>
27 #include <linux/phy.h>
29 #include <linux/tcp.h>
30 #include <linux/skbuff.h>
32 #include <linux/platform_device.h>
33 #include <linux/ethtool.h>
34 #include <linux/init.h>
35 #include <linux/delay.h>
37 #include <linux/dma-mapping.h>
38 #include <linux/module.h>
39 #include <linux/clk.h>
41 #include <asm/checksum.h>
43 #include <lantiq_soc.h>
45 #include <lantiq_platform.h>
47 #define LTQ_SWITCH_BASE 0x1E108000
48 #define LTQ_SWITCH_CORE_BASE LTQ_SWITCH_BASE
49 #define LTQ_SWITCH_TOP_PDI_BASE LTQ_SWITCH_CORE_BASE
50 #define LTQ_SWITCH_BM_PDI_BASE (LTQ_SWITCH_CORE_BASE + 4 * 0x40)
51 #define LTQ_SWITCH_MAC_PDI_0_BASE (LTQ_SWITCH_CORE_BASE + 4 * 0x900)
52 #define LTQ_SWITCH_MAC_PDI_X_BASE(x) (LTQ_SWITCH_MAC_PDI_0_BASE + x * 0x30)
53 #define LTQ_SWITCH_TOPLEVEL_BASE (LTQ_SWITCH_BASE + 4 * 0xC40)
54 #define LTQ_SWITCH_MDIO_PDI_BASE (LTQ_SWITCH_TOPLEVEL_BASE)
55 #define LTQ_SWITCH_MII_PDI_BASE (LTQ_SWITCH_TOPLEVEL_BASE + 4 * 0x36)
56 #define LTQ_SWITCH_PMAC_PDI_BASE (LTQ_SWITCH_TOPLEVEL_BASE + 4 * 0x82)
58 #define LTQ_ETHSW_MAC_CTRL0_PADEN (1 << 8)
59 #define LTQ_ETHSW_MAC_CTRL0_FCS (1 << 7)
60 #define LTQ_ETHSW_MAC_CTRL1_SHORTPRE (1 << 8)
61 #define LTQ_ETHSW_MAC_CTRL2_MLEN (1 << 3)
62 #define LTQ_ETHSW_MAC_CTRL2_LCHKL (1 << 2)
63 #define LTQ_ETHSW_MAC_CTRL2_LCHKS_DIS 0
64 #define LTQ_ETHSW_MAC_CTRL2_LCHKS_UNTAG 1
65 #define LTQ_ETHSW_MAC_CTRL2_LCHKS_TAG 2
66 #define LTQ_ETHSW_MAC_CTRL6_RBUF_DLY_WP_SHIFT 9
67 #define LTQ_ETHSW_MAC_CTRL6_RXBUF_BYPASS (1 << 6)
68 #define LTQ_ETHSW_GLOB_CTRL_SE (1 << 15)
69 #define LTQ_ETHSW_MDC_CFG1_MCEN (1 << 8)
70 #define LTQ_ETHSW_PMAC_HD_CTL_FC (1 << 10)
71 #define LTQ_ETHSW_PMAC_HD_CTL_RC (1 << 4)
72 #define LTQ_ETHSW_PMAC_HD_CTL_AC (1 << 2)
73 #define ADVERTIZE_MPD (1 << 10)
75 #define MDIO_DEVAD_NONE (-1)
77 #define LTQ_ETH_RX_BUFFER_CNT PKTBUFSRX
79 #define LTQ_MDIO_DRV_NAME "ltq-mdio"
80 #define LTQ_ETH_DRV_NAME "ltq-eth"
82 #define LTQ_ETHSW_MAX_GMAC 1
83 #define LTQ_ETHSW_PMAC 1
85 #define ltq_setbits(a, set) \
86 ltq_w32(ltq_r32(a) | (set), a)
88 enum ltq_reset_modules {
98 dbg_ltq_writel(void *a, unsigned int b)
103 int ltq_reset_once(enum ltq_reset_modules module, ulong usec);
105 struct ltq_ethsw_mac_pdi_x_regs {
106 u32 pstat; /* Port status */
107 u32 pisr; /* Interrupt status */
108 u32 pier; /* Interrupt enable */
109 u32 ctrl_0; /* Control 0 */
110 u32 ctrl_1; /* Control 1 */
111 u32 ctrl_2; /* Control 2 */
112 u32 ctrl_3; /* Control 3 */
113 u32 ctrl_4; /* Control 4 */
114 u32 ctrl_5; /* Control 5 */
115 u32 ctrl_6; /* Control 6 */
116 u32 bufst; /* TX/RX buffer control */
117 u32 testen; /* Test enable */
120 struct ltq_ethsw_mac_pdi_regs {
121 struct ltq_ethsw_mac_pdi_x_regs mac[12];
124 struct ltq_ethsw_mdio_pdi_regs {
125 u32 glob_ctrl; /* Global control 0 */
127 u32 mdio_ctrl; /* MDIO control */
128 u32 mdio_read; /* MDIO read data */
129 u32 mdio_write; /* MDIO write data */
130 u32 mdc_cfg_0; /* MDC clock configuration 0 */
131 u32 mdc_cfg_1; /* MDC clock configuration 1 */
133 u32 phy_addr_5; /* PHY address port 5 */
134 u32 phy_addr_4; /* PHY address port 4 */
135 u32 phy_addr_3; /* PHY address port 3 */
136 u32 phy_addr_2; /* PHY address port 2 */
137 u32 phy_addr_1; /* PHY address port 1 */
138 u32 phy_addr_0; /* PHY address port 0 */
139 u32 mdio_stat_0; /* MDIO PHY polling status port 0 */
140 u32 mdio_stat_1; /* MDIO PHY polling status port 1 */
141 u32 mdio_stat_2; /* MDIO PHY polling status port 2 */
142 u32 mdio_stat_3; /* MDIO PHY polling status port 3 */
143 u32 mdio_stat_4; /* MDIO PHY polling status port 4 */
144 u32 mdio_stat_5; /* MDIO PHY polling status port 5 */
147 struct ltq_ethsw_mii_pdi_regs {
148 u32 mii_cfg0; /* xMII port 0 configuration */
149 u32 pcdu0; /* Port 0 clock delay configuration */
150 u32 mii_cfg1; /* xMII port 1 configuration */
151 u32 pcdu1; /* Port 1 clock delay configuration */
152 u32 mii_cfg2; /* xMII port 2 configuration */
154 u32 mii_cfg3; /* xMII port 3 configuration */
156 u32 mii_cfg4; /* xMII port 4 configuration */
158 u32 mii_cfg5; /* xMII port 5 configuration */
159 u32 pcdu5; /* Port 5 clock delay configuration */
162 struct ltq_ethsw_pmac_pdi_regs {
163 u32 hd_ctl; /* PMAC header control */
164 u32 tl; /* PMAC type/length */
165 u32 sa1; /* PMAC source address 1 */
166 u32 sa2; /* PMAC source address 2 */
167 u32 sa3; /* PMAC source address 3 */
168 u32 da1; /* PMAC destination address 1 */
169 u32 da2; /* PMAC destination address 2 */
170 u32 da3; /* PMAC destination address 3 */
171 u32 vlan; /* PMAC VLAN */
172 u32 rx_ipg; /* PMAC interpacket gap in RX direction */
173 u32 st_etype; /* PMAC special tag ethertype */
174 u32 ewan; /* PMAC ethernet WAN group */
177 struct ltq_mdio_phy_addr_reg {
181 unsigned lnkst:2; /* Link status control */
182 unsigned speed:2; /* Speed control */
183 unsigned fdup:2; /* Full duplex control */
184 unsigned fcontx:2; /* Flow control mode TX */
185 unsigned fconrx:2; /* Flow control mode RX */
186 unsigned addr:5; /* PHY address */
192 enum ltq_mdio_phy_addr_lnkst {
193 LTQ_MDIO_PHY_ADDR_LNKST_AUTO = 0,
194 LTQ_MDIO_PHY_ADDR_LNKST_UP = 1,
195 LTQ_MDIO_PHY_ADDR_LNKST_DOWN = 2,
198 enum ltq_mdio_phy_addr_speed {
199 LTQ_MDIO_PHY_ADDR_SPEED_M10 = 0,
200 LTQ_MDIO_PHY_ADDR_SPEED_M100 = 1,
201 LTQ_MDIO_PHY_ADDR_SPEED_G1 = 2,
202 LTQ_MDIO_PHY_ADDR_SPEED_AUTO = 3,
205 enum ltq_mdio_phy_addr_fdup {
206 LTQ_MDIO_PHY_ADDR_FDUP_AUTO = 0,
207 LTQ_MDIO_PHY_ADDR_FDUP_ENABLE = 1,
208 LTQ_MDIO_PHY_ADDR_FDUP_DISABLE = 3,
211 enum ltq_mdio_phy_addr_fcon {
212 LTQ_MDIO_PHY_ADDR_FCON_AUTO = 0,
213 LTQ_MDIO_PHY_ADDR_FCON_ENABLE = 1,
214 LTQ_MDIO_PHY_ADDR_FCON_DISABLE = 3,
217 struct ltq_mii_mii_cfg_reg {
220 unsigned res:1; /* Hardware reset */
221 unsigned en:1; /* xMII interface enable */
222 unsigned isol:1; /* xMII interface isolate */
223 unsigned ldclkdis:1; /* Link down clock disable */
225 unsigned crs:2; /* CRS sensitivity config */
226 unsigned rgmii_ibs:1; /* RGMII In Band status */
227 unsigned rmii:1; /* RMII ref clock direction */
228 unsigned miirate:3; /* xMII interface clock rate */
229 unsigned miimode:4; /* xMII interface mode */
235 enum ltq_mii_mii_cfg_miirate {
236 LTQ_MII_MII_CFG_MIIRATE_M2P5 = 0,
237 LTQ_MII_MII_CFG_MIIRATE_M25 = 1,
238 LTQ_MII_MII_CFG_MIIRATE_M125 = 2,
239 LTQ_MII_MII_CFG_MIIRATE_M50 = 3,
240 LTQ_MII_MII_CFG_MIIRATE_AUTO = 4,
243 enum ltq_mii_mii_cfg_miimode {
244 LTQ_MII_MII_CFG_MIIMODE_MIIP = 0,
245 LTQ_MII_MII_CFG_MIIMODE_MIIM = 1,
246 LTQ_MII_MII_CFG_MIIMODE_RMIIP = 2,
247 LTQ_MII_MII_CFG_MIIMODE_RMIIM = 3,
248 LTQ_MII_MII_CFG_MIIMODE_RGMII = 4,
251 struct ltq_eth_priv {
252 struct ltq_dma_device *dma_dev;
254 struct eth_device *dev;
255 struct phy_device *phymap[LTQ_ETHSW_MAX_GMAC];
259 enum ltq_mdio_mbusy {
260 LTQ_MDIO_MBUSY_IDLE = 0,
261 LTQ_MDIO_MBUSY_BUSY = 1,
265 LTQ_MDIO_OP_WRITE = 1,
266 LTQ_MDIO_OP_READ = 2,
269 struct ltq_mdio_access {
282 enum LTQ_ETH_PORT_FLAGS {
283 LTQ_ETH_PORT_NONE = 0,
284 LTQ_ETH_PORT_PHY = 1,
285 LTQ_ETH_PORT_SWITCH = (1 << 1),
286 LTQ_ETH_PORT_MAC = (1 << 2),
289 struct ltq_eth_port_config {
293 phy_interface_t phy_if;
296 struct ltq_eth_board_config {
297 const struct ltq_eth_port_config *ports;
301 static const struct ltq_eth_port_config eth_port_config[] = {
302 /* GMAC0: external Lantiq PEF7071 10/100/1000 PHY for LAN port 0 */
303 { 0, 0x0, LTQ_ETH_PORT_PHY, PHY_INTERFACE_MODE_RGMII },
304 /* GMAC1: external Lantiq PEF7071 10/100/1000 PHY for LAN port 1 */
305 { 1, 0x1, LTQ_ETH_PORT_PHY, PHY_INTERFACE_MODE_RGMII },
308 static const struct ltq_eth_board_config board_config = {
309 .ports = eth_port_config,
310 .num_ports = ARRAY_SIZE(eth_port_config),
313 static struct ltq_ethsw_mac_pdi_regs *ltq_ethsw_mac_pdi_regs =
314 (struct ltq_ethsw_mac_pdi_regs *) CKSEG1ADDR(LTQ_SWITCH_MAC_PDI_0_BASE);
316 static struct ltq_ethsw_mdio_pdi_regs *ltq_ethsw_mdio_pdi_regs =
317 (struct ltq_ethsw_mdio_pdi_regs *) CKSEG1ADDR(LTQ_SWITCH_MDIO_PDI_BASE);
319 static struct ltq_ethsw_mii_pdi_regs *ltq_ethsw_mii_pdi_regs =
320 (struct ltq_ethsw_mii_pdi_regs *) CKSEG1ADDR(LTQ_SWITCH_MII_PDI_BASE);
322 static struct ltq_ethsw_pmac_pdi_regs *ltq_ethsw_pmac_pdi_regs =
323 (struct ltq_ethsw_pmac_pdi_regs *) CKSEG1ADDR(LTQ_SWITCH_PMAC_PDI_BASE);
326 #define MAX_DMA_CHAN 0x8
327 #define MAX_DMA_CRC_LEN 0x4
328 #define MAX_DMA_DATA_LEN 0x600
330 /* use 2 static channels for TX/RX
331 depending on the SoC we need to use different DMA channels for ethernet */
332 #define LTQ_ETOP_TX_CHANNEL 1
333 #define LTQ_ETOP_RX_CHANNEL 0
335 #define IS_TX(x) (x == LTQ_ETOP_TX_CHANNEL)
336 #define IS_RX(x) (x == LTQ_ETOP_RX_CHANNEL)
338 #define DRV_VERSION "1.0"
340 static void __iomem *ltq_vrx200_membase;
342 struct ltq_vrx200_chan {
345 struct net_device *netdev;
346 struct napi_struct napi;
347 struct ltq_dma_channel dma;
348 struct sk_buff *skb[LTQ_DESC_NUM];
351 struct ltq_vrx200_priv {
352 struct net_device *netdev;
353 struct ltq_eth_data *pldata;
354 struct resource *res;
356 struct mii_bus *mii_bus;
357 struct phy_device *phydev;
359 struct ltq_vrx200_chan ch[MAX_DMA_CHAN];
360 int tx_free[MAX_DMA_CHAN >> 1];
367 static int ltq_vrx200_mdio_wr(struct mii_bus *bus, int phy_addr,
368 int phy_reg, u16 phy_data);
371 ltq_vrx200_alloc_skb(struct ltq_vrx200_chan *ch)
373 ch->skb[ch->dma.desc] = dev_alloc_skb(MAX_DMA_DATA_LEN);
374 if (!ch->skb[ch->dma.desc])
376 ch->dma.desc_base[ch->dma.desc].addr = dma_map_single(NULL,
377 ch->skb[ch->dma.desc]->data, MAX_DMA_DATA_LEN,
379 ch->dma.desc_base[ch->dma.desc].addr =
380 CPHYSADDR(ch->skb[ch->dma.desc]->data);
381 ch->dma.desc_base[ch->dma.desc].ctl =
382 LTQ_DMA_OWN | LTQ_DMA_RX_OFFSET(NET_IP_ALIGN) |
384 skb_reserve(ch->skb[ch->dma.desc], NET_IP_ALIGN);
389 ltq_vrx200_hw_receive(struct ltq_vrx200_chan *ch)
391 struct ltq_vrx200_priv *priv = netdev_priv(ch->netdev);
392 struct ltq_dma_desc *desc = &ch->dma.desc_base[ch->dma.desc];
393 struct sk_buff *skb = ch->skb[ch->dma.desc];
394 int len = (desc->ctl & LTQ_DMA_SIZE_MASK) - MAX_DMA_CRC_LEN;
397 spin_lock_irqsave(&priv->lock, flags);
398 if (ltq_vrx200_alloc_skb(ch)) {
399 netdev_err(ch->netdev,
400 "failed to allocate new rx buffer, stopping DMA\n");
401 ltq_dma_close(&ch->dma);
404 ch->dma.desc %= LTQ_DESC_NUM;
405 spin_unlock_irqrestore(&priv->lock, flags);
408 skb->dev = ch->netdev;
409 skb->protocol = eth_type_trans(skb, ch->netdev);
410 netif_receive_skb(skb);
414 ltq_vrx200_poll_rx(struct napi_struct *napi, int budget)
416 struct ltq_vrx200_chan *ch = container_of(napi,
417 struct ltq_vrx200_chan, napi);
418 struct ltq_vrx200_priv *priv = netdev_priv(ch->netdev);
423 while ((rx < budget) && !complete) {
424 struct ltq_dma_desc *desc = &ch->dma.desc_base[ch->dma.desc];
426 if ((desc->ctl & (LTQ_DMA_OWN | LTQ_DMA_C)) == LTQ_DMA_C) {
427 ltq_vrx200_hw_receive(ch);
433 if (complete || !rx) {
434 napi_complete(&ch->napi);
435 spin_lock_irqsave(&priv->lock, flags);
436 ltq_dma_ack_irq(&ch->dma);
437 spin_unlock_irqrestore(&priv->lock, flags);
443 ltq_vrx200_poll_tx(struct napi_struct *napi, int budget)
445 struct ltq_vrx200_chan *ch =
446 container_of(napi, struct ltq_vrx200_chan, napi);
447 struct ltq_vrx200_priv *priv = netdev_priv(ch->netdev);
448 struct netdev_queue *txq =
449 netdev_get_tx_queue(ch->netdev, ch->idx >> 1);
452 spin_lock_irqsave(&priv->lock, flags);
453 while ((ch->dma.desc_base[ch->tx_free].ctl &
454 (LTQ_DMA_OWN | LTQ_DMA_C)) == LTQ_DMA_C) {
455 dev_kfree_skb_any(ch->skb[ch->tx_free]);
456 ch->skb[ch->tx_free] = NULL;
457 memset(&ch->dma.desc_base[ch->tx_free], 0,
458 sizeof(struct ltq_dma_desc));
460 ch->tx_free %= LTQ_DESC_NUM;
462 spin_unlock_irqrestore(&priv->lock, flags);
464 if (netif_tx_queue_stopped(txq))
465 netif_tx_start_queue(txq);
466 napi_complete(&ch->napi);
467 spin_lock_irqsave(&priv->lock, flags);
468 ltq_dma_ack_irq(&ch->dma);
469 spin_unlock_irqrestore(&priv->lock, flags);
474 ltq_vrx200_dma_irq(int irq, void *_priv)
476 struct ltq_vrx200_priv *priv = _priv;
477 int ch = irq - LTQ_DMA_ETOP;
479 napi_schedule(&priv->ch[ch].napi);
484 ltq_vrx200_free_channel(struct net_device *dev, struct ltq_vrx200_chan *ch)
486 struct ltq_vrx200_priv *priv = netdev_priv(dev);
488 ltq_dma_free(&ch->dma);
490 free_irq(ch->dma.irq, priv);
491 if (IS_RX(ch->idx)) {
493 for (desc = 0; desc < LTQ_DESC_NUM; desc++)
494 dev_kfree_skb_any(ch->skb[ch->dma.desc]);
499 ltq_vrx200_hw_exit(struct net_device *dev)
501 struct ltq_vrx200_priv *priv = netdev_priv(dev);
504 clk_disable(priv->clk_ppe);
506 for (i = 0; i < MAX_DMA_CHAN; i++)
507 if (IS_TX(i) || IS_RX(i))
508 ltq_vrx200_free_channel(dev, &priv->ch[i]);
511 static void *ltq_eth_phy_addr_reg(int num)
515 return <q_ethsw_mdio_pdi_regs->phy_addr_0;
517 return <q_ethsw_mdio_pdi_regs->phy_addr_1;
519 return <q_ethsw_mdio_pdi_regs->phy_addr_2;
521 return <q_ethsw_mdio_pdi_regs->phy_addr_3;
523 return <q_ethsw_mdio_pdi_regs->phy_addr_4;
525 return <q_ethsw_mdio_pdi_regs->phy_addr_5;
531 static void *ltq_eth_mii_cfg_reg(int num)
535 return <q_ethsw_mii_pdi_regs->mii_cfg0;
537 return <q_ethsw_mii_pdi_regs->mii_cfg1;
539 return <q_ethsw_mii_pdi_regs->mii_cfg2;
541 return <q_ethsw_mii_pdi_regs->mii_cfg3;
543 return <q_ethsw_mii_pdi_regs->mii_cfg4;
545 return <q_ethsw_mii_pdi_regs->mii_cfg5;
551 static void ltq_eth_gmac_update(struct phy_device *phydev, int num)
553 struct ltq_mdio_phy_addr_reg phy_addr_reg;
554 struct ltq_mii_mii_cfg_reg mii_cfg_reg;
555 void *phy_addr = ltq_eth_phy_addr_reg(num);
556 void *mii_cfg = ltq_eth_mii_cfg_reg(num);
558 phy_addr_reg.val = ltq_r32(phy_addr);
559 mii_cfg_reg.val = ltq_r32(mii_cfg);
561 phy_addr_reg.bits.addr = phydev->addr;
564 phy_addr_reg.bits.lnkst = LTQ_MDIO_PHY_ADDR_LNKST_UP;
566 phy_addr_reg.bits.lnkst = LTQ_MDIO_PHY_ADDR_LNKST_DOWN;
568 switch (phydev->speed) {
570 phy_addr_reg.bits.speed = LTQ_MDIO_PHY_ADDR_SPEED_G1;
571 mii_cfg_reg.bits.miirate = LTQ_MII_MII_CFG_MIIRATE_M125;
574 phy_addr_reg.bits.speed = LTQ_MDIO_PHY_ADDR_SPEED_M100;
575 switch (mii_cfg_reg.bits.miimode) {
576 case LTQ_MII_MII_CFG_MIIMODE_RMIIM:
577 case LTQ_MII_MII_CFG_MIIMODE_RMIIP:
578 mii_cfg_reg.bits.miirate = LTQ_MII_MII_CFG_MIIRATE_M50;
581 mii_cfg_reg.bits.miirate = LTQ_MII_MII_CFG_MIIRATE_M25;
586 phy_addr_reg.bits.speed = LTQ_MDIO_PHY_ADDR_SPEED_M10;
587 mii_cfg_reg.bits.miirate = LTQ_MII_MII_CFG_MIIRATE_M2P5;
591 if (phydev->duplex == DUPLEX_FULL)
592 phy_addr_reg.bits.fdup = LTQ_MDIO_PHY_ADDR_FDUP_ENABLE;
594 phy_addr_reg.bits.fdup = LTQ_MDIO_PHY_ADDR_FDUP_DISABLE;
596 dbg_ltq_writel(phy_addr, phy_addr_reg.val);
597 dbg_ltq_writel(mii_cfg, mii_cfg_reg.val);
602 static void ltq_eth_port_config(struct ltq_vrx200_priv *priv,
603 const struct ltq_eth_port_config *port)
605 struct ltq_mii_mii_cfg_reg mii_cfg_reg;
606 void *mii_cfg = ltq_eth_mii_cfg_reg(port->num);
609 mii_cfg_reg.val = ltq_r32(mii_cfg);
615 switch (port->phy_if) {
616 case PHY_INTERFACE_MODE_MII:
617 if (port->flags & LTQ_ETH_PORT_PHY)
618 /* MII MAC mode, connected to external PHY */
619 mii_cfg_reg.bits.miimode =
620 LTQ_MII_MII_CFG_MIIMODE_MIIM;
622 /* MII PHY mode, connected to external MAC */
623 mii_cfg_reg.bits.miimode =
624 LTQ_MII_MII_CFG_MIIMODE_MIIP;
627 case PHY_INTERFACE_MODE_RMII:
628 if (port->flags & LTQ_ETH_PORT_PHY)
629 /* RMII MAC mode, connected to external PHY */
630 mii_cfg_reg.bits.miimode =
631 LTQ_MII_MII_CFG_MIIMODE_RMIIM;
633 /* RMII PHY mode, connected to external MAC */
634 mii_cfg_reg.bits.miimode =
635 LTQ_MII_MII_CFG_MIIMODE_RMIIP;
638 case PHY_INTERFACE_MODE_RGMII:
639 /* RGMII MAC mode, connected to external PHY */
640 mii_cfg_reg.bits.miimode =
641 LTQ_MII_MII_CFG_MIIMODE_RGMII;
648 case 2: /* internal GPHY0 */
649 case 3: /* internal GPHY0 */
650 case 4: /* internal GPHY1 */
651 switch (port->phy_if) {
652 case PHY_INTERFACE_MODE_MII:
653 case PHY_INTERFACE_MODE_GMII:
654 /* MII MAC mode, connected to internal GPHY */
655 mii_cfg_reg.bits.miimode =
656 LTQ_MII_MII_CFG_MIIMODE_MIIM;
663 case 5: /* internal GPHY1 or xMII2 */
664 switch (port->phy_if) {
665 case PHY_INTERFACE_MODE_MII:
666 /* MII MAC mode, connected to internal GPHY */
667 mii_cfg_reg.bits.miimode =
668 LTQ_MII_MII_CFG_MIIMODE_MIIM;
671 case PHY_INTERFACE_MODE_RGMII:
672 /* RGMII MAC mode, connected to external PHY */
673 mii_cfg_reg.bits.miimode =
674 LTQ_MII_MII_CFG_MIIMODE_RGMII;
685 /* Enable MII interface */
686 mii_cfg_reg.bits.en = port->flags ? 1 : 0;
687 dbg_ltq_writel(mii_cfg, mii_cfg_reg.val);
691 static void ltq_eth_gmac_init(int num)
693 struct ltq_mdio_phy_addr_reg phy_addr_reg;
694 struct ltq_mii_mii_cfg_reg mii_cfg_reg;
695 void *phy_addr = ltq_eth_phy_addr_reg(num);
696 void *mii_cfg = ltq_eth_mii_cfg_reg(num);
697 struct ltq_ethsw_mac_pdi_x_regs *mac_pdi_regs;
699 mac_pdi_regs = <q_ethsw_mac_pdi_regs->mac[num];
701 /* Reset PHY status to link down */
702 phy_addr_reg.val = ltq_r32(phy_addr);
703 phy_addr_reg.bits.addr = num;
704 phy_addr_reg.bits.lnkst = LTQ_MDIO_PHY_ADDR_LNKST_DOWN;
705 phy_addr_reg.bits.speed = LTQ_MDIO_PHY_ADDR_SPEED_M10;
706 phy_addr_reg.bits.fdup = LTQ_MDIO_PHY_ADDR_FDUP_DISABLE;
707 dbg_ltq_writel(phy_addr, phy_addr_reg.val);
709 /* Reset and disable MII interface */
710 mii_cfg_reg.val = ltq_r32(mii_cfg);
711 mii_cfg_reg.bits.en = 0;
712 mii_cfg_reg.bits.res = 1;
713 mii_cfg_reg.bits.miirate = LTQ_MII_MII_CFG_MIIRATE_M2P5;
714 dbg_ltq_writel(mii_cfg, mii_cfg_reg.val);
717 * Enable padding of short frames, enable frame checksum generation
718 * in transmit direction
720 dbg_ltq_writel(&mac_pdi_regs->ctrl_0, LTQ_ETHSW_MAC_CTRL0_PADEN |
721 LTQ_ETHSW_MAC_CTRL0_FCS);
723 /* Set inter packet gap size to 12 bytes */
724 dbg_ltq_writel(&mac_pdi_regs->ctrl_1, 12);
727 * Configure frame length checks:
728 * - allow jumbo frames
729 * - enable long length check
730 * - enable short length without VLAN tags
732 dbg_ltq_writel(&mac_pdi_regs->ctrl_2, LTQ_ETHSW_MAC_CTRL2_MLEN |
733 LTQ_ETHSW_MAC_CTRL2_LCHKL |
734 LTQ_ETHSW_MAC_CTRL2_LCHKS_UNTAG);
738 static void ltq_eth_pmac_init(void)
740 struct ltq_ethsw_mac_pdi_x_regs *mac_pdi_regs;
742 mac_pdi_regs = <q_ethsw_mac_pdi_regs->mac[LTQ_ETHSW_PMAC];
745 * Enable padding of short frames, enable frame checksum generation
746 * in transmit direction
748 dbg_ltq_writel(&mac_pdi_regs->ctrl_0, LTQ_ETHSW_MAC_CTRL0_PADEN |
749 LTQ_ETHSW_MAC_CTRL0_FCS);
752 * Configure frame length checks:
753 * - allow jumbo frames
754 * - enable long length check
755 * - enable short length without VLAN tags
757 dbg_ltq_writel(&mac_pdi_regs->ctrl_2, LTQ_ETHSW_MAC_CTRL2_MLEN |
758 LTQ_ETHSW_MAC_CTRL2_LCHKL |
759 LTQ_ETHSW_MAC_CTRL2_LCHKS_UNTAG);
762 * Apply workaround for buffer congestion:
763 * - shorten preambel to 1 byte
764 * - set minimum inter packet gap size to 7 bytes
765 * - enable receive buffer bypass mode
767 dbg_ltq_writel(&mac_pdi_regs->ctrl_1, LTQ_ETHSW_MAC_CTRL1_SHORTPRE | 7);
768 dbg_ltq_writel(&mac_pdi_regs->ctrl_6,
769 (6 << LTQ_ETHSW_MAC_CTRL6_RBUF_DLY_WP_SHIFT) |
770 LTQ_ETHSW_MAC_CTRL6_RXBUF_BYPASS);
772 /* Set request assertion threshold to 8, IPG counter to 11 */
773 dbg_ltq_writel(<q_ethsw_pmac_pdi_regs->rx_ipg, 0x8B);
776 * Configure frame header control:
777 * - enable reaction on pause frames (flow control)
778 * - remove CRC for packets from PMAC to DMA
779 * - add CRC for packets from DMA to PMAC
781 dbg_ltq_writel(<q_ethsw_pmac_pdi_regs->hd_ctl, LTQ_ETHSW_PMAC_HD_CTL_FC |
782 /*LTQ_ETHSW_PMAC_HD_CTL_RC | */LTQ_ETHSW_PMAC_HD_CTL_AC);
786 ltq_vrx200_hw_init(struct net_device *dev)
788 struct ltq_vrx200_priv *priv = netdev_priv(dev);
792 netdev_info(dev, "setting up dma\n");
793 ltq_dma_init_port(DMA_PORT_ETOP);
795 netdev_info(dev, "setting up pmu\n");
796 clk_enable(priv->clk_ppe);
798 /* Reset ethernet and switch subsystems */
799 netdev_info(dev, "reset core\n");
800 ltq_reset_once(BIT(8), 10);
802 /* Enable switch macro */
803 ltq_setbits(<q_ethsw_mdio_pdi_regs->glob_ctrl,
804 LTQ_ETHSW_GLOB_CTRL_SE);
806 /* Disable MDIO auto-polling for all ports */
807 dbg_ltq_writel(<q_ethsw_mdio_pdi_regs->mdc_cfg_0, 0);
810 * Enable and set MDIO management clock to 2.5 MHz. This is the
811 * maximum clock for FE PHYs.
812 * Formula for clock is:
815 * x = ----------- - 1
818 dbg_ltq_writel(<q_ethsw_mdio_pdi_regs->mdc_cfg_1,
819 LTQ_ETHSW_MDC_CFG1_MCEN | 9);
821 /* Init MAC connected to CPU */
824 /* Init MACs connected to external MII interfaces */
825 for (i = 0; i < LTQ_ETHSW_MAX_GMAC; i++)
826 ltq_eth_gmac_init(i);
828 for (i = 0; i < MAX_DMA_CHAN && !err; i++) {
829 int irq = LTQ_DMA_ETOP + i;
830 struct ltq_vrx200_chan *ch = &priv->ch[i];
832 ch->idx = ch->dma.nr = i;
835 ltq_dma_alloc_tx(&ch->dma);
836 err = request_irq(irq, ltq_vrx200_dma_irq, IRQF_DISABLED,
838 } else if (IS_RX(i)) {
839 ltq_dma_alloc_rx(&ch->dma);
840 for (ch->dma.desc = 0; ch->dma.desc < LTQ_DESC_NUM;
842 if (ltq_vrx200_alloc_skb(ch))
845 err = request_irq(irq, ltq_vrx200_dma_irq, IRQF_DISABLED,
851 for (i = 0; i < board_config.num_ports; i++)
852 ltq_eth_port_config(priv, &board_config.ports[i]);
857 ltq_vrx200_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
859 strcpy(info->driver, "Lantiq ETOP");
860 strcpy(info->bus_info, "internal");
861 strcpy(info->version, DRV_VERSION);
865 ltq_vrx200_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
867 struct ltq_vrx200_priv *priv = netdev_priv(dev);
869 return phy_ethtool_gset(priv->phydev, cmd);
873 ltq_vrx200_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
875 struct ltq_vrx200_priv *priv = netdev_priv(dev);
877 return phy_ethtool_sset(priv->phydev, cmd);
881 ltq_vrx200_nway_reset(struct net_device *dev)
883 struct ltq_vrx200_priv *priv = netdev_priv(dev);
885 return phy_start_aneg(priv->phydev);
888 static const struct ethtool_ops ltq_vrx200_ethtool_ops = {
889 .get_drvinfo = ltq_vrx200_get_drvinfo,
890 .get_settings = ltq_vrx200_get_settings,
891 .set_settings = ltq_vrx200_set_settings,
892 .nway_reset = ltq_vrx200_nway_reset,
895 static inline int ltq_mdio_poll(struct mii_bus *bus)
897 struct ltq_mdio_access acc;
898 unsigned cnt = 10000;
900 while (likely(cnt--)) {
901 acc.val = ltq_r32(<q_ethsw_mdio_pdi_regs->mdio_ctrl);
910 ltq_vrx200_mdio_wr(struct mii_bus *bus, int addr, int regnum, u16 val)
912 struct ltq_mdio_access acc;
916 acc.bits.mbusy = LTQ_MDIO_MBUSY_BUSY;
917 acc.bits.op = LTQ_MDIO_OP_WRITE;
918 acc.bits.phyad = addr;
919 acc.bits.regad = regnum;
921 ret = ltq_mdio_poll(bus);
925 dbg_ltq_writel(<q_ethsw_mdio_pdi_regs->mdio_write, val);
926 dbg_ltq_writel(<q_ethsw_mdio_pdi_regs->mdio_ctrl, acc.val);
932 ltq_vrx200_mdio_rd(struct mii_bus *bus, int addr, int regnum)
934 struct ltq_mdio_access acc;
938 acc.bits.mbusy = LTQ_MDIO_MBUSY_BUSY;
939 acc.bits.op = LTQ_MDIO_OP_READ;
940 acc.bits.phyad = addr;
941 acc.bits.regad = regnum;
943 ret = ltq_mdio_poll(bus);
947 dbg_ltq_writel(<q_ethsw_mdio_pdi_regs->mdio_ctrl, acc.val);
949 ret = ltq_mdio_poll(bus);
953 ret = ltq_r32(<q_ethsw_mdio_pdi_regs->mdio_read);
961 ltq_vrx200_mdio_link(struct net_device *dev)
963 struct ltq_vrx200_priv *priv = netdev_priv(dev);
964 ltq_eth_gmac_update(priv->phydev, 0);
968 ltq_vrx200_mdio_probe(struct net_device *dev)
970 struct ltq_vrx200_priv *priv = netdev_priv(dev);
971 struct phy_device *phydev = NULL;
974 phydev = priv->mii_bus->phy_map[0];
977 netdev_err(dev, "no PHY found\n");
981 phydev = phy_connect(dev, dev_name(&phydev->dev), <q_vrx200_mdio_link,
984 if (IS_ERR(phydev)) {
985 netdev_err(dev, "Could not attach to PHY\n");
986 return PTR_ERR(phydev);
989 phydev->supported &= (SUPPORTED_10baseT_Half
990 | SUPPORTED_10baseT_Full
991 | SUPPORTED_100baseT_Half
992 | SUPPORTED_100baseT_Full
993 | SUPPORTED_1000baseT_Half
994 | SUPPORTED_1000baseT_Full
998 phydev->advertising = phydev->supported;
999 priv->phydev = phydev;
1001 pr_info("%s: attached PHY [%s] (phy_addr=%s, irq=%d)\n",
1002 dev->name, phydev->drv->name,
1003 dev_name(&phydev->dev), phydev->irq);
1005 val = ltq_vrx200_mdio_rd(priv->mii_bus, MDIO_DEVAD_NONE, MII_CTRL1000);
1006 val |= ADVERTIZE_MPD;
1007 ltq_vrx200_mdio_wr(priv->mii_bus, MDIO_DEVAD_NONE, MII_CTRL1000, val);
1008 ltq_vrx200_mdio_wr(priv->mii_bus, 0, 0, 0x1040);
1010 phy_start_aneg(phydev);
1016 ltq_vrx200_mdio_init(struct net_device *dev)
1018 struct ltq_vrx200_priv *priv = netdev_priv(dev);
1022 priv->mii_bus = mdiobus_alloc();
1023 if (!priv->mii_bus) {
1024 netdev_err(dev, "failed to allocate mii bus\n");
1029 priv->mii_bus->priv = dev;
1030 priv->mii_bus->read = ltq_vrx200_mdio_rd;
1031 priv->mii_bus->write = ltq_vrx200_mdio_wr;
1032 priv->mii_bus->name = "ltq_mii";
1033 snprintf(priv->mii_bus->id, MII_BUS_ID_SIZE, "%x", 0);
1034 priv->mii_bus->irq = kmalloc(sizeof(int) * PHY_MAX_ADDR, GFP_KERNEL);
1035 if (!priv->mii_bus->irq) {
1037 goto err_out_free_mdiobus;
1040 for (i = 0; i < PHY_MAX_ADDR; ++i)
1041 priv->mii_bus->irq[i] = PHY_POLL;
1043 if (mdiobus_register(priv->mii_bus)) {
1045 goto err_out_free_mdio_irq;
1048 if (ltq_vrx200_mdio_probe(dev)) {
1050 goto err_out_unregister_bus;
1054 err_out_unregister_bus:
1055 mdiobus_unregister(priv->mii_bus);
1056 err_out_free_mdio_irq:
1057 kfree(priv->mii_bus->irq);
1058 err_out_free_mdiobus:
1059 mdiobus_free(priv->mii_bus);
1065 ltq_vrx200_mdio_cleanup(struct net_device *dev)
1067 struct ltq_vrx200_priv *priv = netdev_priv(dev);
1069 phy_disconnect(priv->phydev);
1070 mdiobus_unregister(priv->mii_bus);
1071 kfree(priv->mii_bus->irq);
1072 mdiobus_free(priv->mii_bus);
1075 void phy_dump(struct net_device *dev)
1077 struct ltq_vrx200_priv *priv = netdev_priv(dev);
1079 for (i = 0; i < 0x1F; i++) {
1080 unsigned int val = ltq_vrx200_mdio_rd(priv->mii_bus, 0, i);
1081 printk("%d %4X\n", i, val);
1086 ltq_vrx200_open(struct net_device *dev)
1088 struct ltq_vrx200_priv *priv = netdev_priv(dev);
1090 unsigned long flags;
1092 for (i = 0; i < MAX_DMA_CHAN; i++) {
1093 struct ltq_vrx200_chan *ch = &priv->ch[i];
1095 if (!IS_TX(i) && (!IS_RX(i)))
1097 napi_enable(&ch->napi);
1098 spin_lock_irqsave(&priv->lock, flags);
1099 ltq_dma_open(&ch->dma);
1100 spin_unlock_irqrestore(&priv->lock, flags);
1103 phy_start(priv->phydev);
1106 netif_tx_start_all_queues(dev);
1111 ltq_vrx200_stop(struct net_device *dev)
1113 struct ltq_vrx200_priv *priv = netdev_priv(dev);
1115 unsigned long flags;
1117 netif_tx_stop_all_queues(dev);
1119 phy_stop(priv->phydev);
1120 for (i = 0; i < MAX_DMA_CHAN; i++) {
1121 struct ltq_vrx200_chan *ch = &priv->ch[i];
1123 if (!IS_RX(i) && !IS_TX(i))
1125 napi_disable(&ch->napi);
1126 spin_lock_irqsave(&priv->lock, flags);
1127 ltq_dma_close(&ch->dma);
1128 spin_unlock_irqrestore(&priv->lock, flags);
1134 ltq_vrx200_tx(struct sk_buff *skb, struct net_device *dev)
1136 int queue = skb_get_queue_mapping(skb);
1137 struct netdev_queue *txq = netdev_get_tx_queue(dev, queue);
1138 struct ltq_vrx200_priv *priv = netdev_priv(dev);
1139 struct ltq_vrx200_chan *ch = &priv->ch[(queue << 1) | 1];
1140 struct ltq_dma_desc *desc = &ch->dma.desc_base[ch->dma.desc];
1141 unsigned long flags;
1145 len = skb->len < ETH_ZLEN ? ETH_ZLEN : skb->len;
1147 if ((desc->ctl & (LTQ_DMA_OWN | LTQ_DMA_C)) || ch->skb[ch->dma.desc]) {
1148 netdev_err(dev, "tx ring full\n");
1149 netif_tx_stop_queue(txq);
1150 return NETDEV_TX_BUSY;
1153 /* dma needs to start on a 16 byte aligned address */
1154 byte_offset = CPHYSADDR(skb->data) % 16;
1155 ch->skb[ch->dma.desc] = skb;
1157 dev->trans_start = jiffies;
1159 spin_lock_irqsave(&priv->lock, flags);
1160 desc->addr = ((unsigned int) dma_map_single(NULL, skb->data, len,
1161 DMA_TO_DEVICE)) - byte_offset;
1163 desc->ctl = LTQ_DMA_OWN | LTQ_DMA_SOP | LTQ_DMA_EOP |
1164 LTQ_DMA_TX_OFFSET(byte_offset) | (len & LTQ_DMA_SIZE_MASK);
1166 ch->dma.desc %= LTQ_DESC_NUM;
1167 spin_unlock_irqrestore(&priv->lock, flags);
1169 if (ch->dma.desc_base[ch->dma.desc].ctl & LTQ_DMA_OWN)
1170 netif_tx_stop_queue(txq);
1172 return NETDEV_TX_OK;
1176 ltq_vrx200_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
1178 struct ltq_vrx200_priv *priv = netdev_priv(dev);
1180 /* TODO: mii-toll reports "No MII transceiver present!." ?!*/
1181 return phy_mii_ioctl(priv->phydev, rq, cmd);
1185 ltq_vrx200_select_queue(struct net_device *dev, struct sk_buff *skb)
1187 /* we are currently only using the first queue */
1192 ltq_vrx200_init(struct net_device *dev)
1194 struct ltq_vrx200_priv *priv = netdev_priv(dev);
1195 struct sockaddr mac;
1199 dev->watchdog_timeo = 10 * HZ;
1201 err = ltq_vrx200_hw_init(dev);
1205 memcpy(&mac, &priv->pldata->mac, sizeof(struct sockaddr));
1206 if (!is_valid_ether_addr(mac.sa_data)) {
1207 pr_warn("vrx200: invalid MAC, using random\n");
1208 random_ether_addr(mac.sa_data);
1210 eth_mac_addr(dev, &mac);
1212 if (!ltq_vrx200_mdio_init(dev))
1213 dev->ethtool_ops = <q_vrx200_ethtool_ops;
1215 pr_warn("vrx200: mdio probe failed\n");;
1219 ltq_vrx200_hw_exit(dev);
1224 ltq_vrx200_tx_timeout(struct net_device *dev)
1228 ltq_vrx200_hw_exit(dev);
1229 err = ltq_vrx200_hw_init(dev);
1232 dev->trans_start = jiffies;
1233 netif_wake_queue(dev);
1237 ltq_vrx200_hw_exit(dev);
1238 netdev_err(dev, "failed to restart vrx200 after TX timeout\n");
1241 static const struct net_device_ops ltq_eth_netdev_ops = {
1242 .ndo_open = ltq_vrx200_open,
1243 .ndo_stop = ltq_vrx200_stop,
1244 .ndo_start_xmit = ltq_vrx200_tx,
1245 .ndo_change_mtu = eth_change_mtu,
1246 .ndo_do_ioctl = ltq_vrx200_ioctl,
1247 .ndo_set_mac_address = eth_mac_addr,
1248 .ndo_validate_addr = eth_validate_addr,
1249 .ndo_select_queue = ltq_vrx200_select_queue,
1250 .ndo_init = ltq_vrx200_init,
1251 .ndo_tx_timeout = ltq_vrx200_tx_timeout,
1254 static int __devinit
1255 ltq_vrx200_probe(struct platform_device *pdev)
1257 struct net_device *dev;
1258 struct ltq_vrx200_priv *priv;
1259 struct resource *res;
1263 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1265 dev_err(&pdev->dev, "failed to get vrx200 resource\n");
1270 res = devm_request_mem_region(&pdev->dev, res->start,
1271 resource_size(res), dev_name(&pdev->dev));
1273 dev_err(&pdev->dev, "failed to request vrx200 resource\n");
1278 ltq_vrx200_membase = devm_ioremap_nocache(&pdev->dev,
1279 res->start, resource_size(res));
1280 if (!ltq_vrx200_membase) {
1281 dev_err(&pdev->dev, "failed to remap vrx200 engine %d\n",
1287 if (ltq_gpio_request(&pdev->dev, 42, 2, 1, "MDIO") ||
1288 ltq_gpio_request(&pdev->dev, 43, 2, 1, "MDC")) {
1289 dev_err(&pdev->dev, "failed to request MDIO gpios\n");
1294 dev = alloc_etherdev_mq(sizeof(struct ltq_vrx200_priv), 4);
1295 strcpy(dev->name, "eth%d");
1296 dev->netdev_ops = <q_eth_netdev_ops;
1297 priv = netdev_priv(dev);
1299 priv->pldata = dev_get_platdata(&pdev->dev);
1302 priv->clk_ppe = clk_get(&pdev->dev, NULL);
1303 if (IS_ERR(priv->clk_ppe))
1304 return PTR_ERR(priv->clk_ppe);
1306 spin_lock_init(&priv->lock);
1308 for (i = 0; i < MAX_DMA_CHAN; i++) {
1310 netif_napi_add(dev, &priv->ch[i].napi,
1311 ltq_vrx200_poll_tx, 8);
1313 netif_napi_add(dev, &priv->ch[i].napi,
1314 ltq_vrx200_poll_rx, 32);
1315 priv->ch[i].netdev = dev;
1318 err = register_netdev(dev);
1322 platform_set_drvdata(pdev, dev);
1331 static int __devexit
1332 ltq_vrx200_remove(struct platform_device *pdev)
1334 struct net_device *dev = platform_get_drvdata(pdev);
1337 netif_tx_stop_all_queues(dev);
1338 ltq_vrx200_hw_exit(dev);
1339 ltq_vrx200_mdio_cleanup(dev);
1340 unregister_netdev(dev);
1345 static struct platform_driver ltq_mii_driver = {
1346 .probe = ltq_vrx200_probe,
1347 .remove = __devexit_p(ltq_vrx200_remove),
1349 .name = "ltq_vrx200",
1350 .owner = THIS_MODULE,
1354 module_platform_driver(ltq_mii_driver);
1356 MODULE_AUTHOR("John Crispin <blogic@openwrt.org>");
1357 MODULE_DESCRIPTION("Lantiq SoC ETOP");
1358 MODULE_LICENSE("GPL");