target/linux/ipq806x/patches-3.18/110-DT-PCI-qcom-Document-PCIe-devicetree-bindings.patch

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   4 Subject: [v2,3/5] DT: PCI: qcom: Document PCIe devicetree bindings
   5 From: Stanimir Varbanov <svarbanov@mm-sol.com>
   6 X-Patchwork-Id: 6326181
   7 Message-Id: <1430743338-10441-4-git-send-email-svarbanov@mm-sol.com>
   8 To: Rob Herring <robh+dt@kernel.org>, Kumar Gala <galak@codeaurora.org>,
   9         Mark Rutland <mark.rutland@arm.com>,
  10         Grant Likely <grant.likely@linaro.org>,
  11         Bjorn Helgaas <bhelgaas@google.com>,
  12         Kishon Vijay Abraham I <kishon@ti.com>,
  13         Russell King <linux@arm.linux.org.uk>, Arnd Bergmann <arnd@arndb.de>
  14 Cc: linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org,
  15         linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org,
  16         linux-pci@vger.kernel.org, Mathieu Olivari <mathieu@codeaurora.org>,
  17         Srinivas Kandagatla <srinivas.kandagatla@linaro.org>,
  18         Stanimir Varbanov <svarbanov@mm-sol.com>
  19 Date: Mon,  4 May 2015 15:42:16 +0300
  20
  21 Document Qualcomm PCIe driver devicetree bindings.
  22
  23 Signed-off-by: Stanimir Varbanov <svarbanov@mm-sol.com>
  24
  25 ---
  26 .../devicetree/bindings/pci/qcom,pcie.txt          |  231 ++++++++++++++++++++
  27  1 files changed, 231 insertions(+), 0 deletions(-)
  28  create mode 100644 Documentation/devicetree/bindings/pci/qcom,pcie.txt
  29
  30 diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.txt b/Documentation/devicetree/bindings/pci/qcom,pcie.txt
  31 new file mode 100644
  32 index 0000000..dcf7348
  33 --- /dev/null
  34 +++ b/Documentation/devicetree/bindings/pci/qcom,pcie.txt
  35 @@ -0,0 +1,231 @@
  36 +* Qualcomm PCI express root complex
  37 +
  38 +- compatible:
  39 +       Usage: required
  40 +       Value type: <stringlist>
  41 +       Definition: Value shall include
  42 +                   - "qcom,pcie-v0" for apq/ipq8064
  43 +                   - "qcom,pcie-v1" for apq8084
  44 +
  45 +- reg:
  46 +       Usage: required
  47 +       Value type: <prop-encoded-array>
  48 +       Definition: Register ranges as listed in the reg-names property
  49 +
  50 +- reg-names:
  51 +       Usage: required
  52 +       Value type: <stringlist>
  53 +       Definition: Must include the following entries
  54 +                   - "parf"   Qualcomm specific registers
  55 +                   - "dbi"    Designware PCIe registers
  56 +                   - "elbi"   External local bus interface registers
  57 +                   - "config" PCIe configuration space
  58 +
  59 +- device_type:
  60 +       Usage: required
  61 +       Value type: <string>
  62 +       Definition: Should be "pci". As specified in designware-pcie.txt
  63 +
  64 +- #address-cells:
  65 +       Usage: required
  66 +       Value type: <u32>
  67 +       Definition: Should be set to 3. As specified in designware-pcie.txt
  68 +
  69 +- #size-cells:
  70 +       Usage: required
  71 +       Value type: <u32>
  72 +       Definition: Should be set 2. As specified in designware-pcie.txt
  73 +
  74 +- ranges:
  75 +       Usage: required
  76 +       Value type: <prop-encoded-array>
  77 +       Definition: As specified in designware-pcie.txt
  78 +
  79 +- interrupts:
  80 +       Usage: required
  81 +       Value type: <prop-encoded-array>
  82 +       Definition: MSI interrupt
  83 +
  84 +- interrupt-names:
  85 +       Usage: required
  86 +       Value type: <stringlist>
  87 +       Definition: Should contain "msi"
  88 +
  89 +- #interrupt-cells:
  90 +       Usage: required
  91 +       Value type: <u32>
  92 +       Definition: Should be 1. As specified in designware-pcie.txt
  93 +
  94 +- interrupt-map-mask:
  95 +       Usage: required
  96 +       Value type: <prop-encoded-array>
  97 +       Definition: As specified in designware-pcie.txt
  98 +
  99 +- interrupt-map:
 100 +       Usage: required
 101 +       Value type: <prop-encoded-array>
 102 +       Definition: As specified in designware-pcie.txt
 103 +
 104 +- clocks:
 105 +       Usage: required
 106 +       Value type: <prop-encoded-array>
 107 +       Definition: List of phandle and clock specifier pairs as listed
 108 +                   in clock-names property
 109 +
 110 +- clock-names:
 111 +       Usage: required
 112 +       Value type: <stringlist>
 113 +       Definition: Should contain the following entries
 114 +                   * should be populated for v0 and v1
 115 +                       - "iface"      Configuration AHB clock
 116 +
 117 +                   * should be populated for v0
 118 +                       - "core"       Clocks the pcie hw block
 119 +                       - "phy"        Clocks the pcie PHY block
 120 +
 121 +                   * should be populated for v1
 122 +                       - "aux"        Auxiliary (AUX) clock
 123 +                       - "bus_master" Master AXI clock
 124 +                       - "bus_slave"  Slave AXI clock
 125 +
 126 +- resets:
 127 +       Usage: required
 128 +       Value type: <prop-encoded-array>
 129 +       Definition: List of phandle and reset specifier pairs as listed
 130 +                   in reset-names property
 131 +
 132 +- reset-names:
 133 +       Usage: required
 134 +       Value type: <stringlist>
 135 +       Definition: Should contain the following entries
 136 +                   * should be populated for v0
 137 +                       - "axi"  AXI reset
 138 +                       - "ahb"  AHB reset
 139 +                       - "por"  POR reset
 140 +                       - "pci"  PCI reset
 141 +                       - "phy"  PHY reset
 142 +
 143 +                   * should be populated for v1
 144 +                       - "core" Core reset
 145 +
 146 +- power-domains:
 147 +       Usage: required (for v1 only)
 148 +       Value type: <prop-encoded-array>
 149 +       Definition: A phandle and power domain specifier pair to the
 150 +                   power domain which is responsible for collapsing
 151 +                   and restoring power to the peripheral
 152 +
 153 +- <name>-supply:
 154 +       Usage: required
 155 +       Value type: <phandle>
 156 +       Definition: List of phandles to the power supply regulator(s)
 157 +                   * should be populated for v0 and v1
 158 +                       - "vdda"        core analog power supply
 159 +
 160 +                   * should be populated for v0
 161 +                       - "vdda_phy"    analog power supply for PHY
 162 +                       - "vdda_refclk" analog power supply for IC which generate
 163 +                                       reference clock
 164 +
 165 +- phys:
 166 +       Usage: required (for v1 only)
 167 +       Value type: <phandle>
 168 +       Definition: List of phandle(s) as listed in phy-names property
 169 +
 170 +- phy-names:
 171 +       Usage: required (for v1 only)
 172 +       Value type: <stringlist>
 173 +       Definition: Should contain "pciephy"
 174 +
 175 +- <name>-gpio:
 176 +       Usage: optional
 177 +       Value type: <prop-encoded-array>
 178 +       Definition: List of phandle and gpio specifier pairs. Should contain
 179 +                   - "perst"  PCIe endpoint reset signal line
 180 +                   - "pewake" PCIe endpoint wake signal line
 181 +
 182 +- pinctrl-0:
 183 +       Usage: required
 184 +       Value type: <phandle>
 185 +       Definition: List of phandles pointing at a pin(s) configuration
 186 +
 187 +- pinctrl-names
 188 +       Usage: required
 189 +       Value type: <stringlist>
 190 +       Definition: List of names of pinctrl-0 state
 191 +
 192 +* Example for v0
 193 +       pcie0: pci@1b500000 {
 194 +               compatible = "qcom,pcie-v0";
 195 +               reg = <0x1b500000 0x1000
 196 +                      0x1b502000 0x80
 197 +                      0x1b600000 0x100
 198 +                      0x0ff00000 0x100000>;
 199 +               reg-names = "dbi", "elbi", "parf", "config";
 200 +               device_type = "pci";
 201 +               linux,pci-domain = <0>;
 202 +               bus-range = <0x00 0xff>;
 203 +               num-lanes = <1>;
 204 +               #address-cells = <3>;
 205 +               #size-cells = <2>;
 206 +               ranges = <0x81000000 0 0          0x0fe00000 0 0x00100000   /* I/O */
 207 +                         0x82000000 0 0x00000000 0x08000000 0 0x07e00000>; /* memory */
 208 +               interrupts = <GIC_SPI 35 IRQ_TYPE_NONE>;
 209 +               interrupt-names = "msi";
 210 +               #interrupt-cells = <1>;
 211 +               interrupt-map-mask = <0 0 0 0x7>;
 212 +               interrupt-map = <0 0 0 1 &intc 0 36 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
 213 +                               <0 0 0 2 &intc 0 37 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
 214 +                               <0 0 0 3 &intc 0 38 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
 215 +                               <0 0 0 4 &intc 0 39 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
 216 +               clocks = <&gcc PCIE_A_CLK>,
 217 +                        <&gcc PCIE_H_CLK>,
 218 +                        <&gcc PCIE_PHY_CLK>;
 219 +               clock-names = "core", "iface", "phy";
 220 +               resets = <&gcc PCIE_ACLK_RESET>,
 221 +                        <&gcc PCIE_HCLK_RESET>,
 222 +                        <&gcc PCIE_POR_RESET>,
 223 +                        <&gcc PCIE_PCI_RESET>,
 224 +                        <&gcc PCIE_PHY_RESET>;
 225 +               reset-names = "axi", "ahb", "por", "pci", "phy";
 226 +       };
 227 +
 228 +* Example for v1
 229 +       pcie0@fc520000 {
 230 +               compatible = "qcom,pcie-v1";
 231 +               reg = <0xfc520000 0x2000>,
 232 +                     <0xff000000 0x1000>,
 233 +                     <0xff001000 0x1000>,
 234 +                     <0xff002000 0x2000>;
 235 +               reg-names = "parf", "dbi", "elbi", "config";
 236 +               device_type = "pci";
 237 +               linux,pci-domain = <0>;
 238 +               bus-range = <0x00 0xff>;
 239 +               num-lanes = <1>;
 240 +               #address-cells = <3>;
 241 +               #size-cells = <2>;
 242 +               ranges = <0x81000000 0 0          0xff200000 0 0x00100000   /* I/O */
 243 +                         0x82000000 0 0x00300000 0xff300000 0 0x00d00000>; /* memory */
 244 +               interrupts = <GIC_SPI 243 IRQ_TYPE_NONE>;
 245 +               interrupt-names = "msi";
 246 +               #interrupt-cells = <1>;
 247 +               interrupt-map-mask = <0 0 0 0x7>;
 248 +               interrupt-map = <0 0 0 1 &intc 0 244 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
 249 +                               <0 0 0 2 &intc 0 245 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
 250 +                               <0 0 0 3 &intc 0 247 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
 251 +                               <0 0 0 4 &intc 0 248 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
 252 +               clocks = <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
 253 +                        <&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
 254 +                        <&gcc GCC_PCIE_0_SLV_AXI_CLK>,
 255 +                        <&gcc GCC_PCIE_0_AUX_CLK>;
 256 +               clock-names = "iface", "master_bus", "slave_bus", "aux";
 257 +               resets = <&gcc GCC_PCIE_0_BCR>;
 258 +               reset-names = "core";
 259 +               power-domains = <&gcc PCIE0_GDSC>;
 260 +               vdda-supply = <&pma8084_l3>;
 261 +               phys = <&pciephy0>;
 262 +               phy-names = "pciephy";
 263 +               perst-gpio = <&tlmm 70 GPIO_ACTIVE_LOW>;
 264 +               pinctrl-0 = <&pcie0_pins_default>;
 265 +               pinctrl-names = "default";
 266 +       };