target/linux/generic/patches-3.3/020-ssb_update.patch

   1 --- a/drivers/ssb/b43_pci_bridge.c
   2 +++ b/drivers/ssb/b43_pci_bridge.c
   3 @@ -29,11 +29,15 @@ static const struct pci_device_id b43_pc
   4         { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4319) },
   5         { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4320) },
   6         { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4321) },
   7 +       { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4322) },
   8 +       { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 43222) },
   9         { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4324) },
  10         { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4325) },
  11         { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4328) },
  12         { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4329) },
  13         { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x432b) },
  14 +       { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x432c) },
  15 +       { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4350) },
  16         { 0, },
  17  };
  18  MODULE_DEVICE_TABLE(pci, b43_pci_bridge_tbl);
  19 --- a/drivers/ssb/driver_chipcommon.c
  20 +++ b/drivers/ssb/driver_chipcommon.c
  21 @@ -4,6 +4,7 @@
  22   *
  23   * Copyright 2005, Broadcom Corporation
  24   * Copyright 2006, 2007, Michael Buesch <m@bues.ch>
  25 + * Copyright 2012, Hauke Mehrtens <hauke@hauke-m.de>
  26   *
  27   * Licensed under the GNU/GPL. See COPYING for details.
  28   */
  29 @@ -12,6 +13,7 @@
  30  #include <linux/ssb/ssb_regs.h>
  31  #include <linux/export.h>
  32  #include <linux/pci.h>
  33 +#include <linux/bcm47xx_wdt.h>
  34
  35  #include "ssb_private.h"
  36
  37 @@ -280,6 +282,69 @@ static void calc_fast_powerup_delay(stru
  38         cc->fast_pwrup_delay = tmp;
  39  }
  40
  41 +static u32 ssb_chipco_alp_clock(struct ssb_chipcommon *cc)
  42 +{
  43 +       if (cc->capabilities & SSB_CHIPCO_CAP_PMU)
  44 +               return ssb_pmu_get_alp_clock(cc);
  45 +
  46 +       return 20000000;
  47 +}
  48 +
  49 +static u32 ssb_chipco_watchdog_get_max_timer(struct ssb_chipcommon *cc)
  50 +{
  51 +       u32 nb;
  52 +
  53 +       if (cc->capabilities & SSB_CHIPCO_CAP_PMU) {
  54 +               if (cc->dev->id.revision < 26)
  55 +                       nb = 16;
  56 +               else
  57 +                       nb = (cc->dev->id.revision >= 37) ? 32 : 24;
  58 +       } else {
  59 +               nb = 28;
  60 +       }
  61 +       if (nb == 32)
  62 +               return 0xffffffff;
  63 +       else
  64 +               return (1 << nb) - 1;
  65 +}
  66 +
  67 +u32 ssb_chipco_watchdog_timer_set_wdt(struct bcm47xx_wdt *wdt, u32 ticks)
  68 +{
  69 +       struct ssb_chipcommon *cc = bcm47xx_wdt_get_drvdata(wdt);
  70 +
  71 +       if (cc->dev->bus->bustype != SSB_BUSTYPE_SSB)
  72 +               return 0;
  73 +
  74 +       return ssb_chipco_watchdog_timer_set(cc, ticks);
  75 +}
  76 +
  77 +u32 ssb_chipco_watchdog_timer_set_ms(struct bcm47xx_wdt *wdt, u32 ms)
  78 +{
  79 +       struct ssb_chipcommon *cc = bcm47xx_wdt_get_drvdata(wdt);
  80 +       u32 ticks;
  81 +
  82 +       if (cc->dev->bus->bustype != SSB_BUSTYPE_SSB)
  83 +               return 0;
  84 +
  85 +       ticks = ssb_chipco_watchdog_timer_set(cc, cc->ticks_per_ms * ms);
  86 +       return ticks / cc->ticks_per_ms;
  87 +}
  88 +
  89 +static int ssb_chipco_watchdog_ticks_per_ms(struct ssb_chipcommon *cc)
  90 +{
  91 +       struct ssb_bus *bus = cc->dev->bus;
  92 +
  93 +       if (cc->capabilities & SSB_CHIPCO_CAP_PMU) {
  94 +                       /* based on 32KHz ILP clock */
  95 +                       return 32;
  96 +       } else {
  97 +               if (cc->dev->id.revision < 18)
  98 +                       return ssb_clockspeed(bus) / 1000;
  99 +               else
 100 +                       return ssb_chipco_alp_clock(cc) / 1000;
 101 +       }
 102 +}
 103 +
 104  void ssb_chipcommon_init(struct ssb_chipcommon *cc)
 105  {
 106         if (!cc->dev)
 107 @@ -297,6 +362,11 @@ void ssb_chipcommon_init(struct ssb_chip
 108         chipco_powercontrol_init(cc);
 109         ssb_chipco_set_clockmode(cc, SSB_CLKMODE_FAST);
 110         calc_fast_powerup_delay(cc);
 111 +
 112 +       if (cc->dev->bus->bustype == SSB_BUSTYPE_SSB) {
 113 +               cc->ticks_per_ms = ssb_chipco_watchdog_ticks_per_ms(cc);
 114 +               cc->max_timer_ms = ssb_chipco_watchdog_get_max_timer(cc) / cc->ticks_per_ms;
 115 +       }
 116  }
 117
 118  void ssb_chipco_suspend(struct ssb_chipcommon *cc)
 119 @@ -395,10 +465,27 @@ void ssb_chipco_timing_init(struct ssb_c
 120  }
 121
 122  /* Set chip watchdog reset timer to fire in 'ticks' backplane cycles */
 123 -void ssb_chipco_watchdog_timer_set(struct ssb_chipcommon *cc, u32 ticks)
 124 +u32 ssb_chipco_watchdog_timer_set(struct ssb_chipcommon *cc, u32 ticks)
 125  {
 126 -       /* instant NMI */
 127 -       chipco_write32(cc, SSB_CHIPCO_WATCHDOG, ticks);
 128 +       u32 maxt;
 129 +       enum ssb_clkmode clkmode;
 130 +
 131 +       maxt = ssb_chipco_watchdog_get_max_timer(cc);
 132 +       if (cc->capabilities & SSB_CHIPCO_CAP_PMU) {
 133 +               if (ticks == 1)
 134 +                       ticks = 2;
 135 +               else if (ticks > maxt)
 136 +                       ticks = maxt;
 137 +               chipco_write32(cc, SSB_CHIPCO_PMU_WATCHDOG, ticks);
 138 +       } else {
 139 +               clkmode = ticks ? SSB_CLKMODE_FAST : SSB_CLKMODE_DYNAMIC;
 140 +               ssb_chipco_set_clockmode(cc, clkmode);
 141 +               if (ticks > maxt)
 142 +                       ticks = maxt;
 143 +               /* instant NMI */
 144 +               chipco_write32(cc, SSB_CHIPCO_WATCHDOG, ticks);
 145 +       }
 146 +       return ticks;
 147  }
 148
 149  void ssb_chipco_irq_mask(struct ssb_chipcommon *cc, u32 mask, u32 value)
 150 @@ -473,12 +560,7 @@ int ssb_chipco_serial_init(struct ssb_ch
 151                                        chipco_read32(cc, SSB_CHIPCO_CORECTL)
 152                                        | SSB_CHIPCO_CORECTL_UARTCLK0);
 153                 } else if ((ccrev >= 11) && (ccrev != 15)) {
 154 -                       /* Fixed ALP clock */
 155 -                       baud_base = 20000000;
 156 -                       if (cc->capabilities & SSB_CHIPCO_CAP_PMU) {
 157 -                               /* FIXME: baud_base is different for devices with a PMU */
 158 -                               SSB_WARN_ON(1);
 159 -                       }
 160 +                       baud_base = ssb_chipco_alp_clock(cc);
 161                         div = 1;
 162                         if (ccrev >= 21) {
 163                                 /* Turn off UART clock before switching clocksource. */
 164 --- a/drivers/ssb/driver_chipcommon_pmu.c
 165 +++ b/drivers/ssb/driver_chipcommon_pmu.c
 166 @@ -13,6 +13,9 @@
 167  #include <linux/ssb/ssb_driver_chipcommon.h>
 168  #include <linux/delay.h>
 169  #include <linux/export.h>
 170 +#ifdef CONFIG_BCM47XX
 171 +#include <asm/mach-bcm47xx/nvram.h>
 172 +#endif
 173
 174  #include "ssb_private.h"
 175
 176 @@ -92,10 +95,6 @@ static void ssb_pmu0_pllinit_r0(struct s
 177         u32 pmuctl, tmp, pllctl;
 178         unsigned int i;
 179
 180 -       if ((bus->chip_id == 0x5354) && !crystalfreq) {
 181 -               /* The 5354 crystal freq is 25MHz */
 182 -               crystalfreq = 25000;
 183 -       }
 184         if (crystalfreq)
 185                 e = pmu0_plltab_find_entry(crystalfreq);
 186         if (!e)
 187 @@ -321,7 +320,11 @@ static void ssb_pmu_pll_init(struct ssb_
 188         u32 crystalfreq = 0; /* in kHz. 0 = keep default freq. */
 189
 190         if (bus->bustype == SSB_BUSTYPE_SSB) {
 191 -               /* TODO: The user may override the crystal frequency. */
 192 +#ifdef CONFIG_BCM47XX
 193 +               char buf[20];
 194 +               if (nvram_getenv("xtalfreq", buf, sizeof(buf)) >= 0)
 195 +                       crystalfreq = simple_strtoul(buf, NULL, 0);
 196 +#endif
 197         }
 198
 199         switch (bus->chip_id) {
 200 @@ -330,7 +333,11 @@ static void ssb_pmu_pll_init(struct ssb_
 201                 ssb_pmu1_pllinit_r0(cc, crystalfreq);
 202                 break;
 203         case 0x4328:
 204 +               ssb_pmu0_pllinit_r0(cc, crystalfreq);
 205 +               break;
 206         case 0x5354:
 207 +               if (crystalfreq == 0)
 208 +                       crystalfreq = 25000;
 209                 ssb_pmu0_pllinit_r0(cc, crystalfreq);
 210                 break;
 211         case 0x4322:
 212 @@ -339,6 +346,8 @@ static void ssb_pmu_pll_init(struct ssb_
 213                         chipco_write32(cc, SSB_CHIPCO_PLLCTL_DATA, 0x380005C0);
 214                 }
 215                 break;
 216 +       case 43222:
 217 +               break;
 218         default:
 219                 ssb_printk(KERN_ERR PFX
 220                            "ERROR: PLL init unknown for device %04X\n",
 221 @@ -427,6 +436,7 @@ static void ssb_pmu_resources_init(struc
 222                  min_msk = 0xCBB;
 223                  break;
 224         case 0x4322:
 225 +       case 43222:
 226                 /* We keep the default settings:
 227                  * min_msk = 0xCBB
 228                  * max_msk = 0x7FFFF
 229 @@ -607,3 +617,61 @@ void ssb_pmu_set_ldo_paref(struct ssb_ch
 230
 231  EXPORT_SYMBOL(ssb_pmu_set_ldo_voltage);
 232  EXPORT_SYMBOL(ssb_pmu_set_ldo_paref);
 233 +
 234 +static u32 ssb_pmu_get_alp_clock_clk0(struct ssb_chipcommon *cc)
 235 +{
 236 +       u32 crystalfreq;
 237 +       const struct pmu0_plltab_entry *e = NULL;
 238 +
 239 +       crystalfreq = chipco_read32(cc, SSB_CHIPCO_PMU_CTL) &
 240 +                     SSB_CHIPCO_PMU_CTL_XTALFREQ >> SSB_CHIPCO_PMU_CTL_XTALFREQ_SHIFT;
 241 +       e = pmu0_plltab_find_entry(crystalfreq);
 242 +       BUG_ON(!e);
 243 +       return e->freq * 1000;
 244 +}
 245 +
 246 +u32 ssb_pmu_get_alp_clock(struct ssb_chipcommon *cc)
 247 +{
 248 +       struct ssb_bus *bus = cc->dev->bus;
 249 +
 250 +       switch (bus->chip_id) {
 251 +       case 0x5354:
 252 +               ssb_pmu_get_alp_clock_clk0(cc);
 253 +       default:
 254 +               ssb_printk(KERN_ERR PFX
 255 +                          "ERROR: PMU alp clock unknown for device %04X\n",
 256 +                          bus->chip_id);
 257 +               return 0;
 258 +       }
 259 +}
 260 +
 261 +u32 ssb_pmu_get_cpu_clock(struct ssb_chipcommon *cc)
 262 +{
 263 +       struct ssb_bus *bus = cc->dev->bus;
 264 +
 265 +       switch (bus->chip_id) {
 266 +       case 0x5354:
 267 +               /* 5354 chip uses a non programmable PLL of frequency 240MHz */
 268 +               return 240000000;
 269 +       default:
 270 +               ssb_printk(KERN_ERR PFX
 271 +                          "ERROR: PMU cpu clock unknown for device %04X\n",
 272 +                          bus->chip_id);
 273 +               return 0;
 274 +       }
 275 +}
 276 +
 277 +u32 ssb_pmu_get_controlclock(struct ssb_chipcommon *cc)
 278 +{
 279 +       struct ssb_bus *bus = cc->dev->bus;
 280 +
 281 +       switch (bus->chip_id) {
 282 +       case 0x5354:
 283 +               return 120000000;
 284 +       default:
 285 +               ssb_printk(KERN_ERR PFX
 286 +                          "ERROR: PMU controlclock unknown for device %04X\n",
 287 +                          bus->chip_id);
 288 +               return 0;
 289 +       }
 290 +}
 291 --- a/drivers/ssb/driver_extif.c
 292 +++ b/drivers/ssb/driver_extif.c
 293 @@ -112,10 +112,30 @@ void ssb_extif_get_clockcontrol(struct s
 294         *m = extif_read32(extif, SSB_EXTIF_CLOCK_SB);
 295  }
 296
 297 -void ssb_extif_watchdog_timer_set(struct ssb_extif *extif,
 298 -                                 u32 ticks)
 299 +u32 ssb_extif_watchdog_timer_set_wdt(struct bcm47xx_wdt *wdt, u32 ticks)
 300  {
 301 +       struct ssb_extif *extif = bcm47xx_wdt_get_drvdata(wdt);
 302 +
 303 +       return ssb_extif_watchdog_timer_set(extif, ticks);
 304 +}
 305 +
 306 +u32 ssb_extif_watchdog_timer_set_ms(struct bcm47xx_wdt *wdt, u32 ms)
 307 +{
 308 +       struct ssb_extif *extif = bcm47xx_wdt_get_drvdata(wdt);
 309 +       u32 ticks = (SSB_EXTIF_WATCHDOG_CLK / 1000) * ms;
 310 +
 311 +       ticks = ssb_extif_watchdog_timer_set(extif, ticks);
 312 +
 313 +       return (ticks * 1000) / SSB_EXTIF_WATCHDOG_CLK;
 314 +}
 315 +
 316 +u32 ssb_extif_watchdog_timer_set(struct ssb_extif *extif, u32 ticks)
 317 +{
 318 +       if (ticks > SSB_EXTIF_WATCHDOG_MAX_TIMER)
 319 +               ticks = SSB_EXTIF_WATCHDOG_MAX_TIMER;
 320         extif_write32(extif, SSB_EXTIF_WATCHDOG, ticks);
 321 +
 322 +       return ticks;
 323  }
 324
 325  u32 ssb_extif_gpio_in(struct ssb_extif *extif, u32 mask)
 326 --- a/drivers/ssb/driver_mipscore.c
 327 +++ b/drivers/ssb/driver_mipscore.c
 328 @@ -178,9 +178,9 @@ static void ssb_mips_serial_init(struct
 329  {
 330         struct ssb_bus *bus = mcore->dev->bus;
 331
 332 -       if (bus->extif.dev)
 333 +       if (ssb_extif_available(&bus->extif))
 334                 mcore->nr_serial_ports = ssb_extif_serial_init(&bus->extif, mcore->serial_ports);
 335 -       else if (bus->chipco.dev)
 336 +       else if (ssb_chipco_available(&bus->chipco))
 337                 mcore->nr_serial_ports = ssb_chipco_serial_init(&bus->chipco, mcore->serial_ports);
 338         else
 339                 mcore->nr_serial_ports = 0;
 340 @@ -190,16 +190,32 @@ static void ssb_mips_flash_detect(struct
 341  {
 342         struct ssb_bus *bus = mcore->dev->bus;
 343
 344 -       mcore->flash_buswidth = 2;
 345 -       if (bus->chipco.dev) {
 346 -               mcore->flash_window = 0x1c000000;
 347 -               mcore->flash_window_size = 0x02000000;
 348 +       /* When there is no chipcommon on the bus there is 4MB flash */
 349 +       if (!ssb_chipco_available(&bus->chipco)) {
 350 +               mcore->pflash.present = true;
 351 +               mcore->pflash.buswidth = 2;
 352 +               mcore->pflash.window = SSB_FLASH1;
 353 +               mcore->pflash.window_size = SSB_FLASH1_SZ;
 354 +               return;
 355 +       }
 356 +
 357 +       /* There is ChipCommon, so use it to read info about flash */
 358 +       switch (bus->chipco.capabilities & SSB_CHIPCO_CAP_FLASHT) {
 359 +       case SSB_CHIPCO_FLASHT_STSER:
 360 +       case SSB_CHIPCO_FLASHT_ATSER:
 361 +               pr_err("Serial flash not supported\n");
 362 +               break;
 363 +       case SSB_CHIPCO_FLASHT_PARA:
 364 +               pr_debug("Found parallel flash\n");
 365 +               mcore->pflash.present = true;
 366 +               mcore->pflash.window = SSB_FLASH2;
 367 +               mcore->pflash.window_size = SSB_FLASH2_SZ;
 368                 if ((ssb_read32(bus->chipco.dev, SSB_CHIPCO_FLASH_CFG)
 369                                & SSB_CHIPCO_CFG_DS16) == 0)
 370 -                       mcore->flash_buswidth = 1;
 371 -       } else {
 372 -               mcore->flash_window = 0x1fc00000;
 373 -               mcore->flash_window_size = 0x00400000;
 374 +                       mcore->pflash.buswidth = 1;
 375 +               else
 376 +                       mcore->pflash.buswidth = 2;
 377 +               break;
 378         }
 379  }
 380
 381 @@ -208,9 +224,12 @@ u32 ssb_cpu_clock(struct ssb_mipscore *m
 382         struct ssb_bus *bus = mcore->dev->bus;
 383         u32 pll_type, n, m, rate = 0;
 384
 385 -       if (bus->extif.dev) {
 386 +       if (bus->chipco.capabilities & SSB_CHIPCO_CAP_PMU)
 387 +               return ssb_pmu_get_cpu_clock(&bus->chipco);
 388 +
 389 +       if (ssb_extif_available(&bus->extif)) {
 390                 ssb_extif_get_clockcontrol(&bus->extif, &pll_type, &n, &m);
 391 -       } else if (bus->chipco.dev) {
 392 +       } else if (ssb_chipco_available(&bus->chipco)) {
 393                 ssb_chipco_get_clockcpu(&bus->chipco, &pll_type, &n, &m);
 394         } else
 395                 return 0;
 396 @@ -246,9 +265,9 @@ void ssb_mipscore_init(struct ssb_mipsco
 397                 hz = 100000000;
 398         ns = 1000000000 / hz;
 399
 400 -       if (bus->extif.dev)
 401 +       if (ssb_extif_available(&bus->extif))
 402                 ssb_extif_timing_init(&bus->extif, ns);
 403 -       else if (bus->chipco.dev)
 404 +       else if (ssb_chipco_available(&bus->chipco))
 405                 ssb_chipco_timing_init(&bus->chipco, ns);
 406
 407         /* Assign IRQs to all cores on the bus, start with irq line 2, because serial usually takes 1 */
 408 --- a/drivers/ssb/embedded.c
 409 +++ b/drivers/ssb/embedded.c
 410 @@ -4,11 +4,13 @@
 411   *
 412   * Copyright 2005-2008, Broadcom Corporation
 413   * Copyright 2006-2008, Michael Buesch <m@bues.ch>
 414 + * Copyright 2012, Hauke Mehrtens <hauke@hauke-m.de>
 415   *
 416   * Licensed under the GNU/GPL. See COPYING for details.
 417   */
 418
 419  #include <linux/export.h>
 420 +#include <linux/platform_device.h>
 421  #include <linux/ssb/ssb.h>
 422  #include <linux/ssb/ssb_embedded.h>
 423  #include <linux/ssb/ssb_driver_pci.h>
 424 @@ -32,6 +34,39 @@ int ssb_watchdog_timer_set(struct ssb_bu
 425  }
 426  EXPORT_SYMBOL(ssb_watchdog_timer_set);
 427
 428 +int ssb_watchdog_register(struct ssb_bus *bus)
 429 +{
 430 +       struct bcm47xx_wdt wdt = {};
 431 +       struct platform_device *pdev;
 432 +
 433 +       if (ssb_chipco_available(&bus->chipco)) {
 434 +               wdt.driver_data = &bus->chipco;
 435 +               wdt.timer_set = ssb_chipco_watchdog_timer_set_wdt;
 436 +               wdt.timer_set_ms = ssb_chipco_watchdog_timer_set_ms;
 437 +               wdt.max_timer_ms = bus->chipco.max_timer_ms;
 438 +       } else if (ssb_extif_available(&bus->extif)) {
 439 +               wdt.driver_data = &bus->extif;
 440 +               wdt.timer_set = ssb_extif_watchdog_timer_set_wdt;
 441 +               wdt.timer_set_ms = ssb_extif_watchdog_timer_set_ms;
 442 +               wdt.max_timer_ms = SSB_EXTIF_WATCHDOG_MAX_TIMER_MS;
 443 +       } else {
 444 +               return -ENODEV;
 445 +       }
 446 +
 447 +       pdev = platform_device_register_data(NULL, "bcm47xx-wdt",
 448 +                                            bus->busnumber, &wdt,
 449 +                                            sizeof(wdt));
 450 +       if (IS_ERR(pdev)) {
 451 +               ssb_dprintk(KERN_INFO PFX
 452 +                           "can not register watchdog device, err: %li\n",
 453 +                           PTR_ERR(pdev));
 454 +               return PTR_ERR(pdev);
 455 +       }
 456 +
 457 +       bus->watchdog = pdev;
 458 +       return 0;
 459 +}
 460 +
 461  u32 ssb_gpio_in(struct ssb_bus *bus, u32 mask)
 462  {
 463         unsigned long flags;
 464 --- a/drivers/ssb/main.c
 465 +++ b/drivers/ssb/main.c
 466 @@ -13,6 +13,7 @@
 467  #include <linux/delay.h>
 468  #include <linux/io.h>
 469  #include <linux/module.h>
 470 +#include <linux/platform_device.h>
 471  #include <linux/ssb/ssb.h>
 472  #include <linux/ssb/ssb_regs.h>
 473  #include <linux/ssb/ssb_driver_gige.h>
 474 @@ -140,19 +141,6 @@ static void ssb_device_put(struct ssb_de
 475                 put_device(dev->dev);
 476  }
 477
 478 -static inline struct ssb_driver *ssb_driver_get(struct ssb_driver *drv)
 479 -{
 480 -       if (drv)
 481 -               get_driver(&drv->drv);
 482 -       return drv;
 483 -}
 484 -
 485 -static inline void ssb_driver_put(struct ssb_driver *drv)
 486 -{
 487 -       if (drv)
 488 -               put_driver(&drv->drv);
 489 -}
 490 -
 491  static int ssb_device_resume(struct device *dev)
 492  {
 493         struct ssb_device *ssb_dev = dev_to_ssb_dev(dev);
 494 @@ -250,11 +238,9 @@ int ssb_devices_freeze(struct ssb_bus *b
 495                         ssb_device_put(sdev);
 496                         continue;
 497                 }
 498 -               sdrv = ssb_driver_get(drv_to_ssb_drv(sdev->dev->driver));
 499 -               if (!sdrv || SSB_WARN_ON(!sdrv->remove)) {
 500 -                       ssb_device_put(sdev);
 501 +               sdrv = drv_to_ssb_drv(sdev->dev->driver);
 502 +               if (SSB_WARN_ON(!sdrv->remove))
 503                         continue;
 504 -               }
 505                 sdrv->remove(sdev);
 506                 ctx->device_frozen[i] = 1;
 507         }
 508 @@ -293,7 +279,6 @@ int ssb_devices_thaw(struct ssb_freeze_c
 509                                    dev_name(sdev->dev));
 510                         result = err;
 511                 }
 512 -               ssb_driver_put(sdrv);
 513                 ssb_device_put(sdev);
 514         }
 515
 516 @@ -449,6 +434,11 @@ static void ssb_devices_unregister(struc
 517                 if (sdev->dev)
 518                         device_unregister(sdev->dev);
 519         }
 520 +
 521 +#ifdef CONFIG_SSB_EMBEDDED
 522 +       if (bus->bustype == SSB_BUSTYPE_SSB)
 523 +               platform_device_unregister(bus->watchdog);
 524 +#endif
 525  }
 526
 527  void ssb_bus_unregister(struct ssb_bus *bus)
 528 @@ -577,6 +567,8 @@ static int __devinit ssb_attach_queued_b
 529                 if (err)
 530                         goto error;
 531                 ssb_pcicore_init(&bus->pcicore);
 532 +               if (bus->bustype == SSB_BUSTYPE_SSB)
 533 +                       ssb_watchdog_register(bus);
 534                 ssb_bus_may_powerdown(bus);
 535
 536                 err = ssb_devices_register(bus);
 537 @@ -1094,6 +1086,9 @@ u32 ssb_clockspeed(struct ssb_bus *bus)
 538         u32 plltype;
 539         u32 clkctl_n, clkctl_m;
 540
 541 +       if (bus->chipco.capabilities & SSB_CHIPCO_CAP_PMU)
 542 +               return ssb_pmu_get_controlclock(&bus->chipco);
 543 +
 544         if (ssb_extif_available(&bus->extif))
 545                 ssb_extif_get_clockcontrol(&bus->extif, &plltype,
 546                                            &clkctl_n, &clkctl_m);
 547 @@ -1131,8 +1126,7 @@ static u32 ssb_tmslow_reject_bitmask(str
 548         case SSB_IDLOW_SSBREV_27:     /* same here */
 549                 return SSB_TMSLOW_REJECT;       /* this is a guess */
 550         default:
 551 -               printk(KERN_INFO "ssb: Backplane Revision 0x%.8X\n", rev);
 552 -               WARN_ON(1);
 553 +               WARN(1, KERN_INFO "ssb: Backplane Revision 0x%.8X\n", rev);
 554         }
 555         return (SSB_TMSLOW_REJECT | SSB_TMSLOW_REJECT_23);
 556  }
 557 --- a/drivers/ssb/pci.c
 558 +++ b/drivers/ssb/pci.c
 559 @@ -178,6 +178,18 @@ err_pci:
 560  #define SPEX(_outvar, _offset, _mask, _shift) \
 561         SPEX16(_outvar, _offset, _mask, _shift)
 562
 563 +#define SPEX_ARRAY8(_field, _offset, _mask, _shift)    \
 564 +       do {    \
 565 +               SPEX(_field[0], _offset +  0, _mask, _shift);   \
 566 +               SPEX(_field[1], _offset +  2, _mask, _shift);   \
 567 +               SPEX(_field[2], _offset +  4, _mask, _shift);   \
 568 +               SPEX(_field[3], _offset +  6, _mask, _shift);   \
 569 +               SPEX(_field[4], _offset +  8, _mask, _shift);   \
 570 +               SPEX(_field[5], _offset + 10, _mask, _shift);   \
 571 +               SPEX(_field[6], _offset + 12, _mask, _shift);   \
 572 +               SPEX(_field[7], _offset + 14, _mask, _shift);   \
 573 +       } while (0)
 574 +
 575
 576  static inline u8 ssb_crc8(u8 crc, u8 data)
 577  {
 578 @@ -331,7 +343,6 @@ static void sprom_extract_r123(struct ss
 579  {
 580         int i;
 581         u16 v;
 582 -       s8 gain;
 583         u16 loc[3];
 584
 585         if (out->revision == 3)                 /* rev 3 moved MAC */
 586 @@ -361,8 +372,9 @@ static void sprom_extract_r123(struct ss
 587         SPEX(et0mdcport, SSB_SPROM1_ETHPHY, SSB_SPROM1_ETHPHY_ET0M, 14);
 588         SPEX(et1mdcport, SSB_SPROM1_ETHPHY, SSB_SPROM1_ETHPHY_ET1M, 15);
 589         SPEX(board_rev, SSB_SPROM1_BINF, SSB_SPROM1_BINF_BREV, 0);
 590 -       SPEX(country_code, SSB_SPROM1_BINF, SSB_SPROM1_BINF_CCODE,
 591 -            SSB_SPROM1_BINF_CCODE_SHIFT);
 592 +       if (out->revision == 1)
 593 +               SPEX(country_code, SSB_SPROM1_BINF, SSB_SPROM1_BINF_CCODE,
 594 +                    SSB_SPROM1_BINF_CCODE_SHIFT);
 595         SPEX(ant_available_a, SSB_SPROM1_BINF, SSB_SPROM1_BINF_ANTA,
 596              SSB_SPROM1_BINF_ANTA_SHIFT);
 597         SPEX(ant_available_bg, SSB_SPROM1_BINF, SSB_SPROM1_BINF_ANTBG,
 598 @@ -388,22 +400,16 @@ static void sprom_extract_r123(struct ss
 599         SPEX(boardflags_lo, SSB_SPROM1_BFLLO, 0xFFFF, 0);
 600         if (out->revision >= 2)
 601                 SPEX(boardflags_hi, SSB_SPROM2_BFLHI, 0xFFFF, 0);
 602 +       SPEX(alpha2[0], SSB_SPROM1_CCODE, 0xff00, 8);
 603 +       SPEX(alpha2[1], SSB_SPROM1_CCODE, 0x00ff, 0);
 604
 605         /* Extract the antenna gain values. */
 606 -       gain = r123_extract_antgain(out->revision, in,
 607 -                                   SSB_SPROM1_AGAIN_BG,
 608 -                                   SSB_SPROM1_AGAIN_BG_SHIFT);
 609 -       out->antenna_gain.ghz24.a0 = gain;
 610 -       out->antenna_gain.ghz24.a1 = gain;
 611 -       out->antenna_gain.ghz24.a2 = gain;
 612 -       out->antenna_gain.ghz24.a3 = gain;
 613 -       gain = r123_extract_antgain(out->revision, in,
 614 -                                   SSB_SPROM1_AGAIN_A,
 615 -                                   SSB_SPROM1_AGAIN_A_SHIFT);
 616 -       out->antenna_gain.ghz5.a0 = gain;
 617 -       out->antenna_gain.ghz5.a1 = gain;
 618 -       out->antenna_gain.ghz5.a2 = gain;
 619 -       out->antenna_gain.ghz5.a3 = gain;
 620 +       out->antenna_gain.a0 = r123_extract_antgain(out->revision, in,
 621 +                                                   SSB_SPROM1_AGAIN_BG,
 622 +                                                   SSB_SPROM1_AGAIN_BG_SHIFT);
 623 +       out->antenna_gain.a1 = r123_extract_antgain(out->revision, in,
 624 +                                                   SSB_SPROM1_AGAIN_A,
 625 +                                                   SSB_SPROM1_AGAIN_A_SHIFT);
 626  }
 627
 628  /* Revs 4 5 and 8 have partially shared layout */
 629 @@ -464,14 +470,17 @@ static void sprom_extract_r45(struct ssb
 630         SPEX(et0phyaddr, SSB_SPROM4_ETHPHY, SSB_SPROM4_ETHPHY_ET0A, 0);
 631         SPEX(et1phyaddr, SSB_SPROM4_ETHPHY, SSB_SPROM4_ETHPHY_ET1A,
 632              SSB_SPROM4_ETHPHY_ET1A_SHIFT);
 633 +       SPEX(board_rev, SSB_SPROM4_BOARDREV, 0xFFFF, 0);
 634         if (out->revision == 4) {
 635 -               SPEX(country_code, SSB_SPROM4_CCODE, 0xFFFF, 0);
 636 +               SPEX(alpha2[0], SSB_SPROM4_CCODE, 0xff00, 8);
 637 +               SPEX(alpha2[1], SSB_SPROM4_CCODE, 0x00ff, 0);
 638                 SPEX(boardflags_lo, SSB_SPROM4_BFLLO, 0xFFFF, 0);
 639                 SPEX(boardflags_hi, SSB_SPROM4_BFLHI, 0xFFFF, 0);
 640                 SPEX(boardflags2_lo, SSB_SPROM4_BFL2LO, 0xFFFF, 0);
 641                 SPEX(boardflags2_hi, SSB_SPROM4_BFL2HI, 0xFFFF, 0);
 642         } else {
 643 -               SPEX(country_code, SSB_SPROM5_CCODE, 0xFFFF, 0);
 644 +               SPEX(alpha2[0], SSB_SPROM5_CCODE, 0xff00, 8);
 645 +               SPEX(alpha2[1], SSB_SPROM5_CCODE, 0x00ff, 0);
 646                 SPEX(boardflags_lo, SSB_SPROM5_BFLLO, 0xFFFF, 0);
 647                 SPEX(boardflags_hi, SSB_SPROM5_BFLHI, 0xFFFF, 0);
 648                 SPEX(boardflags2_lo, SSB_SPROM5_BFL2LO, 0xFFFF, 0);
 649 @@ -504,16 +513,14 @@ static void sprom_extract_r45(struct ssb
 650         }
 651
 652         /* Extract the antenna gain values. */
 653 -       SPEX(antenna_gain.ghz24.a0, SSB_SPROM4_AGAIN01,
 654 +       SPEX(antenna_gain.a0, SSB_SPROM4_AGAIN01,
 655              SSB_SPROM4_AGAIN0, SSB_SPROM4_AGAIN0_SHIFT);
 656 -       SPEX(antenna_gain.ghz24.a1, SSB_SPROM4_AGAIN01,
 657 +       SPEX(antenna_gain.a1, SSB_SPROM4_AGAIN01,
 658              SSB_SPROM4_AGAIN1, SSB_SPROM4_AGAIN1_SHIFT);
 659 -       SPEX(antenna_gain.ghz24.a2, SSB_SPROM4_AGAIN23,
 660 +       SPEX(antenna_gain.a2, SSB_SPROM4_AGAIN23,
 661              SSB_SPROM4_AGAIN2, SSB_SPROM4_AGAIN2_SHIFT);
 662 -       SPEX(antenna_gain.ghz24.a3, SSB_SPROM4_AGAIN23,
 663 +       SPEX(antenna_gain.a3, SSB_SPROM4_AGAIN23,
 664              SSB_SPROM4_AGAIN3, SSB_SPROM4_AGAIN3_SHIFT);
 665 -       memcpy(&out->antenna_gain.ghz5, &out->antenna_gain.ghz24,
 666 -              sizeof(out->antenna_gain.ghz5));
 667
 668         sprom_extract_r458(out, in);
 669
 670 @@ -523,14 +530,22 @@ static void sprom_extract_r45(struct ssb
 671  static void sprom_extract_r8(struct ssb_sprom *out, const u16 *in)
 672  {
 673         int i;
 674 -       u16 v;
 675 +       u16 v, o;
 676 +       u16 pwr_info_offset[] = {
 677 +               SSB_SROM8_PWR_INFO_CORE0, SSB_SROM8_PWR_INFO_CORE1,
 678 +               SSB_SROM8_PWR_INFO_CORE2, SSB_SROM8_PWR_INFO_CORE3
 679 +       };
 680 +       BUILD_BUG_ON(ARRAY_SIZE(pwr_info_offset) !=
 681 +                       ARRAY_SIZE(out->core_pwr_info));
 682
 683         /* extract the MAC address */
 684         for (i = 0; i < 3; i++) {
 685                 v = in[SPOFF(SSB_SPROM8_IL0MAC) + i];
 686                 *(((__be16 *)out->il0mac) + i) = cpu_to_be16(v);
 687         }
 688 -       SPEX(country_code, SSB_SPROM8_CCODE, 0xFFFF, 0);
 689 +       SPEX(board_rev, SSB_SPROM8_BOARDREV, 0xFFFF, 0);
 690 +       SPEX(alpha2[0], SSB_SPROM8_CCODE, 0xff00, 8);
 691 +       SPEX(alpha2[1], SSB_SPROM8_CCODE, 0x00ff, 0);
 692         SPEX(boardflags_lo, SSB_SPROM8_BFLLO, 0xFFFF, 0);
 693         SPEX(boardflags_hi, SSB_SPROM8_BFLHI, 0xFFFF, 0);
 694         SPEX(boardflags2_lo, SSB_SPROM8_BFL2LO, 0xFFFF, 0);
 695 @@ -596,16 +611,46 @@ static void sprom_extract_r8(struct ssb_
 696         SPEX32(ofdm5ghpo, SSB_SPROM8_OFDM5GHPO, 0xFFFFFFFF, 0);
 697
 698         /* Extract the antenna gain values. */
 699 -       SPEX(antenna_gain.ghz24.a0, SSB_SPROM8_AGAIN01,
 700 +       SPEX(antenna_gain.a0, SSB_SPROM8_AGAIN01,
 701              SSB_SPROM8_AGAIN0, SSB_SPROM8_AGAIN0_SHIFT);
 702 -       SPEX(antenna_gain.ghz24.a1, SSB_SPROM8_AGAIN01,
 703 +       SPEX(antenna_gain.a1, SSB_SPROM8_AGAIN01,
 704              SSB_SPROM8_AGAIN1, SSB_SPROM8_AGAIN1_SHIFT);
 705 -       SPEX(antenna_gain.ghz24.a2, SSB_SPROM8_AGAIN23,
 706 +       SPEX(antenna_gain.a2, SSB_SPROM8_AGAIN23,
 707              SSB_SPROM8_AGAIN2, SSB_SPROM8_AGAIN2_SHIFT);
 708 -       SPEX(antenna_gain.ghz24.a3, SSB_SPROM8_AGAIN23,
 709 +       SPEX(antenna_gain.a3, SSB_SPROM8_AGAIN23,
 710              SSB_SPROM8_AGAIN3, SSB_SPROM8_AGAIN3_SHIFT);
 711 -       memcpy(&out->antenna_gain.ghz5, &out->antenna_gain.ghz24,
 712 -              sizeof(out->antenna_gain.ghz5));
 713 +
 714 +       /* Extract cores power info info */
 715 +       for (i = 0; i < ARRAY_SIZE(pwr_info_offset); i++) {
 716 +               o = pwr_info_offset[i];
 717 +               SPEX(core_pwr_info[i].itssi_2g, o + SSB_SROM8_2G_MAXP_ITSSI,
 718 +                       SSB_SPROM8_2G_ITSSI, SSB_SPROM8_2G_ITSSI_SHIFT);
 719 +               SPEX(core_pwr_info[i].maxpwr_2g, o + SSB_SROM8_2G_MAXP_ITSSI,
 720 +                       SSB_SPROM8_2G_MAXP, 0);
 721 +
 722 +               SPEX(core_pwr_info[i].pa_2g[0], o + SSB_SROM8_2G_PA_0, ~0, 0);
 723 +               SPEX(core_pwr_info[i].pa_2g[1], o + SSB_SROM8_2G_PA_1, ~0, 0);
 724 +               SPEX(core_pwr_info[i].pa_2g[2], o + SSB_SROM8_2G_PA_2, ~0, 0);
 725 +
 726 +               SPEX(core_pwr_info[i].itssi_5g, o + SSB_SROM8_5G_MAXP_ITSSI,
 727 +                       SSB_SPROM8_5G_ITSSI, SSB_SPROM8_5G_ITSSI_SHIFT);
 728 +               SPEX(core_pwr_info[i].maxpwr_5g, o + SSB_SROM8_5G_MAXP_ITSSI,
 729 +                       SSB_SPROM8_5G_MAXP, 0);
 730 +               SPEX(core_pwr_info[i].maxpwr_5gh, o + SSB_SPROM8_5GHL_MAXP,
 731 +                       SSB_SPROM8_5GH_MAXP, 0);
 732 +               SPEX(core_pwr_info[i].maxpwr_5gl, o + SSB_SPROM8_5GHL_MAXP,
 733 +                       SSB_SPROM8_5GL_MAXP, SSB_SPROM8_5GL_MAXP_SHIFT);
 734 +
 735 +               SPEX(core_pwr_info[i].pa_5gl[0], o + SSB_SROM8_5GL_PA_0, ~0, 0);
 736 +               SPEX(core_pwr_info[i].pa_5gl[1], o + SSB_SROM8_5GL_PA_1, ~0, 0);
 737 +               SPEX(core_pwr_info[i].pa_5gl[2], o + SSB_SROM8_5GL_PA_2, ~0, 0);
 738 +               SPEX(core_pwr_info[i].pa_5g[0], o + SSB_SROM8_5G_PA_0, ~0, 0);
 739 +               SPEX(core_pwr_info[i].pa_5g[1], o + SSB_SROM8_5G_PA_1, ~0, 0);
 740 +               SPEX(core_pwr_info[i].pa_5g[2], o + SSB_SROM8_5G_PA_2, ~0, 0);
 741 +               SPEX(core_pwr_info[i].pa_5gh[0], o + SSB_SROM8_5GH_PA_0, ~0, 0);
 742 +               SPEX(core_pwr_info[i].pa_5gh[1], o + SSB_SROM8_5GH_PA_1, ~0, 0);
 743 +               SPEX(core_pwr_info[i].pa_5gh[2], o + SSB_SROM8_5GH_PA_2, ~0, 0);
 744 +       }
 745
 746         /* Extract FEM info */
 747         SPEX(fem.ghz2.tssipos, SSB_SPROM8_FEM2G,
 748 @@ -630,6 +675,63 @@ static void sprom_extract_r8(struct ssb_
 749         SPEX(fem.ghz5.antswlut, SSB_SPROM8_FEM5G,
 750                 SSB_SROM8_FEM_ANTSWLUT, SSB_SROM8_FEM_ANTSWLUT_SHIFT);
 751
 752 +       SPEX(leddc_on_time, SSB_SPROM8_LEDDC, SSB_SPROM8_LEDDC_ON,
 753 +            SSB_SPROM8_LEDDC_ON_SHIFT);
 754 +       SPEX(leddc_off_time, SSB_SPROM8_LEDDC, SSB_SPROM8_LEDDC_OFF,
 755 +            SSB_SPROM8_LEDDC_OFF_SHIFT);
 756 +
 757 +       SPEX(txchain, SSB_SPROM8_TXRXC, SSB_SPROM8_TXRXC_TXCHAIN,
 758 +            SSB_SPROM8_TXRXC_TXCHAIN_SHIFT);
 759 +       SPEX(rxchain, SSB_SPROM8_TXRXC, SSB_SPROM8_TXRXC_RXCHAIN,
 760 +            SSB_SPROM8_TXRXC_RXCHAIN_SHIFT);
 761 +       SPEX(antswitch, SSB_SPROM8_TXRXC, SSB_SPROM8_TXRXC_SWITCH,
 762 +            SSB_SPROM8_TXRXC_SWITCH_SHIFT);
 763 +
 764 +       SPEX(opo, SSB_SPROM8_OFDM2GPO, 0x00ff, 0);
 765 +
 766 +       SPEX_ARRAY8(mcs2gpo, SSB_SPROM8_2G_MCSPO, ~0, 0);
 767 +       SPEX_ARRAY8(mcs5gpo, SSB_SPROM8_5G_MCSPO, ~0, 0);
 768 +       SPEX_ARRAY8(mcs5glpo, SSB_SPROM8_5GL_MCSPO, ~0, 0);
 769 +       SPEX_ARRAY8(mcs5ghpo, SSB_SPROM8_5GH_MCSPO, ~0, 0);
 770 +
 771 +       SPEX(rawtempsense, SSB_SPROM8_RAWTS, SSB_SPROM8_RAWTS_RAWTEMP,
 772 +            SSB_SPROM8_RAWTS_RAWTEMP_SHIFT);
 773 +       SPEX(measpower, SSB_SPROM8_RAWTS, SSB_SPROM8_RAWTS_MEASPOWER,
 774 +            SSB_SPROM8_RAWTS_MEASPOWER_SHIFT);
 775 +       SPEX(tempsense_slope, SSB_SPROM8_OPT_CORRX,
 776 +            SSB_SPROM8_OPT_CORRX_TEMP_SLOPE,
 777 +            SSB_SPROM8_OPT_CORRX_TEMP_SLOPE_SHIFT);
 778 +       SPEX(tempcorrx, SSB_SPROM8_OPT_CORRX, SSB_SPROM8_OPT_CORRX_TEMPCORRX,
 779 +            SSB_SPROM8_OPT_CORRX_TEMPCORRX_SHIFT);
 780 +       SPEX(tempsense_option, SSB_SPROM8_OPT_CORRX,
 781 +            SSB_SPROM8_OPT_CORRX_TEMP_OPTION,
 782 +            SSB_SPROM8_OPT_CORRX_TEMP_OPTION_SHIFT);
 783 +       SPEX(freqoffset_corr, SSB_SPROM8_HWIQ_IQSWP,
 784 +            SSB_SPROM8_HWIQ_IQSWP_FREQ_CORR,
 785 +            SSB_SPROM8_HWIQ_IQSWP_FREQ_CORR_SHIFT);
 786 +       SPEX(iqcal_swp_dis, SSB_SPROM8_HWIQ_IQSWP,
 787 +            SSB_SPROM8_HWIQ_IQSWP_IQCAL_SWP,
 788 +            SSB_SPROM8_HWIQ_IQSWP_IQCAL_SWP_SHIFT);
 789 +       SPEX(hw_iqcal_en, SSB_SPROM8_HWIQ_IQSWP, SSB_SPROM8_HWIQ_IQSWP_HW_IQCAL,
 790 +            SSB_SPROM8_HWIQ_IQSWP_HW_IQCAL_SHIFT);
 791 +
 792 +       SPEX(bw40po, SSB_SPROM8_BW40PO, ~0, 0);
 793 +       SPEX(cddpo, SSB_SPROM8_CDDPO, ~0, 0);
 794 +       SPEX(stbcpo, SSB_SPROM8_STBCPO, ~0, 0);
 795 +       SPEX(bwduppo, SSB_SPROM8_BWDUPPO, ~0, 0);
 796 +
 797 +       SPEX(tempthresh, SSB_SPROM8_THERMAL, SSB_SPROM8_THERMAL_TRESH,
 798 +            SSB_SPROM8_THERMAL_TRESH_SHIFT);
 799 +       SPEX(tempoffset, SSB_SPROM8_THERMAL, SSB_SPROM8_THERMAL_OFFSET,
 800 +            SSB_SPROM8_THERMAL_OFFSET_SHIFT);
 801 +       SPEX(phycal_tempdelta, SSB_SPROM8_TEMPDELTA,
 802 +            SSB_SPROM8_TEMPDELTA_PHYCAL,
 803 +            SSB_SPROM8_TEMPDELTA_PHYCAL_SHIFT);
 804 +       SPEX(temps_period, SSB_SPROM8_TEMPDELTA, SSB_SPROM8_TEMPDELTA_PERIOD,
 805 +            SSB_SPROM8_TEMPDELTA_PERIOD_SHIFT);
 806 +       SPEX(temps_hysteresis, SSB_SPROM8_TEMPDELTA,
 807 +            SSB_SPROM8_TEMPDELTA_HYSTERESIS,
 808 +            SSB_SPROM8_TEMPDELTA_HYSTERESIS_SHIFT);
 809         sprom_extract_r458(out, in);
 810
 811         /* TODO - get remaining rev 8 stuff needed */
 812 @@ -759,7 +861,6 @@ static void ssb_pci_get_boardinfo(struct
 813  {
 814         bi->vendor = bus->host_pci->subsystem_vendor;
 815         bi->type = bus->host_pci->subsystem_device;
 816 -       bi->rev = bus->host_pci->revision;
 817  }
 818
 819  int ssb_pci_get_invariants(struct ssb_bus *bus,
 820 --- a/drivers/ssb/pcmcia.c
 821 +++ b/drivers/ssb/pcmcia.c
 822 @@ -676,14 +676,10 @@ static int ssb_pcmcia_do_get_invariants(
 823         case SSB_PCMCIA_CIS_ANTGAIN:
 824                 GOTO_ERROR_ON(tuple->TupleDataLen != 2,
 825                         "antg tpl size");
 826 -               sprom->antenna_gain.ghz24.a0 = tuple->TupleData[1];
 827 -               sprom->antenna_gain.ghz24.a1 = tuple->TupleData[1];
 828 -               sprom->antenna_gain.ghz24.a2 = tuple->TupleData[1];
 829 -               sprom->antenna_gain.ghz24.a3 = tuple->TupleData[1];
 830 -               sprom->antenna_gain.ghz5.a0 = tuple->TupleData[1];
 831 -               sprom->antenna_gain.ghz5.a1 = tuple->TupleData[1];
 832 -               sprom->antenna_gain.ghz5.a2 = tuple->TupleData[1];
 833 -               sprom->antenna_gain.ghz5.a3 = tuple->TupleData[1];
 834 +               sprom->antenna_gain.a0 = tuple->TupleData[1];
 835 +               sprom->antenna_gain.a1 = tuple->TupleData[1];
 836 +               sprom->antenna_gain.a2 = tuple->TupleData[1];
 837 +               sprom->antenna_gain.a3 = tuple->TupleData[1];
 838                 break;
 839         case SSB_PCMCIA_CIS_BFLAGS:
 840                 GOTO_ERROR_ON((tuple->TupleDataLen != 3) &&
 841 --- a/drivers/ssb/scan.c
 842 +++ b/drivers/ssb/scan.c
 843 @@ -90,6 +90,8 @@ const char *ssb_core_name(u16 coreid)
 844                 return "ARM 1176";
 845         case SSB_DEV_ARM_7TDMI:
 846                 return "ARM 7TDMI";
 847 +       case SSB_DEV_ARM_CM3:
 848 +               return "ARM Cortex M3";
 849         }
 850         return "UNKNOWN";
 851  }
 852 @@ -318,6 +320,9 @@ int ssb_bus_scan(struct ssb_bus *bus,
 853                         bus->chip_package = 0;
 854                 }
 855         }
 856 +       ssb_printk(KERN_INFO PFX "Found chip with id 0x%04X, rev 0x%02X and "
 857 +                  "package 0x%02X\n", bus->chip_id, bus->chip_rev,
 858 +                  bus->chip_package);
 859         if (!bus->nr_devices)
 860                 bus->nr_devices = chipid_to_nrcores(bus->chip_id);
 861         if (bus->nr_devices > ARRAY_SIZE(bus->devices)) {
 862 --- a/drivers/ssb/sdio.c
 863 +++ b/drivers/ssb/sdio.c
 864 @@ -551,14 +551,10 @@ int ssb_sdio_get_invariants(struct ssb_b
 865                         case SSB_SDIO_CIS_ANTGAIN:
 866                                 GOTO_ERROR_ON(tuple->size != 2,
 867                                               "antg tpl size");
 868 -                               sprom->antenna_gain.ghz24.a0 = tuple->data[1];
 869 -                               sprom->antenna_gain.ghz24.a1 = tuple->data[1];
 870 -                               sprom->antenna_gain.ghz24.a2 = tuple->data[1];
 871 -                               sprom->antenna_gain.ghz24.a3 = tuple->data[1];
 872 -                               sprom->antenna_gain.ghz5.a0 = tuple->data[1];
 873 -                               sprom->antenna_gain.ghz5.a1 = tuple->data[1];
 874 -                               sprom->antenna_gain.ghz5.a2 = tuple->data[1];
 875 -                               sprom->antenna_gain.ghz5.a3 = tuple->data[1];
 876 +                               sprom->antenna_gain.a0 = tuple->data[1];
 877 +                               sprom->antenna_gain.a1 = tuple->data[1];
 878 +                               sprom->antenna_gain.a2 = tuple->data[1];
 879 +                               sprom->antenna_gain.a3 = tuple->data[1];
 880                                 break;
 881                         case SSB_SDIO_CIS_BFLAGS:
 882                                 GOTO_ERROR_ON((tuple->size != 3) &&
 883 --- a/drivers/ssb/ssb_private.h
 884 +++ b/drivers/ssb/ssb_private.h
 885 @@ -3,6 +3,7 @@
 886
 887  #include <linux/ssb/ssb.h>
 888  #include <linux/types.h>
 889 +#include <linux/bcm47xx_wdt.h>
 890
 891
 892  #define PFX    "ssb: "
 893 @@ -207,4 +208,38 @@ static inline void b43_pci_ssb_bridge_ex
 894  }
 895  #endif /* CONFIG_SSB_B43_PCI_BRIDGE */
 896
 897 +/* driver_chipcommon_pmu.c */
 898 +extern u32 ssb_pmu_get_cpu_clock(struct ssb_chipcommon *cc);
 899 +extern u32 ssb_pmu_get_controlclock(struct ssb_chipcommon *cc);
 900 +extern u32 ssb_pmu_get_alp_clock(struct ssb_chipcommon *cc);
 901 +
 902 +extern u32 ssb_chipco_watchdog_timer_set_wdt(struct bcm47xx_wdt *wdt,
 903 +                                            u32 ticks);
 904 +extern u32 ssb_chipco_watchdog_timer_set_ms(struct bcm47xx_wdt *wdt, u32 ms);
 905 +
 906 +#ifdef CONFIG_SSB_DRIVER_EXTIF
 907 +extern u32 ssb_extif_watchdog_timer_set_wdt(struct bcm47xx_wdt *wdt, u32 ticks);
 908 +extern u32 ssb_extif_watchdog_timer_set_ms(struct bcm47xx_wdt *wdt, u32 ms);
 909 +#else
 910 +static inline u32 ssb_extif_watchdog_timer_set_wdt(struct bcm47xx_wdt *wdt,
 911 +                                                  u32 ticks)
 912 +{
 913 +       return 0;
 914 +}
 915 +static inline u32 ssb_extif_watchdog_timer_set_ms(struct bcm47xx_wdt *wdt,
 916 +                                                 u32 ms)
 917 +{
 918 +       return 0;
 919 +}
 920 +#endif
 921 +
 922 +#ifdef CONFIG_SSB_EMBEDDED
 923 +extern int ssb_watchdog_register(struct ssb_bus *bus);
 924 +#else /* CONFIG_SSB_EMBEDDED */
 925 +static inline int ssb_watchdog_register(struct ssb_bus *bus)
 926 +{
 927 +       return 0;
 928 +}
 929 +#endif /* CONFIG_SSB_EMBEDDED */
 930 +
 931  #endif /* LINUX_SSB_PRIVATE_H_ */
 932 --- a/include/linux/ssb/ssb.h
 933 +++ b/include/linux/ssb/ssb.h
 934 @@ -8,6 +8,7 @@
 935  #include <linux/pci.h>
 936  #include <linux/mod_devicetable.h>
 937  #include <linux/dma-mapping.h>
 938 +#include <linux/platform_device.h>
 939
 940  #include <linux/ssb/ssb_regs.h>
 941
 942 @@ -16,6 +17,12 @@ struct pcmcia_device;
 943  struct ssb_bus;
 944  struct ssb_driver;
 945
 946 +struct ssb_sprom_core_pwr_info {
 947 +       u8 itssi_2g, itssi_5g;
 948 +       u8 maxpwr_2g, maxpwr_5gl, maxpwr_5g, maxpwr_5gh;
 949 +       u16 pa_2g[4], pa_5gl[4], pa_5g[4], pa_5gh[4];
 950 +};
 951 +
 952  struct ssb_sprom {
 953         u8 revision;
 954         u8 il0mac[6];           /* MAC address for 802.11b/g */
 955 @@ -26,9 +33,12 @@ struct ssb_sprom {
 956         u8 et0mdcport;          /* MDIO for enet0 */
 957         u8 et1mdcport;          /* MDIO for enet1 */
 958         u16 board_rev;          /* Board revision number from SPROM. */
 959 +       u16 board_num;          /* Board number from SPROM. */
 960 +       u16 board_type;         /* Board type from SPROM. */
 961         u8 country_code;        /* Country Code */
 962 -       u16 leddc_on_time;      /* LED Powersave Duty Cycle On Count */
 963 -       u16 leddc_off_time;     /* LED Powersave Duty Cycle Off Count */
 964 +       char alpha2[2];         /* Country Code as two chars like EU or US */
 965 +       u8 leddc_on_time;       /* LED Powersave Duty Cycle On Count */
 966 +       u8 leddc_off_time;      /* LED Powersave Duty Cycle Off Count */
 967         u8 ant_available_a;     /* 2GHz antenna available bits (up to 4) */
 968         u8 ant_available_bg;    /* 5GHz antenna available bits (up to 4) */
 969         u16 pa0b0;
 970 @@ -47,10 +57,10 @@ struct ssb_sprom {
 971         u8 gpio1;               /* GPIO pin 1 */
 972         u8 gpio2;               /* GPIO pin 2 */
 973         u8 gpio3;               /* GPIO pin 3 */
 974 -       u16 maxpwr_bg;          /* 2.4GHz Amplifier Max Power (in dBm Q5.2) */
 975 -       u16 maxpwr_al;          /* 5.2GHz Amplifier Max Power (in dBm Q5.2) */
 976 -       u16 maxpwr_a;           /* 5.3GHz Amplifier Max Power (in dBm Q5.2) */
 977 -       u16 maxpwr_ah;          /* 5.8GHz Amplifier Max Power (in dBm Q5.2) */
 978 +       u8 maxpwr_bg;           /* 2.4GHz Amplifier Max Power (in dBm Q5.2) */
 979 +       u8 maxpwr_al;           /* 5.2GHz Amplifier Max Power (in dBm Q5.2) */
 980 +       u8 maxpwr_a;            /* 5.3GHz Amplifier Max Power (in dBm Q5.2) */
 981 +       u8 maxpwr_ah;           /* 5.8GHz Amplifier Max Power (in dBm Q5.2) */
 982         u8 itssi_a;             /* Idle TSSI Target for A-PHY */
 983         u8 itssi_bg;            /* Idle TSSI Target for B/G-PHY */
 984         u8 tri2g;               /* 2.4GHz TX isolation */
 985 @@ -61,8 +71,8 @@ struct ssb_sprom {
 986         u8 txpid5gl[4];         /* 4.9 - 5.1GHz TX power index */
 987         u8 txpid5g[4];          /* 5.1 - 5.5GHz TX power index */
 988         u8 txpid5gh[4];         /* 5.5 - ...GHz TX power index */
 989 -       u8 rxpo2g;              /* 2GHz RX power offset */
 990 -       u8 rxpo5g;              /* 5GHz RX power offset */
 991 +       s8 rxpo2g;              /* 2GHz RX power offset */
 992 +       s8 rxpo5g;              /* 5GHz RX power offset */
 993         u8 rssisav2g;           /* 2GHz RSSI params */
 994         u8 rssismc2g;
 995         u8 rssismf2g;
 996 @@ -82,16 +92,13 @@ struct ssb_sprom {
 997         u16 boardflags2_hi;     /* Board flags (bits 48-63) */
 998         /* TODO store board flags in a single u64 */
 999
1000 +       struct ssb_sprom_core_pwr_info core_pwr_info[4];
1001 +
1002         /* Antenna gain values for up to 4 antennas
1003          * on each band. Values in dBm/4 (Q5.2). Negative gain means the
1004          * loss in the connectors is bigger than the gain. */
1005         struct {
1006 -               struct {
1007 -                       s8 a0, a1, a2, a3;
1008 -               } ghz24;        /* 2.4GHz band */
1009 -               struct {
1010 -                       s8 a0, a1, a2, a3;
1011 -               } ghz5;         /* 5GHz band */
1012 +               s8 a0, a1, a2, a3;
1013         } antenna_gain;
1014
1015         struct {
1016 @@ -103,14 +110,85 @@ struct ssb_sprom {
1017                 } ghz5;
1018         } fem;
1019
1020 -       /* TODO - add any parameters needed from rev 2, 3, 4, 5 or 8 SPROMs */
1021 +       u16 mcs2gpo[8];
1022 +       u16 mcs5gpo[8];
1023 +       u16 mcs5glpo[8];
1024 +       u16 mcs5ghpo[8];
1025 +       u8 opo;
1026 +
1027 +       u8 rxgainerr2ga[3];
1028 +       u8 rxgainerr5gla[3];
1029 +       u8 rxgainerr5gma[3];
1030 +       u8 rxgainerr5gha[3];
1031 +       u8 rxgainerr5gua[3];
1032 +
1033 +       u8 noiselvl2ga[3];
1034 +       u8 noiselvl5gla[3];
1035 +       u8 noiselvl5gma[3];
1036 +       u8 noiselvl5gha[3];
1037 +       u8 noiselvl5gua[3];
1038 +
1039 +       u8 regrev;
1040 +       u8 txchain;
1041 +       u8 rxchain;
1042 +       u8 antswitch;
1043 +       u16 cddpo;
1044 +       u16 stbcpo;
1045 +       u16 bw40po;
1046 +       u16 bwduppo;
1047 +
1048 +       u8 tempthresh;
1049 +       u8 tempoffset;
1050 +       u16 rawtempsense;
1051 +       u8 measpower;
1052 +       u8 tempsense_slope;
1053 +       u8 tempcorrx;
1054 +       u8 tempsense_option;
1055 +       u8 freqoffset_corr;
1056 +       u8 iqcal_swp_dis;
1057 +       u8 hw_iqcal_en;
1058 +       u8 elna2g;
1059 +       u8 elna5g;
1060 +       u8 phycal_tempdelta;
1061 +       u8 temps_period;
1062 +       u8 temps_hysteresis;
1063 +       u8 measpower1;
1064 +       u8 measpower2;
1065 +       u8 pcieingress_war;
1066 +
1067 +       /* power per rate from sromrev 9 */
1068 +       u16 cckbw202gpo;
1069 +       u16 cckbw20ul2gpo;
1070 +       u32 legofdmbw202gpo;
1071 +       u32 legofdmbw20ul2gpo;
1072 +       u32 legofdmbw205glpo;
1073 +       u32 legofdmbw20ul5glpo;
1074 +       u32 legofdmbw205gmpo;
1075 +       u32 legofdmbw20ul5gmpo;
1076 +       u32 legofdmbw205ghpo;
1077 +       u32 legofdmbw20ul5ghpo;
1078 +       u32 mcsbw202gpo;
1079 +       u32 mcsbw20ul2gpo;
1080 +       u32 mcsbw402gpo;
1081 +       u32 mcsbw205glpo;
1082 +       u32 mcsbw20ul5glpo;
1083 +       u32 mcsbw405glpo;
1084 +       u32 mcsbw205gmpo;
1085 +       u32 mcsbw20ul5gmpo;
1086 +       u32 mcsbw405gmpo;
1087 +       u32 mcsbw205ghpo;
1088 +       u32 mcsbw20ul5ghpo;
1089 +       u32 mcsbw405ghpo;
1090 +       u16 mcs32po;
1091 +       u16 legofdm40duppo;
1092 +       u8 sar2g;
1093 +       u8 sar5g;
1094  };
1095
1096  /* Information about the PCB the circuitry is soldered on. */
1097  struct ssb_boardinfo {
1098         u16 vendor;
1099         u16 type;
1100 -       u8  rev;
1101  };
1102
1103
1104 @@ -166,6 +244,7 @@ struct ssb_bus_ops {
1105  #define SSB_DEV_MINI_MACPHY    0x823
1106  #define SSB_DEV_ARM_1176       0x824
1107  #define SSB_DEV_ARM_7TDMI      0x825
1108 +#define SSB_DEV_ARM_CM3                0x82A
1109
1110  /* Vendor-ID values */
1111  #define SSB_VENDOR_BROADCOM    0x4243
1112 @@ -354,6 +433,7 @@ struct ssb_bus {
1113  #ifdef CONFIG_SSB_EMBEDDED
1114         /* Lock for GPIO register access. */
1115         spinlock_t gpio_lock;
1116 +       struct platform_device *watchdog;
1117  #endif /* EMBEDDED */
1118
1119         /* Internal-only stuff follows. Do not touch. */
1120 --- a/include/linux/ssb/ssb_driver_chipcommon.h
1121 +++ b/include/linux/ssb/ssb_driver_chipcommon.h
1122 @@ -504,7 +504,9 @@
1123  #define SSB_CHIPCO_FLASHCTL_ST_SE      0x02D8          /* Sector Erase */
1124  #define SSB_CHIPCO_FLASHCTL_ST_BE      0x00C7          /* Bulk Erase */
1125  #define SSB_CHIPCO_FLASHCTL_ST_DP      0x00B9          /* Deep Power-down */
1126 -#define SSB_CHIPCO_FLASHCTL_ST_RSIG    0x03AB          /* Read Electronic Signature */
1127 +#define SSB_CHIPCO_FLASHCTL_ST_RES     0x03AB          /* Read Electronic Signature */
1128 +#define SSB_CHIPCO_FLASHCTL_ST_CSA     0x1000          /* Keep chip select asserted */
1129 +#define SSB_CHIPCO_FLASHCTL_ST_SSE     0x0220          /* Sub-sector Erase */
1130
1131  /* Status register bits for ST flashes */
1132  #define SSB_CHIPCO_FLASHSTA_ST_WIP     0x01            /* Write In Progress */
1133 @@ -589,6 +591,8 @@ struct ssb_chipcommon {
1134         /* Fast Powerup Delay constant */
1135         u16 fast_pwrup_delay;
1136         struct ssb_chipcommon_pmu pmu;
1137 +       u32 ticks_per_ms;
1138 +       u32 max_timer_ms;
1139  };
1140
1141  static inline bool ssb_chipco_available(struct ssb_chipcommon *cc)
1142 @@ -628,8 +632,7 @@ enum ssb_clkmode {
1143  extern void ssb_chipco_set_clockmode(struct ssb_chipcommon *cc,
1144                                      enum ssb_clkmode mode);
1145
1146 -extern void ssb_chipco_watchdog_timer_set(struct ssb_chipcommon *cc,
1147 -                                         u32 ticks);
1148 +extern u32 ssb_chipco_watchdog_timer_set(struct ssb_chipcommon *cc, u32 ticks);
1149
1150  void ssb_chipco_irq_mask(struct ssb_chipcommon *cc, u32 mask, u32 value);
1151
1152 --- a/include/linux/ssb/ssb_driver_extif.h
1153 +++ b/include/linux/ssb/ssb_driver_extif.h
1154 @@ -152,6 +152,9 @@
1155  /* watchdog */
1156  #define SSB_EXTIF_WATCHDOG_CLK         48000000        /* Hz */
1157
1158 +#define SSB_EXTIF_WATCHDOG_MAX_TIMER   ((1 << 28) - 1)
1159 +#define SSB_EXTIF_WATCHDOG_MAX_TIMER_MS        (SSB_EXTIF_WATCHDOG_MAX_TIMER \
1160 +                                        / (SSB_EXTIF_WATCHDOG_CLK / 1000))
1161
1162
1163  #ifdef CONFIG_SSB_DRIVER_EXTIF
1164 @@ -171,8 +174,7 @@ extern void ssb_extif_get_clockcontrol(s
1165  extern void ssb_extif_timing_init(struct ssb_extif *extif,
1166                                   unsigned long ns);
1167
1168 -extern void ssb_extif_watchdog_timer_set(struct ssb_extif *extif,
1169 -                                        u32 ticks);
1170 +extern u32 ssb_extif_watchdog_timer_set(struct ssb_extif *extif, u32 ticks);
1171
1172  /* Extif GPIO pin access */
1173  u32 ssb_extif_gpio_in(struct ssb_extif *extif, u32 mask);
1174 @@ -205,10 +207,52 @@ void ssb_extif_get_clockcontrol(struct s
1175  }
1176
1177  static inline
1178 -void ssb_extif_watchdog_timer_set(struct ssb_extif *extif,
1179 -                                 u32 ticks)
1180 +void ssb_extif_timing_init(struct ssb_extif *extif, unsigned long ns)
1181  {
1182  }
1183
1184 +static inline
1185 +u32 ssb_extif_watchdog_timer_set(struct ssb_extif *extif, u32 ticks)
1186 +{
1187 +       return 0;
1188 +}
1189 +
1190 +static inline u32 ssb_extif_gpio_in(struct ssb_extif *extif, u32 mask)
1191 +{
1192 +       return 0;
1193 +}
1194 +
1195 +static inline u32 ssb_extif_gpio_out(struct ssb_extif *extif, u32 mask,
1196 +                                    u32 value)
1197 +{
1198 +       return 0;
1199 +}
1200 +
1201 +static inline u32 ssb_extif_gpio_outen(struct ssb_extif *extif, u32 mask,
1202 +                                      u32 value)
1203 +{
1204 +       return 0;
1205 +}
1206 +
1207 +static inline u32 ssb_extif_gpio_polarity(struct ssb_extif *extif, u32 mask,
1208 +                                         u32 value)
1209 +{
1210 +       return 0;
1211 +}
1212 +
1213 +static inline u32 ssb_extif_gpio_intmask(struct ssb_extif *extif, u32 mask,
1214 +                                        u32 value)
1215 +{
1216 +       return 0;
1217 +}
1218 +
1219 +#ifdef CONFIG_SSB_SERIAL
1220 +static inline int ssb_extif_serial_init(struct ssb_extif *extif,
1221 +                                       struct ssb_serial_port *ports)
1222 +{
1223 +       return 0;
1224 +}
1225 +#endif /* CONFIG_SSB_SERIAL */
1226 +
1227  #endif /* CONFIG_SSB_DRIVER_EXTIF */
1228  #endif /* LINUX_SSB_EXTIFCORE_H_ */
1229 --- a/include/linux/ssb/ssb_driver_gige.h
1230 +++ b/include/linux/ssb/ssb_driver_gige.h
1231 @@ -2,6 +2,7 @@
1232  #define LINUX_SSB_DRIVER_GIGE_H_
1233
1234  #include <linux/ssb/ssb.h>
1235 +#include <linux/bug.h>
1236  #include <linux/pci.h>
1237  #include <linux/spinlock.h>
1238
1239 --- a/include/linux/ssb/ssb_driver_mips.h
1240 +++ b/include/linux/ssb/ssb_driver_mips.h
1241 @@ -13,6 +13,12 @@ struct ssb_serial_port {
1242         unsigned int reg_shift;
1243  };
1244
1245 +struct ssb_pflash {
1246 +       bool present;
1247 +       u8 buswidth;
1248 +       u32 window;
1249 +       u32 window_size;
1250 +};
1251
1252  struct ssb_mipscore {
1253         struct ssb_device *dev;
1254 @@ -20,9 +26,7 @@ struct ssb_mipscore {
1255         int nr_serial_ports;
1256         struct ssb_serial_port serial_ports[4];
1257
1258 -       u8 flash_buswidth;
1259 -       u32 flash_window;
1260 -       u32 flash_window_size;
1261 +       struct ssb_pflash pflash;
1262  };
1263
1264  extern void ssb_mipscore_init(struct ssb_mipscore *mcore);
1265 --- a/include/linux/ssb/ssb_regs.h
1266 +++ b/include/linux/ssb/ssb_regs.h
1267 @@ -228,6 +228,7 @@
1268  #define  SSB_SPROM1_AGAIN_BG_SHIFT     0
1269  #define  SSB_SPROM1_AGAIN_A            0xFF00  /* A-PHY */
1270  #define  SSB_SPROM1_AGAIN_A_SHIFT      8
1271 +#define SSB_SPROM1_CCODE               0x0076
1272
1273  /* SPROM Revision 2 (inherits from rev 1) */
1274  #define SSB_SPROM2_BFLHI               0x0038  /* Boardflags (high 16 bits) */
1275 @@ -267,6 +268,7 @@
1276  #define  SSB_SPROM3_OFDMGPO            0x107A  /* G-PHY OFDM Power Offset (4 bytes, BigEndian) */
1277
1278  /* SPROM Revision 4 */
1279 +#define SSB_SPROM4_BOARDREV            0x0042  /* Board revision */
1280  #define SSB_SPROM4_BFLLO               0x0044  /* Boardflags (low 16 bits) */
1281  #define SSB_SPROM4_BFLHI               0x0046  /* Board Flags Hi */
1282  #define SSB_SPROM4_BFL2LO              0x0048  /* Board flags 2 (low 16 bits) */
1283 @@ -389,6 +391,11 @@
1284  #define  SSB_SPROM8_GPIOB_P2           0x00FF  /* Pin 2 */
1285  #define  SSB_SPROM8_GPIOB_P3           0xFF00  /* Pin 3 */
1286  #define  SSB_SPROM8_GPIOB_P3_SHIFT     8
1287 +#define SSB_SPROM8_LEDDC               0x009A
1288 +#define  SSB_SPROM8_LEDDC_ON           0xFF00  /* oncount */
1289 +#define  SSB_SPROM8_LEDDC_ON_SHIFT     8
1290 +#define  SSB_SPROM8_LEDDC_OFF          0x00FF  /* offcount */
1291 +#define  SSB_SPROM8_LEDDC_OFF_SHIFT    0
1292  #define SSB_SPROM8_ANTAVAIL            0x009C  /* Antenna available bitfields*/
1293  #define  SSB_SPROM8_ANTAVAIL_A         0xFF00  /* A-PHY bitfield */
1294  #define  SSB_SPROM8_ANTAVAIL_A_SHIFT   8
1295 @@ -404,6 +411,13 @@
1296  #define  SSB_SPROM8_AGAIN2_SHIFT       0
1297  #define  SSB_SPROM8_AGAIN3             0xFF00  /* Antenna 3 */
1298  #define  SSB_SPROM8_AGAIN3_SHIFT       8
1299 +#define SSB_SPROM8_TXRXC               0x00A2
1300 +#define  SSB_SPROM8_TXRXC_TXCHAIN      0x000f
1301 +#define  SSB_SPROM8_TXRXC_TXCHAIN_SHIFT        0
1302 +#define  SSB_SPROM8_TXRXC_RXCHAIN      0x00f0
1303 +#define  SSB_SPROM8_TXRXC_RXCHAIN_SHIFT        4
1304 +#define  SSB_SPROM8_TXRXC_SWITCH       0xff00
1305 +#define  SSB_SPROM8_TXRXC_SWITCH_SHIFT 8
1306  #define SSB_SPROM8_RSSIPARM2G          0x00A4  /* RSSI params for 2GHz */
1307  #define  SSB_SPROM8_RSSISMF2G          0x000F
1308  #define  SSB_SPROM8_RSSISMC2G          0x00F0
1309 @@ -430,6 +444,7 @@
1310  #define  SSB_SPROM8_TRI5GH_SHIFT       8
1311  #define SSB_SPROM8_RXPO                        0x00AC  /* RX power offsets */
1312  #define  SSB_SPROM8_RXPO2G             0x00FF  /* 2GHz RX power offset */
1313 +#define  SSB_SPROM8_RXPO2G_SHIFT       0
1314  #define  SSB_SPROM8_RXPO5G             0xFF00  /* 5GHz RX power offset */
1315  #define  SSB_SPROM8_RXPO5G_SHIFT       8
1316  #define SSB_SPROM8_FEM2G               0x00AE
1317 @@ -445,10 +460,71 @@
1318  #define  SSB_SROM8_FEM_ANTSWLUT                0xF800
1319  #define  SSB_SROM8_FEM_ANTSWLUT_SHIFT  11
1320  #define SSB_SPROM8_THERMAL             0x00B2
1321 -#define SSB_SPROM8_MPWR_RAWTS          0x00B4
1322 -#define SSB_SPROM8_TS_SLP_OPT_CORRX    0x00B6
1323 -#define SSB_SPROM8_FOC_HWIQ_IQSWP      0x00B8
1324 -#define SSB_SPROM8_PHYCAL_TEMPDELTA    0x00BA
1325 +#define  SSB_SPROM8_THERMAL_OFFSET     0x00ff
1326 +#define  SSB_SPROM8_THERMAL_OFFSET_SHIFT       0
1327 +#define  SSB_SPROM8_THERMAL_TRESH      0xff00
1328 +#define  SSB_SPROM8_THERMAL_TRESH_SHIFT        8
1329 +/* Temp sense related entries */
1330 +#define SSB_SPROM8_RAWTS               0x00B4
1331 +#define  SSB_SPROM8_RAWTS_RAWTEMP      0x01ff
1332 +#define  SSB_SPROM8_RAWTS_RAWTEMP_SHIFT        0
1333 +#define  SSB_SPROM8_RAWTS_MEASPOWER    0xfe00
1334 +#define  SSB_SPROM8_RAWTS_MEASPOWER_SHIFT      9
1335 +#define SSB_SPROM8_OPT_CORRX           0x00B6
1336 +#define  SSB_SPROM8_OPT_CORRX_TEMP_SLOPE       0x00ff
1337 +#define  SSB_SPROM8_OPT_CORRX_TEMP_SLOPE_SHIFT 0
1338 +#define  SSB_SPROM8_OPT_CORRX_TEMPCORRX        0xfc00
1339 +#define  SSB_SPROM8_OPT_CORRX_TEMPCORRX_SHIFT  10
1340 +#define  SSB_SPROM8_OPT_CORRX_TEMP_OPTION      0x0300
1341 +#define  SSB_SPROM8_OPT_CORRX_TEMP_OPTION_SHIFT        8
1342 +/* FOC: freiquency offset correction, HWIQ: H/W IOCAL enable, IQSWP: IQ CAL swap disable */
1343 +#define SSB_SPROM8_HWIQ_IQSWP          0x00B8
1344 +#define  SSB_SPROM8_HWIQ_IQSWP_FREQ_CORR       0x000f
1345 +#define  SSB_SPROM8_HWIQ_IQSWP_FREQ_CORR_SHIFT 0
1346 +#define  SSB_SPROM8_HWIQ_IQSWP_IQCAL_SWP       0x0010
1347 +#define  SSB_SPROM8_HWIQ_IQSWP_IQCAL_SWP_SHIFT 4
1348 +#define  SSB_SPROM8_HWIQ_IQSWP_HW_IQCAL        0x0020
1349 +#define  SSB_SPROM8_HWIQ_IQSWP_HW_IQCAL_SHIFT  5
1350 +#define SSB_SPROM8_TEMPDELTA           0x00BC
1351 +#define  SSB_SPROM8_TEMPDELTA_PHYCAL   0x00ff
1352 +#define  SSB_SPROM8_TEMPDELTA_PHYCAL_SHIFT     0
1353 +#define  SSB_SPROM8_TEMPDELTA_PERIOD   0x0f00
1354 +#define  SSB_SPROM8_TEMPDELTA_PERIOD_SHIFT     8
1355 +#define  SSB_SPROM8_TEMPDELTA_HYSTERESIS       0xf000
1356 +#define  SSB_SPROM8_TEMPDELTA_HYSTERESIS_SHIFT 12
1357 +
1358 +/* There are 4 blocks with power info sharing the same layout */
1359 +#define SSB_SROM8_PWR_INFO_CORE0       0x00C0
1360 +#define SSB_SROM8_PWR_INFO_CORE1       0x00E0
1361 +#define SSB_SROM8_PWR_INFO_CORE2       0x0100
1362 +#define SSB_SROM8_PWR_INFO_CORE3       0x0120
1363 +
1364 +#define SSB_SROM8_2G_MAXP_ITSSI                0x00
1365 +#define  SSB_SPROM8_2G_MAXP            0x00FF
1366 +#define  SSB_SPROM8_2G_ITSSI           0xFF00
1367 +#define  SSB_SPROM8_2G_ITSSI_SHIFT     8
1368 +#define SSB_SROM8_2G_PA_0              0x02    /* 2GHz power amp settings */
1369 +#define SSB_SROM8_2G_PA_1              0x04
1370 +#define SSB_SROM8_2G_PA_2              0x06
1371 +#define SSB_SROM8_5G_MAXP_ITSSI                0x08    /* 5GHz ITSSI and 5.3GHz Max Power */
1372 +#define  SSB_SPROM8_5G_MAXP            0x00FF
1373 +#define  SSB_SPROM8_5G_ITSSI           0xFF00
1374 +#define  SSB_SPROM8_5G_ITSSI_SHIFT     8
1375 +#define SSB_SPROM8_5GHL_MAXP           0x0A    /* 5.2GHz and 5.8GHz Max Power */
1376 +#define  SSB_SPROM8_5GH_MAXP           0x00FF
1377 +#define  SSB_SPROM8_5GL_MAXP           0xFF00
1378 +#define  SSB_SPROM8_5GL_MAXP_SHIFT     8
1379 +#define SSB_SROM8_5G_PA_0              0x0C    /* 5.3GHz power amp settings */
1380 +#define SSB_SROM8_5G_PA_1              0x0E
1381 +#define SSB_SROM8_5G_PA_2              0x10
1382 +#define SSB_SROM8_5GL_PA_0             0x12    /* 5.2GHz power amp settings */
1383 +#define SSB_SROM8_5GL_PA_1             0x14
1384 +#define SSB_SROM8_5GL_PA_2             0x16
1385 +#define SSB_SROM8_5GH_PA_0             0x18    /* 5.8GHz power amp settings */
1386 +#define SSB_SROM8_5GH_PA_1             0x1A
1387 +#define SSB_SROM8_5GH_PA_2             0x1C
1388 +
1389 +/* TODO: Make it deprecated */
1390  #define SSB_SPROM8_MAXP_BG             0x00C0  /* Max Power 2GHz in path 1 */
1391  #define  SSB_SPROM8_MAXP_BG_MASK       0x00FF  /* Mask for Max Power 2GHz */
1392  #define  SSB_SPROM8_ITSSI_BG           0xFF00  /* Mask for path 1 itssi_bg */
1393 @@ -473,12 +549,23 @@
1394  #define SSB_SPROM8_PA1HIB0             0x00D8  /* 5.8GHz power amp settings */
1395  #define SSB_SPROM8_PA1HIB1             0x00DA
1396  #define SSB_SPROM8_PA1HIB2             0x00DC
1397 +
1398  #define SSB_SPROM8_CCK2GPO             0x0140  /* CCK power offset */
1399  #define SSB_SPROM8_OFDM2GPO            0x0142  /* 2.4GHz OFDM power offset */
1400  #define SSB_SPROM8_OFDM5GPO            0x0146  /* 5.3GHz OFDM power offset */
1401  #define SSB_SPROM8_OFDM5GLPO           0x014A  /* 5.2GHz OFDM power offset */
1402  #define SSB_SPROM8_OFDM5GHPO           0x014E  /* 5.8GHz OFDM power offset */
1403
1404 +#define SSB_SPROM8_2G_MCSPO            0x0152
1405 +#define SSB_SPROM8_5G_MCSPO            0x0162
1406 +#define SSB_SPROM8_5GL_MCSPO           0x0172
1407 +#define SSB_SPROM8_5GH_MCSPO           0x0182
1408 +
1409 +#define SSB_SPROM8_CDDPO               0x0192
1410 +#define SSB_SPROM8_STBCPO              0x0194
1411 +#define SSB_SPROM8_BW40PO              0x0196
1412 +#define SSB_SPROM8_BWDUPPO             0x0198
1413 +
1414  /* Values for boardflags_lo read from SPROM */
1415  #define SSB_BFL_BTCOEXIST              0x0001  /* implements Bluetooth coexistance */
1416  #define SSB_BFL_PACTRL                 0x0002  /* GPIO 9 controlling the PA */