target/linux/generic/files/drivers/net/phy/ar8216.c

   1 /*
   2  * ar8216.c: AR8216 switch driver
   3  *
   4  * Copyright (C) 2009 Felix Fietkau <nbd@openwrt.org>
   5  * Copyright (C) 2011-2012 Gabor Juhos <juhosg@openwrt.org>
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License
   9  * as published by the Free Software Foundation; either version 2
  10  * of the License, or (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  */
  17
  18 #include <linux/if.h>
  19 #include <linux/module.h>
  20 #include <linux/init.h>
  21 #include <linux/list.h>
  22 #include <linux/if_ether.h>
  23 #include <linux/skbuff.h>
  24 #include <linux/netdevice.h>
  25 #include <linux/netlink.h>
  26 #include <linux/bitops.h>
  27 #include <net/genetlink.h>
  28 #include <linux/switch.h>
  29 #include <linux/delay.h>
  30 #include <linux/phy.h>
  31 #include <linux/netdevice.h>
  32 #include <linux/etherdevice.h>
  33 #include <linux/lockdep.h>
  34 #include <linux/ar8216_platform.h>
  35 #include <linux/workqueue.h>
  36 #include <linux/of_device.h>
  37 #include <linux/leds.h>
  38 #include <linux/gpio.h>
  39 #include <linux/version.h>
  40
  41 #include "ar8216.h"
  42
  43 /* size of the vlan table */
  44 #define AR8X16_MAX_VLANS        128
  45 #define AR8X16_PROBE_RETRIES    10
  46 #define AR8X16_MAX_PORTS        8
  47
  48 #define AR8XXX_MIB_WORK_DELAY   2000 /* msecs */
  49
  50 struct ar8xxx_priv;
  51
  52 #define AR8XXX_CAP_GIGE                 BIT(0)
  53 #define AR8XXX_CAP_MIB_COUNTERS         BIT(1)
  54
  55 #define AR8XXX_NUM_PHYS         5
  56
  57 enum {
  58         AR8XXX_VER_AR8216 = 0x01,
  59         AR8XXX_VER_AR8236 = 0x03,
  60         AR8XXX_VER_AR8316 = 0x10,
  61         AR8XXX_VER_AR8327 = 0x12,
  62         AR8XXX_VER_AR8337 = 0x13,
  63 };
  64
  65 struct ar8xxx_mib_desc {
  66         unsigned int size;
  67         unsigned int offset;
  68         const char *name;
  69 };
  70
  71 struct ar8xxx_chip {
  72         unsigned long caps;
  73         bool config_at_probe;
  74         bool mii_lo_first;
  75
  76         /* parameters to calculate REG_PORT_STATS_BASE */
  77         unsigned reg_port_stats_start;
  78         unsigned reg_port_stats_length;
  79
  80         int (*hw_init)(struct ar8xxx_priv *priv);
  81         void (*cleanup)(struct ar8xxx_priv *priv);
  82
  83         const char *name;
  84         int vlans;
  85         int ports;
  86         const struct switch_dev_ops *swops;
  87
  88         void (*init_globals)(struct ar8xxx_priv *priv);
  89         void (*init_port)(struct ar8xxx_priv *priv, int port);
  90         void (*setup_port)(struct ar8xxx_priv *priv, int port, u32 members);
  91         u32 (*read_port_status)(struct ar8xxx_priv *priv, int port);
  92         int (*atu_flush)(struct ar8xxx_priv *priv);
  93         void (*vtu_flush)(struct ar8xxx_priv *priv);
  94         void (*vtu_load_vlan)(struct ar8xxx_priv *priv, u32 vid, u32 port_mask);
  95         void (*phy_fixup)(struct ar8xxx_priv *priv, int phy);
  96         void (*set_mirror_regs)(struct ar8xxx_priv *priv);
  97
  98         const struct ar8xxx_mib_desc *mib_decs;
  99         unsigned num_mibs;
 100         unsigned mib_func;
 101 };
 102
 103 enum ar8327_led_pattern {
 104         AR8327_LED_PATTERN_OFF = 0,
 105         AR8327_LED_PATTERN_BLINK,
 106         AR8327_LED_PATTERN_ON,
 107         AR8327_LED_PATTERN_RULE,
 108 };
 109
 110 struct ar8327_led_entry {
 111         unsigned reg;
 112         unsigned shift;
 113 };
 114
 115 struct ar8327_led {
 116         struct led_classdev cdev;
 117         struct ar8xxx_priv *sw_priv;
 118
 119         char *name;
 120         bool active_low;
 121         u8 led_num;
 122         enum ar8327_led_mode mode;
 123
 124         struct mutex mutex;
 125         spinlock_t lock;
 126         struct work_struct led_work;
 127         bool enable_hw_mode;
 128         enum ar8327_led_pattern pattern;
 129 };
 130
 131 struct ar8327_data {
 132         u32 port0_status;
 133         u32 port6_status;
 134
 135         struct ar8327_led **leds;
 136         unsigned int num_leds;
 137 };
 138
 139 struct ar8xxx_priv {
 140         struct switch_dev dev;
 141         struct mii_bus *mii_bus;
 142         struct phy_device *phy;
 143
 144         u32 (*read)(struct ar8xxx_priv *priv, int reg);
 145         void (*write)(struct ar8xxx_priv *priv, int reg, u32 val);
 146         u32 (*rmw)(struct ar8xxx_priv *priv, int reg, u32 mask, u32 val);
 147
 148         int (*get_port_link)(unsigned port);
 149
 150         const struct net_device_ops *ndo_old;
 151         struct net_device_ops ndo;
 152         struct mutex reg_mutex;
 153         u8 chip_ver;
 154         u8 chip_rev;
 155         const struct ar8xxx_chip *chip;
 156         void *chip_data;
 157         bool initialized;
 158         bool port4_phy;
 159         char buf[2048];
 160
 161         bool init;
 162
 163         struct mutex mib_lock;
 164         struct delayed_work mib_work;
 165         int mib_next_port;
 166         u64 *mib_stats;
 167
 168         struct list_head list;
 169         unsigned int use_count;
 170
 171         /* all fields below are cleared on reset */
 172         bool vlan;
 173         u16 vlan_id[AR8X16_MAX_VLANS];
 174         u8 vlan_table[AR8X16_MAX_VLANS];
 175         u8 vlan_tagged;
 176         u16 pvid[AR8X16_MAX_PORTS];
 177
 178         /* mirroring */
 179         bool mirror_rx;
 180         bool mirror_tx;
 181         int source_port;
 182         int monitor_port;
 183 };
 184
 185 #define MIB_DESC(_s , _o, _n)   \
 186         {                       \
 187                 .size = (_s),   \
 188                 .offset = (_o), \
 189                 .name = (_n),   \
 190         }
 191
 192 static const struct ar8xxx_mib_desc ar8216_mibs[] = {
 193         MIB_DESC(1, AR8216_STATS_RXBROAD, "RxBroad"),
 194         MIB_DESC(1, AR8216_STATS_RXPAUSE, "RxPause"),
 195         MIB_DESC(1, AR8216_STATS_RXMULTI, "RxMulti"),
 196         MIB_DESC(1, AR8216_STATS_RXFCSERR, "RxFcsErr"),
 197         MIB_DESC(1, AR8216_STATS_RXALIGNERR, "RxAlignErr"),
 198         MIB_DESC(1, AR8216_STATS_RXRUNT, "RxRunt"),
 199         MIB_DESC(1, AR8216_STATS_RXFRAGMENT, "RxFragment"),
 200         MIB_DESC(1, AR8216_STATS_RX64BYTE, "Rx64Byte"),
 201         MIB_DESC(1, AR8216_STATS_RX128BYTE, "Rx128Byte"),
 202         MIB_DESC(1, AR8216_STATS_RX256BYTE, "Rx256Byte"),
 203         MIB_DESC(1, AR8216_STATS_RX512BYTE, "Rx512Byte"),
 204         MIB_DESC(1, AR8216_STATS_RX1024BYTE, "Rx1024Byte"),
 205         MIB_DESC(1, AR8216_STATS_RXMAXBYTE, "RxMaxByte"),
 206         MIB_DESC(1, AR8216_STATS_RXTOOLONG, "RxTooLong"),
 207         MIB_DESC(2, AR8216_STATS_RXGOODBYTE, "RxGoodByte"),
 208         MIB_DESC(2, AR8216_STATS_RXBADBYTE, "RxBadByte"),
 209         MIB_DESC(1, AR8216_STATS_RXOVERFLOW, "RxOverFlow"),
 210         MIB_DESC(1, AR8216_STATS_FILTERED, "Filtered"),
 211         MIB_DESC(1, AR8216_STATS_TXBROAD, "TxBroad"),
 212         MIB_DESC(1, AR8216_STATS_TXPAUSE, "TxPause"),
 213         MIB_DESC(1, AR8216_STATS_TXMULTI, "TxMulti"),
 214         MIB_DESC(1, AR8216_STATS_TXUNDERRUN, "TxUnderRun"),
 215         MIB_DESC(1, AR8216_STATS_TX64BYTE, "Tx64Byte"),
 216         MIB_DESC(1, AR8216_STATS_TX128BYTE, "Tx128Byte"),
 217         MIB_DESC(1, AR8216_STATS_TX256BYTE, "Tx256Byte"),
 218         MIB_DESC(1, AR8216_STATS_TX512BYTE, "Tx512Byte"),
 219         MIB_DESC(1, AR8216_STATS_TX1024BYTE, "Tx1024Byte"),
 220         MIB_DESC(1, AR8216_STATS_TXMAXBYTE, "TxMaxByte"),
 221         MIB_DESC(1, AR8216_STATS_TXOVERSIZE, "TxOverSize"),
 222         MIB_DESC(2, AR8216_STATS_TXBYTE, "TxByte"),
 223         MIB_DESC(1, AR8216_STATS_TXCOLLISION, "TxCollision"),
 224         MIB_DESC(1, AR8216_STATS_TXABORTCOL, "TxAbortCol"),
 225         MIB_DESC(1, AR8216_STATS_TXMULTICOL, "TxMultiCol"),
 226         MIB_DESC(1, AR8216_STATS_TXSINGLECOL, "TxSingleCol"),
 227         MIB_DESC(1, AR8216_STATS_TXEXCDEFER, "TxExcDefer"),
 228         MIB_DESC(1, AR8216_STATS_TXDEFER, "TxDefer"),
 229         MIB_DESC(1, AR8216_STATS_TXLATECOL, "TxLateCol"),
 230 };
 231
 232 static const struct ar8xxx_mib_desc ar8236_mibs[] = {
 233         MIB_DESC(1, AR8236_STATS_RXBROAD, "RxBroad"),
 234         MIB_DESC(1, AR8236_STATS_RXPAUSE, "RxPause"),
 235         MIB_DESC(1, AR8236_STATS_RXMULTI, "RxMulti"),
 236         MIB_DESC(1, AR8236_STATS_RXFCSERR, "RxFcsErr"),
 237         MIB_DESC(1, AR8236_STATS_RXALIGNERR, "RxAlignErr"),
 238         MIB_DESC(1, AR8236_STATS_RXRUNT, "RxRunt"),
 239         MIB_DESC(1, AR8236_STATS_RXFRAGMENT, "RxFragment"),
 240         MIB_DESC(1, AR8236_STATS_RX64BYTE, "Rx64Byte"),
 241         MIB_DESC(1, AR8236_STATS_RX128BYTE, "Rx128Byte"),
 242         MIB_DESC(1, AR8236_STATS_RX256BYTE, "Rx256Byte"),
 243         MIB_DESC(1, AR8236_STATS_RX512BYTE, "Rx512Byte"),
 244         MIB_DESC(1, AR8236_STATS_RX1024BYTE, "Rx1024Byte"),
 245         MIB_DESC(1, AR8236_STATS_RX1518BYTE, "Rx1518Byte"),
 246         MIB_DESC(1, AR8236_STATS_RXMAXBYTE, "RxMaxByte"),
 247         MIB_DESC(1, AR8236_STATS_RXTOOLONG, "RxTooLong"),
 248         MIB_DESC(2, AR8236_STATS_RXGOODBYTE, "RxGoodByte"),
 249         MIB_DESC(2, AR8236_STATS_RXBADBYTE, "RxBadByte"),
 250         MIB_DESC(1, AR8236_STATS_RXOVERFLOW, "RxOverFlow"),
 251         MIB_DESC(1, AR8236_STATS_FILTERED, "Filtered"),
 252         MIB_DESC(1, AR8236_STATS_TXBROAD, "TxBroad"),
 253         MIB_DESC(1, AR8236_STATS_TXPAUSE, "TxPause"),
 254         MIB_DESC(1, AR8236_STATS_TXMULTI, "TxMulti"),
 255         MIB_DESC(1, AR8236_STATS_TXUNDERRUN, "TxUnderRun"),
 256         MIB_DESC(1, AR8236_STATS_TX64BYTE, "Tx64Byte"),
 257         MIB_DESC(1, AR8236_STATS_TX128BYTE, "Tx128Byte"),
 258         MIB_DESC(1, AR8236_STATS_TX256BYTE, "Tx256Byte"),
 259         MIB_DESC(1, AR8236_STATS_TX512BYTE, "Tx512Byte"),
 260         MIB_DESC(1, AR8236_STATS_TX1024BYTE, "Tx1024Byte"),
 261         MIB_DESC(1, AR8236_STATS_TX1518BYTE, "Tx1518Byte"),
 262         MIB_DESC(1, AR8236_STATS_TXMAXBYTE, "TxMaxByte"),
 263         MIB_DESC(1, AR8236_STATS_TXOVERSIZE, "TxOverSize"),
 264         MIB_DESC(2, AR8236_STATS_TXBYTE, "TxByte"),
 265         MIB_DESC(1, AR8236_STATS_TXCOLLISION, "TxCollision"),
 266         MIB_DESC(1, AR8236_STATS_TXABORTCOL, "TxAbortCol"),
 267         MIB_DESC(1, AR8236_STATS_TXMULTICOL, "TxMultiCol"),
 268         MIB_DESC(1, AR8236_STATS_TXSINGLECOL, "TxSingleCol"),
 269         MIB_DESC(1, AR8236_STATS_TXEXCDEFER, "TxExcDefer"),
 270         MIB_DESC(1, AR8236_STATS_TXDEFER, "TxDefer"),
 271         MIB_DESC(1, AR8236_STATS_TXLATECOL, "TxLateCol"),
 272 };
 273
 274 static DEFINE_MUTEX(ar8xxx_dev_list_lock);
 275 static LIST_HEAD(ar8xxx_dev_list);
 276
 277 static inline struct ar8xxx_priv *
 278 swdev_to_ar8xxx(struct switch_dev *swdev)
 279 {
 280         return container_of(swdev, struct ar8xxx_priv, dev);
 281 }
 282
 283 static inline bool ar8xxx_has_gige(struct ar8xxx_priv *priv)
 284 {
 285         return priv->chip->caps & AR8XXX_CAP_GIGE;
 286 }
 287
 288 static inline bool ar8xxx_has_mib_counters(struct ar8xxx_priv *priv)
 289 {
 290         return priv->chip->caps & AR8XXX_CAP_MIB_COUNTERS;
 291 }
 292
 293 static inline bool chip_is_ar8216(struct ar8xxx_priv *priv)
 294 {
 295         return priv->chip_ver == AR8XXX_VER_AR8216;
 296 }
 297
 298 static inline bool chip_is_ar8236(struct ar8xxx_priv *priv)
 299 {
 300         return priv->chip_ver == AR8XXX_VER_AR8236;
 301 }
 302
 303 static inline bool chip_is_ar8316(struct ar8xxx_priv *priv)
 304 {
 305         return priv->chip_ver == AR8XXX_VER_AR8316;
 306 }
 307
 308 static inline bool chip_is_ar8327(struct ar8xxx_priv *priv)
 309 {
 310         return priv->chip_ver == AR8XXX_VER_AR8327;
 311 }
 312
 313 static inline bool chip_is_ar8337(struct ar8xxx_priv *priv)
 314 {
 315         return priv->chip_ver == AR8XXX_VER_AR8337;
 316 }
 317
 318 static inline void
 319 split_addr(u32 regaddr, u16 *r1, u16 *r2, u16 *page)
 320 {
 321         regaddr >>= 1;
 322         *r1 = regaddr & 0x1e;
 323
 324         regaddr >>= 5;
 325         *r2 = regaddr & 0x7;
 326
 327         regaddr >>= 3;
 328         *page = regaddr & 0x1ff;
 329 }
 330
 331 /* inspired by phy_poll_reset in drivers/net/phy/phy_device.c */
 332 static int
 333 ar8xxx_phy_poll_reset(struct mii_bus *bus)
 334 {
 335         unsigned int sleep_msecs = 20;
 336         int ret, elapsed, i;
 337
 338         for (elapsed = sleep_msecs; elapsed <= 600;
 339              elapsed += sleep_msecs) {
 340                 msleep(sleep_msecs);
 341                 for (i = 0; i < AR8XXX_NUM_PHYS; i++) {
 342                         ret = mdiobus_read(bus, i, MII_BMCR);
 343                         if (ret < 0)
 344                                 return ret;
 345                         if (ret & BMCR_RESET)
 346                                 break;
 347                         if (i == AR8XXX_NUM_PHYS - 1) {
 348                                 usleep_range(1000, 2000);
 349                                 return 0;
 350                         }
 351                 }
 352         }
 353         return -ETIMEDOUT;
 354 }
 355
 356 static int
 357 ar8xxx_phy_check_aneg(struct phy_device *phydev)
 358 {
 359         int ret;
 360
 361         if (phydev->autoneg != AUTONEG_ENABLE)
 362                 return 0;
 363         /*
 364          * BMCR_ANENABLE might have been cleared
 365          * by phy_init_hw in certain kernel versions
 366          * therefore check for it
 367          */
 368         ret = phy_read(phydev, MII_BMCR);
 369         if (ret < 0)
 370                 return ret;
 371         if (ret & BMCR_ANENABLE)
 372                 return 0;
 373
 374         dev_info(&phydev->dev, "ANEG disabled, re-enabling ...\n");
 375         ret |= BMCR_ANENABLE | BMCR_ANRESTART;
 376         return phy_write(phydev, MII_BMCR, ret);
 377 }
 378
 379 static void
 380 ar8xxx_phy_init(struct ar8xxx_priv *priv)
 381 {
 382         int i;
 383         struct mii_bus *bus;
 384
 385         bus = priv->mii_bus;
 386         for (i = 0; i < AR8XXX_NUM_PHYS; i++) {
 387                 if (priv->chip->phy_fixup)
 388                         priv->chip->phy_fixup(priv, i);
 389
 390                 /* initialize the port itself */
 391                 mdiobus_write(bus, i, MII_ADVERTISE,
 392                         ADVERTISE_ALL | ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
 393                 if (ar8xxx_has_gige(priv))
 394                         mdiobus_write(bus, i, MII_CTRL1000, ADVERTISE_1000FULL);
 395                 mdiobus_write(bus, i, MII_BMCR, BMCR_RESET | BMCR_ANENABLE);
 396         }
 397
 398         ar8xxx_phy_poll_reset(bus);
 399 }
 400
 401 static u32
 402 ar8xxx_mii_read(struct ar8xxx_priv *priv, int reg)
 403 {
 404         struct mii_bus *bus = priv->mii_bus;
 405         u16 r1, r2, page;
 406         u16 lo, hi;
 407
 408         split_addr((u32) reg, &r1, &r2, &page);
 409
 410         mutex_lock(&bus->mdio_lock);
 411
 412         bus->write(bus, 0x18, 0, page);
 413         usleep_range(1000, 2000); /* wait for the page switch to propagate */
 414         lo = bus->read(bus, 0x10 | r2, r1);
 415         hi = bus->read(bus, 0x10 | r2, r1 + 1);
 416
 417         mutex_unlock(&bus->mdio_lock);
 418
 419         return (hi << 16) | lo;
 420 }
 421
 422 static void
 423 ar8xxx_mii_write(struct ar8xxx_priv *priv, int reg, u32 val)
 424 {
 425         struct mii_bus *bus = priv->mii_bus;
 426         u16 r1, r2, r3;
 427         u16 lo, hi;
 428
 429         split_addr((u32) reg, &r1, &r2, &r3);
 430         lo = val & 0xffff;
 431         hi = (u16) (val >> 16);
 432
 433         mutex_lock(&bus->mdio_lock);
 434
 435         bus->write(bus, 0x18, 0, r3);
 436         usleep_range(1000, 2000); /* wait for the page switch to propagate */
 437         if (priv->chip->mii_lo_first) {
 438                 bus->write(bus, 0x10 | r2, r1, lo);
 439                 bus->write(bus, 0x10 | r2, r1 + 1, hi);
 440         } else {
 441                 bus->write(bus, 0x10 | r2, r1 + 1, hi);
 442                 bus->write(bus, 0x10 | r2, r1, lo);
 443         }
 444
 445         mutex_unlock(&bus->mdio_lock);
 446 }
 447
 448 static u32
 449 ar8xxx_mii_rmw(struct ar8xxx_priv *priv, int reg, u32 mask, u32 val)
 450 {
 451         struct mii_bus *bus = priv->mii_bus;
 452         u16 r1, r2, page;
 453         u16 lo, hi;
 454         u32 ret;
 455
 456         split_addr((u32) reg, &r1, &r2, &page);
 457
 458         mutex_lock(&bus->mdio_lock);
 459
 460         bus->write(bus, 0x18, 0, page);
 461         usleep_range(1000, 2000); /* wait for the page switch to propagate */
 462
 463         lo = bus->read(bus, 0x10 | r2, r1);
 464         hi = bus->read(bus, 0x10 | r2, r1 + 1);
 465
 466         ret = hi << 16 | lo;
 467         ret &= ~mask;
 468         ret |= val;
 469
 470         lo = ret & 0xffff;
 471         hi = (u16) (ret >> 16);
 472
 473         if (priv->chip->mii_lo_first) {
 474                 bus->write(bus, 0x10 | r2, r1, lo);
 475                 bus->write(bus, 0x10 | r2, r1 + 1, hi);
 476         } else {
 477                 bus->write(bus, 0x10 | r2, r1 + 1, hi);
 478                 bus->write(bus, 0x10 | r2, r1, lo);
 479         }
 480
 481         mutex_unlock(&bus->mdio_lock);
 482
 483         return ret;
 484 }
 485
 486
 487 static void
 488 ar8xxx_phy_dbg_write(struct ar8xxx_priv *priv, int phy_addr,
 489                      u16 dbg_addr, u16 dbg_data)
 490 {
 491         struct mii_bus *bus = priv->mii_bus;
 492
 493         mutex_lock(&bus->mdio_lock);
 494         bus->write(bus, phy_addr, MII_ATH_DBG_ADDR, dbg_addr);
 495         bus->write(bus, phy_addr, MII_ATH_DBG_DATA, dbg_data);
 496         mutex_unlock(&bus->mdio_lock);
 497 }
 498
 499 static void
 500 ar8xxx_phy_mmd_write(struct ar8xxx_priv *priv, int phy_addr, u16 addr, u16 data)
 501 {
 502         struct mii_bus *bus = priv->mii_bus;
 503
 504         mutex_lock(&bus->mdio_lock);
 505         bus->write(bus, phy_addr, MII_ATH_MMD_ADDR, addr);
 506         bus->write(bus, phy_addr, MII_ATH_MMD_DATA, data);
 507         mutex_unlock(&bus->mdio_lock);
 508 }
 509
 510 static inline u32
 511 ar8xxx_rmw(struct ar8xxx_priv *priv, int reg, u32 mask, u32 val)
 512 {
 513         return priv->rmw(priv, reg, mask, val);
 514 }
 515
 516 static inline void
 517 ar8xxx_reg_set(struct ar8xxx_priv *priv, int reg, u32 val)
 518 {
 519         priv->rmw(priv, reg, 0, val);
 520 }
 521
 522 static int
 523 ar8xxx_reg_wait(struct ar8xxx_priv *priv, u32 reg, u32 mask, u32 val,
 524                 unsigned timeout)
 525 {
 526         int i;
 527
 528         for (i = 0; i < timeout; i++) {
 529                 u32 t;
 530
 531                 t = priv->read(priv, reg);
 532                 if ((t & mask) == val)
 533                         return 0;
 534
 535                 usleep_range(1000, 2000);
 536         }
 537
 538         return -ETIMEDOUT;
 539 }
 540
 541 static int
 542 ar8xxx_mib_op(struct ar8xxx_priv *priv, u32 op)
 543 {
 544         unsigned mib_func = priv->chip->mib_func;
 545         int ret;
 546
 547         lockdep_assert_held(&priv->mib_lock);
 548
 549         /* Capture the hardware statistics for all ports */
 550         ar8xxx_rmw(priv, mib_func, AR8216_MIB_FUNC, (op << AR8216_MIB_FUNC_S));
 551
 552         /* Wait for the capturing to complete. */
 553         ret = ar8xxx_reg_wait(priv, mib_func, AR8216_MIB_BUSY, 0, 10);
 554         if (ret)
 555                 goto out;
 556
 557         ret = 0;
 558
 559 out:
 560         return ret;
 561 }
 562
 563 static int
 564 ar8xxx_mib_capture(struct ar8xxx_priv *priv)
 565 {
 566         return ar8xxx_mib_op(priv, AR8216_MIB_FUNC_CAPTURE);
 567 }
 568
 569 static int
 570 ar8xxx_mib_flush(struct ar8xxx_priv *priv)
 571 {
 572         return ar8xxx_mib_op(priv, AR8216_MIB_FUNC_FLUSH);
 573 }
 574
 575 static void
 576 ar8xxx_mib_fetch_port_stat(struct ar8xxx_priv *priv, int port, bool flush)
 577 {
 578         unsigned int base;
 579         u64 *mib_stats;
 580         int i;
 581
 582         WARN_ON(port >= priv->dev.ports);
 583
 584         lockdep_assert_held(&priv->mib_lock);
 585
 586         base = priv->chip->reg_port_stats_start +
 587                priv->chip->reg_port_stats_length * port;
 588
 589         mib_stats = &priv->mib_stats[port * priv->chip->num_mibs];
 590         for (i = 0; i < priv->chip->num_mibs; i++) {
 591                 const struct ar8xxx_mib_desc *mib;
 592                 u64 t;
 593
 594                 mib = &priv->chip->mib_decs[i];
 595                 t = priv->read(priv, base + mib->offset);
 596                 if (mib->size == 2) {
 597                         u64 hi;
 598
 599                         hi = priv->read(priv, base + mib->offset + 4);
 600                         t |= hi << 32;
 601                 }
 602
 603                 if (flush)
 604                         mib_stats[i] = 0;
 605                 else
 606                         mib_stats[i] += t;
 607         }
 608 }
 609
 610 static void
 611 ar8216_read_port_link(struct ar8xxx_priv *priv, int port,
 612                       struct switch_port_link *link)
 613 {
 614         u32 status;
 615         u32 speed;
 616
 617         memset(link, '\0', sizeof(*link));
 618
 619         status = priv->chip->read_port_status(priv, port);
 620
 621         link->aneg = !!(status & AR8216_PORT_STATUS_LINK_AUTO);
 622         if (link->aneg) {
 623                 link->link = !!(status & AR8216_PORT_STATUS_LINK_UP);
 624         } else {
 625                 link->link = true;
 626
 627                 if (priv->get_port_link) {
 628                         int err;
 629
 630                         err = priv->get_port_link(port);
 631                         if (err >= 0)
 632                                 link->link = !!err;
 633                 }
 634         }
 635
 636         if (!link->link)
 637                 return;
 638
 639         link->duplex = !!(status & AR8216_PORT_STATUS_DUPLEX);
 640         link->tx_flow = !!(status & AR8216_PORT_STATUS_TXFLOW);
 641         link->rx_flow = !!(status & AR8216_PORT_STATUS_RXFLOW);
 642
 643         speed = (status & AR8216_PORT_STATUS_SPEED) >>
 644                  AR8216_PORT_STATUS_SPEED_S;
 645
 646         switch (speed) {
 647         case AR8216_PORT_SPEED_10M:
 648                 link->speed = SWITCH_PORT_SPEED_10;
 649                 break;
 650         case AR8216_PORT_SPEED_100M:
 651                 link->speed = SWITCH_PORT_SPEED_100;
 652                 break;
 653         case AR8216_PORT_SPEED_1000M:
 654                 link->speed = SWITCH_PORT_SPEED_1000;
 655                 break;
 656         default:
 657                 link->speed = SWITCH_PORT_SPEED_UNKNOWN;
 658                 break;
 659         }
 660 }
 661
 662 static struct sk_buff *
 663 ar8216_mangle_tx(struct net_device *dev, struct sk_buff *skb)
 664 {
 665         struct ar8xxx_priv *priv = dev->phy_ptr;
 666         unsigned char *buf;
 667
 668         if (unlikely(!priv))
 669                 goto error;
 670
 671         if (!priv->vlan)
 672                 goto send;
 673
 674         if (unlikely(skb_headroom(skb) < 2)) {
 675                 if (pskb_expand_head(skb, 2, 0, GFP_ATOMIC) < 0)
 676                         goto error;
 677         }
 678
 679         buf = skb_push(skb, 2);
 680         buf[0] = 0x10;
 681         buf[1] = 0x80;
 682
 683 send:
 684         return skb;
 685
 686 error:
 687         dev_kfree_skb_any(skb);
 688         return NULL;
 689 }
 690
 691 static void
 692 ar8216_mangle_rx(struct net_device *dev, struct sk_buff *skb)
 693 {
 694         struct ar8xxx_priv *priv;
 695         unsigned char *buf;
 696         int port, vlan;
 697
 698         priv = dev->phy_ptr;
 699         if (!priv)
 700                 return;
 701
 702         /* don't strip the header if vlan mode is disabled */
 703         if (!priv->vlan)
 704                 return;
 705
 706         /* strip header, get vlan id */
 707         buf = skb->data;
 708         skb_pull(skb, 2);
 709
 710         /* check for vlan header presence */
 711         if ((buf[12 + 2] != 0x81) || (buf[13 + 2] != 0x00))
 712                 return;
 713
 714         port = buf[0] & 0xf;
 715
 716         /* no need to fix up packets coming from a tagged source */
 717         if (priv->vlan_tagged & (1 << port))
 718                 return;
 719
 720         /* lookup port vid from local table, the switch passes an invalid vlan id */
 721         vlan = priv->vlan_id[priv->pvid[port]];
 722
 723         buf[14 + 2] &= 0xf0;
 724         buf[14 + 2] |= vlan >> 8;
 725         buf[15 + 2] = vlan & 0xff;
 726 }
 727
 728 static int
 729 ar8216_wait_bit(struct ar8xxx_priv *priv, int reg, u32 mask, u32 val)
 730 {
 731         int timeout = 20;
 732         u32 t = 0;
 733
 734         while (1) {
 735                 t = priv->read(priv, reg);
 736                 if ((t & mask) == val)
 737                         return 0;
 738
 739                 if (timeout-- <= 0)
 740                         break;
 741
 742                 udelay(10);
 743         }
 744
 745         pr_err("ar8216: timeout on reg %08x: %08x & %08x != %08x\n",
 746                (unsigned int) reg, t, mask, val);
 747         return -ETIMEDOUT;
 748 }
 749
 750 static void
 751 ar8216_vtu_op(struct ar8xxx_priv *priv, u32 op, u32 val)
 752 {
 753         if (ar8216_wait_bit(priv, AR8216_REG_VTU, AR8216_VTU_ACTIVE, 0))
 754                 return;
 755         if ((op & AR8216_VTU_OP) == AR8216_VTU_OP_LOAD) {
 756                 val &= AR8216_VTUDATA_MEMBER;
 757                 val |= AR8216_VTUDATA_VALID;
 758                 priv->write(priv, AR8216_REG_VTU_DATA, val);
 759         }
 760         op |= AR8216_VTU_ACTIVE;
 761         priv->write(priv, AR8216_REG_VTU, op);
 762 }
 763
 764 static void
 765 ar8216_vtu_flush(struct ar8xxx_priv *priv)
 766 {
 767         ar8216_vtu_op(priv, AR8216_VTU_OP_FLUSH, 0);
 768 }
 769
 770 static void
 771 ar8216_vtu_load_vlan(struct ar8xxx_priv *priv, u32 vid, u32 port_mask)
 772 {
 773         u32 op;
 774
 775         op = AR8216_VTU_OP_LOAD | (vid << AR8216_VTU_VID_S);
 776         ar8216_vtu_op(priv, op, port_mask);
 777 }
 778
 779 static int
 780 ar8216_atu_flush(struct ar8xxx_priv *priv)
 781 {
 782         int ret;
 783
 784         ret = ar8216_wait_bit(priv, AR8216_REG_ATU, AR8216_ATU_ACTIVE, 0);
 785         if (!ret)
 786                 priv->write(priv, AR8216_REG_ATU, AR8216_ATU_OP_FLUSH);
 787
 788         return ret;
 789 }
 790
 791 static u32
 792 ar8216_read_port_status(struct ar8xxx_priv *priv, int port)
 793 {
 794         return priv->read(priv, AR8216_REG_PORT_STATUS(port));
 795 }
 796
 797 static void
 798 ar8216_setup_port(struct ar8xxx_priv *priv, int port, u32 members)
 799 {
 800         u32 header;
 801         u32 egress, ingress;
 802         u32 pvid;
 803
 804         if (priv->vlan) {
 805                 pvid = priv->vlan_id[priv->pvid[port]];
 806                 if (priv->vlan_tagged & (1 << port))
 807                         egress = AR8216_OUT_ADD_VLAN;
 808                 else
 809                         egress = AR8216_OUT_STRIP_VLAN;
 810                 ingress = AR8216_IN_SECURE;
 811         } else {
 812                 pvid = port;
 813                 egress = AR8216_OUT_KEEP;
 814                 ingress = AR8216_IN_PORT_ONLY;
 815         }
 816
 817         if (chip_is_ar8216(priv) && priv->vlan && port == AR8216_PORT_CPU)
 818                 header = AR8216_PORT_CTRL_HEADER;
 819         else
 820                 header = 0;
 821
 822         ar8xxx_rmw(priv, AR8216_REG_PORT_CTRL(port),
 823                    AR8216_PORT_CTRL_LEARN | AR8216_PORT_CTRL_VLAN_MODE |
 824                    AR8216_PORT_CTRL_SINGLE_VLAN | AR8216_PORT_CTRL_STATE |
 825                    AR8216_PORT_CTRL_HEADER | AR8216_PORT_CTRL_LEARN_LOCK,
 826                    AR8216_PORT_CTRL_LEARN | header |
 827                    (egress << AR8216_PORT_CTRL_VLAN_MODE_S) |
 828                    (AR8216_PORT_STATE_FORWARD << AR8216_PORT_CTRL_STATE_S));
 829
 830         ar8xxx_rmw(priv, AR8216_REG_PORT_VLAN(port),
 831                    AR8216_PORT_VLAN_DEST_PORTS | AR8216_PORT_VLAN_MODE |
 832                    AR8216_PORT_VLAN_DEFAULT_ID,
 833                    (members << AR8216_PORT_VLAN_DEST_PORTS_S) |
 834                    (ingress << AR8216_PORT_VLAN_MODE_S) |
 835                    (pvid << AR8216_PORT_VLAN_DEFAULT_ID_S));
 836 }
 837
 838 static int
 839 ar8216_hw_init(struct ar8xxx_priv *priv)
 840 {
 841         if (priv->initialized)
 842                 return 0;
 843
 844         ar8xxx_phy_init(priv);
 845
 846         priv->initialized = true;
 847         return 0;
 848 }
 849
 850 static void
 851 ar8216_init_globals(struct ar8xxx_priv *priv)
 852 {
 853         /* standard atheros magic */
 854         priv->write(priv, 0x38, 0xc000050e);
 855
 856         ar8xxx_rmw(priv, AR8216_REG_GLOBAL_CTRL,
 857                    AR8216_GCTRL_MTU, 1518 + 8 + 2);
 858 }
 859
 860 static void
 861 ar8216_init_port(struct ar8xxx_priv *priv, int port)
 862 {
 863         /* Enable port learning and tx */
 864         priv->write(priv, AR8216_REG_PORT_CTRL(port),
 865                 AR8216_PORT_CTRL_LEARN |
 866                 (4 << AR8216_PORT_CTRL_STATE_S));
 867
 868         priv->write(priv, AR8216_REG_PORT_VLAN(port), 0);
 869
 870         if (port == AR8216_PORT_CPU) {
 871                 priv->write(priv, AR8216_REG_PORT_STATUS(port),
 872                         AR8216_PORT_STATUS_LINK_UP |
 873                         (ar8xxx_has_gige(priv) ?
 874                                 AR8216_PORT_SPEED_1000M : AR8216_PORT_SPEED_100M) |
 875                         AR8216_PORT_STATUS_TXMAC |
 876                         AR8216_PORT_STATUS_RXMAC |
 877                         (chip_is_ar8316(priv) ? AR8216_PORT_STATUS_RXFLOW : 0) |
 878                         (chip_is_ar8316(priv) ? AR8216_PORT_STATUS_TXFLOW : 0) |
 879                         AR8216_PORT_STATUS_DUPLEX);
 880         } else {
 881                 priv->write(priv, AR8216_REG_PORT_STATUS(port),
 882                         AR8216_PORT_STATUS_LINK_AUTO);
 883         }
 884 }
 885
 886 static void
 887 ar8236_setup_port(struct ar8xxx_priv *priv, int port, u32 members)
 888 {
 889         u32 egress, ingress;
 890         u32 pvid;
 891
 892         if (priv->vlan) {
 893                 pvid = priv->vlan_id[priv->pvid[port]];
 894                 if (priv->vlan_tagged & (1 << port))
 895                         egress = AR8216_OUT_ADD_VLAN;
 896                 else
 897                         egress = AR8216_OUT_STRIP_VLAN;
 898                 ingress = AR8216_IN_SECURE;
 899         } else {
 900                 pvid = port;
 901                 egress = AR8216_OUT_KEEP;
 902                 ingress = AR8216_IN_PORT_ONLY;
 903         }
 904
 905         ar8xxx_rmw(priv, AR8216_REG_PORT_CTRL(port),
 906                    AR8216_PORT_CTRL_LEARN | AR8216_PORT_CTRL_VLAN_MODE |
 907                    AR8216_PORT_CTRL_SINGLE_VLAN | AR8216_PORT_CTRL_STATE |
 908                    AR8216_PORT_CTRL_HEADER | AR8216_PORT_CTRL_LEARN_LOCK,
 909                    AR8216_PORT_CTRL_LEARN |
 910                    (egress << AR8216_PORT_CTRL_VLAN_MODE_S) |
 911                    (AR8216_PORT_STATE_FORWARD << AR8216_PORT_CTRL_STATE_S));
 912
 913         ar8xxx_rmw(priv, AR8236_REG_PORT_VLAN(port),
 914                    AR8236_PORT_VLAN_DEFAULT_ID,
 915                    (pvid << AR8236_PORT_VLAN_DEFAULT_ID_S));
 916
 917         ar8xxx_rmw(priv, AR8236_REG_PORT_VLAN2(port),
 918                    AR8236_PORT_VLAN2_VLAN_MODE |
 919                    AR8236_PORT_VLAN2_MEMBER,
 920                    (ingress << AR8236_PORT_VLAN2_VLAN_MODE_S) |
 921                    (members << AR8236_PORT_VLAN2_MEMBER_S));
 922 }
 923
 924 static void
 925 ar8236_init_globals(struct ar8xxx_priv *priv)
 926 {
 927         /* enable jumbo frames */
 928         ar8xxx_rmw(priv, AR8216_REG_GLOBAL_CTRL,
 929                    AR8316_GCTRL_MTU, 9018 + 8 + 2);
 930
 931         /* enable cpu port to receive arp frames */
 932         ar8xxx_rmw(priv, AR8216_REG_ATU_CTRL,
 933                    AR8236_ATU_CTRL_RES, AR8236_ATU_CTRL_RES);
 934
 935         /* enable cpu port to receive multicast and broadcast frames */
 936         ar8xxx_rmw(priv, AR8216_REG_FLOOD_MASK,
 937                    AR8236_FM_CPU_BROADCAST_EN | AR8236_FM_CPU_BCAST_FWD_EN,
 938                    AR8236_FM_CPU_BROADCAST_EN | AR8236_FM_CPU_BCAST_FWD_EN);
 939
 940         /* Enable MIB counters */
 941         ar8xxx_rmw(priv, AR8216_REG_MIB_FUNC, AR8216_MIB_FUNC | AR8236_MIB_EN,
 942                    (AR8216_MIB_FUNC_NO_OP << AR8216_MIB_FUNC_S) |
 943                    AR8236_MIB_EN);
 944 }
 945
 946 static int
 947 ar8316_hw_init(struct ar8xxx_priv *priv)
 948 {
 949         u32 val, newval;
 950
 951         val = priv->read(priv, AR8316_REG_POSTRIP);
 952
 953         if (priv->phy->interface == PHY_INTERFACE_MODE_RGMII) {
 954                 if (priv->port4_phy) {
 955                         /* value taken from Ubiquiti RouterStation Pro */
 956                         newval = 0x81461bea;
 957                         pr_info("ar8316: Using port 4 as PHY\n");
 958                 } else {
 959                         newval = 0x01261be2;
 960                         pr_info("ar8316: Using port 4 as switch port\n");
 961                 }
 962         } else if (priv->phy->interface == PHY_INTERFACE_MODE_GMII) {
 963                 /* value taken from AVM Fritz!Box 7390 sources */
 964                 newval = 0x010e5b71;
 965         } else {
 966                 /* no known value for phy interface */
 967                 pr_err("ar8316: unsupported mii mode: %d.\n",
 968                        priv->phy->interface);
 969                 return -EINVAL;
 970         }
 971
 972         if (val == newval)
 973                 goto out;
 974
 975         priv->write(priv, AR8316_REG_POSTRIP, newval);
 976
 977         if (priv->port4_phy &&
 978             priv->phy->interface == PHY_INTERFACE_MODE_RGMII) {
 979                 /* work around for phy4 rgmii mode */
 980                 ar8xxx_phy_dbg_write(priv, 4, 0x12, 0x480c);
 981                 /* rx delay */
 982                 ar8xxx_phy_dbg_write(priv, 4, 0x0, 0x824e);
 983                 /* tx delay */
 984                 ar8xxx_phy_dbg_write(priv, 4, 0x5, 0x3d47);
 985                 msleep(1000);
 986         }
 987
 988         ar8xxx_phy_init(priv);
 989
 990 out:
 991         priv->initialized = true;
 992         return 0;
 993 }
 994
 995 static void
 996 ar8316_init_globals(struct ar8xxx_priv *priv)
 997 {
 998         /* standard atheros magic */
 999         priv->write(priv, 0x38, 0xc000050e);
1000
1001         /* enable cpu port to receive multicast and broadcast frames */
1002         priv->write(priv, AR8216_REG_FLOOD_MASK, 0x003f003f);
1003
1004         /* enable jumbo frames */
1005         ar8xxx_rmw(priv, AR8216_REG_GLOBAL_CTRL,
1006                    AR8316_GCTRL_MTU, 9018 + 8 + 2);
1007
1008         /* Enable MIB counters */
1009         ar8xxx_rmw(priv, AR8216_REG_MIB_FUNC, AR8216_MIB_FUNC | AR8236_MIB_EN,
1010                    (AR8216_MIB_FUNC_NO_OP << AR8216_MIB_FUNC_S) |
1011                    AR8236_MIB_EN);
1012 }
1013
1014 static u32
1015 ar8327_get_pad_cfg(struct ar8327_pad_cfg *cfg)
1016 {
1017         u32 t;
1018
1019         if (!cfg)
1020                 return 0;
1021
1022         t = 0;
1023         switch (cfg->mode) {
1024         case AR8327_PAD_NC:
1025                 break;
1026
1027         case AR8327_PAD_MAC2MAC_MII:
1028                 t = AR8327_PAD_MAC_MII_EN;
1029                 if (cfg->rxclk_sel)
1030                         t |= AR8327_PAD_MAC_MII_RXCLK_SEL;
1031                 if (cfg->txclk_sel)
1032                         t |= AR8327_PAD_MAC_MII_TXCLK_SEL;
1033                 break;
1034
1035         case AR8327_PAD_MAC2MAC_GMII:
1036                 t = AR8327_PAD_MAC_GMII_EN;
1037                 if (cfg->rxclk_sel)
1038                         t |= AR8327_PAD_MAC_GMII_RXCLK_SEL;
1039                 if (cfg->txclk_sel)
1040                         t |= AR8327_PAD_MAC_GMII_TXCLK_SEL;
1041                 break;
1042
1043         case AR8327_PAD_MAC_SGMII:
1044                 t = AR8327_PAD_SGMII_EN;
1045
1046                 /*
1047                  * WAR for the QUalcomm Atheros AP136 board.
1048                  * It seems that RGMII TX/RX delay settings needs to be
1049                  * applied for SGMII mode as well, The ethernet is not
1050                  * reliable without this.
1051                  */
1052                 t |= cfg->txclk_delay_sel << AR8327_PAD_RGMII_TXCLK_DELAY_SEL_S;
1053                 t |= cfg->rxclk_delay_sel << AR8327_PAD_RGMII_RXCLK_DELAY_SEL_S;
1054                 if (cfg->rxclk_delay_en)
1055                         t |= AR8327_PAD_RGMII_RXCLK_DELAY_EN;
1056                 if (cfg->txclk_delay_en)
1057                         t |= AR8327_PAD_RGMII_TXCLK_DELAY_EN;
1058
1059                 if (cfg->sgmii_delay_en)
1060                         t |= AR8327_PAD_SGMII_DELAY_EN;
1061
1062                 break;
1063
1064         case AR8327_PAD_MAC2PHY_MII:
1065                 t = AR8327_PAD_PHY_MII_EN;
1066                 if (cfg->rxclk_sel)
1067                         t |= AR8327_PAD_PHY_MII_RXCLK_SEL;
1068                 if (cfg->txclk_sel)
1069                         t |= AR8327_PAD_PHY_MII_TXCLK_SEL;
1070                 break;
1071
1072         case AR8327_PAD_MAC2PHY_GMII:
1073                 t = AR8327_PAD_PHY_GMII_EN;
1074                 if (cfg->pipe_rxclk_sel)
1075                         t |= AR8327_PAD_PHY_GMII_PIPE_RXCLK_SEL;
1076                 if (cfg->rxclk_sel)
1077                         t |= AR8327_PAD_PHY_GMII_RXCLK_SEL;
1078                 if (cfg->txclk_sel)
1079                         t |= AR8327_PAD_PHY_GMII_TXCLK_SEL;
1080                 break;
1081
1082         case AR8327_PAD_MAC_RGMII:
1083                 t = AR8327_PAD_RGMII_EN;
1084                 t |= cfg->txclk_delay_sel << AR8327_PAD_RGMII_TXCLK_DELAY_SEL_S;
1085                 t |= cfg->rxclk_delay_sel << AR8327_PAD_RGMII_RXCLK_DELAY_SEL_S;
1086                 if (cfg->rxclk_delay_en)
1087                         t |= AR8327_PAD_RGMII_RXCLK_DELAY_EN;
1088                 if (cfg->txclk_delay_en)
1089                         t |= AR8327_PAD_RGMII_TXCLK_DELAY_EN;
1090                 break;
1091
1092         case AR8327_PAD_PHY_GMII:
1093                 t = AR8327_PAD_PHYX_GMII_EN;
1094                 break;
1095
1096         case AR8327_PAD_PHY_RGMII:
1097                 t = AR8327_PAD_PHYX_RGMII_EN;
1098                 break;
1099
1100         case AR8327_PAD_PHY_MII:
1101                 t = AR8327_PAD_PHYX_MII_EN;
1102                 break;
1103         }
1104
1105         return t;
1106 }
1107
1108 static void
1109 ar8327_phy_fixup(struct ar8xxx_priv *priv, int phy)
1110 {
1111         switch (priv->chip_rev) {
1112         case 1:
1113                 /* For 100M waveform */
1114                 ar8xxx_phy_dbg_write(priv, phy, 0, 0x02ea);
1115                 /* Turn on Gigabit clock */
1116                 ar8xxx_phy_dbg_write(priv, phy, 0x3d, 0x68a0);
1117                 break;
1118
1119         case 2:
1120                 ar8xxx_phy_mmd_write(priv, phy, 0x7, 0x3c);
1121                 ar8xxx_phy_mmd_write(priv, phy, 0x4007, 0x0);
1122                 /* fallthrough */
1123         case 4:
1124                 ar8xxx_phy_mmd_write(priv, phy, 0x3, 0x800d);
1125                 ar8xxx_phy_mmd_write(priv, phy, 0x4003, 0x803f);
1126
1127                 ar8xxx_phy_dbg_write(priv, phy, 0x3d, 0x6860);
1128                 ar8xxx_phy_dbg_write(priv, phy, 0x5, 0x2c46);
1129                 ar8xxx_phy_dbg_write(priv, phy, 0x3c, 0x6000);
1130                 break;
1131         }
1132 }
1133
1134 static u32
1135 ar8327_get_port_init_status(struct ar8327_port_cfg *cfg)
1136 {
1137         u32 t;
1138
1139         if (!cfg->force_link)
1140                 return AR8216_PORT_STATUS_LINK_AUTO;
1141
1142         t = AR8216_PORT_STATUS_TXMAC | AR8216_PORT_STATUS_RXMAC;
1143         t |= cfg->duplex ? AR8216_PORT_STATUS_DUPLEX : 0;
1144         t |= cfg->rxpause ? AR8216_PORT_STATUS_RXFLOW : 0;
1145         t |= cfg->txpause ? AR8216_PORT_STATUS_TXFLOW : 0;
1146
1147         switch (cfg->speed) {
1148         case AR8327_PORT_SPEED_10:
1149                 t |= AR8216_PORT_SPEED_10M;
1150                 break;
1151         case AR8327_PORT_SPEED_100:
1152                 t |= AR8216_PORT_SPEED_100M;
1153                 break;
1154         case AR8327_PORT_SPEED_1000:
1155                 t |= AR8216_PORT_SPEED_1000M;
1156                 break;
1157         }
1158
1159         return t;
1160 }
1161
1162 #define AR8327_LED_ENTRY(_num, _reg, _shift) \
1163         [_num] = { .reg = (_reg), .shift = (_shift) }
1164
1165 static const struct ar8327_led_entry
1166 ar8327_led_map[AR8327_NUM_LEDS] = {
1167         AR8327_LED_ENTRY(AR8327_LED_PHY0_0, 0, 14),
1168         AR8327_LED_ENTRY(AR8327_LED_PHY0_1, 1, 14),
1169         AR8327_LED_ENTRY(AR8327_LED_PHY0_2, 2, 14),
1170
1171         AR8327_LED_ENTRY(AR8327_LED_PHY1_0, 3, 8),
1172         AR8327_LED_ENTRY(AR8327_LED_PHY1_1, 3, 10),
1173         AR8327_LED_ENTRY(AR8327_LED_PHY1_2, 3, 12),
1174
1175         AR8327_LED_ENTRY(AR8327_LED_PHY2_0, 3, 14),
1176         AR8327_LED_ENTRY(AR8327_LED_PHY2_1, 3, 16),
1177         AR8327_LED_ENTRY(AR8327_LED_PHY2_2, 3, 18),
1178
1179         AR8327_LED_ENTRY(AR8327_LED_PHY3_0, 3, 20),
1180         AR8327_LED_ENTRY(AR8327_LED_PHY3_1, 3, 22),
1181         AR8327_LED_ENTRY(AR8327_LED_PHY3_2, 3, 24),
1182
1183         AR8327_LED_ENTRY(AR8327_LED_PHY4_0, 0, 30),
1184         AR8327_LED_ENTRY(AR8327_LED_PHY4_1, 1, 30),
1185         AR8327_LED_ENTRY(AR8327_LED_PHY4_2, 2, 30),
1186 };
1187
1188 static void
1189 ar8327_set_led_pattern(struct ar8xxx_priv *priv, unsigned int led_num,
1190                        enum ar8327_led_pattern pattern)
1191 {
1192         const struct ar8327_led_entry *entry;
1193
1194         entry = &ar8327_led_map[led_num];
1195         ar8xxx_rmw(priv, AR8327_REG_LED_CTRL(entry->reg),
1196                    (3 << entry->shift), pattern << entry->shift);
1197 }
1198
1199 static void
1200 ar8327_led_work_func(struct work_struct *work)
1201 {
1202         struct ar8327_led *aled;
1203         u8 pattern;
1204
1205         aled = container_of(work, struct ar8327_led, led_work);
1206
1207         spin_lock(&aled->lock);
1208         pattern = aled->pattern;
1209         spin_unlock(&aled->lock);
1210
1211         ar8327_set_led_pattern(aled->sw_priv, aled->led_num,
1212                                pattern);
1213 }
1214
1215 static void
1216 ar8327_led_schedule_change(struct ar8327_led *aled, u8 pattern)
1217 {
1218         if (aled->pattern == pattern)
1219                 return;
1220
1221         aled->pattern = pattern;
1222         schedule_work(&aled->led_work);
1223 }
1224
1225 static inline struct ar8327_led *
1226 led_cdev_to_ar8327_led(struct led_classdev *led_cdev)
1227 {
1228         return container_of(led_cdev, struct ar8327_led, cdev);
1229 }
1230
1231 static int
1232 ar8327_led_blink_set(struct led_classdev *led_cdev,
1233                      unsigned long *delay_on,
1234                      unsigned long *delay_off)
1235 {
1236         struct ar8327_led *aled = led_cdev_to_ar8327_led(led_cdev);
1237
1238         if (*delay_on == 0 && *delay_off == 0) {
1239                 *delay_on = 125;
1240                 *delay_off = 125;
1241         }
1242
1243         if (*delay_on != 125 || *delay_off != 125) {
1244                 /*
1245                  * The hardware only supports blinking at 4Hz. Fall back
1246                  * to software implementation in other cases.
1247                  */
1248                 return -EINVAL;
1249         }
1250
1251         spin_lock(&aled->lock);
1252
1253         aled->enable_hw_mode = false;
1254         ar8327_led_schedule_change(aled, AR8327_LED_PATTERN_BLINK);
1255
1256         spin_unlock(&aled->lock);
1257
1258         return 0;
1259 }
1260
1261 static void
1262 ar8327_led_set_brightness(struct led_classdev *led_cdev,
1263                           enum led_brightness brightness)
1264 {
1265         struct ar8327_led *aled = led_cdev_to_ar8327_led(led_cdev);
1266         u8 pattern;
1267         bool active;
1268
1269         active = (brightness != LED_OFF);
1270         active ^= aled->active_low;
1271
1272         pattern = (active) ? AR8327_LED_PATTERN_ON :
1273                              AR8327_LED_PATTERN_OFF;
1274
1275         spin_lock(&aled->lock);
1276
1277         aled->enable_hw_mode = false;
1278         ar8327_led_schedule_change(aled, pattern);
1279
1280         spin_unlock(&aled->lock);
1281 }
1282
1283 static ssize_t
1284 ar8327_led_enable_hw_mode_show(struct device *dev,
1285                                struct device_attribute *attr,
1286                                char *buf)
1287 {
1288         struct led_classdev *led_cdev = dev_get_drvdata(dev);
1289         struct ar8327_led *aled = led_cdev_to_ar8327_led(led_cdev);
1290         ssize_t ret = 0;
1291
1292         spin_lock(&aled->lock);
1293         ret += sprintf(buf, "%d\n", aled->enable_hw_mode);
1294         spin_unlock(&aled->lock);
1295
1296         return ret;
1297 }
1298
1299 static ssize_t
1300 ar8327_led_enable_hw_mode_store(struct device *dev,
1301                                 struct device_attribute *attr,
1302                                 const char *buf,
1303                                 size_t size)
1304 {
1305         struct led_classdev *led_cdev = dev_get_drvdata(dev);
1306         struct ar8327_led *aled = led_cdev_to_ar8327_led(led_cdev);
1307         u8 pattern;
1308         u8 value;
1309         int ret;
1310
1311         ret = kstrtou8(buf, 10, &value);
1312         if (ret < 0)
1313                 return -EINVAL;
1314
1315         spin_lock(&aled->lock);
1316
1317         aled->enable_hw_mode = !!value;
1318         if (aled->enable_hw_mode)
1319                 pattern = AR8327_LED_PATTERN_RULE;
1320         else
1321                 pattern = AR8327_LED_PATTERN_OFF;
1322
1323         ar8327_led_schedule_change(aled, pattern);
1324
1325         spin_unlock(&aled->lock);
1326
1327         return size;
1328 }
1329
1330 static DEVICE_ATTR(enable_hw_mode,  S_IRUGO | S_IWUSR,
1331                    ar8327_led_enable_hw_mode_show,
1332                    ar8327_led_enable_hw_mode_store);
1333
1334 static int
1335 ar8327_led_register(struct ar8327_led *aled)
1336 {
1337         int ret;
1338
1339         ret = led_classdev_register(NULL, &aled->cdev);
1340         if (ret < 0)
1341                 return ret;
1342
1343         if (aled->mode == AR8327_LED_MODE_HW) {
1344                 ret = device_create_file(aled->cdev.dev,
1345                                          &dev_attr_enable_hw_mode);
1346                 if (ret)
1347                         goto err_unregister;
1348         }
1349
1350         return 0;
1351
1352 err_unregister:
1353         led_classdev_unregister(&aled->cdev);
1354         return ret;
1355 }
1356
1357 static void
1358 ar8327_led_unregister(struct ar8327_led *aled)
1359 {
1360         if (aled->mode == AR8327_LED_MODE_HW)
1361                 device_remove_file(aled->cdev.dev, &dev_attr_enable_hw_mode);
1362
1363         led_classdev_unregister(&aled->cdev);
1364         cancel_work_sync(&aled->led_work);
1365 }
1366
1367 static int
1368 ar8327_led_create(struct ar8xxx_priv *priv,
1369                   const struct ar8327_led_info *led_info)
1370 {
1371         struct ar8327_data *data = priv->chip_data;
1372         struct ar8327_led *aled;
1373         int ret;
1374
1375         if (!IS_ENABLED(CONFIG_AR8216_PHY_LEDS))
1376                 return 0;
1377
1378         if (!led_info->name)
1379                 return -EINVAL;
1380
1381         if (led_info->led_num >= AR8327_NUM_LEDS)
1382                 return -EINVAL;
1383
1384         aled = kzalloc(sizeof(*aled) + strlen(led_info->name) + 1,
1385                        GFP_KERNEL);
1386         if (!aled)
1387                 return -ENOMEM;
1388
1389         aled->sw_priv = priv;
1390         aled->led_num = led_info->led_num;
1391         aled->active_low = led_info->active_low;
1392         aled->mode = led_info->mode;
1393
1394         if (aled->mode == AR8327_LED_MODE_HW)
1395                 aled->enable_hw_mode = true;
1396
1397         aled->name = (char *)(aled + 1);
1398         strcpy(aled->name, led_info->name);
1399
1400         aled->cdev.name = aled->name;
1401         aled->cdev.brightness_set = ar8327_led_set_brightness;
1402         aled->cdev.blink_set = ar8327_led_blink_set;
1403         aled->cdev.default_trigger = led_info->default_trigger;
1404
1405         spin_lock_init(&aled->lock);
1406         mutex_init(&aled->mutex);
1407         INIT_WORK(&aled->led_work, ar8327_led_work_func);
1408
1409         ret = ar8327_led_register(aled);
1410         if (ret)
1411                 goto err_free;
1412
1413         data->leds[data->num_leds++] = aled;
1414
1415         return 0;
1416
1417 err_free:
1418         kfree(aled);
1419         return ret;
1420 }
1421
1422 static void
1423 ar8327_led_destroy(struct ar8327_led *aled)
1424 {
1425         ar8327_led_unregister(aled);
1426         kfree(aled);
1427 }
1428
1429 static void
1430 ar8327_leds_init(struct ar8xxx_priv *priv)
1431 {
1432         struct ar8327_data *data = priv->chip_data;
1433         unsigned i;
1434
1435         if (!IS_ENABLED(CONFIG_AR8216_PHY_LEDS))
1436                 return;
1437
1438         for (i = 0; i < data->num_leds; i++) {
1439                 struct ar8327_led *aled;
1440
1441                 aled = data->leds[i];
1442
1443                 if (aled->enable_hw_mode)
1444                         aled->pattern = AR8327_LED_PATTERN_RULE;
1445                 else
1446                         aled->pattern = AR8327_LED_PATTERN_OFF;
1447
1448                 ar8327_set_led_pattern(priv, aled->led_num, aled->pattern);
1449         }
1450 }
1451
1452 static void
1453 ar8327_leds_cleanup(struct ar8xxx_priv *priv)
1454 {
1455         struct ar8327_data *data = priv->chip_data;
1456         unsigned i;
1457
1458         if (!IS_ENABLED(CONFIG_AR8216_PHY_LEDS))
1459                 return;
1460
1461         for (i = 0; i < data->num_leds; i++) {
1462                 struct ar8327_led *aled;
1463
1464                 aled = data->leds[i];
1465                 ar8327_led_destroy(aled);
1466         }
1467
1468         kfree(data->leds);
1469 }
1470
1471 static int
1472 ar8327_hw_config_pdata(struct ar8xxx_priv *priv,
1473                        struct ar8327_platform_data *pdata)
1474 {
1475         struct ar8327_led_cfg *led_cfg;
1476         struct ar8327_data *data = priv->chip_data;
1477         u32 pos, new_pos;
1478         u32 t;
1479
1480         if (!pdata)
1481                 return -EINVAL;
1482
1483         priv->get_port_link = pdata->get_port_link;
1484
1485         data->port0_status = ar8327_get_port_init_status(&pdata->port0_cfg);
1486         data->port6_status = ar8327_get_port_init_status(&pdata->port6_cfg);
1487
1488         t = ar8327_get_pad_cfg(pdata->pad0_cfg);
1489         if (chip_is_ar8337(priv))
1490                 t |= AR8337_PAD_MAC06_EXCHANGE_EN;
1491
1492         priv->write(priv, AR8327_REG_PAD0_MODE, t);
1493         t = ar8327_get_pad_cfg(pdata->pad5_cfg);
1494         priv->write(priv, AR8327_REG_PAD5_MODE, t);
1495         t = ar8327_get_pad_cfg(pdata->pad6_cfg);
1496         priv->write(priv, AR8327_REG_PAD6_MODE, t);
1497
1498         pos = priv->read(priv, AR8327_REG_POWER_ON_STRIP);
1499         new_pos = pos;
1500
1501         led_cfg = pdata->led_cfg;
1502         if (led_cfg) {
1503                 if (led_cfg->open_drain)
1504                         new_pos |= AR8327_POWER_ON_STRIP_LED_OPEN_EN;
1505                 else
1506                         new_pos &= ~AR8327_POWER_ON_STRIP_LED_OPEN_EN;
1507
1508                 priv->write(priv, AR8327_REG_LED_CTRL0, led_cfg->led_ctrl0);
1509                 priv->write(priv, AR8327_REG_LED_CTRL1, led_cfg->led_ctrl1);
1510                 priv->write(priv, AR8327_REG_LED_CTRL2, led_cfg->led_ctrl2);
1511                 priv->write(priv, AR8327_REG_LED_CTRL3, led_cfg->led_ctrl3);
1512
1513                 if (new_pos != pos)
1514                         new_pos |= AR8327_POWER_ON_STRIP_POWER_ON_SEL;
1515         }
1516
1517         if (pdata->sgmii_cfg) {
1518                 t = pdata->sgmii_cfg->sgmii_ctrl;
1519                 if (priv->chip_rev == 1)
1520                         t |= AR8327_SGMII_CTRL_EN_PLL |
1521                              AR8327_SGMII_CTRL_EN_RX |
1522                              AR8327_SGMII_CTRL_EN_TX;
1523                 else
1524                         t &= ~(AR8327_SGMII_CTRL_EN_PLL |
1525                                AR8327_SGMII_CTRL_EN_RX |
1526                                AR8327_SGMII_CTRL_EN_TX);
1527
1528                 priv->write(priv, AR8327_REG_SGMII_CTRL, t);
1529
1530                 if (pdata->sgmii_cfg->serdes_aen)
1531                         new_pos &= ~AR8327_POWER_ON_STRIP_SERDES_AEN;
1532                 else
1533                         new_pos |= AR8327_POWER_ON_STRIP_SERDES_AEN;
1534         }
1535
1536         priv->write(priv, AR8327_REG_POWER_ON_STRIP, new_pos);
1537
1538         if (pdata->leds && pdata->num_leds) {
1539                 int i;
1540
1541                 data->leds = kzalloc(pdata->num_leds * sizeof(void *),
1542                                      GFP_KERNEL);
1543                 if (!data->leds)
1544                         return -ENOMEM;
1545
1546                 for (i = 0; i < pdata->num_leds; i++)
1547                         ar8327_led_create(priv, &pdata->leds[i]);
1548         }
1549
1550         return 0;
1551 }
1552
1553 #ifdef CONFIG_OF
1554 static int
1555 ar8327_hw_config_of(struct ar8xxx_priv *priv, struct device_node *np)
1556 {
1557         struct ar8327_data *data = priv->chip_data;
1558         const __be32 *paddr;
1559         int len;
1560         int i;
1561
1562         paddr = of_get_property(np, "qca,ar8327-initvals", &len);
1563         if (!paddr || len < (2 * sizeof(*paddr)))
1564                 return -EINVAL;
1565
1566         len /= sizeof(*paddr);
1567
1568         for (i = 0; i < len - 1; i += 2) {
1569                 u32 reg;
1570                 u32 val;
1571
1572                 reg = be32_to_cpup(paddr + i);
1573                 val = be32_to_cpup(paddr + i + 1);
1574
1575                 switch (reg) {
1576                 case AR8327_REG_PORT_STATUS(0):
1577                         data->port0_status = val;
1578                         break;
1579                 case AR8327_REG_PORT_STATUS(6):
1580                         data->port6_status = val;
1581                         break;
1582                 default:
1583                         priv->write(priv, reg, val);
1584                         break;
1585                 }
1586         }
1587
1588         return 0;
1589 }
1590 #else
1591 static inline int
1592 ar8327_hw_config_of(struct ar8xxx_priv *priv, struct device_node *np)
1593 {
1594         return -EINVAL;
1595 }
1596 #endif
1597
1598 static int
1599 ar8327_hw_init(struct ar8xxx_priv *priv)
1600 {
1601         int ret;
1602
1603         priv->chip_data = kzalloc(sizeof(struct ar8327_data), GFP_KERNEL);
1604         if (!priv->chip_data)
1605                 return -ENOMEM;
1606
1607         if (priv->phy->dev.of_node)
1608                 ret = ar8327_hw_config_of(priv, priv->phy->dev.of_node);
1609         else
1610                 ret = ar8327_hw_config_pdata(priv,
1611                                              priv->phy->dev.platform_data);
1612
1613         if (ret)
1614                 return ret;
1615
1616         ar8327_leds_init(priv);
1617
1618         ar8xxx_phy_init(priv);
1619
1620         return 0;
1621 }
1622
1623 static void
1624 ar8327_cleanup(struct ar8xxx_priv *priv)
1625 {
1626         ar8327_leds_cleanup(priv);
1627 }
1628
1629 static void
1630 ar8327_init_globals(struct ar8xxx_priv *priv)
1631 {
1632         u32 t;
1633
1634         /* enable CPU port and disable mirror port */
1635         t = AR8327_FWD_CTRL0_CPU_PORT_EN |
1636             AR8327_FWD_CTRL0_MIRROR_PORT;
1637         priv->write(priv, AR8327_REG_FWD_CTRL0, t);
1638
1639         /* forward multicast and broadcast frames to CPU */
1640         t = (AR8327_PORTS_ALL << AR8327_FWD_CTRL1_UC_FLOOD_S) |
1641             (AR8327_PORTS_ALL << AR8327_FWD_CTRL1_MC_FLOOD_S) |
1642             (AR8327_PORTS_ALL << AR8327_FWD_CTRL1_BC_FLOOD_S);
1643         priv->write(priv, AR8327_REG_FWD_CTRL1, t);
1644
1645         /* enable jumbo frames */
1646         ar8xxx_rmw(priv, AR8327_REG_MAX_FRAME_SIZE,
1647                    AR8327_MAX_FRAME_SIZE_MTU, 9018 + 8 + 2);
1648
1649         /* Enable MIB counters */
1650         ar8xxx_reg_set(priv, AR8327_REG_MODULE_EN,
1651                        AR8327_MODULE_EN_MIB);
1652
1653         /* Disable EEE on all ports due to stability issues */
1654         t = priv->read(priv, AR8327_REG_EEE_CTRL);
1655         t |= AR8327_EEE_CTRL_DISABLE_PHY(0) |
1656              AR8327_EEE_CTRL_DISABLE_PHY(1) |
1657              AR8327_EEE_CTRL_DISABLE_PHY(2) |
1658              AR8327_EEE_CTRL_DISABLE_PHY(3) |
1659              AR8327_EEE_CTRL_DISABLE_PHY(4);
1660         priv->write(priv, AR8327_REG_EEE_CTRL, t);
1661 }
1662
1663 static void
1664 ar8327_init_port(struct ar8xxx_priv *priv, int port)
1665 {
1666         struct ar8327_data *data = priv->chip_data;
1667         u32 t;
1668
1669         if (port == AR8216_PORT_CPU)
1670                 t = data->port0_status;
1671         else if (port == 6)
1672                 t = data->port6_status;
1673         else
1674                 t = AR8216_PORT_STATUS_LINK_AUTO;
1675
1676         priv->write(priv, AR8327_REG_PORT_STATUS(port), t);
1677         priv->write(priv, AR8327_REG_PORT_HEADER(port), 0);
1678
1679         t = 1 << AR8327_PORT_VLAN0_DEF_SVID_S;
1680         t |= 1 << AR8327_PORT_VLAN0_DEF_CVID_S;
1681         priv->write(priv, AR8327_REG_PORT_VLAN0(port), t);
1682
1683         t = AR8327_PORT_VLAN1_OUT_MODE_UNTOUCH << AR8327_PORT_VLAN1_OUT_MODE_S;
1684         priv->write(priv, AR8327_REG_PORT_VLAN1(port), t);
1685
1686         t = AR8327_PORT_LOOKUP_LEARN;
1687         t |= AR8216_PORT_STATE_FORWARD << AR8327_PORT_LOOKUP_STATE_S;
1688         priv->write(priv, AR8327_REG_PORT_LOOKUP(port), t);
1689 }
1690
1691 static u32
1692 ar8327_read_port_status(struct ar8xxx_priv *priv, int port)
1693 {
1694         return priv->read(priv, AR8327_REG_PORT_STATUS(port));
1695 }
1696
1697 static int
1698 ar8327_atu_flush(struct ar8xxx_priv *priv)
1699 {
1700         int ret;
1701
1702         ret = ar8216_wait_bit(priv, AR8327_REG_ATU_FUNC,
1703                               AR8327_ATU_FUNC_BUSY, 0);
1704         if (!ret)
1705                 priv->write(priv, AR8327_REG_ATU_FUNC,
1706                             AR8327_ATU_FUNC_OP_FLUSH);
1707
1708         return ret;
1709 }
1710
1711 static void
1712 ar8327_vtu_op(struct ar8xxx_priv *priv, u32 op, u32 val)
1713 {
1714         if (ar8216_wait_bit(priv, AR8327_REG_VTU_FUNC1,
1715                             AR8327_VTU_FUNC1_BUSY, 0))
1716                 return;
1717
1718         if ((op & AR8327_VTU_FUNC1_OP) == AR8327_VTU_FUNC1_OP_LOAD)
1719                 priv->write(priv, AR8327_REG_VTU_FUNC0, val);
1720
1721         op |= AR8327_VTU_FUNC1_BUSY;
1722         priv->write(priv, AR8327_REG_VTU_FUNC1, op);
1723 }
1724
1725 static void
1726 ar8327_vtu_flush(struct ar8xxx_priv *priv)
1727 {
1728         ar8327_vtu_op(priv, AR8327_VTU_FUNC1_OP_FLUSH, 0);
1729 }
1730
1731 static void
1732 ar8327_vtu_load_vlan(struct ar8xxx_priv *priv, u32 vid, u32 port_mask)
1733 {
1734         u32 op;
1735         u32 val;
1736         int i;
1737
1738         op = AR8327_VTU_FUNC1_OP_LOAD | (vid << AR8327_VTU_FUNC1_VID_S);
1739         val = AR8327_VTU_FUNC0_VALID | AR8327_VTU_FUNC0_IVL;
1740         for (i = 0; i < AR8327_NUM_PORTS; i++) {
1741                 u32 mode;
1742
1743                 if ((port_mask & BIT(i)) == 0)
1744                         mode = AR8327_VTU_FUNC0_EG_MODE_NOT;
1745                 else if (priv->vlan == 0)
1746                         mode = AR8327_VTU_FUNC0_EG_MODE_KEEP;
1747                 else if ((priv->vlan_tagged & BIT(i)) || (priv->vlan_id[priv->pvid[i]] != vid))
1748                         mode = AR8327_VTU_FUNC0_EG_MODE_TAG;
1749                 else
1750                         mode = AR8327_VTU_FUNC0_EG_MODE_UNTAG;
1751
1752                 val |= mode << AR8327_VTU_FUNC0_EG_MODE_S(i);
1753         }
1754         ar8327_vtu_op(priv, op, val);
1755 }
1756
1757 static void
1758 ar8327_setup_port(struct ar8xxx_priv *priv, int port, u32 members)
1759 {
1760         u32 t;
1761         u32 egress, ingress;
1762         u32 pvid = priv->vlan_id[priv->pvid[port]];
1763
1764         if (priv->vlan) {
1765                 egress = AR8327_PORT_VLAN1_OUT_MODE_UNMOD;
1766                 ingress = AR8216_IN_SECURE;
1767         } else {
1768                 egress = AR8327_PORT_VLAN1_OUT_MODE_UNTOUCH;
1769                 ingress = AR8216_IN_PORT_ONLY;
1770         }
1771
1772         t = pvid << AR8327_PORT_VLAN0_DEF_SVID_S;
1773         t |= pvid << AR8327_PORT_VLAN0_DEF_CVID_S;
1774         priv->write(priv, AR8327_REG_PORT_VLAN0(port), t);
1775
1776         t = AR8327_PORT_VLAN1_PORT_VLAN_PROP;
1777         t |= egress << AR8327_PORT_VLAN1_OUT_MODE_S;
1778         priv->write(priv, AR8327_REG_PORT_VLAN1(port), t);
1779
1780         t = members;
1781         t |= AR8327_PORT_LOOKUP_LEARN;
1782         t |= ingress << AR8327_PORT_LOOKUP_IN_MODE_S;
1783         t |= AR8216_PORT_STATE_FORWARD << AR8327_PORT_LOOKUP_STATE_S;
1784         priv->write(priv, AR8327_REG_PORT_LOOKUP(port), t);
1785 }
1786
1787 static int
1788 ar8xxx_sw_set_vlan(struct switch_dev *dev, const struct switch_attr *attr,
1789                    struct switch_val *val)
1790 {
1791         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1792         priv->vlan = !!val->value.i;
1793         return 0;
1794 }
1795
1796 static int
1797 ar8xxx_sw_get_vlan(struct switch_dev *dev, const struct switch_attr *attr,
1798                    struct switch_val *val)
1799 {
1800         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1801         val->value.i = priv->vlan;
1802         return 0;
1803 }
1804
1805
1806 static int
1807 ar8xxx_sw_set_pvid(struct switch_dev *dev, int port, int vlan)
1808 {
1809         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1810
1811         /* make sure no invalid PVIDs get set */
1812
1813         if (vlan >= dev->vlans)
1814                 return -EINVAL;
1815
1816         priv->pvid[port] = vlan;
1817         return 0;
1818 }
1819
1820 static int
1821 ar8xxx_sw_get_pvid(struct switch_dev *dev, int port, int *vlan)
1822 {
1823         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1824         *vlan = priv->pvid[port];
1825         return 0;
1826 }
1827
1828 static int
1829 ar8xxx_sw_set_vid(struct switch_dev *dev, const struct switch_attr *attr,
1830                   struct switch_val *val)
1831 {
1832         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1833         priv->vlan_id[val->port_vlan] = val->value.i;
1834         return 0;
1835 }
1836
1837 static int
1838 ar8xxx_sw_get_vid(struct switch_dev *dev, const struct switch_attr *attr,
1839                   struct switch_val *val)
1840 {
1841         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1842         val->value.i = priv->vlan_id[val->port_vlan];
1843         return 0;
1844 }
1845
1846 static int
1847 ar8xxx_sw_get_port_link(struct switch_dev *dev, int port,
1848                         struct switch_port_link *link)
1849 {
1850         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1851
1852         ar8216_read_port_link(priv, port, link);
1853         return 0;
1854 }
1855
1856 static int
1857 ar8xxx_sw_get_ports(struct switch_dev *dev, struct switch_val *val)
1858 {
1859         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1860         u8 ports = priv->vlan_table[val->port_vlan];
1861         int i;
1862
1863         val->len = 0;
1864         for (i = 0; i < dev->ports; i++) {
1865                 struct switch_port *p;
1866
1867                 if (!(ports & (1 << i)))
1868                         continue;
1869
1870                 p = &val->value.ports[val->len++];
1871                 p->id = i;
1872                 if (priv->vlan_tagged & (1 << i))
1873                         p->flags = (1 << SWITCH_PORT_FLAG_TAGGED);
1874                 else
1875                         p->flags = 0;
1876         }
1877         return 0;
1878 }
1879
1880 static int
1881 ar8327_sw_get_ports(struct switch_dev *dev, struct switch_val *val)
1882 {
1883         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1884         u8 ports = priv->vlan_table[val->port_vlan];
1885         int i;
1886
1887         val->len = 0;
1888         for (i = 0; i < dev->ports; i++) {
1889                 struct switch_port *p;
1890
1891                 if (!(ports & (1 << i)))
1892                         continue;
1893
1894                 p = &val->value.ports[val->len++];
1895                 p->id = i;
1896                 if ((priv->vlan_tagged & (1 << i)) || (priv->pvid[i] != val->port_vlan))
1897                         p->flags = (1 << SWITCH_PORT_FLAG_TAGGED);
1898                 else
1899                         p->flags = 0;
1900         }
1901         return 0;
1902 }
1903
1904 static int
1905 ar8xxx_sw_set_ports(struct switch_dev *dev, struct switch_val *val)
1906 {
1907         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1908         u8 *vt = &priv->vlan_table[val->port_vlan];
1909         int i, j;
1910
1911         *vt = 0;
1912         for (i = 0; i < val->len; i++) {
1913                 struct switch_port *p = &val->value.ports[i];
1914
1915                 if (p->flags & (1 << SWITCH_PORT_FLAG_TAGGED)) {
1916                         priv->vlan_tagged |= (1 << p->id);
1917                 } else {
1918                         priv->vlan_tagged &= ~(1 << p->id);
1919                         priv->pvid[p->id] = val->port_vlan;
1920
1921                         /* make sure that an untagged port does not
1922                          * appear in other vlans */
1923                         for (j = 0; j < AR8X16_MAX_VLANS; j++) {
1924                                 if (j == val->port_vlan)
1925                                         continue;
1926                                 priv->vlan_table[j] &= ~(1 << p->id);
1927                         }
1928                 }
1929
1930                 *vt |= 1 << p->id;
1931         }
1932         return 0;
1933 }
1934
1935 static int
1936 ar8327_sw_set_ports(struct switch_dev *dev, struct switch_val *val)
1937 {
1938         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1939         u8 *vt = &priv->vlan_table[val->port_vlan];
1940         int i;
1941
1942         *vt = 0;
1943         for (i = 0; i < val->len; i++) {
1944                 struct switch_port *p = &val->value.ports[i];
1945
1946                 if (p->flags & (1 << SWITCH_PORT_FLAG_TAGGED)) {
1947                         if (val->port_vlan == priv->pvid[p->id]) {
1948                                 priv->vlan_tagged |= (1 << p->id);
1949                         }
1950                 } else {
1951                         priv->vlan_tagged &= ~(1 << p->id);
1952                         priv->pvid[p->id] = val->port_vlan;
1953                 }
1954
1955                 *vt |= 1 << p->id;
1956         }
1957         return 0;
1958 }
1959
1960 static void
1961 ar8327_set_mirror_regs(struct ar8xxx_priv *priv)
1962 {
1963         int port;
1964
1965         /* reset all mirror registers */
1966         ar8xxx_rmw(priv, AR8327_REG_FWD_CTRL0,
1967                    AR8327_FWD_CTRL0_MIRROR_PORT,
1968                    (0xF << AR8327_FWD_CTRL0_MIRROR_PORT_S));
1969         for (port = 0; port < AR8327_NUM_PORTS; port++) {
1970                 ar8xxx_rmw(priv, AR8327_REG_PORT_LOOKUP(port),
1971                            AR8327_PORT_LOOKUP_ING_MIRROR_EN,
1972                            0);
1973
1974                 ar8xxx_rmw(priv, AR8327_REG_PORT_HOL_CTRL1(port),
1975                            AR8327_PORT_HOL_CTRL1_EG_MIRROR_EN,
1976                            0);
1977         }
1978
1979         /* now enable mirroring if necessary */
1980         if (priv->source_port >= AR8327_NUM_PORTS ||
1981             priv->monitor_port >= AR8327_NUM_PORTS ||
1982             priv->source_port == priv->monitor_port) {
1983                 return;
1984         }
1985
1986         ar8xxx_rmw(priv, AR8327_REG_FWD_CTRL0,
1987                    AR8327_FWD_CTRL0_MIRROR_PORT,
1988                    (priv->monitor_port << AR8327_FWD_CTRL0_MIRROR_PORT_S));
1989
1990         if (priv->mirror_rx)
1991                 ar8xxx_rmw(priv, AR8327_REG_PORT_LOOKUP(priv->source_port),
1992                            AR8327_PORT_LOOKUP_ING_MIRROR_EN,
1993                            AR8327_PORT_LOOKUP_ING_MIRROR_EN);
1994
1995         if (priv->mirror_tx)
1996                 ar8xxx_rmw(priv, AR8327_REG_PORT_HOL_CTRL1(priv->source_port),
1997                            AR8327_PORT_HOL_CTRL1_EG_MIRROR_EN,
1998                            AR8327_PORT_HOL_CTRL1_EG_MIRROR_EN);
1999 }
2000
2001 static void
2002 ar8216_set_mirror_regs(struct ar8xxx_priv *priv)
2003 {
2004         int port;
2005
2006         /* reset all mirror registers */
2007         ar8xxx_rmw(priv, AR8216_REG_GLOBAL_CPUPORT,
2008                    AR8216_GLOBAL_CPUPORT_MIRROR_PORT,
2009                    (0xF << AR8216_GLOBAL_CPUPORT_MIRROR_PORT_S));
2010         for (port = 0; port < AR8216_NUM_PORTS; port++) {
2011                 ar8xxx_rmw(priv, AR8216_REG_PORT_CTRL(port),
2012                            AR8216_PORT_CTRL_MIRROR_RX,
2013                            0);
2014
2015                 ar8xxx_rmw(priv, AR8216_REG_PORT_CTRL(port),
2016                            AR8216_PORT_CTRL_MIRROR_TX,
2017                            0);
2018         }
2019
2020         /* now enable mirroring if necessary */
2021         if (priv->source_port >= AR8216_NUM_PORTS ||
2022             priv->monitor_port >= AR8216_NUM_PORTS ||
2023             priv->source_port == priv->monitor_port) {
2024                 return;
2025         }
2026
2027         ar8xxx_rmw(priv, AR8216_REG_GLOBAL_CPUPORT,
2028                    AR8216_GLOBAL_CPUPORT_MIRROR_PORT,
2029                    (priv->monitor_port << AR8216_GLOBAL_CPUPORT_MIRROR_PORT_S));
2030
2031         if (priv->mirror_rx)
2032                 ar8xxx_rmw(priv, AR8216_REG_PORT_CTRL(priv->source_port),
2033                            AR8216_PORT_CTRL_MIRROR_RX,
2034                            AR8216_PORT_CTRL_MIRROR_RX);
2035
2036         if (priv->mirror_tx)
2037                 ar8xxx_rmw(priv, AR8216_REG_PORT_CTRL(priv->source_port),
2038                            AR8216_PORT_CTRL_MIRROR_TX,
2039                            AR8216_PORT_CTRL_MIRROR_TX);
2040 }
2041
2042 static int
2043 ar8xxx_sw_hw_apply(struct switch_dev *dev)
2044 {
2045         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
2046         u8 portmask[AR8X16_MAX_PORTS];
2047         int i, j;
2048
2049         mutex_lock(&priv->reg_mutex);
2050         /* flush all vlan translation unit entries */
2051         priv->chip->vtu_flush(priv);
2052
2053         memset(portmask, 0, sizeof(portmask));
2054         if (!priv->init) {
2055                 /* calculate the port destination masks and load vlans
2056                  * into the vlan translation unit */
2057                 for (j = 0; j < AR8X16_MAX_VLANS; j++) {
2058                         u8 vp = priv->vlan_table[j];
2059
2060                         if (!vp)
2061                                 continue;
2062
2063                         for (i = 0; i < dev->ports; i++) {
2064                                 u8 mask = (1 << i);
2065                                 if (vp & mask)
2066                                         portmask[i] |= vp & ~mask;
2067                         }
2068
2069                         priv->chip->vtu_load_vlan(priv, priv->vlan_id[j],
2070                                                  priv->vlan_table[j]);
2071                 }
2072         } else {
2073                 /* vlan disabled:
2074                  * isolate all ports, but connect them to the cpu port */
2075                 for (i = 0; i < dev->ports; i++) {
2076                         if (i == AR8216_PORT_CPU)
2077                                 continue;
2078
2079                         portmask[i] = 1 << AR8216_PORT_CPU;
2080                         portmask[AR8216_PORT_CPU] |= (1 << i);
2081                 }
2082         }
2083
2084         /* update the port destination mask registers and tag settings */
2085         for (i = 0; i < dev->ports; i++) {
2086                 priv->chip->setup_port(priv, i, portmask[i]);
2087         }
2088
2089         priv->chip->set_mirror_regs(priv);
2090
2091         mutex_unlock(&priv->reg_mutex);
2092         return 0;
2093 }
2094
2095 static int
2096 ar8xxx_sw_reset_switch(struct switch_dev *dev)
2097 {
2098         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
2099         int i;
2100
2101         mutex_lock(&priv->reg_mutex);
2102         memset(&priv->vlan, 0, sizeof(struct ar8xxx_priv) -
2103                 offsetof(struct ar8xxx_priv, vlan));
2104
2105         for (i = 0; i < AR8X16_MAX_VLANS; i++)
2106                 priv->vlan_id[i] = i;
2107
2108         /* Configure all ports */
2109         for (i = 0; i < dev->ports; i++)
2110                 priv->chip->init_port(priv, i);
2111
2112         priv->mirror_rx = false;
2113         priv->mirror_tx = false;
2114         priv->source_port = 0;
2115         priv->monitor_port = 0;
2116
2117         priv->chip->init_globals(priv);
2118
2119         mutex_unlock(&priv->reg_mutex);
2120
2121         return ar8xxx_sw_hw_apply(dev);
2122 }
2123
2124 static int
2125 ar8xxx_sw_set_reset_mibs(struct switch_dev *dev,
2126                          const struct switch_attr *attr,
2127                          struct switch_val *val)
2128 {
2129         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
2130         unsigned int len;
2131         int ret;
2132
2133         if (!ar8xxx_has_mib_counters(priv))
2134                 return -EOPNOTSUPP;
2135
2136         mutex_lock(&priv->mib_lock);
2137
2138         len = priv->dev.ports * priv->chip->num_mibs *
2139               sizeof(*priv->mib_stats);
2140         memset(priv->mib_stats, '\0', len);
2141         ret = ar8xxx_mib_flush(priv);
2142         if (ret)
2143                 goto unlock;
2144
2145         ret = 0;
2146
2147 unlock:
2148         mutex_unlock(&priv->mib_lock);
2149         return ret;
2150 }
2151
2152 static int
2153 ar8xxx_sw_set_mirror_rx_enable(struct switch_dev *dev,
2154                                const struct switch_attr *attr,
2155                                struct switch_val *val)
2156 {
2157         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
2158
2159         mutex_lock(&priv->reg_mutex);
2160         priv->mirror_rx = !!val->value.i;
2161         priv->chip->set_mirror_regs(priv);
2162         mutex_unlock(&priv->reg_mutex);
2163
2164         return 0;
2165 }
2166
2167 static int
2168 ar8xxx_sw_get_mirror_rx_enable(struct switch_dev *dev,
2169                                const struct switch_attr *attr,
2170                                struct switch_val *val)
2171 {
2172         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
2173         val->value.i = priv->mirror_rx;
2174         return 0;
2175 }
2176
2177 static int
2178 ar8xxx_sw_set_mirror_tx_enable(struct switch_dev *dev,
2179                                const struct switch_attr *attr,
2180                                struct switch_val *val)
2181 {
2182         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
2183
2184         mutex_lock(&priv->reg_mutex);
2185         priv->mirror_tx = !!val->value.i;
2186         priv->chip->set_mirror_regs(priv);
2187         mutex_unlock(&priv->reg_mutex);
2188
2189         return 0;
2190 }
2191
2192 static int
2193 ar8xxx_sw_get_mirror_tx_enable(struct switch_dev *dev,
2194                                const struct switch_attr *attr,
2195                                struct switch_val *val)
2196 {
2197         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
2198         val->value.i = priv->mirror_tx;
2199         return 0;
2200 }
2201
2202 static int
2203 ar8xxx_sw_set_mirror_monitor_port(struct switch_dev *dev,
2204                                   const struct switch_attr *attr,
2205                                   struct switch_val *val)
2206 {
2207         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
2208
2209         mutex_lock(&priv->reg_mutex);
2210         priv->monitor_port = val->value.i;
2211         priv->chip->set_mirror_regs(priv);
2212         mutex_unlock(&priv->reg_mutex);
2213
2214         return 0;
2215 }
2216
2217 static int
2218 ar8xxx_sw_get_mirror_monitor_port(struct switch_dev *dev,
2219                                   const struct switch_attr *attr,
2220                                   struct switch_val *val)
2221 {
2222         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
2223         val->value.i = priv->monitor_port;
2224         return 0;
2225 }
2226
2227 static int
2228 ar8xxx_sw_set_mirror_source_port(struct switch_dev *dev,
2229                                  const struct switch_attr *attr,
2230                                  struct switch_val *val)
2231 {
2232         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
2233
2234         mutex_lock(&priv->reg_mutex);
2235         priv->source_port = val->value.i;
2236         priv->chip->set_mirror_regs(priv);
2237         mutex_unlock(&priv->reg_mutex);
2238
2239         return 0;
2240 }
2241
2242 static int
2243 ar8xxx_sw_get_mirror_source_port(struct switch_dev *dev,
2244                                  const struct switch_attr *attr,
2245                                  struct switch_val *val)
2246 {
2247         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
2248         val->value.i = priv->source_port;
2249         return 0;
2250 }
2251
2252 static int
2253 ar8xxx_sw_set_port_reset_mib(struct switch_dev *dev,
2254                              const struct switch_attr *attr,
2255                              struct switch_val *val)
2256 {
2257         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
2258         int port;
2259         int ret;
2260
2261         if (!ar8xxx_has_mib_counters(priv))
2262                 return -EOPNOTSUPP;
2263
2264         port = val->port_vlan;
2265         if (port >= dev->ports)
2266                 return -EINVAL;
2267
2268         mutex_lock(&priv->mib_lock);
2269         ret = ar8xxx_mib_capture(priv);
2270         if (ret)
2271                 goto unlock;
2272
2273         ar8xxx_mib_fetch_port_stat(priv, port, true);
2274
2275         ret = 0;
2276
2277 unlock:
2278         mutex_unlock(&priv->mib_lock);
2279         return ret;
2280 }
2281
2282 static int
2283 ar8xxx_sw_get_port_mib(struct switch_dev *dev,
2284                        const struct switch_attr *attr,
2285                        struct switch_val *val)
2286 {
2287         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
2288         const struct ar8xxx_chip *chip = priv->chip;
2289         u64 *mib_stats;
2290         int port;
2291         int ret;
2292         char *buf = priv->buf;
2293         int i, len = 0;
2294
2295         if (!ar8xxx_has_mib_counters(priv))
2296                 return -EOPNOTSUPP;
2297
2298         port = val->port_vlan;
2299         if (port >= dev->ports)
2300                 return -EINVAL;
2301
2302         mutex_lock(&priv->mib_lock);
2303         ret = ar8xxx_mib_capture(priv);
2304         if (ret)
2305                 goto unlock;
2306
2307         ar8xxx_mib_fetch_port_stat(priv, port, false);
2308
2309         len += snprintf(buf + len, sizeof(priv->buf) - len,
2310                         "Port %d MIB counters\n",
2311                         port);
2312
2313         mib_stats = &priv->mib_stats[port * chip->num_mibs];
2314         for (i = 0; i < chip->num_mibs; i++)
2315                 len += snprintf(buf + len, sizeof(priv->buf) - len,
2316                                 "%-12s: %llu\n",
2317                                 chip->mib_decs[i].name,
2318                                 mib_stats[i]);
2319
2320         val->value.s = buf;
2321         val->len = len;
2322
2323         ret = 0;
2324
2325 unlock:
2326         mutex_unlock(&priv->mib_lock);
2327         return ret;
2328 }
2329
2330 static struct switch_attr ar8xxx_sw_attr_globals[] = {
2331         {
2332                 .type = SWITCH_TYPE_INT,
2333                 .name = "enable_vlan",
2334                 .description = "Enable VLAN mode",
2335                 .set = ar8xxx_sw_set_vlan,
2336                 .get = ar8xxx_sw_get_vlan,
2337                 .max = 1
2338         },
2339         {
2340                 .type = SWITCH_TYPE_NOVAL,
2341                 .name = "reset_mibs",
2342                 .description = "Reset all MIB counters",
2343                 .set = ar8xxx_sw_set_reset_mibs,
2344         },
2345         {
2346                 .type = SWITCH_TYPE_INT,
2347                 .name = "enable_mirror_rx",
2348                 .description = "Enable mirroring of RX packets",
2349                 .set = ar8xxx_sw_set_mirror_rx_enable,
2350                 .get = ar8xxx_sw_get_mirror_rx_enable,
2351                 .max = 1
2352         },
2353         {
2354                 .type = SWITCH_TYPE_INT,
2355                 .name = "enable_mirror_tx",
2356                 .description = "Enable mirroring of TX packets",
2357                 .set = ar8xxx_sw_set_mirror_tx_enable,
2358                 .get = ar8xxx_sw_get_mirror_tx_enable,
2359                 .max = 1
2360         },
2361         {
2362                 .type = SWITCH_TYPE_INT,
2363                 .name = "mirror_monitor_port",
2364                 .description = "Mirror monitor port",
2365                 .set = ar8xxx_sw_set_mirror_monitor_port,
2366                 .get = ar8xxx_sw_get_mirror_monitor_port,
2367                 .max = AR8216_NUM_PORTS - 1
2368         },
2369         {
2370                 .type = SWITCH_TYPE_INT,
2371                 .name = "mirror_source_port",
2372                 .description = "Mirror source port",
2373                 .set = ar8xxx_sw_set_mirror_source_port,
2374                 .get = ar8xxx_sw_get_mirror_source_port,
2375                 .max = AR8216_NUM_PORTS - 1
2376         },
2377 };
2378
2379 static struct switch_attr ar8327_sw_attr_globals[] = {
2380         {
2381                 .type = SWITCH_TYPE_INT,
2382                 .name = "enable_vlan",
2383                 .description = "Enable VLAN mode",
2384                 .set = ar8xxx_sw_set_vlan,
2385                 .get = ar8xxx_sw_get_vlan,
2386                 .max = 1
2387         },
2388         {
2389                 .type = SWITCH_TYPE_NOVAL,
2390                 .name = "reset_mibs",
2391                 .description = "Reset all MIB counters",
2392                 .set = ar8xxx_sw_set_reset_mibs,
2393         },
2394         {
2395                 .type = SWITCH_TYPE_INT,
2396                 .name = "enable_mirror_rx",
2397                 .description = "Enable mirroring of RX packets",
2398                 .set = ar8xxx_sw_set_mirror_rx_enable,
2399                 .get = ar8xxx_sw_get_mirror_rx_enable,
2400                 .max = 1
2401         },
2402         {
2403                 .type = SWITCH_TYPE_INT,
2404                 .name = "enable_mirror_tx",
2405                 .description = "Enable mirroring of TX packets",
2406                 .set = ar8xxx_sw_set_mirror_tx_enable,
2407                 .get = ar8xxx_sw_get_mirror_tx_enable,
2408                 .max = 1
2409         },
2410         {
2411                 .type = SWITCH_TYPE_INT,
2412                 .name = "mirror_monitor_port",
2413                 .description = "Mirror monitor port",
2414                 .set = ar8xxx_sw_set_mirror_monitor_port,
2415                 .get = ar8xxx_sw_get_mirror_monitor_port,
2416                 .max = AR8327_NUM_PORTS - 1
2417         },
2418         {
2419                 .type = SWITCH_TYPE_INT,
2420                 .name = "mirror_source_port",
2421                 .description = "Mirror source port",
2422                 .set = ar8xxx_sw_set_mirror_source_port,
2423                 .get = ar8xxx_sw_get_mirror_source_port,
2424                 .max = AR8327_NUM_PORTS - 1
2425         },
2426 };
2427
2428 static struct switch_attr ar8xxx_sw_attr_port[] = {
2429         {
2430                 .type = SWITCH_TYPE_NOVAL,
2431                 .name = "reset_mib",
2432                 .description = "Reset single port MIB counters",
2433                 .set = ar8xxx_sw_set_port_reset_mib,
2434         },
2435         {
2436                 .type = SWITCH_TYPE_STRING,
2437                 .name = "mib",
2438                 .description = "Get port's MIB counters",
2439                 .set = NULL,
2440                 .get = ar8xxx_sw_get_port_mib,
2441         },
2442 };
2443
2444 static struct switch_attr ar8xxx_sw_attr_vlan[] = {
2445         {
2446                 .type = SWITCH_TYPE_INT,
2447                 .name = "vid",
2448                 .description = "VLAN ID (0-4094)",
2449                 .set = ar8xxx_sw_set_vid,
2450                 .get = ar8xxx_sw_get_vid,
2451                 .max = 4094,
2452         },
2453 };
2454
2455 static const struct switch_dev_ops ar8xxx_sw_ops = {
2456         .attr_global = {
2457                 .attr = ar8xxx_sw_attr_globals,
2458                 .n_attr = ARRAY_SIZE(ar8xxx_sw_attr_globals),
2459         },
2460         .attr_port = {
2461                 .attr = ar8xxx_sw_attr_port,
2462                 .n_attr = ARRAY_SIZE(ar8xxx_sw_attr_port),
2463         },
2464         .attr_vlan = {
2465                 .attr = ar8xxx_sw_attr_vlan,
2466                 .n_attr = ARRAY_SIZE(ar8xxx_sw_attr_vlan),
2467         },
2468         .get_port_pvid = ar8xxx_sw_get_pvid,
2469         .set_port_pvid = ar8xxx_sw_set_pvid,
2470         .get_vlan_ports = ar8xxx_sw_get_ports,
2471         .set_vlan_ports = ar8xxx_sw_set_ports,
2472         .apply_config = ar8xxx_sw_hw_apply,
2473         .reset_switch = ar8xxx_sw_reset_switch,
2474         .get_port_link = ar8xxx_sw_get_port_link,
2475 };
2476
2477 static const struct switch_dev_ops ar8327_sw_ops = {
2478         .attr_global = {
2479                 .attr = ar8327_sw_attr_globals,
2480                 .n_attr = ARRAY_SIZE(ar8327_sw_attr_globals),
2481         },
2482         .attr_port = {
2483                 .attr = ar8xxx_sw_attr_port,
2484                 .n_attr = ARRAY_SIZE(ar8xxx_sw_attr_port),
2485         },
2486         .attr_vlan = {
2487                 .attr = ar8xxx_sw_attr_vlan,
2488                 .n_attr = ARRAY_SIZE(ar8xxx_sw_attr_vlan),
2489         },
2490         .get_port_pvid = ar8xxx_sw_get_pvid,
2491         .set_port_pvid = ar8xxx_sw_set_pvid,
2492         .get_vlan_ports = ar8327_sw_get_ports,
2493         .set_vlan_ports = ar8327_sw_set_ports,
2494         .apply_config = ar8xxx_sw_hw_apply,
2495         .reset_switch = ar8xxx_sw_reset_switch,
2496         .get_port_link = ar8xxx_sw_get_port_link,
2497 };
2498
2499 static const struct ar8xxx_chip ar8216_chip = {
2500         .caps = AR8XXX_CAP_MIB_COUNTERS,
2501
2502         .reg_port_stats_start = 0x19000,
2503         .reg_port_stats_length = 0xa0,
2504
2505         .name = "Atheros AR8216",
2506         .ports = AR8216_NUM_PORTS,
2507         .vlans = AR8216_NUM_VLANS,
2508         .swops = &ar8xxx_sw_ops,
2509
2510         .hw_init = ar8216_hw_init,
2511         .init_globals = ar8216_init_globals,
2512         .init_port = ar8216_init_port,
2513         .setup_port = ar8216_setup_port,
2514         .read_port_status = ar8216_read_port_status,
2515         .atu_flush = ar8216_atu_flush,
2516         .vtu_flush = ar8216_vtu_flush,
2517         .vtu_load_vlan = ar8216_vtu_load_vlan,
2518         .set_mirror_regs = ar8216_set_mirror_regs,
2519
2520         .num_mibs = ARRAY_SIZE(ar8216_mibs),
2521         .mib_decs = ar8216_mibs,
2522         .mib_func = AR8216_REG_MIB_FUNC
2523 };
2524
2525 static const struct ar8xxx_chip ar8236_chip = {
2526         .caps = AR8XXX_CAP_MIB_COUNTERS,
2527
2528         .reg_port_stats_start = 0x20000,
2529         .reg_port_stats_length = 0x100,
2530
2531         .name = "Atheros AR8236",
2532         .ports = AR8216_NUM_PORTS,
2533         .vlans = AR8216_NUM_VLANS,
2534         .swops = &ar8xxx_sw_ops,
2535
2536         .hw_init = ar8216_hw_init,
2537         .init_globals = ar8236_init_globals,
2538         .init_port = ar8216_init_port,
2539         .setup_port = ar8236_setup_port,
2540         .read_port_status = ar8216_read_port_status,
2541         .atu_flush = ar8216_atu_flush,
2542         .vtu_flush = ar8216_vtu_flush,
2543         .vtu_load_vlan = ar8216_vtu_load_vlan,
2544         .set_mirror_regs = ar8216_set_mirror_regs,
2545
2546         .num_mibs = ARRAY_SIZE(ar8236_mibs),
2547         .mib_decs = ar8236_mibs,
2548         .mib_func = AR8216_REG_MIB_FUNC
2549 };
2550
2551 static const struct ar8xxx_chip ar8316_chip = {
2552         .caps = AR8XXX_CAP_GIGE | AR8XXX_CAP_MIB_COUNTERS,
2553
2554         .reg_port_stats_start = 0x20000,
2555         .reg_port_stats_length = 0x100,
2556
2557         .name = "Atheros AR8316",
2558         .ports = AR8216_NUM_PORTS,
2559         .vlans = AR8X16_MAX_VLANS,
2560         .swops = &ar8xxx_sw_ops,
2561
2562         .hw_init = ar8316_hw_init,
2563         .init_globals = ar8316_init_globals,
2564         .init_port = ar8216_init_port,
2565         .setup_port = ar8216_setup_port,
2566         .read_port_status = ar8216_read_port_status,
2567         .atu_flush = ar8216_atu_flush,
2568         .vtu_flush = ar8216_vtu_flush,
2569         .vtu_load_vlan = ar8216_vtu_load_vlan,
2570         .set_mirror_regs = ar8216_set_mirror_regs,
2571
2572         .num_mibs = ARRAY_SIZE(ar8236_mibs),
2573         .mib_decs = ar8236_mibs,
2574         .mib_func = AR8216_REG_MIB_FUNC
2575 };
2576
2577 static const struct ar8xxx_chip ar8327_chip = {
2578         .caps = AR8XXX_CAP_GIGE | AR8XXX_CAP_MIB_COUNTERS,
2579         .config_at_probe = true,
2580         .mii_lo_first = true,
2581
2582         .name = "Atheros AR8327",
2583         .ports = AR8327_NUM_PORTS,
2584         .vlans = AR8X16_MAX_VLANS,
2585         .swops = &ar8327_sw_ops,
2586
2587         .reg_port_stats_start = 0x1000,
2588         .reg_port_stats_length = 0x100,
2589
2590         .hw_init = ar8327_hw_init,
2591         .cleanup = ar8327_cleanup,
2592         .init_globals = ar8327_init_globals,
2593         .init_port = ar8327_init_port,
2594         .setup_port = ar8327_setup_port,
2595         .read_port_status = ar8327_read_port_status,
2596         .atu_flush = ar8327_atu_flush,
2597         .vtu_flush = ar8327_vtu_flush,
2598         .vtu_load_vlan = ar8327_vtu_load_vlan,
2599         .phy_fixup = ar8327_phy_fixup,
2600         .set_mirror_regs = ar8327_set_mirror_regs,
2601
2602         .num_mibs = ARRAY_SIZE(ar8236_mibs),
2603         .mib_decs = ar8236_mibs,
2604         .mib_func = AR8327_REG_MIB_FUNC
2605 };
2606
2607 static const struct ar8xxx_chip ar8337_chip = {
2608         .caps = AR8XXX_CAP_GIGE | AR8XXX_CAP_MIB_COUNTERS,
2609         .config_at_probe = true,
2610         .mii_lo_first = true,
2611
2612         .name = "Atheros AR8337",
2613         .ports = AR8327_NUM_PORTS,
2614         .vlans = AR8X16_MAX_VLANS,
2615         .swops = &ar8327_sw_ops,
2616
2617         .reg_port_stats_start = 0x1000,
2618         .reg_port_stats_length = 0x100,
2619
2620         .hw_init = ar8327_hw_init,
2621         .cleanup = ar8327_cleanup,
2622         .init_globals = ar8327_init_globals,
2623         .init_port = ar8327_init_port,
2624         .setup_port = ar8327_setup_port,
2625         .read_port_status = ar8327_read_port_status,
2626         .atu_flush = ar8327_atu_flush,
2627         .vtu_flush = ar8327_vtu_flush,
2628         .vtu_load_vlan = ar8327_vtu_load_vlan,
2629         .phy_fixup = ar8327_phy_fixup,
2630         .set_mirror_regs = ar8327_set_mirror_regs,
2631
2632         .num_mibs = ARRAY_SIZE(ar8236_mibs),
2633         .mib_decs = ar8236_mibs,
2634         .mib_func = AR8327_REG_MIB_FUNC
2635 };
2636
2637 static int
2638 ar8xxx_id_chip(struct ar8xxx_priv *priv)
2639 {
2640         u32 val;
2641         u16 id;
2642         int i;
2643
2644         val = priv->read(priv, AR8216_REG_CTRL);
2645         if (val == ~0)
2646                 return -ENODEV;
2647
2648         id = val & (AR8216_CTRL_REVISION | AR8216_CTRL_VERSION);
2649         for (i = 0; i < AR8X16_PROBE_RETRIES; i++) {
2650                 u16 t;
2651
2652                 val = priv->read(priv, AR8216_REG_CTRL);
2653                 if (val == ~0)
2654                         return -ENODEV;
2655
2656                 t = val & (AR8216_CTRL_REVISION | AR8216_CTRL_VERSION);
2657                 if (t != id)
2658                         return -ENODEV;
2659         }
2660
2661         priv->chip_ver = (id & AR8216_CTRL_VERSION) >> AR8216_CTRL_VERSION_S;
2662         priv->chip_rev = (id & AR8216_CTRL_REVISION);
2663
2664         switch (priv->chip_ver) {
2665         case AR8XXX_VER_AR8216:
2666                 priv->chip = &ar8216_chip;
2667                 break;
2668         case AR8XXX_VER_AR8236:
2669                 priv->chip = &ar8236_chip;
2670                 break;
2671         case AR8XXX_VER_AR8316:
2672                 priv->chip = &ar8316_chip;
2673                 break;
2674         case AR8XXX_VER_AR8327:
2675                 priv->chip = &ar8327_chip;
2676                 break;
2677         case AR8XXX_VER_AR8337:
2678                 priv->chip = &ar8337_chip;
2679                 break;
2680         default:
2681                 pr_err("ar8216: Unknown Atheros device [ver=%d, rev=%d]\n",
2682                        priv->chip_ver, priv->chip_rev);
2683
2684                 return -ENODEV;
2685         }
2686
2687         return 0;
2688 }
2689
2690 static void
2691 ar8xxx_mib_work_func(struct work_struct *work)
2692 {
2693         struct ar8xxx_priv *priv;
2694         int err;
2695
2696         priv = container_of(work, struct ar8xxx_priv, mib_work.work);
2697
2698         mutex_lock(&priv->mib_lock);
2699
2700         err = ar8xxx_mib_capture(priv);
2701         if (err)
2702                 goto next_port;
2703
2704         ar8xxx_mib_fetch_port_stat(priv, priv->mib_next_port, false);
2705
2706 next_port:
2707         priv->mib_next_port++;
2708         if (priv->mib_next_port >= priv->dev.ports)
2709                 priv->mib_next_port = 0;
2710
2711         mutex_unlock(&priv->mib_lock);
2712         schedule_delayed_work(&priv->mib_work,
2713                               msecs_to_jiffies(AR8XXX_MIB_WORK_DELAY));
2714 }
2715
2716 static int
2717 ar8xxx_mib_init(struct ar8xxx_priv *priv)
2718 {
2719         unsigned int len;
2720
2721         if (!ar8xxx_has_mib_counters(priv))
2722                 return 0;
2723
2724         BUG_ON(!priv->chip->mib_decs || !priv->chip->num_mibs);
2725
2726         len = priv->dev.ports * priv->chip->num_mibs *
2727               sizeof(*priv->mib_stats);
2728         priv->mib_stats = kzalloc(len, GFP_KERNEL);
2729
2730         if (!priv->mib_stats)
2731                 return -ENOMEM;
2732
2733         return 0;
2734 }
2735
2736 static void
2737 ar8xxx_mib_start(struct ar8xxx_priv *priv)
2738 {
2739         if (!ar8xxx_has_mib_counters(priv))
2740                 return;
2741
2742         schedule_delayed_work(&priv->mib_work,
2743                               msecs_to_jiffies(AR8XXX_MIB_WORK_DELAY));
2744 }
2745
2746 static void
2747 ar8xxx_mib_stop(struct ar8xxx_priv *priv)
2748 {
2749         if (!ar8xxx_has_mib_counters(priv))
2750                 return;
2751
2752         cancel_delayed_work(&priv->mib_work);
2753 }
2754
2755 static struct ar8xxx_priv *
2756 ar8xxx_create(void)
2757 {
2758         struct ar8xxx_priv *priv;
2759
2760         priv = kzalloc(sizeof(struct ar8xxx_priv), GFP_KERNEL);
2761         if (priv == NULL)
2762                 return NULL;
2763
2764         mutex_init(&priv->reg_mutex);
2765         mutex_init(&priv->mib_lock);
2766         INIT_DELAYED_WORK(&priv->mib_work, ar8xxx_mib_work_func);
2767
2768         return priv;
2769 }
2770
2771 static void
2772 ar8xxx_free(struct ar8xxx_priv *priv)
2773 {
2774         if (priv->chip && priv->chip->cleanup)
2775                 priv->chip->cleanup(priv);
2776
2777         kfree(priv->chip_data);
2778         kfree(priv->mib_stats);
2779         kfree(priv);
2780 }
2781
2782 static struct ar8xxx_priv *
2783 ar8xxx_create_mii(struct mii_bus *bus)
2784 {
2785         struct ar8xxx_priv *priv;
2786
2787         priv = ar8xxx_create();
2788         if (priv) {
2789                 priv->mii_bus = bus;
2790                 priv->read = ar8xxx_mii_read;
2791                 priv->write = ar8xxx_mii_write;
2792                 priv->rmw = ar8xxx_mii_rmw;
2793         }
2794
2795         return priv;
2796 }
2797
2798 static int
2799 ar8xxx_probe_switch(struct ar8xxx_priv *priv)
2800 {
2801         const struct ar8xxx_chip *chip;
2802         struct switch_dev *swdev;
2803         int ret;
2804
2805         ret = ar8xxx_id_chip(priv);
2806         if (ret)
2807                 return ret;
2808
2809         chip = priv->chip;
2810
2811         swdev = &priv->dev;
2812         swdev->cpu_port = AR8216_PORT_CPU;
2813         swdev->name = chip->name;
2814         swdev->vlans = chip->vlans;
2815         swdev->ports = chip->ports;
2816         swdev->ops = chip->swops;
2817
2818         ret = ar8xxx_mib_init(priv);
2819         if (ret)
2820                 return ret;
2821
2822         return 0;
2823 }
2824
2825 static int
2826 ar8xxx_start(struct ar8xxx_priv *priv)
2827 {
2828         int ret;
2829
2830         priv->init = true;
2831
2832         ret = priv->chip->hw_init(priv);
2833         if (ret)
2834                 return ret;
2835
2836         ret = ar8xxx_sw_reset_switch(&priv->dev);
2837         if (ret)
2838                 return ret;
2839
2840         priv->init = false;
2841
2842         ar8xxx_mib_start(priv);
2843
2844         return 0;
2845 }
2846
2847 static int
2848 ar8xxx_phy_config_init(struct phy_device *phydev)
2849 {
2850         struct ar8xxx_priv *priv = phydev->priv;
2851         struct net_device *dev = phydev->attached_dev;
2852         int ret;
2853
2854         if (WARN_ON(!priv))
2855                 return -ENODEV;
2856
2857         if (priv->chip->config_at_probe)
2858                 return ar8xxx_phy_check_aneg(phydev);
2859
2860         priv->phy = phydev;
2861
2862         if (phydev->addr != 0) {
2863                 if (chip_is_ar8316(priv)) {
2864                         /* switch device has been initialized, reinit */
2865                         priv->dev.ports = (AR8216_NUM_PORTS - 1);
2866                         priv->initialized = false;
2867                         priv->port4_phy = true;
2868                         ar8316_hw_init(priv);
2869                         return 0;
2870                 }
2871
2872                 return 0;
2873         }
2874
2875         ret = ar8xxx_start(priv);
2876         if (ret)
2877                 return ret;
2878
2879         /* VID fixup only needed on ar8216 */
2880         if (chip_is_ar8216(priv)) {
2881                 dev->phy_ptr = priv;
2882                 dev->priv_flags |= IFF_NO_IP_ALIGN;
2883                 dev->eth_mangle_rx = ar8216_mangle_rx;
2884                 dev->eth_mangle_tx = ar8216_mangle_tx;
2885         }
2886
2887         return 0;
2888 }
2889
2890 static int
2891 ar8xxx_phy_read_status(struct phy_device *phydev)
2892 {
2893         struct ar8xxx_priv *priv = phydev->priv;
2894         struct switch_port_link link;
2895         int ret;
2896
2897         if (phydev->addr != 0)
2898                 return genphy_read_status(phydev);
2899
2900         ar8216_read_port_link(priv, phydev->addr, &link);
2901         phydev->link = !!link.link;
2902         if (!phydev->link)
2903                 return 0;
2904
2905         switch (link.speed) {
2906         case SWITCH_PORT_SPEED_10:
2907                 phydev->speed = SPEED_10;
2908                 break;
2909         case SWITCH_PORT_SPEED_100:
2910                 phydev->speed = SPEED_100;
2911                 break;
2912         case SWITCH_PORT_SPEED_1000:
2913                 phydev->speed = SPEED_1000;
2914                 break;
2915         default:
2916                 phydev->speed = 0;
2917         }
2918         phydev->duplex = link.duplex ? DUPLEX_FULL : DUPLEX_HALF;
2919
2920         /* flush the address translation unit */
2921         mutex_lock(&priv->reg_mutex);
2922         ret = priv->chip->atu_flush(priv);
2923         mutex_unlock(&priv->reg_mutex);
2924
2925         phydev->state = PHY_RUNNING;
2926         netif_carrier_on(phydev->attached_dev);
2927         phydev->adjust_link(phydev->attached_dev);
2928
2929         return ret;
2930 }
2931
2932 static int
2933 ar8xxx_phy_config_aneg(struct phy_device *phydev)
2934 {
2935         if (phydev->addr == 0)
2936                 return 0;
2937
2938         return genphy_config_aneg(phydev);
2939 }
2940
2941 static const u32 ar8xxx_phy_ids[] = {
2942         0x004dd033,
2943         0x004dd034, /* AR8327 */
2944         0x004dd036, /* AR8337 */
2945         0x004dd041,
2946         0x004dd042,
2947         0x004dd043, /* AR8236 */
2948 };
2949
2950 static bool
2951 ar8xxx_phy_match(u32 phy_id)
2952 {
2953         int i;
2954
2955         for (i = 0; i < ARRAY_SIZE(ar8xxx_phy_ids); i++)
2956                 if (phy_id == ar8xxx_phy_ids[i])
2957                         return true;
2958
2959         return false;
2960 }
2961
2962 static bool
2963 ar8xxx_is_possible(struct mii_bus *bus)
2964 {
2965         unsigned i;
2966
2967         for (i = 0; i < 4; i++) {
2968                 u32 phy_id;
2969
2970                 phy_id = mdiobus_read(bus, i, MII_PHYSID1) << 16;
2971                 phy_id |= mdiobus_read(bus, i, MII_PHYSID2);
2972                 if (!ar8xxx_phy_match(phy_id)) {
2973                         pr_debug("ar8xxx: unknown PHY at %s:%02x id:%08x\n",
2974                                  dev_name(&bus->dev), i, phy_id);
2975                         return false;
2976                 }
2977         }
2978
2979         return true;
2980 }
2981
2982 static int
2983 ar8xxx_phy_probe(struct phy_device *phydev)
2984 {
2985         struct ar8xxx_priv *priv;
2986         struct switch_dev *swdev;
2987         int ret;
2988
2989         /* skip PHYs at unused adresses */
2990         if (phydev->addr != 0 && phydev->addr != 4)
2991                 return -ENODEV;
2992
2993         if (!ar8xxx_is_possible(phydev->bus))
2994                 return -ENODEV;
2995
2996         mutex_lock(&ar8xxx_dev_list_lock);
2997         list_for_each_entry(priv, &ar8xxx_dev_list, list)
2998                 if (priv->mii_bus == phydev->bus)
2999                         goto found;
3000
3001         priv = ar8xxx_create_mii(phydev->bus);
3002         if (priv == NULL) {
3003                 ret = -ENOMEM;
3004                 goto unlock;
3005         }
3006
3007         ret = ar8xxx_probe_switch(priv);
3008         if (ret)
3009                 goto free_priv;
3010
3011         swdev = &priv->dev;
3012         swdev->alias = dev_name(&priv->mii_bus->dev);
3013         ret = register_switch(swdev, NULL);
3014         if (ret)
3015                 goto free_priv;
3016
3017         pr_info("%s: %s rev. %u switch registered on %s\n",
3018                 swdev->devname, swdev->name, priv->chip_rev,
3019                 dev_name(&priv->mii_bus->dev));
3020
3021 found:
3022         priv->use_count++;
3023
3024         if (phydev->addr == 0) {
3025                 if (ar8xxx_has_gige(priv)) {
3026                         phydev->supported = SUPPORTED_1000baseT_Full;
3027                         phydev->advertising = ADVERTISED_1000baseT_Full;
3028                 } else {
3029                         phydev->supported = SUPPORTED_100baseT_Full;
3030                         phydev->advertising = ADVERTISED_100baseT_Full;
3031                 }
3032
3033                 if (priv->chip->config_at_probe) {
3034                         priv->phy = phydev;
3035
3036                         ret = ar8xxx_start(priv);
3037                         if (ret)
3038                                 goto err_unregister_switch;
3039                 }
3040         } else {
3041                 if (ar8xxx_has_gige(priv)) {
3042                         phydev->supported |= SUPPORTED_1000baseT_Full;
3043                         phydev->advertising |= ADVERTISED_1000baseT_Full;
3044                 }
3045         }
3046
3047         phydev->priv = priv;
3048
3049         list_add(&priv->list, &ar8xxx_dev_list);
3050
3051         mutex_unlock(&ar8xxx_dev_list_lock);
3052
3053         return 0;
3054
3055 err_unregister_switch:
3056         if (--priv->use_count)
3057                 goto unlock;
3058
3059         unregister_switch(&priv->dev);
3060
3061 free_priv:
3062         ar8xxx_free(priv);
3063 unlock:
3064         mutex_unlock(&ar8xxx_dev_list_lock);
3065         return ret;
3066 }
3067
3068 static void
3069 ar8xxx_phy_detach(struct phy_device *phydev)
3070 {
3071         struct net_device *dev = phydev->attached_dev;
3072
3073         if (!dev)
3074                 return;
3075
3076         dev->phy_ptr = NULL;
3077         dev->priv_flags &= ~IFF_NO_IP_ALIGN;
3078         dev->eth_mangle_rx = NULL;
3079         dev->eth_mangle_tx = NULL;
3080 }
3081
3082 static void
3083 ar8xxx_phy_remove(struct phy_device *phydev)
3084 {
3085         struct ar8xxx_priv *priv = phydev->priv;
3086
3087         if (WARN_ON(!priv))
3088                 return;
3089
3090         phydev->priv = NULL;
3091         if (--priv->use_count > 0)
3092                 return;
3093
3094         mutex_lock(&ar8xxx_dev_list_lock);
3095         list_del(&priv->list);
3096         mutex_unlock(&ar8xxx_dev_list_lock);
3097
3098         unregister_switch(&priv->dev);
3099         ar8xxx_mib_stop(priv);
3100         ar8xxx_free(priv);
3101 }
3102
3103 #if LINUX_VERSION_CODE >= KERNEL_VERSION(3,14,0)
3104 static int
3105 ar8xxx_phy_soft_reset(struct phy_device *phydev)
3106 {
3107         /* we don't need an extra reset */
3108         return 0;
3109 }
3110 #endif
3111
3112 static struct phy_driver ar8xxx_phy_driver = {
3113         .phy_id         = 0x004d0000,
3114         .name           = "Atheros AR8216/AR8236/AR8316",
3115         .phy_id_mask    = 0xffff0000,
3116         .features       = PHY_BASIC_FEATURES,
3117         .probe          = ar8xxx_phy_probe,
3118         .remove         = ar8xxx_phy_remove,
3119         .detach         = ar8xxx_phy_detach,
3120         .config_init    = ar8xxx_phy_config_init,
3121         .config_aneg    = ar8xxx_phy_config_aneg,
3122         .read_status    = ar8xxx_phy_read_status,
3123 #if LINUX_VERSION_CODE >= KERNEL_VERSION(3,14,0)
3124         .soft_reset     = ar8xxx_phy_soft_reset,
3125 #endif
3126         .driver         = { .owner = THIS_MODULE },
3127 };
3128
3129 int __init
3130 ar8xxx_init(void)
3131 {
3132         return phy_driver_register(&ar8xxx_phy_driver);
3133 }
3134
3135 void __exit
3136 ar8xxx_exit(void)
3137 {
3138         phy_driver_unregister(&ar8xxx_phy_driver);
3139 }
3140
3141 module_init(ar8xxx_init);
3142 module_exit(ar8xxx_exit);
3143 MODULE_LICENSE("GPL");
3144