target/linux/generic/files/drivers/net/phy/ar8216.c

   1 /*
   2  * ar8216.c: AR8216 switch driver
   3  *
   4  * Copyright (C) 2009 Felix Fietkau <nbd@openwrt.org>
   5  * Copyright (C) 2011-2012 Gabor Juhos <juhosg@openwrt.org>
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License
   9  * as published by the Free Software Foundation; either version 2
  10  * of the License, or (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  */
  17
  18 #include <linux/if.h>
  19 #include <linux/module.h>
  20 #include <linux/init.h>
  21 #include <linux/list.h>
  22 #include <linux/if_ether.h>
  23 #include <linux/skbuff.h>
  24 #include <linux/netdevice.h>
  25 #include <linux/netlink.h>
  26 #include <linux/bitops.h>
  27 #include <net/genetlink.h>
  28 #include <linux/switch.h>
  29 #include <linux/delay.h>
  30 #include <linux/phy.h>
  31 #include <linux/netdevice.h>
  32 #include <linux/etherdevice.h>
  33 #include <linux/lockdep.h>
  34 #include <linux/ar8216_platform.h>
  35 #include <linux/workqueue.h>
  36 #include <linux/of_device.h>
  37 #include <linux/leds.h>
  38 #include <linux/gpio.h>
  39 #include <linux/version.h>
  40
  41 #include "ar8216.h"
  42
  43 /* size of the vlan table */
  44 #define AR8X16_MAX_VLANS        128
  45 #define AR8X16_PROBE_RETRIES    10
  46 #define AR8X16_MAX_PORTS        8
  47
  48 #define AR8XXX_MIB_WORK_DELAY   2000 /* msecs */
  49
  50 struct ar8xxx_priv;
  51
  52 #define AR8XXX_CAP_GIGE                 BIT(0)
  53 #define AR8XXX_CAP_MIB_COUNTERS         BIT(1)
  54
  55 #define AR8XXX_NUM_PHYS         5
  56
  57 enum {
  58         AR8XXX_VER_AR8216 = 0x01,
  59         AR8XXX_VER_AR8236 = 0x03,
  60         AR8XXX_VER_AR8316 = 0x10,
  61         AR8XXX_VER_AR8327 = 0x12,
  62         AR8XXX_VER_AR8337 = 0x13,
  63 };
  64
  65 struct ar8xxx_mib_desc {
  66         unsigned int size;
  67         unsigned int offset;
  68         const char *name;
  69 };
  70
  71 struct ar8xxx_chip {
  72         unsigned long caps;
  73         bool config_at_probe;
  74         bool mii_lo_first;
  75
  76         /* parameters to calculate REG_PORT_STATS_BASE */
  77         unsigned reg_port_stats_start;
  78         unsigned reg_port_stats_length;
  79
  80         int (*hw_init)(struct ar8xxx_priv *priv);
  81         void (*cleanup)(struct ar8xxx_priv *priv);
  82
  83         const char *name;
  84         int vlans;
  85         int ports;
  86         const struct switch_dev_ops *swops;
  87
  88         void (*init_globals)(struct ar8xxx_priv *priv);
  89         void (*init_port)(struct ar8xxx_priv *priv, int port);
  90         void (*setup_port)(struct ar8xxx_priv *priv, int port, u32 members);
  91         u32 (*read_port_status)(struct ar8xxx_priv *priv, int port);
  92         int (*atu_flush)(struct ar8xxx_priv *priv);
  93         void (*vtu_flush)(struct ar8xxx_priv *priv);
  94         void (*vtu_load_vlan)(struct ar8xxx_priv *priv, u32 vid, u32 port_mask);
  95         void (*phy_fixup)(struct ar8xxx_priv *priv, int phy);
  96         void (*set_mirror_regs)(struct ar8xxx_priv *priv);
  97
  98         const struct ar8xxx_mib_desc *mib_decs;
  99         unsigned num_mibs;
 100         unsigned mib_func;
 101 };
 102
 103 enum ar8327_led_pattern {
 104         AR8327_LED_PATTERN_OFF = 0,
 105         AR8327_LED_PATTERN_BLINK,
 106         AR8327_LED_PATTERN_ON,
 107         AR8327_LED_PATTERN_RULE,
 108 };
 109
 110 struct ar8327_led_entry {
 111         unsigned reg;
 112         unsigned shift;
 113 };
 114
 115 struct ar8327_led {
 116         struct led_classdev cdev;
 117         struct ar8xxx_priv *sw_priv;
 118
 119         char *name;
 120         bool active_low;
 121         u8 led_num;
 122         enum ar8327_led_mode mode;
 123
 124         struct mutex mutex;
 125         spinlock_t lock;
 126         struct work_struct led_work;
 127         bool enable_hw_mode;
 128         enum ar8327_led_pattern pattern;
 129 };
 130
 131 struct ar8327_data {
 132         u32 port0_status;
 133         u32 port6_status;
 134
 135         struct ar8327_led **leds;
 136         unsigned int num_leds;
 137 };
 138
 139 struct ar8xxx_priv {
 140         struct switch_dev dev;
 141         struct mii_bus *mii_bus;
 142         struct phy_device *phy;
 143
 144         int (*get_port_link)(unsigned port);
 145
 146         const struct net_device_ops *ndo_old;
 147         struct net_device_ops ndo;
 148         struct mutex reg_mutex;
 149         u8 chip_ver;
 150         u8 chip_rev;
 151         const struct ar8xxx_chip *chip;
 152         void *chip_data;
 153         bool initialized;
 154         bool port4_phy;
 155         char buf[2048];
 156
 157         bool init;
 158
 159         struct mutex mib_lock;
 160         struct delayed_work mib_work;
 161         int mib_next_port;
 162         u64 *mib_stats;
 163
 164         struct list_head list;
 165         unsigned int use_count;
 166
 167         /* all fields below are cleared on reset */
 168         bool vlan;
 169         u16 vlan_id[AR8X16_MAX_VLANS];
 170         u8 vlan_table[AR8X16_MAX_VLANS];
 171         u8 vlan_tagged;
 172         u16 pvid[AR8X16_MAX_PORTS];
 173
 174         /* mirroring */
 175         bool mirror_rx;
 176         bool mirror_tx;
 177         int source_port;
 178         int monitor_port;
 179 };
 180
 181 #define MIB_DESC(_s , _o, _n)   \
 182         {                       \
 183                 .size = (_s),   \
 184                 .offset = (_o), \
 185                 .name = (_n),   \
 186         }
 187
 188 static const struct ar8xxx_mib_desc ar8216_mibs[] = {
 189         MIB_DESC(1, AR8216_STATS_RXBROAD, "RxBroad"),
 190         MIB_DESC(1, AR8216_STATS_RXPAUSE, "RxPause"),
 191         MIB_DESC(1, AR8216_STATS_RXMULTI, "RxMulti"),
 192         MIB_DESC(1, AR8216_STATS_RXFCSERR, "RxFcsErr"),
 193         MIB_DESC(1, AR8216_STATS_RXALIGNERR, "RxAlignErr"),
 194         MIB_DESC(1, AR8216_STATS_RXRUNT, "RxRunt"),
 195         MIB_DESC(1, AR8216_STATS_RXFRAGMENT, "RxFragment"),
 196         MIB_DESC(1, AR8216_STATS_RX64BYTE, "Rx64Byte"),
 197         MIB_DESC(1, AR8216_STATS_RX128BYTE, "Rx128Byte"),
 198         MIB_DESC(1, AR8216_STATS_RX256BYTE, "Rx256Byte"),
 199         MIB_DESC(1, AR8216_STATS_RX512BYTE, "Rx512Byte"),
 200         MIB_DESC(1, AR8216_STATS_RX1024BYTE, "Rx1024Byte"),
 201         MIB_DESC(1, AR8216_STATS_RXMAXBYTE, "RxMaxByte"),
 202         MIB_DESC(1, AR8216_STATS_RXTOOLONG, "RxTooLong"),
 203         MIB_DESC(2, AR8216_STATS_RXGOODBYTE, "RxGoodByte"),
 204         MIB_DESC(2, AR8216_STATS_RXBADBYTE, "RxBadByte"),
 205         MIB_DESC(1, AR8216_STATS_RXOVERFLOW, "RxOverFlow"),
 206         MIB_DESC(1, AR8216_STATS_FILTERED, "Filtered"),
 207         MIB_DESC(1, AR8216_STATS_TXBROAD, "TxBroad"),
 208         MIB_DESC(1, AR8216_STATS_TXPAUSE, "TxPause"),
 209         MIB_DESC(1, AR8216_STATS_TXMULTI, "TxMulti"),
 210         MIB_DESC(1, AR8216_STATS_TXUNDERRUN, "TxUnderRun"),
 211         MIB_DESC(1, AR8216_STATS_TX64BYTE, "Tx64Byte"),
 212         MIB_DESC(1, AR8216_STATS_TX128BYTE, "Tx128Byte"),
 213         MIB_DESC(1, AR8216_STATS_TX256BYTE, "Tx256Byte"),
 214         MIB_DESC(1, AR8216_STATS_TX512BYTE, "Tx512Byte"),
 215         MIB_DESC(1, AR8216_STATS_TX1024BYTE, "Tx1024Byte"),
 216         MIB_DESC(1, AR8216_STATS_TXMAXBYTE, "TxMaxByte"),
 217         MIB_DESC(1, AR8216_STATS_TXOVERSIZE, "TxOverSize"),
 218         MIB_DESC(2, AR8216_STATS_TXBYTE, "TxByte"),
 219         MIB_DESC(1, AR8216_STATS_TXCOLLISION, "TxCollision"),
 220         MIB_DESC(1, AR8216_STATS_TXABORTCOL, "TxAbortCol"),
 221         MIB_DESC(1, AR8216_STATS_TXMULTICOL, "TxMultiCol"),
 222         MIB_DESC(1, AR8216_STATS_TXSINGLECOL, "TxSingleCol"),
 223         MIB_DESC(1, AR8216_STATS_TXEXCDEFER, "TxExcDefer"),
 224         MIB_DESC(1, AR8216_STATS_TXDEFER, "TxDefer"),
 225         MIB_DESC(1, AR8216_STATS_TXLATECOL, "TxLateCol"),
 226 };
 227
 228 static const struct ar8xxx_mib_desc ar8236_mibs[] = {
 229         MIB_DESC(1, AR8236_STATS_RXBROAD, "RxBroad"),
 230         MIB_DESC(1, AR8236_STATS_RXPAUSE, "RxPause"),
 231         MIB_DESC(1, AR8236_STATS_RXMULTI, "RxMulti"),
 232         MIB_DESC(1, AR8236_STATS_RXFCSERR, "RxFcsErr"),
 233         MIB_DESC(1, AR8236_STATS_RXALIGNERR, "RxAlignErr"),
 234         MIB_DESC(1, AR8236_STATS_RXRUNT, "RxRunt"),
 235         MIB_DESC(1, AR8236_STATS_RXFRAGMENT, "RxFragment"),
 236         MIB_DESC(1, AR8236_STATS_RX64BYTE, "Rx64Byte"),
 237         MIB_DESC(1, AR8236_STATS_RX128BYTE, "Rx128Byte"),
 238         MIB_DESC(1, AR8236_STATS_RX256BYTE, "Rx256Byte"),
 239         MIB_DESC(1, AR8236_STATS_RX512BYTE, "Rx512Byte"),
 240         MIB_DESC(1, AR8236_STATS_RX1024BYTE, "Rx1024Byte"),
 241         MIB_DESC(1, AR8236_STATS_RX1518BYTE, "Rx1518Byte"),
 242         MIB_DESC(1, AR8236_STATS_RXMAXBYTE, "RxMaxByte"),
 243         MIB_DESC(1, AR8236_STATS_RXTOOLONG, "RxTooLong"),
 244         MIB_DESC(2, AR8236_STATS_RXGOODBYTE, "RxGoodByte"),
 245         MIB_DESC(2, AR8236_STATS_RXBADBYTE, "RxBadByte"),
 246         MIB_DESC(1, AR8236_STATS_RXOVERFLOW, "RxOverFlow"),
 247         MIB_DESC(1, AR8236_STATS_FILTERED, "Filtered"),
 248         MIB_DESC(1, AR8236_STATS_TXBROAD, "TxBroad"),
 249         MIB_DESC(1, AR8236_STATS_TXPAUSE, "TxPause"),
 250         MIB_DESC(1, AR8236_STATS_TXMULTI, "TxMulti"),
 251         MIB_DESC(1, AR8236_STATS_TXUNDERRUN, "TxUnderRun"),
 252         MIB_DESC(1, AR8236_STATS_TX64BYTE, "Tx64Byte"),
 253         MIB_DESC(1, AR8236_STATS_TX128BYTE, "Tx128Byte"),
 254         MIB_DESC(1, AR8236_STATS_TX256BYTE, "Tx256Byte"),
 255         MIB_DESC(1, AR8236_STATS_TX512BYTE, "Tx512Byte"),
 256         MIB_DESC(1, AR8236_STATS_TX1024BYTE, "Tx1024Byte"),
 257         MIB_DESC(1, AR8236_STATS_TX1518BYTE, "Tx1518Byte"),
 258         MIB_DESC(1, AR8236_STATS_TXMAXBYTE, "TxMaxByte"),
 259         MIB_DESC(1, AR8236_STATS_TXOVERSIZE, "TxOverSize"),
 260         MIB_DESC(2, AR8236_STATS_TXBYTE, "TxByte"),
 261         MIB_DESC(1, AR8236_STATS_TXCOLLISION, "TxCollision"),
 262         MIB_DESC(1, AR8236_STATS_TXABORTCOL, "TxAbortCol"),
 263         MIB_DESC(1, AR8236_STATS_TXMULTICOL, "TxMultiCol"),
 264         MIB_DESC(1, AR8236_STATS_TXSINGLECOL, "TxSingleCol"),
 265         MIB_DESC(1, AR8236_STATS_TXEXCDEFER, "TxExcDefer"),
 266         MIB_DESC(1, AR8236_STATS_TXDEFER, "TxDefer"),
 267         MIB_DESC(1, AR8236_STATS_TXLATECOL, "TxLateCol"),
 268 };
 269
 270 static DEFINE_MUTEX(ar8xxx_dev_list_lock);
 271 static LIST_HEAD(ar8xxx_dev_list);
 272
 273 static inline struct ar8xxx_priv *
 274 swdev_to_ar8xxx(struct switch_dev *swdev)
 275 {
 276         return container_of(swdev, struct ar8xxx_priv, dev);
 277 }
 278
 279 static inline bool ar8xxx_has_gige(struct ar8xxx_priv *priv)
 280 {
 281         return priv->chip->caps & AR8XXX_CAP_GIGE;
 282 }
 283
 284 static inline bool ar8xxx_has_mib_counters(struct ar8xxx_priv *priv)
 285 {
 286         return priv->chip->caps & AR8XXX_CAP_MIB_COUNTERS;
 287 }
 288
 289 static inline bool chip_is_ar8216(struct ar8xxx_priv *priv)
 290 {
 291         return priv->chip_ver == AR8XXX_VER_AR8216;
 292 }
 293
 294 static inline bool chip_is_ar8236(struct ar8xxx_priv *priv)
 295 {
 296         return priv->chip_ver == AR8XXX_VER_AR8236;
 297 }
 298
 299 static inline bool chip_is_ar8316(struct ar8xxx_priv *priv)
 300 {
 301         return priv->chip_ver == AR8XXX_VER_AR8316;
 302 }
 303
 304 static inline bool chip_is_ar8327(struct ar8xxx_priv *priv)
 305 {
 306         return priv->chip_ver == AR8XXX_VER_AR8327;
 307 }
 308
 309 static inline bool chip_is_ar8337(struct ar8xxx_priv *priv)
 310 {
 311         return priv->chip_ver == AR8XXX_VER_AR8337;
 312 }
 313
 314 static inline void
 315 split_addr(u32 regaddr, u16 *r1, u16 *r2, u16 *page)
 316 {
 317         regaddr >>= 1;
 318         *r1 = regaddr & 0x1e;
 319
 320         regaddr >>= 5;
 321         *r2 = regaddr & 0x7;
 322
 323         regaddr >>= 3;
 324         *page = regaddr & 0x1ff;
 325 }
 326
 327 /* inspired by phy_poll_reset in drivers/net/phy/phy_device.c */
 328 static int
 329 ar8xxx_phy_poll_reset(struct mii_bus *bus)
 330 {
 331         unsigned int sleep_msecs = 20;
 332         int ret, elapsed, i;
 333
 334         for (elapsed = sleep_msecs; elapsed <= 600;
 335              elapsed += sleep_msecs) {
 336                 msleep(sleep_msecs);
 337                 for (i = 0; i < AR8XXX_NUM_PHYS; i++) {
 338                         ret = mdiobus_read(bus, i, MII_BMCR);
 339                         if (ret < 0)
 340                                 return ret;
 341                         if (ret & BMCR_RESET)
 342                                 break;
 343                         if (i == AR8XXX_NUM_PHYS - 1) {
 344                                 usleep_range(1000, 2000);
 345                                 return 0;
 346                         }
 347                 }
 348         }
 349         return -ETIMEDOUT;
 350 }
 351
 352 static int
 353 ar8xxx_phy_check_aneg(struct phy_device *phydev)
 354 {
 355         int ret;
 356
 357         if (phydev->autoneg != AUTONEG_ENABLE)
 358                 return 0;
 359         /*
 360          * BMCR_ANENABLE might have been cleared
 361          * by phy_init_hw in certain kernel versions
 362          * therefore check for it
 363          */
 364         ret = phy_read(phydev, MII_BMCR);
 365         if (ret < 0)
 366                 return ret;
 367         if (ret & BMCR_ANENABLE)
 368                 return 0;
 369
 370         dev_info(&phydev->dev, "ANEG disabled, re-enabling ...\n");
 371         ret |= BMCR_ANENABLE | BMCR_ANRESTART;
 372         return phy_write(phydev, MII_BMCR, ret);
 373 }
 374
 375 static void
 376 ar8xxx_phy_init(struct ar8xxx_priv *priv)
 377 {
 378         int i;
 379         struct mii_bus *bus;
 380
 381         bus = priv->mii_bus;
 382         for (i = 0; i < AR8XXX_NUM_PHYS; i++) {
 383                 if (priv->chip->phy_fixup)
 384                         priv->chip->phy_fixup(priv, i);
 385
 386                 /* initialize the port itself */
 387                 mdiobus_write(bus, i, MII_ADVERTISE,
 388                         ADVERTISE_ALL | ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
 389                 if (ar8xxx_has_gige(priv))
 390                         mdiobus_write(bus, i, MII_CTRL1000, ADVERTISE_1000FULL);
 391                 mdiobus_write(bus, i, MII_BMCR, BMCR_RESET | BMCR_ANENABLE);
 392         }
 393
 394         ar8xxx_phy_poll_reset(bus);
 395 }
 396
 397 static u32
 398 mii_read32(struct ar8xxx_priv *priv, int phy_id, int regnum)
 399 {
 400         struct mii_bus *bus = priv->mii_bus;
 401         u16 lo, hi;
 402
 403         lo = bus->read(bus, phy_id, regnum);
 404         hi = bus->read(bus, phy_id, regnum + 1);
 405
 406         return (hi << 16) | lo;
 407 }
 408
 409 static void
 410 mii_write32(struct ar8xxx_priv *priv, int phy_id, int regnum, u32 val)
 411 {
 412         struct mii_bus *bus = priv->mii_bus;
 413         u16 lo, hi;
 414
 415         lo = val & 0xffff;
 416         hi = (u16) (val >> 16);
 417
 418         if (priv->chip->mii_lo_first)
 419         {
 420                 bus->write(bus, phy_id, regnum, lo);
 421                 bus->write(bus, phy_id, regnum + 1, hi);
 422         } else {
 423                 bus->write(bus, phy_id, regnum + 1, hi);
 424                 bus->write(bus, phy_id, regnum, lo);
 425         }
 426 }
 427
 428 static u32
 429 ar8xxx_read(struct ar8xxx_priv *priv, int reg)
 430 {
 431         struct mii_bus *bus = priv->mii_bus;
 432         u16 r1, r2, page;
 433         u32 val;
 434
 435         split_addr((u32) reg, &r1, &r2, &page);
 436
 437         mutex_lock(&bus->mdio_lock);
 438
 439         bus->write(bus, 0x18, 0, page);
 440         usleep_range(1000, 2000); /* wait for the page switch to propagate */
 441         val = mii_read32(priv, 0x10 | r2, r1);
 442
 443         mutex_unlock(&bus->mdio_lock);
 444
 445         return val;
 446 }
 447
 448 static void
 449 ar8xxx_write(struct ar8xxx_priv *priv, int reg, u32 val)
 450 {
 451         struct mii_bus *bus = priv->mii_bus;
 452         u16 r1, r2, page;
 453
 454         split_addr((u32) reg, &r1, &r2, &page);
 455
 456         mutex_lock(&bus->mdio_lock);
 457
 458         bus->write(bus, 0x18, 0, page);
 459         usleep_range(1000, 2000); /* wait for the page switch to propagate */
 460         mii_write32(priv, 0x10 | r2, r1, val);
 461
 462         mutex_unlock(&bus->mdio_lock);
 463 }
 464
 465 static u32
 466 ar8xxx_rmw(struct ar8xxx_priv *priv, int reg, u32 mask, u32 val)
 467 {
 468         struct mii_bus *bus = priv->mii_bus;
 469         u16 r1, r2, page;
 470         u32 ret;
 471
 472         split_addr((u32) reg, &r1, &r2, &page);
 473
 474         mutex_lock(&bus->mdio_lock);
 475
 476         bus->write(bus, 0x18, 0, page);
 477         usleep_range(1000, 2000); /* wait for the page switch to propagate */
 478
 479         ret = mii_read32(priv, 0x10 | r2, r1);
 480         ret &= ~mask;
 481         ret |= val;
 482         mii_write32(priv, 0x10 | r2, r1, ret);
 483
 484         mutex_unlock(&bus->mdio_lock);
 485
 486         return ret;
 487 }
 488
 489 static void
 490 ar8xxx_phy_dbg_write(struct ar8xxx_priv *priv, int phy_addr,
 491                      u16 dbg_addr, u16 dbg_data)
 492 {
 493         struct mii_bus *bus = priv->mii_bus;
 494
 495         mutex_lock(&bus->mdio_lock);
 496         bus->write(bus, phy_addr, MII_ATH_DBG_ADDR, dbg_addr);
 497         bus->write(bus, phy_addr, MII_ATH_DBG_DATA, dbg_data);
 498         mutex_unlock(&bus->mdio_lock);
 499 }
 500
 501 static void
 502 ar8xxx_phy_mmd_write(struct ar8xxx_priv *priv, int phy_addr, u16 addr, u16 data)
 503 {
 504         struct mii_bus *bus = priv->mii_bus;
 505
 506         mutex_lock(&bus->mdio_lock);
 507         bus->write(bus, phy_addr, MII_ATH_MMD_ADDR, addr);
 508         bus->write(bus, phy_addr, MII_ATH_MMD_DATA, data);
 509         mutex_unlock(&bus->mdio_lock);
 510 }
 511
 512 static inline void
 513 ar8xxx_reg_set(struct ar8xxx_priv *priv, int reg, u32 val)
 514 {
 515         ar8xxx_rmw(priv, reg, 0, val);
 516 }
 517
 518 static int
 519 ar8xxx_reg_wait(struct ar8xxx_priv *priv, u32 reg, u32 mask, u32 val,
 520                 unsigned timeout)
 521 {
 522         int i;
 523
 524         for (i = 0; i < timeout; i++) {
 525                 u32 t;
 526
 527                 t = ar8xxx_read(priv, reg);
 528                 if ((t & mask) == val)
 529                         return 0;
 530
 531                 usleep_range(1000, 2000);
 532         }
 533
 534         return -ETIMEDOUT;
 535 }
 536
 537 static int
 538 ar8xxx_mib_op(struct ar8xxx_priv *priv, u32 op)
 539 {
 540         unsigned mib_func = priv->chip->mib_func;
 541         int ret;
 542
 543         lockdep_assert_held(&priv->mib_lock);
 544
 545         /* Capture the hardware statistics for all ports */
 546         ar8xxx_rmw(priv, mib_func, AR8216_MIB_FUNC, (op << AR8216_MIB_FUNC_S));
 547
 548         /* Wait for the capturing to complete. */
 549         ret = ar8xxx_reg_wait(priv, mib_func, AR8216_MIB_BUSY, 0, 10);
 550         if (ret)
 551                 goto out;
 552
 553         ret = 0;
 554
 555 out:
 556         return ret;
 557 }
 558
 559 static int
 560 ar8xxx_mib_capture(struct ar8xxx_priv *priv)
 561 {
 562         return ar8xxx_mib_op(priv, AR8216_MIB_FUNC_CAPTURE);
 563 }
 564
 565 static int
 566 ar8xxx_mib_flush(struct ar8xxx_priv *priv)
 567 {
 568         return ar8xxx_mib_op(priv, AR8216_MIB_FUNC_FLUSH);
 569 }
 570
 571 static void
 572 ar8xxx_mib_fetch_port_stat(struct ar8xxx_priv *priv, int port, bool flush)
 573 {
 574         unsigned int base;
 575         u64 *mib_stats;
 576         int i;
 577
 578         WARN_ON(port >= priv->dev.ports);
 579
 580         lockdep_assert_held(&priv->mib_lock);
 581
 582         base = priv->chip->reg_port_stats_start +
 583                priv->chip->reg_port_stats_length * port;
 584
 585         mib_stats = &priv->mib_stats[port * priv->chip->num_mibs];
 586         for (i = 0; i < priv->chip->num_mibs; i++) {
 587                 const struct ar8xxx_mib_desc *mib;
 588                 u64 t;
 589
 590                 mib = &priv->chip->mib_decs[i];
 591                 t = ar8xxx_read(priv, base + mib->offset);
 592                 if (mib->size == 2) {
 593                         u64 hi;
 594
 595                         hi = ar8xxx_read(priv, base + mib->offset + 4);
 596                         t |= hi << 32;
 597                 }
 598
 599                 if (flush)
 600                         mib_stats[i] = 0;
 601                 else
 602                         mib_stats[i] += t;
 603         }
 604 }
 605
 606 static void
 607 ar8216_read_port_link(struct ar8xxx_priv *priv, int port,
 608                       struct switch_port_link *link)
 609 {
 610         u32 status;
 611         u32 speed;
 612
 613         memset(link, '\0', sizeof(*link));
 614
 615         status = priv->chip->read_port_status(priv, port);
 616
 617         link->aneg = !!(status & AR8216_PORT_STATUS_LINK_AUTO);
 618         if (link->aneg) {
 619                 link->link = !!(status & AR8216_PORT_STATUS_LINK_UP);
 620         } else {
 621                 link->link = true;
 622
 623                 if (priv->get_port_link) {
 624                         int err;
 625
 626                         err = priv->get_port_link(port);
 627                         if (err >= 0)
 628                                 link->link = !!err;
 629                 }
 630         }
 631
 632         if (!link->link)
 633                 return;
 634
 635         link->duplex = !!(status & AR8216_PORT_STATUS_DUPLEX);
 636         link->tx_flow = !!(status & AR8216_PORT_STATUS_TXFLOW);
 637         link->rx_flow = !!(status & AR8216_PORT_STATUS_RXFLOW);
 638
 639         speed = (status & AR8216_PORT_STATUS_SPEED) >>
 640                  AR8216_PORT_STATUS_SPEED_S;
 641
 642         switch (speed) {
 643         case AR8216_PORT_SPEED_10M:
 644                 link->speed = SWITCH_PORT_SPEED_10;
 645                 break;
 646         case AR8216_PORT_SPEED_100M:
 647                 link->speed = SWITCH_PORT_SPEED_100;
 648                 break;
 649         case AR8216_PORT_SPEED_1000M:
 650                 link->speed = SWITCH_PORT_SPEED_1000;
 651                 break;
 652         default:
 653                 link->speed = SWITCH_PORT_SPEED_UNKNOWN;
 654                 break;
 655         }
 656 }
 657
 658 static struct sk_buff *
 659 ar8216_mangle_tx(struct net_device *dev, struct sk_buff *skb)
 660 {
 661         struct ar8xxx_priv *priv = dev->phy_ptr;
 662         unsigned char *buf;
 663
 664         if (unlikely(!priv))
 665                 goto error;
 666
 667         if (!priv->vlan)
 668                 goto send;
 669
 670         if (unlikely(skb_headroom(skb) < 2)) {
 671                 if (pskb_expand_head(skb, 2, 0, GFP_ATOMIC) < 0)
 672                         goto error;
 673         }
 674
 675         buf = skb_push(skb, 2);
 676         buf[0] = 0x10;
 677         buf[1] = 0x80;
 678
 679 send:
 680         return skb;
 681
 682 error:
 683         dev_kfree_skb_any(skb);
 684         return NULL;
 685 }
 686
 687 static void
 688 ar8216_mangle_rx(struct net_device *dev, struct sk_buff *skb)
 689 {
 690         struct ar8xxx_priv *priv;
 691         unsigned char *buf;
 692         int port, vlan;
 693
 694         priv = dev->phy_ptr;
 695         if (!priv)
 696                 return;
 697
 698         /* don't strip the header if vlan mode is disabled */
 699         if (!priv->vlan)
 700                 return;
 701
 702         /* strip header, get vlan id */
 703         buf = skb->data;
 704         skb_pull(skb, 2);
 705
 706         /* check for vlan header presence */
 707         if ((buf[12 + 2] != 0x81) || (buf[13 + 2] != 0x00))
 708                 return;
 709
 710         port = buf[0] & 0xf;
 711
 712         /* no need to fix up packets coming from a tagged source */
 713         if (priv->vlan_tagged & (1 << port))
 714                 return;
 715
 716         /* lookup port vid from local table, the switch passes an invalid vlan id */
 717         vlan = priv->vlan_id[priv->pvid[port]];
 718
 719         buf[14 + 2] &= 0xf0;
 720         buf[14 + 2] |= vlan >> 8;
 721         buf[15 + 2] = vlan & 0xff;
 722 }
 723
 724 static int
 725 ar8216_wait_bit(struct ar8xxx_priv *priv, int reg, u32 mask, u32 val)
 726 {
 727         int timeout = 20;
 728         u32 t = 0;
 729
 730         while (1) {
 731                 t = ar8xxx_read(priv, reg);
 732                 if ((t & mask) == val)
 733                         return 0;
 734
 735                 if (timeout-- <= 0)
 736                         break;
 737
 738                 udelay(10);
 739         }
 740
 741         pr_err("ar8216: timeout on reg %08x: %08x & %08x != %08x\n",
 742                (unsigned int) reg, t, mask, val);
 743         return -ETIMEDOUT;
 744 }
 745
 746 static void
 747 ar8216_vtu_op(struct ar8xxx_priv *priv, u32 op, u32 val)
 748 {
 749         if (ar8216_wait_bit(priv, AR8216_REG_VTU, AR8216_VTU_ACTIVE, 0))
 750                 return;
 751         if ((op & AR8216_VTU_OP) == AR8216_VTU_OP_LOAD) {
 752                 val &= AR8216_VTUDATA_MEMBER;
 753                 val |= AR8216_VTUDATA_VALID;
 754                 ar8xxx_write(priv, AR8216_REG_VTU_DATA, val);
 755         }
 756         op |= AR8216_VTU_ACTIVE;
 757         ar8xxx_write(priv, AR8216_REG_VTU, op);
 758 }
 759
 760 static void
 761 ar8216_vtu_flush(struct ar8xxx_priv *priv)
 762 {
 763         ar8216_vtu_op(priv, AR8216_VTU_OP_FLUSH, 0);
 764 }
 765
 766 static void
 767 ar8216_vtu_load_vlan(struct ar8xxx_priv *priv, u32 vid, u32 port_mask)
 768 {
 769         u32 op;
 770
 771         op = AR8216_VTU_OP_LOAD | (vid << AR8216_VTU_VID_S);
 772         ar8216_vtu_op(priv, op, port_mask);
 773 }
 774
 775 static int
 776 ar8216_atu_flush(struct ar8xxx_priv *priv)
 777 {
 778         int ret;
 779
 780         ret = ar8216_wait_bit(priv, AR8216_REG_ATU, AR8216_ATU_ACTIVE, 0);
 781         if (!ret)
 782                 ar8xxx_write(priv, AR8216_REG_ATU, AR8216_ATU_OP_FLUSH);
 783
 784         return ret;
 785 }
 786
 787 static u32
 788 ar8216_read_port_status(struct ar8xxx_priv *priv, int port)
 789 {
 790         return ar8xxx_read(priv, AR8216_REG_PORT_STATUS(port));
 791 }
 792
 793 static void
 794 ar8216_setup_port(struct ar8xxx_priv *priv, int port, u32 members)
 795 {
 796         u32 header;
 797         u32 egress, ingress;
 798         u32 pvid;
 799
 800         if (priv->vlan) {
 801                 pvid = priv->vlan_id[priv->pvid[port]];
 802                 if (priv->vlan_tagged & (1 << port))
 803                         egress = AR8216_OUT_ADD_VLAN;
 804                 else
 805                         egress = AR8216_OUT_STRIP_VLAN;
 806                 ingress = AR8216_IN_SECURE;
 807         } else {
 808                 pvid = port;
 809                 egress = AR8216_OUT_KEEP;
 810                 ingress = AR8216_IN_PORT_ONLY;
 811         }
 812
 813         if (chip_is_ar8216(priv) && priv->vlan && port == AR8216_PORT_CPU)
 814                 header = AR8216_PORT_CTRL_HEADER;
 815         else
 816                 header = 0;
 817
 818         ar8xxx_rmw(priv, AR8216_REG_PORT_CTRL(port),
 819                    AR8216_PORT_CTRL_LEARN | AR8216_PORT_CTRL_VLAN_MODE |
 820                    AR8216_PORT_CTRL_SINGLE_VLAN | AR8216_PORT_CTRL_STATE |
 821                    AR8216_PORT_CTRL_HEADER | AR8216_PORT_CTRL_LEARN_LOCK,
 822                    AR8216_PORT_CTRL_LEARN | header |
 823                    (egress << AR8216_PORT_CTRL_VLAN_MODE_S) |
 824                    (AR8216_PORT_STATE_FORWARD << AR8216_PORT_CTRL_STATE_S));
 825
 826         ar8xxx_rmw(priv, AR8216_REG_PORT_VLAN(port),
 827                    AR8216_PORT_VLAN_DEST_PORTS | AR8216_PORT_VLAN_MODE |
 828                    AR8216_PORT_VLAN_DEFAULT_ID,
 829                    (members << AR8216_PORT_VLAN_DEST_PORTS_S) |
 830                    (ingress << AR8216_PORT_VLAN_MODE_S) |
 831                    (pvid << AR8216_PORT_VLAN_DEFAULT_ID_S));
 832 }
 833
 834 static int
 835 ar8216_hw_init(struct ar8xxx_priv *priv)
 836 {
 837         if (priv->initialized)
 838                 return 0;
 839
 840         ar8xxx_phy_init(priv);
 841
 842         priv->initialized = true;
 843         return 0;
 844 }
 845
 846 static void
 847 ar8216_init_globals(struct ar8xxx_priv *priv)
 848 {
 849         /* standard atheros magic */
 850         ar8xxx_write(priv, 0x38, 0xc000050e);
 851
 852         ar8xxx_rmw(priv, AR8216_REG_GLOBAL_CTRL,
 853                    AR8216_GCTRL_MTU, 1518 + 8 + 2);
 854 }
 855
 856 static void
 857 ar8216_init_port(struct ar8xxx_priv *priv, int port)
 858 {
 859         /* Enable port learning and tx */
 860         ar8xxx_write(priv, AR8216_REG_PORT_CTRL(port),
 861                 AR8216_PORT_CTRL_LEARN |
 862                 (4 << AR8216_PORT_CTRL_STATE_S));
 863
 864         ar8xxx_write(priv, AR8216_REG_PORT_VLAN(port), 0);
 865
 866         if (port == AR8216_PORT_CPU) {
 867                 ar8xxx_write(priv, AR8216_REG_PORT_STATUS(port),
 868                         AR8216_PORT_STATUS_LINK_UP |
 869                         (ar8xxx_has_gige(priv) ?
 870                                 AR8216_PORT_SPEED_1000M : AR8216_PORT_SPEED_100M) |
 871                         AR8216_PORT_STATUS_TXMAC |
 872                         AR8216_PORT_STATUS_RXMAC |
 873                         (chip_is_ar8316(priv) ? AR8216_PORT_STATUS_RXFLOW : 0) |
 874                         (chip_is_ar8316(priv) ? AR8216_PORT_STATUS_TXFLOW : 0) |
 875                         AR8216_PORT_STATUS_DUPLEX);
 876         } else {
 877                 ar8xxx_write(priv, AR8216_REG_PORT_STATUS(port),
 878                         AR8216_PORT_STATUS_LINK_AUTO);
 879         }
 880 }
 881
 882 static void
 883 ar8236_setup_port(struct ar8xxx_priv *priv, int port, u32 members)
 884 {
 885         u32 egress, ingress;
 886         u32 pvid;
 887
 888         if (priv->vlan) {
 889                 pvid = priv->vlan_id[priv->pvid[port]];
 890                 if (priv->vlan_tagged & (1 << port))
 891                         egress = AR8216_OUT_ADD_VLAN;
 892                 else
 893                         egress = AR8216_OUT_STRIP_VLAN;
 894                 ingress = AR8216_IN_SECURE;
 895         } else {
 896                 pvid = port;
 897                 egress = AR8216_OUT_KEEP;
 898                 ingress = AR8216_IN_PORT_ONLY;
 899         }
 900
 901         ar8xxx_rmw(priv, AR8216_REG_PORT_CTRL(port),
 902                    AR8216_PORT_CTRL_LEARN | AR8216_PORT_CTRL_VLAN_MODE |
 903                    AR8216_PORT_CTRL_SINGLE_VLAN | AR8216_PORT_CTRL_STATE |
 904                    AR8216_PORT_CTRL_HEADER | AR8216_PORT_CTRL_LEARN_LOCK,
 905                    AR8216_PORT_CTRL_LEARN |
 906                    (egress << AR8216_PORT_CTRL_VLAN_MODE_S) |
 907                    (AR8216_PORT_STATE_FORWARD << AR8216_PORT_CTRL_STATE_S));
 908
 909         ar8xxx_rmw(priv, AR8236_REG_PORT_VLAN(port),
 910                    AR8236_PORT_VLAN_DEFAULT_ID,
 911                    (pvid << AR8236_PORT_VLAN_DEFAULT_ID_S));
 912
 913         ar8xxx_rmw(priv, AR8236_REG_PORT_VLAN2(port),
 914                    AR8236_PORT_VLAN2_VLAN_MODE |
 915                    AR8236_PORT_VLAN2_MEMBER,
 916                    (ingress << AR8236_PORT_VLAN2_VLAN_MODE_S) |
 917                    (members << AR8236_PORT_VLAN2_MEMBER_S));
 918 }
 919
 920 static void
 921 ar8236_init_globals(struct ar8xxx_priv *priv)
 922 {
 923         /* enable jumbo frames */
 924         ar8xxx_rmw(priv, AR8216_REG_GLOBAL_CTRL,
 925                    AR8316_GCTRL_MTU, 9018 + 8 + 2);
 926
 927         /* enable cpu port to receive arp frames */
 928         ar8xxx_rmw(priv, AR8216_REG_ATU_CTRL,
 929                    AR8236_ATU_CTRL_RES, AR8236_ATU_CTRL_RES);
 930
 931         /* enable cpu port to receive multicast and broadcast frames */
 932         ar8xxx_rmw(priv, AR8216_REG_FLOOD_MASK,
 933                    AR8236_FM_CPU_BROADCAST_EN | AR8236_FM_CPU_BCAST_FWD_EN,
 934                    AR8236_FM_CPU_BROADCAST_EN | AR8236_FM_CPU_BCAST_FWD_EN);
 935
 936         /* Enable MIB counters */
 937         ar8xxx_rmw(priv, AR8216_REG_MIB_FUNC, AR8216_MIB_FUNC | AR8236_MIB_EN,
 938                    (AR8216_MIB_FUNC_NO_OP << AR8216_MIB_FUNC_S) |
 939                    AR8236_MIB_EN);
 940 }
 941
 942 static int
 943 ar8316_hw_init(struct ar8xxx_priv *priv)
 944 {
 945         u32 val, newval;
 946
 947         val = ar8xxx_read(priv, AR8316_REG_POSTRIP);
 948
 949         if (priv->phy->interface == PHY_INTERFACE_MODE_RGMII) {
 950                 if (priv->port4_phy) {
 951                         /* value taken from Ubiquiti RouterStation Pro */
 952                         newval = 0x81461bea;
 953                         pr_info("ar8316: Using port 4 as PHY\n");
 954                 } else {
 955                         newval = 0x01261be2;
 956                         pr_info("ar8316: Using port 4 as switch port\n");
 957                 }
 958         } else if (priv->phy->interface == PHY_INTERFACE_MODE_GMII) {
 959                 /* value taken from AVM Fritz!Box 7390 sources */
 960                 newval = 0x010e5b71;
 961         } else {
 962                 /* no known value for phy interface */
 963                 pr_err("ar8316: unsupported mii mode: %d.\n",
 964                        priv->phy->interface);
 965                 return -EINVAL;
 966         }
 967
 968         if (val == newval)
 969                 goto out;
 970
 971         ar8xxx_write(priv, AR8316_REG_POSTRIP, newval);
 972
 973         if (priv->port4_phy &&
 974             priv->phy->interface == PHY_INTERFACE_MODE_RGMII) {
 975                 /* work around for phy4 rgmii mode */
 976                 ar8xxx_phy_dbg_write(priv, 4, 0x12, 0x480c);
 977                 /* rx delay */
 978                 ar8xxx_phy_dbg_write(priv, 4, 0x0, 0x824e);
 979                 /* tx delay */
 980                 ar8xxx_phy_dbg_write(priv, 4, 0x5, 0x3d47);
 981                 msleep(1000);
 982         }
 983
 984         ar8xxx_phy_init(priv);
 985
 986 out:
 987         priv->initialized = true;
 988         return 0;
 989 }
 990
 991 static void
 992 ar8316_init_globals(struct ar8xxx_priv *priv)
 993 {
 994         /* standard atheros magic */
 995         ar8xxx_write(priv, 0x38, 0xc000050e);
 996
 997         /* enable cpu port to receive multicast and broadcast frames */
 998         ar8xxx_write(priv, AR8216_REG_FLOOD_MASK, 0x003f003f);
 999
1000         /* enable jumbo frames */
1001         ar8xxx_rmw(priv, AR8216_REG_GLOBAL_CTRL,
1002                    AR8316_GCTRL_MTU, 9018 + 8 + 2);
1003
1004         /* Enable MIB counters */
1005         ar8xxx_rmw(priv, AR8216_REG_MIB_FUNC, AR8216_MIB_FUNC | AR8236_MIB_EN,
1006                    (AR8216_MIB_FUNC_NO_OP << AR8216_MIB_FUNC_S) |
1007                    AR8236_MIB_EN);
1008 }
1009
1010 static u32
1011 ar8327_get_pad_cfg(struct ar8327_pad_cfg *cfg)
1012 {
1013         u32 t;
1014
1015         if (!cfg)
1016                 return 0;
1017
1018         t = 0;
1019         switch (cfg->mode) {
1020         case AR8327_PAD_NC:
1021                 break;
1022
1023         case AR8327_PAD_MAC2MAC_MII:
1024                 t = AR8327_PAD_MAC_MII_EN;
1025                 if (cfg->rxclk_sel)
1026                         t |= AR8327_PAD_MAC_MII_RXCLK_SEL;
1027                 if (cfg->txclk_sel)
1028                         t |= AR8327_PAD_MAC_MII_TXCLK_SEL;
1029                 break;
1030
1031         case AR8327_PAD_MAC2MAC_GMII:
1032                 t = AR8327_PAD_MAC_GMII_EN;
1033                 if (cfg->rxclk_sel)
1034                         t |= AR8327_PAD_MAC_GMII_RXCLK_SEL;
1035                 if (cfg->txclk_sel)
1036                         t |= AR8327_PAD_MAC_GMII_TXCLK_SEL;
1037                 break;
1038
1039         case AR8327_PAD_MAC_SGMII:
1040                 t = AR8327_PAD_SGMII_EN;
1041
1042                 /*
1043                  * WAR for the QUalcomm Atheros AP136 board.
1044                  * It seems that RGMII TX/RX delay settings needs to be
1045                  * applied for SGMII mode as well, The ethernet is not
1046                  * reliable without this.
1047                  */
1048                 t |= cfg->txclk_delay_sel << AR8327_PAD_RGMII_TXCLK_DELAY_SEL_S;
1049                 t |= cfg->rxclk_delay_sel << AR8327_PAD_RGMII_RXCLK_DELAY_SEL_S;
1050                 if (cfg->rxclk_delay_en)
1051                         t |= AR8327_PAD_RGMII_RXCLK_DELAY_EN;
1052                 if (cfg->txclk_delay_en)
1053                         t |= AR8327_PAD_RGMII_TXCLK_DELAY_EN;
1054
1055                 if (cfg->sgmii_delay_en)
1056                         t |= AR8327_PAD_SGMII_DELAY_EN;
1057
1058                 break;
1059
1060         case AR8327_PAD_MAC2PHY_MII:
1061                 t = AR8327_PAD_PHY_MII_EN;
1062                 if (cfg->rxclk_sel)
1063                         t |= AR8327_PAD_PHY_MII_RXCLK_SEL;
1064                 if (cfg->txclk_sel)
1065                         t |= AR8327_PAD_PHY_MII_TXCLK_SEL;
1066                 break;
1067
1068         case AR8327_PAD_MAC2PHY_GMII:
1069                 t = AR8327_PAD_PHY_GMII_EN;
1070                 if (cfg->pipe_rxclk_sel)
1071                         t |= AR8327_PAD_PHY_GMII_PIPE_RXCLK_SEL;
1072                 if (cfg->rxclk_sel)
1073                         t |= AR8327_PAD_PHY_GMII_RXCLK_SEL;
1074                 if (cfg->txclk_sel)
1075                         t |= AR8327_PAD_PHY_GMII_TXCLK_SEL;
1076                 break;
1077
1078         case AR8327_PAD_MAC_RGMII:
1079                 t = AR8327_PAD_RGMII_EN;
1080                 t |= cfg->txclk_delay_sel << AR8327_PAD_RGMII_TXCLK_DELAY_SEL_S;
1081                 t |= cfg->rxclk_delay_sel << AR8327_PAD_RGMII_RXCLK_DELAY_SEL_S;
1082                 if (cfg->rxclk_delay_en)
1083                         t |= AR8327_PAD_RGMII_RXCLK_DELAY_EN;
1084                 if (cfg->txclk_delay_en)
1085                         t |= AR8327_PAD_RGMII_TXCLK_DELAY_EN;
1086                 break;
1087
1088         case AR8327_PAD_PHY_GMII:
1089                 t = AR8327_PAD_PHYX_GMII_EN;
1090                 break;
1091
1092         case AR8327_PAD_PHY_RGMII:
1093                 t = AR8327_PAD_PHYX_RGMII_EN;
1094                 break;
1095
1096         case AR8327_PAD_PHY_MII:
1097                 t = AR8327_PAD_PHYX_MII_EN;
1098                 break;
1099         }
1100
1101         return t;
1102 }
1103
1104 static void
1105 ar8327_phy_fixup(struct ar8xxx_priv *priv, int phy)
1106 {
1107         switch (priv->chip_rev) {
1108         case 1:
1109                 /* For 100M waveform */
1110                 ar8xxx_phy_dbg_write(priv, phy, 0, 0x02ea);
1111                 /* Turn on Gigabit clock */
1112                 ar8xxx_phy_dbg_write(priv, phy, 0x3d, 0x68a0);
1113                 break;
1114
1115         case 2:
1116                 ar8xxx_phy_mmd_write(priv, phy, 0x7, 0x3c);
1117                 ar8xxx_phy_mmd_write(priv, phy, 0x4007, 0x0);
1118                 /* fallthrough */
1119         case 4:
1120                 ar8xxx_phy_mmd_write(priv, phy, 0x3, 0x800d);
1121                 ar8xxx_phy_mmd_write(priv, phy, 0x4003, 0x803f);
1122
1123                 ar8xxx_phy_dbg_write(priv, phy, 0x3d, 0x6860);
1124                 ar8xxx_phy_dbg_write(priv, phy, 0x5, 0x2c46);
1125                 ar8xxx_phy_dbg_write(priv, phy, 0x3c, 0x6000);
1126                 break;
1127         }
1128 }
1129
1130 static u32
1131 ar8327_get_port_init_status(struct ar8327_port_cfg *cfg)
1132 {
1133         u32 t;
1134
1135         if (!cfg->force_link)
1136                 return AR8216_PORT_STATUS_LINK_AUTO;
1137
1138         t = AR8216_PORT_STATUS_TXMAC | AR8216_PORT_STATUS_RXMAC;
1139         t |= cfg->duplex ? AR8216_PORT_STATUS_DUPLEX : 0;
1140         t |= cfg->rxpause ? AR8216_PORT_STATUS_RXFLOW : 0;
1141         t |= cfg->txpause ? AR8216_PORT_STATUS_TXFLOW : 0;
1142
1143         switch (cfg->speed) {
1144         case AR8327_PORT_SPEED_10:
1145                 t |= AR8216_PORT_SPEED_10M;
1146                 break;
1147         case AR8327_PORT_SPEED_100:
1148                 t |= AR8216_PORT_SPEED_100M;
1149                 break;
1150         case AR8327_PORT_SPEED_1000:
1151                 t |= AR8216_PORT_SPEED_1000M;
1152                 break;
1153         }
1154
1155         return t;
1156 }
1157
1158 #define AR8327_LED_ENTRY(_num, _reg, _shift) \
1159         [_num] = { .reg = (_reg), .shift = (_shift) }
1160
1161 static const struct ar8327_led_entry
1162 ar8327_led_map[AR8327_NUM_LEDS] = {
1163         AR8327_LED_ENTRY(AR8327_LED_PHY0_0, 0, 14),
1164         AR8327_LED_ENTRY(AR8327_LED_PHY0_1, 1, 14),
1165         AR8327_LED_ENTRY(AR8327_LED_PHY0_2, 2, 14),
1166
1167         AR8327_LED_ENTRY(AR8327_LED_PHY1_0, 3, 8),
1168         AR8327_LED_ENTRY(AR8327_LED_PHY1_1, 3, 10),
1169         AR8327_LED_ENTRY(AR8327_LED_PHY1_2, 3, 12),
1170
1171         AR8327_LED_ENTRY(AR8327_LED_PHY2_0, 3, 14),
1172         AR8327_LED_ENTRY(AR8327_LED_PHY2_1, 3, 16),
1173         AR8327_LED_ENTRY(AR8327_LED_PHY2_2, 3, 18),
1174
1175         AR8327_LED_ENTRY(AR8327_LED_PHY3_0, 3, 20),
1176         AR8327_LED_ENTRY(AR8327_LED_PHY3_1, 3, 22),
1177         AR8327_LED_ENTRY(AR8327_LED_PHY3_2, 3, 24),
1178
1179         AR8327_LED_ENTRY(AR8327_LED_PHY4_0, 0, 30),
1180         AR8327_LED_ENTRY(AR8327_LED_PHY4_1, 1, 30),
1181         AR8327_LED_ENTRY(AR8327_LED_PHY4_2, 2, 30),
1182 };
1183
1184 static void
1185 ar8327_set_led_pattern(struct ar8xxx_priv *priv, unsigned int led_num,
1186                        enum ar8327_led_pattern pattern)
1187 {
1188         const struct ar8327_led_entry *entry;
1189
1190         entry = &ar8327_led_map[led_num];
1191         ar8xxx_rmw(priv, AR8327_REG_LED_CTRL(entry->reg),
1192                    (3 << entry->shift), pattern << entry->shift);
1193 }
1194
1195 static void
1196 ar8327_led_work_func(struct work_struct *work)
1197 {
1198         struct ar8327_led *aled;
1199         u8 pattern;
1200
1201         aled = container_of(work, struct ar8327_led, led_work);
1202
1203         spin_lock(&aled->lock);
1204         pattern = aled->pattern;
1205         spin_unlock(&aled->lock);
1206
1207         ar8327_set_led_pattern(aled->sw_priv, aled->led_num,
1208                                pattern);
1209 }
1210
1211 static void
1212 ar8327_led_schedule_change(struct ar8327_led *aled, u8 pattern)
1213 {
1214         if (aled->pattern == pattern)
1215                 return;
1216
1217         aled->pattern = pattern;
1218         schedule_work(&aled->led_work);
1219 }
1220
1221 static inline struct ar8327_led *
1222 led_cdev_to_ar8327_led(struct led_classdev *led_cdev)
1223 {
1224         return container_of(led_cdev, struct ar8327_led, cdev);
1225 }
1226
1227 static int
1228 ar8327_led_blink_set(struct led_classdev *led_cdev,
1229                      unsigned long *delay_on,
1230                      unsigned long *delay_off)
1231 {
1232         struct ar8327_led *aled = led_cdev_to_ar8327_led(led_cdev);
1233
1234         if (*delay_on == 0 && *delay_off == 0) {
1235                 *delay_on = 125;
1236                 *delay_off = 125;
1237         }
1238
1239         if (*delay_on != 125 || *delay_off != 125) {
1240                 /*
1241                  * The hardware only supports blinking at 4Hz. Fall back
1242                  * to software implementation in other cases.
1243                  */
1244                 return -EINVAL;
1245         }
1246
1247         spin_lock(&aled->lock);
1248
1249         aled->enable_hw_mode = false;
1250         ar8327_led_schedule_change(aled, AR8327_LED_PATTERN_BLINK);
1251
1252         spin_unlock(&aled->lock);
1253
1254         return 0;
1255 }
1256
1257 static void
1258 ar8327_led_set_brightness(struct led_classdev *led_cdev,
1259                           enum led_brightness brightness)
1260 {
1261         struct ar8327_led *aled = led_cdev_to_ar8327_led(led_cdev);
1262         u8 pattern;
1263         bool active;
1264
1265         active = (brightness != LED_OFF);
1266         active ^= aled->active_low;
1267
1268         pattern = (active) ? AR8327_LED_PATTERN_ON :
1269                              AR8327_LED_PATTERN_OFF;
1270
1271         spin_lock(&aled->lock);
1272
1273         aled->enable_hw_mode = false;
1274         ar8327_led_schedule_change(aled, pattern);
1275
1276         spin_unlock(&aled->lock);
1277 }
1278
1279 static ssize_t
1280 ar8327_led_enable_hw_mode_show(struct device *dev,
1281                                struct device_attribute *attr,
1282                                char *buf)
1283 {
1284         struct led_classdev *led_cdev = dev_get_drvdata(dev);
1285         struct ar8327_led *aled = led_cdev_to_ar8327_led(led_cdev);
1286         ssize_t ret = 0;
1287
1288         spin_lock(&aled->lock);
1289         ret += sprintf(buf, "%d\n", aled->enable_hw_mode);
1290         spin_unlock(&aled->lock);
1291
1292         return ret;
1293 }
1294
1295 static ssize_t
1296 ar8327_led_enable_hw_mode_store(struct device *dev,
1297                                 struct device_attribute *attr,
1298                                 const char *buf,
1299                                 size_t size)
1300 {
1301         struct led_classdev *led_cdev = dev_get_drvdata(dev);
1302         struct ar8327_led *aled = led_cdev_to_ar8327_led(led_cdev);
1303         u8 pattern;
1304         u8 value;
1305         int ret;
1306
1307         ret = kstrtou8(buf, 10, &value);
1308         if (ret < 0)
1309                 return -EINVAL;
1310
1311         spin_lock(&aled->lock);
1312
1313         aled->enable_hw_mode = !!value;
1314         if (aled->enable_hw_mode)
1315                 pattern = AR8327_LED_PATTERN_RULE;
1316         else
1317                 pattern = AR8327_LED_PATTERN_OFF;
1318
1319         ar8327_led_schedule_change(aled, pattern);
1320
1321         spin_unlock(&aled->lock);
1322
1323         return size;
1324 }
1325
1326 static DEVICE_ATTR(enable_hw_mode,  S_IRUGO | S_IWUSR,
1327                    ar8327_led_enable_hw_mode_show,
1328                    ar8327_led_enable_hw_mode_store);
1329
1330 static int
1331 ar8327_led_register(struct ar8327_led *aled)
1332 {
1333         int ret;
1334
1335         ret = led_classdev_register(NULL, &aled->cdev);
1336         if (ret < 0)
1337                 return ret;
1338
1339         if (aled->mode == AR8327_LED_MODE_HW) {
1340                 ret = device_create_file(aled->cdev.dev,
1341                                          &dev_attr_enable_hw_mode);
1342                 if (ret)
1343                         goto err_unregister;
1344         }
1345
1346         return 0;
1347
1348 err_unregister:
1349         led_classdev_unregister(&aled->cdev);
1350         return ret;
1351 }
1352
1353 static void
1354 ar8327_led_unregister(struct ar8327_led *aled)
1355 {
1356         if (aled->mode == AR8327_LED_MODE_HW)
1357                 device_remove_file(aled->cdev.dev, &dev_attr_enable_hw_mode);
1358
1359         led_classdev_unregister(&aled->cdev);
1360         cancel_work_sync(&aled->led_work);
1361 }
1362
1363 static int
1364 ar8327_led_create(struct ar8xxx_priv *priv,
1365                   const struct ar8327_led_info *led_info)
1366 {
1367         struct ar8327_data *data = priv->chip_data;
1368         struct ar8327_led *aled;
1369         int ret;
1370
1371         if (!IS_ENABLED(CONFIG_AR8216_PHY_LEDS))
1372                 return 0;
1373
1374         if (!led_info->name)
1375                 return -EINVAL;
1376
1377         if (led_info->led_num >= AR8327_NUM_LEDS)
1378                 return -EINVAL;
1379
1380         aled = kzalloc(sizeof(*aled) + strlen(led_info->name) + 1,
1381                        GFP_KERNEL);
1382         if (!aled)
1383                 return -ENOMEM;
1384
1385         aled->sw_priv = priv;
1386         aled->led_num = led_info->led_num;
1387         aled->active_low = led_info->active_low;
1388         aled->mode = led_info->mode;
1389
1390         if (aled->mode == AR8327_LED_MODE_HW)
1391                 aled->enable_hw_mode = true;
1392
1393         aled->name = (char *)(aled + 1);
1394         strcpy(aled->name, led_info->name);
1395
1396         aled->cdev.name = aled->name;
1397         aled->cdev.brightness_set = ar8327_led_set_brightness;
1398         aled->cdev.blink_set = ar8327_led_blink_set;
1399         aled->cdev.default_trigger = led_info->default_trigger;
1400
1401         spin_lock_init(&aled->lock);
1402         mutex_init(&aled->mutex);
1403         INIT_WORK(&aled->led_work, ar8327_led_work_func);
1404
1405         ret = ar8327_led_register(aled);
1406         if (ret)
1407                 goto err_free;
1408
1409         data->leds[data->num_leds++] = aled;
1410
1411         return 0;
1412
1413 err_free:
1414         kfree(aled);
1415         return ret;
1416 }
1417
1418 static void
1419 ar8327_led_destroy(struct ar8327_led *aled)
1420 {
1421         ar8327_led_unregister(aled);
1422         kfree(aled);
1423 }
1424
1425 static void
1426 ar8327_leds_init(struct ar8xxx_priv *priv)
1427 {
1428         struct ar8327_data *data = priv->chip_data;
1429         unsigned i;
1430
1431         if (!IS_ENABLED(CONFIG_AR8216_PHY_LEDS))
1432                 return;
1433
1434         for (i = 0; i < data->num_leds; i++) {
1435                 struct ar8327_led *aled;
1436
1437                 aled = data->leds[i];
1438
1439                 if (aled->enable_hw_mode)
1440                         aled->pattern = AR8327_LED_PATTERN_RULE;
1441                 else
1442                         aled->pattern = AR8327_LED_PATTERN_OFF;
1443
1444                 ar8327_set_led_pattern(priv, aled->led_num, aled->pattern);
1445         }
1446 }
1447
1448 static void
1449 ar8327_leds_cleanup(struct ar8xxx_priv *priv)
1450 {
1451         struct ar8327_data *data = priv->chip_data;
1452         unsigned i;
1453
1454         if (!IS_ENABLED(CONFIG_AR8216_PHY_LEDS))
1455                 return;
1456
1457         for (i = 0; i < data->num_leds; i++) {
1458                 struct ar8327_led *aled;
1459
1460                 aled = data->leds[i];
1461                 ar8327_led_destroy(aled);
1462         }
1463
1464         kfree(data->leds);
1465 }
1466
1467 static int
1468 ar8327_hw_config_pdata(struct ar8xxx_priv *priv,
1469                        struct ar8327_platform_data *pdata)
1470 {
1471         struct ar8327_led_cfg *led_cfg;
1472         struct ar8327_data *data = priv->chip_data;
1473         u32 pos, new_pos;
1474         u32 t;
1475
1476         if (!pdata)
1477                 return -EINVAL;
1478
1479         priv->get_port_link = pdata->get_port_link;
1480
1481         data->port0_status = ar8327_get_port_init_status(&pdata->port0_cfg);
1482         data->port6_status = ar8327_get_port_init_status(&pdata->port6_cfg);
1483
1484         t = ar8327_get_pad_cfg(pdata->pad0_cfg);
1485         if (chip_is_ar8337(priv))
1486                 t |= AR8337_PAD_MAC06_EXCHANGE_EN;
1487
1488         ar8xxx_write(priv, AR8327_REG_PAD0_MODE, t);
1489         t = ar8327_get_pad_cfg(pdata->pad5_cfg);
1490         ar8xxx_write(priv, AR8327_REG_PAD5_MODE, t);
1491         t = ar8327_get_pad_cfg(pdata->pad6_cfg);
1492         ar8xxx_write(priv, AR8327_REG_PAD6_MODE, t);
1493
1494         pos = ar8xxx_read(priv, AR8327_REG_POWER_ON_STRIP);
1495         new_pos = pos;
1496
1497         led_cfg = pdata->led_cfg;
1498         if (led_cfg) {
1499                 if (led_cfg->open_drain)
1500                         new_pos |= AR8327_POWER_ON_STRIP_LED_OPEN_EN;
1501                 else
1502                         new_pos &= ~AR8327_POWER_ON_STRIP_LED_OPEN_EN;
1503
1504                 ar8xxx_write(priv, AR8327_REG_LED_CTRL0, led_cfg->led_ctrl0);
1505                 ar8xxx_write(priv, AR8327_REG_LED_CTRL1, led_cfg->led_ctrl1);
1506                 ar8xxx_write(priv, AR8327_REG_LED_CTRL2, led_cfg->led_ctrl2);
1507                 ar8xxx_write(priv, AR8327_REG_LED_CTRL3, led_cfg->led_ctrl3);
1508
1509                 if (new_pos != pos)
1510                         new_pos |= AR8327_POWER_ON_STRIP_POWER_ON_SEL;
1511         }
1512
1513         if (pdata->sgmii_cfg) {
1514                 t = pdata->sgmii_cfg->sgmii_ctrl;
1515                 if (priv->chip_rev == 1)
1516                         t |= AR8327_SGMII_CTRL_EN_PLL |
1517                              AR8327_SGMII_CTRL_EN_RX |
1518                              AR8327_SGMII_CTRL_EN_TX;
1519                 else
1520                         t &= ~(AR8327_SGMII_CTRL_EN_PLL |
1521                                AR8327_SGMII_CTRL_EN_RX |
1522                                AR8327_SGMII_CTRL_EN_TX);
1523
1524                 ar8xxx_write(priv, AR8327_REG_SGMII_CTRL, t);
1525
1526                 if (pdata->sgmii_cfg->serdes_aen)
1527                         new_pos &= ~AR8327_POWER_ON_STRIP_SERDES_AEN;
1528                 else
1529                         new_pos |= AR8327_POWER_ON_STRIP_SERDES_AEN;
1530         }
1531
1532         ar8xxx_write(priv, AR8327_REG_POWER_ON_STRIP, new_pos);
1533
1534         if (pdata->leds && pdata->num_leds) {
1535                 int i;
1536
1537                 data->leds = kzalloc(pdata->num_leds * sizeof(void *),
1538                                      GFP_KERNEL);
1539                 if (!data->leds)
1540                         return -ENOMEM;
1541
1542                 for (i = 0; i < pdata->num_leds; i++)
1543                         ar8327_led_create(priv, &pdata->leds[i]);
1544         }
1545
1546         return 0;
1547 }
1548
1549 #ifdef CONFIG_OF
1550 static int
1551 ar8327_hw_config_of(struct ar8xxx_priv *priv, struct device_node *np)
1552 {
1553         struct ar8327_data *data = priv->chip_data;
1554         const __be32 *paddr;
1555         int len;
1556         int i;
1557
1558         paddr = of_get_property(np, "qca,ar8327-initvals", &len);
1559         if (!paddr || len < (2 * sizeof(*paddr)))
1560                 return -EINVAL;
1561
1562         len /= sizeof(*paddr);
1563
1564         for (i = 0; i < len - 1; i += 2) {
1565                 u32 reg;
1566                 u32 val;
1567
1568                 reg = be32_to_cpup(paddr + i);
1569                 val = be32_to_cpup(paddr + i + 1);
1570
1571                 switch (reg) {
1572                 case AR8327_REG_PORT_STATUS(0):
1573                         data->port0_status = val;
1574                         break;
1575                 case AR8327_REG_PORT_STATUS(6):
1576                         data->port6_status = val;
1577                         break;
1578                 default:
1579                         ar8xxx_write(priv, reg, val);
1580                         break;
1581                 }
1582         }
1583
1584         return 0;
1585 }
1586 #else
1587 static inline int
1588 ar8327_hw_config_of(struct ar8xxx_priv *priv, struct device_node *np)
1589 {
1590         return -EINVAL;
1591 }
1592 #endif
1593
1594 static int
1595 ar8327_hw_init(struct ar8xxx_priv *priv)
1596 {
1597         int ret;
1598
1599         priv->chip_data = kzalloc(sizeof(struct ar8327_data), GFP_KERNEL);
1600         if (!priv->chip_data)
1601                 return -ENOMEM;
1602
1603         if (priv->phy->dev.of_node)
1604                 ret = ar8327_hw_config_of(priv, priv->phy->dev.of_node);
1605         else
1606                 ret = ar8327_hw_config_pdata(priv,
1607                                              priv->phy->dev.platform_data);
1608
1609         if (ret)
1610                 return ret;
1611
1612         ar8327_leds_init(priv);
1613
1614         ar8xxx_phy_init(priv);
1615
1616         return 0;
1617 }
1618
1619 static void
1620 ar8327_cleanup(struct ar8xxx_priv *priv)
1621 {
1622         ar8327_leds_cleanup(priv);
1623 }
1624
1625 static void
1626 ar8327_init_globals(struct ar8xxx_priv *priv)
1627 {
1628         u32 t;
1629
1630         /* enable CPU port and disable mirror port */
1631         t = AR8327_FWD_CTRL0_CPU_PORT_EN |
1632             AR8327_FWD_CTRL0_MIRROR_PORT;
1633         ar8xxx_write(priv, AR8327_REG_FWD_CTRL0, t);
1634
1635         /* forward multicast and broadcast frames to CPU */
1636         t = (AR8327_PORTS_ALL << AR8327_FWD_CTRL1_UC_FLOOD_S) |
1637             (AR8327_PORTS_ALL << AR8327_FWD_CTRL1_MC_FLOOD_S) |
1638             (AR8327_PORTS_ALL << AR8327_FWD_CTRL1_BC_FLOOD_S);
1639         ar8xxx_write(priv, AR8327_REG_FWD_CTRL1, t);
1640
1641         /* enable jumbo frames */
1642         ar8xxx_rmw(priv, AR8327_REG_MAX_FRAME_SIZE,
1643                    AR8327_MAX_FRAME_SIZE_MTU, 9018 + 8 + 2);
1644
1645         /* Enable MIB counters */
1646         ar8xxx_reg_set(priv, AR8327_REG_MODULE_EN,
1647                        AR8327_MODULE_EN_MIB);
1648
1649         /* Disable EEE on all ports due to stability issues */
1650         t = ar8xxx_read(priv, AR8327_REG_EEE_CTRL);
1651         t |= AR8327_EEE_CTRL_DISABLE_PHY(0) |
1652              AR8327_EEE_CTRL_DISABLE_PHY(1) |
1653              AR8327_EEE_CTRL_DISABLE_PHY(2) |
1654              AR8327_EEE_CTRL_DISABLE_PHY(3) |
1655              AR8327_EEE_CTRL_DISABLE_PHY(4);
1656         ar8xxx_write(priv, AR8327_REG_EEE_CTRL, t);
1657 }
1658
1659 static void
1660 ar8327_init_port(struct ar8xxx_priv *priv, int port)
1661 {
1662         struct ar8327_data *data = priv->chip_data;
1663         u32 t;
1664
1665         if (port == AR8216_PORT_CPU)
1666                 t = data->port0_status;
1667         else if (port == 6)
1668                 t = data->port6_status;
1669         else
1670                 t = AR8216_PORT_STATUS_LINK_AUTO;
1671
1672         ar8xxx_write(priv, AR8327_REG_PORT_STATUS(port), t);
1673         ar8xxx_write(priv, AR8327_REG_PORT_HEADER(port), 0);
1674
1675         t = 1 << AR8327_PORT_VLAN0_DEF_SVID_S;
1676         t |= 1 << AR8327_PORT_VLAN0_DEF_CVID_S;
1677         ar8xxx_write(priv, AR8327_REG_PORT_VLAN0(port), t);
1678
1679         t = AR8327_PORT_VLAN1_OUT_MODE_UNTOUCH << AR8327_PORT_VLAN1_OUT_MODE_S;
1680         ar8xxx_write(priv, AR8327_REG_PORT_VLAN1(port), t);
1681
1682         t = AR8327_PORT_LOOKUP_LEARN;
1683         t |= AR8216_PORT_STATE_FORWARD << AR8327_PORT_LOOKUP_STATE_S;
1684         ar8xxx_write(priv, AR8327_REG_PORT_LOOKUP(port), t);
1685 }
1686
1687 static u32
1688 ar8327_read_port_status(struct ar8xxx_priv *priv, int port)
1689 {
1690         return ar8xxx_read(priv, AR8327_REG_PORT_STATUS(port));
1691 }
1692
1693 static int
1694 ar8327_atu_flush(struct ar8xxx_priv *priv)
1695 {
1696         int ret;
1697
1698         ret = ar8216_wait_bit(priv, AR8327_REG_ATU_FUNC,
1699                               AR8327_ATU_FUNC_BUSY, 0);
1700         if (!ret)
1701                 ar8xxx_write(priv, AR8327_REG_ATU_FUNC,
1702                             AR8327_ATU_FUNC_OP_FLUSH);
1703
1704         return ret;
1705 }
1706
1707 static void
1708 ar8327_vtu_op(struct ar8xxx_priv *priv, u32 op, u32 val)
1709 {
1710         if (ar8216_wait_bit(priv, AR8327_REG_VTU_FUNC1,
1711                             AR8327_VTU_FUNC1_BUSY, 0))
1712                 return;
1713
1714         if ((op & AR8327_VTU_FUNC1_OP) == AR8327_VTU_FUNC1_OP_LOAD)
1715                 ar8xxx_write(priv, AR8327_REG_VTU_FUNC0, val);
1716
1717         op |= AR8327_VTU_FUNC1_BUSY;
1718         ar8xxx_write(priv, AR8327_REG_VTU_FUNC1, op);
1719 }
1720
1721 static void
1722 ar8327_vtu_flush(struct ar8xxx_priv *priv)
1723 {
1724         ar8327_vtu_op(priv, AR8327_VTU_FUNC1_OP_FLUSH, 0);
1725 }
1726
1727 static void
1728 ar8327_vtu_load_vlan(struct ar8xxx_priv *priv, u32 vid, u32 port_mask)
1729 {
1730         u32 op;
1731         u32 val;
1732         int i;
1733
1734         op = AR8327_VTU_FUNC1_OP_LOAD | (vid << AR8327_VTU_FUNC1_VID_S);
1735         val = AR8327_VTU_FUNC0_VALID | AR8327_VTU_FUNC0_IVL;
1736         for (i = 0; i < AR8327_NUM_PORTS; i++) {
1737                 u32 mode;
1738
1739                 if ((port_mask & BIT(i)) == 0)
1740                         mode = AR8327_VTU_FUNC0_EG_MODE_NOT;
1741                 else if (priv->vlan == 0)
1742                         mode = AR8327_VTU_FUNC0_EG_MODE_KEEP;
1743                 else if ((priv->vlan_tagged & BIT(i)) || (priv->vlan_id[priv->pvid[i]] != vid))
1744                         mode = AR8327_VTU_FUNC0_EG_MODE_TAG;
1745                 else
1746                         mode = AR8327_VTU_FUNC0_EG_MODE_UNTAG;
1747
1748                 val |= mode << AR8327_VTU_FUNC0_EG_MODE_S(i);
1749         }
1750         ar8327_vtu_op(priv, op, val);
1751 }
1752
1753 static void
1754 ar8327_setup_port(struct ar8xxx_priv *priv, int port, u32 members)
1755 {
1756         u32 t;
1757         u32 egress, ingress;
1758         u32 pvid = priv->vlan_id[priv->pvid[port]];
1759
1760         if (priv->vlan) {
1761                 egress = AR8327_PORT_VLAN1_OUT_MODE_UNMOD;
1762                 ingress = AR8216_IN_SECURE;
1763         } else {
1764                 egress = AR8327_PORT_VLAN1_OUT_MODE_UNTOUCH;
1765                 ingress = AR8216_IN_PORT_ONLY;
1766         }
1767
1768         t = pvid << AR8327_PORT_VLAN0_DEF_SVID_S;
1769         t |= pvid << AR8327_PORT_VLAN0_DEF_CVID_S;
1770         ar8xxx_write(priv, AR8327_REG_PORT_VLAN0(port), t);
1771
1772         t = AR8327_PORT_VLAN1_PORT_VLAN_PROP;
1773         t |= egress << AR8327_PORT_VLAN1_OUT_MODE_S;
1774         ar8xxx_write(priv, AR8327_REG_PORT_VLAN1(port), t);
1775
1776         t = members;
1777         t |= AR8327_PORT_LOOKUP_LEARN;
1778         t |= ingress << AR8327_PORT_LOOKUP_IN_MODE_S;
1779         t |= AR8216_PORT_STATE_FORWARD << AR8327_PORT_LOOKUP_STATE_S;
1780         ar8xxx_write(priv, AR8327_REG_PORT_LOOKUP(port), t);
1781 }
1782
1783 static int
1784 ar8xxx_sw_set_vlan(struct switch_dev *dev, const struct switch_attr *attr,
1785                    struct switch_val *val)
1786 {
1787         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1788         priv->vlan = !!val->value.i;
1789         return 0;
1790 }
1791
1792 static int
1793 ar8xxx_sw_get_vlan(struct switch_dev *dev, const struct switch_attr *attr,
1794                    struct switch_val *val)
1795 {
1796         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1797         val->value.i = priv->vlan;
1798         return 0;
1799 }
1800
1801
1802 static int
1803 ar8xxx_sw_set_pvid(struct switch_dev *dev, int port, int vlan)
1804 {
1805         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1806
1807         /* make sure no invalid PVIDs get set */
1808
1809         if (vlan >= dev->vlans)
1810                 return -EINVAL;
1811
1812         priv->pvid[port] = vlan;
1813         return 0;
1814 }
1815
1816 static int
1817 ar8xxx_sw_get_pvid(struct switch_dev *dev, int port, int *vlan)
1818 {
1819         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1820         *vlan = priv->pvid[port];
1821         return 0;
1822 }
1823
1824 static int
1825 ar8xxx_sw_set_vid(struct switch_dev *dev, const struct switch_attr *attr,
1826                   struct switch_val *val)
1827 {
1828         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1829         priv->vlan_id[val->port_vlan] = val->value.i;
1830         return 0;
1831 }
1832
1833 static int
1834 ar8xxx_sw_get_vid(struct switch_dev *dev, const struct switch_attr *attr,
1835                   struct switch_val *val)
1836 {
1837         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1838         val->value.i = priv->vlan_id[val->port_vlan];
1839         return 0;
1840 }
1841
1842 static int
1843 ar8xxx_sw_get_port_link(struct switch_dev *dev, int port,
1844                         struct switch_port_link *link)
1845 {
1846         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1847
1848         ar8216_read_port_link(priv, port, link);
1849         return 0;
1850 }
1851
1852 static int
1853 ar8xxx_sw_get_ports(struct switch_dev *dev, struct switch_val *val)
1854 {
1855         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1856         u8 ports = priv->vlan_table[val->port_vlan];
1857         int i;
1858
1859         val->len = 0;
1860         for (i = 0; i < dev->ports; i++) {
1861                 struct switch_port *p;
1862
1863                 if (!(ports & (1 << i)))
1864                         continue;
1865
1866                 p = &val->value.ports[val->len++];
1867                 p->id = i;
1868                 if (priv->vlan_tagged & (1 << i))
1869                         p->flags = (1 << SWITCH_PORT_FLAG_TAGGED);
1870                 else
1871                         p->flags = 0;
1872         }
1873         return 0;
1874 }
1875
1876 static int
1877 ar8327_sw_get_ports(struct switch_dev *dev, struct switch_val *val)
1878 {
1879         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1880         u8 ports = priv->vlan_table[val->port_vlan];
1881         int i;
1882
1883         val->len = 0;
1884         for (i = 0; i < dev->ports; i++) {
1885                 struct switch_port *p;
1886
1887                 if (!(ports & (1 << i)))
1888                         continue;
1889
1890                 p = &val->value.ports[val->len++];
1891                 p->id = i;
1892                 if ((priv->vlan_tagged & (1 << i)) || (priv->pvid[i] != val->port_vlan))
1893                         p->flags = (1 << SWITCH_PORT_FLAG_TAGGED);
1894                 else
1895                         p->flags = 0;
1896         }
1897         return 0;
1898 }
1899
1900 static int
1901 ar8xxx_sw_set_ports(struct switch_dev *dev, struct switch_val *val)
1902 {
1903         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1904         u8 *vt = &priv->vlan_table[val->port_vlan];
1905         int i, j;
1906
1907         *vt = 0;
1908         for (i = 0; i < val->len; i++) {
1909                 struct switch_port *p = &val->value.ports[i];
1910
1911                 if (p->flags & (1 << SWITCH_PORT_FLAG_TAGGED)) {
1912                         priv->vlan_tagged |= (1 << p->id);
1913                 } else {
1914                         priv->vlan_tagged &= ~(1 << p->id);
1915                         priv->pvid[p->id] = val->port_vlan;
1916
1917                         /* make sure that an untagged port does not
1918                          * appear in other vlans */
1919                         for (j = 0; j < AR8X16_MAX_VLANS; j++) {
1920                                 if (j == val->port_vlan)
1921                                         continue;
1922                                 priv->vlan_table[j] &= ~(1 << p->id);
1923                         }
1924                 }
1925
1926                 *vt |= 1 << p->id;
1927         }
1928         return 0;
1929 }
1930
1931 static int
1932 ar8327_sw_set_ports(struct switch_dev *dev, struct switch_val *val)
1933 {
1934         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1935         u8 *vt = &priv->vlan_table[val->port_vlan];
1936         int i;
1937
1938         *vt = 0;
1939         for (i = 0; i < val->len; i++) {
1940                 struct switch_port *p = &val->value.ports[i];
1941
1942                 if (p->flags & (1 << SWITCH_PORT_FLAG_TAGGED)) {
1943                         if (val->port_vlan == priv->pvid[p->id]) {
1944                                 priv->vlan_tagged |= (1 << p->id);
1945                         }
1946                 } else {
1947                         priv->vlan_tagged &= ~(1 << p->id);
1948                         priv->pvid[p->id] = val->port_vlan;
1949                 }
1950
1951                 *vt |= 1 << p->id;
1952         }
1953         return 0;
1954 }
1955
1956 static void
1957 ar8327_set_mirror_regs(struct ar8xxx_priv *priv)
1958 {
1959         int port;
1960
1961         /* reset all mirror registers */
1962         ar8xxx_rmw(priv, AR8327_REG_FWD_CTRL0,
1963                    AR8327_FWD_CTRL0_MIRROR_PORT,
1964                    (0xF << AR8327_FWD_CTRL0_MIRROR_PORT_S));
1965         for (port = 0; port < AR8327_NUM_PORTS; port++) {
1966                 ar8xxx_rmw(priv, AR8327_REG_PORT_LOOKUP(port),
1967                            AR8327_PORT_LOOKUP_ING_MIRROR_EN,
1968                            0);
1969
1970                 ar8xxx_rmw(priv, AR8327_REG_PORT_HOL_CTRL1(port),
1971                            AR8327_PORT_HOL_CTRL1_EG_MIRROR_EN,
1972                            0);
1973         }
1974
1975         /* now enable mirroring if necessary */
1976         if (priv->source_port >= AR8327_NUM_PORTS ||
1977             priv->monitor_port >= AR8327_NUM_PORTS ||
1978             priv->source_port == priv->monitor_port) {
1979                 return;
1980         }
1981
1982         ar8xxx_rmw(priv, AR8327_REG_FWD_CTRL0,
1983                    AR8327_FWD_CTRL0_MIRROR_PORT,
1984                    (priv->monitor_port << AR8327_FWD_CTRL0_MIRROR_PORT_S));
1985
1986         if (priv->mirror_rx)
1987                 ar8xxx_rmw(priv, AR8327_REG_PORT_LOOKUP(priv->source_port),
1988                            AR8327_PORT_LOOKUP_ING_MIRROR_EN,
1989                            AR8327_PORT_LOOKUP_ING_MIRROR_EN);
1990
1991         if (priv->mirror_tx)
1992                 ar8xxx_rmw(priv, AR8327_REG_PORT_HOL_CTRL1(priv->source_port),
1993                            AR8327_PORT_HOL_CTRL1_EG_MIRROR_EN,
1994                            AR8327_PORT_HOL_CTRL1_EG_MIRROR_EN);
1995 }
1996
1997 static void
1998 ar8216_set_mirror_regs(struct ar8xxx_priv *priv)
1999 {
2000         int port;
2001
2002         /* reset all mirror registers */
2003         ar8xxx_rmw(priv, AR8216_REG_GLOBAL_CPUPORT,
2004                    AR8216_GLOBAL_CPUPORT_MIRROR_PORT,
2005                    (0xF << AR8216_GLOBAL_CPUPORT_MIRROR_PORT_S));
2006         for (port = 0; port < AR8216_NUM_PORTS; port++) {
2007                 ar8xxx_rmw(priv, AR8216_REG_PORT_CTRL(port),
2008                            AR8216_PORT_CTRL_MIRROR_RX,
2009                            0);
2010
2011                 ar8xxx_rmw(priv, AR8216_REG_PORT_CTRL(port),
2012                            AR8216_PORT_CTRL_MIRROR_TX,
2013                            0);
2014         }
2015
2016         /* now enable mirroring if necessary */
2017         if (priv->source_port >= AR8216_NUM_PORTS ||
2018             priv->monitor_port >= AR8216_NUM_PORTS ||
2019             priv->source_port == priv->monitor_port) {
2020                 return;
2021         }
2022
2023         ar8xxx_rmw(priv, AR8216_REG_GLOBAL_CPUPORT,
2024                    AR8216_GLOBAL_CPUPORT_MIRROR_PORT,
2025                    (priv->monitor_port << AR8216_GLOBAL_CPUPORT_MIRROR_PORT_S));
2026
2027         if (priv->mirror_rx)
2028                 ar8xxx_rmw(priv, AR8216_REG_PORT_CTRL(priv->source_port),
2029                            AR8216_PORT_CTRL_MIRROR_RX,
2030                            AR8216_PORT_CTRL_MIRROR_RX);
2031
2032         if (priv->mirror_tx)
2033                 ar8xxx_rmw(priv, AR8216_REG_PORT_CTRL(priv->source_port),
2034                            AR8216_PORT_CTRL_MIRROR_TX,
2035                            AR8216_PORT_CTRL_MIRROR_TX);
2036 }
2037
2038 static int
2039 ar8xxx_sw_hw_apply(struct switch_dev *dev)
2040 {
2041         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
2042         u8 portmask[AR8X16_MAX_PORTS];
2043         int i, j;
2044
2045         mutex_lock(&priv->reg_mutex);
2046         /* flush all vlan translation unit entries */
2047         priv->chip->vtu_flush(priv);
2048
2049         memset(portmask, 0, sizeof(portmask));
2050         if (!priv->init) {
2051                 /* calculate the port destination masks and load vlans
2052                  * into the vlan translation unit */
2053                 for (j = 0; j < AR8X16_MAX_VLANS; j++) {
2054                         u8 vp = priv->vlan_table[j];
2055
2056                         if (!vp)
2057                                 continue;
2058
2059                         for (i = 0; i < dev->ports; i++) {
2060                                 u8 mask = (1 << i);
2061                                 if (vp & mask)
2062                                         portmask[i] |= vp & ~mask;
2063                         }
2064
2065                         priv->chip->vtu_load_vlan(priv, priv->vlan_id[j],
2066                                                  priv->vlan_table[j]);
2067                 }
2068         } else {
2069                 /* vlan disabled:
2070                  * isolate all ports, but connect them to the cpu port */
2071                 for (i = 0; i < dev->ports; i++) {
2072                         if (i == AR8216_PORT_CPU)
2073                                 continue;
2074
2075                         portmask[i] = 1 << AR8216_PORT_CPU;
2076                         portmask[AR8216_PORT_CPU] |= (1 << i);
2077                 }
2078         }
2079
2080         /* update the port destination mask registers and tag settings */
2081         for (i = 0; i < dev->ports; i++) {
2082                 priv->chip->setup_port(priv, i, portmask[i]);
2083         }
2084
2085         priv->chip->set_mirror_regs(priv);
2086
2087         mutex_unlock(&priv->reg_mutex);
2088         return 0;
2089 }
2090
2091 static int
2092 ar8xxx_sw_reset_switch(struct switch_dev *dev)
2093 {
2094         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
2095         int i;
2096
2097         mutex_lock(&priv->reg_mutex);
2098         memset(&priv->vlan, 0, sizeof(struct ar8xxx_priv) -
2099                 offsetof(struct ar8xxx_priv, vlan));
2100
2101         for (i = 0; i < AR8X16_MAX_VLANS; i++)
2102                 priv->vlan_id[i] = i;
2103
2104         /* Configure all ports */
2105         for (i = 0; i < dev->ports; i++)
2106                 priv->chip->init_port(priv, i);
2107
2108         priv->mirror_rx = false;
2109         priv->mirror_tx = false;
2110         priv->source_port = 0;
2111         priv->monitor_port = 0;
2112
2113         priv->chip->init_globals(priv);
2114
2115         mutex_unlock(&priv->reg_mutex);
2116
2117         return ar8xxx_sw_hw_apply(dev);
2118 }
2119
2120 static int
2121 ar8xxx_sw_set_reset_mibs(struct switch_dev *dev,
2122                          const struct switch_attr *attr,
2123                          struct switch_val *val)
2124 {
2125         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
2126         unsigned int len;
2127         int ret;
2128
2129         if (!ar8xxx_has_mib_counters(priv))
2130                 return -EOPNOTSUPP;
2131
2132         mutex_lock(&priv->mib_lock);
2133
2134         len = priv->dev.ports * priv->chip->num_mibs *
2135               sizeof(*priv->mib_stats);
2136         memset(priv->mib_stats, '\0', len);
2137         ret = ar8xxx_mib_flush(priv);
2138         if (ret)
2139                 goto unlock;
2140
2141         ret = 0;
2142
2143 unlock:
2144         mutex_unlock(&priv->mib_lock);
2145         return ret;
2146 }
2147
2148 static int
2149 ar8xxx_sw_set_mirror_rx_enable(struct switch_dev *dev,
2150                                const struct switch_attr *attr,
2151                                struct switch_val *val)
2152 {
2153         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
2154
2155         mutex_lock(&priv->reg_mutex);
2156         priv->mirror_rx = !!val->value.i;
2157         priv->chip->set_mirror_regs(priv);
2158         mutex_unlock(&priv->reg_mutex);
2159
2160         return 0;
2161 }
2162
2163 static int
2164 ar8xxx_sw_get_mirror_rx_enable(struct switch_dev *dev,
2165                                const struct switch_attr *attr,
2166                                struct switch_val *val)
2167 {
2168         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
2169         val->value.i = priv->mirror_rx;
2170         return 0;
2171 }
2172
2173 static int
2174 ar8xxx_sw_set_mirror_tx_enable(struct switch_dev *dev,
2175                                const struct switch_attr *attr,
2176                                struct switch_val *val)
2177 {
2178         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
2179
2180         mutex_lock(&priv->reg_mutex);
2181         priv->mirror_tx = !!val->value.i;
2182         priv->chip->set_mirror_regs(priv);
2183         mutex_unlock(&priv->reg_mutex);
2184
2185         return 0;
2186 }
2187
2188 static int
2189 ar8xxx_sw_get_mirror_tx_enable(struct switch_dev *dev,
2190                                const struct switch_attr *attr,
2191                                struct switch_val *val)
2192 {
2193         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
2194         val->value.i = priv->mirror_tx;
2195         return 0;
2196 }
2197
2198 static int
2199 ar8xxx_sw_set_mirror_monitor_port(struct switch_dev *dev,
2200                                   const struct switch_attr *attr,
2201                                   struct switch_val *val)
2202 {
2203         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
2204
2205         mutex_lock(&priv->reg_mutex);
2206         priv->monitor_port = val->value.i;
2207         priv->chip->set_mirror_regs(priv);
2208         mutex_unlock(&priv->reg_mutex);
2209
2210         return 0;
2211 }
2212
2213 static int
2214 ar8xxx_sw_get_mirror_monitor_port(struct switch_dev *dev,
2215                                   const struct switch_attr *attr,
2216                                   struct switch_val *val)
2217 {
2218         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
2219         val->value.i = priv->monitor_port;
2220         return 0;
2221 }
2222
2223 static int
2224 ar8xxx_sw_set_mirror_source_port(struct switch_dev *dev,
2225                                  const struct switch_attr *attr,
2226                                  struct switch_val *val)
2227 {
2228         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
2229
2230         mutex_lock(&priv->reg_mutex);
2231         priv->source_port = val->value.i;
2232         priv->chip->set_mirror_regs(priv);
2233         mutex_unlock(&priv->reg_mutex);
2234
2235         return 0;
2236 }
2237
2238 static int
2239 ar8xxx_sw_get_mirror_source_port(struct switch_dev *dev,
2240                                  const struct switch_attr *attr,
2241                                  struct switch_val *val)
2242 {
2243         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
2244         val->value.i = priv->source_port;
2245         return 0;
2246 }
2247
2248 static int
2249 ar8xxx_sw_set_port_reset_mib(struct switch_dev *dev,
2250                              const struct switch_attr *attr,
2251                              struct switch_val *val)
2252 {
2253         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
2254         int port;
2255         int ret;
2256
2257         if (!ar8xxx_has_mib_counters(priv))
2258                 return -EOPNOTSUPP;
2259
2260         port = val->port_vlan;
2261         if (port >= dev->ports)
2262                 return -EINVAL;
2263
2264         mutex_lock(&priv->mib_lock);
2265         ret = ar8xxx_mib_capture(priv);
2266         if (ret)
2267                 goto unlock;
2268
2269         ar8xxx_mib_fetch_port_stat(priv, port, true);
2270
2271         ret = 0;
2272
2273 unlock:
2274         mutex_unlock(&priv->mib_lock);
2275         return ret;
2276 }
2277
2278 static int
2279 ar8xxx_sw_get_port_mib(struct switch_dev *dev,
2280                        const struct switch_attr *attr,
2281                        struct switch_val *val)
2282 {
2283         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
2284         const struct ar8xxx_chip *chip = priv->chip;
2285         u64 *mib_stats;
2286         int port;
2287         int ret;
2288         char *buf = priv->buf;
2289         int i, len = 0;
2290
2291         if (!ar8xxx_has_mib_counters(priv))
2292                 return -EOPNOTSUPP;
2293
2294         port = val->port_vlan;
2295         if (port >= dev->ports)
2296                 return -EINVAL;
2297
2298         mutex_lock(&priv->mib_lock);
2299         ret = ar8xxx_mib_capture(priv);
2300         if (ret)
2301                 goto unlock;
2302
2303         ar8xxx_mib_fetch_port_stat(priv, port, false);
2304
2305         len += snprintf(buf + len, sizeof(priv->buf) - len,
2306                         "Port %d MIB counters\n",
2307                         port);
2308
2309         mib_stats = &priv->mib_stats[port * chip->num_mibs];
2310         for (i = 0; i < chip->num_mibs; i++)
2311                 len += snprintf(buf + len, sizeof(priv->buf) - len,
2312                                 "%-12s: %llu\n",
2313                                 chip->mib_decs[i].name,
2314                                 mib_stats[i]);
2315
2316         val->value.s = buf;
2317         val->len = len;
2318
2319         ret = 0;
2320
2321 unlock:
2322         mutex_unlock(&priv->mib_lock);
2323         return ret;
2324 }
2325
2326 static struct switch_attr ar8xxx_sw_attr_globals[] = {
2327         {
2328                 .type = SWITCH_TYPE_INT,
2329                 .name = "enable_vlan",
2330                 .description = "Enable VLAN mode",
2331                 .set = ar8xxx_sw_set_vlan,
2332                 .get = ar8xxx_sw_get_vlan,
2333                 .max = 1
2334         },
2335         {
2336                 .type = SWITCH_TYPE_NOVAL,
2337                 .name = "reset_mibs",
2338                 .description = "Reset all MIB counters",
2339                 .set = ar8xxx_sw_set_reset_mibs,
2340         },
2341         {
2342                 .type = SWITCH_TYPE_INT,
2343                 .name = "enable_mirror_rx",
2344                 .description = "Enable mirroring of RX packets",
2345                 .set = ar8xxx_sw_set_mirror_rx_enable,
2346                 .get = ar8xxx_sw_get_mirror_rx_enable,
2347                 .max = 1
2348         },
2349         {
2350                 .type = SWITCH_TYPE_INT,
2351                 .name = "enable_mirror_tx",
2352                 .description = "Enable mirroring of TX packets",
2353                 .set = ar8xxx_sw_set_mirror_tx_enable,
2354                 .get = ar8xxx_sw_get_mirror_tx_enable,
2355                 .max = 1
2356         },
2357         {
2358                 .type = SWITCH_TYPE_INT,
2359                 .name = "mirror_monitor_port",
2360                 .description = "Mirror monitor port",
2361                 .set = ar8xxx_sw_set_mirror_monitor_port,
2362                 .get = ar8xxx_sw_get_mirror_monitor_port,
2363                 .max = AR8216_NUM_PORTS - 1
2364         },
2365         {
2366                 .type = SWITCH_TYPE_INT,
2367                 .name = "mirror_source_port",
2368                 .description = "Mirror source port",
2369                 .set = ar8xxx_sw_set_mirror_source_port,
2370                 .get = ar8xxx_sw_get_mirror_source_port,
2371                 .max = AR8216_NUM_PORTS - 1
2372         },
2373 };
2374
2375 static struct switch_attr ar8327_sw_attr_globals[] = {
2376         {
2377                 .type = SWITCH_TYPE_INT,
2378                 .name = "enable_vlan",
2379                 .description = "Enable VLAN mode",
2380                 .set = ar8xxx_sw_set_vlan,
2381                 .get = ar8xxx_sw_get_vlan,
2382                 .max = 1
2383         },
2384         {
2385                 .type = SWITCH_TYPE_NOVAL,
2386                 .name = "reset_mibs",
2387                 .description = "Reset all MIB counters",
2388                 .set = ar8xxx_sw_set_reset_mibs,
2389         },
2390         {
2391                 .type = SWITCH_TYPE_INT,
2392                 .name = "enable_mirror_rx",
2393                 .description = "Enable mirroring of RX packets",
2394                 .set = ar8xxx_sw_set_mirror_rx_enable,
2395                 .get = ar8xxx_sw_get_mirror_rx_enable,
2396                 .max = 1
2397         },
2398         {
2399                 .type = SWITCH_TYPE_INT,
2400                 .name = "enable_mirror_tx",
2401                 .description = "Enable mirroring of TX packets",
2402                 .set = ar8xxx_sw_set_mirror_tx_enable,
2403                 .get = ar8xxx_sw_get_mirror_tx_enable,
2404                 .max = 1
2405         },
2406         {
2407                 .type = SWITCH_TYPE_INT,
2408                 .name = "mirror_monitor_port",
2409                 .description = "Mirror monitor port",
2410                 .set = ar8xxx_sw_set_mirror_monitor_port,
2411                 .get = ar8xxx_sw_get_mirror_monitor_port,
2412                 .max = AR8327_NUM_PORTS - 1
2413         },
2414         {
2415                 .type = SWITCH_TYPE_INT,
2416                 .name = "mirror_source_port",
2417                 .description = "Mirror source port",
2418                 .set = ar8xxx_sw_set_mirror_source_port,
2419                 .get = ar8xxx_sw_get_mirror_source_port,
2420                 .max = AR8327_NUM_PORTS - 1
2421         },
2422 };
2423
2424 static struct switch_attr ar8xxx_sw_attr_port[] = {
2425         {
2426                 .type = SWITCH_TYPE_NOVAL,
2427                 .name = "reset_mib",
2428                 .description = "Reset single port MIB counters",
2429                 .set = ar8xxx_sw_set_port_reset_mib,
2430         },
2431         {
2432                 .type = SWITCH_TYPE_STRING,
2433                 .name = "mib",
2434                 .description = "Get port's MIB counters",
2435                 .set = NULL,
2436                 .get = ar8xxx_sw_get_port_mib,
2437         },
2438 };
2439
2440 static struct switch_attr ar8xxx_sw_attr_vlan[] = {
2441         {
2442                 .type = SWITCH_TYPE_INT,
2443                 .name = "vid",
2444                 .description = "VLAN ID (0-4094)",
2445                 .set = ar8xxx_sw_set_vid,
2446                 .get = ar8xxx_sw_get_vid,
2447                 .max = 4094,
2448         },
2449 };
2450
2451 static const struct switch_dev_ops ar8xxx_sw_ops = {
2452         .attr_global = {
2453                 .attr = ar8xxx_sw_attr_globals,
2454                 .n_attr = ARRAY_SIZE(ar8xxx_sw_attr_globals),
2455         },
2456         .attr_port = {
2457                 .attr = ar8xxx_sw_attr_port,
2458                 .n_attr = ARRAY_SIZE(ar8xxx_sw_attr_port),
2459         },
2460         .attr_vlan = {
2461                 .attr = ar8xxx_sw_attr_vlan,
2462                 .n_attr = ARRAY_SIZE(ar8xxx_sw_attr_vlan),
2463         },
2464         .get_port_pvid = ar8xxx_sw_get_pvid,
2465         .set_port_pvid = ar8xxx_sw_set_pvid,
2466         .get_vlan_ports = ar8xxx_sw_get_ports,
2467         .set_vlan_ports = ar8xxx_sw_set_ports,
2468         .apply_config = ar8xxx_sw_hw_apply,
2469         .reset_switch = ar8xxx_sw_reset_switch,
2470         .get_port_link = ar8xxx_sw_get_port_link,
2471 };
2472
2473 static const struct switch_dev_ops ar8327_sw_ops = {
2474         .attr_global = {
2475                 .attr = ar8327_sw_attr_globals,
2476                 .n_attr = ARRAY_SIZE(ar8327_sw_attr_globals),
2477         },
2478         .attr_port = {
2479                 .attr = ar8xxx_sw_attr_port,
2480                 .n_attr = ARRAY_SIZE(ar8xxx_sw_attr_port),
2481         },
2482         .attr_vlan = {
2483                 .attr = ar8xxx_sw_attr_vlan,
2484                 .n_attr = ARRAY_SIZE(ar8xxx_sw_attr_vlan),
2485         },
2486         .get_port_pvid = ar8xxx_sw_get_pvid,
2487         .set_port_pvid = ar8xxx_sw_set_pvid,
2488         .get_vlan_ports = ar8327_sw_get_ports,
2489         .set_vlan_ports = ar8327_sw_set_ports,
2490         .apply_config = ar8xxx_sw_hw_apply,
2491         .reset_switch = ar8xxx_sw_reset_switch,
2492         .get_port_link = ar8xxx_sw_get_port_link,
2493 };
2494
2495 static const struct ar8xxx_chip ar8216_chip = {
2496         .caps = AR8XXX_CAP_MIB_COUNTERS,
2497
2498         .reg_port_stats_start = 0x19000,
2499         .reg_port_stats_length = 0xa0,
2500
2501         .name = "Atheros AR8216",
2502         .ports = AR8216_NUM_PORTS,
2503         .vlans = AR8216_NUM_VLANS,
2504         .swops = &ar8xxx_sw_ops,
2505
2506         .hw_init = ar8216_hw_init,
2507         .init_globals = ar8216_init_globals,
2508         .init_port = ar8216_init_port,
2509         .setup_port = ar8216_setup_port,
2510         .read_port_status = ar8216_read_port_status,
2511         .atu_flush = ar8216_atu_flush,
2512         .vtu_flush = ar8216_vtu_flush,
2513         .vtu_load_vlan = ar8216_vtu_load_vlan,
2514         .set_mirror_regs = ar8216_set_mirror_regs,
2515
2516         .num_mibs = ARRAY_SIZE(ar8216_mibs),
2517         .mib_decs = ar8216_mibs,
2518         .mib_func = AR8216_REG_MIB_FUNC
2519 };
2520
2521 static const struct ar8xxx_chip ar8236_chip = {
2522         .caps = AR8XXX_CAP_MIB_COUNTERS,
2523
2524         .reg_port_stats_start = 0x20000,
2525         .reg_port_stats_length = 0x100,
2526
2527         .name = "Atheros AR8236",
2528         .ports = AR8216_NUM_PORTS,
2529         .vlans = AR8216_NUM_VLANS,
2530         .swops = &ar8xxx_sw_ops,
2531
2532         .hw_init = ar8216_hw_init,
2533         .init_globals = ar8236_init_globals,
2534         .init_port = ar8216_init_port,
2535         .setup_port = ar8236_setup_port,
2536         .read_port_status = ar8216_read_port_status,
2537         .atu_flush = ar8216_atu_flush,
2538         .vtu_flush = ar8216_vtu_flush,
2539         .vtu_load_vlan = ar8216_vtu_load_vlan,
2540         .set_mirror_regs = ar8216_set_mirror_regs,
2541
2542         .num_mibs = ARRAY_SIZE(ar8236_mibs),
2543         .mib_decs = ar8236_mibs,
2544         .mib_func = AR8216_REG_MIB_FUNC
2545 };
2546
2547 static const struct ar8xxx_chip ar8316_chip = {
2548         .caps = AR8XXX_CAP_GIGE | AR8XXX_CAP_MIB_COUNTERS,
2549
2550         .reg_port_stats_start = 0x20000,
2551         .reg_port_stats_length = 0x100,
2552
2553         .name = "Atheros AR8316",
2554         .ports = AR8216_NUM_PORTS,
2555         .vlans = AR8X16_MAX_VLANS,
2556         .swops = &ar8xxx_sw_ops,
2557
2558         .hw_init = ar8316_hw_init,
2559         .init_globals = ar8316_init_globals,
2560         .init_port = ar8216_init_port,
2561         .setup_port = ar8216_setup_port,
2562         .read_port_status = ar8216_read_port_status,
2563         .atu_flush = ar8216_atu_flush,
2564         .vtu_flush = ar8216_vtu_flush,
2565         .vtu_load_vlan = ar8216_vtu_load_vlan,
2566         .set_mirror_regs = ar8216_set_mirror_regs,
2567
2568         .num_mibs = ARRAY_SIZE(ar8236_mibs),
2569         .mib_decs = ar8236_mibs,
2570         .mib_func = AR8216_REG_MIB_FUNC
2571 };
2572
2573 static const struct ar8xxx_chip ar8327_chip = {
2574         .caps = AR8XXX_CAP_GIGE | AR8XXX_CAP_MIB_COUNTERS,
2575         .config_at_probe = true,
2576         .mii_lo_first = true,
2577
2578         .name = "Atheros AR8327",
2579         .ports = AR8327_NUM_PORTS,
2580         .vlans = AR8X16_MAX_VLANS,
2581         .swops = &ar8327_sw_ops,
2582
2583         .reg_port_stats_start = 0x1000,
2584         .reg_port_stats_length = 0x100,
2585
2586         .hw_init = ar8327_hw_init,
2587         .cleanup = ar8327_cleanup,
2588         .init_globals = ar8327_init_globals,
2589         .init_port = ar8327_init_port,
2590         .setup_port = ar8327_setup_port,
2591         .read_port_status = ar8327_read_port_status,
2592         .atu_flush = ar8327_atu_flush,
2593         .vtu_flush = ar8327_vtu_flush,
2594         .vtu_load_vlan = ar8327_vtu_load_vlan,
2595         .phy_fixup = ar8327_phy_fixup,
2596         .set_mirror_regs = ar8327_set_mirror_regs,
2597
2598         .num_mibs = ARRAY_SIZE(ar8236_mibs),
2599         .mib_decs = ar8236_mibs,
2600         .mib_func = AR8327_REG_MIB_FUNC
2601 };
2602
2603 static const struct ar8xxx_chip ar8337_chip = {
2604         .caps = AR8XXX_CAP_GIGE | AR8XXX_CAP_MIB_COUNTERS,
2605         .config_at_probe = true,
2606         .mii_lo_first = true,
2607
2608         .name = "Atheros AR8337",
2609         .ports = AR8327_NUM_PORTS,
2610         .vlans = AR8X16_MAX_VLANS,
2611         .swops = &ar8327_sw_ops,
2612
2613         .reg_port_stats_start = 0x1000,
2614         .reg_port_stats_length = 0x100,
2615
2616         .hw_init = ar8327_hw_init,
2617         .cleanup = ar8327_cleanup,
2618         .init_globals = ar8327_init_globals,
2619         .init_port = ar8327_init_port,
2620         .setup_port = ar8327_setup_port,
2621         .read_port_status = ar8327_read_port_status,
2622         .atu_flush = ar8327_atu_flush,
2623         .vtu_flush = ar8327_vtu_flush,
2624         .vtu_load_vlan = ar8327_vtu_load_vlan,
2625         .phy_fixup = ar8327_phy_fixup,
2626         .set_mirror_regs = ar8327_set_mirror_regs,
2627
2628         .num_mibs = ARRAY_SIZE(ar8236_mibs),
2629         .mib_decs = ar8236_mibs,
2630         .mib_func = AR8327_REG_MIB_FUNC
2631 };
2632
2633 static int
2634 ar8xxx_id_chip(struct ar8xxx_priv *priv)
2635 {
2636         u32 val;
2637         u16 id;
2638         int i;
2639
2640         val = ar8xxx_read(priv, AR8216_REG_CTRL);
2641         if (val == ~0)
2642                 return -ENODEV;
2643
2644         id = val & (AR8216_CTRL_REVISION | AR8216_CTRL_VERSION);
2645         for (i = 0; i < AR8X16_PROBE_RETRIES; i++) {
2646                 u16 t;
2647
2648                 val = ar8xxx_read(priv, AR8216_REG_CTRL);
2649                 if (val == ~0)
2650                         return -ENODEV;
2651
2652                 t = val & (AR8216_CTRL_REVISION | AR8216_CTRL_VERSION);
2653                 if (t != id)
2654                         return -ENODEV;
2655         }
2656
2657         priv->chip_ver = (id & AR8216_CTRL_VERSION) >> AR8216_CTRL_VERSION_S;
2658         priv->chip_rev = (id & AR8216_CTRL_REVISION);
2659
2660         switch (priv->chip_ver) {
2661         case AR8XXX_VER_AR8216:
2662                 priv->chip = &ar8216_chip;
2663                 break;
2664         case AR8XXX_VER_AR8236:
2665                 priv->chip = &ar8236_chip;
2666                 break;
2667         case AR8XXX_VER_AR8316:
2668                 priv->chip = &ar8316_chip;
2669                 break;
2670         case AR8XXX_VER_AR8327:
2671                 priv->chip = &ar8327_chip;
2672                 break;
2673         case AR8XXX_VER_AR8337:
2674                 priv->chip = &ar8337_chip;
2675                 break;
2676         default:
2677                 pr_err("ar8216: Unknown Atheros device [ver=%d, rev=%d]\n",
2678                        priv->chip_ver, priv->chip_rev);
2679
2680                 return -ENODEV;
2681         }
2682
2683         return 0;
2684 }
2685
2686 static void
2687 ar8xxx_mib_work_func(struct work_struct *work)
2688 {
2689         struct ar8xxx_priv *priv;
2690         int err;
2691
2692         priv = container_of(work, struct ar8xxx_priv, mib_work.work);
2693
2694         mutex_lock(&priv->mib_lock);
2695
2696         err = ar8xxx_mib_capture(priv);
2697         if (err)
2698                 goto next_port;
2699
2700         ar8xxx_mib_fetch_port_stat(priv, priv->mib_next_port, false);
2701
2702 next_port:
2703         priv->mib_next_port++;
2704         if (priv->mib_next_port >= priv->dev.ports)
2705                 priv->mib_next_port = 0;
2706
2707         mutex_unlock(&priv->mib_lock);
2708         schedule_delayed_work(&priv->mib_work,
2709                               msecs_to_jiffies(AR8XXX_MIB_WORK_DELAY));
2710 }
2711
2712 static int
2713 ar8xxx_mib_init(struct ar8xxx_priv *priv)
2714 {
2715         unsigned int len;
2716
2717         if (!ar8xxx_has_mib_counters(priv))
2718                 return 0;
2719
2720         BUG_ON(!priv->chip->mib_decs || !priv->chip->num_mibs);
2721
2722         len = priv->dev.ports * priv->chip->num_mibs *
2723               sizeof(*priv->mib_stats);
2724         priv->mib_stats = kzalloc(len, GFP_KERNEL);
2725
2726         if (!priv->mib_stats)
2727                 return -ENOMEM;
2728
2729         return 0;
2730 }
2731
2732 static void
2733 ar8xxx_mib_start(struct ar8xxx_priv *priv)
2734 {
2735         if (!ar8xxx_has_mib_counters(priv))
2736                 return;
2737
2738         schedule_delayed_work(&priv->mib_work,
2739                               msecs_to_jiffies(AR8XXX_MIB_WORK_DELAY));
2740 }
2741
2742 static void
2743 ar8xxx_mib_stop(struct ar8xxx_priv *priv)
2744 {
2745         if (!ar8xxx_has_mib_counters(priv))
2746                 return;
2747
2748         cancel_delayed_work(&priv->mib_work);
2749 }
2750
2751 static struct ar8xxx_priv *
2752 ar8xxx_create(void)
2753 {
2754         struct ar8xxx_priv *priv;
2755
2756         priv = kzalloc(sizeof(struct ar8xxx_priv), GFP_KERNEL);
2757         if (priv == NULL)
2758                 return NULL;
2759
2760         mutex_init(&priv->reg_mutex);
2761         mutex_init(&priv->mib_lock);
2762         INIT_DELAYED_WORK(&priv->mib_work, ar8xxx_mib_work_func);
2763
2764         return priv;
2765 }
2766
2767 static void
2768 ar8xxx_free(struct ar8xxx_priv *priv)
2769 {
2770         if (priv->chip && priv->chip->cleanup)
2771                 priv->chip->cleanup(priv);
2772
2773         kfree(priv->chip_data);
2774         kfree(priv->mib_stats);
2775         kfree(priv);
2776 }
2777
2778 static struct ar8xxx_priv *
2779 ar8xxx_create_mii(struct mii_bus *bus)
2780 {
2781         struct ar8xxx_priv *priv;
2782
2783         priv = ar8xxx_create();
2784         if (priv)
2785                 priv->mii_bus = bus;
2786
2787         return priv;
2788 }
2789
2790 static int
2791 ar8xxx_probe_switch(struct ar8xxx_priv *priv)
2792 {
2793         const struct ar8xxx_chip *chip;
2794         struct switch_dev *swdev;
2795         int ret;
2796
2797         ret = ar8xxx_id_chip(priv);
2798         if (ret)
2799                 return ret;
2800
2801         chip = priv->chip;
2802
2803         swdev = &priv->dev;
2804         swdev->cpu_port = AR8216_PORT_CPU;
2805         swdev->name = chip->name;
2806         swdev->vlans = chip->vlans;
2807         swdev->ports = chip->ports;
2808         swdev->ops = chip->swops;
2809
2810         ret = ar8xxx_mib_init(priv);
2811         if (ret)
2812                 return ret;
2813
2814         return 0;
2815 }
2816
2817 static int
2818 ar8xxx_start(struct ar8xxx_priv *priv)
2819 {
2820         int ret;
2821
2822         priv->init = true;
2823
2824         ret = priv->chip->hw_init(priv);
2825         if (ret)
2826                 return ret;
2827
2828         ret = ar8xxx_sw_reset_switch(&priv->dev);
2829         if (ret)
2830                 return ret;
2831
2832         priv->init = false;
2833
2834         ar8xxx_mib_start(priv);
2835
2836         return 0;
2837 }
2838
2839 static int
2840 ar8xxx_phy_config_init(struct phy_device *phydev)
2841 {
2842         struct ar8xxx_priv *priv = phydev->priv;
2843         struct net_device *dev = phydev->attached_dev;
2844         int ret;
2845
2846         if (WARN_ON(!priv))
2847                 return -ENODEV;
2848
2849         if (priv->chip->config_at_probe)
2850                 return ar8xxx_phy_check_aneg(phydev);
2851
2852         priv->phy = phydev;
2853
2854         if (phydev->addr != 0) {
2855                 if (chip_is_ar8316(priv)) {
2856                         /* switch device has been initialized, reinit */
2857                         priv->dev.ports = (AR8216_NUM_PORTS - 1);
2858                         priv->initialized = false;
2859                         priv->port4_phy = true;
2860                         ar8316_hw_init(priv);
2861                         return 0;
2862                 }
2863
2864                 return 0;
2865         }
2866
2867         ret = ar8xxx_start(priv);
2868         if (ret)
2869                 return ret;
2870
2871         /* VID fixup only needed on ar8216 */
2872         if (chip_is_ar8216(priv)) {
2873                 dev->phy_ptr = priv;
2874                 dev->priv_flags |= IFF_NO_IP_ALIGN;
2875                 dev->eth_mangle_rx = ar8216_mangle_rx;
2876                 dev->eth_mangle_tx = ar8216_mangle_tx;
2877         }
2878
2879         return 0;
2880 }
2881
2882 static int
2883 ar8xxx_phy_read_status(struct phy_device *phydev)
2884 {
2885         struct ar8xxx_priv *priv = phydev->priv;
2886         struct switch_port_link link;
2887         int ret;
2888
2889         if (phydev->addr != 0)
2890                 return genphy_read_status(phydev);
2891
2892         ar8216_read_port_link(priv, phydev->addr, &link);
2893         phydev->link = !!link.link;
2894         if (!phydev->link)
2895                 return 0;
2896
2897         switch (link.speed) {
2898         case SWITCH_PORT_SPEED_10:
2899                 phydev->speed = SPEED_10;
2900                 break;
2901         case SWITCH_PORT_SPEED_100:
2902                 phydev->speed = SPEED_100;
2903                 break;
2904         case SWITCH_PORT_SPEED_1000:
2905                 phydev->speed = SPEED_1000;
2906                 break;
2907         default:
2908                 phydev->speed = 0;
2909         }
2910         phydev->duplex = link.duplex ? DUPLEX_FULL : DUPLEX_HALF;
2911
2912         /* flush the address translation unit */
2913         mutex_lock(&priv->reg_mutex);
2914         ret = priv->chip->atu_flush(priv);
2915         mutex_unlock(&priv->reg_mutex);
2916
2917         phydev->state = PHY_RUNNING;
2918         netif_carrier_on(phydev->attached_dev);
2919         phydev->adjust_link(phydev->attached_dev);
2920
2921         return ret;
2922 }
2923
2924 static int
2925 ar8xxx_phy_config_aneg(struct phy_device *phydev)
2926 {
2927         if (phydev->addr == 0)
2928                 return 0;
2929
2930         return genphy_config_aneg(phydev);
2931 }
2932
2933 static const u32 ar8xxx_phy_ids[] = {
2934         0x004dd033,
2935         0x004dd034, /* AR8327 */
2936         0x004dd036, /* AR8337 */
2937         0x004dd041,
2938         0x004dd042,
2939         0x004dd043, /* AR8236 */
2940 };
2941
2942 static bool
2943 ar8xxx_phy_match(u32 phy_id)
2944 {
2945         int i;
2946
2947         for (i = 0; i < ARRAY_SIZE(ar8xxx_phy_ids); i++)
2948                 if (phy_id == ar8xxx_phy_ids[i])
2949                         return true;
2950
2951         return false;
2952 }
2953
2954 static bool
2955 ar8xxx_is_possible(struct mii_bus *bus)
2956 {
2957         unsigned i;
2958
2959         for (i = 0; i < 4; i++) {
2960                 u32 phy_id;
2961
2962                 phy_id = mdiobus_read(bus, i, MII_PHYSID1) << 16;
2963                 phy_id |= mdiobus_read(bus, i, MII_PHYSID2);
2964                 if (!ar8xxx_phy_match(phy_id)) {
2965                         pr_debug("ar8xxx: unknown PHY at %s:%02x id:%08x\n",
2966                                  dev_name(&bus->dev), i, phy_id);
2967                         return false;
2968                 }
2969         }
2970
2971         return true;
2972 }
2973
2974 static int
2975 ar8xxx_phy_probe(struct phy_device *phydev)
2976 {
2977         struct ar8xxx_priv *priv;
2978         struct switch_dev *swdev;
2979         int ret;
2980
2981         /* skip PHYs at unused adresses */
2982         if (phydev->addr != 0 && phydev->addr != 4)
2983                 return -ENODEV;
2984
2985         if (!ar8xxx_is_possible(phydev->bus))
2986                 return -ENODEV;
2987
2988         mutex_lock(&ar8xxx_dev_list_lock);
2989         list_for_each_entry(priv, &ar8xxx_dev_list, list)
2990                 if (priv->mii_bus == phydev->bus)
2991                         goto found;
2992
2993         priv = ar8xxx_create_mii(phydev->bus);
2994         if (priv == NULL) {
2995                 ret = -ENOMEM;
2996                 goto unlock;
2997         }
2998
2999         ret = ar8xxx_probe_switch(priv);
3000         if (ret)
3001                 goto free_priv;
3002
3003         swdev = &priv->dev;
3004         swdev->alias = dev_name(&priv->mii_bus->dev);
3005         ret = register_switch(swdev, NULL);
3006         if (ret)
3007                 goto free_priv;
3008
3009         pr_info("%s: %s rev. %u switch registered on %s\n",
3010                 swdev->devname, swdev->name, priv->chip_rev,
3011                 dev_name(&priv->mii_bus->dev));
3012
3013 found:
3014         priv->use_count++;
3015
3016         if (phydev->addr == 0) {
3017                 if (ar8xxx_has_gige(priv)) {
3018                         phydev->supported = SUPPORTED_1000baseT_Full;
3019                         phydev->advertising = ADVERTISED_1000baseT_Full;
3020                 } else {
3021                         phydev->supported = SUPPORTED_100baseT_Full;
3022                         phydev->advertising = ADVERTISED_100baseT_Full;
3023                 }
3024
3025                 if (priv->chip->config_at_probe) {
3026                         priv->phy = phydev;
3027
3028                         ret = ar8xxx_start(priv);
3029                         if (ret)
3030                                 goto err_unregister_switch;
3031                 }
3032         } else {
3033                 if (ar8xxx_has_gige(priv)) {
3034                         phydev->supported |= SUPPORTED_1000baseT_Full;
3035                         phydev->advertising |= ADVERTISED_1000baseT_Full;
3036                 }
3037         }
3038
3039         phydev->priv = priv;
3040
3041         list_add(&priv->list, &ar8xxx_dev_list);
3042
3043         mutex_unlock(&ar8xxx_dev_list_lock);
3044
3045         return 0;
3046
3047 err_unregister_switch:
3048         if (--priv->use_count)
3049                 goto unlock;
3050
3051         unregister_switch(&priv->dev);
3052
3053 free_priv:
3054         ar8xxx_free(priv);
3055 unlock:
3056         mutex_unlock(&ar8xxx_dev_list_lock);
3057         return ret;
3058 }
3059
3060 static void
3061 ar8xxx_phy_detach(struct phy_device *phydev)
3062 {
3063         struct net_device *dev = phydev->attached_dev;
3064
3065         if (!dev)
3066                 return;
3067
3068         dev->phy_ptr = NULL;
3069         dev->priv_flags &= ~IFF_NO_IP_ALIGN;
3070         dev->eth_mangle_rx = NULL;
3071         dev->eth_mangle_tx = NULL;
3072 }
3073
3074 static void
3075 ar8xxx_phy_remove(struct phy_device *phydev)
3076 {
3077         struct ar8xxx_priv *priv = phydev->priv;
3078
3079         if (WARN_ON(!priv))
3080                 return;
3081
3082         phydev->priv = NULL;
3083         if (--priv->use_count > 0)
3084                 return;
3085
3086         mutex_lock(&ar8xxx_dev_list_lock);
3087         list_del(&priv->list);
3088         mutex_unlock(&ar8xxx_dev_list_lock);
3089
3090         unregister_switch(&priv->dev);
3091         ar8xxx_mib_stop(priv);
3092         ar8xxx_free(priv);
3093 }
3094
3095 #if LINUX_VERSION_CODE >= KERNEL_VERSION(3,14,0)
3096 static int
3097 ar8xxx_phy_soft_reset(struct phy_device *phydev)
3098 {
3099         /* we don't need an extra reset */
3100         return 0;
3101 }
3102 #endif
3103
3104 static struct phy_driver ar8xxx_phy_driver = {
3105         .phy_id         = 0x004d0000,
3106         .name           = "Atheros AR8216/AR8236/AR8316",
3107         .phy_id_mask    = 0xffff0000,
3108         .features       = PHY_BASIC_FEATURES,
3109         .probe          = ar8xxx_phy_probe,
3110         .remove         = ar8xxx_phy_remove,
3111         .detach         = ar8xxx_phy_detach,
3112         .config_init    = ar8xxx_phy_config_init,
3113         .config_aneg    = ar8xxx_phy_config_aneg,
3114         .read_status    = ar8xxx_phy_read_status,
3115 #if LINUX_VERSION_CODE >= KERNEL_VERSION(3,14,0)
3116         .soft_reset     = ar8xxx_phy_soft_reset,
3117 #endif
3118         .driver         = { .owner = THIS_MODULE },
3119 };
3120
3121 int __init
3122 ar8xxx_init(void)
3123 {
3124         return phy_driver_register(&ar8xxx_phy_driver);
3125 }
3126
3127 void __exit
3128 ar8xxx_exit(void)
3129 {
3130         phy_driver_unregister(&ar8xxx_phy_driver);
3131 }
3132
3133 module_init(ar8xxx_init);
3134 module_exit(ar8xxx_exit);
3135 MODULE_LICENSE("GPL");
3136