target/linux/generic/files/drivers/net/phy/ar8216.c

   1 /*
   2  * ar8216.c: AR8216 switch driver
   3  *
   4  * Copyright (C) 2009 Felix Fietkau <nbd@openwrt.org>
   5  * Copyright (C) 2011-2012 Gabor Juhos <juhosg@openwrt.org>
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License
   9  * as published by the Free Software Foundation; either version 2
  10  * of the License, or (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  */
  17
  18 #include <linux/if.h>
  19 #include <linux/module.h>
  20 #include <linux/init.h>
  21 #include <linux/list.h>
  22 #include <linux/if_ether.h>
  23 #include <linux/skbuff.h>
  24 #include <linux/netdevice.h>
  25 #include <linux/netlink.h>
  26 #include <linux/bitops.h>
  27 #include <net/genetlink.h>
  28 #include <linux/switch.h>
  29 #include <linux/delay.h>
  30 #include <linux/phy.h>
  31 #include <linux/netdevice.h>
  32 #include <linux/etherdevice.h>
  33 #include <linux/lockdep.h>
  34 #include <linux/ar8216_platform.h>
  35 #include <linux/workqueue.h>
  36 #include <linux/of_device.h>
  37 #include <linux/leds.h>
  38 #include <linux/gpio.h>
  39 #include <linux/version.h>
  40
  41 #include "ar8216.h"
  42
  43 /* size of the vlan table */
  44 #define AR8X16_MAX_VLANS        128
  45 #define AR8X16_PROBE_RETRIES    10
  46 #define AR8X16_MAX_PORTS        8
  47
  48 #define AR8XXX_MIB_WORK_DELAY   2000 /* msecs */
  49
  50 struct ar8xxx_priv;
  51
  52 #define AR8XXX_CAP_GIGE                 BIT(0)
  53 #define AR8XXX_CAP_MIB_COUNTERS         BIT(1)
  54
  55 #define AR8XXX_NUM_PHYS         5
  56
  57 static void ar8216_set_mirror_regs(struct ar8xxx_priv *priv);
  58 static void ar8327_set_mirror_regs(struct ar8xxx_priv *priv);
  59
  60 enum {
  61         AR8XXX_VER_AR8216 = 0x01,
  62         AR8XXX_VER_AR8236 = 0x03,
  63         AR8XXX_VER_AR8316 = 0x10,
  64         AR8XXX_VER_AR8327 = 0x12,
  65         AR8XXX_VER_AR8337 = 0x13,
  66 };
  67
  68 struct ar8xxx_mib_desc {
  69         unsigned int size;
  70         unsigned int offset;
  71         const char *name;
  72 };
  73
  74 struct ar8xxx_chip {
  75         unsigned long caps;
  76         bool config_at_probe;
  77         bool mii_lo_first;
  78
  79         /* parameters to calculate REG_PORT_STATS_BASE */
  80         unsigned reg_port_stats_start;
  81         unsigned reg_port_stats_length;
  82
  83         int (*hw_init)(struct ar8xxx_priv *priv);
  84         void (*cleanup)(struct ar8xxx_priv *priv);
  85
  86         void (*init_globals)(struct ar8xxx_priv *priv);
  87         void (*init_port)(struct ar8xxx_priv *priv, int port);
  88         void (*setup_port)(struct ar8xxx_priv *priv, int port, u32 members);
  89         u32 (*read_port_status)(struct ar8xxx_priv *priv, int port);
  90         int (*atu_flush)(struct ar8xxx_priv *priv);
  91         void (*vtu_flush)(struct ar8xxx_priv *priv);
  92         void (*vtu_load_vlan)(struct ar8xxx_priv *priv, u32 vid, u32 port_mask);
  93         void (*phy_fixup)(struct ar8xxx_priv *priv, int phy);
  94         void (*set_mirror_regs)(struct ar8xxx_priv *priv);
  95
  96         const struct ar8xxx_mib_desc *mib_decs;
  97         unsigned num_mibs;
  98         unsigned mib_func;
  99 };
 100
 101 enum ar8327_led_pattern {
 102         AR8327_LED_PATTERN_OFF = 0,
 103         AR8327_LED_PATTERN_BLINK,
 104         AR8327_LED_PATTERN_ON,
 105         AR8327_LED_PATTERN_RULE,
 106 };
 107
 108 struct ar8327_led_entry {
 109         unsigned reg;
 110         unsigned shift;
 111 };
 112
 113 struct ar8327_led {
 114         struct led_classdev cdev;
 115         struct ar8xxx_priv *sw_priv;
 116
 117         char *name;
 118         bool active_low;
 119         u8 led_num;
 120         enum ar8327_led_mode mode;
 121
 122         struct mutex mutex;
 123         spinlock_t lock;
 124         struct work_struct led_work;
 125         bool enable_hw_mode;
 126         enum ar8327_led_pattern pattern;
 127 };
 128
 129 struct ar8327_data {
 130         u32 port0_status;
 131         u32 port6_status;
 132
 133         struct ar8327_led **leds;
 134         unsigned int num_leds;
 135 };
 136
 137 struct ar8xxx_priv {
 138         struct switch_dev dev;
 139         struct mii_bus *mii_bus;
 140         struct phy_device *phy;
 141
 142         u32 (*read)(struct ar8xxx_priv *priv, int reg);
 143         void (*write)(struct ar8xxx_priv *priv, int reg, u32 val);
 144         u32 (*rmw)(struct ar8xxx_priv *priv, int reg, u32 mask, u32 val);
 145
 146         int (*get_port_link)(unsigned port);
 147
 148         const struct net_device_ops *ndo_old;
 149         struct net_device_ops ndo;
 150         struct mutex reg_mutex;
 151         u8 chip_ver;
 152         u8 chip_rev;
 153         const struct ar8xxx_chip *chip;
 154         void *chip_data;
 155         bool initialized;
 156         bool port4_phy;
 157         char buf[2048];
 158
 159         bool init;
 160
 161         struct mutex mib_lock;
 162         struct delayed_work mib_work;
 163         int mib_next_port;
 164         u64 *mib_stats;
 165
 166         struct list_head list;
 167         unsigned int use_count;
 168
 169         /* all fields below are cleared on reset */
 170         bool vlan;
 171         u16 vlan_id[AR8X16_MAX_VLANS];
 172         u8 vlan_table[AR8X16_MAX_VLANS];
 173         u8 vlan_tagged;
 174         u16 pvid[AR8X16_MAX_PORTS];
 175
 176         /* mirroring */
 177         bool mirror_rx;
 178         bool mirror_tx;
 179         int source_port;
 180         int monitor_port;
 181 };
 182
 183 #define MIB_DESC(_s , _o, _n)   \
 184         {                       \
 185                 .size = (_s),   \
 186                 .offset = (_o), \
 187                 .name = (_n),   \
 188         }
 189
 190 static const struct ar8xxx_mib_desc ar8216_mibs[] = {
 191         MIB_DESC(1, AR8216_STATS_RXBROAD, "RxBroad"),
 192         MIB_DESC(1, AR8216_STATS_RXPAUSE, "RxPause"),
 193         MIB_DESC(1, AR8216_STATS_RXMULTI, "RxMulti"),
 194         MIB_DESC(1, AR8216_STATS_RXFCSERR, "RxFcsErr"),
 195         MIB_DESC(1, AR8216_STATS_RXALIGNERR, "RxAlignErr"),
 196         MIB_DESC(1, AR8216_STATS_RXRUNT, "RxRunt"),
 197         MIB_DESC(1, AR8216_STATS_RXFRAGMENT, "RxFragment"),
 198         MIB_DESC(1, AR8216_STATS_RX64BYTE, "Rx64Byte"),
 199         MIB_DESC(1, AR8216_STATS_RX128BYTE, "Rx128Byte"),
 200         MIB_DESC(1, AR8216_STATS_RX256BYTE, "Rx256Byte"),
 201         MIB_DESC(1, AR8216_STATS_RX512BYTE, "Rx512Byte"),
 202         MIB_DESC(1, AR8216_STATS_RX1024BYTE, "Rx1024Byte"),
 203         MIB_DESC(1, AR8216_STATS_RXMAXBYTE, "RxMaxByte"),
 204         MIB_DESC(1, AR8216_STATS_RXTOOLONG, "RxTooLong"),
 205         MIB_DESC(2, AR8216_STATS_RXGOODBYTE, "RxGoodByte"),
 206         MIB_DESC(2, AR8216_STATS_RXBADBYTE, "RxBadByte"),
 207         MIB_DESC(1, AR8216_STATS_RXOVERFLOW, "RxOverFlow"),
 208         MIB_DESC(1, AR8216_STATS_FILTERED, "Filtered"),
 209         MIB_DESC(1, AR8216_STATS_TXBROAD, "TxBroad"),
 210         MIB_DESC(1, AR8216_STATS_TXPAUSE, "TxPause"),
 211         MIB_DESC(1, AR8216_STATS_TXMULTI, "TxMulti"),
 212         MIB_DESC(1, AR8216_STATS_TXUNDERRUN, "TxUnderRun"),
 213         MIB_DESC(1, AR8216_STATS_TX64BYTE, "Tx64Byte"),
 214         MIB_DESC(1, AR8216_STATS_TX128BYTE, "Tx128Byte"),
 215         MIB_DESC(1, AR8216_STATS_TX256BYTE, "Tx256Byte"),
 216         MIB_DESC(1, AR8216_STATS_TX512BYTE, "Tx512Byte"),
 217         MIB_DESC(1, AR8216_STATS_TX1024BYTE, "Tx1024Byte"),
 218         MIB_DESC(1, AR8216_STATS_TXMAXBYTE, "TxMaxByte"),
 219         MIB_DESC(1, AR8216_STATS_TXOVERSIZE, "TxOverSize"),
 220         MIB_DESC(2, AR8216_STATS_TXBYTE, "TxByte"),
 221         MIB_DESC(1, AR8216_STATS_TXCOLLISION, "TxCollision"),
 222         MIB_DESC(1, AR8216_STATS_TXABORTCOL, "TxAbortCol"),
 223         MIB_DESC(1, AR8216_STATS_TXMULTICOL, "TxMultiCol"),
 224         MIB_DESC(1, AR8216_STATS_TXSINGLECOL, "TxSingleCol"),
 225         MIB_DESC(1, AR8216_STATS_TXEXCDEFER, "TxExcDefer"),
 226         MIB_DESC(1, AR8216_STATS_TXDEFER, "TxDefer"),
 227         MIB_DESC(1, AR8216_STATS_TXLATECOL, "TxLateCol"),
 228 };
 229
 230 static const struct ar8xxx_mib_desc ar8236_mibs[] = {
 231         MIB_DESC(1, AR8236_STATS_RXBROAD, "RxBroad"),
 232         MIB_DESC(1, AR8236_STATS_RXPAUSE, "RxPause"),
 233         MIB_DESC(1, AR8236_STATS_RXMULTI, "RxMulti"),
 234         MIB_DESC(1, AR8236_STATS_RXFCSERR, "RxFcsErr"),
 235         MIB_DESC(1, AR8236_STATS_RXALIGNERR, "RxAlignErr"),
 236         MIB_DESC(1, AR8236_STATS_RXRUNT, "RxRunt"),
 237         MIB_DESC(1, AR8236_STATS_RXFRAGMENT, "RxFragment"),
 238         MIB_DESC(1, AR8236_STATS_RX64BYTE, "Rx64Byte"),
 239         MIB_DESC(1, AR8236_STATS_RX128BYTE, "Rx128Byte"),
 240         MIB_DESC(1, AR8236_STATS_RX256BYTE, "Rx256Byte"),
 241         MIB_DESC(1, AR8236_STATS_RX512BYTE, "Rx512Byte"),
 242         MIB_DESC(1, AR8236_STATS_RX1024BYTE, "Rx1024Byte"),
 243         MIB_DESC(1, AR8236_STATS_RX1518BYTE, "Rx1518Byte"),
 244         MIB_DESC(1, AR8236_STATS_RXMAXBYTE, "RxMaxByte"),
 245         MIB_DESC(1, AR8236_STATS_RXTOOLONG, "RxTooLong"),
 246         MIB_DESC(2, AR8236_STATS_RXGOODBYTE, "RxGoodByte"),
 247         MIB_DESC(2, AR8236_STATS_RXBADBYTE, "RxBadByte"),
 248         MIB_DESC(1, AR8236_STATS_RXOVERFLOW, "RxOverFlow"),
 249         MIB_DESC(1, AR8236_STATS_FILTERED, "Filtered"),
 250         MIB_DESC(1, AR8236_STATS_TXBROAD, "TxBroad"),
 251         MIB_DESC(1, AR8236_STATS_TXPAUSE, "TxPause"),
 252         MIB_DESC(1, AR8236_STATS_TXMULTI, "TxMulti"),
 253         MIB_DESC(1, AR8236_STATS_TXUNDERRUN, "TxUnderRun"),
 254         MIB_DESC(1, AR8236_STATS_TX64BYTE, "Tx64Byte"),
 255         MIB_DESC(1, AR8236_STATS_TX128BYTE, "Tx128Byte"),
 256         MIB_DESC(1, AR8236_STATS_TX256BYTE, "Tx256Byte"),
 257         MIB_DESC(1, AR8236_STATS_TX512BYTE, "Tx512Byte"),
 258         MIB_DESC(1, AR8236_STATS_TX1024BYTE, "Tx1024Byte"),
 259         MIB_DESC(1, AR8236_STATS_TX1518BYTE, "Tx1518Byte"),
 260         MIB_DESC(1, AR8236_STATS_TXMAXBYTE, "TxMaxByte"),
 261         MIB_DESC(1, AR8236_STATS_TXOVERSIZE, "TxOverSize"),
 262         MIB_DESC(2, AR8236_STATS_TXBYTE, "TxByte"),
 263         MIB_DESC(1, AR8236_STATS_TXCOLLISION, "TxCollision"),
 264         MIB_DESC(1, AR8236_STATS_TXABORTCOL, "TxAbortCol"),
 265         MIB_DESC(1, AR8236_STATS_TXMULTICOL, "TxMultiCol"),
 266         MIB_DESC(1, AR8236_STATS_TXSINGLECOL, "TxSingleCol"),
 267         MIB_DESC(1, AR8236_STATS_TXEXCDEFER, "TxExcDefer"),
 268         MIB_DESC(1, AR8236_STATS_TXDEFER, "TxDefer"),
 269         MIB_DESC(1, AR8236_STATS_TXLATECOL, "TxLateCol"),
 270 };
 271
 272 static DEFINE_MUTEX(ar8xxx_dev_list_lock);
 273 static LIST_HEAD(ar8xxx_dev_list);
 274
 275 static inline struct ar8xxx_priv *
 276 swdev_to_ar8xxx(struct switch_dev *swdev)
 277 {
 278         return container_of(swdev, struct ar8xxx_priv, dev);
 279 }
 280
 281 static inline bool ar8xxx_has_gige(struct ar8xxx_priv *priv)
 282 {
 283         return priv->chip->caps & AR8XXX_CAP_GIGE;
 284 }
 285
 286 static inline bool ar8xxx_has_mib_counters(struct ar8xxx_priv *priv)
 287 {
 288         return priv->chip->caps & AR8XXX_CAP_MIB_COUNTERS;
 289 }
 290
 291 static inline bool chip_is_ar8216(struct ar8xxx_priv *priv)
 292 {
 293         return priv->chip_ver == AR8XXX_VER_AR8216;
 294 }
 295
 296 static inline bool chip_is_ar8236(struct ar8xxx_priv *priv)
 297 {
 298         return priv->chip_ver == AR8XXX_VER_AR8236;
 299 }
 300
 301 static inline bool chip_is_ar8316(struct ar8xxx_priv *priv)
 302 {
 303         return priv->chip_ver == AR8XXX_VER_AR8316;
 304 }
 305
 306 static inline bool chip_is_ar8327(struct ar8xxx_priv *priv)
 307 {
 308         return priv->chip_ver == AR8XXX_VER_AR8327;
 309 }
 310
 311 static inline bool chip_is_ar8337(struct ar8xxx_priv *priv)
 312 {
 313         return priv->chip_ver == AR8XXX_VER_AR8337;
 314 }
 315
 316 static inline void
 317 split_addr(u32 regaddr, u16 *r1, u16 *r2, u16 *page)
 318 {
 319         regaddr >>= 1;
 320         *r1 = regaddr & 0x1e;
 321
 322         regaddr >>= 5;
 323         *r2 = regaddr & 0x7;
 324
 325         regaddr >>= 3;
 326         *page = regaddr & 0x1ff;
 327 }
 328
 329 /* inspired by phy_poll_reset in drivers/net/phy/phy_device.c */
 330 static int
 331 ar8xxx_phy_poll_reset(struct mii_bus *bus)
 332 {
 333         unsigned int sleep_msecs = 20;
 334         int ret, elapsed, i;
 335
 336         for (elapsed = sleep_msecs; elapsed <= 600;
 337              elapsed += sleep_msecs) {
 338                 msleep(sleep_msecs);
 339                 for (i = 0; i < AR8XXX_NUM_PHYS; i++) {
 340                         ret = mdiobus_read(bus, i, MII_BMCR);
 341                         if (ret < 0)
 342                                 return ret;
 343                         if (ret & BMCR_RESET)
 344                                 break;
 345                         if (i == AR8XXX_NUM_PHYS - 1) {
 346                                 usleep_range(1000, 2000);
 347                                 return 0;
 348                         }
 349                 }
 350         }
 351         return -ETIMEDOUT;
 352 }
 353
 354 static int
 355 ar8xxx_phy_check_aneg(struct phy_device *phydev)
 356 {
 357         int ret;
 358
 359         if (phydev->autoneg != AUTONEG_ENABLE)
 360                 return 0;
 361         /*
 362          * BMCR_ANENABLE might have been cleared
 363          * by phy_init_hw in certain kernel versions
 364          * therefore check for it
 365          */
 366         ret = phy_read(phydev, MII_BMCR);
 367         if (ret < 0)
 368                 return ret;
 369         if (ret & BMCR_ANENABLE)
 370                 return 0;
 371
 372         dev_info(&phydev->dev, "ANEG disabled, re-enabling ...\n");
 373         ret |= BMCR_ANENABLE | BMCR_ANRESTART;
 374         return phy_write(phydev, MII_BMCR, ret);
 375 }
 376
 377 static void
 378 ar8xxx_phy_init(struct ar8xxx_priv *priv)
 379 {
 380         int i;
 381         struct mii_bus *bus;
 382
 383         bus = priv->mii_bus;
 384         for (i = 0; i < AR8XXX_NUM_PHYS; i++) {
 385                 if (priv->chip->phy_fixup)
 386                         priv->chip->phy_fixup(priv, i);
 387
 388                 /* initialize the port itself */
 389                 mdiobus_write(bus, i, MII_ADVERTISE,
 390                         ADVERTISE_ALL | ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
 391                 if (ar8xxx_has_gige(priv))
 392                         mdiobus_write(bus, i, MII_CTRL1000, ADVERTISE_1000FULL);
 393                 mdiobus_write(bus, i, MII_BMCR, BMCR_RESET | BMCR_ANENABLE);
 394         }
 395
 396         ar8xxx_phy_poll_reset(bus);
 397 }
 398
 399 static u32
 400 ar8xxx_mii_read(struct ar8xxx_priv *priv, int reg)
 401 {
 402         struct mii_bus *bus = priv->mii_bus;
 403         u16 r1, r2, page;
 404         u16 lo, hi;
 405
 406         split_addr((u32) reg, &r1, &r2, &page);
 407
 408         mutex_lock(&bus->mdio_lock);
 409
 410         bus->write(bus, 0x18, 0, page);
 411         usleep_range(1000, 2000); /* wait for the page switch to propagate */
 412         lo = bus->read(bus, 0x10 | r2, r1);
 413         hi = bus->read(bus, 0x10 | r2, r1 + 1);
 414
 415         mutex_unlock(&bus->mdio_lock);
 416
 417         return (hi << 16) | lo;
 418 }
 419
 420 static void
 421 ar8xxx_mii_write(struct ar8xxx_priv *priv, int reg, u32 val)
 422 {
 423         struct mii_bus *bus = priv->mii_bus;
 424         u16 r1, r2, r3;
 425         u16 lo, hi;
 426
 427         split_addr((u32) reg, &r1, &r2, &r3);
 428         lo = val & 0xffff;
 429         hi = (u16) (val >> 16);
 430
 431         mutex_lock(&bus->mdio_lock);
 432
 433         bus->write(bus, 0x18, 0, r3);
 434         usleep_range(1000, 2000); /* wait for the page switch to propagate */
 435         if (priv->chip->mii_lo_first) {
 436                 bus->write(bus, 0x10 | r2, r1, lo);
 437                 bus->write(bus, 0x10 | r2, r1 + 1, hi);
 438         } else {
 439                 bus->write(bus, 0x10 | r2, r1 + 1, hi);
 440                 bus->write(bus, 0x10 | r2, r1, lo);
 441         }
 442
 443         mutex_unlock(&bus->mdio_lock);
 444 }
 445
 446 static u32
 447 ar8xxx_mii_rmw(struct ar8xxx_priv *priv, int reg, u32 mask, u32 val)
 448 {
 449         struct mii_bus *bus = priv->mii_bus;
 450         u16 r1, r2, page;
 451         u16 lo, hi;
 452         u32 ret;
 453
 454         split_addr((u32) reg, &r1, &r2, &page);
 455
 456         mutex_lock(&bus->mdio_lock);
 457
 458         bus->write(bus, 0x18, 0, page);
 459         usleep_range(1000, 2000); /* wait for the page switch to propagate */
 460
 461         lo = bus->read(bus, 0x10 | r2, r1);
 462         hi = bus->read(bus, 0x10 | r2, r1 + 1);
 463
 464         ret = hi << 16 | lo;
 465         ret &= ~mask;
 466         ret |= val;
 467
 468         lo = ret & 0xffff;
 469         hi = (u16) (ret >> 16);
 470
 471         if (priv->chip->mii_lo_first) {
 472                 bus->write(bus, 0x10 | r2, r1, lo);
 473                 bus->write(bus, 0x10 | r2, r1 + 1, hi);
 474         } else {
 475                 bus->write(bus, 0x10 | r2, r1 + 1, hi);
 476                 bus->write(bus, 0x10 | r2, r1, lo);
 477         }
 478
 479         mutex_unlock(&bus->mdio_lock);
 480
 481         return ret;
 482 }
 483
 484
 485 static void
 486 ar8xxx_phy_dbg_write(struct ar8xxx_priv *priv, int phy_addr,
 487                      u16 dbg_addr, u16 dbg_data)
 488 {
 489         struct mii_bus *bus = priv->mii_bus;
 490
 491         mutex_lock(&bus->mdio_lock);
 492         bus->write(bus, phy_addr, MII_ATH_DBG_ADDR, dbg_addr);
 493         bus->write(bus, phy_addr, MII_ATH_DBG_DATA, dbg_data);
 494         mutex_unlock(&bus->mdio_lock);
 495 }
 496
 497 static void
 498 ar8xxx_phy_mmd_write(struct ar8xxx_priv *priv, int phy_addr, u16 addr, u16 data)
 499 {
 500         struct mii_bus *bus = priv->mii_bus;
 501
 502         mutex_lock(&bus->mdio_lock);
 503         bus->write(bus, phy_addr, MII_ATH_MMD_ADDR, addr);
 504         bus->write(bus, phy_addr, MII_ATH_MMD_DATA, data);
 505         mutex_unlock(&bus->mdio_lock);
 506 }
 507
 508 static inline u32
 509 ar8xxx_rmw(struct ar8xxx_priv *priv, int reg, u32 mask, u32 val)
 510 {
 511         return priv->rmw(priv, reg, mask, val);
 512 }
 513
 514 static inline void
 515 ar8xxx_reg_set(struct ar8xxx_priv *priv, int reg, u32 val)
 516 {
 517         priv->rmw(priv, reg, 0, val);
 518 }
 519
 520 static int
 521 ar8xxx_reg_wait(struct ar8xxx_priv *priv, u32 reg, u32 mask, u32 val,
 522                 unsigned timeout)
 523 {
 524         int i;
 525
 526         for (i = 0; i < timeout; i++) {
 527                 u32 t;
 528
 529                 t = priv->read(priv, reg);
 530                 if ((t & mask) == val)
 531                         return 0;
 532
 533                 usleep_range(1000, 2000);
 534         }
 535
 536         return -ETIMEDOUT;
 537 }
 538
 539 static int
 540 ar8xxx_mib_op(struct ar8xxx_priv *priv, u32 op)
 541 {
 542         unsigned mib_func = priv->chip->mib_func;
 543         int ret;
 544
 545         lockdep_assert_held(&priv->mib_lock);
 546
 547         /* Capture the hardware statistics for all ports */
 548         ar8xxx_rmw(priv, mib_func, AR8216_MIB_FUNC, (op << AR8216_MIB_FUNC_S));
 549
 550         /* Wait for the capturing to complete. */
 551         ret = ar8xxx_reg_wait(priv, mib_func, AR8216_MIB_BUSY, 0, 10);
 552         if (ret)
 553                 goto out;
 554
 555         ret = 0;
 556
 557 out:
 558         return ret;
 559 }
 560
 561 static int
 562 ar8xxx_mib_capture(struct ar8xxx_priv *priv)
 563 {
 564         return ar8xxx_mib_op(priv, AR8216_MIB_FUNC_CAPTURE);
 565 }
 566
 567 static int
 568 ar8xxx_mib_flush(struct ar8xxx_priv *priv)
 569 {
 570         return ar8xxx_mib_op(priv, AR8216_MIB_FUNC_FLUSH);
 571 }
 572
 573 static void
 574 ar8xxx_mib_fetch_port_stat(struct ar8xxx_priv *priv, int port, bool flush)
 575 {
 576         unsigned int base;
 577         u64 *mib_stats;
 578         int i;
 579
 580         WARN_ON(port >= priv->dev.ports);
 581
 582         lockdep_assert_held(&priv->mib_lock);
 583
 584         base = priv->chip->reg_port_stats_start +
 585                priv->chip->reg_port_stats_length * port;
 586
 587         mib_stats = &priv->mib_stats[port * priv->chip->num_mibs];
 588         for (i = 0; i < priv->chip->num_mibs; i++) {
 589                 const struct ar8xxx_mib_desc *mib;
 590                 u64 t;
 591
 592                 mib = &priv->chip->mib_decs[i];
 593                 t = priv->read(priv, base + mib->offset);
 594                 if (mib->size == 2) {
 595                         u64 hi;
 596
 597                         hi = priv->read(priv, base + mib->offset + 4);
 598                         t |= hi << 32;
 599                 }
 600
 601                 if (flush)
 602                         mib_stats[i] = 0;
 603                 else
 604                         mib_stats[i] += t;
 605         }
 606 }
 607
 608 static void
 609 ar8216_read_port_link(struct ar8xxx_priv *priv, int port,
 610                       struct switch_port_link *link)
 611 {
 612         u32 status;
 613         u32 speed;
 614
 615         memset(link, '\0', sizeof(*link));
 616
 617         status = priv->chip->read_port_status(priv, port);
 618
 619         link->aneg = !!(status & AR8216_PORT_STATUS_LINK_AUTO);
 620         if (link->aneg) {
 621                 link->link = !!(status & AR8216_PORT_STATUS_LINK_UP);
 622         } else {
 623                 link->link = true;
 624
 625                 if (priv->get_port_link) {
 626                         int err;
 627
 628                         err = priv->get_port_link(port);
 629                         if (err >= 0)
 630                                 link->link = !!err;
 631                 }
 632         }
 633
 634         if (!link->link)
 635                 return;
 636
 637         link->duplex = !!(status & AR8216_PORT_STATUS_DUPLEX);
 638         link->tx_flow = !!(status & AR8216_PORT_STATUS_TXFLOW);
 639         link->rx_flow = !!(status & AR8216_PORT_STATUS_RXFLOW);
 640
 641         speed = (status & AR8216_PORT_STATUS_SPEED) >>
 642                  AR8216_PORT_STATUS_SPEED_S;
 643
 644         switch (speed) {
 645         case AR8216_PORT_SPEED_10M:
 646                 link->speed = SWITCH_PORT_SPEED_10;
 647                 break;
 648         case AR8216_PORT_SPEED_100M:
 649                 link->speed = SWITCH_PORT_SPEED_100;
 650                 break;
 651         case AR8216_PORT_SPEED_1000M:
 652                 link->speed = SWITCH_PORT_SPEED_1000;
 653                 break;
 654         default:
 655                 link->speed = SWITCH_PORT_SPEED_UNKNOWN;
 656                 break;
 657         }
 658 }
 659
 660 static struct sk_buff *
 661 ar8216_mangle_tx(struct net_device *dev, struct sk_buff *skb)
 662 {
 663         struct ar8xxx_priv *priv = dev->phy_ptr;
 664         unsigned char *buf;
 665
 666         if (unlikely(!priv))
 667                 goto error;
 668
 669         if (!priv->vlan)
 670                 goto send;
 671
 672         if (unlikely(skb_headroom(skb) < 2)) {
 673                 if (pskb_expand_head(skb, 2, 0, GFP_ATOMIC) < 0)
 674                         goto error;
 675         }
 676
 677         buf = skb_push(skb, 2);
 678         buf[0] = 0x10;
 679         buf[1] = 0x80;
 680
 681 send:
 682         return skb;
 683
 684 error:
 685         dev_kfree_skb_any(skb);
 686         return NULL;
 687 }
 688
 689 static void
 690 ar8216_mangle_rx(struct net_device *dev, struct sk_buff *skb)
 691 {
 692         struct ar8xxx_priv *priv;
 693         unsigned char *buf;
 694         int port, vlan;
 695
 696         priv = dev->phy_ptr;
 697         if (!priv)
 698                 return;
 699
 700         /* don't strip the header if vlan mode is disabled */
 701         if (!priv->vlan)
 702                 return;
 703
 704         /* strip header, get vlan id */
 705         buf = skb->data;
 706         skb_pull(skb, 2);
 707
 708         /* check for vlan header presence */
 709         if ((buf[12 + 2] != 0x81) || (buf[13 + 2] != 0x00))
 710                 return;
 711
 712         port = buf[0] & 0xf;
 713
 714         /* no need to fix up packets coming from a tagged source */
 715         if (priv->vlan_tagged & (1 << port))
 716                 return;
 717
 718         /* lookup port vid from local table, the switch passes an invalid vlan id */
 719         vlan = priv->vlan_id[priv->pvid[port]];
 720
 721         buf[14 + 2] &= 0xf0;
 722         buf[14 + 2] |= vlan >> 8;
 723         buf[15 + 2] = vlan & 0xff;
 724 }
 725
 726 static int
 727 ar8216_wait_bit(struct ar8xxx_priv *priv, int reg, u32 mask, u32 val)
 728 {
 729         int timeout = 20;
 730         u32 t = 0;
 731
 732         while (1) {
 733                 t = priv->read(priv, reg);
 734                 if ((t & mask) == val)
 735                         return 0;
 736
 737                 if (timeout-- <= 0)
 738                         break;
 739
 740                 udelay(10);
 741         }
 742
 743         pr_err("ar8216: timeout on reg %08x: %08x & %08x != %08x\n",
 744                (unsigned int) reg, t, mask, val);
 745         return -ETIMEDOUT;
 746 }
 747
 748 static void
 749 ar8216_vtu_op(struct ar8xxx_priv *priv, u32 op, u32 val)
 750 {
 751         if (ar8216_wait_bit(priv, AR8216_REG_VTU, AR8216_VTU_ACTIVE, 0))
 752                 return;
 753         if ((op & AR8216_VTU_OP) == AR8216_VTU_OP_LOAD) {
 754                 val &= AR8216_VTUDATA_MEMBER;
 755                 val |= AR8216_VTUDATA_VALID;
 756                 priv->write(priv, AR8216_REG_VTU_DATA, val);
 757         }
 758         op |= AR8216_VTU_ACTIVE;
 759         priv->write(priv, AR8216_REG_VTU, op);
 760 }
 761
 762 static void
 763 ar8216_vtu_flush(struct ar8xxx_priv *priv)
 764 {
 765         ar8216_vtu_op(priv, AR8216_VTU_OP_FLUSH, 0);
 766 }
 767
 768 static void
 769 ar8216_vtu_load_vlan(struct ar8xxx_priv *priv, u32 vid, u32 port_mask)
 770 {
 771         u32 op;
 772
 773         op = AR8216_VTU_OP_LOAD | (vid << AR8216_VTU_VID_S);
 774         ar8216_vtu_op(priv, op, port_mask);
 775 }
 776
 777 static int
 778 ar8216_atu_flush(struct ar8xxx_priv *priv)
 779 {
 780         int ret;
 781
 782         ret = ar8216_wait_bit(priv, AR8216_REG_ATU, AR8216_ATU_ACTIVE, 0);
 783         if (!ret)
 784                 priv->write(priv, AR8216_REG_ATU, AR8216_ATU_OP_FLUSH);
 785
 786         return ret;
 787 }
 788
 789 static u32
 790 ar8216_read_port_status(struct ar8xxx_priv *priv, int port)
 791 {
 792         return priv->read(priv, AR8216_REG_PORT_STATUS(port));
 793 }
 794
 795 static void
 796 ar8216_setup_port(struct ar8xxx_priv *priv, int port, u32 members)
 797 {
 798         u32 header;
 799         u32 egress, ingress;
 800         u32 pvid;
 801
 802         if (priv->vlan) {
 803                 pvid = priv->vlan_id[priv->pvid[port]];
 804                 if (priv->vlan_tagged & (1 << port))
 805                         egress = AR8216_OUT_ADD_VLAN;
 806                 else
 807                         egress = AR8216_OUT_STRIP_VLAN;
 808                 ingress = AR8216_IN_SECURE;
 809         } else {
 810                 pvid = port;
 811                 egress = AR8216_OUT_KEEP;
 812                 ingress = AR8216_IN_PORT_ONLY;
 813         }
 814
 815         if (chip_is_ar8216(priv) && priv->vlan && port == AR8216_PORT_CPU)
 816                 header = AR8216_PORT_CTRL_HEADER;
 817         else
 818                 header = 0;
 819
 820         ar8xxx_rmw(priv, AR8216_REG_PORT_CTRL(port),
 821                    AR8216_PORT_CTRL_LEARN | AR8216_PORT_CTRL_VLAN_MODE |
 822                    AR8216_PORT_CTRL_SINGLE_VLAN | AR8216_PORT_CTRL_STATE |
 823                    AR8216_PORT_CTRL_HEADER | AR8216_PORT_CTRL_LEARN_LOCK,
 824                    AR8216_PORT_CTRL_LEARN | header |
 825                    (egress << AR8216_PORT_CTRL_VLAN_MODE_S) |
 826                    (AR8216_PORT_STATE_FORWARD << AR8216_PORT_CTRL_STATE_S));
 827
 828         ar8xxx_rmw(priv, AR8216_REG_PORT_VLAN(port),
 829                    AR8216_PORT_VLAN_DEST_PORTS | AR8216_PORT_VLAN_MODE |
 830                    AR8216_PORT_VLAN_DEFAULT_ID,
 831                    (members << AR8216_PORT_VLAN_DEST_PORTS_S) |
 832                    (ingress << AR8216_PORT_VLAN_MODE_S) |
 833                    (pvid << AR8216_PORT_VLAN_DEFAULT_ID_S));
 834 }
 835
 836 static int
 837 ar8216_hw_init(struct ar8xxx_priv *priv)
 838 {
 839         if (priv->initialized)
 840                 return 0;
 841
 842         ar8xxx_phy_init(priv);
 843
 844         priv->initialized = true;
 845         return 0;
 846 }
 847
 848 static void
 849 ar8216_init_globals(struct ar8xxx_priv *priv)
 850 {
 851         /* standard atheros magic */
 852         priv->write(priv, 0x38, 0xc000050e);
 853
 854         ar8xxx_rmw(priv, AR8216_REG_GLOBAL_CTRL,
 855                    AR8216_GCTRL_MTU, 1518 + 8 + 2);
 856 }
 857
 858 static void
 859 ar8216_init_port(struct ar8xxx_priv *priv, int port)
 860 {
 861         /* Enable port learning and tx */
 862         priv->write(priv, AR8216_REG_PORT_CTRL(port),
 863                 AR8216_PORT_CTRL_LEARN |
 864                 (4 << AR8216_PORT_CTRL_STATE_S));
 865
 866         priv->write(priv, AR8216_REG_PORT_VLAN(port), 0);
 867
 868         if (port == AR8216_PORT_CPU) {
 869                 priv->write(priv, AR8216_REG_PORT_STATUS(port),
 870                         AR8216_PORT_STATUS_LINK_UP |
 871                         (ar8xxx_has_gige(priv) ?
 872                                 AR8216_PORT_SPEED_1000M : AR8216_PORT_SPEED_100M) |
 873                         AR8216_PORT_STATUS_TXMAC |
 874                         AR8216_PORT_STATUS_RXMAC |
 875                         (chip_is_ar8316(priv) ? AR8216_PORT_STATUS_RXFLOW : 0) |
 876                         (chip_is_ar8316(priv) ? AR8216_PORT_STATUS_TXFLOW : 0) |
 877                         AR8216_PORT_STATUS_DUPLEX);
 878         } else {
 879                 priv->write(priv, AR8216_REG_PORT_STATUS(port),
 880                         AR8216_PORT_STATUS_LINK_AUTO);
 881         }
 882 }
 883
 884 static const struct ar8xxx_chip ar8216_chip = {
 885         .caps = AR8XXX_CAP_MIB_COUNTERS,
 886
 887         .reg_port_stats_start = 0x19000,
 888         .reg_port_stats_length = 0xa0,
 889
 890         .hw_init = ar8216_hw_init,
 891         .init_globals = ar8216_init_globals,
 892         .init_port = ar8216_init_port,
 893         .setup_port = ar8216_setup_port,
 894         .read_port_status = ar8216_read_port_status,
 895         .atu_flush = ar8216_atu_flush,
 896         .vtu_flush = ar8216_vtu_flush,
 897         .vtu_load_vlan = ar8216_vtu_load_vlan,
 898         .set_mirror_regs = ar8216_set_mirror_regs,
 899
 900         .num_mibs = ARRAY_SIZE(ar8216_mibs),
 901         .mib_decs = ar8216_mibs,
 902         .mib_func = AR8216_REG_MIB_FUNC
 903 };
 904
 905 static void
 906 ar8236_setup_port(struct ar8xxx_priv *priv, int port, u32 members)
 907 {
 908         u32 egress, ingress;
 909         u32 pvid;
 910
 911         if (priv->vlan) {
 912                 pvid = priv->vlan_id[priv->pvid[port]];
 913                 if (priv->vlan_tagged & (1 << port))
 914                         egress = AR8216_OUT_ADD_VLAN;
 915                 else
 916                         egress = AR8216_OUT_STRIP_VLAN;
 917                 ingress = AR8216_IN_SECURE;
 918         } else {
 919                 pvid = port;
 920                 egress = AR8216_OUT_KEEP;
 921                 ingress = AR8216_IN_PORT_ONLY;
 922         }
 923
 924         ar8xxx_rmw(priv, AR8216_REG_PORT_CTRL(port),
 925                    AR8216_PORT_CTRL_LEARN | AR8216_PORT_CTRL_VLAN_MODE |
 926                    AR8216_PORT_CTRL_SINGLE_VLAN | AR8216_PORT_CTRL_STATE |
 927                    AR8216_PORT_CTRL_HEADER | AR8216_PORT_CTRL_LEARN_LOCK,
 928                    AR8216_PORT_CTRL_LEARN |
 929                    (egress << AR8216_PORT_CTRL_VLAN_MODE_S) |
 930                    (AR8216_PORT_STATE_FORWARD << AR8216_PORT_CTRL_STATE_S));
 931
 932         ar8xxx_rmw(priv, AR8236_REG_PORT_VLAN(port),
 933                    AR8236_PORT_VLAN_DEFAULT_ID,
 934                    (pvid << AR8236_PORT_VLAN_DEFAULT_ID_S));
 935
 936         ar8xxx_rmw(priv, AR8236_REG_PORT_VLAN2(port),
 937                    AR8236_PORT_VLAN2_VLAN_MODE |
 938                    AR8236_PORT_VLAN2_MEMBER,
 939                    (ingress << AR8236_PORT_VLAN2_VLAN_MODE_S) |
 940                    (members << AR8236_PORT_VLAN2_MEMBER_S));
 941 }
 942
 943 static void
 944 ar8236_init_globals(struct ar8xxx_priv *priv)
 945 {
 946         /* enable jumbo frames */
 947         ar8xxx_rmw(priv, AR8216_REG_GLOBAL_CTRL,
 948                    AR8316_GCTRL_MTU, 9018 + 8 + 2);
 949
 950         /* Enable MIB counters */
 951         ar8xxx_rmw(priv, AR8216_REG_MIB_FUNC, AR8216_MIB_FUNC | AR8236_MIB_EN,
 952                    (AR8216_MIB_FUNC_NO_OP << AR8216_MIB_FUNC_S) |
 953                    AR8236_MIB_EN);
 954 }
 955
 956 static const struct ar8xxx_chip ar8236_chip = {
 957         .caps = AR8XXX_CAP_MIB_COUNTERS,
 958
 959         .reg_port_stats_start = 0x20000,
 960         .reg_port_stats_length = 0x100,
 961
 962         .hw_init = ar8216_hw_init,
 963         .init_globals = ar8236_init_globals,
 964         .init_port = ar8216_init_port,
 965         .setup_port = ar8236_setup_port,
 966         .read_port_status = ar8216_read_port_status,
 967         .atu_flush = ar8216_atu_flush,
 968         .vtu_flush = ar8216_vtu_flush,
 969         .vtu_load_vlan = ar8216_vtu_load_vlan,
 970         .set_mirror_regs = ar8216_set_mirror_regs,
 971
 972         .num_mibs = ARRAY_SIZE(ar8236_mibs),
 973         .mib_decs = ar8236_mibs,
 974         .mib_func = AR8216_REG_MIB_FUNC
 975 };
 976
 977 static int
 978 ar8316_hw_init(struct ar8xxx_priv *priv)
 979 {
 980         u32 val, newval;
 981
 982         val = priv->read(priv, AR8316_REG_POSTRIP);
 983
 984         if (priv->phy->interface == PHY_INTERFACE_MODE_RGMII) {
 985                 if (priv->port4_phy) {
 986                         /* value taken from Ubiquiti RouterStation Pro */
 987                         newval = 0x81461bea;
 988                         pr_info("ar8316: Using port 4 as PHY\n");
 989                 } else {
 990                         newval = 0x01261be2;
 991                         pr_info("ar8316: Using port 4 as switch port\n");
 992                 }
 993         } else if (priv->phy->interface == PHY_INTERFACE_MODE_GMII) {
 994                 /* value taken from AVM Fritz!Box 7390 sources */
 995                 newval = 0x010e5b71;
 996         } else {
 997                 /* no known value for phy interface */
 998                 pr_err("ar8316: unsupported mii mode: %d.\n",
 999                        priv->phy->interface);
1000                 return -EINVAL;
1001         }
1002
1003         if (val == newval)
1004                 goto out;
1005
1006         priv->write(priv, AR8316_REG_POSTRIP, newval);
1007
1008         if (priv->port4_phy &&
1009             priv->phy->interface == PHY_INTERFACE_MODE_RGMII) {
1010                 /* work around for phy4 rgmii mode */
1011                 ar8xxx_phy_dbg_write(priv, 4, 0x12, 0x480c);
1012                 /* rx delay */
1013                 ar8xxx_phy_dbg_write(priv, 4, 0x0, 0x824e);
1014                 /* tx delay */
1015                 ar8xxx_phy_dbg_write(priv, 4, 0x5, 0x3d47);
1016                 msleep(1000);
1017         }
1018
1019         ar8xxx_phy_init(priv);
1020
1021 out:
1022         priv->initialized = true;
1023         return 0;
1024 }
1025
1026 static void
1027 ar8316_init_globals(struct ar8xxx_priv *priv)
1028 {
1029         /* standard atheros magic */
1030         priv->write(priv, 0x38, 0xc000050e);
1031
1032         /* enable cpu port to receive multicast and broadcast frames */
1033         priv->write(priv, AR8216_REG_FLOOD_MASK, 0x003f003f);
1034
1035         /* enable jumbo frames */
1036         ar8xxx_rmw(priv, AR8216_REG_GLOBAL_CTRL,
1037                    AR8316_GCTRL_MTU, 9018 + 8 + 2);
1038
1039         /* Enable MIB counters */
1040         ar8xxx_rmw(priv, AR8216_REG_MIB_FUNC, AR8216_MIB_FUNC | AR8236_MIB_EN,
1041                    (AR8216_MIB_FUNC_NO_OP << AR8216_MIB_FUNC_S) |
1042                    AR8236_MIB_EN);
1043 }
1044
1045 static const struct ar8xxx_chip ar8316_chip = {
1046         .caps = AR8XXX_CAP_GIGE | AR8XXX_CAP_MIB_COUNTERS,
1047
1048         .reg_port_stats_start = 0x20000,
1049         .reg_port_stats_length = 0x100,
1050
1051         .hw_init = ar8316_hw_init,
1052         .init_globals = ar8316_init_globals,
1053         .init_port = ar8216_init_port,
1054         .setup_port = ar8216_setup_port,
1055         .read_port_status = ar8216_read_port_status,
1056         .atu_flush = ar8216_atu_flush,
1057         .vtu_flush = ar8216_vtu_flush,
1058         .vtu_load_vlan = ar8216_vtu_load_vlan,
1059         .set_mirror_regs = ar8216_set_mirror_regs,
1060
1061         .num_mibs = ARRAY_SIZE(ar8236_mibs),
1062         .mib_decs = ar8236_mibs,
1063         .mib_func = AR8216_REG_MIB_FUNC
1064 };
1065
1066 static u32
1067 ar8327_get_pad_cfg(struct ar8327_pad_cfg *cfg)
1068 {
1069         u32 t;
1070
1071         if (!cfg)
1072                 return 0;
1073
1074         t = 0;
1075         switch (cfg->mode) {
1076         case AR8327_PAD_NC:
1077                 break;
1078
1079         case AR8327_PAD_MAC2MAC_MII:
1080                 t = AR8327_PAD_MAC_MII_EN;
1081                 if (cfg->rxclk_sel)
1082                         t |= AR8327_PAD_MAC_MII_RXCLK_SEL;
1083                 if (cfg->txclk_sel)
1084                         t |= AR8327_PAD_MAC_MII_TXCLK_SEL;
1085                 break;
1086
1087         case AR8327_PAD_MAC2MAC_GMII:
1088                 t = AR8327_PAD_MAC_GMII_EN;
1089                 if (cfg->rxclk_sel)
1090                         t |= AR8327_PAD_MAC_GMII_RXCLK_SEL;
1091                 if (cfg->txclk_sel)
1092                         t |= AR8327_PAD_MAC_GMII_TXCLK_SEL;
1093                 break;
1094
1095         case AR8327_PAD_MAC_SGMII:
1096                 t = AR8327_PAD_SGMII_EN;
1097
1098                 /*
1099                  * WAR for the QUalcomm Atheros AP136 board.
1100                  * It seems that RGMII TX/RX delay settings needs to be
1101                  * applied for SGMII mode as well, The ethernet is not
1102                  * reliable without this.
1103                  */
1104                 t |= cfg->txclk_delay_sel << AR8327_PAD_RGMII_TXCLK_DELAY_SEL_S;
1105                 t |= cfg->rxclk_delay_sel << AR8327_PAD_RGMII_RXCLK_DELAY_SEL_S;
1106                 if (cfg->rxclk_delay_en)
1107                         t |= AR8327_PAD_RGMII_RXCLK_DELAY_EN;
1108                 if (cfg->txclk_delay_en)
1109                         t |= AR8327_PAD_RGMII_TXCLK_DELAY_EN;
1110
1111                 if (cfg->sgmii_delay_en)
1112                         t |= AR8327_PAD_SGMII_DELAY_EN;
1113
1114                 break;
1115
1116         case AR8327_PAD_MAC2PHY_MII:
1117                 t = AR8327_PAD_PHY_MII_EN;
1118                 if (cfg->rxclk_sel)
1119                         t |= AR8327_PAD_PHY_MII_RXCLK_SEL;
1120                 if (cfg->txclk_sel)
1121                         t |= AR8327_PAD_PHY_MII_TXCLK_SEL;
1122                 break;
1123
1124         case AR8327_PAD_MAC2PHY_GMII:
1125                 t = AR8327_PAD_PHY_GMII_EN;
1126                 if (cfg->pipe_rxclk_sel)
1127                         t |= AR8327_PAD_PHY_GMII_PIPE_RXCLK_SEL;
1128                 if (cfg->rxclk_sel)
1129                         t |= AR8327_PAD_PHY_GMII_RXCLK_SEL;
1130                 if (cfg->txclk_sel)
1131                         t |= AR8327_PAD_PHY_GMII_TXCLK_SEL;
1132                 break;
1133
1134         case AR8327_PAD_MAC_RGMII:
1135                 t = AR8327_PAD_RGMII_EN;
1136                 t |= cfg->txclk_delay_sel << AR8327_PAD_RGMII_TXCLK_DELAY_SEL_S;
1137                 t |= cfg->rxclk_delay_sel << AR8327_PAD_RGMII_RXCLK_DELAY_SEL_S;
1138                 if (cfg->rxclk_delay_en)
1139                         t |= AR8327_PAD_RGMII_RXCLK_DELAY_EN;
1140                 if (cfg->txclk_delay_en)
1141                         t |= AR8327_PAD_RGMII_TXCLK_DELAY_EN;
1142                 break;
1143
1144         case AR8327_PAD_PHY_GMII:
1145                 t = AR8327_PAD_PHYX_GMII_EN;
1146                 break;
1147
1148         case AR8327_PAD_PHY_RGMII:
1149                 t = AR8327_PAD_PHYX_RGMII_EN;
1150                 break;
1151
1152         case AR8327_PAD_PHY_MII:
1153                 t = AR8327_PAD_PHYX_MII_EN;
1154                 break;
1155         }
1156
1157         return t;
1158 }
1159
1160 static void
1161 ar8327_phy_fixup(struct ar8xxx_priv *priv, int phy)
1162 {
1163         switch (priv->chip_rev) {
1164         case 1:
1165                 /* For 100M waveform */
1166                 ar8xxx_phy_dbg_write(priv, phy, 0, 0x02ea);
1167                 /* Turn on Gigabit clock */
1168                 ar8xxx_phy_dbg_write(priv, phy, 0x3d, 0x68a0);
1169                 break;
1170
1171         case 2:
1172                 ar8xxx_phy_mmd_write(priv, phy, 0x7, 0x3c);
1173                 ar8xxx_phy_mmd_write(priv, phy, 0x4007, 0x0);
1174                 /* fallthrough */
1175         case 4:
1176                 ar8xxx_phy_mmd_write(priv, phy, 0x3, 0x800d);
1177                 ar8xxx_phy_mmd_write(priv, phy, 0x4003, 0x803f);
1178
1179                 ar8xxx_phy_dbg_write(priv, phy, 0x3d, 0x6860);
1180                 ar8xxx_phy_dbg_write(priv, phy, 0x5, 0x2c46);
1181                 ar8xxx_phy_dbg_write(priv, phy, 0x3c, 0x6000);
1182                 break;
1183         }
1184 }
1185
1186 static u32
1187 ar8327_get_port_init_status(struct ar8327_port_cfg *cfg)
1188 {
1189         u32 t;
1190
1191         if (!cfg->force_link)
1192                 return AR8216_PORT_STATUS_LINK_AUTO;
1193
1194         t = AR8216_PORT_STATUS_TXMAC | AR8216_PORT_STATUS_RXMAC;
1195         t |= cfg->duplex ? AR8216_PORT_STATUS_DUPLEX : 0;
1196         t |= cfg->rxpause ? AR8216_PORT_STATUS_RXFLOW : 0;
1197         t |= cfg->txpause ? AR8216_PORT_STATUS_TXFLOW : 0;
1198
1199         switch (cfg->speed) {
1200         case AR8327_PORT_SPEED_10:
1201                 t |= AR8216_PORT_SPEED_10M;
1202                 break;
1203         case AR8327_PORT_SPEED_100:
1204                 t |= AR8216_PORT_SPEED_100M;
1205                 break;
1206         case AR8327_PORT_SPEED_1000:
1207                 t |= AR8216_PORT_SPEED_1000M;
1208                 break;
1209         }
1210
1211         return t;
1212 }
1213
1214 #define AR8327_LED_ENTRY(_num, _reg, _shift) \
1215         [_num] = { .reg = (_reg), .shift = (_shift) }
1216
1217 static const struct ar8327_led_entry
1218 ar8327_led_map[AR8327_NUM_LEDS] = {
1219         AR8327_LED_ENTRY(AR8327_LED_PHY0_0, 0, 14),
1220         AR8327_LED_ENTRY(AR8327_LED_PHY0_1, 1, 14),
1221         AR8327_LED_ENTRY(AR8327_LED_PHY0_2, 2, 14),
1222
1223         AR8327_LED_ENTRY(AR8327_LED_PHY1_0, 3, 8),
1224         AR8327_LED_ENTRY(AR8327_LED_PHY1_1, 3, 10),
1225         AR8327_LED_ENTRY(AR8327_LED_PHY1_2, 3, 12),
1226
1227         AR8327_LED_ENTRY(AR8327_LED_PHY2_0, 3, 14),
1228         AR8327_LED_ENTRY(AR8327_LED_PHY2_1, 3, 16),
1229         AR8327_LED_ENTRY(AR8327_LED_PHY2_2, 3, 18),
1230
1231         AR8327_LED_ENTRY(AR8327_LED_PHY3_0, 3, 20),
1232         AR8327_LED_ENTRY(AR8327_LED_PHY3_1, 3, 22),
1233         AR8327_LED_ENTRY(AR8327_LED_PHY3_2, 3, 24),
1234
1235         AR8327_LED_ENTRY(AR8327_LED_PHY4_0, 0, 30),
1236         AR8327_LED_ENTRY(AR8327_LED_PHY4_1, 1, 30),
1237         AR8327_LED_ENTRY(AR8327_LED_PHY4_2, 2, 30),
1238 };
1239
1240 static void
1241 ar8327_set_led_pattern(struct ar8xxx_priv *priv, unsigned int led_num,
1242                        enum ar8327_led_pattern pattern)
1243 {
1244         const struct ar8327_led_entry *entry;
1245
1246         entry = &ar8327_led_map[led_num];
1247         ar8xxx_rmw(priv, AR8327_REG_LED_CTRL(entry->reg),
1248                    (3 << entry->shift), pattern << entry->shift);
1249 }
1250
1251 static void
1252 ar8327_led_work_func(struct work_struct *work)
1253 {
1254         struct ar8327_led *aled;
1255         u8 pattern;
1256
1257         aled = container_of(work, struct ar8327_led, led_work);
1258
1259         spin_lock(&aled->lock);
1260         pattern = aled->pattern;
1261         spin_unlock(&aled->lock);
1262
1263         ar8327_set_led_pattern(aled->sw_priv, aled->led_num,
1264                                pattern);
1265 }
1266
1267 static void
1268 ar8327_led_schedule_change(struct ar8327_led *aled, u8 pattern)
1269 {
1270         if (aled->pattern == pattern)
1271                 return;
1272
1273         aled->pattern = pattern;
1274         schedule_work(&aled->led_work);
1275 }
1276
1277 static inline struct ar8327_led *
1278 led_cdev_to_ar8327_led(struct led_classdev *led_cdev)
1279 {
1280         return container_of(led_cdev, struct ar8327_led, cdev);
1281 }
1282
1283 static int
1284 ar8327_led_blink_set(struct led_classdev *led_cdev,
1285                      unsigned long *delay_on,
1286                      unsigned long *delay_off)
1287 {
1288         struct ar8327_led *aled = led_cdev_to_ar8327_led(led_cdev);
1289
1290         if (*delay_on == 0 && *delay_off == 0) {
1291                 *delay_on = 125;
1292                 *delay_off = 125;
1293         }
1294
1295         if (*delay_on != 125 || *delay_off != 125) {
1296                 /*
1297                  * The hardware only supports blinking at 4Hz. Fall back
1298                  * to software implementation in other cases.
1299                  */
1300                 return -EINVAL;
1301         }
1302
1303         spin_lock(&aled->lock);
1304
1305         aled->enable_hw_mode = false;
1306         ar8327_led_schedule_change(aled, AR8327_LED_PATTERN_BLINK);
1307
1308         spin_unlock(&aled->lock);
1309
1310         return 0;
1311 }
1312
1313 static void
1314 ar8327_led_set_brightness(struct led_classdev *led_cdev,
1315                           enum led_brightness brightness)
1316 {
1317         struct ar8327_led *aled = led_cdev_to_ar8327_led(led_cdev);
1318         u8 pattern;
1319         bool active;
1320
1321         active = (brightness != LED_OFF);
1322         active ^= aled->active_low;
1323
1324         pattern = (active) ? AR8327_LED_PATTERN_ON :
1325                              AR8327_LED_PATTERN_OFF;
1326
1327         spin_lock(&aled->lock);
1328
1329         aled->enable_hw_mode = false;
1330         ar8327_led_schedule_change(aled, pattern);
1331
1332         spin_unlock(&aled->lock);
1333 }
1334
1335 static ssize_t
1336 ar8327_led_enable_hw_mode_show(struct device *dev,
1337                                struct device_attribute *attr,
1338                                char *buf)
1339 {
1340         struct led_classdev *led_cdev = dev_get_drvdata(dev);
1341         struct ar8327_led *aled = led_cdev_to_ar8327_led(led_cdev);
1342         ssize_t ret = 0;
1343
1344         spin_lock(&aled->lock);
1345         ret += sprintf(buf, "%d\n", aled->enable_hw_mode);
1346         spin_unlock(&aled->lock);
1347
1348         return ret;
1349 }
1350
1351 static ssize_t
1352 ar8327_led_enable_hw_mode_store(struct device *dev,
1353                                 struct device_attribute *attr,
1354                                 const char *buf,
1355                                 size_t size)
1356 {
1357         struct led_classdev *led_cdev = dev_get_drvdata(dev);
1358         struct ar8327_led *aled = led_cdev_to_ar8327_led(led_cdev);
1359         u8 pattern;
1360         u8 value;
1361         int ret;
1362
1363         ret = kstrtou8(buf, 10, &value);
1364         if (ret < 0)
1365                 return -EINVAL;
1366
1367         spin_lock(&aled->lock);
1368
1369         aled->enable_hw_mode = !!value;
1370         if (aled->enable_hw_mode)
1371                 pattern = AR8327_LED_PATTERN_RULE;
1372         else
1373                 pattern = AR8327_LED_PATTERN_OFF;
1374
1375         ar8327_led_schedule_change(aled, pattern);
1376
1377         spin_unlock(&aled->lock);
1378
1379         return size;
1380 }
1381
1382 static DEVICE_ATTR(enable_hw_mode,  S_IRUGO | S_IWUSR,
1383                    ar8327_led_enable_hw_mode_show,
1384                    ar8327_led_enable_hw_mode_store);
1385
1386 static int
1387 ar8327_led_register(struct ar8xxx_priv *priv, struct ar8327_led *aled)
1388 {
1389         int ret;
1390
1391         ret = led_classdev_register(NULL, &aled->cdev);
1392         if (ret < 0)
1393                 return ret;
1394
1395         if (aled->mode == AR8327_LED_MODE_HW) {
1396                 ret = device_create_file(aled->cdev.dev,
1397                                          &dev_attr_enable_hw_mode);
1398                 if (ret)
1399                         goto err_unregister;
1400         }
1401
1402         return 0;
1403
1404 err_unregister:
1405         led_classdev_unregister(&aled->cdev);
1406         return ret;
1407 }
1408
1409 static void
1410 ar8327_led_unregister(struct ar8327_led *aled)
1411 {
1412         if (aled->mode == AR8327_LED_MODE_HW)
1413                 device_remove_file(aled->cdev.dev, &dev_attr_enable_hw_mode);
1414
1415         led_classdev_unregister(&aled->cdev);
1416         cancel_work_sync(&aled->led_work);
1417 }
1418
1419 static int
1420 ar8327_led_create(struct ar8xxx_priv *priv,
1421                   const struct ar8327_led_info *led_info)
1422 {
1423         struct ar8327_data *data = priv->chip_data;
1424         struct ar8327_led *aled;
1425         int ret;
1426
1427         if (!IS_ENABLED(CONFIG_AR8216_PHY_LEDS))
1428                 return 0;
1429
1430         if (!led_info->name)
1431                 return -EINVAL;
1432
1433         if (led_info->led_num >= AR8327_NUM_LEDS)
1434                 return -EINVAL;
1435
1436         aled = kzalloc(sizeof(*aled) + strlen(led_info->name) + 1,
1437                        GFP_KERNEL);
1438         if (!aled)
1439                 return -ENOMEM;
1440
1441         aled->sw_priv = priv;
1442         aled->led_num = led_info->led_num;
1443         aled->active_low = led_info->active_low;
1444         aled->mode = led_info->mode;
1445
1446         if (aled->mode == AR8327_LED_MODE_HW)
1447                 aled->enable_hw_mode = true;
1448
1449         aled->name = (char *)(aled + 1);
1450         strcpy(aled->name, led_info->name);
1451
1452         aled->cdev.name = aled->name;
1453         aled->cdev.brightness_set = ar8327_led_set_brightness;
1454         aled->cdev.blink_set = ar8327_led_blink_set;
1455         aled->cdev.default_trigger = led_info->default_trigger;
1456
1457         spin_lock_init(&aled->lock);
1458         mutex_init(&aled->mutex);
1459         INIT_WORK(&aled->led_work, ar8327_led_work_func);
1460
1461         ret = ar8327_led_register(priv, aled);
1462         if (ret)
1463                 goto err_free;
1464
1465         data->leds[data->num_leds++] = aled;
1466
1467         return 0;
1468
1469 err_free:
1470         kfree(aled);
1471         return ret;
1472 }
1473
1474 static void
1475 ar8327_led_destroy(struct ar8327_led *aled)
1476 {
1477         ar8327_led_unregister(aled);
1478         kfree(aled);
1479 }
1480
1481 static void
1482 ar8327_leds_init(struct ar8xxx_priv *priv)
1483 {
1484         struct ar8327_data *data = priv->chip_data;
1485         unsigned i;
1486
1487         if (!IS_ENABLED(CONFIG_AR8216_PHY_LEDS))
1488                 return;
1489
1490         for (i = 0; i < data->num_leds; i++) {
1491                 struct ar8327_led *aled;
1492
1493                 aled = data->leds[i];
1494
1495                 if (aled->enable_hw_mode)
1496                         aled->pattern = AR8327_LED_PATTERN_RULE;
1497                 else
1498                         aled->pattern = AR8327_LED_PATTERN_OFF;
1499
1500                 ar8327_set_led_pattern(priv, aled->led_num, aled->pattern);
1501         }
1502 }
1503
1504 static void
1505 ar8327_leds_cleanup(struct ar8xxx_priv *priv)
1506 {
1507         struct ar8327_data *data = priv->chip_data;
1508         unsigned i;
1509
1510         if (!IS_ENABLED(CONFIG_AR8216_PHY_LEDS))
1511                 return;
1512
1513         for (i = 0; i < data->num_leds; i++) {
1514                 struct ar8327_led *aled;
1515
1516                 aled = data->leds[i];
1517                 ar8327_led_destroy(aled);
1518         }
1519
1520         kfree(data->leds);
1521 }
1522
1523 static int
1524 ar8327_hw_config_pdata(struct ar8xxx_priv *priv,
1525                        struct ar8327_platform_data *pdata)
1526 {
1527         struct ar8327_led_cfg *led_cfg;
1528         struct ar8327_data *data = priv->chip_data;
1529         u32 pos, new_pos;
1530         u32 t;
1531
1532         if (!pdata)
1533                 return -EINVAL;
1534
1535         priv->get_port_link = pdata->get_port_link;
1536
1537         data->port0_status = ar8327_get_port_init_status(&pdata->port0_cfg);
1538         data->port6_status = ar8327_get_port_init_status(&pdata->port6_cfg);
1539
1540         t = ar8327_get_pad_cfg(pdata->pad0_cfg);
1541         if (chip_is_ar8337(priv))
1542                 t |= AR8337_PAD_MAC06_EXCHANGE_EN;
1543
1544         priv->write(priv, AR8327_REG_PAD0_MODE, t);
1545         t = ar8327_get_pad_cfg(pdata->pad5_cfg);
1546         priv->write(priv, AR8327_REG_PAD5_MODE, t);
1547         t = ar8327_get_pad_cfg(pdata->pad6_cfg);
1548         priv->write(priv, AR8327_REG_PAD6_MODE, t);
1549
1550         pos = priv->read(priv, AR8327_REG_POWER_ON_STRIP);
1551         new_pos = pos;
1552
1553         led_cfg = pdata->led_cfg;
1554         if (led_cfg) {
1555                 if (led_cfg->open_drain)
1556                         new_pos |= AR8327_POWER_ON_STRIP_LED_OPEN_EN;
1557                 else
1558                         new_pos &= ~AR8327_POWER_ON_STRIP_LED_OPEN_EN;
1559
1560                 priv->write(priv, AR8327_REG_LED_CTRL0, led_cfg->led_ctrl0);
1561                 priv->write(priv, AR8327_REG_LED_CTRL1, led_cfg->led_ctrl1);
1562                 priv->write(priv, AR8327_REG_LED_CTRL2, led_cfg->led_ctrl2);
1563                 priv->write(priv, AR8327_REG_LED_CTRL3, led_cfg->led_ctrl3);
1564
1565                 if (new_pos != pos)
1566                         new_pos |= AR8327_POWER_ON_STRIP_POWER_ON_SEL;
1567         }
1568
1569         if (pdata->sgmii_cfg) {
1570                 t = pdata->sgmii_cfg->sgmii_ctrl;
1571                 if (priv->chip_rev == 1)
1572                         t |= AR8327_SGMII_CTRL_EN_PLL |
1573                              AR8327_SGMII_CTRL_EN_RX |
1574                              AR8327_SGMII_CTRL_EN_TX;
1575                 else
1576                         t &= ~(AR8327_SGMII_CTRL_EN_PLL |
1577                                AR8327_SGMII_CTRL_EN_RX |
1578                                AR8327_SGMII_CTRL_EN_TX);
1579
1580                 priv->write(priv, AR8327_REG_SGMII_CTRL, t);
1581
1582                 if (pdata->sgmii_cfg->serdes_aen)
1583                         new_pos &= ~AR8327_POWER_ON_STRIP_SERDES_AEN;
1584                 else
1585                         new_pos |= AR8327_POWER_ON_STRIP_SERDES_AEN;
1586         }
1587
1588         priv->write(priv, AR8327_REG_POWER_ON_STRIP, new_pos);
1589
1590         if (pdata->leds && pdata->num_leds) {
1591                 int i;
1592
1593                 data->leds = kzalloc(pdata->num_leds * sizeof(void *),
1594                                      GFP_KERNEL);
1595                 if (!data->leds)
1596                         return -ENOMEM;
1597
1598                 for (i = 0; i < pdata->num_leds; i++)
1599                         ar8327_led_create(priv, &pdata->leds[i]);
1600         }
1601
1602         return 0;
1603 }
1604
1605 #ifdef CONFIG_OF
1606 static int
1607 ar8327_hw_config_of(struct ar8xxx_priv *priv, struct device_node *np)
1608 {
1609         struct ar8327_data *data = priv->chip_data;
1610         const __be32 *paddr;
1611         int len;
1612         int i;
1613
1614         paddr = of_get_property(np, "qca,ar8327-initvals", &len);
1615         if (!paddr || len < (2 * sizeof(*paddr)))
1616                 return -EINVAL;
1617
1618         len /= sizeof(*paddr);
1619
1620         for (i = 0; i < len - 1; i += 2) {
1621                 u32 reg;
1622                 u32 val;
1623
1624                 reg = be32_to_cpup(paddr + i);
1625                 val = be32_to_cpup(paddr + i + 1);
1626
1627                 switch (reg) {
1628                 case AR8327_REG_PORT_STATUS(0):
1629                         data->port0_status = val;
1630                         break;
1631                 case AR8327_REG_PORT_STATUS(6):
1632                         data->port6_status = val;
1633                         break;
1634                 default:
1635                         priv->write(priv, reg, val);
1636                         break;
1637                 }
1638         }
1639
1640         return 0;
1641 }
1642 #else
1643 static inline int
1644 ar8327_hw_config_of(struct ar8xxx_priv *priv, struct device_node *np)
1645 {
1646         return -EINVAL;
1647 }
1648 #endif
1649
1650 static int
1651 ar8327_hw_init(struct ar8xxx_priv *priv)
1652 {
1653         int ret;
1654
1655         priv->chip_data = kzalloc(sizeof(struct ar8327_data), GFP_KERNEL);
1656         if (!priv->chip_data)
1657                 return -ENOMEM;
1658
1659         if (priv->phy->dev.of_node)
1660                 ret = ar8327_hw_config_of(priv, priv->phy->dev.of_node);
1661         else
1662                 ret = ar8327_hw_config_pdata(priv,
1663                                              priv->phy->dev.platform_data);
1664
1665         if (ret)
1666                 return ret;
1667
1668         ar8327_leds_init(priv);
1669
1670         ar8xxx_phy_init(priv);
1671
1672         return 0;
1673 }
1674
1675 static void
1676 ar8327_cleanup(struct ar8xxx_priv *priv)
1677 {
1678         ar8327_leds_cleanup(priv);
1679 }
1680
1681 static void
1682 ar8327_init_globals(struct ar8xxx_priv *priv)
1683 {
1684         u32 t;
1685
1686         /* enable CPU port and disable mirror port */
1687         t = AR8327_FWD_CTRL0_CPU_PORT_EN |
1688             AR8327_FWD_CTRL0_MIRROR_PORT;
1689         priv->write(priv, AR8327_REG_FWD_CTRL0, t);
1690
1691         /* forward multicast and broadcast frames to CPU */
1692         t = (AR8327_PORTS_ALL << AR8327_FWD_CTRL1_UC_FLOOD_S) |
1693             (AR8327_PORTS_ALL << AR8327_FWD_CTRL1_MC_FLOOD_S) |
1694             (AR8327_PORTS_ALL << AR8327_FWD_CTRL1_BC_FLOOD_S);
1695         priv->write(priv, AR8327_REG_FWD_CTRL1, t);
1696
1697         /* enable jumbo frames */
1698         ar8xxx_rmw(priv, AR8327_REG_MAX_FRAME_SIZE,
1699                    AR8327_MAX_FRAME_SIZE_MTU, 9018 + 8 + 2);
1700
1701         /* Enable MIB counters */
1702         ar8xxx_reg_set(priv, AR8327_REG_MODULE_EN,
1703                        AR8327_MODULE_EN_MIB);
1704
1705         /* Disable EEE on all ports due to stability issues */
1706         t = priv->read(priv, AR8327_REG_EEE_CTRL);
1707         t |= AR8327_EEE_CTRL_DISABLE_PHY(0) |
1708              AR8327_EEE_CTRL_DISABLE_PHY(1) |
1709              AR8327_EEE_CTRL_DISABLE_PHY(2) |
1710              AR8327_EEE_CTRL_DISABLE_PHY(3) |
1711              AR8327_EEE_CTRL_DISABLE_PHY(4);
1712         priv->write(priv, AR8327_REG_EEE_CTRL, t);
1713 }
1714
1715 static void
1716 ar8327_init_port(struct ar8xxx_priv *priv, int port)
1717 {
1718         struct ar8327_data *data = priv->chip_data;
1719         u32 t;
1720
1721         if (port == AR8216_PORT_CPU)
1722                 t = data->port0_status;
1723         else if (port == 6)
1724                 t = data->port6_status;
1725         else
1726                 t = AR8216_PORT_STATUS_LINK_AUTO;
1727
1728         priv->write(priv, AR8327_REG_PORT_STATUS(port), t);
1729         priv->write(priv, AR8327_REG_PORT_HEADER(port), 0);
1730
1731         t = 1 << AR8327_PORT_VLAN0_DEF_SVID_S;
1732         t |= 1 << AR8327_PORT_VLAN0_DEF_CVID_S;
1733         priv->write(priv, AR8327_REG_PORT_VLAN0(port), t);
1734
1735         t = AR8327_PORT_VLAN1_OUT_MODE_UNTOUCH << AR8327_PORT_VLAN1_OUT_MODE_S;
1736         priv->write(priv, AR8327_REG_PORT_VLAN1(port), t);
1737
1738         t = AR8327_PORT_LOOKUP_LEARN;
1739         t |= AR8216_PORT_STATE_FORWARD << AR8327_PORT_LOOKUP_STATE_S;
1740         priv->write(priv, AR8327_REG_PORT_LOOKUP(port), t);
1741 }
1742
1743 static u32
1744 ar8327_read_port_status(struct ar8xxx_priv *priv, int port)
1745 {
1746         return priv->read(priv, AR8327_REG_PORT_STATUS(port));
1747 }
1748
1749 static int
1750 ar8327_atu_flush(struct ar8xxx_priv *priv)
1751 {
1752         int ret;
1753
1754         ret = ar8216_wait_bit(priv, AR8327_REG_ATU_FUNC,
1755                               AR8327_ATU_FUNC_BUSY, 0);
1756         if (!ret)
1757                 priv->write(priv, AR8327_REG_ATU_FUNC,
1758                             AR8327_ATU_FUNC_OP_FLUSH);
1759
1760         return ret;
1761 }
1762
1763 static void
1764 ar8327_vtu_op(struct ar8xxx_priv *priv, u32 op, u32 val)
1765 {
1766         if (ar8216_wait_bit(priv, AR8327_REG_VTU_FUNC1,
1767                             AR8327_VTU_FUNC1_BUSY, 0))
1768                 return;
1769
1770         if ((op & AR8327_VTU_FUNC1_OP) == AR8327_VTU_FUNC1_OP_LOAD)
1771                 priv->write(priv, AR8327_REG_VTU_FUNC0, val);
1772
1773         op |= AR8327_VTU_FUNC1_BUSY;
1774         priv->write(priv, AR8327_REG_VTU_FUNC1, op);
1775 }
1776
1777 static void
1778 ar8327_vtu_flush(struct ar8xxx_priv *priv)
1779 {
1780         ar8327_vtu_op(priv, AR8327_VTU_FUNC1_OP_FLUSH, 0);
1781 }
1782
1783 static void
1784 ar8327_vtu_load_vlan(struct ar8xxx_priv *priv, u32 vid, u32 port_mask)
1785 {
1786         u32 op;
1787         u32 val;
1788         int i;
1789
1790         op = AR8327_VTU_FUNC1_OP_LOAD | (vid << AR8327_VTU_FUNC1_VID_S);
1791         val = AR8327_VTU_FUNC0_VALID | AR8327_VTU_FUNC0_IVL;
1792         for (i = 0; i < AR8327_NUM_PORTS; i++) {
1793                 u32 mode;
1794
1795                 if ((port_mask & BIT(i)) == 0)
1796                         mode = AR8327_VTU_FUNC0_EG_MODE_NOT;
1797                 else if (priv->vlan == 0)
1798                         mode = AR8327_VTU_FUNC0_EG_MODE_KEEP;
1799                 else if ((priv->vlan_tagged & BIT(i)) || (priv->vlan_id[priv->pvid[i]] != vid))
1800                         mode = AR8327_VTU_FUNC0_EG_MODE_TAG;
1801                 else
1802                         mode = AR8327_VTU_FUNC0_EG_MODE_UNTAG;
1803
1804                 val |= mode << AR8327_VTU_FUNC0_EG_MODE_S(i);
1805         }
1806         ar8327_vtu_op(priv, op, val);
1807 }
1808
1809 static void
1810 ar8327_setup_port(struct ar8xxx_priv *priv, int port, u32 members)
1811 {
1812         u32 t;
1813         u32 egress, ingress;
1814         u32 pvid = priv->vlan_id[priv->pvid[port]];
1815
1816         if (priv->vlan) {
1817                 egress = AR8327_PORT_VLAN1_OUT_MODE_UNMOD;
1818                 ingress = AR8216_IN_SECURE;
1819         } else {
1820                 egress = AR8327_PORT_VLAN1_OUT_MODE_UNTOUCH;
1821                 ingress = AR8216_IN_PORT_ONLY;
1822         }
1823
1824         t = pvid << AR8327_PORT_VLAN0_DEF_SVID_S;
1825         t |= pvid << AR8327_PORT_VLAN0_DEF_CVID_S;
1826         priv->write(priv, AR8327_REG_PORT_VLAN0(port), t);
1827
1828         t = AR8327_PORT_VLAN1_PORT_VLAN_PROP;
1829         t |= egress << AR8327_PORT_VLAN1_OUT_MODE_S;
1830         priv->write(priv, AR8327_REG_PORT_VLAN1(port), t);
1831
1832         t = members;
1833         t |= AR8327_PORT_LOOKUP_LEARN;
1834         t |= ingress << AR8327_PORT_LOOKUP_IN_MODE_S;
1835         t |= AR8216_PORT_STATE_FORWARD << AR8327_PORT_LOOKUP_STATE_S;
1836         priv->write(priv, AR8327_REG_PORT_LOOKUP(port), t);
1837 }
1838
1839 static const struct ar8xxx_chip ar8327_chip = {
1840         .caps = AR8XXX_CAP_GIGE | AR8XXX_CAP_MIB_COUNTERS,
1841         .config_at_probe = true,
1842         .mii_lo_first = true,
1843
1844         .reg_port_stats_start = 0x1000,
1845         .reg_port_stats_length = 0x100,
1846
1847         .hw_init = ar8327_hw_init,
1848         .cleanup = ar8327_cleanup,
1849         .init_globals = ar8327_init_globals,
1850         .init_port = ar8327_init_port,
1851         .setup_port = ar8327_setup_port,
1852         .read_port_status = ar8327_read_port_status,
1853         .atu_flush = ar8327_atu_flush,
1854         .vtu_flush = ar8327_vtu_flush,
1855         .vtu_load_vlan = ar8327_vtu_load_vlan,
1856         .phy_fixup = ar8327_phy_fixup,
1857         .set_mirror_regs = ar8327_set_mirror_regs,
1858
1859         .num_mibs = ARRAY_SIZE(ar8236_mibs),
1860         .mib_decs = ar8236_mibs,
1861         .mib_func = AR8327_REG_MIB_FUNC
1862 };
1863
1864 static int
1865 ar8xxx_sw_set_vlan(struct switch_dev *dev, const struct switch_attr *attr,
1866                    struct switch_val *val)
1867 {
1868         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1869         priv->vlan = !!val->value.i;
1870         return 0;
1871 }
1872
1873 static int
1874 ar8xxx_sw_get_vlan(struct switch_dev *dev, const struct switch_attr *attr,
1875                    struct switch_val *val)
1876 {
1877         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1878         val->value.i = priv->vlan;
1879         return 0;
1880 }
1881
1882
1883 static int
1884 ar8xxx_sw_set_pvid(struct switch_dev *dev, int port, int vlan)
1885 {
1886         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1887
1888         /* make sure no invalid PVIDs get set */
1889
1890         if (vlan >= dev->vlans)
1891                 return -EINVAL;
1892
1893         priv->pvid[port] = vlan;
1894         return 0;
1895 }
1896
1897 static int
1898 ar8xxx_sw_get_pvid(struct switch_dev *dev, int port, int *vlan)
1899 {
1900         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1901         *vlan = priv->pvid[port];
1902         return 0;
1903 }
1904
1905 static int
1906 ar8xxx_sw_set_vid(struct switch_dev *dev, const struct switch_attr *attr,
1907                   struct switch_val *val)
1908 {
1909         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1910         priv->vlan_id[val->port_vlan] = val->value.i;
1911         return 0;
1912 }
1913
1914 static int
1915 ar8xxx_sw_get_vid(struct switch_dev *dev, const struct switch_attr *attr,
1916                   struct switch_val *val)
1917 {
1918         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1919         val->value.i = priv->vlan_id[val->port_vlan];
1920         return 0;
1921 }
1922
1923 static int
1924 ar8xxx_sw_get_port_link(struct switch_dev *dev, int port,
1925                         struct switch_port_link *link)
1926 {
1927         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1928
1929         ar8216_read_port_link(priv, port, link);
1930         return 0;
1931 }
1932
1933 static int
1934 ar8xxx_sw_get_ports(struct switch_dev *dev, struct switch_val *val)
1935 {
1936         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1937         u8 ports = priv->vlan_table[val->port_vlan];
1938         int i;
1939
1940         val->len = 0;
1941         for (i = 0; i < dev->ports; i++) {
1942                 struct switch_port *p;
1943
1944                 if (!(ports & (1 << i)))
1945                         continue;
1946
1947                 p = &val->value.ports[val->len++];
1948                 p->id = i;
1949                 if (priv->vlan_tagged & (1 << i))
1950                         p->flags = (1 << SWITCH_PORT_FLAG_TAGGED);
1951                 else
1952                         p->flags = 0;
1953         }
1954         return 0;
1955 }
1956
1957 static int
1958 ar8327_sw_get_ports(struct switch_dev *dev, struct switch_val *val)
1959 {
1960         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1961         u8 ports = priv->vlan_table[val->port_vlan];
1962         int i;
1963
1964         val->len = 0;
1965         for (i = 0; i < dev->ports; i++) {
1966                 struct switch_port *p;
1967
1968                 if (!(ports & (1 << i)))
1969                         continue;
1970
1971                 p = &val->value.ports[val->len++];
1972                 p->id = i;
1973                 if ((priv->vlan_tagged & (1 << i)) || (priv->pvid[i] != val->port_vlan))
1974                         p->flags = (1 << SWITCH_PORT_FLAG_TAGGED);
1975                 else
1976                         p->flags = 0;
1977         }
1978         return 0;
1979 }
1980
1981 static int
1982 ar8xxx_sw_set_ports(struct switch_dev *dev, struct switch_val *val)
1983 {
1984         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1985         u8 *vt = &priv->vlan_table[val->port_vlan];
1986         int i, j;
1987
1988         *vt = 0;
1989         for (i = 0; i < val->len; i++) {
1990                 struct switch_port *p = &val->value.ports[i];
1991
1992                 if (p->flags & (1 << SWITCH_PORT_FLAG_TAGGED)) {
1993                         priv->vlan_tagged |= (1 << p->id);
1994                 } else {
1995                         priv->vlan_tagged &= ~(1 << p->id);
1996                         priv->pvid[p->id] = val->port_vlan;
1997
1998                         /* make sure that an untagged port does not
1999                          * appear in other vlans */
2000                         for (j = 0; j < AR8X16_MAX_VLANS; j++) {
2001                                 if (j == val->port_vlan)
2002                                         continue;
2003                                 priv->vlan_table[j] &= ~(1 << p->id);
2004                         }
2005                 }
2006
2007                 *vt |= 1 << p->id;
2008         }
2009         return 0;
2010 }
2011
2012 static int
2013 ar8327_sw_set_ports(struct switch_dev *dev, struct switch_val *val)
2014 {
2015         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
2016         u8 *vt = &priv->vlan_table[val->port_vlan];
2017         int i;
2018
2019         *vt = 0;
2020         for (i = 0; i < val->len; i++) {
2021                 struct switch_port *p = &val->value.ports[i];
2022
2023                 if (p->flags & (1 << SWITCH_PORT_FLAG_TAGGED)) {
2024                         if (val->port_vlan == priv->pvid[p->id]) {
2025                                 priv->vlan_tagged |= (1 << p->id);
2026                         }
2027                 } else {
2028                         priv->vlan_tagged &= ~(1 << p->id);
2029                         priv->pvid[p->id] = val->port_vlan;
2030                 }
2031
2032                 *vt |= 1 << p->id;
2033         }
2034         return 0;
2035 }
2036
2037 static void
2038 ar8327_set_mirror_regs(struct ar8xxx_priv *priv)
2039 {
2040         int port;
2041
2042         /* reset all mirror registers */
2043         ar8xxx_rmw(priv, AR8327_REG_FWD_CTRL0,
2044                    AR8327_FWD_CTRL0_MIRROR_PORT,
2045                    (0xF << AR8327_FWD_CTRL0_MIRROR_PORT_S));
2046         for (port = 0; port < AR8327_NUM_PORTS; port++) {
2047                 ar8xxx_rmw(priv, AR8327_REG_PORT_LOOKUP(port),
2048                            AR8327_PORT_LOOKUP_ING_MIRROR_EN,
2049                            0);
2050
2051                 ar8xxx_rmw(priv, AR8327_REG_PORT_HOL_CTRL1(port),
2052                            AR8327_PORT_HOL_CTRL1_EG_MIRROR_EN,
2053                            0);
2054         }
2055
2056         /* now enable mirroring if necessary */
2057         if (priv->source_port >= AR8327_NUM_PORTS ||
2058             priv->monitor_port >= AR8327_NUM_PORTS ||
2059             priv->source_port == priv->monitor_port) {
2060                 return;
2061         }
2062
2063         ar8xxx_rmw(priv, AR8327_REG_FWD_CTRL0,
2064                    AR8327_FWD_CTRL0_MIRROR_PORT,
2065                    (priv->monitor_port << AR8327_FWD_CTRL0_MIRROR_PORT_S));
2066
2067         if (priv->mirror_rx)
2068                 ar8xxx_rmw(priv, AR8327_REG_PORT_LOOKUP(priv->source_port),
2069                            AR8327_PORT_LOOKUP_ING_MIRROR_EN,
2070                            AR8327_PORT_LOOKUP_ING_MIRROR_EN);
2071
2072         if (priv->mirror_tx)
2073                 ar8xxx_rmw(priv, AR8327_REG_PORT_HOL_CTRL1(priv->source_port),
2074                            AR8327_PORT_HOL_CTRL1_EG_MIRROR_EN,
2075                            AR8327_PORT_HOL_CTRL1_EG_MIRROR_EN);
2076 }
2077
2078 static void
2079 ar8216_set_mirror_regs(struct ar8xxx_priv *priv)
2080 {
2081         int port;
2082
2083         /* reset all mirror registers */
2084         ar8xxx_rmw(priv, AR8216_REG_GLOBAL_CPUPORT,
2085                    AR8216_GLOBAL_CPUPORT_MIRROR_PORT,
2086                    (0xF << AR8216_GLOBAL_CPUPORT_MIRROR_PORT_S));
2087         for (port = 0; port < AR8216_NUM_PORTS; port++) {
2088                 ar8xxx_rmw(priv, AR8216_REG_PORT_CTRL(port),
2089                            AR8216_PORT_CTRL_MIRROR_RX,
2090                            0);
2091
2092                 ar8xxx_rmw(priv, AR8216_REG_PORT_CTRL(port),
2093                            AR8216_PORT_CTRL_MIRROR_TX,
2094                            0);
2095         }
2096
2097         /* now enable mirroring if necessary */
2098         if (priv->source_port >= AR8216_NUM_PORTS ||
2099             priv->monitor_port >= AR8216_NUM_PORTS ||
2100             priv->source_port == priv->monitor_port) {
2101                 return;
2102         }
2103
2104         ar8xxx_rmw(priv, AR8216_REG_GLOBAL_CPUPORT,
2105                    AR8216_GLOBAL_CPUPORT_MIRROR_PORT,
2106                    (priv->monitor_port << AR8216_GLOBAL_CPUPORT_MIRROR_PORT_S));
2107
2108         if (priv->mirror_rx)
2109                 ar8xxx_rmw(priv, AR8216_REG_PORT_CTRL(priv->source_port),
2110                            AR8216_PORT_CTRL_MIRROR_RX,
2111                            AR8216_PORT_CTRL_MIRROR_RX);
2112
2113         if (priv->mirror_tx)
2114                 ar8xxx_rmw(priv, AR8216_REG_PORT_CTRL(priv->source_port),
2115                            AR8216_PORT_CTRL_MIRROR_TX,
2116                            AR8216_PORT_CTRL_MIRROR_TX);
2117 }
2118
2119 static int
2120 ar8xxx_sw_hw_apply(struct switch_dev *dev)
2121 {
2122         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
2123         u8 portmask[AR8X16_MAX_PORTS];
2124         int i, j;
2125
2126         mutex_lock(&priv->reg_mutex);
2127         /* flush all vlan translation unit entries */
2128         priv->chip->vtu_flush(priv);
2129
2130         memset(portmask, 0, sizeof(portmask));
2131         if (!priv->init) {
2132                 /* calculate the port destination masks and load vlans
2133                  * into the vlan translation unit */
2134                 for (j = 0; j < AR8X16_MAX_VLANS; j++) {
2135                         u8 vp = priv->vlan_table[j];
2136
2137                         if (!vp)
2138                                 continue;
2139
2140                         for (i = 0; i < dev->ports; i++) {
2141                                 u8 mask = (1 << i);
2142                                 if (vp & mask)
2143                                         portmask[i] |= vp & ~mask;
2144                         }
2145
2146                         priv->chip->vtu_load_vlan(priv, priv->vlan_id[j],
2147                                                  priv->vlan_table[j]);
2148                 }
2149         } else {
2150                 /* vlan disabled:
2151                  * isolate all ports, but connect them to the cpu port */
2152                 for (i = 0; i < dev->ports; i++) {
2153                         if (i == AR8216_PORT_CPU)
2154                                 continue;
2155
2156                         portmask[i] = 1 << AR8216_PORT_CPU;
2157                         portmask[AR8216_PORT_CPU] |= (1 << i);
2158                 }
2159         }
2160
2161         /* update the port destination mask registers and tag settings */
2162         for (i = 0; i < dev->ports; i++) {
2163                 priv->chip->setup_port(priv, i, portmask[i]);
2164         }
2165
2166         priv->chip->set_mirror_regs(priv);
2167
2168         mutex_unlock(&priv->reg_mutex);
2169         return 0;
2170 }
2171
2172 static int
2173 ar8xxx_sw_reset_switch(struct switch_dev *dev)
2174 {
2175         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
2176         int i;
2177
2178         mutex_lock(&priv->reg_mutex);
2179         memset(&priv->vlan, 0, sizeof(struct ar8xxx_priv) -
2180                 offsetof(struct ar8xxx_priv, vlan));
2181
2182         for (i = 0; i < AR8X16_MAX_VLANS; i++)
2183                 priv->vlan_id[i] = i;
2184
2185         /* Configure all ports */
2186         for (i = 0; i < dev->ports; i++)
2187                 priv->chip->init_port(priv, i);
2188
2189         priv->mirror_rx = false;
2190         priv->mirror_tx = false;
2191         priv->source_port = 0;
2192         priv->monitor_port = 0;
2193
2194         priv->chip->init_globals(priv);
2195
2196         mutex_unlock(&priv->reg_mutex);
2197
2198         return ar8xxx_sw_hw_apply(dev);
2199 }
2200
2201 static int
2202 ar8xxx_sw_set_reset_mibs(struct switch_dev *dev,
2203                          const struct switch_attr *attr,
2204                          struct switch_val *val)
2205 {
2206         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
2207         unsigned int len;
2208         int ret;
2209
2210         if (!ar8xxx_has_mib_counters(priv))
2211                 return -EOPNOTSUPP;
2212
2213         mutex_lock(&priv->mib_lock);
2214
2215         len = priv->dev.ports * priv->chip->num_mibs *
2216               sizeof(*priv->mib_stats);
2217         memset(priv->mib_stats, '\0', len);
2218         ret = ar8xxx_mib_flush(priv);
2219         if (ret)
2220                 goto unlock;
2221
2222         ret = 0;
2223
2224 unlock:
2225         mutex_unlock(&priv->mib_lock);
2226         return ret;
2227 }
2228
2229 static int
2230 ar8xxx_sw_set_mirror_rx_enable(struct switch_dev *dev,
2231                                const struct switch_attr *attr,
2232                                struct switch_val *val)
2233 {
2234         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
2235
2236         mutex_lock(&priv->reg_mutex);
2237         priv->mirror_rx = !!val->value.i;
2238         priv->chip->set_mirror_regs(priv);
2239         mutex_unlock(&priv->reg_mutex);
2240
2241         return 0;
2242 }
2243
2244 static int
2245 ar8xxx_sw_get_mirror_rx_enable(struct switch_dev *dev,
2246                                const struct switch_attr *attr,
2247                                struct switch_val *val)
2248 {
2249         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
2250         val->value.i = priv->mirror_rx;
2251         return 0;
2252 }
2253
2254 static int
2255 ar8xxx_sw_set_mirror_tx_enable(struct switch_dev *dev,
2256                                const struct switch_attr *attr,
2257                                struct switch_val *val)
2258 {
2259         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
2260
2261         mutex_lock(&priv->reg_mutex);
2262         priv->mirror_tx = !!val->value.i;
2263         priv->chip->set_mirror_regs(priv);
2264         mutex_unlock(&priv->reg_mutex);
2265
2266         return 0;
2267 }
2268
2269 static int
2270 ar8xxx_sw_get_mirror_tx_enable(struct switch_dev *dev,
2271                                const struct switch_attr *attr,
2272                                struct switch_val *val)
2273 {
2274         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
2275         val->value.i = priv->mirror_tx;
2276         return 0;
2277 }
2278
2279 static int
2280 ar8xxx_sw_set_mirror_monitor_port(struct switch_dev *dev,
2281                                   const struct switch_attr *attr,
2282                                   struct switch_val *val)
2283 {
2284         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
2285
2286         mutex_lock(&priv->reg_mutex);
2287         priv->monitor_port = val->value.i;
2288         priv->chip->set_mirror_regs(priv);
2289         mutex_unlock(&priv->reg_mutex);
2290
2291         return 0;
2292 }
2293
2294 static int
2295 ar8xxx_sw_get_mirror_monitor_port(struct switch_dev *dev,
2296                                   const struct switch_attr *attr,
2297                                   struct switch_val *val)
2298 {
2299         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
2300         val->value.i = priv->monitor_port;
2301         return 0;
2302 }
2303
2304 static int
2305 ar8xxx_sw_set_mirror_source_port(struct switch_dev *dev,
2306                                  const struct switch_attr *attr,
2307                                  struct switch_val *val)
2308 {
2309         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
2310
2311         mutex_lock(&priv->reg_mutex);
2312         priv->source_port = val->value.i;
2313         priv->chip->set_mirror_regs(priv);
2314         mutex_unlock(&priv->reg_mutex);
2315
2316         return 0;
2317 }
2318
2319 static int
2320 ar8xxx_sw_get_mirror_source_port(struct switch_dev *dev,
2321                                  const struct switch_attr *attr,
2322                                  struct switch_val *val)
2323 {
2324         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
2325         val->value.i = priv->source_port;
2326         return 0;
2327 }
2328
2329 static int
2330 ar8xxx_sw_set_port_reset_mib(struct switch_dev *dev,
2331                              const struct switch_attr *attr,
2332                              struct switch_val *val)
2333 {
2334         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
2335         int port;
2336         int ret;
2337
2338         if (!ar8xxx_has_mib_counters(priv))
2339                 return -EOPNOTSUPP;
2340
2341         port = val->port_vlan;
2342         if (port >= dev->ports)
2343                 return -EINVAL;
2344
2345         mutex_lock(&priv->mib_lock);
2346         ret = ar8xxx_mib_capture(priv);
2347         if (ret)
2348                 goto unlock;
2349
2350         ar8xxx_mib_fetch_port_stat(priv, port, true);
2351
2352         ret = 0;
2353
2354 unlock:
2355         mutex_unlock(&priv->mib_lock);
2356         return ret;
2357 }
2358
2359 static int
2360 ar8xxx_sw_get_port_mib(struct switch_dev *dev,
2361                        const struct switch_attr *attr,
2362                        struct switch_val *val)
2363 {
2364         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
2365         const struct ar8xxx_chip *chip = priv->chip;
2366         u64 *mib_stats;
2367         int port;
2368         int ret;
2369         char *buf = priv->buf;
2370         int i, len = 0;
2371
2372         if (!ar8xxx_has_mib_counters(priv))
2373                 return -EOPNOTSUPP;
2374
2375         port = val->port_vlan;
2376         if (port >= dev->ports)
2377                 return -EINVAL;
2378
2379         mutex_lock(&priv->mib_lock);
2380         ret = ar8xxx_mib_capture(priv);
2381         if (ret)
2382                 goto unlock;
2383
2384         ar8xxx_mib_fetch_port_stat(priv, port, false);
2385
2386         len += snprintf(buf + len, sizeof(priv->buf) - len,
2387                         "Port %d MIB counters\n",
2388                         port);
2389
2390         mib_stats = &priv->mib_stats[port * chip->num_mibs];
2391         for (i = 0; i < chip->num_mibs; i++)
2392                 len += snprintf(buf + len, sizeof(priv->buf) - len,
2393                                 "%-12s: %llu\n",
2394                                 chip->mib_decs[i].name,
2395                                 mib_stats[i]);
2396
2397         val->value.s = buf;
2398         val->len = len;
2399
2400         ret = 0;
2401
2402 unlock:
2403         mutex_unlock(&priv->mib_lock);
2404         return ret;
2405 }
2406
2407 static struct switch_attr ar8xxx_sw_attr_globals[] = {
2408         {
2409                 .type = SWITCH_TYPE_INT,
2410                 .name = "enable_vlan",
2411                 .description = "Enable VLAN mode",
2412                 .set = ar8xxx_sw_set_vlan,
2413                 .get = ar8xxx_sw_get_vlan,
2414                 .max = 1
2415         },
2416         {
2417                 .type = SWITCH_TYPE_NOVAL,
2418                 .name = "reset_mibs",
2419                 .description = "Reset all MIB counters",
2420                 .set = ar8xxx_sw_set_reset_mibs,
2421         },
2422         {
2423                 .type = SWITCH_TYPE_INT,
2424                 .name = "enable_mirror_rx",
2425                 .description = "Enable mirroring of RX packets",
2426                 .set = ar8xxx_sw_set_mirror_rx_enable,
2427                 .get = ar8xxx_sw_get_mirror_rx_enable,
2428                 .max = 1
2429         },
2430         {
2431                 .type = SWITCH_TYPE_INT,
2432                 .name = "enable_mirror_tx",
2433                 .description = "Enable mirroring of TX packets",
2434                 .set = ar8xxx_sw_set_mirror_tx_enable,
2435                 .get = ar8xxx_sw_get_mirror_tx_enable,
2436                 .max = 1
2437         },
2438         {
2439                 .type = SWITCH_TYPE_INT,
2440                 .name = "mirror_monitor_port",
2441                 .description = "Mirror monitor port",
2442                 .set = ar8xxx_sw_set_mirror_monitor_port,
2443                 .get = ar8xxx_sw_get_mirror_monitor_port,
2444                 .max = AR8216_NUM_PORTS - 1
2445         },
2446         {
2447                 .type = SWITCH_TYPE_INT,
2448                 .name = "mirror_source_port",
2449                 .description = "Mirror source port",
2450                 .set = ar8xxx_sw_set_mirror_source_port,
2451                 .get = ar8xxx_sw_get_mirror_source_port,
2452                 .max = AR8216_NUM_PORTS - 1
2453         },
2454 };
2455
2456 static struct switch_attr ar8327_sw_attr_globals[] = {
2457         {
2458                 .type = SWITCH_TYPE_INT,
2459                 .name = "enable_vlan",
2460                 .description = "Enable VLAN mode",
2461                 .set = ar8xxx_sw_set_vlan,
2462                 .get = ar8xxx_sw_get_vlan,
2463                 .max = 1
2464         },
2465         {
2466                 .type = SWITCH_TYPE_NOVAL,
2467                 .name = "reset_mibs",
2468                 .description = "Reset all MIB counters",
2469                 .set = ar8xxx_sw_set_reset_mibs,
2470         },
2471         {
2472                 .type = SWITCH_TYPE_INT,
2473                 .name = "enable_mirror_rx",
2474                 .description = "Enable mirroring of RX packets",
2475                 .set = ar8xxx_sw_set_mirror_rx_enable,
2476                 .get = ar8xxx_sw_get_mirror_rx_enable,
2477                 .max = 1
2478         },
2479         {
2480                 .type = SWITCH_TYPE_INT,
2481                 .name = "enable_mirror_tx",
2482                 .description = "Enable mirroring of TX packets",
2483                 .set = ar8xxx_sw_set_mirror_tx_enable,
2484                 .get = ar8xxx_sw_get_mirror_tx_enable,
2485                 .max = 1
2486         },
2487         {
2488                 .type = SWITCH_TYPE_INT,
2489                 .name = "mirror_monitor_port",
2490                 .description = "Mirror monitor port",
2491                 .set = ar8xxx_sw_set_mirror_monitor_port,
2492                 .get = ar8xxx_sw_get_mirror_monitor_port,
2493                 .max = AR8327_NUM_PORTS - 1
2494         },
2495         {
2496                 .type = SWITCH_TYPE_INT,
2497                 .name = "mirror_source_port",
2498                 .description = "Mirror source port",
2499                 .set = ar8xxx_sw_set_mirror_source_port,
2500                 .get = ar8xxx_sw_get_mirror_source_port,
2501                 .max = AR8327_NUM_PORTS - 1
2502         },
2503 };
2504
2505 static struct switch_attr ar8xxx_sw_attr_port[] = {
2506         {
2507                 .type = SWITCH_TYPE_NOVAL,
2508                 .name = "reset_mib",
2509                 .description = "Reset single port MIB counters",
2510                 .set = ar8xxx_sw_set_port_reset_mib,
2511         },
2512         {
2513                 .type = SWITCH_TYPE_STRING,
2514                 .name = "mib",
2515                 .description = "Get port's MIB counters",
2516                 .set = NULL,
2517                 .get = ar8xxx_sw_get_port_mib,
2518         },
2519 };
2520
2521 static struct switch_attr ar8xxx_sw_attr_vlan[] = {
2522         {
2523                 .type = SWITCH_TYPE_INT,
2524                 .name = "vid",
2525                 .description = "VLAN ID (0-4094)",
2526                 .set = ar8xxx_sw_set_vid,
2527                 .get = ar8xxx_sw_get_vid,
2528                 .max = 4094,
2529         },
2530 };
2531
2532 static const struct switch_dev_ops ar8xxx_sw_ops = {
2533         .attr_global = {
2534                 .attr = ar8xxx_sw_attr_globals,
2535                 .n_attr = ARRAY_SIZE(ar8xxx_sw_attr_globals),
2536         },
2537         .attr_port = {
2538                 .attr = ar8xxx_sw_attr_port,
2539                 .n_attr = ARRAY_SIZE(ar8xxx_sw_attr_port),
2540         },
2541         .attr_vlan = {
2542                 .attr = ar8xxx_sw_attr_vlan,
2543                 .n_attr = ARRAY_SIZE(ar8xxx_sw_attr_vlan),
2544         },
2545         .get_port_pvid = ar8xxx_sw_get_pvid,
2546         .set_port_pvid = ar8xxx_sw_set_pvid,
2547         .get_vlan_ports = ar8xxx_sw_get_ports,
2548         .set_vlan_ports = ar8xxx_sw_set_ports,
2549         .apply_config = ar8xxx_sw_hw_apply,
2550         .reset_switch = ar8xxx_sw_reset_switch,
2551         .get_port_link = ar8xxx_sw_get_port_link,
2552 };
2553
2554 static const struct switch_dev_ops ar8327_sw_ops = {
2555         .attr_global = {
2556                 .attr = ar8327_sw_attr_globals,
2557                 .n_attr = ARRAY_SIZE(ar8327_sw_attr_globals),
2558         },
2559         .attr_port = {
2560                 .attr = ar8xxx_sw_attr_port,
2561                 .n_attr = ARRAY_SIZE(ar8xxx_sw_attr_port),
2562         },
2563         .attr_vlan = {
2564                 .attr = ar8xxx_sw_attr_vlan,
2565                 .n_attr = ARRAY_SIZE(ar8xxx_sw_attr_vlan),
2566         },
2567         .get_port_pvid = ar8xxx_sw_get_pvid,
2568         .set_port_pvid = ar8xxx_sw_set_pvid,
2569         .get_vlan_ports = ar8327_sw_get_ports,
2570         .set_vlan_ports = ar8327_sw_set_ports,
2571         .apply_config = ar8xxx_sw_hw_apply,
2572         .reset_switch = ar8xxx_sw_reset_switch,
2573         .get_port_link = ar8xxx_sw_get_port_link,
2574 };
2575
2576 static int
2577 ar8xxx_id_chip(struct ar8xxx_priv *priv)
2578 {
2579         u32 val;
2580         u16 id;
2581         int i;
2582
2583         val = priv->read(priv, AR8216_REG_CTRL);
2584         if (val == ~0)
2585                 return -ENODEV;
2586
2587         id = val & (AR8216_CTRL_REVISION | AR8216_CTRL_VERSION);
2588         for (i = 0; i < AR8X16_PROBE_RETRIES; i++) {
2589                 u16 t;
2590
2591                 val = priv->read(priv, AR8216_REG_CTRL);
2592                 if (val == ~0)
2593                         return -ENODEV;
2594
2595                 t = val & (AR8216_CTRL_REVISION | AR8216_CTRL_VERSION);
2596                 if (t != id)
2597                         return -ENODEV;
2598         }
2599
2600         priv->chip_ver = (id & AR8216_CTRL_VERSION) >> AR8216_CTRL_VERSION_S;
2601         priv->chip_rev = (id & AR8216_CTRL_REVISION);
2602
2603         switch (priv->chip_ver) {
2604         case AR8XXX_VER_AR8216:
2605                 priv->chip = &ar8216_chip;
2606                 break;
2607         case AR8XXX_VER_AR8236:
2608                 priv->chip = &ar8236_chip;
2609                 break;
2610         case AR8XXX_VER_AR8316:
2611                 priv->chip = &ar8316_chip;
2612                 break;
2613         case AR8XXX_VER_AR8327:
2614                 priv->chip = &ar8327_chip;
2615                 break;
2616         case AR8XXX_VER_AR8337:
2617                 priv->chip = &ar8327_chip;
2618                 break;
2619         default:
2620                 pr_err("ar8216: Unknown Atheros device [ver=%d, rev=%d]\n",
2621                        priv->chip_ver, priv->chip_rev);
2622
2623                 return -ENODEV;
2624         }
2625
2626         return 0;
2627 }
2628
2629 static void
2630 ar8xxx_mib_work_func(struct work_struct *work)
2631 {
2632         struct ar8xxx_priv *priv;
2633         int err;
2634
2635         priv = container_of(work, struct ar8xxx_priv, mib_work.work);
2636
2637         mutex_lock(&priv->mib_lock);
2638
2639         err = ar8xxx_mib_capture(priv);
2640         if (err)
2641                 goto next_port;
2642
2643         ar8xxx_mib_fetch_port_stat(priv, priv->mib_next_port, false);
2644
2645 next_port:
2646         priv->mib_next_port++;
2647         if (priv->mib_next_port >= priv->dev.ports)
2648                 priv->mib_next_port = 0;
2649
2650         mutex_unlock(&priv->mib_lock);
2651         schedule_delayed_work(&priv->mib_work,
2652                               msecs_to_jiffies(AR8XXX_MIB_WORK_DELAY));
2653 }
2654
2655 static int
2656 ar8xxx_mib_init(struct ar8xxx_priv *priv)
2657 {
2658         unsigned int len;
2659
2660         if (!ar8xxx_has_mib_counters(priv))
2661                 return 0;
2662
2663         BUG_ON(!priv->chip->mib_decs || !priv->chip->num_mibs);
2664
2665         len = priv->dev.ports * priv->chip->num_mibs *
2666               sizeof(*priv->mib_stats);
2667         priv->mib_stats = kzalloc(len, GFP_KERNEL);
2668
2669         if (!priv->mib_stats)
2670                 return -ENOMEM;
2671
2672         return 0;
2673 }
2674
2675 static void
2676 ar8xxx_mib_start(struct ar8xxx_priv *priv)
2677 {
2678         if (!ar8xxx_has_mib_counters(priv))
2679                 return;
2680
2681         schedule_delayed_work(&priv->mib_work,
2682                               msecs_to_jiffies(AR8XXX_MIB_WORK_DELAY));
2683 }
2684
2685 static void
2686 ar8xxx_mib_stop(struct ar8xxx_priv *priv)
2687 {
2688         if (!ar8xxx_has_mib_counters(priv))
2689                 return;
2690
2691         cancel_delayed_work(&priv->mib_work);
2692 }
2693
2694 static struct ar8xxx_priv *
2695 ar8xxx_create(void)
2696 {
2697         struct ar8xxx_priv *priv;
2698
2699         priv = kzalloc(sizeof(struct ar8xxx_priv), GFP_KERNEL);
2700         if (priv == NULL)
2701                 return NULL;
2702
2703         mutex_init(&priv->reg_mutex);
2704         mutex_init(&priv->mib_lock);
2705         INIT_DELAYED_WORK(&priv->mib_work, ar8xxx_mib_work_func);
2706
2707         return priv;
2708 }
2709
2710 static void
2711 ar8xxx_free(struct ar8xxx_priv *priv)
2712 {
2713         if (priv->chip && priv->chip->cleanup)
2714                 priv->chip->cleanup(priv);
2715
2716         kfree(priv->chip_data);
2717         kfree(priv->mib_stats);
2718         kfree(priv);
2719 }
2720
2721 static struct ar8xxx_priv *
2722 ar8xxx_create_mii(struct mii_bus *bus)
2723 {
2724         struct ar8xxx_priv *priv;
2725
2726         priv = ar8xxx_create();
2727         if (priv) {
2728                 priv->mii_bus = bus;
2729                 priv->read = ar8xxx_mii_read;
2730                 priv->write = ar8xxx_mii_write;
2731                 priv->rmw = ar8xxx_mii_rmw;
2732         }
2733
2734         return priv;
2735 }
2736
2737 static int
2738 ar8xxx_probe_switch(struct ar8xxx_priv *priv)
2739 {
2740         struct switch_dev *swdev;
2741         int ret;
2742
2743         ret = ar8xxx_id_chip(priv);
2744         if (ret)
2745                 return ret;
2746
2747         swdev = &priv->dev;
2748         swdev->cpu_port = AR8216_PORT_CPU;
2749         swdev->ops = &ar8xxx_sw_ops;
2750
2751         if (chip_is_ar8316(priv)) {
2752                 swdev->name = "Atheros AR8316";
2753                 swdev->vlans = AR8X16_MAX_VLANS;
2754                 swdev->ports = AR8216_NUM_PORTS;
2755         } else if (chip_is_ar8236(priv)) {
2756                 swdev->name = "Atheros AR8236";
2757                 swdev->vlans = AR8216_NUM_VLANS;
2758                 swdev->ports = AR8216_NUM_PORTS;
2759         } else if (chip_is_ar8327(priv)) {
2760                 swdev->name = "Atheros AR8327";
2761                 swdev->vlans = AR8X16_MAX_VLANS;
2762                 swdev->ports = AR8327_NUM_PORTS;
2763                 swdev->ops = &ar8327_sw_ops;
2764         } else if (chip_is_ar8337(priv)) {
2765                 swdev->name = "Atheros AR8337";
2766                 swdev->vlans = AR8X16_MAX_VLANS;
2767                 swdev->ports = AR8327_NUM_PORTS;
2768                 swdev->ops = &ar8327_sw_ops;
2769         } else {
2770                 swdev->name = "Atheros AR8216";
2771                 swdev->vlans = AR8216_NUM_VLANS;
2772                 swdev->ports = AR8216_NUM_PORTS;
2773         }
2774
2775         ret = ar8xxx_mib_init(priv);
2776         if (ret)
2777                 return ret;
2778
2779         return 0;
2780 }
2781
2782 static int
2783 ar8xxx_start(struct ar8xxx_priv *priv)
2784 {
2785         int ret;
2786
2787         priv->init = true;
2788
2789         ret = priv->chip->hw_init(priv);
2790         if (ret)
2791                 return ret;
2792
2793         ret = ar8xxx_sw_reset_switch(&priv->dev);
2794         if (ret)
2795                 return ret;
2796
2797         priv->init = false;
2798
2799         ar8xxx_mib_start(priv);
2800
2801         return 0;
2802 }
2803
2804 static int
2805 ar8xxx_phy_config_init(struct phy_device *phydev)
2806 {
2807         struct ar8xxx_priv *priv = phydev->priv;
2808         struct net_device *dev = phydev->attached_dev;
2809         int ret;
2810
2811         if (WARN_ON(!priv))
2812                 return -ENODEV;
2813
2814         if (priv->chip->config_at_probe)
2815                 return ar8xxx_phy_check_aneg(phydev);
2816
2817         priv->phy = phydev;
2818
2819         if (phydev->addr != 0) {
2820                 if (chip_is_ar8316(priv)) {
2821                         /* switch device has been initialized, reinit */
2822                         priv->dev.ports = (AR8216_NUM_PORTS - 1);
2823                         priv->initialized = false;
2824                         priv->port4_phy = true;
2825                         ar8316_hw_init(priv);
2826                         return 0;
2827                 }
2828
2829                 return 0;
2830         }
2831
2832         ret = ar8xxx_start(priv);
2833         if (ret)
2834                 return ret;
2835
2836         /* VID fixup only needed on ar8216 */
2837         if (chip_is_ar8216(priv)) {
2838                 dev->phy_ptr = priv;
2839                 dev->priv_flags |= IFF_NO_IP_ALIGN;
2840                 dev->eth_mangle_rx = ar8216_mangle_rx;
2841                 dev->eth_mangle_tx = ar8216_mangle_tx;
2842         }
2843
2844         return 0;
2845 }
2846
2847 static int
2848 ar8xxx_phy_read_status(struct phy_device *phydev)
2849 {
2850         struct ar8xxx_priv *priv = phydev->priv;
2851         struct switch_port_link link;
2852         int ret;
2853
2854         if (phydev->addr != 0)
2855                 return genphy_read_status(phydev);
2856
2857         ar8216_read_port_link(priv, phydev->addr, &link);
2858         phydev->link = !!link.link;
2859         if (!phydev->link)
2860                 return 0;
2861
2862         switch (link.speed) {
2863         case SWITCH_PORT_SPEED_10:
2864                 phydev->speed = SPEED_10;
2865                 break;
2866         case SWITCH_PORT_SPEED_100:
2867                 phydev->speed = SPEED_100;
2868                 break;
2869         case SWITCH_PORT_SPEED_1000:
2870                 phydev->speed = SPEED_1000;
2871                 break;
2872         default:
2873                 phydev->speed = 0;
2874         }
2875         phydev->duplex = link.duplex ? DUPLEX_FULL : DUPLEX_HALF;
2876
2877         /* flush the address translation unit */
2878         mutex_lock(&priv->reg_mutex);
2879         ret = priv->chip->atu_flush(priv);
2880         mutex_unlock(&priv->reg_mutex);
2881
2882         phydev->state = PHY_RUNNING;
2883         netif_carrier_on(phydev->attached_dev);
2884         phydev->adjust_link(phydev->attached_dev);
2885
2886         return ret;
2887 }
2888
2889 static int
2890 ar8xxx_phy_config_aneg(struct phy_device *phydev)
2891 {
2892         if (phydev->addr == 0)
2893                 return 0;
2894
2895         return genphy_config_aneg(phydev);
2896 }
2897
2898 static const u32 ar8xxx_phy_ids[] = {
2899         0x004dd033,
2900         0x004dd034, /* AR8327 */
2901         0x004dd036, /* AR8337 */
2902         0x004dd041,
2903         0x004dd042,
2904         0x004dd043, /* AR8236 */
2905 };
2906
2907 static bool
2908 ar8xxx_phy_match(u32 phy_id)
2909 {
2910         int i;
2911
2912         for (i = 0; i < ARRAY_SIZE(ar8xxx_phy_ids); i++)
2913                 if (phy_id == ar8xxx_phy_ids[i])
2914                         return true;
2915
2916         return false;
2917 }
2918
2919 static bool
2920 ar8xxx_is_possible(struct mii_bus *bus)
2921 {
2922         unsigned i;
2923
2924         for (i = 0; i < 4; i++) {
2925                 u32 phy_id;
2926
2927                 phy_id = mdiobus_read(bus, i, MII_PHYSID1) << 16;
2928                 phy_id |= mdiobus_read(bus, i, MII_PHYSID2);
2929                 if (!ar8xxx_phy_match(phy_id)) {
2930                         pr_debug("ar8xxx: unknown PHY at %s:%02x id:%08x\n",
2931                                  dev_name(&bus->dev), i, phy_id);
2932                         return false;
2933                 }
2934         }
2935
2936         return true;
2937 }
2938
2939 static int
2940 ar8xxx_phy_probe(struct phy_device *phydev)
2941 {
2942         struct ar8xxx_priv *priv;
2943         struct switch_dev *swdev;
2944         int ret;
2945
2946         /* skip PHYs at unused adresses */
2947         if (phydev->addr != 0 && phydev->addr != 4)
2948                 return -ENODEV;
2949
2950         if (!ar8xxx_is_possible(phydev->bus))
2951                 return -ENODEV;
2952
2953         mutex_lock(&ar8xxx_dev_list_lock);
2954         list_for_each_entry(priv, &ar8xxx_dev_list, list)
2955                 if (priv->mii_bus == phydev->bus)
2956                         goto found;
2957
2958         priv = ar8xxx_create_mii(phydev->bus);
2959         if (priv == NULL) {
2960                 ret = -ENOMEM;
2961                 goto unlock;
2962         }
2963
2964         ret = ar8xxx_probe_switch(priv);
2965         if (ret)
2966                 goto free_priv;
2967
2968         swdev = &priv->dev;
2969         swdev->alias = dev_name(&priv->mii_bus->dev);
2970         ret = register_switch(swdev, NULL);
2971         if (ret)
2972                 goto free_priv;
2973
2974         pr_info("%s: %s rev. %u switch registered on %s\n",
2975                 swdev->devname, swdev->name, priv->chip_rev,
2976                 dev_name(&priv->mii_bus->dev));
2977
2978 found:
2979         priv->use_count++;
2980
2981         if (phydev->addr == 0) {
2982                 if (ar8xxx_has_gige(priv)) {
2983                         phydev->supported = SUPPORTED_1000baseT_Full;
2984                         phydev->advertising = ADVERTISED_1000baseT_Full;
2985                 } else {
2986                         phydev->supported = SUPPORTED_100baseT_Full;
2987                         phydev->advertising = ADVERTISED_100baseT_Full;
2988                 }
2989
2990                 if (priv->chip->config_at_probe) {
2991                         priv->phy = phydev;
2992
2993                         ret = ar8xxx_start(priv);
2994                         if (ret)
2995                                 goto err_unregister_switch;
2996                 }
2997         } else {
2998                 if (ar8xxx_has_gige(priv)) {
2999                         phydev->supported |= SUPPORTED_1000baseT_Full;
3000                         phydev->advertising |= ADVERTISED_1000baseT_Full;
3001                 }
3002         }
3003
3004         phydev->priv = priv;
3005
3006         list_add(&priv->list, &ar8xxx_dev_list);
3007
3008         mutex_unlock(&ar8xxx_dev_list_lock);
3009
3010         return 0;
3011
3012 err_unregister_switch:
3013         if (--priv->use_count)
3014                 goto unlock;
3015
3016         unregister_switch(&priv->dev);
3017
3018 free_priv:
3019         ar8xxx_free(priv);
3020 unlock:
3021         mutex_unlock(&ar8xxx_dev_list_lock);
3022         return ret;
3023 }
3024
3025 static void
3026 ar8xxx_phy_detach(struct phy_device *phydev)
3027 {
3028         struct net_device *dev = phydev->attached_dev;
3029
3030         if (!dev)
3031                 return;
3032
3033         dev->phy_ptr = NULL;
3034         dev->priv_flags &= ~IFF_NO_IP_ALIGN;
3035         dev->eth_mangle_rx = NULL;
3036         dev->eth_mangle_tx = NULL;
3037 }
3038
3039 static void
3040 ar8xxx_phy_remove(struct phy_device *phydev)
3041 {
3042         struct ar8xxx_priv *priv = phydev->priv;
3043
3044         if (WARN_ON(!priv))
3045                 return;
3046
3047         phydev->priv = NULL;
3048         if (--priv->use_count > 0)
3049                 return;
3050
3051         mutex_lock(&ar8xxx_dev_list_lock);
3052         list_del(&priv->list);
3053         mutex_unlock(&ar8xxx_dev_list_lock);
3054
3055         unregister_switch(&priv->dev);
3056         ar8xxx_mib_stop(priv);
3057         ar8xxx_free(priv);
3058 }
3059
3060 #if LINUX_VERSION_CODE >= KERNEL_VERSION(3,14,0)
3061 static int
3062 ar8xxx_phy_soft_reset(struct phy_device *phydev)
3063 {
3064         /* we don't need an extra reset */
3065         return 0;
3066 }
3067 #endif
3068
3069 static struct phy_driver ar8xxx_phy_driver = {
3070         .phy_id         = 0x004d0000,
3071         .name           = "Atheros AR8216/AR8236/AR8316",
3072         .phy_id_mask    = 0xffff0000,
3073         .features       = PHY_BASIC_FEATURES,
3074         .probe          = ar8xxx_phy_probe,
3075         .remove         = ar8xxx_phy_remove,
3076         .detach         = ar8xxx_phy_detach,
3077         .config_init    = ar8xxx_phy_config_init,
3078         .config_aneg    = ar8xxx_phy_config_aneg,
3079         .read_status    = ar8xxx_phy_read_status,
3080 #if LINUX_VERSION_CODE >= KERNEL_VERSION(3,14,0)
3081         .soft_reset     = ar8xxx_phy_soft_reset,
3082 #endif
3083         .driver         = { .owner = THIS_MODULE },
3084 };
3085
3086 int __init
3087 ar8xxx_init(void)
3088 {
3089         return phy_driver_register(&ar8xxx_phy_driver);
3090 }
3091
3092 void __exit
3093 ar8xxx_exit(void)
3094 {
3095         phy_driver_unregister(&ar8xxx_phy_driver);
3096 }
3097
3098 module_init(ar8xxx_init);
3099 module_exit(ar8xxx_exit);
3100 MODULE_LICENSE("GPL");
3101