target/linux/cns3xxx/patches-3.3/300-laguna_support.patch

   1 --- /dev/null
   2 +++ b/arch/arm/mach-cns3xxx/laguna.c
   3 @@ -0,0 +1,931 @@
   4 +/*
   5 + * Gateworks Corporation Laguna Platform
   6 + *
   7 + * Copyright 2000 Deep Blue Solutions Ltd
   8 + * Copyright 2008 ARM Limited
   9 + * Copyright 2008 Cavium Networks
  10 + *               Scott Shu
  11 + * Copyright 2010 MontaVista Software, LLC.
  12 + *               Anton Vorontsov <avorontsov@mvista.com>
  13 + * Copyright 2011 Gateworks Corporation
  14 + *               Chris Lang <clang@gateworks.com>
  15 + * Copyright 2012 Gateworks Corporation
  16 + *               Tim Harvey <tharvey@gateworks.com>
  17 + *
  18 + * This file is free software; you can redistribute it and/or modify
  19 + * it under the terms of the GNU General Public License, Version 2, as
  20 + * published by the Free Software Foundation.
  21 + */
  22 +
  23 +#include <linux/init.h>
  24 +#include <linux/kernel.h>
  25 +#include <linux/compiler.h>
  26 +#include <linux/io.h>
  27 +#include <linux/gpio.h>
  28 +#include <linux/dma-mapping.h>
  29 +#include <linux/serial_core.h>
  30 +#include <linux/serial_8250.h>
  31 +#include <linux/platform_device.h>
  32 +#include <linux/mtd/mtd.h>
  33 +#include <linux/mtd/physmap.h>
  34 +#include <linux/mtd/partitions.h>
  35 +#include <linux/leds.h>
  36 +#include <linux/i2c.h>
  37 +#include <linux/i2c/at24.h>
  38 +#include <linux/i2c/pca953x.h>
  39 +#include <linux/spi/spi.h>
  40 +#include <linux/spi/flash.h>
  41 +#include <linux/if_ether.h>
  42 +#include <asm/setup.h>
  43 +#include <asm/mach-types.h>
  44 +#include <asm/mach/arch.h>
  45 +#include <asm/mach/map.h>
  46 +#include <asm/mach/time.h>
  47 +#include <mach/cns3xxx.h>
  48 +#include <mach/irqs.h>
  49 +#include <mach/platform.h>
  50 +#include <mach/pm.h>
  51 +#include <asm/hardware/gic.h>
  52 +#include "core.h"
  53 +#include "devices.h"
  54 +
  55 +#define ARRAY_AND_SIZE(x)       (x), ARRAY_SIZE(x)
  56 +
  57 +// Config 1 Bitmap
  58 +#define ETH0_LOAD           BIT(0)
  59 +#define ETH1_LOAD           BIT(1)
  60 +#define ETH2_LOAD           BIT(2)
  61 +#define SATA0_LOAD          BIT(3)
  62 +#define SATA1_LOAD          BIT(4)
  63 +#define PCM_LOAD            BIT(5)
  64 +#define I2S_LOAD            BIT(6)
  65 +#define SPI0_LOAD           BIT(7)
  66 +#define SPI1_LOAD           BIT(8)
  67 +#define PCIE0_LOAD          BIT(9)
  68 +#define PCIE1_LOAD          BIT(10)
  69 +#define USB0_LOAD           BIT(11)
  70 +#define USB1_LOAD           BIT(12)
  71 +#define USB1_ROUTE          BIT(13)
  72 +#define SD_LOAD             BIT(14)
  73 +#define UART0_LOAD          BIT(15)
  74 +#define UART1_LOAD          BIT(16)
  75 +#define UART2_LOAD          BIT(17)
  76 +#define MPCI0_LOAD          BIT(18)
  77 +#define MPCI1_LOAD          BIT(19)
  78 +#define MPCI2_LOAD          BIT(20)
  79 +#define MPCI3_LOAD          BIT(21)
  80 +#define FP_BUT_LOAD         BIT(22)
  81 +#define FP_BUT_HEADER_LOAD  BIT(23)
  82 +#define FP_LED_LOAD         BIT(24)
  83 +#define FP_LED_HEADER_LOAD  BIT(25)
  84 +#define FP_TAMPER_LOAD      BIT(26)
  85 +#define HEADER_33V_LOAD     BIT(27)
  86 +#define SATA_POWER_LOAD     BIT(28)
  87 +#define FP_POWER_LOAD       BIT(29)
  88 +#define GPIO_HEADER_LOAD    BIT(30)
  89 +#define GSP_BAT_LOAD        BIT(31)
  90 +
  91 +// Config 2 Bitmap
  92 +#define FAN_LOAD            BIT(0)
  93 +#define SPI_FLASH_LOAD      BIT(1)
  94 +#define NOR_FLASH_LOAD      BIT(2)
  95 +#define GPS_LOAD            BIT(3)
  96 +#define SUPPLY_5V_LOAD      BIT(6)
  97 +#define SUPPLY_33V_LOAD     BIT(7)
  98 +
  99 +struct laguna_board_info {
 100 +       char model[16];
 101 +       u32 config_bitmap;
 102 +       u32 config2_bitmap;
 103 +       u8 nor_flash_size;
 104 +       u8 spi_flash_size;
 105 +};
 106 +
 107 +static struct laguna_board_info laguna_info __initdata;
 108 +
 109 +/*
 110 + * NOR Flash
 111 + */
 112 +static struct mtd_partition laguna_nor_partitions[] = {
 113 +       {
 114 +               .name           = "uboot",
 115 +               .size           = SZ_256K,
 116 +               .offset         = 0,
 117 +               .mask_flags     = MTD_WRITEABLE,
 118 +       }, {
 119 +               .name           = "params",
 120 +               .size           = SZ_128K,
 121 +               .offset         = SZ_256K,
 122 +       }, {
 123 +               .name           = "kernel",
 124 +               .size           = SZ_2M,
 125 +               .offset         = SZ_256K + SZ_128K,
 126 +       }, {
 127 +               .name           = "rootfs",
 128 +               .size           = SZ_16M - SZ_256K - SZ_128K - SZ_2M,
 129 +               .offset         = SZ_256K + SZ_128K + SZ_2M,
 130 +       },
 131 +};
 132 +
 133 +static struct physmap_flash_data laguna_nor_pdata = {
 134 +       .width = 2,
 135 +       .parts = laguna_nor_partitions,
 136 +       .nr_parts = ARRAY_SIZE(laguna_nor_partitions),
 137 +};
 138 +
 139 +static struct resource laguna_nor_res = {
 140 +       .start = CNS3XXX_FLASH_BASE,
 141 +       .end = CNS3XXX_FLASH_BASE + SZ_128M - 1,
 142 +       .flags = IORESOURCE_MEM | IORESOURCE_MEM_32BIT,
 143 +};
 144 +
 145 +static struct platform_device laguna_nor_pdev = {
 146 +       .name = "physmap-flash",
 147 +       .id = 0,
 148 +       .resource = &laguna_nor_res,
 149 +       .num_resources = 1,
 150 +       .dev = {
 151 +               .platform_data = &laguna_nor_pdata,
 152 +       },
 153 +};
 154 +
 155 +/*
 156 + * SPI
 157 + */
 158 +static struct mtd_partition laguna_spi_partitions[] = {
 159 +       {
 160 +               .name           = "uboot",
 161 +               .size           = SZ_256K,
 162 +               .offset         = 0,
 163 +               .mask_flags     = MTD_WRITEABLE,
 164 +       }, {
 165 +               .name           = "params",
 166 +               .size           = SZ_256K,
 167 +               .offset         = SZ_256K,
 168 +       }, {
 169 +               .name           = "kernel",
 170 +               .size           = SZ_1M + SZ_512K,
 171 +               .offset         = SZ_512K,
 172 +       }, {
 173 +               .name           = "rootfs",
 174 +               .size           = SZ_16M - SZ_2M,
 175 +               .offset         = SZ_2M,
 176 +       },
 177 +};
 178 +
 179 +static struct flash_platform_data laguna_spi_pdata = {
 180 +       .parts = laguna_spi_partitions,
 181 +       .nr_parts = ARRAY_SIZE(laguna_spi_partitions),
 182 +};
 183 +
 184 +static struct spi_board_info __initdata laguna_spi_devices[] = {
 185 +       {
 186 +               .modalias = "m25p80",
 187 +               .platform_data = &laguna_spi_pdata,
 188 +               .max_speed_hz = 50000000,
 189 +               .bus_num = 1,
 190 +               .chip_select = 0,
 191 +       },
 192 +};
 193 +
 194 +static struct platform_device laguna_spi_controller = {
 195 +       .name = "cns3xxx_spi",
 196 +};
 197 +
 198 +/*
 199 + * LED's
 200 + */
 201 +static struct gpio_led laguna_gpio_leds[] = {
 202 +       {
 203 +               .name = "user1", /* Green Led */
 204 +               .gpio = 115,
 205 +               .active_low = 1,
 206 +       },{
 207 +               .name = "user2", /* Red Led */
 208 +               .gpio = 114,
 209 +               .active_low = 1,
 210 +       },{
 211 +               .name = "pwr1", /* Green Led */
 212 +               .gpio = 116,
 213 +               .active_low = 1,
 214 +       },{
 215 +               .name = "pwr2", /* Yellow Led */
 216 +               .gpio = 117,
 217 +               .active_low = 1,
 218 +       },{
 219 +               .name = "txd1", /* Green Led */
 220 +               .gpio = 118,
 221 +               .active_low = 1,
 222 +       },{
 223 +               .name = "txd2", /* Yellow Led */
 224 +               .gpio = 119,
 225 +               .active_low = 1,
 226 +       },{
 227 +               .name = "rxd1", /* Green Led */
 228 +               .gpio = 120,
 229 +               .active_low = 1,
 230 +       },{
 231 +               .name = "rxd2", /* Yellow Led */
 232 +               .gpio = 121,
 233 +               .active_low = 1,
 234 +       },{
 235 +               .name = "ser1", /* Green Led */
 236 +               .gpio = 122,
 237 +               .active_low = 1,
 238 +       },{
 239 +               .name = "ser2", /* Yellow Led */
 240 +               .gpio = 123,
 241 +               .active_low = 1,
 242 +       },{
 243 +               .name = "enet1", /* Green Led */
 244 +               .gpio = 124,
 245 +               .active_low = 1,
 246 +       },{
 247 +               .name = "enet2", /* Yellow Led */
 248 +               .gpio = 125,
 249 +               .active_low = 1,
 250 +       },{
 251 +               .name = "sig1_1", /* Green Led */
 252 +               .gpio = 126,
 253 +               .active_low = 1,
 254 +       },{
 255 +               .name = "sig1_2", /* Yellow Led */
 256 +               .gpio = 127,
 257 +               .active_low = 1,
 258 +       },{
 259 +               .name = "sig2_1", /* Green Led */
 260 +               .gpio = 128,
 261 +               .active_low = 1,
 262 +       },{
 263 +               .name = "sig2_2", /* Yellow Led */
 264 +               .gpio = 129,
 265 +               .active_low = 1,
 266 +       },{
 267 +               .name = "sig3_1", /* Green Led */
 268 +               .gpio = 130,
 269 +               .active_low = 1,
 270 +       },{
 271 +               .name = "sig3_2", /* Yellow Led */
 272 +               .gpio = 131,
 273 +               .active_low = 1,
 274 +       },{
 275 +               .name = "net1", /*Green Led */
 276 +               .gpio = 109,
 277 +               .active_low = 1,
 278 +       },{
 279 +               .name = "net2", /* Red Led */
 280 +               .gpio = 110,
 281 +               .active_low = 1,
 282 +       },{
 283 +               .name = "mod1", /* Green Led */
 284 +               .gpio = 111,
 285 +               .active_low = 1,
 286 +       },{
 287 +               .name = "mod2", /* Red Led */
 288 +               .gpio = 112,
 289 +               .active_low = 1,
 290 +       },
 291 +};
 292 +
 293 +static struct gpio_led_platform_data laguna_gpio_leds_data = {
 294 +       .num_leds = 22,
 295 +       .leds = laguna_gpio_leds,
 296 +};
 297 +
 298 +static struct platform_device laguna_gpio_leds_device = {
 299 +       .name = "leds-gpio",
 300 +       .id = -1,
 301 +       .dev.platform_data = &laguna_gpio_leds_data,
 302 +};
 303 +
 304 +/*
 305 + * Ethernet
 306 + */
 307 +static struct cns3xxx_plat_info laguna_net_data = {
 308 +       .ports = 0,
 309 +       .phy = {
 310 +               0,
 311 +               1,
 312 +               2,
 313 +       },
 314 +};
 315 +
 316 +static struct platform_device laguna_net_device = {
 317 +       .name = "cns3xxx_eth",
 318 +       .id = 0,
 319 +       .dev.platform_data = &laguna_net_data,
 320 +};
 321 +
 322 +/*
 323 + * UART
 324 + */
 325 +static void __init laguna_early_serial_setup(void)
 326 +{
 327 +#ifdef CONFIG_SERIAL_8250_CONSOLE
 328 +       static struct uart_port laguna_serial_port = {
 329 +               .membase        = (void __iomem *)CNS3XXX_UART0_BASE_VIRT,
 330 +               .mapbase        = CNS3XXX_UART0_BASE,
 331 +               .irq            = IRQ_CNS3XXX_UART0,
 332 +               .iotype         = UPIO_MEM,
 333 +               .flags          = UPF_BOOT_AUTOCONF | UPF_FIXED_TYPE,
 334 +               .regshift       = 2,
 335 +               .uartclk        = 24000000,
 336 +               .line           = 0,
 337 +               .type           = PORT_16550A,
 338 +               .fifosize       = 16,
 339 +       };
 340 +
 341 +       early_serial_setup(&laguna_serial_port);
 342 +#endif
 343 +}
 344 +
 345 +static struct resource laguna_uart_resources[] = {
 346 +       {
 347 +               .start = CNS3XXX_UART0_BASE,
 348 +               .end   = CNS3XXX_UART0_BASE + SZ_4K - 1,
 349 +               .flags    = IORESOURCE_MEM
 350 +       },{
 351 +               .start = CNS3XXX_UART2_BASE,
 352 +               .end   = CNS3XXX_UART2_BASE + SZ_4K - 1,
 353 +               .flags    = IORESOURCE_MEM
 354 +       },{
 355 +               .start = CNS3XXX_UART2_BASE,
 356 +               .end   = CNS3XXX_UART2_BASE + SZ_4K - 1,
 357 +               .flags    = IORESOURCE_MEM
 358 +       },
 359 +};
 360 +
 361 +static struct plat_serial8250_port laguna_uart_data[] = {
 362 +       {
 363 +               .membase        = (char*) (CNS3XXX_UART0_BASE_VIRT),
 364 +               .mapbase        = (CNS3XXX_UART0_BASE),
 365 +               .irq            = IRQ_CNS3XXX_UART0,
 366 +               .iotype         = UPIO_MEM,
 367 +               .flags          = UPF_BOOT_AUTOCONF | UPF_FIXED_TYPE | UPF_NO_TXEN_TEST,
 368 +               .regshift       = 2,
 369 +               .uartclk        = 24000000,
 370 +               .type           = PORT_16550A,
 371 +       },{
 372 +               .membase        = (char*) (CNS3XXX_UART1_BASE_VIRT),
 373 +               .mapbase        = (CNS3XXX_UART1_BASE),
 374 +               .irq            = IRQ_CNS3XXX_UART1,
 375 +               .iotype         = UPIO_MEM,
 376 +               .flags          = UPF_BOOT_AUTOCONF | UPF_FIXED_TYPE | UPF_NO_TXEN_TEST,
 377 +               .regshift       = 2,
 378 +               .uartclk        = 24000000,
 379 +               .type           = PORT_16550A,
 380 +       },{
 381 +               .membase        = (char*) (CNS3XXX_UART2_BASE_VIRT),
 382 +               .mapbase        = (CNS3XXX_UART2_BASE),
 383 +               .irq            = IRQ_CNS3XXX_UART2,
 384 +               .iotype         = UPIO_MEM,
 385 +               .flags          = UPF_BOOT_AUTOCONF | UPF_FIXED_TYPE | UPF_NO_TXEN_TEST,
 386 +               .regshift       = 2,
 387 +               .uartclk        = 24000000,
 388 +               .type           = PORT_16550A,
 389 +       },
 390 +       { },
 391 +};
 392 +
 393 +static struct platform_device laguna_uart = {
 394 +       .name     = "serial8250",
 395 +       .id     = PLAT8250_DEV_PLATFORM,
 396 +       .dev.platform_data  = laguna_uart_data,
 397 +       .num_resources    = 3,
 398 +       .resource   = laguna_uart_resources
 399 +};
 400 +
 401 +/*
 402 + * USB
 403 + */
 404 +static struct resource cns3xxx_usb_ehci_resources[] = {
 405 +       [0] = {
 406 +               .start = CNS3XXX_USB_BASE,
 407 +               .end   = CNS3XXX_USB_BASE + SZ_16M - 1,
 408 +               .flags = IORESOURCE_MEM,
 409 +       },
 410 +       [1] = {
 411 +               .start = IRQ_CNS3XXX_USB_EHCI,
 412 +               .flags = IORESOURCE_IRQ,
 413 +       },
 414 +};
 415 +
 416 +static u64 cns3xxx_usb_ehci_dma_mask = DMA_BIT_MASK(32);
 417 +
 418 +static struct platform_device cns3xxx_usb_ehci_device = {
 419 +       .name          = "cns3xxx-ehci",
 420 +       .num_resources = ARRAY_SIZE(cns3xxx_usb_ehci_resources),
 421 +       .resource      = cns3xxx_usb_ehci_resources,
 422 +       .dev           = {
 423 +               .dma_mask          = &cns3xxx_usb_ehci_dma_mask,
 424 +               .coherent_dma_mask = DMA_BIT_MASK(32),
 425 +       },
 426 +};
 427 +
 428 +static struct resource cns3xxx_usb_ohci_resources[] = {
 429 +       [0] = {
 430 +               .start = CNS3XXX_USB_OHCI_BASE,
 431 +               .end   = CNS3XXX_USB_OHCI_BASE + SZ_16M - 1,
 432 +               .flags = IORESOURCE_MEM,
 433 +       },
 434 +       [1] = {
 435 +               .start = IRQ_CNS3XXX_USB_OHCI,
 436 +               .flags = IORESOURCE_IRQ,
 437 +       },
 438 +};
 439 +
 440 +static u64 cns3xxx_usb_ohci_dma_mask = DMA_BIT_MASK(32);
 441 +
 442 +static struct platform_device cns3xxx_usb_ohci_device = {
 443 +       .name          = "cns3xxx-ohci",
 444 +       .num_resources = ARRAY_SIZE(cns3xxx_usb_ohci_resources),
 445 +       .resource      = cns3xxx_usb_ohci_resources,
 446 +       .dev           = {
 447 +               .dma_mask          = &cns3xxx_usb_ohci_dma_mask,
 448 +               .coherent_dma_mask = DMA_BIT_MASK(32),
 449 +       },
 450 +};
 451 +
 452 +static struct resource cns3xxx_usb_otg_resources[] = {
 453 +       [0] = {
 454 +               .start = CNS3XXX_USBOTG_BASE,
 455 +               .end   = CNS3XXX_USBOTG_BASE + SZ_16M - 1,
 456 +               .flags = IORESOURCE_MEM,
 457 +       },
 458 +       [1] = {
 459 +               .start = IRQ_CNS3XXX_USB_OTG,
 460 +               .flags = IORESOURCE_IRQ,
 461 +       },
 462 +};
 463 +
 464 +static u64 cns3xxx_usb_otg_dma_mask = DMA_BIT_MASK(32);
 465 +
 466 +static struct platform_device cns3xxx_usb_otg_device = {
 467 +       .name          = "dwc_otg",
 468 +       .num_resources = ARRAY_SIZE(cns3xxx_usb_otg_resources),
 469 +       .resource      = cns3xxx_usb_otg_resources,
 470 +       .dev           = {
 471 +               .dma_mask          = &cns3xxx_usb_otg_dma_mask,
 472 +               .coherent_dma_mask = DMA_BIT_MASK(32),
 473 +       },
 474 +};
 475 +
 476 +/*
 477 + * I2C
 478 + */
 479 +static struct resource laguna_i2c_resource[] = {
 480 +       {
 481 +               .start    = CNS3XXX_SSP_BASE + 0x20,
 482 +               .end      = 0x7100003f,
 483 +               .flags    = IORESOURCE_MEM,
 484 +       },{
 485 +               .start    = IRQ_CNS3XXX_I2C,
 486 +               .flags    = IORESOURCE_IRQ,
 487 +       },
 488 +};
 489 +
 490 +static struct platform_device laguna_i2c_controller = {
 491 +       .name   = "cns3xxx-i2c",
 492 +       .num_resources  = 2,
 493 +       .resource = laguna_i2c_resource,
 494 +};
 495 +
 496 +static struct memory_accessor *at24_mem_acc;
 497 +
 498 +static void at24_setup(struct memory_accessor *mem_acc, void *context)
 499 +{
 500 +       char buf[16];
 501 +
 502 +       at24_mem_acc = mem_acc;
 503 +
 504 +       /* Read MAC addresses */
 505 +       if (at24_mem_acc->read(at24_mem_acc, buf, 0x100, 6) == 6)
 506 +               memcpy(&laguna_net_data.hwaddr[0], buf, ETH_ALEN);
 507 +       if (at24_mem_acc->read(at24_mem_acc, buf, 0x106, 6) == 6)
 508 +               memcpy(&laguna_net_data.hwaddr[1], buf, ETH_ALEN);
 509 +       if (at24_mem_acc->read(at24_mem_acc, buf, 0x10C, 6) == 6)
 510 +               memcpy(&laguna_net_data.hwaddr[2], buf, ETH_ALEN);
 511 +       if (at24_mem_acc->read(at24_mem_acc, buf, 0x112, 6) == 6)
 512 +               memcpy(&laguna_net_data.hwaddr[3], buf, ETH_ALEN);
 513 +
 514 +       /* Read out Model Information */
 515 +       if (at24_mem_acc->read(at24_mem_acc, buf, 0x130, 16) == 16)
 516 +               memcpy(&laguna_info.model, buf, 16);
 517 +       if (at24_mem_acc->read(at24_mem_acc, buf, 0x140, 1) == 1)
 518 +               memcpy(&laguna_info.nor_flash_size, buf, 1);
 519 +       if (at24_mem_acc->read(at24_mem_acc, buf, 0x141, 1) == 1)
 520 +               memcpy(&laguna_info.spi_flash_size, buf, 1);
 521 +       if (at24_mem_acc->read(at24_mem_acc, buf, 0x142, 4) == 4)
 522 +               memcpy(&laguna_info.config_bitmap, buf, 4);
 523 +       if (at24_mem_acc->read(at24_mem_acc, buf, 0x146, 4) == 4)
 524 +               memcpy(&laguna_info.config2_bitmap, buf, 4);
 525 +};
 526 +
 527 +static struct at24_platform_data laguna_eeprom_info = {
 528 +       .byte_len = 1024,
 529 +       .page_size = 16,
 530 +       .flags = AT24_FLAG_READONLY,
 531 +       .setup = at24_setup,
 532 +};
 533 +
 534 +static struct pca953x_platform_data laguna_pca_data = {
 535 +       .gpio_base = 100,
 536 +       .irq_base = -1,
 537 +};
 538 +
 539 +static struct pca953x_platform_data laguna_pca2_data = {
 540 +       .gpio_base = 116,
 541 +       .irq_base = -1,
 542 +};
 543 +
 544 +static struct i2c_board_info __initdata laguna_i2c_devices[] = {
 545 +       {
 546 +               I2C_BOARD_INFO("pca9555", 0x23),
 547 +               .platform_data = &laguna_pca_data,
 548 +       },{
 549 +               I2C_BOARD_INFO("pca9555", 0x27),
 550 +               .platform_data = &laguna_pca2_data,
 551 +       },{
 552 +               I2C_BOARD_INFO("gsp", 0x29),
 553 +       },{
 554 +               I2C_BOARD_INFO ("24c08",0x50),
 555 +               .platform_data = &laguna_eeprom_info,
 556 +       },{
 557 +               I2C_BOARD_INFO("ds1672", 0x68),
 558 +       },
 559 +};
 560 +
 561 +/*
 562 + * Watchdog
 563 + */
 564 +
 565 +static struct resource laguna_watchdog_resources[] = {
 566 +       [0] = {
 567 +               .start  = CNS3XXX_TC11MP_TWD_BASE + 0x100, // CPU0 watchdog
 568 +               .end    = CNS3XXX_TC11MP_TWD_BASE + SZ_4K - 1,
 569 +               .flags  = IORESOURCE_MEM,
 570 +       },
 571 +       [1] = {
 572 +               .start  = IRQ_LOCALWDOG,
 573 +               .end    = IRQ_LOCALWDOG,
 574 +               .flags  = IORESOURCE_IRQ,
 575 +       }
 576 +};
 577 +
 578 +static struct platform_device laguna_watchdog = {
 579 +       .name           = "mpcore_wdt",
 580 +       .id             = -1,
 581 +       .num_resources  = ARRAY_SIZE(laguna_watchdog_resources),
 582 +       .resource       = laguna_watchdog_resources,
 583 +};
 584 +
 585 +/*
 586 + * GPIO
 587 + */
 588 +
 589 +static struct gpio laguna_gpio_gw2391[] = {
 590 +       {   0, GPIOF_IN           , "*GPS_PPS" },
 591 +       {   1, GPIOF_IN           , "*GSC_IRQ#" },
 592 +       {   2, GPIOF_IN           , "*USB_FAULT#" },
 593 +       {   5, GPIOF_OUT_INIT_LOW , "*USB0_PCI_SEL" },
 594 +       {   6, GPIOF_OUT_INIT_HIGH, "*USB_VBUS_EN" },
 595 +       {   7, GPIOF_OUT_INIT_LOW , "*USB1_PCI_SEL" },
 596 +       {   8, GPIOF_OUT_INIT_HIGH, "*PERST#" },
 597 +       {   9, GPIOF_OUT_INIT_LOW , "*FP_SER_EN#" },
 598 +       { 100, GPIOF_IN           , "*USER_PB#" },
 599 +       { 103, GPIOF_OUT_INIT_HIGH, "*V5_EN" },
 600 +       { 108, GPIOF_IN           , "DIO0" },
 601 +       { 109, GPIOF_IN           , "DIO1" },
 602 +       { 110, GPIOF_IN           , "DIO2" },
 603 +       { 111, GPIOF_IN           , "DIO3" },
 604 +       { 112, GPIOF_IN           , "DIO4" },
 605 +};
 606 +
 607 +static struct gpio laguna_gpio_gw2388[] = {
 608 +       {   0, GPIOF_IN           , "*GPS_PPS" },
 609 +       {   1, GPIOF_IN           , "*GSC_IRQ#" },
 610 +       {   3, GPIOF_IN           , "*USB_FAULT#" },
 611 +       {   6, GPIOF_OUT_INIT_HIGH, "*USB_VBUS_EN" },
 612 +       {   7, GPIOF_OUT_INIT_LOW , "*GSM_SEL0" },
 613 +       {   8, GPIOF_OUT_INIT_LOW , "*GSM_SEL1" },
 614 +       {   9, GPIOF_OUT_INIT_LOW , "*FP_SER_EN" },
 615 +       { 100, GPIOF_OUT_INIT_HIGH, "*USER_PB#" },
 616 +       { 108, GPIOF_IN           , "DIO0" },
 617 +       { 109, GPIOF_IN           , "DIO1" },
 618 +       { 110, GPIOF_IN           , "DIO2" },
 619 +       { 111, GPIOF_IN           , "DIO3" },
 620 +       { 112, GPIOF_IN           , "DIO4" },
 621 +};
 622 +
 623 +static struct gpio laguna_gpio_gw2387[] = {
 624 +       {   0, GPIOF_IN           , "*GPS_PPS" },
 625 +       {   1, GPIOF_IN           , "*GSC_IRQ#" },
 626 +       {   2, GPIOF_IN           , "*USB_FAULT#" },
 627 +       {   5, GPIOF_OUT_INIT_LOW , "*USB_PCI_SEL" },
 628 +       {   6, GPIOF_OUT_INIT_HIGH, "*USB_VBUS_EN" },
 629 +       {   7, GPIOF_OUT_INIT_LOW , "*GSM_SEL0" },
 630 +       {   8, GPIOF_OUT_INIT_LOW , "*GSM_SEL1" },
 631 +       {   9, GPIOF_OUT_INIT_LOW , "*FP_SER_EN" },
 632 +       { 100, GPIOF_IN           , "*USER_PB#" },
 633 +       { 103, GPIOF_OUT_INIT_HIGH, "*V5_EN" },
 634 +       { 108, GPIOF_IN           , "DIO0" },
 635 +       { 109, GPIOF_IN           , "DIO1" },
 636 +       { 110, GPIOF_IN           , "DIO2" },
 637 +       { 111, GPIOF_IN           , "DIO3" },
 638 +       { 112, GPIOF_IN           , "DIO4" },
 639 +       { 113, GPIOF_IN           , "DIO5" },
 640 +};
 641 +
 642 +static struct gpio laguna_gpio_gw2384[] = {
 643 +       {   0, GPIOF_IN           , "*GSC_IRQ#" },
 644 +       {   1, GPIOF_OUT_INIT_HIGH, "*USB_HST_VBUS_EN" },
 645 +       {   2, GPIOF_IN           , "*USB_HST_FAULT#" },
 646 +       {   5, GPIOF_IN           , "*USB_OTG_FAULT#" },
 647 +       {   6, GPIOF_OUT_INIT_LOW , "*USB_HST_PCI_SEL" },
 648 +       {   7, GPIOF_OUT_INIT_LOW , "*GSM_SEL0" },
 649 +       {   8, GPIOF_OUT_INIT_LOW , "*GSM_SEL1" },
 650 +       {   9, GPIOF_OUT_INIT_LOW , "*FP_SER_EN" },
 651 +       {  12, GPIOF_OUT_INIT_LOW , "J10_DIOLED0" },
 652 +       {  13, GPIOF_OUT_INIT_HIGH, "*I2CMUX_RST#" },
 653 +       {  14, GPIOF_OUT_INIT_LOW , "J10_DIOLED1" },
 654 +       {  15, GPIOF_OUT_INIT_LOW , "J10_DIOLED2" },
 655 +       { 100, GPIOF_IN           , "*USER_PB#" },
 656 +       { 103, GPIOF_OUT_INIT_HIGH, "V5_EN" },
 657 +       { 108, GPIOF_IN           , "J9_DIOGSC0" },
 658 +};
 659 +
 660 +static struct gpio laguna_gpio_gw2383[] = {
 661 +       {   0, GPIOF_IN           , "*GPS_PPS" },
 662 +       {   1, GPIOF_IN           , "*GSC_IRQ#" },
 663 +       {   2, GPIOF_OUT_INIT_HIGH, "*PCIE_RST#" },
 664 +       {   3, GPIOF_IN           , "GPIO0" },
 665 +       {   8, GPIOF_IN           , "GPIO1" },
 666 +       { 100, GPIOF_IN           , "DIO0" },
 667 +       { 101, GPIOF_IN           , "DIO1" },
 668 +};
 669 +
 670 +static struct gpio laguna_gpio_gw2382[] = {
 671 +       {   0, GPIOF_IN           , "*GPS_PPS" },
 672 +       {   1, GPIOF_IN           , "*GSC_IRQ#" },
 673 +       {   2, GPIOF_OUT_INIT_HIGH, "*PCIE_RST#" },
 674 +       {   3, GPIOF_IN           , "GPIO0" },
 675 +       {   4, GPIOF_IN           , "GPIO1" },
 676 +       {   9, GPIOF_OUT_INIT_HIGH, "*USB_VBUS_EN" },
 677 +       {  10, GPIOF_OUT_INIT_HIGH, "*USB_PCI_SEL#" },
 678 +       { 100, GPIOF_IN           , "DIO0" },
 679 +       { 101, GPIOF_IN           , "DIO1" },
 680 +};
 681 +
 682 +static struct gpio laguna_gpio_gw2380[] = {
 683 +       {   0, GPIOF_IN           , "*GPS_PPS" },
 684 +       {   1, GPIOF_IN           , "*GSC_IRQ#" },
 685 +       {   3, GPIOF_IN           , "GPIO0" },
 686 +       {   8, GPIOF_IN           , "GPIO1" },
 687 +       { 100, GPIOF_IN           , "DIO0" },
 688 +       { 101, GPIOF_IN           , "DIO1" },
 689 +       { 102, GPIOF_IN           , "DIO2" },
 690 +       { 103, GPIOF_IN           , "DIO3" },
 691 +};
 692 +
 693 +/*
 694 + * Initialization
 695 + */
 696 +static void __init laguna_init(void)
 697 +{
 698 +       cns3xxx_l2x0_init();
 699 +
 700 +       platform_device_register(&laguna_watchdog);
 701 +
 702 +       platform_device_register(&laguna_i2c_controller);
 703 +
 704 +       i2c_register_board_info(0, ARRAY_AND_SIZE(laguna_i2c_devices));
 705 +
 706 +       pm_power_off = cns3xxx_power_off;
 707 +}
 708 +
 709 +static struct map_desc laguna_io_desc[] __initdata = {
 710 +       {
 711 +               .virtual        = CNS3XXX_UART0_BASE_VIRT,
 712 +               .pfn            = __phys_to_pfn(CNS3XXX_UART0_BASE),
 713 +               .length         = SZ_4K,
 714 +               .type           = MT_DEVICE,
 715 +       },{
 716 +               .virtual        = CNS3XXX_UART1_BASE_VIRT,
 717 +               .pfn            = __phys_to_pfn(CNS3XXX_UART1_BASE),
 718 +               .length         = SZ_4K,
 719 +               .type           = MT_DEVICE,
 720 +       },{
 721 +               .virtual        = CNS3XXX_UART2_BASE_VIRT,
 722 +               .pfn            = __phys_to_pfn(CNS3XXX_UART2_BASE),
 723 +               .length         = SZ_4K,
 724 +               .type           = MT_DEVICE,
 725 +       },
 726 +};
 727 +
 728 +static void __init laguna_map_io(void)
 729 +{
 730 +       cns3xxx_common_init();
 731 +       cns3xxx_pcie_iotable_init(0x3);
 732 +       iotable_init(ARRAY_AND_SIZE(laguna_io_desc));
 733 +       laguna_early_serial_setup();
 734 +}
 735 +
 736 +static int laguna_register_gpio(struct gpio *array, size_t num)
 737 +{
 738 +       int i, err, ret;
 739 +
 740 +       ret = 0;
 741 +       for (i = 0; i < num; i++, array++) {
 742 +               const char *label = array->label;
 743 +               if (label[0] == '*')
 744 +                       label++;
 745 +               err = gpio_request_one(array->gpio, array->flags, label);
 746 +               if (err)
 747 +                       ret = err;
 748 +               else {
 749 +                       err = gpio_export(array->gpio, array->label[0] != '*');
 750 +               }
 751 +       }
 752 +       return ret;
 753 +}
 754 +
 755 +static int __init laguna_model_setup(void)
 756 +{
 757 +       u32 __iomem *mem;
 758 +       u32 reg;
 759 +       u8 pcie_bitmap = 0;
 760 +
 761 +       printk("Running on Gateworks Laguna %s\n", laguna_info.model);
 762 +
 763 +       if (strncmp(laguna_info.model, "GW", 2) == 0) {
 764 +               if (laguna_info.config_bitmap & ETH0_LOAD)
 765 +                       laguna_net_data.ports |= BIT(0);
 766 +               if (laguna_info.config_bitmap & ETH1_LOAD)
 767 +                       laguna_net_data.ports |= BIT(1);
 768 +               if (laguna_info.config_bitmap & ETH2_LOAD)
 769 +                       laguna_net_data.ports |= BIT(2);
 770 +               if (laguna_net_data.ports)
 771 +                       platform_device_register(&laguna_net_device);
 772 +
 773 +               if ((laguna_info.config_bitmap & SATA0_LOAD) ||
 774 +                   (laguna_info.config_bitmap & SATA1_LOAD))
 775 +                       cns3xxx_ahci_init();
 776 +
 777 +               if (laguna_info.config_bitmap & (PCIE0_LOAD))
 778 +                       pcie_bitmap |= 0x1;
 779 +
 780 +               if (laguna_info.config_bitmap & (PCIE1_LOAD))
 781 +                       pcie_bitmap |= 0x2;
 782 +
 783 +               cns3xxx_pcie_init(pcie_bitmap);
 784 +
 785 +               if (laguna_info.config_bitmap & (USB0_LOAD)) {
 786 +                       cns3xxx_pwr_power_up(1 << PM_PLL_HM_PD_CTRL_REG_OFFSET_PLL_USB);
 787 +
 788 +                       /* DRVVBUS pins share with GPIOA */
 789 +                       mem = (void __iomem *)(CNS3XXX_MISC_BASE_VIRT + 0x0014);
 790 +                       reg = __raw_readl(mem);
 791 +                       reg |= 0x8;
 792 +                       __raw_writel(reg, mem);
 793 +
 794 +                       /* Enable OTG */
 795 +                       mem = (void __iomem *)(CNS3XXX_MISC_BASE_VIRT + 0x0808);
 796 +                       reg = __raw_readl(mem);
 797 +                       reg &= ~(1 << 10);
 798 +                       __raw_writel(reg, mem);
 799 +
 800 +                       platform_device_register(&cns3xxx_usb_otg_device);
 801 +               }
 802 +
 803 +               if (laguna_info.config_bitmap & (USB1_LOAD)) {
 804 +                       platform_device_register(&cns3xxx_usb_ehci_device);
 805 +                       platform_device_register(&cns3xxx_usb_ohci_device);
 806 +               }
 807 +
 808 +               if (laguna_info.config_bitmap & (SD_LOAD))
 809 +                       cns3xxx_sdhci_init();
 810 +
 811 +               if (laguna_info.config_bitmap & (UART0_LOAD))
 812 +                       laguna_uart.num_resources = 1;
 813 +               if (laguna_info.config_bitmap & (UART1_LOAD))
 814 +                       laguna_uart.num_resources = 2;
 815 +               if (laguna_info.config_bitmap & (UART2_LOAD))
 816 +                       laguna_uart.num_resources = 3;
 817 +               platform_device_register(&laguna_uart);
 818 +
 819 +               if (laguna_info.config2_bitmap & (NOR_FLASH_LOAD)) {
 820 +                       switch (laguna_info.nor_flash_size) {
 821 +                               case 1:
 822 +                                       laguna_nor_partitions[3].size = SZ_8M - SZ_256K - SZ_128K - SZ_2M;
 823 +                                       laguna_nor_res.end = CNS3XXX_FLASH_BASE + SZ_8M - 1;
 824 +                               break;
 825 +                               case 2:
 826 +                                       laguna_nor_partitions[3].size = SZ_16M - SZ_256K - SZ_128K - SZ_2M;
 827 +                                       laguna_nor_res.end = CNS3XXX_FLASH_BASE + SZ_16M - 1;
 828 +                               break;
 829 +                               case 3:
 830 +                                       laguna_nor_partitions[3].size = SZ_32M - SZ_256K - SZ_128K - SZ_2M;
 831 +                                       laguna_nor_res.end = CNS3XXX_FLASH_BASE + SZ_32M - 1;
 832 +                               break;
 833 +                               case 4:
 834 +                                       laguna_nor_partitions[3].size = SZ_64M - SZ_256K - SZ_128K - SZ_2M;
 835 +                                       laguna_nor_res.end = CNS3XXX_FLASH_BASE + SZ_64M - 1;
 836 +                               break;
 837 +                               case 5:
 838 +                                       laguna_nor_partitions[3].size = SZ_128M - SZ_256K - SZ_128K - SZ_2M;
 839 +                                       laguna_nor_res.end = CNS3XXX_FLASH_BASE + SZ_128M - 1;
 840 +                               break;
 841 +                       }
 842 +                       platform_device_register(&laguna_nor_pdev);
 843 +               }
 844 +
 845 +               if (laguna_info.config2_bitmap & (SPI_FLASH_LOAD)) {
 846 +                       switch (laguna_info.spi_flash_size) {
 847 +                               case 1:
 848 +                                       laguna_spi_partitions[3].size = SZ_4M - SZ_2M;
 849 +                               break;
 850 +                               case 2:
 851 +                                       laguna_spi_partitions[3].size = SZ_8M - SZ_2M;
 852 +                               break;
 853 +                               case 3:
 854 +                                       laguna_spi_partitions[3].size = SZ_16M - SZ_2M;
 855 +                               break;
 856 +                               case 4:
 857 +                                       laguna_spi_partitions[3].size = SZ_32M - SZ_2M;
 858 +                               break;
 859 +                               case 5:
 860 +                                       laguna_spi_partitions[3].size = SZ_64M - SZ_2M;
 861 +                               break;
 862 +                       }
 863 +                       spi_register_board_info(ARRAY_AND_SIZE(laguna_spi_devices));
 864 +               }
 865 +
 866 +               if ((laguna_info.config_bitmap & SPI0_LOAD) ||
 867 +                   (laguna_info.config_bitmap & SPI1_LOAD))
 868 +                       platform_device_register(&laguna_spi_controller);
 869 +
 870 +               /*
 871 +                * Do any model specific setup not known by the bitmap by matching
 872 +                *  the first 6 characters of the model name
 873 +                */
 874 +
 875 +               if ( (strncmp(laguna_info.model, "GW2388", 6) == 0)
 876 +                 || (strncmp(laguna_info.model, "GW2389", 6) == 0) )
 877 +               {
 878 +                       // configure GPIO's
 879 +                       laguna_register_gpio(ARRAY_AND_SIZE(laguna_gpio_gw2388));
 880 +                       // configure LED's
 881 +                       laguna_gpio_leds_data.num_leds = 2;
 882 +               } else if (strncmp(laguna_info.model, "GW2387", 6) == 0) {
 883 +                       // configure GPIO's
 884 +                       laguna_register_gpio(ARRAY_AND_SIZE(laguna_gpio_gw2387));
 885 +                       // configure LED's
 886 +                       laguna_gpio_leds_data.num_leds = 2;
 887 +               } else if (strncmp(laguna_info.model, "GW2384", 6) == 0) {
 888 +                       // configure GPIO's
 889 +                       laguna_register_gpio(ARRAY_AND_SIZE(laguna_gpio_gw2384));
 890 +                       // configure LED's
 891 +                       laguna_gpio_leds_data.num_leds = 1;
 892 +               } else if (strncmp(laguna_info.model, "GW2383", 6) == 0) {
 893 +                       // configure GPIO's
 894 +                       laguna_register_gpio(ARRAY_AND_SIZE(laguna_gpio_gw2383));
 895 +                       // configure LED's
 896 +                       laguna_gpio_leds[0].gpio = 107;
 897 +                       laguna_gpio_leds_data.num_leds = 1;
 898 +               } else if (strncmp(laguna_info.model, "GW2382", 6) == 0) {
 899 +                       // configure GPIO's
 900 +                       laguna_register_gpio(ARRAY_AND_SIZE(laguna_gpio_gw2382));
 901 +                       // configure LED's
 902 +                       laguna_gpio_leds[0].gpio = 107;
 903 +                       laguna_gpio_leds_data.num_leds = 1;
 904 +               } else if (strncmp(laguna_info.model, "GW2380", 6) == 0) {
 905 +                       // configure GPIO's
 906 +                       laguna_register_gpio(ARRAY_AND_SIZE(laguna_gpio_gw2380));
 907 +                       // configure LED's
 908 +                       laguna_gpio_leds[0].gpio = 107;
 909 +                       laguna_gpio_leds[1].gpio = 106;
 910 +                       laguna_gpio_leds_data.num_leds = 2;
 911 +               } else if (strncmp(laguna_info.model, "GW2391", 6) == 0) {
 912 +                       // configure GPIO's
 913 +                       laguna_register_gpio(ARRAY_AND_SIZE(laguna_gpio_gw2391));
 914 +                       // configure LED's
 915 +                       laguna_gpio_leds_data.num_leds = 2;
 916 +               }
 917 +               platform_device_register(&laguna_gpio_leds_device);
 918 +       } else {
 919 +               // Do some defaults here, not sure what yet
 920 +       }
 921 +       return 0;
 922 +}
 923 +
 924 +late_initcall(laguna_model_setup);
 925 +
 926 +MACHINE_START(GW2388, "Gateworks Corporation Laguna Platform")
 927 +       .atag_offset    = 0x100,
 928 +       .map_io         = laguna_map_io,
 929 +       .init_irq       = cns3xxx_init_irq,
 930 +       .timer          = &cns3xxx_timer,
 931 +       .handle_irq     = gic_handle_irq,
 932 +       .init_machine   = laguna_init,
 933 +       .restart        = cns3xxx_restart,
 934 +MACHINE_END
 935 --- a/arch/arm/mach-cns3xxx/Kconfig
 936 +++ b/arch/arm/mach-cns3xxx/Kconfig
 937 @@ -11,4 +11,14 @@ config MACH_CNS3420VB
 938           This is a platform with an on-board ARM11 MPCore and has support
 939           for USB, USB-OTG, MMC/SD/SDIO, SATA, PCI-E, etc.
 940
 941 +config MACH_GW2388
 942 +       bool "Support for Gateworks Laguna Platform"
 943 +       select HAVE_ARM_SCU if SMP
 944 +       select MIGHT_HAVE_PCI
 945 +       help
 946 +         Include support for the Gateworks Laguna Platform
 947 +
 948 +         This is a platform with an on-board ARM11 MPCore and has support
 949 +         for USB, USB-OTG, MMC/SD/SDIO, SATA, PCI-E, I2C, GIG, etc.
 950 +
 951  endmenu
 952 --- a/arch/arm/mach-cns3xxx/Makefile
 953 +++ b/arch/arm/mach-cns3xxx/Makefile
 954 @@ -1,6 +1,7 @@
 955  obj-$(CONFIG_ARCH_CNS3XXX)             += core.o pm.o devices.o
 956  obj-$(CONFIG_PCI)                      += pcie.o
 957  obj-$(CONFIG_MACH_CNS3420VB)           += cns3420vb.o
 958 +obj-$(CONFIG_MACH_GW2388)              += laguna.o
 959  obj-$(CONFIG_SMP)                      += platsmp.o headsmp.o
 960  obj-$(CONFIG_HOTPLUG_CPU)              += hotplug.o
 961  obj-$(CONFIG_LOCAL_TIMERS)             += localtimer.o
 962 --- a/arch/arm/mach-cns3xxx/devices.c
 963 +++ b/arch/arm/mach-cns3xxx/devices.c
 964 @@ -19,6 +19,7 @@
 965  #include <mach/cns3xxx.h>
 966  #include <mach/irqs.h>
 967  #include <mach/pm.h>
 968 +#include <asm/mach-types.h>
 969  #include "core.h"
 970  #include "devices.h"
 971
 972 @@ -102,7 +103,11 @@ void __init cns3xxx_sdhci_init(void)
 973         u32 gpioa_pins = __raw_readl(gpioa);
 974
 975         /* MMC/SD pins share with GPIOA */
 976 -       gpioa_pins |= 0x1fff0004;
 977 +       if (machine_is_gw2388()) {
 978 +               gpioa_pins |= 0x1fff0000;
 979 +       } else {
 980 +               gpioa_pins |= 0x1fff0004;
 981 +       }
 982         __raw_writel(gpioa_pins, gpioa);
 983
 984         cns3xxx_pwr_clk_en(CNS3XXX_PWR_CLK_EN(SDIO));