target/linux/cns21xx/patches-3.10/100-cns21xx-core.patch

   1 --- a/arch/arm/Kconfig
   2 +++ b/arch/arm/Kconfig
   3 @@ -206,6 +206,11 @@ config NEED_RET_TO_USER
   4  config ARCH_MTD_XIP
   5         bool
   6
   7 +config ARM_L1_CACHE_SHIFT_4
   8 +       bool
   9 +       help
  10 +         Setting ARM L1 cache line size to 16 bytes.
  11 +
  12  config VECTORS_BASE
  13         hex
  14         default 0xffff0000 if MMU || CPU_HIGH_VECTOR
  15 @@ -361,6 +366,15 @@ config ARCH_AT91
  16           This enables support for systems based on Atmel
  17           AT91RM9200 and AT91SAM9* processors.
  18
  19 +config ARCH_CNS21XX
  20 +       bool "Cavium Networks CNS21xx family"
  21 +       select CPU_FA526
  22 +       select PLAT_FA
  23 +       select PLAT_FA_TIME
  24 +       select ARM_L1_CACHE_SHIFT_4
  25 +       help
  26 +         Support for Cavium Networks CNS21xx family.
  27 +
  28  config ARCH_CLPS711X
  29         bool "Cirrus Logic CLPS711x/EP721x/EP731x-based"
  30         select ARCH_REQUIRE_GPIOLIB
  31 @@ -930,6 +944,8 @@ source "arch/arm/mach-davinci/Kconfig"
  32
  33  source "arch/arm/mach-dove/Kconfig"
  34
  35 +source "arch/arm/mach-cns21xx/Kconfig"
  36 +
  37  source "arch/arm/mach-ep93xx/Kconfig"
  38
  39  source "arch/arm/mach-footbridge/Kconfig"
  40 --- /dev/null
  41 +++ b/arch/arm/mach-cns21xx/Kconfig
  42 @@ -0,0 +1,6 @@
  43 +if ARCH_CNS21XX
  44 +
  45 +menu "Cavium Networks CNS21xx based machines"
  46 +endmenu
  47 +
  48 +endif
  49 --- /dev/null
  50 +++ b/arch/arm/mach-cns21xx/Makefile
  51 @@ -0,0 +1,10 @@
  52 +#
  53 +# Makefile for the linux kernel.
  54 +#
  55 +
  56 +# Object file lists.
  57 +
  58 +obj-y          := core.o irq.o mm.o time.o idle.o
  59 +
  60 +# machine specific files
  61 +
  62 --- /dev/null
  63 +++ b/arch/arm/mach-cns21xx/Makefile.boot
  64 @@ -0,0 +1,3 @@
  65 +   zreladdr-y  += 0x00008000
  66 +params_phys-y  := 0x00000100
  67 +initrd_phys-y  := 0x00C00000
  68 --- a/arch/arm/Makefile
  69 +++ b/arch/arm/Makefile
  70 @@ -146,6 +146,7 @@ machine-$(CONFIG_ARCH_AT91)         += at91
  71  machine-$(CONFIG_ARCH_BCM)             += bcm
  72  machine-$(CONFIG_ARCH_BCM2835)         += bcm2835
  73  machine-$(CONFIG_ARCH_CLPS711X)                += clps711x
  74 +machine-$(CONFIG_ARCH_CNS21XX)         += cns21xx
  75  machine-$(CONFIG_ARCH_CNS3XXX)         += cns3xxx
  76  machine-$(CONFIG_ARCH_DAVINCI)         += davinci
  77  machine-$(CONFIG_ARCH_DOVE)            += dove
  78 --- /dev/null
  79 +++ b/arch/arm/mach-cns21xx/common.h
  80 @@ -0,0 +1,20 @@
  81 +/*
  82 + *  Copyright (c) 2008 Cavium Networks
  83 + *  Copyright (c) 2010-2012 Gabor Juhos <juhosg@openwrt.org>
  84 + *
  85 + *  This file is free software; you can redistribute it and/or modify
  86 + *  it under the terms of the GNU General Public License, Version 2, as
  87 + *  published by the Free Software Foundation.
  88 + */
  89 +
  90 +#ifndef _MACH_CNS21XX_COMMON_H
  91 +#define _MACH_CNS21XX_COMMON_H
  92 +
  93 +void cns21xx_restart(char mode, const char *cmd);
  94 +void cns21xx_map_io(void);
  95 +void cns21xx_init_irq(void);
  96 +void cns21xx_timer_init(void);
  97 +
  98 +extern struct sys_timer cns21xx_timer;
  99 +
 100 +#endif /* _MACH_CNS21XX_COMMON_H */
 101 --- /dev/null
 102 +++ b/arch/arm/mach-cns21xx/mm.c
 103 @@ -0,0 +1,170 @@
 104 +/*
 105 + *  Copyright (c) 2008 Cavium Networks
 106 + *  Copyright (c) 2010-2012 Gabor Juhos <juhosg@openwrt.org>
 107 + *
 108 + *  This file is free software; you can redistribute it and/or modify
 109 + *  it under the terms of the GNU General Public License, Version 2, as
 110 + *  published by the Free Software Foundation.
 111 + */
 112 +
 113 +#include <linux/mm.h>
 114 +#include <linux/init.h>
 115 +
 116 +#include <asm/mach/map.h>
 117 +
 118 +#include <mach/hardware.h>
 119 +#include <mach/cns21xx.h>
 120 +
 121 +#include "common.h"
 122 +
 123 +/*
 124 + * Standard IO mapping
 125 + */
 126 +static struct map_desc cns21xx_io_desc[] __initdata = {
 127 +       {
 128 +               .virtual        = CNS21XX_FLASH_BANK0_BASE_VIRT,
 129 +               .pfn            = __phys_to_pfn(CNS21XX_FLASH_BANK0_BASE),
 130 +               .length         = SZ_256M,
 131 +               .type           = MT_DEVICE
 132 +       }, {
 133 +               .virtual        = CNS21XX_IDE_DEVICE_BASE_VIRT,
 134 +               .pfn            = __phys_to_pfn(CNS21XX_IDE_DEVICE_BASE),
 135 +               .length         = SZ_4K,
 136 +               .type           = MT_DEVICE
 137 +       }, {
 138 +               .virtual        = CNS21XX_GDMAC_BASE_VIRT,
 139 +               .pfn            = __phys_to_pfn(CNS21XX_GDMAC_BASE),
 140 +               .length         = SZ_4K,
 141 +               .type           = MT_DEVICE
 142 +       }, {
 143 +               .virtual        = CNS21XX_NIC_BASE_VIRT,
 144 +               .pfn            = __phys_to_pfn(CNS21XX_NIC_BASE),
 145 +               .length         = SZ_4K,
 146 +               .type           = MT_DEVICE
 147 +       }, {
 148 +               .virtual        = CNS21XX_SPI_BASE_VIRT,
 149 +               .pfn            = __phys_to_pfn(CNS21XX_SPI_BASE),
 150 +               .length         = SZ_4K,
 151 +               .type           = MT_DEVICE
 152 +       }, {
 153 +               .virtual        = CNS21XX_PCM_BASE_VIRT,
 154 +               .pfn            = __phys_to_pfn(CNS21XX_PCM_BASE),
 155 +               .length         = SZ_4K,
 156 +               .type           = MT_DEVICE
 157 +       }, {
 158 +               .virtual        = CNS21XX_I2C_BASE_VIRT,
 159 +               .pfn            = __phys_to_pfn(CNS21XX_I2C_BASE),
 160 +               .length         = SZ_4K,
 161 +               .type           = MT_DEVICE
 162 +       }, {
 163 +               .virtual        = CNS21XX_I2S_BASE_VIRT,
 164 +               .pfn            = __phys_to_pfn(CNS21XX_I2S_BASE),
 165 +               .length         = SZ_4K,
 166 +               .type           = MT_DEVICE
 167 +       }, {
 168 +               .virtual        = CNS21XX_DDRC_BASE_VIRT,
 169 +               .pfn            = __phys_to_pfn(CNS21XX_DDRC_BASE),
 170 +               .length         = SZ_4K,
 171 +               .type           = MT_DEVICE
 172 +       }, {
 173 +               .virtual        = CNS21XX_SMC_BASE_VIRT,
 174 +               .pfn            = __phys_to_pfn(CNS21XX_SMC_BASE),
 175 +               .length         = SZ_4K,
 176 +               .type           = MT_DEVICE
 177 +       }, {
 178 +               .virtual        = CNS21XX_IDE_CTRL_BASE_VIRT,
 179 +               .pfn            = __phys_to_pfn(CNS21XX_IDE_CTRL_BASE),
 180 +               .length         = SZ_4K,
 181 +               .type           = MT_DEVICE
 182 +       }, {
 183 +               .virtual        = CNS21XX_MISC_BASE_VIRT,
 184 +               .pfn            = __phys_to_pfn(CNS21XX_MISC_BASE),
 185 +               .length         = SZ_4K,
 186 +               .type           = MT_DEVICE
 187 +       }, {
 188 +               .virtual        = CNS21XX_CPM_BASE_VIRT,
 189 +               .pfn            = __phys_to_pfn(CNS21XX_CPM_BASE),
 190 +               .length         = SZ_4K,
 191 +               .type           = MT_DEVICE
 192 +       }, {
 193 +               .virtual        = CNS21XX_UART0_BASE_VIRT,
 194 +               .pfn            = __phys_to_pfn(CNS21XX_UART0_BASE),
 195 +               .length         = SZ_4K,
 196 +               .type           = MT_DEVICE
 197 +       }, {
 198 +               .virtual        = CNS21XX_UART1_BASE_VIRT,
 199 +               .pfn            = __phys_to_pfn(CNS21XX_UART1_BASE),
 200 +               .length         = SZ_4K,
 201 +               .type           = MT_DEVICE
 202 +       }, {
 203 +               .virtual        = CNS21XX_TIMER_BASE_VIRT,
 204 +               .pfn            = __phys_to_pfn(CNS21XX_TIMER_BASE),
 205 +               .length         = SZ_4K,
 206 +               .type           = MT_DEVICE
 207 +       }, {
 208 +               .virtual        = CNS21XX_WDT_BASE_VIRT,
 209 +               .pfn            = __phys_to_pfn(CNS21XX_WDT_BASE),
 210 +               .length         = SZ_4K,
 211 +               .type           = MT_DEVICE
 212 +       }, {
 213 +               .virtual        = CNS21XX_RTC_BASE_VIRT,
 214 +               .pfn            = __phys_to_pfn(CNS21XX_RTC_BASE),
 215 +               .length         = SZ_4K,
 216 +               .type           = MT_DEVICE
 217 +       }, {
 218 +               .virtual        = CNS21XX_GPIOA_BASE_VIRT,
 219 +               .pfn            = __phys_to_pfn(CNS21XX_GPIOA_BASE),
 220 +               .length         = SZ_4K,
 221 +               .type           = MT_DEVICE
 222 +       }, {
 223 +               .virtual        = CNS21XX_GPIOB_BASE_VIRT,
 224 +               .pfn            = __phys_to_pfn(CNS21XX_GPIOB_BASE),
 225 +               .length         = SZ_4K,
 226 +               .type           = MT_DEVICE
 227 +       }, {
 228 +               .virtual        = CNS21XX_PCI_CFGDATA_BASE_VIRT,
 229 +               .pfn            = __phys_to_pfn(CNS21XX_PCI_CFGDATA_BASE),
 230 +               .length         = SZ_4K,
 231 +               .type           = MT_DEVICE
 232 +       }, {
 233 +               .virtual        = CNS21XX_PCI_CFGADDR_BASE_VIRT,
 234 +               .pfn            = __phys_to_pfn(CNS21XX_PCI_CFGADDR_BASE),
 235 +               .length         = SZ_4K,
 236 +               .type           = MT_DEVICE
 237 +       }, {
 238 +               .virtual        = CNS21XX_OHCI_CONFIG_BASE_VIRT,
 239 +               .pfn            = __phys_to_pfn(CNS21XX_OHCI_CONFIG_BASE),
 240 +               .length         = SZ_4K,
 241 +               .type           = MT_DEVICE
 242 +       }, {
 243 +               .virtual        = CNS21XX_OHCI_CTRL_BASE_VIRT,
 244 +               .pfn            = __phys_to_pfn(CNS21XX_OHCI_CTRL_BASE),
 245 +               .length         = SZ_4K,
 246 +               .type           = MT_DEVICE
 247 +       }, {
 248 +               .virtual        = CNS21XX_EHCI_CONFIG_BASE_VIRT,
 249 +               .pfn            = __phys_to_pfn(CNS21XX_EHCI_CONFIG_BASE),
 250 +               .length         = SZ_4K,
 251 +               .type           = MT_DEVICE
 252 +       }, {
 253 +               .virtual        = CNS21XX_EHCI_CTRL_BASE_VIRT,
 254 +               .pfn            = __phys_to_pfn(CNS21XX_EHCI_CTRL_BASE),
 255 +               .length         = SZ_4K,
 256 +               .type           = MT_DEVICE
 257 +       }, {
 258 +               .virtual        = CNS21XX_USB_DEVICE_BASE_VIRT,
 259 +               .pfn            = __phys_to_pfn(CNS21XX_USB_DEVICE_BASE),
 260 +               .length         = SZ_4K,
 261 +               .type           = MT_DEVICE
 262 +       }, {
 263 +               .virtual        = CNS21XX_INTC_BASE_VIRT,
 264 +               .pfn            = __phys_to_pfn(CNS21XX_INTC_BASE),
 265 +               .length         = SZ_4K,
 266 +               .type           = MT_DEVICE
 267 +       }
 268 +};
 269 +
 270 +void __init cns21xx_map_io(void)
 271 +{
 272 +       iotable_init(cns21xx_io_desc, ARRAY_SIZE(cns21xx_io_desc));
 273 +}
 274 --- /dev/null
 275 +++ b/arch/arm/mach-cns21xx/include/mach/hardware.h
 276 @@ -0,0 +1,20 @@
 277 +/*
 278 + *  Copyright (c) 2008 Cavium Networks
 279 + *  Copyright (c) 2010-2012 Gabor Juhos <juhosg@openwrt.org>
 280 + *
 281 + *  This file is free software; you can redistribute it and/or modify
 282 + *  it under the terms of the GNU General Public License, Version 2, as
 283 + *  published by the Free Software Foundation.
 284 + */
 285 +
 286 +#ifndef _CNS21XX_HARDWARE_H
 287 +#define _CNS21XX_HARDWARE_H
 288 +
 289 +#ifndef __ASSEMBLY__
 290 +extern unsigned long cns21xx_get_pll_freq(void);
 291 +extern unsigned long cns21xx_get_cpu_freq(void);
 292 +extern unsigned long cns21xx_get_ahb_freq(void);
 293 +extern unsigned long cns21xx_get_apb_freq(void);
 294 +#endif
 295 +
 296 +#endif /* _CNS21XX_HARDWARE_H */
 297 --- /dev/null
 298 +++ b/arch/arm/mach-cns21xx/include/mach/debug-macro.S
 299 @@ -0,0 +1,25 @@
 300 +/*
 301 + *  Copyright (c) 2008 Cavium Networks
 302 + *  Copyright (c) 2010-2012 Gabor Juhos <juhosg@openwrt.org>
 303 + *
 304 + *  This file is free software; you can redistribute it and/or modify
 305 + *  it under the terms of the GNU General Public License, Version 2, as
 306 + *  published by the Free Software Foundation.
 307 + */
 308 +
 309 +#include <mach/cns21xx.h>
 310 +
 311 +/* TODO: make it configurable */
 312 +#define CNS21XX_DEBUG_UART_BASE                CNS21XX_UART0_BASE
 313 +#define CNS21XX_DEBUG_UART_BASE_VIRT   CNS21XX_UART0_BASE_VIRT
 314 +
 315 +       .macro  addruart, rp, rv
 316 +       mov     \rp, #(CNS21XX_DEBUG_UART_BASE)                         @ physical
 317 +       mov     \rv, #(CNS21XX_DEBUG_UART_BASE_VIRT & 0xff000000)       @virtual
 318 +       orr     \rv, \rv, #(CNS21XX_DEBUG_UART_BASE_VIRT & 0x00ff0000)
 319 +       orr     \rv, \rv, #(CNS21XX_DEBUG_UART_BASE_VIRT & 0x0000ff00)
 320 +       orr     \rv, \rv, #(CNS21XX_DEBUG_UART_BASE_VIRT & 0x000000ff)
 321 +       .endm
 322 +
 323 +#define UART_SHIFT 2
 324 +#include <asm/hardware/debug-8250.S>
 325 --- /dev/null
 326 +++ b/arch/arm/mach-cns21xx/include/mach/entry-macro.S
 327 @@ -0,0 +1,39 @@
 328 +/*
 329 + *  Copyright (c) 2008 Cavium Networks
 330 + *  Copyright (c) 2010-2012 Gabor Juhos <juhosg@openwrt.org>
 331 + *
 332 + *  This file is free software; you can redistribute it and/or modify
 333 + *  it under the terms of the GNU General Public License, Version 2, as
 334 + *  published by the Free Software Foundation.
 335 + */
 336 +
 337 +#include <mach/cns21xx.h>
 338 +#include <mach/irqs.h>
 339 +
 340 +#define INTC_IRQ_STATUS        0x1c
 341 +
 342 +       .macro  disable_fiq
 343 +       .endm
 344 +
 345 +       .macro  get_irqnr_preamble, base, tmp
 346 +       .endm
 347 +
 348 +       .macro  arch_ret_to_user, tmp1, tmp2
 349 +       .endm
 350 +
 351 +       .macro get_irqnr_and_base, irqnr, irqstat, base, tmp
 352 +       ldr             \base, =(CNS21XX_INTC_BASE_VIRT + INTC_IRQ_STATUS)
 353 +       ldr             \irqstat, [\base]
 354 +       mov             \irqnr, #0
 355 +9001:
 356 +       tst             \irqstat, #1
 357 +       bne             9002f
 358 +       add             \irqnr, \irqnr, #1
 359 +       mov             \irqstat, \irqstat, lsr #1
 360 +       cmp             \irqnr, #CNS21XX_NR_INTC_IRQS
 361 +       bcc             9001b
 362 +9002:
 363 +       .endm
 364 +
 365 +       .macro irq_prio_table
 366 +       .endm
 367 --- /dev/null
 368 +++ b/arch/arm/mach-cns21xx/include/mach/io.h
 369 @@ -0,0 +1,18 @@
 370 +/*
 371 + *  Copyright (c) 2008 Cavium Networks
 372 + *  Copyright (c) 2010-2012 Gabor Juhos <juhosg@openwrt.org>
 373 + *
 374 + *  This file is free software; you can redistribute it and/or modify
 375 + *  it under the terms of the GNU General Public License, Version 2, as
 376 + *  published by the Free Software Foundation.
 377 + */
 378 +
 379 +#ifndef _CNS21XX_IO_H
 380 +#define _CNS21XX_IO_H
 381 +
 382 +#define IO_SPACE_LIMIT 0xffffffff
 383 +
 384 +#define __io(p)                __typesafe_io(p)
 385 +#define __mem_pci(a)   (a)
 386 +
 387 +#endif /* _CNS21XX_IO_H */
 388 --- /dev/null
 389 +++ b/arch/arm/mach-cns21xx/include/mach/irqs.h
 390 @@ -0,0 +1,53 @@
 391 +/*
 392 + *  Copyright (c) 2008 Cavium Networks
 393 + *  Copyright (c) 2010-2012 Gabor Juhos <juhosg@openwrt.org>
 394 + *
 395 + *  This file is free software; you can redistribute it and/or modify
 396 + *  it under the terms of the GNU General Public License, Version 2, as
 397 + *  published by the Free Software Foundation.
 398 + */
 399 +
 400 +#ifndef _CNS21XX_IRQS_H
 401 +#define _CNS21XX_IRQS_H
 402 +
 403 +#define CNS21XX_IRQ_TIMER1     0
 404 +#define CNS21XX_IRQ_TIMER2     1
 405 +#define CNS21XX_IRQ_CPM                2
 406 +#define CNS21XX_IRQ_WDT                3
 407 +#define CNS21XX_IRQ_GPIO       4
 408 +#define CNS21XX_IRQ_PCI_INTA   5
 409 +#define CNS21XX_IRQ_PCI_INTB   6
 410 +#define CNS21XX_IRQ_PCI_BROKEN 7
 411 +#define CNS21XX_IRQ_AHB2PCI    8
 412 +#define CNS21XX_IRQ_UART0      9
 413 +#define CNS21XX_IRQ_UART1      10
 414 +#define CNS21XX_IRQ_GDMAC_TC   11
 415 +#define CNS21XX_IRQ_GDMAC_ERR  12
 416 +#define CNS21XX_IRQ_PCMCIA     13
 417 +#define CNS21XX_IRQ_RTC                14
 418 +#define CNS21XX_IRQ_PCM                15
 419 +#define CNS21XX_IRQ_USB_DEVICE 16
 420 +#define CNS21XX_IRQ_IDE                17
 421 +#define CNS21XX_IRQ_NIC_STATUS 18
 422 +#define CNS21XX_IRQ_NIC_TXTC   19
 423 +#define CNS21XX_IRQ_NIC_RXRC   20
 424 +#define CNS21XX_IRQ_NIC_TXQE   21
 425 +#define CNS21XX_IRQ_NIC_RXQF   22
 426 +#define CNS21XX_IRQ_OHCI       23
 427 +#define CNS21XX_IRQ_EHCI       24
 428 +#define CNS21XX_IRQ_I2S                25
 429 +#define CNS21XX_IRQ_SPI                26
 430 +#define CNS21XX_IRQ_I2C                27
 431 +#define CNS21XX_IRQ_USB_VBUS   28
 432 +#define CNS21XX_IRQ_EXT_29     29
 433 +#define CNS21XX_IRQ_EXT_30     30
 434 +#define CNS21XX_IRQ_HSDMAC     31
 435 +
 436 +#define CNS21XX_GPIO_IRQ_BASE  32
 437 +
 438 +#define CNS21XX_NR_INTC_IRQS   32
 439 +#define CNS21XX_NR_GPIO_IRQS   64
 440 +
 441 +#define NR_IRQS                        96
 442 +
 443 +#endif /* _CNS21XX_IRQS_H */
 444 --- /dev/null
 445 +++ b/arch/arm/mach-cns21xx/include/mach/timex.h
 446 @@ -0,0 +1,15 @@
 447 +/*
 448 + *  Copyright (c) 2008 Cavium Networks
 449 + *  Copyright (c) 2010-2012 Gabor Juhos <juhosg@openwrt.org>
 450 + *
 451 + *  This file is free software; you can redistribute it and/or modify
 452 + *  it under the terms of the GNU General Public License, Version 2, as
 453 + *  published by the Free Software Foundation.
 454 + */
 455 +
 456 +#ifndef _CNS21XX_TIMEX_H
 457 +#define _CNS21XX_TIMEX_H
 458 +
 459 +#define CLOCK_TICK_RATE                43750000
 460 +
 461 +#endif /* _CNS21XX_TIMEX_H */
 462 --- /dev/null
 463 +++ b/arch/arm/mach-cns21xx/include/mach/uncompress.h
 464 @@ -0,0 +1,40 @@
 465 +/*
 466 + *  Copyright (c) 2008 Cavium Networks
 467 + *  Copyright (c) 2010-2012 Gabor Juhos <juhosg@openwrt.org>
 468 + *
 469 + *  This file is free software; you can redistribute it and/or modify
 470 + *  it under the terms of the GNU General Public License, Version 2, as
 471 + *  published by the Free Software Foundation.
 472 + */
 473 +
 474 +#ifndef _CNS21XX_UNCOMPRESS_H
 475 +#define _CNS21XX_UNCOMPRESS_H
 476 +
 477 +#define UART_BASE      0x78000000
 478 +
 479 +#define UART_REG(offs) (*((volatile unsigned int *)(UART_BASE + offs)))
 480 +
 481 +#define UART_THR       UART_REG(0x00)
 482 +#define UART_LSR       UART_REG(0x14)
 483 +#define THR_EMPTY      (1 << 5)
 484 +
 485 +#define UART_THR_EMPTY()     (((UART_LSR) & THR_EMPTY) == (THR_EMPTY))
 486 +
 487 +static void putc(int c)
 488 +{
 489 +       if (c != 0) {
 490 +               while (!UART_THR_EMPTY())
 491 +                       barrier();
 492 +
 493 +               UART_THR = (int)(c & 0xFF);
 494 +       }
 495 +}
 496 +
 497 +static inline void flush(void)
 498 +{
 499 +}
 500 +
 501 +#define arch_decomp_setup()
 502 +#define arch_decomp_wdog()
 503 +
 504 +#endif /* _CNS21XX_UNCOMPRESS_H */
 505 --- /dev/null
 506 +++ b/arch/arm/mach-cns21xx/irq.c
 507 @@ -0,0 +1,177 @@
 508 +/*
 509 + *  Copyright (c) 2008 Cavium Networks
 510 + *  Copyright (c) 2010-2012 Gabor Juhos <juhosg@openwrt.org>
 511 + *
 512 + *  This file is free software; you can redistribute it and/or modify
 513 + *  it under the terms of the GNU General Public License, Version 2, as
 514 + *  published by the Free Software Foundation.
 515 + */
 516 +
 517 +#include <linux/init.h>
 518 +#include <linux/interrupt.h>
 519 +#include <linux/irq.h>
 520 +#include <linux/io.h>
 521 +#include <linux/ioport.h>
 522 +#include <linux/cpu.h>
 523 +
 524 +#include <asm/system_misc.h>
 525 +
 526 +#include <mach/cns21xx.h>
 527 +
 528 +#define        INTC_INTERRUPT_RAW_STATUS_REG           0x000
 529 +#define        INTC_EDGE_INTERRUPT_SOURCE_CLEAR_REG    0x004
 530 +#define        INTC_INTERRUPT_MASK_REG                 0x008
 531 +#define        INTC_INTERRUPT_MASK_CLEAR_REG           0x00c
 532 +#define        INTC_INTERRUPT_TRIGGER_MODE_REG         0x010
 533 +#define        INTC_INTERRUPT_TRIGGER_LEVEL_REG        0x014
 534 +#define        INTC_FIQ_SELECT_REG                     0x018
 535 +#define        INTC_IRQ_STATUS_REG                     0x01c
 536 +#define        INTC_FIQ_STATUS_REG                     0x020
 537 +#define        INTC_SOFTWARE_INTERRUPT_REG             0x024
 538 +#define        INTC_SOFTWARE_INTERRUPT_CLEAR_REG       0x028
 539 +#define        INTC_SOFTWARE_PRIORITY_MASK_REG         0x02c
 540 +#define        INTC_POWER_MANAGEMENT_INTERRUPT_REG     0x034
 541 +
 542 +#define        INTC_VECTOR_ADDRESS_REG(_x)             ((_x) + 0x040)
 543 +#define        INTC_PRIORITY_REG(_x)                   ((_x) + 0x0c0)
 544 +#define        INTC_IRQ_VECTOR_ADDRESS_REG             0x140
 545 +#define        INTC_VECTOR_INTERRUPT_ENABLE_REG        0x144
 546 +
 547 +#define INTC_SIZE                              0x148
 548 +
 549 +static unsigned int cns21xx_irq_types[CNS21XX_NR_INTC_IRQS] = {
 550 +       [CNS21XX_IRQ_TIMER1]    = IRQ_TYPE_EDGE_RISING,
 551 +       [CNS21XX_IRQ_TIMER2]    = IRQ_TYPE_EDGE_RISING,
 552 +       [CNS21XX_IRQ_CPM]       = IRQ_TYPE_EDGE_FALLING,
 553 +       [CNS21XX_IRQ_WDT]       = IRQ_TYPE_EDGE_RISING,
 554 +       [CNS21XX_IRQ_GPIO]      = IRQ_TYPE_NONE,
 555 +       [CNS21XX_IRQ_PCI_INTA]  = IRQ_TYPE_LEVEL_LOW,
 556 +       [CNS21XX_IRQ_PCI_INTB]  = IRQ_TYPE_LEVEL_LOW,
 557 +       [CNS21XX_IRQ_PCI_BROKEN] = IRQ_TYPE_LEVEL_HIGH,
 558 +       [CNS21XX_IRQ_AHB2PCI]   = IRQ_TYPE_LEVEL_HIGH,
 559 +       [CNS21XX_IRQ_UART0]     = IRQ_TYPE_LEVEL_HIGH,
 560 +       [CNS21XX_IRQ_UART1]     = IRQ_TYPE_LEVEL_HIGH,
 561 +       [CNS21XX_IRQ_GDMAC_TC]  = IRQ_TYPE_LEVEL_HIGH,
 562 +       [CNS21XX_IRQ_GDMAC_ERR] = IRQ_TYPE_LEVEL_HIGH,
 563 +       [CNS21XX_IRQ_PCMCIA]    = IRQ_TYPE_NONE,
 564 +       [CNS21XX_IRQ_RTC]       = IRQ_TYPE_LEVEL_HIGH,
 565 +       [CNS21XX_IRQ_PCM]       = IRQ_TYPE_LEVEL_LOW,
 566 +       [CNS21XX_IRQ_USB_DEVICE] = IRQ_TYPE_LEVEL_LOW,
 567 +       [CNS21XX_IRQ_IDE]       = IRQ_TYPE_LEVEL_HIGH,
 568 +       [CNS21XX_IRQ_NIC_STATUS] = IRQ_TYPE_LEVEL_HIGH,
 569 +       [CNS21XX_IRQ_NIC_TXTC]  = IRQ_TYPE_EDGE_RISING,
 570 +       [CNS21XX_IRQ_NIC_RXRC]  = IRQ_TYPE_EDGE_RISING,
 571 +       [CNS21XX_IRQ_NIC_TXQE]  = IRQ_TYPE_EDGE_RISING,
 572 +       [CNS21XX_IRQ_NIC_RXQF]  = IRQ_TYPE_EDGE_RISING,
 573 +       [CNS21XX_IRQ_OHCI]      = IRQ_TYPE_LEVEL_LOW,
 574 +       [CNS21XX_IRQ_EHCI]      = IRQ_TYPE_LEVEL_LOW,
 575 +       [CNS21XX_IRQ_I2S]       = IRQ_TYPE_LEVEL_LOW,
 576 +       [CNS21XX_IRQ_SPI]       = IRQ_TYPE_LEVEL_LOW,
 577 +       [CNS21XX_IRQ_I2C]       = IRQ_TYPE_LEVEL_LOW,
 578 +       [CNS21XX_IRQ_USB_VBUS]  = IRQ_TYPE_EDGE_RISING,
 579 +       [CNS21XX_IRQ_EXT_29]    = IRQ_TYPE_NONE,
 580 +       [CNS21XX_IRQ_EXT_30]    = IRQ_TYPE_NONE,
 581 +       [CNS21XX_IRQ_HSDMAC]    = IRQ_TYPE_EDGE_RISING,
 582 +};
 583 +
 584 +static void __iomem *cns21xx_intc_base;
 585 +
 586 +static inline void cns21xx_intc_writel(u32 val, unsigned int reg)
 587 +{
 588 +       __raw_writel(val, cns21xx_intc_base + reg);
 589 +}
 590 +
 591 +static inline u32 cns21xx_intc_readl(unsigned int reg)
 592 +{
 593 +       return __raw_readl(cns21xx_intc_base + reg);
 594 +}
 595 +
 596 +static void cns21xx_irq_ack(struct irq_data *d)
 597 +{
 598 +       cns21xx_intc_writel(1 << d->irq, INTC_EDGE_INTERRUPT_SOURCE_CLEAR_REG);
 599 +}
 600 +
 601 +static void cns21xx_irq_mask(struct irq_data *d)
 602 +{
 603 +       cns21xx_intc_writel(1 << d->irq, INTC_INTERRUPT_MASK_REG);
 604 +}
 605 +
 606 +static void cns21xx_irq_unmask(struct irq_data *d)
 607 +{
 608 +       cns21xx_intc_writel(1 << d->irq, INTC_INTERRUPT_MASK_CLEAR_REG);
 609 +}
 610 +
 611 +static struct irq_chip cns21xx_irq_chip = {
 612 +       .name   = "INTC",
 613 +       .irq_ack = cns21xx_irq_ack,
 614 +       .irq_mask = cns21xx_irq_mask,
 615 +       .irq_unmask = cns21xx_irq_unmask,
 616 +};
 617 +
 618 +static struct resource cns21xx_intc_resource = {
 619 +       .name   = "INTC",
 620 +       .flags  = IORESOURCE_MEM,
 621 +       .start  = CNS21XX_INTC_BASE,
 622 +       .end    = CNS21XX_INTC_BASE + INTC_SIZE - 1,
 623 +};
 624 +
 625 +void __init cns21xx_init_irq(void)
 626 +{
 627 +       unsigned int mode = 0;
 628 +       unsigned int level = 0;
 629 +       int i;
 630 +
 631 +       /*
 632 +        * Disable the idle handler by default since it is buggy
 633 +        * For more info see arch/arm/mach-gemini/idle.c
 634 +        */
 635 +       cpu_idle_poll_ctrl(true);
 636 +
 637 +       request_resource(&iomem_resource, &cns21xx_intc_resource);
 638 +       cns21xx_intc_base = ioremap(cns21xx_intc_resource.start, INTC_SIZE);
 639 +
 640 +       cns21xx_intc_writel(0xffffffff, INTC_INTERRUPT_MASK_REG);
 641 +       cns21xx_intc_writel(0xffffffff, INTC_EDGE_INTERRUPT_SOURCE_CLEAR_REG);
 642 +       cns21xx_intc_writel(0xffffffff, INTC_SOFTWARE_INTERRUPT_CLEAR_REG);
 643 +       cns21xx_intc_writel(0, INTC_SOFTWARE_PRIORITY_MASK_REG);
 644 +       cns21xx_intc_writel(0, INTC_FIQ_SELECT_REG);
 645 +       cns21xx_intc_writel(0, INTC_VECTOR_INTERRUPT_ENABLE_REG);
 646 +
 647 +       for (i = 0; i < ARRAY_SIZE(cns21xx_irq_types);  i++) {
 648 +               irq_flow_handler_t handler;
 649 +
 650 +               switch (cns21xx_irq_types[i]) {
 651 +               case IRQ_TYPE_EDGE_RISING:
 652 +                       handler = handle_edge_irq;
 653 +                       mode |= (1 << i);
 654 +                       break;
 655 +
 656 +               case IRQ_TYPE_EDGE_FALLING:
 657 +                       handler = handle_edge_irq;
 658 +                       mode |= (1 << i);
 659 +                       level |= (1 << i);
 660 +                       break;
 661 +
 662 +               case IRQ_TYPE_LEVEL_LOW:
 663 +                       handler = handle_level_irq;
 664 +                       level |= (1 << i);
 665 +                       break;
 666 +
 667 +               case IRQ_TYPE_LEVEL_HIGH:
 668 +               case IRQ_TYPE_NONE:
 669 +                       handler = handle_level_irq;
 670 +                       break;
 671 +
 672 +               default:
 673 +                       BUG();
 674 +                       break;
 675 +               }
 676 +
 677 +               irq_set_chip(i, &cns21xx_irq_chip);
 678 +               irq_set_handler(i, handler);
 679 +               set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
 680 +       }
 681 +
 682 +       cns21xx_intc_writel(mode, INTC_INTERRUPT_TRIGGER_MODE_REG);
 683 +       cns21xx_intc_writel(level, INTC_INTERRUPT_TRIGGER_LEVEL_REG);
 684 +}
 685 --- /dev/null
 686 +++ b/arch/arm/mach-cns21xx/time.c
 687 @@ -0,0 +1,25 @@
 688 +/*
 689 + *  Copyright (c) 2010-2012 Gabor Juhos <juhosg@openwrt.org>
 690 + *
 691 + *  This file is free software; you can redistribute it and/or modify
 692 + *  it under the terms of the GNU General Public License, Version 2, as
 693 + *  published by the Free Software Foundation.
 694 + */
 695 +
 696 +#include <linux/init.h>
 697 +#include <linux/irq.h>
 698 +
 699 +#include <asm/mach/time.h>
 700 +
 701 +#include <plat/time.h>
 702 +#include <mach/hardware.h>
 703 +#include <mach/cns21xx.h>
 704 +
 705 +#include "common.h"
 706 +
 707 +void __init cns21xx_timer_init(void)
 708 +{
 709 +       fa_timer_init(CNS21XX_TIMER_BASE, CNS21XX_IRQ_TIMER1, FA_TIMER1,
 710 +                     cns21xx_get_apb_freq());
 711 +}
 712 +
 713 --- /dev/null
 714 +++ b/arch/arm/mach-cns21xx/include/mach/cns21xx_powermgmt.h
 715 @@ -0,0 +1,591 @@
 716 +/*
 717 + *  Copyright (c) 2008 Cavium Networks
 718 + *  Copyright (c) 2010-2012 Gabor Juhos <juhosg@openwrt.org>
 719 + *
 720 + *  This file is free software; you can redistribute it and/or modify
 721 + *  it under the terms of the GNU General Public License, Version 2, as
 722 + *  published by the Free Software Foundation.
 723 + */
 724 +
 725 +#ifndef _CNS21XX_POWERMGMT_H
 726 +#define _CNS21XX_POWERMGMT_H
 727 +
 728 +#define PWRMGT_MEM_MAP_VALUE(reg_offset) \
 729 +       (*((u32 volatile *)(CNS21XX_CPM_BASE_VIRT + reg_offset)))
 730 +
 731 +/*
 732 + * define access macros
 733 + */
 734 +#define PWRMGT_CLOCK_GATE_CONTROL0_REG         PWRMGT_MEM_MAP_VALUE(0x00)
 735 +#define PWRMGT_CLOCK_GATE_CONTROL1_REG         PWRMGT_MEM_MAP_VALUE(0x04)
 736 +#define PWRMGT_SOFTWARE_RESET_CONTROL_REG      PWRMGT_MEM_MAP_VALUE(0x08)
 737 +#define PWRMGT_SYSTEM_CLOCK_CONTROL_REG                PWRMGT_MEM_MAP_VALUE(0x0C)
 738 +#define PWRMGT_PLL_POWER_DOWN_CONTROL_REG      PWRMGT_MEM_MAP_VALUE(0x10)
 739 +#define PWRMGT_CPU_INITIALIZATION_REG          PWRMGT_MEM_MAP_VALUE(0x14)
 740 +#define PWRMGT_PAD_DRIVE_STRENGTH_CONTROL_REG  PWRMGT_MEM_MAP_VALUE(0x1C)
 741 +#define PWRMGT_USB_DEVICE_POWERMGT_REG         PWRMGT_MEM_MAP_VALUE(0x20)
 742 +#define PWRMGT_REGULATOR_CONTROL_REG           PWRMGT_MEM_MAP_VALUE(0x24)
 743 +#define PWRMGT_RTC_XTAL_CONTROL_REG            PWRMGT_MEM_MAP_VALUE(0x28)
 744 +#define PWRMGT_PLL250_CONTROL_REG              PWRMGT_MEM_MAP_VALUE(0x2C)
 745 +
 746 +
 747 +/*
 748 + * define constants macros
 749 + */
 750 +#define PWRMGT_GLOBAL_SOFTWARE_RESET_MASK_BIT_INDEX            0
 751 +#define PWRMGT_PCMCIA_SOFTWARE_RESET_BIT_INDEX                 1
 752 +#define PWRMGT_IDE_SOFTWARE_RESET_BIT_INDEX                    2
 753 +#define PWRMGT_VIC_SOFTWARE_RESET_BIT_INDEX                    3
 754 +#define PWRMGT_DMA_SOFTWARE_RESET_BIT_INDEX                    4
 755 +#define PWRMGT_NIC_SOFTWARE_RESET_BIT_INDEX                    5
 756 +#define PWRMGT_USB_HOST_SOFTWARE_RESET_BIT_INDEX               6
 757 +#define PWRMGT_PCI_BRIDGE_SOFTWARE_RESET_BIT_INDEX             7
 758 +#define PWRMGT_P2S_SOFTWARE_RESET_BIT_INDEX                    8
 759 +#define PWRMGT_UART0_SOFTWARE_RESET_BIT_INDEX                  9
 760 +#define PWRMGT_UART1_SOFTWARE_RESET_BIT_INDEX                  10
 761 +#define PWRMGT_TIMER_SOFTWARE_RESET_BIT_INDEX                  11
 762 +#define PWRMGT_WDTIMER_SOFTWARE_RESET_BIT_INDEX                        12
 763 +#define PWRMGT_GPIO_SOFTWARE_RESET_BIT_INDEX                   13
 764 +#define PWRMGT_USB_DEVICE_SOFTWARE_RESET_BIT_INDEX             14
 765 +#define PWRMGT_FAST_ETHERNET_PHY_SOFTWARE_RESET_BIT_INDEX      15
 766 +#define PWRMGT_HSDMA_SOFTWARE_RESET_BIT_INDEX                  16
 767 +
 768 +#define PWRMGT_PLL_FREQUENCY_175MHZ            (0 << 0)
 769 +#define PWRMGT_PLL_FREQUENCY_200MHZ            (1 << 0)
 770 +#define PWRMGT_PLL_FREQUENCY_225MHZ            (2 << 0)
 771 +#define PWRMGT_PLL_FREQUENCY_250MHZ            (3 << 0)
 772 +
 773 +#define PWRMGT_CPUCLK_DIVIDER_BY_1             (0 << 2)
 774 +#define PWRMGT_CPUCLK_DIVIDER_BY_2             (1 << 2)
 775 +#define PWRMGT_CPUCLK_DIVIDER_BY_3             (2 << 2)
 776 +#define PWRMGT_CPUCLK_DIVIDER_BY_4             (3 << 2)
 777 +
 778 +#define PWRMGT_HCLK_DIVIDER_BY_1               (0 << 4)
 779 +#define PWRMGT_HCLK_DIVIDER_BY_2               (1 << 4)
 780 +#define PWRMGT_HCLK_DIVIDER_BY_3               (2 << 4)
 781 +#define PWRMGT_HCLK_DIVIDER_BY_4               (3 << 4)
 782 +
 783 +#define PWRMGT_HCLK_SOURCE_FCLK                        (0 << 6)
 784 +#define PWRMGT_HCLK_SOURCE_125MHZ              (1 << 6)
 785 +
 786 +#define PWRMGT_PCLK_DIVIDER_BY_1               (0 << 8)
 787 +#define PWRMGT_PCLK_DIVIDER_BY_2               (1 << 8)
 788 +#define PWRMGT_PCLK_DIVIDER_BY_3               (2 << 8)
 789 +#define PWRMGT_PCLK_DIVIDER_BY_4               (3 << 8)
 790 +
 791 +#define PWRMGT_PCICLK_DIVIDER_BY_1             (0 << 10)
 792 +#define PWRMGT_PCICLK_DIVIDER_BY_2             (1 << 10)
 793 +#define PWRMGT_PCICLK_DIVIDER_BY_3             (2 << 10)
 794 +#define PWRMGT_PCICLK_DIVIDER_BY_4             (3 << 10)
 795 +
 796 +
 797 +#define PWRMGT_PLLCLK_TO_CPUCLK_RATIO_BY_1     1
 798 +#define PWRMGT_PLLCLK_TO_CPUCLK_RATIO_BY_2     2
 799 +#define PWRMGT_PLLCLK_TO_CPUCLK_RATIO_BY_3     3
 800 +#define PWRMGT_PLLCLK_TO_CPUCLK_RATIO_BY_4     4
 801 +
 802 +#define PWRMGT_CPUCLK_TO_HCLK_RATIO_BY_1       1
 803 +#define PWRMGT_CPUCLK_TO_HCLK_RATIO_BY_2       2
 804 +#define PWRMGT_CPUCLK_TO_HCLK_RATIO_BY_3       3
 805 +#define PWRMGT_CPUCLK_TO_HCLK_RATIO_BY_4       4
 806 +
 807 +#define PWRMGT_HCLK_TO_PCLK_RATIO_BY_1         1
 808 +#define PWRMGT_HCLK_TO_PCLK_RATIO_BY_2         2
 809 +#define PWRMGT_HCLK_TO_PCLK_RATIO_BY_3         3
 810 +#define PWRMGT_HCLK_TO_PCLK_RATIO_BY_4         4
 811 +
 812 +/*
 813 + * Macro defines for Clock Gate        Control
 814 + */
 815 +#define HAL_PWRMGT_DISABLE_DRAMC_CLOCK() \
 816 +{ \
 817 +    PWRMGT_CLOCK_GATE_CONTROL0_REG &= ~(0x1); \
 818 +}
 819 +
 820 +
 821 +#define HAL_PWRMGT_ENABLE_NIC_CLOCK() \
 822 +{ \
 823 +    PWRMGT_PLL_POWER_DOWN_CONTROL_REG &= ~(0x1 << 0); \
 824 +    PWRMGT_CLOCK_GATE_CONTROL0_REG |= (0x0F << 20); \
 825 +    PWRMGT_SOFTWARE_RESET_CONTROL_REG |= (0x1 << 5); \
 826 +}
 827 +
 828 +#define HAL_PWRMGT_DISABLE_NIC_CLOCK() \
 829 +{ \
 830 +    PWRMGT_CLOCK_GATE_CONTROL0_REG &= ~(0x0F << 20); \
 831 +}
 832 +
 833 +
 834 +#define HAL_PWRMGT_ENABLE_PCI_BRIDGE_33M_CLOCK() \
 835 +{ \
 836 +    PWRMGT_PLL_POWER_DOWN_CONTROL_REG &= ~(0x1 << 1); \
 837 +    PWRMGT_SYSTEM_CLOCK_CONTROL_REG &= ~(0x3 << 10); \
 838 +    PWRMGT_SYSTEM_CLOCK_CONTROL_REG |= (0x1 << 10); \
 839 +    PWRMGT_CLOCK_GATE_CONTROL0_REG |= (0x1 << 28) | (0x1 << 30); \
 840 +    PWRMGT_SOFTWARE_RESET_CONTROL_REG |= (0x1 << 7); \
 841 +}
 842 +
 843 +#define HAL_PWRMGT_ENABLE_PCI_BRIDGE_66M_CLOCK() \
 844 +{ \
 845 +    PWRMGT_PLL_POWER_DOWN_CONTROL_REG &= ~(0x1 << 1); \
 846 +    PWRMGT_SYSTEM_CLOCK_CONTROL_REG &= ~(0x3 << 10); \
 847 +    PWRMGT_SYSTEM_CLOCK_CONTROL_REG |= (0x0 << 10); \
 848 +    PWRMGT_CLOCK_GATE_CONTROL0_REG |= (0x1 << 28) | (0x1 << 30); \
 849 +    PWRMGT_SOFTWARE_RESET_CONTROL_REG |= (0x1 << 7); \
 850 +}
 851 +
 852 +#define HAL_PWRMGT_DISABLE_PCI_CLOCK() \
 853 +{ \
 854 +    PWRMGT_CLOCK_GATE_CONTROL0_REG &= ~((0x1 << 28) | (0x1 << 30)); \
 855 +}
 856 +
 857 +
 858 +#define HAL_PWRMGT_ENABLE_USB_CLOCK() \
 859 +{ \
 860 +    PWRMGT_PLL_POWER_DOWN_CONTROL_REG &= ~(0xF << 1); \
 861 +    PWRMGT_CLOCK_GATE_CONTROL0_REG |= (0x1 << 24); \
 862 +    PWRMGT_CLOCK_GATE_CONTROL1_REG |= (0x1 << 28); \
 863 +    PWRMGT_SOFTWARE_RESET_CONTROL_REG |= (0x1 << 6) | (0x1 << 14); \
 864 +}
 865 +
 866 +#define HAL_PWRMGT_DISABLE_USB_CLOCK() \
 867 +{ \
 868 +    PWRMGT_CLOCK_GATE_CONTROL0_REG &= ~(0x1 << 24); \
 869 +    PWRMGT_CLOCK_GATE_CONTROL1_REG &= ~(0x1 << 28); \
 870 +}
 871 +
 872 +
 873 +#define HAL_PWRMGT_ENABLE_DMA_CLOCK() \
 874 +{ \
 875 +    PWRMGT_CLOCK_GATE_CONTROL0_REG |= (0x1 << 16); \
 876 +    PWRMGT_SOFTWARE_RESET_CONTROL_REG |= (0x1 << 4); \
 877 +}
 878 +
 879 +#define HAL_PWRMGT_DISABLE_DMA_CLOCK() \
 880 +{ \
 881 +    PWRMGT_CLOCK_GATE_CONTROL0_REG &= ~(0x1 << 16); \
 882 +}
 883 +
 884 +
 885 +#define HAL_PWRMGT_ENABLE_IDE_CLOCK() \
 886 +{ \
 887 +    PWRMGT_CLOCK_GATE_CONTROL0_REG |= (0x1 << 8) | (0x1 << 9); \
 888 +    PWRMGT_SOFTWARE_RESET_CONTROL_REG |= (0x1 << 2); \
 889 +}
 890 +
 891 +#define HAL_PWRMGT_DISABLE_IDE_CLOCK() \
 892 +{ \
 893 +    PWRMGT_CLOCK_GATE_CONTROL0_REG &= ~((0x1 << 8) | (0x1 << 9)); \
 894 +}
 895 +
 896 +
 897 +#define HAL_PWRMGT_ENABLE_UART0_CLOCK()        \
 898 +{ \
 899 +    PWRMGT_PLL_POWER_DOWN_CONTROL_REG &= ~((0x1 << 1) |        (0x1 << 2) | (0x1 << 5)); \
 900 +    PWRMGT_CLOCK_GATE_CONTROL1_REG |= (0x1 << 12); \
 901 +    PWRMGT_SOFTWARE_RESET_CONTROL_REG |= (0x1 << 9); \
 902 +}
 903 +
 904 +#define HAL_PWRMGT_DISABLE_UART0_CLOCK() \
 905 +{ \
 906 +    PWRMGT_CLOCK_GATE_CONTROL1_REG &= ~(0x1 << 12); \
 907 +}
 908 +
 909 +
 910 +#define HAL_PWRMGT_ENABLE_UART1_CLOCK()        \
 911 +{ \
 912 +    PWRMGT_PLL_POWER_DOWN_CONTROL_REG &= ~((0x1 << 1) |        (0x1 << 2) | (0x1 << 5)); \
 913 +    PWRMGT_CLOCK_GATE_CONTROL1_REG |= (0x1 << 13); \
 914 +    PWRMGT_SOFTWARE_RESET_CONTROL_REG |= (0x1 << 10); \
 915 +}
 916 +
 917 +#define HAL_PWRMGT_DISABLE_UART1_CLOCK() \
 918 +{ \
 919 +    PWRMGT_CLOCK_GATE_CONTROL1_REG &= ~(0x1 << 13); \
 920 +}
 921 +
 922 +
 923 +#define HAL_PWRMGT_ENABLE_PCMCIA_CLOCK() \
 924 +{ \
 925 +    PWRMGT_CLOCK_GATE_CONTROL0_REG |= (0x1 << 4) | (0x1 << 5); \
 926 +}
 927 +
 928 +#define HAL_PWRMGT_DISABLE_PCMCIA_CLOCK() \
 929 +{ \
 930 +    PWRMGT_CLOCK_GATE_CONTROL0_REG &= ~((0x1 << 4) | (0x1 << 5)); \
 931 +}
 932 +
 933 +
 934 +#define HAL_PWRMGT_ENABLE_GPIO_CLOCK() \
 935 +{ \
 936 +    PWRMGT_CLOCK_GATE_CONTROL1_REG |= (0x1 << 25); \
 937 +}
 938 +
 939 +#define HAL_PWRMGT_DISABLE_GPIO_CLOCK()        \
 940 +{ \
 941 +    PWRMGT_CLOCK_GATE_CONTROL1_REG &= ~(0x1 << 25); \
 942 +}
 943 +
 944 +
 945 +#define HAL_PWRMGT_ENABLE_WDTIMER_CLOCK() \
 946 +{ \
 947 +    PWRMGT_CLOCK_GATE_CONTROL1_REG |= (0x1 << 21) | (0x1 << 22); \
 948 +}
 949 +
 950 +#define HAL_PWRMGT_DISABLE_WDTIMER_CLOCK() \
 951 +{ \
 952 +    PWRMGT_CLOCK_GATE_CONTROL1_REG &= ~((0x1 << 21) | (0x1 << 22)); \
 953 +}
 954 +
 955 +
 956 +#define HAL_PWRMGT_ENABLE_RTC_CLOCK() \
 957 +{ \
 958 +    PWRMGT_CLOCK_GATE_CONTROL1_REG |= (0x1 << 23); \
 959 +}
 960 +
 961 +#define HAL_PWRMGT_DISABLE_RTC_CLOCK() \
 962 +{ \
 963 +    PWRMGT_CLOCK_GATE_CONTROL1_REG &= ~(0x1 << 23); \
 964 +}
 965 +
 966 +
 967 +#define HAL_PWRMGT_ENABLE_TIMER_CLOCK()        \
 968 +{ \
 969 +    PWRMGT_CLOCK_GATE_CONTROL1_REG |= (0x1 << 17) | (0x1 << 18)        | (0x1 << 19); \
 970 +}
 971 +
 972 +#define HAL_PWRMGT_DISABLE_TIMER_CLOCK() \
 973 +{ \
 974 +    PWRMGT_CLOCK_GATE_CONTROL1_REG &= ~((0x1 << 17) | (0x1 << 18) | (0x1 << 19)); \
 975 +}
 976 +
 977 +
 978 +#define HAL_PWRMGT_ENABLE_I2C_CLOCK() \
 979 +{ \
 980 +    PWRMGT_CLOCK_GATE_CONTROL1_REG |= (0x1 << 1); \
 981 +}
 982 +
 983 +#define HAL_PWRMGT_DISABLE_I2C_CLOCK() \
 984 +{ \
 985 +    PWRMGT_CLOCK_GATE_CONTROL1_REG &= ~(0x1 << 1); \
 986 +}
 987 +
 988 +
 989 +#define HAL_PWRMGT_ENABLE_I2S_CLOCK() \
 990 +{ \
 991 +    PWRMGT_PLL_POWER_DOWN_CONTROL_REG &= ~((0x1 << 5) |        (0x1 << 6)); \
 992 +    PWRMGT_CLOCK_GATE_CONTROL1_REG |= (0x1 << 1) | (0x1 << 10);        \
 993 +    PWRMGT_SOFTWARE_RESET_CONTROL_REG |= (0x1 << 8); \
 994 +}
 995 +
 996 +#define HAL_PWRMGT_DISABLE_I2S_CLOCK() \
 997 +{ \
 998 +    PWRMGT_CLOCK_GATE_CONTROL1_REG &= ~((0x1 << 1) | (0x1 << 10)); \
 999 +}
1000 +
1001 +
1002 +#define HAL_PWRMGT_ENABLE_PCM_CLOCK() \
1003 +{ \
1004 +    PWRMGT_PLL_POWER_DOWN_CONTROL_REG &= ~(0x1 << 5); \
1005 +    PWRMGT_CLOCK_GATE_CONTROL1_REG |= (0x1 << 1) | (0x1 << 6); \
1006 +    PWRMGT_SOFTWARE_RESET_CONTROL_REG |= (0x1 << 8); \
1007 +}
1008 +
1009 +#define HAL_PWRMGT_DISABLE_PCM_CLOCK() \
1010 +{ \
1011 +    PWRMGT_CLOCK_GATE_CONTROL1_REG &= ~((0x1 << 1) | (0x1 << 6)); \
1012 +}
1013 +
1014 +
1015 +#define HAL_PWRMGT_ENABLE_SPI_CLOCK() \
1016 +{ \
1017 +    PWRMGT_CLOCK_GATE_CONTROL1_REG |= (0x1 << 0) | (0x1 << 1); \
1018 +}
1019 +
1020 +#define HAL_PWRMGT_DISABLE_SPI_CLOCK() \
1021 +{ \
1022 +    PWRMGT_CLOCK_GATE_CONTROL1_REG &= ~((0x1 << 0) | (0x1 << 1)); \
1023 +}
1024 +
1025 +
1026 +#define HAL_PWRMGT_ENABLE_VIC_CLOCK() \
1027 +{ \
1028 +    PWRMGT_CLOCK_GATE_CONTROL0_REG |= (0x1 << 12); \
1029 +}
1030 +
1031 +#define HAL_PWRMGT_DISABLE_VIC_CLOCK() \
1032 +{ \
1033 +    PWRMGT_CLOCK_GATE_CONTROL0_REG &= ~(0x1 << 12); \
1034 +}
1035 +
1036 +
1037 +#define HAL_PWRMGT_ENABLE_SMC_CLOCK() \
1038 +{ \
1039 +    PWRMGT_CLOCK_GATE_CONTROL0_REG |= (0x1 << 4) | (0x1 << 5); \
1040 +}
1041 +
1042 +#define HAL_PWRMGT_DISABLE_SMC_CLOCK() \
1043 +{ \
1044 +    PWRMGT_CLOCK_GATE_CONTROL0_REG &= ~((0x1 << 4) | (0x1 << 5)); \
1045 +}
1046 +
1047 +
1048 +#define HAL_PWRMGT_ENABLE_HSDMA_CLOCK()        \
1049 +{ \
1050 +    PWRMGT_CLOCK_GATE_CONTROL1_REG |= (0x1 << 29); \
1051 +    PWRMGT_SOFTWARE_RESET_CONTROL_REG |= (0x1 << 16); \
1052 +}
1053 +
1054 +#define HAL_PWRMGT_DISABLE_HSDMA_CLOCK() \
1055 +{ \
1056 +    PWRMGT_CLOCK_GATE_CONTROL1_REG &= ~(0x1 << 29); \
1057 +}
1058 +
1059 +
1060 +
1061 +/*
1062 + * Macro defines for Reset Control
1063 + */
1064 +#define HAL_PWRMGT_GLOBAL_SOFTWARE_RESET() \
1065 +{ \
1066 +    PWRMGT_SOFTWARE_RESET_CONTROL_REG |= (0x1);        \
1067 +    PWRMGT_SOFTWARE_RESET_CONTROL_REG &= ~(0x1); \
1068 +}
1069 +
1070 +
1071 +/*
1072 + * Macro defines for System Clock Control
1073 + */
1074 +#define HAL_PWRMGT_SET_PLL_FREQUENCY_175MHZ() \
1075 +{ \
1076 +    PWRMGT_SYSTEM_CLOCK_CONTROL_REG &= ~0x3; \
1077 +}
1078 +
1079 +
1080 +#define HAL_PWRMGT_SET_PLL_FREQUENCY_200MHZ() \
1081 +{ \
1082 +    PWRMGT_SYSTEM_CLOCK_CONTROL_REG &= ~0x3; \
1083 +    PWRMGT_SYSTEM_CLOCK_CONTROL_REG |= 0x1; \
1084 +}
1085 +
1086 +
1087 +#define HAL_PWRMGT_SET_PLL_FREQUENCY_225MHZ() \
1088 +{ \
1089 +    PWRMGT_SYSTEM_CLOCK_CONTROL_REG &= ~0x3; \
1090 +    PWRMGT_SYSTEM_CLOCK_CONTROL_REG |= 0x2; \
1091 +}
1092 +
1093 +
1094 +#define HAL_PWRMGT_SET_PLL_FREQUENCY_250MHZ() \
1095 +{ \
1096 +    PWRMGT_SYSTEM_CLOCK_CONTROL_REG &= ~0x3; \
1097 +    PWRMGT_SYSTEM_CLOCK_CONTROL_REG |= 0x3; \
1098 +}
1099 +
1100 +
1101 +#define HAL_PWRMGT_CONFIG_PLLCLK_TO_CPUCLK_RATIO(ratio)        \
1102 +{ \
1103 +    PWRMGT_SYSTEM_CLOCK_CONTROL_REG &= ~(0x3 << 2); \
1104 +    PWRMGT_SYSTEM_CLOCK_CONTROL_REG |= (((ratio        - 1) & 0x3) << 2); \
1105 +}
1106 +
1107 +
1108 +#define HAL_PWRMGT_CONFIG_CPUCLK_TO_HCLK_RATIO(ratio) \
1109 +{ \
1110 +    PWRMGT_SYSTEM_CLOCK_CONTROL_REG &= ~(0x3 << 4); \
1111 +    PWRMGT_SYSTEM_CLOCK_CONTROL_REG |= (((ratio        - 1) & 0x3) << 4); \
1112 +}
1113 +
1114 +
1115 +#define HAL_PWRMGT_HCLK_SOURCE_FCLK() \
1116 +{ \
1117 +    PWRMGT_SYSTEM_CLOCK_CONTROL_REG &= ~(0x1 << 6); \
1118 +}
1119 +
1120 +
1121 +#define HAL_PWRMGT_HCLK_SOURCE_125MHZ()        \
1122 +{ \
1123 +    PWRMGT_SYSTEM_CLOCK_CONTROL_REG |= (0x1 << 6); \
1124 +}
1125 +
1126 +
1127 +#define HAL_PWRMGT_GIGA_NIC_CLOCK_SOURCE_HCLK()        \
1128 +{ \
1129 +    PWRMGT_SYSTEM_CLOCK_CONTROL_REG &= ~(0x1 << 7); \
1130 +}
1131 +
1132 +
1133 +#define HAL_PWRMGT_GIGA_NIC_CLOCK_SOURCE_62_5MHZ() \
1134 +{ \
1135 +    PWRMGT_SYSTEM_CLOCK_CONTROL_REG |= (0x1 << 7); \
1136 +}
1137 +
1138 +
1139 +#define HAL_PWRMGT_CONFIG_HCLK_TO_PCLK_RATIO(ratio) \
1140 +{ \
1141 +    PWRMGT_SYSTEM_CLOCK_CONTROL_REG &= ~(0x3 << 8); \
1142 +    PWRMGT_SYSTEM_CLOCK_CONTROL_REG |= (((ratio        - 1) & 0x3) << 8); \
1143 +}
1144 +
1145 +
1146 +#define HAL_PWRMGT_I2S_CLOCK_SOURCE_8192000HZ()        \
1147 +{ \
1148 +    PWRMGT_SYSTEM_CLOCK_CONTROL_REG &= ~(0x3 << 12); \
1149 +    PWRMGT_SYSTEM_CLOCK_CONTROL_REG |= (0x0 << 12); \
1150 +}
1151 +
1152 +
1153 +#define HAL_PWRMGT_I2S_CLOCK_SOURCE_11289600HZ() \
1154 +{ \
1155 +    PWRMGT_SYSTEM_CLOCK_CONTROL_REG &= ~(0x3 << 12); \
1156 +    PWRMGT_SYSTEM_CLOCK_CONTROL_REG |= (0x1 << 12); \
1157 +}
1158 +
1159 +
1160 +#define HAL_PWRMGT_I2S_CLOCK_SOURCE_12288000HZ() \
1161 +{ \
1162 +    PWRMGT_SYSTEM_CLOCK_CONTROL_REG &= ~(0x3 << 12); \
1163 +    PWRMGT_SYSTEM_CLOCK_CONTROL_REG |= (0x2 << 12); \
1164 +}
1165 +
1166 +
1167 +#define HAL_PWRMGT_CONFIGURE_MDC_CLOCK_DIVIDER(divided_value) \
1168 +{ \
1169 +    PWRMGT_SYSTEM_CLOCK_CONTROL_REG &= ~(0x3 << 14); \
1170 +    PWRMGT_SYSTEM_CLOCK_CONTROL_REG |= ((divided_value & 0x3) << 14); \
1171 +}
1172 +
1173 +
1174 +#define HAL_PWRMGT_CONFIGURE_CLOCK_OUT_PIN(pin_source_select, divided_value) \
1175 +{ \
1176 +    PWRMGT_SYSTEM_CLOCK_CONTROL_REG &= ~(0x3F << 16); \
1177 +    PWRMGT_SYSTEM_CLOCK_CONTROL_REG |= ((pin_source_select & 0xF) << 16); \
1178 +    PWRMGT_SYSTEM_CLOCK_CONTROL_REG |= ((divided_value & 0x3) << 20); \
1179 +}
1180 +
1181 +
1182 +/*
1183 + * Macro defines for PLL Power Down Control
1184 + */
1185 +#define HAL_PWRMGT_POWER_DOWN_SYSTEM_XTAL_PAD()        \
1186 +    PWRMGT_PLL_POWER_DOWN_CONTROL_REG |= (0x1 << 7)
1187 +
1188 +#define HAL_PWRMGT_POWER_ON_SYSTEM_XTAL_PAD() \
1189 +    PWRMGT_PLL_POWER_DOWN_CONTROL_REG &= ~(0x1 << 7)
1190 +
1191 +
1192 +#define HAL_PWRMGT_POWER_DOWN_PLL_X5() \
1193 +    PWRMGT_PLL_POWER_DOWN_CONTROL_REG |= (0x1 << 0)
1194 +
1195 +#define HAL_PWRMGT_POWER_ON_PLL_X5() \
1196 +    PWRMGT_PLL_POWER_DOWN_CONTROL_REG &= ~(0x1 << 0)
1197 +
1198 +
1199 +#define HAL_PWRMGT_POWER_DOWN_PLL_X8() \
1200 +    PWRMGT_PLL_POWER_DOWN_CONTROL_REG |= (0x1 << 1)
1201 +
1202 +#define HAL_PWRMGT_POWER_ON_PLL_X8() \
1203 +    PWRMGT_PLL_POWER_DOWN_CONTROL_REG &= ~(0x1 << 1)
1204 +
1205 +
1206 +#define HAL_PWRMGT_POWER_DOWN_PLL_X3() \
1207 +    PWRMGT_PLL_POWER_DOWN_CONTROL_REG |= (0x1 << 2)
1208 +
1209 +#define HAL_PWRMGT_POWER_ON_PLL_X3() \
1210 +    PWRMGT_PLL_POWER_DOWN_CONTROL_REG &= ~(0x1 << 2)
1211 +
1212 +
1213 +#define HAL_PWRMGT_POWER_DOWN_USBH_PHY_PLL() \
1214 +    PWRMGT_PLL_POWER_DOWN_CONTROL_REG |= (0x1 << 3)
1215 +
1216 +#define HAL_PWRMGT_POWER_ON_USBH_PHY_PLL() \
1217 +    PWRMGT_PLL_POWER_DOWN_CONTROL_REG &= ~(0x1 << 3)
1218 +
1219 +
1220 +#define HAL_PWRMGT_POWER_DOWN_USBD_PHY_PLL() \
1221 +    PWRMGT_PLL_POWER_DOWN_CONTROL_REG |= (0x1 << 4)
1222 +
1223 +#define HAL_PWRMGT_POWER_ON_USBD_PHY_PLL() \
1224 +    PWRMGT_PLL_POWER_DOWN_CONTROL_REG &= ~(0x1 << 4)
1225 +
1226 +
1227 +#define HAL_PWRMGT_POWER_DOWN_PLL_X2250() \
1228 +    PWRMGT_PLL_POWER_DOWN_CONTROL_REG |= (0x1 << 5)
1229 +
1230 +#define HAL_PWRMGT_POWER_ON_PLL_X2250()        \
1231 +    PWRMGT_PLL_POWER_DOWN_CONTROL_REG &= ~(0x1 << 5)
1232 +
1233 +
1234 +#define HAL_PWRMGT_POWER_DOWN_PLL_X7() \
1235 +    PWRMGT_PLL_POWER_DOWN_CONTROL_REG |= (0x1 << 6)
1236 +
1237 +#define HAL_PWRMGT_POWER_ON_PLL_X7() \
1238 +    PWRMGT_PLL_POWER_DOWN_CONTROL_REG &= ~(0x1 << 6)
1239 +
1240 +
1241 +#define HAL_PWRMGT_POWER_DOWN_ALL_PLL()        \
1242 +    PWRMGT_PLL_POWER_DOWN_CONTROL_REG =        0x7F;
1243 +
1244 +#define HAL_PWRMGT_POWER_ON_ALL_PLL() \
1245 +    PWRMGT_PLL_POWER_DOWN_CONTROL_REG =        0;
1246 +
1247 +
1248 +/*
1249 + * Macro defines for Pad Drive Strength        Control
1250 + */
1251 +#define HAL_PWRMGT_SELECT_PAD_DRIVE_STRENGTH_PCMCIA_CARDBUS_MODE() \
1252 +{ \
1253 +    PWRMGT_PAD_DRIVE_STRENGTH_CONTROL_REG &= ~(0x3 << 0); \
1254 +}
1255 +
1256 +#define HAL_PWRMGT_SELECT_PAD_DRIVE_STRENGTH_PCI_MODE()        \
1257 +{ \
1258 +    PWRMGT_PAD_DRIVE_STRENGTH_CONTROL_REG &= ~(0x3 << 0); \
1259 +    PWRMGT_PAD_DRIVE_STRENGTH_CONTROL_REG |= (0x1 << 0); \
1260 +}
1261 +
1262 +#define HAL_PWRMGT_SELECT_PAD_DRIVE_STRENGTH_MII_MODE()        \
1263 +{ \
1264 +    PWRMGT_PAD_DRIVE_STRENGTH_CONTROL_REG |= (0x1 << 2); \
1265 +}
1266 +
1267 +#define HAL_PWRMGT_SELECT_PAD_DRIVE_STRENGTH_RGMII_MODE() \
1268 +{ \
1269 +    PWRMGT_PAD_DRIVE_STRENGTH_CONTROL_REG &= ~(0x1 << 2); \
1270 +}
1271 +
1272 +#define HAL_PWRMGT_ENABLE_MII_PAD_SIGNAL_NOT_BOUNDED() \
1273 +{ \
1274 +    PWRMGT_PAD_DRIVE_STRENGTH_CONTROL_REG |= (0x1 << 3); \
1275 +}
1276 +
1277 +#define HAL_PWRMGT_DISABLE_MII_PAD_SIGNAL_NOT_BOUNDED()        \
1278 +{ \
1279 +    PWRMGT_PAD_DRIVE_STRENGTH_CONTROL_REG &= ~(0x1 << 3); \
1280 +}
1281 +
1282 +
1283 +/*
1284 + * Macro defines for USB Device        Power Management
1285 + */
1286 +#define HAL_PWRMGT_REMOTE_WAKEUP_USB_HOST() \
1287 +{ \
1288 +    PWRMGT_USB_DEVICE_POWERMGT_REG |= (0x1 << 4); \
1289 +}
1290 +
1291 +#define HAL_PWRMGT_USB_DEVICE_PHY_CLOCK_SOURCE_EXTERNAL_12MHZ()        \
1292 +{ \
1293 +    PWRMGT_USB_DEVICE_POWERMGT_REG &= ~(0x1 << 5); \
1294 +}
1295 +
1296 +#define HAL_PWRMGT_USB_DEVICE_PHY_CLOCK_SOURCE_INTERNAL_12MHZ()        \
1297 +{ \
1298 +    PWRMGT_USB_DEVICE_POWERMGT_REG |= (0x1 << 5); \
1299 +}
1300 +
1301 +
1302 +/*
1303 + * Macro defines for Regulator Control
1304 + */
1305 +
1306 +#endif /* _CNS21XX_POWERMGMT_H */
1307 --- /dev/null
1308 +++ b/arch/arm/mach-cns21xx/include/mach/cns21xx.h
1309 @@ -0,0 +1,88 @@
1310 +/*
1311 + *  Copyright (c) 2008 Cavium Networks
1312 + *  Copyright (c) 2010-2012 Gabor Juhos <juhosg@openwrt.org>
1313 + *
1314 + *  This file is free software; you can redistribute it and/or modify
1315 + *  it under the terms of the GNU General Public License, Version 2, as
1316 + *  published by the Free Software Foundation.
1317 + */
1318 +
1319 +#ifndef _CNS21XX_H
1320 +#define _CNS21XX_H
1321 +
1322 +#define CNS21XX_FLASH_BANK0_BASE       0x10000000
1323 +#define CNS21XX_FLASH_BANK1_BASE       0x11000000
1324 +#define CNS21XX_FLASH_BANK2_BASE       0x12000000
1325 +#define CNS21XX_FLASH_BANK3_BASE       0x13000000
1326 +#define CNS21XX_PCMCIA_ATTR_BASE       0x14000000
1327 +#define CNS21XX_PCMCIA_MEM_BASE                0x15000000
1328 +#define CNS21XX_PCMCIA_IO_BASE         0x16000000
1329 +#define CNS21XX_IDE_DEVICE_BASE                0x18000000
1330 +#define CNS21XX_SDRAM_MEMORY_BASE      0x20000000
1331 +#define CNS21XX_GDMAC_BASE             0x60000000
1332 +#define CNS21XX_NIC_BASE               0x70000000
1333 +#define CNS21XX_SPI_BASE               0x71000000
1334 +#define CNS21XX_PCM_BASE               0x71000000
1335 +#define CNS21XX_I2C_BASE               0x71000000
1336 +#define CNS21XX_I2S_BASE               0x71000000
1337 +#define CNS21XX_DDRC_BASE              0x72000000
1338 +#define CNS21XX_SMC_BASE               0x73000000
1339 +#define CNS21XX_PCMCIA_CTRL_BASE       0x73000000
1340 +#define CNS21XX_IDE_CTRL_BASE          0x74000000
1341 +#define CNS21XX_MISC_BASE              0x76000000
1342 +#define CNS21XX_CPM_BASE               0x77000000
1343 +#define CNS21XX_UART0_BASE             0x78000000
1344 +#define CNS21XX_UART1_BASE             0x78800000
1345 +#define CNS21XX_TIMER_BASE             0x79000000
1346 +#define CNS21XX_WDT_BASE               0x7a000000
1347 +#define CNS21XX_RTC_BASE               0x7b000000
1348 +#define CNS21XX_GPIOA_BASE             0x7c000000
1349 +#define CNS21XX_GPIOB_BASE             0x7c800000
1350 +#define CNS21XX_PCI_CFGDATA_BASE       0xa0000000
1351 +#define CNS21XX_PCI_CFGADDR_BASE       0xa4000000
1352 +#define CNS21XX_PCI_IO_BASE            0xa8000000
1353 +#define CNS21XX_PCI_MEMORY_BASE                0xb0000000
1354 +#define CNS21XX_OHCI_CONFIG_BASE       0xc0000000
1355 +#define CNS21XX_OHCI_CTRL_BASE         0xc4000000
1356 +#define CNS21XX_EHCI_CONFIG_BASE       0xc8000000
1357 +#define CNS21XX_EHCI_CTRL_BASE         0xcc000000
1358 +#define CNS21XX_USB_DEVICE_BASE                0xd0000000
1359 +#define CNS21XX_INTC_BASE              0xfffff000
1360 +
1361 +#define CNS21XX_FLASH_BANK0_BASE_VIRT  0xe0000000
1362 +#define CNS21XX_FLASH_BANK1_BASE_VIRT  0xe2000000
1363 +#define CNS21XX_FLASH_BANK2_BASE_VIRT  0xe4000000
1364 +#define CNS21XX_FLASH_BANK3_BASE_VIRT  0xe8000000
1365 +#define CNS21XX_IDE_DEVICE_BASE_VIRT   0xfef00000
1366 +#define CNS21XX_GDMAC_BASE_VIRT                0xfef01000
1367 +#define CNS21XX_NIC_BASE_VIRT          0xfef02000
1368 +#define CNS21XX_SPI_BASE_VIRT          0xfef03000
1369 +#define CNS21XX_PCM_BASE_VIRT          0xfef04000
1370 +#define CNS21XX_I2C_BASE_VIRT          0xfef05000
1371 +#define CNS21XX_I2S_BASE_VIRT          0xfef06000
1372 +#define CNS21XX_DDRC_BASE_VIRT         0xfef07000
1373 +#define CNS21XX_SMC_BASE_VIRT          0xfef08000
1374 +#define CNS21XX_PCMCIA_CTRL_BASE_VIRT  0xfef09000
1375 +#define CNS21XX_IDE_CTRL_BASE_VIRT     0xfef0A000
1376 +#define CNS21XX_MISC_BASE_VIRT         0xfef0B000
1377 +#define CNS21XX_CPM_BASE_VIRT          0xfef0C000
1378 +#define CNS21XX_UART0_BASE_VIRT                0xfef0D000
1379 +#define CNS21XX_UART1_BASE_VIRT                0xfef0E000
1380 +#define CNS21XX_TIMER_BASE_VIRT                0xfef0F000
1381 +#define CNS21XX_WDT_BASE_VIRT          0xfef10000
1382 +#define CNS21XX_RTC_BASE_VIRT          0xfef11000
1383 +#define CNS21XX_GPIOA_BASE_VIRT                0xfef12000
1384 +#define CNS21XX_GPIOB_BASE_VIRT                0xfef13000
1385 +#define CNS21XX_PCI_CFGDATA_BASE_VIRT  0xfef14000
1386 +#define CNS21XX_PCI_CFGADDR_BASE_VIRT  0xfef15000
1387 +#define CNS21XX_OHCI_CONFIG_BASE_VIRT  0xfef16000
1388 +#define CNS21XX_OHCI_CTRL_BASE_VIRT    0xfef17000
1389 +#define CNS21XX_EHCI_CONFIG_BASE_VIRT  0xfef18000
1390 +#define CNS21XX_EHCI_CTRL_BASE_VIRT    0xfef19000
1391 +#define CNS21XX_USB_DEVICE_BASE_VIRT   0xfef1a000
1392 +#define CNS21XX_INTC_BASE_VIRT         0xfef1b000
1393 +
1394 +#define CNS21XX_PHYS_IO                CNS21XX_UART0_BASE
1395 +#define CNS21XX_IO_PAGE_OFFSET ((CNS21XX_UART0_BASE_VIRT) >> 18) & 0xfffc
1396 +
1397 +#endif /* _CNS21XX_H */
1398 --- /dev/null
1399 +++ b/arch/arm/mach-cns21xx/core.c
1400 @@ -0,0 +1,85 @@
1401 +/*
1402 + *  Copyright (c) 2008 Cavium Networks
1403 + *  Copyright (c) 2010-2012 Gabor Juhos <juhosg@openwrt.org>
1404 + *
1405 + *  This file is free software; you can redistribute it and/or modify
1406 + *  it under the terms of the GNU General Public License, Version 2, as
1407 + *  published by the Free Software Foundation.
1408 + */
1409 +
1410 +#include <linux/kernel.h>
1411 +
1412 +#include <mach/hardware.h>
1413 +#include <mach/cns21xx.h>
1414 +#include <mach/cns21xx_powermgmt.h>
1415 +
1416 +static unsigned long cns21xx_pll_freq;
1417 +static unsigned long cns21xx_cpu_freq;
1418 +static unsigned long cns21xx_ahb_freq;
1419 +static unsigned long cns21xx_apb_freq;
1420 +
1421 +static void cns21xx_init_freq(void)
1422 +{
1423 +       static int freq_init_done;
1424 +       unsigned int t;
1425 +
1426 +       if (freq_init_done)
1427 +               return;
1428 +
1429 +       t = PWRMGT_SYSTEM_CLOCK_CONTROL_REG;
1430 +       switch (t & 0x3) {
1431 +       case 0x00:
1432 +               cns21xx_pll_freq = 175000000;
1433 +               break;
1434 +
1435 +       case 0x01:
1436 +               cns21xx_pll_freq = 200000000;
1437 +               break;
1438 +
1439 +       case 0x02:
1440 +               cns21xx_pll_freq = 225000000;
1441 +               break;
1442 +
1443 +       case 0x03:
1444 +               cns21xx_pll_freq = 250000000;
1445 +               break;
1446 +       }
1447 +
1448 +       cns21xx_cpu_freq = cns21xx_pll_freq / (((t >> 2) & 0x3) + 1);
1449 +       cns21xx_ahb_freq = cns21xx_cpu_freq / (((t >> 4) & 0x3) + 1);
1450 +       cns21xx_apb_freq = cns21xx_ahb_freq / (((t >> 8) & 0x3) + 1);
1451 +
1452 +       freq_init_done = 1;
1453 +}
1454 +
1455 +unsigned long cns21xx_get_pll_freq(void)
1456 +{
1457 +       cns21xx_init_freq();
1458 +       return cns21xx_pll_freq;
1459 +}
1460 +
1461 +unsigned long cns21xx_get_cpu_freq(void)
1462 +{
1463 +       cns21xx_init_freq();
1464 +       return cns21xx_cpu_freq;
1465 +}
1466 +
1467 +unsigned long cns21xx_get_ahb_freq(void)
1468 +{
1469 +       cns21xx_init_freq();
1470 +       return cns21xx_ahb_freq;
1471 +}
1472 +
1473 +unsigned long cns21xx_get_apb_freq(void)
1474 +{
1475 +       cns21xx_init_freq();
1476 +       return cns21xx_apb_freq;
1477 +}
1478 +
1479 +void cns21xx_restart(char mode, const char *cmd)
1480 +{
1481 +       PWRMGT_SOFTWARE_RESET_CONTROL_REG |=
1482 +               (1UL << PWRMGT_GLOBAL_SOFTWARE_RESET_MASK_BIT_INDEX);
1483 +       PWRMGT_SOFTWARE_RESET_CONTROL_REG &=
1484 +               ~(1UL << PWRMGT_GLOBAL_SOFTWARE_RESET_MASK_BIT_INDEX);
1485 +}
1486 --- a/arch/arm/mm/Kconfig
1487 +++ b/arch/arm/mm/Kconfig
1488 @@ -903,6 +903,7 @@ config ARM_L1_CACHE_SHIFT_6
1489  config ARM_L1_CACHE_SHIFT
1490         int
1491         default 6 if ARM_L1_CACHE_SHIFT_6
1492 +       default 4 if ARM_L1_CACHE_SHIFT_4
1493         default 5
1494
1495  config ARM_DMA_MEM_BUFFERABLE
1496 --- a/arch/arm/mm/cache-fa.S
1497 +++ b/arch/arm/mm/cache-fa.S
1498 @@ -28,7 +28,7 @@
1499  /*
1500   * The total size of the data cache.
1501   */
1502 -#ifdef CONFIG_ARCH_GEMINI
1503 +#if (defined(CONFIG_ARCH_GEMINI) || defined(CONFIG_ARCH_CNS21XX))
1504  #define CACHE_DSIZE    8192
1505  #else
1506  #define CACHE_DSIZE    16384
1507 --- /dev/null
1508 +++ b/arch/arm/mach-cns21xx/include/mach/cns21xx_misc.h
1509 @@ -0,0 +1,507 @@
1510 +/*******************************************************************************
1511 + *
1512 + *  Copyright (c) 2008 Cavium Networks
1513 + *
1514 + *  This file is free software; you can redistribute it and/or modify
1515 + *  it under the terms of the GNU General Public License, Version 2, as
1516 + *  published by the Free Software Foundation.
1517 + *
1518 + *  This file is distributed in the hope that it will be useful,
1519 + *  but AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty of
1520 + *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
1521 + *  NONINFRINGEMENT.  See the GNU General Public License for more details.
1522 + *
1523 + *  You should have received a copy of the GNU General Public License
1524 + *  along with this file; if not, write to the Free Software
1525 + *  Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA or
1526 + *  visit http://www.gnu.org/licenses/.
1527 + *
1528 + *  This file may also be available under a different license from Cavium.
1529 + *  Contact Cavium Networks for more information
1530 + *
1531 + ******************************************************************************/
1532 +
1533 +#ifndef        _STAR_MISC_H_
1534 +#define _STAR_MISC_H_
1535 +
1536 +#include <mach/cns21xx.h>
1537 +
1538 +#define MISC_MEM_MAP_VALUE(reg_offset) \
1539 +       (*((u32 volatile *)(CNS21XX_MISC_BASE_VIRT + reg_offset)))
1540 +
1541 +/*
1542 + * define access macros
1543 + */
1544 +#define MISC_MEMORY_REMAP_REG                  MISC_MEM_MAP_VALUE(0x00)
1545 +#define MISC_CHIP_CONFIG_REG                   MISC_MEM_MAP_VALUE(0x04)
1546 +#define MISC_DEBUG_PROBE_DATA_REG              MISC_MEM_MAP_VALUE(0x08)
1547 +#define MISC_DEBUG_PROBE_SELECTION_REG         MISC_MEM_MAP_VALUE(0x0C)
1548 +#define MISC_PCI_CONTROL_BROKEN_MASK_REG       MISC_MEM_MAP_VALUE(0x10)
1549 +#define MISC_PCI_BROKEN_STATUS_REG             MISC_MEM_MAP_VALUE(0x14)
1550 +#define MISC_PCI_DEVICE_VENDOR_ID_REG          MISC_MEM_MAP_VALUE(0x18)
1551 +#define MISC_USB_HOST_PHY_CONTROL_TEST_REG     MISC_MEM_MAP_VALUE(0x1C)
1552 +#define MISC_GPIOA_PIN_ENABLE_REG              MISC_MEM_MAP_VALUE(0x20)
1553 +#define MISC_GPIOB_PIN_ENABLE_REG              MISC_MEM_MAP_VALUE(0x24)
1554 +#define MISC_GPIOA_RESISTOR_CONFIG_REG         MISC_MEM_MAP_VALUE(0x28)
1555 +#define MISC_GPIOA_DRIVE_STRENGTH_CONFIG_REG   MISC_MEM_MAP_VALUE(0x2C)
1556 +#define MISC_FAST_ETHERNET_PHY_CONFIG_REG      MISC_MEM_MAP_VALUE(0x30)
1557 +#define MISC_SOFTWARE_TEST_1_REG               MISC_MEM_MAP_VALUE(0x38)
1558 +#define MISC_SOFTWARE_TEST_2_REG               MISC_MEM_MAP_VALUE(0x3C)
1559 +
1560 +#define MISC_E_FUSE_0_REG                      MISC_MEM_MAP_VALUE(0x60)
1561 +#define MISC_E_FUSE_1_REG                      MISC_MEM_MAP_VALUE(0x64)
1562 +
1563 +
1564 +/*
1565 + * define constants macros
1566 + */
1567 +#define MISC_PARALLEL_FLASH_BOOT               0
1568 +#define MISC_SPI_SERIAL_FLASH_BOOT             1
1569 +
1570 +#define MISC_LITTLE_ENDIAN                     0
1571 +#define MISC_BIG_ENDIAN                                1
1572 +
1573 +#define MISC_FARADAY_ICE                       0
1574 +#define MISC_ARM_ICE                           1
1575 +
1576 +#define MISC_EXT_INT29_PINS                    ((0x1 << 0))
1577 +#define MISC_EXT_INT30_PINS                    ((0x1 << 1))
1578 +#define MISC_EXT_INT31_PINS                    ((0x1 << 2))
1579 +#define MISC_I2C_PINS                          ((0x1 << 13) | (0x1 << 14))
1580 +#define MISC_I2S_PINS                          ((0x1 << 15) | (0x1 << 16) | (0x1 << 17))
1581 +#define MISC_I2SSD_PINS                                (1 << 15)
1582 +#define MISC_I2SWS_PINS                                (1 << 16)
1583 +#define MISC_I2SCLK_PINS                       (1 << 17)
1584 +#define MISC_PCM_PINS                          ((0x1 << 18) | (0x1 << 19) | (0x1 << 20) | (0x1 << 21))
1585 +#define MISC_PCMDR_PINS                                (1 << 18)
1586 +#define MISC_PCMDT_PINS                                (1 << 19)
1587 +#define MISC_PCMFS_PINS                                (1 << 20)
1588 +#define MISC_PCMCLK_PINS                       (1 << 21)
1589 +#define MISC_LED0_PINS                         ((0x1 << 22))
1590 +#define MISC_LED1_PINS                         ((0x1 << 23))
1591 +#define MISC_LED2_PINS                         ((0x1 << 24))
1592 +#define MISC_LED012_PINS                       ((0x1 << 22) | (0x1 << 23) | (0x1 << 24))
1593 +#define MISC_WDTIMER_RESET_PINS                        ((0x1 << 25))
1594 +#define MISC_SPIDR_PINS                                (0x1 << 26)
1595 +#define MISC_SPICLK_PINS                       (0x1 << 27)
1596 +#define MISC_SPICSN0_PINS                      (0x1 << 28)
1597 +#define MISC_SPICSN1_PINS                      (0x1 << 29)
1598 +#define MISC_SPICSN2_PINS                      (0x1 << 30)
1599 +#define MISC_SPICSN3_PINS                      (0x1 << 31)
1600 +#define MISC_SPI_PINS                          ((0x1 << 26) | (0x1 << 27) | (0x1 << 28) | (0x1 << 29) | (0x1 << 30) | (0x1 << 31))
1601 +#define MISC_MDC_MDIO_PINS                     ((0x1 << 0) | (0x1 << 1))
1602 +#define MISC_NIC_COL_PINS                      ((0x1 << 2))
1603 +#define MISC_IDE_PINS                          ((0xFF << 3))
1604 +#define MISC_SRAM_BANK1_PINS                   ((0x1 << 11) | (0x1 << 14))
1605 +#define MISC_SRAM_BANK2_PINS                   ((0x1 << 12) | (0x1 << 15))
1606 +#define MISC_SRAM_BANK3_PINS                   ((0x1 << 13) | (0x1 << 16))
1607 +#define MISC_PCMCIA_PINS                       ((0x1 << 17) | (0x1 << 18) | (0x1 << 19) | (0x1 << 20))
1608 +#define MISC_UART1_PINS                                ((0x1 << 21) | (0x1 << 22))
1609 +#define MISC_PCI_PINS                          (((u32)0x1FF << 23))
1610 +
1611 +#define MISC_UART0_ACT0_Pin                    (0x1 << 2)
1612 +#define MISC_UART1_ACT1_Pin                    (0x1 << 3)
1613 +
1614 +#define MISC_GPIOA_PIN_0                       0
1615 +#define MISC_GPIOA_PIN_1                       1
1616 +#define MISC_GPIOA_PIN_2                       2
1617 +#define MISC_GPIOA_PIN_3                       3
1618 +#define MISC_GPIOA_PIN_4                       4
1619 +#define MISC_GPIOA_PIN_5                       5
1620 +#define MISC_GPIOA_PIN_6                       6
1621 +#define MISC_GPIOA_PIN_7                       7
1622 +#define MISC_GPIOA_PIN_8                       8
1623 +#define MISC_GPIOA_PIN_9                       9
1624 +#define MISC_GPIOA_PIN_10                      10
1625 +
1626 +#define MISC_GPIOA_75K_RESISTOR_PULL_DOWN      1
1627 +#define MISC_GPIOA_75K_RESISTOR_PULL_UP                2
1628 +#define MISC_GPIOA_75K_RESISTOR_PULL_KEEPER    3
1629 +
1630 +#define MISC_GPIOA_DRIVE_STRENGTH_4MA          0
1631 +#define MISC_GPIOA_DRIVE_STRENGTH_8MA          1
1632 +
1633 +
1634 +/*
1635 + * macro declarations
1636 + */
1637 +#define HAL_MISC_ENABLE_SPI_SERIAL_FLASH_BANK_ACCESS() \
1638 +{ \
1639 +    (MISC_CHIP_CONFIG_REG) |= (0x1 << 4); \
1640 +}
1641 +
1642 +#define HAL_MISC_DISABLE_SPI_SERIAL_FLASH_BANK_ACCESS()        \
1643 +{ \
1644 +    (MISC_CHIP_CONFIG_REG) &= ~(0x1 << 4); \
1645 +}
1646 +
1647 +
1648 +/*
1649 + * Macro defines for GPIOA and GPIOB Pin Enable        Register
1650 + */
1651 +#define HAL_MISC_ENABLE_EXT_INT29_PINS() \
1652 +{ \
1653 +    (MISC_GPIOA_PIN_ENABLE_REG)        |= (MISC_EXT_INT29_PINS); \
1654 +}
1655 +
1656 +#define HAL_MISC_DISABLE_EXT_INT29_PINS() \
1657 +{ \
1658 +    (MISC_GPIOA_PIN_ENABLE_REG)        &= ~(MISC_EXT_INT29_PINS); \
1659 +}
1660 +
1661 +#define HAL_MISC_ENABLE_EXT_INT30_PINS() \
1662 +{ \
1663 +    (MISC_GPIOA_PIN_ENABLE_REG)        |= (MISC_EXT_INT30_PINS); \
1664 +}
1665 +
1666 +#define HAL_MISC_DISABLE_EXT_INT30_PINS() \
1667 +{ \
1668 +    (MISC_GPIOA_PIN_ENABLE_REG)        &= ~(MISC_EXT_INT30_PINS); \
1669 +}
1670 +
1671 +#define HAL_MISC_ENABLE_I2C_PINS() \
1672 +{ \
1673 +    (MISC_GPIOA_PIN_ENABLE_REG)        |= (MISC_I2C_PINS); \
1674 +}
1675 +
1676 +#define HAL_MISC_DISABLE_I2C_PINS() \
1677 +{ \
1678 +    (MISC_GPIOA_PIN_ENABLE_REG)        &= ~(MISC_I2C_PINS); \
1679 +}
1680 +
1681 +#define HAL_MISC_ENABLE_I2S_PINS() \
1682 +{ \
1683 +    (MISC_GPIOA_PIN_ENABLE_REG)        |= (MISC_I2S_PINS); \
1684 +}
1685 +
1686 +#define HAL_MISC_DISABLE_I2S_PINS() \
1687 +{ \
1688 +    (MISC_GPIOA_PIN_ENABLE_REG)        &= ~(MISC_I2S_PINS); \
1689 +}
1690 +
1691 +#define HAL_MISC_DISABLE_I2SSD_PINS() \
1692 +{ \
1693 +    (MISC_GPIOA_PIN_ENABLE_REG)        &= ~(MISC_I2SSD_PINS); \
1694 +}
1695 +
1696 +#define HAL_MISC_DISABLE_I2SWS_PINS() \
1697 +{ \
1698 +    (MISC_GPIOA_PIN_ENABLE_REG)        &= ~(MISC_I2SWS_PINS); \
1699 +}
1700 +
1701 +#define HAL_MISC_DISABLE_I2SCLK_PINS() \
1702 +{ \
1703 +    (MISC_GPIOA_PIN_ENABLE_REG)        &= ~(MISC_I2SCLK_PINS); \
1704 +}
1705 +
1706 +#define HAL_MISC_ENABLE_PCM_PINS() \
1707 +{ \
1708 +    (MISC_GPIOA_PIN_ENABLE_REG)        |= (MISC_PCM_PINS); \
1709 +}
1710 +
1711 +#define HAL_MISC_DISABLE_PCM_PINS() \
1712 +{ \
1713 +    (MISC_GPIOA_PIN_ENABLE_REG)        &= ~(MISC_PCM_PINS); \
1714 +}
1715 +
1716 +#define HAL_MISC_DISABLE_PCMDR_PINS() \
1717 +{ \
1718 +    (MISC_GPIOA_PIN_ENABLE_REG)        &= ~(MISC_PCMDR_PINS); \
1719 +}
1720 +
1721 +#define HAL_MISC_DISABLE_PCMDT_PINS() \
1722 +{ \
1723 +    (MISC_GPIOA_PIN_ENABLE_REG)        &= ~(MISC_PCMDT_PINS); \
1724 +}
1725 +
1726 +#define HAL_MISC_DISABLE_PCMFS_PINS() \
1727 +{ \
1728 +    (MISC_GPIOA_PIN_ENABLE_REG)        &= ~(MISC_PCMFS_PINS); \
1729 +}
1730 +
1731 +#define HAL_MISC_DISABLE_PCMCLK_PINS() \
1732 +{ \
1733 +    (MISC_GPIOA_PIN_ENABLE_REG)        &= ~(MISC_PCMCLK_PINS); \
1734 +}
1735 +
1736 +#define HAL_MISC_ENABLE_LED0_PINS() \
1737 +{ \
1738 +    (MISC_GPIOA_PIN_ENABLE_REG)        |= (MISC_LED0_PINS); \
1739 +}
1740 +
1741 +#define HAL_MISC_DISABLE_LED0_PINS() \
1742 +{ \
1743 +    (MISC_GPIOA_PIN_ENABLE_REG)        &= ~(MISC_LED0_PINS); \
1744 +}
1745 +
1746 +#define HAL_MISC_ENABLE_LED1_PINS() \
1747 +{ \
1748 +    (MISC_GPIOA_PIN_ENABLE_REG)        |= (MISC_LED1_PINS); \
1749 +}
1750 +
1751 +#define HAL_MISC_DISABLE_LED1_PINS() \
1752 +{ \
1753 +    (MISC_GPIOA_PIN_ENABLE_REG)        &= ~(MISC_LED1_PINS); \
1754 +}
1755 +
1756 +#define HAL_MISC_ENABLE_LED2_PINS() \
1757 +{ \
1758 +    (MISC_GPIOA_PIN_ENABLE_REG)        |= (MISC_LED2_PINS); \
1759 +}
1760 +
1761 +#define HAL_MISC_DISABLE_LED2_PINS() \
1762 +{ \
1763 +    (MISC_GPIOA_PIN_ENABLE_REG)        &= ~(MISC_LED2_PINS); \
1764 +}
1765 +
1766 +#define HAL_MISC_ENABLE_LED012_PINS() \
1767 +{ \
1768 +    (MISC_GPIOA_PIN_ENABLE_REG)        |= (MISC_LED012_PINS); \
1769 +}
1770 +
1771 +#define HAL_MISC_DISABLE_LED012_PINS() \
1772 +{ \
1773 +    (MISC_GPIOA_PIN_ENABLE_REG)        &= ~(MISC_LED012_PINS); \
1774 +}
1775 +
1776 +#define HAL_MISC_ENABLE_WDTIMER_RESET_PINS() \
1777 +{ \
1778 +    (MISC_GPIOA_PIN_ENABLE_REG)        |= (MISC_WDTIMER_RESET_PINS); \
1779 +}
1780 +
1781 +#define HAL_MISC_DISABLE_WDTIMER_RESET_PINS() \
1782 +{ \
1783 +    (MISC_GPIOA_PIN_ENABLE_REG)        &= ~(MISC_WDTIMER_RESET_PINS); \
1784 +}
1785 +
1786 +#define HAL_MISC_ENABLE_SPI_PINS() \
1787 +{ \
1788 +    (MISC_GPIOA_PIN_ENABLE_REG)        |= (MISC_SPI_PINS); \
1789 +}
1790 +
1791 +#define HAL_MISC_ENABLE_SPIDR_PINS() \
1792 +{ \
1793 +    (MISC_GPIOA_PIN_ENABLE_REG)        |= (MISC_SPIDR_PINS); \
1794 +}
1795 +
1796 +#define HAL_MISC_ENABLE_SPICLK_PINS() \
1797 +{ \
1798 +    (MISC_GPIOA_PIN_ENABLE_REG)        |= (MISC_SPICLK_PINS); \
1799 +}
1800 +
1801 +#define HAL_MISC_ENABLE_SPICSN0_PINS() \
1802 +{ \
1803 +    (MISC_GPIOA_PIN_ENABLE_REG)        |= (MISC_SPICSN0_PINS); \
1804 +}
1805 +
1806 +#define HAL_MISC_ENABLE_SPICSN0_PINS() \
1807 +{ \
1808 +    (MISC_GPIOA_PIN_ENABLE_REG)        |= (MISC_SPICSN0_PINS); \
1809 +}
1810 +
1811 +#define HAL_MISC_ENABLE_SPICSN1_PINS() \
1812 +{ \
1813 +    (MISC_GPIOA_PIN_ENABLE_REG)        |= (MISC_SPICSN1_PINS); \
1814 +}
1815 +
1816 +#define HAL_MISC_ENABLE_SPICSN2_PINS() \
1817 +{ \
1818 +    (MISC_GPIOA_PIN_ENABLE_REG)        |= (MISC_SPICSN2_PINS); \
1819 +}
1820 +
1821 +#define HAL_MISC_ENABLE_SPICSN3_PINS() \
1822 +{ \
1823 +    (MISC_GPIOA_PIN_ENABLE_REG)        |= (MISC_SPICSN3_PINS); \
1824 +}
1825 +
1826 +#define HAL_MISC_DISABLE_SPI_PINS() \
1827 +{ \
1828 +    (MISC_GPIOA_PIN_ENABLE_REG)        &= ~(MISC_SPI_PINS); \
1829 +}
1830 +
1831 +#define HAL_MISC_DISABLE_SPIDR_PINS() \
1832 +{ \
1833 +    (MISC_GPIOA_PIN_ENABLE_REG)        &= ~(MISC_SPIDR_PINS); \
1834 +}
1835 +
1836 +#define HAL_MISC_DISABLE_SPICLK_PINS() \
1837 +{ \
1838 +    (MISC_GPIOA_PIN_ENABLE_REG)        &= ~(MISC_SPICLK_PINS); \
1839 +}
1840 +
1841 +#define HAL_MISC_DISABLE_SPICSN0_PINS() \
1842 +{ \
1843 +    (MISC_GPIOA_PIN_ENABLE_REG)        &= ~(MISC_SPICSN0_PINS); \
1844 +}
1845 +
1846 +#define HAL_MISC_DISABLE_SPICSN1_PINS() \
1847 +{ \
1848 +    (MISC_GPIOA_PIN_ENABLE_REG)        &= ~(MISC_SPICSN1_PINS); \
1849 +}
1850 +
1851 +#define HAL_MISC_DISABLE_SPICSN2_PINS() \
1852 +{ \
1853 +    (MISC_GPIOA_PIN_ENABLE_REG)        &= ~(MISC_SPICSN2_PINS); \
1854 +}
1855 +
1856 +#define HAL_MISC_DISABLE_SPICSN3_PINS() \
1857 +{ \
1858 +    (MISC_GPIOA_PIN_ENABLE_REG)        &= ~(MISC_SPICSN3_PINS); \
1859 +}
1860 +
1861 +#define HAL_MISC_ENABLE_UART0_ACT0_PIN() \
1862 +{ \
1863 +    (MISC_GPIOA_PIN_ENABLE_REG)        |= (MISC_UART0_ACT0_Pin); \
1864 +}
1865 +
1866 +#define HAL_MISC_DISABLE_UART0_ACT0_PIN() \
1867 +{ \
1868 +    (MISC_GPIOA_PIN_ENABLE_REG)        &= ~(MISC_UART0_ACT0_Pin); \
1869 +}
1870 +
1871 +#define HAL_MISC_ENABLE_UART1_ACT1_PIN() \
1872 +{ \
1873 +    (MISC_GPIOA_PIN_ENABLE_REG)        |= (MISC_UART1_ACT1_Pin); \
1874 +}
1875 +
1876 +#define HAL_MISC_DISABLE_UART1_ACT1_PIN() \
1877 +{ \
1878 +    (MISC_GPIOA_PIN_ENABLE_REG)        &= ~(MISC_UART1_ACT1_Pin); \
1879 +}
1880 +
1881 +#define HAL_MISC_ENABLE_MDC_MDIO_PINS()        \
1882 +{ \
1883 +    (MISC_GPIOB_PIN_ENABLE_REG)        |= (MISC_MDC_MDIO_PINS); \
1884 +}
1885 +
1886 +#define HAL_MISC_DISABLE_MDC_MDIO_PINS() \
1887 +{ \
1888 +    (MISC_GPIOB_PIN_ENABLE_REG)        &= ~(MISC_MDC_MDIO_PINS); \
1889 +}
1890 +
1891 +#define HAL_MISC_ENABLE_NIC_COL_PINS() \
1892 +{ \
1893 +    (MISC_GPIOB_PIN_ENABLE_REG)        |= (MISC_NIC_COL_PINS); \
1894 +}
1895 +
1896 +#define HAL_MISC_DISABLE_NIC_COL_PINS()        \
1897 +{ \
1898 +    (MISC_GPIOB_PIN_ENABLE_REG)        &= ~(MISC_NIC_COL_PINS); \
1899 +}
1900 +
1901 +#define HAL_MISC_ENABLE_IDE_PINS() \
1902 +{ \
1903 +    (MISC_GPIOB_PIN_ENABLE_REG)        |= (MISC_IDE_PINS); \
1904 +}
1905 +
1906 +#define HAL_MISC_DISABLE_IDE_PINS() \
1907 +{ \
1908 +    (MISC_GPIOB_PIN_ENABLE_REG)        &= ~(MISC_IDE_PINS); \
1909 +}
1910 +
1911 +#define HAL_MISC_ENABLE_SRAM_BANK1_PINS() \
1912 +{ \
1913 +    (MISC_GPIOB_PIN_ENABLE_REG)        |= (MISC_SRAM_BANK1_PINS); \
1914 +}
1915 +
1916 +#define HAL_MISC_DISABLE_SRAM_BANK1_PINS() \
1917 +{ \
1918 +    (MISC_GPIOB_PIN_ENABLE_REG)        &= ~(MISC_SRAM_BANK1_PINS); \
1919 +}
1920 +
1921 +#define HAL_MISC_ENABLE_SRAM_BANK2_PINS() \
1922 +{ \
1923 +    (MISC_GPIOB_PIN_ENABLE_REG)        |= (MISC_SRAM_BANK2_PINS); \
1924 +}
1925 +
1926 +#define HAL_MISC_DISABLE_SRAM_BANK2_PINS() \
1927 +{ \
1928 +    (MISC_GPIOB_PIN_ENABLE_REG)        &= ~(MISC_SRAM_BANK2_PINS); \
1929 +}
1930 +
1931 +#define HAL_MISC_ENABLE_SRAM_BANK3_PINS() \
1932 +{ \
1933 +    (MISC_GPIOB_PIN_ENABLE_REG)        |= (MISC_SRAM_BANK3_PINS); \
1934 +}
1935 +
1936 +#define HAL_MISC_DISABLE_SRAM_BANK3_PINS() \
1937 +{ \
1938 +    (MISC_GPIOB_PIN_ENABLE_REG)        &= ~(MISC_SRAM_BANK3_PINS); \
1939 +}
1940 +
1941 +#define HAL_MISC_ENABLE_PCMCIA_PINS() \
1942 +{ \
1943 +    (MISC_GPIOB_PIN_ENABLE_REG)        |= (MISC_PCMCIA_PINS); \
1944 +}
1945 +
1946 +#define HAL_MISC_DISABLE_PCMCIA_PINS() \
1947 +{ \
1948 +    (MISC_GPIOB_PIN_ENABLE_REG)        &= ~(MISC_PCMCIA_PINS); \
1949 +}
1950 +
1951 +#define HAL_MISC_ENABLE_UART1_PINS() \
1952 +{ \
1953 +    (MISC_GPIOB_PIN_ENABLE_REG)        |= (MISC_UART1_PINS); \
1954 +}
1955 +
1956 +#define HAL_MISC_DISABLE_UART1_PINS() \
1957 +{ \
1958 +    (MISC_GPIOB_PIN_ENABLE_REG)        &= ~(MISC_UART1_PINS); \
1959 +}
1960 +
1961 +#define HAL_MISC_ENABLE_PCI_PINS() \
1962 +{ \
1963 +    (MISC_GPIOB_PIN_ENABLE_REG)        |= (MISC_PCI_PINS); \
1964 +}
1965 +
1966 +#define HAL_MISC_DISABLE_PCI_PINS() \
1967 +{ \
1968 +    (MISC_GPIOB_PIN_ENABLE_REG)        &= ~(MISC_PCI_PINS); \
1969 +}
1970 +
1971 +#define HAL_MISC_ENABLE_ALL_SHARED_GPIO_PINS() \
1972 +{ \
1973 +    (MISC_GPIOA_PIN_ENABLE_REG)        = (0x0); \
1974 +    (MISC_GPIOB_PIN_ENABLE_REG)        = (0x0); \
1975 +}
1976 +
1977 +#define HAL_MISC_DISABLE_ALL_SHARED_GPIO_PINS()        \
1978 +{ \
1979 +    (MISC_GPIOA_PIN_ENABLE_REG)        = (0xFFFFFFFF); \
1980 +    (MISC_GPIOB_PIN_ENABLE_REG)        = (0xFFFFFFFF); \
1981 +}
1982 +
1983 +#define HAL_MISC_CONFIGURE_GPIOA_RESISTOR(pin_index, value) \
1984 +{ \
1985 +    (MISC_GPIOA_RESISTOR_CONFIG_REG) &=        ~(0x3 << (2 * pin_index)); \
1986 +    (MISC_GPIOA_RESISTOR_CONFIG_REG) |=        ((value & 0x3) << (2 * pin_index)); \
1987 +}
1988 +
1989 +#define HAL_MISC_CONFIGURE_GPIOA_DRIVE_STRENGTH(pin_index, value) \
1990 +{ \
1991 +    (MISC_GPIOA_DRIVE_STRENGTH_CONFIG_REG) &= ~(0x1 << pin_index); \
1992 +    (MISC_GPIOA_DRIVE_STRENGTH_CONFIG_REG) |= (value <<        pin_index); \
1993 +}
1994 +
1995 +#define HAL_MISC_SELECT_FAST_ETHERNET_PHY_LED_MODE0() \
1996 +{ \
1997 +    (MISC_FAST_ETHERNET_PHY_CONFIG_REG)        = (0x0); \
1998 +}
1999 +
2000 +#define HAL_MISC_SELECT_FAST_ETHERNET_PHY_LED_MODE1() \
2001 +{ \
2002 +    (MISC_FAST_ETHERNET_PHY_CONFIG_REG)        = (0x1); \
2003 +}
2004 +
2005 +#define HAL_MISC_SELECT_FAST_ETHERNET_PHY_LED_MODE2() \
2006 +{ \
2007 +    (MISC_FAST_ETHERNET_PHY_CONFIG_REG)        = (0x2); \
2008 +}
2009 +
2010 +#define HAL_MISC_SELECT_FAST_ETHERNET_PHY_LED_MODE3() \
2011 +{ \
2012 +    (MISC_FAST_ETHERNET_PHY_CONFIG_REG)        = (0x3); \
2013 +}
2014 +
2015 +
2016 +#endif // end of #ifndef _STAR_MISC_H_
2017 --- /dev/null
2018 +++ b/arch/arm/mach-cns21xx/idle.c
2019 @@ -0,0 +1,31 @@
2020 +/*
2021 + * arch/arm/mach-cns21xx/idle.c
2022 + */
2023 +
2024 +#include <linux/init.h>
2025 +#include <asm/system.h>
2026 +#include <asm/proc-fns.h>
2027 +
2028 +static void cns21xx_idle(void)
2029 +{
2030 +       /*
2031 +        * Because of broken hardware we have to enable interrupts or the CPU
2032 +        * will never wakeup... Acctualy it is not very good to enable
2033 +        * interrupts first since scheduler can miss a tick, but there is
2034 +        * no other way around this. Platforms that needs it for power saving
2035 +        * should enable it in init code, since by default it is
2036 +        * disabled.
2037 +        */
2038 +
2039 +       /* FIXME: Enabling interrupts here is racy! */
2040 +       local_irq_enable();
2041 +       cpu_do_idle();
2042 +}
2043 +
2044 +static int __init cns21xx_idle_init(void)
2045 +{
2046 +       arm_pm_idle = cns21xx_idle;
2047 +       return 0;
2048 +}
2049 +
2050 +arch_initcall(cns21xx_idle_init);