target/linux/brcm63xx/patches-4.1/360-MIPS-BCM63XX-add-support-for-raw-sproms.patch

   1 From cedee63bc73f8b7d45b8c0cba1236986812c1f83 Mon Sep 17 00:00:00 2001
   2 From: Jonas Gorski <jogo@openwrt.org>
   3 Date: Tue, 29 Jul 2014 22:16:36 +0200
   4 Subject: [PATCH 05/10] MIPS: BCM63XX: add support for "raw" sproms
   5
   6 Allow using raw sprom content as templates.
   7
   8 Signed-off-by: Jonas Gorski <jogo@openwrt.org>
   9 ---
  10  arch/mips/bcm63xx/sprom.c | 482 ++++++++++++++++++++++++++++++++++++++++++++++
  11  1 file changed, 482 insertions(+)
  12
  13 --- a/arch/mips/bcm63xx/sprom.c
  14 +++ b/arch/mips/bcm63xx/sprom.c
  15 @@ -55,13 +55,492 @@ int bcm63xx_get_fallback_sprom(struct ss
  16                 return -EINVAL;
  17         }
  18  }
  19 +
  20 +/* FIXME: use lib_sprom after submission upstream */
  21 +
  22 +/* Get the word-offset for a SSB_SPROM_XXX define. */
  23 +#define SPOFF(offset)  ((offset) / sizeof(u16))
  24 +/* Helper to extract some _offset, which is one of the SSB_SPROM_XXX defines. */
  25 +#define SPEX16(_outvar, _offset, _mask, _shift)        \
  26 +       out->_outvar = ((in[SPOFF(_offset)] & (_mask)) >> (_shift))
  27 +#define SPEX32(_outvar, _offset, _mask, _shift)        \
  28 +       out->_outvar = ((((u32)in[SPOFF((_offset)+2)] << 16 | \
  29 +                          in[SPOFF(_offset)]) & (_mask)) >> (_shift))
  30 +#define SPEX(_outvar, _offset, _mask, _shift) \
  31 +       SPEX16(_outvar, _offset, _mask, _shift)
  32 +
  33 +#define SPEX_ARRAY8(_field, _offset, _mask, _shift)    \
  34 +       do {    \
  35 +               SPEX(_field[0], _offset +  0, _mask, _shift);   \
  36 +               SPEX(_field[1], _offset +  2, _mask, _shift);   \
  37 +               SPEX(_field[2], _offset +  4, _mask, _shift);   \
  38 +               SPEX(_field[3], _offset +  6, _mask, _shift);   \
  39 +               SPEX(_field[4], _offset +  8, _mask, _shift);   \
  40 +               SPEX(_field[5], _offset + 10, _mask, _shift);   \
  41 +               SPEX(_field[6], _offset + 12, _mask, _shift);   \
  42 +               SPEX(_field[7], _offset + 14, _mask, _shift);   \
  43 +       } while (0)
  44 +
  45 +
  46 +static s8 r123_extract_antgain(u8 sprom_revision, const u16 *in,
  47 +                              u16 mask, u16 shift)
  48 +{
  49 +       u16 v;
  50 +       u8 gain;
  51 +
  52 +       v = in[SPOFF(SSB_SPROM1_AGAIN)];
  53 +       gain = (v & mask) >> shift;
  54 +       if (gain == 0xFF)
  55 +               gain = 2; /* If unset use 2dBm */
  56 +       if (sprom_revision == 1) {
  57 +               /* Convert to Q5.2 */
  58 +               gain <<= 2;
  59 +       } else {
  60 +               /* Q5.2 Fractional part is stored in 0xC0 */
  61 +               gain = ((gain & 0xC0) >> 6) | ((gain & 0x3F) << 2);
  62 +       }
  63 +
  64 +       return (s8)gain;
  65 +}
  66 +
  67 +static void sprom_extract_r23(struct ssb_sprom *out, const u16 *in)
  68 +{
  69 +       SPEX(boardflags_hi, SSB_SPROM2_BFLHI, 0xFFFF, 0);
  70 +       SPEX(opo, SSB_SPROM2_OPO, SSB_SPROM2_OPO_VALUE, 0);
  71 +       SPEX(pa1lob0, SSB_SPROM2_PA1LOB0, 0xFFFF, 0);
  72 +       SPEX(pa1lob1, SSB_SPROM2_PA1LOB1, 0xFFFF, 0);
  73 +       SPEX(pa1lob2, SSB_SPROM2_PA1LOB2, 0xFFFF, 0);
  74 +       SPEX(pa1hib0, SSB_SPROM2_PA1HIB0, 0xFFFF, 0);
  75 +       SPEX(pa1hib1, SSB_SPROM2_PA1HIB1, 0xFFFF, 0);
  76 +       SPEX(pa1hib2, SSB_SPROM2_PA1HIB2, 0xFFFF, 0);
  77 +       SPEX(maxpwr_ah, SSB_SPROM2_MAXP_A, SSB_SPROM2_MAXP_A_HI, 0);
  78 +       SPEX(maxpwr_al, SSB_SPROM2_MAXP_A, SSB_SPROM2_MAXP_A_LO,
  79 +            SSB_SPROM2_MAXP_A_LO_SHIFT);
  80 +}
  81 +
  82 +static void sprom_extract_r123(struct ssb_sprom *out, const u16 *in)
  83 +{
  84 +       u16 loc[3];
  85 +
  86 +       if (out->revision == 3)                 /* rev 3 moved MAC */
  87 +               loc[0] = SSB_SPROM3_IL0MAC;
  88 +       else {
  89 +               loc[0] = SSB_SPROM1_IL0MAC;
  90 +               loc[1] = SSB_SPROM1_ET0MAC;
  91 +               loc[2] = SSB_SPROM1_ET1MAC;
  92 +       }
  93 +
  94 +       SPEX(et0phyaddr, SSB_SPROM1_ETHPHY, SSB_SPROM1_ETHPHY_ET0A, 0);
  95 +       SPEX(et1phyaddr, SSB_SPROM1_ETHPHY, SSB_SPROM1_ETHPHY_ET1A,
  96 +            SSB_SPROM1_ETHPHY_ET1A_SHIFT);
  97 +       SPEX(et0mdcport, SSB_SPROM1_ETHPHY, SSB_SPROM1_ETHPHY_ET0M, 14);
  98 +       SPEX(et1mdcport, SSB_SPROM1_ETHPHY, SSB_SPROM1_ETHPHY_ET1M, 15);
  99 +       SPEX(board_rev, SSB_SPROM1_BINF, SSB_SPROM1_BINF_BREV, 0);
 100 +       SPEX(board_type, SSB_SPROM1_SPID, 0xFFFF, 0);
 101 +       if (out->revision == 1)
 102 +               SPEX(country_code, SSB_SPROM1_BINF, SSB_SPROM1_BINF_CCODE,
 103 +                    SSB_SPROM1_BINF_CCODE_SHIFT);
 104 +       SPEX(ant_available_a, SSB_SPROM1_BINF, SSB_SPROM1_BINF_ANTA,
 105 +            SSB_SPROM1_BINF_ANTA_SHIFT);
 106 +       SPEX(ant_available_bg, SSB_SPROM1_BINF, SSB_SPROM1_BINF_ANTBG,
 107 +            SSB_SPROM1_BINF_ANTBG_SHIFT);
 108 +       SPEX(pa0b0, SSB_SPROM1_PA0B0, 0xFFFF, 0);
 109 +       SPEX(pa0b1, SSB_SPROM1_PA0B1, 0xFFFF, 0);
 110 +       SPEX(pa0b2, SSB_SPROM1_PA0B2, 0xFFFF, 0);
 111 +       SPEX(pa1b0, SSB_SPROM1_PA1B0, 0xFFFF, 0);
 112 +       SPEX(pa1b1, SSB_SPROM1_PA1B1, 0xFFFF, 0);
 113 +       SPEX(pa1b2, SSB_SPROM1_PA1B2, 0xFFFF, 0);
 114 +       SPEX(gpio0, SSB_SPROM1_GPIOA, SSB_SPROM1_GPIOA_P0, 0);
 115 +       SPEX(gpio1, SSB_SPROM1_GPIOA, SSB_SPROM1_GPIOA_P1,
 116 +            SSB_SPROM1_GPIOA_P1_SHIFT);
 117 +       SPEX(gpio2, SSB_SPROM1_GPIOB, SSB_SPROM1_GPIOB_P2, 0);
 118 +       SPEX(gpio3, SSB_SPROM1_GPIOB, SSB_SPROM1_GPIOB_P3,
 119 +            SSB_SPROM1_GPIOB_P3_SHIFT);
 120 +       SPEX(maxpwr_a, SSB_SPROM1_MAXPWR, SSB_SPROM1_MAXPWR_A,
 121 +            SSB_SPROM1_MAXPWR_A_SHIFT);
 122 +       SPEX(maxpwr_bg, SSB_SPROM1_MAXPWR, SSB_SPROM1_MAXPWR_BG, 0);
 123 +       SPEX(itssi_a, SSB_SPROM1_ITSSI, SSB_SPROM1_ITSSI_A,
 124 +            SSB_SPROM1_ITSSI_A_SHIFT);
 125 +       SPEX(itssi_bg, SSB_SPROM1_ITSSI, SSB_SPROM1_ITSSI_BG, 0);
 126 +       SPEX(boardflags_lo, SSB_SPROM1_BFLLO, 0xFFFF, 0);
 127 +
 128 +       SPEX(alpha2[0], SSB_SPROM1_CCODE, 0xff00, 8);
 129 +       SPEX(alpha2[1], SSB_SPROM1_CCODE, 0x00ff, 0);
 130 +
 131 +       /* Extract the antenna gain values. */
 132 +       out->antenna_gain.a0 = r123_extract_antgain(out->revision, in,
 133 +                                                   SSB_SPROM1_AGAIN_BG,
 134 +                                                   SSB_SPROM1_AGAIN_BG_SHIFT);
 135 +       out->antenna_gain.a1 = r123_extract_antgain(out->revision, in,
 136 +                                                   SSB_SPROM1_AGAIN_A,
 137 +                                                   SSB_SPROM1_AGAIN_A_SHIFT);
 138 +       if (out->revision >= 2)
 139 +               sprom_extract_r23(out, in);
 140 +}
 141 +
 142 +/* Revs 4 5 and 8 have partially shared layout */
 143 +static void sprom_extract_r458(struct ssb_sprom *out, const u16 *in)
 144 +{
 145 +       SPEX(txpid2g[0], SSB_SPROM4_TXPID2G01,
 146 +            SSB_SPROM4_TXPID2G0, SSB_SPROM4_TXPID2G0_SHIFT);
 147 +       SPEX(txpid2g[1], SSB_SPROM4_TXPID2G01,
 148 +            SSB_SPROM4_TXPID2G1, SSB_SPROM4_TXPID2G1_SHIFT);
 149 +       SPEX(txpid2g[2], SSB_SPROM4_TXPID2G23,
 150 +            SSB_SPROM4_TXPID2G2, SSB_SPROM4_TXPID2G2_SHIFT);
 151 +       SPEX(txpid2g[3], SSB_SPROM4_TXPID2G23,
 152 +            SSB_SPROM4_TXPID2G3, SSB_SPROM4_TXPID2G3_SHIFT);
 153 +
 154 +       SPEX(txpid5gl[0], SSB_SPROM4_TXPID5GL01,
 155 +            SSB_SPROM4_TXPID5GL0, SSB_SPROM4_TXPID5GL0_SHIFT);
 156 +       SPEX(txpid5gl[1], SSB_SPROM4_TXPID5GL01,
 157 +            SSB_SPROM4_TXPID5GL1, SSB_SPROM4_TXPID5GL1_SHIFT);
 158 +       SPEX(txpid5gl[2], SSB_SPROM4_TXPID5GL23,
 159 +            SSB_SPROM4_TXPID5GL2, SSB_SPROM4_TXPID5GL2_SHIFT);
 160 +       SPEX(txpid5gl[3], SSB_SPROM4_TXPID5GL23,
 161 +            SSB_SPROM4_TXPID5GL3, SSB_SPROM4_TXPID5GL3_SHIFT);
 162 +
 163 +       SPEX(txpid5g[0], SSB_SPROM4_TXPID5G01,
 164 +            SSB_SPROM4_TXPID5G0, SSB_SPROM4_TXPID5G0_SHIFT);
 165 +       SPEX(txpid5g[1], SSB_SPROM4_TXPID5G01,
 166 +            SSB_SPROM4_TXPID5G1, SSB_SPROM4_TXPID5G1_SHIFT);
 167 +       SPEX(txpid5g[2], SSB_SPROM4_TXPID5G23,
 168 +            SSB_SPROM4_TXPID5G2, SSB_SPROM4_TXPID5G2_SHIFT);
 169 +       SPEX(txpid5g[3], SSB_SPROM4_TXPID5G23,
 170 +            SSB_SPROM4_TXPID5G3, SSB_SPROM4_TXPID5G3_SHIFT);
 171 +
 172 +       SPEX(txpid5gh[0], SSB_SPROM4_TXPID5GH01,
 173 +            SSB_SPROM4_TXPID5GH0, SSB_SPROM4_TXPID5GH0_SHIFT);
 174 +       SPEX(txpid5gh[1], SSB_SPROM4_TXPID5GH01,
 175 +            SSB_SPROM4_TXPID5GH1, SSB_SPROM4_TXPID5GH1_SHIFT);
 176 +       SPEX(txpid5gh[2], SSB_SPROM4_TXPID5GH23,
 177 +            SSB_SPROM4_TXPID5GH2, SSB_SPROM4_TXPID5GH2_SHIFT);
 178 +       SPEX(txpid5gh[3], SSB_SPROM4_TXPID5GH23,
 179 +            SSB_SPROM4_TXPID5GH3, SSB_SPROM4_TXPID5GH3_SHIFT);
 180 +}
 181 +
 182 +static void sprom_extract_r45(struct ssb_sprom *out, const u16 *in)
 183 +{
 184 +       u16 il0mac_offset;
 185 +
 186 +       if (out->revision == 4)
 187 +               il0mac_offset = SSB_SPROM4_IL0MAC;
 188 +       else
 189 +               il0mac_offset = SSB_SPROM5_IL0MAC;
 190 +
 191 +       SPEX(et0phyaddr, SSB_SPROM4_ETHPHY, SSB_SPROM4_ETHPHY_ET0A, 0);
 192 +       SPEX(et1phyaddr, SSB_SPROM4_ETHPHY, SSB_SPROM4_ETHPHY_ET1A,
 193 +            SSB_SPROM4_ETHPHY_ET1A_SHIFT);
 194 +       SPEX(board_rev, SSB_SPROM4_BOARDREV, 0xFFFF, 0);
 195 +       SPEX(board_type, SSB_SPROM1_SPID, 0xFFFF, 0);
 196 +       if (out->revision == 4) {
 197 +               SPEX(alpha2[0], SSB_SPROM4_CCODE, 0xff00, 8);
 198 +               SPEX(alpha2[1], SSB_SPROM4_CCODE, 0x00ff, 0);
 199 +               SPEX(boardflags_lo, SSB_SPROM4_BFLLO, 0xFFFF, 0);
 200 +               SPEX(boardflags_hi, SSB_SPROM4_BFLHI, 0xFFFF, 0);
 201 +               SPEX(boardflags2_lo, SSB_SPROM4_BFL2LO, 0xFFFF, 0);
 202 +               SPEX(boardflags2_hi, SSB_SPROM4_BFL2HI, 0xFFFF, 0);
 203 +       } else {
 204 +               SPEX(alpha2[0], SSB_SPROM5_CCODE, 0xff00, 8);
 205 +               SPEX(alpha2[1], SSB_SPROM5_CCODE, 0x00ff, 0);
 206 +               SPEX(boardflags_lo, SSB_SPROM5_BFLLO, 0xFFFF, 0);
 207 +               SPEX(boardflags_hi, SSB_SPROM5_BFLHI, 0xFFFF, 0);
 208 +               SPEX(boardflags2_lo, SSB_SPROM5_BFL2LO, 0xFFFF, 0);
 209 +               SPEX(boardflags2_hi, SSB_SPROM5_BFL2HI, 0xFFFF, 0);
 210 +       }
 211 +       SPEX(ant_available_a, SSB_SPROM4_ANTAVAIL, SSB_SPROM4_ANTAVAIL_A,
 212 +            SSB_SPROM4_ANTAVAIL_A_SHIFT);
 213 +       SPEX(ant_available_bg, SSB_SPROM4_ANTAVAIL, SSB_SPROM4_ANTAVAIL_BG,
 214 +            SSB_SPROM4_ANTAVAIL_BG_SHIFT);
 215 +       SPEX(maxpwr_bg, SSB_SPROM4_MAXP_BG, SSB_SPROM4_MAXP_BG_MASK, 0);
 216 +       SPEX(itssi_bg, SSB_SPROM4_MAXP_BG, SSB_SPROM4_ITSSI_BG,
 217 +            SSB_SPROM4_ITSSI_BG_SHIFT);
 218 +       SPEX(maxpwr_a, SSB_SPROM4_MAXP_A, SSB_SPROM4_MAXP_A_MASK, 0);
 219 +       SPEX(itssi_a, SSB_SPROM4_MAXP_A, SSB_SPROM4_ITSSI_A,
 220 +            SSB_SPROM4_ITSSI_A_SHIFT);
 221 +       if (out->revision == 4) {
 222 +               SPEX(gpio0, SSB_SPROM4_GPIOA, SSB_SPROM4_GPIOA_P0, 0);
 223 +               SPEX(gpio1, SSB_SPROM4_GPIOA, SSB_SPROM4_GPIOA_P1,
 224 +                    SSB_SPROM4_GPIOA_P1_SHIFT);
 225 +               SPEX(gpio2, SSB_SPROM4_GPIOB, SSB_SPROM4_GPIOB_P2, 0);
 226 +               SPEX(gpio3, SSB_SPROM4_GPIOB, SSB_SPROM4_GPIOB_P3,
 227 +                    SSB_SPROM4_GPIOB_P3_SHIFT);
 228 +       } else {
 229 +               SPEX(gpio0, SSB_SPROM5_GPIOA, SSB_SPROM5_GPIOA_P0, 0);
 230 +               SPEX(gpio1, SSB_SPROM5_GPIOA, SSB_SPROM5_GPIOA_P1,
 231 +                    SSB_SPROM5_GPIOA_P1_SHIFT);
 232 +               SPEX(gpio2, SSB_SPROM5_GPIOB, SSB_SPROM5_GPIOB_P2, 0);
 233 +               SPEX(gpio3, SSB_SPROM5_GPIOB, SSB_SPROM5_GPIOB_P3,
 234 +                    SSB_SPROM5_GPIOB_P3_SHIFT);
 235 +       }
 236 +
 237 +       /* Extract the antenna gain values. */
 238 +       SPEX(antenna_gain.a0, SSB_SPROM4_AGAIN01,
 239 +            SSB_SPROM4_AGAIN0, SSB_SPROM4_AGAIN0_SHIFT);
 240 +       SPEX(antenna_gain.a1, SSB_SPROM4_AGAIN01,
 241 +            SSB_SPROM4_AGAIN1, SSB_SPROM4_AGAIN1_SHIFT);
 242 +       SPEX(antenna_gain.a2, SSB_SPROM4_AGAIN23,
 243 +            SSB_SPROM4_AGAIN2, SSB_SPROM4_AGAIN2_SHIFT);
 244 +       SPEX(antenna_gain.a3, SSB_SPROM4_AGAIN23,
 245 +            SSB_SPROM4_AGAIN3, SSB_SPROM4_AGAIN3_SHIFT);
 246 +
 247 +       sprom_extract_r458(out, in);
 248 +
 249 +       /* TODO - get remaining rev 4 stuff needed */
 250 +}
 251 +
 252 +static void sprom_extract_r8(struct ssb_sprom *out, const u16 *in)
 253 +{
 254 +       int i;
 255 +       u16 o;
 256 +       u16 pwr_info_offset[] = {
 257 +               SSB_SROM8_PWR_INFO_CORE0, SSB_SROM8_PWR_INFO_CORE1,
 258 +               SSB_SROM8_PWR_INFO_CORE2, SSB_SROM8_PWR_INFO_CORE3
 259 +       };
 260 +       BUILD_BUG_ON(ARRAY_SIZE(pwr_info_offset) !=
 261 +                       ARRAY_SIZE(out->core_pwr_info));
 262 +
 263 +       SPEX(board_rev, SSB_SPROM8_BOARDREV, 0xFFFF, 0);
 264 +       SPEX(board_type, SSB_SPROM1_SPID, 0xFFFF, 0);
 265 +       SPEX(alpha2[0], SSB_SPROM8_CCODE, 0xff00, 8);
 266 +       SPEX(alpha2[1], SSB_SPROM8_CCODE, 0x00ff, 0);
 267 +       SPEX(boardflags_lo, SSB_SPROM8_BFLLO, 0xFFFF, 0);
 268 +       SPEX(boardflags_hi, SSB_SPROM8_BFLHI, 0xFFFF, 0);
 269 +       SPEX(boardflags2_lo, SSB_SPROM8_BFL2LO, 0xFFFF, 0);
 270 +       SPEX(boardflags2_hi, SSB_SPROM8_BFL2HI, 0xFFFF, 0);
 271 +       SPEX(ant_available_a, SSB_SPROM8_ANTAVAIL, SSB_SPROM8_ANTAVAIL_A,
 272 +            SSB_SPROM8_ANTAVAIL_A_SHIFT);
 273 +       SPEX(ant_available_bg, SSB_SPROM8_ANTAVAIL, SSB_SPROM8_ANTAVAIL_BG,
 274 +            SSB_SPROM8_ANTAVAIL_BG_SHIFT);
 275 +       SPEX(maxpwr_bg, SSB_SPROM8_MAXP_BG, SSB_SPROM8_MAXP_BG_MASK, 0);
 276 +       SPEX(itssi_bg, SSB_SPROM8_MAXP_BG, SSB_SPROM8_ITSSI_BG,
 277 +            SSB_SPROM8_ITSSI_BG_SHIFT);
 278 +       SPEX(maxpwr_a, SSB_SPROM8_MAXP_A, SSB_SPROM8_MAXP_A_MASK, 0);
 279 +       SPEX(itssi_a, SSB_SPROM8_MAXP_A, SSB_SPROM8_ITSSI_A,
 280 +            SSB_SPROM8_ITSSI_A_SHIFT);
 281 +       SPEX(maxpwr_ah, SSB_SPROM8_MAXP_AHL, SSB_SPROM8_MAXP_AH_MASK, 0);
 282 +       SPEX(maxpwr_al, SSB_SPROM8_MAXP_AHL, SSB_SPROM8_MAXP_AL_MASK,
 283 +            SSB_SPROM8_MAXP_AL_SHIFT);
 284 +       SPEX(gpio0, SSB_SPROM8_GPIOA, SSB_SPROM8_GPIOA_P0, 0);
 285 +       SPEX(gpio1, SSB_SPROM8_GPIOA, SSB_SPROM8_GPIOA_P1,
 286 +            SSB_SPROM8_GPIOA_P1_SHIFT);
 287 +       SPEX(gpio2, SSB_SPROM8_GPIOB, SSB_SPROM8_GPIOB_P2, 0);
 288 +       SPEX(gpio3, SSB_SPROM8_GPIOB, SSB_SPROM8_GPIOB_P3,
 289 +            SSB_SPROM8_GPIOB_P3_SHIFT);
 290 +       SPEX(tri2g, SSB_SPROM8_TRI25G, SSB_SPROM8_TRI2G, 0);
 291 +       SPEX(tri5g, SSB_SPROM8_TRI25G, SSB_SPROM8_TRI5G,
 292 +            SSB_SPROM8_TRI5G_SHIFT);
 293 +       SPEX(tri5gl, SSB_SPROM8_TRI5GHL, SSB_SPROM8_TRI5GL, 0);
 294 +       SPEX(tri5gh, SSB_SPROM8_TRI5GHL, SSB_SPROM8_TRI5GH,
 295 +            SSB_SPROM8_TRI5GH_SHIFT);
 296 +       SPEX(rxpo2g, SSB_SPROM8_RXPO, SSB_SPROM8_RXPO2G, 0);
 297 +       SPEX(rxpo5g, SSB_SPROM8_RXPO, SSB_SPROM8_RXPO5G,
 298 +            SSB_SPROM8_RXPO5G_SHIFT);
 299 +       SPEX(rssismf2g, SSB_SPROM8_RSSIPARM2G, SSB_SPROM8_RSSISMF2G, 0);
 300 +       SPEX(rssismc2g, SSB_SPROM8_RSSIPARM2G, SSB_SPROM8_RSSISMC2G,
 301 +            SSB_SPROM8_RSSISMC2G_SHIFT);
 302 +       SPEX(rssisav2g, SSB_SPROM8_RSSIPARM2G, SSB_SPROM8_RSSISAV2G,
 303 +            SSB_SPROM8_RSSISAV2G_SHIFT);
 304 +       SPEX(bxa2g, SSB_SPROM8_RSSIPARM2G, SSB_SPROM8_BXA2G,
 305 +            SSB_SPROM8_BXA2G_SHIFT);
 306 +       SPEX(rssismf5g, SSB_SPROM8_RSSIPARM5G, SSB_SPROM8_RSSISMF5G, 0);
 307 +       SPEX(rssismc5g, SSB_SPROM8_RSSIPARM5G, SSB_SPROM8_RSSISMC5G,
 308 +            SSB_SPROM8_RSSISMC5G_SHIFT);
 309 +       SPEX(rssisav5g, SSB_SPROM8_RSSIPARM5G, SSB_SPROM8_RSSISAV5G,
 310 +            SSB_SPROM8_RSSISAV5G_SHIFT);
 311 +       SPEX(bxa5g, SSB_SPROM8_RSSIPARM5G, SSB_SPROM8_BXA5G,
 312 +            SSB_SPROM8_BXA5G_SHIFT);
 313 +       SPEX(pa0b0, SSB_SPROM8_PA0B0, 0xFFFF, 0);
 314 +       SPEX(pa0b1, SSB_SPROM8_PA0B1, 0xFFFF, 0);
 315 +       SPEX(pa0b2, SSB_SPROM8_PA0B2, 0xFFFF, 0);
 316 +       SPEX(pa1b0, SSB_SPROM8_PA1B0, 0xFFFF, 0);
 317 +       SPEX(pa1b1, SSB_SPROM8_PA1B1, 0xFFFF, 0);
 318 +       SPEX(pa1b2, SSB_SPROM8_PA1B2, 0xFFFF, 0);
 319 +       SPEX(pa1lob0, SSB_SPROM8_PA1LOB0, 0xFFFF, 0);
 320 +       SPEX(pa1lob1, SSB_SPROM8_PA1LOB1, 0xFFFF, 0);
 321 +       SPEX(pa1lob2, SSB_SPROM8_PA1LOB2, 0xFFFF, 0);
 322 +       SPEX(pa1hib0, SSB_SPROM8_PA1HIB0, 0xFFFF, 0);
 323 +       SPEX(pa1hib1, SSB_SPROM8_PA1HIB1, 0xFFFF, 0);
 324 +       SPEX(pa1hib2, SSB_SPROM8_PA1HIB2, 0xFFFF, 0);
 325 +       SPEX(cck2gpo, SSB_SPROM8_CCK2GPO, 0xFFFF, 0);
 326 +       SPEX32(ofdm2gpo, SSB_SPROM8_OFDM2GPO, 0xFFFFFFFF, 0);
 327 +       SPEX32(ofdm5glpo, SSB_SPROM8_OFDM5GLPO, 0xFFFFFFFF, 0);
 328 +       SPEX32(ofdm5gpo, SSB_SPROM8_OFDM5GPO, 0xFFFFFFFF, 0);
 329 +       SPEX32(ofdm5ghpo, SSB_SPROM8_OFDM5GHPO, 0xFFFFFFFF, 0);
 330 +
 331 +       /* Extract the antenna gain values. */
 332 +       SPEX(antenna_gain.a0, SSB_SPROM8_AGAIN01,
 333 +            SSB_SPROM8_AGAIN0, SSB_SPROM8_AGAIN0_SHIFT);
 334 +       SPEX(antenna_gain.a1, SSB_SPROM8_AGAIN01,
 335 +            SSB_SPROM8_AGAIN1, SSB_SPROM8_AGAIN1_SHIFT);
 336 +       SPEX(antenna_gain.a2, SSB_SPROM8_AGAIN23,
 337 +            SSB_SPROM8_AGAIN2, SSB_SPROM8_AGAIN2_SHIFT);
 338 +       SPEX(antenna_gain.a3, SSB_SPROM8_AGAIN23,
 339 +            SSB_SPROM8_AGAIN3, SSB_SPROM8_AGAIN3_SHIFT);
 340 +
 341 +       /* Extract cores power info info */
 342 +       for (i = 0; i < ARRAY_SIZE(pwr_info_offset); i++) {
 343 +               o = pwr_info_offset[i];
 344 +               SPEX(core_pwr_info[i].itssi_2g, o + SSB_SROM8_2G_MAXP_ITSSI,
 345 +                       SSB_SPROM8_2G_ITSSI, SSB_SPROM8_2G_ITSSI_SHIFT);
 346 +               SPEX(core_pwr_info[i].maxpwr_2g, o + SSB_SROM8_2G_MAXP_ITSSI,
 347 +                       SSB_SPROM8_2G_MAXP, 0);
 348 +
 349 +               SPEX(core_pwr_info[i].pa_2g[0], o + SSB_SROM8_2G_PA_0, ~0, 0);
 350 +               SPEX(core_pwr_info[i].pa_2g[1], o + SSB_SROM8_2G_PA_1, ~0, 0);
 351 +               SPEX(core_pwr_info[i].pa_2g[2], o + SSB_SROM8_2G_PA_2, ~0, 0);
 352 +
 353 +               SPEX(core_pwr_info[i].itssi_5g, o + SSB_SROM8_5G_MAXP_ITSSI,
 354 +                       SSB_SPROM8_5G_ITSSI, SSB_SPROM8_5G_ITSSI_SHIFT);
 355 +               SPEX(core_pwr_info[i].maxpwr_5g, o + SSB_SROM8_5G_MAXP_ITSSI,
 356 +                       SSB_SPROM8_5G_MAXP, 0);
 357 +               SPEX(core_pwr_info[i].maxpwr_5gh, o + SSB_SPROM8_5GHL_MAXP,
 358 +                       SSB_SPROM8_5GH_MAXP, 0);
 359 +               SPEX(core_pwr_info[i].maxpwr_5gl, o + SSB_SPROM8_5GHL_MAXP,
 360 +                       SSB_SPROM8_5GL_MAXP, SSB_SPROM8_5GL_MAXP_SHIFT);
 361 +
 362 +               SPEX(core_pwr_info[i].pa_5gl[0], o + SSB_SROM8_5GL_PA_0, ~0, 0);
 363 +               SPEX(core_pwr_info[i].pa_5gl[1], o + SSB_SROM8_5GL_PA_1, ~0, 0);
 364 +               SPEX(core_pwr_info[i].pa_5gl[2], o + SSB_SROM8_5GL_PA_2, ~0, 0);
 365 +               SPEX(core_pwr_info[i].pa_5g[0], o + SSB_SROM8_5G_PA_0, ~0, 0);
 366 +               SPEX(core_pwr_info[i].pa_5g[1], o + SSB_SROM8_5G_PA_1, ~0, 0);
 367 +               SPEX(core_pwr_info[i].pa_5g[2], o + SSB_SROM8_5G_PA_2, ~0, 0);
 368 +               SPEX(core_pwr_info[i].pa_5gh[0], o + SSB_SROM8_5GH_PA_0, ~0, 0);
 369 +               SPEX(core_pwr_info[i].pa_5gh[1], o + SSB_SROM8_5GH_PA_1, ~0, 0);
 370 +               SPEX(core_pwr_info[i].pa_5gh[2], o + SSB_SROM8_5GH_PA_2, ~0, 0);
 371 +       }
 372 +
 373 +       /* Extract FEM info */
 374 +       SPEX(fem.ghz2.tssipos, SSB_SPROM8_FEM2G,
 375 +               SSB_SROM8_FEM_TSSIPOS, SSB_SROM8_FEM_TSSIPOS_SHIFT);
 376 +       SPEX(fem.ghz2.extpa_gain, SSB_SPROM8_FEM2G,
 377 +               SSB_SROM8_FEM_EXTPA_GAIN, SSB_SROM8_FEM_EXTPA_GAIN_SHIFT);
 378 +       SPEX(fem.ghz2.pdet_range, SSB_SPROM8_FEM2G,
 379 +               SSB_SROM8_FEM_PDET_RANGE, SSB_SROM8_FEM_PDET_RANGE_SHIFT);
 380 +       SPEX(fem.ghz2.tr_iso, SSB_SPROM8_FEM2G,
 381 +               SSB_SROM8_FEM_TR_ISO, SSB_SROM8_FEM_TR_ISO_SHIFT);
 382 +       SPEX(fem.ghz2.antswlut, SSB_SPROM8_FEM2G,
 383 +               SSB_SROM8_FEM_ANTSWLUT, SSB_SROM8_FEM_ANTSWLUT_SHIFT);
 384 +
 385 +       SPEX(fem.ghz5.tssipos, SSB_SPROM8_FEM5G,
 386 +               SSB_SROM8_FEM_TSSIPOS, SSB_SROM8_FEM_TSSIPOS_SHIFT);
 387 +       SPEX(fem.ghz5.extpa_gain, SSB_SPROM8_FEM5G,
 388 +               SSB_SROM8_FEM_EXTPA_GAIN, SSB_SROM8_FEM_EXTPA_GAIN_SHIFT);
 389 +       SPEX(fem.ghz5.pdet_range, SSB_SPROM8_FEM5G,
 390 +               SSB_SROM8_FEM_PDET_RANGE, SSB_SROM8_FEM_PDET_RANGE_SHIFT);
 391 +       SPEX(fem.ghz5.tr_iso, SSB_SPROM8_FEM5G,
 392 +               SSB_SROM8_FEM_TR_ISO, SSB_SROM8_FEM_TR_ISO_SHIFT);
 393 +       SPEX(fem.ghz5.antswlut, SSB_SPROM8_FEM5G,
 394 +               SSB_SROM8_FEM_ANTSWLUT, SSB_SROM8_FEM_ANTSWLUT_SHIFT);
 395 +
 396 +       SPEX(leddc_on_time, SSB_SPROM8_LEDDC, SSB_SPROM8_LEDDC_ON,
 397 +            SSB_SPROM8_LEDDC_ON_SHIFT);
 398 +       SPEX(leddc_off_time, SSB_SPROM8_LEDDC, SSB_SPROM8_LEDDC_OFF,
 399 +            SSB_SPROM8_LEDDC_OFF_SHIFT);
 400 +
 401 +       SPEX(txchain, SSB_SPROM8_TXRXC, SSB_SPROM8_TXRXC_TXCHAIN,
 402 +            SSB_SPROM8_TXRXC_TXCHAIN_SHIFT);
 403 +       SPEX(rxchain, SSB_SPROM8_TXRXC, SSB_SPROM8_TXRXC_RXCHAIN,
 404 +            SSB_SPROM8_TXRXC_RXCHAIN_SHIFT);
 405 +       SPEX(antswitch, SSB_SPROM8_TXRXC, SSB_SPROM8_TXRXC_SWITCH,
 406 +            SSB_SPROM8_TXRXC_SWITCH_SHIFT);
 407 +
 408 +       SPEX(opo, SSB_SPROM8_OFDM2GPO, 0x00ff, 0);
 409 +
 410 +       SPEX_ARRAY8(mcs2gpo, SSB_SPROM8_2G_MCSPO, ~0, 0);
 411 +       SPEX_ARRAY8(mcs5gpo, SSB_SPROM8_5G_MCSPO, ~0, 0);
 412 +       SPEX_ARRAY8(mcs5glpo, SSB_SPROM8_5GL_MCSPO, ~0, 0);
 413 +       SPEX_ARRAY8(mcs5ghpo, SSB_SPROM8_5GH_MCSPO, ~0, 0);
 414 +
 415 +       SPEX(rawtempsense, SSB_SPROM8_RAWTS, SSB_SPROM8_RAWTS_RAWTEMP,
 416 +            SSB_SPROM8_RAWTS_RAWTEMP_SHIFT);
 417 +       SPEX(measpower, SSB_SPROM8_RAWTS, SSB_SPROM8_RAWTS_MEASPOWER,
 418 +            SSB_SPROM8_RAWTS_MEASPOWER_SHIFT);
 419 +       SPEX(tempsense_slope, SSB_SPROM8_OPT_CORRX,
 420 +            SSB_SPROM8_OPT_CORRX_TEMP_SLOPE,
 421 +            SSB_SPROM8_OPT_CORRX_TEMP_SLOPE_SHIFT);
 422 +       SPEX(tempcorrx, SSB_SPROM8_OPT_CORRX, SSB_SPROM8_OPT_CORRX_TEMPCORRX,
 423 +            SSB_SPROM8_OPT_CORRX_TEMPCORRX_SHIFT);
 424 +       SPEX(tempsense_option, SSB_SPROM8_OPT_CORRX,
 425 +            SSB_SPROM8_OPT_CORRX_TEMP_OPTION,
 426 +            SSB_SPROM8_OPT_CORRX_TEMP_OPTION_SHIFT);
 427 +       SPEX(freqoffset_corr, SSB_SPROM8_HWIQ_IQSWP,
 428 +            SSB_SPROM8_HWIQ_IQSWP_FREQ_CORR,
 429 +            SSB_SPROM8_HWIQ_IQSWP_FREQ_CORR_SHIFT);
 430 +       SPEX(iqcal_swp_dis, SSB_SPROM8_HWIQ_IQSWP,
 431 +            SSB_SPROM8_HWIQ_IQSWP_IQCAL_SWP,
 432 +            SSB_SPROM8_HWIQ_IQSWP_IQCAL_SWP_SHIFT);
 433 +       SPEX(hw_iqcal_en, SSB_SPROM8_HWIQ_IQSWP, SSB_SPROM8_HWIQ_IQSWP_HW_IQCAL,
 434 +            SSB_SPROM8_HWIQ_IQSWP_HW_IQCAL_SHIFT);
 435 +
 436 +       SPEX(bw40po, SSB_SPROM8_BW40PO, ~0, 0);
 437 +       SPEX(cddpo, SSB_SPROM8_CDDPO, ~0, 0);
 438 +       SPEX(stbcpo, SSB_SPROM8_STBCPO, ~0, 0);
 439 +       SPEX(bwduppo, SSB_SPROM8_BWDUPPO, ~0, 0);
 440 +
 441 +       SPEX(tempthresh, SSB_SPROM8_THERMAL, SSB_SPROM8_THERMAL_TRESH,
 442 +            SSB_SPROM8_THERMAL_TRESH_SHIFT);
 443 +       SPEX(tempoffset, SSB_SPROM8_THERMAL, SSB_SPROM8_THERMAL_OFFSET,
 444 +            SSB_SPROM8_THERMAL_OFFSET_SHIFT);
 445 +       SPEX(phycal_tempdelta, SSB_SPROM8_TEMPDELTA,
 446 +            SSB_SPROM8_TEMPDELTA_PHYCAL,
 447 +            SSB_SPROM8_TEMPDELTA_PHYCAL_SHIFT);
 448 +       SPEX(temps_period, SSB_SPROM8_TEMPDELTA, SSB_SPROM8_TEMPDELTA_PERIOD,
 449 +            SSB_SPROM8_TEMPDELTA_PERIOD_SHIFT);
 450 +       SPEX(temps_hysteresis, SSB_SPROM8_TEMPDELTA,
 451 +            SSB_SPROM8_TEMPDELTA_HYSTERESIS,
 452 +            SSB_SPROM8_TEMPDELTA_HYSTERESIS_SHIFT);
 453 +       sprom_extract_r458(out, in);
 454 +
 455 +       /* TODO - get remaining rev 8 stuff needed */
 456 +}
 457 +
 458 +static int sprom_extract(struct ssb_sprom *out, const u16 *in, u16 size)
 459 +{
 460 +       memset(out, 0, sizeof(*out));
 461 +
 462 +       out->revision = in[size - 1] & 0x00FF;
 463 +       memset(out->et0mac, 0xFF, 6);           /* preset et0 and et1 mac */
 464 +       memset(out->et1mac, 0xFF, 6);
 465 +
 466 +       switch (out->revision) {
 467 +       case 1:
 468 +       case 2:
 469 +       case 3:
 470 +               sprom_extract_r123(out, in);
 471 +               break;
 472 +       case 4:
 473 +       case 5:
 474 +               sprom_extract_r45(out, in);
 475 +               break;
 476 +       case 8:
 477 +               sprom_extract_r8(out, in);
 478 +               break;
 479 +       default:
 480 +               pr_warn("Unsupported SPROM revision %d detected. Will extract v1\n",
 481 +                        out->revision);
 482 +               out->revision = 1;
 483 +               sprom_extract_r123(out, in);
 484 +       }
 485 +
 486 +       if (out->boardflags_lo == 0xFFFF)
 487 +               out->boardflags_lo = 0;  /* per specs */
 488 +       if (out->boardflags_hi == 0xFFFF)
 489 +               out->boardflags_hi = 0;  /* per specs */
 490 +
 491 +       return 0;
 492 +}
 493 +
 494 +static __initdata u16 template_sprom[220];
 495  #endif
 496
 497 +
 498  int __init bcm63xx_register_fallback_sprom(struct fallback_sprom_data *data)
 499  {
 500         int ret = 0;
 501
 502  #ifdef CONFIG_SSB_PCIHOST
 503 +       u16 size = 0;
 504 +
 505         switch (data->type) {
 506         case SPROM_DEFAULT:
 507                 memcpy(&bcm63xx_sprom, &bcm63xx_default_sprom,
 508 @@ -71,6 +550,9 @@ int __init bcm63xx_register_fallback_spr
 509                 return -EINVAL;
 510         }
 511
 512 +       if (size > 0)
 513 +               sprom_extract(&bcm63xx_sprom, template_sprom, size);
 514 +
 515         memcpy(bcm63xx_sprom.il0mac, data->mac_addr, ETH_ALEN);
 516         memcpy(bcm63xx_sprom.et0mac, data->mac_addr, ETH_ALEN);
 517         memcpy(bcm63xx_sprom.et1mac, data->mac_addr, ETH_ALEN);