target/linux/bcm53xx/patches-4.1/130-dt-bindings-add-SMP-enable-method-for-Broadcom-NSP.patch

   1 From 204b9dbd7c4bd5a223fd104b9cba56c12fe04add Mon Sep 17 00:00:00 2001
   2 From: Kapil Hali <kapilh@broadcom.com>
   3 Date: Wed, 19 Aug 2015 13:42:23 -0400
   4 Subject: [PATCH 130/134] dt-bindings: add SMP enable-method for Broadcom NSP
   5
   6 Add a compatible string "brcm,bcm-nsp-smp" for Broadcom's
   7 Northstar Plus CPU to the 32-bit ARM CPU device tree binding
   8 documentation file and create a new binding documentation for
   9 Northstar Plus CPU.
  10
  11 Signed-off-by: Kapil Hali <kapilh@broadcom.com>
  12 ---
  13  .../bindings/arm/bcm/brcm,nsp-cpu-method.txt       | 39 ++++++++++++++++++++++
  14  Documentation/devicetree/bindings/arm/cpus.txt     |  1 +
  15  2 files changed, 40 insertions(+)
  16  create mode 100644 Documentation/devicetree/bindings/arm/bcm/brcm,nsp-cpu-method.txt
  17
  18 --- /dev/null
  19 +++ b/Documentation/devicetree/bindings/arm/bcm/brcm,nsp-cpu-method.txt
  20 @@ -0,0 +1,39 @@
  21 +Broadcom Northstar Plus SoC CPU Enable Method
  22 +---------------------------------------------
  23 +This binding defines the enable method used for starting secondary
  24 +CPUs in the following Broadcom SoCs:
  25 +  BCM58522, BCM58525, BCM58535, BCM58622, BCM58623, BCM58625, BCM88312
  26 +
  27 +The enable method is specified by defining the following required
  28 +properties in the "cpus" device tree node:
  29 +  - enable-method = "brcm,bcm-nsp-smp";
  30 +  - secondary-boot-reg = <...>;
  31 +
  32 +The secondary-boot-reg property is a u32 value that specifies the
  33 +physical address of the register which should hold the common
  34 +entry point for a secondary CPU. This entry is cpu node specific
  35 +and should be added per cpu. E.g., in case of NSP (BCM58625) which
  36 +is a dual core CPU SoC, this entry should be added to cpu1 node.
  37 +
  38 +
  39 +Example:
  40 +       cpus {
  41 +               #address-cells = <1>;
  42 +               #size-cells = <0>;
  43 +               enable-method = "brcm,bcm-nsp-smp";
  44 +
  45 +               cpu0: cpu@0 {
  46 +                       device_type = "cpu";
  47 +                       compatible = "arm,cortex-a9";
  48 +                       next-level-cache = <&L2>;
  49 +                       reg = <0>;
  50 +               };
  51 +
  52 +               cpu1: cpu@1 {
  53 +                       device_type = "cpu";
  54 +                       compatible = "arm,cortex-a9";
  55 +                       next-level-cache = <&L2>;
  56 +                       reg = <1>;
  57 +                       secondary-boot-reg = <0xffff042c>;
  58 +               };
  59 +       };
  60 --- a/Documentation/devicetree/bindings/arm/cpus.txt
  61 +++ b/Documentation/devicetree/bindings/arm/cpus.txt
  62 @@ -189,6 +189,7 @@ nodes to be present and contain the prop
  63                           can be one of:
  64                             "allwinner,sun6i-a31"
  65                             "arm,psci"
  66 +                           "brcm,bcm-nsp-smp"
  67                             "brcm,brahma-b15"
  68                             "marvell,armada-375-smp"
  69                             "marvell,armada-380-smp"