target/linux/ar71xx/files/drivers/net/ag71xx/ag71xx_main.c

   1 /*
   2  *  Atheros AR71xx built-in ethernet mac driver
   3  *
   4  *  Copyright (C) 2008-2010 Gabor Juhos <juhosg@openwrt.org>
   5  *  Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
   6  *
   7  *  Based on Atheros' AG7100 driver
   8  *
   9  *  This program is free software; you can redistribute it and/or modify it
  10  *  under the terms of the GNU General Public License version 2 as published
  11  *  by the Free Software Foundation.
  12  */
  13
  14 #include "ag71xx.h"
  15
  16 #define AG71XX_DEFAULT_MSG_ENABLE       \
  17         ( NETIF_MSG_DRV                 \
  18         | NETIF_MSG_PROBE               \
  19         | NETIF_MSG_LINK                \
  20         | NETIF_MSG_TIMER               \
  21         | NETIF_MSG_IFDOWN              \
  22         | NETIF_MSG_IFUP                \
  23         | NETIF_MSG_RX_ERR              \
  24         | NETIF_MSG_TX_ERR )
  25
  26 static int ag71xx_msg_level = -1;
  27
  28 module_param_named(msg_level, ag71xx_msg_level, int, 0);
  29 MODULE_PARM_DESC(msg_level, "Message level (-1=defaults,0=none,...,16=all)");
  30
  31 static void ag71xx_dump_dma_regs(struct ag71xx *ag)
  32 {
  33         DBG("%s: dma_tx_ctrl=%08x, dma_tx_desc=%08x, dma_tx_status=%08x\n",
  34                 ag->dev->name,
  35                 ag71xx_rr(ag, AG71XX_REG_TX_CTRL),
  36                 ag71xx_rr(ag, AG71XX_REG_TX_DESC),
  37                 ag71xx_rr(ag, AG71XX_REG_TX_STATUS));
  38
  39         DBG("%s: dma_rx_ctrl=%08x, dma_rx_desc=%08x, dma_rx_status=%08x\n",
  40                 ag->dev->name,
  41                 ag71xx_rr(ag, AG71XX_REG_RX_CTRL),
  42                 ag71xx_rr(ag, AG71XX_REG_RX_DESC),
  43                 ag71xx_rr(ag, AG71XX_REG_RX_STATUS));
  44 }
  45
  46 static void ag71xx_dump_regs(struct ag71xx *ag)
  47 {
  48         DBG("%s: mac_cfg1=%08x, mac_cfg2=%08x, ipg=%08x, hdx=%08x, mfl=%08x\n",
  49                 ag->dev->name,
  50                 ag71xx_rr(ag, AG71XX_REG_MAC_CFG1),
  51                 ag71xx_rr(ag, AG71XX_REG_MAC_CFG2),
  52                 ag71xx_rr(ag, AG71XX_REG_MAC_IPG),
  53                 ag71xx_rr(ag, AG71XX_REG_MAC_HDX),
  54                 ag71xx_rr(ag, AG71XX_REG_MAC_MFL));
  55         DBG("%s: mac_ifctl=%08x, mac_addr1=%08x, mac_addr2=%08x\n",
  56                 ag->dev->name,
  57                 ag71xx_rr(ag, AG71XX_REG_MAC_IFCTL),
  58                 ag71xx_rr(ag, AG71XX_REG_MAC_ADDR1),
  59                 ag71xx_rr(ag, AG71XX_REG_MAC_ADDR2));
  60         DBG("%s: fifo_cfg0=%08x, fifo_cfg1=%08x, fifo_cfg2=%08x\n",
  61                 ag->dev->name,
  62                 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG0),
  63                 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG1),
  64                 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG2));
  65         DBG("%s: fifo_cfg3=%08x, fifo_cfg4=%08x, fifo_cfg5=%08x\n",
  66                 ag->dev->name,
  67                 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG3),
  68                 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG4),
  69                 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG5));
  70 }
  71
  72 static inline void ag71xx_dump_intr(struct ag71xx *ag, char *label, u32 intr)
  73 {
  74         DBG("%s: %s intr=%08x %s%s%s%s%s%s\n",
  75                 ag->dev->name, label, intr,
  76                 (intr & AG71XX_INT_TX_PS) ? "TXPS " : "",
  77                 (intr & AG71XX_INT_TX_UR) ? "TXUR " : "",
  78                 (intr & AG71XX_INT_TX_BE) ? "TXBE " : "",
  79                 (intr & AG71XX_INT_RX_PR) ? "RXPR " : "",
  80                 (intr & AG71XX_INT_RX_OF) ? "RXOF " : "",
  81                 (intr & AG71XX_INT_RX_BE) ? "RXBE " : "");
  82 }
  83
  84 static void ag71xx_ring_free(struct ag71xx_ring *ring)
  85 {
  86         kfree(ring->buf);
  87
  88         if (ring->descs_cpu)
  89                 dma_free_coherent(NULL, ring->size * ring->desc_size,
  90                                   ring->descs_cpu, ring->descs_dma);
  91 }
  92
  93 static int ag71xx_ring_alloc(struct ag71xx_ring *ring, unsigned int size)
  94 {
  95         int err;
  96         int i;
  97
  98         ring->desc_size = sizeof(struct ag71xx_desc);
  99         if (ring->desc_size % cache_line_size()) {
 100                 DBG("ag71xx: ring %p, desc size %u rounded to %u\n",
 101                         ring, ring->desc_size,
 102                         roundup(ring->desc_size, cache_line_size()));
 103                 ring->desc_size = roundup(ring->desc_size, cache_line_size());
 104         }
 105
 106         ring->descs_cpu = dma_alloc_coherent(NULL, size * ring->desc_size,
 107                                              &ring->descs_dma, GFP_ATOMIC);
 108         if (!ring->descs_cpu) {
 109                 err = -ENOMEM;
 110                 goto err;
 111         }
 112
 113         ring->size = size;
 114
 115         ring->buf = kzalloc(size * sizeof(*ring->buf), GFP_KERNEL);
 116         if (!ring->buf) {
 117                 err = -ENOMEM;
 118                 goto err;
 119         }
 120
 121         for (i = 0; i < size; i++) {
 122                 ring->buf[i].desc = (struct ag71xx_desc *)&ring->descs_cpu[i * ring->desc_size];
 123                 DBG("ag71xx: ring %p, desc %d at %p\n",
 124                         ring, i, ring->buf[i].desc);
 125         }
 126
 127         return 0;
 128
 129  err:
 130         return err;
 131 }
 132
 133 static void ag71xx_ring_tx_clean(struct ag71xx *ag)
 134 {
 135         struct ag71xx_ring *ring = &ag->tx_ring;
 136         struct net_device *dev = ag->dev;
 137
 138         while (ring->curr != ring->dirty) {
 139                 u32 i = ring->dirty % AG71XX_TX_RING_SIZE;
 140
 141                 if (!ag71xx_desc_empty(ring->buf[i].desc)) {
 142                         ring->buf[i].desc->ctrl = 0;
 143                         dev->stats.tx_errors++;
 144                 }
 145
 146                 if (ring->buf[i].skb)
 147                         dev_kfree_skb_any(ring->buf[i].skb);
 148
 149                 ring->buf[i].skb = NULL;
 150
 151                 ring->dirty++;
 152         }
 153
 154         /* flush descriptors */
 155         wmb();
 156
 157 }
 158
 159 static void ag71xx_ring_tx_init(struct ag71xx *ag)
 160 {
 161         struct ag71xx_ring *ring = &ag->tx_ring;
 162         int i;
 163
 164         for (i = 0; i < AG71XX_TX_RING_SIZE; i++) {
 165                 ring->buf[i].desc->next = (u32) (ring->descs_dma +
 166                         ring->desc_size * ((i + 1) % AG71XX_TX_RING_SIZE));
 167
 168                 ring->buf[i].desc->ctrl = DESC_EMPTY;
 169                 ring->buf[i].skb = NULL;
 170         }
 171
 172         /* flush descriptors */
 173         wmb();
 174
 175         ring->curr = 0;
 176         ring->dirty = 0;
 177 }
 178
 179 static void ag71xx_ring_rx_clean(struct ag71xx *ag)
 180 {
 181         struct ag71xx_ring *ring = &ag->rx_ring;
 182         int i;
 183
 184         if (!ring->buf)
 185                 return;
 186
 187         for (i = 0; i < AG71XX_RX_RING_SIZE; i++)
 188                 if (ring->buf[i].skb) {
 189                         dma_unmap_single(&ag->dev->dev, ring->buf[i].dma_addr,
 190                                          AG71XX_RX_PKT_SIZE, DMA_FROM_DEVICE);
 191                         kfree_skb(ring->buf[i].skb);
 192                 }
 193 }
 194
 195 static int ag71xx_rx_reserve(struct ag71xx *ag)
 196 {
 197         int reserve = 0;
 198
 199         if (ag71xx_get_pdata(ag)->is_ar724x) {
 200                 if (!ag71xx_has_ar8216(ag))
 201                         reserve = 2;
 202
 203                 if (ag->phy_dev)
 204                         reserve += 4 - (ag->phy_dev->pkt_align % 4);
 205
 206                 reserve %= 4;
 207         }
 208
 209         return reserve + AG71XX_RX_PKT_RESERVE;
 210 }
 211
 212
 213 static int ag71xx_ring_rx_init(struct ag71xx *ag)
 214 {
 215         struct ag71xx_ring *ring = &ag->rx_ring;
 216         unsigned int reserve = ag71xx_rx_reserve(ag);
 217         unsigned int i;
 218         int ret;
 219
 220         ret = 0;
 221         for (i = 0; i < AG71XX_RX_RING_SIZE; i++) {
 222                 ring->buf[i].desc->next = (u32) (ring->descs_dma +
 223                         ring->desc_size * ((i + 1) % AG71XX_RX_RING_SIZE));
 224
 225                 DBG("ag71xx: RX desc at %p, next is %08x\n",
 226                         ring->buf[i].desc,
 227                         ring->buf[i].desc->next);
 228         }
 229
 230         for (i = 0; i < AG71XX_RX_RING_SIZE; i++) {
 231                 struct sk_buff *skb;
 232                 dma_addr_t dma_addr;
 233
 234                 skb = dev_alloc_skb(AG71XX_RX_PKT_SIZE + reserve);
 235                 if (!skb) {
 236                         ret = -ENOMEM;
 237                         break;
 238                 }
 239
 240                 skb->dev = ag->dev;
 241                 skb_reserve(skb, reserve);
 242
 243                 dma_addr = dma_map_single(&ag->dev->dev, skb->data,
 244                                           AG71XX_RX_PKT_SIZE,
 245                                           DMA_FROM_DEVICE);
 246                 ring->buf[i].skb = skb;
 247                 ring->buf[i].dma_addr = dma_addr;
 248                 ring->buf[i].desc->data = (u32) dma_addr;
 249                 ring->buf[i].desc->ctrl = DESC_EMPTY;
 250         }
 251
 252         /* flush descriptors */
 253         wmb();
 254
 255         ring->curr = 0;
 256         ring->dirty = 0;
 257
 258         return ret;
 259 }
 260
 261 static int ag71xx_ring_rx_refill(struct ag71xx *ag)
 262 {
 263         struct ag71xx_ring *ring = &ag->rx_ring;
 264         unsigned int reserve = ag71xx_rx_reserve(ag);
 265         unsigned int count;
 266
 267         count = 0;
 268         for (; ring->curr - ring->dirty > 0; ring->dirty++) {
 269                 unsigned int i;
 270
 271                 i = ring->dirty % AG71XX_RX_RING_SIZE;
 272
 273                 if (ring->buf[i].skb == NULL) {
 274                         dma_addr_t dma_addr;
 275                         struct sk_buff *skb;
 276
 277                         skb = dev_alloc_skb(AG71XX_RX_PKT_SIZE + reserve);
 278                         if (skb == NULL)
 279                                 break;
 280
 281                         skb_reserve(skb, reserve);
 282                         skb->dev = ag->dev;
 283
 284                         dma_addr = dma_map_single(&ag->dev->dev, skb->data,
 285                                                   AG71XX_RX_PKT_SIZE,
 286                                                   DMA_FROM_DEVICE);
 287
 288                         ring->buf[i].skb = skb;
 289                         ring->buf[i].dma_addr = dma_addr;
 290                         ring->buf[i].desc->data = (u32) dma_addr;
 291                 }
 292
 293                 ring->buf[i].desc->ctrl = DESC_EMPTY;
 294                 count++;
 295         }
 296
 297         /* flush descriptors */
 298         wmb();
 299
 300         DBG("%s: %u rx descriptors refilled\n", ag->dev->name, count);
 301
 302         return count;
 303 }
 304
 305 static int ag71xx_rings_init(struct ag71xx *ag)
 306 {
 307         int ret;
 308
 309         ret = ag71xx_ring_alloc(&ag->tx_ring, AG71XX_TX_RING_SIZE);
 310         if (ret)
 311                 return ret;
 312
 313         ag71xx_ring_tx_init(ag);
 314
 315         ret = ag71xx_ring_alloc(&ag->rx_ring, AG71XX_RX_RING_SIZE);
 316         if (ret)
 317                 return ret;
 318
 319         ret = ag71xx_ring_rx_init(ag);
 320         return ret;
 321 }
 322
 323 static void ag71xx_rings_cleanup(struct ag71xx *ag)
 324 {
 325         ag71xx_ring_rx_clean(ag);
 326         ag71xx_ring_free(&ag->rx_ring);
 327
 328         ag71xx_ring_tx_clean(ag);
 329         ag71xx_ring_free(&ag->tx_ring);
 330 }
 331
 332 static unsigned char *ag71xx_speed_str(struct ag71xx *ag)
 333 {
 334         switch (ag->speed) {
 335         case SPEED_1000:
 336                 return "1000";
 337         case SPEED_100:
 338                 return "100";
 339         case SPEED_10:
 340                 return "10";
 341         }
 342
 343         return "?";
 344 }
 345
 346 void ag71xx_link_adjust(struct ag71xx *ag)
 347 {
 348         struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag);
 349         u32 cfg2;
 350         u32 ifctl;
 351         u32 fifo5;
 352         u32 mii_speed;
 353
 354         if (!ag->link) {
 355                 netif_carrier_off(ag->dev);
 356                 if (netif_msg_link(ag))
 357                         printk(KERN_INFO "%s: link down\n", ag->dev->name);
 358                 return;
 359         }
 360
 361         cfg2 = ag71xx_rr(ag, AG71XX_REG_MAC_CFG2);
 362         cfg2 &= ~(MAC_CFG2_IF_1000 | MAC_CFG2_IF_10_100 | MAC_CFG2_FDX);
 363         cfg2 |= (ag->duplex) ? MAC_CFG2_FDX : 0;
 364
 365         ifctl = ag71xx_rr(ag, AG71XX_REG_MAC_IFCTL);
 366         ifctl &= ~(MAC_IFCTL_SPEED);
 367
 368         fifo5 = ag71xx_rr(ag, AG71XX_REG_FIFO_CFG5);
 369         fifo5 &= ~FIFO_CFG5_BM;
 370
 371         switch (ag->speed) {
 372         case SPEED_1000:
 373                 mii_speed =  MII_CTRL_SPEED_1000;
 374                 cfg2 |= MAC_CFG2_IF_1000;
 375                 fifo5 |= FIFO_CFG5_BM;
 376                 break;
 377         case SPEED_100:
 378                 mii_speed = MII_CTRL_SPEED_100;
 379                 cfg2 |= MAC_CFG2_IF_10_100;
 380                 ifctl |= MAC_IFCTL_SPEED;
 381                 break;
 382         case SPEED_10:
 383                 mii_speed = MII_CTRL_SPEED_10;
 384                 cfg2 |= MAC_CFG2_IF_10_100;
 385                 break;
 386         default:
 387                 BUG();
 388                 return;
 389         }
 390
 391         if (pdata->is_ar91xx)
 392                 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG3, 0x00780fff);
 393         else if (pdata->is_ar724x)
 394                 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG3, pdata->fifo_cfg3);
 395         else
 396                 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG3, 0x008001ff);
 397
 398         if (pdata->set_pll)
 399                 pdata->set_pll(ag->speed);
 400
 401         ag71xx_mii_ctrl_set_speed(ag, mii_speed);
 402
 403         ag71xx_wr(ag, AG71XX_REG_MAC_CFG2, cfg2);
 404         ag71xx_wr(ag, AG71XX_REG_FIFO_CFG5, fifo5);
 405         ag71xx_wr(ag, AG71XX_REG_MAC_IFCTL, ifctl);
 406
 407         netif_carrier_on(ag->dev);
 408         if (netif_msg_link(ag))
 409                 printk(KERN_INFO "%s: link up (%sMbps/%s duplex)\n",
 410                         ag->dev->name,
 411                         ag71xx_speed_str(ag),
 412                         (DUPLEX_FULL == ag->duplex) ? "Full" : "Half");
 413
 414         DBG("%s: fifo_cfg0=%#x, fifo_cfg1=%#x, fifo_cfg2=%#x\n",
 415                 ag->dev->name,
 416                 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG0),
 417                 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG1),
 418                 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG2));
 419
 420         DBG("%s: fifo_cfg3=%#x, fifo_cfg4=%#x, fifo_cfg5=%#x\n",
 421                 ag->dev->name,
 422                 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG3),
 423                 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG4),
 424                 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG5));
 425
 426         DBG("%s: mac_cfg2=%#x, mac_ifctl=%#x, mii_ctrl=%#x\n",
 427                 ag->dev->name,
 428                 ag71xx_rr(ag, AG71XX_REG_MAC_CFG2),
 429                 ag71xx_rr(ag, AG71XX_REG_MAC_IFCTL),
 430                 ag71xx_mii_ctrl_rr(ag));
 431 }
 432
 433 static void ag71xx_hw_set_macaddr(struct ag71xx *ag, unsigned char *mac)
 434 {
 435         u32 t;
 436
 437         t = (((u32) mac[5]) << 24) | (((u32) mac[4]) << 16)
 438           | (((u32) mac[3]) << 8) | ((u32) mac[2]);
 439
 440         ag71xx_wr(ag, AG71XX_REG_MAC_ADDR1, t);
 441
 442         t = (((u32) mac[1]) << 24) | (((u32) mac[0]) << 16);
 443         ag71xx_wr(ag, AG71XX_REG_MAC_ADDR2, t);
 444 }
 445
 446 static void ag71xx_dma_reset(struct ag71xx *ag)
 447 {
 448         u32 val;
 449         int i;
 450
 451         ag71xx_dump_dma_regs(ag);
 452
 453         /* stop RX and TX */
 454         ag71xx_wr(ag, AG71XX_REG_RX_CTRL, 0);
 455         ag71xx_wr(ag, AG71XX_REG_TX_CTRL, 0);
 456
 457         /*
 458          * give the hardware some time to really stop all rx/tx activity
 459          * clearing the descriptors too early causes random memory corruption
 460          */
 461         mdelay(1);
 462
 463         /* clear descriptor addresses */
 464         ag71xx_wr(ag, AG71XX_REG_TX_DESC, 0);
 465         ag71xx_wr(ag, AG71XX_REG_RX_DESC, 0);
 466
 467         /* clear pending RX/TX interrupts */
 468         for (i = 0; i < 256; i++) {
 469                 ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_PR);
 470                 ag71xx_wr(ag, AG71XX_REG_TX_STATUS, TX_STATUS_PS);
 471         }
 472
 473         /* clear pending errors */
 474         ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_BE | RX_STATUS_OF);
 475         ag71xx_wr(ag, AG71XX_REG_TX_STATUS, TX_STATUS_BE | TX_STATUS_UR);
 476
 477         val = ag71xx_rr(ag, AG71XX_REG_RX_STATUS);
 478         if (val)
 479                 printk(KERN_ALERT "%s: unable to clear DMA Rx status: %08x\n",
 480                         ag->dev->name, val);
 481
 482         val = ag71xx_rr(ag, AG71XX_REG_TX_STATUS);
 483
 484         /* mask out reserved bits */
 485         val &= ~0xff000000;
 486
 487         if (val)
 488                 printk(KERN_ALERT "%s: unable to clear DMA Tx status: %08x\n",
 489                         ag->dev->name, val);
 490
 491         ag71xx_dump_dma_regs(ag);
 492 }
 493
 494 #define MAC_CFG1_INIT   (MAC_CFG1_RXE | MAC_CFG1_TXE | \
 495                          MAC_CFG1_SRX | MAC_CFG1_STX)
 496
 497 #define FIFO_CFG0_INIT  (FIFO_CFG0_ALL << FIFO_CFG0_ENABLE_SHIFT)
 498
 499 #define FIFO_CFG4_INIT  (FIFO_CFG4_DE | FIFO_CFG4_DV | FIFO_CFG4_FC | \
 500                          FIFO_CFG4_CE | FIFO_CFG4_CR | FIFO_CFG4_LM | \
 501                          FIFO_CFG4_LO | FIFO_CFG4_OK | FIFO_CFG4_MC | \
 502                          FIFO_CFG4_BC | FIFO_CFG4_DR | FIFO_CFG4_LE | \
 503                          FIFO_CFG4_CF | FIFO_CFG4_PF | FIFO_CFG4_UO | \
 504                          FIFO_CFG4_VT)
 505
 506 #define FIFO_CFG5_INIT  (FIFO_CFG5_DE | FIFO_CFG5_DV | FIFO_CFG5_FC | \
 507                          FIFO_CFG5_CE | FIFO_CFG5_LO | FIFO_CFG5_OK | \
 508                          FIFO_CFG5_MC | FIFO_CFG5_BC | FIFO_CFG5_DR | \
 509                          FIFO_CFG5_CF | FIFO_CFG5_PF | FIFO_CFG5_VT | \
 510                          FIFO_CFG5_LE | FIFO_CFG5_FT | FIFO_CFG5_16 | \
 511                          FIFO_CFG5_17 | FIFO_CFG5_SF)
 512
 513 static void ag71xx_hw_init(struct ag71xx *ag)
 514 {
 515         struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag);
 516
 517         ag71xx_sb(ag, AG71XX_REG_MAC_CFG1, MAC_CFG1_SR);
 518         udelay(20);
 519
 520         ar71xx_device_stop(pdata->reset_bit);
 521         mdelay(100);
 522         ar71xx_device_start(pdata->reset_bit);
 523         mdelay(100);
 524
 525         /* setup MAC configuration registers */
 526         if (pdata->is_ar724x)
 527                 ag71xx_wr(ag, AG71XX_REG_MAC_CFG1,
 528                           MAC_CFG1_INIT | MAC_CFG1_TFC | MAC_CFG1_RFC);
 529         else
 530                 ag71xx_wr(ag, AG71XX_REG_MAC_CFG1, MAC_CFG1_INIT);
 531
 532         ag71xx_sb(ag, AG71XX_REG_MAC_CFG2,
 533                   MAC_CFG2_PAD_CRC_EN | MAC_CFG2_LEN_CHECK);
 534
 535         /* setup max frame length */
 536         ag71xx_wr(ag, AG71XX_REG_MAC_MFL, AG71XX_TX_MTU_LEN);
 537
 538         /* setup MII interface type */
 539         ag71xx_mii_ctrl_set_if(ag, pdata->mii_if);
 540
 541         /* setup FIFO configuration registers */
 542         ag71xx_wr(ag, AG71XX_REG_FIFO_CFG0, FIFO_CFG0_INIT);
 543         if (pdata->is_ar724x) {
 544                 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG1, pdata->fifo_cfg1);
 545                 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG2, pdata->fifo_cfg2);
 546         } else {
 547                 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG1, 0x0fff0000);
 548                 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG2, 0x00001fff);
 549         }
 550         ag71xx_wr(ag, AG71XX_REG_FIFO_CFG4, FIFO_CFG4_INIT);
 551         ag71xx_wr(ag, AG71XX_REG_FIFO_CFG5, FIFO_CFG5_INIT);
 552
 553         ag71xx_dma_reset(ag);
 554 }
 555
 556 static void ag71xx_hw_start(struct ag71xx *ag)
 557 {
 558         /* start RX engine */
 559         ag71xx_wr(ag, AG71XX_REG_RX_CTRL, RX_CTRL_RXE);
 560
 561         /* enable interrupts */
 562         ag71xx_wr(ag, AG71XX_REG_INT_ENABLE, AG71XX_INT_INIT);
 563 }
 564
 565 static void ag71xx_hw_stop(struct ag71xx *ag)
 566 {
 567         /* disable all interrupts */
 568         ag71xx_wr(ag, AG71XX_REG_INT_ENABLE, 0);
 569
 570         ag71xx_dma_reset(ag);
 571 }
 572
 573 static int ag71xx_open(struct net_device *dev)
 574 {
 575         struct ag71xx *ag = netdev_priv(dev);
 576         struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag);
 577         int ret;
 578
 579         ret = ag71xx_rings_init(ag);
 580         if (ret)
 581                 goto err;
 582
 583         if (pdata->is_ar724x)
 584                 ag71xx_hw_init(ag);
 585
 586         napi_enable(&ag->napi);
 587
 588         netif_carrier_off(dev);
 589         ag71xx_phy_start(ag);
 590
 591         ag71xx_wr(ag, AG71XX_REG_TX_DESC, ag->tx_ring.descs_dma);
 592         ag71xx_wr(ag, AG71XX_REG_RX_DESC, ag->rx_ring.descs_dma);
 593
 594         ag71xx_hw_set_macaddr(ag, dev->dev_addr);
 595
 596         ag71xx_hw_start(ag);
 597
 598         netif_start_queue(dev);
 599
 600         return 0;
 601
 602  err:
 603         ag71xx_rings_cleanup(ag);
 604         return ret;
 605 }
 606
 607 static int ag71xx_stop(struct net_device *dev)
 608 {
 609         struct ag71xx *ag = netdev_priv(dev);
 610         unsigned long flags;
 611
 612         netif_carrier_off(dev);
 613         ag71xx_phy_stop(ag);
 614
 615         spin_lock_irqsave(&ag->lock, flags);
 616
 617         netif_stop_queue(dev);
 618
 619         ag71xx_hw_stop(ag);
 620
 621         napi_disable(&ag->napi);
 622         del_timer_sync(&ag->oom_timer);
 623
 624         spin_unlock_irqrestore(&ag->lock, flags);
 625
 626         ag71xx_rings_cleanup(ag);
 627
 628         return 0;
 629 }
 630
 631 static netdev_tx_t ag71xx_hard_start_xmit(struct sk_buff *skb,
 632                                           struct net_device *dev)
 633 {
 634         struct ag71xx *ag = netdev_priv(dev);
 635         struct ag71xx_ring *ring = &ag->tx_ring;
 636         struct ag71xx_desc *desc;
 637         dma_addr_t dma_addr;
 638         int i;
 639
 640         i = ring->curr % AG71XX_TX_RING_SIZE;
 641         desc = ring->buf[i].desc;
 642
 643         if (!ag71xx_desc_empty(desc))
 644                 goto err_drop;
 645
 646         if (ag71xx_has_ar8216(ag))
 647                 ag71xx_add_ar8216_header(ag, skb);
 648
 649         if (skb->len <= 0) {
 650                 DBG("%s: packet len is too small\n", ag->dev->name);
 651                 goto err_drop;
 652         }
 653
 654         dma_addr = dma_map_single(&dev->dev, skb->data, skb->len,
 655                                   DMA_TO_DEVICE);
 656
 657         ring->buf[i].skb = skb;
 658
 659         /* setup descriptor fields */
 660         desc->data = (u32) dma_addr;
 661         desc->ctrl = (skb->len & DESC_PKTLEN_M);
 662
 663         /* flush descriptor */
 664         wmb();
 665
 666         ring->curr++;
 667         if (ring->curr == (ring->dirty + AG71XX_TX_THRES_STOP)) {
 668                 DBG("%s: tx queue full\n", ag->dev->name);
 669                 netif_stop_queue(dev);
 670         }
 671
 672         DBG("%s: packet injected into TX queue\n", ag->dev->name);
 673
 674         /* enable TX engine */
 675         ag71xx_wr(ag, AG71XX_REG_TX_CTRL, TX_CTRL_TXE);
 676
 677         return NETDEV_TX_OK;
 678
 679  err_drop:
 680         dev->stats.tx_dropped++;
 681
 682         dev_kfree_skb(skb);
 683         return NETDEV_TX_OK;
 684 }
 685
 686 static int ag71xx_do_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
 687 {
 688         struct ag71xx *ag = netdev_priv(dev);
 689         int ret;
 690
 691         switch (cmd) {
 692         case SIOCETHTOOL:
 693                 if (ag->phy_dev == NULL)
 694                         break;
 695
 696                 spin_lock_irq(&ag->lock);
 697                 ret = phy_ethtool_ioctl(ag->phy_dev, (void *) ifr->ifr_data);
 698                 spin_unlock_irq(&ag->lock);
 699                 return ret;
 700
 701         case SIOCSIFHWADDR:
 702                 if (copy_from_user
 703                         (dev->dev_addr, ifr->ifr_data, sizeof(dev->dev_addr)))
 704                         return -EFAULT;
 705                 return 0;
 706
 707         case SIOCGIFHWADDR:
 708                 if (copy_to_user
 709                         (ifr->ifr_data, dev->dev_addr, sizeof(dev->dev_addr)))
 710                         return -EFAULT;
 711                 return 0;
 712
 713         case SIOCGMIIPHY:
 714         case SIOCGMIIREG:
 715         case SIOCSMIIREG:
 716                 if (ag->phy_dev == NULL)
 717                         break;
 718
 719                 return phy_mii_ioctl(ag->phy_dev, ifr, cmd);
 720
 721         default:
 722                 break;
 723         }
 724
 725         return -EOPNOTSUPP;
 726 }
 727
 728 static void ag71xx_oom_timer_handler(unsigned long data)
 729 {
 730         struct net_device *dev = (struct net_device *) data;
 731         struct ag71xx *ag = netdev_priv(dev);
 732
 733         napi_schedule(&ag->napi);
 734 }
 735
 736 static void ag71xx_tx_timeout(struct net_device *dev)
 737 {
 738         struct ag71xx *ag = netdev_priv(dev);
 739
 740         if (netif_msg_tx_err(ag))
 741                 printk(KERN_DEBUG "%s: tx timeout\n", ag->dev->name);
 742
 743         schedule_work(&ag->restart_work);
 744 }
 745
 746 static void ag71xx_restart_work_func(struct work_struct *work)
 747 {
 748         struct ag71xx *ag = container_of(work, struct ag71xx, restart_work);
 749
 750         ag71xx_stop(ag->dev);
 751         ag71xx_open(ag->dev);
 752 }
 753
 754 static int ag71xx_tx_packets(struct ag71xx *ag)
 755 {
 756         struct ag71xx_ring *ring = &ag->tx_ring;
 757         int sent;
 758
 759         DBG("%s: processing TX ring\n", ag->dev->name);
 760
 761         sent = 0;
 762         while (ring->dirty != ring->curr) {
 763                 unsigned int i = ring->dirty % AG71XX_TX_RING_SIZE;
 764                 struct ag71xx_desc *desc = ring->buf[i].desc;
 765                 struct sk_buff *skb = ring->buf[i].skb;
 766
 767                 if (!ag71xx_desc_empty(desc))
 768                         break;
 769
 770                 ag71xx_wr(ag, AG71XX_REG_TX_STATUS, TX_STATUS_PS);
 771
 772                 ag->dev->stats.tx_bytes += skb->len;
 773                 ag->dev->stats.tx_packets++;
 774
 775                 dev_kfree_skb_any(skb);
 776                 ring->buf[i].skb = NULL;
 777
 778                 ring->dirty++;
 779                 sent++;
 780         }
 781
 782         DBG("%s: %d packets sent out\n", ag->dev->name, sent);
 783
 784         if ((ring->curr - ring->dirty) < AG71XX_TX_THRES_WAKEUP)
 785                 netif_wake_queue(ag->dev);
 786
 787         return sent;
 788 }
 789
 790 static int ag71xx_rx_packets(struct ag71xx *ag, int limit)
 791 {
 792         struct net_device *dev = ag->dev;
 793         struct ag71xx_ring *ring = &ag->rx_ring;
 794         int done = 0;
 795
 796         DBG("%s: rx packets, limit=%d, curr=%u, dirty=%u\n",
 797                         dev->name, limit, ring->curr, ring->dirty);
 798
 799         while (done < limit) {
 800                 unsigned int i = ring->curr % AG71XX_RX_RING_SIZE;
 801                 struct ag71xx_desc *desc = ring->buf[i].desc;
 802                 struct sk_buff *skb;
 803                 int pktlen;
 804                 int err = 0;
 805
 806                 if (ag71xx_desc_empty(desc))
 807                         break;
 808
 809                 if ((ring->dirty + AG71XX_RX_RING_SIZE) == ring->curr) {
 810                         ag71xx_assert(0);
 811                         break;
 812                 }
 813
 814                 ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_PR);
 815
 816                 skb = ring->buf[i].skb;
 817                 pktlen = ag71xx_desc_pktlen(desc);
 818                 pktlen -= ETH_FCS_LEN;
 819
 820                 dma_unmap_single(&dev->dev, ring->buf[i].dma_addr,
 821                                  AG71XX_RX_PKT_SIZE, DMA_FROM_DEVICE);
 822
 823                 dev->last_rx = jiffies;
 824                 dev->stats.rx_packets++;
 825                 dev->stats.rx_bytes += pktlen;
 826
 827                 skb_put(skb, pktlen);
 828                 if (ag71xx_has_ar8216(ag))
 829                         err = ag71xx_remove_ar8216_header(ag, skb, pktlen);
 830
 831                 if (err) {
 832                         dev->stats.rx_dropped++;
 833                         kfree_skb(skb);
 834                 } else {
 835                         skb->dev = dev;
 836                         skb->ip_summed = CHECKSUM_NONE;
 837                         if (ag->phy_dev) {
 838                                 ag->phy_dev->netif_receive_skb(skb);
 839                         } else {
 840                                 skb->protocol = eth_type_trans(skb, dev);
 841                                 netif_receive_skb(skb);
 842                         }
 843                 }
 844
 845                 ring->buf[i].skb = NULL;
 846                 done++;
 847
 848                 ring->curr++;
 849         }
 850
 851         ag71xx_ring_rx_refill(ag);
 852
 853         DBG("%s: rx finish, curr=%u, dirty=%u, done=%d\n",
 854                 dev->name, ring->curr, ring->dirty, done);
 855
 856         return done;
 857 }
 858
 859 static int ag71xx_poll(struct napi_struct *napi, int limit)
 860 {
 861         struct ag71xx *ag = container_of(napi, struct ag71xx, napi);
 862         struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag);
 863         struct net_device *dev = ag->dev;
 864         struct ag71xx_ring *rx_ring;
 865         unsigned long flags;
 866         u32 status;
 867         int tx_done;
 868         int rx_done;
 869
 870         pdata->ddr_flush();
 871         tx_done = ag71xx_tx_packets(ag);
 872
 873         DBG("%s: processing RX ring\n", dev->name);
 874         rx_done = ag71xx_rx_packets(ag, limit);
 875
 876         ag71xx_debugfs_update_napi_stats(ag, rx_done, tx_done);
 877
 878         rx_ring = &ag->rx_ring;
 879         if (rx_ring->buf[rx_ring->dirty % AG71XX_RX_RING_SIZE].skb == NULL)
 880                 goto oom;
 881
 882         status = ag71xx_rr(ag, AG71XX_REG_RX_STATUS);
 883         if (unlikely(status & RX_STATUS_OF)) {
 884                 ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_OF);
 885                 dev->stats.rx_fifo_errors++;
 886
 887                 /* restart RX */
 888                 ag71xx_wr(ag, AG71XX_REG_RX_CTRL, RX_CTRL_RXE);
 889         }
 890
 891         if (rx_done < limit) {
 892                 if (status & RX_STATUS_PR)
 893                         goto more;
 894
 895                 status = ag71xx_rr(ag, AG71XX_REG_TX_STATUS);
 896                 if (status & TX_STATUS_PS)
 897                         goto more;
 898
 899                 DBG("%s: disable polling mode, rx=%d, tx=%d,limit=%d\n",
 900                         dev->name, rx_done, tx_done, limit);
 901
 902                 napi_complete(napi);
 903
 904                 /* enable interrupts */
 905                 spin_lock_irqsave(&ag->lock, flags);
 906                 ag71xx_int_enable(ag, AG71XX_INT_POLL);
 907                 spin_unlock_irqrestore(&ag->lock, flags);
 908                 return rx_done;
 909         }
 910
 911  more:
 912         DBG("%s: stay in polling mode, rx=%d, tx=%d, limit=%d\n",
 913                         dev->name, rx_done, tx_done, limit);
 914         return rx_done;
 915
 916  oom:
 917         if (netif_msg_rx_err(ag))
 918                 printk(KERN_DEBUG "%s: out of memory\n", dev->name);
 919
 920         mod_timer(&ag->oom_timer, jiffies + AG71XX_OOM_REFILL);
 921         napi_complete(napi);
 922         return 0;
 923 }
 924
 925 static irqreturn_t ag71xx_interrupt(int irq, void *dev_id)
 926 {
 927         struct net_device *dev = dev_id;
 928         struct ag71xx *ag = netdev_priv(dev);
 929         u32 status;
 930
 931         status = ag71xx_rr(ag, AG71XX_REG_INT_STATUS);
 932         ag71xx_dump_intr(ag, "raw", status);
 933
 934         if (unlikely(!status))
 935                 return IRQ_NONE;
 936
 937         if (unlikely(status & AG71XX_INT_ERR)) {
 938                 if (status & AG71XX_INT_TX_BE) {
 939                         ag71xx_wr(ag, AG71XX_REG_TX_STATUS, TX_STATUS_BE);
 940                         dev_err(&dev->dev, "TX BUS error\n");
 941                 }
 942                 if (status & AG71XX_INT_RX_BE) {
 943                         ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_BE);
 944                         dev_err(&dev->dev, "RX BUS error\n");
 945                 }
 946         }
 947
 948         if (likely(status & AG71XX_INT_POLL)) {
 949                 ag71xx_int_disable(ag, AG71XX_INT_POLL);
 950                 DBG("%s: enable polling mode\n", dev->name);
 951                 napi_schedule(&ag->napi);
 952         }
 953
 954         ag71xx_debugfs_update_int_stats(ag, status);
 955
 956         return IRQ_HANDLED;
 957 }
 958
 959 static void ag71xx_set_multicast_list(struct net_device *dev)
 960 {
 961         /* TODO */
 962 }
 963
 964 #ifdef CONFIG_NET_POLL_CONTROLLER
 965 /*
 966  * Polling 'interrupt' - used by things like netconsole to send skbs
 967  * without having to re-enable interrupts. It's not called while
 968  * the interrupt routine is executing.
 969  */
 970 static void ag71xx_netpoll(struct net_device *dev)
 971 {
 972         disable_irq(dev->irq);
 973         ag71xx_interrupt(dev->irq, dev);
 974         enable_irq(dev->irq);
 975 }
 976 #endif
 977
 978 static const struct net_device_ops ag71xx_netdev_ops = {
 979         .ndo_open               = ag71xx_open,
 980         .ndo_stop               = ag71xx_stop,
 981         .ndo_start_xmit         = ag71xx_hard_start_xmit,
 982         .ndo_set_multicast_list = ag71xx_set_multicast_list,
 983         .ndo_do_ioctl           = ag71xx_do_ioctl,
 984         .ndo_tx_timeout         = ag71xx_tx_timeout,
 985         .ndo_change_mtu         = eth_change_mtu,
 986         .ndo_set_mac_address    = eth_mac_addr,
 987         .ndo_validate_addr      = eth_validate_addr,
 988 #ifdef CONFIG_NET_POLL_CONTROLLER
 989         .ndo_poll_controller    = ag71xx_netpoll,
 990 #endif
 991 };
 992
 993 static int __devinit ag71xx_probe(struct platform_device *pdev)
 994 {
 995         struct net_device *dev;
 996         struct resource *res;
 997         struct ag71xx *ag;
 998         struct ag71xx_platform_data *pdata;
 999         int err;
1000
1001         pdata = pdev->dev.platform_data;
1002         if (!pdata) {
1003                 dev_err(&pdev->dev, "no platform data specified\n");
1004                 err = -ENXIO;
1005                 goto err_out;
1006         }
1007
1008         if (pdata->mii_bus_dev == NULL) {
1009                 dev_err(&pdev->dev, "no MII bus device specified\n");
1010                 err = -EINVAL;
1011                 goto err_out;
1012         }
1013
1014         dev = alloc_etherdev(sizeof(*ag));
1015         if (!dev) {
1016                 dev_err(&pdev->dev, "alloc_etherdev failed\n");
1017                 err = -ENOMEM;
1018                 goto err_out;
1019         }
1020
1021         SET_NETDEV_DEV(dev, &pdev->dev);
1022
1023         ag = netdev_priv(dev);
1024         ag->pdev = pdev;
1025         ag->dev = dev;
1026         ag->msg_enable = netif_msg_init(ag71xx_msg_level,
1027                                         AG71XX_DEFAULT_MSG_ENABLE);
1028         spin_lock_init(&ag->lock);
1029
1030         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mac_base");
1031         if (!res) {
1032                 dev_err(&pdev->dev, "no mac_base resource found\n");
1033                 err = -ENXIO;
1034                 goto err_out;
1035         }
1036
1037         ag->mac_base = ioremap_nocache(res->start, res->end - res->start + 1);
1038         if (!ag->mac_base) {
1039                 dev_err(&pdev->dev, "unable to ioremap mac_base\n");
1040                 err = -ENOMEM;
1041                 goto err_free_dev;
1042         }
1043
1044         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mii_ctrl");
1045         if (!res) {
1046                 dev_err(&pdev->dev, "no mii_ctrl resource found\n");
1047                 err = -ENXIO;
1048                 goto err_unmap_base;
1049         }
1050
1051         ag->mii_ctrl = ioremap_nocache(res->start, res->end - res->start + 1);
1052         if (!ag->mii_ctrl) {
1053                 dev_err(&pdev->dev, "unable to ioremap mii_ctrl\n");
1054                 err = -ENOMEM;
1055                 goto err_unmap_base;
1056         }
1057
1058         dev->irq = platform_get_irq(pdev, 0);
1059         err = request_irq(dev->irq, ag71xx_interrupt,
1060                           IRQF_DISABLED | IRQF_SAMPLE_RANDOM,
1061                           dev->name, dev);
1062         if (err) {
1063                 dev_err(&pdev->dev, "unable to request IRQ %d\n", dev->irq);
1064                 goto err_unmap_mii_ctrl;
1065         }
1066
1067         dev->base_addr = (unsigned long)ag->mac_base;
1068         dev->netdev_ops = &ag71xx_netdev_ops;
1069         dev->ethtool_ops = &ag71xx_ethtool_ops;
1070
1071         INIT_WORK(&ag->restart_work, ag71xx_restart_work_func);
1072
1073         init_timer(&ag->oom_timer);
1074         ag->oom_timer.data = (unsigned long) dev;
1075         ag->oom_timer.function = ag71xx_oom_timer_handler;
1076
1077         memcpy(dev->dev_addr, pdata->mac_addr, ETH_ALEN);
1078
1079         netif_napi_add(dev, &ag->napi, ag71xx_poll, AG71XX_NAPI_WEIGHT);
1080
1081         err = register_netdev(dev);
1082         if (err) {
1083                 dev_err(&pdev->dev, "unable to register net device\n");
1084                 goto err_free_irq;
1085         }
1086
1087         printk(KERN_INFO "%s: Atheros AG71xx at 0x%08lx, irq %d\n",
1088                dev->name, dev->base_addr, dev->irq);
1089
1090         ag71xx_dump_regs(ag);
1091
1092         ag71xx_hw_init(ag);
1093
1094         ag71xx_dump_regs(ag);
1095
1096         err = ag71xx_phy_connect(ag);
1097         if (err)
1098                 goto err_unregister_netdev;
1099
1100         err = ag71xx_debugfs_init(ag);
1101         if (err)
1102                 goto err_phy_disconnect;
1103
1104         platform_set_drvdata(pdev, dev);
1105
1106         return 0;
1107
1108  err_phy_disconnect:
1109         ag71xx_phy_disconnect(ag);
1110  err_unregister_netdev:
1111         unregister_netdev(dev);
1112  err_free_irq:
1113         free_irq(dev->irq, dev);
1114  err_unmap_mii_ctrl:
1115         iounmap(ag->mii_ctrl);
1116  err_unmap_base:
1117         iounmap(ag->mac_base);
1118  err_free_dev:
1119         kfree(dev);
1120  err_out:
1121         platform_set_drvdata(pdev, NULL);
1122         return err;
1123 }
1124
1125 static int __devexit ag71xx_remove(struct platform_device *pdev)
1126 {
1127         struct net_device *dev = platform_get_drvdata(pdev);
1128
1129         if (dev) {
1130                 struct ag71xx *ag = netdev_priv(dev);
1131
1132                 ag71xx_debugfs_exit(ag);
1133                 ag71xx_phy_disconnect(ag);
1134                 unregister_netdev(dev);
1135                 free_irq(dev->irq, dev);
1136                 iounmap(ag->mii_ctrl);
1137                 iounmap(ag->mac_base);
1138                 kfree(dev);
1139                 platform_set_drvdata(pdev, NULL);
1140         }
1141
1142         return 0;
1143 }
1144
1145 static struct platform_driver ag71xx_driver = {
1146         .probe          = ag71xx_probe,
1147         .remove         = __exit_p(ag71xx_remove),
1148         .driver = {
1149                 .name   = AG71XX_DRV_NAME,
1150         }
1151 };
1152
1153 static int __init ag71xx_module_init(void)
1154 {
1155         int ret;
1156
1157         ret = ag71xx_debugfs_root_init();
1158         if (ret)
1159                 goto err_out;
1160
1161         ret = ag71xx_mdio_driver_init();
1162         if (ret)
1163                 goto err_debugfs_exit;
1164
1165         ret = platform_driver_register(&ag71xx_driver);
1166         if (ret)
1167                 goto err_mdio_exit;
1168
1169         return 0;
1170
1171  err_mdio_exit:
1172         ag71xx_mdio_driver_exit();
1173  err_debugfs_exit:
1174         ag71xx_debugfs_root_exit();
1175  err_out:
1176         return ret;
1177 }
1178
1179 static void __exit ag71xx_module_exit(void)
1180 {
1181         platform_driver_unregister(&ag71xx_driver);
1182         ag71xx_mdio_driver_exit();
1183         ag71xx_debugfs_root_exit();
1184 }
1185
1186 module_init(ag71xx_module_init);
1187 module_exit(ag71xx_module_exit);
1188
1189 MODULE_VERSION(AG71XX_DRV_VERSION);
1190 MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org>");
1191 MODULE_AUTHOR("Imre Kaloz <kaloz@openwrt.org>");
1192 MODULE_LICENSE("GPL v2");
1193 MODULE_ALIAS("platform:" AG71XX_DRV_NAME);