target/linux/sunxi/patches-3.14/140-dt-sunxi-convert-to-new-clock-compats.patch

   1 From 46b2ee17d7321149b4d48dd86ee2e346624aa141 Mon Sep 17 00:00:00 2001
   2 From: Maxime Ripard <maxime.ripard@free-electrons.com>
   3 Date: Thu, 6 Feb 2014 09:55:58 +0100
   4 Subject: [PATCH] ARM: sunxi: dt: Convert to the new clock compatibles
   5
   6 Switch the device tree to the new compatibles introduced in the clock drivers
   7 to have a common pattern accross all Allwinner SoCs.
   8
   9 Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
  10 ---
  11  arch/arm/boot/dts/sun4i-a10.dtsi  | 60 +++++++++++++++++++--------------------
  12  arch/arm/boot/dts/sun5i-a10s.dtsi | 48 +++++++++++++++----------------
  13  arch/arm/boot/dts/sun5i-a13.dtsi  | 48 +++++++++++++++----------------
  14  arch/arm/boot/dts/sun6i-a31.dtsi  | 10 +++----
  15  arch/arm/boot/dts/sun7i-a20.dtsi  | 54 +++++++++++++++++------------------
  16  5 files changed, 110 insertions(+), 110 deletions(-)
  17
  18 --- a/arch/arm/boot/dts/sun4i-a10.dtsi
  19 +++ b/arch/arm/boot/dts/sun4i-a10.dtsi
  20 @@ -60,7 +60,7 @@
  21
  22                 osc24M: clk@01c20050 {
  23                         #clock-cells = <0>;
  24 -                       compatible = "allwinner,sun4i-osc-clk";
  25 +                       compatible = "allwinner,sun4i-a10-osc-clk";
  26                         reg = <0x01c20050 0x4>;
  27                         clock-frequency = <24000000>;
  28                         clock-output-names = "osc24M";
  29 @@ -75,7 +75,7 @@
  30
  31                 pll1: clk@01c20000 {
  32                         #clock-cells = <0>;
  33 -                       compatible = "allwinner,sun4i-pll1-clk";
  34 +                       compatible = "allwinner,sun4i-a10-pll1-clk";
  35                         reg = <0x01c20000 0x4>;
  36                         clocks = <&osc24M>;
  37                         clock-output-names = "pll1";
  38 @@ -83,7 +83,7 @@
  39
  40                 pll4: clk@01c20018 {
  41                         #clock-cells = <0>;
  42 -                       compatible = "allwinner,sun4i-pll1-clk";
  43 +                       compatible = "allwinner,sun4i-a10-pll1-clk";
  44                         reg = <0x01c20018 0x4>;
  45                         clocks = <&osc24M>;
  46                         clock-output-names = "pll4";
  47 @@ -91,7 +91,7 @@
  48
  49                 pll5: clk@01c20020 {
  50                         #clock-cells = <1>;
  51 -                       compatible = "allwinner,sun4i-pll5-clk";
  52 +                       compatible = "allwinner,sun4i-a10-pll5-clk";
  53                         reg = <0x01c20020 0x4>;
  54                         clocks = <&osc24M>;
  55                         clock-output-names = "pll5_ddr", "pll5_other";
  56 @@ -99,7 +99,7 @@
  57
  58                 pll6: clk@01c20028 {
  59                         #clock-cells = <1>;
  60 -                       compatible = "allwinner,sun4i-pll6-clk";
  61 +                       compatible = "allwinner,sun4i-a10-pll6-clk";
  62                         reg = <0x01c20028 0x4>;
  63                         clocks = <&osc24M>;
  64                         clock-output-names = "pll6_sata", "pll6_other", "pll6";
  65 @@ -108,7 +108,7 @@
  66                 /* dummy is 200M */
  67                 cpu: cpu@01c20054 {
  68                         #clock-cells = <0>;
  69 -                       compatible = "allwinner,sun4i-cpu-clk";
  70 +                       compatible = "allwinner,sun4i-a10-cpu-clk";
  71                         reg = <0x01c20054 0x4>;
  72                         clocks = <&osc32k>, <&osc24M>, <&pll1>, <&dummy>;
  73                         clock-output-names = "cpu";
  74 @@ -116,7 +116,7 @@
  75
  76                 axi: axi@01c20054 {
  77                         #clock-cells = <0>;
  78 -                       compatible = "allwinner,sun4i-axi-clk";
  79 +                       compatible = "allwinner,sun4i-a10-axi-clk";
  80                         reg = <0x01c20054 0x4>;
  81                         clocks = <&cpu>;
  82                         clock-output-names = "axi";
  83 @@ -124,7 +124,7 @@
  84
  85                 axi_gates: clk@01c2005c {
  86                         #clock-cells = <1>;
  87 -                       compatible = "allwinner,sun4i-axi-gates-clk";
  88 +                       compatible = "allwinner,sun4i-a10-axi-gates-clk";
  89                         reg = <0x01c2005c 0x4>;
  90                         clocks = <&axi>;
  91                         clock-output-names = "axi_dram";
  92 @@ -132,7 +132,7 @@
  93
  94                 ahb: ahb@01c20054 {
  95                         #clock-cells = <0>;
  96 -                       compatible = "allwinner,sun4i-ahb-clk";
  97 +                       compatible = "allwinner,sun4i-a10-ahb-clk";
  98                         reg = <0x01c20054 0x4>;
  99                         clocks = <&axi>;
 100                         clock-output-names = "ahb";
 101 @@ -140,7 +140,7 @@
 102
 103                 ahb_gates: clk@01c20060 {
 104                         #clock-cells = <1>;
 105 -                       compatible = "allwinner,sun4i-ahb-gates-clk";
 106 +                       compatible = "allwinner,sun4i-a10-ahb-gates-clk";
 107                         reg = <0x01c20060 0x8>;
 108                         clocks = <&ahb>;
 109                         clock-output-names = "ahb_usb0", "ahb_ehci0",
 110 @@ -158,7 +158,7 @@
 111
 112                 apb0: apb0@01c20054 {
 113                         #clock-cells = <0>;
 114 -                       compatible = "allwinner,sun4i-apb0-clk";
 115 +                       compatible = "allwinner,sun4i-a10-apb0-clk";
 116                         reg = <0x01c20054 0x4>;
 117                         clocks = <&ahb>;
 118                         clock-output-names = "apb0";
 119 @@ -166,7 +166,7 @@
 120
 121                 apb0_gates: clk@01c20068 {
 122                         #clock-cells = <1>;
 123 -                       compatible = "allwinner,sun4i-apb0-gates-clk";
 124 +                       compatible = "allwinner,sun4i-a10-apb0-gates-clk";
 125                         reg = <0x01c20068 0x4>;
 126                         clocks = <&apb0>;
 127                         clock-output-names = "apb0_codec", "apb0_spdif",
 128 @@ -176,7 +176,7 @@
 129
 130                 apb1_mux: apb1_mux@01c20058 {
 131                         #clock-cells = <0>;
 132 -                       compatible = "allwinner,sun4i-apb1-mux-clk";
 133 +                       compatible = "allwinner,sun4i-a10-apb1-mux-clk";
 134                         reg = <0x01c20058 0x4>;
 135                         clocks = <&osc24M>, <&pll6 1>, <&osc32k>;
 136                         clock-output-names = "apb1_mux";
 137 @@ -184,7 +184,7 @@
 138
 139                 apb1: apb1@01c20058 {
 140                         #clock-cells = <0>;
 141 -                       compatible = "allwinner,sun4i-apb1-clk";
 142 +                       compatible = "allwinner,sun4i-a10-apb1-clk";
 143                         reg = <0x01c20058 0x4>;
 144                         clocks = <&apb1_mux>;
 145                         clock-output-names = "apb1";
 146 @@ -192,7 +192,7 @@
 147
 148                 apb1_gates: clk@01c2006c {
 149                         #clock-cells = <1>;
 150 -                       compatible = "allwinner,sun4i-apb1-gates-clk";
 151 +                       compatible = "allwinner,sun4i-a10-apb1-gates-clk";
 152                         reg = <0x01c2006c 0x4>;
 153                         clocks = <&apb1>;
 154                         clock-output-names = "apb1_i2c0", "apb1_i2c1",
 155 @@ -205,7 +205,7 @@
 156
 157                 nand_clk: clk@01c20080 {
 158                         #clock-cells = <0>;
 159 -                       compatible = "allwinner,sun4i-mod0-clk";
 160 +                       compatible = "allwinner,sun4i-a10-mod0-clk";
 161                         reg = <0x01c20080 0x4>;
 162                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 163                         clock-output-names = "nand";
 164 @@ -213,7 +213,7 @@
 165
 166                 ms_clk: clk@01c20084 {
 167                         #clock-cells = <0>;
 168 -                       compatible = "allwinner,sun4i-mod0-clk";
 169 +                       compatible = "allwinner,sun4i-a10-mod0-clk";
 170                         reg = <0x01c20084 0x4>;
 171                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 172                         clock-output-names = "ms";
 173 @@ -221,7 +221,7 @@
 174
 175                 mmc0_clk: clk@01c20088 {
 176                         #clock-cells = <0>;
 177 -                       compatible = "allwinner,sun4i-mod0-clk";
 178 +                       compatible = "allwinner,sun4i-a10-mod0-clk";
 179                         reg = <0x01c20088 0x4>;
 180                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 181                         clock-output-names = "mmc0";
 182 @@ -229,7 +229,7 @@
 183
 184                 mmc1_clk: clk@01c2008c {
 185                         #clock-cells = <0>;
 186 -                       compatible = "allwinner,sun4i-mod0-clk";
 187 +                       compatible = "allwinner,sun4i-a10-mod0-clk";
 188                         reg = <0x01c2008c 0x4>;
 189                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 190                         clock-output-names = "mmc1";
 191 @@ -237,7 +237,7 @@
 192
 193                 mmc2_clk: clk@01c20090 {
 194                         #clock-cells = <0>;
 195 -                       compatible = "allwinner,sun4i-mod0-clk";
 196 +                       compatible = "allwinner,sun4i-a10-mod0-clk";
 197                         reg = <0x01c20090 0x4>;
 198                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 199                         clock-output-names = "mmc2";
 200 @@ -245,7 +245,7 @@
 201
 202                 mmc3_clk: clk@01c20094 {
 203                         #clock-cells = <0>;
 204 -                       compatible = "allwinner,sun4i-mod0-clk";
 205 +                       compatible = "allwinner,sun4i-a10-mod0-clk";
 206                         reg = <0x01c20094 0x4>;
 207                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 208                         clock-output-names = "mmc3";
 209 @@ -253,7 +253,7 @@
 210
 211                 ts_clk: clk@01c20098 {
 212                         #clock-cells = <0>;
 213 -                       compatible = "allwinner,sun4i-mod0-clk";
 214 +                       compatible = "allwinner,sun4i-a10-mod0-clk";
 215                         reg = <0x01c20098 0x4>;
 216                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 217                         clock-output-names = "ts";
 218 @@ -261,7 +261,7 @@
 219
 220                 ss_clk: clk@01c2009c {
 221                         #clock-cells = <0>;
 222 -                       compatible = "allwinner,sun4i-mod0-clk";
 223 +                       compatible = "allwinner,sun4i-a10-mod0-clk";
 224                         reg = <0x01c2009c 0x4>;
 225                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 226                         clock-output-names = "ss";
 227 @@ -269,7 +269,7 @@
 228
 229                 spi0_clk: clk@01c200a0 {
 230                         #clock-cells = <0>;
 231 -                       compatible = "allwinner,sun4i-mod0-clk";
 232 +                       compatible = "allwinner,sun4i-a10-mod0-clk";
 233                         reg = <0x01c200a0 0x4>;
 234                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 235                         clock-output-names = "spi0";
 236 @@ -277,7 +277,7 @@
 237
 238                 spi1_clk: clk@01c200a4 {
 239                         #clock-cells = <0>;
 240 -                       compatible = "allwinner,sun4i-mod0-clk";
 241 +                       compatible = "allwinner,sun4i-a10-mod0-clk";
 242                         reg = <0x01c200a4 0x4>;
 243                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 244                         clock-output-names = "spi1";
 245 @@ -285,7 +285,7 @@
 246
 247                 spi2_clk: clk@01c200a8 {
 248                         #clock-cells = <0>;
 249 -                       compatible = "allwinner,sun4i-mod0-clk";
 250 +                       compatible = "allwinner,sun4i-a10-mod0-clk";
 251                         reg = <0x01c200a8 0x4>;
 252                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 253                         clock-output-names = "spi2";
 254 @@ -293,7 +293,7 @@
 255
 256                 pata_clk: clk@01c200ac {
 257                         #clock-cells = <0>;
 258 -                       compatible = "allwinner,sun4i-mod0-clk";
 259 +                       compatible = "allwinner,sun4i-a10-mod0-clk";
 260                         reg = <0x01c200ac 0x4>;
 261                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 262                         clock-output-names = "pata";
 263 @@ -301,7 +301,7 @@
 264
 265                 ir0_clk: clk@01c200b0 {
 266                         #clock-cells = <0>;
 267 -                       compatible = "allwinner,sun4i-mod0-clk";
 268 +                       compatible = "allwinner,sun4i-a10-mod0-clk";
 269                         reg = <0x01c200b0 0x4>;
 270                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 271                         clock-output-names = "ir0";
 272 @@ -309,7 +309,7 @@
 273
 274                 ir1_clk: clk@01c200b4 {
 275                         #clock-cells = <0>;
 276 -                       compatible = "allwinner,sun4i-mod0-clk";
 277 +                       compatible = "allwinner,sun4i-a10-mod0-clk";
 278                         reg = <0x01c200b4 0x4>;
 279                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 280                         clock-output-names = "ir1";
 281 @@ -326,7 +326,7 @@
 282
 283                 spi3_clk: clk@01c200d4 {
 284                         #clock-cells = <0>;
 285 -                       compatible = "allwinner,sun4i-mod0-clk";
 286 +                       compatible = "allwinner,sun4i-a10-mod0-clk";
 287                         reg = <0x01c200d4 0x4>;
 288                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 289                         clock-output-names = "spi3";
 290 --- a/arch/arm/boot/dts/sun5i-a10s.dtsi
 291 +++ b/arch/arm/boot/dts/sun5i-a10s.dtsi
 292 @@ -49,7 +49,7 @@
 293
 294                 osc24M: clk@01c20050 {
 295                         #clock-cells = <0>;
 296 -                       compatible = "allwinner,sun4i-osc-clk";
 297 +                       compatible = "allwinner,sun4i-a10-osc-clk";
 298                         reg = <0x01c20050 0x4>;
 299                         clock-frequency = <24000000>;
 300                         clock-output-names = "osc24M";
 301 @@ -64,7 +64,7 @@
 302
 303                 pll1: clk@01c20000 {
 304                         #clock-cells = <0>;
 305 -                       compatible = "allwinner,sun4i-pll1-clk";
 306 +                       compatible = "allwinner,sun4i-a10-pll1-clk";
 307                         reg = <0x01c20000 0x4>;
 308                         clocks = <&osc24M>;
 309                         clock-output-names = "pll1";
 310 @@ -72,7 +72,7 @@
 311
 312                 pll4: clk@01c20018 {
 313                         #clock-cells = <0>;
 314 -                       compatible = "allwinner,sun4i-pll1-clk";
 315 +                       compatible = "allwinner,sun4i-a10-pll1-clk";
 316                         reg = <0x01c20018 0x4>;
 317                         clocks = <&osc24M>;
 318                         clock-output-names = "pll4";
 319 @@ -80,7 +80,7 @@
 320
 321                 pll5: clk@01c20020 {
 322                         #clock-cells = <1>;
 323 -                       compatible = "allwinner,sun4i-pll5-clk";
 324 +                       compatible = "allwinner,sun4i-a10-pll5-clk";
 325                         reg = <0x01c20020 0x4>;
 326                         clocks = <&osc24M>;
 327                         clock-output-names = "pll5_ddr", "pll5_other";
 328 @@ -88,7 +88,7 @@
 329
 330                 pll6: clk@01c20028 {
 331                         #clock-cells = <1>;
 332 -                       compatible = "allwinner,sun4i-pll6-clk";
 333 +                       compatible = "allwinner,sun4i-a10-pll6-clk";
 334                         reg = <0x01c20028 0x4>;
 335                         clocks = <&osc24M>;
 336                         clock-output-names = "pll6_sata", "pll6_other", "pll6";
 337 @@ -97,7 +97,7 @@
 338                 /* dummy is 200M */
 339                 cpu: cpu@01c20054 {
 340                         #clock-cells = <0>;
 341 -                       compatible = "allwinner,sun4i-cpu-clk";
 342 +                       compatible = "allwinner,sun4i-a10-cpu-clk";
 343                         reg = <0x01c20054 0x4>;
 344                         clocks = <&osc32k>, <&osc24M>, <&pll1>, <&dummy>;
 345                         clock-output-names = "cpu";
 346 @@ -105,7 +105,7 @@
 347
 348                 axi: axi@01c20054 {
 349                         #clock-cells = <0>;
 350 -                       compatible = "allwinner,sun4i-axi-clk";
 351 +                       compatible = "allwinner,sun4i-a10-axi-clk";
 352                         reg = <0x01c20054 0x4>;
 353                         clocks = <&cpu>;
 354                         clock-output-names = "axi";
 355 @@ -113,7 +113,7 @@
 356
 357                 axi_gates: clk@01c2005c {
 358                         #clock-cells = <1>;
 359 -                       compatible = "allwinner,sun4i-axi-gates-clk";
 360 +                       compatible = "allwinner,sun4i-a10-axi-gates-clk";
 361                         reg = <0x01c2005c 0x4>;
 362                         clocks = <&axi>;
 363                         clock-output-names = "axi_dram";
 364 @@ -121,7 +121,7 @@
 365
 366                 ahb: ahb@01c20054 {
 367                         #clock-cells = <0>;
 368 -                       compatible = "allwinner,sun4i-ahb-clk";
 369 +                       compatible = "allwinner,sun4i-a10-ahb-clk";
 370                         reg = <0x01c20054 0x4>;
 371                         clocks = <&axi>;
 372                         clock-output-names = "ahb";
 373 @@ -143,7 +143,7 @@
 374
 375                 apb0: apb0@01c20054 {
 376                         #clock-cells = <0>;
 377 -                       compatible = "allwinner,sun4i-apb0-clk";
 378 +                       compatible = "allwinner,sun4i-a10-apb0-clk";
 379                         reg = <0x01c20054 0x4>;
 380                         clocks = <&ahb>;
 381                         clock-output-names = "apb0";
 382 @@ -160,7 +160,7 @@
 383
 384                 apb1_mux: apb1_mux@01c20058 {
 385                         #clock-cells = <0>;
 386 -                       compatible = "allwinner,sun4i-apb1-mux-clk";
 387 +                       compatible = "allwinner,sun4i-a10-apb1-mux-clk";
 388                         reg = <0x01c20058 0x4>;
 389                         clocks = <&osc24M>, <&pll6 1>, <&osc32k>;
 390                         clock-output-names = "apb1_mux";
 391 @@ -168,7 +168,7 @@
 392
 393                 apb1: apb1@01c20058 {
 394                         #clock-cells = <0>;
 395 -                       compatible = "allwinner,sun4i-apb1-clk";
 396 +                       compatible = "allwinner,sun4i-a10-apb1-clk";
 397                         reg = <0x01c20058 0x4>;
 398                         clocks = <&apb1_mux>;
 399                         clock-output-names = "apb1";
 400 @@ -186,7 +186,7 @@
 401
 402                 nand_clk: clk@01c20080 {
 403                         #clock-cells = <0>;
 404 -                       compatible = "allwinner,sun4i-mod0-clk";
 405 +                       compatible = "allwinner,sun4i-a10-mod0-clk";
 406                         reg = <0x01c20080 0x4>;
 407                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 408                         clock-output-names = "nand";
 409 @@ -194,7 +194,7 @@
 410
 411                 ms_clk: clk@01c20084 {
 412                         #clock-cells = <0>;
 413 -                       compatible = "allwinner,sun4i-mod0-clk";
 414 +                       compatible = "allwinner,sun4i-a10-mod0-clk";
 415                         reg = <0x01c20084 0x4>;
 416                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 417                         clock-output-names = "ms";
 418 @@ -202,7 +202,7 @@
 419
 420                 mmc0_clk: clk@01c20088 {
 421                         #clock-cells = <0>;
 422 -                       compatible = "allwinner,sun4i-mod0-clk";
 423 +                       compatible = "allwinner,sun4i-a10-mod0-clk";
 424                         reg = <0x01c20088 0x4>;
 425                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 426                         clock-output-names = "mmc0";
 427 @@ -210,7 +210,7 @@
 428
 429                 mmc1_clk: clk@01c2008c {
 430                         #clock-cells = <0>;
 431 -                       compatible = "allwinner,sun4i-mod0-clk";
 432 +                       compatible = "allwinner,sun4i-a10-mod0-clk";
 433                         reg = <0x01c2008c 0x4>;
 434                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 435                         clock-output-names = "mmc1";
 436 @@ -218,7 +218,7 @@
 437
 438                 mmc2_clk: clk@01c20090 {
 439                         #clock-cells = <0>;
 440 -                       compatible = "allwinner,sun4i-mod0-clk";
 441 +                       compatible = "allwinner,sun4i-a10-mod0-clk";
 442                         reg = <0x01c20090 0x4>;
 443                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 444                         clock-output-names = "mmc2";
 445 @@ -226,7 +226,7 @@
 446
 447                 ts_clk: clk@01c20098 {
 448                         #clock-cells = <0>;
 449 -                       compatible = "allwinner,sun4i-mod0-clk";
 450 +                       compatible = "allwinner,sun4i-a10-mod0-clk";
 451                         reg = <0x01c20098 0x4>;
 452                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 453                         clock-output-names = "ts";
 454 @@ -234,7 +234,7 @@
 455
 456                 ss_clk: clk@01c2009c {
 457                         #clock-cells = <0>;
 458 -                       compatible = "allwinner,sun4i-mod0-clk";
 459 +                       compatible = "allwinner,sun4i-a10-mod0-clk";
 460                         reg = <0x01c2009c 0x4>;
 461                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 462                         clock-output-names = "ss";
 463 @@ -242,7 +242,7 @@
 464
 465                 spi0_clk: clk@01c200a0 {
 466                         #clock-cells = <0>;
 467 -                       compatible = "allwinner,sun4i-mod0-clk";
 468 +                       compatible = "allwinner,sun4i-a10-mod0-clk";
 469                         reg = <0x01c200a0 0x4>;
 470                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 471                         clock-output-names = "spi0";
 472 @@ -250,7 +250,7 @@
 473
 474                 spi1_clk: clk@01c200a4 {
 475                         #clock-cells = <0>;
 476 -                       compatible = "allwinner,sun4i-mod0-clk";
 477 +                       compatible = "allwinner,sun4i-a10-mod0-clk";
 478                         reg = <0x01c200a4 0x4>;
 479                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 480                         clock-output-names = "spi1";
 481 @@ -258,7 +258,7 @@
 482
 483                 spi2_clk: clk@01c200a8 {
 484                         #clock-cells = <0>;
 485 -                       compatible = "allwinner,sun4i-mod0-clk";
 486 +                       compatible = "allwinner,sun4i-a10-mod0-clk";
 487                         reg = <0x01c200a8 0x4>;
 488                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 489                         clock-output-names = "spi2";
 490 @@ -266,7 +266,7 @@
 491
 492                 ir0_clk: clk@01c200b0 {
 493                         #clock-cells = <0>;
 494 -                       compatible = "allwinner,sun4i-mod0-clk";
 495 +                       compatible = "allwinner,sun4i-a10-mod0-clk";
 496                         reg = <0x01c200b0 0x4>;
 497                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 498                         clock-output-names = "ir0";
 499 @@ -283,7 +283,7 @@
 500
 501                 mbus_clk: clk@01c2015c {
 502                         #clock-cells = <0>;
 503 -                       compatible = "allwinner,sun4i-mod0-clk";
 504 +                       compatible = "allwinner,sun4i-a10-mod0-clk";
 505                         reg = <0x01c2015c 0x4>;
 506                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 507                         clock-output-names = "mbus";
 508 --- a/arch/arm/boot/dts/sun5i-a13.dtsi
 509 +++ b/arch/arm/boot/dts/sun5i-a13.dtsi
 510 @@ -54,7 +54,7 @@
 511
 512                 osc24M: clk@01c20050 {
 513                         #clock-cells = <0>;
 514 -                       compatible = "allwinner,sun4i-osc-clk";
 515 +                       compatible = "allwinner,sun4i-a10-osc-clk";
 516                         reg = <0x01c20050 0x4>;
 517                         clock-frequency = <24000000>;
 518                         clock-output-names = "osc24M";
 519 @@ -69,7 +69,7 @@
 520
 521                 pll1: clk@01c20000 {
 522                         #clock-cells = <0>;
 523 -                       compatible = "allwinner,sun4i-pll1-clk";
 524 +                       compatible = "allwinner,sun4i-a10-pll1-clk";
 525                         reg = <0x01c20000 0x4>;
 526                         clocks = <&osc24M>;
 527                         clock-output-names = "pll1";
 528 @@ -77,7 +77,7 @@
 529
 530                 pll4: clk@01c20018 {
 531                         #clock-cells = <0>;
 532 -                       compatible = "allwinner,sun4i-pll1-clk";
 533 +                       compatible = "allwinner,sun4i-a10-pll1-clk";
 534                         reg = <0x01c20018 0x4>;
 535                         clocks = <&osc24M>;
 536                         clock-output-names = "pll4";
 537 @@ -85,7 +85,7 @@
 538
 539                 pll5: clk@01c20020 {
 540                         #clock-cells = <1>;
 541 -                       compatible = "allwinner,sun4i-pll5-clk";
 542 +                       compatible = "allwinner,sun4i-a10-pll5-clk";
 543                         reg = <0x01c20020 0x4>;
 544                         clocks = <&osc24M>;
 545                         clock-output-names = "pll5_ddr", "pll5_other";
 546 @@ -93,7 +93,7 @@
 547
 548                 pll6: clk@01c20028 {
 549                         #clock-cells = <1>;
 550 -                       compatible = "allwinner,sun4i-pll6-clk";
 551 +                       compatible = "allwinner,sun4i-a10-pll6-clk";
 552                         reg = <0x01c20028 0x4>;
 553                         clocks = <&osc24M>;
 554                         clock-output-names = "pll6_sata", "pll6_other", "pll6";
 555 @@ -102,7 +102,7 @@
 556                 /* dummy is 200M */
 557                 cpu: cpu@01c20054 {
 558                         #clock-cells = <0>;
 559 -                       compatible = "allwinner,sun4i-cpu-clk";
 560 +                       compatible = "allwinner,sun4i-a10-cpu-clk";
 561                         reg = <0x01c20054 0x4>;
 562                         clocks = <&osc32k>, <&osc24M>, <&pll1>, <&dummy>;
 563                         clock-output-names = "cpu";
 564 @@ -110,7 +110,7 @@
 565
 566                 axi: axi@01c20054 {
 567                         #clock-cells = <0>;
 568 -                       compatible = "allwinner,sun4i-axi-clk";
 569 +                       compatible = "allwinner,sun4i-a10-axi-clk";
 570                         reg = <0x01c20054 0x4>;
 571                         clocks = <&cpu>;
 572                         clock-output-names = "axi";
 573 @@ -118,7 +118,7 @@
 574
 575                 axi_gates: clk@01c2005c {
 576                         #clock-cells = <1>;
 577 -                       compatible = "allwinner,sun4i-axi-gates-clk";
 578 +                       compatible = "allwinner,sun4i-a10-axi-gates-clk";
 579                         reg = <0x01c2005c 0x4>;
 580                         clocks = <&axi>;
 581                         clock-output-names = "axi_dram";
 582 @@ -126,7 +126,7 @@
 583
 584                 ahb: ahb@01c20054 {
 585                         #clock-cells = <0>;
 586 -                       compatible = "allwinner,sun4i-ahb-clk";
 587 +                       compatible = "allwinner,sun4i-a10-ahb-clk";
 588                         reg = <0x01c20054 0x4>;
 589                         clocks = <&axi>;
 590                         clock-output-names = "ahb";
 591 @@ -147,7 +147,7 @@
 592
 593                 apb0: apb0@01c20054 {
 594                         #clock-cells = <0>;
 595 -                       compatible = "allwinner,sun4i-apb0-clk";
 596 +                       compatible = "allwinner,sun4i-a10-apb0-clk";
 597                         reg = <0x01c20054 0x4>;
 598                         clocks = <&ahb>;
 599                         clock-output-names = "apb0";
 600 @@ -163,7 +163,7 @@
 601
 602                 apb1_mux: apb1_mux@01c20058 {
 603                         #clock-cells = <0>;
 604 -                       compatible = "allwinner,sun4i-apb1-mux-clk";
 605 +                       compatible = "allwinner,sun4i-a10-apb1-mux-clk";
 606                         reg = <0x01c20058 0x4>;
 607                         clocks = <&osc24M>, <&pll6 1>, <&osc32k>;
 608                         clock-output-names = "apb1_mux";
 609 @@ -171,7 +171,7 @@
 610
 611                 apb1: apb1@01c20058 {
 612                         #clock-cells = <0>;
 613 -                       compatible = "allwinner,sun4i-apb1-clk";
 614 +                       compatible = "allwinner,sun4i-a10-apb1-clk";
 615                         reg = <0x01c20058 0x4>;
 616                         clocks = <&apb1_mux>;
 617                         clock-output-names = "apb1";
 618 @@ -188,7 +188,7 @@
 619
 620                 nand_clk: clk@01c20080 {
 621                         #clock-cells = <0>;
 622 -                       compatible = "allwinner,sun4i-mod0-clk";
 623 +                       compatible = "allwinner,sun4i-a10-mod0-clk";
 624                         reg = <0x01c20080 0x4>;
 625                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 626                         clock-output-names = "nand";
 627 @@ -196,7 +196,7 @@
 628
 629                 ms_clk: clk@01c20084 {
 630                         #clock-cells = <0>;
 631 -                       compatible = "allwinner,sun4i-mod0-clk";
 632 +                       compatible = "allwinner,sun4i-a10-mod0-clk";
 633                         reg = <0x01c20084 0x4>;
 634                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 635                         clock-output-names = "ms";
 636 @@ -204,7 +204,7 @@
 637
 638                 mmc0_clk: clk@01c20088 {
 639                         #clock-cells = <0>;
 640 -                       compatible = "allwinner,sun4i-mod0-clk";
 641 +                       compatible = "allwinner,sun4i-a10-mod0-clk";
 642                         reg = <0x01c20088 0x4>;
 643                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 644                         clock-output-names = "mmc0";
 645 @@ -212,7 +212,7 @@
 646
 647                 mmc1_clk: clk@01c2008c {
 648                         #clock-cells = <0>;
 649 -                       compatible = "allwinner,sun4i-mod0-clk";
 650 +                       compatible = "allwinner,sun4i-a10-mod0-clk";
 651                         reg = <0x01c2008c 0x4>;
 652                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 653                         clock-output-names = "mmc1";
 654 @@ -220,7 +220,7 @@
 655
 656                 mmc2_clk: clk@01c20090 {
 657                         #clock-cells = <0>;
 658 -                       compatible = "allwinner,sun4i-mod0-clk";
 659 +                       compatible = "allwinner,sun4i-a10-mod0-clk";
 660                         reg = <0x01c20090 0x4>;
 661                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 662                         clock-output-names = "mmc2";
 663 @@ -228,7 +228,7 @@
 664
 665                 ts_clk: clk@01c20098 {
 666                         #clock-cells = <0>;
 667 -                       compatible = "allwinner,sun4i-mod0-clk";
 668 +                       compatible = "allwinner,sun4i-a10-mod0-clk";
 669                         reg = <0x01c20098 0x4>;
 670                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 671                         clock-output-names = "ts";
 672 @@ -236,7 +236,7 @@
 673
 674                 ss_clk: clk@01c2009c {
 675                         #clock-cells = <0>;
 676 -                       compatible = "allwinner,sun4i-mod0-clk";
 677 +                       compatible = "allwinner,sun4i-a10-mod0-clk";
 678                         reg = <0x01c2009c 0x4>;
 679                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 680                         clock-output-names = "ss";
 681 @@ -244,7 +244,7 @@
 682
 683                 spi0_clk: clk@01c200a0 {
 684                         #clock-cells = <0>;
 685 -                       compatible = "allwinner,sun4i-mod0-clk";
 686 +                       compatible = "allwinner,sun4i-a10-mod0-clk";
 687                         reg = <0x01c200a0 0x4>;
 688                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 689                         clock-output-names = "spi0";
 690 @@ -252,7 +252,7 @@
 691
 692                 spi1_clk: clk@01c200a4 {
 693                         #clock-cells = <0>;
 694 -                       compatible = "allwinner,sun4i-mod0-clk";
 695 +                       compatible = "allwinner,sun4i-a10-mod0-clk";
 696                         reg = <0x01c200a4 0x4>;
 697                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 698                         clock-output-names = "spi1";
 699 @@ -260,7 +260,7 @@
 700
 701                 spi2_clk: clk@01c200a8 {
 702                         #clock-cells = <0>;
 703 -                       compatible = "allwinner,sun4i-mod0-clk";
 704 +                       compatible = "allwinner,sun4i-a10-mod0-clk";
 705                         reg = <0x01c200a8 0x4>;
 706                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 707                         clock-output-names = "spi2";
 708 @@ -268,7 +268,7 @@
 709
 710                 ir0_clk: clk@01c200b0 {
 711                         #clock-cells = <0>;
 712 -                       compatible = "allwinner,sun4i-mod0-clk";
 713 +                       compatible = "allwinner,sun4i-a10-mod0-clk";
 714                         reg = <0x01c200b0 0x4>;
 715                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 716                         clock-output-names = "ir0";
 717 @@ -285,7 +285,7 @@
 718
 719                 mbus_clk: clk@01c2015c {
 720                         #clock-cells = <0>;
 721 -                       compatible = "allwinner,sun4i-mod0-clk";
 722 +                       compatible = "allwinner,sun4i-a10-mod0-clk";
 723                         reg = <0x01c2015c 0x4>;
 724                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 725                         clock-output-names = "mbus";
 726 --- a/arch/arm/boot/dts/sun6i-a31.dtsi
 727 +++ b/arch/arm/boot/dts/sun6i-a31.dtsi
 728 @@ -95,7 +95,7 @@
 729
 730                 cpu: cpu@01c20050 {
 731                         #clock-cells = <0>;
 732 -                       compatible = "allwinner,sun4i-cpu-clk";
 733 +                       compatible = "allwinner,sun4i-a10-cpu-clk";
 734                         reg = <0x01c20050 0x4>;
 735
 736                         /*
 737 @@ -110,7 +110,7 @@
 738
 739                 axi: axi@01c20050 {
 740                         #clock-cells = <0>;
 741 -                       compatible = "allwinner,sun4i-axi-clk";
 742 +                       compatible = "allwinner,sun4i-a10-axi-clk";
 743                         reg = <0x01c20050 0x4>;
 744                         clocks = <&cpu>;
 745                         clock-output-names = "axi";
 746 @@ -126,7 +126,7 @@
 747
 748                 ahb1: ahb1@01c20054 {
 749                         #clock-cells = <0>;
 750 -                       compatible = "allwinner,sun4i-ahb-clk";
 751 +                       compatible = "allwinner,sun4i-a10-ahb-clk";
 752                         reg = <0x01c20054 0x4>;
 753                         clocks = <&ahb1_mux>;
 754                         clock-output-names = "ahb1";
 755 @@ -155,7 +155,7 @@
 756
 757                 apb1: apb1@01c20054 {
 758                         #clock-cells = <0>;
 759 -                       compatible = "allwinner,sun4i-apb0-clk";
 760 +                       compatible = "allwinner,sun4i-a10-apb0-clk";
 761                         reg = <0x01c20054 0x4>;
 762                         clocks = <&ahb1>;
 763                         clock-output-names = "apb1";
 764 @@ -173,7 +173,7 @@
 765
 766                 apb2_mux: apb2_mux@01c20058 {
 767                         #clock-cells = <0>;
 768 -                       compatible = "allwinner,sun4i-apb1-mux-clk";
 769 +                       compatible = "allwinner,sun4i-a10-apb1-mux-clk";
 770                         reg = <0x01c20058 0x4>;
 771                         clocks = <&osc32k>, <&osc24M>, <&pll6>, <&pll6>;
 772                         clock-output-names = "apb2_mux";
 773 --- a/arch/arm/boot/dts/sun7i-a20.dtsi
 774 +++ b/arch/arm/boot/dts/sun7i-a20.dtsi
 775 @@ -64,7 +64,7 @@
 776
 777                 osc24M: clk@01c20050 {
 778                         #clock-cells = <0>;
 779 -                       compatible = "allwinner,sun4i-osc-clk";
 780 +                       compatible = "allwinner,sun4i-a10-osc-clk";
 781                         reg = <0x01c20050 0x4>;
 782                         clock-frequency = <24000000>;
 783                         clock-output-names = "osc24M";
 784 @@ -79,7 +79,7 @@
 785
 786                 pll1: clk@01c20000 {
 787                         #clock-cells = <0>;
 788 -                       compatible = "allwinner,sun4i-pll1-clk";
 789 +                       compatible = "allwinner,sun4i-a10-pll1-clk";
 790                         reg = <0x01c20000 0x4>;
 791                         clocks = <&osc24M>;
 792                         clock-output-names = "pll1";
 793 @@ -87,7 +87,7 @@
 794
 795                 pll4: clk@01c20018 {
 796                         #clock-cells = <0>;
 797 -                       compatible = "allwinner,sun4i-pll1-clk";
 798 +                       compatible = "allwinner,sun4i-a10-pll1-clk";
 799                         reg = <0x01c20018 0x4>;
 800                         clocks = <&osc24M>;
 801                         clock-output-names = "pll4";
 802 @@ -95,7 +95,7 @@
 803
 804                 pll5: clk@01c20020 {
 805                         #clock-cells = <1>;
 806 -                       compatible = "allwinner,sun4i-pll5-clk";
 807 +                       compatible = "allwinner,sun4i-a10-pll5-clk";
 808                         reg = <0x01c20020 0x4>;
 809                         clocks = <&osc24M>;
 810                         clock-output-names = "pll5_ddr", "pll5_other";
 811 @@ -103,7 +103,7 @@
 812
 813                 pll6: clk@01c20028 {
 814                         #clock-cells = <1>;
 815 -                       compatible = "allwinner,sun4i-pll6-clk";
 816 +                       compatible = "allwinner,sun4i-a10-pll6-clk";
 817                         reg = <0x01c20028 0x4>;
 818                         clocks = <&osc24M>;
 819                         clock-output-names = "pll6_sata", "pll6_other", "pll6";
 820 @@ -111,7 +111,7 @@
 821
 822                 cpu: cpu@01c20054 {
 823                         #clock-cells = <0>;
 824 -                       compatible = "allwinner,sun4i-cpu-clk";
 825 +                       compatible = "allwinner,sun4i-a10-cpu-clk";
 826                         reg = <0x01c20054 0x4>;
 827                         clocks = <&osc32k>, <&osc24M>, <&pll1>, <&pll6 1>;
 828                         clock-output-names = "cpu";
 829 @@ -119,7 +119,7 @@
 830
 831                 axi: axi@01c20054 {
 832                         #clock-cells = <0>;
 833 -                       compatible = "allwinner,sun4i-axi-clk";
 834 +                       compatible = "allwinner,sun4i-a10-axi-clk";
 835                         reg = <0x01c20054 0x4>;
 836                         clocks = <&cpu>;
 837                         clock-output-names = "axi";
 838 @@ -127,7 +127,7 @@
 839
 840                 ahb: ahb@01c20054 {
 841                         #clock-cells = <0>;
 842 -                       compatible = "allwinner,sun4i-ahb-clk";
 843 +                       compatible = "allwinner,sun4i-a10-ahb-clk";
 844                         reg = <0x01c20054 0x4>;
 845                         clocks = <&axi>;
 846                         clock-output-names = "ahb";
 847 @@ -155,7 +155,7 @@
 848
 849                 apb0: apb0@01c20054 {
 850                         #clock-cells = <0>;
 851 -                       compatible = "allwinner,sun4i-apb0-clk";
 852 +                       compatible = "allwinner,sun4i-a10-apb0-clk";
 853                         reg = <0x01c20054 0x4>;
 854                         clocks = <&ahb>;
 855                         clock-output-names = "apb0";
 856 @@ -174,7 +174,7 @@
 857
 858                 apb1_mux: apb1_mux@01c20058 {
 859                         #clock-cells = <0>;
 860 -                       compatible = "allwinner,sun4i-apb1-mux-clk";
 861 +                       compatible = "allwinner,sun4i-a10-apb1-mux-clk";
 862                         reg = <0x01c20058 0x4>;
 863                         clocks = <&osc24M>, <&pll6 1>, <&osc32k>;
 864                         clock-output-names = "apb1_mux";
 865 @@ -182,7 +182,7 @@
 866
 867                 apb1: apb1@01c20058 {
 868                         #clock-cells = <0>;
 869 -                       compatible = "allwinner,sun4i-apb1-clk";
 870 +                       compatible = "allwinner,sun4i-a10-apb1-clk";
 871                         reg = <0x01c20058 0x4>;
 872                         clocks = <&apb1_mux>;
 873                         clock-output-names = "apb1";
 874 @@ -203,7 +203,7 @@
 875
 876                 nand_clk: clk@01c20080 {
 877                         #clock-cells = <0>;
 878 -                       compatible = "allwinner,sun4i-mod0-clk";
 879 +                       compatible = "allwinner,sun4i-a10-mod0-clk";
 880                         reg = <0x01c20080 0x4>;
 881                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 882                         clock-output-names = "nand";
 883 @@ -211,7 +211,7 @@
 884
 885                 ms_clk: clk@01c20084 {
 886                         #clock-cells = <0>;
 887 -                       compatible = "allwinner,sun4i-mod0-clk";
 888 +                       compatible = "allwinner,sun4i-a10-mod0-clk";
 889                         reg = <0x01c20084 0x4>;
 890                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 891                         clock-output-names = "ms";
 892 @@ -219,7 +219,7 @@
 893
 894                 mmc0_clk: clk@01c20088 {
 895                         #clock-cells = <0>;
 896 -                       compatible = "allwinner,sun4i-mod0-clk";
 897 +                       compatible = "allwinner,sun4i-a10-mod0-clk";
 898                         reg = <0x01c20088 0x4>;
 899                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 900                         clock-output-names = "mmc0";
 901 @@ -227,7 +227,7 @@
 902
 903                 mmc1_clk: clk@01c2008c {
 904                         #clock-cells = <0>;
 905 -                       compatible = "allwinner,sun4i-mod0-clk";
 906 +                       compatible = "allwinner,sun4i-a10-mod0-clk";
 907                         reg = <0x01c2008c 0x4>;
 908                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 909                         clock-output-names = "mmc1";
 910 @@ -235,7 +235,7 @@
 911
 912                 mmc2_clk: clk@01c20090 {
 913                         #clock-cells = <0>;
 914 -                       compatible = "allwinner,sun4i-mod0-clk";
 915 +                       compatible = "allwinner,sun4i-a10-mod0-clk";
 916                         reg = <0x01c20090 0x4>;
 917                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 918                         clock-output-names = "mmc2";
 919 @@ -243,7 +243,7 @@
 920
 921                 mmc3_clk: clk@01c20094 {
 922                         #clock-cells = <0>;
 923 -                       compatible = "allwinner,sun4i-mod0-clk";
 924 +                       compatible = "allwinner,sun4i-a10-mod0-clk";
 925                         reg = <0x01c20094 0x4>;
 926                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 927                         clock-output-names = "mmc3";
 928 @@ -251,7 +251,7 @@
 929
 930                 ts_clk: clk@01c20098 {
 931                         #clock-cells = <0>;
 932 -                       compatible = "allwinner,sun4i-mod0-clk";
 933 +                       compatible = "allwinner,sun4i-a10-mod0-clk";
 934                         reg = <0x01c20098 0x4>;
 935                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 936                         clock-output-names = "ts";
 937 @@ -259,7 +259,7 @@
 938
 939                 ss_clk: clk@01c2009c {
 940                         #clock-cells = <0>;
 941 -                       compatible = "allwinner,sun4i-mod0-clk";
 942 +                       compatible = "allwinner,sun4i-a10-mod0-clk";
 943                         reg = <0x01c2009c 0x4>;
 944                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 945                         clock-output-names = "ss";
 946 @@ -267,7 +267,7 @@
 947
 948                 spi0_clk: clk@01c200a0 {
 949                         #clock-cells = <0>;
 950 -                       compatible = "allwinner,sun4i-mod0-clk";
 951 +                       compatible = "allwinner,sun4i-a10-mod0-clk";
 952                         reg = <0x01c200a0 0x4>;
 953                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 954                         clock-output-names = "spi0";
 955 @@ -275,7 +275,7 @@
 956
 957                 spi1_clk: clk@01c200a4 {
 958                         #clock-cells = <0>;
 959 -                       compatible = "allwinner,sun4i-mod0-clk";
 960 +                       compatible = "allwinner,sun4i-a10-mod0-clk";
 961                         reg = <0x01c200a4 0x4>;
 962                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 963                         clock-output-names = "spi1";
 964 @@ -283,7 +283,7 @@
 965
 966                 spi2_clk: clk@01c200a8 {
 967                         #clock-cells = <0>;
 968 -                       compatible = "allwinner,sun4i-mod0-clk";
 969 +                       compatible = "allwinner,sun4i-a10-mod0-clk";
 970                         reg = <0x01c200a8 0x4>;
 971                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 972                         clock-output-names = "spi2";
 973 @@ -291,7 +291,7 @@
 974
 975                 pata_clk: clk@01c200ac {
 976                         #clock-cells = <0>;
 977 -                       compatible = "allwinner,sun4i-mod0-clk";
 978 +                       compatible = "allwinner,sun4i-a10-mod0-clk";
 979                         reg = <0x01c200ac 0x4>;
 980                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 981                         clock-output-names = "pata";
 982 @@ -299,7 +299,7 @@
 983
 984                 ir0_clk: clk@01c200b0 {
 985                         #clock-cells = <0>;
 986 -                       compatible = "allwinner,sun4i-mod0-clk";
 987 +                       compatible = "allwinner,sun4i-a10-mod0-clk";
 988                         reg = <0x01c200b0 0x4>;
 989                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 990                         clock-output-names = "ir0";
 991 @@ -307,7 +307,7 @@
 992
 993                 ir1_clk: clk@01c200b4 {
 994                         #clock-cells = <0>;
 995 -                       compatible = "allwinner,sun4i-mod0-clk";
 996 +                       compatible = "allwinner,sun4i-a10-mod0-clk";
 997                         reg = <0x01c200b4 0x4>;
 998                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 999                         clock-output-names = "ir1";
1000 @@ -324,7 +324,7 @@
1001
1002                 spi3_clk: clk@01c200d4 {
1003                         #clock-cells = <0>;
1004 -                       compatible = "allwinner,sun4i-mod0-clk";
1005 +                       compatible = "allwinner,sun4i-a10-mod0-clk";
1006                         reg = <0x01c200d4 0x4>;
1007                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
1008                         clock-output-names = "spi3";
1009 @@ -332,7 +332,7 @@
1010
1011                 mbus_clk: clk@01c2015c {
1012                         #clock-cells = <0>;
1013 -                       compatible = "allwinner,sun4i-mod0-clk";
1014 +                       compatible = "allwinner,sun4i-a10-mod0-clk";
1015                         reg = <0x01c2015c 0x4>;
1016                         clocks = <&osc24M>, <&pll6 2>, <&pll5 1>;
1017                         clock-output-names = "mbus";