target/linux/sunxi/patches-3.13/211-dt-sun7i-add-external-clk-output.patch

   1 From 6dd612e3d7e0c76f863efaddae4738fadc461f72 Mon Sep 17 00:00:00 2001
   2 From: Chen-Yu Tsai <wens@csie.org>
   3 Date: Tue, 24 Dec 2013 21:26:18 +0800
   4 Subject: [PATCH] ARM: dts: sun7i: external clock outputs
   5
   6 This commit adds the two external clock outputs available on A20 to
   7 its device tree. A dummy fixed factor clock is also added to serve as
   8 the first input of the clock outputs, which according to AW's A20 user
   9 manual, is the 24MHz oscillator divided by 750.
  10
  11 Signed-off-by: Chen-Yu Tsai <wens@csie.org>
  12 ---
  13  arch/arm/boot/dts/sun7i-a20.dtsi | 27 +++++++++++++++++++++++++++
  14  1 file changed, 27 insertions(+)
  15
  16 --- a/arch/arm/boot/dts/sun7i-a20.dtsi
  17 +++ b/arch/arm/boot/dts/sun7i-a20.dtsi
  18 @@ -312,6 +312,33 @@
  19                         clocks = <&osc24M>, <&pll6 2>, <&pll5 1>;
  20                         clock-output-names = "mbus";
  21                 };
  22 +
  23 +               /*
  24 +                * Dummy clock used by output clocks
  25 +                */
  26 +               osc24M_32k: osc24M_32k {
  27 +                       #clock-cells = <0>;
  28 +                       compatible = "fixed-factor-clock";
  29 +                       clock-div = <750>;
  30 +                       clock-mult = <1>;
  31 +                       clocks = <&osc24M>;
  32 +               };
  33 +
  34 +               clk_out_a: clk@01c201f0 {
  35 +                       #clock-cells = <0>;
  36 +                       compatible = "allwinner,sun7i-a20-out-clk";
  37 +                       reg = <0x01c201f0 0x4>;
  38 +                       clocks = <&osc24M_32k>, <&osc32k>, <&osc24M>;
  39 +                       clock-output-names = "clk_out_a";
  40 +               };
  41 +
  42 +               clk_out_b: clk@01c201f4 {
  43 +                       #clock-cells = <0>;
  44 +                       compatible = "allwinner,sun7i-a20-out-clk";
  45 +                       reg = <0x01c201f4 0x4>;
  46 +                       clocks = <&osc24M_32k>, <&osc32k>, <&osc24M>;
  47 +                       clock-output-names = "clk_out_b";
  48 +               };
  49         };
  50
  51         timer {