1 From 3d56b9643ff9fff3c7ceb095e03f4ab7e149b9ce Mon Sep 17 00:00:00 2001
2 From: =?UTF-8?q?Emilio=20L=C3=B3pez?= <emilio@elopez.com.ar>
3 Date: Mon, 23 Dec 2013 00:32:34 -0300
4 Subject: [PATCH] clk: sunxi: add gating support to PLL1
6 Content-Type: text/plain; charset=UTF-8
7 Content-Transfer-Encoding: 8bit
9 This commit adds gating support to PLL1 on the clock driver. This makes
10 the PLL1 implementation fully compatible with PLL4 as well.
12 Signed-off-by: Emilio López <emilio@elopez.com.ar>
13 Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
14 Acked-by: Mike Turquette <mturquette@linaro.org>
16 Documentation/devicetree/bindings/clock/sunxi.txt | 2 +-
17 drivers/clk/sunxi/clk-sunxi.c | 2 ++
18 2 files changed, 3 insertions(+), 1 deletion(-)
20 diff --git a/Documentation/devicetree/bindings/clock/sunxi.txt b/Documentation/devicetree/bindings/clock/sunxi.txt
21 index 91a748f..b8c6cc4 100644
22 --- a/Documentation/devicetree/bindings/clock/sunxi.txt
23 +++ b/Documentation/devicetree/bindings/clock/sunxi.txt
24 @@ -7,7 +7,7 @@ This binding uses the common clock binding[1].
26 - compatible : shall be one of the following:
27 "allwinner,sun4i-osc-clk" - for a gatable oscillator
28 - "allwinner,sun4i-pll1-clk" - for the main PLL clock
29 + "allwinner,sun4i-pll1-clk" - for the main PLL clock and PLL4
30 "allwinner,sun6i-a31-pll1-clk" - for the main PLL clock on A31
31 "allwinner,sun4i-cpu-clk" - for the CPU multiplexer clock
32 "allwinner,sun4i-axi-clk" - for the AXI clock
33 diff --git a/drivers/clk/sunxi/clk-sunxi.c b/drivers/clk/sunxi/clk-sunxi.c
34 index 25ebba8..52f34ec 100644
35 --- a/drivers/clk/sunxi/clk-sunxi.c
36 +++ b/drivers/clk/sunxi/clk-sunxi.c
37 @@ -301,11 +301,13 @@ struct factors_data {
40 static const struct factors_data sun4i_pll1_data __initconst = {
42 .table = &sun4i_pll1_config,
43 .getter = sun4i_get_pll1_factors,
46 static const struct factors_data sun6i_a31_pll1_data __initconst = {
48 .table = &sun6i_a31_pll1_config,
49 .getter = sun6i_a31_get_pll1_factors,