target/linux/ramips/patches-3.18/500-alsa.patch

   1 --- a/sound/soc/Kconfig
   2 +++ b/sound/soc/Kconfig
   3 @@ -56,6 +56,7 @@ source "sound/soc/spear/Kconfig"
   4  source "sound/soc/tegra/Kconfig"
   5  source "sound/soc/txx9/Kconfig"
   6  source "sound/soc/ux500/Kconfig"
   7 +source "sound/soc/mtk/Kconfig"
   8
   9  # Supported codecs
  10  source "sound/soc/codecs/Kconfig"
  11 --- a/sound/soc/Makefile
  12 +++ b/sound/soc/Makefile
  13 @@ -33,3 +33,4 @@ obj-$(CONFIG_SND_SOC) += spear/
  14  obj-$(CONFIG_SND_SOC)  += tegra/
  15  obj-$(CONFIG_SND_SOC)  += txx9/
  16  obj-$(CONFIG_SND_SOC)  += ux500/
  17 +obj-$(CONFIG_SND_SOC)   += mtk/
  18 --- a/sound/soc/codecs/Kconfig
  19 +++ b/sound/soc/codecs/Kconfig
  20 @@ -725,7 +725,7 @@ config SND_SOC_WM8955
  21         tristate
  22
  23  config SND_SOC_WM8960
  24 -       tristate
  25 +       tristate "WM8960"
  26
  27  config SND_SOC_WM8961
  28         tristate
  29 --- /dev/null
  30 +++ b/sound/soc/mtk/Kconfig
  31 @@ -0,0 +1,35 @@
  32 +config SND_MT76XX_SOC
  33 +       tristate "SoC Audio for MT76XX APSoC Machine"
  34 +       depends on SND_SOC && (SOC_MT7620 || SOC_MT7621)
  35 +
  36 +       help
  37 +         Say Y or M if you want to add support for codecs attached to
  38 +         the MTK I2S interface.
  39 +
  40 +choice
  41 +       prompt "Selected SoC type"
  42 +       depends on SND_MT76XX_SOC
  43 +       default SND_MT76XX_SOC_MT7620
  44 +
  45 +config SND_MT76XX_SOC_MT7620
  46 +       bool "MT7620"
  47 +       depends on SOC_MT7620
  48 +
  49 +config SND_MT76XX_SOC_MT7628
  50 +       bool "MT7628"
  51 +       depends on SOC_MT7620
  52 +
  53 +config SND_MT76XX_SOC_MT7621
  54 +       bool "MT7621"
  55 +       depends on SOC_MT7621
  56 +
  57 +endchoice
  58 +
  59 +config SND_MT76XX_PCM
  60 +       tristate "MTK SoC Audio PCM Platform"
  61 +       depends on SND_MT76XX_SOC
  62 +
  63 +config SND_MT76XX_I2S
  64 +       tristate "MTK SoC I2S Support"
  65 +       depends on SND_MT76XX_SOC
  66 +
  67 --- /dev/null
  68 +++ b/sound/soc/mtk/Makefile
  69 @@ -0,0 +1,40 @@
  70 +KBUILD_CFLAGS += -I$(srctree)
  71 +
  72 +ifeq ($(CONFIG_SND_MT76XX_SOC_MT7620),y)
  73 +KBUILD_CFLAGS += -DCONFIG_MT7620 -DCONFIG_RALINK_MT7620
  74 +endif
  75 +ifeq ($(CONFIG_SND_MT76XX_SOC_MT7628),y)
  76 +KBUILD_CFLAGS += -DCONFIG_MT7628 -DCONFIG_RALINK_MT7628
  77 +endif
  78 +ifeq ($(CONFIG_SOC_MT7620),y)
  79 +KBUILD_CFLAGS += -DRALINK_SYSCTL_BASE=0xB0000000
  80 +KBUILD_CFLAGS += -DRALINK_INTCL_BASE=0xB0000200
  81 +KBUILD_CFLAGS += -DRALINK_PIO_BASE=0xB0000600
  82 +KBUILD_CFLAGS += -DRALINK_I2S_BASE=0xB0000A00
  83 +KBUILD_CFLAGS += -DRALINK_GDMA_BASE=0xB0002800
  84 +KBUILD_CFLAGS += -DCONFIG_GDMA_EVERYBODY
  85 +KBUILD_CFLAGS += -DCONFIG_SND_MT76XX_SOC
  86 +KBUILD_CFLAGS += -DCONFIG_I2S_WM8960
  87 +#KBUILD_CFLAGS += -DCONFIG_I2S_MCLK_12P288MHZ
  88 +KBUILD_CFLAGS += -DCONFIG_I2S_MCLK_12MHZ
  89 +KBUILD_CFLAGS += -DCONFIG_GDMA_EVERYBODY
  90 +KBUILD_CFLAGS += -DSURFBOARDINT_DMA=15
  91 +KBUILD_CFLAGS += -DRALINK_INTCTL_DMA=128
  92 +KBUILD_CFLAGS += -DCONFIG_SND_SOC_WM8960
  93 +endif
  94 +
  95 +# MTK APSoC Platform Support
  96 +snd-soc-mt76xx-i2s-ctl-objs := i2s_ctrl.o i2s_debug.o #i2c_wm8960.o
  97 +snd-soc-mt76xx-pcm-objs := mt76xx_pcm.o
  98 +snd-soc-mt76xx-i2s-objs := mt76xx_i2s.o
  99 +
 100 +obj-$(CONFIG_SND_MT76XX_PCM) += snd-soc-mt76xx-pcm.o
 101 +obj-$(CONFIG_SND_MT76XX_I2S) += snd-soc-mt76xx-i2s-ctl.o snd-soc-mt76xx-i2s.o
 102 +
 103 +# MTK APSoC Machine Support
 104 +snd-soc-mt76xx-machine-objs := mt76xx_machine.o
 105 +
 106 +obj-$(CONFIG_SND_MT76XX_SOC) += i2c_wm8960.o ralink_gdma.o snd-soc-mt76xx-machine.o
 107 +
 108 +
 109 +
 110 --- /dev/null
 111 +++ b/sound/soc/mtk/i2c_wm8960.c
 112 @@ -0,0 +1,492 @@
 113 +#include <linux/kernel.h>
 114 +#include <linux/version.h>
 115 +#include <linux/init.h>
 116 +#include <linux/module.h>
 117 +#include <linux/slab.h>
 118 +#include <linux/i2c.h>
 119 +#include <linux/delay.h>
 120 +#include <linux/interrupt.h>
 121 +#include <linux/fs.h>
 122 +#include <linux/fcntl.h>
 123 +#include <linux/cdev.h>
 124 +#if defined(CONFIG_ARCH_MT7623)
 125 +#include <mt_i2c.h>
 126 +#include <mach/mt_gpio.h>
 127 +#endif
 128 +#include "i2c_wm8960.h"
 129 +#include "i2s_ctrl.h"
 130 +
 131 +
 132 +#define BUF_SIZE               20
 133 +
 134 +#undef MSG
 135 +#define MSG printk
 136 +
 137 +
 138 +#if defined(CONFIG_ARCH_MT7623)
 139 +/*FIXME*/
 140 +//static struct i2c_board_info __initdata i2c_devs1 = { I2C_BOARD_INFO("codec_wm8960", (0X34>>1))};
 141 +static struct i2c_board_info __initdata i2c_devs1 = { I2C_BOARD_INFO("codec_wm8960", (0X34))};
 142 +
 143 +#endif
 144 +unsigned long wm_reg_data[56];
 145 +struct wm8960_data *wmio;
 146 +
 147 +struct wm8960_data {
 148 +       struct i2c_client       *client;
 149 +       struct device       *dev;
 150 +       const char                      *name;
 151 +};
 152 +
 153 +
 154 +void i2c_WM8960_write(u32 reg, u32 data)
 155 +{
 156 +       int ret;
 157 +        struct i2c_msg msg;
 158 +       u8 buf[2]={0};
 159 +
 160 +#if defined(CONFIG_ARCH_MT7623)
 161 +       unsigned int ext_flag = 0;
 162 +
 163 +       ext_flag &= 0x7FFFFFFF;
 164 +       ext_flag |= I2C_A_FILTER_MSG;
 165 +       ext_flag |= I2C_POLLING_FLAG;
 166 +#endif
 167 +
 168 +       wm_reg_data[reg] = data;
 169 +
 170 +       buf[0]= (reg<<1)|(0x01&(data>>8));
 171 +       buf[1]= (data&0xFF);
 172 +
 173 +#if defined(CONFIG_ARCH_MT7623)
 174 +       /*FIXME*/
 175 +       //msg.addr = wmio->client->addr;
 176 +       msg.addr = wmio->client->addr>>1;
 177 +
 178 +#else
 179 +        msg.addr = wmio->client->addr>>1;
 180 +#endif
 181 +       msg.flags = 0;
 182 +        msg.buf = (char *)buf;
 183 +       msg.len = 2;
 184 +#if defined(CONFIG_ARCH_MT7623)
 185 +       msg.timing = 80;
 186 +       msg.ext_flag = ext_flag & 0x7FFFFFFF;
 187 +#endif
 188 +
 189 +        ret = i2c_transfer(wmio->client->adapter, &msg, 1);
 190 +       MSG("[WM8960(%02X)=0x%08X]\n",(unsigned int)reg,(unsigned int)data);
 191 +
 192 +        if (ret <= 0)
 193 +                printk("%s: i2c write error!\n", __func__);
 194 +}
 195 +
 196 +
 197 +
 198 +// Reset and power up the WM8960
 199 +void audiohw_preinit(void)
 200 +{
 201 +       memset(wm_reg_data, 0 , sizeof(unsigned long)*55);
 202 +
 203 +       i2c_WM8960_write(RESET, RESET_RESET);    // Reset (0x0F)
 204 +
 205 +       mdelay(50);
 206 +       wm_reg_data[RESET] = 0xFFFF;
 207 +       mdelay(50);
 208 +}
 209 +
 210 +void audiohw_set_apll(int srate)
 211 +{
 212 +       unsigned long data;
 213 +
 214 +       if((srate==8000) || (srate==12000) || (srate==16000) || (srate==24000) || (srate==32000) || (srate==48000))
 215 +       {
 216 +               // Provide 12.288MHz SYSCLK
 217 +               data = wm_reg_data[PLL1];
 218 +               i2c_WM8960_write(PLL1, data | PLL1_OPCLKDIV_1 | PLL1_SDM_FRACTIONAL | PLL1_PLLPRESCALE_1 | PLL1_PLLN(0x8));   // PLL1 (0x34)
 219 +
 220 +               i2c_WM8960_write(PLL2, PLL2_PLLK_23_16(0x31));  // PLL2 (0x35)
 221 +               i2c_WM8960_write(PLL3, PLL3_PLLK_15_8(0x26));  // PLL3 (0x36)
 222 +               i2c_WM8960_write(PLL4, PLL4_PLLK_7_0(0xe9));  // PLL4 (0x37)
 223 +       }
 224 +       else if ((srate==11025) || (srate==22050) || (srate==44100))
 225 +       {
 226 +               //Provide 11.2896MHz SYSCLK
 227 +               data = wm_reg_data[PLL1];
 228 +               i2c_WM8960_write(PLL1, data | PLL1_OPCLKDIV_1 | PLL1_SDM_FRACTIONAL | PLL1_PLLPRESCALE_1 | PLL1_PLLN(0x7));   //PLL1 (0x34)
 229 +
 230 +               i2c_WM8960_write(PLL2, PLL2_PLLK_23_16(0x86));  //PLL2 (0x35)
 231 +               i2c_WM8960_write(PLL3, PLL3_PLLK_15_8(0xc2));  //PLL3 (0x36)
 232 +               i2c_WM8960_write(PLL4, PLL4_PLLK_7_0(0x26));  //PLL4 (0x37)
 233 +       }
 234 +       else
 235 +       {
 236 +               printk("Not support this srate\n");
 237 +       }
 238 +       mdelay(3);
 239 +}
 240 +
 241 +
 242 +void audiohw_set_frequency(int fsel, int pll_en)
 243 +{
 244 +        MSG("audiohw_set_frequency_=0x%08X\n",fsel);
 245 +
 246 +       if (pll_en)
 247 +       {
 248 +               printk("PLL enable\n");
 249 +               i2c_WM8960_write(CLOCKING1, (fsel<<3) | CLOCKING1_SYSCLKDIV_2 | CLOCKING1_CLKSEL_PLL);  //CLOCKING (0x04)=>0x05
 250 +
 251 +       }
 252 +       else
 253 +       {
 254 +               printk("PLL disable\n");
 255 +               i2c_WM8960_write(CLOCKING1, (fsel<<3));//| CLOCKING1_SYSCLKDIV_2);  //CLOCKING (0x04)
 256 +       }
 257 +
 258 +}
 259 +
 260 +//FIXME
 261 +int audiohw_set_lineout_vol(int Aout, int vol_l, int vol_r)
 262 +{
 263 +       MSG("audiohw_set_lineout_vol_\n");
 264 +       switch(Aout)
 265 +       {
 266 +       case 1:
 267 +               //i2c_WM8960_write(LOUT1, LOUT1_LO1VU|LOUT1_LO1ZC|LOUT1_LOUT1VOL(0x7f)); //LOUT1(0x02)
 268 +               //i2c_WM8960_write(ROUT1, ROUT1_RO1VU|ROUT1_RO1ZC|ROUT1_ROUT1VOL(0x7f)); //ROUT1(0x03)
 269 +               i2c_WM8960_write(LOUT1, LOUT1_LO1VU|LOUT1_LO1ZC|LOUT1_LOUT1VOL(vol_l)); //LOUT1(0x02)
 270 +               i2c_WM8960_write(ROUT1, ROUT1_RO1VU|ROUT1_RO1ZC|ROUT1_ROUT1VOL(vol_r)); //ROUT1(0x03)
 271 +               break;
 272 +       case 2:
 273 +               i2c_WM8960_write(LSPK, LSPK_SPKLVU|LSPK_SPKLZC| LSPK_SPKLVOL(vol_l));
 274 +               i2c_WM8960_write(RSPK, RSPK_SPKRVU|RSPK_SPKRZC| RSPK_SPKRVOL(vol_r));
 275 +               break;
 276 +       default:
 277 +               break;
 278 +       }
 279 +       return 0;
 280 +}
 281 +
 282 +//FIXME
 283 +int audiohw_set_linein_vol(int vol_l, int vol_r)
 284 +{
 285 +       MSG("audiohw_set_linein_vol_\n");
 286 +
 287 +    i2c_WM8960_write(LINV, LINV_IPVU|LINV_LINVOL(vol_l)); //LINV(0x00)=>0x12b
 288 +       i2c_WM8960_write(RINV, RINV_IPVU|RINV_RINVOL(vol_r)); //LINV(0x01)=>0x12b
 289 +
 290 +       return 0;
 291 +}
 292 +
 293 +//Set signal path
 294 +int audiohw_postinit(int bSlave, int AIn, int AOut, int pll_en, int wordLen24b)
 295 +{
 296 +
 297 +       int i;
 298 +       unsigned long data;
 299 +
 300 +       if(wm_reg_data[RESET]!=0xFFFF)
 301 +       return 0;
 302 +
 303 +       if(bSlave)
 304 +       {
 305 +               MSG("WM8960 slave.....\n");
 306 +               if(wordLen24b)
 307 +               {
 308 +                       printk("24 bit word length\n");
 309 +                       i2c_WM8960_write(AINTFCE1, AINTFCE1_WL_24 | AINTFCE1_FORMAT_I2S); //AINTFCE1(0x07)
 310 +               }
 311 +               else
 312 +               {
 313 +                       printk("16 bit word length\n");
 314 +                       i2c_WM8960_write(AINTFCE1, AINTFCE1_WL_16 | AINTFCE1_FORMAT_I2S); //AINTFCE1(0x07)
 315 +               }
 316 +       }
 317 +       else
 318 +       {
 319 +               MSG("WM8960 master.....\n");
 320 +               i2c_WM8960_write(CLOCKING2, 0x1c4);//CLOCKING2_BCLKDIV(0x1c4));  //CLOCKING2(0x08)
 321 +
 322 +               if(wordLen24b)
 323 +               {
 324 +                       printk("24 bit word length\n");
 325 +                       i2c_WM8960_write(AINTFCE1, AINTFCE1_MS | AINTFCE1_WL_24 | AINTFCE1_FORMAT_I2S); //AINTFCE1(0x07)
 326 +               }
 327 +               else
 328 +               {
 329 +                       printk("16 bit word length\n");
 330 +                       i2c_WM8960_write(AINTFCE1, AINTFCE1_MS | AINTFCE1_WL_16 | AINTFCE1_FORMAT_I2S); //AINTFCE1(0x07)
 331 +               }
 332 +               mdelay(5);
 333 +       }
 334 +
 335 +
 336 +       //From app notes: allow Vref to stabilize to reduce clicks
 337 +       for(i = 0; i < 1000*HZ; i++);
 338 +
 339 +       if(AIn > 0)
 340 +       {
 341 +                       data = wm_reg_data[PWRMGMT1];
 342 +               i2c_WM8960_write(PWRMGMT1, data|PWRMGMT1_ADCL|PWRMGMT1_ADCR|PWRMGMT1_AINL |PWRMGMT1_AINR);//|PWRMGMT1_MICB);//PWRMGMT1(0x19)
 343 +
 344 +               data = wm_reg_data[ADDITIONAL1];
 345 +               i2c_WM8960_write(ADDITIONAL1, data|ADDITIONAL1_DATSEL(0x01)); //ADDITIONAL1(0x17)
 346 +               i2c_WM8960_write(LADCVOL, LADCVOL_LAVU_EN|LADCVOL_LADCVOL(0xc3)); //LADCVOL(0x15)
 347 +               i2c_WM8960_write(RADCVOL, RADCVOL_RAVU_EN|RADCVOL_RADCVOL(0xc3)); //RADCVOL(0x16)
 348 +               i2c_WM8960_write(ADCLPATH, ADCLPATH_LMN1|ADCLPATH_LMIC2B);//|ADCLPATH_LMICBOOST_13DB); //ADCLPATH(0x20)=>(0x108)
 349 +               i2c_WM8960_write(ADCRPATH, ADCRPATH_RMN1|ADCRPATH_RMIC2B);//|ADCRPATH_RMICBOOST_13DB); //ADCRPATH(0x21)=>(0x108)
 350 +               i2c_WM8960_write(PWRMGMT3, PWRMGMT3_LMIC|PWRMGMT3_RMIC); //PWRMGMT3(0x2f)
 351 +
 352 +               //i2c_WM8960_write(LINBMIX, 0x000); //LINBMIX(0x2B)
 353 +
 354 +               if (AOut<=0)
 355 +               {
 356 +                       i2c_WM8960_write(AINTFCE2, 0x40); //FIXME:(0x09)
 357 +
 358 +                       data = wm_reg_data[PWRMGMT2];
 359 +                       if(pll_en)
 360 +                       {
 361 +                               i2c_WM8960_write(PWRMGMT2, data|PWRMGMT2_PLL_EN|PWRMGMT2_DACL|PWRMGMT2_DACR); //PWRMGMT2(0x1a)
 362 +                       }
 363 +                       else
 364 +                       {
 365 +                               i2c_WM8960_write(PWRMGMT2, data|PWRMGMT2_DACL|PWRMGMT2_DACR); //PWRMGMT2(0x1a)
 366 +
 367 +                       }
 368 +               }
 369 +       }
 370 +       if(AOut>0)
 371 +       {
 372 +               //Power management 2 setting
 373 +               data = wm_reg_data[PWRMGMT2];
 374 +
 375 +               if(pll_en)
 376 +               {
 377 +                       i2c_WM8960_write(PWRMGMT2, data|PWRMGMT2_PLL_EN|PWRMGMT2_DACL|PWRMGMT2_DACR|PWRMGMT2_LOUT1|PWRMGMT2_ROUT1|PWRMGMT2_SPKL|PWRMGMT2_SPKR); //PWRMGMT2(0x1a)
 378 +               }
 379 +               else
 380 +               {
 381 +                       i2c_WM8960_write(PWRMGMT2, data|PWRMGMT2_DACL|PWRMGMT2_DACR|PWRMGMT2_LOUT1|PWRMGMT2_ROUT1|PWRMGMT2_SPKL|PWRMGMT2_SPKR); //PWRMGMT2(0x1a)
 382 +
 383 +               }
 384 +
 385 +               mdelay(10);
 386 +
 387 +               i2c_WM8960_write(AINTFCE2, 0x40); //FIXME:(0x09)
 388 +
 389 +               i2c_WM8960_write(LEFTGAIN, LEFTGAIN_LDVU|LEFTGAIN_LDACVOL(0xff)); //LEFTGAIN(0x0a)
 390 +               i2c_WM8960_write(RIGHTGAIN, RIGHTGAIN_RDVU|RIGHTGAIN_RDACVOL(0xff)); //RIGHTGAIN(0x0b)
 391 +
 392 +               i2c_WM8960_write(LEFTMIX1, 0x100);  //LEFTMIX1(0x22)
 393 +               i2c_WM8960_write(RIGHTMIX2, 0x100); //RIGHTMIX2(0x25)
 394 +
 395 +               data = wm_reg_data[PWRMGMT3]; //FIXME
 396 +               i2c_WM8960_write(PWRMGMT3, data|PWRMGMT3_ROMIX|PWRMGMT3_LOMIX); //PWRMGMT3(0x2f)
 397 +
 398 +               data = wm_reg_data[CLASSDCTRL1]; //CLASSDCTRL1(0x31) SPEAKER FIXME
 399 +               i2c_WM8960_write(CLASSDCTRL1, 0xf7);//data|CLASSDCTRL1_OP_LRSPK);
 400 +
 401 +               data = wm_reg_data[CLASSDCTRL3];        //CLASSDCTRL3(0x33)
 402 +               i2c_WM8960_write(CLASSDCTRL3, 0xad);//data|(0x1b));
 403 +       }
 404 +
 405 +       i2c_WM8960_write(DACCTRL1, 0x000);  //DACCTRL1(0x05)
 406 +
 407 +       data = wm_reg_data[PWRMGMT1];
 408 +       i2c_WM8960_write(PWRMGMT1, data|0x1c0); //FIXME:PWRMGMT1(0x19)
 409 +
 410 +
 411 +       printk("WM8960 All initial ok!\n");
 412 +
 413 +       return 0;
 414 +
 415 +}
 416 +
 417 +void audiohw_micboost(int boostgain)
 418 +{
 419 +       unsigned long data;
 420 +
 421 +       data =  wm_reg_data[ADCLPATH];
 422 +       i2c_WM8960_write(ADCLPATH, data|(boostgain << 4));
 423 +
 424 +       data =  wm_reg_data[ADCRPATH];
 425 +       i2c_WM8960_write(ADCRPATH, data|(boostgain << 4));
 426 +}
 427 +
 428 +void audiohw_micin(int enableMic)
 429 +{
 430 +       unsigned long data;
 431 +
 432 +       if (enableMic==1)
 433 +       {
 434 +               data =  wm_reg_data[PWRMGMT1];
 435 +               i2c_WM8960_write(PWRMGMT1, data|PWRMGMT1_MICB);
 436 +       }
 437 +#if 1
 438 +       else
 439 +       {
 440 +               data =  wm_reg_data[PWRMGMT1];
 441 +               i2c_WM8960_write(PWRMGMT1, data & (~(PWRMGMT1_MICB)));
 442 +       }
 443 +#endif
 444 +}
 445 +
 446 +void audiohw_mute( bool mute)
 447 +{
 448 +    //Mute:   Set DACMU = 1 to soft-mute the audio DACs.
 449 +    //Unmute: Set DACMU = 0 to soft-un-mute the audio DACs.
 450 +    i2c_WM8960_write(DACCTRL1, mute ? DACCTRL1_DACMU : 0);
 451 +}
 452 +
 453 +
 454 +//Nice shutdown of WM8960 codec
 455 +void audiohw_close(void)
 456 +{
 457 +       i2c_WM8960_write(DACCTRL1,DACCTRL1_DACMU); //0x05->0x08
 458 +       i2c_WM8960_write(PWRMGMT1, 0x000); //0x19->0x000
 459 +       mdelay(400);
 460 +       i2c_WM8960_write(PWRMGMT2, 0x000); //0x1a->0x000
 461 +
 462 +}
 463 +
 464 +void audiohw_loopback(int fsel)
 465 +{
 466 +}
 467 +
 468 +void audiohw_codec_exlbk(void)
 469 +{
 470 +       memset(wm_reg_data, 0 , sizeof(unsigned long)*55);
 471 +
 472 +       i2c_WM8960_write(LINV, 0x117); //0x00->0x117
 473 +       i2c_WM8960_write(RINV, 0x117); //0x01->0x117
 474 +       i2c_WM8960_write(LOUT1, 0x179); //0x02->0x179
 475 +       i2c_WM8960_write(ROUT1, 0x179); //0x03->0x179
 476 +       i2c_WM8960_write(CLOCKING1, 0x00); //0x04->0x00
 477 +       //i2c_WM8960_write(CLOCKING1, 0x40); //0x04->0x00
 478 +       i2c_WM8960_write(DACCTRL1, 0x00); //0x05->0x00
 479 +       i2c_WM8960_write(AINTFCE2, 0x41); //0x09->0x41
 480 +       i2c_WM8960_write(LADCVOL, 0x1c3); //0x15->0x1c3
 481 +       i2c_WM8960_write(RADCVOL, 0x1c3); //0x16->0x1c3
 482 +       i2c_WM8960_write(PWRMGMT1, 0xfc); //0x19->0xfc
 483 +       i2c_WM8960_write(PWRMGMT2, 0x1e0); //0x1a->0x1e0
 484 +       i2c_WM8960_write(ADCLPATH, 0x108); //0x20->0x108
 485 +       i2c_WM8960_write(ADCRPATH, 0x108); //0x21->0x108
 486 +       i2c_WM8960_write(LEFTMIX1, 0x150); //0x22->0x150
 487 +       i2c_WM8960_write(RIGHTMIX2, 0x150); //0x25->0x150
 488 +       i2c_WM8960_write(BYPASS1, 0x00); //0x2d->0x00
 489 +       i2c_WM8960_write(BYPASS2, 0x00); //0x2e->0x00
 490 +       i2c_WM8960_write(PWRMGMT3, 0x3c); //0x2f->0x3c
 491 +}
 492 +
 493 +void audiohw_bypass(void)
 494 +{
 495 +       int i;
 496 +
 497 +       memset(wm_reg_data, 0 , sizeof(unsigned long)*55);
 498 +       i2c_WM8960_write(RESET, 0x000);    //0x0f(R15)->0x000
 499 +
 500 +       for(i = 0; i < 1000*HZ; i++);
 501 +
 502 +       i2c_WM8960_write(PWRMGMT1, 0xf0); //0x19(R25)->0xf0
 503 +       i2c_WM8960_write(PWRMGMT2, 0x60); //0x1a(R26)->0x60
 504 +       i2c_WM8960_write(PWRMGMT3, 0x3c); //0x2f(R47)->0x3c
 505 +       i2c_WM8960_write(LINV, 0x117); // 0x00(R0)->0x117
 506 +       i2c_WM8960_write(RINV, 0x117); // 0x01(R1)->0x117
 507 +       i2c_WM8960_write(ADCLPATH, 0x108); //0x20(R32)->0x108
 508 +       i2c_WM8960_write(ADCRPATH, 0x108); //0x21(R33)->0x108
 509 +       i2c_WM8960_write(BYPASS1, 0x80); //0x2d(R45)->0x80
 510 +       i2c_WM8960_write(BYPASS2, 0x80); //0x2e(R46)->0x80
 511 +       i2c_WM8960_write(LOUT1, 0x179); // 0x02(R2)->0x179
 512 +       i2c_WM8960_write(ROUT1, 0x179); // 0x03(R3)->0x179
 513 +}
 514 +EXPORT_SYMBOL(audiohw_set_frequency);
 515 +EXPORT_SYMBOL(audiohw_close);
 516 +EXPORT_SYMBOL(audiohw_postinit);
 517 +EXPORT_SYMBOL(audiohw_preinit);
 518 +EXPORT_SYMBOL(audiohw_set_apll);
 519 +EXPORT_SYMBOL(audiohw_codec_exlbk);
 520 +EXPORT_SYMBOL(audiohw_bypass);
 521 +EXPORT_SYMBOL(audiohw_set_lineout_vol);
 522 +EXPORT_SYMBOL(audiohw_set_linein_vol);
 523 +EXPORT_SYMBOL(audiohw_micin);
 524 +EXPORT_SYMBOL(audiohw_mute);
 525 +EXPORT_SYMBOL(audiohw_loopback);
 526 +EXPORT_SYMBOL(audiohw_micboost);
 527 +
 528 +static int codec_wm8960_i2c_probe(struct i2c_client *client, const struct i2c_device_id *id)
 529 +{
 530 +       struct wm8960_data *wm;
 531 +
 532 +printk("*******Enter %s********\n", __func__);
 533 +
 534 +       if (!i2c_check_functionality(client->adapter, I2C_FUNC_I2C))
 535 +               return -EIO;
 536 +
 537 +       wm = devm_kzalloc(&client->dev, sizeof(struct wm8960_data), GFP_KERNEL);
 538 +       if (!wm)
 539 +               return -ENOMEM;
 540 +
 541 +#if defined(CONFIG_ARCH_MT7623)
 542 +       mt_set_gpio_mode(GPIO242, GPIO_MODE_04);
 543 +        mt_set_gpio_mode(GPIO243, GPIO_MODE_04);
 544 +#endif
 545 +       wm->client = client;
 546 +       wm->dev = &client->dev;
 547 +       wm->name = id->name;
 548 +       i2c_set_clientdata(client, wm);
 549 +       wmio = wm;
 550 +
 551 +       memset(wm_reg_data, 0 , sizeof(unsigned long)*55);
 552 +
 553 +       return 0;
 554 +}
 555 +
 556 +#if LINUX_VERSION_CODE >= KERNEL_VERSION(3,8,0)
 557 +static int codec_wm8960_i2c_remove(struct i2c_client *client)
 558 +#else
 559 +static int __devexit codec_wm8960_i2c_remove(struct i2c_client *client)
 560 +#endif
 561 +{
 562 +       struct wm8960_data *wm = i2c_get_clientdata(client);
 563 +       kfree(wm);
 564 +
 565 +       return 0;
 566 +}
 567 +
 568 +static const struct i2c_device_id wm8960_id[] = {
 569 +       { "codec_wm8960", 0 },
 570 +       {}
 571 +};
 572 +
 573 +static struct i2c_driver codec_wm8960_i2c_driver = {
 574 +       .driver = {
 575 +               .name   = "codec_wm8960"
 576 +       },
 577 +       .probe  = codec_wm8960_i2c_probe,
 578 +#if LINUX_VERSION_CODE >= KERNEL_VERSION(3,8,0)
 579 +        .remove = codec_wm8960_i2c_remove,
 580 +#else
 581 +       .remove = __devexit_p(codec_wm8960_i2c_remove),
 582 +#endif
 583 +       .id_table = wm8960_id,
 584 +};
 585 +static int __init wm8960_i2c_init(void)
 586 +{
 587 +#if defined(CONFIG_ARCH_MT7623)
 588 +       i2c_register_board_info(1, &i2c_devs1, 1);
 589 +#endif
 590 +       return i2c_add_driver(&codec_wm8960_i2c_driver);;
 591 +}
 592 +
 593 +static void __exit wm8960_i2c_exit(void)
 594 +{
 595 +       i2c_del_driver(&codec_wm8960_i2c_driver);
 596 +}
 597 +
 598 +module_init(wm8960_i2c_init);
 599 +module_exit(wm8960_i2c_exit);
 600 +
 601 +MODULE_AUTHOR("Ryder Lee <ryder.lee@mediatek.com>");
 602 +MODULE_DESCRIPTION("WM8960 I2C client driver");
 603 +MODULE_LICENSE("GPL");
 604 +
 605 --- /dev/null
 606 +++ b/sound/soc/mtk/i2c_wm8960.h
 607 @@ -0,0 +1,288 @@
 608 +/* wm8960.h  --  WM8960 Soc Audio driver */
 609 +#ifndef _WM8960_H
 610 +#define _WM8960_H
 611 +
 612 +#define bool   unsigned char
 613 +#define false 0
 614 +#define true 1
 615 +
 616 +/* volume/balance/treble/bass interdependency */
 617 +#define VOLUME_MIN     -730
 618 +#define VOLUME_MAX     60
 619 +
 620 +
 621 +/* Register addresses and bits */
 622 +#define OUTPUT_MUTED                   0x2f
 623 +#define OUTPUT_0DB                     0x79
 624 +
 625 +#define LINV                           0x00
 626 +#define LINV_IPVU                      (1 << 8)  /* FIXME */
 627 +#define LINV_LINMUTE                   (1 << 7)
 628 +#define LINV_LIZC                       (1 << 6)
 629 +#define LINV_LINVOL(x)                 ((x) & 0x3f)
 630 +
 631 +#define RINV                           0x01
 632 +#define RINV_IPVU                      (1 << 8) /* FIXME */
 633 +#define RINV_RINMUTE                   (1 << 7)
 634 +#define RINV_RIZC                      (1 << 6)
 635 +#define RINV_RINVOL(x)                 ((x) & 0x3f)
 636 +
 637 +#define LOUT1                          0x02
 638 +#define LOUT1_LO1VU                    (1 << 8)
 639 +#define LOUT1_LO1ZC                    (1 << 7)
 640 +#define LOUT1_LOUT1VOL(x)              ((x) & 0x7f)
 641 +
 642 +#define ROUT1                          0x03
 643 +#define ROUT1_RO1VU                    (1 << 8)
 644 +#define ROUT1_RO1ZC                    (1 << 7)
 645 +#define ROUT1_ROUT1VOL(x)              ((x) & 0x7f)
 646 +
 647 +#define CLOCKING1                      0x04  /* FIXME */
 648 +#define CLOCKING1_ADCDIV(x)            (((x) & 0x7) << 6)
 649 +#define CLOCKING1_DACDIV(x)            (((x) & 0x7) << 3)
 650 +#define CLOCKING1_SYSCLKDIV_1          (0 << 1)
 651 +#define CLOCKING1_SYSCLKDIV_2          (2 << 1)
 652 +#define CLOCKING1_CLKSEL_MCLK          (0 << 0)
 653 +#define CLOCKING1_CLKSEL_PLL           (1 << 0)
 654 +
 655 +#define DACCTRL1                       0x05
 656 +#define DACCTRL1_DATTENUATE             (1 << 7)
 657 +#define DACCTRL1_DACMU                 (1 << 3)
 658 +#define DACCTRL1_DEEMPH_48             (3 << 1)
 659 +#define DACCTRL1_DEEMPH_44             (2 << 1)
 660 +#define DACCTRL1_DEEMPH_32             (1 << 1)
 661 +#define DACCTRL1_DEEMPH_NONE           (0 << 1)
 662 +#define DACCTRL1_DEEMPH(x)             ((x) & (0x3 << 1))
 663 +
 664 +#define DACCTRL2                       0x06
 665 +
 666 +#define AINTFCE1                       0x07
 667 +#define AINTFCE1_BCLKINV               (1 << 7)
 668 +#define AINTFCE1_MS                    (1 << 6)
 669 +#define AINTFCE1_LRSWAP                (1 << 5)
 670 +#define AINTFCE1_LRP                   (1 << 4)
 671 +#define AINTFCE1_WL_32                 (3 << 2)
 672 +#define AINTFCE1_WL_24                  (2 << 2)
 673 +#define AINTFCE1_WL_20                  (1 << 2)
 674 +#define AINTFCE1_WL_16                 (0 << 2)
 675 +#define AINTFCE1_WL(x)                 (((x) & 0x3) << 2)
 676 +#define AINTFCE1_FORMAT_DSP             (3 << 0)
 677 +#define AINTFCE1_FORMAT_I2S             (2 << 0)
 678 +#define AINTFCE1_FORMAT_LJUST           (1 << 0)
 679 +#define AINTFCE1_FORMAT_RJUST          (0 << 0)
 680 +#define AINTFCE1_FORMAT(x)             ((x) & 0x3)
 681 +
 682 +/* FIXME */
 683 +#define CLOCKING2                      0x08
 684 +#define CLOCKING2_DCLKDIV(x)            (((x) & 0x7) << 6)
 685 +#define CLOCKING2_BCLKDIV(x)           (((x) & 0xf) << 0)
 686 +
 687 +#define AINTFCE2                       0x09
 688 +#define AINTFCE2_ALRCGPIO_ALRC         (0 << 6)
 689 +#define        AINTFCE2_ALRCGPIO_GPIO          (1 << 6)
 690 +#define        AINTFCE2_LOOPBACK               (1 << 0)
 691 +
 692 +#define LEFTGAIN                       0x0a
 693 +#define LEFTGAIN_LDVU                   (1 << 8)
 694 +#define LEFTGAIN_LDACVOL(x)            ((x) & 0xff)
 695 +
 696 +#define RIGHTGAIN                      0x0b
 697 +#define RIGHTGAIN_RDVU                  (1 << 8)
 698 +#define RIGHTGAIN_RDACVOL(x)           ((x) & 0xff)
 699 +
 700 +#define RESET                          0x0f
 701 +#define RESET_RESET                    0x000
 702 +
 703 +#define ALC1                           0x11
 704 +#define ALC1_ALCOFF                    (0x0 << 7)
 705 +#define        ALC1_ALCRONLY                   (0x1 << 7)
 706 +#define ALC1_ALCLONLY                  (0x2 << 7)
 707 +#define ALC1_ALCSTEREO                 (0x3 << 7)
 708 +#define ALC1_ALCSEL(x)                 (((x) & 0x3) << 7)
 709 +#define ALC1_SET_MAXGAIN(x)            ((x & 0x7) << 4)
 710 +#define ALC1_GET_MAXGAIN(x)            ((x) & (0x7 << 4))
 711 +#define ALC1_ALCL(x)                   ((x) & 0x0f)
 712 +
 713 +#define ALC2                           0x12
 714 +#define ALC2_MINGAIN(x)                ((x & 0x7) << 4)
 715 +#define ALC2_HLD(x)                    ((x) & 0x0f)
 716 +
 717 +#define ALC3                           0x13
 718 +#define ALC3_SET_DCY(x)                        ((x & 0x0f) << 4)
 719 +#define ALC3_GET_DCY(x)                        ((x) & (0x0f << 4))
 720 +#define ALC3_ATK(x)                    ((x) & 0x0f)
 721 +
 722 +#define NOISEGATE                      0x14
 723 +#define NOISEGATE_SET_NGTH(x)          ((x & 0x1f) << 3)
 724 +#define NOISEGATE_GET_NGTH(x)          ((x) & (0x1f << 3))
 725 +#define NOISEGATE_NGAT_ENABLE          1
 726 +
 727 +#define LADCVOL                                0x15
 728 +#define LADCVOL_LAVU_EN                        (1 << 8)
 729 +#define LADCVOL_LADCVOL(x)             ((x) & 0x0ff)
 730 +
 731 +#define RADCVOL                                0x16
 732 +#define RADCVOL_RAVU_EN                        (1 << 8)
 733 +#define RADCVOL_RADCVOL(x)             ((x) & 0x0ff)
 734 +
 735 +#define ADDITIONAL1                    0x17
 736 +#define ADDITIONAL1_TSDEN               (1 << 8)
 737 +#define ADDITIONAL1_VSEL_LOWEST        (0 << 6)
 738 +#define ADDITIONAL1_VSEL_LOW           (1 << 6)
 739 +#define ADDITIONAL1_VSEL_DEFAULT2      (2 << 6)
 740 +#define ADDITIONAL1_VSEL_DEFAULT       (3 << 6)
 741 +#define ADDITIONAL1_VSEL(x)            (((x) & 0x3) << 6)
 742 +#define ADDITIONAL1_DMONOMIX_STEREO    (0 << 4)
 743 +#define ADDITIONAL1_DMONOMIX_MONO      (1 << 4)
 744 +#define ADDITIONAL1_DATSEL(x)          (((x) & 0x3) << 2)
 745 +#define ADDITIONAL1_TOCLKSEL            (1 << 1)
 746 +#define ADDITIONAL1_TOEN                (1 << 0)
 747 +
 748 +#define ADDITIONAL2                    0x18
 749 +#define ADDITIONAL2_HPSWEN              (1 << 6)
 750 +#define ADDITIONAL2_HPSWPOL             (1 << 5)
 751 +#define ADDITIONAL2_TRIS                (1 << 3)
 752 +#define ADDITIONAL2_LRCM_ON            (1 << 2)
 753 +
 754 +#define PWRMGMT1                       0x19
 755 +#define PWRMGMT1_VMIDSEL_DISABLED      (0 << 7)
 756 +#define PWRMGMT1_VMIDSEL_50K           (1 << 7)
 757 +#define PWRMGMT1_VMIDSEL_250K          (2 << 7)
 758 +#define PWRMGMT1_VMIDSEL_5K            (3 << 7)
 759 +#define PWRMGMT1_VREF                   (1 << 6)
 760 +#define PWRMGMT1_AINL                   (1 << 5)
 761 +#define PWRMGMT1_AINR                   (1 << 4)
 762 +#define PWRMGMT1_ADCL                   (1 << 3)
 763 +#define PWRMGMT1_ADCR                   (1 << 2)
 764 +#define PWRMGMT1_MICB                   (1 << 1)
 765 +#define PWRMGMT1_DIGENB                 (1 << 0)
 766 +
 767 +#define PWRMGMT2                       0x1a
 768 +#define PWRMGMT2_DACL                  (1 << 8)
 769 +#define PWRMGMT2_DACR                   (1 << 7)
 770 +#define PWRMGMT2_LOUT1                  (1 << 6)
 771 +#define PWRMGMT2_ROUT1                  (1 << 5)
 772 +#define PWRMGMT2_SPKL                   (1 << 4)
 773 +#define PWRMGMT2_SPKR                   (1 << 3)
 774 +#define PWRMGMT2_OUT3                   (1 << 1)
 775 +#define PWRMGMT2_PLL_EN                 (1 << 0)
 776 +
 777 +#define ADDITIONAL3                    0x1b
 778 +#define ADDITIONAL3_VROI               (1 << 6)
 779 +#define ADDITIONAL3_OUT3CAP             (1 << 3)
 780 +#define ADDITIONAL3_ADC_ALC_SR(x)       ((x) & 0x7)
 781 +
 782 +#define ANTIPOP1                       0x1c
 783 +#define ANTIPOP2                       0x1d
 784 +
 785 +#define ADCLPATH                       0x20
 786 +#define ADCLPATH_LMN1                  (1 << 8)
 787 +#define ADCLPATH_LMP3                   (1 << 7)
 788 +#define ADCLPATH_LMP2                   (1 << 6)
 789 +#define ADCLPATH_LMICBOOST_29DB         (0x3 << 4)
 790 +#define ADCLPATH_LMICBOOST_20DB         (0x2 << 4)
 791 +#define ADCLPATH_LMICBOOST_13DB         (0x1 << 4)
 792 +#define ADCLPATH_SET_LMICBOOST(x)       ((x & 0x3) << 4)
 793 +#define ADCLPATH_LMIC2B                 (1 << 3)
 794 +
 795 +
 796 +#define ADCRPATH                       0x21
 797 +#define ADCRPATH_RMN1                  (1 << 8)
 798 +#define ADCRPATH_RMP3                   (1 << 7)
 799 +#define ADCRPATH_RMP2                   (1 << 6)
 800 +#define ADCRPATH_RMICBOOST_29DB         (0x3 << 4)
 801 +#define ADCRPATH_RMICBOOST_20DB         (0x2 << 4)
 802 +#define ADCRPATH_RMICBOOST_13DB         (0x1 << 4)
 803 +#define ADCRPATH_SET_RMICBOOST(x)       ((x & 0x3) << 4)
 804 +#define ADCRPATH_RMIC2B                 (1 << 3)
 805 +
 806 +
 807 +#define LEFTMIX1                       0x22
 808 +#define LEFTMIX1_LD2LO                 (1 << 8)
 809 +#define LEFTMIX1_LI2LO                  (1 << 7)
 810 +#define LEFTMIX1_LI2LO_DEFAULT          (5 << 4)
 811 +#define LEFTMIX1_LI2LOVOL(x)            (((x) & 0x7) << 4)
 812 +
 813 +#define RIGHTMIX2                      0x25
 814 +#define RIGHTMIX2_RD2RO                (1 << 8)
 815 +#define RIGHTMIX2_RI2RO                 (1 << 7)
 816 +#define RIGHTMIX2_RI2RO_DEFAULT         (5 << 4)
 817 +#define RIGHTMIX2_RI2ROVOL(x)           (((x) & 0x7) << 4)
 818 +
 819 +#define MONOMIX1                       0x26
 820 +#define MONOMIX1_L2MO                  (1 << 7)
 821 +
 822 +#define MONOMIX2                       0x27
 823 +#define MONOMIX2_R2MO                  (1 << 7)
 824 +
 825 +#define LSPK                           0x28
 826 +#define LSPK_SPKLVU                    (1 << 8)
 827 +#define LSPK_SPKLZC                     (1 << 7)
 828 +#define LSPK_SPKLVOL(x)                 ((x) & 0x7f)
 829 +
 830 +#define RSPK                           0x29
 831 +#define RSPK_SPKRVU                    (1 << 8)
 832 +#define RSPK_SPKRZC                     (1 << 7)
 833 +#define RSPK_SPKRVOL(x)                 ((x) & 0x7f)
 834 +
 835 +#define OUT3V                          0x2a
 836 +#define LINBMIX                                0x2b
 837 +#define RINBMIX                                0x2c
 838 +#define BYPASS1                        0x2d
 839 +#define BYPASS2                                0x2e
 840 +
 841 +#define PWRMGMT3                       0x2f
 842 +#define PWRMGMT3_LMIC                  (1<<5)
 843 +#define PWRMGMT3_RMIC                   (1<<4)
 844 +#define PWRMGMT3_LOMIX                  (1<<3)
 845 +#define PWRMGMT3_ROMIX                  (1<<2)
 846 +
 847 +#define ADDITIONAL4                    0x30
 848 +
 849 +#define CLASSDCTRL1                    0x31
 850 +#define CLASSDCTRL1_OP_OFF             (0<<6)
 851 +#define CLASSDCTRL1_OP_LSPK            (1<<6)
 852 +#define CLASSDCTRL1_OP_RSPK            (2<<6)
 853 +#define CLASSDCTRL1_OP_LRSPK           (3<<6)
 854 +
 855 +#define CLASSDCTRL3                    0x33
 856 +
 857 +#define PLL1                           0x34
 858 +#define PLL1_OPCLKDIV_1                        (0<<6)
 859 +#define PLL1_OPCLKDIV_2                        (1<<6)
 860 +#define PLL1_OPCLKDIV_3                        (2<<6)
 861 +#define PLL1_OPCLKDIV_4                        (3<<6)
 862 +#define        PLL1_OPCLKDIV_5p5               (4<<6)
 863 +#define        PLL1_OPCLKDIV_6                 (5<<6)
 864 +#define PLL1_SDM_INTERGER              (0<<5)
 865 +#define PLL1_SDM_FRACTIONAL            (1<<5)
 866 +#define PLL1_PLLPRESCALE_1             (0<<4)
 867 +#define PLL1_PLLPRESCALE_2             (1<<4)
 868 +#define PLL1_PLLN(x)                   ((x) & 0xf)
 869 +
 870 +#define PLL2                           0x35
 871 +#define        PLL2_PLLK_23_16(x)              ((x) & 0x1ff)
 872 +
 873 +#define PLL3                           0x36
 874 +#define PLL3_PLLK_15_8(x)              ((x) & 0x1ff)
 875 +
 876 +#define PLL4                           0x37
 877 +#define PLL4_PLLK_7_0(x)               ((x) & 0x1ff)
 878 +
 879 +/* codec API */
 880 +void audiohw_preinit(void);
 881 +int audiohw_postinit(int bSlave, int AIn, int AOut, int pll_en, int wordLen24b);
 882 +void audiohw_close(void);
 883 +void audiohw_set_frequency(int fsel, int pll_en);
 884 +void audiohw_mute(bool mute);
 885 +void audiohw_micboost(int boostgain);
 886 +void audiohw_micin(int enableMic);
 887 +void audiohw_set_apll(int srate);
 888 +int audiohw_set_lineout_vol(int Aout, int vol_l, int vol_r);
 889 +int audiohw_set_linein_vol(int vol_l, int vol_r);
 890 +void audiohw_mute( bool mute);
 891 +void audiohw_loopback(int fsel);
 892 +void audiohw_codec_exlbk(void);
 893 +void audiohw_bypass(void);
 894 +
 895 +#endif /* _WM875x_H */
 896 --- /dev/null
 897 +++ b/sound/soc/mtk/i2s_ctrl.c
 898 @@ -0,0 +1,3524 @@
 899 +#include <linux/init.h>
 900 +#include <linux/version.h>
 901 +#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,35)
 902 +#include <linux/sched.h>
 903 +#endif
 904 +#include <linux/module.h>
 905 +#include <linux/kernel.h> /* _printk() */
 906 +#include <linux/slab.h> /* kmalloc() */
 907 +#include <linux/fs.h> /* everything... */
 908 +#include <linux/errno.h> /* error codes */
 909 +#include <linux/types.h> /* size_t */
 910 +#include <linux/proc_fs.h>
 911 +#include <linux/fcntl.h> /* O_ACCMODE */
 912 +#if LINUX_VERSION_CODE < KERNEL_VERSION(3,10,14)
 913 +#include <asm/system.h> /* cli(), *_flags */
 914 +#endif
 915 +#include <asm/uaccess.h> /* copy_from/to_user */
 916 +#include <linux/interrupt.h>
 917 +#include <linux/mm.h>
 918 +#include <linux/mm_types.h>
 919 +#include <linux/pci.h>
 920 +#include <linux/delay.h>
 921 +#include "ralink_gdma.h"
 922 +#if defined(CONFIG_I2S_WITH_AEC)
 923 +#include "../aec/aec_api.h"
 924 +#endif
 925 +
 926 +#ifdef  CONFIG_DEVFS_FS
 927 +#include <linux/devfs_fs_kernel.h>
 928 +static devfs_handle_t devfs_handle;
 929 +#endif
 930 +
 931 +#include "i2s_ctrl.h"
 932 +
 933 +#if defined(CONFIG_SND_MT76XX_SOC)
 934 +#include <sound/soc/mtk/mt76xx_machine.h>
 935 +#endif
 936 +
 937 +#if defined(CONFIG_I2S_WM8750)
 938 +#include "../codec/i2c_wm8750.h"
 939 +#endif
 940 +#if defined(CONFIG_I2S_WM8751)
 941 +#include "../codec/i2c_wm8751.h"
 942 +#endif
 943 +#if defined(CONFIG_I2S_WM8960)
 944 +#include "i2c_wm8960.h"
 945 +#endif
 946 +
 947 +static int i2sdrv_major =  191;
 948 +#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,35)
 949 +#else
 950 +static struct class *i2smodule_class;
 951 +#endif
 952 +
 953 +static int _printk(char *fmt, ...)
 954 +{
 955 +       return 0;
 956 +}
 957 +
 958 +/* external functions declarations */
 959 +#if defined(CONFIG_I2S_WM8960)
 960 +extern void audiohw_set_frequency(int fsel, int codec_pll_en);
 961 +void audiohw_set_apll(int srate);
 962 +#elif defined(CONFIG_I2S_WM8750)||defined(CONFIG_I2S_WM8751)
 963 +extern void audiohw_set_frequency(int fsel);
 964 +#endif
 965 +#if defined(CONFIG_I2S_WM8960)||defined(CONFIG_I2S_WM8750)||defined(CONFIG_I2S_WM8751)
 966 +extern int audiohw_set_lineout_vol(int Aout, int vol_l, int vol_r);
 967 +extern int audiohw_set_master_vol(int vol_l, int vol_r);
 968 +extern int audiohw_set_linein_vol(int vol_l, int vol_r);
 969 +#endif
 970 +
 971 +extern void audiohw_micboost(int boostgain);
 972 +
 973 +extern int GdmaI2sTx(uint32_t Src, uint32_t Dst, uint8_t TxNo, uint16_t TransCount,
 974 +                void (*DoneIntCallback)(uint32_t data),
 975 +                void (*UnMaskIntCallback)(uint32_t data));
 976 +
 977 +extern int GdmaI2sRx(uint32_t Src, uint32_t Dst, uint8_t RxNo, uint16_t TransCount,
 978 +                void (*DoneIntCallback)(uint32_t data),
 979 +                void (*UnMaskIntCallback)(uint32_t data));
 980 +
 981 +extern int GdmaMaskChannel(uint32_t ChNum);
 982 +
 983 +extern int GdmaUnMaskChannel(uint32_t ChNum);
 984 +
 985 +/* internal functions declarations */
 986 +irqreturn_t i2s_irq_isr(int irq, void *irqaction);
 987 +int i2s_debug_cmd(unsigned int cmd, unsigned long arg);
 988 +
 989 +/* forward declarations for _fops */
 990 +#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,35)
 991 +static long i2s_ioctl(struct file *file, unsigned int cmd, unsigned long arg);
 992 +#else
 993 +static int i2s_ioctl(struct inode *inode, struct file *file, unsigned int cmd, unsigned long arg);
 994 +#endif
 995 +static int i2s_mmap(struct file *file, struct vm_area_struct *vma);
 996 +static int i2s_open(struct inode *inode, struct file *file);
 997 +static int i2s_release(struct inode *inode, struct file *file);
 998 +int i2s_mmap_alloc(unsigned long size);
 999 +int i2s_mmap_remap(struct vm_area_struct *vma, unsigned long size);
1000 +
1001 +/* global varable definitions */
1002 +i2s_config_type i2s_config;
1003 +i2s_status_type i2s_status;
1004 +i2s_config_type* pi2s_config = &i2s_config;;
1005 +i2s_status_type* pi2s_status = &i2s_status;;
1006 +
1007 +static inline long
1008 +ugly_hack_sleep_on_timeout(wait_queue_head_t *q, long timeout)
1009 +{
1010 +       unsigned long flags;
1011 +       wait_queue_t wait;
1012 +
1013 +       init_waitqueue_entry(&wait, current);
1014 +
1015 +       __set_current_state(TASK_INTERRUPTIBLE);
1016 +       spin_lock_irqsave(&q->lock, flags);
1017 +       __add_wait_queue(q, &wait);
1018 +       spin_unlock(&q->lock);
1019 +
1020 +       timeout = schedule_timeout(timeout);
1021 +
1022 +       spin_lock_irq(&q->lock);
1023 +       __remove_wait_queue(q, &wait);
1024 +       spin_unlock_irqrestore(&q->lock, flags);
1025 +
1026 +       return timeout;
1027 +}
1028 +
1029 +#define interruptible_sleep_on(x) \
1030 +       ugly_hack_sleep_on_timeout(x, MAX_SCHEDULE_TIMEOUT);
1031 +
1032 +
1033 +#if defined(ARM_ARCH)
1034 +static dma_addr_t i2s_txdma_addr0, i2s_txdma_addr1;
1035 +static dma_addr_t i2s_rxdma_addr0, i2s_rxdma_addr1;
1036 +#define I2S_TX_FIFO_WREG_PHY (I2S_TX_FIFO_WREG & 0x1FFFFFFF)
1037 +#define I2S_RX_FIFO_RREG_PHY (I2S_RX_FIFO_RREG & 0x1FFFFFFF)
1038 +#else
1039 +static dma_addr_t i2s_txdma_addr, i2s_rxdma_addr;
1040 +#endif
1041 +static dma_addr_t i2s_mmap_addr[MAX_I2S_PAGE*2];
1042 +                                     /* 8khz 11.025khz 12khz  16khz 22.05khz 24Khz  32khz 44.1khz 48khz 88.2khz 96khz*/
1043 +unsigned long i2s_inclk_15p625Mhz[11] = {60<<8, 43<<8,  40<<8, 30<<8, 21<<8,  19<<8, 14<<8, 10<<8, 9<<8,  7<<8,  4<<8};
1044 +unsigned long i2s_exclk_12p288Mhz[11] = {47<<8, 34<<8,  31<<8, 23<<8, 16<<8,  15<<8, 11<<8,  8<<8, 7<<8,  5<<8,  3<<8};
1045 +unsigned long i2s_exclk_12Mhz[11]     = {46<<8, 33<<8,  30<<8, 22<<8, 16<<8,  15<<8, 11<<8,  8<<8, 7<<8,  5<<8,  3<<8};
1046 +#if defined(CONFIG_I2S_WM8750) || defined(CONFIG_SND_SOC_WM8750)
1047 +                                       /* 8k  11.025k  12k   16k  22.05k  24k  32k   44.1k   48k  88.2k   96k*/
1048 +unsigned long i2s_codec_12p288Mhz[11]  = {0x0C,  0x00, 0x10, 0x14,  0x38, 0x38, 0x18,  0x20, 0x00,  0x00, 0x1C};
1049 +unsigned long i2s_codec_12Mhz[11]      = {0x0C,  0x32, 0x10, 0x14,  0x37, 0x38, 0x18,  0x22, 0x00,  0x3E, 0x1C};
1050 +unsigned long i2s_codec_24p576Mhz[11]  = {0x4C,  0x00, 0x50, 0x54,  0x00, 0x78, 0x58,  0x00, 0x40,  0x00, 0x5C};
1051 +unsigned long i2s_codec_18p432Mhz[11]  = {0x0e,  0x32, 0x12, 0x16,  0x36, 0x3a, 0x1a,  0x22, 0x02,  0x3e, 0x1e};
1052 +#endif
1053 +#if defined(CONFIG_I2S_WM8751) || defined(CONFIG_SND_SOC_WM8751)
1054 +unsigned long i2s_codec_12p288Mhz[11]  = {0x04,  0x00, 0x10, 0x14,  0x38, 0x38, 0x18,  0x20, 0x00,  0x00, 0x1C};
1055 +unsigned long i2s_codec_12Mhz[11]      = {0x04,  0x32, 0x10, 0x14,  0x37, 0x38, 0x18,  0x22, 0x00,  0x3E, 0x1C};
1056 +#endif
1057 +#if defined(CONFIG_I2S_WM8960) || defined(CONFIG_SND_SOC_WM8960)
1058 +unsigned long i2s_codec_12p288Mhz[11]  = {0x36,  0x24, 0x24, 0x1b,  0x12, 0x12, 0x09,  0x00, 0x00,  0x00, 0x00};
1059 +unsigned long i2s_codec_12Mhz[11]      = {0x36,  0x24, 0x24, 0x1b,  0x12, 0x12, 0x09,  0x00, 0x00,  0x00, 0x00};
1060 +#endif
1061 +EXPORT_SYMBOL(i2s_codec_12p288Mhz);
1062 +EXPORT_SYMBOL(i2s_codec_12Mhz);
1063 +
1064 +#if defined(CONFIG_RALINK_RT6855A)
1065 +                                  /* 8K  11.025k  12k   16k  22.05k   24k   32k  44.1K   48k  88.2k  96k */
1066 +unsigned long i2s_inclk_int[11]  = {  97,    70,    65,   48,    35,    32,   24,   17,    16,   12,    8};
1067 +unsigned long i2s_inclk_comp[11] = { 336,   441,    53,  424,   220,   282,  212,  366,   141,  185,   70};
1068 +#elif defined (CONFIG_RALINK_MT7621)
1069 +#ifdef MT7621_ASIC_BOARD
1070 +#if defined (CONFIG_I2S_MCLK_12P288MHZ)
1071 +unsigned long i2s_inclk_int[11]  = { 576,   384,    0,   288,   192,   192,  144,   96,    96,   48,   48};
1072 +unsigned long i2s_inclk_comp[11] = {   0,     0,    0,     0,     0,     0,    0,    0,     0,    0,    0};
1073 +#elif defined(CONFIG_I2S_MCLK_12MHZ)
1074 +unsigned long i2s_inclk_int[11] =  {1171,   850,    0,   585,   425,   390,  292,  212,   195,   106,   97};
1075 +unsigned long i2s_inclk_comp[11] = { 448,   174,    0,   480,    87,   320,  496,  299,   160,   149,  336};
1076 +#endif
1077 +#else //MT7621_FPGA_BOARD
1078 +unsigned long i2s_inclk_int[11] =  { 529,   384,    0,   264,   192,   176,  132,   96,    88,    48,   44};
1079 +unsigned long i2s_inclk_comp[11] = { 102,     0,    0,   307,     0,   204,  153,    0,   102,     0,   51};
1080 +#endif
1081 +#elif defined (CONFIG_RALINK_MT7628)
1082 +#ifdef MT7628_ASIC_BOARD
1083 +                                      /* 8K  11.025k 12k  16k 22.05k 24k  32k 44.1K  48k  88.2k 96k  176k 192k */
1084 +unsigned long i2s_inclk_int_16bit[13] = {937,  680,   0,  468,  340, 312, 234, 170,  156,   85, 78,   42,  39};
1085 +unsigned long i2s_inclk_comp_16bit[13]= {256,  139,   0,  384,   69, 256, 192,  34,  128,   17, 64,  267,  32};
1086 +unsigned long i2s_inclk_int_24bit[13] = {625,  404,   0,  312,  226, 208, 156, 113,  104,   56, 52,   28,  26};
1087 +unsigned long i2s_inclk_comp_24bit[13]= {  0,  404,   0,  256,  387, 170, 128, 193,   85,  352, 42,  176,  21};
1088 +#else
1089 +                                     /* 8K  11.025k 12k  16k 22.05k 24k  32k 44.1K  48k  88.2k 96k  176k 192k */
1090 +unsigned long i2s_inclk_int_16bit[13] = {468,  340,   0,  234,  170, 156, 117,  85,   78,   42, 39,   21,  19};
1091 +unsigned long i2s_inclk_comp_16bit[13]= {384,   69,   0,  192,   34, 128,  96,  17,   64,  264, 32,  133, 272};
1092 +unsigned long i2s_inclk_int_24bit[13] = {312,  202,   0,  156,  113, 104,  78,  56,   52,   28, 26,   14,  13};
1093 +unsigned long i2s_inclk_comp_24bit[13]= {256,  202,   0,  128,  193,  85,  64, 352,   42,  176,  21,  88,  10};
1094 +#endif
1095 +#elif defined (CONFIG_ARCH_MT7623)
1096 +#if defined MT7623_ASIC_BOARD
1097 +                                     /* 8K  11.025k 12k  16k 22.05k 24k  32k 44.1K  48k  88.2k 96k  176k 192k */
1098 +unsigned long i2s_inclk_int_16bit[13] = {576,  384,   0,  288,  192, 192, 144,  96,  96,    48, 48,   24,  24};
1099 +unsigned long i2s_inclk_comp_16bit[13]= { 0,    0,    0,    0,   0,    0,   0,   0,   0,     0,  0,    0,   0};
1100 +unsigned long i2s_inclk_int_24bit[13] = {384,  256,   0,  192,  128, 128,  96,  64,  64,    32, 32,   16,  16};
1101 +unsigned long i2s_inclk_comp_24bit[13]= { 0,    0,    0,    0,   0,    0,   0,   0,   0,     0,  0,    0,   0};
1102 +#else
1103 +                                     /* 8K  11.025k 12k  16k 22.05k 24k  32k 44.1K  48k  88.2k 96k  176k 192k */
1104 +unsigned long i2s_inclk_int_16bit[13] = {72,   48,    0,   36,  24,   24,  18,  12,   12,    6,  6,    3,   3};
1105 +unsigned long i2s_inclk_comp_16bit[13]= { 0,    0,    0,    0,   0,    0,   0,   0,    0,    0,  0,    0,   0};
1106 +unsigned long i2s_inclk_int_24bit[13] = {48,   32,    0,   24,  16,   16,  12,   8,    8,    4,  4,    2,   2};
1107 +unsigned long i2s_inclk_comp_24bit[13]= { 0,    0,    0,    0,   0,    0,   0,   0,    0,    0,  0,    0,   0};
1108 +#endif
1109 +#else
1110 +                                 /* 8K  11.025k 12k  16k  22.05k  24k  32k  44.1K  48k  88.2k  96k */
1111 +unsigned long i2s_inclk_int[11]  = { 78,    56,   52,  39,   28,    26,  19,   14,   13,   9,    6};
1112 +unsigned long i2s_inclk_comp[11] = { 64,   352,   42,  32,  176,    21, 272,   88,   10, 455,  261};
1113 +#endif
1114 +
1115 +#if defined(CONFIG_I2S_WITH_AEC)
1116 +aecFuncTbl_t *aecFuncP;
1117 +#endif
1118 +/* USB mode 22.05Khz register value in datasheet is 0x36 but will cause slow clock, 0x37 is correct value */
1119 +/* USB mode 44.1Khz register value in datasheet is 0x22 but will cause slow clock, 0x23 is correct value */
1120 +
1121 +struct tasklet_struct i2s_tx_tasklet;
1122 +struct tasklet_struct i2s_rx_tasklet;
1123 +EXPORT_SYMBOL(i2s_tx_tasklet);
1124 +EXPORT_SYMBOL(i2s_rx_tasklet);
1125 +
1126 +char test_buf[I2S_PAGE_SIZE];
1127 +char test_buf_1[I2S_PAGE_SIZE];
1128 +char test_buf_2[I2S_PAGE_SIZE];
1129 +
1130 +static const struct file_operations i2s_fops = {
1131 +       owner           : THIS_MODULE,
1132 +       mmap            : i2s_mmap,
1133 +       open            : i2s_open,
1134 +       release         : i2s_release,
1135 +#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,35)
1136 +       unlocked_ioctl:     i2s_ioctl,
1137 +#else
1138 +       ioctl           : i2s_ioctl,
1139 +#endif
1140 +};
1141 +
1142 +int __init i2s_mod_init(void)
1143 +{
1144 +       int result;
1145 +
1146 +       _printk("******* i2s module init **********\n");
1147 +       /* register device with kernel */
1148 +#ifdef  CONFIG_DEVFS_FS
1149 +       if(devfs_register_chrdev(i2sdrv_major, I2SDRV_DEVNAME , &i2s_fops)) {
1150 +               _printk(KERN_WARNING " i2s: can't create device node - %s\n", I2SDRV_DEVNAME);
1151 +               return -EIO;
1152 +       }
1153 +
1154 +       devfs_handle = devfs_register(NULL, I2SDRV_DEVNAME, DEVFS_FL_DEFAULT, i2sdrv_major, 0,
1155 +           S_IFCHR | S_IRUGO | S_IWUGO, &i2s_fops, NULL);
1156 +#else
1157 +       result = register_chrdev(i2sdrv_major, I2SDRV_DEVNAME, &i2s_fops);
1158 +       if (result < 0) {
1159 +               _printk(KERN_WARNING "i2s: can't get major %d\n",i2sdrv_major);
1160 +               return result;
1161 +       }
1162 +
1163 +       if (i2sdrv_major == 0) {
1164 +               i2sdrv_major = result; /* dynamic */
1165 +       }
1166 +#endif
1167 +
1168 +#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,35)
1169 +#else
1170 +       i2smodule_class=class_create(THIS_MODULE, I2SDRV_DEVNAME);
1171 +       if (IS_ERR(i2smodule_class))
1172 +               return -EFAULT;
1173 +       device_create(i2smodule_class, NULL, MKDEV(i2sdrv_major, 0), I2SDRV_DEVNAME);
1174 +#endif
1175 +
1176 +#if defined(CONFIG_I2S_WITH_AEC)
1177 +       _printk("AEC FuncP init \n");
1178 +       /*Add by mtk04880*/
1179 +       aecFuncP = kmalloc(sizeof(aecFuncTbl_t), GFP_KERNEL);
1180 +       /*If aecFuncP cannot request memory,it will be ignored in I2S module. Since AEC & I2S are independent
1181 +        * when AEC module is inserted,It will return err message (but I2S will keep running without AEC support)
1182 +        * */
1183 +       if(aecFuncP){
1184 +               memset(aecFuncP,0,sizeof(aecFuncTbl_t));
1185 +       }
1186 +#endif
1187 +
1188 +       return 0;
1189 +}
1190 +
1191 +void i2s_mod_exit(void)
1192 +{
1193 +       _printk("************ i2s module exit *************\n");
1194 +#ifdef  CONFIG_DEVFS_FS
1195 +       devfs_unregister_chrdev(i2sdrv_major, I2SDRV_DEVNAME);
1196 +       devfs_unregister(devfs_handle);
1197 +#else
1198 +       unregister_chrdev(i2sdrv_major, I2SDRV_DEVNAME);
1199 +#endif
1200 +#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,35)
1201 +#else
1202 +       device_destroy(i2smodule_class,MKDEV(i2sdrv_major, 0));
1203 +       class_destroy(i2smodule_class);
1204 +#endif
1205 +       return ;
1206 +}
1207 +
1208 +
1209 +int i2s_open(struct inode *inode, struct file *filp)
1210 +{
1211 +#if defined(I2S_HW_INTERRUPT_EN)&&(I2S_SW_IRQ_EN)
1212 +       int Ret;
1213 +#endif
1214 +       int minor = iminor(inode);
1215 +
1216 +       if (minor >= I2S_MAX_DEV)
1217 +               return -ENODEV;
1218 +
1219 +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0)
1220 +       MOD_INC_USE_COUNT;
1221 +#else
1222 +       try_module_get(THIS_MODULE);
1223 +#endif
1224 +
1225 +       if (filp->f_flags & O_NONBLOCK) {
1226 +               MSG("filep->f_flags O_NONBLOCK set\n");
1227 +               return -EAGAIN;
1228 +       }
1229 +
1230 +       /* set i2s_config */
1231 +       filp->private_data = pi2s_config;
1232 +       memset(pi2s_config, 0, sizeof(i2s_config_type));
1233 +#ifdef I2S_STATISTIC
1234 +       memset(pi2s_status, 0, sizeof(i2s_status_type));
1235 +#endif
1236 +       i2s_param_init(pi2s_config);
1237 +
1238 +#if defined(I2S_HW_INTERRUPT_EN)&&(I2S_SW_IRQ_EN)
1239 +#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,35)
1240 +       Ret = request_irq(SURFBOARDINT_I2S, i2s_irq_isr, IRQF_DISABLED, "Ralink_I2S", NULL);
1241 +#else
1242 +       Ret = request_irq(SURFBOARDINT_I2S, i2s_irq_isr, SA_INTERRUPT, "Ralink_I2S", NULL);
1243 +#endif
1244 +
1245 +       if(Ret){
1246 +               MSG("IRQ %d is not free.\n", SURFBOARDINT_I2S);
1247 +               i2s_release(inode, filp);
1248 +               return -1;
1249 +       }
1250 +#endif
1251 +
1252 +       init_waitqueue_head(&(pi2s_config->i2s_tx_qh));
1253 +       init_waitqueue_head(&(pi2s_config->i2s_rx_qh));
1254 +       spin_lock_init(&pi2s_config->lock);
1255 +
1256 +       return 0;
1257 +}
1258 +
1259 +
1260 +static int i2s_release(struct inode *inode, struct file *filp)
1261 +{
1262 +       i2s_config_type* ptri2s_config;
1263 +
1264 +       /* decrement usage count */
1265 +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0)
1266 +       MOD_DEC_USE_COUNT;
1267 +#else
1268 +       module_put(THIS_MODULE);
1269 +#endif
1270 +
1271 +#if defined(I2S_HW_INTERRUPT_EN)&&(I2S_SW_IRQ_EN)
1272 +       free_irq(SURFBOARDINT_I2S, NULL);
1273 +#endif
1274 +
1275 +       ptri2s_config = filp->private_data;
1276 +       if(ptri2s_config==NULL)
1277 +               goto EXIT;
1278 +#ifdef CONFIG_I2S_MMAP
1279 +       i2s_mem_unmap(ptri2s_config);
1280 +#else
1281 +       i2s_txbuf_free(ptri2s_config);
1282 +       i2s_rxbuf_free(ptri2s_config);
1283 +#endif
1284 +       /* free buffer */
1285 +       i2s_txPagebuf_free(ptri2s_config);
1286 +       i2s_rxPagebuf_free(ptri2s_config);
1287 +EXIT:
1288 +       MSG("i2s_release succeeds\n");
1289 +       return 0;
1290 +}
1291 +
1292 +int i2s_mmap_alloc(unsigned long size)
1293 +{
1294 +       int i;
1295 +       u32 page_size;
1296 +               int first_index;
1297 +
1298 +       page_size = I2S_PAGE_SIZE;
1299 +
1300 +       if ((pi2s_config->mmap_index == 0) || (pi2s_config->mmap_index == MAX_I2S_PAGE))
1301 +       {
1302 +               MSG("mmap_index=%d\n", pi2s_config->mmap_index);
1303 +
1304 +               first_index = pi2s_config->mmap_index;
1305 +       pi2s_config->pMMAPBufPtr[pi2s_config->mmap_index] = kmalloc(size, GFP_DMA);
1306 +       i2s_mmap_addr[pi2s_config->mmap_index] = (dma_addr_t)dma_map_single(NULL, pi2s_config->pMMAPBufPtr[pi2s_config->mmap_index], size, DMA_BIDIRECTIONAL);
1307 +
1308 +       if( pi2s_config->pMMAPBufPtr[pi2s_config->mmap_index] == NULL )
1309 +       {
1310 +               MSG("i2s_mmap failed\n");
1311 +               return -1;
1312 +       }
1313 +       }
1314 +       else
1315 +       {
1316 +               _printk("illegal index:%d\n", pi2s_config->mmap_index);
1317 +               return -1;
1318 +       }
1319 +
1320 +       _printk("MMAP[%d]=0x%08X, i2s_mmap_addr[%d]=0x%08x\n",
1321 +               pi2s_config->mmap_index, (u32)pi2s_config->pMMAPBufPtr[pi2s_config->mmap_index],
1322 +                pi2s_config->mmap_index, i2s_mmap_addr[pi2s_config->mmap_index]);
1323 +
1324 +       memset(pi2s_config->pMMAPBufPtr[pi2s_config->mmap_index], 0, size);
1325 +       pi2s_config->mmap_index++;
1326 +
1327 +       for (i=1; i<MAX_I2S_PAGE; i++)
1328 +       {
1329 +               i2s_mmap_addr[pi2s_config->mmap_index] = i2s_mmap_addr[first_index] + i*page_size;
1330 +               pi2s_config->pMMAPBufPtr[pi2s_config->mmap_index] = pi2s_config->pMMAPBufPtr[first_index] + i*page_size;
1331 +
1332 +               _printk("MMAP[%d]=0x%08X, i2s_mmap_addr[%d]=0x%08x\n",pi2s_config->mmap_index, (u32)pi2s_config->pMMAPBufPtr[pi2s_config->mmap_index], pi2s_config->mmap_index, i2s_mmap_addr[pi2s_config->mmap_index]);
1333 +
1334 +               /* Notice: The last mmap_index's value should be MAX_I2S_PAGE or MAX_I2S_PAGE*2 */
1335 +               pi2s_config->mmap_index++;
1336 +       }
1337 +
1338 +       return 0;
1339 +}
1340 +
1341 +int i2s_mmap_remap(struct vm_area_struct *vma, unsigned long size)
1342 +{
1343 +       int nRet;
1344 +
1345 +       if((pi2s_config->pMMAPBufPtr[0]!=NULL) && (pi2s_config->mmap_index == MAX_I2S_PAGE))
1346 +       {
1347 +               MSG("i2s_mmap_remap:0\n");
1348 +               nRet = remap_pfn_range(vma, vma->vm_start, virt_to_phys((void *)pi2s_config->pMMAPBufPtr[0]) >> PAGE_SHIFT,  size, vma->vm_page_prot);
1349 +
1350 +               if( nRet != 0 )
1351 +               {
1352 +                       _printk("i2s_mmap->remap_pfn_range failed\n");
1353 +                       return -EIO;
1354 +               }
1355 +       }
1356 +
1357 +       if((pi2s_config->pMMAPBufPtr[MAX_I2S_PAGE]!=NULL) && (pi2s_config->mmap_index == MAX_I2S_PAGE*2))
1358 +       {
1359 +               MSG("i2s_mmap_remap:%d\n", MAX_I2S_PAGE);
1360 +
1361 +               nRet = remap_pfn_range(vma, vma->vm_start, virt_to_phys((void *)pi2s_config->pMMAPBufPtr[MAX_I2S_PAGE]) >> PAGE_SHIFT,  size, vma->vm_page_prot);
1362 +
1363 +               if( nRet != 0 )
1364 +               {
1365 +                       _printk("i2s_mmap->remap_pfn_range failed\n");
1366 +                       return -EIO;
1367 +               }
1368 +       }
1369 +
1370 +       return 0;
1371 +}
1372 +
1373 +static int i2s_mmap(struct file *filp, struct vm_area_struct *vma)
1374 +{
1375 +       unsigned long size = vma->vm_end-vma->vm_start;
1376 +       _printk("page_size=%d, ksize=%lu\n", I2S_PAGE_SIZE, size);
1377 +
1378 +       if((pi2s_config->pMMAPBufPtr[0]==NULL)&&(pi2s_config->mmap_index!=0))
1379 +               pi2s_config->mmap_index = 0;
1380 +
1381 +       _printk("%s: vm_start=%08X,vm_end=%08X\n", __func__, (u32)vma->vm_start, (u32)vma->vm_end);
1382 +
1383 +       /* Do memory allocate and dma sync */
1384 +       i2s_mmap_alloc(size);
1385 +
1386 +       i2s_mmap_remap(vma, size);
1387 +
1388 +
1389 +       return 0;
1390 +}
1391 +
1392 +int i2s_mem_unmap(i2s_config_type* ptri2s_config)
1393 +{
1394 +       u32 page_size;
1395 +
1396 +       page_size = I2S_PAGE_SIZE;
1397 +
1398 +       if(ptri2s_config->pMMAPBufPtr[0])
1399 +       {
1400 +               _printk("ummap MMAP[0]=0x%08X\n", (u32)ptri2s_config->pMMAPBufPtr[0]);
1401 +               dma_unmap_single(NULL, i2s_mmap_addr[0], MAX_I2S_PAGE*page_size, DMA_BIDIRECTIONAL);
1402 +               kfree(ptri2s_config->pMMAPBufPtr[0]);
1403 +       }
1404 +
1405 +       if(ptri2s_config->pMMAPBufPtr[MAX_I2S_PAGE])
1406 +       {
1407 +               _printk("ummap MMAP[%d]=0x%08X\n", MAX_I2S_PAGE, (u32)ptri2s_config->pMMAPBufPtr[MAX_I2S_PAGE]);
1408 +               dma_unmap_single(NULL, i2s_mmap_addr[MAX_I2S_PAGE], MAX_I2S_PAGE*page_size, DMA_BIDIRECTIONAL);
1409 +               kfree(ptri2s_config->pMMAPBufPtr[MAX_I2S_PAGE]);
1410 +       }
1411 +
1412 +       ptri2s_config->mmap_index = 0;
1413 +
1414 +       return 0;
1415 +}
1416 +
1417 +int i2s_param_init(i2s_config_type* ptri2s_config)
1418 +{
1419 +       ptri2s_config->dmach = GDMA_I2S_TX0;
1420 +       ptri2s_config->tx_ff_thres = CONFIG_I2S_TFF_THRES;
1421 +       ptri2s_config->tx_ch_swap = CONFIG_I2S_CH_SWAP;
1422 +       ptri2s_config->rx_ff_thres = CONFIG_I2S_TFF_THRES;
1423 +       ptri2s_config->rx_ch_swap = CONFIG_I2S_CH_SWAP;
1424 +       ptri2s_config->slave_en = CONFIG_I2S_SLAVE_EN;
1425 +       ptri2s_config->codec_pll_en = CONFIG_I2S_CODEC_PLL_EN;
1426 +
1427 +       ptri2s_config->bRxDMAEnable = 0;
1428 +       ptri2s_config->bTxDMAEnable = 0;
1429 +       //ptri2s_config->bALSAEnable = 0;
1430 +       ptri2s_config->srate = 44100;
1431 +       ptri2s_config->txvol = 0;
1432 +       ptri2s_config->rxvol = 0;
1433 +       ptri2s_config->lbk = 0;
1434 +       ptri2s_config->extlbk = 0;
1435 +       ptri2s_config->txrx_coexist = 0;
1436 +       ptri2s_config->wordlen_24b = 0;
1437 +#if defined(CONFIG_RALINK_MT7628) || defined(CONFIG_ARCH_MT7623)
1438 +       ptri2s_config->sys_endian = 0;
1439 +       ptri2s_config->fmt = 0;
1440 +#endif
1441 +       ptri2s_config->micboost = 0;
1442 +       ptri2s_config->micin = 0;
1443 +
1444 +       return 0;
1445 +}
1446 +
1447 +int i2s_txbuf_alloc(i2s_config_type* ptri2s_config)
1448 +{
1449 +       int i;
1450 +
1451 +       for( i = 0 ; i < MAX_I2S_PAGE ; i ++ )
1452 +        {
1453 +#if defined(CONFIG_I2S_MMAP)
1454 +               ptri2s_config->pMMAPTxBufPtr[i] = ptri2s_config->pMMAPBufPtr[i];
1455 +#else
1456 +                if(ptri2s_config->pMMAPTxBufPtr[i]==NULL)
1457 +                       ptri2s_config->pMMAPTxBufPtr[i] = kmalloc(I2S_PAGE_SIZE, GFP_KERNEL);
1458 +#endif
1459 +               memset(ptri2s_config->pMMAPTxBufPtr[i], 0, I2S_PAGE_SIZE);
1460 +       }
1461 +
1462 +       return 0;
1463 +}
1464 +
1465 +int i2s_rxbuf_alloc(i2s_config_type* ptri2s_config)
1466 +{
1467 +       int i;
1468 +
1469 +       for( i = 0 ; i < MAX_I2S_PAGE ; i ++ )
1470 +        {
1471 +#if defined(CONFIG_I2S_MMAP)
1472 +               ptri2s_config->pMMAPRxBufPtr[i] = ptri2s_config->pMMAPBufPtr[i+(ptri2s_config->mmap_index-MAX_I2S_PAGE)];
1473 +#else
1474 +                if(ptri2s_config->pMMAPRxBufPtr[i]==NULL)
1475 +                       ptri2s_config->pMMAPRxBufPtr[i] = kmalloc(I2S_PAGE_SIZE, GFP_KERNEL);
1476 +#endif
1477 +               memset(ptri2s_config->pMMAPRxBufPtr[i], 0, I2S_PAGE_SIZE);
1478 +        }
1479 +
1480 +       return 0;
1481 +}
1482 +
1483 +int i2s_txPagebuf_alloc(i2s_config_type* ptri2s_config)
1484 +{
1485 +#if defined(ARM_ARCH)
1486 +       ptri2s_config->pPage0TxBuf8ptr = (u8*)pci_alloc_consistent(NULL, I2S_PAGE_SIZE , &i2s_txdma_addr0);
1487 +       ptri2s_config->pPage1TxBuf8ptr = (u8*)pci_alloc_consistent(NULL, I2S_PAGE_SIZE , &i2s_txdma_addr1);
1488 +       if(ptri2s_config->pPage0TxBuf8ptr==NULL)
1489 +        {
1490 +               MSG("Allocate Tx Page0 Buffer Failed\n");
1491 +                return -1;
1492 +        }
1493 +       if(ptri2s_config->pPage1TxBuf8ptr==NULL)
1494 +        {
1495 +               MSG("Allocate Tx Page1 Buffer Failed\n");
1496 +                return -1;
1497 +        }
1498 +#else
1499 +       ptri2s_config->pPage0TxBuf8ptr = (u8*)pci_alloc_consistent(NULL, I2S_PAGE_SIZE*2 , &i2s_txdma_addr);
1500 +        if(ptri2s_config->pPage0TxBuf8ptr==NULL)
1501 +        {
1502 +               MSG("Allocate Tx Page Buffer Failed\n");
1503 +                return -1;
1504 +        }
1505 +        ptri2s_config->pPage1TxBuf8ptr = ptri2s_config->pPage0TxBuf8ptr + I2S_PAGE_SIZE;
1506 +#endif
1507 +       return 0;
1508 +}
1509 +
1510 +int i2s_rxPagebuf_alloc(i2s_config_type* ptri2s_config)
1511 +{
1512 +#if defined(ARM_ARCH)
1513 +       ptri2s_config->pPage0RxBuf8ptr = (u8*)pci_alloc_consistent(NULL, I2S_PAGE_SIZE, &i2s_rxdma_addr0);
1514 +       ptri2s_config->pPage1RxBuf8ptr = (u8*)pci_alloc_consistent(NULL, I2S_PAGE_SIZE, &i2s_rxdma_addr1);
1515 +       if(ptri2s_config->pPage0RxBuf8ptr==NULL)
1516 +       {
1517 +               MSG("Allocate Rx Page Buffer Failed\n");
1518 +               return -1;
1519 +       }
1520 +       if(ptri2s_config->pPage1RxBuf8ptr==NULL)
1521 +       {
1522 +               MSG("Allocate Rx Page Buffer Failed\n");
1523 +               return -1;
1524 +       }
1525 +#else
1526 +       ptri2s_config->pPage0RxBuf8ptr = (u8*)pci_alloc_consistent(NULL, I2S_PAGE_SIZE*2 , &i2s_rxdma_addr);
1527 +       if(ptri2s_config->pPage0RxBuf8ptr==NULL)
1528 +       {
1529 +               MSG("Allocate Rx Page Buffer Failed\n");
1530 +               return -1;
1531 +       }
1532 +       ptri2s_config->pPage1RxBuf8ptr = ptri2s_config->pPage0RxBuf8ptr + I2S_PAGE_SIZE;
1533 +#endif
1534 +       return 0;
1535 +}
1536 +
1537 +int i2s_txbuf_free(i2s_config_type* ptri2s_config)
1538 +{
1539 +       int i;
1540 +
1541 +       for(i = 0 ; i < MAX_I2S_PAGE ; i ++)
1542 +       {
1543 +               if(ptri2s_config->pMMAPTxBufPtr[i] != NULL)
1544 +               {
1545 +#if defined(CONFIG_I2S_MMAP)
1546 +                        ptri2s_config->pMMAPTxBufPtr[i] = NULL;
1547 +#else
1548 +                       kfree(ptri2s_config->pMMAPTxBufPtr[i]);
1549 +                       ptri2s_config->pMMAPTxBufPtr[i] = NULL;
1550 +#endif
1551 +               }
1552 +       }
1553 +       return 0;
1554 +}
1555 +
1556 +int i2s_rxbuf_free(i2s_config_type* ptri2s_config)
1557 +{
1558 +       int i;
1559 +
1560 +       for(i = 0 ; i < MAX_I2S_PAGE ; i ++)
1561 +       {
1562 +               if(ptri2s_config->pMMAPRxBufPtr[i] != NULL)
1563 +               {
1564 +#if defined(CONFIG_I2S_MMAP)
1565 +                        ptri2s_config->pMMAPRxBufPtr[i] = NULL;
1566 +#else
1567 +                       kfree(ptri2s_config->pMMAPRxBufPtr[i]);
1568 +                       ptri2s_config->pMMAPRxBufPtr[i] = NULL;
1569 +#endif
1570 +               }
1571 +       }
1572 +
1573 +       return 0;
1574 +}
1575 +
1576 +int i2s_txPagebuf_free(i2s_config_type* ptri2s_config)
1577 +{
1578 +#if defined(ARM_ARCH)
1579 +       if (ptri2s_config->pPage0TxBuf8ptr)
1580 +       {
1581 +               pci_free_consistent(NULL, I2S_PAGE_SIZE, ptri2s_config->pPage0TxBuf8ptr, i2s_txdma_addr0);
1582 +               ptri2s_config->pPage0TxBuf8ptr = NULL;
1583 +       }
1584 +
1585 +       if (ptri2s_config->pPage1TxBuf8ptr)
1586 +       {
1587 +               pci_free_consistent(NULL, I2S_PAGE_SIZE, ptri2s_config->pPage1TxBuf8ptr, i2s_txdma_addr1);
1588 +               ptri2s_config->pPage1TxBuf8ptr = NULL;
1589 +       }
1590 +       _printk("Free tx page buffer\n");
1591 +#else
1592 +       if (ptri2s_config->pPage0TxBuf8ptr)
1593 +       {
1594 +               pci_free_consistent(NULL, I2S_PAGE_SIZE*2, ptri2s_config->pPage0TxBuf8ptr, i2s_txdma_addr);
1595 +               ptri2s_config->pPage0TxBuf8ptr = NULL;
1596 +       }
1597 +#endif
1598 +       return 0;
1599 +
1600 +}
1601 +
1602 +int i2s_rxPagebuf_free(i2s_config_type* ptri2s_config)
1603 +{
1604 +#if defined(ARM_ARCH)
1605 +       if (ptri2s_config->pPage0RxBuf8ptr)
1606 +       {
1607 +               pci_free_consistent(NULL, I2S_PAGE_SIZE, ptri2s_config->pPage0RxBuf8ptr, i2s_rxdma_addr0);
1608 +               ptri2s_config->pPage0RxBuf8ptr = NULL;
1609 +       }
1610 +       if (ptri2s_config->pPage1RxBuf8ptr)
1611 +       {
1612 +               pci_free_consistent(NULL, I2S_PAGE_SIZE, ptri2s_config->pPage1RxBuf8ptr, i2s_rxdma_addr1);
1613 +               ptri2s_config->pPage1RxBuf8ptr = NULL;
1614 +       }
1615 +       _printk("Free rx page buffer\n");
1616 +#else
1617 +       if (ptri2s_config->pPage0RxBuf8ptr)
1618 +       {
1619 +               pci_free_consistent(NULL, I2S_PAGE_SIZE*2, ptri2s_config->pPage0RxBuf8ptr, i2s_rxdma_addr);
1620 +               ptri2s_config->pPage0RxBuf8ptr = NULL;
1621 +       }
1622 +#endif
1623 +       return 0;
1624 +}
1625 +
1626 +int i2s_reset_tx_param(i2s_config_type* ptri2s_config)
1627 +{
1628 +       ptri2s_config->tx_isr_cnt = 0;
1629 +       ptri2s_config->tx_w_idx = 0;
1630 +       ptri2s_config->tx_r_idx = 0;
1631 +       ptri2s_config->enLable = 0;
1632 +       ptri2s_config->tx_pause_en = 0;
1633 +       ptri2s_config->end_cnt = 0;
1634 +       ptri2s_config->tx_stop_cnt = 0;
1635 +
1636 +#ifdef I2S_STATISTIC
1637 +       pi2s_status->txbuffer_unrun = 0;
1638 +       pi2s_status->txbuffer_ovrun = 0;
1639 +       pi2s_status->txdmafault = 0;
1640 +       pi2s_status->txovrun = 0;
1641 +       pi2s_status->txunrun = 0;
1642 +       pi2s_status->txthres = 0;
1643 +       pi2s_status->txbuffer_len = 0;
1644 +#endif
1645 +
1646 +       return 0;
1647 +}
1648 +
1649 +int i2s_reset_rx_param(i2s_config_type* ptri2s_config)
1650 +{
1651 +       ptri2s_config->rx_isr_cnt = 0;
1652 +       ptri2s_config->rx_w_idx = 0;
1653 +       ptri2s_config->rx_r_idx = 0;
1654 +       ptri2s_config->enLable = 0;
1655 +       ptri2s_config->rx_pause_en = 0;
1656 +       ptri2s_config->rx_stop_cnt = 0;
1657 +
1658 +#ifdef I2S_STATISTIC
1659 +       pi2s_status->rxbuffer_unrun = 0;
1660 +       pi2s_status->rxbuffer_ovrun = 0;
1661 +       pi2s_status->rxdmafault = 0;
1662 +       pi2s_status->rxovrun = 0;
1663 +       pi2s_status->rxunrun = 0;
1664 +       pi2s_status->rxthres = 0;
1665 +       pi2s_status->rxbuffer_len = 0;
1666 +#endif
1667 +
1668 +       return 0;
1669 +}
1670 +#ifdef MT7621_ASIC_BOARD
1671 +int i2s_pll_config_mt7621(unsigned long index)
1672 +{
1673 +        unsigned long data;
1674 +       unsigned long regValue;
1675 +       bool xtal_20M_en = 0;
1676 +//     bool xtal_25M_en = 0;
1677 +       bool xtal_40M_en = 0;
1678 +
1679 +       regValue = i2s_inw(RALINK_SYSCTL_BASE + 0x10);
1680 +               regValue = (regValue >> 6) & 0x7;
1681 +       if (regValue < 3)
1682 +       {
1683 +               xtal_20M_en = 1;
1684 +               MSG("Xtal is 20MHz. \n");
1685 +       }
1686 +       else if (regValue < 6)
1687 +       {
1688 +               xtal_40M_en = 1;
1689 +               MSG("Xtal is 40M.\n");
1690 +       }
1691 +       else
1692 +       {
1693 +               //xtal_25M_en = 1;
1694 +               MSG("Xtal is 25M.\n");
1695 +       }
1696 +
1697 +#if defined (CONFIG_I2S_MCLK_12P288MHZ)
1698 +       _printk("MT7621 provide 12.288M/11.298MHz REFCLK\n");
1699 +       /* Firstly, reset all required register to default value */
1700 +       i2s_outw(RALINK_ANA_CTRL_BASE, 0x00008000);
1701 +       i2s_outw(RALINK_ANA_CTRL_BASE+0x0014, 0x01001d61);//0x01401d61);
1702 +       i2s_outw(RALINK_ANA_CTRL_BASE+0x0018, 0x38233d0e);
1703 +       i2s_outw(RALINK_ANA_CTRL_BASE+0x001c, 0x80100004);//0x80120004);
1704 +       i2s_outw(RALINK_ANA_CTRL_BASE+0x0020, 0x1c7dbf48);
1705 +
1706 +        /* toggle RG_XPTL_CHG */
1707 +        i2s_outw(RALINK_ANA_CTRL_BASE, 0x00008800);
1708 +        i2s_outw(RALINK_ANA_CTRL_BASE, 0x00008c00);
1709 +
1710 +        data = i2s_inw(RALINK_ANA_CTRL_BASE+0x0014);
1711 +        data &= ~(0x0000ffc0);
1712 +       if ((xtal_40M_en) || (xtal_20M_en))
1713 +       {
1714 +               data |= REGBIT(0x1d, 8); /* for 40M or 20M */
1715 +       }
1716 +       else
1717 +       {
1718 +               data |= REGBIT(0x17, 8); /* for 25M */
1719 +       }
1720 +
1721 +       if (xtal_40M_en)
1722 +       {
1723 +               data |= REGBIT(0x1, 6);  /* for 40M */
1724 +       }
1725 +       i2s_outw(RALINK_ANA_CTRL_BASE+0x0014, data);
1726 +
1727 +
1728 +        data = i2s_inw(RALINK_ANA_CTRL_BASE+0x0018);
1729 +        data &= ~(0xf0773f00);
1730 +        data |= REGBIT(0x3, 28);
1731 +        data |= REGBIT(0x2, 20);
1732 +       if ((xtal_40M_en) || (xtal_20M_en))
1733 +       {
1734 +               data |= REGBIT(0x3, 16); /* for 40M or 20M */
1735 +       }
1736 +       else
1737 +       {
1738 +               data |= REGBIT(0x2, 16); /* for 25M */
1739 +       }
1740 +        data |= REGBIT(0x3, 12);
1741 +       if ((xtal_40M_en) || (xtal_20M_en))
1742 +       {
1743 +               data |= REGBIT(0xd, 8); /* for 40M or 20M */
1744 +       }
1745 +       else
1746 +       {
1747 +               data |= REGBIT(0x7, 8); /* for 25M */
1748 +       }
1749 +        i2s_outw(RALINK_ANA_CTRL_BASE+0x0018, data);
1750 +
1751 +        if((index==1)|(index==4)|(index==7)|(index==9))// 270 MHz for 22.05K, 44.1K, 88.2K, 176.4K
1752 +        {
1753 +               if ((xtal_40M_en) || (xtal_20M_en))
1754 +               {
1755 +                       i2s_outw(RALINK_ANA_CTRL_BASE+0x0020, 0x1a18548a); /* for 40M or 20M */
1756 +               }
1757 +               else
1758 +               {
1759 +                       i2s_outw(RALINK_ANA_CTRL_BASE+0x0020, 0x14ad106e); /* for 25M */
1760 +               }
1761 +        }
1762 +        else if ((index==0)|(index==3)|(index==5)|(index==6)|(index==8)|(index==10))// 294 MHZ for 24K, 48K, 96K, 192K
1763 +        {
1764 +               if ((xtal_40M_en) || (xtal_20M_en))
1765 +               {
1766 +                       i2s_outw(RALINK_ANA_CTRL_BASE+0x0020, 0x1c7dbf48); /* for 40M or 20M */
1767 +               }
1768 +               else
1769 +               {
1770 +                       i2s_outw(RALINK_ANA_CTRL_BASE+0x0020, 0x1697cc39); /* for 25M */
1771 +               }
1772 +        }
1773 +       else if (index==2)
1774 +       {
1775 +               _printk("Not support 12KHz sampling rate!\n");
1776 +               return -1;
1777 +       }
1778 +        else
1779 +        {
1780 +                _printk("Wrong sampling rate!\n");
1781 +                return -1;
1782 +        }
1783 +
1784 +        //*Common setting - Set PLLGP_CTRL_4 *//
1785 +       /* 1. Bit 31 */
1786 +        data = i2s_inw(RALINK_ANA_CTRL_BASE+0x001c);
1787 +        data &= ~(REGBIT(0x1, 31));
1788 +        i2s_outw(RALINK_ANA_CTRL_BASE+0x001c, data);
1789 +       ndelay(10);
1790 +
1791 +        /* 2. Bit 0 */
1792 +        data = i2s_inw(RALINK_ANA_CTRL_BASE+0x001c);
1793 +        data |= REGBIT(0x1, 0);
1794 +        i2s_outw(RALINK_ANA_CTRL_BASE+0x001c, data);
1795 +       udelay(200);
1796 +
1797 +        /* 3. Bit 3 */
1798 +        data = i2s_inw(RALINK_ANA_CTRL_BASE+0x001c);
1799 +        data |= REGBIT(0x1, 3);
1800 +        i2s_outw(RALINK_ANA_CTRL_BASE+0x001c, data);
1801 +       udelay(1);
1802 +
1803 +        /* 4. Bit 8 */
1804 +        data = i2s_inw(RALINK_ANA_CTRL_BASE+0x001c);
1805 +        data |= REGBIT(0x1, 8);
1806 +        i2s_outw(RALINK_ANA_CTRL_BASE+0x001c, data);
1807 +       ndelay(40);
1808 +
1809 +        /* 5. Bit 6 */
1810 +        data = i2s_inw(RALINK_ANA_CTRL_BASE+0x001c);
1811 +        data |= REGBIT(0x1, 6);
1812 +        i2s_outw(RALINK_ANA_CTRL_BASE+0x001c, data);
1813 +       ndelay(40);
1814 +
1815 +        /* 6. Bit 5 & Bit 7*/
1816 +        data = i2s_inw(RALINK_ANA_CTRL_BASE+0x001c);
1817 +        data |= REGBIT(0x1, 5);
1818 +       data |= REGBIT(0x1, 7);
1819 +        i2s_outw(RALINK_ANA_CTRL_BASE+0x001c, data);
1820 +       udelay(1);
1821 +
1822 +        /* 7. Bit 17 */
1823 +        data = i2s_inw(RALINK_ANA_CTRL_BASE+0x001c);
1824 +        data |= REGBIT(0x1, 17);
1825 +        i2s_outw(RALINK_ANA_CTRL_BASE+0x001c, data);
1826 +
1827 +#elif defined(CONFIG_I2S_MCLK_12MHZ)
1828 +       _printk("MT7621 provide 12MHz REFCLK\n");
1829 +       /* Firstly, reset all required register to default value */
1830 +       i2s_outw(RALINK_ANA_CTRL_BASE+0x0014, 0x01401d61);//0x01401d61);
1831 +       i2s_outw(RALINK_ANA_CTRL_BASE+0x001c, 0x80120004);//0x80100004);
1832 +       i2s_outw(RALINK_ANA_CTRL_BASE+0x0018, 0x38233d0e);
1833 +
1834 +       if (xtal_40M_en)
1835 +       {
1836 +               data = i2s_inw(RALINK_ANA_CTRL_BASE+0x001c);
1837 +               data &= ~REGBIT(0x1, 17);
1838 +               i2s_outw(RALINK_ANA_CTRL_BASE+0x001c, data);
1839 +
1840 +               data = i2s_inw(RALINK_ANA_CTRL_BASE+0x0014);
1841 +               data &= ~REGBIT(0x3, 4);
1842 +               data |= REGBIT(0x1, 4);
1843 +               i2s_outw(RALINK_ANA_CTRL_BASE+0x0014, data);
1844 +
1845 +               data = i2s_inw(RALINK_ANA_CTRL_BASE+0x001c);
1846 +               data &= ~REGBIT(0x1, 31);
1847 +               i2s_outw(RALINK_ANA_CTRL_BASE+0x001c, data);
1848 +       }
1849 +       else if (xtal_20M_en)
1850 +       {
1851 +               data = i2s_inw(RALINK_ANA_CTRL_BASE+0x001c);
1852 +               data &= ~REGBIT(0x1, 17);
1853 +               i2s_outw(RALINK_ANA_CTRL_BASE+0x001c, data);
1854 +
1855 +               data = i2s_inw(RALINK_ANA_CTRL_BASE+0x0014);
1856 +               data &= ~REGBIT(0x3, 6);
1857 +               i2s_outw(RALINK_ANA_CTRL_BASE+0x0014, data);
1858 +
1859 +               data = i2s_inw(RALINK_ANA_CTRL_BASE+0x0014);
1860 +               data &= ~REGBIT(0x3, 4);
1861 +               data |= REGBIT(0x1, 4);
1862 +               i2s_outw(RALINK_ANA_CTRL_BASE+0x0014, data);
1863 +
1864 +               data = i2s_inw(RALINK_ANA_CTRL_BASE+0x001c);
1865 +               data &= ~REGBIT(0x1, 31);
1866 +               i2s_outw(RALINK_ANA_CTRL_BASE+0x001c, data);
1867 +       }
1868 +       else
1869 +       {
1870 +               data = i2s_inw(RALINK_ANA_CTRL_BASE+0x001c);
1871 +               data &= ~REGBIT(0x1, 17);
1872 +               i2s_outw(RALINK_ANA_CTRL_BASE+0x001c, data);
1873 +
1874 +               data = i2s_inw(RALINK_ANA_CTRL_BASE+0x0014);
1875 +               data &= ~REGBIT(0x7f, 8);
1876 +               data |= REGBIT(0x17, 8);
1877 +               i2s_outw(RALINK_ANA_CTRL_BASE+0x0014, data);
1878 +
1879 +               data = i2s_inw(RALINK_ANA_CTRL_BASE+0x0014);
1880 +               data &= ~REGBIT(0x3, 6);
1881 +               i2s_outw(RALINK_ANA_CTRL_BASE+0x0014, data);
1882 +
1883 +               data = i2s_inw(RALINK_ANA_CTRL_BASE+0x0018);
1884 +               data &= ~REGBIT(0x7, 16);
1885 +               data |= REGBIT(0x2, 16);
1886 +               i2s_outw(RALINK_ANA_CTRL_BASE+0x0018, data);
1887 +
1888 +               data = i2s_inw(RALINK_ANA_CTRL_BASE+0x0018);
1889 +               data &= ~REGBIT(0xf, 8);
1890 +               data |= REGBIT(0x7, 8);
1891 +               i2s_outw(RALINK_ANA_CTRL_BASE+0x0018, data);
1892 +
1893 +
1894 +               data = i2s_inw(RALINK_ANA_CTRL_BASE+0x0014);
1895 +               data &= ~REGBIT(0x3, 4);
1896 +               data |= REGBIT(0x1, 4);
1897 +               i2s_outw(RALINK_ANA_CTRL_BASE+0x0014, data);
1898 +
1899 +               data = i2s_inw(RALINK_ANA_CTRL_BASE+0x001c);
1900 +               data &= ~REGBIT(0x1, 31);
1901 +               i2s_outw(RALINK_ANA_CTRL_BASE+0x001c, data);
1902 +
1903 +       }
1904 +#endif
1905 +        return 0;
1906 +}
1907 +#if defined(CONFIG_I2S_IN_MCLK)
1908 +int i2s_pll_refclk_set(void)
1909 +{
1910 +       unsigned long data;
1911 +
1912 +       /* Set APLL register for REFCLK */
1913 +        data = i2s_inw(RALINK_SYSCTL_BASE+0x90);
1914 +        data &= ~(0x0000f000);
1915 +        data |= REGBIT(0x1, 12);
1916 +        i2s_outw(RALINK_SYSCTL_BASE+0x0090, data);
1917 +
1918 +        data = i2s_inw(RALINK_SYSCTL_BASE+0x0090);
1919 +        data &= ~(0x00000300);
1920 +        i2s_outw(RALINK_SYSCTL_BASE+0x0090, data);
1921 +        MSG("Set 0x90 register\n");
1922 +
1923 +       return 0;
1924 +}
1925 +#endif
1926 +#endif
1927 +
1928 +#ifdef MT7623_ASIC_BOARD
1929 +int i2s_pll_config_mt7623(unsigned long index)
1930 +{
1931 +       unsigned long data;
1932 +
1933 +       /* xPLL PWR ON */
1934 +       data = i2s_inw(AUD2PLL_PWR_CON0);
1935 +       data |= 0x1;
1936 +       i2s_outw(AUD2PLL_PWR_CON0, data);
1937 +       udelay(5);
1938 +
1939 +       /* xPLL ISO Disable */
1940 +       data = i2s_inw(AUD2PLL_PWR_CON0);
1941 +       data &= ~(0x2);
1942 +       i2s_outw(AUD2PLL_PWR_CON0, data);
1943 +
1944 +       /* xPLL Frequency Set */
1945 +       data = i2s_inw(AUD2PLL_CON0);
1946 +       data |= 0x1;
1947 +       i2s_outw(AUD2PLL_CON0, data);
1948 +
1949 +       /* AUD1PLL Frequency Set(change from 98.304MHz to 294.912MHz) */
1950 +       i2s_outw(AUD1PLL_CON0, 0x121);
1951 +       i2s_outw(AUD1PLL_CON1, 0xad5efee6);
1952 +       udelay(40);
1953 +
1954 +       /* Audio clock setting */
1955 +       if((index==1)|(index==4)|(index==7)|(index==9)|(index==11))// for 22.05K, 44.1K, 88.2K, 176.4K
1956 +       {
1957 +               _printk("\n*****%s:index=%d(270MHz)*****\n", __func__, (int)index);
1958 +               data = i2s_inw(0xFB00002c);
1959 +               //data &= ~REGBIT(0x8, 1);
1960 +               data &= ~(0x80);
1961 +               i2s_outw(0xFB00002C, data); /* AUD1PLL 270.9204MHz */
1962 +       }
1963 +       else if ((index==0)|(index==3)|(index==5)|(index==6)|(index==8)|(index==10)|(index==12)) //for 24K, 48K, 96K, 192K
1964 +       {
1965 +               _printk("\n*****%s:index=%d(294MHz)*****\n", __func__, (int)index);
1966 +               data = i2s_inw(0xFB00002c);
1967 +               //data |= REGBIT(0x8, 1);
1968 +               data |= (0x80);
1969 +               i2s_outw(0xFB00002c, data); /* AUD1PLL 294.912MHz */
1970 +       }
1971 +       else if (index==2)
1972 +       {
1973 +               _printk("Not support 12KHz sampling rate!\n");
1974 +               return -1;
1975 +       }
1976 +        else
1977 +        {
1978 +                _printk("Wrong sampling rate!\n");
1979 +                return -1;
1980 +        }
1981 +       return 0;
1982 +}
1983 +#endif
1984 +
1985 +#if defined(MT7628_ASIC_BOARD) || defined(CONFIG_ARCH_MT7623)
1986 +int i2s_driving_strength_adjust(void)
1987 +{
1988 +#if defined(MT7628_ASIC_BOARD)
1989 +        unsigned long data;
1990 +
1991 +        MSG("Adjust MT7628 current's driving strngth\n");
1992 +        /* Adjust REFCLK0's driving strength of current which can avoid
1993 +         * the glitch of REFCKL0
1994 +         * E4 = 0xb0001354[5]; E8 = 0xb0001364[5]
1995 +         * (E4,E8)=(0,0)-> 4 mA;
1996 +         *        =(1,0)-> 8 mA;
1997 +         *        =(0,1)-> 12 mA;
1998 +         *        =(1,1)-> 16 mA*/
1999 +
2000 +        /* Set to 12mA */
2001 +        data = i2s_inw(0xb0001354);
2002 +        data &= ~(0x1<<5);
2003 +        i2s_outw(0xb0001354, data);
2004 +
2005 +        data = i2s_inw(0xb0001364);
2006 +        data |= (0x1<<5);
2007 +        i2s_outw(0xb0001364, data);
2008 +#endif
2009 +#if defined(CONFIG_ARCH_MT7623)
2010 +       MSG("Adjust MT7623 current's driving strngth\n");
2011 +
2012 +       i2s_outw(0xF0005F80, 0x7777);
2013 +#endif
2014 +
2015 +        return 0;
2016 +}
2017 +#endif
2018 +
2019 +#if defined(CONFIG_I2S_IN_MCLK)
2020 +#if defined(CONFIG_I2S_MCLK_12MHZ)
2021 +int i2s_refclk_12m_enable(void)
2022 +{
2023 +       unsigned long data;
2024 +
2025 +       MSG("Enable SoC MCLK 12Mhz\n");
2026 +
2027 +#if defined(CONFIG_RALINK_RT6855A)
2028 +       data = i2s_inw(RALINK_SYSCTL_BASE+0x860);
2029 +       data |= (0x1<<17);
2030 +       data &= ~(0x7<<18);
2031 +       data |= (0x1<<18);
2032 +       i2s_outw(RALINK_SYSCTL_BASE+0x860, data);
2033 +#elif defined(CONFIG_RALINK_RT3350)
2034 +       data = i2s_inw(RALINK_SYSCTL_BASE+0x2c);
2035 +       data |= (0x1<<8);
2036 +       i2s_outw(RALINK_SYSCTL_BASE+0x2c, data);
2037 +#elif defined(CONFIG_RALINK_RT3883)
2038 +       data = i2s_inw(RALINK_SYSCTL_BASE+0x2c);
2039 +       data &= ~(0x03<<13);
2040 +       data |= (0x1<<13);
2041 +       i2s_outw(RALINK_SYSCTL_BASE+0x2c, data);
2042 +#elif defined(CONFIG_RALINK_RT3352)||defined(CONFIG_RALINK_RT5350) || defined (CONFIG_RALINK_RT6855)
2043 +       data = i2s_inw(RALINK_SYSCTL_BASE+0x2c);
2044 +       data &= ~(0x0F<<8);
2045 +       data |= (0x3<<8);
2046 +       i2s_outw(RALINK_SYSCTL_BASE+0x2c, data);
2047 +#elif defined(CONFIG_RALINK_MT7620)
2048 +       data = i2s_inw(RALINK_SYSCTL_BASE+0x2c);
2049 +       data &= ~(0x07<<9);
2050 +       data |= (1<<9);
2051 +       i2s_outw(RALINK_SYSCTL_BASE+0x2c, data);
2052 +#elif defined(CONFIG_RALINK_MT7621)
2053 +       data = i2s_inw(RALINK_SYSCTL_BASE+0x2c);
2054 +       data &= ~(0x1f<<18);
2055 +       data |= REGBIT(0x19, 18);
2056 +       data &= ~(0x1f<<12);
2057 +       data |= REGBIT(0x1, 12);
2058 +       data &= ~(0x7<<9);
2059 +       data |= REGBIT(0x5, 9);
2060 +       i2s_outw(RALINK_SYSCTL_BASE+0x2c, data);
2061 +#elif defined(CONFIG_RALINK_MT7628)
2062 +       data = i2s_inw(RALINK_SYSCTL_BASE+0x2c);
2063 +       MSG("turn on REFCLK output for MCLK1\n");
2064 +       data &= ~(0x7<<9);
2065 +       data |= (0x1<<9);  /* output for MCLK */
2066 +       i2s_outw(RALINK_SYSCTL_BASE+0x2c, data);
2067 +#else
2068 +       #error "This SoC does not provide 12MHz clock to audio codec\n");
2069 +#endif
2070 +       i2s_refclk_gpio_out_config();
2071 +
2072 +       return 0;
2073 +}
2074 +#endif
2075 +
2076 +#if defined(CONFIG_I2S_MCLK_12P288MHZ)
2077 +int i2s_refclk_12p288m_enable(void)
2078 +{
2079 +       unsigned long data;
2080 +       MSG("Enable SoC MCLK 12.288Mhz\n");
2081 +
2082 +#if defined(CONFIG_RALINK_RT3352)||defined(CONFIG_RALINK_RT5350) || defined (CONFIG_RALINK_RT6855)
2083 +       data = i2s_inw(RALINK_SYSCTL_BASE+0x2c);
2084 +       data &= ~(0x01F<<18);
2085 +       data |= 31<<18;
2086 +       data &= ~(0x01F<<12);
2087 +       data |= 1<<12;
2088 +       data |= (0xF<<8);
2089 +       i2s_outw(RALINK_SYSCTL_BASE+0x2c, data);
2090 +#elif defined(CONFIG_RALINK_MT7621)
2091 +       data = i2s_inw(RALINK_SYSCTL_BASE+0x2c);
2092 +       data &= ~(0x1f<<18);
2093 +       data |= REGBIT(0xc, 18);
2094 +       data &= ~(0x1f<<12);
2095 +       data |= REGBIT(0x1, 12);
2096 +       data &= ~(0x7<<9);
2097 +       data |= REGBIT(0x5, 9);
2098 +       i2s_outw(RALINK_SYSCTL_BASE+0x2c, data);
2099 +       _printk("MT7621 provide REFCLK 12.288MHz/11.289MHz\n");
2100 +#elif defined(CONFIG_ARCH_MT7623)
2101 +       /* MT7623 does not need to set divider for REFCLK */
2102 +       /* GPIO126 - I2S0_MCLK */
2103 +       data = i2s_inw(0xF00058F0);
2104 +       data &= ~(0x7<<3);
2105 +       data |= (0x6<<3);
2106 +       i2s_outw(0xF00058F0, data);
2107 +       /* GPIO_DIR8: OUT */
2108 +       data = i2s_inw(0xF0005070);
2109 +       data |= (0x1<<14);
2110 +       i2s_outw(0xF0005070, data);
2111 +#else
2112 +       #error "This SoC does not provide 12.288Mhz clock to audio codec\n");
2113 +#endif
2114 +
2115 +       return 0;
2116 +}
2117 +#endif
2118 +
2119 +#if defined(CONFIG_I2S_MCLK_18P432MHZ)
2120 +int i2s_refclk_18p432m_enable(unsigned long index)
2121 +{
2122 +       unsigned long data;
2123 +       MSG("Enable SoC MCLK 18.432MHz/16.934MHz");
2124 +
2125 +       if((index==1)|(index==4)|(index==7)|(index==9))// 16.934MHz for 22.05K, 44.1K, 88.2K, 176.4K
2126 +        {
2127 +               data = i2s_inw(ETHDMASYS_SYSCTL_BASE+0x2c);
2128 +               data &= ~(0x1<<7);
2129 +               i2s_outw(ETHDMASYS_SYSCTL_BASE+0x2c, data);
2130 +       }
2131 +       else if((index==0)|(index==3)|(index==5)|(index==6)|(index==8)|(index==10))// 18.432MHZ for 24K, 48K, 96K, 192K
2132 +        {
2133 +               data = i2s_inw(ETHDMASYS_SYSCTL_BASE+0x2c);
2134 +               data |= (0x1<<7);
2135 +               i2s_outw(ETHDMASYS_SYSCTL_BASE+0x2c, data);
2136 +       }
2137 +
2138 +       data = i2s_inw(ETHDMASYS_SYSCTL_BASE+0x30);
2139 +       data |= (0x1<<17);
2140 +       i2s_outw(ETHDMASYS_SYSCTL_BASE+0x30, data);
2141 +
2142 +       return 0;
2143 +}
2144 +#endif
2145 +#endif
2146 +
2147 +int i2s_refclk_disable(void)
2148 +{
2149 +       unsigned long data;
2150 +
2151 +#if defined(CONFIG_RALINK_RT6855A)
2152 +       data = i2s_inw(RALINK_SYSCTL_BASE+0x860);
2153 +       data &= ~(1<<17);
2154 +       i2s_outw(RALINK_SYSCTL_BASE+0x860, data);
2155 +#elif defined(CONFIG_RALINK_RT3350)
2156 +       data = i2s_inw(RALINK_SYSCTL_BASE+0x2c);
2157 +       data &= ~(0x1<<8);
2158 +       i2s_outw(RALINK_SYSCTL_BASE+0x2c, data);
2159 +#elif defined(CONFIG_RALINK_RT3883)
2160 +       data = i2s_inw(RALINK_SYSCTL_BASE+0x2c);
2161 +        data &= ~(0x0F<<13);
2162 +       i2s_outw(RALINK_SYSCTL_BASE+0x2c, data);
2163 +#elif defined(CONFIG_RALINK_RT3352)||defined(CONFIG_RALINK_RT5350)||defined (CONFIG_RALINK_RT6855)
2164 +       data = i2s_inw(RALINK_SYSCTL_BASE+0x2c);
2165 +       data &= ~(0x0F<<8);
2166 +       i2s_outw(RALINK_SYSCTL_BASE+0x2c, data);
2167 +#elif defined (CONFIG_RALINK_MT7620)||defined (CONFIG_RALINK_MT7621)||defined (CONFIG_RALINK_MT7628)
2168 +       _printk("turn off REFCLK output from internal CLK\n");
2169 +       data = i2s_inw(RALINK_SYSCTL_BASE+0x2c);
2170 +       data &= ~(0x07<<9);
2171 +       i2s_outw(RALINK_SYSCTL_BASE+0x2c, data);
2172 +#elif defined (CONFIG_ARCH_MT7623) /*FIXME:2*/
2173 +#ifdef MT7623_ASIC_BOARD
2174 +       _printk("turn off REFCLK output from internal CLK\n");
2175 +       /* GPIO126 - I2S0_MCLK */
2176 +        data = i2s_inw(0xF00058F0);
2177 +        data &= ~(0x7<<3);
2178 +       //data |= (0x2<<3);
2179 +        i2s_outw(0xF00058F0, data);
2180 +       /* GPIO126 => GPIO_DIR8: IN */
2181 +       data = i2s_inw(0xF0005070);
2182 +       data &= ~(0x1<<14);
2183 +       i2s_outw(0xF0005070, data);
2184 +#else
2185 +       _printk("turn off REFCLK output from internal CLK\n");
2186 +       data = i2s_inw(ETHDMASYS_SYSCTL_BASE+0x30);
2187 +       data &= ~(0x1<<17);
2188 +       i2s_outw(ETHDMASYS_SYSCTL_BASE+0x30, data);
2189 +#endif
2190 +#endif
2191 +       return 0;
2192 +}
2193 +
2194 +int i2s_refclk_gpio_out_config(void)
2195 +{
2196 +#ifndef CONFIG_ARCH_MT7623
2197 +       unsigned long data; /* FIXME */
2198 +#endif
2199 +
2200 +       /* Set REFCLK GPIO pin as REFCLK mode*/
2201 +#if defined(CONFIG_RALINK_MT7620)
2202 +       data = i2s_inw(RALINK_SYSCTL_BASE+0x60);
2203 +       data &= ~(0x03<<21);  /* WDT */
2204 +       data |= (1<<21);
2205 +       //data &= ~(0x03<<16);  /* PERST */
2206 +       //data |= (1<<16);
2207 +       i2s_outw(RALINK_SYSCTL_BASE+0x60, data);
2208 +#endif
2209 +#if defined(CONFIG_RALINK_MT7621)
2210 +       data = i2s_inw(RALINK_SYSCTL_BASE+0x60);
2211 +       //data &= ~(0x3<<10); /* PERST */
2212 +       //data |= (0x2<<10);
2213 +       data &= ~(0x3<<8); /* WDT */
2214 +       data |= (0x2<<8);
2215 +       i2s_outw(RALINK_SYSCTL_BASE+0x60, data);
2216 +       MSG("Set 0x60 register\n");
2217 +#endif
2218 +#if defined(CONFIG_RALINK_MT7628)
2219 +       data = i2s_inw(RALINK_SYSCTL_BASE+0x60);
2220 +       data &= ~(0x1<<18);
2221 +       i2s_outw(RALINK_SYSCTL_BASE+0x60, data);
2222 +#endif
2223 +
2224 +       return 0;
2225 +}
2226 +
2227 +int i2s_refclk_gpio_in_config(void)
2228 +{
2229 +#ifndef CONFIG_ARCH_MT7623
2230 +       unsigned long data; /* FIXME */
2231 +#endif
2232 +
2233 +#if defined (CONFIG_RALINK_MT7620)
2234 +       data = i2s_inw(RALINK_SYSCTL_BASE+0x60);
2235 +       data &= ~(0x03<<21);  /* WDT */
2236 +       data |= (1<<21);
2237 +       //data &= ~(0x03<<16);  /* PERST */
2238 +       //data |= (1<<16);
2239 +       i2s_outw(RALINK_SYSCTL_BASE+0x60, data);
2240 +
2241 +       data = i2s_inw(RALINK_PIO_BASE);
2242 +       data &= ~(0x1<<17); /* GPIO share ping 17 for WDT */
2243 +       i2s_outw(RALINK_PIO_BASE, data);
2244 +
2245 +       //data = i2s_inw(RALINK_PIO_BASE+0x04);
2246 +       //data &= ~(0x1<<4); /* GPIO share ping 36 for PERST */
2247 +       //i2s_outw(RALINK_PIO_BASE+0x04, data);
2248 +#endif
2249 +#if defined (CONFIG_RALINK_MT7621)
2250 +       data = i2s_inw(RALINK_SYSCTL_BASE+0x60);
2251 +       //data &= ~(0x3<<10); /* PERST */
2252 +       //data |= (0x1<<10);
2253 +       data &= ~(0x3<<8); /* WDT */
2254 +       data |= (0x1<<8);
2255 +       i2s_outw(RALINK_SYSCTL_BASE+0x60, data);
2256 +
2257 +       data = i2s_inw(RALINK_PIO_BASE);
2258 +       //data &= ~(0x1<<19); /* GPIO share ping 19 for RERST */
2259 +       data &= ~(0x1<<18); /* GPIO share ping 18 for WDT */
2260 +       i2s_outw(RALINK_PIO_BASE, data);
2261 +#endif
2262 +#if defined (CONFIG_RALINK_MT7628)
2263 +       /* To use external OSC, set REFCLK_GPIO ping as GPIO mode and set it as input direction */
2264 +       data = i2s_inw(RALINK_SYSCTL_BASE+0x60);
2265 +       data |= (0x1<<18);
2266 +       i2s_outw(RALINK_SYSCTL_BASE+0x60, data);
2267 +
2268 +       data = i2s_inw(RALINK_PIO_BASE+0x04);
2269 +       data &= ~(0x1<<5); /* GPIO share ping 37*/
2270 +       i2s_outw(RALINK_PIO_BASE+0x04, data);
2271 +#endif
2272 +
2273 +       return 0;
2274 +}
2275 +
2276 +int i2s_slave_clock_gpio_in_mt7623(void)
2277 +{
2278 +       unsigned long data;
2279 +
2280 +       /* GPIO74(I2S0_BCLK)=>GPIO_DIR5: IN */
2281 +       data = i2s_inw(0xF0005040);
2282 +       data &= ~(0x1<<10);
2283 +       i2s_outw(0xF0005040, data);
2284 +
2285 +       /* GPIO73(I2S0_LRCK)=>GPIO_DIR5: IN */
2286 +       data = i2s_inw(0xF0005040);
2287 +       data &= ~(0x1<<9);
2288 +       i2s_outw(0xF0005040, data);
2289 +
2290 +       _printk("i2s_slave_clock_gpio_in_mt7623\n");
2291 +
2292 +       return 0;
2293 +}
2294 +
2295 +int i2s_master_clock_gpio_out_mt7623(void)
2296 +{
2297 +       unsigned long data;
2298 +
2299 +       /* GPIO74(I2S0_BCLK)=>GPIO_DIR5: OUT */
2300 +       data = i2s_inw(0xF0005040);
2301 +       data |= (0x1<<10);
2302 +       i2s_outw(0xF0005040, data);
2303 +
2304 +       /* GPIO73(I2S0_LRCK)=>GPIO_DIR5: OUT */
2305 +       data = i2s_inw(0xF0005040);
2306 +       data |= (0x1<<9);
2307 +       i2s_outw(0xF0005040, data);
2308 +
2309 +       _printk("i2s_master_clock_gpio_out_mt7623\n");
2310 +
2311 +       return 0;
2312 +}
2313 +
2314 +int i2s_share_pin_mt7623(i2s_config_type* ptri2s_config)
2315 +{
2316 +       unsigned long data;
2317 +
2318 +       _printk("\nConfig MT7623 I2S pinmux\n");
2319 +       /* GPIO74 - I2S0_BCLK */
2320 +       data = i2s_inw(0xF0005840);
2321 +       data &= ~(0x7<<12);
2322 +       data |= (0x6<<12);
2323 +       i2s_outw(0xF0005840, data);
2324 +
2325 +       /* GPIO73 - I2S0_LRCK */
2326 +       data = i2s_inw(0xF0005840);
2327 +       data &= ~(0x7<<9);
2328 +       data |= (0x6<<9);
2329 +       i2s_outw(0xF0005840, data);
2330 +
2331 +       if(ptri2s_config->slave_en==0)
2332 +               i2s_master_clock_gpio_out_mt7623();
2333 +       else
2334 +               i2s_slave_clock_gpio_in_mt7623();
2335 +
2336 +       /* GPIO49 - I2S0_DATA */
2337 +       data = i2s_inw(0xF00057F0);
2338 +       data &= ~(0x7<<12);
2339 +       data |= (0x6<<12);
2340 +       i2s_outw(0xF00057F0, data);
2341 +       /* GPIO_DIR4: OUT */
2342 +       data = i2s_inw(0xF0005030);
2343 +       data |= (0x1<<1);
2344 +       i2s_outw(0xF0005030, data);
2345 +
2346 +       /* GPIO72 - I2S0_DATA_IN */
2347 +       data = i2s_inw(0xF0005840);
2348 +       data &= ~(0x7<<6);
2349 +       data |= (0x6<<6);
2350 +       i2s_outw(0xF0005840, data);
2351 +       /* GPIO_DIR5: IN */
2352 +       data = i2s_inw(0xF0005040);
2353 +       data &= ~(0x1<<8);
2354 +       i2s_outw(0xF0005040, data);
2355 +
2356 +       return 0;
2357 +}
2358 +
2359 +int i2s_share_pin_config(i2s_config_type* ptri2s_config)
2360 +{
2361 +#ifndef CONFIG_ARCH_MT7623
2362 +       unsigned long data; /*FIXME*/
2363 +#endif
2364 +
2365 +       /* set share pins to i2s/gpio mode and i2c mode */
2366 +#if defined(CONFIG_RALINK_RT6855A)
2367 +       data = i2s_inw(RALINK_SYSCTL_BASE+0x860);
2368 +       data |= 0x00008080;
2369 +       i2s_outw(RALINK_SYSCTL_BASE+0x860, data);
2370 +#elif defined(CONFIG_RALINK_MT7621)
2371 +       data = i2s_inw(RALINK_SYSCTL_BASE+0x60);
2372 +       data &= 0xFFFFFFE3;
2373 +       data |= 0x00000010;
2374 +       i2s_outw(RALINK_SYSCTL_BASE+0x60, data);
2375 +#elif defined(CONFIG_RALINK_MT7628)
2376 +       data = i2s_inw(RALINK_SYSCTL_BASE+0x60);
2377 +       data &= ~(0x3<<6);    /* I2S_MODE */
2378 +       data &= ~(0x3<<20);   /* I2C_MODE */
2379 +       i2s_outw(RALINK_SYSCTL_BASE+0x60, data);
2380 +#elif defined(CONFIG_ARCH_MT7623)
2381 +       i2s_share_pin_mt7623(ptri2s_config);
2382 +#else
2383 +       data = i2s_inw(RALINK_SYSCTL_BASE+0x60);
2384 +       data &= 0xFFFFFFE2;
2385 +       data |= 0x00000018;
2386 +       i2s_outw(RALINK_SYSCTL_BASE+0x60, data);
2387 +#endif
2388 +       return 0;
2389 +}
2390 +
2391 +int i2s_ws_config(i2s_config_type* ptri2s_config, unsigned long index)
2392 +{
2393 +       unsigned long data;
2394 +       unsigned long* pTable;
2395 +
2396 +#if defined(CONFIG_I2S_IN_CLK)
2397 +       /* REFCLK is 15.625Mhz or 40Mhz(fractional division) */
2398 +#if defined(CONFIG_I2S_FRAC_DIV)
2399 +       MSG("Internal REFCLK with fractional division\n");
2400 +#if defined(CONFIG_RALINK_MT7628) || defined(CONFIG_ARCH_MT7623)
2401 +       if (ptri2s_config->wordlen_24b == 1)
2402 +       {
2403 +               MSG("24 bit int table\n");
2404 +               pTable = i2s_inclk_int_24bit;
2405 +       }
2406 +       else
2407 +       {
2408 +               MSG("16 bit int table\n");
2409 +               pTable = i2s_inclk_int_16bit;
2410 +       }
2411 +#else
2412 +       pTable = i2s_inclk_int;
2413 +#endif /* CONFIG_RALINK_MT7628 */
2414 +
2415 +       data = (unsigned long)(pTable[index]);
2416 +       i2s_outw(I2S_DIVINT_CFG, data);
2417 +
2418 +#if defined(CONFIG_RALINK_MT7628) || defined(CONFIG_ARCH_MT7623)
2419 +       if (ptri2s_config->wordlen_24b == 1)
2420 +       {
2421 +               MSG("24 bit comp table\n");
2422 +               pTable = i2s_inclk_comp_24bit;
2423 +       }
2424 +       else
2425 +       {
2426 +               MSG("16 bit comp table\n");
2427 +               pTable = i2s_inclk_comp_16bit;
2428 +       }
2429 +#else
2430 +       pTable = i2s_inclk_comp;
2431 +#endif /* CONFIG_RALINK_MT7628 */
2432 +
2433 +       data = (unsigned long)(pTable[index]);
2434 +       data |= REGBIT(1, I2S_CLKDIV_EN);
2435 +       i2s_outw(I2S_DIVCOMP_CFG, data);
2436 +#else
2437 +       MSG("Internal REFCLK 15.625Mhz \n");
2438 +       pTable = i2s_inclk_15p625Mhz;
2439 +       data = i2s_inw(RALINK_SYSCTL_BASE+0x30);
2440 +       data &= 0xFFFF00FF;
2441 +       data |= (unsigned long)(pTable[index]);
2442 +       data |= 0x00008000;
2443 +       i2s_outw(RALINK_SYSCTL_BASE+0x30, data);
2444 +#endif /* CONFIG_I2S_FRAC_DIV */
2445 +#else
2446 +#if defined(CONFIG_I2S_MCLK_12MHZ)
2447 +       /* REFCLK = MCLK = 12Mhz */
2448 +       MSG("External REFCLK 12Mhz \n");
2449 +       pTable = i2s_exclk_12Mhz;
2450 +       data = i2s_inw(RALINK_SYSCTL_BASE+0x30);
2451 +       data &= 0xFFFF00FF;
2452 +       data |= (unsigned long)(pTable[index]);
2453 +       data |= 0x0000C000;
2454 +       i2s_outw(RALINK_SYSCTL_BASE+0x30, data);
2455 +#else
2456 +       /* REFCLK = MCLK = 12.288Mhz */
2457 +       pTable = i2s_exclk_12p288Mhz;
2458 +       MSG("External REFCLK 12.288Mhz \n");
2459 +       data = i2s_inw(RALINK_SYSCTL_BASE+0x30);
2460 +       data &= 0xFFFF00FF;
2461 +       data |= (unsigned long)(pTable[index]);
2462 +       data |= 0x0000C000;
2463 +       i2s_outw(RALINK_SYSCTL_BASE+0x30, data);
2464 +#endif /* CONFIG_I2S_MCLK_12MHZ */
2465 +#endif /* Not CONFIG_I2S_IN_CLK */
2466 +
2467 +#if defined(CONFIG_I2S_WS_EDGE)
2468 +       data = i2s_inw(I2S_I2SCFG);
2469 +       data |= REGBIT(0x1, I2S_WS_INV);
2470 +       i2s_outw(I2S_I2SCFG, data);
2471 +#endif
2472 +
2473 +       return 0;
2474 +}
2475 +
2476 +int i2s_mode_config(u32 slave_en)
2477 +{
2478 +       unsigned long data;
2479 +
2480 +       if(slave_en==0)
2481 +       {
2482 +               /* Master mode*/
2483 +               _printk("This SoC is in Master mode\n");
2484 +#if defined(CONFIG_RALINK_RT3052)
2485 +               data = i2s_inw(I2S_I2SCFG);
2486 +               data &= ~REGBIT(0x1, I2S_SLAVE_EN);
2487 +               data &= ~REGBIT(0x1, I2S_CLK_OUT_DIS);
2488 +               i2s_outw(I2S_I2SCFG, data);
2489 +#elif defined(CONFIG_RALINK_RT3883)||defined(CONFIG_RALINK_RT3352)||\
2490 +       defined(CONFIG_RALINK_RT5350)||defined(CONFIG_RALINK_RT6855)||\
2491 +       defined(CONFIG_RALINK_MT7620)||defined(CONFIG_RALINK_RT6855A)||\
2492 +       defined(CONFIG_RALINK_MT7621)||defined(CONFIG_RALINK_MT7628)||\
2493 +       defined(CONFIG_ARCH_MT7623)
2494 +               data = i2s_inw(I2S_I2SCFG);
2495 +               data &= ~REGBIT(0x1, I2S_SLAVE_MODE);
2496 +               i2s_outw(I2S_I2SCFG, data);
2497 +#else
2498 +       #error "a strange clock mode"
2499 +#endif
2500 +       }
2501 +       else
2502 +       {
2503 +               /* Slave mode */
2504 +               _printk("This SoC is in Slave mode\n");
2505 +#if defined(CONFIG_RALINK_RT3052)
2506 +               data = i2s_inw(I2S_I2SCFG);
2507 +               data |= REGBIT(0x1, I2S_SLAVE_EN);
2508 +               data |= REGBIT(0x1, I2S_CLK_OUT_DIS);
2509 +               i2s_outw(I2S_I2SCFG, data);
2510 +#elif defined(CONFIG_RALINK_RT3883)||defined(CONFIG_RALINK_RT3352)||\
2511 +       defined(CONFIG_RALINK_RT5350)||defined(CONFIG_RALINK_RT6855)||\
2512 +       defined(CONFIG_RALINK_MT7620)||defined(CONFIG_RALINK_RT6855A)||\
2513 +       defined(CONFIG_RALINK_MT7621)||defined(CONFIG_RALINK_MT7628)||\
2514 +       defined(CONFIG_ARCH_MT7623)
2515 +               data = i2s_inw(I2S_I2SCFG);
2516 +               data |= REGBIT(0x1, I2S_SLAVE_MODE);
2517 +               i2s_outw(I2S_I2SCFG, data);
2518 +#else
2519 +               #error "a strange clock mode "
2520 +#endif
2521 +       }
2522 +
2523 +       return 0;
2524 +}
2525 +
2526 +int i2s_codec_frequency_config(i2s_config_type* ptri2s_config, unsigned long index)
2527 +{
2528 +#if defined(CONFIG_I2S_WM8960)||defined(CONFIG_I2S_WM8750)||defined(CONFIG_I2S_WM8751)
2529 +       unsigned long data;
2530 +       unsigned long* pTable;
2531 +#endif
2532 +
2533 +#if defined(CONFIG_I2S_MCLK_12MHZ)
2534 +#if defined(CONFIG_I2S_WM8960)||defined(CONFIG_I2S_WM8750)||defined(CONFIG_I2S_WM8751)
2535 +       pTable = i2s_codec_12Mhz;
2536 +       data = pTable[index];
2537 +#endif
2538 +#if defined(CONFIG_I2S_WM8960)
2539 +       audiohw_set_frequency(data, ptri2s_config->codec_pll_en);
2540 +#elif defined(CONFIG_I2S_WM8750)||defined(CONFIG_I2S_WM8751)
2541 +       audiohw_set_frequency(data|0x01);
2542 +#endif
2543 +#else
2544 +#if defined(CONFIG_I2S_WM8960)||defined(CONFIG_I2S_WM8750)||defined(CONFIG_I2S_WM8751)
2545 +#if defined(MT7623_FPGA_BOARD) && defined(CONFIG_I2S_WM8750)
2546 +       pTable = i2s_codec_18p432Mhz;
2547 +#else
2548 +       pTable = i2s_codec_12p288Mhz;
2549 +#endif
2550 +       data = pTable[index];
2551 +#endif
2552 +#if defined(CONFIG_I2S_WM8960)
2553 +       audiohw_set_frequency(data, ptri2s_config->codec_pll_en);
2554 +#elif defined(CONFIG_I2S_WM8750)||defined(CONFIG_I2S_WM8751)
2555 +       audiohw_set_frequency(data);
2556 +#endif
2557 +#endif
2558 +       return 0;
2559 +}
2560 +
2561 +/*
2562 + *  Ralink Audio System Clock Enable
2563 + *
2564 + *  I2S_WS : signal direction opposite to/same as I2S_CLK
2565 + *
2566 + *  I2S_CLK : Integer division or fractional division
2567 + *                       REFCLK from Internal or External (external REFCLK not support for fractional division)
2568 + *                       Suppose external REFCLK always be the same as external MCLK
2569 + *
2570 + *  MCLK : External OSC or internal generation
2571 + *
2572 + */
2573 +int i2s_clock_enable(i2s_config_type* ptri2s_config)
2574 +{
2575 +       unsigned long index;
2576 +       /* audio sampling rate decision */
2577 +       switch(ptri2s_config->srate)
2578 +       {
2579 +               case 8000:
2580 +                       index = 0;
2581 +                       break;
2582 +               case 11025:
2583 +                       index = 1;
2584 +                       break;
2585 +               case 12000:
2586 +                       index = 2;
2587 +                       break;
2588 +               case 16000:
2589 +                       index = 3;
2590 +                       break;
2591 +               case 22050:
2592 +                       index = 4;
2593 +                       break;
2594 +               case 24000:
2595 +                       index = 5;
2596 +                       break;
2597 +               case 32000:
2598 +                       index = 6;
2599 +                       break;
2600 +               case 44100:
2601 +                       index = 7;
2602 +                       break;
2603 +               case 48000:
2604 +                       index = 8;
2605 +                       break;
2606 +               case 88200:
2607 +                       index = 9;
2608 +                       break;
2609 +               case 96000:
2610 +                       index = 10;
2611 +                       break;
2612 +#if defined(CONFIG_RALINK_MT7628) || defined(CONFIG_ARCH_MT7623)
2613 +               case 176000:
2614 +                       index = 11;
2615 +                       break;
2616 +               case 192000:
2617 +                       index = 12;
2618 +                       break;
2619 +#endif
2620 +               default:
2621 +                       index = 7;
2622 +       }
2623 +#ifdef MT7621_ASIC_BOARD
2624 +        /* Set pll config  */
2625 +        i2s_pll_config_mt7621(index);
2626 +#endif
2627 +#ifdef MT7623_ASIC_BOARD
2628 +        /* Set pll config  */
2629 +        i2s_pll_config_mt7623(index);
2630 +#endif
2631 +
2632 +       /* enable internal MCLK */
2633 +#if defined(CONFIG_I2S_IN_MCLK)
2634 +#if defined(CONFIG_RALINK_MT7621)
2635 +       i2s_pll_refclk_set();
2636 +#endif
2637 +#if defined(CONFIG_I2S_MCLK_12MHZ)
2638 +#if defined(MT7628_ASIC_BOARD) || defined(CONFIG_ARCH_MT7623)
2639 +        i2s_driving_strength_adjust();
2640 +#endif
2641 +       i2s_refclk_12m_enable();
2642 +#endif /* MCLK_12MHZ */
2643 +#if defined(CONFIG_I2S_MCLK_12P288MHZ)
2644 +       i2s_refclk_12p288m_enable();
2645 +#endif /* MCLK_12P288MHZ */
2646 +#if defined(CONFIG_I2S_MCLK_18P432MHZ)
2647 +       i2s_refclk_18p432m_enable(index);
2648 +#endif
2649 +       i2s_refclk_gpio_out_config();
2650 +
2651 +#else
2652 +       MSG("Disable SoC MCLK, use external OSC\n");
2653 +       i2s_refclk_disable();
2654 +       i2s_refclk_gpio_in_config();
2655 +#endif /* CONFIG_I2S_IN_MCLK */
2656 +
2657 +       i2s_share_pin_config(ptri2s_config);
2658 +
2659 +       if(ptri2s_config->slave_en==0)
2660 +       {
2661 +               /* Setup I2S_WS and I2S_CLK */
2662 +               i2s_ws_config(ptri2s_config, index);
2663 +       }
2664 +
2665 +       i2s_mode_config(ptri2s_config->slave_en);
2666 +
2667 +       if(!ptri2s_config->bALSAEnable)
2668 +       {
2669 +#if defined(CONFIG_I2S_WM8750) || defined(CONFIG_I2S_WM8751)|| defined(CONFIG_I2S_WM8960)
2670 +       i2s_codec_enable(ptri2s_config);
2671 +#endif
2672 +       i2s_codec_frequency_config(ptri2s_config,index);
2673 +       }
2674 +
2675 +       return 0;
2676 +}
2677 +
2678 +int i2s_clock_disable(i2s_config_type* ptri2s_config)
2679 +{
2680 +       if(!ptri2s_config->bALSAEnable)
2681 +       {
2682 +#if defined(CONFIG_I2S_WM8960) || defined(CONFIG_I2S_WM8750) || defined(CONFIG_I2S_WM8751)
2683 +       i2s_codec_disable(ptri2s_config);
2684 +#endif
2685 +       }
2686 +
2687 +       /* disable internal MCLK */
2688 +#if defined(CONFIG_I2S_IN_MCLK)
2689 +       i2s_refclk_disable();
2690 +       i2s_refclk_gpio_in_config();
2691 +#endif
2692 +       return 0;
2693 +}
2694 +
2695 +
2696 +int i2s_codec_enable(i2s_config_type* ptri2s_config)
2697 +{
2698 +
2699 +       int AIn = 0, AOut = 0;
2700 +#if 1
2701 +#if defined(CONFIG_I2S_WM8960) || defined(CONFIG_I2S_WM8750) || defined(CONFIG_I2S_WM8751)
2702 +       /* Codec initialization */
2703 +       audiohw_preinit();
2704 +#endif
2705 +#endif
2706 +
2707 +#if defined(CONFIG_I2S_WM8960)
2708 +       if(ptri2s_config->codec_pll_en)
2709 +       {
2710 +               MSG("Codec PLL EN = %d\n", pi2s_config->codec_pll_en);
2711 +               audiohw_set_apll(ptri2s_config->srate);
2712 +       }
2713 +#endif
2714 +
2715 +#if defined(CONFIG_I2S_TXRX)
2716 +       if((ptri2s_config->bTxDMAEnable) || (ptri2s_config->txrx_coexist))
2717 +               AOut = 1;
2718 +       if((ptri2s_config->bRxDMAEnable) || (ptri2s_config->txrx_coexist))
2719 +               AIn = 1;
2720 +#if defined(CONFIG_I2S_WM8960)
2721 +       audiohw_postinit(!(ptri2s_config->slave_en), AIn, AOut, ptri2s_config->codec_pll_en, ptri2s_config->wordlen_24b);
2722 +       audiohw_micboost(ptri2s_config->micboost);
2723 +       audiohw_micin(ptri2s_config->micin);
2724 +#elif defined(CONFIG_I2S_WM8750)
2725 +       audiohw_postinit(!(ptri2s_config->slave_en), AIn, AOut, ptri2s_config->wordlen_24b);
2726 +#endif
2727 +       MSG("AOut=%d, AIn=%d\n", AOut, AIn);
2728 +#else
2729 +#if defined(CONFIG_I2S_WM8750)
2730 +       audiohw_postinit(!(ptri2s_config->slave_en), 0, 1);
2731 +#elif defined(CONFIG_I2S_WM8960)
2732 +       audiohw_postinit(!(ptri2s_config->slave_en), 1, 1, ptri2s_config->codec_pll_en);
2733 +#elif defined(CONFIG_I2S_WM8751)
2734 +       if(ptri2s_config->slave_en==0)
2735 +               audiohw_postinit(1,1);
2736 +       else
2737 +               audiohw_postinit(0,1);
2738 +#endif
2739 +#endif
2740 +       return 0;
2741 +}
2742 +
2743 +int i2s_codec_disable(i2s_config_type* ptri2s_config)
2744 +{
2745 +#if defined(CONFIG_I2S_WM8960) || defined(CONFIG_I2S_WM8750) || defined(CONFIG_I2S_WM8751)
2746 +       audiohw_close();
2747 +#endif
2748 +       return 0;
2749 +}
2750 +
2751 +int i2s_reset_config(i2s_config_type* ptri2s_config)
2752 +{
2753 +       unsigned long data;
2754 +
2755 +       /* RESET bit: write 1 clear */
2756 +#if defined(CONFIG_RALINK_RT6855A)
2757 +       data = i2s_inw(RALINK_SYSCTL_BASE+0x834);
2758 +       data |= (1<<17);
2759 +       i2s_outw(RALINK_SYSCTL_BASE+0x834, data);
2760 +
2761 +       data = i2s_inw(RALINK_SYSCTL_BASE+0x834);
2762 +       data &= ~(1<<17);
2763 +       i2s_outw(RALINK_SYSCTL_BASE+0x834, data);
2764 +#elif defined(CONFIG_ARCH_MT7623)
2765 +       data = i2s_inw(0xFB000000+0x34);
2766 +       data |= (1<<17);
2767 +       i2s_outw(0xFB000000+0x34, data);
2768 +
2769 +       data = i2s_inw(0xFB000000+0x34);
2770 +       data &= ~(1<<17);
2771 +       i2s_outw(0xFB000000+0x34, data);
2772 +#else
2773 +       data = i2s_inw(RALINK_SYSCTL_BASE+0x34);
2774 +       data |= (1<<17);
2775 +       i2s_outw(RALINK_SYSCTL_BASE+0x34, data);
2776 +
2777 +       data = i2s_inw(RALINK_SYSCTL_BASE+0x34);
2778 +       data &= ~(1<<17);
2779 +       i2s_outw(RALINK_SYSCTL_BASE+0x34, data);
2780 +
2781 +#if 0  /* Reset GDMA */
2782 +       data = i2s_inw(RALINK_SYSCTL_BASE+0x34);
2783 +       data |= (1<<14);
2784 +       i2s_outw(RALINK_SYSCTL_BASE+0x34, data);
2785 +
2786 +       data = i2s_inw(RALINK_SYSCTL_BASE+0x34);
2787 +       data &= ~(1<<14);
2788 +       i2s_outw(RALINK_SYSCTL_BASE+0x34, data);
2789 +#endif
2790 +#endif
2791 +       _printk("I2S reset complete!!\n");
2792 +       return 0;
2793 +}
2794 +
2795 +int i2s_tx_config(i2s_config_type* ptri2s_config)
2796 +{
2797 +       unsigned long data;
2798 +       /* set I2S_I2SCFG */
2799 +       data = i2s_inw(I2S_I2SCFG);
2800 +       data &= 0xFFFFFF81;
2801 +       data |= REGBIT(ptri2s_config->tx_ff_thres, I2S_TX_FF_THRES);
2802 +       data |= REGBIT(ptri2s_config->tx_ch_swap, I2S_TX_CH_SWAP);
2803 +#if defined(CONFIG_RALINK_RT6855A)
2804 +       data |= REGBIT(1, I2S_BYTE_SWAP);
2805 +#endif
2806 +#if defined(CONFIG_RALINK_MT7628) || defined(CONFIG_ARCH_MT7623)
2807 +       MSG("TX:wordLen=%d, sysEndian=%d\n", ptri2s_config->wordlen_24b, ptri2s_config->sys_endian);
2808 +       data |= REGBIT(ptri2s_config->wordlen_24b, I2S_DATA_24BIT);
2809 +       data |= REGBIT(ptri2s_config->sys_endian, I2S_SYS_ENDIAN);
2810 +       data |= REGBIT(ptri2s_config->little_edn, I2S_LITTLE_ENDIAN);
2811 +#endif
2812 +       data &= ~REGBIT(1, I2S_TX_CH0_OFF);
2813 +       data &= ~REGBIT(1, I2S_TX_CH1_OFF);
2814 +       i2s_outw(I2S_I2SCFG, data);
2815 +
2816 +       /* set I2S_I2SCFG1 */
2817 +       MSG("internal loopback: %d\n", ptri2s_config->lbk);
2818 +       data = i2s_inw(I2S_I2SCFG1);
2819 +       data |= REGBIT(ptri2s_config->lbk, I2S_LBK_EN);
2820 +       data |= REGBIT(ptri2s_config->extlbk, I2S_EXT_LBK_EN);
2821 +       data &= 0xFFFFFFFC;
2822 +#if defined(CONFIG_RALINK_MT7628) || defined(CONFIG_ARCH_MT7623)
2823 +       data |= REGBIT(ptri2s_config->fmt, I2S_DATA_FMT);
2824 +#endif
2825 +       i2s_outw(I2S_I2SCFG1, data);
2826 +
2827 +       return 0;
2828 +}
2829 +
2830 +int i2s_rx_config(i2s_config_type* ptri2s_config)
2831 +{
2832 +       unsigned long data;
2833 +       /* set I2S_I2SCFG */
2834 +       data = i2s_inw(I2S_I2SCFG);
2835 +       data &= 0xFFFF81FF;
2836 +       data |= REGBIT(ptri2s_config->rx_ff_thres, I2S_RX_FF_THRES);
2837 +       data |= REGBIT(ptri2s_config->rx_ch_swap, I2S_RX_CH_SWAP);
2838 +       data &= ~REGBIT(1, I2S_RX_CH0_OFF);
2839 +       data &= ~REGBIT(1, I2S_RX_CH1_OFF);
2840 +#if defined(CONFIG_RALINK_MT7628) || defined(CONFIG_ARCH_MT7623)
2841 +       MSG("RX:wordLen=%d, sysEndian=%d\n", ptri2s_config->wordlen_24b, ptri2s_config->sys_endian);
2842 +       data |= REGBIT(ptri2s_config->wordlen_24b, I2S_DATA_24BIT);
2843 +       data |= REGBIT(ptri2s_config->sys_endian, I2S_SYS_ENDIAN);
2844 +       data |= REGBIT(ptri2s_config->little_edn, I2S_LITTLE_ENDIAN);
2845 +#endif
2846 +       i2s_outw(I2S_I2SCFG, data);
2847 +
2848 +       /* set I2S_I2SCFG1 */
2849 +       data = i2s_inw(I2S_I2SCFG1);
2850 +       data |= REGBIT(ptri2s_config->lbk, I2S_LBK_EN);
2851 +       data |= REGBIT(ptri2s_config->extlbk, I2S_EXT_LBK_EN);
2852 +#if defined(CONFIG_RALINK_MT7628) || defined(CONFIG_ARCH_MT7623)
2853 +       data &= 0xFFFFFFFC;
2854 +       data |= REGBIT(ptri2s_config->fmt, I2S_DATA_FMT);
2855 +#endif
2856 +       i2s_outw(I2S_I2SCFG1, data);
2857 +
2858 +       return 0;
2859 +}
2860 +
2861 +/* Turn On Tx DMA and INT */
2862 +int i2s_tx_enable(i2s_config_type* ptri2s_config)
2863 +{
2864 +       unsigned long data;
2865 +
2866 +#if defined(I2S_HW_INTERRUPT_EN)
2867 +       data = i2s_inw(I2S_INT_EN);
2868 +       data |= REGBIT(0x1, I2S_TX_INT3_EN);  /* FIFO DMA fault */
2869 +       data |= REGBIT(0x1, I2S_TX_INT2_EN);  /* FIFO overrun */
2870 +       data |= REGBIT(0x1, I2S_TX_INT1_EN);  /* FIFO underrun */
2871 +       data |= REGBIT(0x1, I2S_TX_INT0_EN);  /* FIFO below threshold */
2872 +       i2s_outw(I2S_INT_EN, data);
2873 +#endif
2874 +
2875 +       data = i2s_inw(I2S_I2SCFG);
2876 +#if defined(CONFIG_I2S_TXRX)
2877 +       data |= REGBIT(0x1, I2S_TX_EN);
2878 +#endif
2879 +       data |= REGBIT(0x1, I2S_DMA_EN);
2880 +       i2s_outw(I2S_I2SCFG, data);
2881 +
2882 +       data = i2s_inw(I2S_I2SCFG);
2883 +       data |= REGBIT(0x1, I2S_EN);
2884 +       i2s_outw(I2S_I2SCFG, data);
2885 +
2886 +       MSG("i2s_tx_enable done\n");
2887 +       return I2S_OK;
2888 +}
2889 +
2890 +/* Turn On Rx DMA and INT */
2891 +int i2s_rx_enable(i2s_config_type* ptri2s_config)
2892 +{
2893 +       unsigned long data;
2894 +
2895 +#if defined(I2S_HW_INTERRUPT_EN)
2896 +       data = i2s_inw(I2S_INT_EN);
2897 +       data |= REGBIT(0x1, I2S_RX_INT3_EN);  /* FIFO DMA fault */
2898 +       data |= REGBIT(0x1, I2S_RX_INT2_EN);  /* FIFO overrun */
2899 +       data |= REGBIT(0x1, I2S_RX_INT1_EN);  /* FIFO underrun */
2900 +       data |= REGBIT(0x1, I2S_RX_INT0_EN);  /* FIFO below threshold */
2901 +       i2s_outw(I2S_INT_EN, data);
2902 +#endif
2903 +
2904 +       data = i2s_inw(I2S_I2SCFG);
2905 +#if defined(CONFIG_I2S_TXRX)
2906 +       data |= REGBIT(0x1, I2S_RX_EN);
2907 +#endif
2908 +       data |= REGBIT(0x1, I2S_DMA_EN);
2909 +       i2s_outw(I2S_I2SCFG, data);
2910 +
2911 +       data = i2s_inw(I2S_I2SCFG);
2912 +       data |= REGBIT(0x1, I2S_EN);
2913 +       i2s_outw(I2S_I2SCFG, data);
2914 +
2915 +       MSG("i2s_rx_enable done\n");
2916 +       return I2S_OK;
2917 +}
2918 +/* Turn Off Tx DMA and INT */
2919 +int i2s_tx_disable(i2s_config_type* ptri2s_config)
2920 +{
2921 +       unsigned long data;
2922 +
2923 +#if defined(I2S_HW_INTERRUPT_EN)
2924 +       data = i2s_inw(I2S_INT_EN);
2925 +       data &= ~REGBIT(0x1, I2S_TX_INT3_EN);
2926 +       data &= ~REGBIT(0x1, I2S_TX_INT2_EN);
2927 +       data &= ~REGBIT(0x1, I2S_TX_INT1_EN);
2928 +       data &= ~REGBIT(0x1, I2S_TX_INT0_EN);
2929 +       i2s_outw(I2S_INT_EN, data);
2930 +#endif
2931 +
2932 +       data = i2s_inw(I2S_I2SCFG);
2933 +#if defined(CONFIG_I2S_TXRX)
2934 +       data &= ~REGBIT(0x1, I2S_TX_EN);
2935 +#endif
2936 +       if(ptri2s_config->bRxDMAEnable==0)
2937 +       {
2938 +               ptri2s_config->bTxDMAEnable = 0;
2939 +               data &= ~REGBIT(0x1, I2S_DMA_EN);
2940 +                data &= ~REGBIT(0x1, I2S_EN);
2941 +       }
2942 +       i2s_outw(I2S_I2SCFG, data);
2943 +       return I2S_OK;
2944 +}
2945 +/* Turn Off Rx DMA and INT */
2946 +int i2s_rx_disable(i2s_config_type* ptri2s_config)
2947 +{
2948 +       unsigned long data;
2949 +
2950 +#if defined(I2S_HW_INTERRUPT_EN)
2951 +       data = i2s_inw(I2S_INT_EN);
2952 +       data &= ~REGBIT(0x1, I2S_RX_INT3_EN);
2953 +       data &= ~REGBIT(0x1, I2S_RX_INT2_EN);
2954 +       data &= ~REGBIT(0x1, I2S_RX_INT1_EN);
2955 +       data &= ~REGBIT(0x1, I2S_RX_INT0_EN);
2956 +       i2s_outw(I2S_INT_EN, data);
2957 +#endif
2958 +
2959 +       data = i2s_inw(I2S_I2SCFG);
2960 +#if defined(CONFIG_I2S_TXRX)
2961 +       data &= ~REGBIT(0x1, I2S_RX_EN);
2962 +#endif
2963 +       if(ptri2s_config->bTxDMAEnable==0)
2964 +       {
2965 +               ptri2s_config->bRxDMAEnable = 0;
2966 +               data &= ~REGBIT(0x1, I2S_DMA_EN);
2967 +                data &= ~REGBIT(0x1, I2S_EN);
2968 +       }
2969 +       i2s_outw(I2S_I2SCFG, data);
2970 +       return I2S_OK;
2971 +}
2972 +
2973 +int i2s_dma_tx_transf_data(i2s_config_type* ptri2s_config, u32 dma_ch)
2974 +{
2975 +       int tx_r_idx;
2976 +
2977 +       if ((pi2s_config->bALSAEnable==1) && (pi2s_config->bALSAMMAPEnable==1))
2978 +               tx_r_idx = (pi2s_config->tx_r_idx + ALSA_MMAP_IDX_SHIFT)%MAX_I2S_PAGE;
2979 +       else
2980 +               tx_r_idx = pi2s_config->tx_r_idx;
2981 +
2982 +       if(dma_ch==GDMA_I2S_TX0)
2983 +        {
2984 +#if defined(CONFIG_I2S_MMAP)
2985 +               dma_sync_single_for_device(NULL,  i2s_mmap_addr[tx_r_idx], I2S_PAGE_SIZE, DMA_TO_DEVICE);
2986 +#if defined(ARM_ARCH)
2987 +               GdmaI2sTx(i2s_mmap_addr[tx_r_idx], I2S_TX_FIFO_WREG_PHY, 0, I2S_PAGE_SIZE, i2s_dma_tx_handler, i2s_dma_tx_unmask_handler);
2988 +#else
2989 +                GdmaI2sTx((u32)(pi2s_config->pMMAPTxBufPtr[tx_r_idx]), I2S_TX_FIFO_WREG, 0, I2S_PAGE_SIZE, i2s_dma_tx_handler, i2s_dma_tx_unmask_handler);
2990 +#endif
2991 +#else
2992 +                memcpy(pi2s_config->pPage0TxBuf8ptr,  pi2s_config->pMMAPTxBufPtr[tx_r_idx], I2S_PAGE_SIZE);
2993 +#if defined(ARM_ARCH)
2994 +               GdmaI2sTx(i2s_txdma_addr0, I2S_TX_FIFO_WREG_PHY, 0, I2S_PAGE_SIZE, i2s_dma_tx_handler, i2s_dma_tx_unmask_handler);
2995 +#else
2996 +                GdmaI2sTx((u32)(pi2s_config->pPage0TxBuf8ptr), I2S_TX_FIFO_WREG, 0, I2S_PAGE_SIZE, i2s_dma_tx_handler, i2s_dma_tx_unmask_handler);
2997 +#endif
2998 +#endif
2999 +                pi2s_config->dmach = GDMA_I2S_TX0;
3000 +                pi2s_config->tx_r_idx = (pi2s_config->tx_r_idx+1)%MAX_I2S_PAGE;
3001 +       }
3002 +        else
3003 +        {
3004 +#if defined(CONFIG_I2S_MMAP)
3005 +               dma_sync_single_for_device(NULL,  i2s_mmap_addr[tx_r_idx], I2S_PAGE_SIZE, DMA_TO_DEVICE);
3006 +#if defined(ARM_ARCH)
3007 +               GdmaI2sTx(i2s_mmap_addr[tx_r_idx], I2S_TX_FIFO_WREG_PHY, 1, I2S_PAGE_SIZE, i2s_dma_tx_handler, i2s_dma_tx_unmask_handler);
3008 +#else
3009 +                GdmaI2sTx((u32)(pi2s_config->pMMAPTxBufPtr[tx_r_idx]), I2S_TX_FIFO_WREG, 1, I2S_PAGE_SIZE, i2s_dma_tx_handler, i2s_dma_tx_unmask_handler);
3010 +#endif
3011 +#else
3012 +                memcpy(pi2s_config->pPage1TxBuf8ptr,  pi2s_config->pMMAPTxBufPtr[tx_r_idx], I2S_PAGE_SIZE);
3013 +#if defined(ARM_ARCH)
3014 +               GdmaI2sTx(i2s_txdma_addr1, I2S_TX_FIFO_WREG_PHY, 1, I2S_PAGE_SIZE, i2s_dma_tx_handler, i2s_dma_tx_unmask_handler);
3015 +#else
3016 +                GdmaI2sTx((u32)(pi2s_config->pPage1TxBuf8ptr), I2S_TX_FIFO_WREG, 1, I2S_PAGE_SIZE, i2s_dma_tx_handler, i2s_dma_tx_unmask_handler);
3017 +#endif
3018 +#endif
3019 +                pi2s_config->dmach = GDMA_I2S_TX1;
3020 +                pi2s_config->tx_r_idx = (pi2s_config->tx_r_idx+1)%MAX_I2S_PAGE;
3021 +       }
3022 +#if defined(CONFIG_I2S_WITH_AEC)
3023 +       if(aecFuncP->AECFeEnq){
3024 +               aecFuncP->AECFeEnq(0,pi2s_config->pMMAPTxBufPtr[pi2s_config->tx_r_idx],I2S_PAGE_SIZE);
3025 +       }
3026 +#endif
3027 +       return 0;
3028 +}
3029 +
3030 +int i2s_dma_tx_transf_zero(i2s_config_type* ptri2s_config, u32 dma_ch)
3031 +{
3032 +       if(dma_ch==GDMA_I2S_TX0)
3033 +        {
3034 +               memset(pi2s_config->pPage0TxBuf8ptr, 0, I2S_PAGE_SIZE);
3035 +#if defined(ARM_ARCH)
3036 +               GdmaI2sTx(i2s_txdma_addr0, I2S_TX_FIFO_WREG_PHY, 0, I2S_PAGE_SIZE, i2s_dma_tx_handler, i2s_dma_tx_unmask_handler);
3037 +#else
3038 +                GdmaI2sTx((u32)pi2s_config->pPage0TxBuf8ptr, I2S_TX_FIFO_WREG, 0, I2S_PAGE_SIZE, i2s_dma_tx_handler, i2s_dma_tx_unmask_handler);
3039 +#endif
3040 +        }
3041 +        else
3042 +        {
3043 +                memset(pi2s_config->pPage1TxBuf8ptr, 0, I2S_PAGE_SIZE);
3044 +#if defined(ARM_ARCH)
3045 +               GdmaI2sTx(i2s_txdma_addr1, I2S_TX_FIFO_WREG_PHY, 1, I2S_PAGE_SIZE, i2s_dma_tx_handler, i2s_dma_tx_unmask_handler);
3046 +#else
3047 +                GdmaI2sTx((u32)pi2s_config->pPage1TxBuf8ptr, I2S_TX_FIFO_WREG, 1, I2S_PAGE_SIZE, i2s_dma_tx_handler, i2s_dma_tx_unmask_handler);
3048 +#endif
3049 +        }
3050 +       return 0;
3051 +}
3052 +
3053 +int i2s_dma_rx_transf_data(i2s_config_type* ptri2s_config, u32 dma_ch)
3054 +{
3055 +       int rx_w_idx;
3056 +
3057 +       pi2s_config->rx_w_idx = (pi2s_config->rx_w_idx+1)%MAX_I2S_PAGE;
3058 +
3059 +       if ((pi2s_config->bALSAEnable==1) && (pi2s_config->bALSAMMAPEnable==1))
3060 +               rx_w_idx = (pi2s_config->rx_w_idx+ALSA_MMAP_IDX_SHIFT)%MAX_I2S_PAGE;
3061 +       else
3062 +               rx_w_idx = (pi2s_config->rx_w_idx)%MAX_I2S_PAGE;
3063 +
3064 +       if(dma_ch==GDMA_I2S_RX0)
3065 +        {
3066 +
3067 +#ifdef CONFIG_I2S_MMAP
3068 +                dma_sync_single_for_device(NULL,  i2s_mmap_addr[rx_w_idx+(pi2s_config->mmap_index-MAX_I2S_PAGE)], I2S_PAGE_SIZE, DMA_FROM_DEVICE);
3069 +#if defined(ARM_ARCH)
3070 +               GdmaI2sRx(I2S_RX_FIFO_RREG_PHY, (u32)i2s_mmap_addr[rx_w_idx+(pi2s_config->mmap_index-MAX_I2S_PAGE)], 0, I2S_PAGE_SIZE, i2s_dma_rx_handler, i2s_dma_rx_unmask_handler);
3071 +#else
3072 +                GdmaI2sRx(I2S_RX_FIFO_RREG, (u32)(pi2s_config->pMMAPRxBufPtr[rx_w_idx]), 0, I2S_PAGE_SIZE, i2s_dma_rx_handler, i2s_dma_rx_unmask_handler);
3073 +#endif
3074 +#else
3075 +                memcpy(pi2s_config->pMMAPRxBufPtr[rx_w_idx], pi2s_config->pPage0RxBuf8ptr, I2S_PAGE_SIZE);
3076 +#if defined(ARM_ARCH)
3077 +               GdmaI2sRx(I2S_RX_FIFO_RREG_PHY, i2s_rxdma_addr0, 0, I2S_PAGE_SIZE, i2s_dma_rx_handler, i2s_dma_rx_unmask_handler);
3078 +#else
3079 +                GdmaI2sRx(I2S_RX_FIFO_RREG, (u32)(pi2s_config->pPage0RxBuf8ptr), 0, I2S_PAGE_SIZE, i2s_dma_rx_handler, i2s_dma_rx_unmask_handler);
3080 +#endif
3081 +#endif
3082 +                pi2s_config->dmach = GDMA_I2S_RX0;
3083 +        }
3084 +       else
3085 +        {
3086 +
3087 +#ifdef CONFIG_I2S_MMAP
3088 +                dma_sync_single_for_device(NULL,  i2s_mmap_addr[rx_w_idx+(pi2s_config->mmap_index-MAX_I2S_PAGE)], I2S_PAGE_SIZE, DMA_FROM_DEVICE);
3089 +#if defined(ARM_ARCH)
3090 +               GdmaI2sRx(I2S_RX_FIFO_RREG_PHY, (u32)i2s_mmap_addr[rx_w_idx+(pi2s_config->mmap_index-MAX_I2S_PAGE)], 1, I2S_PAGE_SIZE, i2s_dma_rx_handler, i2s_dma_rx_unmask_handler);
3091 +#else
3092 +                GdmaI2sRx(I2S_RX_FIFO_RREG, (u32)(pi2s_config->pMMAPRxBufPtr[rx_w_idx]), 1, I2S_PAGE_SIZE, i2s_dma_rx_handler, i2s_dma_rx_unmask_handler);
3093 +#endif
3094 +#else
3095 +                memcpy(pi2s_config->pMMAPRxBufPtr[rx_w_idx], pi2s_config->pPage1RxBuf8ptr, I2S_PAGE_SIZE);
3096 +#if defined(ARM_ARCH)
3097 +               GdmaI2sRx(I2S_RX_FIFO_RREG_PHY, i2s_rxdma_addr1, 1, I2S_PAGE_SIZE, i2s_dma_rx_handler, i2s_dma_rx_unmask_handler);
3098 +#else
3099 +                GdmaI2sRx(I2S_RX_FIFO_RREG, (u32)(pi2s_config->pPage1RxBuf8ptr), 1, I2S_PAGE_SIZE, i2s_dma_rx_handler, i2s_dma_rx_unmask_handler);
3100 +#endif
3101 +#endif
3102 +                pi2s_config->dmach = GDMA_I2S_RX1;
3103 +
3104 +        }
3105 +#if defined(CONFIG_I2S_WITH_AEC)
3106 +               if(aecFuncP->AECNeEnq){
3107 +                       aecFuncP->AECNeEnq(0,pi2s_config->pMMAPRxBufPtr[rx_w_idx],I2S_PAGE_SIZE);
3108 +               }
3109 +#endif
3110 +       return 0;
3111 +}
3112 +
3113 +int i2s_dma_rx_transf_zero(i2s_config_type* ptri2s_config, u32 dma_ch)
3114 +{
3115 +       if(dma_ch==GDMA_I2S_RX0)
3116 +        {
3117 +               memset(pi2s_config->pPage0RxBuf8ptr, 0, I2S_PAGE_SIZE);
3118 +#if defined(ARM_ARCH)
3119 +               GdmaI2sRx(I2S_RX_FIFO_RREG_PHY, i2s_rxdma_addr0, 0, I2S_PAGE_SIZE, i2s_dma_rx_handler, i2s_dma_rx_unmask_handler);
3120 +#else
3121 +               GdmaI2sRx(I2S_RX_FIFO_RREG, (u32)pi2s_config->pPage0RxBuf8ptr, 0, I2S_PAGE_SIZE, i2s_dma_rx_handler, i2s_dma_rx_unmask_handler);
3122 +#endif
3123 +        }
3124 +        else
3125 +               {
3126 +               memset(pi2s_config->pPage1RxBuf8ptr, 0, I2S_PAGE_SIZE);
3127 +#if defined(ARM_ARCH)
3128 +               GdmaI2sRx(I2S_RX_FIFO_RREG_PHY, i2s_rxdma_addr1, 1, I2S_PAGE_SIZE, i2s_dma_rx_handler, i2s_dma_rx_unmask_handler);
3129 +#else
3130 +                GdmaI2sRx(I2S_RX_FIFO_RREG, (u32)pi2s_config->pPage1RxBuf8ptr, 1, I2S_PAGE_SIZE, i2s_dma_rx_handler, i2s_dma_rx_unmask_handler);
3131 +#endif
3132 +        }
3133 +       return 0;
3134 +}
3135 +
3136 +void i2s_dma_tx_handler(u32 dma_ch)
3137 +{
3138 +       pi2s_config->enLable = 1; /* TX:enLabel=1; RX:enLabel=2 */
3139 +
3140 +       if(pi2s_config->bTxDMAEnable==0)
3141 +       {
3142 +               if(pi2s_config->end_cnt != 0)
3143 +               {
3144 +                       i2s_dma_tx_transf_data(pi2s_config, dma_ch);
3145 +                       pi2s_config->end_cnt --;
3146 +                       MSG("end_cnt = %d, r_idx = %d\n", pi2s_config->end_cnt, pi2s_config->tx_r_idx);
3147 +               }
3148 +               else
3149 +               {
3150 +                       pi2s_config->tx_stop_cnt++;
3151 +                       i2s_dma_tx_soft_stop(pi2s_config, dma_ch);
3152 +                       MSG("tx_stop=%d, ch=%d\n", pi2s_config->tx_stop_cnt, dma_ch);
3153 +                       if (pi2s_config->tx_stop_cnt == 3)
3154 +                       {
3155 +                               wake_up_interruptible(&(pi2s_config->i2s_tx_qh));
3156 +                               _printk("T:wake up!!\n");
3157 +                       }
3158 +               }
3159 +               return;
3160 +       }
3161 +
3162 +       pi2s_config->tx_isr_cnt++;
3163 +
3164 +#ifdef         I2S_STATISTIC
3165 +       i2s_int_status(dma_ch);
3166 +#endif
3167 +       /* FIXME */
3168 +       if(pi2s_config->bALSAEnable)
3169 +       {
3170 +               if(pi2s_config->dmaStat[STREAM_PLAYBACK])
3171 +               {
3172 +                       if(!pi2s_config->bTrigger[STREAM_PLAYBACK]){
3173 +                               //_printk("trigger stop: rIdx:%d widx:%d\n", pi2s_config->tx_r_idx,pi2s_config->tx_w_idx);
3174 +                                i2s_dma_tx_transf_zero(pi2s_config, dma_ch);
3175 +                                if(pi2s_config->bPreTrigger[STREAM_PLAYBACK]){
3176 +                                        /* mtk04880 commented:
3177 +                                         * for corner case, there are cases which ALSA Trigger stop before disabling DMA.
3178 +                                         * For which case, it needs to keep call snd_pcm_elapased to keep ALSA hw ptr updating.
3179 +                                         * It is so called post stop handlment.
3180 +                                         */
3181 +                                        //_printk("post-stop\n");
3182 +                                        goto EXIT;
3183 +                                }
3184 +                                else{
3185 +                                        //_printk("pre-stop\n");
3186 +                                        wake_up_interruptible(&(pi2s_config->i2s_tx_qh));
3187 +                                        return;
3188 +                                }
3189 +                        }
3190 +                        else{
3191 +                                if(!pi2s_config->bPreTrigger[STREAM_PLAYBACK])
3192 +                                        pi2s_config->bPreTrigger[STREAM_PLAYBACK] = 1;
3193 +
3194 +                       }
3195 +               }
3196 +       }
3197 +       else
3198 +       {
3199 +               if(pi2s_config->tx_r_idx==pi2s_config->tx_w_idx)
3200 +               {
3201 +                       /* Buffer Empty */
3202 +                       MSG("TXBE r=%d w=%d[i=%u,c=%u]\n",pi2s_config->tx_r_idx,pi2s_config->tx_w_idx,pi2s_config->tx_isr_cnt,dma_ch);
3203 +#ifdef I2S_STATISTIC
3204 +                       pi2s_status->txbuffer_unrun++;
3205 +#endif
3206 +                       i2s_dma_tx_transf_zero(pi2s_config, dma_ch);
3207 +                       goto EXIT;
3208 +               }
3209 +       }
3210 +
3211 +       if(pi2s_config->pMMAPTxBufPtr[pi2s_config->tx_r_idx]==NULL)
3212 +       {
3213 +               MSG("mmap buf NULL [%d]\n",pi2s_config->tx_r_idx);
3214 +               i2s_dma_tx_transf_zero(pi2s_config, dma_ch);
3215 +
3216 +               goto EXIT;
3217 +       }
3218 +
3219 +       if(pi2s_config->tx_pause_en == 1)
3220 +       {
3221 +               /* Enable PAUSE */
3222 +               MSG("TX pause now\n");
3223 +               i2s_dma_tx_transf_zero(pi2s_config, dma_ch);
3224 +
3225 +               goto EXIT;
3226 +       }
3227 +
3228 +#ifdef I2S_STATISTIC
3229 +       pi2s_status->txbuffer_len--;
3230 +#endif
3231 +       i2s_dma_tx_transf_data(pi2s_config, dma_ch);
3232 +
3233 +EXIT:
3234 +#if defined(CONFIG_SND_MT76XX_SOC)
3235 +       if(pi2s_config->bALSAEnable == 1){
3236 +               if(pi2s_config->pss[STREAM_PLAYBACK])
3237 +                       snd_pcm_period_elapsed(pi2s_config->pss[STREAM_PLAYBACK]);
3238 +       }
3239 +#endif
3240 +       wake_up_interruptible(&(pi2s_config->i2s_tx_qh));
3241 +       return;
3242 +}
3243 +
3244 +void i2s_dma_rx_handler(u32 dma_ch)
3245 +{
3246 +       pi2s_config->enLable = 2; /* TX:enLabel=1; RX:enLabel=2 */
3247 +#if defined(CONFIG_I2S_TXRX)
3248 +       if(pi2s_config->rx_isr_cnt==0)
3249 +       {
3250 +               pi2s_config->next_p0_idx = 0;
3251 +               pi2s_config->next_p1_idx = 1;
3252 +       }
3253 +       pi2s_config->rx_isr_cnt++;
3254 +
3255 +#ifdef  I2S_STATISTIC
3256 +       i2s_int_status(dma_ch);
3257 +#endif
3258 +
3259 +       if (pi2s_config->bRxDMAEnable==0)
3260 +       {
3261 +               pi2s_config->rx_stop_cnt++;
3262 +               i2s_dma_rx_soft_stop(pi2s_config, dma_ch);
3263 +               MSG("rx_stop=%d\n", pi2s_config->rx_stop_cnt);
3264 +
3265 +               if(pi2s_config->rx_stop_cnt == 2)
3266 +               {
3267 +                       wake_up_interruptible(&(pi2s_config->i2s_rx_qh));
3268 +                       _printk("R:wake up!!\n");
3269 +               }
3270 +               return;
3271 +       }
3272 +
3273 +       if(pi2s_config->bALSAEnable)
3274 +       {
3275 +                if(pi2s_config->dmaStat[STREAM_CAPTURE]){
3276 +                       if(!pi2s_config->bTrigger[STREAM_CAPTURE]){
3277 +                                MSG("trigger stop: rIdx:%d widx:%d\n", pi2s_config->rx_r_idx,pi2s_config->rx_w_idx);
3278 +                               i2s_dma_rx_transf_zero(pi2s_config, dma_ch);
3279 +                                wake_up_interruptible(&(pi2s_config->i2s_rx_qh));
3280 +                                return;
3281 +                       }
3282 +                }
3283 +       }
3284 +       else
3285 +       {
3286 +               if(((pi2s_config->rx_w_idx+1)%MAX_I2S_PAGE)==pi2s_config->rx_r_idx){
3287 +                       /* Buffer Full */
3288 +                       MSG("RXBF r=%d w=%d[i=%u,c=%u]\n",pi2s_config->rx_r_idx,pi2s_config->rx_w_idx,pi2s_config->rx_isr_cnt,dma_ch);
3289 +#ifdef I2S_STATISTIC
3290 +                       pi2s_status->rxbuffer_unrun++;
3291 +#endif
3292 +                       i2s_dma_rx_transf_zero(pi2s_config, dma_ch);
3293 +                       goto EXIT;
3294 +               }
3295 +       }
3296 +
3297 +       if(pi2s_config->rx_pause_en == 1)
3298 +       {
3299 +               /* Enable PAUSE */
3300 +               i2s_dma_rx_transf_zero(pi2s_config, dma_ch);
3301 +
3302 +               goto EXIT;
3303 +       }
3304 +
3305 +#ifdef I2S_STATISTIC
3306 +       pi2s_status->rxbuffer_len++;
3307 +#endif
3308 +       i2s_dma_rx_transf_data(pi2s_config, dma_ch);
3309 +
3310 +EXIT:
3311 +#if defined(CONFIG_SND_MT76XX_SOC)
3312 +       if(pi2s_config->bALSAEnable == 1){
3313 +               if(pi2s_config->pss[STREAM_CAPTURE])
3314 +                       snd_pcm_period_elapsed(pi2s_config->pss[STREAM_CAPTURE]);
3315 +       }
3316 +#endif
3317 +       wake_up_interruptible(&(pi2s_config->i2s_rx_qh));
3318 +#endif
3319 +       return;
3320 +}
3321 +
3322 +#ifdef I2S_STATISTIC
3323 +void i2s_int_status(u32 dma_ch)
3324 +{
3325 +       u32 i2s_status;
3326 +
3327 +       if((pi2s_config->tx_isr_cnt>0)||(pi2s_config->rx_isr_cnt>0))
3328 +       {
3329 +               i2s_status = i2s_inw(I2S_INT_STATUS);
3330 +
3331 +               if(i2s_status&REGBIT(1, I2S_TX_DMA_FAULT))
3332 +               {
3333 +                       pi2s_status->txdmafault++;
3334 +               }
3335 +               if(i2s_status&REGBIT(1, I2S_TX_OVRUN))
3336 +               {
3337 +                       pi2s_status->txovrun++;
3338 +               }
3339 +               if(i2s_status&REGBIT(1, I2S_TX_UNRUN))
3340 +               {
3341 +                       pi2s_status->txunrun++;
3342 +               }
3343 +               if(i2s_status&REGBIT(1, I2S_TX_THRES))
3344 +               {
3345 +                       pi2s_status->txthres++;
3346 +               }
3347 +               if(i2s_status&REGBIT(1, I2S_RX_DMA_FAULT))
3348 +               {
3349 +                       pi2s_status->rxdmafault++;
3350 +               }
3351 +               if(i2s_status&REGBIT(1, I2S_RX_OVRUN))
3352 +               {
3353 +                       pi2s_status->rxovrun++;
3354 +               }
3355 +               if(i2s_status&REGBIT(1, I2S_RX_UNRUN))
3356 +               {
3357 +                       pi2s_status->rxunrun++;
3358 +               }
3359 +               if(i2s_status&REGBIT(1, I2S_RX_THRES))
3360 +               {
3361 +                       pi2s_status->rxthres++;
3362 +               }
3363 +       }
3364 +#if 0
3365 +       if(pi2s_config->enLable == 1)
3366 +       {
3367 +               if((pi2s_config->tx_isr_cnt>0) && (pi2s_config->tx_isr_cnt%40==0))
3368 +               {
3369 +                       MSG("tisr i=%u,ch=%u,o=%u,u=%d,s=%X [r=%d,w=%d]\n",\
3370 +                               pi2s_config->tx_isr_cnt,dma_ch,pi2s_status->txovrun,pi2s_status->txunrun,\
3371 +                               i2s_inw(I2S_INT_STATUS),pi2s_config->tx_r_idx,pi2s_config->tx_w_idx);
3372 +               }
3373 +       }
3374 +
3375 +       if(pi2s_config->enLable == 2)
3376 +       {
3377 +               if((pi2s_config->rx_isr_cnt>0) && (pi2s_config->rx_isr_cnt%40==0))
3378 +               {
3379 +                       MSG("risr i=%u,ch=%u,o=%u,u=%d,s=%X [r=%d,w=%d]\n",\
3380 +                               pi2s_config->rx_isr_cnt,dma_ch,pi2s_status->rxovrun,pi2s_status->rxunrun,\
3381 +                               i2s_inw(I2S_INT_STATUS),pi2s_config->rx_r_idx,pi2s_config->rx_w_idx);
3382 +               }
3383 +       }
3384 +#endif
3385 +
3386 +       *(unsigned long*)(I2S_INT_STATUS) = 0xFFFFFFFF;
3387 +}
3388 +#endif
3389 +
3390 +#if defined(I2S_HW_INTERRUPT_EN)&&(I2S_SW_IRQ_EN)
3391 +irqreturn_t i2s_irq_isr(int irq, void *irqaction)
3392 +{
3393 +       u32 i2s_status;
3394 +
3395 +       //MSG("i2s_irq_isr [0x%08X]\n",i2s_inw(I2S_INT_STATUS));
3396 +       if((pi2s_config->tx_isr_cnt>0)||(pi2s_config->rx_isr_cnt>0))
3397 +       {
3398 +               i2s_status = i2s_inw(I2S_INT_STATUS);
3399 +               MSG("i2s_irq_isr [0x%08X]\n",i2s_status);
3400 +       }
3401 +       else
3402 +               return IRQ_HANDLED;
3403 +
3404 +       if(i2s_status&REGBIT(1, I2S_TX_DMA_FAULT))
3405 +       {
3406 +#ifdef I2S_STATISTIC
3407 +               pi2s_status->txdmafault++;
3408 +#endif
3409 +       }
3410 +       if(i2s_status&REGBIT(1, I2S_TX_OVRUN))
3411 +       {
3412 +#ifdef I2S_STATISTIC
3413 +               pi2s_status->txovrun++;
3414 +#endif
3415 +       }
3416 +       if(i2s_status&REGBIT(1, I2S_TX_UNRUN))
3417 +       {
3418 +#ifdef I2S_STATISTIC
3419 +               pi2s_status->txunrun++;
3420 +#endif
3421 +       }
3422 +       if(i2s_status&REGBIT(1, I2S_TX_THRES))
3423 +       {
3424 +#ifdef I2S_STATISTIC
3425 +               pi2s_status->txthres++;
3426 +#endif
3427 +       }
3428 +       if(i2s_status&REGBIT(1, I2S_RX_DMA_FAULT))
3429 +       {
3430 +#ifdef I2S_STATISTIC
3431 +               pi2s_status->rxdmafault++;
3432 +#endif
3433 +       }
3434 +       if(i2s_status&REGBIT(1, I2S_RX_OVRUN))
3435 +       {
3436 +#ifdef I2S_STATISTIC
3437 +               pi2s_status->rxovrun++;
3438 +#endif
3439 +       }
3440 +       if(i2s_status&REGBIT(1, I2S_RX_UNRUN))
3441 +       {
3442 +#ifdef I2S_STATISTIC
3443 +               pi2s_status->rxunrun++;
3444 +#endif
3445 +       }
3446 +       if(i2s_status&REGBIT(1, I2S_RX_THRES))
3447 +       {
3448 +#ifdef I2S_STATISTIC
3449 +               pi2s_status->rxthres++;
3450 +#endif
3451 +       }
3452 +       i2s_outw(I2S_INT_STATUS, 0xFFFFFFFF);
3453 +       return IRQ_HANDLED;
3454 +}
3455 +#endif
3456 +
3457 +void i2s_tx_task(unsigned long pData)
3458 +{
3459 +       unsigned long flags;
3460 +       spin_lock_irqsave(&pi2s_config->lock, flags);
3461 +       //if (pi2s_config->bTxDMAEnable!=0)
3462 +       {
3463 +               if (pi2s_config->tx_unmask_ch!=0)
3464 +               {
3465 +                       u32 dmach = pi2s_config->tx_unmask_ch;
3466 +                       u32 ch;
3467 +                       for (ch = 0; ch < 16; ch++)
3468 +                       {
3469 +                               if (dmach& (1<<ch))
3470 +                               {
3471 +                                       MSG("do unmask ch%d tisr=%d in tx_isr\n",ch,pi2s_config->tx_isr_cnt);
3472 +                                       GdmaUnMaskChannel(ch);
3473 +                               }
3474 +                       }
3475 +                       pi2s_config->tx_unmask_ch = 0;
3476 +               }
3477 +       }
3478 +       spin_unlock_irqrestore(&pi2s_config->lock, flags);
3479 +}
3480 +
3481 +void i2s_rx_task(unsigned long pData)
3482 +{
3483 +       unsigned long flags;
3484 +       spin_lock_irqsave(&pi2s_config->lock, flags);
3485 +       //if (pi2s_config->bRxDMAEnable!=0)
3486 +       {
3487 +               if (pi2s_config->rx_unmask_ch!=0)
3488 +               {
3489 +                       u32 dmach = pi2s_config->rx_unmask_ch;
3490 +                       u32 ch;
3491 +                       for (ch = 0; ch < 16; ch++)
3492 +                       {
3493 +                               if (dmach& (1<<ch))
3494 +                               {
3495 +                                       MSG("do unmask ch%d risr=%d in rx_isr\n",ch,pi2s_config->rx_isr_cnt);
3496 +                                       GdmaUnMaskChannel(ch);
3497 +                               }
3498 +                       }
3499 +                       pi2s_config->rx_unmask_ch = 0;
3500 +
3501 +               }
3502 +       }
3503 +       spin_unlock_irqrestore(&pi2s_config->lock, flags);
3504 +}
3505 +
3506 +
3507 +void i2s_dma_unmask_handler(u32 dma_ch)
3508 +{
3509 +       MSG("i2s_dma_unmask_handler ch=%d\n",dma_ch);
3510 +
3511 +       GdmaUnMaskChannel(dma_ch);
3512 +
3513 +       return;
3514 +}
3515 +
3516 +void i2s_dma_tx_unmask_handler(u32 dma_ch)
3517 +{
3518 +       MSG("i2s_dma_tx_unmask_handler ch=%d\n",dma_ch);
3519 +       pi2s_config->tx_unmask_ch |= (1<<dma_ch);
3520 +       tasklet_hi_schedule(&i2s_tx_tasklet);
3521 +       return;
3522 +}
3523 +
3524 +void i2s_dma_rx_unmask_handler(u32 dma_ch)
3525 +{
3526 +       MSG("i2s_dma_rx_unmask_handler ch=%d\n",dma_ch);
3527 +       pi2s_config->rx_unmask_ch |= (1<<dma_ch);
3528 +       tasklet_hi_schedule(&i2s_rx_tasklet);
3529 +       return;
3530 +}
3531 +
3532 +void i2s_dma_mask_handler(u32 dma_ch)
3533 +{
3534 +        MSG("i2s_dma_mask_handler ch=%d\n", dma_ch);
3535 +        GdmaMaskChannel(dma_ch);
3536 +        return;
3537 +}
3538 +
3539 +void i2s_dma_tx_init(i2s_config_type* ptri2s_config)
3540 +{
3541 +       memset(pi2s_config->pPage0TxBuf8ptr, 0, I2S_PAGE_SIZE);
3542 +       memset(pi2s_config->pPage1TxBuf8ptr, 0, I2S_PAGE_SIZE);
3543 +#if defined(ARM_ARCH)
3544 +       GdmaI2sTx(i2s_txdma_addr0, I2S_TX_FIFO_WREG_PHY, 0, I2S_PAGE_SIZE, i2s_dma_tx_handler, i2s_dma_tx_unmask_handler);
3545 +       GdmaI2sTx(i2s_txdma_addr1, I2S_TX_FIFO_WREG_PHY, 1, I2S_PAGE_SIZE, i2s_dma_tx_handler, i2s_dma_tx_unmask_handler);
3546 +#else
3547 +       GdmaI2sTx((u32)ptri2s_config->pPage0TxBuf8ptr, I2S_FIFO_WREG, 0, I2S_PAGE_SIZE, i2s_dma_tx_handler, i2s_dma_tx_unmask_handler);
3548 +       GdmaI2sTx((u32)ptri2s_config->pPage1TxBuf8ptr, I2S_FIFO_WREG, 1, I2S_PAGE_SIZE, i2s_dma_tx_handler, i2s_dma_tx_unmask_handler);
3549 +#endif
3550 +
3551 +       return;
3552 +}
3553 +
3554 +void i2s_dma_rx_init(i2s_config_type* ptri2s_config)
3555 +{
3556 +       memset(pi2s_config->pPage0RxBuf8ptr, 0, I2S_PAGE_SIZE);
3557 +       memset(pi2s_config->pPage1RxBuf8ptr, 0, I2S_PAGE_SIZE);
3558 +
3559 +#if defined(ARM_ARCH)
3560 +       GdmaI2sRx(I2S_RX_FIFO_RREG_PHY, i2s_rxdma_addr0, 0, I2S_PAGE_SIZE, i2s_dma_rx_handler, i2s_dma_rx_unmask_handler);
3561 +       GdmaI2sRx(I2S_RX_FIFO_RREG_PHY, i2s_rxdma_addr1, 1, I2S_PAGE_SIZE, i2s_dma_rx_handler, i2s_dma_rx_unmask_handler);
3562 +#else
3563 +       GdmaI2sRx(I2S_RX_FIFO_RREG, (u32)ptri2s_config->pPage0RxBuf8ptr, 0, I2S_PAGE_SIZE, i2s_dma_rx_handler, i2s_dma_rx_unmask_handler);
3564 +       GdmaI2sRx(I2S_RX_FIFO_RREG, (u32)ptri2s_config->pPage1RxBuf8ptr, 1, I2S_PAGE_SIZE, i2s_dma_rx_handler, i2s_dma_rx_unmask_handler);
3565 +#endif
3566 +
3567 +       return;
3568 +}
3569 +
3570 +void i2s_dma_tx_end_handle(i2s_config_type* ptri2s_config)
3571 +{
3572 +       if (ptri2s_config->tx_w_idx < ptri2s_config->tx_r_idx)
3573 +        {
3574 +               ptri2s_config->end_cnt = (ptri2s_config->tx_w_idx + MAX_I2S_PAGE)-ptri2s_config->tx_r_idx;
3575 +                _printk("case1: w=%d, r=%d, end=%d\n", ptri2s_config->tx_w_idx, ptri2s_config->tx_r_idx, ptri2s_config->end_cnt);
3576 +        }
3577 +        else if (ptri2s_config->tx_w_idx > ptri2s_config->tx_r_idx)
3578 +        {
3579 +                ptri2s_config->end_cnt = ptri2s_config->tx_w_idx-ptri2s_config->tx_r_idx;
3580 +                _printk("case2: w=%d, r=%d, end=%d\n", ptri2s_config->tx_w_idx, ptri2s_config->tx_r_idx, ptri2s_config->end_cnt);
3581 +        }
3582 +       else
3583 +       {
3584 +               _printk("case3: w=%d, r=%d, end=%d\n", ptri2s_config->tx_w_idx, ptri2s_config->tx_r_idx, ptri2s_config->end_cnt);
3585 +
3586 +       }
3587 +
3588 +       if (ptri2s_config->end_cnt > 0)
3589 +       {
3590 +               interruptible_sleep_on(&(ptri2s_config->i2s_tx_qh));
3591 +       }
3592 +
3593 +       return;
3594 +}
3595 +
3596 +void i2s_tx_end_sleep_on(i2s_config_type* ptri2s_config)
3597 +{
3598 +       while(ptri2s_config->tx_stop_cnt<3)
3599 +               interruptible_sleep_on(&(ptri2s_config->i2s_tx_qh));
3600 +
3601 +       return;
3602 +}
3603 +
3604 +void i2s_rx_end_sleep_on(i2s_config_type* ptri2s_config)
3605 +{
3606 +       while(ptri2s_config->rx_stop_cnt<2)
3607 +               interruptible_sleep_on(&(ptri2s_config->i2s_rx_qh));
3608 +       return;
3609 +}
3610 +
3611 +int i2s_dma_tx_soft_stop(i2s_config_type* ptri2s_config, u32 dma_ch)
3612 +{
3613 +       if(dma_ch==GDMA_I2S_TX0)
3614 +        {
3615 +#if defined(ARM_ARCH)
3616 +               GdmaI2sTx(i2s_txdma_addr0, I2S_TX_FIFO_WREG_PHY, 0, 4, i2s_dma_tx_handler, i2s_dma_tx_unmask_handler);
3617 +#else
3618 +               GdmaI2sTx((u32)pi2s_config->pPage0TxBuf8ptr, I2S_TX_FIFO_WREG, 0, 4, i2s_dma_tx_handler, i2s_dma_tx_unmask_handler);
3619 +#endif
3620 +        }
3621 +        else
3622 +        {
3623 +#if defined(ARM_ARCH)
3624 +               GdmaI2sTx(i2s_txdma_addr1, I2S_TX_FIFO_WREG_PHY, 1, 4, i2s_dma_tx_handler, i2s_dma_tx_unmask_handler);
3625 +#else
3626 +                GdmaI2sTx((u32)pi2s_config->pPage1TxBuf8ptr, I2S_TX_FIFO_WREG, 1, 4, i2s_dma_tx_handler, i2s_dma_tx_unmask_handler);
3627 +#endif
3628 +        }
3629 +
3630 +       return 0;
3631 +}
3632 +
3633 +int i2s_dma_rx_soft_stop(i2s_config_type* ptri2s_config, u32 dma_ch)
3634 +{
3635 +       if(dma_ch==GDMA_I2S_RX0)
3636 +        {
3637 +               memset(pi2s_config->pPage0RxBuf8ptr, 0, I2S_PAGE_SIZE);
3638 +#if defined(ARM_ARCH)
3639 +               GdmaI2sRx(I2S_RX_FIFO_RREG_PHY, i2s_rxdma_addr0, 0, 4, i2s_dma_rx_handler, i2s_dma_rx_unmask_handler);
3640 +#else
3641 +               GdmaI2sRx(I2S_RX_FIFO_RREG, (u32)pi2s_config->pPage0RxBuf8ptr, 0, 4, i2s_dma_rx_handler, i2s_dma_rx_unmask_handler);
3642 +#endif
3643 +        }
3644 +        else
3645 +        {
3646 +               memset(pi2s_config->pPage1RxBuf8ptr, 0, I2S_PAGE_SIZE);
3647 +#if defined(ARM_ARCH)
3648 +               GdmaI2sRx(I2S_RX_FIFO_RREG_PHY, i2s_rxdma_addr1, 1, 4, i2s_dma_rx_handler, i2s_dma_rx_unmask_handler);
3649 +#else
3650 +                GdmaI2sRx(I2S_RX_FIFO_RREG, (u32)pi2s_config->pPage1RxBuf8ptr, 1, 4, i2s_dma_rx_handler, i2s_dma_rx_unmask_handler);
3651 +#endif
3652 +        }
3653 +
3654 +       return 0;
3655 +}
3656 +
3657 +void i2s_gen_test_pattern(void)
3658 +{
3659 +       int i;
3660 +       for (i=0; i<I2S_PAGE_SIZE; i++)
3661 +       {
3662 +               test_buf[i] = 0x5A;
3663 +               test_buf_1[i] = 0x11;
3664 +               test_buf_2[i] = 0x22;
3665 +
3666 +       }
3667 +}
3668 +
3669 +int i2s_put_audio(i2s_config_type* ptri2s_config, unsigned long arg)
3670 +{
3671 +       unsigned long flags;
3672 +       int tx_w_idx;
3673 +
3674 +       do{
3675 +               spin_lock_irqsave(&ptri2s_config->lock, flags);
3676 +
3677 +               if(((ptri2s_config->tx_w_idx+4)%MAX_I2S_PAGE)!=ptri2s_config->tx_r_idx)
3678 +               {
3679 +                       ptri2s_config->tx_w_idx = (ptri2s_config->tx_w_idx+1)%MAX_I2S_PAGE;
3680 +                       tx_w_idx = ptri2s_config->tx_w_idx;
3681 +                       spin_unlock_irqrestore(&ptri2s_config->lock, flags);
3682 +                       //_printk("put TB[%d] for user write\n",ptri2s_config->tx_w_idx);
3683 +#if defined(CONFIG_I2S_MMAP)
3684 +                       put_user(tx_w_idx, (int*)arg);
3685 +#else
3686 +                       copy_from_user(ptri2s_config->pMMAPTxBufPtr[tx_w_idx], (char*)arg, I2S_PAGE_SIZE);
3687 +#endif
3688 +                       pi2s_status->txbuffer_len++;
3689 +                       //spin_unlock_irqrestore(&ptri2s_config->lock, flags);
3690 +                       break;
3691 +               }
3692 +               else
3693 +               {
3694 +                       /* Buffer Full */
3695 +                       //_printk("TBF tr=%d, tw=%d\n", ptri2s_config->tx_r_idx, ptri2s_config->tx_w_idx);
3696 +                       pi2s_status->txbuffer_ovrun++;
3697 +                       spin_unlock_irqrestore(&ptri2s_config->lock, flags);
3698 +                       interruptible_sleep_on(&(ptri2s_config->i2s_tx_qh));
3699 +                       if (ptri2s_config->bTxDMAEnable==0 && ptri2s_config->end_cnt==0)
3700 +                       {
3701 +                               _printk("wake up for exit i2s driver\n");
3702 +                               put_user(-1, (int*)arg);
3703 +                               break;
3704 +                       }
3705 +               }
3706 +       }while(1);
3707 +
3708 +       return 0;
3709 +}
3710 +
3711 +int i2s_get_audio(i2s_config_type* ptri2s_config, unsigned long arg)
3712 +{
3713 +       unsigned long flags;
3714 +       int rx_r_idx;
3715 +
3716 +       do{
3717 +               spin_lock_irqsave(&ptri2s_config->lock, flags);
3718 +               //_printk("GA rr=%d, rw=%d,i=%d\n", ptri2s_config->rx_r_idx, ptri2s_config->rx_w_idx,ptri2s_config->rx_isr_cnt);
3719 +               if(((ptri2s_config->rx_r_idx+2)%MAX_I2S_PAGE)!=ptri2s_config->rx_w_idx)
3720 +               {
3721 +                       rx_r_idx = ptri2s_config->rx_r_idx;
3722 +                       ptri2s_config->rx_r_idx = (ptri2s_config->rx_r_idx+1)%MAX_I2S_PAGE;
3723 +                       spin_unlock_irqrestore(&ptri2s_config->lock, flags);
3724 +#if defined(CONFIG_I2S_MMAP)
3725 +                       put_user(rx_r_idx, (int*)arg);
3726 +#else
3727 +                       copy_to_user((char*)arg, ptri2s_config->pMMAPRxBufPtr[rx_r_idx], I2S_PAGE_SIZE);
3728 +#endif
3729 +                       //_printk("rx_r_idx=%d\n", ptri2s_config->rx_r_idx);
3730 +                       //ptri2s_config->rx_r_idx = (ptri2s_config->rx_r_idx+1)%MAX_I2S_PAGE;
3731 +                       pi2s_status->rxbuffer_len--;
3732 +                       //spin_unlock_irqrestore(&ptri2s_config->lock, flags);
3733 +                       break;
3734 +               }
3735 +               else
3736 +               {
3737 +                       /* Buffer Full */
3738 +                       //_printk("RBF rr=%d, rw=%d\n", ptri2s_config->rx_r_idx, ptri2s_config->rx_w_idx);
3739 +                       pi2s_status->rxbuffer_ovrun++;
3740 +                       spin_unlock_irqrestore(&ptri2s_config->lock, flags);
3741 +                       interruptible_sleep_on(&(ptri2s_config->i2s_rx_qh));
3742 +               }
3743 +#if defined(CONFIG_I2S_WITH_AEC)
3744 +               if(aecFuncP->AECECDeq){
3745 +                       aecFuncP->AECECDeq(0,pi2s_config->pMMAPRxBufPtr[ptri2s_config->rx_r_idx],I2S_PAGE_SIZE);
3746 +               }
3747 +#endif
3748 +       }while(1);
3749 +
3750 +       return 0;
3751 +}
3752 +
3753 +#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,35)
3754 +long i2s_ioctl (struct file *filp, unsigned int cmd, unsigned long arg)
3755 +#else
3756 +int i2s_ioctl (struct inode *inode, struct file *filp, unsigned int cmd, unsigned long arg)
3757 +#endif
3758 +{
3759 +       int i ;
3760 +       i2s_config_type* ptri2s_config;
3761 +       unsigned long flags;
3762 +
3763 +       ptri2s_config = filp->private_data;
3764 +       switch (cmd) {
3765 +       case I2S_RESET:
3766 +               spin_lock_irqsave(&ptri2s_config->lock, flags);
3767 +               i2s_reset_config(ptri2s_config);
3768 +               spin_unlock_irqrestore(&ptri2s_config->lock, flags);
3769 +               break;
3770 +       case I2S_SRATE:
3771 +               spin_lock_irqsave(&ptri2s_config->lock, flags);
3772 +#if defined(CONFIG_I2S_WM8960)
3773 +               if((arg>MAX_SRATE_HZ)||(arg<MIN_SRATE_HZ))
3774 +               {
3775 +                       MSG("Audio sampling rate %u should be %d ~ %d Hz. Set SRate to 48000Hz\n", (u32)arg, MIN_SRATE_HZ, MAX_SRATE_HZ);
3776 +                       ptri2s_config->srate = 48000;
3777 +                       spin_unlock(&ptri2s_config->lock);
3778 +                       break;
3779 +               }
3780 +#elif defined(CONFIG_I2S_WM8750)
3781 +               if((arg>MAX_SRATE_HZ)||(arg<MIN_SRATE_HZ))
3782 +               {
3783 +                       MSG("Audio sampling rate %u should be %d ~ %d Hz. Set SRate to 96000Hz\n", (u32)arg, MIN_SRATE_HZ, MAX_SRATE_HZ);
3784 +                       ptri2s_config->srate = 96000;
3785 +                       spin_unlock(&ptri2s_config->lock);
3786 +                       break;
3787 +               }
3788 +#endif
3789 +               ptri2s_config->srate = arg;
3790 +               spin_unlock_irqrestore(&ptri2s_config->lock, flags);
3791 +               MSG("set audio sampling rate to %d Hz\n", ptri2s_config->srate);
3792 +               break;
3793 +       case I2S_TX_VOL:
3794 +               spin_lock_irqsave(&ptri2s_config->lock, flags);
3795 +
3796 +               if((int)arg > 127)
3797 +                       ptri2s_config->txvol = 127;
3798 +               else if((int)arg < 48)
3799 +                       ptri2s_config->txvol = 48;
3800 +               else
3801 +                       ptri2s_config->txvol = arg;
3802 +
3803 +               spin_unlock_irqrestore(&ptri2s_config->lock, flags);
3804 +
3805 +               spin_lock_irqsave(&ptri2s_config->lock, flags);
3806 +#if (defined(CONFIG_I2S_WM8750) || defined(CONFIG_I2S_WM8751))
3807 +               audiohw_set_master_vol(arg,arg);
3808 +#elif defined(CONFIG_I2S_WM8960)
3809 +               audiohw_set_lineout_vol(1, ptri2s_config->txvol, ptri2s_config->txvol);
3810 +#endif
3811 +               spin_unlock_irqrestore(&ptri2s_config->lock, flags);
3812 +               break;
3813 +       case I2S_RX_VOL:
3814 +               spin_lock_irqsave(&ptri2s_config->lock, flags);
3815 +
3816 +               if((int)arg > 63)
3817 +                       ptri2s_config->rxvol = 63;
3818 +               else if((int)arg < 0)
3819 +                       ptri2s_config->rxvol = 0;
3820 +               else
3821 +                       ptri2s_config->rxvol = arg;
3822 +
3823 +               spin_unlock_irqrestore(&ptri2s_config->lock, flags);
3824 +               break;
3825 +#if defined (CONFIG_RALINK_MT7628) || defined(CONFIG_ARCH_MT7623)
3826 +       case I2S_WORD_LEN:
3827 +               spin_lock_irqsave(&ptri2s_config->lock, flags);
3828 +               if((int)arg == 16)
3829 +               {
3830 +                       ptri2s_config->wordlen_24b = 0;
3831 +                       MSG("Enable 16 bit word length.\n");
3832 +               }
3833 +               else if ((int)arg == 24)
3834 +               {
3835 +                       ptri2s_config->wordlen_24b = 1;
3836 +                       MSG("Enable 24 bit word length.\n");
3837 +               }
3838 +               else
3839 +               {
3840 +                       MSG("MT7628 only support 16bit/24bit word length.\n");
3841 +                       spin_unlock(&ptri2s_config->lock);
3842 +                       break;
3843 +               }
3844 +               spin_unlock_irqrestore(&ptri2s_config->lock, flags);
3845 +               break;
3846 +       case I2S_ENDIAN_FMT:
3847 +               spin_lock_irqsave(&ptri2s_config->lock, flags);
3848 +               if((int)arg == 1)
3849 +               {
3850 +                       ptri2s_config->little_edn = 1;
3851 +                       MSG("Little endian format.\n");
3852 +               }
3853 +               else
3854 +               {
3855 +                       ptri2s_config->little_edn = 0;
3856 +                       MSG("Big endian format.\n");
3857 +               }
3858 +               spin_unlock_irqrestore(&ptri2s_config->lock, flags);
3859 +               break;
3860 +#endif
3861 +       case I2S_INTERNAL_LBK:
3862 +               spin_lock_irqsave(&ptri2s_config->lock, flags);
3863 +               if((int)arg == 1)
3864 +               {
3865 +                       ptri2s_config->lbk = 1;
3866 +                       MSG("Enable internal loopback.\n");
3867 +               }
3868 +               else
3869 +               {
3870 +                       ptri2s_config->lbk = 0;
3871 +                       MSG("Disable internal loopback.\n");
3872 +               }
3873 +               spin_unlock_irqrestore(&ptri2s_config->lock, flags);
3874 +               break;
3875 +       case I2S_EXTERNAL_LBK:
3876 +               spin_lock_irqsave(&ptri2s_config->lock, flags);
3877 +               if((int)arg == 1)
3878 +               {
3879 +                       ptri2s_config->extlbk = 1;
3880 +                       MSG("Enable external loopback.\n");
3881 +               }
3882 +               else
3883 +               {
3884 +                       ptri2s_config->extlbk = 0;
3885 +                       MSG("Disable external loopback.\n");
3886 +               }
3887 +               spin_unlock_irqrestore(&ptri2s_config->lock, flags);
3888 +               break;
3889 +       case I2S_TXRX_COEXIST:
3890 +               spin_lock_irqsave(&ptri2s_config->lock, flags);
3891 +               if((int)arg == 1)
3892 +               {
3893 +                       ptri2s_config->txrx_coexist = 1;
3894 +                       MSG("TX/RX coexist.\n");
3895 +               }
3896 +               else
3897 +               {
3898 +                       ptri2s_config->txrx_coexist = 0;
3899 +                       MSG("TX/RX coexist.\n");
3900 +               }
3901 +               spin_unlock_irqrestore(&ptri2s_config->lock, flags);
3902 +               break;
3903 +
3904 +       case I2S_TX_ENABLE:
3905 +               spin_lock_irqsave(&ptri2s_config->lock, flags);
3906 +               MSG("I2S_TXENABLE\n");
3907 +
3908 +               pi2s_config->tx_unmask_ch = 0;
3909 +               tasklet_init(&i2s_tx_tasklet, i2s_tx_task, (u32)pi2s_config);
3910 +
3911 +               pi2s_config->dis_match = 0;
3912 +               pi2s_config->start_cnt = 0;
3913 +               i2s_gen_test_pattern();
3914 +
3915 +               /* allocate tx buffer */
3916 +               i2s_txPagebuf_alloc(ptri2s_config);
3917 +               i2s_txbuf_alloc(ptri2s_config);
3918 +
3919 +               /* Init two dma channels */
3920 +               i2s_dma_tx_init(ptri2s_config);
3921 +               spin_unlock_irqrestore(&ptri2s_config->lock, flags);
3922 +
3923 +               spin_lock_irqsave(&ptri2s_config->lock, flags);
3924 +               /* Init & config all tx param */
3925 +               i2s_reset_tx_param(ptri2s_config);
3926 +               ptri2s_config->bTxDMAEnable = 1;
3927 +               /* Clear all ALSA related config */
3928 +               ptri2s_config->bALSAEnable = 0;
3929 +               ptri2s_config->bALSAMMAPEnable = 0;
3930 +
3931 +               i2s_tx_config(ptri2s_config);
3932 +
3933 +               if(ptri2s_config->bRxDMAEnable==0)
3934 +                       i2s_clock_enable(ptri2s_config);
3935 +               spin_unlock_irqrestore(&ptri2s_config->lock, flags);
3936 +
3937 +               spin_lock_irqsave(&ptri2s_config->lock, flags);
3938 +#if defined(CONFIG_I2S_WM8960)||defined(CONFIG_I2S_WM8750)||defined(CONFIG_I2S_WM8751)
3939 +               audiohw_set_lineout_vol(1, ptri2s_config->txvol, ptri2s_config->txvol);
3940 +#endif
3941 +               GdmaUnMaskChannel(GDMA_I2S_TX0);
3942 +
3943 +               i2s_tx_enable(ptri2s_config);
3944 +
3945 +               /* Kick off dma channel */
3946 +               //GdmaUnMaskChannel(GDMA_I2S_TX0);
3947 +
3948 +               MSG("I2S_TXENABLE done\n");
3949 +               spin_unlock_irqrestore(&ptri2s_config->lock, flags);
3950 +               break;
3951 +       case I2S_TX_DISABLE:
3952 +               spin_lock_irqsave(&ptri2s_config->lock, flags);
3953 +               MSG("I2S_TXDISABLE\n");
3954 +
3955 +               //tasklet_kill(&i2s_tx_tasklet);
3956 +
3957 +               /* Handle tx end data */
3958 +               ptri2s_config->bTxDMAEnable = 0;
3959 +               spin_unlock_irqrestore(&ptri2s_config->lock, flags);
3960 +
3961 +               i2s_tx_end_sleep_on(ptri2s_config);
3962 +
3963 +               tasklet_kill(&i2s_tx_tasklet);
3964 +
3965 +               spin_lock_irqsave(&ptri2s_config->lock, flags);
3966 +               i2s_reset_tx_param(ptri2s_config);
3967 +               i2s_tx_disable(ptri2s_config);
3968 +               if((ptri2s_config->bRxDMAEnable==0)&&(ptri2s_config->bTxDMAEnable==0))
3969 +                       i2s_clock_disable(ptri2s_config);
3970 +
3971 +               i2s_txbuf_free(ptri2s_config);
3972 +               if(ptri2s_config->mmap_index <= MAX_I2S_PAGE)
3973 +                       ptri2s_config->mmap_index = 0;
3974 +
3975 +               spin_unlock_irqrestore(&ptri2s_config->lock, flags);
3976 +               break;
3977 +       case I2S_RX_ENABLE:
3978 +               spin_lock_irqsave(&ptri2s_config->lock, flags);
3979 +               MSG("I2S_RXENABLE\n");
3980 +               pi2s_config->rx_unmask_ch = 0;
3981 +               tasklet_init(&i2s_rx_tasklet, i2s_rx_task, (u32)pi2s_config);
3982 +
3983 +               /* allocate rx buffer */
3984 +               i2s_rxPagebuf_alloc(ptri2s_config);
3985 +               i2s_rxbuf_alloc(ptri2s_config);
3986 +
3987 +               /* Init two dma channels */
3988 +               i2s_dma_rx_init(ptri2s_config);
3989 +               spin_unlock_irqrestore(&ptri2s_config->lock, flags);
3990 +
3991 +               spin_lock_irqsave(&ptri2s_config->lock, flags);
3992 +               /* Init & config all rx param */
3993 +               i2s_reset_rx_param(ptri2s_config);
3994 +               ptri2s_config->bRxDMAEnable = 1;
3995 +               ptri2s_config->bALSAEnable = 0;
3996 +               ptri2s_config->bALSAMMAPEnable = 0;
3997 +
3998 +               i2s_rx_config(ptri2s_config);
3999 +
4000 +               if(ptri2s_config->bTxDMAEnable==0)
4001 +                       i2s_clock_enable(ptri2s_config);
4002 +
4003 +#if defined(CONFIG_I2S_TXRX)
4004 +#if defined(CONFIG_I2S_WM8960)||defined(CONFIG_I2S_WM8750)||defined(CONFIG_I2S_WM8751)
4005 +               audiohw_set_linein_vol(ptri2s_config->rxvol,  ptri2s_config->rxvol);
4006 +#endif
4007 +#endif
4008 +               spin_unlock_irqrestore(&ptri2s_config->lock, flags);
4009 +
4010 +               spin_lock_irqsave(&ptri2s_config->lock, flags);
4011 +               /* Kick off dma channel */
4012 +               GdmaUnMaskChannel(GDMA_I2S_RX0);
4013 +
4014 +               i2s_rx_enable(ptri2s_config);
4015 +               spin_unlock_irqrestore(&ptri2s_config->lock, flags);
4016 +               break;
4017 +       case I2S_RX_DISABLE:
4018 +               spin_lock_irqsave(&ptri2s_config->lock, flags);
4019 +               MSG("I2S_RXDISABLE\n");
4020 +               //tasklet_kill(&i2s_rx_tasklet);
4021 +
4022 +               ptri2s_config->bRxDMAEnable = 0;
4023 +               spin_unlock_irqrestore(&ptri2s_config->lock, flags);
4024 +
4025 +               i2s_rx_end_sleep_on(ptri2s_config);
4026 +               tasklet_kill(&i2s_rx_tasklet);
4027 +
4028 +               spin_lock_irqsave(&ptri2s_config->lock, flags);
4029 +               i2s_reset_rx_param(ptri2s_config);
4030 +               i2s_rx_disable(ptri2s_config);
4031 +               if((ptri2s_config->bRxDMAEnable==0)&&(ptri2s_config->bTxDMAEnable==0))
4032 +                       i2s_clock_disable(ptri2s_config);
4033 +
4034 +               i2s_rxbuf_free(ptri2s_config);
4035 +               if(ptri2s_config->mmap_index <= MAX_I2S_PAGE)
4036 +                       ptri2s_config->mmap_index = 0;
4037 +               //i2s_rxPagebuf_free(ptri2s_config);
4038 +               spin_unlock_irqrestore(&ptri2s_config->lock, flags);
4039 +               break;
4040 +       case I2S_PUT_AUDIO:
4041 +               i2s_put_audio(ptri2s_config, arg);
4042 +               break;
4043 +       case I2S_GET_AUDIO:
4044 +               i2s_get_audio(ptri2s_config, arg);
4045 +               break;
4046 +       case I2S_TX_STOP:
4047 +               spin_lock_irqsave(&ptri2s_config->lock, flags);
4048 +               MSG("TxGDMA STOP\n");
4049 +               ptri2s_config->bTxDMAEnable = 0;
4050 +               ptri2s_config->end_cnt = 0;
4051 +               spin_unlock_irqrestore(&ptri2s_config->lock, flags);
4052 +
4053 +               while(ptri2s_config->tx_stop_cnt<3)
4054 +                        interruptible_sleep_on(&(ptri2s_config->i2s_tx_qh));
4055 +
4056 +               spin_lock_irqsave(&ptri2s_config->lock, flags);
4057 +               i2s_reset_tx_param(ptri2s_config);
4058 +               i2s_tx_disable(ptri2s_config);
4059 +               if((ptri2s_config->bRxDMAEnable==0)&&(ptri2s_config->bTxDMAEnable==0))
4060 +                       i2s_clock_disable(ptri2s_config);
4061 +
4062 +               spin_unlock_irqrestore(&ptri2s_config->lock, flags);
4063 +
4064 +               spin_lock_irqsave(&ptri2s_config->lock, flags);
4065 +               i2s_txbuf_free(ptri2s_config);
4066 +               if(ptri2s_config->mmap_index <= MAX_I2S_PAGE)
4067 +                       ptri2s_config->mmap_index = 0;
4068 +               //i2s_txPagebuf_free(ptri2s_config);
4069 +               spin_unlock_irqrestore(&ptri2s_config->lock, flags);
4070 +               break;
4071 +       case I2S_TX_PAUSE:
4072 +               spin_lock_irqsave(&ptri2s_config->lock, flags);
4073 +                ptri2s_config->tx_pause_en = 1;
4074 +               MSG("* tx_pause_en = 1 *\n");
4075 +               spin_unlock_irqrestore(&ptri2s_config->lock, flags);
4076 +                break;
4077 +       case I2S_TX_RESUME:
4078 +               spin_lock_irqsave(&ptri2s_config->lock, flags);
4079 +                ptri2s_config->tx_pause_en = 0;
4080 +               MSG("# tx_pause_en = 0 #\n");
4081 +               spin_unlock_irqrestore(&ptri2s_config->lock, flags);
4082 +                break;
4083 +       case I2S_RX_STOP:
4084 +               spin_lock_irqsave(&ptri2s_config->lock, flags);
4085 +               MSG("I2S_RX_STOP\n");
4086 +               ptri2s_config->bRxDMAEnable = 0;
4087 +               spin_unlock_irqrestore(&ptri2s_config->lock, flags);
4088 +
4089 +               while(ptri2s_config->rx_stop_cnt<2)
4090 +                        interruptible_sleep_on(&(ptri2s_config->i2s_rx_qh));
4091 +
4092 +               spin_lock_irqsave(&ptri2s_config->lock, flags);
4093 +               i2s_reset_rx_param(ptri2s_config);
4094 +               i2s_rx_disable(ptri2s_config);
4095 +               if((ptri2s_config->bRxDMAEnable==0)&&(ptri2s_config->bTxDMAEnable==0))
4096 +                       i2s_clock_disable(ptri2s_config);
4097 +               spin_unlock_irqrestore(&ptri2s_config->lock, flags);
4098 +
4099 +               spin_lock_irqsave(&ptri2s_config->lock, flags);
4100 +               i2s_rxbuf_free(ptri2s_config);
4101 +               if(ptri2s_config->mmap_index <= MAX_I2S_PAGE)
4102 +                       ptri2s_config->mmap_index = 0;
4103 +               //i2s_rxPagebuf_free(ptri2s_config);
4104 +               spin_unlock_irqrestore(&ptri2s_config->lock, flags);
4105 +               break;
4106 +       case I2S_RX_PAUSE:
4107 +               spin_lock_irqsave(&ptri2s_config->lock, flags);
4108 +                ptri2s_config->rx_pause_en = 1;
4109 +               MSG("* rx_pause_en = 1 *\n");
4110 +               spin_unlock_irqrestore(&ptri2s_config->lock, flags);
4111 +                break;
4112 +       case I2S_RX_RESUME:
4113 +               spin_lock_irqsave(&ptri2s_config->lock, flags);
4114 +                ptri2s_config->rx_pause_en = 0;
4115 +               MSG("# rx_pause_en = 0 #\n");
4116 +               spin_unlock_irqrestore(&ptri2s_config->lock, flags);
4117 +                break;
4118 +       case I2S_CODEC_MIC_BOOST:
4119 +               spin_lock_irqsave(&ptri2s_config->lock, flags);
4120 +               if((int)arg > 3)
4121 +                       ptri2s_config->micboost = 3;
4122 +               else if((int)arg < 0)
4123 +                       ptri2s_config->micboost = 0;
4124 +               else
4125 +                       ptri2s_config->micboost = arg;
4126 +               spin_unlock_irqrestore(&ptri2s_config->lock, flags);
4127 +               break;
4128 +       case I2S_CODEC_MIC_IN:
4129 +               spin_lock_irqsave(&ptri2s_config->lock, flags);
4130 +               if((int)arg == 1)
4131 +                       ptri2s_config->micin = 1;
4132 +               else
4133 +                       ptri2s_config->micin = 0;
4134 +               spin_unlock_irqrestore(&ptri2s_config->lock, flags);
4135 +               break;
4136 +        case I2S_CLOCK_ENABLE:
4137 +               spin_lock_irqsave(&ptri2s_config->lock, flags);
4138 +                i2s_clock_disable(ptri2s_config);
4139 +#if defined(CONFIG_RALINK_MT7628) || defined(CONFIG_ARCH_MT7623)
4140 +                ptri2s_config->wordlen_24b = 1;
4141 +#endif
4142 +                i2s_tx_config(ptri2s_config);
4143 +                i2s_clock_enable(ptri2s_config);
4144 +                i2s_tx_enable(ptri2s_config);
4145 +                spin_unlock_irqrestore(&ptri2s_config->lock, flags);
4146 +                break;
4147 +       case I2S_DEBUG_CODEC:
4148 +               spin_lock_irqsave(&ptri2s_config->lock, flags);
4149 +               for (i=0; i<10; i++)
4150 +               {
4151 +                       _printk("### i=%d ###\n", i);
4152 +                       i2s_clock_enable(ptri2s_config);
4153 +                       i2s_clock_disable(ptri2s_config);
4154 +               }
4155 +               spin_unlock_irqrestore(&ptri2s_config->lock, flags);
4156 +               break;
4157 +#if defined(CONFIG_I2S_MS_CTRL)
4158 +       case I2S_MS_MODE_CTRL:
4159 +               spin_lock_irqsave(&ptri2s_config->lock, flags);
4160 +               if((int)arg == 1)
4161 +               {
4162 +                       ptri2s_config->slave_en = 1;
4163 +                       _printk("I2S in slave mode.\n");
4164 +               }
4165 +               else
4166 +               {
4167 +                       ptri2s_config->slave_en = 0;
4168 +                       _printk("I2S in master mode.\n");
4169 +               }
4170 +               spin_unlock_irqrestore(&ptri2s_config->lock, flags);
4171 +               break;
4172 +#endif
4173 +       case I2S_DEBUG_CLKGEN:
4174 +       case I2S_DEBUG_INLBK:
4175 +       case I2S_DEBUG_EXLBK:
4176 +       case I2S_DEBUG_CODECBYPASS:
4177 +       case I2S_DEBUG_FMT:
4178 +#if defined(CONFIG_I2S_WM8960)
4179 +       case I2S_DEBUG_CODEC_EXLBK:
4180 +#endif
4181 +       case I2S_DEBUG_RESET:
4182 +               i2s_debug_cmd(cmd, arg);
4183 +               break;
4184 +       default :
4185 +               MSG("i2s_ioctl: command format error\n");
4186 +       }
4187 +
4188 +       return 0;
4189 +}
4190 +
4191 +/************************
4192 + *      API for ALSA    *
4193 + *                      *
4194 + ************************/
4195 +char* i2s_memPool_Alloc(i2s_config_type* ptri2s_config,int dir)
4196 +{
4197 +        //_printk("%s\n",__func__);
4198 +        if(!ptri2s_config)
4199 +                return NULL;
4200 +        if(dir == STREAM_PLAYBACK){
4201 +#if defined(CONFIG_I2S_MMAP)
4202 +                i2s_mmap_alloc(I2S_TOTAL_PAGE_SIZE);
4203 +#endif
4204 +                i2s_txbuf_alloc(ptri2s_config);
4205 +               return ptri2s_config->pMMAPTxBufPtr[0];
4206 +        }else{
4207 +#if defined(CONFIG_I2S_MMAP)
4208 +                i2s_mmap_alloc(I2S_TOTAL_PAGE_SIZE);
4209 +#endif
4210 +               i2s_rxbuf_alloc(ptri2s_config);
4211 +               return ptri2s_config->pMMAPRxBufPtr[0];
4212 +       }
4213 +        return NULL;
4214 +}
4215 +
4216 +void i2s_memPool_free(i2s_config_type* ptri2s_config,int dir)
4217 +{
4218 +        if(!ptri2s_config)
4219 +                return;
4220 +        if(dir == STREAM_PLAYBACK){
4221 +#if defined(CONFIG_I2S_MMAP)
4222 +               i2s_mem_unmap(ptri2s_config);
4223 +#endif
4224 +               i2s_txbuf_free(ptri2s_config);
4225 +        }else{
4226 +#if defined(CONFIG_I2S_MMAP)
4227 +               i2s_mem_unmap(ptri2s_config);
4228 +#endif
4229 +               i2s_rxbuf_free(ptri2s_config);
4230 +        }
4231 +
4232 +        return;
4233 +}
4234 +
4235 +int i2s_page_prepare(i2s_config_type* ptri2s_config,int dir)
4236 +{
4237 +        if(dir == STREAM_PLAYBACK){
4238 +                /* allocate tx buffer */
4239 +                i2s_txPagebuf_alloc(ptri2s_config);
4240 +               i2s_dma_tx_init(ptri2s_config);
4241 +       }else{
4242 +                /* allocate rx buffer */
4243 +               i2s_rxPagebuf_alloc(ptri2s_config);
4244 +               i2s_dma_rx_init(ptri2s_config);
4245 +        }
4246 +        return 0;
4247 +}
4248 +
4249 +int i2s_page_release(i2s_config_type* ptri2s_config,int dir)
4250 +{
4251 +        if(!ptri2s_config)
4252 +                return (-1);
4253 +        if(dir == STREAM_PLAYBACK)
4254 +               i2s_txPagebuf_free(ptri2s_config);
4255 +        else
4256 +               i2s_rxPagebuf_free(ptri2s_config);
4257 +
4258 +       return 0;
4259 +}
4260 +
4261 +int i2s_startup(void)
4262 +{
4263 +       memset(pi2s_config, 0, sizeof(i2s_config_type));
4264 +
4265 +#ifdef I2S_STATISTIC
4266 +       memset(pi2s_status, 0, sizeof(i2s_status_type));
4267 +#endif
4268 +
4269 +       i2s_param_init(pi2s_config);
4270 +       pi2s_config->bALSAEnable = 1;
4271 +#if defined(CONFIG_I2S_MMAP)
4272 +       pi2s_config->bALSAMMAPEnable = 1;
4273 +#endif
4274 +
4275 +#if defined (CONFIG_RALINK_MT7628) || defined(CONFIG_ARCH_MT7623)
4276 +       pi2s_config->little_edn = 1;
4277 +#endif
4278 +
4279 +       init_waitqueue_head(&(pi2s_config->i2s_tx_qh));
4280 +       init_waitqueue_head(&(pi2s_config->i2s_rx_qh));
4281 +       spin_lock_init(&pi2s_config->lock);
4282 +
4283 +       return 0;
4284 +}
4285 +
4286 +int gdma_En_Switch(i2s_config_type* ptri2s_config,int dir,int enabled){
4287 +        if(!ptri2s_config)
4288 +                return (-1);
4289 +        if(dir == STREAM_PLAYBACK){
4290 +                ptri2s_config->bTxDMAEnable = enabled;
4291 +                //MSG("%s:%d\n",__func__,ptri2s_config->bTxDMAEnable);
4292 +        }else{
4293 +                ptri2s_config->bRxDMAEnable = enabled;
4294 +        }
4295 +        return 0;
4296 +}
4297 +
4298 +int i2s_audio_exchange(i2s_config_type* ptri2s_config,int dir,unsigned long arg)
4299 +{
4300 +        //MSG("I2S_PUT_AUDIO\n");
4301 +        if(!ptri2s_config)
4302 +                return (-1);
4303 +        if(dir == STREAM_PLAYBACK){
4304 +               i2s_put_audio(ptri2s_config, arg);
4305 +       }else{
4306 +               i2s_get_audio(ptri2s_config, arg);
4307 +        }
4308 +        return 0;
4309 +}
4310 +
4311 +void gdma_mask_handler(u32 dma_ch)
4312 +{
4313 +       i2s_dma_mask_handler(dma_ch);
4314 +        return;
4315 +}
4316 +
4317 +void gdma_unmask_handler(u32 dma_ch)
4318 +{
4319 +        i2s_dma_unmask_handler(dma_ch);
4320 +       return;
4321 +}
4322 +
4323 +u32 i2s_mmap_phys_addr(i2s_config_type* ptri2s_config)
4324 +{
4325 +       if((ptri2s_config->pMMAPBufPtr[0]!=NULL) && (ptri2s_config->mmap_index == MAX_I2S_PAGE))
4326 +               return (dma_addr_t)i2s_mmap_addr[0];
4327 +       else if((ptri2s_config->pMMAPBufPtr[MAX_I2S_PAGE]!=NULL) && (ptri2s_config->mmap_index == MAX_I2S_PAGE*2))
4328 +               return (dma_addr_t)i2s_mmap_addr[MAX_I2S_PAGE];
4329 +       else
4330 +               return -1;
4331 +}
4332 +
4333 +EXPORT_SYMBOL(i2s_startup);
4334 +EXPORT_SYMBOL(i2s_mem_unmap);
4335 +EXPORT_SYMBOL(i2s_mmap_alloc);
4336 +EXPORT_SYMBOL(i2s_mmap_remap);
4337 +EXPORT_SYMBOL(i2s_param_init);
4338 +EXPORT_SYMBOL(i2s_txbuf_alloc);
4339 +EXPORT_SYMBOL(i2s_rxbuf_alloc);
4340 +EXPORT_SYMBOL(i2s_txPagebuf_alloc);
4341 +EXPORT_SYMBOL(i2s_rxPagebuf_alloc);
4342 +EXPORT_SYMBOL(i2s_txbuf_free);
4343 +EXPORT_SYMBOL(i2s_rxbuf_free);
4344 +EXPORT_SYMBOL(i2s_txPagebuf_free);
4345 +EXPORT_SYMBOL(i2s_rxPagebuf_free);
4346 +EXPORT_SYMBOL(i2s_rx_disable);
4347 +EXPORT_SYMBOL(i2s_tx_disable);
4348 +EXPORT_SYMBOL(i2s_rx_enable);
4349 +EXPORT_SYMBOL(i2s_tx_enable);
4350 +EXPORT_SYMBOL(i2s_rx_config);
4351 +EXPORT_SYMBOL(i2s_tx_config);
4352 +EXPORT_SYMBOL(i2s_reset_config);
4353 +EXPORT_SYMBOL(i2s_clock_disable);
4354 +EXPORT_SYMBOL(i2s_clock_enable);
4355 +EXPORT_SYMBOL(i2s_reset_rx_param);
4356 +EXPORT_SYMBOL(i2s_reset_tx_param);
4357 +EXPORT_SYMBOL(i2s_dma_rx_handler);
4358 +EXPORT_SYMBOL(i2s_dma_tx_handler);
4359 +EXPORT_SYMBOL(i2s_dma_unmask_handler);
4360 +EXPORT_SYMBOL(i2s_dma_tx_unmask_handler);
4361 +EXPORT_SYMBOL(i2s_dma_rx_unmask_handler);
4362 +EXPORT_SYMBOL(i2s_dma_mask_handler);
4363 +EXPORT_SYMBOL(i2s_dma_tx_init);
4364 +EXPORT_SYMBOL(i2s_dma_rx_init);
4365 +EXPORT_SYMBOL(i2s_tx_end_sleep_on);
4366 +EXPORT_SYMBOL(i2s_rx_end_sleep_on);
4367 +EXPORT_SYMBOL(i2s_mmap_phys_addr);
4368 +EXPORT_SYMBOL(i2s_open);
4369 +EXPORT_SYMBOL(pi2s_config);
4370 +#if defined(CONFIG_I2S_IN_MCLK)
4371 +#if defined(CONFIG_I2S_MCLK_12MHZ)
4372 +EXPORT_SYMBOL(i2s_refclk_12m_enable);
4373 +#endif
4374 +#if defined(CONFIG_I2S_MCLK_12P288MHZ)
4375 +EXPORT_SYMBOL(i2s_refclk_12p288m_enable);
4376 +#endif
4377 +#endif
4378 +#if defined(MT7628_ASIC_BOARD) || defined(CONFIG_ARCH_MT7623)
4379 +EXPORT_SYMBOL(i2s_driving_strength_adjust);
4380 +#endif
4381 +EXPORT_SYMBOL(i2s_refclk_disable);
4382 +EXPORT_SYMBOL(i2s_refclk_gpio_out_config);
4383 +EXPORT_SYMBOL(i2s_refclk_gpio_in_config);
4384 +EXPORT_SYMBOL(i2s_share_pin_config);
4385 +EXPORT_SYMBOL(i2s_share_pin_mt7623);
4386 +EXPORT_SYMBOL(i2s_ws_config);
4387 +EXPORT_SYMBOL(i2s_mode_config);
4388 +EXPORT_SYMBOL(i2s_codec_frequency_config);
4389 +EXPORT_SYMBOL(i2s_dma_tx_transf_data);
4390 +EXPORT_SYMBOL(i2s_dma_tx_transf_zero);
4391 +EXPORT_SYMBOL(i2s_dma_rx_transf_data);
4392 +EXPORT_SYMBOL(i2s_dma_rx_transf_zero);
4393 +EXPORT_SYMBOL(i2s_dma_tx_end_handle);
4394 +EXPORT_SYMBOL(i2s_dma_tx_soft_stop);
4395 +EXPORT_SYMBOL(i2s_dma_rx_soft_stop);
4396 +EXPORT_SYMBOL(i2s_tx_task);
4397 +EXPORT_SYMBOL(i2s_rx_task);
4398 +
4399 +EXPORT_SYMBOL(i2s_memPool_Alloc);
4400 +EXPORT_SYMBOL(i2s_memPool_free);
4401 +EXPORT_SYMBOL(i2s_page_prepare);
4402 +EXPORT_SYMBOL(i2s_page_release);
4403 +EXPORT_SYMBOL(gdma_En_Switch);
4404 +EXPORT_SYMBOL(i2s_audio_exchange);
4405 +EXPORT_SYMBOL(gdma_mask_handler);
4406 +EXPORT_SYMBOL(gdma_unmask_handler);
4407 +#if defined(CONFIG_I2S_WITH_AEC)
4408 +EXPORT_SYMBOL(aecFuncP);
4409 +#endif
4410 +module_init(i2s_mod_init);
4411 +module_exit(i2s_mod_exit);
4412 +
4413 +MODULE_DESCRIPTION("Ralink SoC I2S Controller Module");
4414 +MODULE_AUTHOR("Qwert Chin <qwert.chin@ralinktech.com.tw>");
4415 +MODULE_SUPPORTED_DEVICE("I2S");
4416 +MODULE_VERSION(I2S_MOD_VERSION);
4417 +MODULE_LICENSE("GPL");
4418 +#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,12)
4419 +MODULE_PARM (i2sdrv_major, "i");
4420 +#else
4421 +module_param (i2sdrv_major, int, 0);
4422 +#endif
4423 --- /dev/null
4424 +++ b/sound/soc/mtk/i2s_ctrl.h
4425 @@ -0,0 +1,523 @@
4426 +#ifndef __RALINK_I2S_H_
4427 +#define __RALINK_I2S_H_
4428 +
4429 +#ifdef __KERNEL__
4430 +//#include <asm/rt2880/rt_mmap.h>
4431 +#endif
4432 +
4433 +#if defined(CONFIG_I2S_WITH_AEC)
4434 +#include "aec/aec_api.h"
4435 +#endif
4436 +
4437 +#define I2S_MAX_DEV                    1
4438 +#define I2S_MOD_VERSION                        "0.1"
4439 +#define phys_to_bus(a) (a & 0x1FFFFFFF)
4440 +
4441 +#ifndef u32
4442 +#define u32 unsigned int
4443 +#endif
4444 +
4445 +#ifndef u16
4446 +#define u16 unsigned short
4447 +#endif
4448 +
4449 +#ifndef u8
4450 +#define u8 unsigned char
4451 +#endif
4452 +
4453 +#ifndef REGBIT
4454 +#define REGBIT(x, n)           (x << n)
4455 +#endif
4456 +
4457 +#define Virtual2Physical(x)             (((int)x) & 0x1fffffff)
4458 +#define Physical2Virtual(x)             (((int)x) | 0x80000000)
4459 +#define Virtual2NonCache(x)             (((int)x) | 0x20000000)
4460 +#define Physical2NonCache(x)            (((int)x) | 0xa0000000)
4461 +#define NonCache2Virtual(x)             (((int)x) & 0xDFFFFFFF)
4462 +
4463 +#if defined(CONFIG_I2S_MCLK_12MHZ)
4464 +#define CONFIG_I2S_CODEC_PLL_EN                1
4465 +#else
4466 +#define CONFIG_I2S_CODEC_PLL_EN                0
4467 +#endif
4468 +
4469 +//#define CONFIG_I2S_MS_CTRL
4470 +//#define CONFIG_I2S_MS_MODE
4471 +//#define memory_test
4472 +
4473 +#if defined (CONFIG_ARCH_MT7623)
4474 +#define MT7623_ASIC_BOARD
4475 +#define ARM_ARCH
4476 +#endif
4477 +
4478 +#if defined (CONFIG_RALINK_MT7621)
4479 +#define MT7621_ASIC_BOARD
4480 +#endif
4481 +
4482 +#if defined (CONFIG_RALINK_MT7628)
4483 +#define MT7628_ASIC_BOARD
4484 +#endif
4485 +
4486 +//#define I2S_DEBUG_PRN
4487 +#ifdef I2S_DEBUG_PRN
4488 +#define MSG(fmt, args...) printk("I2S: " fmt, ## args)
4489 +#else
4490 +#define MSG(fmt, args...) { }
4491 +#endif
4492 +
4493 +#ifdef I2S_DEBUG_PRN
4494 +#define i2s_outw(address, value)       do{printk("0x%08X = 0x%08X\n",(u32)address,(u32)value);*((volatile uint32_t *)(address)) = cpu_to_le32(value);}while(0)
4495 +#else
4496 +#define i2s_outw(address, value)       *((volatile uint32_t *)(address)) = cpu_to_le32(value)
4497 +#endif
4498 +#define i2s_inw(address)               le32_to_cpu(*(volatile u32 *)(address))
4499 +
4500 +/* HW feature definiations */
4501 +#if defined(CONFIG_RALINK_RT3883)
4502 +#define CONFIG_I2S_TXRX                        1
4503 +#define CONFIG_I2S_IN_MCLK             1
4504 +//#define CONFIG_I2S_WS_EDGE           1
4505 +#define CONFIG_I2S_FRAC_DIV            1
4506 +#define CONFIG_I2S_IN_CLK              1
4507 +#define CONFIG_I2S_MS_MODE             1
4508 +#endif
4509 +
4510 +#if defined(CONFIG_RALINK_RT3352)||defined(CONFIG_RALINK_RT5350) || defined (CONFIG_RALINK_RT6855) \
4511 +       || defined(CONFIG_RALINK_RT6855A) || defined(CONFIG_RALINK_MT7620) || defined(CONFIG_RALINK_MT7621) \
4512 +       || defined (CONFIG_RALINK_MT7628) || defined(CONFIG_ARCH_MT7623)
4513 +#define CONFIG_I2S_TXRX                        1
4514 +//#define CONFIG_I2S_WS_EDGE           1
4515 +#define CONFIG_I2S_FRAC_DIV            1
4516 +#define CONFIG_I2S_IN_CLK              1
4517 +#endif
4518 +
4519 +#if defined(CONFIG_RALINK_RT3350)
4520 +#define CONFIG_I2S_IN_MCLK             1
4521 +#endif
4522 +
4523 +#if defined(CONFIG_RALINK_RT3052)
4524 +#define CONFIG_I2S_MS_MODE             1
4525 +#endif
4526 +
4527 +/* This is decided in menuconfig */
4528 +#define CONFIG_I2S_MMAP                1
4529 +
4530 +/* For MT7623 ASIC PLL Setting */
4531 +#if defined(CONFIG_ARCH_MT7623)
4532 +#define AUD1PLL_CON0           (0xF0209270)
4533 +#define AUD1PLL_CON1           (0xF0209274)
4534 +#define AUD1PLL_CON2           (0xF0209278)
4535 +#define AUD1PLL_PWR_CON0       (0xF020927C)
4536 +#define AUD2PLL_CON0           (0xF02092C0)
4537 +#define AUD2PLL_CON1           (0xF02092C4)
4538 +#define AUD2PLL_CON2           (0xF02092C8)
4539 +#define AUD2PLL_PWR_CON0       (0xF02092CC)
4540 +#endif
4541 +
4542 +/* Register Map, Ref to RT3052 Data Sheet */
4543 +
4544 +/* Register Map Detail */
4545 +#if defined(CONFIG_ARCH_MT7623)
4546 +#define I2S_I2SCFG                     (ETHDMASYS_I2S_BASE+0x0000)
4547 +#define I2S_INT_STATUS                 (ETHDMASYS_I2S_BASE+0x0004)
4548 +#define I2S_INT_EN                     (ETHDMASYS_I2S_BASE+0x0008)
4549 +#define I2S_FF_STATUS                  (ETHDMASYS_I2S_BASE+0x000c)
4550 +#define I2S_FIFO_WREG                  (ETHDMASYS_I2S_BASE+0x0010)
4551 +#define I2S_TX_FIFO_WREG               I2S_FIFO_WREG
4552 +#define I2S_RX_FIFO_RREG               (ETHDMASYS_I2S_BASE+0x0014)
4553 +#define I2S_I2SCFG1                    (ETHDMASYS_I2S_BASE+0x0018)
4554 +#define I2S_DIVINT_CFG                 (ETHDMASYS_I2S_BASE+0x0024)
4555 +#define I2S_DIVCOMP_CFG                        (ETHDMASYS_I2S_BASE+0x0020)
4556 +#else
4557 +#define I2S_I2SCFG                     (RALINK_I2S_BASE+0x0000)
4558 +#define I2S_INT_STATUS                 (RALINK_I2S_BASE+0x0004)
4559 +#define I2S_INT_EN                     (RALINK_I2S_BASE+0x0008)
4560 +#define I2S_FF_STATUS                  (RALINK_I2S_BASE+0x000c)
4561 +#define I2S_FIFO_WREG                  (RALINK_I2S_BASE+0x0010)
4562 +#define I2S_TX_FIFO_WREG               I2S_FIFO_WREG
4563 +#define I2S_RX_FIFO_RREG               (RALINK_I2S_BASE+0x0014)
4564 +#define I2S_I2SCFG1                    (RALINK_I2S_BASE+0x0018)
4565 +#define I2S_DIVINT_CFG                 (RALINK_I2S_BASE+0x0024)
4566 +#define I2S_DIVCOMP_CFG                        (RALINK_I2S_BASE+0x0020)
4567 +#endif
4568 +
4569 +
4570 +/* I2SCFG bit field */
4571 +#define I2S_EN                 31
4572 +#define I2S_DMA_EN             30
4573 +#if defined(CONFIG_RALINK_MT7628) || defined(CONFIG_ARCH_MT7623)
4574 +#define I2S_LITTLE_ENDIAN      29
4575 +#define I2S_SYS_ENDIAN         28
4576 +#elif defined(CONFIG_RALINK_RT6855A)
4577 +#define I2S_BYTE_SWAP          28
4578 +#endif
4579 +#define I2S_TX_EN              24
4580 +#define I2S_RX_EN              20
4581 +#if defined(CONFIG_RALINK_MT7628) || defined(CONFIG_ARCH_MT7623)
4582 +#define I2S_NORM_24BIT         18
4583 +#define I2S_DATA_24BIT         17
4584 +#endif
4585 +#define I2S_SLAVE_MODE         16
4586 +#define I2S_RX_FF_THRES                12
4587 +#define I2S_RX_CH_SWAP         11
4588 +#define I2S_RX_CH1_OFF         10
4589 +#define I2S_RX_CH0_OFF         9
4590 +#if defined(CONFIG_RALINK_RT3052)
4591 +#define I2S_CLK_OUT_DIS                8
4592 +#endif
4593 +#define I2S_TX_FF_THRES                4
4594 +#define I2S_TX_CH_SWAP         3
4595 +#define I2S_TX_CH1_OFF         2
4596 +#define I2S_TX_CH0_OFF         1
4597 +#if defined(CONFIG_RALINK_RT3052)
4598 +#define I2S_SLAVE_EN            0
4599 +#else
4600 +#define I2S_WS_INV             0
4601 +#endif
4602 +/* INT_EN bit field */
4603 +#define I2S_RX_INT3_EN         7
4604 +#define I2S_RX_INT2_EN         6
4605 +#define I2S_RX_INT1_EN         5
4606 +#define I2S_RX_INT0_EN         4
4607 +#define I2S_TX_INT3_EN         3
4608 +#define I2S_TX_INT2_EN         2
4609 +#define I2S_TX_INT1_EN         1
4610 +#define I2S_TX_INT0_EN         0
4611 +
4612 +/* INT_STATUS bit field */
4613 +#define I2S_RX_DMA_FAULT       7
4614 +#define I2S_RX_OVRUN           6
4615 +#define I2S_RX_UNRUN           5
4616 +#define I2S_RX_THRES           4
4617 +#define I2S_TX_DMA_FAULT       3
4618 +#define I2S_TX_OVRUN           2
4619 +#define I2S_TX_UNRUN           1
4620 +#define I2S_TX_THRES           0
4621 +
4622 +/* FF_STATUS bit field */
4623 +#define I2S_RX_EPCNT           4
4624 +#define I2S_TX_EPCNT           0
4625 +/* I2S_DIVCOMP_CFG bit field */
4626 +#define I2S_CLKDIV_EN          31
4627 +
4628 +/* I2S_CFG1 bit field */
4629 +#define I2S_LBK_EN             31
4630 +#define I2S_EXT_LBK_EN         30
4631 +#if defined(CONFIG_RALINK_MT7628) || defined(CONFIG_ARCH_MT7623)
4632 +#define I2S_DATA_FMT           0
4633 +#endif
4634 +
4635 +/* FIFO_WREG bit field */
4636 +#define I2S_FIFO_WDATA         0
4637 +
4638 +/* Constant definition */
4639 +#define NFF_THRES              4
4640 +#define I2S_PAGE_SIZE          3072//(3*4096)//(1152*2*2*2)
4641 +#define I2S_MIN_PAGE_SIZE      4096
4642 +#define MAX_I2S_PAGE           8
4643 +#define I2S_TOTAL_PAGE_SIZE    (I2S_PAGE_SIZE*MAX_I2S_PAGE)
4644 +
4645 +#if defined(CONFIG_I2S_WM8960)
4646 +#define MAX_SRATE_HZ            48000
4647 +#define MIN_SRATE_HZ            8000
4648 +#elif defined(CONFIG_I2S_WM8750)
4649 +#define MAX_SRATE_HZ           96000
4650 +#define MIN_SRATE_HZ           8000
4651 +#endif
4652 +
4653 +#define MAX_VOL_DB             +0
4654 +#define MIN_VOL_DB             -127
4655 +
4656 +#define ALSA_MMAP_IDX_SHIFT    2
4657 +#if defined(CONFIG_SND_MT76XX_SOC)
4658 +#define STREAM_PLAYBACK                SNDRV_PCM_STREAM_PLAYBACK
4659 +#define STREAM_CAPTURE         SNDRV_PCM_STREAM_CAPTURE
4660 +#else
4661 +#define STREAM_PLAYBACK                0
4662 +#define STREAM_CAPTURE         1
4663 +#endif
4664 +
4665 +/* I2S I/O command */
4666 +#define I2S_SRATE              0
4667 +#define I2S_VOL                        1
4668 +#define I2S_ENABLE             2
4669 +#define I2S_DISABLE            3
4670 +#define I2S_TX_ENABLE          27
4671 +#define I2S_TX_DISABLE         3
4672 +#define I2S_GET_WBUF           4
4673 +#define I2S_PUT_WBUF           5
4674 +#define I2S_RX_ENABLE          6
4675 +#define I2S_RX_DISABLE         7
4676 +#define I2S_PUT_AUDIO          4
4677 +#define I2S_GET_AUDIO          5
4678 +#define I2S_TX_VOL             1
4679 +#define I2S_RX_VOL             8
4680 +#define I2S_WORD_LEN           9
4681 +#define I2S_ENDIAN_FMT         10
4682 +#define I2S_INTERNAL_LBK       11
4683 +#define I2S_TX_STOP             12
4684 +#define I2S_DEBUG_CODEC                13
4685 +#define I2S_MS_MODE_CTRL       14
4686 +#define I2S_TX_PAUSE           15
4687 +#define I2S_TX_RESUME          16
4688 +#define I2S_RESET              17
4689 +#define I2S_RX_STOP            18
4690 +#define I2S_EXTERNAL_LBK       19
4691 +#define I2S_TXRX_COEXIST       20
4692 +#define I2S_RX_PAUSE           21
4693 +#define I2S_RX_RESUME          22
4694 +#define I2S_CODEC_MIC_BOOST    23
4695 +#define I2S_CODEC_MIC_IN       24
4696 +#define I2S_CLOCK_ENABLE       25
4697 +#define I2S_TEST_TEST          26
4698 +
4699 +#define I2S_DEBUG              30
4700 +#define I2S_DEBUG_CLKGEN       30
4701 +#define I2S_DEBUG_INLBK                31
4702 +#define I2S_DEBUG_EXLBK                32
4703 +#define I2S_DEBUG_FMT          33
4704 +#define I2S_DEBUG_RESET                34
4705 +#define I2S_DEBUG_CODECBYPASS  35
4706 +#if defined(CONFIG_I2S_WM8960)
4707 +#define I2S_DEBUG_CODEC_EXLBK  36
4708 +#endif
4709 +
4710 +/* configuration */
4711 +#define CONFIG_I2S_TFF_THRES   NFF_THRES
4712 +#define CONFIG_I2S_CH_SWAP     0
4713 +#if defined(CONFIG_I2S_MS_MODE)
4714 +#define CONFIG_I2S_SLAVE_EN    0
4715 +#else
4716 +#define CONFIG_I2S_SLAVE_EN    1
4717 +#endif
4718 +
4719 +/* driver status definition */
4720 +#define I2S_OK                 0
4721 +#define I2S_OUTOFMEM           0x01
4722 +#define I2S_GDMAFAILED         0x02
4723 +#define I2S_REQUEST_IRQ_FAILED 0x04
4724 +#define I2S_REG_SETUP_FAILED   0x08
4725 +
4726 +#define I2S_STATISTIC
4727 +//#define I2S_HW_INTERRUPT_EN
4728 +//#define I2S_SW_IRQ_EN
4729 +#define I2S_MAJOR              234
4730 +
4731 +/* parameter for ALSA */
4732 +/*GDMA for I2S Status*/
4733 +#define GDMA_I2S_DIS (0)
4734 +#define GDMA_I2S_EN (1)
4735 +
4736 +
4737 +typedef struct i2s_status_t
4738 +{
4739 +       u32 txdmafault;
4740 +       u32 txovrun;
4741 +       u32 txunrun;
4742 +       u32 txthres;
4743 +       int txbuffer_unrun;
4744 +       int txbuffer_ovrun;
4745 +       int txbuffer_len;
4746 +
4747 +       u32 rxdmafault;
4748 +       u32 rxovrun;
4749 +       u32 rxunrun;
4750 +       u32 rxthres;
4751 +       int rxbuffer_unrun;
4752 +       int rxbuffer_ovrun;
4753 +       int rxbuffer_len;
4754 +}i2s_status_type;
4755 +
4756 +
4757 +typedef struct i2s_config_t
4758 +{
4759 +
4760 +       int srate;
4761 +       int txvol;
4762 +       int rxvol;
4763 +       u32 pos;
4764 +       u32 tx_isr_cnt;
4765 +       u32 rx_isr_cnt;
4766 +       int bSleep;
4767 +       int bTxDMAEnable;
4768 +       int bRxDMAEnable;
4769 +       int enLable;
4770 +       int micboost;
4771 +       int micin;
4772 +
4773 +       /* parameters fo ALSA */
4774 +       int bALSAEnable;
4775 +       int bALSAMMAPEnable;
4776 +       unsigned char bTrigger[2];
4777 +       unsigned char bPreTrigger[2];
4778 +       unsigned char dmaStat[2];
4779 +       unsigned char i2sStat[2];
4780 +       unsigned int hw_base_frame[2];
4781 +       struct snd_pcm_substream *pss[2];
4782 +
4783 +#ifdef __KERNEL__
4784 +       spinlock_t lock;
4785 +       wait_queue_head_t i2s_tx_qh, i2s_rx_qh;
4786 +#endif
4787 +       u32 dmach;
4788 +       u32 tx_unmask_ch;
4789 +       u32 rx_unmask_ch;
4790 +       u32 dma_unmask_status;
4791 +       u32 dma_done_status;
4792 +       u32 tx_ff_thres;
4793 +       u32 tx_ch_swap;
4794 +       u32 rx_ff_thres;
4795 +       u32 rx_ch_swap;
4796 +       u32 slave_en;
4797 +
4798 +       u32 dis_match;
4799 +       int start_cnt;
4800 +#if defined (CONFIG_RALINK_MT7628) || defined(CONFIG_ARCH_MT7623)
4801 +       int little_edn;  /* test file's fmt: little endian->1; big endian->0 */
4802 +        int sys_endian;  /* kernal' system fmt: little endian->0; big endian->1 */
4803 +#endif
4804 +       int wordlen_24b;
4805 +       int codec_pll_en;
4806 +       int codec_num;
4807 +       int tx_pause_en;
4808 +       int rx_pause_en;
4809 +       int end_cnt;
4810 +       int txrx_coexist;
4811 +       int tx_stop_cnt;
4812 +       int rx_stop_cnt;
4813 +       /* for I2S_CFG1 */
4814 +       u32 lbk;
4815 +       u32 extlbk;
4816 +       u32 fmt;
4817 +
4818 +       int w_idx;
4819 +       int r_idx;
4820 +
4821 +       int tx_w_idx;
4822 +       int tx_r_idx;
4823 +       int rx_w_idx;
4824 +       int rx_r_idx;
4825 +       int mmap_index;
4826 +       int next_p0_idx;
4827 +       int next_p1_idx;
4828 +
4829 +       u8* buf8ptr;
4830 +       char* pMMAPBufPtr[MAX_I2S_PAGE*2];
4831 +       char* pMMAPTxBufPtr[MAX_I2S_PAGE];
4832 +       char* pMMAPRxBufPtr[MAX_I2S_PAGE];
4833 +
4834 +       union {
4835 +               u16* pPage0TxBuf16Ptr;
4836 +               u8* pPage0TxBuf8ptr;
4837 +       };
4838 +       union {
4839 +               u16* pPage1TxBuf16Ptr;
4840 +               u8* pPage1TxBuf8ptr;
4841 +       };
4842 +
4843 +       union {
4844 +               u16* pPage0RxBuf16Ptr;
4845 +               u8* pPage0RxBuf8ptr;
4846 +       };
4847 +       union {
4848 +               u16* pPage1RxBuf16Ptr;
4849 +               u8* pPage1RxBuf8ptr;
4850 +       };
4851 +
4852 +}i2s_config_type;
4853 +
4854 +
4855 +void i2s_gen_test_pattern(void);
4856 +int i2s_mem_unmap(i2s_config_type* ptri2s_config);
4857 +int i2s_param_init(i2s_config_type* ptri2s_config);
4858 +int i2s_txbuf_alloc(i2s_config_type* ptri2s_config);
4859 +int i2s_rxbuf_alloc(i2s_config_type* ptri2s_config);
4860 +int i2s_txPagebuf_alloc(i2s_config_type* ptri2s_config);
4861 +int i2s_rxPagebuf_alloc(i2s_config_type* ptri2s_config);
4862 +int i2s_txbuf_free(i2s_config_type* ptri2s_config);
4863 +int i2s_rxbuf_free(i2s_config_type* ptri2s_config);
4864 +int i2s_txPagebuf_free(i2s_config_type* ptri2s_config);
4865 +int i2s_rxPagebuf_free(i2s_config_type* ptri2s_config);
4866 +int i2s_reset_tx_param(i2s_config_type* ptri2s_config);
4867 +int i2s_reset_rx_param(i2s_config_type* ptri2s_config);
4868 +int i2s_tx_config(i2s_config_type* ptri2s_config);
4869 +int i2s_rx_config(i2s_config_type* ptri2s_config);
4870 +int i2s_tx_enable(i2s_config_type* ptri2s_config);
4871 +int i2s_tx_disable(i2s_config_type* ptri2s_config);
4872 +int i2s_rx_enable(i2s_config_type* ptri2s_config);
4873 +int i2s_rx_disable(i2s_config_type* ptri2s_config);
4874 +int i2s_codec_enable(i2s_config_type* ptri2s_config);
4875 +int i2s_codec_disable(i2s_config_type* ptri2s_config);
4876 +int i2s_clock_enable(i2s_config_type* ptri2s_config);
4877 +int i2s_clock_disable(i2s_config_type* ptri2s_config);
4878 +int i2s_reset_config(i2s_config_type* ptri2s_config);
4879 +int i2s_refclk_disable(void);
4880 +int i2s_refclk_gpio_out_config(void);
4881 +int i2s_refclk_gpio_in_config(void);
4882 +int i2s_share_pin_config(i2s_config_type* ptri2s_config);
4883 +int i2s_share_pin_mt7623(i2s_config_type* ptri2s_config);
4884 +int i2s_master_clock_gpio_out_mt7623(void);
4885 +int i2s_slave_clock_gpio_in_mt7623(void);
4886 +int i2s_ws_config(i2s_config_type* ptri2s_config, unsigned long index);
4887 +int i2s_mode_config(u32 slave_en);
4888 +int i2s_codec_frequency_config(i2s_config_type* ptri2s_config, unsigned long index);
4889 +void i2s_tx_end_sleep_on(i2s_config_type* ptri2s_config);
4890 +void i2s_rx_end_sleep_on(i2s_config_type* ptri2s_config);
4891 +
4892 +#if defined(CONFIG_I2S_MCLK_12MHZ)
4893 +int i2s_refclk_12m_enable(void);
4894 +#endif
4895 +#if defined(CONFIG_I2S_MCLK_12P288MHZ)
4896 +int i2s_refclk_12p288m_enable(void);
4897 +#endif
4898 +
4899 +#if defined(MT7621_ASIC_BOARD)
4900 +int i2s_pll_config_mt7621(unsigned long index);
4901 +int i2s_pll_refclk_set(void);
4902 +#endif
4903 +#if defined(MT7623_ASIC_BOARD)
4904 +int i2s_pll_config_mt7623(unsigned long index);
4905 +#endif
4906 +#if defined(MT7628_ASIC_BOARD) || defined(CONFIG_ARCH_MT7623)
4907 +int i2s_driving_strength_adjust(void);
4908 +#endif
4909 +#if defined(I2S_STATISTIC)
4910 +void i2s_int_status(u32 dma_ch);
4911 +#endif
4912 +void i2s_dma_tx_handler(u32 dma_ch);
4913 +void i2s_dma_rx_handler(u32 dma_ch);
4914 +void i2s_dma_unmask_handler(u32 dma_ch);
4915 +void i2s_dma_mask_handler(u32 dma_ch);
4916 +void i2s_dma_tx_init(i2s_config_type* ptri2s_config);
4917 +void i2s_dma_rx_init(i2s_config_type* ptri2s_config);
4918 +void i2s_tx_task(unsigned long pData);
4919 +void i2s_rx_task(unsigned long pData);
4920 +void i2s_dma_tx_unmask_handler(u32 dma_ch);
4921 +void i2s_dma_rx_unmask_handler(u32 dma_ch);
4922 +int i2s_dma_tx_transf_data(i2s_config_type* ptri2s_config, u32 dma_ch);
4923 +int i2s_dma_tx_transf_zero(i2s_config_type* ptri2s_config, u32 dma_ch);
4924 +int i2s_dma_rx_transf_data(i2s_config_type* ptri2s_config, u32 dma_ch);
4925 +int i2s_dma_rx_transf_zero(i2s_config_type* ptri2s_config, u32 dma_ch);
4926 +void i2s_dma_tx_end_handle(i2s_config_type* ptri2s_config);
4927 +int i2s_dma_tx_soft_stop(i2s_config_type* ptri2s_config, u32 dma_ch);
4928 +int i2s_dma_rx_soft_stop(i2s_config_type* ptri2s_config, u32 dma_ch);
4929 +
4930 +int i2s_page_prepare(i2s_config_type* ptri2s_config,int dir);
4931 +int i2s_page_release(i2s_config_type* ptri2s_config,int dir);
4932 +int gdma_En_Switch(i2s_config_type* ptri2s_config,int dir,int enabled);
4933 +int i2s_startup(void);
4934 +int i2s_audio_exchange(i2s_config_type* ptri2s_config,int dir,unsigned long arg);
4935 +void gdma_unmask_handler(u32 dma_ch);
4936 +char* i2s_memPool_Alloc(i2s_config_type* ptri2s_config,int dir);
4937 +void i2s_memPool_free(i2s_config_type* ptri2s_config,int dir);
4938 +u32 i2s_mmap_phys_addr(i2s_config_type* ptri2s_config);
4939 +
4940 +#if !defined(CONFIG_I2S_TXRX)
4941 +#define GdmaI2sRx      //GdmaI2sRx
4942 +#endif
4943 +
4944 +#define RALINK_I2S_VERSION     "1.0"
4945 +#define I2SDRV_DEVNAME         "i2s0"
4946 +
4947 +#endif /* __RALINK_I2S_H_ */
4948 +
4949 --- /dev/null
4950 +++ b/sound/soc/mtk/mt76xx_i2s.c
4951 @@ -0,0 +1,304 @@
4952 +/*
4953 + * mtk_audio_drv.c
4954 + *
4955 + *  Created on: 2013/8/20
4956 + *      Author: MTK04880
4957 + */
4958 +#include <linux/init.h>
4959 +#include <linux/version.h>
4960 +#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,35)
4961 +#include <linux/sched.h>
4962 +#endif
4963 +#include <linux/module.h>
4964 +#include <linux/kernel.h> /* printk() */
4965 +#include <linux/slab.h> /* kmalloc() */
4966 +#include <linux/fs.h> /* everything... */
4967 +#include <linux/errno.h> /* error codes */
4968 +#include <linux/types.h> /* size_t */
4969 +#include <linux/proc_fs.h>
4970 +#include <linux/fcntl.h> /* O_ACCMODE */
4971 +#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,36)
4972 +#include <asm/system.h> /* cli(), *_flags */
4973 +#endif
4974 +#include <asm/uaccess.h> /* copy_from/to_user */
4975 +#include <linux/interrupt.h>
4976 +#include <linux/mm.h>
4977 +#include <linux/dma-mapping.h>
4978 +#include <sound/core.h>
4979 +#include <linux/pci.h>
4980 +#include <sound/pcm.h>
4981 +#include <sound/pcm_params.h>
4982 +#include <sound/soc.h>
4983 +#include <sound/soc-dapm.h>
4984 +#include <sound/initval.h>
4985 +#include "ralink_gdma.h"
4986 +#include "mt76xx_i2s.h"
4987 +
4988 +/****************************/
4989 +/*GLOBAL VARIABLE DEFINITION*/
4990 +/****************************/
4991 +extern i2s_config_type* pi2s_config;
4992 +
4993 +/****************************/
4994 +/*FUNCTION DECLRATION          */
4995 +/****************************/
4996 +static int mt76xx_i2s_set_fmt(struct snd_soc_dai *cpu_dai,\
4997 +               unsigned int fmt);
4998 +
4999 +//static int  mt76xx_i2s_shutdown(struct snd_pcm_substream *substream,
5000 +//                    struct snd_soc_dai *dai);
5001 +static int  mt76xx_i2s_startup(struct snd_pcm_substream *substream,
5002 +                      struct snd_soc_dai *dai);
5003 +static int mt76xx_i2s_hw_params(struct snd_pcm_substream *substream,\
5004 +                               struct snd_pcm_hw_params *params,\
5005 +                               struct snd_soc_dai *dai);
5006 +static int mt76xx_i2s_play_prepare(struct snd_pcm_substream *substream,struct snd_soc_dai *dai);
5007 +static int mt76xx_i2s_rec_prepare(struct snd_pcm_substream *substream,struct snd_soc_dai *dai);
5008 +static int mt76xx_i2s_hw_free(struct snd_pcm_substream *substream,struct snd_soc_dai *dai);
5009 +static int mt76xx_i2s_prepare(struct snd_pcm_substream *substream, struct snd_soc_dai *dai);
5010 +
5011 +#if LINUX_VERSION_CODE >= KERNEL_VERSION(3,10,20)
5012 +static int mt76xx_i2s_drv_probe(struct platform_device *pdev);
5013 +static int mt76xx_i2s_drv_remove(struct platform_device *pdev);
5014 +#endif
5015 +/****************************/
5016 +/*STRUCTURE DEFINITION         */
5017 +/****************************/
5018 +
5019 +
5020 +static struct snd_soc_dai_ops mt76xx_i2s_dai_ops = {
5021 +       .startup   = mt76xx_i2s_startup,
5022 +       .hw_params = mt76xx_i2s_hw_params,
5023 +       .hw_free   = mt76xx_i2s_hw_free,
5024 +       //.shutdown = mt76xx_i2s_shutdown,
5025 +       .prepare   = mt76xx_i2s_prepare,
5026 +       .set_fmt   = mt76xx_i2s_set_fmt,
5027 +       //.set_sysclk = mt76xx_i2s_set_sysclk,
5028 +};
5029 +
5030 +const struct snd_soc_component_driver mt76xx_i2s_component = {
5031 +       .name           = "mt76xx-i2s",
5032 +};
5033 +
5034 +struct snd_soc_dai_driver mt76xx_i2s_dai = {
5035 +       .playback = {
5036 +               .channels_min = 1,
5037 +               .channels_max = 2,
5038 +               .rates = (SNDRV_PCM_RATE_8000|SNDRV_PCM_RATE_11025|\
5039 +               SNDRV_PCM_RATE_16000|SNDRV_PCM_RATE_22050|SNDRV_PCM_RATE_32000|\
5040 +               SNDRV_PCM_RATE_44100|SNDRV_PCM_RATE_48000),
5041 +
5042 +               .formats = (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\
5043 +                               SNDRV_PCM_FMTBIT_S24_LE),
5044 +       },
5045 +       .capture = {
5046 +               .channels_min = 1,
5047 +               .channels_max = 2,
5048 +               .rates = (SNDRV_PCM_RATE_8000|SNDRV_PCM_RATE_11025|\
5049 +                               SNDRV_PCM_RATE_16000|SNDRV_PCM_RATE_22050|SNDRV_PCM_RATE_32000|\
5050 +                               SNDRV_PCM_RATE_44100|SNDRV_PCM_RATE_48000),
5051 +               .formats = (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\
5052 +                               SNDRV_PCM_FMTBIT_S24_LE),
5053 +       },
5054 +       .ops = &mt76xx_i2s_dai_ops,
5055 +       .symmetric_rates = 1,
5056 +};
5057 +
5058 +/****************************/
5059 +/*FUNCTION BODY                                */
5060 +/****************************/
5061 +
5062 +static int mt76xx_i2s_set_fmt(struct snd_soc_dai *cpu_dai,
5063 +               unsigned int fmt)
5064 +{//TODO
5065 +
5066 +       //printk("******* %s *******\n", __func__);
5067 +       return 0;
5068 +}
5069 +
5070 +static int mt76xx_i2s_play_prepare(struct snd_pcm_substream *substream, struct snd_soc_dai *dai)
5071 +{
5072 +       //printk("******* %s *******\n", __func__);
5073 +       i2s_config_type* rtd = (i2s_config_type*)substream->runtime->private_data;
5074 +       rtd->pss[SNDRV_PCM_STREAM_PLAYBACK] = substream;
5075 +       if(! rtd->i2sStat[SNDRV_PCM_STREAM_PLAYBACK]){
5076 +               i2s_reset_tx_param( rtd);
5077 +               i2s_tx_config( rtd);
5078 +               gdma_En_Switch(rtd, STREAM_PLAYBACK, GDMA_I2S_EN);
5079 +
5080 +               if( rtd->bRxDMAEnable==0)
5081 +                       i2s_clock_enable( rtd);
5082 +
5083 +               i2s_tx_enable( rtd);
5084 +               rtd->i2sStat[SNDRV_PCM_STREAM_PLAYBACK] = 1;
5085 +               MSG("I2S_TXENABLE done\n");
5086 +       }
5087 +
5088 +       return 0;
5089 +}
5090 +
5091 +static int mt76xx_i2s_rec_prepare(struct snd_pcm_substream *substream, struct snd_soc_dai *dai)
5092 +{
5093 +
5094 +       //printk("******* %s *******\n", __func__);
5095 +       i2s_config_type* rtd = (i2s_config_type*)substream->runtime->private_data;
5096 +       rtd->pss[SNDRV_PCM_STREAM_CAPTURE] = substream;
5097 +       if(! rtd->i2sStat[SNDRV_PCM_STREAM_CAPTURE]) {
5098 +               i2s_reset_rx_param(rtd);
5099 +               i2s_rx_config(rtd);
5100 +               gdma_En_Switch(rtd, STREAM_CAPTURE, GDMA_I2S_EN);
5101 +
5102 +               if(rtd->bTxDMAEnable==0)
5103 +                       i2s_clock_enable(rtd);
5104 +
5105 +               i2s_rx_enable(rtd);
5106 +               rtd->i2sStat[SNDRV_PCM_STREAM_CAPTURE] = 1;
5107 +       }
5108 +       return 0;
5109 +}
5110 +
5111 +/*static int  mt76xx_i2s_shutdown(struct snd_pcm_substream *substream,
5112 +                      struct snd_soc_dai *dai)
5113 +{
5114 +       //i2s_config_type* rtd = (i2s_config_type*)substream->runtime->private_data;
5115 +       //printk("******* %s *******\n", __func__);
5116 +       return 0;
5117 +}
5118 +*/
5119 +static int  mt76xx_i2s_startup(struct snd_pcm_substream *substream,
5120 +                      struct snd_soc_dai *dai)
5121 +{
5122 +
5123 +       //printk("******* %s *******\n", __func__);
5124 +       if((!pi2s_config->i2sStat[SNDRV_PCM_STREAM_PLAYBACK]) && (!pi2s_config->i2sStat[SNDRV_PCM_STREAM_CAPTURE])){
5125 +               i2s_startup();
5126 +               if(!pi2s_config)
5127 +                       return -1;
5128 +               i2s_reset_config(pi2s_config);
5129 +       }
5130 +       substream->runtime->private_data = pi2s_config;
5131 +       return 0;
5132 +}
5133 +
5134 +static int mt76xx_i2s_hw_params(struct snd_pcm_substream *substream,\
5135 +                               struct snd_pcm_hw_params *params,\
5136 +                               struct snd_soc_dai *dai){
5137 +       unsigned int srate = 0;
5138 +       //unsigned long data;
5139 +       struct snd_pcm_runtime *runtime = substream->runtime;
5140 +       i2s_config_type* rtd = runtime->private_data;
5141 +
5142 +       //printk("******* %s *******\n", __func__);
5143 +       switch(params_rate(params)){
5144 +       case 8000:
5145 +               srate = 8000;
5146 +               break;
5147 +       case 16000:
5148 +               srate = 16000;
5149 +               break;
5150 +       case 32000:
5151 +               srate = 32000;
5152 +               break;
5153 +       case 44100:
5154 +               srate = 44100;
5155 +               break;
5156 +       case 48000:
5157 +               srate = 48000;
5158 +               break;
5159 +       default:
5160 +               srate = 44100;
5161 +               //MSG("audio sampling rate %u should be %d ~ %d Hz\n", (u32)params_rate(params), MIN_SRATE_HZ, MAX_SRATE_HZ);
5162 +               break;
5163 +       }
5164 +       if(srate){
5165 +               if((rtd->bRxDMAEnable != GDMA_I2S_EN) && (rtd->bTxDMAEnable != GDMA_I2S_EN)){
5166 +                       rtd->srate = srate;
5167 +                       MSG("set audio sampling rate to %d Hz\n", rtd->srate);
5168 +               }
5169 +       }
5170 +
5171 +       return 0;
5172 +}
5173 +static int mt76xx_i2s_hw_free(struct snd_pcm_substream *substream,struct snd_soc_dai *dai){
5174 +
5175 +       //printk("******* %s *******\n", __func__);
5176 +       i2s_config_type* rtd = (i2s_config_type*)substream->runtime->private_data;
5177 +       if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK){
5178 +               if(rtd->i2sStat[SNDRV_PCM_STREAM_PLAYBACK]){
5179 +                       MSG("I2S_TXDISABLE\n");
5180 +                       i2s_reset_tx_param(rtd);
5181 +
5182 +                       if((rtd->bRxDMAEnable==0)&&(rtd->bTxDMAEnable==0)){
5183 +                               i2s_clock_disable(rtd);
5184 +                       }
5185 +                       rtd->i2sStat[SNDRV_PCM_STREAM_PLAYBACK] = 0;
5186 +               }
5187 +       }
5188 +       else{
5189 +               if(rtd->i2sStat[SNDRV_PCM_STREAM_CAPTURE]){
5190 +                       MSG("I2S_RXDISABLE\n");
5191 +                       i2s_reset_rx_param(rtd);
5192 +
5193 +                       if((rtd->bRxDMAEnable==0)&&(rtd->bTxDMAEnable==0)){
5194 +                               i2s_clock_disable(rtd);
5195 +                       }
5196 +                       rtd->i2sStat[SNDRV_PCM_STREAM_CAPTURE] = 0;
5197 +               }
5198 +       }
5199 +       return 0;
5200 +}
5201 +static int mt76xx_i2s_prepare(struct snd_pcm_substream *substream,struct snd_soc_dai *dai)
5202 +{
5203 +
5204 +       //printk("******* %s *******\n", __func__);
5205 +       if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
5206 +               return mt76xx_i2s_play_prepare(substream, dai);
5207 +       else
5208 +               return mt76xx_i2s_rec_prepare(substream, dai);
5209 +
5210 +       return 0;
5211 +}
5212 +
5213 +#if LINUX_VERSION_CODE >= KERNEL_VERSION(3,10,20)
5214 +static int mt76xx_i2s_drv_probe(struct platform_device *pdev)
5215 +{
5216 +       //printk("****** %s ******\n", __func__);
5217 +       return snd_soc_register_component(&pdev->dev, &mt76xx_i2s_component,
5218 +                                       &mt76xx_i2s_dai, 1);
5219 +}
5220 +
5221 +static int mt76xx_i2s_drv_remove(struct platform_device *pdev)
5222 +{
5223 +       snd_soc_unregister_component(&pdev->dev);
5224 +       return 0;
5225 +}
5226 +
5227 +static struct platform_driver mt76xx_i2s_driver = {
5228 +       .probe  = mt76xx_i2s_drv_probe,
5229 +       .remove = mt76xx_i2s_drv_remove,
5230 +       .driver = {
5231 +               .name  = "mt76xx-i2s",
5232 +               .owner = THIS_MODULE,
5233 +       },
5234 +};
5235 +
5236 +static int __init mt76xx_i2s_init(void)
5237 +{
5238 +
5239 +       //printk("****** %s ******\n", __func__);
5240 +       return platform_driver_register(&mt76xx_i2s_driver);
5241 +}
5242 +
5243 +static void __exit mt76xx_i2s_exit(void)
5244 +{
5245 +       //printk("****** %s ******\n", __func__);
5246 +       platform_driver_unregister(&mt76xx_i2s_driver);
5247 +}
5248 +
5249 +module_init(mt76xx_i2s_init);
5250 +module_exit(mt76xx_i2s_exit);
5251 +
5252 +MODULE_AUTHOR("Dora Chen");
5253 +MODULE_DESCRIPTION("Stretch MT76xx I2S Interface");
5254 +MODULE_LICENSE("GPL");
5255 +#endif
5256 --- /dev/null
5257 +++ b/sound/soc/mtk/mt76xx_i2s.h
5258 @@ -0,0 +1,18 @@
5259 +/*
5260 + * mtk_i2s.h
5261 + *
5262 + *  Created on: 2013/8/20
5263 + *      Author: MTK04880
5264 + */
5265 +
5266 +#ifndef MTK_I2S_H_
5267 +#define MTK_I2S_H_
5268 +
5269 +
5270 +#ifdef __KERNEL__
5271 +//#include <asm/rt2880/rt_mmap.h>
5272 +#include <linux/fs.h>
5273 +#endif
5274 +
5275 +#include "i2s_ctrl.h"
5276 +#endif /* MTK_I2S_H_ */
5277 --- /dev/null
5278 +++ b/sound/soc/mtk/mt76xx_machine.c
5279 @@ -0,0 +1,317 @@
5280 +/*
5281 + * mt76xx_machine.c
5282 + *
5283 + */
5284 +#include <linux/init.h>
5285 +#include <linux/version.h>
5286 +#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,35)
5287 +#include <linux/sched.h>
5288 +#endif
5289 +#include <linux/module.h>
5290 +#include <linux/kernel.h> /* printk() */
5291 +#include <linux/slab.h> /* kmalloc() */
5292 +#include <linux/fs.h> /* everything... */
5293 +#include <linux/errno.h> /* error codes */
5294 +#include <linux/types.h> /* size_t */
5295 +#include <linux/proc_fs.h>
5296 +#include <linux/fcntl.h> /* O_ACCMODE */
5297 +#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,36)
5298 +#include <asm/system.h> /* cli(), *_flags */
5299 +#endif
5300 +#include <asm/uaccess.h> /* copy_from/to_user */
5301 +#include <linux/interrupt.h>
5302 +#include <linux/mm.h>
5303 +#include <linux/dma-mapping.h>
5304 +#include <sound/core.h>
5305 +#include <linux/pci.h>
5306 +#include <sound/pcm.h>
5307 +#include <sound/pcm_params.h>
5308 +#include <sound/soc.h>
5309 +#include <sound/soc-dapm.h>
5310 +#include <sound/initval.h>
5311 +#include <linux/i2c.h>
5312 +#include <linux/ioport.h>
5313 +#include <linux/delay.h>
5314 +#include "ralink_gdma.h"
5315 +#include "mt76xx_i2s.h"
5316 +#include "mt76xx_machine.h"
5317 +#if defined(CONFIG_SND_SOC_WM8960)
5318 +#include "../codecs/wm8960.h"
5319 +#endif
5320 +
5321 +#define I2C_AUDIO_DEV_ID       (0)
5322 +/****************************/
5323 +/*FUNCTION DECLRATION          */
5324 +/****************************/
5325 +extern unsigned long i2s_codec_12p288Mhz[11];
5326 +extern unsigned long i2s_codec_12Mhz[11];
5327 +
5328 +
5329 +static int mt76xx_codec_clock_hwparams(struct snd_pcm_substream *substream,\
5330 +                               struct snd_pcm_hw_params *params);
5331 +static int mt76xx_codec_startup(struct snd_pcm_substream *substream);
5332 +static int mt76xx_codec_init(struct snd_soc_pcm_runtime *rtd);
5333 +extern struct snd_soc_dai_driver mt76xx_i2s_dai;
5334 +extern struct snd_soc_platform_driver mt76xx_soc_platform;
5335 +struct platform_device *mt76xx_audio_device;
5336 +
5337 +#if defined(CONFIG_SND_SOC_WM8960)
5338 +extern struct snd_soc_dai wm8960_dai;
5339 +extern struct snd_soc_codec_device soc_codec_dev_wm8960;
5340 +#endif
5341 +
5342 +static struct snd_soc_ops mtk_audio_ops = {
5343 +       .hw_params = mt76xx_codec_clock_hwparams,
5344 +       .startup = mt76xx_codec_startup,
5345 +};
5346 +
5347 +static struct snd_soc_dai_link mtk_audio_dai = {
5348 +       .name = "mtk_dai",
5349 +       .stream_name = "WMserious PCM",
5350 +       .cpu_dai_name   = "mt76xx-i2s",
5351 +       .codec_dai_name = "wm8960-hifi",
5352 +       .codec_name     = "wm8960.0-001a",
5353 +       .platform_name  = "mt76xx-pcm",
5354 +       .ignore_pmdown_time = true,
5355 +       .init = mt76xx_codec_init,
5356 +       .ops = &mtk_audio_ops,
5357 +};
5358 +
5359 +static struct snd_soc_card mtk_audio_card = {
5360 +       .name = "MTK APSoC I2S",
5361 +       .owner = THIS_MODULE,
5362 +       .dai_link = &mtk_audio_dai,//I2S/Codec
5363 +       .num_links = 1,
5364 +};
5365 +
5366 +static int mt76xx_codec_clock_hwparams(struct snd_pcm_substream *substream,
5367 +                               struct snd_pcm_hw_params *params)
5368 +{
5369 +       struct snd_soc_pcm_runtime *p = substream->private_data;
5370 +       struct snd_soc_dai *codec_dai = p->codec_dai;
5371 +       struct snd_pcm_runtime *runtime = substream->runtime;
5372 +       i2s_config_type* rtd = runtime->private_data;
5373 +       unsigned long data,index = 0;
5374 +       unsigned long* pTable;
5375 +       int mclk,ret,targetClk = 0;
5376 +
5377 +       /*For duplex mode, avoid setting twice.*/
5378 +       if((rtd->bRxDMAEnable == GDMA_I2S_EN) || (rtd->bTxDMAEnable == GDMA_I2S_EN))
5379 +               return 0;
5380 +#if defined(CONFIG_I2S_MCLK_12MHZ)
5381 +       mclk = 12000000;
5382 +#elif defined(CONFIG_I2S_MCLK_12P288MHZ)
5383 +       mclk = 12288000;
5384 +#else
5385 +       mclk = 12000000;
5386 +#endif
5387 +       //snd_soc_dai_set_sysclk(codec_dai,0,mclk, SND_SOC_CLOCK_IN);
5388 +
5389 +       switch(params_rate(params)){
5390 +       case 8000:
5391 +               index = 0;
5392 +               targetClk = 12288000;
5393 +               break;
5394 +       case 12000:
5395 +               index = 2;
5396 +               targetClk = 12288000;
5397 +               break;
5398 +       case 16000:
5399 +               index = 3;
5400 +               targetClk = 12288000;
5401 +               break;
5402 +       case 24000:
5403 +               index = 5;
5404 +               targetClk = 12288000;
5405 +               break;
5406 +       case 32000:
5407 +               index = 6;
5408 +               targetClk = 12288000;
5409 +               break;
5410 +       case 48000:
5411 +               index = 8;
5412 +               targetClk = 12288000;
5413 +               break;
5414 +       case 11025:
5415 +               index = 1;
5416 +               targetClk = 11289600;
5417 +               break;
5418 +       case 22050:
5419 +               index = 4;
5420 +               targetClk = 11289600;
5421 +               break;
5422 +       case 44100:
5423 +               index = 7;
5424 +               targetClk = 11289600;
5425 +               break;
5426 +       case 88200:
5427 +               index = 9;
5428 +               targetClk = 11289600;
5429 +               break;
5430 +       case 96000:
5431 +               index = 10;
5432 +               targetClk = 11289600;
5433 +               break;
5434 +       default:
5435 +               index = 7;
5436 +               targetClk = 12288000;
5437 +               //MSG("audio sampling rate %u should be %d ~ %d Hz\n", (u32)params_rate(params), MIN_SRATE_HZ, MAX_SRATE_HZ);
5438 +               break;
5439 +       }
5440 +#if defined(CONFIG_SND_SOC_WM8960)
5441 +       /*
5442 +        * There is a fixed divide by 4 in the PLL and a selectable
5443 +        * divide by N after the PLL which should be set to divide by 2 to meet this requirement.
5444 +        * */
5445 +       ret = snd_soc_dai_set_pll(codec_dai, 0, 0,mclk, targetClk*2);
5446 +       /* From app notes: allow Vref to stabilize to reduce clicks */
5447 +       if(rtd->slave_en){
5448 +               //printk("WM8960 is in master mode\n");
5449 +               ret = snd_soc_dai_set_clkdiv(codec_dai, WM8960_DCLKDIV, 0x1c4);
5450 +               ret = snd_soc_dai_set_clkdiv(codec_dai, WM8960_SYSCLKDIV, 0x5);
5451 +       }
5452 +
5453 +#endif
5454 +       if(!rtd->slave_en)
5455 +               snd_soc_dai_set_fmt(codec_dai,SND_SOC_DAIFMT_CBS_CFS|SND_SOC_DAIFMT_I2S|SND_SOC_DAIFMT_NB_NF);
5456 +       else{
5457 +               snd_soc_dai_set_fmt(codec_dai,SND_SOC_DAIFMT_CBM_CFM|SND_SOC_DAIFMT_I2S|SND_SOC_DAIFMT_NB_NF);
5458 +       }
5459 +       mdelay(5);
5460 +
5461 +#if defined(CONFIG_SND_SOC_WM8960)
5462 +#if defined(CONFIG_I2S_MCLK_12MHZ)
5463 +       pTable = i2s_codec_12Mhz;
5464 +       data = pTable[index];
5465 +#else
5466 +       pTable = i2s_codec_12p288Mhz;
5467 +       data = pTable[index];
5468 +#endif
5469 +       if(rtd->codec_pll_en)
5470 +               ret = snd_soc_dai_set_clkdiv(codec_dai, WM8960_DACDIV, (data<<3)|0x5);
5471 +       else
5472 +               ret = snd_soc_dai_set_clkdiv(codec_dai, WM8960_DACDIV, (data<<3|0x4));
5473 +#endif
5474 +
5475 +       return 0;
5476 +}
5477 +
5478 +static int mt76xx_codec_startup(struct snd_pcm_substream *substream)
5479 +{
5480 +       //printk("******* %s *******\n", __func__);
5481 +       return 0;
5482 +}
5483 +static int mt76xx_codec_init(struct snd_soc_pcm_runtime *rtd)
5484 +{
5485 +
5486 +       //printk("******* %s *******\n", __func__);
5487 +       return 0;
5488 +}
5489 +
5490 +static struct i2c_board_info i2c_board_info[] = {
5491 +       {
5492 +#if defined(CONFIG_SND_SOC_WM8750)
5493 +               I2C_BOARD_INFO("wm8750", (0x36 >> 1)),
5494 +#elif defined(CONFIG_SND_SOC_WM8960)
5495 +               I2C_BOARD_INFO("codec_wm8960", (0x34)),
5496 +       }, {
5497 +               I2C_BOARD_INFO("wm8960", (0x34 >> 1)),
5498 +#endif
5499 +       }
5500 +};
5501 +
5502 +static struct platform_device *soc_mtk_i2s_dev;
5503 +static struct platform_device *soc_mtk_pcm_dev;
5504 +
5505 +static int __init mt76xx_machine_init(void)
5506 +{
5507 +       //struct snd_soc_device *socdev = &mtk_audio_devdata;
5508 +       //struct i2c_adapter *adapter = NULL;
5509 +       //struct i2c_client *client = NULL;
5510 +       int ret = 0;
5511 +       struct i2c_adapter *adapter = NULL;
5512 +        struct i2c_client *client = NULL;
5513 +
5514 +       adapter = i2c_get_adapter(I2C_AUDIO_DEV_ID);
5515 +       if (!adapter)
5516 +               return -ENODEV;
5517 +       client = i2c_new_device(adapter, &i2c_board_info[0]);
5518 +       if (!client)
5519 +               return -ENODEV;
5520 +       i2c_get_clientdata(client);
5521 +
5522 +       client = i2c_new_device(adapter, &i2c_board_info[1]);
5523 +       if (!client)
5524 +               return -ENODEV;
5525 +       i2c_get_clientdata(client);
5526 +
5527 +       i2c_put_adapter(adapter);
5528 +
5529 +       soc_mtk_i2s_dev =
5530 +               platform_device_register_simple("mt76xx-i2s", -1, NULL, 0);
5531 +       if (IS_ERR(soc_mtk_i2s_dev))
5532 +               return PTR_ERR(soc_mtk_i2s_dev);
5533 +
5534 +       soc_mtk_pcm_dev =
5535 +               platform_device_register_simple("mt76xx-pcm", -1, NULL, 0);
5536 +       if (IS_ERR(soc_mtk_pcm_dev))
5537 +               return PTR_ERR(soc_mtk_pcm_dev);
5538 +
5539 +       mt76xx_audio_device = platform_device_alloc("soc-audio",-1);
5540 +       if (mt76xx_audio_device == NULL) {
5541 +               ret = -ENOMEM;
5542 +               goto err_device_alloc;
5543 +       }
5544 +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,38)
5545 +       platform_set_drvdata(mt76xx_audio_device, &mtk_audio_card);
5546 +#else
5547 +       platform_set_drvdata(mt76xx_audio_device, &mtk_audio_devdata);
5548 +       mtk_audio_devdata.dev = &mt76xx_audio_device->dev;
5549 +#endif
5550 +
5551 +       /*Ralink I2S register process end*/
5552 +       ret = platform_device_add(mt76xx_audio_device);
5553 +       if (ret) {
5554 +               printk("mtk audio device : platform_device_add failed (%d)\n",ret);
5555 +               goto err_device_add;
5556 +       }
5557 +
5558 +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,38)
5559 +#else
5560 +       snd_soc_register_dai(&mt76xx_i2s_dai);
5561 +#endif
5562 +
5563 +       return 0;
5564 +
5565 +err_device_add:
5566 +       if (mt76xx_audio_device!= NULL) {
5567 +               platform_device_put(mt76xx_audio_device);
5568 +               mt76xx_audio_device = NULL;
5569 +       }
5570 +err_device_alloc:
5571 +       return ret;
5572 +}
5573 +
5574 +
5575 +static void __exit mt76xx_machine_exit(void)
5576 +{
5577 +
5578 +       platform_device_unregister(mt76xx_audio_device);
5579 +#if LINUX_VERSION_CODE >= KERNEL_VERSION(3,10,20)
5580 +       /* Do nothing */
5581 +#elif LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,38)
5582 +       snd_soc_unregister_platform(&mt76xx_audio_device->dev);
5583 +#else
5584 +       snd_soc_unregister_platform(&mt76xx_soc_platform);
5585 +#endif
5586 +       platform_device_unregister(soc_mtk_i2s_dev);
5587 +       platform_device_unregister(soc_mtk_pcm_dev);
5588 +
5589 +       mt76xx_audio_device = NULL;
5590 +}
5591 +
5592 +//module_init(mt76xx_machine_init);
5593 +late_initcall(mt76xx_machine_init);
5594 +module_exit(mt76xx_machine_exit);
5595 +//EXPORT_SYMBOL_GPL(mt76xx_soc_platform);
5596 +MODULE_LICENSE("GPL");
5597 --- /dev/null
5598 +++ b/sound/soc/mtk/mt76xx_machine.h
5599 @@ -0,0 +1,21 @@
5600 +/*
5601 + * mtk_audio_device.h
5602 + *
5603 + *  Created on: 2013/10/23
5604 + *      Author: MTK04880
5605 + */
5606 +
5607 +#ifndef MT76XX_MACHINE_H_
5608 +#define MT76XX_MACHINE_H_
5609 +#include <sound/pcm.h>
5610 +#include <sound/pcm_params.h>
5611 +#include <sound/soc.h>
5612 +#include <sound/soc-dapm.h>
5613 +
5614 +#if 0
5615 +#ifdef CONFIG_I2S_MMAP
5616 +#undef CONFIG_I2S_MMAP
5617 +#endif
5618 +#endif
5619 +
5620 +#endif /* MT76XX_MACHINE_H_ */
5621 --- /dev/null
5622 +++ b/sound/soc/mtk/mt76xx_pcm.c
5623 @@ -0,0 +1,499 @@
5624 +/*
5625 + * mt76xx_pcm.c
5626 + *
5627 + *  Created on: 2013/9/6
5628 + *      Author: MTK04880
5629 + */
5630 +
5631 +#include <linux/init.h>
5632 +#include <linux/version.h>
5633 +#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,35)
5634 +#include <linux/sched.h>
5635 +#endif
5636 +#include <linux/module.h>
5637 +#include <linux/kernel.h> /* printk() */
5638 +#include <linux/slab.h> /* kmalloc() */
5639 +#include <linux/fs.h> /* everything... */
5640 +#include <linux/errno.h> /* error codes */
5641 +#include <linux/types.h> /* size_t */
5642 +#include <linux/proc_fs.h>
5643 +#include <linux/fcntl.h> /* O_ACCMODE */
5644 +#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,36)
5645 +#include <asm/system.h> /* cli(), *_flags */
5646 +#endif
5647 +#include <asm/uaccess.h> /* copy_from/to_user */
5648 +#include <linux/interrupt.h>
5649 +#include <linux/mm.h>
5650 +#include <linux/dma-mapping.h>
5651 +#include <sound/core.h>
5652 +#include <linux/pci.h>
5653 +#include <sound/pcm.h>
5654 +#include <sound/pcm_params.h>
5655 +#include <sound/soc.h>
5656 +#include <sound/soc-dapm.h>
5657 +#include <sound/initval.h>
5658 +#include "ralink_gdma.h"
5659 +#include "mt76xx_i2s.h"
5660 +
5661 +#define GDMA_PAGE_SIZE                 I2S_PAGE_SIZE
5662 +#define GDMA_PAGE_NUM          MAX_I2S_PAGE
5663 +#define GDMA_TOTAL_PAGE_SIZE   I2S_TOTAL_PAGE_SIZE
5664 +
5665 +dma_addr_t i2s_txdma_addr, i2s_rxdma_addr;
5666 +dma_addr_t i2s_mmap_addr[GDMA_PAGE_NUM*2];
5667 +
5668 +extern struct tasklet_struct i2s_tx_tasklet;
5669 +extern struct tasklet_struct i2s_rx_tasklet;
5670 +extern int i2s_mmap_remap(struct vm_area_struct *vma, unsigned long size);
5671 +extern void i2s_tx_end_sleep_on(i2s_config_type* ptri2s_config);
5672 +extern void i2s_rx_end_sleep_on(i2s_config_type* ptri2s_config);
5673 +
5674 +static int mt76xx_pcm_open(struct snd_pcm_substream *substream);
5675 +static int mt76xx_pcm_new(struct snd_soc_pcm_runtime *rtd);
5676 +static void mt76xx_pcm_free(struct snd_pcm *pcm);
5677 +static int mt76xx_pcm_close(struct snd_pcm_substream *substream);
5678 +static snd_pcm_uframes_t mt76xx_pcm_pointer(struct snd_pcm_substream *substream);
5679 +static int mt76xx_pcm_trigger(struct snd_pcm_substream *substream, int cmd);
5680 +static int mt76xx_pcm_prepare(struct snd_pcm_substream *substream);
5681 +static int mt76xx_pcm_hw_params(struct snd_pcm_substream *substream,\
5682 +                                struct snd_pcm_hw_params *hw_params);
5683 +static int mt76xx_pcm_copy(struct snd_pcm_substream *substream, int channel,\
5684 +               snd_pcm_uframes_t pos,void __user *buf, snd_pcm_uframes_t count);
5685 +static int mt76xx_pcm_mmap(struct snd_pcm_substream *substream, struct vm_area_struct *vma);
5686 +static int mt76xx_pcm_hw_free(struct snd_pcm_substream *substream);
5687 +
5688 +static int mt76xx_pcm_free_dma_buffer(struct snd_pcm_substream *substream,int stream);
5689 +static int mt76xx_pcm_allocate_dma_buffer(struct snd_pcm_substream *substream,int stream);
5690 +
5691 +#if LINUX_VERSION_CODE > KERNEL_VERSION(3,10,20)
5692 +static int mt76xx_platform_drv_probe(struct platform_device *pdev);
5693 +static int mt76xx_platform_drv_remove(struct platform_device *pdev);
5694 +#endif
5695 +
5696 +static const struct snd_pcm_hardware mt76xx_pcm_hwparam = {
5697 +#if defined(CONFIG_I2S_MMAP)
5698 +       .info                   = (SNDRV_PCM_INFO_INTERLEAVED |
5699 +                               SNDRV_PCM_INFO_PAUSE |
5700 +                               SNDRV_PCM_INFO_RESUME |
5701 +                               SNDRV_PCM_INFO_MMAP |
5702 +                               SNDRV_PCM_INFO_MMAP_VALID),
5703 +#else
5704 +       .info                   = (SNDRV_PCM_INFO_INTERLEAVED |
5705 +                               SNDRV_PCM_INFO_PAUSE |
5706 +                               SNDRV_PCM_INFO_RESUME),
5707 +#endif
5708 +       .formats                = SNDRV_PCM_FMTBIT_S16_LE,
5709 +       .period_bytes_min       = GDMA_PAGE_SIZE,
5710 +       .period_bytes_max       = GDMA_PAGE_SIZE,
5711 +       .periods_min            = 1,
5712 +       .periods_max            = GDMA_PAGE_NUM,
5713 +       .buffer_bytes_max       = GDMA_TOTAL_PAGE_SIZE,
5714 +};
5715 +
5716 +static struct snd_pcm_ops mt76xx_pcm_ops = {
5717 +
5718 +       .open =         mt76xx_pcm_open,
5719 +       .ioctl =        snd_pcm_lib_ioctl,
5720 +       .hw_params =    mt76xx_pcm_hw_params,
5721 +       .hw_free =      mt76xx_pcm_hw_free,
5722 +       .trigger =      mt76xx_pcm_trigger,
5723 +       .prepare =      mt76xx_pcm_prepare,
5724 +       .pointer =      mt76xx_pcm_pointer,
5725 +       .close =        mt76xx_pcm_close,
5726 +#if defined(CONFIG_I2S_MMAP)
5727 +       .mmap = mt76xx_pcm_mmap,
5728 +#endif
5729 +       .copy = mt76xx_pcm_copy,
5730 +};
5731 +#if LINUX_VERSION_CODE > KERNEL_VERSION(3,10,0)
5732 +struct snd_soc_platform_driver mt76xx_soc_platform = {
5733 +       .ops            = &mt76xx_pcm_ops,
5734 +       .pcm_new        = mt76xx_pcm_new,
5735 +       .pcm_free       = mt76xx_pcm_free,
5736 +};
5737 +#else
5738 +struct snd_soc_platform mt76xx_soc_platform = {
5739 +       .name           = "mtk-dma",
5740 +       .pcm_ops        = &mt76xx_pcm_ops,
5741 +       .pcm_new        = mt76xx_pcm_new,
5742 +       .pcm_free       = mt76xx_pcm_free,
5743 +};
5744 +#endif
5745 +
5746 +static int mt76xx_pcm_close(struct snd_pcm_substream *substream){
5747 +
5748 +       //printk("******* %s *********\n", __func__);
5749 +       return 0;
5750 +}
5751 +
5752 +static snd_pcm_uframes_t mt76xx_pcm_pointer(struct snd_pcm_substream *substream)
5753 +{
5754 +       struct snd_pcm_runtime *runtime = substream->runtime;
5755 +       i2s_config_type* rtd = runtime->private_data;
5756 +       unsigned int offset = 0;
5757 +       //int buff_frame_bond = bytes_to_frames(runtime, GDMA_PAGE_SIZE);
5758 +       //printk("\n******* %s *********\n", __func__);
5759 +
5760 +       if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK){
5761 +               offset = bytes_to_frames(runtime, GDMA_PAGE_SIZE*rtd->tx_r_idx);
5762 +               //printk("r:%d w:%d (%d) \n",rtd->tx_r_idx,rtd->tx_w_idx,(runtime->control->appl_ptr/buff_frame_bond)%GDMA_PAGE_NUM);
5763 +       }
5764 +       else{
5765 +               offset = bytes_to_frames(runtime, GDMA_PAGE_SIZE*rtd->rx_w_idx);
5766 +               //printk("w:%d r:%d appl_ptr:%x\n",rtd->rx_w_idx,rtd->rx_r_idx,(runtime->control->appl_ptr/buff_frame_bond)%GDMA_PAGE_NUM);
5767 +       }
5768 +       return offset;
5769 +}
5770 +
5771 +
5772 +static int mt76xx_pcm_trigger(struct snd_pcm_substream *substream, int cmd)
5773 +{
5774 +       int ret = 0;
5775 +       i2s_config_type* rtd = (i2s_config_type*)substream->runtime->private_data;
5776 +       //struct snd_pcm_runtime *runtime= substream->runtime;
5777 +
5778 +       //printk("******* %s *********\n", __func__);
5779 +/*     printk("trigger cmd:%s\n",(cmd==SNDRV_PCM_TRIGGER_START)?"START":\
5780 +                       (cmd==SNDRV_PCM_TRIGGER_RESUME)?"RESUME":\
5781 +                       (cmd==SNDRV_PCM_TRIGGER_PAUSE_RELEASE)?"PAUSE_RELEASE":\
5782 +                       (cmd==SNDRV_PCM_TRIGGER_STOP)?"STOP":\
5783 +                       (cmd==SNDRV_PCM_TRIGGER_SUSPEND)?"SUSPEND":\
5784 +                       (cmd==SNDRV_PCM_TRIGGER_PAUSE_PUSH)?"PAUSE_PUSH":"default");
5785 +*/
5786 +       switch (cmd) {
5787 +       case SNDRV_PCM_TRIGGER_START:
5788 +               if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
5789 +                       rtd->bTrigger[SNDRV_PCM_STREAM_PLAYBACK] = 1;
5790 +               } else {
5791 +                       rtd->bTrigger[SNDRV_PCM_STREAM_CAPTURE] = 1;
5792 +               }
5793 +               break;
5794 +       case SNDRV_PCM_TRIGGER_STOP:
5795 +               if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
5796 +                       rtd->bTrigger[SNDRV_PCM_STREAM_PLAYBACK] = 0;
5797 +               } else {
5798 +                       rtd->bTrigger[SNDRV_PCM_STREAM_CAPTURE] = 0;
5799 +               }
5800 +               break;
5801 +       case SNDRV_PCM_TRIGGER_RESUME:
5802 +       case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
5803 +               if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK){
5804 +                       rtd->tx_pause_en = 0;
5805 +               } else {
5806 +                       rtd->rx_pause_en = 0;
5807 +               }
5808 +               break;
5809 +
5810 +       case SNDRV_PCM_TRIGGER_SUSPEND:
5811 +       case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
5812 +               if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK){
5813 +                       rtd->tx_pause_en = 1;
5814 +               } else {
5815 +                       rtd->rx_pause_en = 1;
5816 +               }
5817 +               break;
5818 +       default:
5819 +               ret = -EINVAL;
5820 +               break;
5821 +       }
5822 +       return ret;
5823 +}
5824 +
5825 +static int mt76xx_pcm_copy(struct snd_pcm_substream *substream, int channel,\
5826 +               snd_pcm_uframes_t pos,void __user *buf, snd_pcm_uframes_t count)
5827 +{
5828 +       struct snd_pcm_runtime *runtime= substream->runtime;
5829 +       i2s_config_type* rtd = runtime->private_data;
5830 +       int tx_w_idx = 0;
5831 +        int rx_r_idx = 0;
5832 +        char *hwbuf = NULL;
5833 +
5834 +       //printk("******* %s *********\n", __func__);
5835 +       hwbuf = runtime->dma_area + frames_to_bytes(runtime, pos);
5836 +       //MSG("%s bur:%x\n",__func__,hwbuf);
5837 +       //printk("hw_ptr:%d, buffer_size:%d, appl_prt:%d, boundary:%d\n",
5838 +       //              runtime->status->hw_ptr, runtime->buffer_size, runtime->control->appl_ptr, runtime->boundary);
5839 +
5840 +       if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK){
5841 +               rtd->tx_w_idx = (rtd->tx_w_idx+1)%MAX_I2S_PAGE;
5842 +                tx_w_idx = rtd->tx_w_idx;
5843 +                //printk("put TB[%d - %x] for user write\n",rtd->tx_w_idx,pos);
5844 +                copy_from_user(rtd->pMMAPTxBufPtr[tx_w_idx], (char*)buf, I2S_PAGE_SIZE);
5845 +       }
5846 +       else{
5847 +               rx_r_idx = rtd->rx_r_idx;
5848 +                rtd->rx_r_idx = (rtd->rx_r_idx+1)%MAX_I2S_PAGE;
5849 +                copy_to_user((char*)buf, rtd->pMMAPRxBufPtr[rx_r_idx], I2S_PAGE_SIZE);
5850 +       }
5851 +       return 0;
5852 +}
5853 +
5854 +static int mt76xx_pcm_mmap(struct snd_pcm_substream *substream, struct vm_area_struct *vma)
5855 +{
5856 +        int ret;
5857 +        unsigned long size;
5858 +
5859 +        size = vma->vm_end-vma->vm_start;
5860 +        printk("******* %s: size :%lx end:%lx start:%lx *******\n", __func__,size,vma->vm_end,vma->vm_start);
5861 +        ret = i2s_mmap_remap(vma, size);
5862 +
5863 +        return ret;
5864 +}
5865 +
5866 +
5867 +static int mt76xx_pcm_prepare(struct snd_pcm_substream *substream)
5868 +{
5869 +       struct snd_pcm_runtime *runtime= substream->runtime;
5870 +       i2s_config_type *rtd = (i2s_config_type*)runtime->private_data;
5871 +       //runtime->buffer_size = GDMA_PAGE_NUM*GDMA_PAGE_SIZE;
5872 +       //runtime->boundary = (GDMA_PAGE_NUM*GDMA_PAGE_SIZE)/4;
5873 +
5874 +       //printk("******* %s *******\n", __func__);
5875 +       if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK){
5876 +               //printk("===== %s:%s:%d =====\n", __FILE__, __func__, __LINE__);
5877 +               mt76xx_pcm_allocate_dma_buffer(substream,SNDRV_PCM_STREAM_PLAYBACK);
5878 +
5879 +               if(! rtd->dmaStat[SNDRV_PCM_STREAM_PLAYBACK]){
5880 +                       i2s_page_prepare(rtd,STREAM_PLAYBACK);
5881 +                       tasklet_init(&i2s_tx_tasklet, i2s_tx_task, (u32)rtd);
5882 +                       rtd->dmaStat[SNDRV_PCM_STREAM_PLAYBACK] = 1;
5883 +                       gdma_unmask_handler(GDMA_I2S_TX0);
5884 +               }
5885 +       } else {
5886 +               mt76xx_pcm_allocate_dma_buffer(substream,SNDRV_PCM_STREAM_CAPTURE);
5887 +
5888 +               if(! rtd->dmaStat[SNDRV_PCM_STREAM_CAPTURE]){
5889 +                       i2s_page_prepare(rtd,STREAM_CAPTURE); /* TX:enLabel=1; RX:enLabel=2 */
5890 +                       tasklet_init(&i2s_rx_tasklet, i2s_rx_task, (u32)rtd);
5891 +                       rtd->dmaStat[SNDRV_PCM_STREAM_CAPTURE] = 1;
5892 +                       gdma_unmask_handler(GDMA_I2S_RX0);
5893 +               }
5894 +       }
5895 +
5896 +       return 0;
5897 +}
5898 +
5899 +
5900 +static int mt76xx_pcm_hw_params(struct snd_pcm_substream *substream,
5901 +                                struct snd_pcm_hw_params *hw_params)
5902 +{
5903 +       /*struct snd_pcm_runtime *runtime = substream->runtime;
5904 +       i2s_config_type *rtd = (i2s_config_type*)runtime->private_data;
5905 +       */
5906 +       int ret,i;
5907 +       ret = i = 0;
5908 +
5909 +       //printk("******* %s *******\n", __func__);
5910 +       if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK){
5911 +               //i2s_page_prepare(rtd,STREAM_PLAYBACK);
5912 +       } else {
5913 +               //i2s_page_prepare(rtd,STREAM_CAPTURE);
5914 +       }
5915 +
5916 +       return ret;
5917 +}
5918 +
5919 +static int mt76xx_pcm_hw_free(struct snd_pcm_substream *substream)
5920 +{
5921 +       i2s_config_type* rtd = (i2s_config_type*)substream->runtime->private_data;
5922 +       //struct snd_dma_buffer *buf = &substream->dma_buffer;
5923 +
5924 +       //printk("******* %s *******\n", __func__);
5925 +       if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK){
5926 +               if(rtd->dmaStat[SNDRV_PCM_STREAM_PLAYBACK]){
5927 +
5928 +                       gdma_En_Switch(rtd,STREAM_PLAYBACK,GDMA_I2S_DIS);
5929 +                       i2s_tx_end_sleep_on(rtd);
5930 +                       tasklet_kill(&i2s_tx_tasklet);
5931 +                       i2s_tx_disable(rtd);
5932 +                       //mt76xx_pcm_free_dma_buffer(substream,substream->stream);
5933 +                       i2s_page_release(rtd,STREAM_PLAYBACK);
5934 +                       rtd->dmaStat[SNDRV_PCM_STREAM_PLAYBACK] = 0;
5935 +               }
5936 +               mt76xx_pcm_free_dma_buffer(substream,substream->stream);
5937 +       }
5938 +       else{
5939 +               if(rtd->dmaStat[SNDRV_PCM_STREAM_CAPTURE]){
5940 +
5941 +                       gdma_En_Switch(rtd,STREAM_CAPTURE,GDMA_I2S_DIS);
5942 +                       i2s_rx_end_sleep_on(rtd);
5943 +                       tasklet_kill(&i2s_rx_tasklet);
5944 +                       i2s_rx_disable(rtd);
5945 +                       //mt76xx_pcm_free_dma_buffer(substream,substream->stream);
5946 +                       i2s_page_release(rtd,STREAM_CAPTURE);
5947 +                       rtd->dmaStat[SNDRV_PCM_STREAM_CAPTURE] = 0;
5948 +               }
5949 +               mt76xx_pcm_free_dma_buffer(substream,substream->stream);
5950 +       }
5951 +       return 0;
5952 +}
5953 +
5954 +static int mt76xx_pcm_free_dma_buffer(struct snd_pcm_substream *substream,
5955 +       int stream)
5956 +{
5957 +
5958 +       //struct snd_pcm_substream *substream = pcm->streams[stream].substream;
5959 +       struct snd_dma_buffer *buf = &substream->dma_buffer;
5960 +       i2s_config_type* rtd = (i2s_config_type*)substream->runtime->private_data;
5961 +
5962 +       //printk("******* %s *******\n", __func__);
5963 +       if (!buf->area)
5964 +               return 0;
5965 +       if(substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
5966 +               i2s_memPool_free(rtd,STREAM_PLAYBACK);
5967 +       else
5968 +               i2s_memPool_free(rtd,STREAM_CAPTURE);
5969 +       buf->area = NULL;
5970 +       snd_pcm_set_runtime_buffer(substream, NULL);
5971 +       return 0;
5972 +}
5973 +
5974 +static int mt76xx_pcm_allocate_dma_buffer(struct snd_pcm_substream *substream,
5975 +       int stream)
5976 +{
5977 +       //struct snd_pcm_substream *substream = pcm->streams[stream].substream;
5978 +       struct snd_dma_buffer *buf = &substream->dma_buffer;
5979 +       i2s_config_type* rtd = (i2s_config_type*)substream->runtime->private_data;
5980 +
5981 +       //printk("******* %s *******\n", __func__);
5982 +       if(!buf->area){
5983 +#if defined(CONFIG_I2S_MMAP)
5984 +               printk("\n############## MMAP ##############\n");
5985 +               buf->dev.type = SNDRV_DMA_TYPE_DEV;
5986 +#else
5987 +               buf->dev.type = SNDRV_DMA_TYPE_UNKNOWN;
5988 +#endif
5989 +               buf->dev.dev = NULL;
5990 +               buf->private_data = NULL;
5991 +               if(stream == SNDRV_PCM_STREAM_PLAYBACK)
5992 +                       buf->area = i2s_memPool_Alloc(rtd,STREAM_PLAYBACK);
5993 +               else
5994 +                       buf->area = i2s_memPool_Alloc(rtd,STREAM_CAPTURE);
5995 +
5996 +               if (!buf->area)
5997 +                       return -ENOMEM;
5998 +               buf->bytes = GDMA_TOTAL_PAGE_SIZE;
5999 +#if defined(CONFIG_I2S_MMAP)
6000 +               buf->addr = i2s_mmap_phys_addr(rtd);
6001 +#endif
6002 +               snd_pcm_set_runtime_buffer(substream, buf);
6003 +       } else{
6004 +               //printk("Buffer have been allocated!\n");
6005 +       }
6006 +
6007 +       return 0;
6008 +}
6009 +
6010 +static int mt76xx_pcm_open(struct snd_pcm_substream *substream)
6011 +{
6012 +       struct snd_pcm_runtime *runtime= substream->runtime;
6013 +       struct snd_dma_buffer *buf = &substream->dma_buffer;
6014 +       int stream = substream->stream;
6015 +       int ret = 0;
6016 +
6017 +       //printk("******* %s *******\n", __func__);
6018 +       snd_soc_set_runtime_hwparams(substream, &mt76xx_pcm_hwparam);
6019 +       /* ensure that buffer size is a multiple of period size */
6020 +       ret = snd_pcm_hw_constraint_integer(runtime,
6021 +                                               SNDRV_PCM_HW_PARAM_PERIODS);
6022 +       if (ret < 0)
6023 +               goto out;
6024 +
6025 +#if 1
6026 +       if(stream == SNDRV_PCM_STREAM_PLAYBACK){
6027 +               ret = mt76xx_pcm_allocate_dma_buffer(substream,
6028 +                               SNDRV_PCM_STREAM_PLAYBACK);
6029 +       }
6030 +       else{
6031 +               ret = mt76xx_pcm_allocate_dma_buffer(substream,
6032 +                               SNDRV_PCM_STREAM_CAPTURE);
6033 +       }
6034 +#endif
6035 +
6036 +       if (ret)
6037 +               goto out;
6038 +
6039 +       if(buf)
6040 +               memset(buf->area,0,sizeof(I2S_PAGE_SIZE*MAX_I2S_PAGE));
6041 +
6042 + out:
6043 +       return ret;
6044 +}
6045 +
6046 +
6047 +
6048 +static int mt76xx_pcm_new(struct snd_soc_pcm_runtime *rtd)
6049 +{
6050 +//     int ret = 0;
6051 +
6052 +       //printk("******* %s *******\n", __func__);
6053 +       return 0;
6054 +}
6055 +
6056 +static void mt76xx_pcm_free(struct snd_pcm *pcm)
6057 +{
6058 +       /*struct snd_pcm_substream *substream;
6059 +       struct snd_dma_buffer *buf;
6060 +       i2s_config_type* rtd;
6061 +       int stream;
6062 +*/
6063 +       //printk("******* %s *******\n", __func__);
6064 +       //return 0;
6065 +}
6066 +
6067 +#if LINUX_VERSION_CODE >= KERNEL_VERSION(3,10,20)
6068 +static int mt76xx_platform_drv_probe(struct platform_device *pdev)
6069 +{
6070 +       //printk("******* %s *******\n", __func__);
6071 +       return snd_soc_register_platform(&pdev->dev, &mt76xx_soc_platform);
6072 +}
6073 +
6074 +static int mt76xx_platform_drv_remove(struct platform_device *pdev)
6075 +{
6076 +       //printk("******* %s *******\n", __func__);
6077 +       snd_soc_unregister_platform(&pdev->dev);
6078 +       return 0;
6079 +}
6080 +
6081 +static struct platform_driver mt76xx_pcm_driver = {
6082 +       .driver = {
6083 +               .name = "mt76xx-pcm",
6084 +               .owner = THIS_MODULE,
6085 +       },
6086 +
6087 +       .probe = mt76xx_platform_drv_probe,
6088 +       .remove = mt76xx_platform_drv_remove,
6089 +};
6090 +
6091 +static int __init mt76xx_pcm_init(void)
6092 +{
6093 +
6094 +       printk("******* %s *******\n", __func__);
6095 +       return platform_driver_register(&mt76xx_pcm_driver);
6096 +}
6097 +
6098 +static void __exit mt76xx_pcm_exit(void)
6099 +{
6100 +       platform_driver_unregister(&mt76xx_pcm_driver);
6101 +}
6102 +#else
6103 +static int __init mt76xx_pcm_init(void)
6104 +{
6105 +
6106 +       printk("******* %s *******\n", __func__);
6107 +       return snd_soc_register_platform(&mt76xx_soc_platform);
6108 +}
6109 +
6110 +static void __exit mt76xx_pcm_exit(void)
6111 +{
6112 +       printk("******* %s *******\n", __func__);
6113 +       snd_soc_unregister_platform(&mt76xx_soc_platform);
6114 +}
6115 +#endif
6116 +module_init(mt76xx_pcm_init);
6117 +module_exit(mt76xx_pcm_exit);
6118 +
6119 +MODULE_AUTHOR("Dora Chen");
6120 +MODULE_DESCRIPTION("MTK APSoC I2S DMA driver");
6121 +MODULE_LICENSE("GPL");
6122 +
6123 --- /dev/null
6124 +++ b/sound/soc/mtk/ralink_gdma.c
6125 @@ -0,0 +1,918 @@
6126 +/*
6127 + ***************************************************************************
6128 + * Ralink Tech Inc.
6129 + * 5F., No.36, Taiyuan St., Jhubei City,
6130 + * Hsinchu County 302,
6131 + * Taiwan, R.O.C.
6132 + *
6133 + * (c) Copyright, Ralink Technology, Inc.
6134 + *
6135 + *  This program is free software; you can redistribute  it and/or modify it
6136 + *  under  the terms of  the GNU General  Public License as published by the
6137 + *  Free Software Foundation;  either version 2 of the  License, or (at your
6138 + *  option) any later version.
6139 + *
6140 + *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
6141 + *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
6142 + *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
6143 + *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
6144 + *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
6145 + *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
6146 + *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
6147 + *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
6148 + *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
6149 + *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
6150 + *
6151 + *  You should have received a copy of the  GNU General Public License along
6152 + *  with this program; if not, write  to the Free Software Foundation, Inc.,
6153 + *  675 Mass Ave, Cambridge, MA 02139, USA.
6154 + *
6155 + *
6156 + ***************************************************************************
6157 + *
6158 +  Module Name:
6159 +  ralink_gdma.c
6160 +
6161 +  Abstract:
6162 +
6163 +  Revision History:
6164 +  Who         When            What
6165 +  --------    ----------      ----------------------------------------------
6166 +  Name        Date            Modification logs
6167 +  Steven Liu  2009-03-24      Support RT3883
6168 + *
6169 + */
6170 +#include <linux/init.h>
6171 +#include <linux/version.h>
6172 +#include <linux/module.h>
6173 +#include <linux/kernel.h>
6174 +#include <linux/interrupt.h>
6175 +#include <linux/fs.h>
6176 +#if defined (CONFIG_MIPS)
6177 +  #include <asm/uaccess.h>
6178 +  #include <asm/addrspace.h>
6179 +#endif
6180 +
6181 +#include "ralink_gdma.h"
6182 +
6183 +/*
6184 + * RT305x:
6185 + * Ch0 : Pcm0_Rx0 | Pcm0_Rx0 | ALL
6186 + * Ch1 : Pcm0_Rx1 | Pcm0_Rx1 | ALL
6187 + * Ch2 : Pcm0_Tx0 | Pcm0_Tx0 | ALL
6188 + * Ch3 : Pcm0_Tx1 | Pcm0_Tx1 | ALL
6189 + * Ch4 : Pcm1_Rx0 | I2S_Tx0  | ALL
6190 + * Ch5 : Pcm1_Rx1 | I2S_Tx1  | ALL
6191 + * Ch6 : Pcm1_Tx0 |  ALL     | ALL
6192 + * Ch7 : Pcm1_Tx1 |  ALL     | ALL
6193 + *
6194 + * RT3883:
6195 + * Ch0  : Pcm0_Rx0 | Pcm0_Rx0 | ALL
6196 + * Ch1  : Pcm0_Rx1 | Pcm0_Rx1 | ALL
6197 + * Ch2  : Pcm0_Tx0 | Pcm0_Tx0 | ALL
6198 + * Ch3  : Pcm0_Tx1 | Pcm0_Tx1 | ALL
6199 + * Ch4  : Pcm1_Rx0 | I2S_Tx0  | ALL
6200 + * Ch5  : Pcm1_Rx1 | I2S_Tx1  | ALL
6201 + * Ch6  : Pcm1_Tx0 | I2S_Rx0  | ALL
6202 + * Ch7  : Pcm1_Tx1 | I2S_Rx1  | ALL
6203 + * Ch8  : ALL     |  ALL     | ALL
6204 + * Ch9  : ALL     |  ALL     | ALL
6205 + * Ch10 : ALL     |  ALL     | ALL
6206 + * Ch11 : ALL     |  ALL     | ALL
6207 + * Ch12 : ALL     |  ALL     | ALL PCI TX
6208 + * Ch13 : ALL     |  ALL     | ALL PCI RX
6209 + * Ch14 : ALL     |  ALL     | ALL
6210 + * Ch15 : ALL     |  ALL     | ALL
6211 + *
6212 + */
6213 +
6214 +spinlock_t  gdma_lock;
6215 +spinlock_t  gdma_lock_mem;
6216 +spinlock_t  gdma_int_lock;
6217 +void (*GdmaDoneIntCallback[MAX_GDMA_CHANNEL])(uint32_t);
6218 +void (*GdmaUnMaskIntCallback[MAX_GDMA_CHANNEL])(uint32_t);
6219 +
6220 +
6221 +/**
6222 + * @brief Get free GDMA channel
6223 + *
6224 + * @param  ChNum   GDMA channel number
6225 + * @retval 1      channel is available
6226 + * @retval 0      channels are all busy
6227 + */
6228 +int _GdmaGetFreeCh(uint32_t *ChNum)
6229 +{
6230 +    unsigned long flags;
6231 +    uint32_t Data=0;
6232 +    uint32_t Ch=0;
6233 +#if defined (CONFIG_GDMA_DEBUG)
6234 +    static uint32_t Ch_RR=0;
6235 +#endif
6236 +
6237 +    spin_lock_irqsave(&gdma_lock, flags);
6238 +
6239 +#if defined (CONFIG_GDMA_PCM_ONLY)
6240 +#if defined (CONFIG_RALINK_RT3883) || defined (CONFIG_RALINK_RT3352) || defined (CONFIG_RALINK_RT5350) || defined (CONFIG_RALINK_RT6855) || defined (CONFIG_RALINK_RT6855A) || defined (CONFIG_RALINK_MT7620)  ||  defined (CONFIG_RALINK_MT7621) || defined (CONFIG_RALINK_MT7628) || defined (CONFIG_ARCH_MT7623)
6241 +    for(Ch=14; Ch<MAX_GDMA_CHANNEL;Ch++)  //channel 14~max_channe, channel 0~13 be usedl
6242 +#else
6243 +    for(Ch=MAX_GDMA_CHANNEL; Ch<MAX_GDMA_CHANNEL;Ch++)  //no free channel
6244 +#endif
6245 +#elif defined (CONFIG_GDMA_PCM_I2S_OTHERS)
6246 +#if defined (CONFIG_RALINK_RT3883) || defined (CONFIG_RALINK_RT3352) || defined (CONFIG_RALINK_RT5350) || defined (CONFIG_RALINK_RT6855) || defined (CONFIG_RALINK_RT6855A) || defined (CONFIG_RALINK_MT7620)  ||  defined (CONFIG_RALINK_MT7621) || defined (CONFIG_RALINK_MT7628) || defined (CONFIG_ARCH_MT7623)
6247 +    for(Ch=14; Ch<MAX_GDMA_CHANNEL;Ch++)  //channel 14~max_channe, channel 0~13 be usedl
6248 +#else
6249 +    for(Ch=6; Ch<MAX_GDMA_CHANNEL;Ch++)  //channel 6~max_channel
6250 +#endif
6251 +#elif defined (CONFIG_GDMA_EVERYBODY)
6252 +    for(Ch=0; Ch<MAX_GDMA_CHANNEL;Ch++)  //all channel
6253 +#elif defined (CONFIG_GDMA_DEBUG)
6254 +    for(Ch=(Ch_RR++)%MAX_GDMA_CHANNEL; Ch<MAX_GDMA_CHANNEL;Ch++)  //round robin
6255 +#endif
6256 +    {
6257 +       Data=GDMA_READ_REG(GDMA_CTRL_REG(Ch));
6258 +
6259 +       /* hardware will reset this bit if transaction is done.
6260 +        * It means channel is free */
6261 +       if((Data & (0x01<<CH_EBL_OFFSET))==0) {
6262 +           *ChNum = Ch;
6263 +           spin_unlock_irqrestore(&gdma_lock, flags);
6264 +           return 1; //Channel is free
6265 +       }
6266 +    }
6267 +
6268 +    spin_unlock_irqrestore(&gdma_lock, flags);
6269 +    return 0; // Channels are all busy
6270 +
6271 +}
6272 +
6273 +/**
6274 + * @brief Set channel is masked
6275 + *
6276 + * When channel is masked, the GDMA transaction will stop.
6277 + * When GDMA controller comes back from another channel (chain feature)
6278 + *
6279 + * >> Channel Mask=0: It's strange, and turns on related bit in GDMA interrupt
6280 + * status register (16:23 Unmasked)
6281 + *
6282 + * >> Channel Mask=1: It'll start GDMA transation, and clear this bit.
6283 + *
6284 + * @param  ChNum       GDMA channel number
6285 + * @retval 1           success
6286 + * @retval 0           fail
6287 + */
6288 +int GdmaMaskChannel(uint32_t ChNum)
6289 +{
6290 +    uint32_t Data=0;
6291 +
6292 +    Data=GDMA_READ_REG(GDMA_CTRL_REG1(ChNum));
6293 +    Data |= ( 0x01 << CH_MASK_OFFSET);
6294 +    GDMA_WRITE_REG(GDMA_CTRL_REG1(ChNum), Data);
6295 +    GDMA_PRINT("%s: Write %0X to %X\n", __FUNCTION__, Data, GDMA_CTRL_REG1(ChNum));
6296 +
6297 +    return 1;
6298 +}
6299 +
6300 +/**
6301 + * @brief Set channel is unmasked
6302 + *
6303 + * You can unmask the channel to start GDMA transaction.
6304 + *
6305 + * When GDMA controller comes back from another channel (chain feature)
6306 + *
6307 + * >> Channel Mask=0: It's strange, and turns on related bit in GDMA interrupt
6308 + * status register (16:23 Unmasked)
6309 + *
6310 + * >> Channel Mask=1: It'll start GDMA transation, and clear this bit.
6311 + *
6312 + * @param  ChNum       GDMA channel number
6313 + * @retval 1           success
6314 + * @retval 0           fail
6315 + */
6316 +int GdmaUnMaskChannel(uint32_t ChNum)
6317 +{
6318 +    uint32_t Data=0;
6319 +
6320 +    Data=GDMA_READ_REG(GDMA_CTRL_REG1(ChNum));
6321 +    Data &= ~( 0x01 << CH_MASK_OFFSET);
6322 +    GDMA_WRITE_REG(GDMA_CTRL_REG1(ChNum), Data);
6323 +    GDMA_PRINT("%s: Write %0X to %X\n", __FUNCTION__, Data, GDMA_CTRL_REG1(ChNum));
6324 +
6325 +    return 1;
6326 +}
6327 +
6328 +/**
6329 + * @brief Insert new GDMA entry to start GDMA transaction
6330 + *
6331 + * @param  ChNum       GDMA channel number
6332 + * @retval 1           success
6333 + * @retval 0           fail
6334 + */
6335 +int GdmaReqQuickIns(uint32_t ChNum)
6336 +{
6337 +    uint32_t Data=0;
6338 +
6339 +    //Mask Channel
6340 +    Data = GDMA_READ_REG(GDMA_CTRL_REG1(ChNum));
6341 +    Data |= ( 0x1 << CH_MASK_OFFSET);
6342 +    GDMA_WRITE_REG(GDMA_CTRL_REG1(ChNum), Data);
6343 +
6344 +    //Channel Enable
6345 +    Data = GDMA_READ_REG(GDMA_CTRL_REG(ChNum));
6346 +    Data |= (0x01<<CH_EBL_OFFSET);
6347 +    GDMA_WRITE_REG(GDMA_CTRL_REG(ChNum), Data);
6348 +
6349 +    return 1;
6350 +
6351 +}
6352 +
6353 +int _GdmaReqEntryIns(GdmaReqEntry *NewEntry)
6354 +{
6355 +    uint32_t Data=0;
6356 +
6357 +    GDMA_PRINT("== << GDMA Control Reg (Channel=%d) >> ===\n", NewEntry->ChNum);
6358 +    GDMA_PRINT(" Channel Source Addr = %x \n", NewEntry->Src);
6359 +    GDMA_PRINT(" Channel Dest Addr = %x \n", NewEntry->Dst);
6360 +    GDMA_PRINT(" Transfer Count=%d\n", NewEntry->TransCount);
6361 +    GDMA_PRINT(" Source DMA Req= DMA_REQ%d\n", NewEntry->SrcReqNum);
6362 +    GDMA_PRINT(" Dest DMA Req= DMA_REQ%d\n", NewEntry->DstReqNum);
6363 +    GDMA_PRINT(" Source Burst Mode=%s\n", NewEntry->SrcBurstMode ? "Fix" : "Inc");
6364 +    GDMA_PRINT(" Dest Burst Mode=%s\n", NewEntry->DstBurstMode ? "Fix" : "Inc");
6365 +    GDMA_PRINT(" Burst Size=%s\n", NewEntry->BurstSize ==0 ? "1 transfer" : \
6366 +           NewEntry->BurstSize ==1 ? "2 transfer" :\
6367 +           NewEntry->BurstSize ==2 ? "4 transfer" :\
6368 +           NewEntry->BurstSize ==3 ? "8 transfer" :\
6369 +           NewEntry->BurstSize ==4 ? "16 transfer" :\
6370 +           "Error");
6371 +    GDMA_PRINT(" Hardware/Software Mode = %s\n", NewEntry->SoftMode ?
6372 +           "Soft" : "Hw");
6373 +    GDMA_PRINT("== << GDMA Control Reg1 (Channel=%d) >> =\n", NewEntry->ChNum);
6374 +    GDMA_PRINT("Channel Done Interrput=%s\n", (NewEntry->DoneIntCallback!=NULL) ?
6375 +           "Enable" : "Disable");
6376 +    GDMA_PRINT("Channel Unmasked Int=%s\n", (NewEntry->UnMaskIntCallback!=NULL) ?
6377 +           "Enable" : "Disable");
6378 +#if !defined (CONFIG_RALINK_RT3052) && !defined (CONFIG_RALINK_RT3883)
6379 +    GDMA_PRINT("Coherent Interrupt =%s\n", (NewEntry->CoherentIntEbl==1)?
6380 +           "Enable" : "Disable");
6381 +#endif
6382 +    GDMA_PRINT("Next Unmasked Channel=%d\n", NewEntry->NextUnMaskCh);
6383 +    GDMA_PRINT("Channel Mask=%d\n", NewEntry->ChMask);
6384 +    GDMA_PRINT("========================================\n");
6385 +
6386 +    GDMA_WRITE_REG(GDMA_SRC_REG(NewEntry->ChNum), NewEntry->Src);
6387 +    GDMA_PRINT("SrcAddr: Write %0X to %X\n", \
6388 +           NewEntry->Src, GDMA_SRC_REG(NewEntry->ChNum));
6389 +
6390 +    GDMA_WRITE_REG(GDMA_DST_REG(NewEntry->ChNum), NewEntry->Dst);
6391 +    GDMA_PRINT("DstAddr: Write %0X to %X\n", \
6392 +           NewEntry->Dst, GDMA_DST_REG(NewEntry->ChNum));
6393 +
6394 +    Data |= ( (NewEntry->NextUnMaskCh) << NEXT_UNMASK_CH_OFFSET);
6395 +    Data |= ( NewEntry->ChMask << CH_MASK_OFFSET);
6396 +#if !defined (CONFIG_RALINK_RT3052) && !defined (CONFIG_RALINK_RT3883)
6397 +    Data |= ( NewEntry->CoherentIntEbl << COHERENT_INT_EBL_OFFSET);
6398 +#endif
6399 +
6400 +    if(NewEntry->UnMaskIntCallback!=NULL) {
6401 +       Data |= (0x01<<CH_UNMASKINT_EBL_OFFSET);
6402 +       GdmaUnMaskIntCallback[NewEntry->ChNum] = NewEntry->UnMaskIntCallback;
6403 +    }
6404 +
6405 +#if defined (CONFIG_RALINK_RT3883) || defined (CONFIG_RALINK_RT3352) || defined (CONFIG_RALINK_RT5350) || defined (CONFIG_RALINK_RT6855) || defined (CONFIG_RALINK_RT6855A) || defined (CONFIG_RALINK_MT7620)  ||  defined (CONFIG_RALINK_MT7621) || defined (CONFIG_RALINK_MT7628) || defined (CONFIG_ARCH_MT7623)
6406 +    Data |= (NewEntry->SrcReqNum << SRC_DMA_REQ_OFFSET);
6407 +    Data |= (NewEntry->DstReqNum << DST_DMA_REQ_OFFSET);
6408 +#endif
6409 +
6410 +    GDMA_WRITE_REG(GDMA_CTRL_REG1(NewEntry->ChNum), Data);
6411 +    GDMA_PRINT("CTRL1: Write %08X to %8X\n", Data, GDMA_CTRL_REG1(NewEntry->ChNum));
6412 +
6413 +    Data = ((NewEntry->TransCount) << TRANS_CNT_OFFSET);
6414 +#if defined (CONFIG_RALINK_RT3052)
6415 +    Data |= (NewEntry->SrcReqNum << SRC_DMA_REQ_OFFSET);
6416 +    Data |= (NewEntry->DstReqNum << DST_DMA_REQ_OFFSET);
6417 +#endif
6418 +    Data |= (NewEntry->SrcBurstMode << SRC_BRST_MODE_OFFSET);
6419 +    Data |= (NewEntry->DstBurstMode << DST_BRST_MODE_OFFSET);
6420 +    Data |= (NewEntry->BurstSize << BRST_SIZE_OFFSET);
6421 +
6422 +    if(NewEntry->DoneIntCallback!=NULL) {
6423 +       Data |= (0x01<<CH_DONEINT_EBL_OFFSET);
6424 +       GdmaDoneIntCallback[NewEntry->ChNum] = NewEntry->DoneIntCallback;
6425 +    }
6426 +
6427 +    if(NewEntry->SoftMode) {
6428 +       Data |= (0x01<<MODE_SEL_OFFSET);
6429 +    }
6430 +
6431 +    Data |= (0x01<<CH_EBL_OFFSET);
6432 +    GDMA_WRITE_REG(GDMA_CTRL_REG(NewEntry->ChNum), Data);
6433 +    //GDMA_READ_REG(GDMA_CTRL_REG(NewEntry->ChNum));
6434 +    GDMA_PRINT("CTRL: Write %08X to %8X\n", Data, GDMA_CTRL_REG(NewEntry->ChNum));
6435 +     //if there is no interrupt handler, this function will
6436 +    //return 1 until GDMA done.
6437 +    if(NewEntry->DoneIntCallback==NULL) {
6438 +       //wait for GDMA processing done
6439 +#if defined (CONFIG_RALINK_RT3052)
6440 +       while((GDMA_READ_REG(RALINK_GDMAISTS) &
6441 +                   (0x1<<NewEntry->ChNum))==0);
6442 +       //write 1 clear
6443 +       GDMA_WRITE_REG(RALINK_GDMAISTS, 1<< NewEntry->ChNum);
6444 +#elif defined (CONFIG_RALINK_RT3883) || defined (CONFIG_RALINK_RT3352) || defined (CONFIG_RALINK_RT5350) || defined (CONFIG_RALINK_RT6855) || defined (CONFIG_RALINK_RT6855A) || defined (CONFIG_RALINK_MT7620)  ||  defined (CONFIG_RALINK_MT7621) || defined (CONFIG_RALINK_MT7628) || defined (CONFIG_ARCH_MT7623)
6445 +       while((GDMA_READ_REG(RALINK_GDMA_DONEINT) &
6446 +                   (0x1<<NewEntry->ChNum))==0);
6447 +       //write 1 clear
6448 +       GDMA_WRITE_REG(RALINK_GDMA_DONEINT, 1<< NewEntry->ChNum);
6449 +#endif
6450 +    }
6451 +
6452 +    return 1;
6453 +
6454 +}
6455 +
6456 +#if defined(CONFIG_RALINK_MT7620) || defined (CONFIG_RALINK_MT7621) || defined (CONFIG_RALINK_MT7628) || defined (CONFIG_ARCH_MT7623)
6457 +/**
6458 + * @brief Start GDMA transaction for sending data to SPI
6459 + *
6460 + * @param  *Src        source address
6461 + * @param  *Dst        destination address
6462 +
6463 + * @param  TransCount          data length
6464 + * @param  *DoneIntCallback  callback function when transcation is done
6465 + * @param  *UnMaskIntCallback  callback func when ch mask field is incorrect
6466 + * @retval 1           success
6467 + * @retval 0           fail
6468 + */
6469 +int GdmaSpiTx(
6470 +       uint32_t Src,
6471 +       uint32_t Dst,
6472 +       uint16_t TransCount,
6473 +       void (*DoneIntCallback)(uint32_t data),
6474 +       void (*UnMaskIntCallback)(uint32_t data)
6475 +       )
6476 +{
6477 +    GdmaReqEntry Entry;
6478 +
6479 +       #if defined (CONFIG_MIPS)
6480 +    Entry.Src= (Src & 0x1FFFFFFF);
6481 +    Entry.Dst= (Dst & 0x1FFFFFFF);
6482 +  #else
6483 +    Entry.Src= Src;
6484 +    Entry.Dst= Dst;
6485 +  #endif
6486 +    Entry.TransCount = TransCount;
6487 +    Entry.SrcBurstMode=INC_MODE;
6488 +    Entry.DstBurstMode=FIX_MODE;
6489 +    Entry.BurstSize=BUSTER_SIZE_4B;
6490 +    Entry.SrcReqNum=DMA_MEM_REQ;
6491 +    Entry.DstReqNum=DMA_SPI_TX_REQ;
6492 +    Entry.DoneIntCallback=DoneIntCallback;
6493 +    Entry.UnMaskIntCallback=UnMaskIntCallback;
6494 +    Entry.SoftMode=0;
6495 +    Entry.ChMask=0;
6496 +    Entry.CoherentIntEbl=0;
6497 +
6498 +       //enable chain feature
6499 +       Entry.ChNum = GDMA_SPI_TX;
6500 +       Entry.NextUnMaskCh = GDMA_SPI_TX;
6501 +
6502 +    return _GdmaReqEntryIns(&Entry);
6503 +}
6504 +
6505 +int GdmaSpiRx(
6506 +       uint32_t Src,
6507 +       uint32_t Dst,
6508 +       uint16_t TransCount,
6509 +       void (*DoneIntCallback)(uint32_t data),
6510 +       void (*UnMaskIntCallback)(uint32_t data)
6511 +       )
6512 +{
6513 +    GdmaReqEntry Entry;
6514 +
6515 +       #if defined (CONFIG_MIPS)
6516 +    Entry.Src= (Src & 0x1FFFFFFF);
6517 +    Entry.Dst= (Dst & 0x1FFFFFFF);
6518 +  #else
6519 +    Entry.Src= Src;
6520 +    Entry.Dst= Dst;
6521 +  #endif
6522 +    Entry.TransCount = TransCount;
6523 +    Entry.SrcBurstMode=FIX_MODE;
6524 +    Entry.DstBurstMode=INC_MODE;
6525 +    Entry.BurstSize=BUSTER_SIZE_4B;
6526 +    Entry.SrcReqNum=DMA_SPI_RX_REQ;
6527 +    Entry.DstReqNum=DMA_MEM_REQ;
6528 +    Entry.DoneIntCallback=DoneIntCallback;
6529 +    Entry.UnMaskIntCallback=UnMaskIntCallback;
6530 +    Entry.SoftMode=0;
6531 +    Entry.ChMask=0;
6532 +    Entry.CoherentIntEbl=1;
6533 +
6534 +
6535 +       //enable chain feature
6536 +       Entry.ChNum=GDMA_SPI_RX;
6537 +       Entry.NextUnMaskCh=GDMA_SPI_RX;
6538 +
6539 +
6540 +    return _GdmaReqEntryIns(&Entry);
6541 +
6542 +}
6543 +#endif
6544 +
6545 +
6546 +/**
6547 + * @brief Start GDMA transaction for sending data to I2S
6548 + *
6549 + * @param  *Src        source address
6550 + * @param  *Dst        destination address
6551 + * @param  TxNo        I2S Tx number
6552 + * @param  TransCount          data length
6553 + * @param  *DoneIntCallback  callback function when transcation is done
6554 + * @param  *UnMaskIntCallback  callback func when ch mask field is incorrect
6555 + * @retval 1           success
6556 + * @retval 0           fail
6557 + */
6558 +int GdmaI2sTx(
6559 +       uint32_t Src,
6560 +       uint32_t Dst,
6561 +       uint8_t TxNo,
6562 +       uint16_t TransCount,
6563 +       void (*DoneIntCallback)(uint32_t data),
6564 +       void (*UnMaskIntCallback)(uint32_t data)
6565 +       )
6566 +{
6567 +    GdmaReqEntry Entry;
6568 +
6569 +       #if defined (CONFIG_MIPS)
6570 +    Entry.Src= (Src & 0x1FFFFFFF);
6571 +    Entry.Dst= (Dst & 0x1FFFFFFF);
6572 +  #else
6573 +    Entry.Src= Src;
6574 +    Entry.Dst= Dst;
6575 +  #endif
6576 +    Entry.TransCount = TransCount;
6577 +    Entry.SrcBurstMode=INC_MODE;
6578 +    Entry.DstBurstMode=FIX_MODE;
6579 +    Entry.BurstSize=BUSTER_SIZE_4B;
6580 +    Entry.SrcReqNum=DMA_MEM_REQ;
6581 +    Entry.DstReqNum=DMA_I2S_TX_REQ;
6582 +    Entry.DoneIntCallback=DoneIntCallback;
6583 +    Entry.UnMaskIntCallback=UnMaskIntCallback;
6584 +    Entry.SoftMode=0;
6585 +    Entry.ChMask=1;
6586 +    Entry.CoherentIntEbl=0;
6587 +
6588 +    if(TxNo==0) { //TX0
6589 +       //enable chain feature
6590 +       Entry.ChNum=GDMA_I2S_TX0;
6591 +       Entry.NextUnMaskCh= (TransCount==4) ?  GDMA_I2S_TX0 : GDMA_I2S_TX1;
6592 +    }else if(TxNo==1) { //TX1
6593 +       //enable chain feature
6594 +       Entry.ChNum=GDMA_I2S_TX1;
6595 +       Entry.NextUnMaskCh= (TransCount==4) ? GDMA_I2S_TX1 : GDMA_I2S_TX0;
6596 +    }else {
6597 +       GDMA_PRINT("I2S Tx Number %x is invalid\n", TxNo);
6598 +       return 0;
6599 +    }
6600 +
6601 +    return _GdmaReqEntryIns(&Entry);
6602 +
6603 +}
6604 +
6605 +
6606 +#if defined (CONFIG_RALINK_RT3883) || defined (CONFIG_RALINK_RT3352) || defined (CONFIG_RALINK_RT5350) || defined (CONFIG_RALINK_RT6855) || defined (CONFIG_RALINK_RT6855A) || defined (CONFIG_RALINK_MT7620) || defined (CONFIG_RALINK_MT7621) || defined (CONFIG_RALINK_MT7628) || defined (CONFIG_ARCH_MT7623)
6607 +/**
6608 + * @brief Start GDMA transaction for receiving data to I2S
6609 + *
6610 + * @param  *Src        source address
6611 + * @param  *Dst        destination address
6612 + * @param  TxNo        I2S Tx number
6613 + * @param  TransCount          data length
6614 + * @param  *DoneIntCallback  callback function when transcation is done
6615 + * @param  *UnMaskIntCallback  callback func when ch mask field is incorrect
6616 + * @retval 1           success
6617 + * @retval 0           fail
6618 + */
6619 +int GdmaI2sRx(
6620 +       uint32_t Src,
6621 +       uint32_t Dst,
6622 +       uint8_t RxNo,
6623 +       uint16_t TransCount,
6624 +       void (*DoneIntCallback)(uint32_t data),
6625 +       void (*UnMaskIntCallback)(uint32_t data)
6626 +       )
6627 +{
6628 +    GdmaReqEntry Entry;
6629 +       #if defined (CONFIG_MIPS)
6630 +    Entry.Src= (Src & 0x1FFFFFFF);
6631 +    Entry.Dst= (Dst & 0x1FFFFFFF);
6632 +  #else
6633 +    Entry.Src= Src;
6634 +    Entry.Dst= Dst;
6635 +  #endif
6636 +    Entry.TransCount = TransCount;
6637 +    Entry.SrcBurstMode=FIX_MODE;
6638 +    Entry.DstBurstMode=INC_MODE;
6639 +    Entry.BurstSize=BUSTER_SIZE_4B;
6640 +    Entry.SrcReqNum=DMA_I2S_RX_REQ;
6641 +    Entry.DstReqNum=DMA_MEM_REQ;
6642 +    Entry.DoneIntCallback=DoneIntCallback;
6643 +    Entry.UnMaskIntCallback=UnMaskIntCallback;
6644 +    Entry.SoftMode=0;
6645 +    Entry.ChMask=1;
6646 +    Entry.CoherentIntEbl=1;
6647 +
6648 +    if(RxNo==0) { //RX0
6649 +       //enable chain feature
6650 +       Entry.ChNum=GDMA_I2S_RX0;
6651 +       Entry.NextUnMaskCh=(TransCount==4) ? GDMA_I2S_RX0 : GDMA_I2S_RX1;
6652 +    }else if(RxNo==1) { //RX1
6653 +       //enable chain feature
6654 +       Entry.ChNum=GDMA_I2S_RX1;
6655 +       Entry.NextUnMaskCh=(TransCount==4) ? GDMA_I2S_RX1 : GDMA_I2S_RX0;
6656 +    }else {
6657 +       GDMA_PRINT("I2S Rx Number %x is invalid\n", RxNo);
6658 +       return 0;
6659 +    }
6660 +
6661 +    return _GdmaReqEntryIns(&Entry);
6662 +
6663 +}
6664 +
6665 +#endif
6666 +
6667 +/**
6668 + * @brief Start GDMA transaction for receiving data from PCM
6669 + *
6670 + * @param  *Src        source address
6671 + * @param  *Dst        destination address
6672 + * @param  TransCount   data length
6673 + * @param  PcmNo       PCM channel
6674 + * @param  RxNo        PCM Rx number
6675 + * @param  *DoneIntCallback  callback function when transcation is done
6676 + * @param  *UnMaskIntCallback  callback func when ch mask field is incorrect
6677 + * @retval 1           success
6678 + * @retval 0           fail
6679 + */
6680 +int GdmaPcmRx(
6681 +       uint32_t Src,
6682 +       uint32_t Dst,
6683 +       uint8_t PcmNo,
6684 +       uint8_t RxNo,
6685 +       uint16_t TransCount,
6686 +       void (*DoneIntCallback)(uint32_t data),
6687 +       void (*UnMaskIntCallback)(uint32_t data)
6688 +       )
6689 +{
6690 +    GdmaReqEntry Entry;
6691 +
6692 +       #if defined (CONFIG_MIPS)
6693 +    Entry.Src= (Src & 0x1FFFFFFF);
6694 +    Entry.Dst= (Dst & 0x1FFFFFFF);
6695 +  #else
6696 +    Entry.Src= Src;
6697 +    Entry.Dst= Dst;
6698 +  #endif
6699 +    Entry.TransCount = TransCount;
6700 +    Entry.SrcBurstMode=FIX_MODE;
6701 +    Entry.DstBurstMode=INC_MODE;
6702 +    Entry.BurstSize=BUSTER_SIZE_4B;
6703 +    Entry.DstReqNum=DMA_MEM_REQ;
6704 +    Entry.DoneIntCallback=DoneIntCallback;
6705 +    Entry.UnMaskIntCallback=UnMaskIntCallback;
6706 +    Entry.SoftMode=0;
6707 +    Entry.ChMask=1;
6708 +    Entry.CoherentIntEbl=1;
6709 +
6710 +       if(RxNo > 2) {
6711 +               GDMA_PRINT("PCM Rx Number %x is invalid\n", RxNo);
6712 +               return 0;
6713 +       }
6714 +
6715 +       switch(PcmNo)
6716 +       {
6717 +       case 0:
6718 +               Entry.SrcReqNum=DMA_PCM_RX0_REQ;
6719 +               break;
6720 +       case 1:
6721 +               Entry.SrcReqNum=DMA_PCM_RX1_REQ;
6722 +               break;
6723 +#if defined(CONFIG_RALINK_MT7620) || defined (CONFIG_RALINK_MT7621) || defined (CONFIG_RALINK_MT7628) || defined (CONFIG_ARCH_MT7623)
6724 +       case 2:
6725 +               Entry.SrcReqNum=DMA_PCM_RX2_REQ;
6726 +               break;
6727 +       case 3:
6728 +               Entry.SrcReqNum=DMA_PCM_RX3_REQ;
6729 +               break;
6730 +#endif
6731 +       default:
6732 +               GDMA_PRINT("PCM Channel %x is invalid\n", PcmNo);
6733 +               return 0;
6734 +       }
6735 +       Entry.ChNum=GDMA_PCM_RX(PcmNo,RxNo);
6736 +       Entry.NextUnMaskCh=GDMA_PCM_RX(PcmNo,1-RxNo);
6737 +
6738 +    return _GdmaReqEntryIns(&Entry);
6739 +
6740 +}
6741 +
6742 +/**
6743 + * @brief Start GDMA transaction for sending data to PCM
6744 + *
6745 + * @param  *Src                    source address
6746 + * @param  *Dst                    destination address
6747 + * @param  TransCount      data length
6748 + * @param  PcmNo           PCM channel
6749 + * @param  TxNo                    PCM Tx number
6750 + * @param  *DoneIntCallback  callback func when transcation is done
6751 + * @param  *UnMaskIntCallback  callback func when ch mask field is incorrect
6752 + * @retval 1               success
6753 + * @retval 0               fail
6754 + */
6755 +int GdmaPcmTx(
6756 +       uint32_t Src,
6757 +       uint32_t Dst,
6758 +       uint8_t PcmNo,
6759 +       uint8_t TxNo,
6760 +       uint16_t TransCount,
6761 +       void (*DoneIntCallback)(uint32_t data),
6762 +       void (*UnMaskIntCallback)(uint32_t data)
6763 +       )
6764 +{
6765 +    GdmaReqEntry Entry;
6766 +
6767 +       #if defined (CONFIG_MIPS)
6768 +    Entry.Src= (Src & 0x1FFFFFFF);
6769 +    Entry.Dst= (Dst & 0x1FFFFFFF);
6770 +  #else
6771 +    Entry.Src= Src;
6772 +    Entry.Dst= Dst;
6773 +  #endif
6774 +    Entry.TransCount = TransCount;
6775 +    Entry.SrcBurstMode=INC_MODE;
6776 +    Entry.DstBurstMode=FIX_MODE;
6777 +    Entry.BurstSize=BUSTER_SIZE_4B;
6778 +    Entry.SrcReqNum=DMA_MEM_REQ;
6779 +    Entry.DoneIntCallback=DoneIntCallback;
6780 +    Entry.UnMaskIntCallback=UnMaskIntCallback;
6781 +    Entry.SoftMode=0; //Hardware Mode
6782 +    Entry.ChMask=1;
6783 +    Entry.CoherentIntEbl=0;
6784 +
6785 +       if(TxNo > 2) {
6786 +        GDMA_PRINT("PCM Tx Number %x is invalid\n", TxNo);
6787 +               return 0;
6788 +       }
6789 +       switch(PcmNo)
6790 +       {
6791 +       case 0:
6792 +               Entry.DstReqNum=DMA_PCM_TX0_REQ;
6793 +               break;
6794 +       case 1:
6795 +               Entry.DstReqNum=DMA_PCM_TX1_REQ;
6796 +               break;
6797 +#if defined(CONFIG_RALINK_MT7620) || defined (CONFIG_RALINK_MT7621) || defined (CONFIG_RALINK_MT7628) || defined (CONFIG_ARCH_MT7623)
6798 +       case 2:
6799 +               Entry.DstReqNum=DMA_PCM_TX2_REQ;
6800 +               break;
6801 +       case 3:
6802 +               Entry.DstReqNum=DMA_PCM_TX3_REQ;
6803 +               break;
6804 +#endif
6805 +       default:
6806 +               GDMA_PRINT("PCM Channel %x is invalid\n", PcmNo);
6807 +               return 0;
6808 +       }
6809 +       Entry.ChNum=GDMA_PCM_TX(PcmNo,TxNo);
6810 +       Entry.NextUnMaskCh=GDMA_PCM_TX(PcmNo,1-TxNo);
6811 +
6812 +    return _GdmaReqEntryIns(&Entry);
6813 +
6814 +}
6815 +
6816 +
6817 +/**
6818 + * @brief Start GDMA transaction for memory to memory copy
6819 + *
6820 + * @param  *Src                    source address
6821 + * @param  *Dst                    destination address
6822 + * @param  TransCount      data length
6823 + * @param  *DoneIntCallback  callback function when transcation is done
6824 + * @retval 1               success
6825 + * @retval 0               fail
6826 + */
6827 +int GdmaMem2Mem(
6828 +       uint32_t Src,
6829 +       uint32_t Dst,
6830 +       uint16_t TransCount,
6831 +       void (*DoneIntCallback)(uint32_t data)
6832 +       )
6833 +
6834 +{
6835 +
6836 +    GdmaReqEntry Entry;
6837 +       #if defined (CONFIG_MIPS)
6838 +    Entry.Src= (Src & 0x1FFFFFFF);
6839 +    Entry.Dst= (Dst & 0x1FFFFFFF);
6840 +  #else
6841 +    Entry.Src= Src;
6842 +    Entry.Dst= Dst;
6843 +  #endif
6844 +
6845 +    //Entry.Src= virt_to_phys(Src);
6846 +    //Entry.Dst= virt_to_phys(Dst);
6847 +
6848 +
6849 +
6850 +    Entry.TransCount = TransCount;
6851 +    Entry.SrcBurstMode=INC_MODE;
6852 +    Entry.DstBurstMode=INC_MODE;
6853 +    Entry.BurstSize=BUSTER_SIZE_64B;
6854 +    Entry.SrcReqNum=DMA_MEM_REQ;
6855 +    Entry.DstReqNum=DMA_MEM_REQ;
6856 +    Entry.DoneIntCallback=DoneIntCallback;
6857 +    Entry.UnMaskIntCallback=NULL;
6858 +    Entry.SoftMode=1;
6859 +    Entry.ChMask=0;
6860 +
6861 +    Entry.CoherentIntEbl=1;
6862 +
6863 +    //No reserved channel for Memory to Memory GDMA,
6864 +    //get free channel on demand
6865 +    if(!_GdmaGetFreeCh(&Entry.ChNum)) {
6866 +                       GDMA_PRINT("GDMA Channels are all busy\n");
6867 +                       return 0;
6868 +    }
6869 +
6870 +
6871 +    //set next channel to their own channel
6872 +    //to disable chain feature
6873 +    Entry.NextUnMaskCh= Entry.ChNum;
6874 +      //printk ("ChNum = %d\n", Entry.ChNum);
6875 +    //set next channel to another channel
6876 +    //to enable chain feature
6877 +    //Entry.NextUnMaskCh= (Entry.ChNum+1) % MAX_GDMA_CHANNEL;
6878 +
6879 +    return _GdmaReqEntryIns(&Entry);
6880 +
6881 +
6882 +}
6883 +
6884 +/**
6885 + * @brief GDMA interrupt handler
6886 + *
6887 + * When GDMA transcation is done, call related handler
6888 + * to do the remain job.
6889 + *
6890 + */
6891 +irqreturn_t GdmaIrqHandler(
6892 +       int irq,
6893 +       void *irqaction
6894 +       )
6895 +{
6896 +
6897 +    u32 Ch=0;
6898 +    unsigned long flags;
6899 +#if defined (CONFIG_RALINK_RT3052)
6900 +    u32 GdmaUnMaskStatus=GDMA_READ_REG(RALINK_GDMAISTS) & 0xFF0000;
6901 +    u32 GdmaDoneStatus=GDMA_READ_REG(RALINK_GDMAISTS) & 0xFF;
6902 +#elif defined (CONFIG_RALINK_RT3883) || defined (CONFIG_RALINK_RT3352) || defined (CONFIG_RALINK_RT5350) || defined (CONFIG_RALINK_RT6855) || defined (CONFIG_RALINK_RT6855A) || defined (CONFIG_RALINK_MT7620)  ||  defined (CONFIG_RALINK_MT7621) || defined (CONFIG_RALINK_MT7628) || defined (CONFIG_ARCH_MT7623)
6903 +    u32 GdmaUnMaskStatus=GDMA_READ_REG(RALINK_GDMA_UNMASKINT);
6904 +    u32 GdmaDoneStatus=GDMA_READ_REG(RALINK_GDMA_DONEINT);
6905 +#endif
6906 +    //printk("********GDMA Interrupt*******************\n");
6907 +
6908 +    //GDMA_PRINT("========================================\n");
6909 +    //GDMA_PRINT("GdmaUnMask Interrupt=%x\n",GdmaUnMaskStatus);
6910 +    //GDMA_PRINT("GdmaDone Interrupt=%x\n",GdmaDoneStatus);
6911 +    //GDMA_PRINT("========================================\n");
6912 +
6913 +    spin_lock_irqsave(&gdma_int_lock, flags);
6914 +
6915 +    //write 1 clear
6916 +#if defined (CONFIG_RALINK_RT3052)
6917 +    GDMA_WRITE_REG(RALINK_GDMAISTS, GdmaUnMaskStatus);
6918 +#elif defined (CONFIG_RALINK_RT3883) || defined (CONFIG_RALINK_RT3352) || defined (CONFIG_RALINK_RT5350) || defined (CONFIG_RALINK_RT6855) || defined (CONFIG_RALINK_RT6855A) || defined (CONFIG_RALINK_MT7620)  ||  defined (CONFIG_RALINK_MT7621) || defined (CONFIG_RALINK_MT7628) || defined (CONFIG_ARCH_MT7623)
6919 +    GDMA_WRITE_REG(RALINK_GDMA_UNMASKINT, GdmaUnMaskStatus);
6920 +#endif
6921 +
6922 +    //UnMask error
6923 +    for(Ch=0;Ch<MAX_GDMA_CHANNEL;Ch++) {
6924 +
6925 +       if(GdmaUnMaskStatus & (0x1 << (UNMASK_INT_STATUS(Ch))) ) {
6926 +           if(GdmaUnMaskIntCallback[Ch] != NULL) {
6927 +               GdmaUnMaskIntCallback[Ch](Ch);
6928 +             // printk("GdmaUnMaskIntCallback \n");
6929 +           }
6930 +       }
6931 +     }
6932 +
6933 +    //write 1 clear
6934 +#if defined (CONFIG_RALINK_RT3052)
6935 +     GDMA_WRITE_REG(RALINK_GDMAISTS, GdmaDoneStatus);
6936 +#elif defined (CONFIG_RALINK_RT3883) || defined (CONFIG_RALINK_RT3352) || defined (CONFIG_RALINK_RT5350) || defined (CONFIG_RALINK_RT6855) || defined (CONFIG_RALINK_RT6855A) || defined (CONFIG_RALINK_MT7620)  ||  defined (CONFIG_RALINK_MT7621) || defined (CONFIG_RALINK_MT7628) || defined (CONFIG_ARCH_MT7623)
6937 +     GDMA_WRITE_REG(RALINK_GDMA_DONEINT, GdmaDoneStatus);
6938 +#endif
6939 +
6940 +     //printk("interrupt status = %x \n", GdmaDoneStatus);
6941 +     //processing done
6942 +     for(Ch=0;Ch<MAX_GDMA_CHANNEL;Ch++) {
6943 +                       if(GdmaDoneStatus & (0x1<<Ch)) {
6944 +               if(GdmaDoneIntCallback[Ch] != NULL) {
6945 +                       //printk("*************Interrupt Ch=%d***********\n", Ch);
6946 +                                       GdmaDoneIntCallback[Ch](Ch);
6947 +               }
6948 +                       }
6949 +    }
6950 +
6951 +//printk("interrupt status clear = %x \n", GDMA_READ_REG(RALINK_GDMA_DONEINT));
6952 +    spin_unlock_irqrestore(&gdma_int_lock, flags);
6953 +
6954 +    return IRQ_HANDLED;
6955 +
6956 +}
6957 +
6958 +static int RalinkGdmaInit(void)
6959 +{
6960 +
6961 +    uint32_t Ret=0;
6962 +    uint32_t val = 0;
6963 +    printk("Enable Ralink GDMA Controller Module \n");
6964 +#if defined (CONFIG_RALINK_RT3883) || defined (CONFIG_RALINK_RT3352) || defined (CONFIG_RALINK_RT5350) || defined (CONFIG_RALINK_RT6855) || defined (CONFIG_RALINK_RT6855A) || defined (CONFIG_RALINK_MT7620)  ||  defined (CONFIG_RALINK_MT7621) || defined (CONFIG_RALINK_MT7628) || defined (CONFIG_ARCH_MT7623)
6965 +    printk("GDMA IP Version=%d\n", GET_GDMA_IP_VER);
6966 +#endif
6967 +spin_lock_init(&gdma_int_lock);
6968 +spin_lock_init(&gdma_lock);
6969 +//spin_lock_init(&gdma_lock_mem);
6970 +
6971 +#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,35)
6972 +       #if defined (CONFIG_MIPS)
6973 +           Ret = request_irq(SURFBOARDINT_DMA, GdmaIrqHandler, \
6974 +                   IRQF_DISABLED, "Ralink_DMA", NULL);
6975 +       #else
6976 +           Ret = request_irq(SURFBOARDINT_DMA, GdmaIrqHandler, \
6977 +                   IRQF_TRIGGER_LOW, "Ralink_DMA", NULL);
6978 +       #endif
6979 +#else
6980 +    Ret = request_irq(SURFBOARDINT_DMA, GdmaIrqHandler, \
6981 +           SA_INTERRUPT, "Ralink_DMA", NULL);
6982 +#endif
6983 +
6984 +/*
6985 +    Ret = request_irq(131, GdmaIrqHandler, \
6986 +           IRQF_TRIGGER_LOW, "Ralink_DMA", NULL);
6987 +           */
6988 +    if(Ret){
6989 +       GDMA_PRINT("IRQ %d is not free.\n", SURFBOARDINT_DMA);
6990 +       return 1;
6991 +    }
6992 +
6993 +#if defined (CONFIG_MIPS)
6994 +    //Enable GDMA interrupt
6995 +    val = le32_to_cpu(*(volatile u32 *)(RALINK_REG_INTENA));
6996 +    val |= RALINK_INTCTL_DMA;
6997 +    GDMA_WRITE_REG(RALINK_REG_INTENA, val);
6998 +#endif
6999 +
7000 +    //Channel0~Channel7 are round-robin
7001 +#if defined (CONFIG_RALINK_RT3052)
7002 +    GDMA_WRITE_REG(RALINK_GDMAGCT, 0x01);
7003 +#elif defined (CONFIG_RALINK_RT3883) || defined (CONFIG_RALINK_RT3352) || defined (CONFIG_RALINK_RT5350) || defined (CONFIG_RALINK_RT6855) || defined (CONFIG_RALINK_RT6855A) || defined (CONFIG_RALINK_MT7620)  ||  defined (CONFIG_RALINK_MT7621) || defined (CONFIG_RALINK_MT7628) || defined (CONFIG_ARCH_MT7623)
7004 +    GDMA_WRITE_REG(RALINK_GDMA_GCT, 0x01);
7005 +#else
7006 +#error Please Choose System Type
7007 +#endif
7008 +
7009 +    return 0;
7010 +}
7011 +
7012 +static void __exit RalinkGdmaExit(void)
7013 +{
7014 +
7015 +    printk("Disable Ralink GDMA Controller Module\n");
7016 +#if defined (CONFIG_MIPS)
7017 +    //Disable GDMA interrupt
7018 +    GDMA_WRITE_REG(RALINK_REG_INTDIS, RALINK_INTCTL_DMA);
7019 +#endif
7020 +    free_irq(SURFBOARDINT_DMA, NULL);
7021 +}
7022 +
7023 +module_init(RalinkGdmaInit);
7024 +module_exit(RalinkGdmaExit);
7025 +
7026 +EXPORT_SYMBOL(GdmaI2sRx);
7027 +EXPORT_SYMBOL(GdmaI2sTx);
7028 +EXPORT_SYMBOL(GdmaPcmRx);
7029 +EXPORT_SYMBOL(GdmaPcmTx);
7030 +#if defined(CONFIG_RALINK_MT7620) || defined (CONFIG_RALINK_MT7621) || defined (CONFIG_RALINK_MT7628) || defined (CONFIG_ARCH_MT7623)
7031 +EXPORT_SYMBOL(GdmaSpiRx);
7032 +EXPORT_SYMBOL(GdmaSpiTx);
7033 +#endif
7034 +EXPORT_SYMBOL(GdmaMem2Mem);
7035 +EXPORT_SYMBOL(GdmaReqQuickIns);
7036 +EXPORT_SYMBOL(GdmaMaskChannel);
7037 +EXPORT_SYMBOL(GdmaUnMaskChannel);
7038 +
7039 +
7040 +MODULE_DESCRIPTION("Ralink SoC GDMA Controller API Module");
7041 +MODULE_AUTHOR("Steven Liu <steven_liu@ralinktech.com.tw>");
7042 +MODULE_LICENSE("GPL");
7043 +MODULE_VERSION(MOD_VERSION);
7044 --- /dev/null
7045 +++ b/sound/soc/mtk/ralink_gdma.h
7046 @@ -0,0 +1,326 @@
7047 +/*
7048 + ***************************************************************************
7049 + * Ralink Tech Inc.
7050 + * 5F., No.36, Taiyuan St., Jhubei City,
7051 + * Hsinchu County 302,
7052 + * Taiwan, R.O.C.
7053 + *
7054 + * (c) Copyright, Ralink Technology, Inc.
7055 + *
7056 + *  This program is free software; you can redistribute  it and/or modify it
7057 + *  under  the terms of  the GNU General  Public License as published by the
7058 + *  Free Software Foundation;  either version 2 of the  License, or (at your
7059 + *  option) any later version.
7060 + *
7061 + *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
7062 + *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
7063 + *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
7064 + *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
7065 + *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
7066 + *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
7067 + *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
7068 + *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
7069 + *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
7070 + *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
7071 + *
7072 + *  You should have received a copy of the  GNU General Public License along
7073 + *  with this program; if not, write  to the Free Software Foundation, Inc.,
7074 + *  675 Mass Ave, Cambridge, MA 02139, USA.
7075 + *
7076 + *
7077 + ***************************************************************************
7078 + */
7079 +
7080 +#ifndef __RALINK_DMA_CTRL_H__
7081 +#define __RALINK_DMA_CTRL_H__
7082 +
7083 +//#include <asm/rt2880/rt_mmap.h>
7084 +
7085 +/*
7086 + * DEFINITIONS AND MACROS
7087 + */
7088 +#define MOD_VERSION                    "0.4"
7089 +
7090 +#if defined (CONFIG_RALINK_MT7621) || defined (CONFIG_ARCH_MT7623)
7091 +#define MAX_GDMA_CHANNEL               16
7092 +#elif defined (CONFIG_RALINK_RT3052)
7093 +#define MAX_GDMA_CHANNEL               8
7094 +#elif defined (CONFIG_RALINK_RT3883) || defined (CONFIG_RALINK_RT3352) || defined (CONFIG_RALINK_RT5350) || defined (CONFIG_RALINK_RT6855) || defined (CONFIG_RALINK_RT6855A) || defined (CONFIG_RALINK_MT7620) || defined (CONFIG_RALINK_MT7628)
7095 +#define MAX_GDMA_CHANNEL               16
7096 +#else
7097 +#error Please Choose System Type
7098 +#endif
7099 +
7100 +
7101 +#define RALINK_GDMA_CTRL_BASE          (RALINK_GDMA_BASE)
7102 +#if defined (CONFIG_RALINK_RT3052)
7103 +#define RALINK_GDMAISTS                        (RALINK_GDMA_BASE + 0x80)
7104 +#define RALINK_GDMAGCT                 (RALINK_GDMA_BASE + 0x88)
7105 +#elif defined (CONFIG_RALINK_RT3883) || defined (CONFIG_RALINK_RT3352) || defined (CONFIG_RALINK_RT5350) || defined (CONFIG_RALINK_RT6855) || defined (CONFIG_RALINK_RT6855A) || defined (CONFIG_RALINK_MT7620)  ||  defined (CONFIG_RALINK_MT7621) || defined (CONFIG_RALINK_MT7628) || defined (CONFIG_ARCH_MT7623)
7106 +#define RALINK_GDMA_UNMASKINT          (RALINK_GDMA_BASE + 0x200)
7107 +#define RALINK_GDMA_DONEINT            (RALINK_GDMA_BASE + 0x204)
7108 +#define RALINK_GDMA_GCT                        (RALINK_GDMA_BASE + 0x220)
7109 +#endif
7110 +
7111 +#define KSEG1                   0xa0000000
7112 +#define PHYS_TO_VIRT(x)         ((void *)((x) | KSEG1))
7113 +#define VIRT_TO_PHYS(x)         ((unsigned long)(x) & ~KSEG1)
7114 +
7115 +
7116 +
7117 +
7118 +#if defined (CONFIG_ARCH_MT7623)
7119 +#include <mach/sync_write.h>
7120 +#define GDMA_READ_REG(phys)            (*(volatile unsigned int *)((phys)))
7121 +#define GDMA_WRITE_REG(phys, val)      mt65xx_reg_sync_writel((val), (phys))
7122 +
7123 +#else
7124 +#define GDMA_READ_REG(addr)            (le32_to_cpu(*(volatile u32 *)(addr)))
7125 +#define GDMA_WRITE_REG(addr, val)      *((volatile uint32_t *)(addr)) = cpu_to_le32(val)
7126 +
7127 +
7128 +
7129 +#endif
7130 +
7131 +
7132 +#define GET_GDMA_IP_VER                        (GDMA_READ_REG(RALINK_GDMA_GCT) & 0x6) >> 1 //GDMA_GCT[2:1]
7133 +
7134 +#define RALINK_IRQ_ADDR                 RALINK_INTCL_BASE
7135 +#if defined (CONFIG_RALINK_MT7621) || defined (CONFIG_ARCH_MT7628)
7136 +#define RALINK_REG_INTENA               (RALINK_IRQ_ADDR + 0x80)
7137 +#define RALINK_REG_INTDIS               (RALINK_IRQ_ADDR + 0x78)
7138 +#else
7139 +#define RALINK_REG_INTENA               (RALINK_IRQ_ADDR + 0x34)
7140 +#define RALINK_REG_INTDIS               (RALINK_IRQ_ADDR + 0x38)
7141 +#endif
7142 +
7143 +/*
7144 + * 12bytes=GDMA Channel n Source Address(4) +
7145 + *         GDMA Channel n Destination Address(4) +
7146 + *         GDMA Channel n Control Register(4)
7147 + *
7148 + */
7149 +#define GDMA_SRC_REG(ch)               (RALINK_GDMA_BASE + ch*16)
7150 +#define GDMA_DST_REG(ch)               (GDMA_SRC_REG(ch) + 4)
7151 +#define GDMA_CTRL_REG(ch)              (GDMA_DST_REG(ch) + 4)
7152 +#define GDMA_CTRL_REG1(ch)             (GDMA_CTRL_REG(ch) + 4)
7153 +
7154 +//GDMA Interrupt Status Register
7155 +#if defined (CONFIG_RALINK_RT3052)
7156 +#define UNMASK_INT_STATUS(ch)           (ch+16)
7157 +#elif defined (CONFIG_RALINK_RT3883) || defined (CONFIG_RALINK_RT3352) || defined (CONFIG_RALINK_RT5350) || defined (CONFIG_RALINK_RT6855) || defined (CONFIG_RALINK_RT6855A) || defined (CONFIG_RALINK_MT7620)  ||  defined (CONFIG_RALINK_MT7621) || defined (CONFIG_RALINK_MT7628) || defined (CONFIG_ARCH_MT7623)
7158 +#define UNMASK_INT_STATUS(ch)           (ch)
7159 +#endif
7160 +#define TXDONE_INT_STATUS(ch)           (ch)
7161 +
7162 +//Control Reg0
7163 +#define MODE_SEL_OFFSET                        0
7164 +#define CH_EBL_OFFSET                  1
7165 +#define CH_DONEINT_EBL_OFFSET          2
7166 +#define BRST_SIZE_OFFSET               3
7167 +#define DST_BRST_MODE_OFFSET           6
7168 +#define SRC_BRST_MODE_OFFSET           7
7169 +#define TRANS_CNT_OFFSET               16
7170 +
7171 +//Control Reg1
7172 +#if defined (CONFIG_RALINK_RT3052)
7173 +#define CH_UNMASKINT_EBL_OFFSET                4
7174 +#define NEXT_UNMASK_CH_OFFSET          1
7175 +#elif defined (CONFIG_RALINK_RT3883) || defined (CONFIG_RALINK_RT3352) || defined (CONFIG_RALINK_RT5350) || defined (CONFIG_RALINK_RT6855) || defined (CONFIG_RALINK_RT6855A) || defined (CONFIG_RALINK_MT7620)  ||  defined (CONFIG_RALINK_MT7621) || defined (CONFIG_RALINK_MT7628) || defined (CONFIG_ARCH_MT7623)
7176 +#define CH_UNMASKINT_EBL_OFFSET                1
7177 +#define NEXT_UNMASK_CH_OFFSET          3
7178 +#endif
7179 +#define COHERENT_INT_EBL_OFFSET                2
7180 +#define CH_MASK_OFFSET                 0
7181 +
7182 +
7183 +#if defined (CONFIG_RALINK_RT3052)
7184 +//Control Reg0
7185 +#define DST_DMA_REQ_OFFSET             8
7186 +#define SRC_DMA_REQ_OFFSET             12
7187 +#elif defined (CONFIG_RALINK_RT3883) || defined (CONFIG_RALINK_RT3352) || defined (CONFIG_RALINK_RT5350) || defined (CONFIG_RALINK_RT6855) || defined (CONFIG_RALINK_RT6855A) || defined (CONFIG_RALINK_MT7620)  ||  defined (CONFIG_RALINK_MT7621) || defined (CONFIG_RALINK_MT7628) || defined (CONFIG_ARCH_MT7623)
7188 +//Control Reg1
7189 +#define DST_DMA_REQ_OFFSET             8
7190 +#define SRC_DMA_REQ_OFFSET             16
7191 +#endif
7192 +
7193 +#define GDMA_PCM0_RX0                  0
7194 +#define GDMA_PCM0_RX1                  1
7195 +#define GDMA_PCM0_TX0                  2
7196 +#define GDMA_PCM0_TX1                  3
7197 +
7198 +#define GDMA_PCM1_RX0                  4
7199 +#define GDMA_PCM1_RX1                  5
7200 +#define GDMA_PCM1_TX0                  6
7201 +#define GDMA_PCM1_TX1                  7
7202 +
7203 +#define GDMA_PCM_RX(i,j)               (0+((i)<<2)+j)
7204 +#define GDMA_PCM_TX(i,j)        (2+((i)<<2)+j)
7205 +
7206 +#define GDMA_I2S_TX0                   4
7207 +#define GDMA_I2S_TX1                   5
7208 +#define GDMA_I2S_RX0                   6
7209 +#define GDMA_I2S_RX1                   7
7210 +
7211 +#define GDMA_SPI_TX       13
7212 +#define GDMA_SPI_RX       12
7213 +
7214 +
7215 +//#define GDMA_DEBUG
7216 +#ifdef GDMA_DEBUG
7217 +#define GDMA_PRINT(fmt, args...) printk(KERN_INFO "GDMA: " fmt, ## args)
7218 +#else
7219 +#define GDMA_PRINT(fmt, args...) { }
7220 +#endif
7221 +
7222 +/*
7223 + * TYPEDEFS AND STRUCTURES
7224 + */
7225 +
7226 +enum GdmaBusterMode {
7227 +       INC_MODE=0,
7228 +       FIX_MODE=1
7229 +};
7230 +
7231 +enum GdmaBusterSize {
7232 +       BUSTER_SIZE_4B=0,       /* 1 transfer */
7233 +       BUSTER_SIZE_8B=1,       /* 2 transfer */
7234 +       BUSTER_SIZE_16B=2,      /* 4 transfer */
7235 +       BUSTER_SIZE_32B=3,      /* 8 transfer */
7236 +       BUSTER_SIZE_64B=4       /* 16 transfer */
7237 +};
7238 +
7239 +enum GdmaDmaReqNum {
7240 +#if defined (CONFIG_RALINK_RT3052)
7241 +       DMA_REQ0=0,
7242 +       DMA_NAND_REQ=1,
7243 +       DMA_I2S_TX_REQ=2,
7244 +       DMA_PCM_RX0_REQ=3,
7245 +       DMA_PCM_RX1_REQ=4,
7246 +       DMA_PCM_TX0_REQ=5,
7247 +       DMA_PCM_TX1_REQ=6,
7248 +       DMA_REG7=7,
7249 +       DMA_MEM_REQ=8
7250 +#elif defined (CONFIG_RALINK_RT3883) || defined (CONFIG_RALINK_RT3352) || defined (CONFIG_RALINK_RT5350) || defined (CONFIG_RALINK_RT6855)
7251 +       DMA_REQ0=0,
7252 +       DMA_NAND_REQ=1,
7253 +       DMA_I2S_TX_REQ=2,
7254 +       DMA_I2S_RX_REQ=3,
7255 +       DMA_PCM_RX0_REQ=4,
7256 +       DMA_PCM_RX1_REQ=5,
7257 +       DMA_PCM_TX0_REQ=6,
7258 +       DMA_PCM_TX1_REQ=7,
7259 +       DMA_CODEC0_REQ8=8,
7260 +       DMA_CODEC1_REQ9=9,
7261 +       DMA_REQ10=10,
7262 +       DMA_REQ11=11,
7263 +       DMA_REQ12=12,
7264 +       DMA_REQ13=13,
7265 +       DMA_REQ14=14,
7266 +       DMA_REQ15=15,
7267 +
7268 +       #if defined (CONFIG_RALINK_RT3883)
7269 +               DMA_MEM_REQ=16
7270 +       #elif defined (CONFIG_RALINK_RT3352) || defined (CONFIG_RALINK_RT5350) || defined (CONFIG_RALINK_RT6855)
7271 +               DMA_MEM_REQ=32
7272 +       #endif
7273 +
7274 +#elif defined(CONFIG_RALINK_MT7620) || defined (CONFIG_RALINK_MT7621) || defined (CONFIG_RALINK_MT7628) || defined (CONFIG_ARCH_MT7623)
7275 +       DMA_REQ0=0,
7276 +       DMA_NAND_REQ=1,
7277 +       DMA_I2S_TX_REQ=2,
7278 +       DMA_I2S_RX_REQ=3,
7279 +       DMA_PCM_RX0_REQ=4,
7280 +       DMA_PCM_RX1_REQ=5,
7281 +       DMA_PCM_TX0_REQ=6,
7282 +       DMA_PCM_TX1_REQ=7,
7283 +       DMA_PCM_RX2_REQ=8,
7284 +       DMA_PCM_RX3_REQ=9,
7285 +       DMA_PCM_TX2_REQ=10,
7286 +       DMA_PCM_TX3_REQ=11,
7287 +       DMA_SPI_RX_REQ=12,
7288 +       DMA_SPI_TX_REQ=13,
7289 +       DMA_MEM_REQ=32
7290 +
7291 +#elif defined (CONFIG_RALINK_RT6855A)
7292 +       DMA_NAND_REQ=0,
7293 +       DMA_I2S_TX_REQ=1,
7294 +       DMA_I2S_RX_REQ=2,
7295 +       DMA_REQ0=3,
7296 +       DMA_PCM_RX0_REQ=4,
7297 +       DMA_PCM_RX1_REQ=5,
7298 +       DMA_PCM_TX0_REQ=6,
7299 +       DMA_PCM_TX1_REQ=7,
7300 +       DMA_CODEC0_REQ8=8,
7301 +       DMA_CODEC1_REQ9=9,
7302 +       DMA_REQ10=10,
7303 +       DMA_REQ11=11,
7304 +       DMA_REQ12=12,
7305 +       DMA_REQ13=13,
7306 +       DMA_REQ14=14,
7307 +       DMA_REQ15=15,
7308 +       DMA_MEM_REQ=32
7309 +#else
7310 +#error Please Choose System Type
7311 +#endif
7312 +};
7313 +
7314 +
7315 +
7316 +typedef struct {
7317 +       uint32_t Src;
7318 +       uint32_t Dst;
7319 +       uint16_t TransCount;
7320 +       uint8_t  SoftMode;
7321 +       uint8_t  NextUnMaskCh;
7322 +       uint8_t  ChMask;
7323 +       uint8_t  CoherentIntEbl;
7324 +       uint32_t  ChNum;
7325 +       enum GdmaDmaReqNum SrcReqNum;
7326 +       enum GdmaDmaReqNum DstReqNum;
7327 +       enum GdmaBusterMode SrcBurstMode;
7328 +       enum GdmaBusterMode DstBurstMode;
7329 +       enum GdmaBusterSize BurstSize;
7330 +       void (*DoneIntCallback)(uint32_t);
7331 +       void (*UnMaskIntCallback)(uint32_t);
7332 +} GdmaReqEntry;
7333 +
7334 +/*
7335 + * EXPORT FUNCTION
7336 + */
7337 +int GdmaI2sTx(uint32_t Src, uint32_t Dst, uint8_t TxNo, uint16_t TransCount,
7338 +               void (*DoneIntCallback)(uint32_t data),
7339 +               void (*UnMaskIntCallback)(uint32_t data));
7340 +
7341 +int GdmaI2sRx(uint32_t Src, uint32_t Dst, uint8_t RxNo, uint16_t TransCount,
7342 +               void (*DoneIntCallback)(uint32_t data),
7343 +               void (*UnMaskIntCallback)(uint32_t data));
7344 +
7345 +int GdmaPcmRx(uint32_t Src, uint32_t Dst, uint8_t PcmNo, uint8_t RxNo, uint16_t TransCount,
7346 +               void (*DoneIntCallback)(uint32_t data),
7347 +               void (*UnMaskIntCallback)(uint32_t data));
7348 +
7349 +int GdmaPcmTx(uint32_t Src, uint32_t Dst, uint8_t PcmNo, uint8_t TxNo, uint16_t TransCount,
7350 +               void (*DoneIntCallback)(uint32_t data),
7351 +               void (*UnMaskIntCallback)(uint32_t data));
7352 +
7353 +int GdmaSpiTx(uint32_t Src, uint32_t Dst, uint16_t TransCount,
7354 +       void (*DoneIntCallback)(uint32_t data),
7355 +       void (*UnMaskIntCallback)(uint32_t data));
7356 +
7357 +int GdmaSpiRx(uint32_t Src, uint32_t Dst, uint16_t TransCount,
7358 +       void (*DoneIntCallback)(uint32_t data),
7359 +       void (*UnMaskIntCallback)(uint32_t data));
7360 +
7361 +
7362 +int GdmaMem2Mem(uint32_t Src, uint32_t Dst, uint16_t TransCount,
7363 +               void (*DoneIntCallback)(uint32_t data));
7364 +
7365 +int GdmaMaskChannel(uint32_t ChNum);
7366 +
7367 +int GdmaUnMaskChannel(uint32_t ChNum);
7368 +
7369 +int GdmaReqQuickIns(uint32_t ChNum);
7370 +
7371 +
7372 +#endif
7373 --- a/sound/soc/soc-core.c
7374 +++ b/sound/soc/soc-core.c
7375 @@ -1851,7 +1851,8 @@ static int soc_probe(struct platform_dev
7376         /* Bodge while we unpick instantiation */
7377         card->dev = &pdev->dev;
7378
7379 -       return snd_soc_register_card(card);
7380 +       snd_soc_register_card(card);
7381 +       return 0;
7382  }
7383
7384  static int soc_cleanup_card_resources(struct snd_soc_card *card)
7385 --- /dev/null
7386 +++ b/sound/soc/mtk/i2s_debug.c
7387 @@ -0,0 +1,698 @@
7388 +#include <linux/init.h>
7389 +#include <linux/version.h>
7390 +#include <linux/module.h>
7391 +#include <linux/kernel.h> /* printk() */
7392 +#include "i2s_ctrl.h"
7393 +#include <linux/delay.h>
7394 +#include <linux/jiffies.h>
7395 +#include <linux/random.h>
7396 +#include <linux/slab.h>
7397 +#include <asm/uaccess.h> /* copy_from/to_user */
7398 +
7399 +#if defined(CONFIG_SND_RALINK_SOC)
7400 +#include <sound/soc/mtk/mtk_audio_device.h>
7401 +#endif
7402 +
7403 +#if defined(CONFIG_I2S_WM8750)
7404 +#include "../codec/i2c_wm8750.h"
7405 +#endif
7406 +#if defined(CONFIG_I2S_WM8751)
7407 +#include "../codec/i2c_wm8751.h"
7408 +#endif
7409 +#if defined(CONFIG_I2S_WM8960)
7410 +#include "i2c_wm8960.h"
7411 +#endif
7412 +
7413 +
7414 +//#define INTERNAL_LOOPBACK_DEBUG
7415 +
7416 +extern unsigned long i2s_codec_12p288Mhz[11];
7417 +extern unsigned long i2s_codec_12Mhz[11];
7418 +#if defined(CONFIG_RALINK_MT7628) || defined(CONFIG_ARCH_MT7623)
7419 +extern unsigned long i2s_inclk_int_16bit[13];
7420 +extern unsigned long i2s_inclk_comp_16bit[13];
7421 +extern unsigned long i2s_inclk_int_24bit[13];
7422 +extern unsigned long i2s_inclk_comp_24bit[13];
7423 +#else
7424 +extern unsigned long i2s_inclk_int[11];
7425 +extern unsigned long i2s_inclk_comp[11];
7426 +#endif
7427 +extern int i2s_pll_config_mt7621(unsigned long index);
7428 +extern int i2s_pll_config_mt7623(unsigned long index);
7429 +
7430 +#if defined(CONFIG_I2S_WM8960) || defined(CONFIG_I2S_WM8750) || defined(CONFIG_I2S_WM8751)
7431 +extern void audiohw_loopback(int fsel);
7432 +extern void audiohw_bypass(void);
7433 +extern int audiohw_set_lineout_vol(int Aout, int vol_l, int vol_r);
7434 +extern int audiohw_set_linein_vol(int vol_l, int vol_r);
7435 +#endif
7436 +
7437 +#if defined(CONFIG_I2S_WM8960)
7438 +extern void audiohw_codec_exlbk(void);
7439 +#endif
7440 +
7441 +unsigned long txbuffer[512] = {
7442 +                               0x01020304, 0x05060708, 0x090a0b0c, 0x0d0e0f10, 0x11121314, 0x15161718, 0x191a1b1c, 0x1d1e1f20,
7443 +                               0x21222324, 0x25262728, 0x292a2b2c, 0x2d2e2f30, 0x31323334, 0x35363738, 0x393a3b3c, 0x3d3e3f40,
7444 +                               0x41424344, 0x45464748, 0x494a4b4c, 0x4d4e4f50, 0x51525354, 0x55565758, 0x595a5b5c, 0x5d5e5f60,
7445 +                               0x61626364, 0x65666768, 0x696a6b6c, 0x6d6e6f70, 0x71727374, 0x75767778, 0x797a7b7c, 0x7d7e7f80,
7446 +                               0x81828384, 0x85868788, 0x898a8b8c, 0x8d8e8f90, 0x91929394, 0x95969798, 0x999a9b9c, 0x9d9e9fa0,
7447 +                               0xa1a2a3a4, 0xa5a6a7a8, 0xa9aaabac, 0xadaeafb0, 0xb1b2b3b4, 0xb5b6b7b8, 0xb9babbbc, 0xbdbebfc0,
7448 +                               0xc1c2c3c4, 0xc5c6c7c8, 0xc9cacbcc, 0xcdcecfd0, 0xd1d2d3d4, 0xd5d6d7d8, 0xd9dadbdc, 0xdddedfe0,
7449 +                               0xe1e2e3e4, 0xe5e6e7e8, 0xe9eaebec, 0xedeeeff0, 0xf1f2f3f4, 0xf5f6f7f8, 0xf9fafbfc, 0xfdfeff00, //round 1
7450 +0x01020304, 0x05060708, 0x090a0b0c, 0x0d0e0f10, 0x11121314, 0x15161718, 0x191a1b1c, 0x1d1e1f20,
7451 +                               0x21222324, 0x25262728, 0x292a2b2c, 0x2d2e2f30, 0x31323334, 0x35363738, 0x393a3b3c, 0x3d3e3f40,
7452 +                               0x41424344, 0x45464748, 0x494a4b4c, 0x4d4e4f50, 0x51525354, 0x55565758, 0x595a5b5c, 0x5d5e5f60,
7453 +                               0x61626364, 0x65666768, 0x696a6b6c, 0x6d6e6f70, 0x71727374, 0x75767778, 0x797a7b7c, 0x7d7e7f80,
7454 +                               0x81828384, 0x85868788, 0x898a8b8c, 0x8d8e8f90, 0x91929394, 0x95969798, 0x999a9b9c, 0x9d9e9fa0,
7455 +                               0xa1a2a3a4, 0xa5a6a7a8, 0xa9aaabac, 0xadaeafb0, 0xb1b2b3b4, 0xb5b6b7b8, 0xb9babbbc, 0xbdbebfc0,
7456 +                               0xc1c2c3c4, 0xc5c6c7c8, 0xc9cacbcc, 0xcdcecfd0, 0xd1d2d3d4, 0xd5d6d7d8, 0xd9dadbdc, 0xdddedfe0,
7457 +                               0xe1e2e3e4, 0xe5e6e7e8, 0xe9eaebec, 0xedeeeff0, 0xf1f2f3f4, 0xf5f6f7f8, 0xf9fafbfc, 0xfdfeff00, //round 2
7458 +0x01020304, 0x05060708, 0x090a0b0c, 0x0d0e0f10, 0x11121314, 0x15161718, 0x191a1b1c, 0x1d1e1f20,
7459 +                               0x21222324, 0x25262728, 0x292a2b2c, 0x2d2e2f30, 0x31323334, 0x35363738, 0x393a3b3c, 0x3d3e3f40,
7460 +                               0x41424344, 0x45464748, 0x494a4b4c, 0x4d4e4f50, 0x51525354, 0x55565758, 0x595a5b5c, 0x5d5e5f60,
7461 +                               0x61626364, 0x65666768, 0x696a6b6c, 0x6d6e6f70, 0x71727374, 0x75767778, 0x797a7b7c, 0x7d7e7f80,
7462 +                               0x81828384, 0x85868788, 0x898a8b8c, 0x8d8e8f90, 0x91929394, 0x95969798, 0x999a9b9c, 0x9d9e9fa0,
7463 +                               0xa1a2a3a4, 0xa5a6a7a8, 0xa9aaabac, 0xadaeafb0, 0xb1b2b3b4, 0xb5b6b7b8, 0xb9babbbc, 0xbdbebfc0,
7464 +                               0xc1c2c3c4, 0xc5c6c7c8, 0xc9cacbcc, 0xcdcecfd0, 0xd1d2d3d4, 0xd5d6d7d8, 0xd9dadbdc, 0xdddedfe0,
7465 +                               0xe1e2e3e4, 0xe5e6e7e8, 0xe9eaebec, 0xedeeeff0, 0xf1f2f3f4, 0xf5f6f7f8, 0xf9fafbfc, 0xfdfeff00, //round 3
7466 +0x01020304, 0x05060708, 0x090a0b0c, 0x0d0e0f10, 0x11121314, 0x15161718, 0x191a1b1c, 0x1d1e1f20,
7467 +                               0x21222324, 0x25262728, 0x292a2b2c, 0x2d2e2f30, 0x31323334, 0x35363738, 0x393a3b3c, 0x3d3e3f40,
7468 +                               0x41424344, 0x45464748, 0x494a4b4c, 0x4d4e4f50, 0x51525354, 0x55565758, 0x595a5b5c, 0x5d5e5f60,
7469 +                               0x61626364, 0x65666768, 0x696a6b6c, 0x6d6e6f70, 0x71727374, 0x75767778, 0x797a7b7c, 0x7d7e7f80,
7470 +                               0x81828384, 0x85868788, 0x898a8b8c, 0x8d8e8f90, 0x91929394, 0x95969798, 0x999a9b9c, 0x9d9e9fa0,
7471 +                               0xa1a2a3a4, 0xa5a6a7a8, 0xa9aaabac, 0xadaeafb0, 0xb1b2b3b4, 0xb5b6b7b8, 0xb9babbbc, 0xbdbebfc0,
7472 +                               0xc1c2c3c4, 0xc5c6c7c8, 0xc9cacbcc, 0xcdcecfd0, 0xd1d2d3d4, 0xd5d6d7d8, 0xd9dadbdc, 0xdddedfe0,
7473 +                               0xe1e2e3e4, 0xe5e6e7e8, 0xe9eaebec, 0xedeeeff0, 0xf1f2f3f4, 0xf5f6f7f8, 0xf9fafbfc, 0xfdfeff00, //round 4
7474 +0x01020304, 0x05060708, 0x090a0b0c, 0x0d0e0f10, 0x11121314, 0x15161718, 0x191a1b1c, 0x1d1e1f20,
7475 +                               0x21222324, 0x25262728, 0x292a2b2c, 0x2d2e2f30, 0x31323334, 0x35363738, 0x393a3b3c, 0x3d3e3f40,
7476 +                               0x41424344, 0x45464748, 0x494a4b4c, 0x4d4e4f50, 0x51525354, 0x55565758, 0x595a5b5c, 0x5d5e5f60,
7477 +                               0x61626364, 0x65666768, 0x696a6b6c, 0x6d6e6f70, 0x71727374, 0x75767778, 0x797a7b7c, 0x7d7e7f80,
7478 +                               0x81828384, 0x85868788, 0x898a8b8c, 0x8d8e8f90, 0x91929394, 0x95969798, 0x999a9b9c, 0x9d9e9fa0,
7479 +                               0xa1a2a3a4, 0xa5a6a7a8, 0xa9aaabac, 0xadaeafb0, 0xb1b2b3b4, 0xb5b6b7b8, 0xb9babbbc, 0xbdbebfc0,
7480 +                               0xc1c2c3c4, 0xc5c6c7c8, 0xc9cacbcc, 0xcdcecfd0, 0xd1d2d3d4, 0xd5d6d7d8, 0xd9dadbdc, 0xdddedfe0,
7481 +                               0xe1e2e3e4, 0xe5e6e7e8, 0xe9eaebec, 0xedeeeff0, 0xf1f2f3f4, 0xf5f6f7f8, 0xf9fafbfc, 0xfdfeff00, //round 5
7482 +0x01020304, 0x05060708, 0x090a0b0c, 0x0d0e0f10, 0x11121314, 0x15161718, 0x191a1b1c, 0x1d1e1f20,
7483 +                               0x21222324, 0x25262728, 0x292a2b2c, 0x2d2e2f30, 0x31323334, 0x35363738, 0x393a3b3c, 0x3d3e3f40,
7484 +                               0x41424344, 0x45464748, 0x494a4b4c, 0x4d4e4f50, 0x51525354, 0x55565758, 0x595a5b5c, 0x5d5e5f60,
7485 +                               0x61626364, 0x65666768, 0x696a6b6c, 0x6d6e6f70, 0x71727374, 0x75767778, 0x797a7b7c, 0x7d7e7f80,
7486 +                               0x81828384, 0x85868788, 0x898a8b8c, 0x8d8e8f90, 0x91929394, 0x95969798, 0x999a9b9c, 0x9d9e9fa0,
7487 +                               0xa1a2a3a4, 0xa5a6a7a8, 0xa9aaabac, 0xadaeafb0, 0xb1b2b3b4, 0xb5b6b7b8, 0xb9babbbc, 0xbdbebfc0,
7488 +                               0xc1c2c3c4, 0xc5c6c7c8, 0xc9cacbcc, 0xcdcecfd0, 0xd1d2d3d4, 0xd5d6d7d8, 0xd9dadbdc, 0xdddedfe0,
7489 +                               0xe1e2e3e4, 0xe5e6e7e8, 0xe9eaebec, 0xedeeeff0, 0xf1f2f3f4, 0xf5f6f7f8, 0xf9fafbfc, 0xfdfeff00, //round 6
7490 +0x01020304, 0x05060708, 0x090a0b0c, 0x0d0e0f10, 0x11121314, 0x15161718, 0x191a1b1c, 0x1d1e1f20,
7491 +                               0x21222324, 0x25262728, 0x292a2b2c, 0x2d2e2f30, 0x31323334, 0x35363738, 0x393a3b3c, 0x3d3e3f40,
7492 +                               0x41424344, 0x45464748, 0x494a4b4c, 0x4d4e4f50, 0x51525354, 0x55565758, 0x595a5b5c, 0x5d5e5f60,
7493 +                               0x61626364, 0x65666768, 0x696a6b6c, 0x6d6e6f70, 0x71727374, 0x75767778, 0x797a7b7c, 0x7d7e7f80,
7494 +                               0x81828384, 0x85868788, 0x898a8b8c, 0x8d8e8f90, 0x91929394, 0x95969798, 0x999a9b9c, 0x9d9e9fa0,
7495 +                               0xa1a2a3a4, 0xa5a6a7a8, 0xa9aaabac, 0xadaeafb0, 0xb1b2b3b4, 0xb5b6b7b8, 0xb9babbbc, 0xbdbebfc0,
7496 +                               0xc1c2c3c4, 0xc5c6c7c8, 0xc9cacbcc, 0xcdcecfd0, 0xd1d2d3d4, 0xd5d6d7d8, 0xd9dadbdc, 0xdddedfe0,
7497 +                               0xe1e2e3e4, 0xe5e6e7e8, 0xe9eaebec, 0xedeeeff0, 0xf1f2f3f4, 0xf5f6f7f8, 0xf9fafbfc, 0xfdfeff00, //round 7
7498 +0x01020304, 0x05060708, 0x090a0b0c, 0x0d0e0f10, 0x11121314, 0x15161718, 0x191a1b1c, 0x1d1e1f20,
7499 +                               0x21222324, 0x25262728, 0x292a2b2c, 0x2d2e2f30, 0x31323334, 0x35363738, 0x393a3b3c, 0x3d3e3f40,
7500 +                               0x41424344, 0x45464748, 0x494a4b4c, 0x4d4e4f50, 0x51525354, 0x55565758, 0x595a5b5c, 0x5d5e5f60,
7501 +                               0x61626364, 0x65666768, 0x696a6b6c, 0x6d6e6f70, 0x71727374, 0x75767778, 0x797a7b7c, 0x7d7e7f80,
7502 +                               0x81828384, 0x85868788, 0x898a8b8c, 0x8d8e8f90, 0x91929394, 0x95969798, 0x999a9b9c, 0x9d9e9fa0,
7503 +                               0xa1a2a3a4, 0xa5a6a7a8, 0xa9aaabac, 0xadaeafb0, 0xb1b2b3b4, 0xb5b6b7b8, 0xb9babbbc, 0xbdbebfc0,
7504 +                               0xc1c2c3c4, 0xc5c6c7c8, 0xc9cacbcc, 0xcdcecfd0, 0xd1d2d3d4, 0xd5d6d7d8, 0xd9dadbdc, 0xdddedfe0,
7505 +                               0xe1e2e3e4, 0xe5e6e7e8, 0xe9eaebec, 0xedeeeff0, 0xf1f2f3f4, 0xf5f6f7f8, 0xf9fafbfc, 0xfdfeff00  //round 8
7506 +                               };
7507 +
7508 +int i2s_debug_cmd(unsigned int cmd, unsigned long arg)
7509 +{
7510 +       unsigned long data, index;
7511 +       unsigned long *pTable;
7512 +       int i;
7513 +
7514 +       switch(cmd)
7515 +       {
7516 +               case I2S_DEBUG_CLKGEN:
7517 +                       MSG("I2S_DEBUG_CLKGEN\n");
7518 +#if defined(CONFIG_RALINK_RT3052)
7519 +                       *(volatile unsigned long*)(0xB0000060) = 0x00000016;
7520 +                       *(volatile unsigned long*)(0xB0000030) = 0x00009E00;
7521 +                       *(volatile unsigned long*)(0xB0000A00) = 0xC0000040;
7522 +#elif defined(CONFIG_RALINK_RT3350)
7523 +                       *(volatile unsigned long*)(0xB0000060) = 0x00000018;
7524 +                       *(volatile unsigned long*)(0xB000002C) = 0x00000100;
7525 +                       *(volatile unsigned long*)(0xB0000030) = 0x00009E00;
7526 +                       *(volatile unsigned long*)(0xB0000A00) = 0xC0000040;
7527 +#elif defined(CONFIG_RALINK_RT3883)
7528 +                       *(volatile unsigned long*)(0xB0000060) = 0x00000018;
7529 +                       *(volatile unsigned long*)(0xB000002C) = 0x00003000;
7530 +                       *(volatile unsigned long*)(0xB0000A00) = 0xC1104040;
7531 +                       *(volatile unsigned long*)(0xB0000A24) = 0x00000027;
7532 +                       *(volatile unsigned long*)(0xB0000A20) = 0x80000020;
7533 +#elif (defined(CONFIG_RALINK_RT3352)||defined(CONFIG_RALINK_RT5350)) || defined (CONFIG_RALINK_RT6855)
7534 +                       *(volatile unsigned long*)(0xB0000060) = 0x00000018;
7535 +                       *(volatile unsigned long*)(0xB000002C) = 0x00000300;
7536 +                       *(volatile unsigned long*)(0xB0000A00) = 0xC1104040;
7537 +                       *(volatile unsigned long*)(0xB0000A24) = 0x00000027;
7538 +                       *(volatile unsigned long*)(0xB0000A20) = 0x80000020;
7539 +#elif defined(CONFIG_RALINK_RT6855A)
7540 +                       *(volatile unsigned long*)(RALINK_SYSCTL_BASE+0x860) = 0x00008080;
7541 +                       *(volatile unsigned long*)(RALINK_SYSCTL_BASE+0x82C) = 0x00000300;
7542 +                       *(volatile unsigned long*)(RALINK_I2S_BASE+0x00) = 0xC1104040;
7543 +                       *(volatile unsigned long*)(RALINK_I2S_BASE+0x24) = 0x00000027;
7544 +                       *(volatile unsigned long*)(RALINK_I2S_BASE+0x20) = 0x80000020;
7545 +#else
7546 +//#error "I2S debug mode not support this Chip"
7547 +#endif
7548 +                       break;
7549 +               case I2S_DEBUG_INLBK:
7550 +                       MSG("I2S_DEBUG_INLBK\n");
7551 +#if defined(CONFIG_RALINK_MT7621)
7552 +                        switch(96000)
7553 +                        {
7554 +                                case 8000:
7555 +                                        index = 0;
7556 +                                        break;
7557 +                                case 11025:
7558 +                                        index = 1;
7559 +                                        break;
7560 +                                case 12000:
7561 +                                        index = 2;
7562 +                                        break;
7563 +                                case 16000:
7564 +                                        index = 3;
7565 +                                        break;
7566 +                                case 22050:
7567 +                                        index = 4;
7568 +                                        break;
7569 +                                case 24000:
7570 +                                        index = 5;
7571 +                                        break;
7572 +                                case 32000:
7573 +                                        index = 6;
7574 +                                        break;
7575 +                                case 44100:
7576 +                                        index = 7;
7577 +                                        break;
7578 +                                case 48000:
7579 +                                        index = 8;
7580 +                                        break;
7581 +                                case 88200:
7582 +                                        index = 9;
7583 +                                        break;
7584 +                                case 96000:
7585 +                                        index = 10;
7586 +                                        break;
7587 +                               case 192000:
7588 +                                        index = 11;
7589 +                                        break;
7590 +                                default:
7591 +                                        index = 7;
7592 +                        }
7593 +                        i2s_pll_config_mt7621(index);
7594 +#elif defined(CONFIG_ARCH_MT7623)
7595 +                       i2s_pll_config_mt7623(11);
7596 +#endif
7597 +
7598 +
7599 +#if defined(CONFIG_RALINK_RT3052)
7600 +                       break;
7601 +#endif
7602 +#if defined(CONFIG_RALINK_RT6855A)
7603 +                       *(volatile unsigned long*)(RALINK_SYSCTL_BASE+0x834) |= 0x00020000;
7604 +                       *(volatile unsigned long*)(RALINK_SYSCTL_BASE+0x834) &= 0xFFFDFFFF;
7605 +                       *(volatile unsigned long*)(RALINK_I2S_BASE+0x0) &= 0x7FFFFFFF;  //Rest I2S to default vaule
7606 +                       *(volatile unsigned long*)(RALINK_SYSCTL_BASE+0x860) |= 0x00008080;
7607 +                       *(volatile unsigned long*)(RALINK_SYSCTL_BASE+0x82C) = 0x00000300;
7608 +#elif defined(CONFIG_RALINK_MT7621)
7609 +                        *(volatile unsigned long*)(RALINK_SYSCTL_BASE+0x34) |= 0x00020000;
7610 +                        *(volatile unsigned long*)(RALINK_SYSCTL_BASE+0x34) &= 0xFFFDFFFF;
7611 +                        *(volatile unsigned long*)(RALINK_I2S_BASE+0x0) &= 0x7FFFFFFF;   //Rest I2S to default vaule
7612 +                        *(volatile unsigned long*)(RALINK_SYSCTL_BASE+0x60) = 0x00000010;     //GPIO purpose selection
7613 +#elif defined(CONFIG_RALINK_MT7628)
7614 +                        *(volatile unsigned long*)(RALINK_SYSCTL_BASE+0x34) |= 0x00020000;
7615 +                        *(volatile unsigned long*)(RALINK_SYSCTL_BASE+0x34) &= 0xFFFDFFFF;
7616 +                        *(volatile unsigned long*)(RALINK_I2S_BASE+0x0) &= 0x7FFFFFFF;   //Rest I2S to default vaule
7617 +                        *(volatile unsigned long*)(RALINK_SYSCTL_BASE+0x60) &= ~((0x3)<<6);     //GPIO purpose selection /*FIXME*/
7618 +#elif defined(CONFIG_ARCH_MT7623)
7619 +                       *(volatile unsigned long*)(0xFB000034) |= 0x00020000;
7620 +                       *(volatile unsigned long*)(0xFB000034) &= 0xFFFDFFFF;
7621 +                       *(volatile unsigned long*)(ETHDMASYS_I2S_BASE+0x0) &= 0x7FFFFFFF;   //Rest I2S to default vaule
7622 +
7623 +                       *(volatile unsigned long*)(0xF0005840) &= ~((0x7)<<12);
7624 +                       *(volatile unsigned long*)(0xF0005840) |= ((0x6)<<12);
7625 +                       *(volatile unsigned long*)(0xF0005840) &= ~((0x7)<<9);
7626 +                       *(volatile unsigned long*)(0xF0005840) |= ((0x6)<<9);
7627 +                       *(volatile unsigned long*)(0xF0005040) |= ((0x1)<<10);
7628 +                       *(volatile unsigned long*)(0xF0005040) |= ((0x1)<<9);
7629 +
7630 +                       *(volatile unsigned long*)(0xF00057F0) &= ~((0x7)<<12);
7631 +                       *(volatile unsigned long*)(0xF00057F0) |= ((0x6)<<12);
7632 +                       *(volatile unsigned long*)(0xF0005030) |= ((0x1)<<1);
7633 +
7634 +                       *(volatile unsigned long*)(0xF0005840) &= ~((0x7)<<6);
7635 +                       *(volatile unsigned long*)(0xF0005840) |= ((0x6)<<6);
7636 +                       *(volatile unsigned long*)(0xF0005040) &= ~((0x1)<<8);
7637 +
7638 +                       *(volatile unsigned long*)(0xF00058F0) &= ~((0x7)<<3);
7639 +                       *(volatile unsigned long*)(0xF00058F0) |= ((0x6)<<3);
7640 +                       *(volatile unsigned long*)(0xF0005070) |= ((0x1)<<14);
7641 +
7642 +
7643 +#else
7644 +                       *(volatile unsigned long*)(0xB0000034) |= 0x00020000;
7645 +                       *(volatile unsigned long*)(0xB0000034) &= 0xFFFDFFFF;
7646 +                       *(volatile unsigned long*)(0xB0000A00) &= 0x7FFFFFFF;   //Rest I2S to default vaule
7647 +                       *(volatile unsigned long*)(0xB0000060) = 0x00000018;
7648 +
7649 +#if defined(CONFIG_RALINK_RT3883)
7650 +                       *(volatile unsigned long*)(0xB000002C) = 0x00003000;
7651 +#elif defined(CONFIG_ARCH_MT7623)
7652 +
7653 +#else
7654 +                       *(volatile unsigned long*)(0xB000002C) = 0x00000300;
7655 +#endif
7656 +#endif
7657 +#if defined(CONFIG_RALINK_MT7621)
7658 +                        *(volatile unsigned long*)(RALINK_I2S_BASE+0x18) = 0x80000000;
7659 +                        *(volatile unsigned long*)(RALINK_I2S_BASE+0x00) = 0xc1104040;
7660 +
7661 +                        pTable = i2s_inclk_int;
7662 +                        data = pTable[index];
7663 +                        //*(volatile unsigned long*)(RALINK_I2S_BASE+0x24) = data;
7664 +                        i2s_outw(RALINK_I2S_BASE+0x24, data);
7665 +
7666 +                        pTable = i2s_inclk_comp;
7667 +                        data = pTable[index];
7668 +                        //*(volatile unsigned long*)(RALINK_I2S_BASE+0x20) = data;
7669 +                        i2s_outw(RALINK_I2S_BASE+0x20, (data|0x80000000));
7670 +#elif defined(CONFIG_RALINK_MT7628)
7671 +                       index =11;  /* SR: 192k */
7672 +                       *(volatile unsigned long*)(RALINK_I2S_BASE+0x18) = 0x80000000;
7673 +                        *(volatile unsigned long*)(RALINK_I2S_BASE+0x00) = 0xc1104040;
7674 +
7675 +                        pTable = i2s_inclk_int_16bit;
7676 +                       //pTable = i2s_inclk_int_24bit;
7677 +                        data = pTable[index];
7678 +                        //*(volatile unsigned long*)(RALINK_I2S_BASE+0x24) = data;
7679 +                        i2s_outw(RALINK_I2S_BASE+0x24, data);
7680 +
7681 +                        pTable = i2s_inclk_comp_16bit;
7682 +                       //pTable = i2s_inclk_comp_24bit;
7683 +                        data = pTable[index];
7684 +                        //*(volatile unsigned long*)(RALINK_I2S_BASE+0x20) = data;
7685 +                        i2s_outw(RALINK_I2S_BASE+0x20, (data|0x80000000));
7686 +                       mdelay(5);
7687 +#elif defined(CONFIG_ARCH_MT7623)
7688 +                       index = 11;
7689 +                       *(volatile unsigned long*)(I2S_I2SCFG1) = 0x80000000;
7690 +                       *(volatile unsigned long*)(I2S_I2SCFG) = 0xE1104040;
7691 +                       *(volatile unsigned long*)(ETHDMASYS_SYSCTL_BASE+0x30) |= 0x00020000;
7692 +                       *(volatile unsigned long*)(ETHDMASYS_SYSCTL_BASE+0x2c) |= 0x00000080;
7693 +
7694 +                       pTable = i2s_inclk_int_16bit;
7695 +                       //pTable = i2s_inclk_int_24bit;
7696 +                        data = pTable[index];
7697 +                        i2s_outw(I2S_DIVINT_CFG, data);
7698 +
7699 +                        pTable = i2s_inclk_comp_16bit;
7700 +                       //pTable = i2s_inclk_comp_24bit;
7701 +                        data = pTable[index];
7702 +                        i2s_outw(I2S_DIVCOMP_CFG, (data|0x80000000));
7703 +                       mdelay(5);
7704 +#else
7705 +                       *(volatile unsigned long*)(RALINK_I2S_BASE+0x18) = 0x80000000;
7706 +                       *(volatile unsigned long*)(RALINK_I2S_BASE+0x00) = 0xC1104040;
7707 +                       *(volatile unsigned long*)(RALINK_I2S_BASE+0x24) = 0x00000006;
7708 +                       *(volatile unsigned long*)(RALINK_I2S_BASE+0x20) = 0x80000105;
7709 +#endif
7710 +                       {
7711 +                               int count = 0;
7712 +                               int k=0;
7713 +                               int enable_cnt=0;
7714 +                               unsigned long param[4];
7715 +                               unsigned long data;
7716 +                               //unsigned long data_tmp;
7717 +                               unsigned long ff_status;
7718 +                               //unsigned long* txbuffer;
7719 +#if 0
7720 +                               int j=0;
7721 +                               int temp = 0;
7722 +#endif
7723 +#if defined (INTERNAL_LOOPBACK_DEBUG)
7724 +                               int count2 = 0;
7725 +#endif
7726 +                               memset(param, 0, 4*sizeof(unsigned long) );
7727 +                               copy_from_user(param, (unsigned long*)arg, sizeof(long)*2);
7728 +#if 0
7729 +                               txbuffer = (unsigned long*)kcalloc(param[0], sizeof(unsigned long), GFP_KERNEL);
7730 +                               if(txbuffer == NULL)
7731 +                                       return -1;
7732 +#endif
7733 +
7734 +                               //ff_status = *(volatile unsigned long*)(RALINK_I2S_BASE+0x0C);
7735 +                               ff_status = *(volatile unsigned long*)(I2S_FF_STATUS);
7736 +                               printk("ff status=[0x%08X]\n",(u32)ff_status);
7737 +
7738 +#if 0
7739 +                               for(i = 0; i < param[0]; i++)
7740 +                               {
7741 +                                       if (i==0)
7742 +                                       {
7743 +                                               txbuffer[i] = 0x555A555A;
7744 +                                               printk("%d: 0x%8lx\n", i, txbuffer[i]);
7745 +                                       }
7746 +                                       else
7747 +                                       {
7748 +                                               #if LINUX_VERSION_CODE < KERNEL_VERSION(3,10,14)
7749 +                                               srandom32(jiffies);
7750 +                                               txbuffer[i] = random32()%(0x555A555A)+1;
7751 +                                               //printk("%d: 0x%8x\n", i, txbuffer[i]);
7752 +                                               #else
7753 +                                               //TODO:do we need to implement random32()
7754 +                                               txbuffer[i] = 0x01010101;
7755 +                                               #endif
7756 +                                       }
7757 +                               }
7758 +#endif
7759 +
7760 +                               for( i = 0 ; i < param[0] ; i ++ )
7761 +                               {
7762 +                                       ff_status = *(volatile unsigned long*)(I2S_FF_STATUS);
7763 +                               #if defined(CONFIG_RALINK_MT7628) || defined(CONFIG_ARCH_MT7623)
7764 +                                       if((ff_status&0xFF) > 0)
7765 +                               #else
7766 +                                       if((ff_status&0x0F) > 0)
7767 +                               #endif
7768 +                                       {
7769 +                                               *(volatile unsigned long*)(I2S_TX_FIFO_WREG) = txbuffer[i];
7770 +                                               mdelay(1);
7771 +                                       }
7772 +                                       else
7773 +                                       {
7774 +                                               mdelay(1);
7775 +                                               printk("[%d]NO TX FREE FIFO ST=[0x%08X]\n", i, (u32)ff_status);
7776 +                                               continue;
7777 +                                       }
7778 +
7779 +                                       //if(i >= 16)
7780 +                                       {
7781 +
7782 +                                               ff_status = *(volatile unsigned long*)(I2S_FF_STATUS);
7783 +                                       #if defined(CONFIG_RALINK_MT7628)
7784 +                                               if(((ff_status>>8)&0xFF) > 0)
7785 +                                       #else
7786 +                                               if(((ff_status>>4)&0x0F) > 0)
7787 +                                       #endif
7788 +                                               {
7789 +                                                       data = *(volatile unsigned long*)(I2S_RX_FIFO_RREG);
7790 +                                                       //data_tmp = *(volatile unsigned long*)(I2S_RX_FIFO_RREG);
7791 +                                                       //MSG("[0x%08X] vs [0x%08X]\n", (u32)data, (u32)data_tmp);
7792 +                                               }
7793 +                                               else
7794 +                                               {
7795 +                                                       printk("*[%d]NO RX FREE FIFO ST=[0x%08X]\n", i, (u32)ff_status);
7796 +                                                       continue;
7797 +                                               }
7798 +
7799 +                                               if (data == txbuffer[0])
7800 +                                               {
7801 +                                                       k = i;
7802 +                                                       enable_cnt = 1;
7803 +                                               }
7804 +                                               if (enable_cnt==1)
7805 +                                               {
7806 +                                                       if(data!= txbuffer[i-k])
7807 +                                                       {
7808 +                                                               MSG("[%d][0x%08X] vs [0x%08X]\n", (i-k), (u32)data, (u32)txbuffer[i-k]);
7809 +                                                       }
7810 +                                                       else
7811 +                                                       {
7812 +                                                               //MSG("**[%d][0x%08X] vs [0x%08X]\n" ,(i-k), (u32)data , (u32)txbuffer[i-k]);
7813 +                                                               count++;
7814 +                                                               data=0;
7815 +                                                       }
7816 +                                               }
7817 +
7818 +                                       }
7819 +                               }
7820 +#if 0
7821 +                               temp = i-k;
7822 +                               for (j=0; j<k; j++)
7823 +                               {
7824 +
7825 +                                       //ff_status = *(volatile unsigned long*)(RALINK_I2S_BASE+0x0C);
7826 +                                       ff_status = *(volatile unsigned long*)(I2S_FF_STATUS);
7827 +                               #if defined(CONFIG_RALINK_MT7628) || defined(CONFIG_ARCH_MT7623)
7828 +                                       if(((ff_status>>8)&0xFF) > 0)
7829 +                               #else
7830 +                                       if(((ff_status>>4)&0x0F) > 0)
7831 +                               #endif
7832 +                                       {
7833 +                                               //data = *(volatile unsigned long*)(RALINK_I2S_BASE+0x14);
7834 +                                               data = *(volatile unsigned long*)(I2S_RX_FIFO_RREG);
7835 +                                       }
7836 +                                       else
7837 +                                       {
7838 +                                               printk("*NO RX FREE FIFO ST=[0x%08X]\n", (u32)ff_status);
7839 +                                               continue;
7840 +                                       }
7841 +
7842 +                                       if(data!= txbuffer[temp+j])
7843 +                                       {
7844 +                                               MSG("[%d][0x%08X] vs [0x%08X]\n", (temp+j), (u32)data, (u32)txbuffer[temp+j]);
7845 +                                       }
7846 +                                       else
7847 +                                       {
7848 +                                               //MSG("&&[%d][0x%08X] vs [0x%08X]\n" ,(temp+j), (u32)data , (u32)txbuffer[temp+j]);
7849 +                                               count++;
7850 +                                               data=0;
7851 +                                       }
7852 +                                       if ((temp+j)==128)
7853 +                                       {
7854 +                                               //ff_status = *(volatile unsigned long*)(RALINK_I2S_BASE+0x0C);
7855 +                                               ff_status = *(volatile unsigned long*)(I2S_FF_STATUS);
7856 +                                               //printk("[%d]FIFO ST=[0x%08X]\n", (temp+j), (u32)ff_status);
7857 +                                       }
7858 +                               }
7859 +#endif
7860 +
7861 +#if defined (INTERNAL_LOOPBACK_DEBUG)
7862 +                               for( i = 0 ; i < param[0] ; i ++ )
7863 +                               {
7864 +                                       //ff_status = *(volatile unsigned long*)(RALINK_I2S_BASE+0x0C);
7865 +                                       ff_status = *(volatile unsigned long*)(I2S_FF_STATUS);
7866 +                               #if defined(CONFIG_RALINK_MT7628)|| defined(CONFIG_ARCH_MT7623)
7867 +                                       if((ff_status&0xFF) > 0)
7868 +                               #else
7869 +                                       if((ff_status&0x0F) > 0)
7870 +                               #endif
7871 +                                       {
7872 +                                               //*(volatile unsigned long*)(RALINK_I2S_BASE+0x10) = txbuffer[i];
7873 +                                               *(volatile unsigned long*)(I2S_TX_FIFO_WREG) = txbuffer[i];
7874 +                                               mdelay(1);
7875 +                                       }
7876 +                                       else
7877 +                                       {
7878 +                                               mdelay(1);
7879 +                                               printk("[%d]NO TX FREE FIFO ST=[0x%08X]\n", i, (u32)ff_status);
7880 +                                               continue;
7881 +                                       }
7882 +
7883 +                                       //if(i >= 16)
7884 +                                       {
7885 +
7886 +                                               //ff_status = *(volatile unsigned long*)(RALINK_I2S_BASE+0x0C);
7887 +                                               ff_status = *(volatile unsigned long*)(I2S_FF_STATUS);
7888 +                                       #if defined(CONFIG_RALINK_MT7628)|| defined(CONFIG_ARCH_MT7623)
7889 +                                               if(((ff_status>>8)&0xFF) > 0)
7890 +                                       #else
7891 +                                               if(((ff_status>>4)&0x0F) > 0)
7892 +                                       #endif
7893 +                                               {
7894 +                                                       //data = *(volatile unsigned long*)(RALINK_I2S_BASE+0x14);
7895 +                                                       data = *(volatile unsigned long*)(I2S_RX_FIFO_RREG);
7896 +                                               }
7897 +                                               else
7898 +                                               {
7899 +                                                       printk("*[%d]NO RX FREE FIFO ST=[0x%08X]\n", i, (u32)ff_status);
7900 +                                                       continue;
7901 +                                               }
7902 +
7903 +                                               {
7904 +                                                       if(data!= txbuffer[i])
7905 +                                                       {
7906 +                                                               MSG("[%d][0x%08X] vs [0x%08X]\n", (i), (u32)data, (u32)txbuffer[i]);
7907 +                                                       }
7908 +                                                       else
7909 +                                                       {
7910 +                                                               MSG("**[%d][0x%08X] vs [0x%08X]\n" ,(i), (u32)data , (u32)txbuffer[i]);
7911 +                                                               count2++;
7912 +                                                               data=0;
7913 +                                                       }
7914 +                                               }
7915 +
7916 +                                       }
7917 +                               }
7918 +                               printk("Pattern match done count2=%d.\n", count2);
7919 +#endif
7920 +                               printk("Pattern match done count=%d.\n", count);
7921 +
7922 +                       }
7923 +#if defined(CONFIG_ARCH_MT7623)
7924 +                       *(volatile unsigned long*)(0xFB000034) |= 0x00020000;
7925 +                       *(volatile unsigned long*)(0xFB000034) &= 0xFFFDFFFF;
7926 +                       *(volatile unsigned long*)(ETHDMASYS_I2S_BASE+0x0) &= 0x7FFFFFFF;   //Rest I2S to default vaule
7927 +#endif
7928 +
7929 +#if !defined(CONFIG_RALINK_RT3052)
7930 +                       break;
7931 +#endif
7932 +               case I2S_DEBUG_EXLBK:
7933 +                       MSG("I2S_DEBUG_EXLBK\n");
7934 +#if !defined(CONFIG_ARCH_MT7623)
7935 +                       switch(arg)
7936 +                       {
7937 +                               case 8000:
7938 +                                       index = 0;
7939 +                                       break;
7940 +                               case 11025:
7941 +                                       index = 1;
7942 +                                       break;
7943 +                               case 12000:
7944 +                                       index = 2;
7945 +                                       break;
7946 +                               case 16000:
7947 +                                       index = 3;
7948 +                                       break;
7949 +                               case 22050:
7950 +                                       index = 4;
7951 +                                       break;
7952 +                               case 24000:
7953 +                                       index = 5;
7954 +                                       break;
7955 +                               case 32000:
7956 +                                       index = 6;
7957 +                                       break;
7958 +                               case 44100:
7959 +                                       index = 7;
7960 +                                       break;
7961 +                               case 48000:
7962 +                                       index = 8;
7963 +                                       break;
7964 +                               case 88200:
7965 +                                       index = 9;
7966 +                                       break;
7967 +                               case 96000:
7968 +                                       index = 10;
7969 +                                       break;
7970 +                               default:
7971 +                                       index = 7;
7972 +                       }
7973 +#if defined(CONFIG_RALINK_RT3052)
7974 +                       break;
7975 +#endif
7976 +#if defined(CONFIG_RALINK_RT6855A)
7977 +                       *(volatile unsigned long*)(RALINK_SYSCTL_BASE+0x860) = 0x00008080;
7978 +                       //*(volatile unsigned long*)(RALINK_SYSCTL_BASE+0x82C) = 0x00000300;
7979 +#else
7980 +                       *(volatile unsigned long*)(RALINK_SYSCTL_BASE+0x60) = 0x00000018;
7981 +#if defined(CONFIG_RALINK_RT3883)
7982 +                       *(volatile unsigned long*)(RALINK_SYSCTL_BASE+0x2C) = 0x00003000;
7983 +#else
7984 +                       *(volatile unsigned long*)(RALINK_SYSCTL_BASE+0x2C) = 0x00000300;
7985 +#endif
7986 +#endif
7987 +
7988 +                       *(volatile unsigned long*)(RALINK_I2S_BASE+0x18) = 0x40000000;
7989 +                       *(volatile unsigned long*)(RALINK_I2S_BASE+0x00) = 0x81104040;
7990 +#if defined(CONFIG_RALINK_MT7628)
7991 +                       pTable = i2s_inclk_int_16bit;
7992 +#else
7993 +                       pTable = i2s_inclk_int;
7994 +#endif
7995 +                       data = (volatile unsigned long)(pTable[index]);
7996 +                       i2s_outw(I2S_DIVINT_CFG, data);
7997 +#if defined(CONFIG_RALINK_MT7628)
7998 +                       pTable = i2s_inclk_comp_16bit;
7999 +#else
8000 +                       pTable = i2s_inclk_comp;
8001 +#endif
8002 +                       data = (volatile unsigned long)(pTable[index]);
8003 +                       data |= REGBIT(1, I2S_CLKDIV_EN);
8004 +                       i2s_outw(I2S_DIVCOMP_CFG, data);
8005 +
8006 +               #if defined(CONFIG_I2S_MCLK_12MHZ)
8007 +                       pTable = i2s_codec_12Mhz;
8008 +                       #if defined(CONFIG_I2S_WM8960)
8009 +                               data = pTable[index];
8010 +                       #else
8011 +                               data = pTable[index]|0x01;
8012 +                       #endif
8013 +               #else
8014 +                       pTable = i2s_codec_12p288Mhz;
8015 +                       data = pTable[index];
8016 +               #endif
8017 +
8018 +               #if defined(CONFIG_I2S_WM8960) || defined(CONFIG_I2S_WM8750) || defined(CONFIG_I2S_WM8751)
8019 +                       audiohw_preinit();
8020 +               #endif
8021 +
8022 +
8023 +               #if defined (CONFIG_I2S_WM8960)
8024 +                       audiohw_postinit(1, 1, 1, 1, 0); // for codec apll enable, 16 bit word length
8025 +               #elif defined(CONFIG_I2S_WM8750) || defined(CONFIG_I2S_WM8751)
8026 +                       audiohw_postinit(1, 1, 1, 0); // for 16 bit word length
8027 +               #endif
8028 +
8029 +
8030 +               #if defined (CONFIG_I2S_WM8960)
8031 +                       audiohw_set_frequency(data, 1); // for codec apll enable
8032 +               #elif defined(CONFIG_I2S_WM8750) || defined(CONFIG_I2S_WM8751)
8033 +                       audiohw_set_frequency(data|0x1);
8034 +               #endif
8035 +
8036 +
8037 +               #if defined(CONFIG_I2S_WM8960) || defined(CONFIG_I2S_WM8750) || defined(CONFIG_I2S_WM8751)
8038 +                       audiohw_set_lineout_vol(1, 100, 100);
8039 +                       audiohw_set_linein_vol(100, 100);
8040 +               #endif
8041 +
8042 +
8043 +               #if defined(CONFIG_I2S_TXRX)
8044 +                       //audiohw_loopback(data);
8045 +               #endif
8046 +               #if !defined(CONFIG_RALINK_RT3052)
8047 +                       break;
8048 +               #endif
8049 +#endif
8050 +               case I2S_DEBUG_CODECBYPASS:
8051 +               #if defined(CONFIG_I2S_TXRX)
8052 +               #if defined(CONFIG_RALINK_MT7628)
8053 +                       data = i2s_inw(RALINK_SYSCTL_BASE+0x60);
8054 +                       //data &= ~(0x3<<4);
8055 +                       data &= ~(0x3<<6);
8056 +                       data &= ~(0x3<<16);
8057 +                       data &= ~(0x1<<14);
8058 +                       i2s_outw(RALINK_SYSCTL_BASE+0x60, data);
8059 +
8060 +                       data = i2s_inw(RALINK_SYSCTL_BASE+0x2c);
8061 +                       data &= ~(0x07<<9);
8062 +                       i2s_outw(RALINK_SYSCTL_BASE+0x2c, data);
8063 +               #endif
8064 +
8065 +               #if defined(CONFIG_I2S_WM8960) || defined(CONFIG_I2S_WM8750) || defined(CONFIG_I2S_WM8751)
8066 +                       audiohw_bypass();       /* did not work */
8067 +               #endif
8068 +               #endif
8069 +                       break;
8070 +               case I2S_DEBUG_FMT:
8071 +                       break;
8072 +               case I2S_DEBUG_RESET:
8073 +                       break;
8074 +#if defined(CONFIG_I2S_WM8960)
8075 +               case I2S_DEBUG_CODEC_EXLBK:
8076 +                       audiohw_codec_exlbk();
8077 +                       break;
8078 +#endif
8079 +               default:
8080 +                       MSG("Not support this debug cmd [%d]\n", cmd);
8081 +                       break;
8082 +       }
8083 +
8084 +       return 0;
8085 +}
8086 --- a/sound/soc/codecs/wm8960.c
8087 +++ b/sound/soc/codecs/wm8960.c
8088 @@ -53,10 +53,10 @@
8089   * using 2 wire for device control, so we cache them instead.
8090   */
8091  static const struct reg_default wm8960_reg_defaults[] = {
8092 -       {  0x0, 0x00a7 },
8093 -       {  0x1, 0x00a7 },
8094 -       {  0x2, 0x0000 },
8095 -       {  0x3, 0x0000 },
8096 +       {  0x0, 0x002b },
8097 +       {  0x1, 0x002b },
8098 +       {  0x2, 0x00ff },
8099 +       {  0x3, 0x00ff },
8100         {  0x4, 0x0000 },
8101         {  0x5, 0x0008 },
8102         {  0x6, 0x0000 },
8103 @@ -88,8 +88,8 @@ static const struct reg_default wm8960_r
8104         { 0x25, 0x0050 },
8105         { 0x26, 0x0000 },
8106         { 0x27, 0x0000 },
8107 -       { 0x28, 0x0000 },
8108 -       { 0x29, 0x0000 },
8109 +       { 0x28, 0x007b },
8110 +       { 0x29, 0x007b },
8111         { 0x2a, 0x0040 },
8112         { 0x2b, 0x0000 },
8113         { 0x2c, 0x0000 },
8114 @@ -126,8 +126,7 @@ struct wm8960_priv {
8115         bool deemph;
8116         int playback_fs;
8117  };
8118 -
8119 -#define wm8960_reset(c)        snd_soc_write(c, WM8960_RESET, 0)
8120 +static char init_mtk;
8121
8122  /* enumerated controls */
8123  static const char *wm8960_polarity[] = {"No Inversion", "Left Inverted",
8124 @@ -181,8 +180,8 @@ static int wm8960_get_deemph(struct snd_
8125         struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
8126         struct wm8960_priv *wm8960 = snd_soc_codec_get_drvdata(codec);
8127
8128 -       ucontrol->value.integer.value[0] = wm8960->deemph;
8129 -       return 0;
8130 +       //ucontrol->value.integer.value[0] = wm8960->deemph;
8131 +       return wm8960->deemph;
8132  }
8133
8134  static int wm8960_put_deemph(struct snd_kcontrol *kcontrol,
8135 @@ -200,6 +199,65 @@ static int wm8960_put_deemph(struct snd_
8136         return wm8960_set_deemph(codec);
8137  }
8138
8139 +static void wm8960_reset(struct snd_soc_codec *codec)
8140 +{
8141 +       snd_soc_write(codec, WM8960_RESET, 0);
8142 +       init_mtk = false;
8143 +}
8144 +
8145 +static int wm8960_init(struct snd_soc_codec *codec)
8146 +{
8147 +       u32 data;
8148 +       // In
8149 +       data = snd_soc_read(codec, WM8960_POWER1);
8150 +       snd_soc_write(codec, WM8960_POWER1, data|WM8960_PWR1_ADCL|WM8960_PWR1_ADCR|WM8960_PWR1_AINL |WM8960_PWR1_AINR|WM8960_PWR1_MICB|WM8960_PWR1_VMIDSEL_5K|WM8960_PWR1_VREF);//0x19
8151 +       data = snd_soc_read(codec, WM8960_ADDCTL1);
8152 +       snd_soc_write(codec, WM8960_ADDCTL1, data|ADDITIONAL1_DATSEL(0x01));//0x17
8153 +       snd_soc_write(codec, WM8960_LADC, LEFTGAIN_LDVU|LEFTGAIN_LDACVOL(0xce));//0x15
8154 +       snd_soc_write(codec, WM8960_RADC, LEFTGAIN_LDVU|LEFTGAIN_LDACVOL(0xce));//0x16
8155 +       snd_soc_write(codec, WM8960_LINPATH, 0x168);//0x20
8156 +       snd_soc_write(codec, WM8960_RINPATH, 0x168);//0x21
8157 +       snd_soc_write(codec, WM8960_POWER3, WM8960_PWR3_LMIC|WM8960_PWR3_RMIC|WM8960_PWR3_ROMIX|WM8960_PWR3_LOMIX);//0x2f
8158 +
8159 +       // Out
8160 +       data = snd_soc_read(codec, WM8960_POWER2);
8161 +       snd_soc_write(codec, WM8960_POWER2, data|WM8960_PWR2_DACL|WM8960_PWR2_DACR|WM8960_PWR2_LOUT1|WM8960_PWR2_ROUT1|WM8960_PWR2_SPKL|WM8960_PWR2_SPKR);//0x1a
8162 +       mdelay(10);
8163 +       snd_soc_write(codec, WM8960_IFACE2, 0x40);
8164 +       snd_soc_write(codec, WM8960_LDAC, LEFTGAIN_LDVU|LEFTGAIN_LDACVOL(0xff));//0x0a
8165 +       snd_soc_write(codec, WM8960_RDAC, RIGHTGAIN_RDVU|RIGHTGAIN_RDACVOL(0xff));//0x0b
8166 +       snd_soc_write(codec, WM8960_LOUTMIX, 0x100);//0x22
8167 +       snd_soc_write(codec, WM8960_ROUTMIX, 0x100);//0x25
8168 +
8169 +       snd_soc_write(codec, WM8960_CLASSD1, 0xf7);//0x31
8170 +       snd_soc_write(codec, WM8960_CLASSD3, 0xad);//0x33
8171 +       snd_soc_write(codec, WM8960_DACCTL1,  0x000);//0x05
8172 +
8173 +       snd_soc_write(codec, WM8960_LOUT1, LOUT1_LO1VU|LOUT1_LO1ZC|LOUT1_LOUT1VOL(120));//0x02
8174 +       snd_soc_write(codec, WM8960_ROUT1, ROUT1_RO1VU|ROUT1_RO1ZC|ROUT1_ROUT1VOL(120));//0x03
8175 +
8176 +       data = snd_soc_read(codec, WM8960_LINVOL);
8177 +       data &= ~LINV_LINMUTE;
8178 +       snd_soc_write(codec, WM8960_LINVOL, data|LINV_IPVU|LINV_LINVOL(96));//LINV(0x00)
8179 +
8180 +       data = snd_soc_read(codec, WM8960_RINVOL);
8181 +       data &= ~RINV_RINMUTE;
8182 +       snd_soc_write(codec, WM8960_RINVOL, data|RINV_IPVU|RINV_RINVOL(96)); //LINV(0x01)
8183 +
8184 +       init_mtk = true;
8185 +       return 0;
8186 +}
8187 +
8188 +static int wm8960_close(struct snd_soc_codec *codec)
8189 +{
8190 +       snd_soc_write(codec, WM8960_DACCTL1,0x8); //0x05->0x08
8191 +       snd_soc_write(codec, WM8960_POWER1, 0x000); //0x19->0x000
8192 +       mdelay(300);
8193 +       snd_soc_write(codec, WM8960_POWER2, 0x000); //0x1a->0x000
8194 +
8195 +       return 0;
8196 +}
8197 +
8198  static const DECLARE_TLV_DB_SCALE(adc_tlv, -9700, 50, 0);
8199  static const DECLARE_TLV_DB_SCALE(dac_tlv, -12700, 50, 1);
8200  static const DECLARE_TLV_DB_SCALE(bypass_tlv, -2100, 300, 0);
8201 @@ -542,6 +600,9 @@ static int wm8960_set_dai_fmt(struct snd
8202
8203         /* set iface */
8204         snd_soc_write(codec, WM8960_IFACE1, iface);
8205 +       if (!init_mtk)
8206 +               wm8960_init(codec);
8207 +
8208         return 0;
8209  }
8210
8211 @@ -623,11 +684,15 @@ static int wm8960_set_bias_level_out3(st
8212                 break;
8213
8214         case SND_SOC_BIAS_PREPARE:
8215 +#if 0
8216                 /* Set VMID to 2x50k */
8217                 snd_soc_update_bits(codec, WM8960_POWER1, 0x180, 0x80);
8218 +#endif
8219                 break;
8220
8221         case SND_SOC_BIAS_STANDBY:
8222 +#if 0
8223 +
8224                 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) {
8225                         regcache_sync(wm8960->regmap);
8226
8227 @@ -650,9 +715,13 @@ static int wm8960_set_bias_level_out3(st
8228
8229                 /* Set VMID to 2x250k */
8230                 snd_soc_update_bits(codec, WM8960_POWER1, 0x180, 0x100);
8231 +#endif
8232                 break;
8233
8234         case SND_SOC_BIAS_OFF:
8235 +#if 0
8236 +               wm8960_close(codec);
8237 +
8238                 /* Enable anti-pop features */
8239                 snd_soc_write(codec, WM8960_APOP1,
8240                              WM8960_POBCTRL | WM8960_SOFT_ST |
8241 @@ -661,6 +730,7 @@ static int wm8960_set_bias_level_out3(st
8242                 /* Disable VMID and VREF, let them discharge */
8243                 snd_soc_write(codec, WM8960_POWER1, 0);
8244                 msleep(600);
8245 +#endif
8246                 break;
8247         }
8248
8249 @@ -853,7 +923,6 @@ static int wm8960_set_dai_pll(struct snd
8250
8251         if (pll_div.k) {
8252                 reg |= 0x20;
8253 -
8254                 snd_soc_write(codec, WM8960_PLL2, (pll_div.k >> 16) & 0xff);
8255                 snd_soc_write(codec, WM8960_PLL3, (pll_div.k >> 8) & 0xff);
8256                 snd_soc_write(codec, WM8960_PLL4, pll_div.k & 0xff);
8257 @@ -962,7 +1031,7 @@ static int wm8960_probe(struct snd_soc_c
8258  {
8259         struct wm8960_priv *wm8960 = snd_soc_codec_get_drvdata(codec);
8260         struct wm8960_data *pdata = dev_get_platdata(codec->dev);
8261 -       int ret;
8262 +       int ret = 0;
8263
8264         wm8960->set_bias_level = wm8960_set_bias_level_out3;
8265
8266 @@ -973,26 +1042,9 @@ static int wm8960_probe(struct snd_soc_c
8267                         wm8960->set_bias_level = wm8960_set_bias_level_capless;
8268         }
8269
8270 -       ret = wm8960_reset(codec);
8271 -       if (ret < 0) {
8272 -               dev_err(codec->dev, "Failed to issue reset\n");
8273 -               return ret;
8274 -       }
8275 -
8276 -       wm8960->set_bias_level(codec, SND_SOC_BIAS_STANDBY);
8277 -
8278 -       /* Latch the update bits */
8279 -       snd_soc_update_bits(codec, WM8960_LINVOL, 0x100, 0x100);
8280 -       snd_soc_update_bits(codec, WM8960_RINVOL, 0x100, 0x100);
8281 -       snd_soc_update_bits(codec, WM8960_LADC, 0x100, 0x100);
8282 -       snd_soc_update_bits(codec, WM8960_RADC, 0x100, 0x100);
8283 -       snd_soc_update_bits(codec, WM8960_LDAC, 0x100, 0x100);
8284 -       snd_soc_update_bits(codec, WM8960_RDAC, 0x100, 0x100);
8285 -       snd_soc_update_bits(codec, WM8960_LOUT1, 0x100, 0x100);
8286 -       snd_soc_update_bits(codec, WM8960_ROUT1, 0x100, 0x100);
8287 -       snd_soc_update_bits(codec, WM8960_LOUT2, 0x100, 0x100);
8288 -       snd_soc_update_bits(codec, WM8960_ROUT2, 0x100, 0x100);
8289 -
8290 +       wm8960_reset(codec);
8291 +       //mdelay(400);
8292 +
8293         snd_soc_add_codec_controls(codec, wm8960_snd_controls,
8294                                      ARRAY_SIZE(wm8960_snd_controls));
8295         wm8960_add_widgets(codec);
8296 --- a/sound/soc/codecs/wm8960.h
8297 +++ b/sound/soc/codecs/wm8960.h
8298 @@ -110,4 +110,68 @@
8299  #define WM8960_OPCLK_DIV_5_5           (4 << 0)
8300  #define WM8960_OPCLK_DIV_6             (5 << 0)
8301
8302 +/*
8303 + * WM8960 Power management
8304 +  */
8305 +#define WM8960_PWR1_VMIDSEL_DISABLED    (0 << 7)
8306 +#define WM8960_PWR1_VMIDSEL_50K         (1 << 7)
8307 +#define WM8960_PWR1_VMIDSEL_250K        (2 << 7)
8308 +#define WM8960_PWR1_VMIDSEL_5K          (3 << 7)
8309 +#define WM8960_PWR1_VREF                (1 << 6)
8310 +#define WM8960_PWR1_AINL                (1 << 5)
8311 +#define WM8960_PWR1_AINR                (1 << 4)
8312 +#define WM8960_PWR1_ADCL                (1 << 3)
8313 +#define WM8960_PWR1_ADCR                (1 << 2)
8314 +#define WM8960_PWR1_MICB                (1 << 1)
8315 +#define WM8960_PWR1_DIGENB              (1 << 0)
8316 +
8317 +#define WM8960_PWR2_DACL                (1 << 8)
8318 +#define WM8960_PWR2_DACR                (1 << 7)
8319 +//#define WM8960_PWR2_LOUT1               (1 << 6)
8320 +//#define WM8960_PWR2_ROUT1               (1 << 5)
8321 +#define WM8960_PWR2_SPKL                (1 << 4)
8322 +#define WM8960_PWR2_SPKR                (1 << 3)
8323 +//#define WM8960_PWR2_OUT3                (1 << 1)
8324 +#define WM8960_PWR2_PLL_EN              (1 << 0)
8325 +
8326 +#define WM8960_PWR3_LMIC                                (1 << 5)
8327 +#define WM8960_PWR3_RMIC                                (1 << 4)
8328 +#define WM8960_PWR3_LOMIX                               (1 << 3)
8329 +#define WM8960_PWR3_ROMIX                               (1 << 2)
8330 +
8331 +#define LEFTGAIN                        0x0a
8332 +#define LEFTGAIN_LDVU                   (1 << 8)
8333 +#define LEFTGAIN_LDACVOL(x)             ((x) & 0xff)
8334 +
8335 +#define RIGHTGAIN                       0x0b
8336 +#define RIGHTGAIN_RDVU                  (1 << 8)
8337 +#define RIGHTGAIN_RDACVOL(x)            ((x) & 0xff)
8338 +
8339 +#define ADDITIONAL1_DATSEL(x)           (((x) & 0x3) << 2)
8340 +
8341 +#define AINTFCE1_WL_32                  (3 << 2)
8342 +#define AINTFCE1_WL_24                  (2 << 2)
8343 +#define AINTFCE1_WL_20                  (1 << 2)
8344 +#define AINTFCE1_WL_16                  (0 << 2)
8345 +#define AINTFCE1_FORMAT_I2S             (2 << 0)
8346 +
8347 +#define LOUT1_LO1VU                     (1 << 8)
8348 +#define LOUT1_LO1ZC                     (1 << 7)
8349 +#define LOUT1_LOUT1VOL(x)               ((x) & 0x7f)
8350 +
8351 +#define ROUT1_RO1VU                     (1 << 8)
8352 +#define ROUT1_RO1ZC                     (1 << 7)
8353 +#define ROUT1_ROUT1VOL(x)               ((x) & 0x7f)
8354 +
8355 +#define LINV_IPVU                       (1 << 8)  /* FIXME */
8356 +
8357 +#define LINV_LINMUTE                    (1 << 7)
8358 +#define LINV_LIZC                       (1 << 6)
8359 +#define LINV_LINVOL(x)                  ((x) & 0x3f)
8360 +
8361 +#define RINV_IPVU                       (1 << 8) /* FIXME */
8362 +#define RINV_RINMUTE                    (1 << 7)
8363 +#define RINV_RIZC                       (1 << 6)
8364 +#define RINV_RINVOL(x)                  ((x) & 0x3f)
8365 +#define MBSEL                          (1 << 0)
8366  #endif