target/linux/ramips/patches-3.18/0052-i2c-MIPS-adds-ralink-I2C-driver.patch

   1 From 225f36695bb07dad9510f9affd79e63f1a44a195 Mon Sep 17 00:00:00 2001
   2 From: John Crispin <blogic@openwrt.org>
   3 Date: Sun, 27 Jul 2014 09:52:56 +0100
   4 Subject: [PATCH 52/57] i2c: MIPS: adds ralink I2C driver
   5
   6 Signed-off-by: John Crispin <blogic@openwrt.org>
   7 ---
   8  .../devicetree/bindings/i2c/i2c-ralink.txt         |   27 ++
   9  drivers/i2c/busses/Kconfig                         |    4 +
  10  drivers/i2c/busses/Makefile                        |    1 +
  11  drivers/i2c/busses/i2c-ralink.c                    |  274 ++++++++++++++++++++
  12  4 files changed, 306 insertions(+)
  13  create mode 100644 Documentation/devicetree/bindings/i2c/i2c-ralink.txt
  14  create mode 100644 drivers/i2c/busses/i2c-ralink.c
  15
  16 --- /dev/null
  17 +++ b/Documentation/devicetree/bindings/i2c/i2c-ralink.txt
  18 @@ -0,0 +1,27 @@
  19 +I2C for Ralink platforms
  20 +
  21 +Required properties :
  22 +- compatible : Must be "link,rt3052-i2c"
  23 +- reg: physical base address of the controller and length of memory mapped
  24 +     region.
  25 +- #address-cells = <1>;
  26 +- #size-cells = <0>;
  27 +
  28 +Optional properties:
  29 +- Child nodes conforming to i2c bus binding
  30 +
  31 +Example :
  32 +
  33 +palmbus@10000000 {
  34 +       i2c@900 {
  35 +               compatible = "link,rt3052-i2c";
  36 +               reg = <0x900 0x100>;
  37 +               #address-cells = <1>;
  38 +               #size-cells = <0>;
  39 +
  40 +               hwmon@4b {
  41 +                       compatible = "national,lm92";
  42 +                       reg = <0x4b>;
  43 +               };
  44 +       };
  45 +};
  46 --- a/drivers/i2c/busses/Kconfig
  47 +++ b/drivers/i2c/busses/Kconfig
  48 @@ -711,6 +711,10 @@ config I2C_RK3X
  49           This driver can also be built as a module. If so, the module will
  50           be called i2c-rk3x.
  51
  52 +config I2C_RALINK
  53 +       tristate "Ralink I2C Controller"
  54 +       select OF_I2C
  55 +
  56  config HAVE_S3C2410_I2C
  57         bool
  58         help
  59 --- a/drivers/i2c/busses/Makefile
  60 +++ b/drivers/i2c/busses/Makefile
  61 @@ -66,6 +66,7 @@ obj-$(CONFIG_I2C_PNX)         += i2c-pnx.o
  62  obj-$(CONFIG_I2C_PUV3)         += i2c-puv3.o
  63  obj-$(CONFIG_I2C_PXA)          += i2c-pxa.o
  64  obj-$(CONFIG_I2C_PXA_PCI)      += i2c-pxa-pci.o
  65 +obj-$(CONFIG_I2C_RALINK)       += i2c-ralink.o
  66  obj-$(CONFIG_I2C_QUP)          += i2c-qup.o
  67  obj-$(CONFIG_I2C_RIIC)         += i2c-riic.o
  68  obj-$(CONFIG_I2C_RK3X)         += i2c-rk3x.o
  69 --- /dev/null
  70 +++ b/drivers/i2c/busses/i2c-ralink.c
  71 @@ -0,0 +1,308 @@
  72 +/*
  73 + * drivers/i2c/busses/i2c-ralink.c
  74 + *
  75 + * Copyright (C) 2013 Steven Liu <steven_liu@mediatek.com>
  76 + *
  77 + * Improve driver for i2cdetect from i2c-tools to detect i2c devices on the bus.
  78 + * (C) 2014 Sittisak <sittisaks@hotmail.com>
  79 + *
  80 + * This software is licensed under the terms of the GNU General Public
  81 + * License version 2, as published by the Free Software Foundation, and
  82 + * may be copied, distributed, and modified under those terms.
  83 + *
  84 + * This program is distributed in the hope that it will be useful,
  85 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
  86 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  87 + * GNU General Public License for more details.
  88 + *
  89 + */
  90 +
  91 +#include <linux/interrupt.h>
  92 +#include <linux/kernel.h>
  93 +#include <linux/module.h>
  94 +#include <linux/reset.h>
  95 +#include <linux/delay.h>
  96 +#include <linux/slab.h>
  97 +#include <linux/init.h>
  98 +#include <linux/errno.h>
  99 +#include <linux/platform_device.h>
 100 +#include <linux/of_platform.h>
 101 +#include <linux/i2c.h>
 102 +#include <linux/io.h>
 103 +#include <linux/err.h>
 104 +
 105 +#include <asm/mach-ralink/ralink_regs.h>
 106 +
 107 +#define REG_CONFIG_REG         0x00
 108 +#define REG_CLKDIV_REG         0x04
 109 +#define REG_DEVADDR_REG                0x08
 110 +#define REG_ADDR_REG           0x0C
 111 +#define REG_DATAOUT_REG                0x10
 112 +#define REG_DATAIN_REG         0x14
 113 +#define REG_STATUS_REG         0x18
 114 +#define REG_STARTXFR_REG       0x1C
 115 +#define REG_BYTECNT_REG                0x20
 116 +#define REG_SM0CFG2                    0x28
 117 +#define REG_SM0CTL0                    0x40
 118 +
 119 +#define SYSC_REG_RESET_CTRL    0x34
 120 +
 121 +#define I2C_RST                        (1<<16)
 122 +#define I2C_STARTERR           BIT(4)
 123 +#define I2C_ACKERR             BIT(3)
 124 +#define I2C_DATARDY            BIT(2)
 125 +#define I2C_SDOEMPTY           BIT(1)
 126 +#define I2C_BUSY               BIT(0)
 127 +
 128 +#define I2C_DEVADLEN_7         (6 << 2)
 129 +#define I2C_ADDRDIS            BIT(1)
 130 +
 131 +#define CLKDIV_VALUE           200
 132 +
 133 +#define READ_CMD               0x01
 134 +#define WRITE_CMD              0x00
 135 +#define READ_BLOCK              64
 136 +
 137 +#define SM0CTL0_OD             BIT(31)
 138 +#define SM0CTL0_VTRIG          BIT(28)
 139 +#define SM0CTL0_OUTHI          BIT(6)
 140 +#define SM0CTL0_STRETCH                BIT(1)
 141 +#define SM0CTL0_DEFAULT                (SM0CTL0_OD | SM0CTL0_VTRIG | SM0CTL0_OUTHI | SM0CTL0_STRETCH)
 142 +
 143 +#define MAX_SIZE                       63
 144 +
 145 +enum {
 146 +       I2C_TYPE_RALINK,
 147 +       I2C_TYPE_MEDIATEK,
 148 +};
 149 +
 150 +static void __iomem *membase;
 151 +static struct i2c_adapter *adapter;
 152 +static int hw_type;
 153 +
 154 +static void rt_i2c_w32(u32 val, unsigned reg)
 155 +{
 156 +       iowrite32(val, membase + reg);
 157 +}
 158 +
 159 +static u32 rt_i2c_r32(unsigned reg)
 160 +{
 161 +       return ioread32(membase + reg);
 162 +}
 163 +
 164 +static void rt_i2c_default_speed(void)
 165 +{
 166 +       if (hw_type == I2C_TYPE_RALINK) {
 167 +               rt_i2c_w32(CLKDIV_VALUE, REG_CLKDIV_REG);
 168 +       } else {
 169 +               rt_i2c_w32((CLKDIV_VALUE << 16) | SM0CTL0_DEFAULT, REG_SM0CTL0);
 170 +               rt_i2c_w32(1, REG_SM0CFG2);
 171 +       }
 172 +}
 173 +
 174 +static void rt_i2c_init(struct i2c_adapter *a)
 175 +{/*
 176 +       u32 val;
 177 +
 178 +       val = rt_sysc_r32(SYSC_REG_RESET_CTRL);
 179 +       val |= I2C_RST;
 180 +       rt_sysc_w32(val, SYSC_REG_RESET_CTRL);
 181 +
 182 +       val &= ~I2C_RST;
 183 +       rt_sysc_w32(val, SYSC_REG_RESET_CTRL);
 184 +*/
 185 +       device_reset(a->dev.parent);
 186 +
 187 +       udelay(500);
 188 +       rt_i2c_w32(I2C_DEVADLEN_7 | I2C_ADDRDIS, REG_CONFIG_REG);
 189 +
 190 +       rt_i2c_default_speed();
 191 +}
 192 +
 193 +static inline int rt_i2c_wait_rx_done(void)
 194 +{
 195 +       while (!(rt_i2c_r32(REG_STATUS_REG) & I2C_DATARDY));
 196 +       return 0;
 197 +}
 198 +
 199 +static inline int rt_i2c_wait_idle(void)
 200 +{
 201 +       while (rt_i2c_r32(REG_STATUS_REG) & I2C_BUSY);
 202 +       return 0;
 203 +}
 204 +
 205 +static inline int rt_i2c_wait_tx_done(void)
 206 +{
 207 +       while (!(rt_i2c_r32(REG_STATUS_REG) & I2C_SDOEMPTY));
 208 +       return 0;
 209 +}
 210 +
 211 +static int rt_i2c_handle_msg(struct i2c_adapter *a, struct i2c_msg* msg)
 212 +{
 213 +       int i = 0, j = 0, pos = 0;
 214 +       int nblock = msg->len / READ_BLOCK;
 215 +       int rem = msg->len % READ_BLOCK;
 216 +       int ret = 0;
 217 +
 218 +       if (msg->flags & I2C_M_TEN) {
 219 +               printk("10 bits addr not supported\n");
 220 +               return -EINVAL;
 221 +       }
 222 +
 223 +       if (msg->len > MAX_SIZE) {
 224 +               printk("Notice! The FIFO data length is 64 Byte\n");
 225 +               return -EINVAL;
 226 +       }
 227 +
 228 +       if (msg->flags & I2C_M_RD) {
 229 +               for (i = 0; i < nblock; i++) {
 230 +                       rt_i2c_wait_idle();
 231 +                       rt_i2c_w32(READ_BLOCK - 1, REG_BYTECNT_REG);
 232 +                       rt_i2c_w32(READ_CMD, REG_STARTXFR_REG);
 233 +                       for (j = 0; j < READ_BLOCK; j++) {
 234 +                               rt_i2c_wait_rx_done();
 235 +                               msg->buf[pos++] = rt_i2c_r32(REG_DATAIN_REG);
 236 +                       }
 237 +               }
 238 +
 239 +               rt_i2c_wait_idle();
 240 +               if (rem) {
 241 +                       rt_i2c_w32(rem - 1, REG_BYTECNT_REG);
 242 +                       rt_i2c_w32(READ_CMD, REG_STARTXFR_REG);
 243 +               }
 244 +               for (i = 0; i < rem; i++) {
 245 +                       rt_i2c_wait_rx_done();
 246 +                       msg->buf[pos++] = rt_i2c_r32(REG_DATAIN_REG);
 247 +               }
 248 +       } else {
 249 +               rt_i2c_wait_idle();
 250 +               rt_i2c_w32(msg->len - 1, REG_BYTECNT_REG);
 251 +               for (i = 0; i < msg->len; i++) {
 252 +                       rt_i2c_w32(msg->buf[i], REG_DATAOUT_REG);
 253 +                       if (i == 0)
 254 +                               rt_i2c_w32(WRITE_CMD, REG_STARTXFR_REG);
 255 +                       rt_i2c_wait_tx_done();
 256 +               }
 257 +               //mdelay(2);
 258 +       }
 259 +
 260 +       return ret;
 261 +}
 262 +
 263 +static int rt_i2c_master_xfer(struct i2c_adapter *a, struct i2c_msg *m, int n)
 264 +{
 265 +       int i = 0;
 266 +       int ret = 0;
 267 +
 268 +       rt_i2c_w32(m->addr, REG_DEVADDR_REG);
 269 +       rt_i2c_w32(0, REG_ADDR_REG);
 270 +
 271 +       for (i = 0; ret == 0 && i !=n; i++) {
 272 +               ret = rt_i2c_handle_msg(a, &m[i]);
 273 +
 274 +               if (ret < 0) {
 275 +                       return ret;
 276 +               }
 277 +       }
 278 +
 279 +       return i;
 280 +}
 281 +
 282 +static u32 rt_i2c_func(struct i2c_adapter *a)
 283 +{
 284 +       return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
 285 +}
 286 +
 287 +static const struct i2c_algorithm rt_i2c_algo = {
 288 +       .master_xfer    = rt_i2c_master_xfer,
 289 +       .functionality  = rt_i2c_func,
 290 +};
 291 +
 292 +static const struct of_device_id i2c_rt_dt_ids[] = {
 293 +       { .compatible = "ralink,rt2880-i2c", .data = (void *) I2C_TYPE_RALINK },
 294 +       { .compatible = "mediatek,mt7628-i2c", .data = (void *) I2C_TYPE_MEDIATEK },
 295 +       { /* sentinel */ }
 296 +};
 297 +
 298 +MODULE_DEVICE_TABLE(of, i2c_rt_dt_ids);
 299 +
 300 +static int rt_i2c_probe(struct platform_device *pdev)
 301 +{
 302 +       struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 303 +       const struct of_device_id *match;
 304 +       int ret;
 305 +
 306 +       match = of_match_device(i2c_rt_dt_ids, &pdev->dev);
 307 +       hw_type = (int) match->data;
 308 +
 309 +       if (!res) {
 310 +               dev_err(&pdev->dev, "no memory resource found\n");
 311 +               return -ENODEV;
 312 +       }
 313 +
 314 +       adapter = devm_kzalloc(&pdev->dev, sizeof(struct i2c_adapter), GFP_KERNEL);
 315 +       if (!adapter) {
 316 +               dev_err(&pdev->dev, "failed to allocate i2c_adapter\n");
 317 +               return -ENOMEM;
 318 +       }
 319 +
 320 +       membase = devm_ioremap_resource(&pdev->dev, res);
 321 +       if (IS_ERR(membase))
 322 +               return PTR_ERR(membase);
 323 +
 324 +       strlcpy(adapter->name, dev_name(&pdev->dev), sizeof(adapter->name));
 325 +       adapter->owner = THIS_MODULE;
 326 +       adapter->nr = pdev->id;
 327 +       adapter->timeout = HZ;
 328 +       adapter->algo = &rt_i2c_algo;
 329 +       adapter->class = I2C_CLASS_HWMON | I2C_CLASS_SPD;
 330 +       adapter->dev.parent = &pdev->dev;
 331 +       adapter->dev.of_node = pdev->dev.of_node;
 332 +
 333 +       ret = i2c_add_numbered_adapter(adapter);
 334 +       if (ret)
 335 +               return ret;
 336 +
 337 +       platform_set_drvdata(pdev, adapter);
 338 +
 339 +       rt_i2c_init(adapter);
 340 +
 341 +       dev_info(&pdev->dev, "loaded\n");
 342 +
 343 +       return 0;
 344 +}
 345 +
 346 +static int rt_i2c_remove(struct platform_device *pdev)
 347 +{
 348 +       platform_set_drvdata(pdev, NULL);
 349 +
 350 +       return 0;
 351 +}
 352 +
 353 +static struct platform_driver rt_i2c_driver = {
 354 +       .probe          = rt_i2c_probe,
 355 +       .remove         = rt_i2c_remove,
 356 +       .driver         = {
 357 +               .owner  = THIS_MODULE,
 358 +               .name   = "i2c-ralink",
 359 +               .of_match_table = i2c_rt_dt_ids,
 360 +       },
 361 +};
 362 +
 363 +static int __init i2c_rt_init (void)
 364 +{
 365 +       return platform_driver_register(&rt_i2c_driver);
 366 +}
 367 +subsys_initcall(i2c_rt_init);
 368 +
 369 +static void __exit i2c_rt_exit (void)
 370 +{
 371 +       platform_driver_unregister(&rt_i2c_driver);
 372 +}
 373 +
 374 +module_exit (i2c_rt_exit);
 375 +
 376 +MODULE_AUTHOR("Steven Liu <steven_liu@mediatek.com>");
 377 +MODULE_DESCRIPTION("Ralink I2c host driver");
 378 +MODULE_LICENSE("GPL");
 379 +MODULE_ALIAS("platform:Ralink-I2C");