target/linux/lantiq/patches-3.18/0042-USB-DWC2-big-endian-support.patch

   1 --- a/drivers/usb/dwc2/core.c
   2 +++ b/drivers/usb/dwc2/core.c
   3 @@ -67,10 +67,10 @@ static void dwc2_enable_common_interrupt
   4         u32 intmsk;
   5
   6         /* Clear any pending OTG Interrupts */
   7 -       writel(0xffffffff, hsotg->regs + GOTGINT);
   8 +       dwc2_writel(0xffffffff, hsotg->regs + GOTGINT);
   9
  10         /* Clear any pending interrupts */
  11 -       writel(0xffffffff, hsotg->regs + GINTSTS);
  12 +       dwc2_writel(0xffffffff, hsotg->regs + GINTSTS);
  13
  14         /* Enable the interrupts in the GINTMSK */
  15         intmsk = GINTSTS_MODEMIS | GINTSTS_OTGINT;
  16 @@ -81,7 +81,7 @@ static void dwc2_enable_common_interrupt
  17         intmsk |= GINTSTS_CONIDSTSCHNG | GINTSTS_WKUPINT | GINTSTS_USBSUSP |
  18                   GINTSTS_SESSREQINT;
  19
  20 -       writel(intmsk, hsotg->regs + GINTMSK);
  21 +       dwc2_writel(intmsk, hsotg->regs + GINTMSK);
  22  }
  23
  24  /*
  25 @@ -104,10 +104,10 @@ static void dwc2_init_fs_ls_pclk_sel(str
  26         }
  27
  28         dev_dbg(hsotg->dev, "Initializing HCFG.FSLSPClkSel to %08x\n", val);
  29 -       hcfg = readl(hsotg->regs + HCFG);
  30 +       hcfg = dwc2_readl(hsotg->regs + HCFG);
  31         hcfg &= ~HCFG_FSLSPCLKSEL_MASK;
  32         hcfg |= val << HCFG_FSLSPCLKSEL_SHIFT;
  33 -       writel(hcfg, hsotg->regs + HCFG);
  34 +       dwc2_writel(hcfg, hsotg->regs + HCFG);
  35  }
  36
  37  /*
  38 @@ -125,7 +125,7 @@ static int dwc2_core_reset(struct dwc2_h
  39         /* Wait for AHB master IDLE state */
  40         do {
  41                 usleep_range(20000, 40000);
  42 -               greset = readl(hsotg->regs + GRSTCTL);
  43 +               greset = dwc2_readl(hsotg->regs + GRSTCTL);
  44                 if (++count > 50) {
  45                         dev_warn(hsotg->dev,
  46                                  "%s() HANG! AHB Idle GRSTCTL=%0x\n",
  47 @@ -137,10 +137,10 @@ static int dwc2_core_reset(struct dwc2_h
  48         /* Core Soft Reset */
  49         count = 0;
  50         greset |= GRSTCTL_CSFTRST;
  51 -       writel(greset, hsotg->regs + GRSTCTL);
  52 +       dwc2_writel(greset, hsotg->regs + GRSTCTL);
  53         do {
  54                 usleep_range(20000, 40000);
  55 -               greset = readl(hsotg->regs + GRSTCTL);
  56 +               greset = dwc2_readl(hsotg->regs + GRSTCTL);
  57                 if (++count > 50) {
  58                         dev_warn(hsotg->dev,
  59                                  "%s() HANG! Soft Reset GRSTCTL=%0x\n",
  60 @@ -150,20 +150,20 @@ static int dwc2_core_reset(struct dwc2_h
  61         } while (greset & GRSTCTL_CSFTRST);
  62
  63         if (hsotg->dr_mode == USB_DR_MODE_HOST) {
  64 -               gusbcfg = readl(hsotg->regs + GUSBCFG);
  65 +               gusbcfg = dwc2_readl(hsotg->regs + GUSBCFG);
  66                 gusbcfg &= ~GUSBCFG_FORCEDEVMODE;
  67                 gusbcfg |= GUSBCFG_FORCEHOSTMODE;
  68 -               writel(gusbcfg, hsotg->regs + GUSBCFG);
  69 +               dwc2_writel(gusbcfg, hsotg->regs + GUSBCFG);
  70         } else if (hsotg->dr_mode == USB_DR_MODE_PERIPHERAL) {
  71 -               gusbcfg = readl(hsotg->regs + GUSBCFG);
  72 +               gusbcfg = dwc2_readl(hsotg->regs + GUSBCFG);
  73                 gusbcfg &= ~GUSBCFG_FORCEHOSTMODE;
  74                 gusbcfg |= GUSBCFG_FORCEDEVMODE;
  75 -               writel(gusbcfg, hsotg->regs + GUSBCFG);
  76 +               dwc2_writel(gusbcfg, hsotg->regs + GUSBCFG);
  77         } else if (hsotg->dr_mode == USB_DR_MODE_OTG) {
  78 -               gusbcfg = readl(hsotg->regs + GUSBCFG);
  79 +               gusbcfg = dwc2_readl(hsotg->regs + GUSBCFG);
  80                 gusbcfg &= ~GUSBCFG_FORCEHOSTMODE;
  81                 gusbcfg &= ~GUSBCFG_FORCEDEVMODE;
  82 -               writel(gusbcfg, hsotg->regs + GUSBCFG);
  83 +               dwc2_writel(gusbcfg, hsotg->regs + GUSBCFG);
  84         }
  85
  86         /*
  87 @@ -186,9 +186,9 @@ static int dwc2_fs_phy_init(struct dwc2_
  88          */
  89         if (select_phy) {
  90                 dev_dbg(hsotg->dev, "FS PHY selected\n");
  91 -               usbcfg = readl(hsotg->regs + GUSBCFG);
  92 +               usbcfg = dwc2_readl(hsotg->regs + GUSBCFG);
  93                 usbcfg |= GUSBCFG_PHYSEL;
  94 -               writel(usbcfg, hsotg->regs + GUSBCFG);
  95 +               dwc2_writel(usbcfg, hsotg->regs + GUSBCFG);
  96
  97                 /* Reset after a PHY select */
  98                 retval = dwc2_core_reset(hsotg);
  99 @@ -211,18 +211,18 @@ static int dwc2_fs_phy_init(struct dwc2_
 100                 dev_dbg(hsotg->dev, "FS PHY enabling I2C\n");
 101
 102                 /* Program GUSBCFG.OtgUtmiFsSel to I2C */
 103 -               usbcfg = readl(hsotg->regs + GUSBCFG);
 104 +               usbcfg = dwc2_readl(hsotg->regs + GUSBCFG);
 105                 usbcfg |= GUSBCFG_OTG_UTMI_FS_SEL;
 106 -               writel(usbcfg, hsotg->regs + GUSBCFG);
 107 +               dwc2_writel(usbcfg, hsotg->regs + GUSBCFG);
 108
 109                 /* Program GI2CCTL.I2CEn */
 110 -               i2cctl = readl(hsotg->regs + GI2CCTL);
 111 +               i2cctl = dwc2_readl(hsotg->regs + GI2CCTL);
 112                 i2cctl &= ~GI2CCTL_I2CDEVADDR_MASK;
 113                 i2cctl |= 1 << GI2CCTL_I2CDEVADDR_SHIFT;
 114                 i2cctl &= ~GI2CCTL_I2CEN;
 115 -               writel(i2cctl, hsotg->regs + GI2CCTL);
 116 +               dwc2_writel(i2cctl, hsotg->regs + GI2CCTL);
 117                 i2cctl |= GI2CCTL_I2CEN;
 118 -               writel(i2cctl, hsotg->regs + GI2CCTL);
 119 +               dwc2_writel(i2cctl, hsotg->regs + GI2CCTL);
 120         }
 121
 122         return retval;
 123 @@ -236,7 +236,7 @@ static int dwc2_hs_phy_init(struct dwc2_
 124         if (!select_phy)
 125                 return 0;
 126
 127 -       usbcfg = readl(hsotg->regs + GUSBCFG);
 128 +       usbcfg = dwc2_readl(hsotg->regs + GUSBCFG);
 129
 130         /*
 131          * HS PHY parameters. These parameters are preserved during soft reset
 132 @@ -264,7 +264,7 @@ static int dwc2_hs_phy_init(struct dwc2_
 133                 break;
 134         }
 135
 136 -       writel(usbcfg, hsotg->regs + GUSBCFG);
 137 +       dwc2_writel(usbcfg, hsotg->regs + GUSBCFG);
 138
 139         /* Reset after setting the PHY parameters */
 140         retval = dwc2_core_reset(hsotg);
 141 @@ -299,15 +299,15 @@ static int dwc2_phy_init(struct dwc2_hso
 142             hsotg->hw_params.fs_phy_type == GHWCFG2_FS_PHY_TYPE_DEDICATED &&
 143             hsotg->core_params->ulpi_fs_ls > 0) {
 144                 dev_dbg(hsotg->dev, "Setting ULPI FSLS\n");
 145 -               usbcfg = readl(hsotg->regs + GUSBCFG);
 146 +               usbcfg = dwc2_readl(hsotg->regs + GUSBCFG);
 147                 usbcfg |= GUSBCFG_ULPI_FS_LS;
 148                 usbcfg |= GUSBCFG_ULPI_CLK_SUSP_M;
 149 -               writel(usbcfg, hsotg->regs + GUSBCFG);
 150 +               dwc2_writel(usbcfg, hsotg->regs + GUSBCFG);
 151         } else {
 152 -               usbcfg = readl(hsotg->regs + GUSBCFG);
 153 +               usbcfg = dwc2_readl(hsotg->regs + GUSBCFG);
 154                 usbcfg &= ~GUSBCFG_ULPI_FS_LS;
 155                 usbcfg &= ~GUSBCFG_ULPI_CLK_SUSP_M;
 156 -               writel(usbcfg, hsotg->regs + GUSBCFG);
 157 +               dwc2_writel(usbcfg, hsotg->regs + GUSBCFG);
 158         }
 159
 160         return retval;
 161 @@ -315,7 +315,7 @@ static int dwc2_phy_init(struct dwc2_hso
 162
 163  static int dwc2_gahbcfg_init(struct dwc2_hsotg *hsotg)
 164  {
 165 -       u32 ahbcfg = readl(hsotg->regs + GAHBCFG);
 166 +       u32 ahbcfg = dwc2_readl(hsotg->regs + GAHBCFG);
 167
 168         switch (hsotg->hw_params.arch) {
 169         case GHWCFG2_EXT_DMA_ARCH:
 170 @@ -354,7 +354,7 @@ static int dwc2_gahbcfg_init(struct dwc2
 171         if (hsotg->core_params->dma_enable > 0)
 172                 ahbcfg |= GAHBCFG_DMA_EN;
 173
 174 -       writel(ahbcfg, hsotg->regs + GAHBCFG);
 175 +       dwc2_writel(ahbcfg, hsotg->regs + GAHBCFG);
 176
 177         return 0;
 178  }
 179 @@ -363,7 +363,7 @@ static void dwc2_gusbcfg_init(struct dwc
 180  {
 181         u32 usbcfg;
 182
 183 -       usbcfg = readl(hsotg->regs + GUSBCFG);
 184 +       usbcfg = dwc2_readl(hsotg->regs + GUSBCFG);
 185         usbcfg &= ~(GUSBCFG_HNPCAP | GUSBCFG_SRPCAP);
 186
 187         switch (hsotg->hw_params.op_mode) {
 188 @@ -391,7 +391,7 @@ static void dwc2_gusbcfg_init(struct dwc
 189                 break;
 190         }
 191
 192 -       writel(usbcfg, hsotg->regs + GUSBCFG);
 193 +       dwc2_writel(usbcfg, hsotg->regs + GUSBCFG);
 194  }
 195
 196  /**
 197 @@ -409,7 +409,7 @@ int dwc2_core_init(struct dwc2_hsotg *hs
 198
 199         dev_dbg(hsotg->dev, "%s(%p)\n", __func__, hsotg);
 200
 201 -       usbcfg = readl(hsotg->regs + GUSBCFG);
 202 +       usbcfg = dwc2_readl(hsotg->regs + GUSBCFG);
 203
 204         /* Set ULPI External VBUS bit if needed */
 205         usbcfg &= ~GUSBCFG_ULPI_EXT_VBUS_DRV;
 206 @@ -422,7 +422,7 @@ int dwc2_core_init(struct dwc2_hsotg *hs
 207         if (hsotg->core_params->ts_dline > 0)
 208                 usbcfg |= GUSBCFG_TERMSELDLPULSE;
 209
 210 -       writel(usbcfg, hsotg->regs + GUSBCFG);
 211 +       dwc2_writel(usbcfg, hsotg->regs + GUSBCFG);
 212
 213         /* Reset the Controller */
 214         retval = dwc2_core_reset(hsotg);
 215 @@ -448,11 +448,11 @@ int dwc2_core_init(struct dwc2_hsotg *hs
 216         dwc2_gusbcfg_init(hsotg);
 217
 218         /* Program the GOTGCTL register */
 219 -       otgctl = readl(hsotg->regs + GOTGCTL);
 220 +       otgctl = dwc2_readl(hsotg->regs + GOTGCTL);
 221         otgctl &= ~GOTGCTL_OTGVER;
 222         if (hsotg->core_params->otg_ver > 0)
 223                 otgctl |= GOTGCTL_OTGVER;
 224 -       writel(otgctl, hsotg->regs + GOTGCTL);
 225 +       dwc2_writel(otgctl, hsotg->regs + GOTGCTL);
 226         dev_dbg(hsotg->dev, "OTG VER PARAM: %d\n", hsotg->core_params->otg_ver);
 227
 228         /* Clear the SRP success bit for FS-I2c */
 229 @@ -498,16 +498,16 @@ void dwc2_enable_host_interrupts(struct
 230         dev_dbg(hsotg->dev, "%s()\n", __func__);
 231
 232         /* Disable all interrupts */
 233 -       writel(0, hsotg->regs + GINTMSK);
 234 -       writel(0, hsotg->regs + HAINTMSK);
 235 +       dwc2_writel(0, hsotg->regs + GINTMSK);
 236 +       dwc2_writel(0, hsotg->regs + HAINTMSK);
 237
 238         /* Enable the common interrupts */
 239         dwc2_enable_common_interrupts(hsotg);
 240
 241         /* Enable host mode interrupts without disturbing common interrupts */
 242 -       intmsk = readl(hsotg->regs + GINTMSK);
 243 +       intmsk = dwc2_readl(hsotg->regs + GINTMSK);
 244         intmsk |= GINTSTS_DISCONNINT | GINTSTS_PRTINT | GINTSTS_HCHINT;
 245 -       writel(intmsk, hsotg->regs + GINTMSK);
 246 +       dwc2_writel(intmsk, hsotg->regs + GINTMSK);
 247  }
 248
 249  /**
 250 @@ -517,12 +517,12 @@ void dwc2_enable_host_interrupts(struct
 251   */
 252  void dwc2_disable_host_interrupts(struct dwc2_hsotg *hsotg)
 253  {
 254 -       u32 intmsk = readl(hsotg->regs + GINTMSK);
 255 +       u32 intmsk = dwc2_readl(hsotg->regs + GINTMSK);
 256
 257         /* Disable host mode interrupts without disturbing common interrupts */
 258         intmsk &= ~(GINTSTS_SOF | GINTSTS_PRTINT | GINTSTS_HCHINT |
 259                     GINTSTS_PTXFEMP | GINTSTS_NPTXFEMP);
 260 -       writel(intmsk, hsotg->regs + GINTMSK);
 261 +       dwc2_writel(intmsk, hsotg->regs + GINTMSK);
 262  }
 263
 264  /*
 265 @@ -602,36 +602,36 @@ static void dwc2_config_fifos(struct dwc
 266         dwc2_calculate_dynamic_fifo(hsotg);
 267
 268         /* Rx FIFO */
 269 -       grxfsiz = readl(hsotg->regs + GRXFSIZ);
 270 +       grxfsiz = dwc2_readl(hsotg->regs + GRXFSIZ);
 271         dev_dbg(hsotg->dev, "initial grxfsiz=%08x\n", grxfsiz);
 272         grxfsiz &= ~GRXFSIZ_DEPTH_MASK;
 273         grxfsiz |= params->host_rx_fifo_size <<
 274                    GRXFSIZ_DEPTH_SHIFT & GRXFSIZ_DEPTH_MASK;
 275 -       writel(grxfsiz, hsotg->regs + GRXFSIZ);
 276 -       dev_dbg(hsotg->dev, "new grxfsiz=%08x\n", readl(hsotg->regs + GRXFSIZ));
 277 +       dwc2_writel(grxfsiz, hsotg->regs + GRXFSIZ);
 278 +       dev_dbg(hsotg->dev, "new grxfsiz=%08x\n", dwc2_readl(hsotg->regs + GRXFSIZ));
 279
 280         /* Non-periodic Tx FIFO */
 281         dev_dbg(hsotg->dev, "initial gnptxfsiz=%08x\n",
 282 -               readl(hsotg->regs + GNPTXFSIZ));
 283 +               dwc2_readl(hsotg->regs + GNPTXFSIZ));
 284         nptxfsiz = params->host_nperio_tx_fifo_size <<
 285                    FIFOSIZE_DEPTH_SHIFT & FIFOSIZE_DEPTH_MASK;
 286         nptxfsiz |= params->host_rx_fifo_size <<
 287                     FIFOSIZE_STARTADDR_SHIFT & FIFOSIZE_STARTADDR_MASK;
 288 -       writel(nptxfsiz, hsotg->regs + GNPTXFSIZ);
 289 +       dwc2_writel(nptxfsiz, hsotg->regs + GNPTXFSIZ);
 290         dev_dbg(hsotg->dev, "new gnptxfsiz=%08x\n",
 291 -               readl(hsotg->regs + GNPTXFSIZ));
 292 +               dwc2_readl(hsotg->regs + GNPTXFSIZ));
 293
 294         /* Periodic Tx FIFO */
 295         dev_dbg(hsotg->dev, "initial hptxfsiz=%08x\n",
 296 -               readl(hsotg->regs + HPTXFSIZ));
 297 +               dwc2_readl(hsotg->regs + HPTXFSIZ));
 298         hptxfsiz = params->host_perio_tx_fifo_size <<
 299                    FIFOSIZE_DEPTH_SHIFT & FIFOSIZE_DEPTH_MASK;
 300         hptxfsiz |= (params->host_rx_fifo_size +
 301                      params->host_nperio_tx_fifo_size) <<
 302                     FIFOSIZE_STARTADDR_SHIFT & FIFOSIZE_STARTADDR_MASK;
 303 -       writel(hptxfsiz, hsotg->regs + HPTXFSIZ);
 304 +       dwc2_writel(hptxfsiz, hsotg->regs + HPTXFSIZ);
 305         dev_dbg(hsotg->dev, "new hptxfsiz=%08x\n",
 306 -               readl(hsotg->regs + HPTXFSIZ));
 307 +               dwc2_readl(hsotg->regs + HPTXFSIZ));
 308
 309         if (hsotg->core_params->en_multiple_tx_fifo > 0 &&
 310             hsotg->hw_params.snpsid <= DWC2_CORE_REV_2_94a) {
 311 @@ -639,14 +639,14 @@ static void dwc2_config_fifos(struct dwc
 312                  * Global DFIFOCFG calculation for Host mode -
 313                  * include RxFIFO, NPTXFIFO and HPTXFIFO
 314                  */
 315 -               dfifocfg = readl(hsotg->regs + GDFIFOCFG);
 316 +               dfifocfg = dwc2_readl(hsotg->regs + GDFIFOCFG);
 317                 dfifocfg &= ~GDFIFOCFG_EPINFOBASE_MASK;
 318                 dfifocfg |= (params->host_rx_fifo_size +
 319                              params->host_nperio_tx_fifo_size +
 320                              params->host_perio_tx_fifo_size) <<
 321                             GDFIFOCFG_EPINFOBASE_SHIFT &
 322                             GDFIFOCFG_EPINFOBASE_MASK;
 323 -               writel(dfifocfg, hsotg->regs + GDFIFOCFG);
 324 +               dwc2_writel(dfifocfg, hsotg->regs + GDFIFOCFG);
 325         }
 326  }
 327
 328 @@ -667,14 +667,14 @@ void dwc2_core_host_init(struct dwc2_hso
 329         dev_dbg(hsotg->dev, "%s(%p)\n", __func__, hsotg);
 330
 331         /* Restart the Phy Clock */
 332 -       writel(0, hsotg->regs + PCGCTL);
 333 +       dwc2_writel(0, hsotg->regs + PCGCTL);
 334
 335         /* Initialize Host Configuration Register */
 336         dwc2_init_fs_ls_pclk_sel(hsotg);
 337         if (hsotg->core_params->speed == DWC2_SPEED_PARAM_FULL) {
 338 -               hcfg = readl(hsotg->regs + HCFG);
 339 +               hcfg = dwc2_readl(hsotg->regs + HCFG);
 340                 hcfg |= HCFG_FSLSSUPP;
 341 -               writel(hcfg, hsotg->regs + HCFG);
 342 +               dwc2_writel(hcfg, hsotg->regs + HCFG);
 343         }
 344
 345         /*
 346 @@ -683,9 +683,9 @@ void dwc2_core_host_init(struct dwc2_hso
 347          * and its value must not be changed during runtime.
 348          */
 349         if (hsotg->core_params->reload_ctl > 0) {
 350 -               hfir = readl(hsotg->regs + HFIR);
 351 +               hfir = dwc2_readl(hsotg->regs + HFIR);
 352                 hfir |= HFIR_RLDCTRL;
 353 -               writel(hfir, hsotg->regs + HFIR);
 354 +               dwc2_writel(hfir, hsotg->regs + HFIR);
 355         }
 356
 357         if (hsotg->core_params->dma_desc_enable > 0) {
 358 @@ -701,9 +701,9 @@ void dwc2_core_host_init(struct dwc2_hso
 359                                 "falling back to buffer DMA mode.\n");
 360                         hsotg->core_params->dma_desc_enable = 0;
 361                 } else {
 362 -                       hcfg = readl(hsotg->regs + HCFG);
 363 +                       hcfg = dwc2_readl(hsotg->regs + HCFG);
 364                         hcfg |= HCFG_DESCDMA;
 365 -                       writel(hcfg, hsotg->regs + HCFG);
 366 +                       dwc2_writel(hcfg, hsotg->regs + HCFG);
 367                 }
 368         }
 369
 370 @@ -712,18 +712,18 @@ void dwc2_core_host_init(struct dwc2_hso
 371
 372         /* TODO - check this */
 373         /* Clear Host Set HNP Enable in the OTG Control Register */
 374 -       otgctl = readl(hsotg->regs + GOTGCTL);
 375 +       otgctl = dwc2_readl(hsotg->regs + GOTGCTL);
 376         otgctl &= ~GOTGCTL_HSTSETHNPEN;
 377 -       writel(otgctl, hsotg->regs + GOTGCTL);
 378 +       dwc2_writel(otgctl, hsotg->regs + GOTGCTL);
 379
 380         /* Make sure the FIFOs are flushed */
 381         dwc2_flush_tx_fifo(hsotg, 0x10 /* all TX FIFOs */);
 382         dwc2_flush_rx_fifo(hsotg);
 383
 384         /* Clear Host Set HNP Enable in the OTG Control Register */
 385 -       otgctl = readl(hsotg->regs + GOTGCTL);
 386 +       otgctl = dwc2_readl(hsotg->regs + GOTGCTL);
 387         otgctl &= ~GOTGCTL_HSTSETHNPEN;
 388 -       writel(otgctl, hsotg->regs + GOTGCTL);
 389 +       dwc2_writel(otgctl, hsotg->regs + GOTGCTL);
 390
 391         if (hsotg->core_params->dma_desc_enable <= 0) {
 392                 int num_channels, i;
 393 @@ -732,25 +732,25 @@ void dwc2_core_host_init(struct dwc2_hso
 394                 /* Flush out any leftover queued requests */
 395                 num_channels = hsotg->core_params->host_channels;
 396                 for (i = 0; i < num_channels; i++) {
 397 -                       hcchar = readl(hsotg->regs + HCCHAR(i));
 398 +                       hcchar = dwc2_readl(hsotg->regs + HCCHAR(i));
 399                         hcchar &= ~HCCHAR_CHENA;
 400                         hcchar |= HCCHAR_CHDIS;
 401                         hcchar &= ~HCCHAR_EPDIR;
 402 -                       writel(hcchar, hsotg->regs + HCCHAR(i));
 403 +                       dwc2_writel(hcchar, hsotg->regs + HCCHAR(i));
 404                 }
 405
 406                 /* Halt all channels to put them into a known state */
 407                 for (i = 0; i < num_channels; i++) {
 408                         int count = 0;
 409
 410 -                       hcchar = readl(hsotg->regs + HCCHAR(i));
 411 +                       hcchar = dwc2_readl(hsotg->regs + HCCHAR(i));
 412                         hcchar |= HCCHAR_CHENA | HCCHAR_CHDIS;
 413                         hcchar &= ~HCCHAR_EPDIR;
 414 -                       writel(hcchar, hsotg->regs + HCCHAR(i));
 415 +                       dwc2_writel(hcchar, hsotg->regs + HCCHAR(i));
 416                         dev_dbg(hsotg->dev, "%s: Halt channel %d\n",
 417                                 __func__, i);
 418                         do {
 419 -                               hcchar = readl(hsotg->regs + HCCHAR(i));
 420 +                               hcchar = dwc2_readl(hsotg->regs + HCCHAR(i));
 421                                 if (++count > 1000) {
 422                                         dev_err(hsotg->dev,
 423                                                 "Unable to clear enable on channel %d\n",
 424 @@ -771,7 +771,7 @@ void dwc2_core_host_init(struct dwc2_hso
 425                         !!(hprt0 & HPRT0_PWR));
 426                 if (!(hprt0 & HPRT0_PWR)) {
 427                         hprt0 |= HPRT0_PWR;
 428 -                       writel(hprt0, hsotg->regs + HPRT0);
 429 +                       dwc2_writel(hprt0, hsotg->regs + HPRT0);
 430                 }
 431         }
 432
 433 @@ -851,7 +851,7 @@ static void dwc2_hc_enable_slave_ints(st
 434                 break;
 435         }
 436
 437 -       writel(hcintmsk, hsotg->regs + HCINTMSK(chan->hc_num));
 438 +       dwc2_writel(hcintmsk, hsotg->regs + HCINTMSK(chan->hc_num));
 439         if (dbg_hc(chan))
 440                 dev_vdbg(hsotg->dev, "set HCINTMSK to %08x\n", hcintmsk);
 441  }
 442 @@ -888,7 +888,7 @@ static void dwc2_hc_enable_dma_ints(stru
 443                 }
 444         }
 445
 446 -       writel(hcintmsk, hsotg->regs + HCINTMSK(chan->hc_num));
 447 +       dwc2_writel(hcintmsk, hsotg->regs + HCINTMSK(chan->hc_num));
 448         if (dbg_hc(chan))
 449                 dev_vdbg(hsotg->dev, "set HCINTMSK to %08x\n", hcintmsk);
 450  }
 451 @@ -909,16 +909,16 @@ static void dwc2_hc_enable_ints(struct d
 452         }
 453
 454         /* Enable the top level host channel interrupt */
 455 -       intmsk = readl(hsotg->regs + HAINTMSK);
 456 +       intmsk = dwc2_readl(hsotg->regs + HAINTMSK);
 457         intmsk |= 1 << chan->hc_num;
 458 -       writel(intmsk, hsotg->regs + HAINTMSK);
 459 +       dwc2_writel(intmsk, hsotg->regs + HAINTMSK);
 460         if (dbg_hc(chan))
 461                 dev_vdbg(hsotg->dev, "set HAINTMSK to %08x\n", intmsk);
 462
 463         /* Make sure host channel interrupts are enabled */
 464 -       intmsk = readl(hsotg->regs + GINTMSK);
 465 +       intmsk = dwc2_readl(hsotg->regs + GINTMSK);
 466         intmsk |= GINTSTS_HCHINT;
 467 -       writel(intmsk, hsotg->regs + GINTMSK);
 468 +       dwc2_writel(intmsk, hsotg->regs + GINTMSK);
 469         if (dbg_hc(chan))
 470                 dev_vdbg(hsotg->dev, "set GINTMSK to %08x\n", intmsk);
 471  }
 472 @@ -947,7 +947,7 @@ void dwc2_hc_init(struct dwc2_hsotg *hso
 473         /* Clear old interrupt conditions for this host channel */
 474         hcintmsk = 0xffffffff;
 475         hcintmsk &= ~HCINTMSK_RESERVED14_31;
 476 -       writel(hcintmsk, hsotg->regs + HCINT(hc_num));
 477 +       dwc2_writel(hcintmsk, hsotg->regs + HCINT(hc_num));
 478
 479         /* Enable channel interrupts required for this transfer */
 480         dwc2_hc_enable_ints(hsotg, chan);
 481 @@ -964,7 +964,7 @@ void dwc2_hc_init(struct dwc2_hsotg *hso
 482                 hcchar |= HCCHAR_LSPDDEV;
 483         hcchar |= chan->ep_type << HCCHAR_EPTYPE_SHIFT & HCCHAR_EPTYPE_MASK;
 484         hcchar |= chan->max_packet << HCCHAR_MPS_SHIFT & HCCHAR_MPS_MASK;
 485 -       writel(hcchar, hsotg->regs + HCCHAR(hc_num));
 486 +       dwc2_writel(hcchar, hsotg->regs + HCCHAR(hc_num));
 487         if (dbg_hc(chan)) {
 488                 dev_vdbg(hsotg->dev, "set HCCHAR(%d) to %08x\n",
 489                          hc_num, hcchar);
 490 @@ -1018,7 +1018,7 @@ void dwc2_hc_init(struct dwc2_hsotg *hso
 491                 }
 492         }
 493
 494 -       writel(hcsplt, hsotg->regs + HCSPLT(hc_num));
 495 +       dwc2_writel(hcsplt, hsotg->regs + HCSPLT(hc_num));
 496  }
 497
 498  /**
 499 @@ -1070,14 +1070,14 @@ void dwc2_hc_halt(struct dwc2_hsotg *hso
 500                 u32 hcintmsk = HCINTMSK_CHHLTD;
 501
 502                 dev_vdbg(hsotg->dev, "dequeue/error\n");
 503 -               writel(hcintmsk, hsotg->regs + HCINTMSK(chan->hc_num));
 504 +               dwc2_writel(hcintmsk, hsotg->regs + HCINTMSK(chan->hc_num));
 505
 506                 /*
 507                  * Make sure no other interrupts besides halt are currently
 508                  * pending. Handling another interrupt could cause a crash due
 509                  * to the QTD and QH state.
 510                  */
 511 -               writel(~hcintmsk, hsotg->regs + HCINT(chan->hc_num));
 512 +               dwc2_writel(~hcintmsk, hsotg->regs + HCINT(chan->hc_num));
 513
 514                 /*
 515                  * Make sure the halt status is set to URB_DEQUEUE or AHB_ERR
 516 @@ -1086,7 +1086,7 @@ void dwc2_hc_halt(struct dwc2_hsotg *hso
 517                  */
 518                 chan->halt_status = halt_status;
 519
 520 -               hcchar = readl(hsotg->regs + HCCHAR(chan->hc_num));
 521 +               hcchar = dwc2_readl(hsotg->regs + HCCHAR(chan->hc_num));
 522                 if (!(hcchar & HCCHAR_CHENA)) {
 523                         /*
 524                          * The channel is either already halted or it hasn't
 525 @@ -1114,7 +1114,7 @@ void dwc2_hc_halt(struct dwc2_hsotg *hso
 526                 return;
 527         }
 528
 529 -       hcchar = readl(hsotg->regs + HCCHAR(chan->hc_num));
 530 +       hcchar = dwc2_readl(hsotg->regs + HCCHAR(chan->hc_num));
 531
 532         /* No need to set the bit in DDMA for disabling the channel */
 533         /* TODO check it everywhere channel is disabled */
 534 @@ -1137,7 +1137,7 @@ void dwc2_hc_halt(struct dwc2_hsotg *hso
 535                 if (chan->ep_type == USB_ENDPOINT_XFER_CONTROL ||
 536                     chan->ep_type == USB_ENDPOINT_XFER_BULK) {
 537                         dev_vdbg(hsotg->dev, "control/bulk\n");
 538 -                       nptxsts = readl(hsotg->regs + GNPTXSTS);
 539 +                       nptxsts = dwc2_readl(hsotg->regs + GNPTXSTS);
 540                         if ((nptxsts & TXSTS_QSPCAVAIL_MASK) == 0) {
 541                                 dev_vdbg(hsotg->dev, "Disabling channel\n");
 542                                 hcchar &= ~HCCHAR_CHENA;
 543 @@ -1145,7 +1145,7 @@ void dwc2_hc_halt(struct dwc2_hsotg *hso
 544                 } else {
 545                         if (dbg_perio())
 546                                 dev_vdbg(hsotg->dev, "isoc/intr\n");
 547 -                       hptxsts = readl(hsotg->regs + HPTXSTS);
 548 +                       hptxsts = dwc2_readl(hsotg->regs + HPTXSTS);
 549                         if ((hptxsts & TXSTS_QSPCAVAIL_MASK) == 0 ||
 550                             hsotg->queuing_high_bandwidth) {
 551                                 if (dbg_perio())
 552 @@ -1158,7 +1158,7 @@ void dwc2_hc_halt(struct dwc2_hsotg *hso
 553                         dev_vdbg(hsotg->dev, "DMA enabled\n");
 554         }
 555
 556 -       writel(hcchar, hsotg->regs + HCCHAR(chan->hc_num));
 557 +       dwc2_writel(hcchar, hsotg->regs + HCCHAR(chan->hc_num));
 558         chan->halt_status = halt_status;
 559
 560         if (hcchar & HCCHAR_CHENA) {
 561 @@ -1205,10 +1205,10 @@ void dwc2_hc_cleanup(struct dwc2_hsotg *
 562          * Clear channel interrupt enables and any unhandled channel interrupt
 563          * conditions
 564          */
 565 -       writel(0, hsotg->regs + HCINTMSK(chan->hc_num));
 566 +       dwc2_writel(0, hsotg->regs + HCINTMSK(chan->hc_num));
 567         hcintmsk = 0xffffffff;
 568         hcintmsk &= ~HCINTMSK_RESERVED14_31;
 569 -       writel(hcintmsk, hsotg->regs + HCINT(chan->hc_num));
 570 +       dwc2_writel(hcintmsk, hsotg->regs + HCINT(chan->hc_num));
 571  }
 572
 573  /**
 574 @@ -1294,13 +1294,13 @@ static void dwc2_hc_write_packet(struct
 575         if (((unsigned long)data_buf & 0x3) == 0) {
 576                 /* xfer_buf is DWORD aligned */
 577                 for (i = 0; i < dword_count; i++, data_buf++)
 578 -                       writel(*data_buf, data_fifo);
 579 +                       dwc2_writel(*data_buf, data_fifo);
 580         } else {
 581                 /* xfer_buf is not DWORD aligned */
 582                 for (i = 0; i < dword_count; i++, data_buf++) {
 583                         u32 data = data_buf[0] | data_buf[1] << 8 |
 584                                    data_buf[2] << 16 | data_buf[3] << 24;
 585 -                       writel(data, data_fifo);
 586 +                       dwc2_writel(data, data_fifo);
 587                 }
 588         }
 589
 590 @@ -1453,7 +1453,7 @@ void dwc2_hc_start_transfer(struct dwc2_
 591         hctsiz |= num_packets << TSIZ_PKTCNT_SHIFT & TSIZ_PKTCNT_MASK;
 592         hctsiz |= chan->data_pid_start << TSIZ_SC_MC_PID_SHIFT &
 593                   TSIZ_SC_MC_PID_MASK;
 594 -       writel(hctsiz, hsotg->regs + HCTSIZ(chan->hc_num));
 595 +       dwc2_writel(hctsiz, hsotg->regs + HCTSIZ(chan->hc_num));
 596         if (dbg_hc(chan)) {
 597                 dev_vdbg(hsotg->dev, "Wrote %08x to HCTSIZ(%d)\n",
 598                          hctsiz, chan->hc_num);
 599 @@ -1481,7 +1481,7 @@ void dwc2_hc_start_transfer(struct dwc2_
 600                 } else {
 601                         dma_addr = chan->xfer_dma;
 602                 }
 603 -               writel((u32)dma_addr, hsotg->regs + HCDMA(chan->hc_num));
 604 +               dwc2_writel((u32)dma_addr, hsotg->regs + HCDMA(chan->hc_num));
 605                 if (dbg_hc(chan))
 606                         dev_vdbg(hsotg->dev, "Wrote %08lx to HCDMA(%d)\n",
 607                                  (unsigned long)dma_addr, chan->hc_num);
 608 @@ -1489,13 +1489,13 @@ void dwc2_hc_start_transfer(struct dwc2_
 609
 610         /* Start the split */
 611         if (chan->do_split) {
 612 -               u32 hcsplt = readl(hsotg->regs + HCSPLT(chan->hc_num));
 613 +               u32 hcsplt = dwc2_readl(hsotg->regs + HCSPLT(chan->hc_num));
 614
 615                 hcsplt |= HCSPLT_SPLTENA;
 616 -               writel(hcsplt, hsotg->regs + HCSPLT(chan->hc_num));
 617 +               dwc2_writel(hcsplt, hsotg->regs + HCSPLT(chan->hc_num));
 618         }
 619
 620 -       hcchar = readl(hsotg->regs + HCCHAR(chan->hc_num));
 621 +       hcchar = dwc2_readl(hsotg->regs + HCCHAR(chan->hc_num));
 622         hcchar &= ~HCCHAR_MULTICNT_MASK;
 623         hcchar |= chan->multi_count << HCCHAR_MULTICNT_SHIFT &
 624                   HCCHAR_MULTICNT_MASK;
 625 @@ -1515,7 +1515,7 @@ void dwc2_hc_start_transfer(struct dwc2_
 626                          (hcchar & HCCHAR_MULTICNT_MASK) >>
 627                          HCCHAR_MULTICNT_SHIFT);
 628
 629 -       writel(hcchar, hsotg->regs + HCCHAR(chan->hc_num));
 630 +       dwc2_writel(hcchar, hsotg->regs + HCCHAR(chan->hc_num));
 631         if (dbg_hc(chan))
 632                 dev_vdbg(hsotg->dev, "Wrote %08x to HCCHAR(%d)\n", hcchar,
 633                          chan->hc_num);
 634 @@ -1574,18 +1574,18 @@ void dwc2_hc_start_transfer_ddma(struct
 635                 dev_vdbg(hsotg->dev, "   NTD: %d\n", chan->ntd - 1);
 636         }
 637
 638 -       writel(hctsiz, hsotg->regs + HCTSIZ(chan->hc_num));
 639 +       dwc2_writel(hctsiz, hsotg->regs + HCTSIZ(chan->hc_num));
 640
 641         hc_dma = (u32)chan->desc_list_addr & HCDMA_DMA_ADDR_MASK;
 642
 643         /* Always start from first descriptor */
 644         hc_dma &= ~HCDMA_CTD_MASK;
 645 -       writel(hc_dma, hsotg->regs + HCDMA(chan->hc_num));
 646 +       dwc2_writel(hc_dma, hsotg->regs + HCDMA(chan->hc_num));
 647         if (dbg_hc(chan))
 648                 dev_vdbg(hsotg->dev, "Wrote %08x to HCDMA(%d)\n",
 649                          hc_dma, chan->hc_num);
 650
 651 -       hcchar = readl(hsotg->regs + HCCHAR(chan->hc_num));
 652 +       hcchar = dwc2_readl(hsotg->regs + HCCHAR(chan->hc_num));
 653         hcchar &= ~HCCHAR_MULTICNT_MASK;
 654         hcchar |= chan->multi_count << HCCHAR_MULTICNT_SHIFT &
 655                   HCCHAR_MULTICNT_MASK;
 656 @@ -1604,7 +1604,7 @@ void dwc2_hc_start_transfer_ddma(struct
 657                          (hcchar & HCCHAR_MULTICNT_MASK) >>
 658                          HCCHAR_MULTICNT_SHIFT);
 659
 660 -       writel(hcchar, hsotg->regs + HCCHAR(chan->hc_num));
 661 +       dwc2_writel(hcchar, hsotg->regs + HCCHAR(chan->hc_num));
 662         if (dbg_hc(chan))
 663                 dev_vdbg(hsotg->dev, "Wrote %08x to HCCHAR(%d)\n", hcchar,
 664                          chan->hc_num);
 665 @@ -1661,7 +1661,7 @@ int dwc2_hc_continue_transfer(struct dwc
 666                  * transfer completes, the extra requests for the channel will
 667                  * be flushed.
 668                  */
 669 -               u32 hcchar = readl(hsotg->regs + HCCHAR(chan->hc_num));
 670 +               u32 hcchar = dwc2_readl(hsotg->regs + HCCHAR(chan->hc_num));
 671
 672                 dwc2_hc_set_even_odd_frame(hsotg, chan, &hcchar);
 673                 hcchar |= HCCHAR_CHENA;
 674 @@ -1669,7 +1669,7 @@ int dwc2_hc_continue_transfer(struct dwc
 675                 if (dbg_hc(chan))
 676                         dev_vdbg(hsotg->dev, "   IN xfer: hcchar = 0x%08x\n",
 677                                  hcchar);
 678 -               writel(hcchar, hsotg->regs + HCCHAR(chan->hc_num));
 679 +               dwc2_writel(hcchar, hsotg->regs + HCCHAR(chan->hc_num));
 680                 chan->requests++;
 681                 return 1;
 682         }
 683 @@ -1679,7 +1679,7 @@ int dwc2_hc_continue_transfer(struct dwc
 684         if (chan->xfer_count < chan->xfer_len) {
 685                 if (chan->ep_type == USB_ENDPOINT_XFER_INT ||
 686                     chan->ep_type == USB_ENDPOINT_XFER_ISOC) {
 687 -                       u32 hcchar = readl(hsotg->regs +
 688 +                       u32 hcchar = dwc2_readl(hsotg->regs +
 689                                            HCCHAR(chan->hc_num));
 690
 691                         dwc2_hc_set_even_odd_frame(hsotg, chan,
 692 @@ -1716,12 +1716,12 @@ void dwc2_hc_do_ping(struct dwc2_hsotg *
 693
 694         hctsiz = TSIZ_DOPNG;
 695         hctsiz |= 1 << TSIZ_PKTCNT_SHIFT;
 696 -       writel(hctsiz, hsotg->regs + HCTSIZ(chan->hc_num));
 697 +       dwc2_writel(hctsiz, hsotg->regs + HCTSIZ(chan->hc_num));
 698
 699 -       hcchar = readl(hsotg->regs + HCCHAR(chan->hc_num));
 700 +       hcchar = dwc2_readl(hsotg->regs + HCCHAR(chan->hc_num));
 701         hcchar |= HCCHAR_CHENA;
 702         hcchar &= ~HCCHAR_CHDIS;
 703 -       writel(hcchar, hsotg->regs + HCCHAR(chan->hc_num));
 704 +       dwc2_writel(hcchar, hsotg->regs + HCCHAR(chan->hc_num));
 705  }
 706
 707  /**
 708 @@ -1740,8 +1740,8 @@ u32 dwc2_calc_frame_interval(struct dwc2
 709         u32 hprt0;
 710         int clock = 60; /* default value */
 711
 712 -       usbcfg = readl(hsotg->regs + GUSBCFG);
 713 -       hprt0 = readl(hsotg->regs + HPRT0);
 714 +       usbcfg = dwc2_readl(hsotg->regs + GUSBCFG);
 715 +       hprt0 = dwc2_readl(hsotg->regs + HPRT0);
 716
 717         if (!(usbcfg & GUSBCFG_PHYSEL) && (usbcfg & GUSBCFG_ULPI_UTMI_SEL) &&
 718             !(usbcfg & GUSBCFG_PHYIF16))
 719 @@ -1797,7 +1797,7 @@ void dwc2_read_packet(struct dwc2_hsotg
 720         dev_vdbg(hsotg->dev, "%s(%p,%p,%d)\n", __func__, hsotg, dest, bytes);
 721
 722         for (i = 0; i < word_count; i++, data_buf++)
 723 -               *data_buf = readl(fifo);
 724 +               *data_buf = dwc2_readl(fifo);
 725  }
 726
 727  /**
 728 @@ -1817,56 +1817,56 @@ void dwc2_dump_host_registers(struct dwc
 729         dev_dbg(hsotg->dev, "Host Global Registers\n");
 730         addr = hsotg->regs + HCFG;
 731         dev_dbg(hsotg->dev, "HCFG        @0x%08lX : 0x%08X\n",
 732 -               (unsigned long)addr, readl(addr));
 733 +               (unsigned long)addr, dwc2_readl(addr));
 734         addr = hsotg->regs + HFIR;
 735         dev_dbg(hsotg->dev, "HFIR        @0x%08lX : 0x%08X\n",
 736 -               (unsigned long)addr, readl(addr));
 737 +               (unsigned long)addr, dwc2_readl(addr));
 738         addr = hsotg->regs + HFNUM;
 739         dev_dbg(hsotg->dev, "HFNUM       @0x%08lX : 0x%08X\n",
 740 -               (unsigned long)addr, readl(addr));
 741 +               (unsigned long)addr, dwc2_readl(addr));
 742         addr = hsotg->regs + HPTXSTS;
 743         dev_dbg(hsotg->dev, "HPTXSTS     @0x%08lX : 0x%08X\n",
 744 -               (unsigned long)addr, readl(addr));
 745 +               (unsigned long)addr, dwc2_readl(addr));
 746         addr = hsotg->regs + HAINT;
 747         dev_dbg(hsotg->dev, "HAINT       @0x%08lX : 0x%08X\n",
 748 -               (unsigned long)addr, readl(addr));
 749 +               (unsigned long)addr, dwc2_readl(addr));
 750         addr = hsotg->regs + HAINTMSK;
 751         dev_dbg(hsotg->dev, "HAINTMSK    @0x%08lX : 0x%08X\n",
 752 -               (unsigned long)addr, readl(addr));
 753 +               (unsigned long)addr, dwc2_readl(addr));
 754         if (hsotg->core_params->dma_desc_enable > 0) {
 755                 addr = hsotg->regs + HFLBADDR;
 756                 dev_dbg(hsotg->dev, "HFLBADDR @0x%08lX : 0x%08X\n",
 757 -                       (unsigned long)addr, readl(addr));
 758 +                       (unsigned long)addr, dwc2_readl(addr));
 759         }
 760
 761         addr = hsotg->regs + HPRT0;
 762         dev_dbg(hsotg->dev, "HPRT0       @0x%08lX : 0x%08X\n",
 763 -               (unsigned long)addr, readl(addr));
 764 +               (unsigned long)addr, dwc2_readl(addr));
 765
 766         for (i = 0; i < hsotg->core_params->host_channels; i++) {
 767                 dev_dbg(hsotg->dev, "Host Channel %d Specific Registers\n", i);
 768                 addr = hsotg->regs + HCCHAR(i);
 769                 dev_dbg(hsotg->dev, "HCCHAR      @0x%08lX : 0x%08X\n",
 770 -                       (unsigned long)addr, readl(addr));
 771 +                       (unsigned long)addr, dwc2_readl(addr));
 772                 addr = hsotg->regs + HCSPLT(i);
 773                 dev_dbg(hsotg->dev, "HCSPLT      @0x%08lX : 0x%08X\n",
 774 -                       (unsigned long)addr, readl(addr));
 775 +                       (unsigned long)addr, dwc2_readl(addr));
 776                 addr = hsotg->regs + HCINT(i);
 777                 dev_dbg(hsotg->dev, "HCINT       @0x%08lX : 0x%08X\n",
 778 -                       (unsigned long)addr, readl(addr));
 779 +                       (unsigned long)addr, dwc2_readl(addr));
 780                 addr = hsotg->regs + HCINTMSK(i);
 781                 dev_dbg(hsotg->dev, "HCINTMSK    @0x%08lX : 0x%08X\n",
 782 -                       (unsigned long)addr, readl(addr));
 783 +                       (unsigned long)addr, dwc2_readl(addr));
 784                 addr = hsotg->regs + HCTSIZ(i);
 785                 dev_dbg(hsotg->dev, "HCTSIZ      @0x%08lX : 0x%08X\n",
 786 -                       (unsigned long)addr, readl(addr));
 787 +                       (unsigned long)addr, dwc2_readl(addr));
 788                 addr = hsotg->regs + HCDMA(i);
 789                 dev_dbg(hsotg->dev, "HCDMA       @0x%08lX : 0x%08X\n",
 790 -                       (unsigned long)addr, readl(addr));
 791 +                       (unsigned long)addr, dwc2_readl(addr));
 792                 if (hsotg->core_params->dma_desc_enable > 0) {
 793                         addr = hsotg->regs + HCDMAB(i);
 794                         dev_dbg(hsotg->dev, "HCDMAB      @0x%08lX : 0x%08X\n",
 795 -                               (unsigned long)addr, readl(addr));
 796 +                               (unsigned long)addr, dwc2_readl(addr));
 797                 }
 798         }
 799  #endif
 800 @@ -1888,80 +1888,80 @@ void dwc2_dump_global_registers(struct d
 801         dev_dbg(hsotg->dev, "Core Global Registers\n");
 802         addr = hsotg->regs + GOTGCTL;
 803         dev_dbg(hsotg->dev, "GOTGCTL     @0x%08lX : 0x%08X\n",
 804 -               (unsigned long)addr, readl(addr));
 805 +               (unsigned long)addr, dwc2_readl(addr));
 806         addr = hsotg->regs + GOTGINT;
 807         dev_dbg(hsotg->dev, "GOTGINT     @0x%08lX : 0x%08X\n",
 808 -               (unsigned long)addr, readl(addr));
 809 +               (unsigned long)addr, dwc2_readl(addr));
 810         addr = hsotg->regs + GAHBCFG;
 811         dev_dbg(hsotg->dev, "GAHBCFG     @0x%08lX : 0x%08X\n",
 812 -               (unsigned long)addr, readl(addr));
 813 +               (unsigned long)addr, dwc2_readl(addr));
 814         addr = hsotg->regs + GUSBCFG;
 815         dev_dbg(hsotg->dev, "GUSBCFG     @0x%08lX : 0x%08X\n",
 816 -               (unsigned long)addr, readl(addr));
 817 +               (unsigned long)addr, dwc2_readl(addr));
 818         addr = hsotg->regs + GRSTCTL;
 819         dev_dbg(hsotg->dev, "GRSTCTL     @0x%08lX : 0x%08X\n",
 820 -               (unsigned long)addr, readl(addr));
 821 +               (unsigned long)addr, dwc2_readl(addr));
 822         addr = hsotg->regs + GINTSTS;
 823         dev_dbg(hsotg->dev, "GINTSTS     @0x%08lX : 0x%08X\n",
 824 -               (unsigned long)addr, readl(addr));
 825 +               (unsigned long)addr, dwc2_readl(addr));
 826         addr = hsotg->regs + GINTMSK;
 827         dev_dbg(hsotg->dev, "GINTMSK     @0x%08lX : 0x%08X\n",
 828 -               (unsigned long)addr, readl(addr));
 829 +               (unsigned long)addr, dwc2_readl(addr));
 830         addr = hsotg->regs + GRXSTSR;
 831         dev_dbg(hsotg->dev, "GRXSTSR     @0x%08lX : 0x%08X\n",
 832 -               (unsigned long)addr, readl(addr));
 833 +               (unsigned long)addr, dwc2_readl(addr));
 834         addr = hsotg->regs + GRXFSIZ;
 835         dev_dbg(hsotg->dev, "GRXFSIZ     @0x%08lX : 0x%08X\n",
 836 -               (unsigned long)addr, readl(addr));
 837 +               (unsigned long)addr, dwc2_readl(addr));
 838         addr = hsotg->regs + GNPTXFSIZ;
 839         dev_dbg(hsotg->dev, "GNPTXFSIZ   @0x%08lX : 0x%08X\n",
 840 -               (unsigned long)addr, readl(addr));
 841 +               (unsigned long)addr, dwc2_readl(addr));
 842         addr = hsotg->regs + GNPTXSTS;
 843         dev_dbg(hsotg->dev, "GNPTXSTS    @0x%08lX : 0x%08X\n",
 844 -               (unsigned long)addr, readl(addr));
 845 +               (unsigned long)addr, dwc2_readl(addr));
 846         addr = hsotg->regs + GI2CCTL;
 847         dev_dbg(hsotg->dev, "GI2CCTL     @0x%08lX : 0x%08X\n",
 848 -               (unsigned long)addr, readl(addr));
 849 +               (unsigned long)addr, dwc2_readl(addr));
 850         addr = hsotg->regs + GPVNDCTL;
 851         dev_dbg(hsotg->dev, "GPVNDCTL    @0x%08lX : 0x%08X\n",
 852 -               (unsigned long)addr, readl(addr));
 853 +               (unsigned long)addr, dwc2_readl(addr));
 854         addr = hsotg->regs + GGPIO;
 855         dev_dbg(hsotg->dev, "GGPIO       @0x%08lX : 0x%08X\n",
 856 -               (unsigned long)addr, readl(addr));
 857 +               (unsigned long)addr, dwc2_readl(addr));
 858         addr = hsotg->regs + GUID;
 859         dev_dbg(hsotg->dev, "GUID        @0x%08lX : 0x%08X\n",
 860 -               (unsigned long)addr, readl(addr));
 861 +               (unsigned long)addr, dwc2_readl(addr));
 862         addr = hsotg->regs + GSNPSID;
 863         dev_dbg(hsotg->dev, "GSNPSID     @0x%08lX : 0x%08X\n",
 864 -               (unsigned long)addr, readl(addr));
 865 +               (unsigned long)addr, dwc2_readl(addr));
 866         addr = hsotg->regs + GHWCFG1;
 867         dev_dbg(hsotg->dev, "GHWCFG1     @0x%08lX : 0x%08X\n",
 868 -               (unsigned long)addr, readl(addr));
 869 +               (unsigned long)addr, dwc2_readl(addr));
 870         addr = hsotg->regs + GHWCFG2;
 871         dev_dbg(hsotg->dev, "GHWCFG2     @0x%08lX : 0x%08X\n",
 872 -               (unsigned long)addr, readl(addr));
 873 +               (unsigned long)addr, dwc2_readl(addr));
 874         addr = hsotg->regs + GHWCFG3;
 875         dev_dbg(hsotg->dev, "GHWCFG3     @0x%08lX : 0x%08X\n",
 876 -               (unsigned long)addr, readl(addr));
 877 +               (unsigned long)addr, dwc2_readl(addr));
 878         addr = hsotg->regs + GHWCFG4;
 879         dev_dbg(hsotg->dev, "GHWCFG4     @0x%08lX : 0x%08X\n",
 880 -               (unsigned long)addr, readl(addr));
 881 +               (unsigned long)addr, dwc2_readl(addr));
 882         addr = hsotg->regs + GLPMCFG;
 883         dev_dbg(hsotg->dev, "GLPMCFG     @0x%08lX : 0x%08X\n",
 884 -               (unsigned long)addr, readl(addr));
 885 +               (unsigned long)addr, dwc2_readl(addr));
 886         addr = hsotg->regs + GPWRDN;
 887         dev_dbg(hsotg->dev, "GPWRDN      @0x%08lX : 0x%08X\n",
 888 -               (unsigned long)addr, readl(addr));
 889 +               (unsigned long)addr, dwc2_readl(addr));
 890         addr = hsotg->regs + GDFIFOCFG;
 891         dev_dbg(hsotg->dev, "GDFIFOCFG   @0x%08lX : 0x%08X\n",
 892 -               (unsigned long)addr, readl(addr));
 893 +               (unsigned long)addr, dwc2_readl(addr));
 894         addr = hsotg->regs + HPTXFSIZ;
 895         dev_dbg(hsotg->dev, "HPTXFSIZ    @0x%08lX : 0x%08X\n",
 896 -               (unsigned long)addr, readl(addr));
 897 +               (unsigned long)addr, dwc2_readl(addr));
 898
 899         addr = hsotg->regs + PCGCTL;
 900         dev_dbg(hsotg->dev, "PCGCTL      @0x%08lX : 0x%08X\n",
 901 -               (unsigned long)addr, readl(addr));
 902 +               (unsigned long)addr, dwc2_readl(addr));
 903  #endif
 904  }
 905
 906 @@ -1980,15 +1980,15 @@ void dwc2_flush_tx_fifo(struct dwc2_hsot
 907
 908         greset = GRSTCTL_TXFFLSH;
 909         greset |= num << GRSTCTL_TXFNUM_SHIFT & GRSTCTL_TXFNUM_MASK;
 910 -       writel(greset, hsotg->regs + GRSTCTL);
 911 +       dwc2_writel(greset, hsotg->regs + GRSTCTL);
 912
 913         do {
 914 -               greset = readl(hsotg->regs + GRSTCTL);
 915 +               greset = dwc2_readl(hsotg->regs + GRSTCTL);
 916                 if (++count > 10000) {
 917                         dev_warn(hsotg->dev,
 918                                  "%s() HANG! GRSTCTL=%0x GNPTXSTS=0x%08x\n",
 919                                  __func__, greset,
 920 -                                readl(hsotg->regs + GNPTXSTS));
 921 +                                dwc2_readl(hsotg->regs + GNPTXSTS));
 922                         break;
 923                 }
 924                 udelay(1);
 925 @@ -2011,10 +2011,10 @@ void dwc2_flush_rx_fifo(struct dwc2_hsot
 926         dev_vdbg(hsotg->dev, "%s()\n", __func__);
 927
 928         greset = GRSTCTL_RXFFLSH;
 929 -       writel(greset, hsotg->regs + GRSTCTL);
 930 +       dwc2_writel(greset, hsotg->regs + GRSTCTL);
 931
 932         do {
 933 -               greset = readl(hsotg->regs + GRSTCTL);
 934 +               greset = dwc2_readl(hsotg->regs + GRSTCTL);
 935                 if (++count > 10000) {
 936                         dev_warn(hsotg->dev, "%s() HANG! GRSTCTL=%0x\n",
 937                                  __func__, greset);
 938 @@ -2676,7 +2676,7 @@ int dwc2_get_hwparams(struct dwc2_hsotg
 939          * 0x45f42xxx or 0x45f43xxx, which corresponds to either "OT2" or "OT3",
 940          * as in "OTG version 2.xx" or "OTG version 3.xx".
 941          */
 942 -       hw->snpsid = readl(hsotg->regs + GSNPSID);
 943 +       hw->snpsid = dwc2_readl(hsotg->regs + GSNPSID);
 944         if ((hw->snpsid & 0xfffff000) != 0x4f542000 &&
 945             (hw->snpsid & 0xfffff000) != 0x4f543000) {
 946                 dev_err(hsotg->dev, "Bad value for GSNPSID: 0x%08x\n",
 947 @@ -2688,11 +2688,11 @@ int dwc2_get_hwparams(struct dwc2_hsotg
 948                 hw->snpsid >> 12 & 0xf, hw->snpsid >> 8 & 0xf,
 949                 hw->snpsid >> 4 & 0xf, hw->snpsid & 0xf, hw->snpsid);
 950
 951 -       hwcfg1 = readl(hsotg->regs + GHWCFG1);
 952 -       hwcfg2 = readl(hsotg->regs + GHWCFG2);
 953 -       hwcfg3 = readl(hsotg->regs + GHWCFG3);
 954 -       hwcfg4 = readl(hsotg->regs + GHWCFG4);
 955 -       grxfsiz = readl(hsotg->regs + GRXFSIZ);
 956 +       hwcfg1 = dwc2_readl(hsotg->regs + GHWCFG1);
 957 +       hwcfg2 = dwc2_readl(hsotg->regs + GHWCFG2);
 958 +       hwcfg3 = dwc2_readl(hsotg->regs + GHWCFG3);
 959 +       hwcfg4 = dwc2_readl(hsotg->regs + GHWCFG4);
 960 +       grxfsiz = dwc2_readl(hsotg->regs + GRXFSIZ);
 961
 962         dev_dbg(hsotg->dev, "hwcfg1=%08x\n", hwcfg1);
 963         dev_dbg(hsotg->dev, "hwcfg2=%08x\n", hwcfg2);
 964 @@ -2701,18 +2701,18 @@ int dwc2_get_hwparams(struct dwc2_hsotg
 965         dev_dbg(hsotg->dev, "grxfsiz=%08x\n", grxfsiz);
 966
 967         /* Force host mode to get HPTXFSIZ / GNPTXFSIZ exact power on value */
 968 -       gusbcfg = readl(hsotg->regs + GUSBCFG);
 969 +       gusbcfg = dwc2_readl(hsotg->regs + GUSBCFG);
 970         gusbcfg |= GUSBCFG_FORCEHOSTMODE;
 971 -       writel(gusbcfg, hsotg->regs + GUSBCFG);
 972 +       dwc2_writel(gusbcfg, hsotg->regs + GUSBCFG);
 973         usleep_range(100000, 150000);
 974
 975 -       gnptxfsiz = readl(hsotg->regs + GNPTXFSIZ);
 976 -       hptxfsiz = readl(hsotg->regs + HPTXFSIZ);
 977 +       gnptxfsiz = dwc2_readl(hsotg->regs + GNPTXFSIZ);
 978 +       hptxfsiz = dwc2_readl(hsotg->regs + HPTXFSIZ);
 979         dev_dbg(hsotg->dev, "gnptxfsiz=%08x\n", gnptxfsiz);
 980         dev_dbg(hsotg->dev, "hptxfsiz=%08x\n", hptxfsiz);
 981 -       gusbcfg = readl(hsotg->regs + GUSBCFG);
 982 +       gusbcfg = dwc2_readl(hsotg->regs + GUSBCFG);
 983         gusbcfg &= ~GUSBCFG_FORCEHOSTMODE;
 984 -       writel(gusbcfg, hsotg->regs + GUSBCFG);
 985 +       dwc2_writel(gusbcfg, hsotg->regs + GUSBCFG);
 986         usleep_range(100000, 150000);
 987
 988         /* hwcfg2 */
 989 @@ -2831,7 +2831,7 @@ u16 dwc2_get_otg_version(struct dwc2_hso
 990
 991  bool dwc2_is_controller_alive(struct dwc2_hsotg *hsotg)
 992  {
 993 -       if (readl(hsotg->regs + GSNPSID) == 0xffffffff)
 994 +       if (dwc2_readl(hsotg->regs + GSNPSID) == 0xffffffff)
 995                 return false;
 996         else
 997                 return true;
 998 @@ -2845,10 +2845,10 @@ bool dwc2_is_controller_alive(struct dwc
 999   */
1000  void dwc2_enable_global_interrupts(struct dwc2_hsotg *hsotg)
1001  {
1002 -       u32 ahbcfg = readl(hsotg->regs + GAHBCFG);
1003 +       u32 ahbcfg = dwc2_readl(hsotg->regs + GAHBCFG);
1004
1005         ahbcfg |= GAHBCFG_GLBL_INTR_EN;
1006 -       writel(ahbcfg, hsotg->regs + GAHBCFG);
1007 +       dwc2_writel(ahbcfg, hsotg->regs + GAHBCFG);
1008  }
1009
1010  /**
1011 @@ -2859,10 +2859,10 @@ void dwc2_enable_global_interrupts(struc
1012   */
1013  void dwc2_disable_global_interrupts(struct dwc2_hsotg *hsotg)
1014  {
1015 -       u32 ahbcfg = readl(hsotg->regs + GAHBCFG);
1016 +       u32 ahbcfg = dwc2_readl(hsotg->regs + GAHBCFG);
1017
1018         ahbcfg &= ~GAHBCFG_GLBL_INTR_EN;
1019 -       writel(ahbcfg, hsotg->regs + GAHBCFG);
1020 +       dwc2_writel(ahbcfg, hsotg->regs + GAHBCFG);
1021  }
1022
1023  MODULE_DESCRIPTION("DESIGNWARE HS OTG Core");
1024 --- a/drivers/usb/dwc2/core.h
1025 +++ b/drivers/usb/dwc2/core.h
1026 @@ -44,16 +44,28 @@
1027  #include <linux/usb/phy.h>
1028  #include "hw.h"
1029
1030 -#ifdef DWC2_LOG_WRITES
1031 -static inline void do_write(u32 value, void *addr)
1032 +static inline u32 dwc2_readl(const void __iomem *addr)
1033  {
1034 -       writel(value, addr);
1035 -       pr_info("INFO:: wrote %08x to %p\n", value, addr);
1036 +       u32 value = __raw_readl(addr);
1037 +
1038 +       /* In order to preserve endianness __raw_* operation is used. Therefore
1039 +          a barrier is needed to ensure IO access is not re-ordered across
1040 +          reads or writes */
1041 +       mb();
1042 +       return value;
1043  }
1044
1045 -#undef writel
1046 -#define writel(v, a)   do_write(v, a)
1047 +static inline void dwc2_writel(u32 value, void __iomem *addr)
1048 +{
1049 +       __raw_writel(value, addr);
1050 +       /* In order to preserve endianness __raw_* operation is used. Therefore
1051 +          a barrier is needed to ensure IO access is not re-ordered across
1052 +          reads or writes */
1053 +       mb();
1054 +#ifdef DWC2_LOG_WRITES
1055 +       pr_info("INFO:: wrote %08x to %p\n", value, addr);
1056  #endif
1057 +}
1058
1059  /* Maximum number of Endpoints/HostChannels */
1060  #define MAX_EPS_CHANNELS       16
1061 --- a/drivers/usb/dwc2/core_intr.c
1062 +++ b/drivers/usb/dwc2/core_intr.c
1063 @@ -80,15 +80,15 @@ static const char *dwc2_op_state_str(str
1064   */
1065  static void dwc2_handle_usb_port_intr(struct dwc2_hsotg *hsotg)
1066  {
1067 -       u32 hprt0 = readl(hsotg->regs + HPRT0);
1068 +       u32 hprt0 = dwc2_readl(hsotg->regs + HPRT0);
1069
1070         if (hprt0 & HPRT0_ENACHG) {
1071                 hprt0 &= ~HPRT0_ENA;
1072 -               writel(hprt0, hsotg->regs + HPRT0);
1073 +               dwc2_writel(hprt0, hsotg->regs + HPRT0);
1074         }
1075
1076         /* Clear interrupt */
1077 -       writel(GINTSTS_PRTINT, hsotg->regs + GINTSTS);
1078 +       dwc2_writel(GINTSTS_PRTINT, hsotg->regs + GINTSTS);
1079  }
1080
1081  /**
1082 @@ -102,7 +102,7 @@ static void dwc2_handle_mode_mismatch_in
1083                  dwc2_is_host_mode(hsotg) ? "Host" : "Device");
1084
1085         /* Clear interrupt */
1086 -       writel(GINTSTS_MODEMIS, hsotg->regs + GINTSTS);
1087 +       dwc2_writel(GINTSTS_MODEMIS, hsotg->regs + GINTSTS);
1088  }
1089
1090  /**
1091 @@ -117,8 +117,8 @@ static void dwc2_handle_otg_intr(struct
1092         u32 gotgctl;
1093         u32 gintmsk;
1094
1095 -       gotgint = readl(hsotg->regs + GOTGINT);
1096 -       gotgctl = readl(hsotg->regs + GOTGCTL);
1097 +       gotgint = dwc2_readl(hsotg->regs + GOTGINT);
1098 +       gotgctl = dwc2_readl(hsotg->regs + GOTGCTL);
1099         dev_dbg(hsotg->dev, "++OTG Interrupt gotgint=%0x [%s]\n", gotgint,
1100                 dwc2_op_state_str(hsotg));
1101
1102 @@ -126,7 +126,7 @@ static void dwc2_handle_otg_intr(struct
1103                 dev_dbg(hsotg->dev,
1104                         " ++OTG Interrupt: Session End Detected++ (%s)\n",
1105                         dwc2_op_state_str(hsotg));
1106 -               gotgctl = readl(hsotg->regs + GOTGCTL);
1107 +               gotgctl = dwc2_readl(hsotg->regs + GOTGCTL);
1108
1109                 if (hsotg->op_state == OTG_STATE_B_HOST) {
1110                         hsotg->op_state = OTG_STATE_B_PERIPHERAL;
1111 @@ -149,15 +149,15 @@ static void dwc2_handle_otg_intr(struct
1112                         hsotg->lx_state = DWC2_L0;
1113                 }
1114
1115 -               gotgctl = readl(hsotg->regs + GOTGCTL);
1116 +               gotgctl = dwc2_readl(hsotg->regs + GOTGCTL);
1117                 gotgctl &= ~GOTGCTL_DEVHNPEN;
1118 -               writel(gotgctl, hsotg->regs + GOTGCTL);
1119 +               dwc2_writel(gotgctl, hsotg->regs + GOTGCTL);
1120         }
1121
1122         if (gotgint & GOTGINT_SES_REQ_SUC_STS_CHNG) {
1123                 dev_dbg(hsotg->dev,
1124                         " ++OTG Interrupt: Session Request Success Status Change++\n");
1125 -               gotgctl = readl(hsotg->regs + GOTGCTL);
1126 +               gotgctl = dwc2_readl(hsotg->regs + GOTGCTL);
1127                 if (gotgctl & GOTGCTL_SESREQSCS) {
1128                         if (hsotg->core_params->phy_type ==
1129                                         DWC2_PHY_TYPE_PARAM_FS
1130 @@ -165,9 +165,9 @@ static void dwc2_handle_otg_intr(struct
1131                                 hsotg->srp_success = 1;
1132                         } else {
1133                                 /* Clear Session Request */
1134 -                               gotgctl = readl(hsotg->regs + GOTGCTL);
1135 +                               gotgctl = dwc2_readl(hsotg->regs + GOTGCTL);
1136                                 gotgctl &= ~GOTGCTL_SESREQ;
1137 -                               writel(gotgctl, hsotg->regs + GOTGCTL);
1138 +                               dwc2_writel(gotgctl, hsotg->regs + GOTGCTL);
1139                         }
1140                 }
1141         }
1142 @@ -177,7 +177,7 @@ static void dwc2_handle_otg_intr(struct
1143                  * Print statements during the HNP interrupt handling
1144                  * can cause it to fail
1145                  */
1146 -               gotgctl = readl(hsotg->regs + GOTGCTL);
1147 +               gotgctl = dwc2_readl(hsotg->regs + GOTGCTL);
1148                 /*
1149                  * WA for 3.00a- HW is not setting cur_mode, even sometimes
1150                  * this does not help
1151 @@ -197,9 +197,9 @@ static void dwc2_handle_otg_intr(struct
1152                                  * interrupt does not get handled and Linux
1153                                  * complains loudly.
1154                                  */
1155 -                               gintmsk = readl(hsotg->regs + GINTMSK);
1156 +                               gintmsk = dwc2_readl(hsotg->regs + GINTMSK);
1157                                 gintmsk &= ~GINTSTS_SOF;
1158 -                               writel(gintmsk, hsotg->regs + GINTMSK);
1159 +                               dwc2_writel(gintmsk, hsotg->regs + GINTMSK);
1160
1161                                 /*
1162                                  * Call callback function with spin lock
1163 @@ -213,9 +213,9 @@ static void dwc2_handle_otg_intr(struct
1164                                 hsotg->op_state = OTG_STATE_B_HOST;
1165                         }
1166                 } else {
1167 -                       gotgctl = readl(hsotg->regs + GOTGCTL);
1168 +                       gotgctl = dwc2_readl(hsotg->regs + GOTGCTL);
1169                         gotgctl &= ~(GOTGCTL_HNPREQ | GOTGCTL_DEVHNPEN);
1170 -                       writel(gotgctl, hsotg->regs + GOTGCTL);
1171 +                       dwc2_writel(gotgctl, hsotg->regs + GOTGCTL);
1172                         dev_dbg(hsotg->dev, "HNP Failed\n");
1173                         dev_err(hsotg->dev,
1174                                 "Device Not Connected/Responding\n");
1175 @@ -241,9 +241,9 @@ static void dwc2_handle_otg_intr(struct
1176                         hsotg->op_state = OTG_STATE_A_PERIPHERAL;
1177                 } else {
1178                         /* Need to disable SOF interrupt immediately */
1179 -                       gintmsk = readl(hsotg->regs + GINTMSK);
1180 +                       gintmsk = dwc2_readl(hsotg->regs + GINTMSK);
1181                         gintmsk &= ~GINTSTS_SOF;
1182 -                       writel(gintmsk, hsotg->regs + GINTMSK);
1183 +                       dwc2_writel(gintmsk, hsotg->regs + GINTMSK);
1184                         spin_unlock(&hsotg->lock);
1185                         dwc2_hcd_start(hsotg);
1186                         spin_lock(&hsotg->lock);
1187 @@ -258,7 +258,7 @@ static void dwc2_handle_otg_intr(struct
1188                 dev_dbg(hsotg->dev, " ++OTG Interrupt: Debounce Done++\n");
1189
1190         /* Clear GOTGINT */
1191 -       writel(gotgint, hsotg->regs + GOTGINT);
1192 +       dwc2_writel(gotgint, hsotg->regs + GOTGINT);
1193  }
1194
1195  /**
1196 @@ -273,11 +273,11 @@ static void dwc2_handle_otg_intr(struct
1197   */
1198  static void dwc2_handle_conn_id_status_change_intr(struct dwc2_hsotg *hsotg)
1199  {
1200 -       u32 gintmsk = readl(hsotg->regs + GINTMSK);
1201 +       u32 gintmsk = dwc2_readl(hsotg->regs + GINTMSK);
1202
1203         /* Need to disable SOF interrupt immediately */
1204         gintmsk &= ~GINTSTS_SOF;
1205 -       writel(gintmsk, hsotg->regs + GINTMSK);
1206 +       dwc2_writel(gintmsk, hsotg->regs + GINTMSK);
1207
1208         dev_dbg(hsotg->dev, " ++Connector ID Status Change Interrupt++  (%s)\n",
1209                 dwc2_is_host_mode(hsotg) ? "Host" : "Device");
1210 @@ -292,7 +292,7 @@ static void dwc2_handle_conn_id_status_c
1211         spin_lock(&hsotg->lock);
1212
1213         /* Clear interrupt */
1214 -       writel(GINTSTS_CONIDSTSCHNG, hsotg->regs + GINTSTS);
1215 +       dwc2_writel(GINTSTS_CONIDSTSCHNG, hsotg->regs + GINTSTS);
1216  }
1217
1218  /**
1219 @@ -311,7 +311,7 @@ static void dwc2_handle_session_req_intr
1220         dev_dbg(hsotg->dev, "++Session Request Interrupt++\n");
1221
1222         /* Clear interrupt */
1223 -       writel(GINTSTS_SESSREQINT, hsotg->regs + GINTSTS);
1224 +       dwc2_writel(GINTSTS_SESSREQINT, hsotg->regs + GINTSTS);
1225  }
1226
1227  /*
1228 @@ -327,23 +327,23 @@ static void dwc2_handle_wakeup_detected_
1229         dev_dbg(hsotg->dev, "%s lxstate = %d\n", __func__, hsotg->lx_state);
1230
1231         if (dwc2_is_device_mode(hsotg)) {
1232 -               dev_dbg(hsotg->dev, "DSTS=0x%0x\n", readl(hsotg->regs + DSTS));
1233 +               dev_dbg(hsotg->dev, "DSTS=0x%0x\n", dwc2_readl(hsotg->regs + DSTS));
1234                 if (hsotg->lx_state == DWC2_L2) {
1235 -                       u32 dctl = readl(hsotg->regs + DCTL);
1236 +                       u32 dctl = dwc2_readl(hsotg->regs + DCTL);
1237
1238                         /* Clear Remote Wakeup Signaling */
1239                         dctl &= ~DCTL_RMTWKUPSIG;
1240 -                       writel(dctl, hsotg->regs + DCTL);
1241 +                       dwc2_writel(dctl, hsotg->regs + DCTL);
1242                 }
1243                 /* Change to L0 state */
1244                 hsotg->lx_state = DWC2_L0;
1245         } else {
1246                 if (hsotg->lx_state != DWC2_L1) {
1247 -                       u32 pcgcctl = readl(hsotg->regs + PCGCTL);
1248 +                       u32 pcgcctl = dwc2_readl(hsotg->regs + PCGCTL);
1249
1250                         /* Restart the Phy Clock */
1251                         pcgcctl &= ~PCGCTL_STOPPCLK;
1252 -                       writel(pcgcctl, hsotg->regs + PCGCTL);
1253 +                       dwc2_writel(pcgcctl, hsotg->regs + PCGCTL);
1254                         mod_timer(&hsotg->wkp_timer,
1255                                   jiffies + msecs_to_jiffies(71));
1256                 } else {
1257 @@ -353,7 +353,7 @@ static void dwc2_handle_wakeup_detected_
1258         }
1259
1260         /* Clear interrupt */
1261 -       writel(GINTSTS_WKUPINT, hsotg->regs + GINTSTS);
1262 +       dwc2_writel(GINTSTS_WKUPINT, hsotg->regs + GINTSTS);
1263  }
1264
1265  /*
1266 @@ -369,7 +369,7 @@ static void dwc2_handle_disconnect_intr(
1267         /* Change to L3 (OFF) state */
1268         hsotg->lx_state = DWC2_L3;
1269
1270 -       writel(GINTSTS_DISCONNINT, hsotg->regs + GINTSTS);
1271 +       dwc2_writel(GINTSTS_DISCONNINT, hsotg->regs + GINTSTS);
1272  }
1273
1274  /*
1275 @@ -391,7 +391,7 @@ static void dwc2_handle_usb_suspend_intr
1276                  * Check the Device status register to determine if the Suspend
1277                  * state is active
1278                  */
1279 -               dsts = readl(hsotg->regs + DSTS);
1280 +               dsts = dwc2_readl(hsotg->regs + DSTS);
1281                 dev_dbg(hsotg->dev, "DSTS=0x%0x\n", dsts);
1282                 dev_dbg(hsotg->dev,
1283                         "DSTS.Suspend Status=%d HWCFG4.Power Optimize=%d\n",
1284 @@ -413,7 +413,7 @@ static void dwc2_handle_usb_suspend_intr
1285         hsotg->lx_state = DWC2_L2;
1286
1287         /* Clear interrupt */
1288 -       writel(GINTSTS_USBSUSP, hsotg->regs + GINTSTS);
1289 +       dwc2_writel(GINTSTS_USBSUSP, hsotg->regs + GINTSTS);
1290  }
1291
1292  #define GINTMSK_COMMON (GINTSTS_WKUPINT | GINTSTS_SESSREQINT |         \
1293 @@ -431,9 +431,9 @@ static u32 dwc2_read_common_intr(struct
1294         u32 gahbcfg;
1295         u32 gintmsk_common = GINTMSK_COMMON;
1296
1297 -       gintsts = readl(hsotg->regs + GINTSTS);
1298 -       gintmsk = readl(hsotg->regs + GINTMSK);
1299 -       gahbcfg = readl(hsotg->regs + GAHBCFG);
1300 +       gintsts = dwc2_readl(hsotg->regs + GINTSTS);
1301 +       gintmsk = dwc2_readl(hsotg->regs + GINTMSK);
1302 +       gahbcfg = dwc2_readl(hsotg->regs + GAHBCFG);
1303
1304         /* If any common interrupts set */
1305         if (gintsts & gintmsk_common)
1306 --- a/drivers/usb/dwc2/gadget.c
1307 +++ b/drivers/usb/dwc2/gadget.c
1308 @@ -55,12 +55,12 @@ static inline struct s3c_hsotg *to_hsotg
1309
1310  static inline void __orr32(void __iomem *ptr, u32 val)
1311  {
1312 -       writel(readl(ptr) | val, ptr);
1313 +       dwc2_writel(dwc2_readl(ptr) | val, ptr);
1314  }
1315
1316  static inline void __bic32(void __iomem *ptr, u32 val)
1317  {
1318 -       writel(readl(ptr) & ~val, ptr);
1319 +       dwc2_writel(dwc2_readl(ptr) & ~val, ptr);
1320  }
1321
1322  /* forward decleration of functions */
1323 @@ -97,14 +97,14 @@ static inline bool using_dma(struct s3c_
1324   */
1325  static void s3c_hsotg_en_gsint(struct s3c_hsotg *hsotg, u32 ints)
1326  {
1327 -       u32 gsintmsk = readl(hsotg->regs + GINTMSK);
1328 +       u32 gsintmsk = dwc2_readl(hsotg->regs + GINTMSK);
1329         u32 new_gsintmsk;
1330
1331         new_gsintmsk = gsintmsk | ints;
1332
1333         if (new_gsintmsk != gsintmsk) {
1334                 dev_dbg(hsotg->dev, "gsintmsk now 0x%08x\n", new_gsintmsk);
1335 -               writel(new_gsintmsk, hsotg->regs + GINTMSK);
1336 +               dwc2_writel(new_gsintmsk, hsotg->regs + GINTMSK);
1337         }
1338  }
1339
1340 @@ -115,13 +115,13 @@ static void s3c_hsotg_en_gsint(struct s3
1341   */
1342  static void s3c_hsotg_disable_gsint(struct s3c_hsotg *hsotg, u32 ints)
1343  {
1344 -       u32 gsintmsk = readl(hsotg->regs + GINTMSK);
1345 +       u32 gsintmsk = dwc2_readl(hsotg->regs + GINTMSK);
1346         u32 new_gsintmsk;
1347
1348         new_gsintmsk = gsintmsk & ~ints;
1349
1350         if (new_gsintmsk != gsintmsk)
1351 -               writel(new_gsintmsk, hsotg->regs + GINTMSK);
1352 +               dwc2_writel(new_gsintmsk, hsotg->regs + GINTMSK);
1353  }
1354
1355  /**
1356 @@ -146,12 +146,12 @@ static void s3c_hsotg_ctrl_epint(struct
1357                 bit <<= 16;
1358
1359         local_irq_save(flags);
1360 -       daint = readl(hsotg->regs + DAINTMSK);
1361 +       daint = dwc2_readl(hsotg->regs + DAINTMSK);
1362         if (en)
1363                 daint |= bit;
1364         else
1365                 daint &= ~bit;
1366 -       writel(daint, hsotg->regs + DAINTMSK);
1367 +       dwc2_writel(daint, hsotg->regs + DAINTMSK);
1368         local_irq_restore(flags);
1369  }
1370
1371 @@ -169,8 +169,8 @@ static void s3c_hsotg_init_fifo(struct s
1372
1373         /* set FIFO sizes to 2048/1024 */
1374
1375 -       writel(2048, hsotg->regs + GRXFSIZ);
1376 -       writel((2048 << FIFOSIZE_STARTADDR_SHIFT) |
1377 +       dwc2_writel(2048, hsotg->regs + GRXFSIZ);
1378 +       dwc2_writel((2048 << FIFOSIZE_STARTADDR_SHIFT) |
1379                 (1024 << FIFOSIZE_DEPTH_SHIFT), hsotg->regs + GNPTXFSIZ);
1380
1381         /*
1382 @@ -200,7 +200,7 @@ static void s3c_hsotg_init_fifo(struct s
1383                           "insufficient fifo memory");
1384                 addr += size;
1385
1386 -               writel(val, hsotg->regs + DPTXFSIZN(ep));
1387 +               dwc2_writel(val, hsotg->regs + DPTXFSIZN(ep));
1388         }
1389         /* 768*4=3072 bytes FIFO length */
1390         size = 768;
1391 @@ -211,7 +211,7 @@ static void s3c_hsotg_init_fifo(struct s
1392                           "insufficient fifo memory");
1393                 addr += size;
1394
1395 -               writel(val, hsotg->regs + DPTXFSIZN(ep));
1396 +               dwc2_writel(val, hsotg->regs + DPTXFSIZN(ep));
1397         }
1398
1399         /*
1400 @@ -219,13 +219,13 @@ static void s3c_hsotg_init_fifo(struct s
1401          * all fifos are flushed before continuing
1402          */
1403
1404 -       writel(GRSTCTL_TXFNUM(0x10) | GRSTCTL_TXFFLSH |
1405 +       dwc2_writel(GRSTCTL_TXFNUM(0x10) | GRSTCTL_TXFFLSH |
1406                GRSTCTL_RXFFLSH, hsotg->regs + GRSTCTL);
1407
1408         /* wait until the fifos are both flushed */
1409         timeout = 100;
1410         while (1) {
1411 -               val = readl(hsotg->regs + GRSTCTL);
1412 +               val = dwc2_readl(hsotg->regs + GRSTCTL);
1413
1414                 if ((val & (GRSTCTL_TXFFLSH | GRSTCTL_RXFFLSH)) == 0)
1415                         break;
1416 @@ -317,7 +317,7 @@ static int s3c_hsotg_write_fifo(struct s
1417                                 struct s3c_hsotg_req *hs_req)
1418  {
1419         bool periodic = is_ep_periodic(hs_ep);
1420 -       u32 gnptxsts = readl(hsotg->regs + GNPTXSTS);
1421 +       u32 gnptxsts = dwc2_readl(hsotg->regs + GNPTXSTS);
1422         int buf_pos = hs_req->req.actual;
1423         int to_write = hs_ep->size_loaded;
1424         void *data;
1425 @@ -332,7 +332,7 @@ static int s3c_hsotg_write_fifo(struct s
1426                 return 0;
1427
1428         if (periodic && !hsotg->dedicated_fifos) {
1429 -               u32 epsize = readl(hsotg->regs + DIEPTSIZ(hs_ep->index));
1430 +               u32 epsize = dwc2_readl(hsotg->regs + DIEPTSIZ(hs_ep->index));
1431                 int size_left;
1432                 int size_done;
1433
1434 @@ -373,7 +373,7 @@ static int s3c_hsotg_write_fifo(struct s
1435                         return -ENOSPC;
1436                 }
1437         } else if (hsotg->dedicated_fifos && hs_ep->index != 0) {
1438 -               can_write = readl(hsotg->regs + DTXFSTS(hs_ep->index));
1439 +               can_write = dwc2_readl(hsotg->regs + DTXFSTS(hs_ep->index));
1440
1441                 can_write &= 0xffff;
1442                 can_write *= 4;
1443 @@ -550,11 +550,11 @@ static void s3c_hsotg_start_req(struct s
1444         epsize_reg = dir_in ? DIEPTSIZ(index) : DOEPTSIZ(index);
1445
1446         dev_dbg(hsotg->dev, "%s: DxEPCTL=0x%08x, ep %d, dir %s\n",
1447 -               __func__, readl(hsotg->regs + epctrl_reg), index,
1448 +               __func__, dwc2_readl(hsotg->regs + epctrl_reg), index,
1449                 hs_ep->dir_in ? "in" : "out");
1450
1451         /* If endpoint is stalled, we will restart request later */
1452 -       ctrl = readl(hsotg->regs + epctrl_reg);
1453 +       ctrl = dwc2_readl(hsotg->regs + epctrl_reg);
1454
1455         if (ctrl & DXEPCTL_STALL) {
1456                 dev_warn(hsotg->dev, "%s: ep%d is stalled\n", __func__, index);
1457 @@ -622,7 +622,7 @@ static void s3c_hsotg_start_req(struct s
1458         hs_ep->req = hs_req;
1459
1460         /* write size / packets */
1461 -       writel(epsize, hsotg->regs + epsize_reg);
1462 +       dwc2_writel(epsize, hsotg->regs + epsize_reg);
1463
1464         if (using_dma(hsotg) && !continuing) {
1465                 unsigned int dma_reg;
1466 @@ -633,7 +633,7 @@ static void s3c_hsotg_start_req(struct s
1467                  */
1468
1469                 dma_reg = dir_in ? DIEPDMA(index) : DOEPDMA(index);
1470 -               writel(ureq->dma, hsotg->regs + dma_reg);
1471 +               dwc2_writel(ureq->dma, hsotg->regs + dma_reg);
1472
1473                 dev_dbg(hsotg->dev, "%s: %pad => 0x%08x\n",
1474                         __func__, &ureq->dma, dma_reg);
1475 @@ -652,7 +652,7 @@ static void s3c_hsotg_start_req(struct s
1476
1477
1478         dev_dbg(hsotg->dev, "%s: DxEPCTL=0x%08x\n", __func__, ctrl);
1479 -       writel(ctrl, hsotg->regs + epctrl_reg);
1480 +       dwc2_writel(ctrl, hsotg->regs + epctrl_reg);
1481
1482         /*
1483          * set these, it seems that DMA support increments past the end
1484 @@ -674,7 +674,7 @@ static void s3c_hsotg_start_req(struct s
1485          * to debugging to see what is going on.
1486          */
1487         if (dir_in)
1488 -               writel(DIEPMSK_INTKNTXFEMPMSK,
1489 +               dwc2_writel(DIEPMSK_INTKNTXFEMPMSK,
1490                        hsotg->regs + DIEPINT(index));
1491
1492         /*
1493 @@ -683,13 +683,13 @@ static void s3c_hsotg_start_req(struct s
1494          */
1495
1496         /* check ep is enabled */
1497 -       if (!(readl(hsotg->regs + epctrl_reg) & DXEPCTL_EPENA))
1498 +       if (!(dwc2_readl(hsotg->regs + epctrl_reg) & DXEPCTL_EPENA))
1499                 dev_warn(hsotg->dev,
1500                          "ep%d: failed to become enabled (DXEPCTL=0x%08x)?\n",
1501 -                        index, readl(hsotg->regs + epctrl_reg));
1502 +                        index, dwc2_readl(hsotg->regs + epctrl_reg));
1503
1504         dev_dbg(hsotg->dev, "%s: DXEPCTL=0x%08x\n",
1505 -               __func__, readl(hsotg->regs + epctrl_reg));
1506 +               __func__, dwc2_readl(hsotg->regs + epctrl_reg));
1507
1508         /* enable ep interrupts */
1509         s3c_hsotg_ctrl_epint(hsotg, hs_ep->index, hs_ep->dir_in, 1);
1510 @@ -1051,14 +1051,14 @@ static void s3c_hsotg_stall_ep0(struct s
1511          * taken effect, so no need to clear later.
1512          */
1513
1514 -       ctrl = readl(hsotg->regs + reg);
1515 +       ctrl = dwc2_readl(hsotg->regs + reg);
1516         ctrl |= DXEPCTL_STALL;
1517         ctrl |= DXEPCTL_CNAK;
1518 -       writel(ctrl, hsotg->regs + reg);
1519 +       dwc2_writel(ctrl, hsotg->regs + reg);
1520
1521         dev_dbg(hsotg->dev,
1522                 "written DXEPCTL=0x%08x to %08x (DXEPCTL=0x%08x)\n",
1523 -               ctrl, reg, readl(hsotg->regs + reg));
1524 +               ctrl, reg, dwc2_readl(hsotg->regs + reg));
1525
1526          /*
1527           * complete won't be called, so we enqueue
1528 @@ -1108,11 +1108,11 @@ static void s3c_hsotg_process_control(st
1529                 switch (ctrl->bRequest) {
1530                 case USB_REQ_SET_ADDRESS:
1531                         s3c_hsotg_disconnect(hsotg);
1532 -                       dcfg = readl(hsotg->regs + DCFG);
1533 +                       dcfg = dwc2_readl(hsotg->regs + DCFG);
1534                         dcfg &= ~DCFG_DEVADDR_MASK;
1535                         dcfg |= (le16_to_cpu(ctrl->wValue) <<
1536                                  DCFG_DEVADDR_SHIFT) & DCFG_DEVADDR_MASK;
1537 -                       writel(dcfg, hsotg->regs + DCFG);
1538 +                       dwc2_writel(dcfg, hsotg->regs + DCFG);
1539
1540                         dev_info(hsotg->dev, "new address %d\n", ctrl->wValue);
1541
1542 @@ -1302,7 +1302,7 @@ static void s3c_hsotg_rx_data(struct s3c
1543
1544
1545         if (!hs_req) {
1546 -               u32 epctl = readl(hsotg->regs + DOEPCTL(ep_idx));
1547 +               u32 epctl = dwc2_readl(hsotg->regs + DOEPCTL(ep_idx));
1548                 int ptr;
1549
1550                 dev_warn(hsotg->dev,
1551 @@ -1311,7 +1311,7 @@ static void s3c_hsotg_rx_data(struct s3c
1552
1553                 /* dump the data from the FIFO, we've nothing we can do */
1554                 for (ptr = 0; ptr < size; ptr += 4)
1555 -                       (void)readl(fifo);
1556 +                       (void)dwc2_readl(fifo);
1557
1558                 return;
1559         }
1560 @@ -1378,14 +1378,14 @@ static void s3c_hsotg_send_zlp(struct s3
1561         dev_dbg(hsotg->dev, "sending zero-length packet\n");
1562
1563         /* issue a zero-sized packet to terminate this */
1564 -       writel(DXEPTSIZ_MC(1) | DXEPTSIZ_PKTCNT(1) |
1565 +       dwc2_writel(DXEPTSIZ_MC(1) | DXEPTSIZ_PKTCNT(1) |
1566                DXEPTSIZ_XFERSIZE(0), hsotg->regs + DIEPTSIZ(0));
1567
1568 -       ctrl = readl(hsotg->regs + DIEPCTL0);
1569 +       ctrl = dwc2_readl(hsotg->regs + DIEPCTL0);
1570         ctrl |= DXEPCTL_CNAK;  /* clear NAK set by core */
1571         ctrl |= DXEPCTL_EPENA; /* ensure ep enabled */
1572         ctrl |= DXEPCTL_USBACTEP;
1573 -       writel(ctrl, hsotg->regs + DIEPCTL0);
1574 +       dwc2_writel(ctrl, hsotg->regs + DIEPCTL0);
1575  }
1576
1577  /**
1578 @@ -1401,7 +1401,7 @@ static void s3c_hsotg_send_zlp(struct s3
1579  static void s3c_hsotg_handle_outdone(struct s3c_hsotg *hsotg,
1580                                      int epnum, bool was_setup)
1581  {
1582 -       u32 epsize = readl(hsotg->regs + DOEPTSIZ(epnum));
1583 +       u32 epsize = dwc2_readl(hsotg->regs + DOEPTSIZ(epnum));
1584         struct s3c_hsotg_ep *hs_ep = &hsotg->eps[epnum];
1585         struct s3c_hsotg_req *hs_req = hs_ep->req;
1586         struct usb_request *req = &hs_req->req;
1587 @@ -1475,7 +1475,7 @@ static u32 s3c_hsotg_read_frameno(struct
1588  {
1589         u32 dsts;
1590
1591 -       dsts = readl(hsotg->regs + DSTS);
1592 +       dsts = dwc2_readl(hsotg->regs + DSTS);
1593         dsts &= DSTS_SOFFN_MASK;
1594         dsts >>= DSTS_SOFFN_SHIFT;
1595
1596 @@ -1500,7 +1500,7 @@ static u32 s3c_hsotg_read_frameno(struct
1597   */
1598  static void s3c_hsotg_handle_rx(struct s3c_hsotg *hsotg)
1599  {
1600 -       u32 grxstsr = readl(hsotg->regs + GRXSTSP);
1601 +       u32 grxstsr = dwc2_readl(hsotg->regs + GRXSTSP);
1602         u32 epnum, status, size;
1603
1604         WARN_ON(using_dma(hsotg));
1605 @@ -1532,7 +1532,7 @@ static void s3c_hsotg_handle_rx(struct s
1606                 dev_dbg(hsotg->dev,
1607                         "SetupDone (Frame=0x%08x, DOPEPCTL=0x%08x)\n",
1608                         s3c_hsotg_read_frameno(hsotg),
1609 -                       readl(hsotg->regs + DOEPCTL(0)));
1610 +                       dwc2_readl(hsotg->regs + DOEPCTL(0)));
1611
1612                 s3c_hsotg_handle_outdone(hsotg, epnum, true);
1613                 break;
1614 @@ -1545,7 +1545,7 @@ static void s3c_hsotg_handle_rx(struct s
1615                 dev_dbg(hsotg->dev,
1616                         "SetupRX (Frame=0x%08x, DOPEPCTL=0x%08x)\n",
1617                         s3c_hsotg_read_frameno(hsotg),
1618 -                       readl(hsotg->regs + DOEPCTL(0)));
1619 +                       dwc2_readl(hsotg->regs + DOEPCTL(0)));
1620
1621                 s3c_hsotg_rx_data(hsotg, epnum, size);
1622                 break;
1623 @@ -1622,16 +1622,16 @@ static void s3c_hsotg_set_ep_maxpacket(s
1624          * if one of the directions may not be in use.
1625          */
1626
1627 -       reg = readl(regs + DIEPCTL(ep));
1628 +       reg = dwc2_readl(regs + DIEPCTL(ep));
1629         reg &= ~DXEPCTL_MPS_MASK;
1630         reg |= mpsval;
1631 -       writel(reg, regs + DIEPCTL(ep));
1632 +       dwc2_writel(reg, regs + DIEPCTL(ep));
1633
1634         if (ep) {
1635 -               reg = readl(regs + DOEPCTL(ep));
1636 +               reg = dwc2_readl(regs + DOEPCTL(ep));
1637                 reg &= ~DXEPCTL_MPS_MASK;
1638                 reg |= mpsval;
1639 -               writel(reg, regs + DOEPCTL(ep));
1640 +               dwc2_writel(reg, regs + DOEPCTL(ep));
1641         }
1642
1643         return;
1644 @@ -1650,14 +1650,14 @@ static void s3c_hsotg_txfifo_flush(struc
1645         int timeout;
1646         int val;
1647
1648 -       writel(GRSTCTL_TXFNUM(idx) | GRSTCTL_TXFFLSH,
1649 +       dwc2_writel(GRSTCTL_TXFNUM(idx) | GRSTCTL_TXFFLSH,
1650                 hsotg->regs + GRSTCTL);
1651
1652         /* wait until the fifo is flushed */
1653         timeout = 100;
1654
1655         while (1) {
1656 -               val = readl(hsotg->regs + GRSTCTL);
1657 +               val = dwc2_readl(hsotg->regs + GRSTCTL);
1658
1659                 if ((val & (GRSTCTL_TXFFLSH)) == 0)
1660                         break;
1661 @@ -1718,7 +1718,7 @@ static void s3c_hsotg_complete_in(struct
1662                                   struct s3c_hsotg_ep *hs_ep)
1663  {
1664         struct s3c_hsotg_req *hs_req = hs_ep->req;
1665 -       u32 epsize = readl(hsotg->regs + DIEPTSIZ(hs_ep->index));
1666 +       u32 epsize = dwc2_readl(hsotg->regs + DIEPTSIZ(hs_ep->index));
1667         int size_left, size_done;
1668
1669         if (!hs_req) {
1670 @@ -1801,11 +1801,11 @@ static void s3c_hsotg_epint(struct s3c_h
1671         u32 ints;
1672         u32 ctrl;
1673
1674 -       ints = readl(hsotg->regs + epint_reg);
1675 -       ctrl = readl(hsotg->regs + epctl_reg);
1676 +       ints = dwc2_readl(hsotg->regs + epint_reg);
1677 +       ctrl = dwc2_readl(hsotg->regs + epctl_reg);
1678
1679         /* Clear endpoint interrupts */
1680 -       writel(ints, hsotg->regs + epint_reg);
1681 +       dwc2_writel(ints, hsotg->regs + epint_reg);
1682
1683         dev_dbg(hsotg->dev, "%s: ep%d(%s) DxEPINT=0x%08x\n",
1684                 __func__, idx, dir_in ? "in" : "out", ints);
1685 @@ -1816,13 +1816,13 @@ static void s3c_hsotg_epint(struct s3c_h
1686                                 ctrl |= DXEPCTL_SETEVENFR;
1687                         else
1688                                 ctrl |= DXEPCTL_SETODDFR;
1689 -                       writel(ctrl, hsotg->regs + epctl_reg);
1690 +                       dwc2_writel(ctrl, hsotg->regs + epctl_reg);
1691                 }
1692
1693                 dev_dbg(hsotg->dev,
1694                         "%s: XferCompl: DxEPCTL=0x%08x, DXEPTSIZ=%08x\n",
1695 -                       __func__, readl(hsotg->regs + epctl_reg),
1696 -                       readl(hsotg->regs + epsiz_reg));
1697 +                       __func__, dwc2_readl(hsotg->regs + epctl_reg),
1698 +                       dwc2_readl(hsotg->regs + epsiz_reg));
1699
1700                 /*
1701                  * we get OutDone from the FIFO, so we only need to look
1702 @@ -1847,16 +1847,16 @@ static void s3c_hsotg_epint(struct s3c_h
1703                 dev_dbg(hsotg->dev, "%s: EPDisbld\n", __func__);
1704
1705                 if (dir_in) {
1706 -                       int epctl = readl(hsotg->regs + epctl_reg);
1707 +                       int epctl = dwc2_readl(hsotg->regs + epctl_reg);
1708
1709                         s3c_hsotg_txfifo_flush(hsotg, hs_ep->fifo_index);
1710
1711                         if ((epctl & DXEPCTL_STALL) &&
1712                                 (epctl & DXEPCTL_EPTYPE_BULK)) {
1713 -                               int dctl = readl(hsotg->regs + DCTL);
1714 +                               int dctl = dwc2_readl(hsotg->regs + DCTL);
1715
1716                                 dctl |= DCTL_CGNPINNAK;
1717 -                               writel(dctl, hsotg->regs + DCTL);
1718 +                               dwc2_writel(dctl, hsotg->regs + DCTL);
1719                         }
1720                 }
1721         }
1722 @@ -1918,7 +1918,7 @@ static void s3c_hsotg_epint(struct s3c_h
1723   */
1724  static void s3c_hsotg_irq_enumdone(struct s3c_hsotg *hsotg)
1725  {
1726 -       u32 dsts = readl(hsotg->regs + DSTS);
1727 +       u32 dsts = dwc2_readl(hsotg->regs + DSTS);
1728         int ep0_mps = 0, ep_mps = 8;
1729
1730         /*
1731 @@ -1979,8 +1979,8 @@ static void s3c_hsotg_irq_enumdone(struc
1732         s3c_hsotg_enqueue_setup(hsotg);
1733
1734         dev_dbg(hsotg->dev, "EP0: DIEPCTL0=0x%08x, DOEPCTL0=0x%08x\n",
1735 -               readl(hsotg->regs + DIEPCTL0),
1736 -               readl(hsotg->regs + DOEPCTL0));
1737 +               dwc2_readl(hsotg->regs + DIEPCTL0),
1738 +               dwc2_readl(hsotg->regs + DOEPCTL0));
1739  }
1740
1741  /**
1742 @@ -2014,7 +2014,7 @@ static void kill_all_requests(struct s3c
1743         }
1744         if (!hsotg->dedicated_fifos)
1745                 return;
1746 -       size = (readl(hsotg->regs + DTXFSTS(ep->index)) & 0xffff) * 4;
1747 +       size = (dwc2_readl(hsotg->regs + DTXFSTS(ep->index)) & 0xffff) * 4;
1748         if (size < ep->fifo_size)
1749                 s3c_hsotg_txfifo_flush(hsotg, ep->fifo_index);
1750  }
1751 @@ -2084,11 +2084,11 @@ static int s3c_hsotg_corereset(struct s3
1752         dev_dbg(hsotg->dev, "resetting core\n");
1753
1754         /* issue soft reset */
1755 -       writel(GRSTCTL_CSFTRST, hsotg->regs + GRSTCTL);
1756 +       dwc2_writel(GRSTCTL_CSFTRST, hsotg->regs + GRSTCTL);
1757
1758         timeout = 10000;
1759         do {
1760 -               grstctl = readl(hsotg->regs + GRSTCTL);
1761 +               grstctl = dwc2_readl(hsotg->regs + GRSTCTL);
1762         } while ((grstctl & GRSTCTL_CSFTRST) && timeout-- > 0);
1763
1764         if (grstctl & GRSTCTL_CSFTRST) {
1765 @@ -2099,7 +2099,7 @@ static int s3c_hsotg_corereset(struct s3
1766         timeout = 10000;
1767
1768         while (1) {
1769 -               u32 grstctl = readl(hsotg->regs + GRSTCTL);
1770 +               u32 grstctl = dwc2_readl(hsotg->regs + GRSTCTL);
1771
1772                 if (timeout-- < 0) {
1773                         dev_info(hsotg->dev,
1774 @@ -2134,22 +2134,22 @@ static void s3c_hsotg_core_init(struct s
1775          */
1776
1777         /* set the PLL on, remove the HNP/SRP and set the PHY */
1778 -       writel(hsotg->phyif | GUSBCFG_TOUTCAL(7) |
1779 +       dwc2_writel(hsotg->phyif | GUSBCFG_TOUTCAL(7) |
1780                (0x5 << 10), hsotg->regs + GUSBCFG);
1781
1782         s3c_hsotg_init_fifo(hsotg);
1783
1784         __orr32(hsotg->regs + DCTL, DCTL_SFTDISCON);
1785
1786 -       writel(1 << 18 | DCFG_DEVSPD_HS,  hsotg->regs + DCFG);
1787 +       dwc2_writel(1 << 18 | DCFG_DEVSPD_HS,  hsotg->regs + DCFG);
1788
1789         /* Clear any pending OTG interrupts */
1790 -       writel(0xffffffff, hsotg->regs + GOTGINT);
1791 +       dwc2_writel(0xffffffff, hsotg->regs + GOTGINT);
1792
1793         /* Clear any pending interrupts */
1794 -       writel(0xffffffff, hsotg->regs + GINTSTS);
1795 +       dwc2_writel(0xffffffff, hsotg->regs + GINTSTS);
1796
1797 -       writel(GINTSTS_ERLYSUSP | GINTSTS_SESSREQINT |
1798 +       dwc2_writel(GINTSTS_ERLYSUSP | GINTSTS_SESSREQINT |
1799                 GINTSTS_GOUTNAKEFF | GINTSTS_GINNAKEFF |
1800                 GINTSTS_CONIDSTSCHNG | GINTSTS_USBRST |
1801                 GINTSTS_ENUMDONE | GINTSTS_OTGINT |
1802 @@ -2157,11 +2157,11 @@ static void s3c_hsotg_core_init(struct s
1803                 hsotg->regs + GINTMSK);
1804
1805         if (using_dma(hsotg))
1806 -               writel(GAHBCFG_GLBL_INTR_EN | GAHBCFG_DMA_EN |
1807 +               dwc2_writel(GAHBCFG_GLBL_INTR_EN | GAHBCFG_DMA_EN |
1808                        GAHBCFG_HBSTLEN_INCR4,
1809                        hsotg->regs + GAHBCFG);
1810         else
1811 -               writel(((hsotg->dedicated_fifos) ? (GAHBCFG_NP_TXF_EMP_LVL |
1812 +               dwc2_writel(((hsotg->dedicated_fifos) ? (GAHBCFG_NP_TXF_EMP_LVL |
1813                                                     GAHBCFG_P_TXF_EMP_LVL) : 0) |
1814                        GAHBCFG_GLBL_INTR_EN,
1815                        hsotg->regs + GAHBCFG);
1816 @@ -2172,7 +2172,7 @@ static void s3c_hsotg_core_init(struct s
1817          * interrupts.
1818          */
1819
1820 -       writel(((hsotg->dedicated_fifos) ? DIEPMSK_TXFIFOEMPTY |
1821 +       dwc2_writel(((hsotg->dedicated_fifos) ? DIEPMSK_TXFIFOEMPTY |
1822                 DIEPMSK_INTKNTXFEMPMSK : 0) |
1823                 DIEPMSK_EPDISBLDMSK | DIEPMSK_XFERCOMPLMSK |
1824                 DIEPMSK_TIMEOUTMSK | DIEPMSK_AHBERRMSK |
1825 @@ -2183,17 +2183,17 @@ static void s3c_hsotg_core_init(struct s
1826          * don't need XferCompl, we get that from RXFIFO in slave mode. In
1827          * DMA mode we may need this.
1828          */
1829 -       writel((using_dma(hsotg) ? (DIEPMSK_XFERCOMPLMSK |
1830 +       dwc2_writel((using_dma(hsotg) ? (DIEPMSK_XFERCOMPLMSK |
1831                                     DIEPMSK_TIMEOUTMSK) : 0) |
1832                 DOEPMSK_EPDISBLDMSK | DOEPMSK_AHBERRMSK |
1833                 DOEPMSK_SETUPMSK,
1834                 hsotg->regs + DOEPMSK);
1835
1836 -       writel(0, hsotg->regs + DAINTMSK);
1837 +       dwc2_writel(0, hsotg->regs + DAINTMSK);
1838
1839         dev_dbg(hsotg->dev, "EP0: DIEPCTL0=0x%08x, DOEPCTL0=0x%08x\n",
1840 -               readl(hsotg->regs + DIEPCTL0),
1841 -               readl(hsotg->regs + DOEPCTL0));
1842 +               dwc2_readl(hsotg->regs + DIEPCTL0),
1843 +               dwc2_readl(hsotg->regs + DOEPCTL0));
1844
1845         /* enable in and out endpoint interrupts */
1846         s3c_hsotg_en_gsint(hsotg, GINTSTS_OEPINT | GINTSTS_IEPINT);
1847 @@ -2214,7 +2214,7 @@ static void s3c_hsotg_core_init(struct s
1848         udelay(10);  /* see openiboot */
1849         __bic32(hsotg->regs + DCTL, DCTL_PWRONPRGDONE);
1850
1851 -       dev_dbg(hsotg->dev, "DCTL=0x%08x\n", readl(hsotg->regs + DCTL));
1852 +       dev_dbg(hsotg->dev, "DCTL=0x%08x\n", dwc2_readl(hsotg->regs + DCTL));
1853
1854         /*
1855          * DxEPCTL_USBActEp says RO in manual, but seems to be set by
1856 @@ -2222,26 +2222,26 @@ static void s3c_hsotg_core_init(struct s
1857          */
1858
1859         /* set to read 1 8byte packet */
1860 -       writel(DXEPTSIZ_MC(1) | DXEPTSIZ_PKTCNT(1) |
1861 +       dwc2_writel(DXEPTSIZ_MC(1) | DXEPTSIZ_PKTCNT(1) |
1862                DXEPTSIZ_XFERSIZE(8), hsotg->regs + DOEPTSIZ0);
1863
1864 -       writel(s3c_hsotg_ep0_mps(hsotg->eps[0].ep.maxpacket) |
1865 +       dwc2_writel(s3c_hsotg_ep0_mps(hsotg->eps[0].ep.maxpacket) |
1866                DXEPCTL_CNAK | DXEPCTL_EPENA |
1867                DXEPCTL_USBACTEP,
1868                hsotg->regs + DOEPCTL0);
1869
1870         /* enable, but don't activate EP0in */
1871 -       writel(s3c_hsotg_ep0_mps(hsotg->eps[0].ep.maxpacket) |
1872 +       dwc2_writel(s3c_hsotg_ep0_mps(hsotg->eps[0].ep.maxpacket) |
1873                DXEPCTL_USBACTEP, hsotg->regs + DIEPCTL0);
1874
1875         s3c_hsotg_enqueue_setup(hsotg);
1876
1877         dev_dbg(hsotg->dev, "EP0: DIEPCTL0=0x%08x, DOEPCTL0=0x%08x\n",
1878 -               readl(hsotg->regs + DIEPCTL0),
1879 -               readl(hsotg->regs + DOEPCTL0));
1880 +               dwc2_readl(hsotg->regs + DIEPCTL0),
1881 +               dwc2_readl(hsotg->regs + DOEPCTL0));
1882
1883         /* clear global NAKs */
1884 -       writel(DCTL_CGOUTNAK | DCTL_CGNPINNAK,
1885 +       dwc2_writel(DCTL_CGOUTNAK | DCTL_CGNPINNAK,
1886                hsotg->regs + DCTL);
1887
1888         /* must be at-least 3ms to allow bus to see disconnect */
1889 @@ -2265,8 +2265,8 @@ static irqreturn_t s3c_hsotg_irq(int irq
1890
1891         spin_lock(&hsotg->lock);
1892  irq_retry:
1893 -       gintsts = readl(hsotg->regs + GINTSTS);
1894 -       gintmsk = readl(hsotg->regs + GINTMSK);
1895 +       gintsts = dwc2_readl(hsotg->regs + GINTSTS);
1896 +       gintmsk = dwc2_readl(hsotg->regs + GINTMSK);
1897
1898         dev_dbg(hsotg->dev, "%s: %08x %08x (%08x) retry %d\n",
1899                 __func__, gintsts, gintsts & gintmsk, gintmsk, retry_count);
1900 @@ -2274,35 +2274,35 @@ irq_retry:
1901         gintsts &= gintmsk;
1902
1903         if (gintsts & GINTSTS_OTGINT) {
1904 -               u32 otgint = readl(hsotg->regs + GOTGINT);
1905 +               u32 otgint = dwc2_readl(hsotg->regs + GOTGINT);
1906
1907                 dev_info(hsotg->dev, "OTGInt: %08x\n", otgint);
1908
1909 -               writel(otgint, hsotg->regs + GOTGINT);
1910 +               dwc2_writel(otgint, hsotg->regs + GOTGINT);
1911         }
1912
1913         if (gintsts & GINTSTS_SESSREQINT) {
1914                 dev_dbg(hsotg->dev, "%s: SessReqInt\n", __func__);
1915 -               writel(GINTSTS_SESSREQINT, hsotg->regs + GINTSTS);
1916 +               dwc2_writel(GINTSTS_SESSREQINT, hsotg->regs + GINTSTS);
1917         }
1918
1919         if (gintsts & GINTSTS_ENUMDONE) {
1920 -               writel(GINTSTS_ENUMDONE, hsotg->regs + GINTSTS);
1921 +               dwc2_writel(GINTSTS_ENUMDONE, hsotg->regs + GINTSTS);
1922
1923                 s3c_hsotg_irq_enumdone(hsotg);
1924         }
1925
1926         if (gintsts & GINTSTS_CONIDSTSCHNG) {
1927                 dev_dbg(hsotg->dev, "ConIDStsChg (DSTS=0x%08x, GOTCTL=%08x)\n",
1928 -                       readl(hsotg->regs + DSTS),
1929 -                       readl(hsotg->regs + GOTGCTL));
1930 +                       dwc2_readl(hsotg->regs + DSTS),
1931 +                       dwc2_readl(hsotg->regs + GOTGCTL));
1932
1933 -               writel(GINTSTS_CONIDSTSCHNG, hsotg->regs + GINTSTS);
1934 +               dwc2_writel(GINTSTS_CONIDSTSCHNG, hsotg->regs + GINTSTS);
1935         }
1936
1937         if (gintsts & (GINTSTS_OEPINT | GINTSTS_IEPINT)) {
1938 -               u32 daint = readl(hsotg->regs + DAINT);
1939 -               u32 daintmsk = readl(hsotg->regs + DAINTMSK);
1940 +               u32 daint = dwc2_readl(hsotg->regs + DAINT);
1941 +               u32 daintmsk = dwc2_readl(hsotg->regs + DAINTMSK);
1942                 u32 daint_out, daint_in;
1943                 int ep;
1944
1945 @@ -2325,13 +2325,13 @@ irq_retry:
1946
1947         if (gintsts & GINTSTS_USBRST) {
1948
1949 -               u32 usb_status = readl(hsotg->regs + GOTGCTL);
1950 +               u32 usb_status = dwc2_readl(hsotg->regs + GOTGCTL);
1951
1952                 dev_dbg(hsotg->dev, "%s: USBRst\n", __func__);
1953                 dev_dbg(hsotg->dev, "GNPTXSTS=%08x\n",
1954 -                       readl(hsotg->regs + GNPTXSTS));
1955 +                       dwc2_readl(hsotg->regs + GNPTXSTS));
1956
1957 -               writel(GINTSTS_USBRST, hsotg->regs + GINTSTS);
1958 +               dwc2_writel(GINTSTS_USBRST, hsotg->regs + GINTSTS);
1959
1960                 if (usb_status & GOTGCTL_BSESVLD) {
1961                         if (time_after(jiffies, hsotg->last_rst +
1962 @@ -2382,26 +2382,26 @@ irq_retry:
1963
1964         if (gintsts & GINTSTS_MODEMIS) {
1965                 dev_warn(hsotg->dev, "warning, mode mismatch triggered\n");
1966 -               writel(GINTSTS_MODEMIS, hsotg->regs + GINTSTS);
1967 +               dwc2_writel(GINTSTS_MODEMIS, hsotg->regs + GINTSTS);
1968         }
1969
1970         if (gintsts & GINTSTS_USBSUSP) {
1971                 dev_info(hsotg->dev, "GINTSTS_USBSusp\n");
1972 -               writel(GINTSTS_USBSUSP, hsotg->regs + GINTSTS);
1973 +               dwc2_writel(GINTSTS_USBSUSP, hsotg->regs + GINTSTS);
1974
1975                 call_gadget(hsotg, suspend);
1976         }
1977
1978         if (gintsts & GINTSTS_WKUPINT) {
1979                 dev_info(hsotg->dev, "GINTSTS_WkUpIn\n");
1980 -               writel(GINTSTS_WKUPINT, hsotg->regs + GINTSTS);
1981 +               dwc2_writel(GINTSTS_WKUPINT, hsotg->regs + GINTSTS);
1982
1983                 call_gadget(hsotg, resume);
1984         }
1985
1986         if (gintsts & GINTSTS_ERLYSUSP) {
1987                 dev_dbg(hsotg->dev, "GINTSTS_ErlySusp\n");
1988 -               writel(GINTSTS_ERLYSUSP, hsotg->regs + GINTSTS);
1989 +               dwc2_writel(GINTSTS_ERLYSUSP, hsotg->regs + GINTSTS);
1990         }
1991
1992         /*
1993 @@ -2413,7 +2413,7 @@ irq_retry:
1994         if (gintsts & GINTSTS_GOUTNAKEFF) {
1995                 dev_info(hsotg->dev, "GOUTNakEff triggered\n");
1996
1997 -               writel(DCTL_CGOUTNAK, hsotg->regs + DCTL);
1998 +               dwc2_writel(DCTL_CGOUTNAK, hsotg->regs + DCTL);
1999
2000                 s3c_hsotg_dump(hsotg);
2001         }
2002 @@ -2421,7 +2421,7 @@ irq_retry:
2003         if (gintsts & GINTSTS_GINNAKEFF) {
2004                 dev_info(hsotg->dev, "GINNakEff triggered\n");
2005
2006 -               writel(DCTL_CGNPINNAK, hsotg->regs + DCTL);
2007 +               dwc2_writel(DCTL_CGNPINNAK, hsotg->regs + DCTL);
2008
2009                 s3c_hsotg_dump(hsotg);
2010         }
2011 @@ -2479,7 +2479,7 @@ static int s3c_hsotg_ep_enable(struct us
2012         /* note, we handle this here instead of s3c_hsotg_set_ep_maxpacket */
2013
2014         epctrl_reg = dir_in ? DIEPCTL(index) : DOEPCTL(index);
2015 -       epctrl = readl(hsotg->regs + epctrl_reg);
2016 +       epctrl = dwc2_readl(hsotg->regs + epctrl_reg);
2017
2018         dev_dbg(hsotg->dev, "%s: read DxEPCTL=0x%08x from 0x%08x\n",
2019                 __func__, epctrl, epctrl_reg);
2020 @@ -2550,7 +2550,7 @@ static int s3c_hsotg_ep_enable(struct us
2021                 for (i = 1; i <= 8; ++i) {
2022                         if (hsotg->fifo_map & (1<<i))
2023                                 continue;
2024 -                       val = readl(hsotg->regs + DPTXFSIZN(i));
2025 +                       val = dwc2_readl(hsotg->regs + DPTXFSIZN(i));
2026                         val = (val >> FIFOSIZE_DEPTH_SHIFT)*4;
2027                         if (val < size)
2028                                 continue;
2029 @@ -2574,9 +2574,9 @@ static int s3c_hsotg_ep_enable(struct us
2030         dev_dbg(hsotg->dev, "%s: write DxEPCTL=0x%08x\n",
2031                 __func__, epctrl);
2032
2033 -       writel(epctrl, hsotg->regs + epctrl_reg);
2034 +       dwc2_writel(epctrl, hsotg->regs + epctrl_reg);
2035         dev_dbg(hsotg->dev, "%s: read DxEPCTL=0x%08x\n",
2036 -               __func__, readl(hsotg->regs + epctrl_reg));
2037 +               __func__, dwc2_readl(hsotg->regs + epctrl_reg));
2038
2039         /* enable the endpoint interrupt */
2040         s3c_hsotg_ctrl_epint(hsotg, index, dir_in, 1);
2041 @@ -2617,13 +2617,13 @@ static int s3c_hsotg_ep_disable(struct u
2042         hs_ep->fifo_index = 0;
2043         hs_ep->fifo_size = 0;
2044
2045 -       ctrl = readl(hsotg->regs + epctrl_reg);
2046 +       ctrl = dwc2_readl(hsotg->regs + epctrl_reg);
2047         ctrl &= ~DXEPCTL_EPENA;
2048         ctrl &= ~DXEPCTL_USBACTEP;
2049         ctrl |= DXEPCTL_SNAK;
2050
2051         dev_dbg(hsotg->dev, "%s: DxEPCTL=0x%08x\n", __func__, ctrl);
2052 -       writel(ctrl, hsotg->regs + epctrl_reg);
2053 +       dwc2_writel(ctrl, hsotg->regs + epctrl_reg);
2054
2055         /* disable endpoint interrupts */
2056         s3c_hsotg_ctrl_epint(hsotg, hs_ep->index, hs_ep->dir_in, 0);
2057 @@ -2704,7 +2704,7 @@ static int s3c_hsotg_ep_sethalt(struct u
2058         /* write both IN and OUT control registers */
2059
2060         epreg = DIEPCTL(index);
2061 -       epctl = readl(hs->regs + epreg);
2062 +       epctl = dwc2_readl(hs->regs + epreg);
2063
2064         if (value) {
2065                 epctl |= DXEPCTL_STALL + DXEPCTL_SNAK;
2066 @@ -2718,10 +2718,10 @@ static int s3c_hsotg_ep_sethalt(struct u
2067                                 epctl |= DXEPCTL_SETD0PID;
2068         }
2069
2070 -       writel(epctl, hs->regs + epreg);
2071 +       dwc2_writel(epctl, hs->regs + epreg);
2072
2073         epreg = DOEPCTL(index);
2074 -       epctl = readl(hs->regs + epreg);
2075 +       epctl = dwc2_readl(hs->regs + epreg);
2076
2077         if (value)
2078                 epctl |= DXEPCTL_STALL;
2079 @@ -2733,7 +2733,7 @@ static int s3c_hsotg_ep_sethalt(struct u
2080                                 epctl |= DXEPCTL_SETD0PID;
2081         }
2082
2083 -       writel(epctl, hs->regs + epreg);
2084 +       dwc2_writel(epctl, hs->regs + epreg);
2085
2086         hs_ep->halted = value;
2087
2088 @@ -2822,38 +2822,38 @@ static void s3c_hsotg_init(struct s3c_hs
2089  {
2090         /* unmask subset of endpoint interrupts */
2091
2092 -       writel(DIEPMSK_TIMEOUTMSK | DIEPMSK_AHBERRMSK |
2093 +       dwc2_writel(DIEPMSK_TIMEOUTMSK | DIEPMSK_AHBERRMSK |
2094                 DIEPMSK_EPDISBLDMSK | DIEPMSK_XFERCOMPLMSK,
2095                 hsotg->regs + DIEPMSK);
2096
2097 -       writel(DOEPMSK_SETUPMSK | DOEPMSK_AHBERRMSK |
2098 +       dwc2_writel(DOEPMSK_SETUPMSK | DOEPMSK_AHBERRMSK |
2099                 DOEPMSK_EPDISBLDMSK | DOEPMSK_XFERCOMPLMSK,
2100                 hsotg->regs + DOEPMSK);
2101
2102 -       writel(0, hsotg->regs + DAINTMSK);
2103 +       dwc2_writel(0, hsotg->regs + DAINTMSK);
2104
2105         /* Be in disconnected state until gadget is registered */
2106         __orr32(hsotg->regs + DCTL, DCTL_SFTDISCON);
2107
2108         if (0) {
2109                 /* post global nak until we're ready */
2110 -               writel(DCTL_SGNPINNAK | DCTL_SGOUTNAK,
2111 +               dwc2_writel(DCTL_SGNPINNAK | DCTL_SGOUTNAK,
2112                        hsotg->regs + DCTL);
2113         }
2114
2115         /* setup fifos */
2116
2117         dev_dbg(hsotg->dev, "GRXFSIZ=0x%08x, GNPTXFSIZ=0x%08x\n",
2118 -               readl(hsotg->regs + GRXFSIZ),
2119 -               readl(hsotg->regs + GNPTXFSIZ));
2120 +               dwc2_readl(hsotg->regs + GRXFSIZ),
2121 +               dwc2_readl(hsotg->regs + GNPTXFSIZ));
2122
2123         s3c_hsotg_init_fifo(hsotg);
2124
2125         /* set the PLL on, remove the HNP/SRP and set the PHY */
2126 -       writel(GUSBCFG_PHYIF16 | GUSBCFG_TOUTCAL(7) | (0x5 << 10),
2127 +       dwc2_writel(GUSBCFG_PHYIF16 | GUSBCFG_TOUTCAL(7) | (0x5 << 10),
2128                hsotg->regs + GUSBCFG);
2129
2130 -       writel(using_dma(hsotg) ? GAHBCFG_DMA_EN : 0x0,
2131 +       dwc2_writel(using_dma(hsotg) ? GAHBCFG_DMA_EN : 0x0,
2132                hsotg->regs + GAHBCFG);
2133  }
2134
2135 @@ -3045,8 +3045,8 @@ static void s3c_hsotg_initep(struct s3c_
2136
2137         if (using_dma(hsotg)) {
2138                 u32 next = DXEPCTL_NEXTEP((epnum + 1) % 15);
2139 -               writel(next, hsotg->regs + DIEPCTL(epnum));
2140 -               writel(next, hsotg->regs + DOEPCTL(epnum));
2141 +               dwc2_writel(next, hsotg->regs + DIEPCTL(epnum));
2142 +               dwc2_writel(next, hsotg->regs + DOEPCTL(epnum));
2143         }
2144  }
2145
2146 @@ -3061,13 +3061,13 @@ static void s3c_hsotg_hw_cfg(struct s3c_
2147         u32 cfg2, cfg3, cfg4;
2148         /* check hardware configuration */
2149
2150 -       cfg2 = readl(hsotg->regs + 0x48);
2151 +       cfg2 = dwc2_readl(hsotg->regs + 0x48);
2152         hsotg->num_of_eps = (cfg2 >> 10) & 0xF;
2153
2154 -       cfg3 = readl(hsotg->regs + 0x4C);
2155 +       cfg3 = dwc2_readl(hsotg->regs + 0x4C);
2156         hsotg->fifo_mem = (cfg3 >> 16);
2157
2158 -       cfg4 = readl(hsotg->regs + 0x50);
2159 +       cfg4 = dwc2_readl(hsotg->regs + 0x50);
2160         hsotg->dedicated_fifos = (cfg4 >> 25) & 1;
2161
2162         dev_info(hsotg->dev, "EPs: %d, %s fifos, %d entries in SPRAM\n",
2163 @@ -3089,19 +3089,19 @@ static void s3c_hsotg_dump(struct s3c_hs
2164         int idx;
2165
2166         dev_info(dev, "DCFG=0x%08x, DCTL=0x%08x, DIEPMSK=%08x\n",
2167 -                readl(regs + DCFG), readl(regs + DCTL),
2168 -                readl(regs + DIEPMSK));
2169 +                dwc2_readl(regs + DCFG), dwc2_readl(regs + DCTL),
2170 +                dwc2_readl(regs + DIEPMSK));
2171
2172         dev_info(dev, "GAHBCFG=0x%08x, 0x44=0x%08x\n",
2173 -                readl(regs + GAHBCFG), readl(regs + 0x44));
2174 +                dwc2_readl(regs + GAHBCFG), dwc2_readl(regs + 0x44));
2175
2176         dev_info(dev, "GRXFSIZ=0x%08x, GNPTXFSIZ=0x%08x\n",
2177 -                readl(regs + GRXFSIZ), readl(regs + GNPTXFSIZ));
2178 +                dwc2_readl(regs + GRXFSIZ), dwc2_readl(regs + GNPTXFSIZ));
2179
2180         /* show periodic fifo settings */
2181
2182         for (idx = 1; idx <= 15; idx++) {
2183 -               val = readl(regs + DPTXFSIZN(idx));
2184 +               val = dwc2_readl(regs + DPTXFSIZN(idx));
2185                 dev_info(dev, "DPTx[%d] FSize=%d, StAddr=0x%08x\n", idx,
2186                          val >> FIFOSIZE_DEPTH_SHIFT,
2187                          val & FIFOSIZE_STARTADDR_MASK);
2188 @@ -3110,21 +3110,21 @@ static void s3c_hsotg_dump(struct s3c_hs
2189         for (idx = 0; idx < 15; idx++) {
2190                 dev_info(dev,
2191                          "ep%d-in: EPCTL=0x%08x, SIZ=0x%08x, DMA=0x%08x\n", idx,
2192 -                        readl(regs + DIEPCTL(idx)),
2193 -                        readl(regs + DIEPTSIZ(idx)),
2194 -                        readl(regs + DIEPDMA(idx)));
2195 +                        dwc2_readl(regs + DIEPCTL(idx)),
2196 +                        dwc2_readl(regs + DIEPTSIZ(idx)),
2197 +                        dwc2_readl(regs + DIEPDMA(idx)));
2198
2199 -               val = readl(regs + DOEPCTL(idx));
2200 +               val = dwc2_readl(regs + DOEPCTL(idx));
2201                 dev_info(dev,
2202                          "ep%d-out: EPCTL=0x%08x, SIZ=0x%08x, DMA=0x%08x\n",
2203 -                        idx, readl(regs + DOEPCTL(idx)),
2204 -                        readl(regs + DOEPTSIZ(idx)),
2205 -                        readl(regs + DOEPDMA(idx)));
2206 +                        idx, dwc2_readl(regs + DOEPCTL(idx)),
2207 +                        dwc2_readl(regs + DOEPTSIZ(idx)),
2208 +                        dwc2_readl(regs + DOEPDMA(idx)));
2209
2210         }
2211
2212         dev_info(dev, "DVBUSDIS=0x%08x, DVBUSPULSE=%08x\n",
2213 -                readl(regs + DVBUSDIS), readl(regs + DVBUSPULSE));
2214 +                dwc2_readl(regs + DVBUSDIS), dwc2_readl(regs + DVBUSPULSE));
2215  #endif
2216  }
2217
2218 @@ -3144,38 +3144,38 @@ static int state_show(struct seq_file *s
2219         int idx;
2220
2221         seq_printf(seq, "DCFG=0x%08x, DCTL=0x%08x, DSTS=0x%08x\n",
2222 -                readl(regs + DCFG),
2223 -                readl(regs + DCTL),
2224 -                readl(regs + DSTS));
2225 +                dwc2_readl(regs + DCFG),
2226 +                dwc2_readl(regs + DCTL),
2227 +                dwc2_readl(regs + DSTS));
2228
2229         seq_printf(seq, "DIEPMSK=0x%08x, DOEPMASK=0x%08x\n",
2230 -                  readl(regs + DIEPMSK), readl(regs + DOEPMSK));
2231 +                  dwc2_readl(regs + DIEPMSK), dwc2_readl(regs + DOEPMSK));
2232
2233         seq_printf(seq, "GINTMSK=0x%08x, GINTSTS=0x%08x\n",
2234 -                  readl(regs + GINTMSK),
2235 -                  readl(regs + GINTSTS));
2236 +                  dwc2_readl(regs + GINTMSK),
2237 +                  dwc2_readl(regs + GINTSTS));
2238
2239         seq_printf(seq, "DAINTMSK=0x%08x, DAINT=0x%08x\n",
2240 -                  readl(regs + DAINTMSK),
2241 -                  readl(regs + DAINT));
2242 +                  dwc2_readl(regs + DAINTMSK),
2243 +                  dwc2_readl(regs + DAINT));
2244
2245         seq_printf(seq, "GNPTXSTS=0x%08x, GRXSTSR=%08x\n",
2246 -                  readl(regs + GNPTXSTS),
2247 -                  readl(regs + GRXSTSR));
2248 +                  dwc2_readl(regs + GNPTXSTS),
2249 +                  dwc2_readl(regs + GRXSTSR));
2250
2251         seq_puts(seq, "\nEndpoint status:\n");
2252
2253         for (idx = 0; idx < 15; idx++) {
2254                 u32 in, out;
2255
2256 -               in = readl(regs + DIEPCTL(idx));
2257 -               out = readl(regs + DOEPCTL(idx));
2258 +               in = dwc2_readl(regs + DIEPCTL(idx));
2259 +               out = dwc2_readl(regs + DOEPCTL(idx));
2260
2261                 seq_printf(seq, "ep%d: DIEPCTL=0x%08x, DOEPCTL=0x%08x",
2262                            idx, in, out);
2263
2264 -               in = readl(regs + DIEPTSIZ(idx));
2265 -               out = readl(regs + DOEPTSIZ(idx));
2266 +               in = dwc2_readl(regs + DIEPTSIZ(idx));
2267 +               out = dwc2_readl(regs + DOEPTSIZ(idx));
2268
2269                 seq_printf(seq, ", DIEPTSIZ=0x%08x, DOEPTSIZ=0x%08x",
2270                            in, out);
2271 @@ -3215,9 +3215,9 @@ static int fifo_show(struct seq_file *se
2272         int idx;
2273
2274         seq_puts(seq, "Non-periodic FIFOs:\n");
2275 -       seq_printf(seq, "RXFIFO: Size %d\n", readl(regs + GRXFSIZ));
2276 +       seq_printf(seq, "RXFIFO: Size %d\n", dwc2_readl(regs + GRXFSIZ));
2277
2278 -       val = readl(regs + GNPTXFSIZ);
2279 +       val = dwc2_readl(regs + GNPTXFSIZ);
2280         seq_printf(seq, "NPTXFIFO: Size %d, Start 0x%08x\n",
2281                    val >> FIFOSIZE_DEPTH_SHIFT,
2282                    val & FIFOSIZE_DEPTH_MASK);
2283 @@ -3225,7 +3225,7 @@ static int fifo_show(struct seq_file *se
2284         seq_puts(seq, "\nPeriodic TXFIFOs:\n");
2285
2286         for (idx = 1; idx <= 15; idx++) {
2287 -               val = readl(regs + DPTXFSIZN(idx));
2288 +               val = dwc2_readl(regs + DPTXFSIZN(idx));
2289
2290                 seq_printf(seq, "\tDPTXFIFO%2d: Size %d, Start 0x%08x\n", idx,
2291                            val >> FIFOSIZE_DEPTH_SHIFT,
2292 @@ -3278,20 +3278,20 @@ static int ep_show(struct seq_file *seq,
2293         /* first show the register state */
2294
2295         seq_printf(seq, "\tDIEPCTL=0x%08x, DOEPCTL=0x%08x\n",
2296 -                  readl(regs + DIEPCTL(index)),
2297 -                  readl(regs + DOEPCTL(index)));
2298 +                  dwc2_readl(regs + DIEPCTL(index)),
2299 +                  dwc2_readl(regs + DOEPCTL(index)));
2300
2301         seq_printf(seq, "\tDIEPDMA=0x%08x, DOEPDMA=0x%08x\n",
2302 -                  readl(regs + DIEPDMA(index)),
2303 -                  readl(regs + DOEPDMA(index)));
2304 +                  dwc2_readl(regs + DIEPDMA(index)),
2305 +                  dwc2_readl(regs + DOEPDMA(index)));
2306
2307         seq_printf(seq, "\tDIEPINT=0x%08x, DOEPINT=0x%08x\n",
2308 -                  readl(regs + DIEPINT(index)),
2309 -                  readl(regs + DOEPINT(index)));
2310 +                  dwc2_readl(regs + DIEPINT(index)),
2311 +                  dwc2_readl(regs + DOEPINT(index)));
2312
2313         seq_printf(seq, "\tDIEPTSIZ=0x%08x, DOEPTSIZ=0x%08x\n",
2314 -                  readl(regs + DIEPTSIZ(index)),
2315 -                  readl(regs + DOEPTSIZ(index)));
2316 +                  dwc2_readl(regs + DIEPTSIZ(index)),
2317 +                  dwc2_readl(regs + DOEPTSIZ(index)));
2318
2319         seq_puts(seq, "\n");
2320         seq_printf(seq, "mps %d\n", ep->ep.maxpacket);
2321 --- a/drivers/usb/dwc2/hcd.c
2322 +++ b/drivers/usb/dwc2/hcd.c
2323 @@ -80,10 +80,10 @@ static void dwc2_dump_channel_info(struc
2324         if (chan == NULL)
2325                 return;
2326
2327 -       hcchar = readl(hsotg->regs + HCCHAR(chan->hc_num));
2328 -       hcsplt = readl(hsotg->regs + HCSPLT(chan->hc_num));
2329 -       hctsiz = readl(hsotg->regs + HCTSIZ(chan->hc_num));
2330 -       hc_dma = readl(hsotg->regs + HCDMA(chan->hc_num));
2331 +       hcchar = dwc2_readl(hsotg->regs + HCCHAR(chan->hc_num));
2332 +       hcsplt = dwc2_readl(hsotg->regs + HCSPLT(chan->hc_num));
2333 +       hctsiz = dwc2_readl(hsotg->regs + HCTSIZ(chan->hc_num));
2334 +       hc_dma = dwc2_readl(hsotg->regs + HCDMA(chan->hc_num));
2335
2336         dev_dbg(hsotg->dev, "  Assigned to channel %p:\n", chan);
2337         dev_dbg(hsotg->dev, "    hcchar 0x%08x, hcsplt 0x%08x\n",
2338 @@ -207,7 +207,7 @@ void dwc2_hcd_start(struct dwc2_hsotg *h
2339                  */
2340                 hprt0 = dwc2_read_hprt0(hsotg);
2341                 hprt0 |= HPRT0_RST;
2342 -               writel(hprt0, hsotg->regs + HPRT0);
2343 +               dwc2_writel(hprt0, hsotg->regs + HPRT0);
2344         }
2345
2346         queue_delayed_work(hsotg->wq_otg, &hsotg->start_work,
2347 @@ -228,11 +228,11 @@ static void dwc2_hcd_cleanup_channels(st
2348                         channel = hsotg->hc_ptr_array[i];
2349                         if (!list_empty(&channel->hc_list_entry))
2350                                 continue;
2351 -                       hcchar = readl(hsotg->regs + HCCHAR(i));
2352 +                       hcchar = dwc2_readl(hsotg->regs + HCCHAR(i));
2353                         if (hcchar & HCCHAR_CHENA) {
2354                                 hcchar &= ~(HCCHAR_CHENA | HCCHAR_EPDIR);
2355                                 hcchar |= HCCHAR_CHDIS;
2356 -                               writel(hcchar, hsotg->regs + HCCHAR(i));
2357 +                               dwc2_writel(hcchar, hsotg->regs + HCCHAR(i));
2358                         }
2359                 }
2360         }
2361 @@ -241,11 +241,11 @@ static void dwc2_hcd_cleanup_channels(st
2362                 channel = hsotg->hc_ptr_array[i];
2363                 if (!list_empty(&channel->hc_list_entry))
2364                         continue;
2365 -               hcchar = readl(hsotg->regs + HCCHAR(i));
2366 +               hcchar = dwc2_readl(hsotg->regs + HCCHAR(i));
2367                 if (hcchar & HCCHAR_CHENA) {
2368                         /* Halt the channel */
2369                         hcchar |= HCCHAR_CHDIS;
2370 -                       writel(hcchar, hsotg->regs + HCCHAR(i));
2371 +                       dwc2_writel(hcchar, hsotg->regs + HCCHAR(i));
2372                 }
2373
2374                 dwc2_hc_cleanup(hsotg, channel);
2375 @@ -279,11 +279,11 @@ void dwc2_hcd_disconnect(struct dwc2_hso
2376          * interrupt mask and status bits and disabling subsequent host
2377          * channel interrupts.
2378          */
2379 -       intr = readl(hsotg->regs + GINTMSK);
2380 +       intr = dwc2_readl(hsotg->regs + GINTMSK);
2381         intr &= ~(GINTSTS_NPTXFEMP | GINTSTS_PTXFEMP | GINTSTS_HCHINT);
2382 -       writel(intr, hsotg->regs + GINTMSK);
2383 +       dwc2_writel(intr, hsotg->regs + GINTMSK);
2384         intr = GINTSTS_NPTXFEMP | GINTSTS_PTXFEMP | GINTSTS_HCHINT;
2385 -       writel(intr, hsotg->regs + GINTSTS);
2386 +       dwc2_writel(intr, hsotg->regs + GINTSTS);
2387
2388         /*
2389          * Turn off the vbus power only if the core has transitioned to device
2390 @@ -293,7 +293,7 @@ void dwc2_hcd_disconnect(struct dwc2_hso
2391         if (dwc2_is_device_mode(hsotg)) {
2392                 if (hsotg->op_state != OTG_STATE_A_SUSPEND) {
2393                         dev_dbg(hsotg->dev, "Disconnect: PortPower off\n");
2394 -                       writel(0, hsotg->regs + HPRT0);
2395 +                       dwc2_writel(0, hsotg->regs + HPRT0);
2396                 }
2397
2398                 dwc2_disable_host_interrupts(hsotg);
2399 @@ -344,7 +344,7 @@ void dwc2_hcd_stop(struct dwc2_hsotg *hs
2400
2401         /* Turn off the vbus power */
2402         dev_dbg(hsotg->dev, "PortPower off\n");
2403 -       writel(0, hsotg->regs + HPRT0);
2404 +       dwc2_writel(0, hsotg->regs + HPRT0);
2405  }
2406
2407  static int dwc2_hcd_urb_enqueue(struct dwc2_hsotg *hsotg,
2408 @@ -369,7 +369,7 @@ static int dwc2_hcd_urb_enqueue(struct d
2409         if ((dev_speed == USB_SPEED_LOW) &&
2410             (hsotg->hw_params.fs_phy_type == GHWCFG2_FS_PHY_TYPE_DEDICATED) &&
2411             (hsotg->hw_params.hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI)) {
2412 -               u32 hprt0 = readl(hsotg->regs + HPRT0);
2413 +               u32 hprt0 = dwc2_readl(hsotg->regs + HPRT0);
2414                 u32 prtspd = (hprt0 & HPRT0_SPD_MASK) >> HPRT0_SPD_SHIFT;
2415
2416                 if (prtspd == HPRT0_SPD_FULL_SPEED)
2417 @@ -391,7 +391,7 @@ static int dwc2_hcd_urb_enqueue(struct d
2418                 return retval;
2419         }
2420
2421 -       intr_mask = readl(hsotg->regs + GINTMSK);
2422 +       intr_mask = dwc2_readl(hsotg->regs + GINTMSK);
2423         if (!(intr_mask & GINTSTS_SOF)) {
2424                 enum dwc2_transaction_type tr_type;
2425
2426 @@ -1059,7 +1059,7 @@ static void dwc2_process_periodic_channe
2427         if (dbg_perio())
2428                 dev_vdbg(hsotg->dev, "Queue periodic transactions\n");
2429
2430 -       tx_status = readl(hsotg->regs + HPTXSTS);
2431 +       tx_status = dwc2_readl(hsotg->regs + HPTXSTS);
2432         qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >>
2433                     TXSTS_QSPCAVAIL_SHIFT;
2434         fspcavail = (tx_status & TXSTS_FSPCAVAIL_MASK) >>
2435 @@ -1074,7 +1074,7 @@ static void dwc2_process_periodic_channe
2436
2437         qh_ptr = hsotg->periodic_sched_assigned.next;
2438         while (qh_ptr != &hsotg->periodic_sched_assigned) {
2439 -               tx_status = readl(hsotg->regs + HPTXSTS);
2440 +               tx_status = dwc2_readl(hsotg->regs + HPTXSTS);
2441                 qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >>
2442                             TXSTS_QSPCAVAIL_SHIFT;
2443                 if (qspcavail == 0) {
2444 @@ -1134,7 +1134,7 @@ static void dwc2_process_periodic_channe
2445         }
2446
2447         if (hsotg->core_params->dma_enable <= 0) {
2448 -               tx_status = readl(hsotg->regs + HPTXSTS);
2449 +               tx_status = dwc2_readl(hsotg->regs + HPTXSTS);
2450                 qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >>
2451                             TXSTS_QSPCAVAIL_SHIFT;
2452                 fspcavail = (tx_status & TXSTS_FSPCAVAIL_MASK) >>
2453 @@ -1157,9 +1157,9 @@ static void dwc2_process_periodic_channe
2454                          * level to ensure that new requests are loaded as
2455                          * soon as possible.)
2456                          */
2457 -                       gintmsk = readl(hsotg->regs + GINTMSK);
2458 +                       gintmsk = dwc2_readl(hsotg->regs + GINTMSK);
2459                         gintmsk |= GINTSTS_PTXFEMP;
2460 -                       writel(gintmsk, hsotg->regs + GINTMSK);
2461 +                       dwc2_writel(gintmsk, hsotg->regs + GINTMSK);
2462                 } else {
2463                         /*
2464                          * Disable the Tx FIFO empty interrupt since there are
2465 @@ -1168,9 +1168,9 @@ static void dwc2_process_periodic_channe
2466                          * handlers to queue more transactions as transfer
2467                          * states change.
2468                          */
2469 -                       gintmsk = readl(hsotg->regs + GINTMSK);
2470 +                       gintmsk = dwc2_readl(hsotg->regs + GINTMSK);
2471                         gintmsk &= ~GINTSTS_PTXFEMP;
2472 -                       writel(gintmsk, hsotg->regs + GINTMSK);
2473 +                       dwc2_writel(gintmsk, hsotg->regs + GINTMSK);
2474                 }
2475         }
2476  }
2477 @@ -1199,7 +1199,7 @@ static void dwc2_process_non_periodic_ch
2478
2479         dev_vdbg(hsotg->dev, "Queue non-periodic transactions\n");
2480
2481 -       tx_status = readl(hsotg->regs + GNPTXSTS);
2482 +       tx_status = dwc2_readl(hsotg->regs + GNPTXSTS);
2483         qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >>
2484                     TXSTS_QSPCAVAIL_SHIFT;
2485         fspcavail = (tx_status & TXSTS_FSPCAVAIL_MASK) >>
2486 @@ -1222,7 +1222,7 @@ static void dwc2_process_non_periodic_ch
2487          * available in the request queue or the Tx FIFO
2488          */
2489         do {
2490 -               tx_status = readl(hsotg->regs + GNPTXSTS);
2491 +               tx_status = dwc2_readl(hsotg->regs + GNPTXSTS);
2492                 qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >>
2493                             TXSTS_QSPCAVAIL_SHIFT;
2494                 if (hsotg->core_params->dma_enable <= 0 && qspcavail == 0) {
2495 @@ -1259,7 +1259,7 @@ next:
2496         } while (hsotg->non_periodic_qh_ptr != orig_qh_ptr);
2497
2498         if (hsotg->core_params->dma_enable <= 0) {
2499 -               tx_status = readl(hsotg->regs + GNPTXSTS);
2500 +               tx_status = dwc2_readl(hsotg->regs + GNPTXSTS);
2501                 qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >>
2502                             TXSTS_QSPCAVAIL_SHIFT;
2503                 fspcavail = (tx_status & TXSTS_FSPCAVAIL_MASK) >>
2504 @@ -1279,9 +1279,9 @@ next:
2505                          * level to ensure that new requests are loaded as
2506                          * soon as possible.)
2507                          */
2508 -                       gintmsk = readl(hsotg->regs + GINTMSK);
2509 +                       gintmsk = dwc2_readl(hsotg->regs + GINTMSK);
2510                         gintmsk |= GINTSTS_NPTXFEMP;
2511 -                       writel(gintmsk, hsotg->regs + GINTMSK);
2512 +                       dwc2_writel(gintmsk, hsotg->regs + GINTMSK);
2513                 } else {
2514                         /*
2515                          * Disable the Tx FIFO empty interrupt since there are
2516 @@ -1290,9 +1290,9 @@ next:
2517                          * handlers to queue more transactions as transfer
2518                          * states change.
2519                          */
2520 -                       gintmsk = readl(hsotg->regs + GINTMSK);
2521 +                       gintmsk = dwc2_readl(hsotg->regs + GINTMSK);
2522                         gintmsk &= ~GINTSTS_NPTXFEMP;
2523 -                       writel(gintmsk, hsotg->regs + GINTMSK);
2524 +                       dwc2_writel(gintmsk, hsotg->regs + GINTMSK);
2525                 }
2526         }
2527  }
2528 @@ -1330,10 +1330,10 @@ void dwc2_hcd_queue_transactions(struct
2529                          * Ensure NP Tx FIFO empty interrupt is disabled when
2530                          * there are no non-periodic transfers to process
2531                          */
2532 -                       u32 gintmsk = readl(hsotg->regs + GINTMSK);
2533 +                       u32 gintmsk = dwc2_readl(hsotg->regs + GINTMSK);
2534
2535                         gintmsk &= ~GINTSTS_NPTXFEMP;
2536 -                       writel(gintmsk, hsotg->regs + GINTMSK);
2537 +                       dwc2_writel(gintmsk, hsotg->regs + GINTMSK);
2538                 }
2539         }
2540  }
2541 @@ -1347,7 +1347,7 @@ static void dwc2_conn_id_status_change(s
2542
2543         dev_dbg(hsotg->dev, "%s()\n", __func__);
2544
2545 -       gotgctl = readl(hsotg->regs + GOTGCTL);
2546 +       gotgctl = dwc2_readl(hsotg->regs + GOTGCTL);
2547         dev_dbg(hsotg->dev, "gotgctl=%0x\n", gotgctl);
2548         dev_dbg(hsotg->dev, "gotgctl.b.conidsts=%d\n",
2549                 !!(gotgctl & GOTGCTL_CONID_B));
2550 @@ -1408,9 +1408,9 @@ static void dwc2_wakeup_detected(unsigne
2551         hprt0 = dwc2_read_hprt0(hsotg);
2552         dev_dbg(hsotg->dev, "Resume: HPRT0=%0x\n", hprt0);
2553         hprt0 &= ~HPRT0_RES;
2554 -       writel(hprt0, hsotg->regs + HPRT0);
2555 +       dwc2_writel(hprt0, hsotg->regs + HPRT0);
2556         dev_dbg(hsotg->dev, "Clear Resume: HPRT0=%0x\n",
2557 -               readl(hsotg->regs + HPRT0));
2558 +               dwc2_readl(hsotg->regs + HPRT0));
2559
2560         dwc2_hcd_rem_wakeup(hsotg);
2561
2562 @@ -1438,30 +1438,30 @@ static void dwc2_port_suspend(struct dwc
2563         spin_lock_irqsave(&hsotg->lock, flags);
2564
2565         if (windex == hsotg->otg_port && dwc2_host_is_b_hnp_enabled(hsotg)) {
2566 -               gotgctl = readl(hsotg->regs + GOTGCTL);
2567 +               gotgctl = dwc2_readl(hsotg->regs + GOTGCTL);
2568                 gotgctl |= GOTGCTL_HSTSETHNPEN;
2569 -               writel(gotgctl, hsotg->regs + GOTGCTL);
2570 +               dwc2_writel(gotgctl, hsotg->regs + GOTGCTL);
2571                 hsotg->op_state = OTG_STATE_A_SUSPEND;
2572         }
2573
2574         hprt0 = dwc2_read_hprt0(hsotg);
2575         hprt0 |= HPRT0_SUSP;
2576 -       writel(hprt0, hsotg->regs + HPRT0);
2577 +       dwc2_writel(hprt0, hsotg->regs + HPRT0);
2578
2579         /* Update lx_state */
2580         hsotg->lx_state = DWC2_L2;
2581
2582         /* Suspend the Phy Clock */
2583 -       pcgctl = readl(hsotg->regs + PCGCTL);
2584 +       pcgctl = dwc2_readl(hsotg->regs + PCGCTL);
2585         pcgctl |= PCGCTL_STOPPCLK;
2586 -       writel(pcgctl, hsotg->regs + PCGCTL);
2587 +       dwc2_writel(pcgctl, hsotg->regs + PCGCTL);
2588         udelay(10);
2589
2590         /* For HNP the bus must be suspended for at least 200ms */
2591         if (dwc2_host_is_b_hnp_enabled(hsotg)) {
2592 -               pcgctl = readl(hsotg->regs + PCGCTL);
2593 +               pcgctl = dwc2_readl(hsotg->regs + PCGCTL);
2594                 pcgctl &= ~PCGCTL_STOPPCLK;
2595 -               writel(pcgctl, hsotg->regs + PCGCTL);
2596 +               dwc2_writel(pcgctl, hsotg->regs + PCGCTL);
2597
2598                 spin_unlock_irqrestore(&hsotg->lock, flags);
2599
2600 @@ -1510,23 +1510,23 @@ static int dwc2_hcd_hub_control(struct d
2601                                 "ClearPortFeature USB_PORT_FEAT_ENABLE\n");
2602                         hprt0 = dwc2_read_hprt0(hsotg);
2603                         hprt0 |= HPRT0_ENA;
2604 -                       writel(hprt0, hsotg->regs + HPRT0);
2605 +                       dwc2_writel(hprt0, hsotg->regs + HPRT0);
2606                         break;
2607
2608                 case USB_PORT_FEAT_SUSPEND:
2609                         dev_dbg(hsotg->dev,
2610                                 "ClearPortFeature USB_PORT_FEAT_SUSPEND\n");
2611 -                       writel(0, hsotg->regs + PCGCTL);
2612 +                       dwc2_writel(0, hsotg->regs + PCGCTL);
2613                         msleep(USB_RESUME_TIMEOUT);
2614
2615                         hprt0 = dwc2_read_hprt0(hsotg);
2616                         hprt0 |= HPRT0_RES;
2617 -                       writel(hprt0, hsotg->regs + HPRT0);
2618 +                       dwc2_writel(hprt0, hsotg->regs + HPRT0);
2619                         hprt0 &= ~HPRT0_SUSP;
2620                         usleep_range(100000, 150000);
2621
2622                         hprt0 &= ~HPRT0_RES;
2623 -                       writel(hprt0, hsotg->regs + HPRT0);
2624 +                       dwc2_writel(hprt0, hsotg->regs + HPRT0);
2625                         break;
2626
2627                 case USB_PORT_FEAT_POWER:
2628 @@ -1534,7 +1534,7 @@ static int dwc2_hcd_hub_control(struct d
2629                                 "ClearPortFeature USB_PORT_FEAT_POWER\n");
2630                         hprt0 = dwc2_read_hprt0(hsotg);
2631                         hprt0 &= ~HPRT0_PWR;
2632 -                       writel(hprt0, hsotg->regs + HPRT0);
2633 +                       dwc2_writel(hprt0, hsotg->regs + HPRT0);
2634                         break;
2635
2636                 case USB_PORT_FEAT_INDICATOR:
2637 @@ -1653,7 +1653,7 @@ static int dwc2_hcd_hub_control(struct d
2638                         break;
2639                 }
2640
2641 -               hprt0 = readl(hsotg->regs + HPRT0);
2642 +               hprt0 = dwc2_readl(hsotg->regs + HPRT0);
2643                 dev_vdbg(hsotg->dev, "  HPRT0: 0x%08x\n", hprt0);
2644
2645                 if (hprt0 & HPRT0_CONNSTS)
2646 @@ -1718,18 +1718,18 @@ static int dwc2_hcd_hub_control(struct d
2647                                 "SetPortFeature - USB_PORT_FEAT_POWER\n");
2648                         hprt0 = dwc2_read_hprt0(hsotg);
2649                         hprt0 |= HPRT0_PWR;
2650 -                       writel(hprt0, hsotg->regs + HPRT0);
2651 +                       dwc2_writel(hprt0, hsotg->regs + HPRT0);
2652                         break;
2653
2654                 case USB_PORT_FEAT_RESET:
2655                         hprt0 = dwc2_read_hprt0(hsotg);
2656                         dev_dbg(hsotg->dev,
2657                                 "SetPortFeature - USB_PORT_FEAT_RESET\n");
2658 -                       pcgctl = readl(hsotg->regs + PCGCTL);
2659 +                       pcgctl = dwc2_readl(hsotg->regs + PCGCTL);
2660                         pcgctl &= ~(PCGCTL_ENBL_SLEEP_GATING | PCGCTL_STOPPCLK);
2661 -                       writel(pcgctl, hsotg->regs + PCGCTL);
2662 +                       dwc2_writel(pcgctl, hsotg->regs + PCGCTL);
2663                         /* ??? Original driver does this */
2664 -                       writel(0, hsotg->regs + PCGCTL);
2665 +                       dwc2_writel(0, hsotg->regs + PCGCTL);
2666
2667                         hprt0 = dwc2_read_hprt0(hsotg);
2668                         /* Clear suspend bit if resetting from suspend state */
2669 @@ -1744,13 +1744,13 @@ static int dwc2_hcd_hub_control(struct d
2670                                 hprt0 |= HPRT0_PWR | HPRT0_RST;
2671                                 dev_dbg(hsotg->dev,
2672                                         "In host mode, hprt0=%08x\n", hprt0);
2673 -                               writel(hprt0, hsotg->regs + HPRT0);
2674 +                               dwc2_writel(hprt0, hsotg->regs + HPRT0);
2675                         }
2676
2677                         /* Clear reset bit in 10ms (FS/LS) or 50ms (HS) */
2678                         usleep_range(50000, 70000);
2679                         hprt0 &= ~HPRT0_RST;
2680 -                       writel(hprt0, hsotg->regs + HPRT0);
2681 +                       dwc2_writel(hprt0, hsotg->regs + HPRT0);
2682                         hsotg->lx_state = DWC2_L0; /* Now back to On state */
2683                         break;
2684
2685 @@ -1814,7 +1814,7 @@ static int dwc2_hcd_is_status_changed(st
2686
2687  int dwc2_hcd_get_frame_number(struct dwc2_hsotg *hsotg)
2688  {
2689 -       u32 hfnum = readl(hsotg->regs + HFNUM);
2690 +       u32 hfnum = dwc2_readl(hsotg->regs + HFNUM);
2691
2692  #ifdef DWC2_DEBUG_SOF
2693         dev_vdbg(hsotg->dev, "DWC OTG HCD GET FRAME NUMBER %d\n",
2694 @@ -1917,11 +1917,11 @@ void dwc2_hcd_dump_state(struct dwc2_hso
2695                 if (chan->xfer_started) {
2696                         u32 hfnum, hcchar, hctsiz, hcint, hcintmsk;
2697
2698 -                       hfnum = readl(hsotg->regs + HFNUM);
2699 -                       hcchar = readl(hsotg->regs + HCCHAR(i));
2700 -                       hctsiz = readl(hsotg->regs + HCTSIZ(i));
2701 -                       hcint = readl(hsotg->regs + HCINT(i));
2702 -                       hcintmsk = readl(hsotg->regs + HCINTMSK(i));
2703 +                       hfnum = dwc2_readl(hsotg->regs + HFNUM);
2704 +                       hcchar = dwc2_readl(hsotg->regs + HCCHAR(i));
2705 +                       hctsiz = dwc2_readl(hsotg->regs + HCTSIZ(i));
2706 +                       hcint = dwc2_readl(hsotg->regs + HCINT(i));
2707 +                       hcintmsk = dwc2_readl(hsotg->regs + HCINTMSK(i));
2708                         dev_dbg(hsotg->dev, "    hfnum: 0x%08x\n", hfnum);
2709                         dev_dbg(hsotg->dev, "    hcchar: 0x%08x\n", hcchar);
2710                         dev_dbg(hsotg->dev, "    hctsiz: 0x%08x\n", hctsiz);
2711 @@ -1969,12 +1969,12 @@ void dwc2_hcd_dump_state(struct dwc2_hso
2712         dev_dbg(hsotg->dev, "  periodic_channels: %d\n",
2713                 hsotg->periodic_channels);
2714         dev_dbg(hsotg->dev, "  periodic_usecs: %d\n", hsotg->periodic_usecs);
2715 -       np_tx_status = readl(hsotg->regs + GNPTXSTS);
2716 +       np_tx_status = dwc2_readl(hsotg->regs + GNPTXSTS);
2717         dev_dbg(hsotg->dev, "  NP Tx Req Queue Space Avail: %d\n",
2718                 (np_tx_status & TXSTS_QSPCAVAIL_MASK) >> TXSTS_QSPCAVAIL_SHIFT);
2719         dev_dbg(hsotg->dev, "  NP Tx FIFO Space Avail: %d\n",
2720                 (np_tx_status & TXSTS_FSPCAVAIL_MASK) >> TXSTS_FSPCAVAIL_SHIFT);
2721 -       p_tx_status = readl(hsotg->regs + HPTXSTS);
2722 +       p_tx_status = dwc2_readl(hsotg->regs + HPTXSTS);
2723         dev_dbg(hsotg->dev, "  P Tx Req Queue Space Avail: %d\n",
2724                 (p_tx_status & TXSTS_QSPCAVAIL_MASK) >> TXSTS_QSPCAVAIL_SHIFT);
2725         dev_dbg(hsotg->dev, "  P Tx FIFO Space Avail: %d\n",
2726 @@ -2238,7 +2238,7 @@ static void dwc2_hcd_reset_func(struct w
2727         dev_dbg(hsotg->dev, "USB RESET function called\n");
2728         hprt0 = dwc2_read_hprt0(hsotg);
2729         hprt0 &= ~HPRT0_RST;
2730 -       writel(hprt0, hsotg->regs + HPRT0);
2731 +       dwc2_writel(hprt0, hsotg->regs + HPRT0);
2732         hsotg->flags.b.port_reset_change = 1;
2733  }
2734
2735 @@ -2715,17 +2715,17 @@ static void dwc2_hcd_free(struct dwc2_hs
2736                 hsotg->status_buf = NULL;
2737         }
2738
2739 -       ahbcfg = readl(hsotg->regs + GAHBCFG);
2740 +       ahbcfg = dwc2_readl(hsotg->regs + GAHBCFG);
2741
2742         /* Disable all interrupts */
2743         ahbcfg &= ~GAHBCFG_GLBL_INTR_EN;
2744 -       writel(ahbcfg, hsotg->regs + GAHBCFG);
2745 -       writel(0, hsotg->regs + GINTMSK);
2746 +       dwc2_writel(ahbcfg, hsotg->regs + GAHBCFG);
2747 +       dwc2_writel(0, hsotg->regs + GINTMSK);
2748
2749         if (hsotg->hw_params.snpsid >= DWC2_CORE_REV_3_00a) {
2750 -               dctl = readl(hsotg->regs + DCTL);
2751 +               dctl = dwc2_readl(hsotg->regs + DCTL);
2752                 dctl |= DCTL_SFTDISCON;
2753 -               writel(dctl, hsotg->regs + DCTL);
2754 +               dwc2_writel(dctl, hsotg->regs + DCTL);
2755         }
2756
2757         if (hsotg->wq_otg) {
2758 @@ -2788,7 +2788,7 @@ int dwc2_hcd_init(struct dwc2_hsotg *hso
2759
2760         retval = -ENOMEM;
2761
2762 -       hcfg = readl(hsotg->regs + HCFG);
2763 +       hcfg = dwc2_readl(hsotg->regs + HCFG);
2764         dev_dbg(hsotg->dev, "hcfg=%08x\n", hcfg);
2765
2766  #ifdef CONFIG_USB_DWC2_TRACK_MISSED_SOFS
2767 --- a/drivers/usb/dwc2/hcd_ddma.c
2768 +++ b/drivers/usb/dwc2/hcd_ddma.c
2769 @@ -169,19 +169,19 @@ static void dwc2_per_sched_enable(struct
2770
2771         spin_lock_irqsave(&hsotg->lock, flags);
2772
2773 -       hcfg = readl(hsotg->regs + HCFG);
2774 +       hcfg = dwc2_readl(hsotg->regs + HCFG);
2775         if (hcfg & HCFG_PERSCHEDENA) {
2776                 /* already enabled */
2777                 spin_unlock_irqrestore(&hsotg->lock, flags);
2778                 return;
2779         }
2780
2781 -       writel(hsotg->frame_list_dma, hsotg->regs + HFLBADDR);
2782 +       dwc2_writel(hsotg->frame_list_dma, hsotg->regs + HFLBADDR);
2783
2784         hcfg &= ~HCFG_FRLISTEN_MASK;
2785         hcfg |= fr_list_en | HCFG_PERSCHEDENA;
2786         dev_vdbg(hsotg->dev, "Enabling Periodic schedule\n");
2787 -       writel(hcfg, hsotg->regs + HCFG);
2788 +       dwc2_writel(hcfg, hsotg->regs + HCFG);
2789
2790         spin_unlock_irqrestore(&hsotg->lock, flags);
2791  }
2792 @@ -193,7 +193,7 @@ static void dwc2_per_sched_disable(struc
2793
2794         spin_lock_irqsave(&hsotg->lock, flags);
2795
2796 -       hcfg = readl(hsotg->regs + HCFG);
2797 +       hcfg = dwc2_readl(hsotg->regs + HCFG);
2798         if (!(hcfg & HCFG_PERSCHEDENA)) {
2799                 /* already disabled */
2800                 spin_unlock_irqrestore(&hsotg->lock, flags);
2801 @@ -202,7 +202,7 @@ static void dwc2_per_sched_disable(struc
2802
2803         hcfg &= ~HCFG_PERSCHEDENA;
2804         dev_vdbg(hsotg->dev, "Disabling Periodic schedule\n");
2805 -       writel(hcfg, hsotg->regs + HCFG);
2806 +       dwc2_writel(hcfg, hsotg->regs + HCFG);
2807
2808         spin_unlock_irqrestore(&hsotg->lock, flags);
2809  }
2810 --- a/drivers/usb/dwc2/hcd.h
2811 +++ b/drivers/usb/dwc2/hcd.h
2812 @@ -371,10 +371,10 @@ static inline struct usb_hcd *dwc2_hsotg
2813   */
2814  static inline void disable_hc_int(struct dwc2_hsotg *hsotg, int chnum, u32 intr)
2815  {
2816 -       u32 mask = readl(hsotg->regs + HCINTMSK(chnum));
2817 +       u32 mask = dwc2_readl(hsotg->regs + HCINTMSK(chnum));
2818
2819         mask &= ~intr;
2820 -       writel(mask, hsotg->regs + HCINTMSK(chnum));
2821 +       dwc2_writel(mask, hsotg->regs + HCINTMSK(chnum));
2822  }
2823
2824  /*
2825 @@ -382,11 +382,11 @@ static inline void disable_hc_int(struct
2826   */
2827  static inline int dwc2_is_host_mode(struct dwc2_hsotg *hsotg)
2828  {
2829 -       return (readl(hsotg->regs + GINTSTS) & GINTSTS_CURMODE_HOST) != 0;
2830 +       return (dwc2_readl(hsotg->regs + GINTSTS) & GINTSTS_CURMODE_HOST) != 0;
2831  }
2832  static inline int dwc2_is_device_mode(struct dwc2_hsotg *hsotg)
2833  {
2834 -       return (readl(hsotg->regs + GINTSTS) & GINTSTS_CURMODE_HOST) == 0;
2835 +       return (dwc2_readl(hsotg->regs + GINTSTS) & GINTSTS_CURMODE_HOST) == 0;
2836  }
2837
2838  /*
2839 @@ -395,7 +395,7 @@ static inline int dwc2_is_device_mode(st
2840   */
2841  static inline u32 dwc2_read_hprt0(struct dwc2_hsotg *hsotg)
2842  {
2843 -       u32 hprt0 = readl(hsotg->regs + HPRT0);
2844 +       u32 hprt0 = dwc2_readl(hsotg->regs + HPRT0);
2845
2846         hprt0 &= ~(HPRT0_ENA | HPRT0_CONNDET | HPRT0_ENACHG | HPRT0_OVRCURRCHG);
2847         return hprt0;
2848 @@ -582,7 +582,7 @@ static inline u16 dwc2_micro_frame_num(u
2849   */
2850  static inline u32 dwc2_read_core_intr(struct dwc2_hsotg *hsotg)
2851  {
2852 -       return readl(hsotg->regs + GINTSTS) & readl(hsotg->regs + GINTMSK);
2853 +       return dwc2_readl(hsotg->regs + GINTSTS) & dwc2_readl(hsotg->regs + GINTMSK);
2854  }
2855
2856  static inline u32 dwc2_hcd_urb_get_status(struct dwc2_hcd_urb *dwc2_urb)
2857 @@ -744,7 +744,7 @@ do {                                                                        \
2858                            qtd_list_entry);                             \
2859         if (usb_pipeint(_qtd_->urb->pipe) &&                            \
2860             (_qh_)->start_split_frame != 0 && !_qtd_->complete_split) { \
2861 -               _hfnum_.d32 = readl((_hcd_)->regs + HFNUM);             \
2862 +               _hfnum_.d32 = dwc2_readl((_hcd_)->regs + HFNUM);                \
2863                 switch (_hfnum_.b.frnum & 0x7) {                        \
2864                 case 7:                                                 \
2865                         (_hcd_)->hfnum_7_samples_##_letter_++;          \
2866 --- a/drivers/usb/dwc2/hcd_intr.c
2867 +++ b/drivers/usb/dwc2/hcd_intr.c
2868 @@ -148,7 +148,7 @@ static void dwc2_sof_intr(struct dwc2_hs
2869                 dwc2_hcd_queue_transactions(hsotg, tr_type);
2870
2871         /* Clear interrupt */
2872 -       writel(GINTSTS_SOF, hsotg->regs + GINTSTS);
2873 +       dwc2_writel(GINTSTS_SOF, hsotg->regs + GINTSTS);
2874  }
2875
2876  /*
2877 @@ -164,7 +164,7 @@ static void dwc2_rx_fifo_level_intr(stru
2878         if (dbg_perio())
2879                 dev_vdbg(hsotg->dev, "--RxFIFO Level Interrupt--\n");
2880
2881 -       grxsts = readl(hsotg->regs + GRXSTSP);
2882 +       grxsts = dwc2_readl(hsotg->regs + GRXSTSP);
2883         chnum = (grxsts & GRXSTS_HCHNUM_MASK) >> GRXSTS_HCHNUM_SHIFT;
2884         chan = hsotg->hc_ptr_array[chnum];
2885         if (!chan) {
2886 @@ -247,11 +247,11 @@ static void dwc2_hprt0_enable(struct dwc
2887         dev_vdbg(hsotg->dev, "%s(%p)\n", __func__, hsotg);
2888
2889         /* Every time when port enables calculate HFIR.FrInterval */
2890 -       hfir = readl(hsotg->regs + HFIR);
2891 +       hfir = dwc2_readl(hsotg->regs + HFIR);
2892         hfir &= ~HFIR_FRINT_MASK;
2893         hfir |= dwc2_calc_frame_interval(hsotg) << HFIR_FRINT_SHIFT &
2894                 HFIR_FRINT_MASK;
2895 -       writel(hfir, hsotg->regs + HFIR);
2896 +       dwc2_writel(hfir, hsotg->regs + HFIR);
2897
2898         /* Check if we need to adjust the PHY clock speed for low power */
2899         if (!params->host_support_fs_ls_low_power) {
2900 @@ -260,7 +260,7 @@ static void dwc2_hprt0_enable(struct dwc
2901                 return;
2902         }
2903
2904 -       usbcfg = readl(hsotg->regs + GUSBCFG);
2905 +       usbcfg = dwc2_readl(hsotg->regs + GUSBCFG);
2906         prtspd = (hprt0 & HPRT0_SPD_MASK) >> HPRT0_SPD_SHIFT;
2907
2908         if (prtspd == HPRT0_SPD_LOW_SPEED || prtspd == HPRT0_SPD_FULL_SPEED) {
2909 @@ -268,11 +268,11 @@ static void dwc2_hprt0_enable(struct dwc
2910                 if (!(usbcfg & GUSBCFG_PHY_LP_CLK_SEL)) {
2911                         /* Set PHY low power clock select for FS/LS devices */
2912                         usbcfg |= GUSBCFG_PHY_LP_CLK_SEL;
2913 -                       writel(usbcfg, hsotg->regs + GUSBCFG);
2914 +                       dwc2_writel(usbcfg, hsotg->regs + GUSBCFG);
2915                         do_reset = 1;
2916                 }
2917
2918 -               hcfg = readl(hsotg->regs + HCFG);
2919 +               hcfg = dwc2_readl(hsotg->regs + HCFG);
2920                 fslspclksel = (hcfg & HCFG_FSLSPCLKSEL_MASK) >>
2921                               HCFG_FSLSPCLKSEL_SHIFT;
2922
2923 @@ -286,7 +286,7 @@ static void dwc2_hprt0_enable(struct dwc
2924                                 fslspclksel = HCFG_FSLSPCLKSEL_6_MHZ;
2925                                 hcfg &= ~HCFG_FSLSPCLKSEL_MASK;
2926                                 hcfg |= fslspclksel << HCFG_FSLSPCLKSEL_SHIFT;
2927 -                               writel(hcfg, hsotg->regs + HCFG);
2928 +                               dwc2_writel(hcfg, hsotg->regs + HCFG);
2929                                 do_reset = 1;
2930                         }
2931                 } else {
2932 @@ -297,7 +297,7 @@ static void dwc2_hprt0_enable(struct dwc
2933                                 fslspclksel = HCFG_FSLSPCLKSEL_48_MHZ;
2934                                 hcfg &= ~HCFG_FSLSPCLKSEL_MASK;
2935                                 hcfg |= fslspclksel << HCFG_FSLSPCLKSEL_SHIFT;
2936 -                               writel(hcfg, hsotg->regs + HCFG);
2937 +                               dwc2_writel(hcfg, hsotg->regs + HCFG);
2938                                 do_reset = 1;
2939                         }
2940                 }
2941 @@ -305,7 +305,7 @@ static void dwc2_hprt0_enable(struct dwc
2942                 /* Not low power */
2943                 if (usbcfg & GUSBCFG_PHY_LP_CLK_SEL) {
2944                         usbcfg &= ~GUSBCFG_PHY_LP_CLK_SEL;
2945 -                       writel(usbcfg, hsotg->regs + GUSBCFG);
2946 +                       dwc2_writel(usbcfg, hsotg->regs + GUSBCFG);
2947                         do_reset = 1;
2948                 }
2949         }
2950 @@ -332,7 +332,7 @@ static void dwc2_port_intr(struct dwc2_h
2951
2952         dev_vdbg(hsotg->dev, "--Port Interrupt--\n");
2953
2954 -       hprt0 = readl(hsotg->regs + HPRT0);
2955 +       hprt0 = dwc2_readl(hsotg->regs + HPRT0);
2956         hprt0_modify = hprt0;
2957
2958         /*
2959 @@ -385,7 +385,7 @@ static void dwc2_port_intr(struct dwc2_h
2960         }
2961
2962         /* Clear Port Interrupts */
2963 -       writel(hprt0_modify, hsotg->regs + HPRT0);
2964 +       dwc2_writel(hprt0_modify, hsotg->regs + HPRT0);
2965  }
2966
2967  /*
2968 @@ -405,7 +405,7 @@ static u32 dwc2_get_actual_xfer_length(s
2969  {
2970         u32 hctsiz, count, length;
2971
2972 -       hctsiz = readl(hsotg->regs + HCTSIZ(chnum));
2973 +       hctsiz = dwc2_readl(hsotg->regs + HCTSIZ(chnum));
2974
2975         if (halt_status == DWC2_HC_XFER_COMPLETE) {
2976                 if (chan->ep_is_in) {
2977 @@ -483,7 +483,7 @@ static int dwc2_update_urb_state(struct
2978                 urb->status = 0;
2979         }
2980
2981 -       hctsiz = readl(hsotg->regs + HCTSIZ(chnum));
2982 +       hctsiz = dwc2_readl(hsotg->regs + HCTSIZ(chnum));
2983         dev_vdbg(hsotg->dev, "DWC_otg: %s: %s, channel %d\n",
2984                  __func__, (chan->ep_is_in ? "IN" : "OUT"), chnum);
2985         dev_vdbg(hsotg->dev, "  chan->xfer_len %d\n", chan->xfer_len);
2986 @@ -506,7 +506,7 @@ void dwc2_hcd_save_data_toggle(struct dw
2987                                struct dwc2_host_chan *chan, int chnum,
2988                                struct dwc2_qtd *qtd)
2989  {
2990 -       u32 hctsiz = readl(hsotg->regs + HCTSIZ(chnum));
2991 +       u32 hctsiz = dwc2_readl(hsotg->regs + HCTSIZ(chnum));
2992         u32 pid = (hctsiz & TSIZ_SC_MC_PID_MASK) >> TSIZ_SC_MC_PID_SHIFT;
2993
2994         if (chan->ep_type != USB_ENDPOINT_XFER_CONTROL) {
2995 @@ -753,9 +753,9 @@ cleanup:
2996                 }
2997         }
2998
2999 -       haintmsk = readl(hsotg->regs + HAINTMSK);
3000 +       haintmsk = dwc2_readl(hsotg->regs + HAINTMSK);
3001         haintmsk &= ~(1 << chan->hc_num);
3002 -       writel(haintmsk, hsotg->regs + HAINTMSK);
3003 +       dwc2_writel(haintmsk, hsotg->regs + HAINTMSK);
3004
3005         /* Try to queue more transfers now that there's a free channel */
3006         tr_type = dwc2_hcd_select_transactions(hsotg);
3007 @@ -802,9 +802,9 @@ static void dwc2_halt_channel(struct dwc
3008                          * is enabled so that the non-periodic schedule will
3009                          * be processed
3010                          */
3011 -                       gintmsk = readl(hsotg->regs + GINTMSK);
3012 +                       gintmsk = dwc2_readl(hsotg->regs + GINTMSK);
3013                         gintmsk |= GINTSTS_NPTXFEMP;
3014 -                       writel(gintmsk, hsotg->regs + GINTMSK);
3015 +                       dwc2_writel(gintmsk, hsotg->regs + GINTMSK);
3016                 } else {
3017                         dev_vdbg(hsotg->dev, "isoc/intr\n");
3018                         /*
3019 @@ -821,9 +821,9 @@ static void dwc2_halt_channel(struct dwc
3020                          * enabled so that the periodic schedule will be
3021                          * processed
3022                          */
3023 -                       gintmsk = readl(hsotg->regs + GINTMSK);
3024 +                       gintmsk = dwc2_readl(hsotg->regs + GINTMSK);
3025                         gintmsk |= GINTSTS_PTXFEMP;
3026 -                       writel(gintmsk, hsotg->regs + GINTMSK);
3027 +                       dwc2_writel(gintmsk, hsotg->regs + GINTMSK);
3028                 }
3029         }
3030  }
3031 @@ -888,7 +888,7 @@ static void dwc2_complete_periodic_xfer(
3032                                         struct dwc2_qtd *qtd,
3033                                         enum dwc2_halt_status halt_status)
3034  {
3035 -       u32 hctsiz = readl(hsotg->regs + HCTSIZ(chnum));
3036 +       u32 hctsiz = dwc2_readl(hsotg->regs + HCTSIZ(chnum));
3037
3038         qtd->error_count = 0;
3039
3040 @@ -1158,7 +1158,7 @@ static void dwc2_update_urb_state_abn(st
3041
3042         urb->actual_length += xfer_length;
3043
3044 -       hctsiz = readl(hsotg->regs + HCTSIZ(chnum));
3045 +       hctsiz = dwc2_readl(hsotg->regs + HCTSIZ(chnum));
3046         dev_vdbg(hsotg->dev, "DWC_otg: %s: %s, channel %d\n",
3047                  __func__, (chan->ep_is_in ? "IN" : "OUT"), chnum);
3048         dev_vdbg(hsotg->dev, "  chan->start_pkt_count %d\n",
3049 @@ -1469,10 +1469,10 @@ static void dwc2_hc_ahberr_intr(struct d
3050
3051         dwc2_hc_handle_tt_clear(hsotg, chan, qtd);
3052
3053 -       hcchar = readl(hsotg->regs + HCCHAR(chnum));
3054 -       hcsplt = readl(hsotg->regs + HCSPLT(chnum));
3055 -       hctsiz = readl(hsotg->regs + HCTSIZ(chnum));
3056 -       hc_dma = readl(hsotg->regs + HCDMA(chnum));
3057 +       hcchar = dwc2_readl(hsotg->regs + HCCHAR(chnum));
3058 +       hcsplt = dwc2_readl(hsotg->regs + HCSPLT(chnum));
3059 +       hctsiz = dwc2_readl(hsotg->regs + HCTSIZ(chnum));
3060 +       hc_dma = dwc2_readl(hsotg->regs + HCDMA(chnum));
3061
3062         dev_err(hsotg->dev, "AHB ERROR, Channel %d\n", chnum);
3063         dev_err(hsotg->dev, "  hcchar 0x%08x, hcsplt 0x%08x\n", hcchar, hcsplt);
3064 @@ -1685,10 +1685,10 @@ static bool dwc2_halt_status_ok(struct d
3065                  * This code is here only as a check. This condition should
3066                  * never happen. Ignore the halt if it does occur.
3067                  */
3068 -               hcchar = readl(hsotg->regs + HCCHAR(chnum));
3069 -               hctsiz = readl(hsotg->regs + HCTSIZ(chnum));
3070 -               hcintmsk = readl(hsotg->regs + HCINTMSK(chnum));
3071 -               hcsplt = readl(hsotg->regs + HCSPLT(chnum));
3072 +               hcchar = dwc2_readl(hsotg->regs + HCCHAR(chnum));
3073 +               hctsiz = dwc2_readl(hsotg->regs + HCTSIZ(chnum));
3074 +               hcintmsk = dwc2_readl(hsotg->regs + HCINTMSK(chnum));
3075 +               hcsplt = dwc2_readl(hsotg->regs + HCSPLT(chnum));
3076                 dev_dbg(hsotg->dev,
3077                         "%s: chan->halt_status DWC2_HC_XFER_NO_HALT_STATUS,\n",
3078                          __func__);
3079 @@ -1712,7 +1712,7 @@ static bool dwc2_halt_status_ok(struct d
3080          * when the halt interrupt occurs. Halt the channel again if it does
3081          * occur.
3082          */
3083 -       hcchar = readl(hsotg->regs + HCCHAR(chnum));
3084 +       hcchar = dwc2_readl(hsotg->regs + HCCHAR(chnum));
3085         if (hcchar & HCCHAR_CHDIS) {
3086                 dev_warn(hsotg->dev,
3087                          "%s: hcchar.chdis set unexpectedly, hcchar 0x%08x, trying to halt again\n",
3088 @@ -1772,7 +1772,7 @@ static void dwc2_hc_chhltd_intr_dma(stru
3089                 return;
3090         }
3091
3092 -       hcintmsk = readl(hsotg->regs + HCINTMSK(chnum));
3093 +       hcintmsk = dwc2_readl(hsotg->regs + HCINTMSK(chnum));
3094
3095         if (chan->hcint & HCINTMSK_XFERCOMPL) {
3096                 /*
3097 @@ -1867,7 +1867,7 @@ static void dwc2_hc_chhltd_intr_dma(stru
3098                                 dev_err(hsotg->dev,
3099                                         "hcint 0x%08x, intsts 0x%08x\n",
3100                                         chan->hcint,
3101 -                                       readl(hsotg->regs + GINTSTS));
3102 +                                       dwc2_readl(hsotg->regs + GINTSTS));
3103                                 goto error;
3104                         }
3105                 }
3106 @@ -1922,11 +1922,11 @@ static void dwc2_hc_n_intr(struct dwc2_h
3107
3108         chan = hsotg->hc_ptr_array[chnum];
3109
3110 -       hcint = readl(hsotg->regs + HCINT(chnum));
3111 -       hcintmsk = readl(hsotg->regs + HCINTMSK(chnum));
3112 +       hcint = dwc2_readl(hsotg->regs + HCINT(chnum));
3113 +       hcintmsk = dwc2_readl(hsotg->regs + HCINTMSK(chnum));
3114         if (!chan) {
3115                 dev_err(hsotg->dev, "## hc_ptr_array for channel is NULL ##\n");
3116 -               writel(hcint, hsotg->regs + HCINT(chnum));
3117 +               dwc2_writel(hcint, hsotg->regs + HCINT(chnum));
3118                 return;
3119         }
3120
3121 @@ -1938,7 +1938,7 @@ static void dwc2_hc_n_intr(struct dwc2_h
3122                          hcint, hcintmsk, hcint & hcintmsk);
3123         }
3124
3125 -       writel(hcint, hsotg->regs + HCINT(chnum));
3126 +       dwc2_writel(hcint, hsotg->regs + HCINT(chnum));
3127         chan->hcint = hcint;
3128         hcint &= hcintmsk;
3129
3130 @@ -2030,7 +2030,7 @@ static void dwc2_hc_intr(struct dwc2_hso
3131         u32 haint;
3132         int i;
3133
3134 -       haint = readl(hsotg->regs + HAINT);
3135 +       haint = dwc2_readl(hsotg->regs + HAINT);
3136         if (dbg_perio()) {
3137                 dev_vdbg(hsotg->dev, "%s()\n", __func__);
3138
3139 @@ -2098,8 +2098,8 @@ irqreturn_t dwc2_handle_hcd_intr(struct
3140                                  "DWC OTG HCD Finished Servicing Interrupts\n");
3141                         dev_vdbg(hsotg->dev,
3142                                  "DWC OTG HCD gintsts=0x%08x gintmsk=0x%08x\n",
3143 -                                readl(hsotg->regs + GINTSTS),
3144 -                                readl(hsotg->regs + GINTMSK));
3145 +                                dwc2_readl(hsotg->regs + GINTSTS),
3146 +                                dwc2_readl(hsotg->regs + GINTMSK));
3147                 }
3148         }
3149
3150 --- a/drivers/usb/dwc2/hcd_queue.c
3151 +++ b/drivers/usb/dwc2/hcd_queue.c
3152 @@ -115,7 +115,7 @@ static void dwc2_qh_init(struct dwc2_hso
3153                 if (qh->ep_type == USB_ENDPOINT_XFER_INT)
3154                         qh->interval = 8;
3155  #endif
3156 -               hprt = readl(hsotg->regs + HPRT0);
3157 +               hprt = dwc2_readl(hsotg->regs + HPRT0);
3158                 prtspd = (hprt & HPRT0_SPD_MASK) >> HPRT0_SPD_SHIFT;
3159                 if (prtspd == HPRT0_SPD_HIGH_SPEED &&
3160                     (dev_speed == USB_SPEED_LOW ||
3161 @@ -593,9 +593,9 @@ int dwc2_hcd_qh_add(struct dwc2_hsotg *h
3162         if (status)
3163                 return status;
3164         if (!hsotg->periodic_qh_count) {
3165 -               intr_mask = readl(hsotg->regs + GINTMSK);
3166 +               intr_mask = dwc2_readl(hsotg->regs + GINTMSK);
3167                 intr_mask |= GINTSTS_SOF;
3168 -               writel(intr_mask, hsotg->regs + GINTMSK);
3169 +               dwc2_writel(intr_mask, hsotg->regs + GINTMSK);
3170         }
3171         hsotg->periodic_qh_count++;
3172
3173 @@ -630,9 +630,9 @@ void dwc2_hcd_qh_unlink(struct dwc2_hsot
3174         dwc2_deschedule_periodic(hsotg, qh);
3175         hsotg->periodic_qh_count--;
3176         if (!hsotg->periodic_qh_count) {
3177 -               intr_mask = readl(hsotg->regs + GINTMSK);
3178 +               intr_mask = dwc2_readl(hsotg->regs + GINTMSK);
3179                 intr_mask &= ~GINTSTS_SOF;
3180 -               writel(intr_mask, hsotg->regs + GINTMSK);
3181 +               dwc2_writel(intr_mask, hsotg->regs + GINTMSK);
3182         }
3183  }
3184