target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/ddr2/mvDramIfBasicInit.S

   1 /*******************************************************************************
   2 Copyright (C) Marvell International Ltd. and its affiliates
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  36 If you received this File from Marvell, you may opt to use, redistribute and/or
  37 modify this File under the following licensing terms.
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  48     *   Neither the name of Marvell nor the names of its contributors may be
  49         used to endorse or promote products derived from this software without
  50         specific prior written permission.
  51
  52 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
  53 ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  54 WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  55 DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
  56 ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  57 (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  58 LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
  59 ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  60 (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  61 SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  62
  63 *******************************************************************************/
  64
  65 #define _ASMLANGUAGE
  66 #define MV_ASMLANGUAGE
  67 #include "mvSysHwConfig.h"
  68 #include "mvOsAsm.h"
  69 #include "boardEnv/mvBoardEnvSpec.h"
  70 #include "ctrlEnv/sys/mvCpuIfRegs.h"
  71 #include "mvDramIfConfig.h"
  72 #include "mvDramIfRegs.h"
  73 #include "pex/mvPexRegs.h"
  74 #include "ctrlEnv/mvCtrlEnvSpec.h"
  75 #include "ctrlEnv/mvCtrlEnvAsm.h"
  76 #include "mvCommon.h"
  77
  78 /* defines */
  79
  80 #if defined(MV_STATIC_DRAM_ON_BOARD)
  81 .globl dramBoot1
  82 dramBoot1:
  83         .word   0
  84
  85 /******************************************************************************
  86 *
  87 *
  88 *
  89 *
  90 *******************************************************************************/
  91 #if defined(DB_MV78XX0) || defined(DB_MV88F632X)
  92 /* DDR2 boards 512MB 333MHz */
  93 #define STATIC_SDRAM0_BANK0_SIZE                0x1ffffff1 /*   0x1504  */
  94 #define STATIC_SDRAM_CONFIG                     0x43048C30 /*   0x1400  */
  95 #define STATIC_SDRAM_MODE                       0x00000652 /*   0x141c  */
  96 #define STATIC_DUNIT_CTRL_LOW                   0x38543000 /*   0x1404  */
  97 #define STATIC_DUNIT_CTRL_HI                    0x0000FFFF /*   0x1424  */
  98 #define STATIC_SDRAM_ADDR_CTRL                  0x00000088 /*   0x1410  */
  99 #define STATIC_SDRAM_TIME_CTRL_LOW              0x22125441 /*   0x1408  */
 100 #define STATIC_SDRAM_TIME_CTRL_HI               0x00000A29 /*   0x140c  */
 101 #define STATIC_SDRAM_ODT_CTRL_LOW               0x84210000 /*   0x1494  */
 102 #define STATIC_SDRAM_ODT_CTRL_HI                0x00000000 /*   0x1498  */
 103 #define STATIC_SDRAM_DUNIT_ODT_CTRL             0x0000E80F /*   0x149c  */
 104 #define STATIC_SDRAM_EXT_MODE                   0x00000040 /*   0x1420  */
 105 #define STATIC_SDRAM_DDR2_TIMING_LO             0x00085520 /*   0x1428  */
 106 #define STATIC_SDRAM_DDR2_TIMING_HI             0x00008552 /*   0x147C  */
 107
 108 #elif defined(RD_MV78XX0_AMC)
 109 /* On board DDR2 512MB 400MHz CL5 */
 110 #define STATIC_SDRAM0_BANK0_SIZE                0x1ffffff1 /*   0x1504  */
 111 #define STATIC_SDRAM_CONFIG                     0x43008C30 /*   0x1400  */
 112 #define STATIC_SDRAM_MODE                       0x00000652 /*   0x141c  */
 113 #define STATIC_DUNIT_CTRL_LOW                   0x38543000 /*   0x1404  */
 114 #define STATIC_DUNIT_CTRL_HI                    0x0000F07F /*   0x1424  */
 115 #define STATIC_SDRAM_ADDR_CTRL                  0x000000DD /*   0x1410  */
 116 #define STATIC_SDRAM_TIME_CTRL_LOW              0x23135441 /*   0x1408  */
 117 #define STATIC_SDRAM_TIME_CTRL_HI               0x00000A32 /*   0x140c  */
 118 #define STATIC_SDRAM_ODT_CTRL_LOW               0x84210000 /*   0x1494  */
 119 #define STATIC_SDRAM_ODT_CTRL_HI                0x00000000 /*   0x1498  */
 120 #define STATIC_SDRAM_DUNIT_ODT_CTRL             0x0000EB0F /*   0x149c  */
 121 #define STATIC_SDRAM_EXT_MODE                   0x00000040 /*   0x1420  */
 122 #define STATIC_SDRAM_DDR2_TIMING_LO             0x00085520 /*   0x1428  */
 123 #define STATIC_SDRAM_DDR2_TIMING_HI             0x00008552 /*   0x147C  */
 124
 125 #elif defined(RD_MV78XX0_H3C)
 126 /* DDR2 boards 512MB 333MHz */
 127 #define STATIC_SDRAM0_BANK0_SIZE                0x1ffffff1 /*   0x1504  */
 128 #define STATIC_SDRAM_CONFIG                     0x43048a25 /*   0x1400  */
 129 #define STATIC_SDRAM_MODE                       0x00000652 /*   0x141c  */
 130 #define STATIC_DUNIT_CTRL_LOW                   0x38543000 /*   0x1404  */
 131 #define STATIC_DUNIT_CTRL_HI                    0x0000F07F /*   0x1424  */
 132 #define STATIC_SDRAM_ADDR_CTRL                  0x00000088 /*   0x1410  */
 133 #define STATIC_SDRAM_TIME_CTRL_LOW              0x2202444e /*   0x1408  */
 134 #define STATIC_SDRAM_TIME_CTRL_HI               0x00000A22 /*   0x140c  */
 135 #define STATIC_SDRAM_ODT_CTRL_LOW               0x84210000 /*   0x1494  */
 136 #define STATIC_SDRAM_ODT_CTRL_HI                0x00000000 /*   0x1498  */
 137 #define STATIC_SDRAM_DUNIT_ODT_CTRL             0x0000EB0F /*   0x149c  */
 138 #define STATIC_SDRAM_EXT_MODE                   0x00000040 /*   0x1420  */
 139 #define STATIC_SDRAM_DDR2_TIMING_LO             0x00085520 /*   0x1428  */
 140 #define STATIC_SDRAM_DDR2_TIMING_HI             0x00008552 /*   0x147C  */
 141
 142 #elif defined(RD_MV78XX0_PCAC)
 143 /* DDR2 boards 256MB 200MHz */
 144 #define STATIC_SDRAM0_BANK0_SIZE                0x0ffffff1 /*   0x1504  */
 145 #define STATIC_SDRAM_CONFIG                     0x43000a25 /*   0x1400  */
 146 #define STATIC_SDRAM_MODE                       0x00000652 /*   0x141c  */
 147 #define STATIC_DUNIT_CTRL_LOW                   0x38543000 /*   0x1404  */
 148 #define STATIC_DUNIT_CTRL_HI                    0x0000F07F /*   0x1424  */
 149 #define STATIC_SDRAM_ADDR_CTRL                  0x000000DD /*   0x1410  */
 150 #define STATIC_SDRAM_TIME_CTRL_LOW              0x2202444e /*   0x1408  */
 151 #define STATIC_SDRAM_TIME_CTRL_HI               0x00000822 /*   0x140c  */
 152 #define STATIC_SDRAM_ODT_CTRL_LOW               0x84210000 /*   0x1494  */
 153 #define STATIC_SDRAM_ODT_CTRL_HI                0x00000000 /*   0x1498  */
 154 #define STATIC_SDRAM_DUNIT_ODT_CTRL             0x0000EB0F /*   0x149c  */
 155 #define STATIC_SDRAM_EXT_MODE                   0x00000040 /*   0x1420  */
 156 #define STATIC_SDRAM_DDR2_TIMING_LO             0x00085520 /*   0x1428  */
 157 #define STATIC_SDRAM_DDR2_TIMING_HI             0x00008552 /*   0x147C  */
 158
 159 #else
 160 /* DDR2 MV88F6281 boards 256MB 400MHz */
 161 #define STATIC_SDRAM0_BANK0_SIZE                0x0FFFFFF1 /*   0x1504  */
 162 #define STATIC_SDRAM_CONFIG                     0x43000c30 /*   0x1400  */
 163 #define STATIC_SDRAM_MODE                       0x00000C52 /*   0x141c  */
 164 #define STATIC_DUNIT_CTRL_LOW                   0x39543000 /*   0x1404  */
 165 #define STATIC_DUNIT_CTRL_HI                    0x0000F1FF /*   0x1424  */
 166 #define STATIC_SDRAM_ADDR_CTRL                  0x000000cc /*   0x1410  */
 167 #define STATIC_SDRAM_TIME_CTRL_LOW              0x22125451 /*   0x1408  */
 168 #define STATIC_SDRAM_TIME_CTRL_HI               0x00000A33 /*   0x140c  */
 169 #define STATIC_SDRAM_ODT_CTRL_LOW               0x003C0000 /*   0x1494  */
 170 #define STATIC_SDRAM_ODT_CTRL_HI                0x00000000 /*   0x1498  */
 171 #define STATIC_SDRAM_DUNIT_ODT_CTRL             0x0000F80F /*   0x149c  */
 172 #define STATIC_SDRAM_EXT_MODE                   0x00000042 /*   0x1420  */
 173 #define STATIC_SDRAM_DDR2_TIMING_LO             0x00085520 /*   0x1428  */
 174 #define STATIC_SDRAM_DDR2_TIMING_HI             0x00008552 /*   0x147C  */
 175 #endif /* MV78XX0 */
 176
 177         .globl _mvDramIfStaticInit
 178 _mvDramIfStaticInit:
 179
 180         mov     r11, LR                 /* Save link register */
 181         mov     r10, r2
 182
 183 #ifdef MV78XX0
 184         MV_REG_READ_ASM (r6, r5, SDRAM_DUNIT_CTRL_REG)
 185         orr     r6, r6, #BIT4   /* Enable 2T mode */
 186         bic     r6, r6, #BIT6   /* clear ctrlPos */
 187         MV_REG_WRITE_ASM (r6, r5, SDRAM_DUNIT_CTRL_REG)
 188 #endif
 189
 190         /*DDR SDRAM Initialization Control */
 191         ldr     r6, =DSICR_INIT_EN
 192         MV_REG_WRITE_ASM (r6, r1, DDR_SDRAM_INIT_CTRL_REG)
 193 2:      MV_REG_READ_ASM (r6, r1, DDR_SDRAM_INIT_CTRL_REG)
 194          and    r6, r6, #DSICR_INIT_EN
 195          cmp    r6, #0
 196          bne 2b
 197
 198         /* If we boot from NAND jump to DRAM address */
 199         mov     r5, #1
 200         ldr     r6, =dramBoot1
 201         str     r5, [r6]                /* We started executing from DRAM */
 202
 203         ldr     r6, dramBoot1
 204         cmp     r6, #0
 205         bne     1f
 206
 207         /* set all dram windows to 0 */
 208         mov     r6, #0
 209         MV_REG_WRITE_ASM(r6, r5, SDRAM_SIZE_REG(0,0))
 210         MV_REG_WRITE_ASM(r6, r5, SDRAM_SIZE_REG(0,1))
 211         MV_REG_WRITE_ASM(r6, r5, SDRAM_SIZE_REG(0,2))
 212         MV_REG_WRITE_ASM(r6, r5, SDRAM_SIZE_REG(0,3))
 213         ldr     r6, = STATIC_SDRAM0_BANK0_SIZE
 214         MV_REG_WRITE_ASM(r6, r5, SDRAM_SIZE_REG(0,0))
 215
 216
 217         /* set all dram configuration in temp registers */
 218         ldr     r6, = STATIC_SDRAM0_BANK0_SIZE
 219         MV_REG_WRITE_ASM(r6, r5, DRAM_BUF_REG0)
 220         ldr     r6, = STATIC_SDRAM_CONFIG
 221         MV_REG_WRITE_ASM(r6, r5, DRAM_BUF_REG1)
 222         ldr     r6, = STATIC_SDRAM_MODE
 223         MV_REG_WRITE_ASM(r6, r5, DRAM_BUF_REG2)
 224         ldr     r6, = STATIC_DUNIT_CTRL_LOW
 225         MV_REG_WRITE_ASM(r6, r5, DRAM_BUF_REG3)
 226         ldr     r6, = STATIC_SDRAM_ADDR_CTRL
 227         MV_REG_WRITE_ASM(r6, r5, DRAM_BUF_REG4)
 228         ldr     r6, = STATIC_SDRAM_TIME_CTRL_LOW
 229         MV_REG_WRITE_ASM(r6, r5, DRAM_BUF_REG5)
 230         ldr     r6, = STATIC_SDRAM_TIME_CTRL_HI
 231         MV_REG_WRITE_ASM(r6, r5, DRAM_BUF_REG6)
 232         ldr     r6, = STATIC_SDRAM_ODT_CTRL_LOW
 233         MV_REG_WRITE_ASM(r6, r5, DRAM_BUF_REG7)
 234         ldr     r6, = STATIC_SDRAM_ODT_CTRL_HI
 235         MV_REG_WRITE_ASM(r6, r5, DRAM_BUF_REG8)
 236         ldr     r6, = STATIC_SDRAM_DUNIT_ODT_CTRL
 237         MV_REG_WRITE_ASM(r6, r5, DRAM_BUF_REG9)
 238         ldr     r6, = STATIC_SDRAM_EXT_MODE
 239         MV_REG_WRITE_ASM(r6, r5, DRAM_BUF_REG10)
 240         ldr     r6, = STATIC_SDRAM_DDR2_TIMING_LO
 241         MV_REG_WRITE_ASM(r6, r5, DRAM_BUF_REG11)
 242         ldr     r6, = STATIC_SDRAM_DDR2_TIMING_HI
 243         MV_REG_WRITE_ASM(r6, r5, DRAM_BUF_REG12)
 244 #ifndef MV_NAND_BOOT
 245         ldr     r6, = STATIC_DUNIT_CTRL_HI
 246         MV_REG_WRITE_ASM(r6, r5, DRAM_BUF_REG13)
 247 #endif
 248
 249         ldr     sp,=0
 250         bl      _mvDramIfConfig
 251         ldr     r0, =0
 252 #ifdef MV78XX0
 253         bl      _mvDramIfEccMemInit
 254 #endif
 255 1:
 256         mov     r2, r10
 257         mov     PC, r11                 /* r11 is saved link register */
 258
 259 #else  /* #if defined(MV_STATIC_DRAM_ON_BOARD) */
 260
 261 .globl dramBoot1
 262 dramBoot1:
 263         .word   0
 264
 265 /*******************************************************************************
 266 * mvDramIfBasicInit - Basic initialization of DRAM interface
 267 *
 268 * DESCRIPTION:
 269 *       The function will initialize the DRAM for basic usage. The function
 270 *       will use the TWSI assembly API to extract DIMM parameters according
 271 *       to which DRAM interface will be initialized.
 272 *       The function referes to the following DRAM parameters:
 273 *       1) DIMM is registered or not.
 274 *       2) DIMM width detection.
 275 *       3) DIMM density.
 276 *
 277 * INPUT:
 278 *       r3 - required size for initial DRAM.
 279 *
 280 * OUTPUT:
 281 *       None.
 282 *
 283 * RETURN:
 284 *       None.
 285 *
 286 *       Note:
 287 *       r4 holds I2C EEPROM address
 288 *       r5 holds SDRAM register base address
 289 *       r7 holds returned values
 290 *       r8 holds SDRAM various configuration registers value.
 291 *       r11 holds return function address.
 292 *******************************************************************************/
 293 /* Setting the offsets of the I2C registers */
 294 #define DIMM_TYPE_OFFSET              2
 295 #define NUM_OF_ROWS_OFFSET            3
 296 #define NUM_OF_COLS_OFFSET            4
 297 #define NUM_OF_RANKS                  5
 298 #define DIMM_CONFIG_TYPE             11
 299 #define SDRAM_WIDTH_OFFSET           13
 300 #define NUM_OF_BANKS_OFFSET          17
 301 #define SUPPORTED_CL_OFFSET          18
 302 #define DIMM_TYPE_INFO_OFFSET        20         /* DDR2 only    */
 303 #define SDRAM_MODULES_ATTR_OFFSET    21
 304 #define RANK_SIZE_OFFSET             31
 305
 306 #define DRAM_DEV_DENSITY_128M         128
 307 #define DRAM_DEV_DENSITY_256M         256
 308 #define DRAM_DEV_DENSITY_512M         512
 309 #define DRAM_DEV_DENSITY_1G          1024
 310 #define DRAM_DEV_DENSITY_2G          2048
 311
 312 #define DRAM_RANK_DENSITY_128M       0x20
 313 #define DRAM_RANK_DENSITY_256M       0x40
 314 #define DRAM_RANK_DENSITY_512M       0x80
 315 #define DRAM_RANK_DENSITY_1G         0x1
 316 #define DRAM_RANK_DENSITY_2G         0x2
 317
 318        .globl _mvDramIfBasicInit
 319        .extern _i2cInit
 320 _mvDramIfBasicInit:
 321
 322         mov     r11, LR                 /* Save link register */
 323
 324         /* Set Dunit high control register            */
 325         MV_REG_READ_ASM (r6, r5, SDRAM_DUNIT_CTRL_HI_REG)
 326         orr     r6, r6, #BIT7 /* SDRAM__D2P_EN */
 327         orr     r6, r6, #BIT8 /* SDRAM__P2D_EN */
 328 #ifdef MV78XX0
 329         orr     r6, r6, #BIT9 /* SDRAM__ADD_HALF_FCC_EN */
 330         orr     r6, r6, #BIT10 /* SDRAM__PUP_ZERO_SKEW_EN */
 331         orr     r6, r6, #BIT11 /* SDRAM__WR_MASH_DELAY_EN */
 332 #endif
 333         MV_REG_WRITE_ASM (r6, r5, SDRAM_DUNIT_CTRL_HI_REG)
 334
 335 #ifdef MV78XX0
 336         MV_REG_READ_ASM (r6, r5, SDRAM_DUNIT_CTRL_REG)
 337         orr     r6, r6, #BIT4   /* Enable 2T mode */
 338         bic     r6, r6, #BIT6   /* clear ctrlPos */
 339         MV_REG_WRITE_ASM (r6, r5, SDRAM_DUNIT_CTRL_REG)
 340 #endif
 341
 342         /*DDR SDRAM Initialization Control */
 343         ldr     r6, =DSICR_INIT_EN
 344         MV_REG_WRITE_ASM (r6, r1, DDR_SDRAM_INIT_CTRL_REG)
 345 2:      MV_REG_READ_ASM (r6, r1, DDR_SDRAM_INIT_CTRL_REG)
 346          and    r6, r6, #DSICR_INIT_EN
 347          cmp    r6, #0
 348          bne 2b
 349
 350         mov     r5, #1
 351         ldr     r8, =dramBoot1
 352         str     r5, [r8]                /* We started executing from DRAM */
 353
 354         /* If we boot from NAND jump to DRAM address */
 355         ldr     r8, dramBoot1
 356         cmp     r8, #0
 357         movne   pc, r11
 358
 359         bl      _i2cInit                /* Initialize TWSI master             */
 360
 361         /* Check if we have more then 1 dimm */
 362         ldr     r6, =0
 363         MV_REG_WRITE_ASM (r6, r1, DRAM_BUF_REG14)
 364 #ifdef MV78XX0
 365         bl _is_Second_Dimm_Exist
 366         beq single_dimm
 367         ldr     r6, =1
 368         MV_REG_WRITE_ASM (r6, r1, DRAM_BUF_REG14)
 369 single_dimm:
 370         bl      _i2cInit                /* Initialize TWSI master             */
 371 #endif
 372
 373         /* Get default SDRAM Config values */
 374         MV_REG_READ_ASM (r8, r5, SDRAM_CONFIG_REG)
 375
 376         /* Get registered/non registered info from DIMM */
 377         bl      _is_Registered
 378         beq     nonRegistered
 379
 380 setRegistered:
 381         orr     r8, r8, #SDRAM_REGISTERED   /* Set registered bit(17)         */
 382 nonRegistered:
 383 #ifdef MV78XX0
 384         /* Get ECC/non ECC info from DIMM */
 385         bl      _is_Ecc
 386         beq     setConfigReg
 387
 388 setEcc:
 389         orr     r8, r8, #SDRAM_ECC_EN   /* Set ecc bit(18)         */
 390 #endif
 391 setConfigReg:
 392         MV_REG_WRITE_ASM (r8, r5, DRAM_BUF_REG1)
 393
 394         /* Set maximum CL supported by DIMM */
 395         bl      _get_CAL
 396
 397         /* r7 is DIMM supported CAS (e.g: 3 --> 0x1C)                         */
 398         clz     r6, r7
 399         rsb     r6, r6, #31     /* r6 = the bit number of MAX CAS supported   */
 400
 401 casDdr2:
 402         ldr     r7, =0x41        /* stBurstInDel|stBurstOutDel field value     */
 403         ldr     r3, =0x53       /* stBurstInDel|stBurstOutDel registered value*/
 404         ldr     r8, =0x32      /* Assuming MAX CL = 3           */
 405         cmp     r6, #3          /* If CL = 3 break              */
 406         beq     casDdr2Cont
 407
 408         ldr     r7, =0x53        /* stBurstInDel|stBurstOutDel field value     */
 409         ldr     r3, =0x65       /* stBurstInDel|stBurstOutDel registered value*/
 410         ldr     r8, =0x42      /* Assuming MAX CL = 4           */
 411         cmp     r6, #4          /* If CL = 4 break              */
 412         beq     casDdr2Cont
 413
 414         ldr     r7, =0x65        /* stBurstInDel|stBurstOutDel field value     */
 415         ldr     r3, =0x77       /* stBurstInDel|stBurstOutDel registered value*/
 416         ldr     r8, =0x52      /* Assuming MAX CL = 5           */
 417         cmp     r6, #5          /* If CL = 5 break              */
 418         beq     casDdr2Cont
 419
 420         ldr     r7, =0x77        /* stBurstInDel|stBurstOutDel field value     */
 421         ldr     r3, =0x89       /* stBurstInDel|stBurstOutDel registered value*/
 422         ldr     r8, =0x62      /* Assuming MAX CL = 6           */
 423         cmp     r6, #6          /* If CL = 5 break              */
 424         beq     casDdr2Cont
 425
 426         /* This is an error. return */
 427         b       exit_ddrAutoConfig      /* This is an error !!  */
 428 casDdr2Cont:
 429
 430         /* Get default SDRAM Mode values */
 431         MV_REG_READ_ASM (r6, r5, SDRAM_MODE_REG)
 432         bic     r6, r6, #(BIT6 | BIT5 | BIT4) /* Clear CL filed */
 433         orr     r6, r6, r8
 434         MV_REG_WRITE_ASM (r6, r5, DRAM_BUF_REG2)
 435
 436         /* Set Dunit control register according to max CL detected            */
 437         MV_REG_READ_ASM (r6, r5, DRAM_BUF_REG1)
 438         tst     r6, #SDRAM_REGISTERED
 439         beq     setDunitReg
 440         mov     r7, r3
 441
 442 setDunitReg:
 443 #ifdef MV78XX0
 444         /* Set SDRAM Extended Mode register for double DIMM */
 445         /* Check DRAM frequency for more then 267MHz set ODT Rtt to 50ohm */
 446
 447         MV_REG_READ_ASM (r4, r5, CPU_RESET_SAMPLE_L_REG)
 448         ldr     r5, =MSAR_SYSCLCK_MASK
 449         and     r4, r4, r5
 450         ldr     r5, =MSAR_SYSCLCK_333
 451         cmp     r4, r5
 452         ble     Clock333
 453         add r7, r7, #0x10
 454 Clock333:
 455 #endif
 456
 457         MV_REG_READ_ASM (r6, r5, SDRAM_DUNIT_CTRL_REG)
 458         bic     r6, r6, #(0xff << 20) /* Clear SBout and SBin */
 459         orr     r6, r6, #BIT4   /* Enable 2T mode */
 460         bic     r6, r6, #BIT6   /* clear ctrlPos */
 461         orr     r6, r6, r7, LSL #20
 462         MV_REG_WRITE_ASM (r6, r5, DRAM_BUF_REG3)
 463
 464         /* Set Dunit high control register            */
 465         MV_REG_READ_ASM (r6, r5, SDRAM_DUNIT_CTRL_HI_REG)
 466         orr     r6, r6, #BIT7 /* SDRAM__D2P_EN */
 467         orr     r6, r6, #BIT8 /* SDRAM__P2D_EN */
 468 #ifdef MV78XX0
 469         orr     r6, r6, #BIT9 /* SDRAM__ADD_HALF_FCC_EN */
 470         orr     r6, r6, #BIT10 /* SDRAM__PUP_ZERO_SKEW_EN */
 471         orr     r6, r6, #BIT11 /* SDRAM__WR_MASH_DELAY_EN */
 472 #endif
 473         MV_REG_WRITE_ASM (r6, r5, DRAM_BUF_REG13)
 474
 475         /* DIMM density configuration*/
 476         /* Density = (1 << (rowNum + colNum)) * dramWidth * dramBankNum       */
 477 Density:
 478         /* Get bank 0 and 1 density */
 479         ldr     r6, =0
 480         bl      _getDensity
 481
 482         mov     r8, r7
 483         mov     r8, r8, LSR #20 /* Move density 20 bits to the right  */
 484                                 /* For example 0x10000000 --> 0x1000 */
 485
 486         mov     r3, #(SDRAM_DSIZE_256Mb(0) | SDRAM_DSIZE_256Mb(1))
 487         cmp     r8, #DRAM_DEV_DENSITY_256M
 488         beq     get_bank_2_density
 489
 490         mov     r3, #(SDRAM_DSIZE_512Mb(0) | SDRAM_DSIZE_512Mb(1))
 491         cmp     r8, #DRAM_DEV_DENSITY_512M
 492         beq     get_bank_2_density
 493
 494         mov     r3, #(SDRAM_DSIZE_1Gb(0) | SDRAM_DSIZE_1Gb(1))
 495         cmp     r8, #DRAM_DEV_DENSITY_1G
 496         beq     get_bank_2_density
 497
 498         mov     r3, #(SDRAM_DSIZE_2Gb(0) | SDRAM_DSIZE_2Gb(1))
 499         cmp     r8, #DRAM_DEV_DENSITY_2G
 500         beq     get_bank_2_density
 501
 502         /* This is an error. return */
 503         b       exit_ddrAutoConfig
 504
 505 get_bank_2_density:
 506         /* Check for second dimm */
 507         MV_REG_READ_ASM (r6, r1, DRAM_BUF_REG14)
 508         cmp     r6, #1
 509         bne     get_width
 510
 511         /* Get bank 2 and 3 density */
 512         ldr     r6, =2
 513         bl      _getDensity
 514
 515         mov     r8, r7
 516         mov     r8, r8, LSR #20 /* Move density 20 bits to the right  */
 517                                 /* For example 0x10000000 --> 0x1000 */
 518
 519         orr     r3, r3, #(SDRAM_DSIZE_256Mb(2) | SDRAM_DSIZE_256Mb(3))
 520         cmp     r8, #DRAM_DEV_DENSITY_256M
 521         beq     get_width
 522
 523         and     r3, r3, #~(SDRAM_DSIZE_MASK(2) | SDRAM_DSIZE_MASK(3))
 524         orr     r3, r3, #(SDRAM_DSIZE_512Mb(2) | SDRAM_DSIZE_512Mb(3))
 525         cmp     r8, #DRAM_DEV_DENSITY_512M
 526         beq     get_width
 527
 528         and     r3, r3, #~(SDRAM_DSIZE_MASK(2) | SDRAM_DSIZE_MASK(3))
 529         orr     r3, r3, #(SDRAM_DSIZE_1Gb(2) | SDRAM_DSIZE_1Gb(3))
 530         cmp     r8, #DRAM_DEV_DENSITY_1G
 531         beq     get_width
 532
 533         and     r3, r3, #~(SDRAM_DSIZE_MASK(2) | SDRAM_DSIZE_MASK(3))
 534         orr     r3, r3, #(SDRAM_DSIZE_2Gb(2) | SDRAM_DSIZE_2Gb(3))
 535         cmp     r8, #DRAM_DEV_DENSITY_2G
 536         beq     get_width
 537
 538         /* This is an error. return */
 539         b       exit_ddrAutoConfig
 540
 541         /* Get SDRAM width */
 542 get_width:
 543         /* Get bank 0 and 1 width */
 544         ldr     r6, =0
 545         bl      _get_width
 546
 547         cmp     r7, #8           /* x8 devices   */
 548         beq     get_bank_2_width
 549
 550         orr     r3, r3, #(SDRAM_ADDRSEL_X16(0) | SDRAM_ADDRSEL_X16(1)) /* x16 devices  */
 551         cmp     r7, #16
 552         beq     get_bank_2_width
 553
 554         /* This is an error. return */
 555         b       exit_ddrAutoConfig
 556
 557 get_bank_2_width:
 558         /* Check for second dimm */
 559         MV_REG_READ_ASM (r6, r1, DRAM_BUF_REG14)
 560         cmp     r6, #1
 561         bne     densCont
 562
 563         /* Get bank 2 and 3 width */
 564         ldr     r6, =2
 565         bl      _get_width
 566
 567         cmp     r7, #8           /* x8 devices   */
 568         beq     densCont
 569
 570         orr     r3, r3, #(SDRAM_ADDRSEL_X16(2) | SDRAM_ADDRSEL_X16(3)) /* x16 devices  */
 571         cmp     r7, #16
 572         beq     densCont
 573
 574         /* This is an error. return */
 575         b       exit_ddrAutoConfig
 576
 577 densCont:
 578         MV_REG_WRITE_ASM (r3, r5, DRAM_BUF_REG4)
 579
 580         /* Set SDRAM timing control low register */
 581         ldr     r4, =SDRAM_TIMING_CTRL_LOW_REG_DEFAULT
 582         /* MV_REG_READ_ASM (r4, r5, SDRAM_TIMING_CTRL_LOW_REG) */
 583         MV_REG_WRITE_ASM(r4, r5, DRAM_BUF_REG5)
 584
 585         /* Set SDRAM timing control high register */
 586         ldr     r6, =SDRAM_TIMING_CTRL_HIGH_REG_DEFAULT
 587
 588     MV_REG_READ_ASM (r4, r5, CPU_RESET_SAMPLE_L_REG)
 589         ldr     r5, =MSAR_SYSCLCK_MASK
 590         and     r4, r4, r5
 591         ldr     r5, =MSAR_SYSCLCK_333
 592         cmp     r4, r5
 593         blt     timingHighClock333
 594     orr r6, r6, #BIT9
 595
 596 timingHighClock333:
 597     /* MV_REG_READ_ASM (r6, r5, SDRAM_TIMING_CTRL_HIGH_REG) */
 598     MV_REG_WRITE_ASM(r6, r5, DRAM_BUF_REG6)
 599
 600         /* Check for second dimm */
 601         MV_REG_READ_ASM (r6, r1, DRAM_BUF_REG14)
 602         cmp     r6, #1
 603         bne     single_dimm_odt
 604
 605         /* Set SDRAM ODT control low register for double DIMM*/
 606         ldr     r4, =DDR2_ODT_CTRL_LOW_CS0_CS1_CS2_CS3_DV
 607         MV_REG_WRITE_ASM(r4, r5, DRAM_BUF_REG7)
 608
 609         /* Set DUNIT ODT control register for double DIMM */
 610         ldr     r4, =DDR2_DUNIT_ODT_CTRL_CS0_CS1_CS2_CS3_DV
 611         MV_REG_WRITE_ASM(r4, r5, DRAM_BUF_REG9)
 612
 613 #ifdef MV78XX0
 614         /* Set SDRAM Extended Mode register for double DIMM */
 615         /* Check DRAM frequency for more then 267MHz set ODT Rtt to 50ohm */
 616
 617         MV_REG_READ_ASM (r4, r5, CPU_RESET_SAMPLE_L_REG)
 618         ldr     r5, =MSAR_SYSCLCK_MASK
 619         and     r4, r4, r5
 620         ldr     r5, =MSAR_SYSCLCK_267
 621         cmp     r4, r5
 622         beq     slow_dram_clock_rtt
 623         ldr     r5, =MSAR_SYSCLCK_300
 624         cmp     r4, r5
 625         beq     slow_dram_clock_rtt
 626         ldr     r5, =MSAR_SYSCLCK_333
 627         cmp     r4, r5
 628         beq     fast_dram_clock_rtt
 629         ldr     r5, =MSAR_SYSCLCK_400
 630         cmp     r4, r5
 631         beq     fast_dram_clock_rtt
 632
 633         b       slow_dram_clock_rtt
 634
 635 fast_dram_clock_rtt:
 636         ldr     r4, =DDR_SDRAM_EXT_MODE_FAST_CS0_CS1_CS2_CS3_DV
 637         MV_REG_WRITE_ASM(r4, r5, DRAM_BUF_REG10)
 638         b odt_config_end
 639 #endif
 640 slow_dram_clock_rtt:
 641         ldr     r4, =DDR_SDRAM_EXT_MODE_CS0_CS1_CS2_CS3_DV
 642         MV_REG_WRITE_ASM(r4, r5, DRAM_BUF_REG10)
 643         b odt_config_end
 644
 645 single_dimm_odt:
 646         /* Set SDRAM ODT control low register */
 647         ldr     r4, =DDR2_ODT_CTRL_LOW_CS0_CS1_DV
 648         MV_REG_WRITE_ASM(r4, r5, DRAM_BUF_REG7)
 649
 650         /* Set DUNIT ODT control register */
 651         ldr     r4, =DDR2_DUNIT_ODT_CTRL_CS0_CS1_DV
 652         MV_REG_WRITE_ASM(r4, r5, DRAM_BUF_REG9)
 653
 654         /* Set SDRAM Extended Mode register */
 655         ldr     r4, =DDR_SDRAM_EXT_MODE_CS0_CS1_DV
 656         MV_REG_WRITE_ASM(r4, r5, DRAM_BUF_REG10)
 657
 658 odt_config_end:
 659         /* SDRAM ODT control high register is left as default */
 660         MV_REG_READ_ASM (r4, r5, DDR2_SDRAM_ODT_CTRL_HIGH_REG)
 661         MV_REG_WRITE_ASM(r4, r5, DRAM_BUF_REG8)
 662
 663         /*Read CL and set the DDR2 registers accordingly */
 664         MV_REG_READ_ASM (r6, r5, DRAM_BUF_REG2)
 665         and r6, r6, #SDRAM_CL_MASK
 666         mov r4, r6
 667         orr r4, r4, r6, LSL #4
 668         orr r4, r4, r6, LSL #8
 669         orr r4, r4, r6, LSL #12
 670         mov r5, #0x30000
 671         add r4, r4, r5
 672         sub r4, r4, #0x30
 673         /* Set SDRAM Ddr2 Timing Low register */
 674         MV_REG_WRITE_ASM(r4, r5, DRAM_BUF_REG11)
 675
 676         /* Set SDRAM Ddr2 Timing High register */
 677         mov r4, r4, LSR #4
 678         MV_REG_WRITE_ASM(r4, r5, DRAM_BUF_REG12)
 679
 680 timeParamDone:
 681         /* Close all windows */
 682         MV_REG_READ_ASM (r6, r5, SDRAM_SIZE_REG(0,0))
 683         and     r6, r6,#~SCSR_SIZE_MASK
 684         and     r6, r6,#~1
 685         MV_REG_WRITE_ASM (r6, r5, SDRAM_SIZE_REG(0,0))
 686         MV_REG_READ_ASM (r6, r5, SDRAM_SIZE_REG(0,1))
 687         and     r6, r6,#~SCSR_SIZE_MASK
 688         and     r6, r6,#~1
 689         MV_REG_WRITE_ASM (r6, r5, SDRAM_SIZE_REG(0,1))
 690         MV_REG_READ_ASM (r6, r5, SDRAM_SIZE_REG(0,2))
 691         and     r6, r6,#~SCSR_SIZE_MASK
 692         and     r6, r6,#~1
 693         MV_REG_WRITE_ASM (r6, r5, SDRAM_SIZE_REG(0,2))
 694         MV_REG_READ_ASM (r6, r5, SDRAM_SIZE_REG(0,3))
 695         and     r6, r6,#~SCSR_SIZE_MASK
 696         and     r6, r6,#~1
 697         MV_REG_WRITE_ASM (r6, r5, SDRAM_SIZE_REG(0,3))
 698
 699         /* Set sdram bank 0 size and enable it */
 700         ldr     r6, =0
 701         bl _mvDramIfGetDimmSizeFromSpd
 702 #ifdef MV78XX0
 703         /* Check DRAM width */
 704         MV_REG_READ_ASM (r4, r5, SDRAM_CONFIG_REG)
 705         ldr     r5, =SDRAM_DWIDTH_MASK
 706         and     r4, r4, r5
 707         ldr     r5, =SDRAM_DWIDTH_64BIT
 708         cmp     r4, r5
 709         beq     dram_64bit_width
 710         /* Utilize only 32bit width */
 711         mov     r8, r8, LSR #1
 712 #else
 713         /* Utilize only 16bit width */
 714         mov     r8, r8, LSR #2
 715 #endif
 716 dram_64bit_width:
 717         /* Update first dimm size return value R8 */
 718         MV_REG_READ_ASM (r5, r6, SDRAM_SIZE_REG(0,0))
 719         ldr     r6, =~SCSR_SIZE_MASK
 720         and     r5, r5, r6
 721         orr     r5, r5, r8
 722         MV_REG_WRITE_ASM(r5, r8, SDRAM_SIZE_REG(0,0))
 723
 724         /* Clear bank 2 size */
 725         MV_REG_READ_ASM (r6, r5, SDRAM_SIZE_REG(0,2))
 726         and     r6, r6,#~SCSR_SIZE_MASK
 727         MV_REG_WRITE_ASM (r6, r5, SDRAM_SIZE_REG(0,2))
 728
 729         /* Check for second dimm */
 730         MV_REG_READ_ASM (r6, r1, DRAM_BUF_REG14)
 731         cmp     r6, #1
 732         bne     defualt_order
 733
 734         /* Set sdram bank 2 size */
 735         ldr     r6, =2
 736         bl _mvDramIfGetDimmSizeFromSpd
 737 #ifdef MV78XX0
 738         /* Check DRAM width */
 739         MV_REG_READ_ASM (r4, r5, SDRAM_CONFIG_REG)
 740         ldr     r5, =SDRAM_DWIDTH_MASK
 741         and     r4, r4, r5
 742         ldr     r5, =SDRAM_DWIDTH_64BIT
 743         cmp     r4, r5
 744         beq     dram_64bit_width2
 745         /* Utilize only 32bit width */
 746         mov     r8, r8, LSR #1
 747 #else
 748         /* Utilize only 16bit width */
 749         mov     r8, r8, LSR #2
 750 #endif
 751 dram_64bit_width2:
 752         /* Update first dimm size return value R8 */
 753         MV_REG_READ_ASM (r5, r6, SDRAM_SIZE_REG(0,2))
 754         ldr     r6, =~SCSR_SIZE_MASK
 755         and     r5, r5, r6
 756         orr     r5, r5, r8
 757         MV_REG_WRITE_ASM(r5, r8, SDRAM_SIZE_REG(0,2))
 758
 759         /* Close windows 1 and 3 */
 760         MV_REG_READ_ASM (r6, r5, SDRAM_SIZE_REG(0,1))
 761         and     r6, r6,#~1
 762         MV_REG_WRITE_ASM (r6, r5, SDRAM_SIZE_REG(0,1))
 763         MV_REG_READ_ASM (r6, r5, SDRAM_SIZE_REG(0,3))
 764         and     r6, r6,#~1
 765         MV_REG_WRITE_ASM (r6, r5, SDRAM_SIZE_REG(0,3))
 766
 767         /* Check dimm size for setting dram bank order */
 768         MV_REG_READ_ASM (r6, r5, SDRAM_SIZE_REG(0,0))
 769         MV_REG_READ_ASM (r4, r5, SDRAM_SIZE_REG(0,2))
 770         and     r6, r6,#SCSR_SIZE_MASK
 771         and     r4, r4,#SCSR_SIZE_MASK
 772         cmp     r6, r4
 773         bge     defualt_order
 774
 775         /* Bank 2 is biger then bank 0 */
 776         ldr     r6,=0
 777         MV_REG_WRITE_ASM (r6, r5, SDRAM_BASE_ADDR_REG(0,2))
 778
 779         /* Open win 2 */
 780         MV_REG_READ_ASM (r6, r5, SDRAM_SIZE_REG(0,2))
 781         orr     r6, r6,#1
 782         MV_REG_WRITE_ASM (r6, r5, SDRAM_SIZE_REG(0,2))
 783
 784         ldr     sp,=0
 785         bl      _mvDramIfConfig
 786 #ifdef MV78XX0
 787         /* Init ECC on CS 2 */
 788         ldr     r0, =2
 789         bl      _mvDramIfEccMemInit
 790 #endif
 791         mov     PC, r11         /* r11 is saved link register */
 792
 793 defualt_order:
 794
 795         /* Open win 0 */
 796         MV_REG_READ_ASM (r6, r5, SDRAM_SIZE_REG(0,0))
 797         orr     r6, r6,#1
 798         MV_REG_WRITE_ASM (r6, r5, SDRAM_SIZE_REG(0,0))
 799
 800         ldr     sp,=0
 801         bl      _mvDramIfConfig
 802 #ifdef MV78XX0
 803         /* Init ECC on CS 0 */
 804         ldr     r0, =0
 805         bl      _mvDramIfEccMemInit
 806 #endif
 807 exit_ddrAutoConfig:
 808         mov     PC, r11         /* r11 is saved link register */
 809
 810
 811 /***************************************************************************************/
 812 /*       r4 holds I2C EEPROM address
 813  *       r7 holds I2C EEPROM offset parameter for i2cRead and its --> returned value
 814  *       r8 holds SDRAM various configuration registers value.
 815  *      r13 holds Link register
 816  */
 817 /**************************/
 818 _getDensity:
 819         mov     r13, LR                            /* Save link register */
 820
 821         /* Read SPD rank size from DIMM0 */
 822         mov     r4, #MV_BOARD_DIMM0_I2C_ADDR       /* reading from DIMM0      */
 823
 824         cmp     r6, #0
 825         beq     1f
 826
 827         /* Read SPD rank size from DIMM1 */
 828         mov     r4, #MV_BOARD_DIMM1_I2C_ADDR /* reading from DIMM1            */
 829
 830 1:
 831         mov     r7, #NUM_OF_ROWS_OFFSET            /* offset  3               */
 832         bl      _i2cRead
 833         mov     r8, r7                             /* r8 save number of rows  */
 834
 835         mov     r7, #NUM_OF_COLS_OFFSET            /* offset  4               */
 836         bl      _i2cRead
 837         add     r8, r8, r7                         /* r8 = number of rows + number of col */
 838
 839         mov     r7, #0x1
 840         mov     r8, r7, LSL r8                     /* r8 = (1 << r8)          */
 841
 842         mov     r7, #SDRAM_WIDTH_OFFSET            /* offset 13 */
 843         bl      _i2cRead
 844         mul     r8, r7, r8
 845
 846         mov     r7, #NUM_OF_BANKS_OFFSET           /* offset 17               */
 847         bl      _i2cRead
 848         mul     r7, r8, r7
 849
 850         mov     PC, r13
 851
 852 /**************************/
 853 _get_width:
 854         mov     r13, LR                 /* Save link register */
 855
 856         /* Read SPD rank size from DIMM0 */
 857         mov     r4, #MV_BOARD_DIMM0_I2C_ADDR /* reading from DIMM0            */
 858
 859         cmp     r6, #0
 860         beq     1f
 861
 862         /* Read SPD rank size from DIMM1 */
 863         mov     r4, #MV_BOARD_DIMM1_I2C_ADDR /* reading from DIMM1            */
 864
 865 1:
 866         /* Get SDRAM width (SPD offset 13) */
 867         mov     r7, #SDRAM_WIDTH_OFFSET
 868         bl      _i2cRead                /* result in r7                       */
 869
 870         mov     PC, r13
 871
 872 /**************************/
 873 _get_CAL:
 874         mov     r13, LR                 /* Save link register */
 875
 876         /* Set maximum CL supported by DIMM */
 877         mov     r4, #MV_BOARD_DIMM0_I2C_ADDR /* reading from DIMM0            */
 878         mov     r7, #SUPPORTED_CL_OFFSET     /* offset  18 */
 879         bl      _i2cRead
 880
 881         mov     PC, r13
 882
 883 /**************************/
 884 /* R8 - sdram configuration register.
 885  * Return value in flag if no-registered then Z-flag is set
 886  */
 887 _is_Registered:
 888         mov     r13, LR                 /* Save link register */
 889 #if defined(MV645xx)
 890         /* Get registered/non registered info from DIMM */
 891         tst     r8, #SDRAM_DTYPE_DDR2
 892         bne     regDdr2
 893
 894 regDdr1:
 895         mov     r4, #MV_BOARD_DIMM0_I2C_ADDR /* reading from DIMM0            */
 896         mov     r7, #SDRAM_MODULES_ATTR_OFFSET
 897         bl      _i2cRead                /* result in r7                       */
 898
 899         tst     r7, #0x2
 900         b       exit
 901 #endif
 902 regDdr2:
 903         mov     r4, #MV_BOARD_DIMM0_I2C_ADDR /* reading from DIMM0            */
 904         mov     r7, #DIMM_TYPE_INFO_OFFSET
 905         bl      _i2cRead                /* result in r7                       */
 906
 907         tst     r7, #0x11               /* DIMM type = regular RDIMM (0x01)   */
 908                                         /* or Mini-RDIMM (0x10)               */
 909 exit:
 910         mov     PC, r13
 911
 912
 913 /**************************/
 914 /* Return value in flag if no-Ecc then Z-flag is set */
 915 _is_Ecc:
 916         mov     r13, LR                 /* Save link register */
 917
 918         mov     r4, #MV_BOARD_DIMM0_I2C_ADDR /* reading from DIMM0            */
 919         mov     r7, #DIMM_CONFIG_TYPE
 920         bl      _i2cRead                /* result in r7                       */
 921
 922         tst     r7, #0x2               /* bit 1 -> Data ECC */
 923         mov     PC, r13
 924
 925 /**************************/
 926 /* Return value in flag if no second DIMM then Z-flag is set */
 927 _is_Second_Dimm_Exist:
 928         mov     r13, LR                 /* Save link register */
 929
 930         mov     r4, #MV_BOARD_DIMM1_I2C_ADDR /* reading from DIMM0            */
 931         mov     r7, #DIMM_TYPE_OFFSET
 932         bl      _i2cRead                /* result in r7                       */
 933
 934         tst     r7, #0x8               /* bit3 is '1' -> DDR 2 */
 935         mov     PC, r13
 936
 937 /*******************************************************************************
 938 * _mvDramIfGetDimmSizeFromSpd  - read bank 0 dram's size
 939 *
 940 * DESCRIPTION:
 941 *       The function will read the bank 0 dram size(SPD version 1.0 and above )
 942 *
 943 * INPUT:
 944 *       r6 - dram bank number.
 945 *
 946 * OUTPUT:
 947 *       none
 948 */
 949 _mvDramIfGetDimmSizeFromSpd:
 950
 951         mov     r13, LR                 /* Save link register */
 952
 953         /* Read SPD rank size from DIMM0 */
 954         mov     r4, #MV_BOARD_DIMM0_I2C_ADDR /* reading from DIMM0            */
 955
 956         cmp     r6, #0
 957         beq     1f
 958
 959         /* Read SPD rank size from DIMM1 */
 960         mov     r4, #MV_BOARD_DIMM1_I2C_ADDR /* reading from DIMM1            */
 961
 962 1:
 963         mov     r7, #RANK_SIZE_OFFSET   /* offset  31 */
 964         bl      _i2cRead
 965
 966 pass_read:
 967         ldr     r8, =(0x7 << SCSR_SIZE_OFFS)
 968         cmp     r7, #DRAM_RANK_DENSITY_128M
 969         beq     endDimmSize
 970
 971         ldr     r8, =(0xf << SCSR_SIZE_OFFS)
 972         cmp     r7, #DRAM_RANK_DENSITY_256M
 973         beq     endDimmSize
 974
 975         ldr     r8, =(0x1f << SCSR_SIZE_OFFS)
 976         cmp     r7, #DRAM_RANK_DENSITY_512M
 977         beq     endDimmSize
 978
 979         ldr     r8, =(0x3f << SCSR_SIZE_OFFS)
 980         cmp     r7, #DRAM_RANK_DENSITY_1G
 981         beq     endDimmSize
 982
 983         ldr     r8, =(0x7f  << SCSR_SIZE_OFFS)     /* DRAM_RANK_DENSITY_2G */
 984 endDimmSize:
 985         mov     PC, r13
 986 #endif