1 From e9898a39fce7db84ae56329d4f90da92af3bd584 Mon Sep 17 00:00:00 2001
2 From: P33M <P33M@github.com>
3 Date: Wed, 24 Sep 2014 11:57:51 +0100
4 Subject: [PATCH 091/114] dwc_otg: FIQ support on SMP. Set up FIQ stack and
5 handler on Core 0 only.
8 drivers/usb/host/dwc_otg/dwc_otg_hcd_linux.c | 96 ++++++++++++++--------------
9 1 file changed, 49 insertions(+), 47 deletions(-)
11 --- a/drivers/usb/host/dwc_otg/dwc_otg_hcd_linux.c
12 +++ b/drivers/usb/host/dwc_otg/dwc_otg_hcd_linux.c
13 @@ -397,7 +397,55 @@ static struct fiq_handler fh = {
17 +static void hcd_init_fiq(void *cookie)
19 + dwc_otg_device_t *otg_dev = cookie;
20 + dwc_otg_hcd_t *dwc_otg_hcd = otg_dev->hcd;
21 + struct pt_regs regs;
23 + if (claim_fiq(&fh)) {
24 + DWC_ERROR("Can't claim FIQ");
27 + DWC_WARN("FIQ at 0x%08x", (fiq_fsm_enable ? (int)&dwc_otg_fiq_fsm : (int)&dwc_otg_fiq_nop));
28 + DWC_WARN("FIQ ASM at 0x%08x length %d", (int)&_dwc_otg_fiq_stub, (int)(&_dwc_otg_fiq_stub_end - &_dwc_otg_fiq_stub));
29 + set_fiq_handler((void *) &_dwc_otg_fiq_stub, &_dwc_otg_fiq_stub_end - &_dwc_otg_fiq_stub);
30 + memset(®s,0,sizeof(regs));
32 + regs.ARM_r8 = (long) dwc_otg_hcd->fiq_state;
33 + if (fiq_fsm_enable) {
34 + regs.ARM_r9 = dwc_otg_hcd->core_if->core_params->host_channels;
35 + //regs.ARM_r10 = dwc_otg_hcd->dma;
36 + regs.ARM_fp = (long) dwc_otg_fiq_fsm;
38 + regs.ARM_fp = (long) dwc_otg_fiq_nop;
41 + regs.ARM_sp = (long) dwc_otg_hcd->fiq_stack + (sizeof(struct fiq_stack) - 4);
43 +// __show_regs(®s);
44 + set_fiq_regs(®s);
46 + //Set the mphi periph to the required registers
47 + dwc_otg_hcd->fiq_state->mphi_regs.base = otg_dev->os_dep.mphi_base;
48 + dwc_otg_hcd->fiq_state->mphi_regs.ctrl = otg_dev->os_dep.mphi_base + 0x4c;
49 + dwc_otg_hcd->fiq_state->mphi_regs.outdda = otg_dev->os_dep.mphi_base + 0x28;
50 + dwc_otg_hcd->fiq_state->mphi_regs.outddb = otg_dev->os_dep.mphi_base + 0x2c;
51 + dwc_otg_hcd->fiq_state->mphi_regs.intstat = otg_dev->os_dep.mphi_base + 0x50;
52 + dwc_otg_hcd->fiq_state->dwc_regs_base = otg_dev->os_dep.base;
53 + DWC_WARN("MPHI regs_base at 0x%08x", (int)dwc_otg_hcd->fiq_state->mphi_regs.base);
54 + //Enable mphi peripheral
55 + writel((1<<31),dwc_otg_hcd->fiq_state->mphi_regs.ctrl);
57 + if (readl(dwc_otg_hcd->fiq_state->mphi_regs.ctrl) & 0x80000000)
58 + DWC_WARN("MPHI periph has been enabled");
60 + DWC_WARN("MPHI periph has NOT been enabled");
62 + // Enable FIQ interrupt from USB peripheral
63 + enable_fiq(INTERRUPT_VC_USB);
68 * Initializes the HCD. This function allocates memory for and initializes the
69 @@ -412,7 +460,6 @@ int hcd_init(dwc_bus_dev_t *_dev)
70 dwc_otg_device_t *otg_dev = DWC_OTG_BUSDRVDATA(_dev);
73 - struct pt_regs regs;
75 DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD INIT otg_dev=%p\n", otg_dev);
77 @@ -464,52 +511,7 @@ int hcd_init(dwc_bus_dev_t *_dev)
82 - if (claim_fiq(&fh)) {
83 - DWC_ERROR("Can't claim FIQ");
87 - DWC_WARN("FIQ at 0x%08x", (fiq_fsm_enable ? (int)&dwc_otg_fiq_fsm : (int)&dwc_otg_fiq_nop));
88 - DWC_WARN("FIQ ASM at 0x%08x length %d", (int)&_dwc_otg_fiq_stub, (int)(&_dwc_otg_fiq_stub_end - &_dwc_otg_fiq_stub));
90 - set_fiq_handler((void *) &_dwc_otg_fiq_stub, &_dwc_otg_fiq_stub_end - &_dwc_otg_fiq_stub);
91 - memset(®s,0,sizeof(regs));
93 - regs.ARM_r8 = (long) dwc_otg_hcd->fiq_state;
94 - if (fiq_fsm_enable) {
95 - regs.ARM_r9 = dwc_otg_hcd->core_if->core_params->host_channels;
96 - //regs.ARM_r10 = dwc_otg_hcd->dma;
97 - regs.ARM_fp = (long) dwc_otg_fiq_fsm;
99 - regs.ARM_fp = (long) dwc_otg_fiq_nop;
102 - regs.ARM_sp = (long) dwc_otg_hcd->fiq_stack + (sizeof(struct fiq_stack) - 4);
104 -// __show_regs(®s);
105 - set_fiq_regs(®s);
107 - //Set the mphi periph to the required registers
108 - dwc_otg_hcd->fiq_state->mphi_regs.base = otg_dev->os_dep.mphi_base;
109 - dwc_otg_hcd->fiq_state->mphi_regs.ctrl = otg_dev->os_dep.mphi_base + 0x4c;
110 - dwc_otg_hcd->fiq_state->mphi_regs.outdda = otg_dev->os_dep.mphi_base + 0x28;
111 - dwc_otg_hcd->fiq_state->mphi_regs.outddb = otg_dev->os_dep.mphi_base + 0x2c;
112 - dwc_otg_hcd->fiq_state->mphi_regs.intstat = otg_dev->os_dep.mphi_base + 0x50;
113 - dwc_otg_hcd->fiq_state->dwc_regs_base = otg_dev->os_dep.base;
114 - DWC_WARN("MPHI regs_base at 0x%08x", (int)dwc_otg_hcd->fiq_state->mphi_regs.base);
115 - //Enable mphi peripheral
116 - writel((1<<31),dwc_otg_hcd->fiq_state->mphi_regs.ctrl);
118 - if (readl(dwc_otg_hcd->fiq_state->mphi_regs.ctrl) & 0x80000000)
119 - DWC_WARN("MPHI periph has been enabled");
121 - DWC_WARN("MPHI periph has NOT been enabled");
123 - // Enable FIQ interrupt from USB peripheral
124 - enable_fiq(INTERRUPT_VC_USB);
125 - local_fiq_enable();
127 + smp_call_function_single(0, hcd_init_fiq, otg_dev, 1);
130 otg_dev->hcd->otg_dev = otg_dev;