target/linux/brcm2708/patches-3.18/0090-bcm2709-Simplify-and-strip-down-IRQ-handler.patch

   1 From 1ef33cbb3347c38f563de1c7df7d103f8b7d23ca Mon Sep 17 00:00:00 2001
   2 From: popcornmix <popcornmix@gmail.com>
   3 Date: Fri, 20 Jun 2014 17:19:27 +0100
   4 Subject: [PATCH 090/114] bcm2709: Simplify and strip down IRQ handler
   5
   6 ---
   7  arch/arm/include/asm/entry-macro-multi.S         |   2 +
   8  arch/arm/mach-bcm2709/include/mach/entry-macro.S | 169 +++++++++++------------
   9  2 files changed, 85 insertions(+), 86 deletions(-)
  10
  11 diff --git a/arch/arm/include/asm/entry-macro-multi.S b/arch/arm/include/asm/entry-macro-multi.S
  12 index 469a2b3..9c0a7eb 100644
  13 --- a/arch/arm/include/asm/entry-macro-multi.S
  14 +++ b/arch/arm/include/asm/entry-macro-multi.S
  15 @@ -1,5 +1,6 @@
  16  #include <asm/assembler.h>
  17
  18 +#ifndef CONFIG_ARCH_BCM2709
  19  /*
  20   * Interrupt handling.  Preserves r7, r8, r9
  21   */
  22 @@ -28,6 +29,7 @@
  23  #endif
  24  9997:
  25         .endm
  26 +#endif
  27
  28         .macro  arch_irq_handler, symbol_name
  29         .align  5
  30 diff --git a/arch/arm/mach-bcm2709/include/mach/entry-macro.S b/arch/arm/mach-bcm2709/include/mach/entry-macro.S
  31 index d08591b..101d9f1 100644
  32 --- a/arch/arm/mach-bcm2709/include/mach/entry-macro.S
  33 +++ b/arch/arm/mach-bcm2709/include/mach/entry-macro.S
  34 @@ -22,102 +22,99 @@
  35  #include <mach/hardware.h>
  36  #include <mach/irqs.h>
  37
  38 -               .macro  disable_fiq
  39 -               .endm
  40 +       .macro  arch_ret_to_user, tmp1, tmp2
  41 +       .endm
  42
  43 -               .macro  get_irqnr_preamble, base, tmp
  44 -               ldr     \base, =IO_ADDRESS(ARMCTRL_IC_BASE)
  45 -               .endm
  46 +       .macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
  47
  48 -               .macro  arch_ret_to_user, tmp1, tmp2
  49 -               .endm
  50 +       /* get core number */
  51 +       mrc     p15, 0, \base, c0, c0, 5
  52 +       ubfx    \base, \base, #0, #2
  53
  54 -               .macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
  55 -               /* get core number */
  56 -               mrc     p15, 0, \tmp, c0, c0, 5
  57 -               ubfx    \tmp, \tmp, #0, #2
  58 +       /* get core's local interrupt controller */
  59 +       ldr     \irqstat, = __io_address(ARM_LOCAL_IRQ_PENDING0)        @ local interrupt source
  60 +       add     \irqstat, \irqstat, \base, lsl #2
  61 +       ldr     \tmp, [\irqstat]
  62
  63 -               /* get core's local interrupt controller */
  64 -               ldr     \irqstat, = __io_address(ARM_LOCAL_IRQ_PENDING0)        @ local interrupt source
  65 -               add     \irqstat, \irqstat, \tmp, lsl #2
  66 -               ldr     \tmp, [\irqstat]
  67 -               /* ignore gpu interrupt */
  68 -               bic     \tmp, #0x100
  69 -               /* ignore mailbox interrupts */
  70 -               bics    \tmp, #0xf0
  71 -               beq     1005f
  72 +       /* test for mailbox0 (IPI) interrupt */
  73 +       tst     \tmp, #0x10
  74 +       beq     1030f
  75
  76 -               @ For non-zero x, LSB(x) = 31 - CLZ(x^(x-1))
  77 -               @ N.B. CLZ is an ARM5 instruction.
  78 -               mov     \irqnr, #(ARM_IRQ_LOCAL_BASE + 31)
  79 -               sub     \irqstat, \tmp, #1
  80 -               eor     \irqstat, \irqstat, \tmp
  81 -               clz     \tmp, \irqstat
  82 -               sub     \irqnr, \tmp
  83 -               b       1020f
  84 -1005:
  85 -               /* get core number */
  86 -               mrc     p15, 0, \tmp, c0, c0, 5
  87 -               ubfx    \tmp, \tmp, #0, #2
  88 +       /* get core's mailbox interrupt control */
  89 +       ldr     \irqstat, = __io_address(ARM_LOCAL_MAILBOX0_CLR0)       @ mbox_clr
  90 +       add     \irqstat, \irqstat, \base, lsl #4
  91 +       ldr     \tmp, [\irqstat]
  92 +       clz     \tmp, \tmp
  93 +       rsb     \irqnr, \tmp, #31
  94 +       mov     \tmp, #1
  95 +       lsl     \tmp, \irqnr
  96 +       str     \tmp, [\irqstat]  @ clear interrupt source
  97 +       dsb
  98 +       mov     r1, sp
  99 +       adr     lr, BSYM(1b)
 100 +       b       do_IPI
 101
 102 -                cmp    \tmp, #1
 103 -               beq     1020f
 104 -                cmp    \tmp, #2
 105 -               beq     1020f
 106 -                cmp    \tmp, #3
 107 -               beq     1020f
 108 +1030:
 109 +       /* check gpu interrupt */
 110 +       tst     \tmp, #0x100
 111 +       beq     1040f
 112
 113 -               /* get masked status */
 114 -               ldr     \irqstat, [\base, #(ARM_IRQ_PEND0 - ARMCTRL_IC_BASE)]
 115 -               mov     \irqnr, #(ARM_IRQ0_BASE + 31)
 116 -               and     \tmp, \irqstat, #0x300           @ save bits 8 and 9
 117 -               /* clear bits 8 and 9, and test */
 118 -               bics    \irqstat, \irqstat, #0x300
 119 -               bne     1010f
 120 +       ldr     \base, =IO_ADDRESS(ARMCTRL_IC_BASE)
 121 +       /* get masked status */
 122 +       ldr     \irqstat, [\base, #(ARM_IRQ_PEND0 - ARMCTRL_IC_BASE)]
 123 +       mov     \irqnr, #(ARM_IRQ0_BASE + 31)
 124 +       and     \tmp, \irqstat, #0x300           @ save bits 8 and 9
 125 +       /* clear bits 8 and 9, and test */
 126 +       bics    \irqstat, \irqstat, #0x300
 127 +       bne     1010f
 128
 129 -               tst     \tmp, #0x100
 130 -               ldrne   \irqstat, [\base, #(ARM_IRQ_PEND1 - ARMCTRL_IC_BASE)]
 131 -               movne \irqnr, #(ARM_IRQ1_BASE + 31)
 132 -               @ Mask out the interrupts also present in PEND0 - see SW-5809
 133 -               bicne \irqstat, #((1<<7) | (1<<9) | (1<<10))
 134 -               bicne \irqstat, #((1<<18) | (1<<19))
 135 -               bne     1010f
 136 -
 137 -               tst     \tmp, #0x200
 138 -               ldrne \irqstat, [\base, #(ARM_IRQ_PEND2 - ARMCTRL_IC_BASE)]
 139 -               movne \irqnr, #(ARM_IRQ2_BASE + 31)
 140 -               @ Mask out the interrupts also present in PEND0 - see SW-5809
 141 -               bicne \irqstat, #((1<<21) | (1<<22) | (1<<23) | (1<<24) | (1<<25))
 142 -               bicne \irqstat, #((1<<30))
 143 -               beq 1020f
 144 +       tst     \tmp, #0x100
 145 +       ldrne   \irqstat, [\base, #(ARM_IRQ_PEND1 - ARMCTRL_IC_BASE)]
 146 +       movne   \irqnr, #(ARM_IRQ1_BASE + 31)
 147 +       @ Mask out the interrupts also present in PEND0 - see SW-5809
 148 +       bicne   \irqstat, #((1<<7) | (1<<9) | (1<<10))
 149 +       bicne   \irqstat, #((1<<18) | (1<<19))
 150 +       bne     1010f
 151
 152 +       tst     \tmp, #0x200
 153 +       ldrne   \irqstat, [\base, #(ARM_IRQ_PEND2 - ARMCTRL_IC_BASE)]
 154 +       movne   \irqnr, #(ARM_IRQ2_BASE + 31)
 155 +       @ Mask out the interrupts also present in PEND0 - see SW-5809
 156 +       bicne   \irqstat, #((1<<21) | (1<<22) | (1<<23) | (1<<24) | (1<<25))
 157 +       bicne   \irqstat, #((1<<30))
 158 +       beq     1020f
 159  1010:
 160 -               @ For non-zero x, LSB(x) = 31 - CLZ(x^(x-1))
 161 -               @ N.B. CLZ is an ARM5 instruction.
 162 -               sub     \tmp, \irqstat, #1
 163 -               eor     \irqstat, \irqstat, \tmp
 164 -               clz     \tmp, \irqstat
 165 -               sub     \irqnr, \tmp
 166 +       @ For non-zero x, LSB(x) = 31 - CLZ(x^(x-1))
 167 +       sub     \tmp, \irqstat, #1
 168 +       eor     \irqstat, \irqstat, \tmp
 169 +       clz     \tmp, \irqstat
 170 +       sub     \irqnr, \tmp
 171 +       b       1050f
 172 +1040:
 173 +       cmp     \tmp, #0
 174 +       beq     1020f
 175
 176 -1020:  @ EQ will be set if no irqs pending
 177 +       /* handle local (e.g. timer) interrupts */
 178 +       @ For non-zero x, LSB(x) = 31 - CLZ(x^(x-1))
 179 +       mov     \irqnr, #(ARM_IRQ_LOCAL_BASE + 31)
 180 +       sub     \irqstat, \tmp, #1
 181 +       eor     \irqstat, \irqstat, \tmp
 182 +       clz     \tmp, \irqstat
 183 +       sub     \irqnr, \tmp
 184 +1050:
 185 +       mov     r1, sp
 186 +       @
 187 +       @ routine called with r0 = irq number, r1 = struct pt_regs *
 188 +       @
 189 +       adr     lr, BSYM(1b)
 190 +       b       asm_do_IRQ
 191
 192 -               .endm
 193 +1020:  @ EQ will be set if no irqs pending
 194 +       .endm
 195
 196 -               .macro  test_for_ipi, irqnr, irqstat, base, tmp
 197 -               /* get core number */
 198 -               mrc     p15, 0, \tmp, c0, c0, 5
 199 -               ubfx    \tmp, \tmp, #0, #2
 200 -               /* get core's mailbox interrupt control */
 201 -               ldr     \irqstat, = __io_address(ARM_LOCAL_MAILBOX0_CLR0)       @ mbox_clr
 202 -               add     \irqstat, \irqstat, \tmp, lsl #4
 203 -               ldr     \tmp, [\irqstat]
 204 -               cmp     \tmp, #0
 205 -               beq     1030f
 206 -               clz     \tmp, \tmp
 207 -               rsb     \irqnr, \tmp, #31
 208 -               mov     \tmp, #1
 209 -               lsl     \tmp, \irqnr
 210 -               str     \tmp, [\irqstat]  @ clear interrupt source
 211 -               dsb
 212 -1030:  @ EQ will be set if no irqs pending
 213 -               .endm
 214 +/*
 215 + * Interrupt handling.  Preserves r7, r8, r9
 216 + */
 217 +       .macro  arch_irq_handler_default
 218 +1:     get_irqnr_and_base r0, r2, r6, lr
 219 +       .endm
 220 --
 221 1.8.3.2
 222