target/linux/brcm2708/patches-3.18/0029-dmaengine-Add-support-for-BCM2708.patch

   1 From ce3d899b0ed284a6e901fb6f4a459fdcf003cadb Mon Sep 17 00:00:00 2001
   2 From: Florian Meier <florian.meier@koalo.de>
   3 Date: Fri, 22 Nov 2013 14:22:53 +0100
   4 Subject: [PATCH 029/114] dmaengine: Add support for BCM2708
   5
   6 Add support for DMA controller of BCM2708 as used in the Raspberry Pi.
   7 Currently it only supports cyclic DMA.
   8
   9 Signed-off-by: Florian Meier <florian.meier@koalo.de>
  10
  11 dmaengine: expand functionality by supporting scatter/gather transfers sdhci-bcm2708 and dma.c: fix for LITE channels
  12
  13 DMA: fix cyclic LITE length overflow bug
  14 ---
  15  arch/arm/mach-bcm2708/dma.c              |    2 +
  16  arch/arm/mach-bcm2708/include/mach/dma.h |    6 +-
  17  drivers/dma/Kconfig                      |    6 +
  18  drivers/dma/Makefile                     |    1 +
  19  drivers/dma/bcm2708-dmaengine.c          | 1052 ++++++++++++++++++++++++++++++
  20  5 files changed, 1066 insertions(+), 1 deletion(-)
  21  create mode 100644 drivers/dma/bcm2708-dmaengine.c
  22
  23 --- a/arch/arm/mach-bcm2708/dma.c
  24 +++ b/arch/arm/mach-bcm2708/dma.c
  25 @@ -156,6 +156,8 @@ static void vc_dmaman_init(struct vc_dma
  26         dmaman->chan_available = chans_available;
  27         dmaman->has_feature[BCM_DMA_FEATURE_FAST_ORD] = 0x0c;  /* chans 2 & 3 */
  28         dmaman->has_feature[BCM_DMA_FEATURE_BULK_ORD] = 0x01;  /* chan 0 */
  29 +       dmaman->has_feature[BCM_DMA_FEATURE_NORMAL_ORD] = 0xfe;  /* chans 1 to 7 */
  30 +       dmaman->has_feature[BCM_DMA_FEATURE_LITE_ORD] = 0x7f00;  /* chans 8 to 14 */
  31  }
  32
  33  static int vc_dmaman_chan_alloc(struct vc_dmaman *dmaman,
  34 --- a/arch/arm/mach-bcm2708/include/mach/dma.h
  35 +++ b/arch/arm/mach-bcm2708/include/mach/dma.h
  36 @@ -77,9 +77,13 @@ extern int /*rc*/ bcm_dma_abort(void __i
  37     those with higher priority smaller ordinal numbers */
  38  #define BCM_DMA_FEATURE_FAST_ORD 0
  39  #define BCM_DMA_FEATURE_BULK_ORD 1
  40 +#define BCM_DMA_FEATURE_NORMAL_ORD 2
  41 +#define BCM_DMA_FEATURE_LITE_ORD 3
  42  #define BCM_DMA_FEATURE_FAST    (1<<BCM_DMA_FEATURE_FAST_ORD)
  43  #define BCM_DMA_FEATURE_BULK    (1<<BCM_DMA_FEATURE_BULK_ORD)
  44 -#define BCM_DMA_FEATURE_COUNT   2
  45 +#define BCM_DMA_FEATURE_NORMAL  (1<<BCM_DMA_FEATURE_NORMAL_ORD)
  46 +#define BCM_DMA_FEATURE_LITE    (1<<BCM_DMA_FEATURE_LITE_ORD)
  47 +#define BCM_DMA_FEATURE_COUNT   4
  48
  49  /* return channel no or -ve error */
  50  extern int bcm_dma_chan_alloc(unsigned preferred_feature_set,
  51 --- a/drivers/dma/Kconfig
  52 +++ b/drivers/dma/Kconfig
  53 @@ -330,6 +330,12 @@ config DMA_BCM2835
  54         select DMA_ENGINE
  55         select DMA_VIRTUAL_CHANNELS
  56
  57 +config DMA_BCM2708
  58 +       tristate "BCM2708 DMA engine support"
  59 +       depends on MACH_BCM2708
  60 +       select DMA_ENGINE
  61 +       select DMA_VIRTUAL_CHANNELS
  62 +
  63  config TI_CPPI41
  64         tristate "AM33xx CPPI41 DMA support"
  65         depends on ARCH_OMAP
  66 --- a/drivers/dma/Makefile
  67 +++ b/drivers/dma/Makefile
  68 @@ -38,6 +38,7 @@ obj-$(CONFIG_DMA_SA11X0) += sa11x0-dma.o
  69  obj-$(CONFIG_MMP_TDMA) += mmp_tdma.o
  70  obj-$(CONFIG_DMA_OMAP) += omap-dma.o
  71  obj-$(CONFIG_DMA_BCM2835) += bcm2835-dma.o
  72 +obj-$(CONFIG_DMA_BCM2708) += bcm2708-dmaengine.o
  73  obj-$(CONFIG_MMP_PDMA) += mmp_pdma.o
  74  obj-$(CONFIG_DMA_JZ4740) += dma-jz4740.o
  75  obj-$(CONFIG_TI_CPPI41) += cppi41.o
  76 --- /dev/null
  77 +++ b/drivers/dma/bcm2708-dmaengine.c
  78 @@ -0,0 +1,1052 @@
  79 +/*
  80 + * BCM2835 DMA engine support
  81 + *
  82 + * This driver supports cyclic and scatter/gather DMA transfers.
  83 + *
  84 + * Author:      Florian Meier <florian.meier@koalo.de>
  85 + *              Gellert Weisz <gellert@raspberrypi.org>
  86 + *              Copyright 2013-2014
  87 + *
  88 + * Based on
  89 + *     OMAP DMAengine support by Russell King
  90 + *
  91 + *     BCM2708 DMA Driver
  92 + *     Copyright (C) 2010 Broadcom
  93 + *
  94 + *     Raspberry Pi PCM I2S ALSA Driver
  95 + *     Copyright (c) by Phil Poole 2013
  96 + *
  97 + *     MARVELL MMP Peripheral DMA Driver
  98 + *     Copyright 2012 Marvell International Ltd.
  99 + *
 100 + * This program is free software; you can redistribute it and/or modify
 101 + * it under the terms of the GNU General Public License as published by
 102 + * the Free Software Foundation; either version 2 of the License, or
 103 + * (at your option) any later version.
 104 + *
 105 + * This program is distributed in the hope that it will be useful,
 106 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
 107 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 108 + * GNU General Public License for more details.
 109 + */
 110 +
 111 +#include <linux/dmaengine.h>
 112 +#include <linux/dma-mapping.h>
 113 +#include <linux/err.h>
 114 +#include <linux/init.h>
 115 +#include <linux/interrupt.h>
 116 +#include <linux/list.h>
 117 +#include <linux/module.h>
 118 +#include <linux/platform_device.h>
 119 +#include <linux/slab.h>
 120 +#include <linux/io.h>
 121 +#include <linux/spinlock.h>
 122 +
 123 +#ifndef CONFIG_OF
 124 +
 125 +/* dma manager */
 126 +#include <mach/dma.h>
 127 +
 128 +//#define DMA_COMPLETE DMA_SUCCESS
 129 +
 130 +#endif
 131 +
 132 +#include <linux/of.h>
 133 +#include <linux/of_dma.h>
 134 +
 135 +#include "virt-dma.h"
 136 +
 137 +
 138 +struct bcm2835_dmadev {
 139 +       struct dma_device ddev;
 140 +       spinlock_t lock;
 141 +       void __iomem *base;
 142 +       struct device_dma_parameters dma_parms;
 143 +};
 144 +
 145 +struct bcm2835_dma_cb {
 146 +       uint32_t info;
 147 +       uint32_t src;
 148 +       uint32_t dst;
 149 +       uint32_t length;
 150 +       uint32_t stride;
 151 +       uint32_t next;
 152 +       uint32_t pad[2];
 153 +};
 154 +
 155 +struct bcm2835_chan {
 156 +       struct virt_dma_chan vc;
 157 +       struct list_head node;
 158 +
 159 +       struct dma_slave_config cfg;
 160 +       bool cyclic;
 161 +
 162 +       int ch;
 163 +       struct bcm2835_desc *desc;
 164 +
 165 +       void __iomem *chan_base;
 166 +       int irq_number;
 167 +
 168 +       unsigned int dreq;
 169 +};
 170 +
 171 +struct bcm2835_desc {
 172 +       struct virt_dma_desc vd;
 173 +       enum dma_transfer_direction dir;
 174 +
 175 +       unsigned int control_block_size;
 176 +       struct bcm2835_dma_cb *control_block_base;
 177 +       dma_addr_t control_block_base_phys;
 178 +
 179 +       unsigned int frames;
 180 +       size_t size;
 181 +};
 182 +
 183 +#define BCM2835_DMA_CS         0x00
 184 +#define BCM2835_DMA_ADDR       0x04
 185 +#define BCM2835_DMA_SOURCE_AD  0x0c
 186 +#define BCM2835_DMA_DEST_AD    0x10
 187 +#define BCM2835_DMA_NEXTCB     0x1C
 188 +
 189 +/* DMA CS Control and Status bits */
 190 +#define BCM2835_DMA_ACTIVE     BIT(0)
 191 +#define BCM2835_DMA_INT        BIT(2)
 192 +#define BCM2835_DMA_ISPAUSED   BIT(4)  /* Pause requested or not active */
 193 +#define BCM2835_DMA_ISHELD     BIT(5)  /* Is held by DREQ flow control */
 194 +#define BCM2835_DMA_ERR        BIT(8)
 195 +#define BCM2835_DMA_ABORT      BIT(30) /* Stop current CB, go to next, WO */
 196 +#define BCM2835_DMA_RESET      BIT(31) /* WO, self clearing */
 197 +
 198 +#define BCM2835_DMA_INT_EN     BIT(0)
 199 +#define BCM2835_DMA_WAIT_RESP  BIT(3)
 200 +#define BCM2835_DMA_D_INC      BIT(4)
 201 +#define BCM2835_DMA_D_WIDTH    BIT(5)
 202 +#define BCM2835_DMA_D_DREQ     BIT(6)
 203 +#define BCM2835_DMA_S_INC      BIT(8)
 204 +#define BCM2835_DMA_S_WIDTH    BIT(9)
 205 +#define BCM2835_DMA_S_DREQ     BIT(10)
 206 +
 207 +#define BCM2835_DMA_PER_MAP(x) ((x) << 16)
 208 +#define        BCM2835_DMA_WAITS(x)    (((x)&0x1f) << 21)
 209 +
 210 +#define SDHCI_BCM_DMA_WAITS 0  /* delays slowing DMA transfers: 0-31 */
 211 +
 212 +#define BCM2835_DMA_DATA_TYPE_S8       1
 213 +#define BCM2835_DMA_DATA_TYPE_S16      2
 214 +#define BCM2835_DMA_DATA_TYPE_S32      4
 215 +#define BCM2835_DMA_DATA_TYPE_S128     16
 216 +
 217 +#define BCM2835_DMA_BULK_MASK  BIT(0)
 218 +#define BCM2835_DMA_FIQ_MASK   (BIT(2) | BIT(3))
 219 +
 220 +
 221 +/* Valid only for channels 0 - 14, 15 has its own base address */
 222 +#define BCM2835_DMA_CHAN(n)    ((n) << 8) /* Base address */
 223 +#define BCM2835_DMA_CHANIO(base, n) ((base) + BCM2835_DMA_CHAN(n))
 224 +
 225 +#define MAX_LITE_TRANSFER 32768
 226 +#define MAX_NORMAL_TRANSFER 1073741824
 227 +
 228 +static inline struct bcm2835_dmadev *to_bcm2835_dma_dev(struct dma_device *d)
 229 +{
 230 +       return container_of(d, struct bcm2835_dmadev, ddev);
 231 +}
 232 +
 233 +static inline struct bcm2835_chan *to_bcm2835_dma_chan(struct dma_chan *c)
 234 +{
 235 +       return container_of(c, struct bcm2835_chan, vc.chan);
 236 +}
 237 +
 238 +static inline struct bcm2835_desc *to_bcm2835_dma_desc(
 239 +               struct dma_async_tx_descriptor *t)
 240 +{
 241 +       return container_of(t, struct bcm2835_desc, vd.tx);
 242 +}
 243 +
 244 +static void dma_dumpregs(struct bcm2835_chan *c)
 245 +{
 246 +       pr_debug("-------------DMA DUMPREGS-------------\n");
 247 +       pr_debug("CS=                   %u\n",
 248 +               readl(c->chan_base + BCM2835_DMA_CS));
 249 +       pr_debug("ADDR=                 %u\n",
 250 +               readl(c->chan_base + BCM2835_DMA_ADDR));
 251 +       pr_debug("SOURCE_ADDR=  %u\n",
 252 +               readl(c->chan_base + BCM2835_DMA_SOURCE_AD));
 253 +       pr_debug("DEST_AD=              %u\n",
 254 +               readl(c->chan_base + BCM2835_DMA_DEST_AD));
 255 +       pr_debug("NEXTCB=                       %u\n",
 256 +               readl(c->chan_base + BCM2835_DMA_NEXTCB));
 257 +       pr_debug("--------------------------------------\n");
 258 +}
 259 +
 260 +static void bcm2835_dma_desc_free(struct virt_dma_desc *vd)
 261 +{
 262 +       struct bcm2835_desc *desc = container_of(vd, struct bcm2835_desc, vd);
 263 +       dma_free_coherent(desc->vd.tx.chan->device->dev,
 264 +                       desc->control_block_size,
 265 +                       desc->control_block_base,
 266 +                       desc->control_block_base_phys);
 267 +       kfree(desc);
 268 +}
 269 +
 270 +static int bcm2835_dma_abort(void __iomem *chan_base)
 271 +{
 272 +       unsigned long cs;
 273 +       long int timeout = 10000;
 274 +
 275 +       cs = readl(chan_base + BCM2835_DMA_CS);
 276 +       if (!(cs & BCM2835_DMA_ACTIVE))
 277 +               return 0;
 278 +
 279 +       /* Write 0 to the active bit - Pause the DMA */
 280 +       writel(0, chan_base + BCM2835_DMA_CS);
 281 +
 282 +       /* Wait for any current AXI transfer to complete */
 283 +       while ((cs & BCM2835_DMA_ISPAUSED) && --timeout) {
 284 +               cpu_relax();
 285 +               cs = readl(chan_base + BCM2835_DMA_CS);
 286 +       }
 287 +
 288 +       /* We'll un-pause when we set of our next DMA */
 289 +       if (!timeout)
 290 +               return -ETIMEDOUT;
 291 +
 292 +       if (!(cs & BCM2835_DMA_ACTIVE))
 293 +               return 0;
 294 +
 295 +       /* Terminate the control block chain */
 296 +       writel(0, chan_base + BCM2835_DMA_NEXTCB);
 297 +
 298 +       /* Abort the whole DMA */
 299 +       writel(BCM2835_DMA_ABORT | BCM2835_DMA_ACTIVE,
 300 +              chan_base + BCM2835_DMA_CS);
 301 +
 302 +       return 0;
 303 +}
 304 +
 305 +
 306 +static void bcm2835_dma_start_desc(struct bcm2835_chan *c)
 307 +{
 308 +       struct virt_dma_desc *vd = vchan_next_desc(&c->vc);
 309 +       struct bcm2835_desc *d;
 310 +
 311 +       if (!vd) {
 312 +               c->desc = NULL;
 313 +               return;
 314 +       }
 315 +
 316 +       list_del(&vd->node);
 317 +
 318 +       c->desc = d = to_bcm2835_dma_desc(&vd->tx);
 319 +
 320 +       writel(d->control_block_base_phys, c->chan_base + BCM2835_DMA_ADDR);
 321 +       writel(BCM2835_DMA_ACTIVE, c->chan_base + BCM2835_DMA_CS);
 322 +
 323 +}
 324 +
 325 +static irqreturn_t bcm2835_dma_callback(int irq, void *data)
 326 +{
 327 +       struct bcm2835_chan *c = data;
 328 +       struct bcm2835_desc *d;
 329 +       unsigned long flags;
 330 +
 331 +       spin_lock_irqsave(&c->vc.lock, flags);
 332 +
 333 +       /* Acknowledge interrupt */
 334 +       writel(BCM2835_DMA_INT, c->chan_base + BCM2835_DMA_CS);
 335 +
 336 +       d = c->desc;
 337 +
 338 +       if (d) {
 339 +               if (c->cyclic) {
 340 +                       vchan_cyclic_callback(&d->vd);
 341 +
 342 +                       /* Keep the DMA engine running */
 343 +                       writel(BCM2835_DMA_ACTIVE,
 344 +                               c->chan_base + BCM2835_DMA_CS);
 345 +
 346 +               } else {
 347 +                       vchan_cookie_complete(&c->desc->vd);
 348 +                       bcm2835_dma_start_desc(c);
 349 +               }
 350 +       }
 351 +
 352 +       spin_unlock_irqrestore(&c->vc.lock, flags);
 353 +
 354 +       return IRQ_HANDLED;
 355 +}
 356 +
 357 +static int bcm2835_dma_alloc_chan_resources(struct dma_chan *chan)
 358 +{
 359 +       struct bcm2835_chan *c = to_bcm2835_dma_chan(chan);
 360 +       int ret;
 361 +
 362 +       dev_dbg(c->vc.chan.device->dev,
 363 +                       "Allocating DMA channel %d\n", c->ch);
 364 +
 365 +       ret = request_irq(c->irq_number,
 366 +                       bcm2835_dma_callback, 0, "DMA IRQ", c);
 367 +
 368 +       return ret;
 369 +}
 370 +
 371 +static void bcm2835_dma_free_chan_resources(struct dma_chan *chan)
 372 +{
 373 +       struct bcm2835_chan *c = to_bcm2835_dma_chan(chan);
 374 +
 375 +       vchan_free_chan_resources(&c->vc);
 376 +       free_irq(c->irq_number, c);
 377 +
 378 +       dev_dbg(c->vc.chan.device->dev, "Freeing DMA channel %u\n", c->ch);
 379 +}
 380 +
 381 +static size_t bcm2835_dma_desc_size(struct bcm2835_desc *d)
 382 +{
 383 +       return d->size;
 384 +}
 385 +
 386 +static size_t bcm2835_dma_desc_size_pos(struct bcm2835_desc *d, dma_addr_t addr)
 387 +{
 388 +       unsigned int i;
 389 +       size_t size;
 390 +
 391 +       for (size = i = 0; i < d->frames; i++) {
 392 +               struct bcm2835_dma_cb *control_block =
 393 +                       &d->control_block_base[i];
 394 +               size_t this_size = control_block->length;
 395 +               dma_addr_t dma;
 396 +
 397 +               if (d->dir == DMA_DEV_TO_MEM)
 398 +                       dma = control_block->dst;
 399 +               else
 400 +                       dma = control_block->src;
 401 +
 402 +               if (size)
 403 +                       size += this_size;
 404 +               else if (addr >= dma && addr < dma + this_size)
 405 +                       size += dma + this_size - addr;
 406 +       }
 407 +
 408 +       return size;
 409 +}
 410 +
 411 +static enum dma_status bcm2835_dma_tx_status(struct dma_chan *chan,
 412 +       dma_cookie_t cookie, struct dma_tx_state *txstate)
 413 +{
 414 +       struct bcm2835_chan *c = to_bcm2835_dma_chan(chan);
 415 +       struct bcm2835_desc *d;
 416 +       struct virt_dma_desc *vd;
 417 +       enum dma_status ret;
 418 +       unsigned long flags;
 419 +       dma_addr_t pos;
 420 +
 421 +       ret = dma_cookie_status(chan, cookie, txstate);
 422 +       if (ret == DMA_COMPLETE || !txstate)
 423 +               return ret;
 424 +
 425 +       spin_lock_irqsave(&c->vc.lock, flags);
 426 +       vd = vchan_find_desc(&c->vc, cookie);
 427 +       if (vd) {
 428 +               txstate->residue =
 429 +                       bcm2835_dma_desc_size(to_bcm2835_dma_desc(&vd->tx));
 430 +       } else if (c->desc && c->desc->vd.tx.cookie == cookie) {
 431 +               d = c->desc;
 432 +
 433 +               if (d->dir == DMA_MEM_TO_DEV)
 434 +                       pos = readl(c->chan_base + BCM2835_DMA_SOURCE_AD);
 435 +               else if (d->dir == DMA_DEV_TO_MEM)
 436 +                       pos = readl(c->chan_base + BCM2835_DMA_DEST_AD);
 437 +               else
 438 +                       pos = 0;
 439 +
 440 +               txstate->residue = bcm2835_dma_desc_size_pos(d, pos);
 441 +       } else {
 442 +               txstate->residue = 0;
 443 +       }
 444 +
 445 +       spin_unlock_irqrestore(&c->vc.lock, flags);
 446 +
 447 +       return ret;
 448 +}
 449 +
 450 +static void bcm2835_dma_issue_pending(struct dma_chan *chan)
 451 +{
 452 +       struct bcm2835_chan *c = to_bcm2835_dma_chan(chan);
 453 +       unsigned long flags;
 454 +
 455 +       spin_lock_irqsave(&c->vc.lock, flags);
 456 +       if (vchan_issue_pending(&c->vc) && !c->desc)
 457 +               bcm2835_dma_start_desc(c);
 458 +
 459 +       spin_unlock_irqrestore(&c->vc.lock, flags);
 460 +}
 461 +
 462 +static struct dma_async_tx_descriptor *bcm2835_dma_prep_dma_cyclic(
 463 +       struct dma_chan *chan, dma_addr_t buf_addr, size_t buf_len,
 464 +       size_t period_len, enum dma_transfer_direction direction,
 465 +       unsigned long flags)
 466 +{
 467 +       struct bcm2835_chan *c = to_bcm2835_dma_chan(chan);
 468 +       enum dma_slave_buswidth dev_width;
 469 +       struct bcm2835_desc *d;
 470 +       dma_addr_t dev_addr;
 471 +       unsigned int es, sync_type;
 472 +       unsigned int frame, max_size;
 473 +
 474 +       /* Grab configuration */
 475 +       if (!is_slave_direction(direction)) {
 476 +               dev_err(chan->device->dev, "%s: bad direction?\n", __func__);
 477 +               return NULL;
 478 +       }
 479 +
 480 +       if (direction == DMA_DEV_TO_MEM) {
 481 +               dev_addr = c->cfg.src_addr;
 482 +               dev_width = c->cfg.src_addr_width;
 483 +               sync_type = BCM2835_DMA_S_DREQ;
 484 +       } else {
 485 +               dev_addr = c->cfg.dst_addr;
 486 +               dev_width = c->cfg.dst_addr_width;
 487 +               sync_type = BCM2835_DMA_D_DREQ;
 488 +       }
 489 +
 490 +       /* Bus width translates to the element size (ES) */
 491 +       switch (dev_width) {
 492 +       case DMA_SLAVE_BUSWIDTH_4_BYTES:
 493 +               es = BCM2835_DMA_DATA_TYPE_S32;
 494 +               break;
 495 +       default:
 496 +               return NULL;
 497 +       }
 498 +
 499 +       /* Now allocate and setup the descriptor. */
 500 +       d = kzalloc(sizeof(*d), GFP_NOWAIT);
 501 +       if (!d)
 502 +               return NULL;
 503 +
 504 +       d->dir = direction;
 505 +
 506 +       if (c->ch >= 8) /* we have a LITE channel */
 507 +               max_size = MAX_LITE_TRANSFER;
 508 +       else
 509 +               max_size = MAX_NORMAL_TRANSFER;
 510 +       period_len = min(period_len, max_size);
 511 +
 512 +       d->frames = (buf_len-1) / period_len + 1;
 513 +
 514 +       /* Allocate memory for control blocks */
 515 +       d->control_block_size = d->frames * sizeof(struct bcm2835_dma_cb);
 516 +       d->control_block_base = dma_zalloc_coherent(chan->device->dev,
 517 +                       d->control_block_size, &d->control_block_base_phys,
 518 +                       GFP_NOWAIT);
 519 +
 520 +       if (!d->control_block_base) {
 521 +               kfree(d);
 522 +               return NULL;
 523 +       }
 524 +
 525 +       /*
 526 +        * Iterate over all frames, create a control block
 527 +        * for each frame and link them together.
 528 +        */
 529 +       for (frame = 0; frame < d->frames; frame++) {
 530 +               struct bcm2835_dma_cb *control_block =
 531 +                       &d->control_block_base[frame];
 532 +
 533 +               /* Setup adresses */
 534 +               if (d->dir == DMA_DEV_TO_MEM) {
 535 +                       control_block->info = BCM2835_DMA_D_INC;
 536 +                       control_block->src = dev_addr;
 537 +                       control_block->dst = buf_addr + frame * period_len;
 538 +               } else {
 539 +                       control_block->info = BCM2835_DMA_S_INC;
 540 +                       control_block->src = buf_addr + frame * period_len;
 541 +                       control_block->dst = dev_addr;
 542 +               }
 543 +
 544 +               /* Enable interrupt */
 545 +               control_block->info |= BCM2835_DMA_INT_EN;
 546 +
 547 +               /* Setup synchronization */
 548 +               if (sync_type != 0)
 549 +                       control_block->info |= sync_type;
 550 +
 551 +               /* Setup DREQ channel */
 552 +               if (c->cfg.slave_id != 0)
 553 +                       control_block->info |=
 554 +                               BCM2835_DMA_PER_MAP(c->cfg.slave_id);
 555 +
 556 +               /* Length of a frame */
 557 +               if (frame != d->frames-1)
 558 +                       control_block->length = period_len;
 559 +               else
 560 +                       control_block->length = buf_len - (d->frames - 1) * period_len;
 561 +
 562 +               d->size += control_block->length;
 563 +
 564 +               /*
 565 +                * Next block is the next frame.
 566 +                * This function is called on cyclic DMA transfers.
 567 +                * Therefore, wrap around at number of frames.
 568 +                */
 569 +               control_block->next = d->control_block_base_phys +
 570 +                       sizeof(struct bcm2835_dma_cb)
 571 +                       * ((frame + 1) % d->frames);
 572 +       }
 573 +
 574 +       c->cyclic = true;
 575 +
 576 +       return vchan_tx_prep(&c->vc, &d->vd, flags);
 577 +}
 578 +
 579 +
 580 +static struct dma_async_tx_descriptor *bcm2835_dma_prep_slave_sg(
 581 +       struct dma_chan *chan, struct scatterlist *sgl,
 582 +       unsigned int sg_len, enum dma_transfer_direction direction,
 583 +       unsigned long flags, void *context)
 584 +{
 585 +       struct bcm2835_chan *c = to_bcm2835_dma_chan(chan);
 586 +       enum dma_slave_buswidth dev_width;
 587 +       struct bcm2835_desc *d;
 588 +       dma_addr_t dev_addr;
 589 +       struct scatterlist *sgent;
 590 +       unsigned int es, sync_type;
 591 +       unsigned int i, j, splitct, max_size;
 592 +
 593 +       if (!is_slave_direction(direction)) {
 594 +               dev_err(chan->device->dev, "%s: bad direction?\n", __func__);
 595 +               return NULL;
 596 +       }
 597 +
 598 +       if (direction == DMA_DEV_TO_MEM) {
 599 +               dev_addr = c->cfg.src_addr;
 600 +               dev_width = c->cfg.src_addr_width;
 601 +               sync_type = BCM2835_DMA_S_DREQ;
 602 +       } else {
 603 +               dev_addr = c->cfg.dst_addr;
 604 +               dev_width = c->cfg.dst_addr_width;
 605 +               sync_type = BCM2835_DMA_D_DREQ;
 606 +       }
 607 +
 608 +       /* Bus width translates to the element size (ES) */
 609 +       switch (dev_width) {
 610 +       case DMA_SLAVE_BUSWIDTH_4_BYTES:
 611 +               es = BCM2835_DMA_DATA_TYPE_S32;
 612 +               break;
 613 +       default:
 614 +               return NULL;
 615 +       }
 616 +
 617 +       /* Now allocate and setup the descriptor. */
 618 +       d = kzalloc(sizeof(*d), GFP_NOWAIT);
 619 +       if (!d)
 620 +               return NULL;
 621 +
 622 +       d->dir = direction;
 623 +
 624 +       if (c->ch >= 8) /* we have a LITE channel */
 625 +               max_size = MAX_LITE_TRANSFER;
 626 +       else
 627 +               max_size = MAX_NORMAL_TRANSFER;
 628 +
 629 +       /* We store the length of the SG list in d->frames
 630 +          taking care to account for splitting up transfers
 631 +          too large for a LITE channel */
 632 +
 633 +       d->frames = 0;
 634 +       for_each_sg(sgl, sgent, sg_len, i) {
 635 +               uint32_t len = sg_dma_len(sgent);
 636 +               d->frames += 1 + len / max_size;
 637 +       }
 638 +
 639 +       /* Allocate memory for control blocks */
 640 +       d->control_block_size = d->frames * sizeof(struct bcm2835_dma_cb);
 641 +       d->control_block_base = dma_zalloc_coherent(chan->device->dev,
 642 +                       d->control_block_size, &d->control_block_base_phys,
 643 +                       GFP_NOWAIT);
 644 +
 645 +       if (!d->control_block_base) {
 646 +               kfree(d);
 647 +               return NULL;
 648 +       }
 649 +
 650 +       /*
 651 +        * Iterate over all SG entries, create a control block
 652 +        * for each frame and link them together.
 653 +        */
 654 +
 655 +       /* we count the number of times an SG entry had to be splitct
 656 +          as a result of using a LITE channel */
 657 +       splitct = 0;
 658 +
 659 +       for_each_sg(sgl, sgent, sg_len, i) {
 660 +               dma_addr_t addr = sg_dma_address(sgent);
 661 +               uint32_t len = sg_dma_len(sgent);
 662 +
 663 +               for (j = 0; j < len; j += max_size) {
 664 +                       struct bcm2835_dma_cb *control_block =
 665 +                               &d->control_block_base[i+splitct];
 666 +
 667 +                       /* Setup adresses */
 668 +                       if (d->dir == DMA_DEV_TO_MEM) {
 669 +                               control_block->info = BCM2835_DMA_D_INC |
 670 +                                       BCM2835_DMA_D_WIDTH | BCM2835_DMA_S_DREQ;
 671 +                               control_block->src = dev_addr;
 672 +                               control_block->dst = addr + (dma_addr_t)j;
 673 +                       } else {
 674 +                               control_block->info = BCM2835_DMA_S_INC |
 675 +                                       BCM2835_DMA_S_WIDTH | BCM2835_DMA_D_DREQ;
 676 +                               control_block->src = addr + (dma_addr_t)j;
 677 +                               control_block->dst = dev_addr;
 678 +                       }
 679 +
 680 +                       /* Common part */
 681 +                       control_block->info |= BCM2835_DMA_WAITS(SDHCI_BCM_DMA_WAITS);
 682 +                       control_block->info |= BCM2835_DMA_WAIT_RESP;
 683 +
 684 +                       /* Enable  */
 685 +                       if (i == sg_len-1 && len-j <= max_size)
 686 +                               control_block->info |= BCM2835_DMA_INT_EN;
 687 +
 688 +                       /* Setup synchronization */
 689 +                       if (sync_type != 0)
 690 +                               control_block->info |= sync_type;
 691 +
 692 +                       /* Setup DREQ channel */
 693 +                       c->dreq = c->cfg.slave_id; /* DREQ loaded from config */
 694 +
 695 +                       if (c->dreq != 0)
 696 +                               control_block->info |=
 697 +                                       BCM2835_DMA_PER_MAP(c->dreq);
 698 +
 699 +                       /* Length of a frame */
 700 +                       control_block->length = min(len-j, max_size);
 701 +                       d->size += control_block->length;
 702 +
 703 +                       /*
 704 +                        * Next block is the next frame.
 705 +                        */
 706 +                       if (i < sg_len-1 || len-j > max_size) {
 707 +                               /* next block is the next frame. */
 708 +                               control_block->next = d->control_block_base_phys +
 709 +                               sizeof(struct bcm2835_dma_cb) * (i + splitct + 1);
 710 +                       } else {
 711 +                               /* next block is empty. */
 712 +                               control_block->next = 0;
 713 +                       }
 714 +
 715 +                       if (len-j > max_size)
 716 +                               splitct++;
 717 +               }
 718 +       }
 719 +
 720 +       c->cyclic = false;
 721 +
 722 +       return vchan_tx_prep(&c->vc, &d->vd, flags);
 723 +}
 724 +
 725 +static int bcm2835_dma_slave_config(struct bcm2835_chan *c,
 726 +               struct dma_slave_config *cfg)
 727 +{
 728 +       if ((cfg->direction == DMA_DEV_TO_MEM &&
 729 +            cfg->src_addr_width != DMA_SLAVE_BUSWIDTH_4_BYTES) ||
 730 +           (cfg->direction == DMA_MEM_TO_DEV &&
 731 +            cfg->dst_addr_width != DMA_SLAVE_BUSWIDTH_4_BYTES) ||
 732 +           !is_slave_direction(cfg->direction)) {
 733 +               return -EINVAL;
 734 +       }
 735 +
 736 +       c->cfg = *cfg;
 737 +
 738 +       return 0;
 739 +}
 740 +
 741 +static int bcm2835_dma_terminate_all(struct bcm2835_chan *c)
 742 +{
 743 +       struct bcm2835_dmadev *d = to_bcm2835_dma_dev(c->vc.chan.device);
 744 +       unsigned long flags;
 745 +       int timeout = 10000;
 746 +       LIST_HEAD(head);
 747 +
 748 +       spin_lock_irqsave(&c->vc.lock, flags);
 749 +
 750 +       /* Prevent this channel being scheduled */
 751 +       spin_lock(&d->lock);
 752 +       list_del_init(&c->node);
 753 +       spin_unlock(&d->lock);
 754 +
 755 +       /*
 756 +        * Stop DMA activity: we assume the callback will not be called
 757 +        * after bcm_dma_abort() returns (even if it does, it will see
 758 +        * c->desc is NULL and exit.)
 759 +        */
 760 +       if (c->desc) {
 761 +               c->desc = NULL;
 762 +               bcm2835_dma_abort(c->chan_base);
 763 +
 764 +               /* Wait for stopping */
 765 +               while (--timeout) {
 766 +                       if (!(readl(c->chan_base + BCM2835_DMA_CS) &
 767 +                                               BCM2835_DMA_ACTIVE))
 768 +                               break;
 769 +
 770 +                       cpu_relax();
 771 +               }
 772 +
 773 +               if (!timeout)
 774 +                       dev_err(d->ddev.dev, "DMA transfer could not be terminated\n");
 775 +       }
 776 +
 777 +       vchan_get_all_descriptors(&c->vc, &head);
 778 +       spin_unlock_irqrestore(&c->vc.lock, flags);
 779 +       vchan_dma_desc_free_list(&c->vc, &head);
 780 +
 781 +       return 0;
 782 +}
 783 +
 784 +static int bcm2835_dma_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
 785 +       unsigned long arg)
 786 +{
 787 +       struct bcm2835_chan *c = to_bcm2835_dma_chan(chan);
 788 +
 789 +       switch (cmd) {
 790 +       case DMA_SLAVE_CONFIG:
 791 +               return bcm2835_dma_slave_config(c,
 792 +                               (struct dma_slave_config *)arg);
 793 +
 794 +       case DMA_TERMINATE_ALL:
 795 +               return bcm2835_dma_terminate_all(c);
 796 +
 797 +       default:
 798 +               return -ENXIO;
 799 +       }
 800 +}
 801 +
 802 +#ifdef CONFIG_OF
 803 +static int bcm2835_dma_chan_init(struct bcm2835_dmadev *d, int chan_id, int irq)
 804 +{
 805 +       struct bcm2835_chan *c;
 806 +
 807 +       c = devm_kzalloc(d->ddev.dev, sizeof(*c), GFP_KERNEL);
 808 +       if (!c)
 809 +               return -ENOMEM;
 810 +
 811 +       c->vc.desc_free = bcm2835_dma_desc_free;
 812 +       vchan_init(&c->vc, &d->ddev);
 813 +       INIT_LIST_HEAD(&c->node);
 814 +
 815 +       d->ddev.chancnt++;
 816 +
 817 +       c->chan_base = BCM2835_DMA_CHANIO(d->base, chan_id);
 818 +       c->ch = chan_id;
 819 +       c->irq_number = irq;
 820 +
 821 +       return 0;
 822 +}
 823 +#endif
 824 +
 825 +static int bcm2708_dma_chan_init(struct bcm2835_dmadev *d,
 826 +       void __iomem *chan_base, int chan_id, int irq)
 827 +{
 828 +       struct bcm2835_chan *c;
 829 +
 830 +       c = devm_kzalloc(d->ddev.dev, sizeof(*c), GFP_KERNEL);
 831 +       if (!c)
 832 +               return -ENOMEM;
 833 +
 834 +       c->vc.desc_free = bcm2835_dma_desc_free;
 835 +       vchan_init(&c->vc, &d->ddev);
 836 +       INIT_LIST_HEAD(&c->node);
 837 +
 838 +       d->ddev.chancnt++;
 839 +
 840 +       c->chan_base = chan_base;
 841 +       c->ch = chan_id;
 842 +       c->irq_number = irq;
 843 +
 844 +       return 0;
 845 +}
 846 +
 847 +
 848 +static void bcm2835_dma_free(struct bcm2835_dmadev *od)
 849 +{
 850 +       struct bcm2835_chan *c, *next;
 851 +
 852 +       list_for_each_entry_safe(c, next, &od->ddev.channels,
 853 +                                vc.chan.device_node) {
 854 +               list_del(&c->vc.chan.device_node);
 855 +               tasklet_kill(&c->vc.task);
 856 +       }
 857 +}
 858 +
 859 +static const struct of_device_id bcm2835_dma_of_match[] = {
 860 +       { .compatible = "brcm,bcm2835-dma", },
 861 +       {},
 862 +};
 863 +MODULE_DEVICE_TABLE(of, bcm2835_dma_of_match);
 864 +
 865 +#ifdef CONFIG_OF
 866 +static struct dma_chan *bcm2835_dma_xlate(struct of_phandle_args *spec,
 867 +                                          struct of_dma *ofdma)
 868 +{
 869 +       struct bcm2835_dmadev *d = ofdma->of_dma_data;
 870 +       struct dma_chan *chan;
 871 +
 872 +       chan = dma_get_any_slave_channel(&d->ddev);
 873 +       if (!chan)
 874 +               return NULL;
 875 +
 876 +       /* Set DREQ from param */
 877 +       to_bcm2835_dma_chan(chan)->dreq = spec->args[0];
 878 +
 879 +       return chan;
 880 +}
 881 +#endif
 882 +
 883 +static int bcm2835_dma_device_slave_caps(struct dma_chan *dchan,
 884 +       struct dma_slave_caps *caps)
 885 +{
 886 +       caps->src_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_4_BYTES);
 887 +       caps->dstn_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_4_BYTES);
 888 +       caps->directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV);
 889 +       caps->cmd_pause = false;
 890 +       caps->cmd_terminate = true;
 891 +
 892 +       return 0;
 893 +}
 894 +
 895 +static int bcm2835_dma_probe(struct platform_device *pdev)
 896 +{
 897 +       struct bcm2835_dmadev *od;
 898 +#ifdef CONFIG_OF
 899 +       struct resource *res;
 900 +       void __iomem *base;
 901 +       uint32_t chans_available;
 902 +#endif
 903 +       int rc;
 904 +       int i;
 905 +       int irq;
 906 +
 907 +
 908 +       if (!pdev->dev.dma_mask)
 909 +               pdev->dev.dma_mask = &pdev->dev.coherent_dma_mask;
 910 +
 911 +       /* If CONFIG_OF is selected, device tree is used */
 912 +       /* hence the difference between probing */
 913 +
 914 +#ifndef CONFIG_OF
 915 +
 916 +       rc = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
 917 +       if (rc)
 918 +               return rc;
 919 +       dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32));
 920 +
 921 +
 922 +       od = devm_kzalloc(&pdev->dev, sizeof(*od), GFP_KERNEL);
 923 +       if (!od)
 924 +               return -ENOMEM;
 925 +
 926 +       pdev->dev.dma_parms = &od->dma_parms;
 927 +       dma_set_max_seg_size(&pdev->dev, 0x3FFFFFFF);
 928 +
 929 +
 930 +       dma_cap_set(DMA_SLAVE, od->ddev.cap_mask);
 931 +       dma_cap_set(DMA_PRIVATE, od->ddev.cap_mask);
 932 +       dma_cap_set(DMA_CYCLIC, od->ddev.cap_mask);
 933 +       od->ddev.device_alloc_chan_resources = bcm2835_dma_alloc_chan_resources;
 934 +       od->ddev.device_free_chan_resources = bcm2835_dma_free_chan_resources;
 935 +       od->ddev.device_tx_status = bcm2835_dma_tx_status;
 936 +       od->ddev.device_issue_pending = bcm2835_dma_issue_pending;
 937 +       od->ddev.device_slave_caps = bcm2835_dma_device_slave_caps;
 938 +       od->ddev.device_prep_dma_cyclic = bcm2835_dma_prep_dma_cyclic;
 939 +       od->ddev.device_prep_slave_sg = bcm2835_dma_prep_slave_sg;
 940 +       od->ddev.device_control = bcm2835_dma_control;
 941 +       od->ddev.dev = &pdev->dev;
 942 +       INIT_LIST_HEAD(&od->ddev.channels);
 943 +       spin_lock_init(&od->lock);
 944 +
 945 +       platform_set_drvdata(pdev, od);
 946 +
 947 +       for (i = 0; i < 5; i++) {
 948 +               void __iomem *chan_base;
 949 +               int chan_id;
 950 +
 951 +               chan_id = bcm_dma_chan_alloc(BCM_DMA_FEATURE_LITE,
 952 +                       &chan_base,
 953 +                       &irq);
 954 +
 955 +               if (chan_id < 0)
 956 +                       break;
 957 +
 958 +               rc = bcm2708_dma_chan_init(od, chan_base, chan_id, irq);
 959 +               if (rc)
 960 +                       goto err_no_dma;
 961 +       }
 962 +#else
 963 +       rc = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
 964 +       if (rc)
 965 +               return rc;
 966 +
 967 +
 968 +       od = devm_kzalloc(&pdev->dev, sizeof(*od), GFP_KERNEL);
 969 +       if (!od)
 970 +               return -ENOMEM;
 971 +
 972 +       pdev->dev.dma_parms = &od->dma_parms;
 973 +       dma_set_max_seg_size(&pdev->dev, 0x3FFFFFFF);
 974 +
 975 +
 976 +       res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 977 +       base = devm_ioremap_resource(&pdev->dev, res);
 978 +       if (IS_ERR(base))
 979 +               return PTR_ERR(base);
 980 +
 981 +       od->base = base;
 982 +
 983 +
 984 +       dma_cap_set(DMA_SLAVE, od->ddev.cap_mask);
 985 +       dma_cap_set(DMA_PRIVATE, od->ddev.cap_mask);
 986 +       dma_cap_set(DMA_CYCLIC, od->ddev.cap_mask);
 987 +       od->ddev.device_alloc_chan_resources = bcm2835_dma_alloc_chan_resources;
 988 +       od->ddev.device_free_chan_resources = bcm2835_dma_free_chan_resources;
 989 +       od->ddev.device_tx_status = bcm2835_dma_tx_status;
 990 +       od->ddev.device_issue_pending = bcm2835_dma_issue_pending;
 991 +       od->ddev.device_slave_caps = bcm2835_dma_device_slave_caps;
 992 +       od->ddev.device_prep_dma_cyclic = bcm2835_dma_prep_dma_cyclic;
 993 +       od->ddev.device_prep_slave_sg = bcm2835_dma_prep_slave_sg;
 994 +       od->ddev.device_control = bcm2835_dma_control;
 995 +       od->ddev.dev = &pdev->dev;
 996 +       INIT_LIST_HEAD(&od->ddev.channels);
 997 +       spin_lock_init(&od->lock);
 998 +
 999 +       platform_set_drvdata(pdev, od);
1000 +
1001 +
1002 +       /* Request DMA channel mask from device tree */
1003 +       if (of_property_read_u32(pdev->dev.of_node,
1004 +                       "brcm,dma-channel-mask",
1005 +                       &chans_available)) {
1006 +               dev_err(&pdev->dev, "Failed to get channel mask\n");
1007 +               rc = -EINVAL;
1008 +               goto err_no_dma;
1009 +       }
1010 +
1011 +
1012 +       /*
1013 +        * Do not use the FIQ and BULK channels,
1014 +        * because they are used by the GPU.
1015 +        */
1016 +       chans_available &= ~(BCM2835_DMA_FIQ_MASK | BCM2835_DMA_BULK_MASK);
1017 +
1018 +
1019 +       for (i = 0; i < pdev->num_resources; i++) {
1020 +               irq = platform_get_irq(pdev, i);
1021 +               if (irq < 0)
1022 +                       break;
1023 +
1024 +               if (chans_available & (1 << i)) {
1025 +                       rc = bcm2835_dma_chan_init(od, i, irq);
1026 +                       if (rc)
1027 +                               goto err_no_dma;
1028 +               }
1029 +       }
1030 +
1031 +       dev_dbg(&pdev->dev, "Initialized %i DMA channels\n", i);
1032 +
1033 +       /* Device-tree DMA controller registration */
1034 +       rc = of_dma_controller_register(pdev->dev.of_node,
1035 +                       bcm2835_dma_xlate, od);
1036 +       if (rc) {
1037 +               dev_err(&pdev->dev, "Failed to register DMA controller\n");
1038 +               goto err_no_dma;
1039 +       }
1040 +#endif
1041 +
1042 +       rc = dma_async_device_register(&od->ddev);
1043 +       if (rc) {
1044 +               dev_err(&pdev->dev,
1045 +                       "Failed to register slave DMA engine device: %d\n", rc);
1046 +               goto err_no_dma;
1047 +       }
1048 +
1049 +       dev_info(&pdev->dev, "Load BCM2835 DMA engine driver\n");
1050 +
1051 +       return 0;
1052 +
1053 +err_no_dma:
1054 +       bcm2835_dma_free(od);
1055 +       return rc;
1056 +}
1057 +
1058 +static int bcm2835_dma_remove(struct platform_device *pdev)
1059 +{
1060 +       struct bcm2835_dmadev *od = platform_get_drvdata(pdev);
1061 +
1062 +       dma_async_device_unregister(&od->ddev);
1063 +       bcm2835_dma_free(od);
1064 +
1065 +       return 0;
1066 +}
1067 +
1068 +#ifndef CONFIG_OF
1069 +
1070 +
1071 +static struct platform_driver bcm2835_dma_driver = {
1072 +       .probe  = bcm2835_dma_probe,
1073 +       .remove = bcm2835_dma_remove,
1074 +       .driver = {
1075 +               .name = "bcm2708-dmaengine",
1076 +               .owner = THIS_MODULE,
1077 +       },
1078 +};
1079 +
1080 +static struct platform_device *pdev;
1081 +
1082 +static const struct platform_device_info bcm2835_dma_dev_info = {
1083 +       .name = "bcm2708-dmaengine",
1084 +       .id = -1,
1085 +};
1086 +
1087 +static int bcm2835_dma_init(void)
1088 +{
1089 +       int rc = platform_driver_register(&bcm2835_dma_driver);
1090 +
1091 +       if (rc == 0) {
1092 +               pdev = platform_device_register_full(&bcm2835_dma_dev_info);
1093 +               if (IS_ERR(pdev)) {
1094 +                       platform_driver_unregister(&bcm2835_dma_driver);
1095 +                       rc = PTR_ERR(pdev);
1096 +               }
1097 +       }
1098 +
1099 +       return rc;
1100 +}
1101 +module_init(bcm2835_dma_init); /* preferable to subsys_initcall */
1102 +
1103 +static void __exit bcm2835_dma_exit(void)
1104 +{
1105 +       platform_device_unregister(pdev);
1106 +       platform_driver_unregister(&bcm2835_dma_driver);
1107 +}
1108 +module_exit(bcm2835_dma_exit);
1109 +
1110 +#else
1111 +
1112 +static struct platform_driver bcm2835_dma_driver = {
1113 +       .probe  = bcm2835_dma_probe,
1114 +       .remove = bcm2835_dma_remove,
1115 +       .driver = {
1116 +               .name = "bcm2835-dma",
1117 +               .owner = THIS_MODULE,
1118 +               .of_match_table = of_match_ptr(bcm2835_dma_of_match),
1119 +       },
1120 +};
1121 +
1122 +module_platform_driver(bcm2835_dma_driver);
1123 +
1124 +#endif
1125 +
1126 +MODULE_ALIAS("platform:bcm2835-dma");
1127 +MODULE_DESCRIPTION("BCM2835 DMA engine driver");
1128 +MODULE_AUTHOR("Florian Meier <florian.meier@koalo.de>");
1129 +MODULE_AUTHOR("Gellert Weisz <gellert@raspberrypi.org>");
1130 +MODULE_LICENSE("GPL v2");