target/linux/ar71xx/patches-3.10/707-MIPS-ath79-add-support-for-QCA953x-SoC.patch

   1 From 5300a7cd7ed2f88488ddba62947b9c6bb9663777 Mon Sep 17 00:00:00 2001
   2 Message-Id: <5300a7cd7ed2f88488ddba62947b9c6bb9663777.1396122227.git.mschiffer@universe-factory.net>
   3 From: Matthias Schiffer <mschiffer@universe-factory.net>
   4 Date: Sat, 29 Mar 2014 20:26:08 +0100
   5 Subject: [PATCH 1/2] MIPS: ath79: add support for QCA953x SoC
   6
   7 Note that the clock calculation looks very similar to the QCA955x, but the
   8 meaning of the bits CPUCLK_FROM_CPUPLL and DDRCLK_FROM_DDRPLL is reversed.
   9 ---
  10  arch/mips/ath79/Kconfig                        |  6 +-
  11  arch/mips/ath79/clock.c                        | 78 ++++++++++++++++++++++++++
  12  arch/mips/ath79/common.c                       |  4 ++
  13  arch/mips/ath79/dev-common.c                   |  1 +
  14  arch/mips/ath79/dev-wmac.c                     | 20 +++++++
  15  arch/mips/ath79/early_printk.c                 |  1 +
  16  arch/mips/ath79/gpio.c                         |  4 +-
  17  arch/mips/ath79/irq.c                          |  4 ++
  18  arch/mips/ath79/setup.c                        |  8 ++-
  19  arch/mips/include/asm/mach-ath79/ar71xx_regs.h | 48 ++++++++++++++++
  20  arch/mips/include/asm/mach-ath79/ath79.h       | 11 ++++
  21  11 files changed, 182 insertions(+), 3 deletions(-)
  22
  23 --- a/arch/mips/ath79/Kconfig
  24 +++ b/arch/mips/ath79/Kconfig
  25 @@ -929,6 +929,10 @@ config SOC_AR934X
  26         select PCI_AR724X if PCI
  27         def_bool n
  28
  29 +config SOC_QCA953X
  30 +       select USB_ARCH_HAS_EHCI
  31 +       def_bool n
  32 +
  33  config SOC_QCA955X
  34         select USB_ARCH_HAS_EHCI
  35         select HW_HAS_PCI
  36 @@ -972,7 +976,7 @@ config ATH79_DEV_USB
  37         def_bool n
  38
  39  config ATH79_DEV_WMAC
  40 -       depends on (SOC_AR913X || SOC_AR933X || SOC_AR934X || SOC_QCA955X)
  41 +       depends on (SOC_AR913X || SOC_AR933X || SOC_AR934X || SOC_QCA953X || SOC_QCA955X)
  42         def_bool n
  43
  44  config ATH79_NVRAM
  45 --- a/arch/mips/ath79/clock.c
  46 +++ b/arch/mips/ath79/clock.c
  47 @@ -295,6 +295,82 @@ static void __init ar934x_clocks_init(vo
  48         iounmap(dpll_base);
  49  }
  50
  51 +static void __init qca953x_clocks_init(void)
  52 +{
  53 +       u32 pll, out_div, ref_div, nint, frac, clk_ctrl, postdiv;
  54 +       u32 cpu_pll, ddr_pll;
  55 +       u32 bootstrap;
  56 +
  57 +       bootstrap = ath79_reset_rr(QCA953X_RESET_REG_BOOTSTRAP);
  58 +       if (bootstrap & QCA953X_BOOTSTRAP_REF_CLK_40)
  59 +               ath79_ref_clk.rate = 40 * 1000 * 1000;
  60 +       else
  61 +               ath79_ref_clk.rate = 25 * 1000 * 1000;
  62 +
  63 +       pll = ath79_pll_rr(QCA953X_PLL_CPU_CONFIG_REG);
  64 +       out_div = (pll >> QCA953X_PLL_CPU_CONFIG_OUTDIV_SHIFT) &
  65 +                 QCA953X_PLL_CPU_CONFIG_OUTDIV_MASK;
  66 +       ref_div = (pll >> QCA953X_PLL_CPU_CONFIG_REFDIV_SHIFT) &
  67 +                 QCA953X_PLL_CPU_CONFIG_REFDIV_MASK;
  68 +       nint = (pll >> QCA953X_PLL_CPU_CONFIG_NINT_SHIFT) &
  69 +              QCA953X_PLL_CPU_CONFIG_NINT_MASK;
  70 +       frac = (pll >> QCA953X_PLL_CPU_CONFIG_NFRAC_SHIFT) &
  71 +              QCA953X_PLL_CPU_CONFIG_NFRAC_MASK;
  72 +
  73 +       cpu_pll = nint * ath79_ref_clk.rate / ref_div;
  74 +       cpu_pll += frac * (ath79_ref_clk.rate >> 6) / ref_div;
  75 +       cpu_pll /= (1 << out_div);
  76 +
  77 +       pll = ath79_pll_rr(QCA953X_PLL_DDR_CONFIG_REG);
  78 +       out_div = (pll >> QCA953X_PLL_DDR_CONFIG_OUTDIV_SHIFT) &
  79 +                 QCA953X_PLL_DDR_CONFIG_OUTDIV_MASK;
  80 +       ref_div = (pll >> QCA953X_PLL_DDR_CONFIG_REFDIV_SHIFT) &
  81 +                 QCA953X_PLL_DDR_CONFIG_REFDIV_MASK;
  82 +       nint = (pll >> QCA953X_PLL_DDR_CONFIG_NINT_SHIFT) &
  83 +              QCA953X_PLL_DDR_CONFIG_NINT_MASK;
  84 +       frac = (pll >> QCA953X_PLL_DDR_CONFIG_NFRAC_SHIFT) &
  85 +              QCA953X_PLL_DDR_CONFIG_NFRAC_MASK;
  86 +
  87 +       ddr_pll = nint * ath79_ref_clk.rate / ref_div;
  88 +       ddr_pll += frac * (ath79_ref_clk.rate >> 6) / (ref_div << 4);
  89 +       ddr_pll /= (1 << out_div);
  90 +
  91 +       clk_ctrl = ath79_pll_rr(QCA953X_PLL_CLK_CTRL_REG);
  92 +
  93 +       postdiv = (clk_ctrl >> QCA953X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT) &
  94 +                 QCA953X_PLL_CLK_CTRL_CPU_POST_DIV_MASK;
  95 +
  96 +       if (clk_ctrl & QCA953X_PLL_CLK_CTRL_CPU_PLL_BYPASS)
  97 +               ath79_cpu_clk.rate = ath79_ref_clk.rate;
  98 +       else if (clk_ctrl & QCA953X_PLL_CLK_CTRL_CPUCLK_FROM_CPUPLL)
  99 +               ath79_cpu_clk.rate = cpu_pll / (postdiv + 1);
 100 +       else
 101 +               ath79_cpu_clk.rate = ddr_pll / (postdiv + 1);
 102 +
 103 +       postdiv = (clk_ctrl >> QCA953X_PLL_CLK_CTRL_DDR_POST_DIV_SHIFT) &
 104 +                 QCA953X_PLL_CLK_CTRL_DDR_POST_DIV_MASK;
 105 +
 106 +       if (clk_ctrl & QCA953X_PLL_CLK_CTRL_DDR_PLL_BYPASS)
 107 +               ath79_ddr_clk.rate = ath79_ref_clk.rate;
 108 +       else if (clk_ctrl & QCA953X_PLL_CLK_CTRL_DDRCLK_FROM_DDRPLL)
 109 +               ath79_ddr_clk.rate = ddr_pll / (postdiv + 1);
 110 +       else
 111 +               ath79_ddr_clk.rate = cpu_pll / (postdiv + 1);
 112 +
 113 +       postdiv = (clk_ctrl >> QCA953X_PLL_CLK_CTRL_AHB_POST_DIV_SHIFT) &
 114 +                 QCA953X_PLL_CLK_CTRL_AHB_POST_DIV_MASK;
 115 +
 116 +       if (clk_ctrl & QCA953X_PLL_CLK_CTRL_AHB_PLL_BYPASS)
 117 +               ath79_ahb_clk.rate = ath79_ref_clk.rate;
 118 +       else if (clk_ctrl & QCA953X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL)
 119 +               ath79_ahb_clk.rate = ddr_pll / (postdiv + 1);
 120 +       else
 121 +               ath79_ahb_clk.rate = cpu_pll / (postdiv + 1);
 122 +
 123 +       ath79_wdt_clk.rate = ath79_ref_clk.rate;
 124 +       ath79_uart_clk.rate = ath79_ref_clk.rate;
 125 +}
 126 +
 127  static void __init qca955x_clocks_init(void)
 128  {
 129         u32 pll, out_div, ref_div, nint, frac, clk_ctrl, postdiv;
 130 @@ -383,6 +459,8 @@ void __init ath79_clocks_init(void)
 131                 ar933x_clocks_init();
 132         else if (soc_is_ar934x())
 133                 ar934x_clocks_init();
 134 +       else if (soc_is_qca953x())
 135 +               qca953x_clocks_init();
 136         else if (soc_is_qca955x())
 137                 qca955x_clocks_init();
 138         else
 139 --- a/arch/mips/ath79/common.c
 140 +++ b/arch/mips/ath79/common.c
 141 @@ -73,6 +73,8 @@ void ath79_device_reset_set(u32 mask)
 142                 reg = AR933X_RESET_REG_RESET_MODULE;
 143         else if (soc_is_ar934x())
 144                 reg = AR934X_RESET_REG_RESET_MODULE;
 145 +       else if (soc_is_qca953x())
 146 +               reg = QCA953X_RESET_REG_RESET_MODULE;
 147         else if (soc_is_qca955x())
 148                 reg = QCA955X_RESET_REG_RESET_MODULE;
 149         else
 150 @@ -101,6 +103,8 @@ void ath79_device_reset_clear(u32 mask)
 151                 reg = AR933X_RESET_REG_RESET_MODULE;
 152         else if (soc_is_ar934x())
 153                 reg = AR934X_RESET_REG_RESET_MODULE;
 154 +       else if (soc_is_qca953x())
 155 +               reg = QCA953X_RESET_REG_RESET_MODULE;
 156         else if (soc_is_qca955x())
 157                 reg = QCA955X_RESET_REG_RESET_MODULE;
 158         else
 159 --- a/arch/mips/ath79/dev-common.c
 160 +++ b/arch/mips/ath79/dev-common.c
 161 @@ -100,6 +100,7 @@ void __init ath79_register_uart(void)
 162             soc_is_ar724x() ||
 163             soc_is_ar913x() ||
 164             soc_is_ar934x() ||
 165 +           soc_is_qca953x() ||
 166             soc_is_qca955x()) {
 167                 ath79_uart_data[0].uartclk = clk_get_rate(clk);
 168                 platform_device_register(&ath79_uart_device);
 169 --- a/arch/mips/ath79/dev-wmac.c
 170 +++ b/arch/mips/ath79/dev-wmac.c
 171 @@ -149,6 +149,24 @@ static void ar934x_wmac_setup(void)
 172                 ath79_wmac_data.is_clk_25mhz = true;
 173  }
 174
 175 +static void qca953x_wmac_setup(void)
 176 +{
 177 +       u32 t;
 178 +
 179 +       ath79_wmac_device.name = "qca953x_wmac";
 180 +
 181 +       ath79_wmac_resources[0].start = QCA953X_WMAC_BASE;
 182 +       ath79_wmac_resources[0].end = QCA953X_WMAC_BASE + QCA953X_WMAC_SIZE - 1;
 183 +       ath79_wmac_resources[1].start = ATH79_CPU_IRQ(2);
 184 +       ath79_wmac_resources[1].end = ATH79_CPU_IRQ(2);
 185 +
 186 +       t = ath79_reset_rr(QCA953X_RESET_REG_BOOTSTRAP);
 187 +       if (t & QCA953X_BOOTSTRAP_REF_CLK_40)
 188 +               ath79_wmac_data.is_clk_25mhz = false;
 189 +       else
 190 +               ath79_wmac_data.is_clk_25mhz = true;
 191 +}
 192 +
 193  static void qca955x_wmac_setup(void)
 194  {
 195         u32 t;
 196 @@ -366,6 +384,8 @@ void __init ath79_register_wmac(u8 *cal_
 197                 ar933x_wmac_setup();
 198         else if (soc_is_ar934x())
 199                 ar934x_wmac_setup();
 200 +       else if (soc_is_qca953x())
 201 +               qca953x_wmac_setup();
 202         else if (soc_is_qca955x())
 203                 qca955x_wmac_setup();
 204         else
 205 --- a/arch/mips/ath79/early_printk.c
 206 +++ b/arch/mips/ath79/early_printk.c
 207 @@ -114,6 +114,7 @@ static void prom_putchar_init(void)
 208         case REV_ID_MAJOR_AR9341:
 209         case REV_ID_MAJOR_AR9342:
 210         case REV_ID_MAJOR_AR9344:
 211 +       case REV_ID_MAJOR_QCA9533:
 212         case REV_ID_MAJOR_QCA9556:
 213         case REV_ID_MAJOR_QCA9558:
 214                 _prom_putchar = prom_putchar_ar71xx;
 215 --- a/arch/mips/ath79/gpio.c
 216 +++ b/arch/mips/ath79/gpio.c
 217 @@ -224,6 +224,8 @@ void __init ath79_gpio_init(void)
 218                 ath79_gpio_count = AR933X_GPIO_COUNT;
 219         else if (soc_is_ar934x())
 220                 ath79_gpio_count = AR934X_GPIO_COUNT;
 221 +       else if (soc_is_qca953x())
 222 +               ath79_gpio_count = QCA953X_GPIO_COUNT;
 223         else if (soc_is_qca955x())
 224                 ath79_gpio_count = QCA955X_GPIO_COUNT;
 225         else
 226 @@ -231,7 +233,7 @@ void __init ath79_gpio_init(void)
 227
 228         ath79_gpio_base = ioremap_nocache(AR71XX_GPIO_BASE, AR71XX_GPIO_SIZE);
 229         ath79_gpio_chip.ngpio = ath79_gpio_count;
 230 -       if (soc_is_ar934x() || soc_is_qca955x()) {
 231 +       if (soc_is_ar934x() || soc_is_qca953x() || soc_is_qca955x()) {
 232                 ath79_gpio_chip.direction_input = ar934x_gpio_direction_input;
 233                 ath79_gpio_chip.direction_output = ar934x_gpio_direction_output;
 234         }
 235 --- a/arch/mips/ath79/irq.c
 236 +++ b/arch/mips/ath79/irq.c
 237 @@ -106,6 +106,7 @@ static void __init ath79_misc_irq_init(v
 238         else if (soc_is_ar724x() ||
 239                  soc_is_ar933x() ||
 240                  soc_is_ar934x() ||
 241 +                soc_is_qca953x() ||
 242                  soc_is_qca955x())
 243                 ath79_misc_irq_chip.irq_ack = ar724x_misc_irq_ack;
 244         else
 245 @@ -352,6 +353,9 @@ void __init arch_init_irq(void)
 246         } else if (soc_is_ar934x()) {
 247                 ath79_ip2_handler = ath79_default_ip2_handler;
 248                 ath79_ip3_handler = ar934x_ip3_handler;
 249 +       } else if (soc_is_qca953x()) {
 250 +               ath79_ip2_handler = ath79_default_ip2_handler;
 251 +               ath79_ip3_handler = ath79_default_ip3_handler;
 252         } else if (soc_is_qca955x()) {
 253                 ath79_ip2_handler = ath79_default_ip2_handler;
 254                 ath79_ip3_handler = ath79_default_ip3_handler;
 255 --- a/arch/mips/ath79/setup.c
 256 +++ b/arch/mips/ath79/setup.c
 257 @@ -151,6 +151,12 @@ static void __init ath79_detect_sys_type
 258                 rev = id & AR934X_REV_ID_REVISION_MASK;
 259                 break;
 260
 261 +       case REV_ID_MAJOR_QCA9533:
 262 +               ath79_soc = ATH79_SOC_QCA9533;
 263 +               chip = "9533";
 264 +               rev = id & QCA953X_REV_ID_REVISION_MASK;
 265 +               break;
 266 +
 267         case REV_ID_MAJOR_QCA9556:
 268                 ath79_soc = ATH79_SOC_QCA9556;
 269                 chip = "9556";
 270 @@ -169,7 +175,7 @@ static void __init ath79_detect_sys_type
 271
 272         ath79_soc_rev = rev;
 273
 274 -       if (soc_is_qca955x())
 275 +       if (soc_is_qca953x() || soc_is_qca955x())
 276                 sprintf(ath79_sys_type, "Qualcomm Atheros QCA%s rev %u",
 277                         chip, rev);
 278         else
 279 --- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
 280 +++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
 281 @@ -106,6 +106,9 @@
 282  #define AR934X_SRIF_BASE       (AR71XX_APB_BASE + 0x00116000)
 283  #define AR934X_SRIF_SIZE       0x1000
 284
 285 +#define QCA953X_WMAC_BASE      (AR71XX_APB_BASE + 0x00100000)
 286 +#define QCA953X_WMAC_SIZE      0x20000
 287 +
 288  #define QCA955X_PCI_MEM_BASE0  0x10000000
 289  #define QCA955X_PCI_MEM_BASE1  0x12000000
 290  #define QCA955X_PCI_MEM_SIZE   0x02000000
 291 @@ -280,6 +283,43 @@
 292
 293  #define AR934X_PLL_SWITCH_CLOCK_CONTROL_MDIO_CLK_SEL   BIT(6)
 294
 295 +#define QCA953X_PLL_CPU_CONFIG_REG             0x00
 296 +#define QCA953X_PLL_DDR_CONFIG_REG             0x04
 297 +#define QCA953X_PLL_CLK_CTRL_REG               0x08
 298 +#define QCA953X_PLL_ETH_XMII_CONTROL_REG       0x2c
 299 +#define QCA953X_PLL_ETH_SGMII_CONTROL_REG      0x48
 300 +
 301 +#define QCA953X_PLL_CPU_CONFIG_NFRAC_SHIFT     0
 302 +#define QCA953X_PLL_CPU_CONFIG_NFRAC_MASK      0x3f
 303 +#define QCA953X_PLL_CPU_CONFIG_NINT_SHIFT      6
 304 +#define QCA953X_PLL_CPU_CONFIG_NINT_MASK       0x3f
 305 +#define QCA953X_PLL_CPU_CONFIG_REFDIV_SHIFT    12
 306 +#define QCA953X_PLL_CPU_CONFIG_REFDIV_MASK     0x1f
 307 +#define QCA953X_PLL_CPU_CONFIG_OUTDIV_SHIFT    19
 308 +#define QCA953X_PLL_CPU_CONFIG_OUTDIV_MASK     0x3
 309 +
 310 +#define QCA953X_PLL_DDR_CONFIG_NFRAC_SHIFT     0
 311 +#define QCA953X_PLL_DDR_CONFIG_NFRAC_MASK      0x3ff
 312 +#define QCA953X_PLL_DDR_CONFIG_NINT_SHIFT      10
 313 +#define QCA953X_PLL_DDR_CONFIG_NINT_MASK       0x3f
 314 +#define QCA953X_PLL_DDR_CONFIG_REFDIV_SHIFT    16
 315 +#define QCA953X_PLL_DDR_CONFIG_REFDIV_MASK     0x1f
 316 +#define QCA953X_PLL_DDR_CONFIG_OUTDIV_SHIFT    23
 317 +#define QCA953X_PLL_DDR_CONFIG_OUTDIV_MASK     0x7
 318 +
 319 +#define QCA953X_PLL_CLK_CTRL_CPU_PLL_BYPASS            BIT(2)
 320 +#define QCA953X_PLL_CLK_CTRL_DDR_PLL_BYPASS            BIT(3)
 321 +#define QCA953X_PLL_CLK_CTRL_AHB_PLL_BYPASS            BIT(4)
 322 +#define QCA953X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT                5
 323 +#define QCA953X_PLL_CLK_CTRL_CPU_POST_DIV_MASK         0x1f
 324 +#define QCA953X_PLL_CLK_CTRL_DDR_POST_DIV_SHIFT                10
 325 +#define QCA953X_PLL_CLK_CTRL_DDR_POST_DIV_MASK         0x1f
 326 +#define QCA953X_PLL_CLK_CTRL_AHB_POST_DIV_SHIFT                15
 327 +#define QCA953X_PLL_CLK_CTRL_AHB_POST_DIV_MASK         0x1f
 328 +#define QCA953X_PLL_CLK_CTRL_CPUCLK_FROM_CPUPLL                BIT(20)
 329 +#define QCA953X_PLL_CLK_CTRL_DDRCLK_FROM_DDRPLL                BIT(21)
 330 +#define QCA953X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL                BIT(24)
 331 +
 332  #define QCA955X_PLL_CPU_CONFIG_REG             0x00
 333  #define QCA955X_PLL_DDR_CONFIG_REG             0x04
 334  #define QCA955X_PLL_CLK_CTRL_REG               0x08
 335 @@ -356,6 +396,10 @@
 336  #define AR934X_RESET_REG_BOOTSTRAP             0xb0
 337  #define AR934X_RESET_REG_PCIE_WMAC_INT_STATUS  0xac
 338
 339 +#define QCA953X_RESET_REG_RESET_MODULE         0x1c
 340 +#define QCA953X_RESET_REG_BOOTSTRAP            0xb0
 341 +#define QCA953X_RESET_REG_EXT_INT_STATUS       0xac
 342 +
 343  #define QCA955X_RESET_REG_RESET_MODULE         0x1c
 344  #define QCA955X_RESET_REG_BOOTSTRAP            0xb0
 345  #define QCA955X_RESET_REG_EXT_INT_STATUS       0xac
 346 @@ -504,6 +548,8 @@
 347  #define AR934X_BOOTSTRAP_SDRAM_DISABLED BIT(1)
 348  #define AR934X_BOOTSTRAP_DDR1          BIT(0)
 349
 350 +#define QCA953X_BOOTSTRAP_REF_CLK_40   BIT(4)
 351 +
 352  #define QCA955X_BOOTSTRAP_REF_CLK_40   BIT(4)
 353
 354  #define AR934X_PCIE_WMAC_INT_WMAC_MISC         BIT(0)
 355 @@ -566,6 +612,7 @@
 356  #define REV_ID_MAJOR_AR9341            0x0120
 357  #define REV_ID_MAJOR_AR9342            0x1120
 358  #define REV_ID_MAJOR_AR9344            0x2120
 359 +#define REV_ID_MAJOR_QCA9533           0x0140
 360  #define REV_ID_MAJOR_QCA9556           0x0130
 361  #define REV_ID_MAJOR_QCA9558           0x1130
 362
 363 @@ -588,6 +635,8 @@
 364
 365  #define AR934X_REV_ID_REVISION_MASK    0xf
 366
 367 +#define QCA953X_REV_ID_REVISION_MASK   0xf
 368 +
 369  #define QCA955X_REV_ID_REVISION_MASK   0xf
 370
 371  /*
 372 @@ -641,6 +690,7 @@
 373  #define AR913X_GPIO_COUNT              22
 374  #define AR933X_GPIO_COUNT              30
 375  #define AR934X_GPIO_COUNT              23
 376 +#define QCA953X_GPIO_COUNT             24
 377  #define QCA955X_GPIO_COUNT             24
 378
 379  /*
 380 --- a/arch/mips/include/asm/mach-ath79/ath79.h
 381 +++ b/arch/mips/include/asm/mach-ath79/ath79.h
 382 @@ -32,6 +32,7 @@ enum ath79_soc_type {
 383         ATH79_SOC_AR9341,
 384         ATH79_SOC_AR9342,
 385         ATH79_SOC_AR9344,
 386 +       ATH79_SOC_QCA9533,
 387         ATH79_SOC_QCA9556,
 388         ATH79_SOC_QCA9558,
 389  };
 390 @@ -100,6 +101,16 @@ static inline int soc_is_ar934x(void)
 391         return soc_is_ar9341() || soc_is_ar9342() || soc_is_ar9344();
 392  }
 393
 394 +static inline int soc_is_qca9533(void)
 395 +{
 396 +       return ath79_soc == ATH79_SOC_QCA9533;
 397 +}
 398 +
 399 +static inline int soc_is_qca953x(void)
 400 +{
 401 +       return soc_is_qca9533();
 402 +}
 403 +
 404  static inline int soc_is_qca9556(void)
 405  {
 406         return ath79_soc == ATH79_SOC_QCA9556;