--- /dev/null
+/*
+ * Copyright (C) 2012 Gateworks Corporation
+ * Chris Lang <clang@gateworks.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include <linux/linkage.h>
+#include <asm/assembler.h>
+#include <asm/asm-offsets.h>
+
+#define D_CACHE_LINE_SIZE 32
+
+ .text
+
+/*
+ * R8 - DMA Start Address
+ * R9 - DMA Length
+ * R10 - DMA Direction
+ * R11 - DMA type
+ * R12 - fiq_buffer Address
+ * R13 - DMA type Address
+*/
+
+ .global cns3xxx_fiq_end
+ENTRY(cns3xxx_fiq_start)
+ mov r8, #0
+ str r8, [r13]
+
+ ldr r9, [r12]
+ ldr r8, [r9]
+ add r8, r8, #1
+ str r8, [r9]
+
+ ldmib r12, {r8, r9, r10}
+ and r11, r10, #0x3000000
+ and r10, r10, #0xff
+
+ teq r11, #0x1000000
+ beq cns3xxx_dma_map_area
+ teq r11, #0x2000000
+ beq cns3xxx_dma_unmap_area
+ b cns3xxx_dma_flush_range
+
+cns3xxx_fiq_exit:
+ mov r8, #0
+ str r8, [r12, #12]
+ mcr p15, 0, r8, c7, c10, 4 @ drain write buffer
+ subs pc, lr, #4
+
+cns3xxx_dma_map_area:
+ add r9, r9, r8
+ teq r10, #DMA_FROM_DEVICE
+ beq cns3xxx_dma_inv_range
+ b cns3xxx_dma_clean_range
+
+cns3xxx_dma_unmap_area:
+ add r9, r9, r8
+ teq r10, #DMA_TO_DEVICE
+ bne cns3xxx_dma_inv_range
+ b cns3xxx_fiq_exit
+
+cns3xxx_dma_flush_range:
+ bic r8, r8, #D_CACHE_LINE_SIZE - 1
+1:
+ mcr p15, 0, r8, c7, c14, 1 @ clean & invalidate D line
+ add r8, r8, #D_CACHE_LINE_SIZE
+ cmp r8, r9
+ blo 1b
+ b cns3xxx_fiq_exit
+
+cns3xxx_dma_clean_range:
+ bic r8, r8, #D_CACHE_LINE_SIZE - 1
+1:
+ mcr p15, 0, r8, c7, c10, 1 @ clean D line
+ add r8, r8, #D_CACHE_LINE_SIZE
+ cmp r8, r9
+ blo 1b
+ b cns3xxx_fiq_exit
+
+cns3xxx_dma_inv_range:
+ tst r8, #D_CACHE_LINE_SIZE - 1
+ bic r8, r8, #D_CACHE_LINE_SIZE - 1
+ mcrne p15, 0, r8, c7, c10, 1 @ clean D line
+ tst r9, #D_CACHE_LINE_SIZE - 1
+ bic r9, r9, #D_CACHE_LINE_SIZE - 1
+ mcrne p15, 0, r9, c7, c14, 1 @ clean & invalidate D line
+1:
+ mcr p15, 0, r8, c7, c6, 1 @ invalidate D line
+ add r8, r8, #D_CACHE_LINE_SIZE
+ cmp r8, r9
+ blo 1b
+ b cns3xxx_fiq_exit
+
+cns3xxx_fiq_end:
--- /dev/null
+/*
+ * Copyright 2012 Gateworks Corporation
+ * Chris Lang <clang@gateworks.com>
+ * Tim Harvey <tharvey@gateworks.com>
+ *
+ * This file is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License, Version 2, as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/interrupt.h>
+#include <linux/io.h>
+#include <linux/gpio.h>
+#include <linux/irq.h>
+
+#include <asm/mach/irq.h>
+
+/*
+ * Registers
+ */
+#define GPIO_INPUT 0x04
+#define GPIO_DIR 0x08
+#define GPIO_SET 0x10
+#define GPIO_CLEAR 0x14
+#define GPIO_INTERRUPT_ENABLE 0x20
+#define GPIO_INTERRUPT_RAW_STATUS 0x24
+#define GPIO_INTERRUPT_MASKED_STATUS 0x28
+#define GPIO_INTERRUPT_MASK 0x2C
+#define GPIO_INTERRUPT_CLEAR 0x30
+#define GPIO_INTERRUPT_TRIGGER_METHOD 0x34
+#define GPIO_INTERRUPT_TRIGGER_BOTH_EDGES 0x38
+#define GPIO_INTERRUPT_TRIGGER_TYPE 0x3C
+
+#define GPIO_INTERRUPT_TRIGGER_METHOD_EDGE 0
+#define GPIO_INTERRUPT_TRIGGER_METHOD_LEVEL 1
+#define GPIO_INTERRUPT_TRIGGER_EDGE_SINGLE 0
+#define GPIO_INTERRUPT_TRIGGER_EDGE_BOTH 1
+#define GPIO_INTERRUPT_TRIGGER_TYPE_RISING 0
+#define GPIO_INTERRUPT_TRIGGER_TYPE_FALLING 1
+#define GPIO_INTERRUPT_TRIGGER_TYPE_HIGH 0
+#define GPIO_INTERRUPT_TRIGGER_TYPE_LOW 1
+
+struct cns3xxx_gpio_chip {
+ struct gpio_chip chip;
+ spinlock_t lock;
+ void __iomem *base;
+ int secondary_irq_base;
+};
+
+static struct cns3xxx_gpio_chip cns3xxx_gpio_chips[2];
+static int cns3xxx_gpio_chip_count;
+
+static inline void
+__set_direction(struct cns3xxx_gpio_chip *cchip, unsigned pin, int input)
+{
+ u32 reg;
+
+ reg = __raw_readl(cchip->base + GPIO_DIR);
+ if (input)
+ reg |= 1 << pin;
+ else
+ reg &= !(1 << pin);
+ __raw_writel(reg, cchip->base + GPIO_DIR);
+}
+
+/*
+ * GENERIC_GPIO primatives
+ */
+static int cns3xxx_gpio_direction_input(struct gpio_chip *chip, unsigned pin)
+{
+ struct cns3xxx_gpio_chip *cchip =
+ container_of(chip, struct cns3xxx_gpio_chip, chip);
+ unsigned long flags;
+
+ spin_lock_irqsave(&cchip->lock, flags);
+ __set_direction(cchip, pin, 1);
+ spin_unlock_irqrestore(&cchip->lock, flags);
+
+ return 0;
+}
+
+static int cns3xxx_gpio_get(struct gpio_chip *chip, unsigned pin)
+{
+ struct cns3xxx_gpio_chip *cchip =
+ container_of(chip, struct cns3xxx_gpio_chip, chip);
+ int val;
+
+ val = ((__raw_readl(cchip->base + GPIO_INPUT) >> pin) & 0x1);
+
+ return val;
+}
+
+static int cns3xxx_gpio_direction_output(struct gpio_chip *chip, unsigned pin, int level)
+{
+ struct cns3xxx_gpio_chip *cchip =
+ container_of(chip, struct cns3xxx_gpio_chip, chip);
+ unsigned long flags;
+
+ spin_lock_irqsave(&cchip->lock, flags);
+ if (level)
+ __raw_writel(1 << pin, cchip->base + GPIO_SET);
+ else
+ __raw_writel(1 << pin, cchip->base + GPIO_CLEAR);
+ __set_direction(cchip, pin, 0);
+ spin_unlock_irqrestore(&cchip->lock, flags);
+
+ return 0;
+}
+
+static void cns3xxx_gpio_set(struct gpio_chip *chip, unsigned pin,
+ int level)
+{
+ struct cns3xxx_gpio_chip *cchip =
+ container_of(chip, struct cns3xxx_gpio_chip, chip);
+
+ if (level)
+ __raw_writel(1 << pin, cchip->base + GPIO_SET);
+ else
+ __raw_writel(1 << pin, cchip->base + GPIO_CLEAR);
+}
+
+static int cns3xxx_gpio_to_irq(struct gpio_chip *chip, unsigned pin)
+{
+ struct cns3xxx_gpio_chip *cchip =
+ container_of(chip, struct cns3xxx_gpio_chip, chip);
+
+ return cchip->secondary_irq_base + pin;
+}
+
+
+/*
+ * IRQ support
+ */
+
+/* one interrupt per GPIO controller (GPIOA/GPIOB)
+ * this is called in task context, with IRQs enabled
+ */
+static void cns3xxx_gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
+{
+ struct cns3xxx_gpio_chip *cchip = irq_get_handler_data(irq);
+ struct irq_chip *chip = irq_get_chip(irq);
+ struct irq_chip_generic *gc = irq_desc_get_chip_data(desc);
+ struct irq_chip_type *ct = gc->chip_types;
+ u16 i;
+ u32 reg;
+
+ chained_irq_enter(chip, desc); /* mask and ack the base interrupt */
+
+ /* see which pin(s) triggered the interrupt */
+ reg = __raw_readl(cchip->base + GPIO_INTERRUPT_RAW_STATUS);
+ for (i = 0; i < 32; i++) {
+ if (reg & (1 << i)) {
+ /* let the generic IRQ layer handle an interrupt */
+ generic_handle_irq(cchip->secondary_irq_base + i);
+ }
+ }
+
+ chained_irq_exit(chip, desc); /* unmask the base interrupt */
+}
+
+static int cns3xxx_gpio_irq_set_type(struct irq_data *d, u32 irqtype)
+{
+ struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
+ struct cns3xxx_gpio_chip *cchip = gc->private;
+ u32 gpio = d->irq - cchip->secondary_irq_base;
+ unsigned long flags;
+ u32 method, edges, type;
+
+ spin_lock_irqsave(&cchip->lock, flags);
+ method = __raw_readl(cchip->base + GPIO_INTERRUPT_TRIGGER_METHOD);
+ edges = __raw_readl(cchip->base + GPIO_INTERRUPT_TRIGGER_BOTH_EDGES);
+ type = __raw_readl(cchip->base + GPIO_INTERRUPT_TRIGGER_TYPE);
+ method &= ~(1 << gpio);
+ edges &= ~(1 << gpio);
+ type &= ~(1 << gpio);
+
+ switch(irqtype) {
+ case IRQ_TYPE_EDGE_RISING:
+ method |= (GPIO_INTERRUPT_TRIGGER_METHOD_EDGE << gpio);
+ edges |= (GPIO_INTERRUPT_TRIGGER_EDGE_SINGLE << gpio);
+ type |= (GPIO_INTERRUPT_TRIGGER_TYPE_RISING << gpio);
+ break;
+ case IRQ_TYPE_EDGE_FALLING:
+ method |= (GPIO_INTERRUPT_TRIGGER_METHOD_EDGE << gpio);
+ edges |= (GPIO_INTERRUPT_TRIGGER_EDGE_SINGLE << gpio);
+ type |= (GPIO_INTERRUPT_TRIGGER_TYPE_FALLING << gpio);
+ break;
+ case IRQ_TYPE_EDGE_BOTH:
+ method |= (GPIO_INTERRUPT_TRIGGER_METHOD_EDGE << gpio);
+ edges |= (GPIO_INTERRUPT_TRIGGER_EDGE_BOTH << gpio);
+ break;
+ case IRQ_TYPE_LEVEL_LOW:
+ method |= (GPIO_INTERRUPT_TRIGGER_METHOD_LEVEL << gpio);
+ type |= (GPIO_INTERRUPT_TRIGGER_TYPE_LOW << gpio);
+ break;
+ case IRQ_TYPE_LEVEL_HIGH:
+ method |= (GPIO_INTERRUPT_TRIGGER_METHOD_LEVEL << gpio);
+ type |= (GPIO_INTERRUPT_TRIGGER_TYPE_HIGH << gpio);
+ break;
+ default:
+ printk(KERN_WARNING "No irq type\n");
+ spin_unlock_irqrestore(&cchip->lock, flags);
+ return -EINVAL;
+ }
+
+ __raw_writel(method, cchip->base + GPIO_INTERRUPT_TRIGGER_METHOD);
+ __raw_writel(edges, cchip->base + GPIO_INTERRUPT_TRIGGER_BOTH_EDGES);
+ __raw_writel(type, cchip->base + GPIO_INTERRUPT_TRIGGER_TYPE);
+ spin_unlock_irqrestore(&cchip->lock, flags);
+
+ if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH))
+ __irq_set_handler_locked(d->irq, handle_level_irq);
+ else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
+ __irq_set_handler_locked(d->irq, handle_edge_irq);
+
+ return 0;
+}
+
+void __init cns3xxx_gpio_init(int gpio_base, int ngpio,
+ u32 base, int irq, int secondary_irq_base)
+{
+ struct cns3xxx_gpio_chip *cchip;
+ struct irq_chip_generic *gc;
+ struct irq_chip_type *ct;
+ char gc_label[16];
+
+ if (cns3xxx_gpio_chip_count == ARRAY_SIZE(cns3xxx_gpio_chips))
+ return;
+
+ snprintf(gc_label, sizeof(gc_label), "cns3xxx_gpio%d",
+ cns3xxx_gpio_chip_count);
+
+ cchip = cns3xxx_gpio_chips + cns3xxx_gpio_chip_count;
+ cchip->chip.label = kstrdup(gc_label, GFP_KERNEL);
+ cchip->chip.direction_input = cns3xxx_gpio_direction_input;
+ cchip->chip.get = cns3xxx_gpio_get;
+ cchip->chip.direction_output = cns3xxx_gpio_direction_output;
+ cchip->chip.set = cns3xxx_gpio_set;
+ cchip->chip.to_irq = cns3xxx_gpio_to_irq;
+ cchip->chip.base = gpio_base;
+ cchip->chip.ngpio = ngpio;
+ cchip->chip.can_sleep = 0;
+ spin_lock_init(&cchip->lock);
+ cchip->base = (void __iomem *)base;
+ cchip->secondary_irq_base = secondary_irq_base;
+
+ BUG_ON(gpiochip_add(&cchip->chip) < 0);
+ cns3xxx_gpio_chip_count++;
+
+ /* clear GPIO interrupts */
+ __raw_writel(0xffff, cchip->base + GPIO_INTERRUPT_CLEAR);
+
+ /*
+ * IRQ chip init
+ */
+ gc = irq_alloc_generic_chip("cns3xxx_gpio_irq", 1, secondary_irq_base,
+ cchip->base, handle_edge_irq);
+ gc->private = cchip;
+
+ ct = gc->chip_types;
+ ct->type = IRQ_TYPE_EDGE_FALLING;
+ ct->regs.ack = GPIO_INTERRUPT_CLEAR;
+ ct->regs.enable = GPIO_INTERRUPT_ENABLE;
+ ct->chip.irq_ack = irq_gc_ack_set_bit;
+ ct->chip.irq_enable = irq_gc_unmask_enable_reg;
+ ct->chip.irq_disable = irq_gc_mask_disable_reg;
+ ct->chip.irq_set_type = cns3xxx_gpio_irq_set_type;
+ ct->handler = handle_edge_irq;
+
+ irq_setup_generic_chip(gc, IRQ_MSK(ngpio), IRQ_GC_INIT_MASK_CACHE,
+ IRQ_NOREQUEST, 0);
+
+ irq_set_chained_handler(irq, cns3xxx_gpio_irq_handler);
+ irq_set_handler_data(irq, cchip);
+}
--- /dev/null
+/*
+ * linux/arch/arm/mach-cns3xxx/headsmp.S
+ *
+ * Cloned from linux/arch/arm/plat-versatile/headsmp.S
+ *
+ * Copyright (c) 2003 ARM Limited
+ * All Rights Reserved
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include <linux/linkage.h>
+#include <linux/init.h>
+
+ __INIT
+
+/*
+ * CNS3XXX specific entry point for secondary CPUs. This provides
+ * a "holding pen" into which all secondary cores are held until we're
+ * ready for them to initialise.
+ */
+ENTRY(cns3xxx_secondary_startup)
+ mrc p15, 0, r0, c0, c0, 5
+ and r0, r0, #15
+ adr r4, 1f
+ ldmia r4, {r5, r6}
+ sub r4, r4, r5
+ add r6, r6, r4
+pen: ldr r7, [r6]
+ cmp r7, r0
+ bne pen
+
+ /*
+ * we've been released from the holding pen: secondary_stack
+ * should now contain the SVC stack for this core
+ */
+ b secondary_startup
+
+ .align
+1: .long .
+ .long pen_release
--- /dev/null
+/* linux arch/arm/mach-cns3xxx/hotplug.c
+ *
+ * Cloned from linux/arch/arm/mach-realview/hotplug.c
+ *
+ * Copyright (C) 2002 ARM Ltd.
+ * All Rights Reserved
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/kernel.h>
+#include <linux/errno.h>
+#include <linux/smp.h>
+
+#include <asm/cacheflush.h>
+
+extern volatile int pen_release;
+
+static inline void cpu_enter_lowpower(void)
+{
+ unsigned int v;
+
+ flush_cache_all();
+ asm volatile(
+ " mcr p15, 0, %1, c7, c5, 0\n"
+ " mcr p15, 0, %1, c7, c10, 4\n"
+ /*
+ * Turn off coherency
+ */
+ " mrc p15, 0, %0, c1, c0, 1\n"
+ " bic %0, %0, %3\n"
+ " mcr p15, 0, %0, c1, c0, 1\n"
+ " mrc p15, 0, %0, c1, c0, 0\n"
+ " bic %0, %0, %2\n"
+ " mcr p15, 0, %0, c1, c0, 0\n"
+ : "=&r" (v)
+ : "r" (0), "Ir" (CR_C), "Ir" (0x40)
+ : "cc");
+}
+
+static inline void cpu_leave_lowpower(void)
+{
+ unsigned int v;
+
+ asm volatile(
+ "mrc p15, 0, %0, c1, c0, 0\n"
+ " orr %0, %0, %1\n"
+ " mcr p15, 0, %0, c1, c0, 0\n"
+ " mrc p15, 0, %0, c1, c0, 1\n"
+ " orr %0, %0, %2\n"
+ " mcr p15, 0, %0, c1, c0, 1\n"
+ : "=&r" (v)
+ : "Ir" (CR_C), "Ir" (0x40)
+ : "cc");
+}
+
+static inline void platform_do_lowpower(unsigned int cpu, int *spurious)
+{
+ /*
+ * there is no power-control hardware on this platform, so all
+ * we can do is put the core into WFI; this is safe as the calling
+ * code will have already disabled interrupts
+ */
+ for (;;) {
+ /*
+ * here's the WFI
+ */
+ asm(".word 0xe320f003\n"
+ :
+ :
+ : "memory", "cc");
+
+ if (pen_release == cpu) {
+ /*
+ * OK, proper wakeup, we're done
+ */
+ break;
+ }
+
+ /*
+ * Getting here, means that we have come out of WFI without
+ * having been woken up - this shouldn't happen
+ *
+ * Just note it happening - when we're woken, we can report
+ * its occurrence.
+ */
+ (*spurious)++;
+ }
+}
+
+int platform_cpu_kill(unsigned int cpu)
+{
+ return 1;
+}
+
+/*
+ * platform-specific code to shutdown a CPU
+ *
+ * Called with IRQs disabled
+ */
+void platform_cpu_die(unsigned int cpu)
+{
+ int spurious = 0;
+
+ /*
+ * we're ready for shutdown now, so do it
+ */
+ cpu_enter_lowpower();
+ platform_do_lowpower(cpu, &spurious);
+
+ /*
+ * bring this CPU back into the world of cache
+ * coherency, and then restore interrupts
+ */
+ cpu_leave_lowpower();
+
+ if (spurious)
+ pr_warn("CPU%u: %u spurious wakeup calls\n", cpu, spurious);
+}
+
+int platform_cpu_disable(unsigned int cpu)
+{
+ /*
+ * we don't allow CPU 0 to be shutdown (it is still too special
+ * e.g. clock tick interrupts)
+ */
+ return cpu == 0 ? -EPERM : 0;
+}
--- /dev/null
+/*
+ * arch/arm/mach-cns3xxx/include/mach/gpio.h
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ *
+ */
+#ifndef __ASM_ARCH_CNS3XXX_GPIO_H
+#define __ASM_ARCH_CNS3XXX_GPIO_H
+
+#include <linux/kernel.h>
+
+extern void __init cns3xxx_gpio_init(int gpio_base, int ngpio,
+ u32 base, int irq, int secondary_irq_base);
+
+#endif
--- /dev/null
+/*
+ * arch/arm/mach-cns3xxx/include/mach/platform.h
+ *
+ * Copyright 2011 Gateworks Corporation
+ * Chris Lang <clang@gateworks.com
+ *
+ * This file is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License, Version 2, as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#ifndef __ASM_ARCH_PLATFORM_H
+#define __ASM_ARCH_PLATFORM_H
+
+#ifndef __ASSEMBLY__
+
+/* Information about built-in Ethernet MAC interfaces */
+struct cns3xxx_plat_info {
+ u8 ports; /* Bitmap of enabled Ports */
+ u8 hwaddr[4][6];
+ u32 phy[3];
+};
+
+#endif /* __ASM_ARCH_PLATFORM_H */
+#endif
--- /dev/null
+#ifndef __MACH_SMP_H
+#define __MACH_SMP_H
+
+extern void smp_dma_map_area(const void *, size_t, int);
+extern void smp_dma_unmap_area(const void *, size_t, int);
+extern void smp_dma_flush_range(const void *, const void *);
+
+#endif
--- /dev/null
+/*
+ * Gateworks Corporation Laguna Platform
+ *
+ * Copyright 2000 Deep Blue Solutions Ltd
+ * Copyright 2008 ARM Limited
+ * Copyright 2008 Cavium Networks
+ * Scott Shu
+ * Copyright 2010 MontaVista Software, LLC.
+ * Anton Vorontsov <avorontsov@mvista.com>
+ * Copyright 2011 Gateworks Corporation
+ * Chris Lang <clang@gateworks.com>
+ * Copyright 2012 Gateworks Corporation
+ * Tim Harvey <tharvey@gateworks.com>
+ *
+ * This file is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License, Version 2, as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/compiler.h>
+#include <linux/io.h>
+#include <linux/gpio.h>
+#include <linux/dma-mapping.h>
+#include <linux/serial_core.h>
+#include <linux/serial_8250.h>
+#include <linux/platform_device.h>
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/physmap.h>
+#include <linux/mtd/partitions.h>
+#include <linux/leds.h>
+#include <linux/i2c.h>
+#include <linux/i2c/at24.h>
+#include <linux/i2c/pca953x.h>
+#include <linux/spi/spi.h>
+#include <linux/spi/flash.h>
+#include <linux/if_ether.h>
+#include <asm/setup.h>
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/map.h>
+#include <asm/mach/time.h>
+#include <mach/cns3xxx.h>
+#include <mach/irqs.h>
+#include <mach/platform.h>
+#include <mach/pm.h>
+#include <mach/gpio.h>
+#include <asm/hardware/gic.h>
+#include "core.h"
+#include "devices.h"
+
+#define ARRAY_AND_SIZE(x) (x), ARRAY_SIZE(x)
+
+// Config 1 Bitmap
+#define ETH0_LOAD BIT(0)
+#define ETH1_LOAD BIT(1)
+#define ETH2_LOAD BIT(2)
+#define SATA0_LOAD BIT(3)
+#define SATA1_LOAD BIT(4)
+#define PCM_LOAD BIT(5)
+#define I2S_LOAD BIT(6)
+#define SPI0_LOAD BIT(7)
+#define SPI1_LOAD BIT(8)
+#define PCIE0_LOAD BIT(9)
+#define PCIE1_LOAD BIT(10)
+#define USB0_LOAD BIT(11)
+#define USB1_LOAD BIT(12)
+#define USB1_ROUTE BIT(13)
+#define SD_LOAD BIT(14)
+#define UART0_LOAD BIT(15)
+#define UART1_LOAD BIT(16)
+#define UART2_LOAD BIT(17)
+#define MPCI0_LOAD BIT(18)
+#define MPCI1_LOAD BIT(19)
+#define MPCI2_LOAD BIT(20)
+#define MPCI3_LOAD BIT(21)
+#define FP_BUT_LOAD BIT(22)
+#define FP_BUT_HEADER_LOAD BIT(23)
+#define FP_LED_LOAD BIT(24)
+#define FP_LED_HEADER_LOAD BIT(25)
+#define FP_TAMPER_LOAD BIT(26)
+#define HEADER_33V_LOAD BIT(27)
+#define SATA_POWER_LOAD BIT(28)
+#define FP_POWER_LOAD BIT(29)
+#define GPIO_HEADER_LOAD BIT(30)
+#define GSP_BAT_LOAD BIT(31)
+
+// Config 2 Bitmap
+#define FAN_LOAD BIT(0)
+#define SPI_FLASH_LOAD BIT(1)
+#define NOR_FLASH_LOAD BIT(2)
+#define GPS_LOAD BIT(3)
+#define SUPPLY_5V_LOAD BIT(6)
+#define SUPPLY_33V_LOAD BIT(7)
+
+struct laguna_board_info {
+ char model[16];
+ u32 config_bitmap;
+ u32 config2_bitmap;
+ u8 nor_flash_size;
+ u8 spi_flash_size;
+};
+
+static struct laguna_board_info laguna_info __initdata;
+
+/*
+ * NOR Flash
+ */
+static struct mtd_partition laguna_nor_partitions[] = {
+ {
+ .name = "uboot",
+ .size = SZ_256K,
+ .offset = 0,
+ .mask_flags = MTD_WRITEABLE,
+ }, {
+ .name = "params",
+ .size = SZ_128K,
+ .offset = SZ_256K,
+ }, {
+ .name = "kernel",
+ .size = SZ_2M,
+ .offset = SZ_256K + SZ_128K,
+ }, {
+ .name = "rootfs",
+ .size = SZ_16M - SZ_256K - SZ_128K - SZ_2M,
+ .offset = SZ_256K + SZ_128K + SZ_2M,
+ },
+};
+
+static struct physmap_flash_data laguna_nor_pdata = {
+ .width = 2,
+ .parts = laguna_nor_partitions,
+ .nr_parts = ARRAY_SIZE(laguna_nor_partitions),
+};
+
+static struct resource laguna_nor_res = {
+ .start = CNS3XXX_FLASH_BASE,
+ .end = CNS3XXX_FLASH_BASE + SZ_128M - 1,
+ .flags = IORESOURCE_MEM | IORESOURCE_MEM_32BIT,
+};
+
+static struct platform_device laguna_nor_pdev = {
+ .name = "physmap-flash",
+ .id = 0,
+ .resource = &laguna_nor_res,
+ .num_resources = 1,
+ .dev = {
+ .platform_data = &laguna_nor_pdata,
+ },
+};
+
+/*
+ * SPI
+ */
+static struct mtd_partition laguna_spi_partitions[] = {
+ {
+ .name = "uboot",
+ .size = SZ_256K,
+ .offset = 0,
+ .mask_flags = MTD_WRITEABLE,
+ }, {
+ .name = "params",
+ .size = SZ_256K,
+ .offset = SZ_256K,
+ }, {
+ .name = "kernel",
+ .size = SZ_1M + SZ_512K,
+ .offset = SZ_512K,
+ }, {
+ .name = "rootfs",
+ .size = SZ_16M - SZ_2M,
+ .offset = SZ_2M,
+ },
+};
+
+static struct flash_platform_data laguna_spi_pdata = {
+ .parts = laguna_spi_partitions,
+ .nr_parts = ARRAY_SIZE(laguna_spi_partitions),
+};
+
+static struct spi_board_info __initdata laguna_spi_devices[] = {
+ {
+ .modalias = "m25p80",
+ .platform_data = &laguna_spi_pdata,
+ .max_speed_hz = 50000000,
+ .bus_num = 1,
+ .chip_select = 0,
+ },
+};
+
+static struct platform_device laguna_spi_controller = {
+ .name = "cns3xxx_spi",
+};
+
+/*
+ * LED's
+ */
+static struct gpio_led laguna_gpio_leds[] = {
+ {
+ .name = "user1", /* Green Led */
+ .gpio = 115,
+ .active_low = 1,
+ },{
+ .name = "user2", /* Red Led */
+ .gpio = 114,
+ .active_low = 1,
+ },{
+ .name = "pwr1", /* Green Led */
+ .gpio = 116,
+ .active_low = 1,
+ },{
+ .name = "pwr2", /* Yellow Led */
+ .gpio = 117,
+ .active_low = 1,
+ },{
+ .name = "txd1", /* Green Led */
+ .gpio = 118,
+ .active_low = 1,
+ },{
+ .name = "txd2", /* Yellow Led */
+ .gpio = 119,
+ .active_low = 1,
+ },{
+ .name = "rxd1", /* Green Led */
+ .gpio = 120,
+ .active_low = 1,
+ },{
+ .name = "rxd2", /* Yellow Led */
+ .gpio = 121,
+ .active_low = 1,
+ },{
+ .name = "ser1", /* Green Led */
+ .gpio = 122,
+ .active_low = 1,
+ },{
+ .name = "ser2", /* Yellow Led */
+ .gpio = 123,
+ .active_low = 1,
+ },{
+ .name = "enet1", /* Green Led */
+ .gpio = 124,
+ .active_low = 1,
+ },{
+ .name = "enet2", /* Yellow Led */
+ .gpio = 125,
+ .active_low = 1,
+ },{
+ .name = "sig1_1", /* Green Led */
+ .gpio = 126,
+ .active_low = 1,
+ },{
+ .name = "sig1_2", /* Yellow Led */
+ .gpio = 127,
+ .active_low = 1,
+ },{
+ .name = "sig2_1", /* Green Led */
+ .gpio = 128,
+ .active_low = 1,
+ },{
+ .name = "sig2_2", /* Yellow Led */
+ .gpio = 129,
+ .active_low = 1,
+ },{
+ .name = "sig3_1", /* Green Led */
+ .gpio = 130,
+ .active_low = 1,
+ },{
+ .name = "sig3_2", /* Yellow Led */
+ .gpio = 131,
+ .active_low = 1,
+ },{
+ .name = "net1", /*Green Led */
+ .gpio = 109,
+ .active_low = 1,
+ },{
+ .name = "net2", /* Red Led */
+ .gpio = 110,
+ .active_low = 1,
+ },{
+ .name = "mod1", /* Green Led */
+ .gpio = 111,
+ .active_low = 1,
+ },{
+ .name = "mod2", /* Red Led */
+ .gpio = 112,
+ .active_low = 1,
+ },
+};
+
+static struct gpio_led_platform_data laguna_gpio_leds_data = {
+ .num_leds = 22,
+ .leds = laguna_gpio_leds,
+};
+
+static struct platform_device laguna_gpio_leds_device = {
+ .name = "leds-gpio",
+ .id = -1,
+ .dev.platform_data = &laguna_gpio_leds_data,
+};
+
+/*
+ * Ethernet
+ */
+static struct cns3xxx_plat_info laguna_net_data = {
+ .ports = 0,
+ .phy = {
+ 0,
+ 1,
+ 2,
+ },
+};
+
+static struct platform_device laguna_net_device = {
+ .name = "cns3xxx_eth",
+ .id = 0,
+ .dev.platform_data = &laguna_net_data,
+};
+
+/*
+ * UART
+ */
+static void __init laguna_early_serial_setup(void)
+{
+#ifdef CONFIG_SERIAL_8250_CONSOLE
+ static struct uart_port laguna_serial_port = {
+ .membase = (void __iomem *)CNS3XXX_UART0_BASE_VIRT,
+ .mapbase = CNS3XXX_UART0_BASE,
+ .irq = IRQ_CNS3XXX_UART0,
+ .iotype = UPIO_MEM,
+ .flags = UPF_BOOT_AUTOCONF | UPF_FIXED_TYPE,
+ .regshift = 2,
+ .uartclk = 24000000,
+ .line = 0,
+ .type = PORT_16550A,
+ .fifosize = 16,
+ };
+
+ early_serial_setup(&laguna_serial_port);
+#endif
+}
+
+static struct resource laguna_uart_resources[] = {
+ {
+ .start = CNS3XXX_UART0_BASE,
+ .end = CNS3XXX_UART0_BASE + SZ_4K - 1,
+ .flags = IORESOURCE_MEM
+ },{
+ .start = CNS3XXX_UART2_BASE,
+ .end = CNS3XXX_UART2_BASE + SZ_4K - 1,
+ .flags = IORESOURCE_MEM
+ },{
+ .start = CNS3XXX_UART2_BASE,
+ .end = CNS3XXX_UART2_BASE + SZ_4K - 1,
+ .flags = IORESOURCE_MEM
+ },
+};
+
+static struct plat_serial8250_port laguna_uart_data[] = {
+ {
+ .membase = (char*) (CNS3XXX_UART0_BASE_VIRT),
+ .mapbase = (CNS3XXX_UART0_BASE),
+ .irq = IRQ_CNS3XXX_UART0,
+ .iotype = UPIO_MEM,
+ .flags = UPF_BOOT_AUTOCONF | UPF_FIXED_TYPE | UPF_NO_TXEN_TEST,
+ .regshift = 2,
+ .uartclk = 24000000,
+ .type = PORT_16550A,
+ },{
+ .membase = (char*) (CNS3XXX_UART1_BASE_VIRT),
+ .mapbase = (CNS3XXX_UART1_BASE),
+ .irq = IRQ_CNS3XXX_UART1,
+ .iotype = UPIO_MEM,
+ .flags = UPF_BOOT_AUTOCONF | UPF_FIXED_TYPE | UPF_NO_TXEN_TEST,
+ .regshift = 2,
+ .uartclk = 24000000,
+ .type = PORT_16550A,
+ },{
+ .membase = (char*) (CNS3XXX_UART2_BASE_VIRT),
+ .mapbase = (CNS3XXX_UART2_BASE),
+ .irq = IRQ_CNS3XXX_UART2,
+ .iotype = UPIO_MEM,
+ .flags = UPF_BOOT_AUTOCONF | UPF_FIXED_TYPE | UPF_NO_TXEN_TEST,
+ .regshift = 2,
+ .uartclk = 24000000,
+ .type = PORT_16550A,
+ },
+ { },
+};
+
+static struct platform_device laguna_uart = {
+ .name = "serial8250",
+ .id = PLAT8250_DEV_PLATFORM,
+ .dev.platform_data = laguna_uart_data,
+ .num_resources = 3,
+ .resource = laguna_uart_resources
+};
+
+/*
+ * USB
+ */
+static struct resource cns3xxx_usb_ehci_resources[] = {
+ [0] = {
+ .start = CNS3XXX_USB_BASE,
+ .end = CNS3XXX_USB_BASE + SZ_16M - 1,
+ .flags = IORESOURCE_MEM,
+ },
+ [1] = {
+ .start = IRQ_CNS3XXX_USB_EHCI,
+ .flags = IORESOURCE_IRQ,
+ },
+};
+
+static u64 cns3xxx_usb_ehci_dma_mask = DMA_BIT_MASK(32);
+
+static struct platform_device cns3xxx_usb_ehci_device = {
+ .name = "cns3xxx-ehci",
+ .num_resources = ARRAY_SIZE(cns3xxx_usb_ehci_resources),
+ .resource = cns3xxx_usb_ehci_resources,
+ .dev = {
+ .dma_mask = &cns3xxx_usb_ehci_dma_mask,
+ .coherent_dma_mask = DMA_BIT_MASK(32),
+ },
+};
+
+static struct resource cns3xxx_usb_ohci_resources[] = {
+ [0] = {
+ .start = CNS3XXX_USB_OHCI_BASE,
+ .end = CNS3XXX_USB_OHCI_BASE + SZ_16M - 1,
+ .flags = IORESOURCE_MEM,
+ },
+ [1] = {
+ .start = IRQ_CNS3XXX_USB_OHCI,
+ .flags = IORESOURCE_IRQ,
+ },
+};
+
+static u64 cns3xxx_usb_ohci_dma_mask = DMA_BIT_MASK(32);
+
+static struct platform_device cns3xxx_usb_ohci_device = {
+ .name = "cns3xxx-ohci",
+ .num_resources = ARRAY_SIZE(cns3xxx_usb_ohci_resources),
+ .resource = cns3xxx_usb_ohci_resources,
+ .dev = {
+ .dma_mask = &cns3xxx_usb_ohci_dma_mask,
+ .coherent_dma_mask = DMA_BIT_MASK(32),
+ },
+};
+
+static struct resource cns3xxx_usb_otg_resources[] = {
+ [0] = {
+ .start = CNS3XXX_USBOTG_BASE,
+ .end = CNS3XXX_USBOTG_BASE + SZ_16M - 1,
+ .flags = IORESOURCE_MEM,
+ },
+ [1] = {
+ .start = IRQ_CNS3XXX_USB_OTG,
+ .flags = IORESOURCE_IRQ,
+ },
+};
+
+static u64 cns3xxx_usb_otg_dma_mask = DMA_BIT_MASK(32);
+
+static struct platform_device cns3xxx_usb_otg_device = {
+ .name = "dwc_otg",
+ .num_resources = ARRAY_SIZE(cns3xxx_usb_otg_resources),
+ .resource = cns3xxx_usb_otg_resources,
+ .dev = {
+ .dma_mask = &cns3xxx_usb_otg_dma_mask,
+ .coherent_dma_mask = DMA_BIT_MASK(32),
+ },
+};
+
+/*
+ * I2C
+ */
+static struct resource laguna_i2c_resource[] = {
+ {
+ .start = CNS3XXX_SSP_BASE + 0x20,
+ .end = 0x7100003f,
+ .flags = IORESOURCE_MEM,
+ },{
+ .start = IRQ_CNS3XXX_I2C,
+ .flags = IORESOURCE_IRQ,
+ },
+};
+
+static struct platform_device laguna_i2c_controller = {
+ .name = "cns3xxx-i2c",
+ .num_resources = 2,
+ .resource = laguna_i2c_resource,
+};
+
+static struct memory_accessor *at24_mem_acc;
+
+static void at24_setup(struct memory_accessor *mem_acc, void *context)
+{
+ char buf[16];
+
+ at24_mem_acc = mem_acc;
+
+ /* Read MAC addresses */
+ if (at24_mem_acc->read(at24_mem_acc, buf, 0x100, 6) == 6)
+ memcpy(&laguna_net_data.hwaddr[0], buf, ETH_ALEN);
+ if (at24_mem_acc->read(at24_mem_acc, buf, 0x106, 6) == 6)
+ memcpy(&laguna_net_data.hwaddr[1], buf, ETH_ALEN);
+ if (at24_mem_acc->read(at24_mem_acc, buf, 0x10C, 6) == 6)
+ memcpy(&laguna_net_data.hwaddr[2], buf, ETH_ALEN);
+ if (at24_mem_acc->read(at24_mem_acc, buf, 0x112, 6) == 6)
+ memcpy(&laguna_net_data.hwaddr[3], buf, ETH_ALEN);
+
+ /* Read out Model Information */
+ if (at24_mem_acc->read(at24_mem_acc, buf, 0x130, 16) == 16)
+ memcpy(&laguna_info.model, buf, 16);
+ if (at24_mem_acc->read(at24_mem_acc, buf, 0x140, 1) == 1)
+ memcpy(&laguna_info.nor_flash_size, buf, 1);
+ if (at24_mem_acc->read(at24_mem_acc, buf, 0x141, 1) == 1)
+ memcpy(&laguna_info.spi_flash_size, buf, 1);
+ if (at24_mem_acc->read(at24_mem_acc, buf, 0x142, 4) == 4)
+ memcpy(&laguna_info.config_bitmap, buf, 4);
+ if (at24_mem_acc->read(at24_mem_acc, buf, 0x146, 4) == 4)
+ memcpy(&laguna_info.config2_bitmap, buf, 4);
+};
+
+static struct at24_platform_data laguna_eeprom_info = {
+ .byte_len = 1024,
+ .page_size = 16,
+ .flags = AT24_FLAG_READONLY,
+ .setup = at24_setup,
+};
+
+static struct pca953x_platform_data laguna_pca_data = {
+ .gpio_base = 100,
+ .irq_base = -1,
+};
+
+static struct pca953x_platform_data laguna_pca2_data = {
+ .gpio_base = 116,
+ .irq_base = -1,
+};
+
+static struct i2c_board_info __initdata laguna_i2c_devices[] = {
+ {
+ I2C_BOARD_INFO("pca9555", 0x23),
+ .platform_data = &laguna_pca_data,
+ },{
+ I2C_BOARD_INFO("pca9555", 0x27),
+ .platform_data = &laguna_pca2_data,
+ },{
+ I2C_BOARD_INFO("gsp", 0x29),
+ },{
+ I2C_BOARD_INFO ("24c08",0x50),
+ .platform_data = &laguna_eeprom_info,
+ },{
+ I2C_BOARD_INFO("ds1672", 0x68),
+ },
+};
+
+/*
+ * Watchdog
+ */
+
+static struct resource laguna_watchdog_resources[] = {
+ [0] = {
+ .start = CNS3XXX_TC11MP_TWD_BASE + 0x100, // CPU0 watchdog
+ .end = CNS3XXX_TC11MP_TWD_BASE + SZ_4K - 1,
+ .flags = IORESOURCE_MEM,
+ },
+ [1] = {
+ .start = IRQ_LOCALWDOG,
+ .end = IRQ_LOCALWDOG,
+ .flags = IORESOURCE_IRQ,
+ }
+};
+
+static struct platform_device laguna_watchdog = {
+ .name = "mpcore_wdt",
+ .id = -1,
+ .num_resources = ARRAY_SIZE(laguna_watchdog_resources),
+ .resource = laguna_watchdog_resources,
+};
+
+/*
+ * GPIO
+ */
+
+static struct gpio laguna_gpio_gw2391[] = {
+ { 0, GPIOF_IN , "*GPS_PPS" },
+ { 1, GPIOF_IN , "*GSC_IRQ#" },
+ { 2, GPIOF_IN , "*USB_FAULT#" },
+ { 5, GPIOF_OUT_INIT_LOW , "*USB0_PCI_SEL" },
+ { 6, GPIOF_OUT_INIT_HIGH, "*USB_VBUS_EN" },
+ { 7, GPIOF_OUT_INIT_LOW , "*USB1_PCI_SEL" },
+ { 8, GPIOF_OUT_INIT_HIGH, "*PERST#" },
+ { 9, GPIOF_OUT_INIT_LOW , "*FP_SER_EN#" },
+ { 100, GPIOF_IN , "*USER_PB#" },
+ { 103, GPIOF_OUT_INIT_HIGH, "*V5_EN" },
+ { 108, GPIOF_IN , "DIO0" },
+ { 109, GPIOF_IN , "DIO1" },
+ { 110, GPIOF_IN , "DIO2" },
+ { 111, GPIOF_IN , "DIO3" },
+ { 112, GPIOF_IN , "DIO4" },
+};
+
+static struct gpio laguna_gpio_gw2388[] = {
+ { 0, GPIOF_IN , "*GPS_PPS" },
+ { 1, GPIOF_IN , "*GSC_IRQ#" },
+ { 3, GPIOF_IN , "*USB_FAULT#" },
+ { 6, GPIOF_OUT_INIT_HIGH, "*USB_VBUS_EN" },
+ { 7, GPIOF_OUT_INIT_LOW , "*GSM_SEL0" },
+ { 8, GPIOF_OUT_INIT_LOW , "*GSM_SEL1" },
+ { 9, GPIOF_OUT_INIT_LOW , "*FP_SER_EN" },
+ { 100, GPIOF_OUT_INIT_HIGH, "*USER_PB#" },
+ { 108, GPIOF_IN , "DIO0" },
+ { 109, GPIOF_IN , "DIO1" },
+ { 110, GPIOF_IN , "DIO2" },
+ { 111, GPIOF_IN , "DIO3" },
+ { 112, GPIOF_IN , "DIO4" },
+};
+
+static struct gpio laguna_gpio_gw2387[] = {
+ { 0, GPIOF_IN , "*GPS_PPS" },
+ { 1, GPIOF_IN , "*GSC_IRQ#" },
+ { 2, GPIOF_IN , "*USB_FAULT#" },
+ { 5, GPIOF_OUT_INIT_LOW , "*USB_PCI_SEL" },
+ { 6, GPIOF_OUT_INIT_HIGH, "*USB_VBUS_EN" },
+ { 7, GPIOF_OUT_INIT_LOW , "*GSM_SEL0" },
+ { 8, GPIOF_OUT_INIT_LOW , "*GSM_SEL1" },
+ { 9, GPIOF_OUT_INIT_LOW , "*FP_SER_EN" },
+ { 100, GPIOF_IN , "*USER_PB#" },
+ { 103, GPIOF_OUT_INIT_HIGH, "*V5_EN" },
+ { 108, GPIOF_IN , "DIO0" },
+ { 109, GPIOF_IN , "DIO1" },
+ { 110, GPIOF_IN , "DIO2" },
+ { 111, GPIOF_IN , "DIO3" },
+ { 112, GPIOF_IN , "DIO4" },
+ { 113, GPIOF_IN , "DIO5" },
+};
+
+static struct gpio laguna_gpio_gw2384[] = {
+ { 0, GPIOF_IN , "*GSC_IRQ#" },
+ { 1, GPIOF_OUT_INIT_HIGH, "*USB_HST_VBUS_EN" },
+ { 2, GPIOF_IN , "*USB_HST_FAULT#" },
+ { 5, GPIOF_IN , "*USB_OTG_FAULT#" },
+ { 6, GPIOF_OUT_INIT_LOW , "*USB_HST_PCI_SEL" },
+ { 7, GPIOF_OUT_INIT_LOW , "*GSM_SEL0" },
+ { 8, GPIOF_OUT_INIT_LOW , "*GSM_SEL1" },
+ { 9, GPIOF_OUT_INIT_LOW , "*FP_SER_EN" },
+ { 12, GPIOF_OUT_INIT_LOW , "J10_DIOLED0" },
+ { 13, GPIOF_OUT_INIT_HIGH, "*I2CMUX_RST#" },
+ { 14, GPIOF_OUT_INIT_LOW , "J10_DIOLED1" },
+ { 15, GPIOF_OUT_INIT_LOW , "J10_DIOLED2" },
+ { 100, GPIOF_IN , "*USER_PB#" },
+ { 103, GPIOF_OUT_INIT_HIGH, "V5_EN" },
+ { 108, GPIOF_IN , "J9_DIOGSC0" },
+};
+
+static struct gpio laguna_gpio_gw2383[] = {
+ { 0, GPIOF_IN , "*GPS_PPS" },
+ { 1, GPIOF_IN , "*GSC_IRQ#" },
+ { 2, GPIOF_OUT_INIT_HIGH, "*PCIE_RST#" },
+ { 3, GPIOF_IN , "GPIO0" },
+ { 8, GPIOF_IN , "GPIO1" },
+ { 100, GPIOF_IN , "DIO0" },
+ { 101, GPIOF_IN , "DIO1" },
+};
+
+static struct gpio laguna_gpio_gw2382[] = {
+ { 0, GPIOF_IN , "*GPS_PPS" },
+ { 1, GPIOF_IN , "*GSC_IRQ#" },
+ { 2, GPIOF_OUT_INIT_HIGH, "*PCIE_RST#" },
+ { 3, GPIOF_IN , "GPIO0" },
+ { 4, GPIOF_IN , "GPIO1" },
+ { 9, GPIOF_OUT_INIT_HIGH, "*USB_VBUS_EN" },
+ { 10, GPIOF_OUT_INIT_HIGH, "*USB_PCI_SEL#" },
+ { 100, GPIOF_IN , "DIO0" },
+ { 101, GPIOF_IN , "DIO1" },
+};
+
+static struct gpio laguna_gpio_gw2380[] = {
+ { 0, GPIOF_IN , "*GPS_PPS" },
+ { 1, GPIOF_IN , "*GSC_IRQ#" },
+ { 3, GPIOF_IN , "GPIO0" },
+ { 8, GPIOF_IN , "GPIO1" },
+ { 100, GPIOF_IN , "DIO0" },
+ { 101, GPIOF_IN , "DIO1" },
+ { 102, GPIOF_IN , "DIO2" },
+ { 103, GPIOF_IN , "DIO3" },
+};
+
+/*
+ * Initialization
+ */
+static void __init laguna_init(void)
+{
+ cns3xxx_l2x0_init();
+
+ platform_device_register(&laguna_watchdog);
+
+ platform_device_register(&laguna_i2c_controller);
+
+ i2c_register_board_info(0, ARRAY_AND_SIZE(laguna_i2c_devices));
+
+ pm_power_off = cns3xxx_power_off;
+}
+
+static struct map_desc laguna_io_desc[] __initdata = {
+ {
+ .virtual = CNS3XXX_UART0_BASE_VIRT,
+ .pfn = __phys_to_pfn(CNS3XXX_UART0_BASE),
+ .length = SZ_4K,
+ .type = MT_DEVICE,
+ },{
+ .virtual = CNS3XXX_UART1_BASE_VIRT,
+ .pfn = __phys_to_pfn(CNS3XXX_UART1_BASE),
+ .length = SZ_4K,
+ .type = MT_DEVICE,
+ },{
+ .virtual = CNS3XXX_UART2_BASE_VIRT,
+ .pfn = __phys_to_pfn(CNS3XXX_UART2_BASE),
+ .length = SZ_4K,
+ .type = MT_DEVICE,
+ },
+};
+
+static void __init laguna_map_io(void)
+{
+ cns3xxx_common_init();
+ cns3xxx_pcie_iotable_init();
+ iotable_init(ARRAY_AND_SIZE(laguna_io_desc));
+ laguna_early_serial_setup();
+}
+
+static int laguna_register_gpio(struct gpio *array, size_t num)
+{
+ int i, err, ret;
+
+ ret = 0;
+ for (i = 0; i < num; i++, array++) {
+ const char *label = array->label;
+ if (label[0] == '*')
+ label++;
+ err = gpio_request_one(array->gpio, array->flags, label);
+ if (err)
+ ret = err;
+ else {
+ err = gpio_export(array->gpio, array->label[0] != '*');
+ }
+ }
+ return ret;
+}
+
+static int __init laguna_pcie_init(void)
+{
+ if (!machine_is_gw2388())
+ return 0;
+
+ return cns3xxx_pcie_init();
+}
+subsys_initcall(laguna_pcie_init);
+
+static int __init laguna_model_setup(void)
+{
+ u32 __iomem *mem;
+ u32 reg;
+
+ printk("Running on Gateworks Laguna %s\n", laguna_info.model);
+ cns3xxx_gpio_init( 0, 32, CNS3XXX_GPIOA_BASE_VIRT, IRQ_CNS3XXX_GPIOA,
+ NR_IRQS_CNS3XXX);
+ cns3xxx_gpio_init(32, 32, CNS3XXX_GPIOB_BASE_VIRT, IRQ_CNS3XXX_GPIOB,
+ NR_IRQS_CNS3XXX + 32);
+
+ if (strncmp(laguna_info.model, "GW", 2) == 0) {
+ if (laguna_info.config_bitmap & ETH0_LOAD)
+ laguna_net_data.ports |= BIT(0);
+ if (laguna_info.config_bitmap & ETH1_LOAD)
+ laguna_net_data.ports |= BIT(1);
+ if (laguna_info.config_bitmap & ETH2_LOAD)
+ laguna_net_data.ports |= BIT(2);
+ if (laguna_net_data.ports)
+ platform_device_register(&laguna_net_device);
+
+ if ((laguna_info.config_bitmap & SATA0_LOAD) ||
+ (laguna_info.config_bitmap & SATA1_LOAD))
+ cns3xxx_ahci_init();
+
+ if (laguna_info.config_bitmap & (USB0_LOAD)) {
+ cns3xxx_pwr_power_up(1 << PM_PLL_HM_PD_CTRL_REG_OFFSET_PLL_USB);
+
+ /* DRVVBUS pins share with GPIOA */
+ mem = (void __iomem *)(CNS3XXX_MISC_BASE_VIRT + 0x0014);
+ reg = __raw_readl(mem);
+ reg |= 0x8;
+ __raw_writel(reg, mem);
+
+ /* Enable OTG */
+ mem = (void __iomem *)(CNS3XXX_MISC_BASE_VIRT + 0x0808);
+ reg = __raw_readl(mem);
+ reg &= ~(1 << 10);
+ __raw_writel(reg, mem);
+
+ platform_device_register(&cns3xxx_usb_otg_device);
+ }
+
+ if (laguna_info.config_bitmap & (USB1_LOAD)) {
+ platform_device_register(&cns3xxx_usb_ehci_device);
+ platform_device_register(&cns3xxx_usb_ohci_device);
+ }
+
+ if (laguna_info.config_bitmap & (SD_LOAD))
+ cns3xxx_sdhci_init();
+
+ if (laguna_info.config_bitmap & (UART0_LOAD))
+ laguna_uart.num_resources = 1;
+ if (laguna_info.config_bitmap & (UART1_LOAD))
+ laguna_uart.num_resources = 2;
+ if (laguna_info.config_bitmap & (UART2_LOAD))
+ laguna_uart.num_resources = 3;
+ platform_device_register(&laguna_uart);
+
+ if (laguna_info.config2_bitmap & (NOR_FLASH_LOAD)) {
+ switch (laguna_info.nor_flash_size) {
+ case 1:
+ laguna_nor_partitions[3].size = SZ_8M - SZ_256K - SZ_128K - SZ_2M;
+ laguna_nor_res.end = CNS3XXX_FLASH_BASE + SZ_8M - 1;
+ break;
+ case 2:
+ laguna_nor_partitions[3].size = SZ_16M - SZ_256K - SZ_128K - SZ_2M;
+ laguna_nor_res.end = CNS3XXX_FLASH_BASE + SZ_16M - 1;
+ break;
+ case 3:
+ laguna_nor_partitions[3].size = SZ_32M - SZ_256K - SZ_128K - SZ_2M;
+ laguna_nor_res.end = CNS3XXX_FLASH_BASE + SZ_32M - 1;
+ break;
+ case 4:
+ laguna_nor_partitions[3].size = SZ_64M - SZ_256K - SZ_128K - SZ_2M;
+ laguna_nor_res.end = CNS3XXX_FLASH_BASE + SZ_64M - 1;
+ break;
+ case 5:
+ laguna_nor_partitions[3].size = SZ_128M - SZ_256K - SZ_128K - SZ_2M;
+ laguna_nor_res.end = CNS3XXX_FLASH_BASE + SZ_128M - 1;
+ break;
+ }
+ platform_device_register(&laguna_nor_pdev);
+ }
+
+ if (laguna_info.config2_bitmap & (SPI_FLASH_LOAD)) {
+ switch (laguna_info.spi_flash_size) {
+ case 1:
+ laguna_spi_partitions[3].size = SZ_4M - SZ_2M;
+ break;
+ case 2:
+ laguna_spi_partitions[3].size = SZ_8M - SZ_2M;
+ break;
+ case 3:
+ laguna_spi_partitions[3].size = SZ_16M - SZ_2M;
+ break;
+ case 4:
+ laguna_spi_partitions[3].size = SZ_32M - SZ_2M;
+ break;
+ case 5:
+ laguna_spi_partitions[3].size = SZ_64M - SZ_2M;
+ break;
+ }
+ spi_register_board_info(ARRAY_AND_SIZE(laguna_spi_devices));
+ }
+
+ if ((laguna_info.config_bitmap & SPI0_LOAD) ||
+ (laguna_info.config_bitmap & SPI1_LOAD))
+ platform_device_register(&laguna_spi_controller);
+
+ /*
+ * Do any model specific setup not known by the bitmap by matching
+ * the first 6 characters of the model name
+ */
+
+ if ( (strncmp(laguna_info.model, "GW2388", 6) == 0)
+ || (strncmp(laguna_info.model, "GW2389", 6) == 0) )
+ {
+ // configure GPIO's
+ laguna_register_gpio(ARRAY_AND_SIZE(laguna_gpio_gw2388));
+ // configure LED's
+ laguna_gpio_leds_data.num_leds = 2;
+ } else if (strncmp(laguna_info.model, "GW2387", 6) == 0) {
+ // configure GPIO's
+ laguna_register_gpio(ARRAY_AND_SIZE(laguna_gpio_gw2387));
+ // configure LED's
+ laguna_gpio_leds_data.num_leds = 2;
+ } else if (strncmp(laguna_info.model, "GW2384", 6) == 0) {
+ // configure GPIO's
+ laguna_register_gpio(ARRAY_AND_SIZE(laguna_gpio_gw2384));
+ // configure LED's
+ laguna_gpio_leds_data.num_leds = 1;
+ } else if (strncmp(laguna_info.model, "GW2383", 6) == 0) {
+ // configure GPIO's
+ laguna_register_gpio(ARRAY_AND_SIZE(laguna_gpio_gw2383));
+ // configure LED's
+ laguna_gpio_leds[0].gpio = 107;
+ laguna_gpio_leds_data.num_leds = 1;
+ } else if (strncmp(laguna_info.model, "GW2382", 6) == 0) {
+ // configure GPIO's
+ laguna_register_gpio(ARRAY_AND_SIZE(laguna_gpio_gw2382));
+ // configure LED's
+ laguna_gpio_leds[0].gpio = 107;
+ laguna_gpio_leds_data.num_leds = 1;
+ } else if (strncmp(laguna_info.model, "GW2380", 6) == 0) {
+ // configure GPIO's
+ laguna_register_gpio(ARRAY_AND_SIZE(laguna_gpio_gw2380));
+ // configure LED's
+ laguna_gpio_leds[0].gpio = 107;
+ laguna_gpio_leds[1].gpio = 106;
+ laguna_gpio_leds_data.num_leds = 2;
+ } else if (strncmp(laguna_info.model, "GW2391", 6) == 0) {
+ // configure GPIO's
+ laguna_register_gpio(ARRAY_AND_SIZE(laguna_gpio_gw2391));
+ // configure LED's
+ laguna_gpio_leds_data.num_leds = 2;
+ }
+ platform_device_register(&laguna_gpio_leds_device);
+ } else {
+ // Do some defaults here, not sure what yet
+ }
+ return 0;
+}
+late_initcall(laguna_model_setup);
+
+MACHINE_START(GW2388, "Gateworks Corporation Laguna Platform")
+ .atag_offset = 0x100,
+ .map_io = laguna_map_io,
+ .init_irq = cns3xxx_init_irq,
+ .timer = &cns3xxx_timer,
+ .handle_irq = gic_handle_irq,
+ .init_machine = laguna_init,
+ .restart = cns3xxx_restart,
+MACHINE_END
--- /dev/null
+/* linux/arch/arm/mach-cns3xxx/localtimer.c
+ *
+ * Cloned from linux/arch/arm/mach-realview/localtimer.c
+ *
+ * Copyright (C) 2002 ARM Ltd.
+ * All Rights Reserved
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/clockchips.h>
+
+#include <asm/irq.h>
+#include <asm/localtimer.h>
+
+/*
+ * Setup the local clock events for a CPU.
+ */
+int __cpuinit local_timer_setup(struct clock_event_device *evt)
+{
+ evt->irq = IRQ_LOCALTIMER;
+ twd_timer_setup(evt);
+ return 0;
+}
--- /dev/null
+/*
+ * linux/arch/arm/mach-cns3xxx/platsmp.c
+ *
+ * Copyright (C) 2002 ARM Ltd.
+ * Copyright 2012 Gateworks Corporation
+ * Chris Lang <clang@gateworks.com>
+ * Tim Harvey <tharvey@gateworks.com>
+ *
+ * All Rights Reserved
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include <linux/init.h>
+#include <linux/errno.h>
+#include <linux/delay.h>
+#include <linux/device.h>
+#include <linux/jiffies.h>
+#include <linux/smp.h>
+#include <linux/io.h>
+
+#include <asm/cacheflush.h>
+#include <asm/hardware/gic.h>
+#include <asm/smp_scu.h>
+#include <asm/unified.h>
+#include <asm/fiq.h>
+#include <mach/smp.h>
+#include <mach/cns3xxx.h>
+
+static struct fiq_handler fh = {
+ .name = "cns3xxx-fiq"
+};
+
+static unsigned int fiq_buffer[8];
+
+#define FIQ_ENABLED 0x80000000
+#define FIQ_GENERATE 0x00010000
+#define CNS3XXX_MAP_AREA 0x01000000
+#define CNS3XXX_UNMAP_AREA 0x02000000
+#define CNS3XXX_FLUSH_RANGE 0x03000000
+
+extern void cns3xxx_secondary_startup(void);
+extern unsigned char cns3xxx_fiq_start, cns3xxx_fiq_end;
+extern unsigned int fiq_number[2];
+extern struct cpu_cache_fns cpu_cache;
+struct cpu_cache_fns cpu_cache_save;
+
+#define SCU_CPU_STATUS 0x08
+static void __iomem *scu_base;
+
+/*
+ * control for which core is the next to come out of the secondary
+ * boot "holding pen"
+ */
+volatile int __cpuinitdata pen_release = -1;
+
+static void __init cns3xxx_set_fiq_regs(void)
+{
+ struct pt_regs FIQ_regs;
+ unsigned int cpu = smp_processor_id();
+
+ if (cpu) {
+ FIQ_regs.ARM_ip = (unsigned int)&fiq_buffer[4];
+ FIQ_regs.ARM_sp = (unsigned int)MISC_FIQ_CPU(0);
+ } else {
+ FIQ_regs.ARM_ip = (unsigned int)&fiq_buffer[0];
+ FIQ_regs.ARM_sp = (unsigned int)MISC_FIQ_CPU(1);
+ }
+ set_fiq_regs(&FIQ_regs);
+}
+
+static void __init cns3xxx_init_fiq(void)
+{
+ void *fiqhandler_start;
+ unsigned int fiqhandler_length;
+ int ret;
+
+ fiqhandler_start = &cns3xxx_fiq_start;
+ fiqhandler_length = &cns3xxx_fiq_end - &cns3xxx_fiq_start;
+
+ ret = claim_fiq(&fh);
+
+ if (ret) {
+ return;
+ }
+
+ set_fiq_handler(fiqhandler_start, fiqhandler_length);
+ fiq_buffer[0] = (unsigned int)&fiq_number[0];
+ fiq_buffer[3] = 0;
+ fiq_buffer[4] = (unsigned int)&fiq_number[1];
+ fiq_buffer[7] = 0;
+}
+
+
+/*
+ * Write pen_release in a way that is guaranteed to be visible to all
+ * observers, irrespective of whether they're taking part in coherency
+ * or not. This is necessary for the hotplug code to work reliably.
+ */
+static void __cpuinit write_pen_release(int val)
+{
+ pen_release = val;
+ smp_wmb();
+ __cpuc_flush_dcache_area((void *)&pen_release, sizeof(pen_release));
+ outer_clean_range(__pa(&pen_release), __pa(&pen_release + 1));
+}
+
+static DEFINE_SPINLOCK(boot_lock);
+
+void __cpuinit platform_secondary_init(unsigned int cpu)
+{
+ /*
+ * if any interrupts are already enabled for the primary
+ * core (e.g. timer irq), then they will not have been enabled
+ * for us: do so
+ */
+ gic_secondary_init(0);
+
+ /*
+ * Setup Secondary Core FIQ regs
+ */
+ cns3xxx_set_fiq_regs();
+
+ /*
+ * let the primary processor know we're out of the
+ * pen, then head off into the C entry point
+ */
+ write_pen_release(-1);
+
+ /*
+ * Fixup DMA Operations
+ *
+ */
+ cpu_cache.dma_map_area = (void *)smp_dma_map_area;
+ cpu_cache.dma_unmap_area = (void *)smp_dma_unmap_area;
+ cpu_cache.dma_flush_range = (void *)smp_dma_flush_range;
+
+ /*
+ * Synchronise with the boot thread.
+ */
+ spin_lock(&boot_lock);
+ spin_unlock(&boot_lock);
+}
+
+int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
+{
+ unsigned long timeout;
+
+ /*
+ * Set synchronisation state between this boot processor
+ * and the secondary one
+ */
+ spin_lock(&boot_lock);
+
+ /*
+ * The secondary processor is waiting to be released from
+ * the holding pen - release it, then wait for it to flag
+ * that it has been released by resetting pen_release.
+ *
+ * Note that "pen_release" is the hardware CPU ID, whereas
+ * "cpu" is Linux's internal ID.
+ */
+ write_pen_release(cpu);
+
+ /*
+ * Send the secondary CPU a soft interrupt, thereby causing
+ * the boot monitor to read the system wide flags register,
+ * and branch to the address found there.
+ */
+ gic_raise_softirq(cpumask_of(cpu), 1);
+
+ timeout = jiffies + (1 * HZ);
+ while (time_before(jiffies, timeout)) {
+ smp_rmb();
+ if (pen_release == -1)
+ break;
+
+ udelay(10);
+ }
+
+ /*
+ * now the secondary core is starting up let it run its
+ * calibrations, then wait for it to finish
+ */
+ spin_unlock(&boot_lock);
+
+ return pen_release != -1 ? -ENOSYS : 0;
+}
+
+/*
+ * Initialise the CPU possible map early - this describes the CPUs
+ * which may be present or become present in the system.
+ */
+void __init smp_init_cpus(void)
+{
+ unsigned int i, ncores;
+ unsigned int status;
+
+ scu_base = (void __iomem *) CNS3XXX_TC11MP_SCU_BASE_VIRT;
+
+ /* for CNS3xxx SCU_CPU_STATUS must be examined instead of SCU_CONFIGURATION
+ * used in scu_get_core_count
+ */
+ status = __raw_readl(scu_base + SCU_CPU_STATUS);
+ for (i = 0; i < NR_CPUS+1; i++) {
+ if (((status >> (i*2)) & 0x3) == 0)
+ set_cpu_possible(i, true);
+ else
+ break;
+ }
+ ncores = i;
+
+ set_smp_cross_call(gic_raise_softirq);
+}
+
+void __init platform_smp_prepare_cpus(unsigned int max_cpus)
+{
+ int i;
+
+ /*
+ * Initialise the present map, which describes the set of CPUs
+ * actually populated at the present time.
+ */
+ for (i = 0; i < max_cpus; i++) {
+ set_cpu_present(i, true);
+ }
+
+ /*
+ * enable SCU
+ */
+ scu_enable(scu_base);
+
+ /*
+ * Write the address of secondary startup into the
+ * system-wide flags register. The boot monitor waits
+ * until it receives a soft interrupt, and then the
+ * secondary CPU branches to this address.
+ */
+ __raw_writel(virt_to_phys(cns3xxx_secondary_startup),
+ (void __iomem *)(CNS3XXX_MISC_BASE_VIRT + 0x0600));
+
+ /*
+ * Setup FIQ's for main cpu
+ */
+ cns3xxx_init_fiq();
+ cns3xxx_set_fiq_regs();
+ memcpy((void *)&cpu_cache_save, (void *)&cpu_cache, sizeof(struct cpu_cache_fns));
+}
+
+
+static inline unsigned long cns3xxx_cpu_id(void)
+{
+ unsigned long cpu;
+
+ asm volatile(
+ " mrc p15, 0, %0, c0, c0, 5 @ cns3xxx_cpu_id\n"
+ : "=r" (cpu) : : "memory", "cc");
+ return (cpu & 0xf);
+}
+
+void smp_dma_map_area(const void *addr, size_t size, int dir)
+{
+ unsigned int cpu;
+ unsigned long flags;
+ raw_local_irq_save(flags);
+ cpu = cns3xxx_cpu_id();
+ if (cpu) {
+ fiq_buffer[1] = (unsigned int)addr;
+ fiq_buffer[2] = size;
+ fiq_buffer[3] = dir | CNS3XXX_MAP_AREA | FIQ_ENABLED;
+ smp_mb();
+ __raw_writel(FIQ_GENERATE, MISC_FIQ_CPU(1));
+
+ cpu_cache_save.dma_map_area(addr, size, dir);
+ while ((fiq_buffer[3]) & FIQ_ENABLED) { barrier(); }
+ } else {
+
+ fiq_buffer[5] = (unsigned int)addr;
+ fiq_buffer[6] = size;
+ fiq_buffer[7] = dir | CNS3XXX_MAP_AREA | FIQ_ENABLED;
+ smp_mb();
+ __raw_writel(FIQ_GENERATE, MISC_FIQ_CPU(0));
+
+ cpu_cache_save.dma_map_area(addr, size, dir);
+ while ((fiq_buffer[7]) & FIQ_ENABLED) { barrier(); }
+ }
+ raw_local_irq_restore(flags);
+}
+
+void smp_dma_unmap_area(const void *addr, size_t size, int dir)
+{
+ unsigned int cpu;
+ unsigned long flags;
+
+ raw_local_irq_save(flags);
+ cpu = cns3xxx_cpu_id();
+ if (cpu) {
+
+ fiq_buffer[1] = (unsigned int)addr;
+ fiq_buffer[2] = size;
+ fiq_buffer[3] = dir | CNS3XXX_UNMAP_AREA | FIQ_ENABLED;
+ smp_mb();
+ __raw_writel(FIQ_GENERATE, MISC_FIQ_CPU(1));
+
+ cpu_cache_save.dma_unmap_area(addr, size, dir);
+ while ((fiq_buffer[3]) & FIQ_ENABLED) { barrier(); }
+ } else {
+
+ fiq_buffer[5] = (unsigned int)addr;
+ fiq_buffer[6] = size;
+ fiq_buffer[7] = dir | CNS3XXX_UNMAP_AREA | FIQ_ENABLED;
+ smp_mb();
+ __raw_writel(FIQ_GENERATE, MISC_FIQ_CPU(0));
+
+ cpu_cache_save.dma_unmap_area(addr, size, dir);
+ while ((fiq_buffer[7]) & FIQ_ENABLED) { barrier(); }
+ }
+ raw_local_irq_restore(flags);
+}
+
+void smp_dma_flush_range(const void *start, const void *end)
+{
+ unsigned int cpu;
+ unsigned long flags;
+ raw_local_irq_save(flags);
+ cpu = cns3xxx_cpu_id();
+ if (cpu) {
+
+ fiq_buffer[1] = (unsigned int)start;
+ fiq_buffer[2] = (unsigned int)end;
+ fiq_buffer[3] = CNS3XXX_FLUSH_RANGE | FIQ_ENABLED;
+ smp_mb();
+ __raw_writel(FIQ_GENERATE, MISC_FIQ_CPU(1));
+
+ cpu_cache_save.dma_flush_range(start, end);
+ while ((fiq_buffer[3]) & FIQ_ENABLED) { barrier(); }
+ } else {
+
+ fiq_buffer[5] = (unsigned int)start;
+ fiq_buffer[6] = (unsigned int)end;
+ fiq_buffer[7] = CNS3XXX_FLUSH_RANGE | FIQ_ENABLED;
+ smp_mb();
+ __raw_writel(FIQ_GENERATE, MISC_FIQ_CPU(0));
+
+ cpu_cache_save.dma_flush_range(start, end);
+ while ((fiq_buffer[7]) & FIQ_ENABLED) { barrier(); }
+ }
+ raw_local_irq_restore(flags);
+}
+obj-$(CONFIG_SMP) += platsmp.o headsmp.o
+obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o
+obj-$(CONFIG_LOCAL_TIMERS) += localtimer.o
---- /dev/null
-+++ b/arch/arm/mach-cns3xxx/headsmp.S
-@@ -0,0 +1,42 @@
-+/*
-+ * linux/arch/arm/mach-cns3xxx/headsmp.S
-+ *
-+ * Cloned from linux/arch/arm/plat-versatile/headsmp.S
-+ *
-+ * Copyright (c) 2003 ARM Limited
-+ * All Rights Reserved
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License version 2 as
-+ * published by the Free Software Foundation.
-+ */
-+#include <linux/linkage.h>
-+#include <linux/init.h>
-+
-+ __INIT
-+
-+/*
-+ * CNS3XXX specific entry point for secondary CPUs. This provides
-+ * a "holding pen" into which all secondary cores are held until we're
-+ * ready for them to initialise.
-+ */
-+ENTRY(cns3xxx_secondary_startup)
-+ mrc p15, 0, r0, c0, c0, 5
-+ and r0, r0, #15
-+ adr r4, 1f
-+ ldmia r4, {r5, r6}
-+ sub r4, r4, r5
-+ add r6, r6, r4
-+pen: ldr r7, [r6]
-+ cmp r7, r0
-+ bne pen
-+
-+ /*
-+ * we've been released from the holding pen: secondary_stack
-+ * should now contain the SVC stack for this core
-+ */
-+ b secondary_startup
-+
-+ .align
-+1: .long .
-+ .long pen_release
---- /dev/null
-+++ b/arch/arm/mach-cns3xxx/hotplug.c
-@@ -0,0 +1,130 @@
-+/* linux arch/arm/mach-cns3xxx/hotplug.c
-+ *
-+ * Cloned from linux/arch/arm/mach-realview/hotplug.c
-+ *
-+ * Copyright (C) 2002 ARM Ltd.
-+ * All Rights Reserved
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License version 2 as
-+ * published by the Free Software Foundation.
-+*/
-+
-+#include <linux/kernel.h>
-+#include <linux/errno.h>
-+#include <linux/smp.h>
-+
-+#include <asm/cacheflush.h>
-+
-+extern volatile int pen_release;
-+
-+static inline void cpu_enter_lowpower(void)
-+{
-+ unsigned int v;
-+
-+ flush_cache_all();
-+ asm volatile(
-+ " mcr p15, 0, %1, c7, c5, 0\n"
-+ " mcr p15, 0, %1, c7, c10, 4\n"
-+ /*
-+ * Turn off coherency
-+ */
-+ " mrc p15, 0, %0, c1, c0, 1\n"
-+ " bic %0, %0, %3\n"
-+ " mcr p15, 0, %0, c1, c0, 1\n"
-+ " mrc p15, 0, %0, c1, c0, 0\n"
-+ " bic %0, %0, %2\n"
-+ " mcr p15, 0, %0, c1, c0, 0\n"
-+ : "=&r" (v)
-+ : "r" (0), "Ir" (CR_C), "Ir" (0x40)
-+ : "cc");
-+}
-+
-+static inline void cpu_leave_lowpower(void)
-+{
-+ unsigned int v;
-+
-+ asm volatile(
-+ "mrc p15, 0, %0, c1, c0, 0\n"
-+ " orr %0, %0, %1\n"
-+ " mcr p15, 0, %0, c1, c0, 0\n"
-+ " mrc p15, 0, %0, c1, c0, 1\n"
-+ " orr %0, %0, %2\n"
-+ " mcr p15, 0, %0, c1, c0, 1\n"
-+ : "=&r" (v)
-+ : "Ir" (CR_C), "Ir" (0x40)
-+ : "cc");
-+}
-+
-+static inline void platform_do_lowpower(unsigned int cpu, int *spurious)
-+{
-+ /*
-+ * there is no power-control hardware on this platform, so all
-+ * we can do is put the core into WFI; this is safe as the calling
-+ * code will have already disabled interrupts
-+ */
-+ for (;;) {
-+ /*
-+ * here's the WFI
-+ */
-+ asm(".word 0xe320f003\n"
-+ :
-+ :
-+ : "memory", "cc");
-+
-+ if (pen_release == cpu) {
-+ /*
-+ * OK, proper wakeup, we're done
-+ */
-+ break;
-+ }
-+
-+ /*
-+ * Getting here, means that we have come out of WFI without
-+ * having been woken up - this shouldn't happen
-+ *
-+ * Just note it happening - when we're woken, we can report
-+ * its occurrence.
-+ */
-+ (*spurious)++;
-+ }
-+}
-+
-+int platform_cpu_kill(unsigned int cpu)
-+{
-+ return 1;
-+}
-+
-+/*
-+ * platform-specific code to shutdown a CPU
-+ *
-+ * Called with IRQs disabled
-+ */
-+void platform_cpu_die(unsigned int cpu)
-+{
-+ int spurious = 0;
-+
-+ /*
-+ * we're ready for shutdown now, so do it
-+ */
-+ cpu_enter_lowpower();
-+ platform_do_lowpower(cpu, &spurious);
-+
-+ /*
-+ * bring this CPU back into the world of cache
-+ * coherency, and then restore interrupts
-+ */
-+ cpu_leave_lowpower();
-+
-+ if (spurious)
-+ pr_warn("CPU%u: %u spurious wakeup calls\n", cpu, spurious);
-+}
-+
-+int platform_cpu_disable(unsigned int cpu)
-+{
-+ /*
-+ * we don't allow CPU 0 to be shutdown (it is still too special
-+ * e.g. clock tick interrupts)
-+ */
-+ return cpu == 0 ? -EPERM : 0;
-+}
--- a/arch/arm/mach-cns3xxx/Kconfig
+++ b/arch/arm/mach-cns3xxx/Kconfig
@@ -3,6 +3,7 @@ menu "CNS3XXX platform type"
select MIGHT_HAVE_PCI
help
Include support for the Cavium Networks CNS3420 MPCore Platform
---- /dev/null
-+++ b/arch/arm/mach-cns3xxx/localtimer.c
-@@ -0,0 +1,26 @@
-+/* linux/arch/arm/mach-cns3xxx/localtimer.c
-+ *
-+ * Cloned from linux/arch/arm/mach-realview/localtimer.c
-+ *
-+ * Copyright (C) 2002 ARM Ltd.
-+ * All Rights Reserved
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License version 2 as
-+ * published by the Free Software Foundation.
-+*/
-+
-+#include <linux/clockchips.h>
-+
-+#include <asm/irq.h>
-+#include <asm/localtimer.h>
-+
-+/*
-+ * Setup the local clock events for a CPU.
-+ */
-+int __cpuinit local_timer_setup(struct clock_event_device *evt)
-+{
-+ evt->irq = IRQ_LOCALTIMER;
-+ twd_timer_setup(evt);
-+ return 0;
-+}
---- /dev/null
-+++ b/arch/arm/mach-cns3xxx/platsmp.c
-@@ -0,0 +1,175 @@
-+/* linux/arch/arm/mach-cns3xxx/platsmp.c
-+ *
-+ * Copyright 2011 Gateworks Corporation
-+ * Chris Lang <clang@gateworks.com>
-+ *
-+ * Cloned from linux/arch/arm/mach-vexpress/platsmp.c
-+ *
-+ * Copyright (C) 2002 ARM Ltd.
-+ * All Rights Reserved
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License version 2 as
-+ * published by the Free Software Foundation.
-+*/
-+
-+#include <linux/init.h>
-+#include <linux/errno.h>
-+#include <linux/delay.h>
-+#include <linux/device.h>
-+#include <linux/jiffies.h>
-+#include <linux/smp.h>
-+#include <linux/io.h>
-+
-+#include <asm/cacheflush.h>
-+#include <asm/hardware/gic.h>
-+#include <asm/smp_scu.h>
-+#include <asm/unified.h>
-+
-+#include <mach/cns3xxx.h>
-+
-+extern void cns3xxx_secondary_startup(void);
-+
-+/*
-+ * control for which core is the next to come out of the secondary
-+ * boot "holding pen"
-+ */
-+
-+volatile int __cpuinitdata pen_release = -1;
-+
-+/*
-+ * Write pen_release in a way that is guaranteed to be visible to all
-+ * observers, irrespective of whether they're taking part in coherency
-+ * or not. This is necessary for the hotplug code to work reliably.
-+ */
-+static void write_pen_release(int val)
-+{
-+ pen_release = val;
-+ smp_wmb();
-+ __cpuc_flush_dcache_area((void *)&pen_release, sizeof(pen_release));
-+ outer_clean_range(__pa(&pen_release), __pa(&pen_release + 1));
-+}
-+
-+static void __iomem *scu_base_addr(void)
-+{
-+ return (void __iomem *)(CNS3XXX_TC11MP_SCU_BASE_VIRT);
-+}
-+
-+static DEFINE_SPINLOCK(boot_lock);
-+
-+void __cpuinit platform_secondary_init(unsigned int cpu)
-+{
-+ /*
-+ * if any interrupts are already enabled for the primary
-+ * core (e.g. timer irq), then they will not have been enabled
-+ * for us: do so
-+ */
-+ gic_secondary_init(0);
-+
-+ /*
-+ * let the primary processor know we're out of the
-+ * pen, then head off into the C entry point
-+ */
-+ write_pen_release(-1);
-+
-+ /*
-+ * Synchronise with the boot thread.
-+ */
-+ spin_lock(&boot_lock);
-+ spin_unlock(&boot_lock);
-+}
-+
-+int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
-+{
-+ unsigned long timeout;
-+
-+ /*
-+ * Set synchronisation state between this boot processor
-+ * and the secondary one
-+ */
-+ spin_lock(&boot_lock);
-+
-+ /*
-+ * The secondary processor is waiting to be released from
-+ * the holding pen - release it, then wait for it to flag
-+ * that it has been released by resetting pen_release.
-+ *
-+ * Note that "pen_release" is the hardware CPU ID, whereas
-+ * "cpu" is Linux's internal ID.
-+ */
-+ write_pen_release(cpu);
-+
-+ /*
-+ * Send the secondary CPU a soft interrupt, thereby causing
-+ * the boot monitor to read the system wide flags register,
-+ * and branch to the address found there.
-+ */
-+ gic_raise_softirq(cpumask_of(cpu), 1);
-+
-+ timeout = jiffies + (1 * HZ);
-+ while (time_before(jiffies, timeout)) {
-+ smp_rmb();
-+ if (pen_release == -1)
-+ break;
-+
-+ udelay(10);
-+ }
-+
-+ /*
-+ * now the secondary core is starting up let it run its
-+ * calibrations, then wait for it to finish
-+ */
-+ spin_unlock(&boot_lock);
-+
-+ return pen_release != -1 ? -ENOSYS : 0;
-+}
-+
-+/*
-+ * Initialise the CPU possible map early - this describes the CPUs
-+ * which may be present or become present in the system.
-+ */
-+
-+void __init smp_init_cpus(void)
-+{
-+ void __iomem *scu_base = scu_base_addr();
-+ unsigned int i, ncores;
-+
-+ ncores = scu_base ? scu_get_core_count(scu_base) : 1;
-+
-+ /* sanity check */
-+ if (ncores > NR_CPUS) {
-+ printk(KERN_WARNING
-+ "cns3xxx: no. of cores (%d) greater than configured "
-+ "maximum of %d - clipping\n",
-+ ncores, NR_CPUS);
-+ ncores = NR_CPUS;
-+ }
-+
-+ for (i = 0; i < ncores; i++)
-+ set_cpu_possible(i, true);
-+
-+ set_smp_cross_call(gic_raise_softirq);
-+}
-+
-+void __init platform_smp_prepare_cpus(unsigned int max_cpus)
-+{
-+ int i;
-+
-+ /*
-+ * Initialise the present map, which describes the set of CPUs
-+ * actually populated at the present time.
-+ */
-+ for (i = 0; i < max_cpus; i++)
-+ set_cpu_present(i, true);
-+
-+ scu_enable(scu_base_addr());
-+
-+ /*
-+ * Write the address of secondary startup into the
-+ * system-wide flags register. The boot monitor waits
-+ * until it receives a soft interrupt, and then the
-+ * secondary CPU branches to this address.
-+ */
-+ __raw_writel(virt_to_phys(cns3xxx_secondary_startup),
-+ (void __iomem *)(CNS3XXX_MISC_BASE_VIRT + 0x0600));
-+}
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -373,6 +373,7 @@ config ARCH_CNS3XXX
+MODULE_DESCRIPTION("Cavium CNS3xxx Ethernet driver");
+MODULE_LICENSE("GPL v2");
+MODULE_ALIAS("platform:cns3xxx_eth");
---- /dev/null
-+++ b/arch/arm/mach-cns3xxx/include/mach/platform.h
-@@ -0,0 +1,26 @@
-+/*
-+ * arch/arm/mach-cns3xxx/include/mach/platform.h
-+ *
-+ * Copyright 2011 Gateworks Corporation
-+ * Chris Lang <clang@gateworks.com
-+ *
-+ * This file is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License, Version 2, as
-+ * published by the Free Software Foundation.
-+ *
-+ */
-+
-+#ifndef __ASM_ARCH_PLATFORM_H
-+#define __ASM_ARCH_PLATFORM_H
-+
-+#ifndef __ASSEMBLY__
-+
-+/* Information about built-in Ethernet MAC interfaces */
-+struct cns3xxx_plat_info {
-+ u8 ports; /* Bitmap of enabled Ports */
-+ u8 hwaddr[4][6];
-+ u32 phy[3];
-+};
-+
-+#endif /* __ASM_ARCH_PLATFORM_H */
-+#endif
--- a/drivers/net/ethernet/Kconfig
+++ b/drivers/net/ethernet/Kconfig
@@ -32,6 +32,7 @@ source "drivers/net/ethernet/calxeda/Kco
select GENERIC_CLOCKEVENTS
select ARM_GIC
select CLKDEV_LOOKUP
---- /dev/null
-+++ b/arch/arm/mach-cns3xxx/include/mach/gpio.h
-@@ -0,0 +1,98 @@
-+/*
-+ * arch/arm/mach-cns3xxx/include/mach/gpio.h
-+ *
-+ * CNS3xxx GPIO wrappers for arch-neutral GPIO calls
-+ *
-+ * Copyright 2011 Gateworks Corporation
-+ * Chris Lang <clang@gateworks.com>
-+ *
-+ * Based on IXP implementation by Milan Svoboda <msvoboda@ra.rockwell.com>
-+ * Based on PXA implementation by Philipp Zabel <philipp.zabel@gmail.com>
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License as published by
-+ * the Free Software Foundation; either version 2 of the License, or
-+ * (at your option) any later version.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+ * GNU General Public License for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program; if not, write to the Free Software
-+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-+ *
-+ */
-+
-+#ifndef __ASM_ARCH_CNS3XXX_GPIO_H
-+#define __ASM_ARCH_CNS3XXX_GPIO_H
-+
-+#include <linux/kernel.h>
-+#include <linux/io.h>
-+#include <mach/platform.h>
-+#include <asm-generic/gpio.h> /* cansleep wrappers */
-+
-+#define NR_BUILTIN_GPIO 64
-+
-+#define CNS3XXX_GPIO_IN 0x0
-+#define CNS3XXX_GPIO_OUT 0x1
-+
-+#define CNS3XXX_GPIO_LO 0
-+#define CNS3XXX_GPIO_HI 1
-+
-+#define CNS3XXX_GPIO_OUTPUT 0x00
-+#define CNS3XXX_GPIO_INPUT 0x04
-+#define CNS3XXX_GPIO_DIR 0x08
-+#define CNS3XXX_GPIO_SET 0x10
-+#define CNS3XXX_GPIO_CLEAR 0x14
-+
-+static inline void gpio_line_get(u8 line, int *value)
-+{
-+ if (line < 32)
-+ *value = ((__raw_readl(CNS3XXX_GPIOA_BASE_VIRT + CNS3XXX_GPIO_INPUT) >> line) & 0x1);
-+ else
-+ *value = ((__raw_readl(CNS3XXX_GPIOB_BASE_VIRT + CNS3XXX_GPIO_INPUT) >> (line - 32)) & 0x1);
-+}
-+
-+static inline void gpio_line_set(u8 line, int value)
-+{
-+ if (line < 32) {
-+ if (value)
-+ __raw_writel((1 << line), CNS3XXX_GPIOA_BASE_VIRT + CNS3XXX_GPIO_SET);
-+ else
-+ __raw_writel((1 << line), CNS3XXX_GPIOA_BASE_VIRT + CNS3XXX_GPIO_CLEAR);
-+ } else {
-+ if (value)
-+ __raw_writel((1 << line), CNS3XXX_GPIOB_BASE_VIRT + CNS3XXX_GPIO_SET);
-+ else
-+ __raw_writel((1 << line), CNS3XXX_GPIOB_BASE_VIRT + CNS3XXX_GPIO_CLEAR);
-+ }
-+}
-+
-+static inline int gpio_get_value(unsigned gpio)
-+{
-+ if (gpio < NR_BUILTIN_GPIO)
-+ {
-+ int value;
-+ gpio_line_get(gpio, &value);
-+ return value;
-+ }
-+ else
-+ return __gpio_get_value(gpio);
-+}
-+
-+static inline void gpio_set_value(unsigned gpio, int value)
-+{
-+ if (gpio < NR_BUILTIN_GPIO)
-+ gpio_line_set(gpio, value);
-+ else
-+ __gpio_set_value(gpio, value);
-+}
-+
-+#define gpio_cansleep __gpio_cansleep
-+
-+extern int gpio_to_irq(int gpio);
-+extern int irq_to_gpio(int gpio);
-+
-+#endif
---- /dev/null
-+++ b/arch/arm/mach-cns3xxx/laguna.c
-@@ -0,0 +1,931 @@
-+/*
-+ * Gateworks Corporation Laguna Platform
-+ *
-+ * Copyright 2000 Deep Blue Solutions Ltd
-+ * Copyright 2008 ARM Limited
-+ * Copyright 2008 Cavium Networks
-+ * Scott Shu
-+ * Copyright 2010 MontaVista Software, LLC.
-+ * Anton Vorontsov <avorontsov@mvista.com>
-+ * Copyright 2011 Gateworks Corporation
-+ * Chris Lang <clang@gateworks.com>
-+ * Copyright 2012 Gateworks Corporation
-+ * Tim Harvey <tharvey@gateworks.com>
-+ *
-+ * This file is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License, Version 2, as
-+ * published by the Free Software Foundation.
-+ */
-+
-+#include <linux/init.h>
-+#include <linux/kernel.h>
-+#include <linux/compiler.h>
-+#include <linux/io.h>
-+#include <linux/gpio.h>
-+#include <linux/dma-mapping.h>
-+#include <linux/serial_core.h>
-+#include <linux/serial_8250.h>
-+#include <linux/platform_device.h>
-+#include <linux/mtd/mtd.h>
-+#include <linux/mtd/physmap.h>
-+#include <linux/mtd/partitions.h>
-+#include <linux/leds.h>
-+#include <linux/i2c.h>
-+#include <linux/i2c/at24.h>
-+#include <linux/i2c/pca953x.h>
-+#include <linux/spi/spi.h>
-+#include <linux/spi/flash.h>
-+#include <linux/if_ether.h>
-+#include <asm/setup.h>
-+#include <asm/mach-types.h>
-+#include <asm/mach/arch.h>
-+#include <asm/mach/map.h>
-+#include <asm/mach/time.h>
-+#include <mach/cns3xxx.h>
-+#include <mach/irqs.h>
-+#include <mach/platform.h>
-+#include <mach/pm.h>
-+#include <asm/hardware/gic.h>
-+#include "core.h"
-+#include "devices.h"
-+
-+#define ARRAY_AND_SIZE(x) (x), ARRAY_SIZE(x)
-+
-+// Config 1 Bitmap
-+#define ETH0_LOAD BIT(0)
-+#define ETH1_LOAD BIT(1)
-+#define ETH2_LOAD BIT(2)
-+#define SATA0_LOAD BIT(3)
-+#define SATA1_LOAD BIT(4)
-+#define PCM_LOAD BIT(5)
-+#define I2S_LOAD BIT(6)
-+#define SPI0_LOAD BIT(7)
-+#define SPI1_LOAD BIT(8)
-+#define PCIE0_LOAD BIT(9)
-+#define PCIE1_LOAD BIT(10)
-+#define USB0_LOAD BIT(11)
-+#define USB1_LOAD BIT(12)
-+#define USB1_ROUTE BIT(13)
-+#define SD_LOAD BIT(14)
-+#define UART0_LOAD BIT(15)
-+#define UART1_LOAD BIT(16)
-+#define UART2_LOAD BIT(17)
-+#define MPCI0_LOAD BIT(18)
-+#define MPCI1_LOAD BIT(19)
-+#define MPCI2_LOAD BIT(20)
-+#define MPCI3_LOAD BIT(21)
-+#define FP_BUT_LOAD BIT(22)
-+#define FP_BUT_HEADER_LOAD BIT(23)
-+#define FP_LED_LOAD BIT(24)
-+#define FP_LED_HEADER_LOAD BIT(25)
-+#define FP_TAMPER_LOAD BIT(26)
-+#define HEADER_33V_LOAD BIT(27)
-+#define SATA_POWER_LOAD BIT(28)
-+#define FP_POWER_LOAD BIT(29)
-+#define GPIO_HEADER_LOAD BIT(30)
-+#define GSP_BAT_LOAD BIT(31)
-+
-+// Config 2 Bitmap
-+#define FAN_LOAD BIT(0)
-+#define SPI_FLASH_LOAD BIT(1)
-+#define NOR_FLASH_LOAD BIT(2)
-+#define GPS_LOAD BIT(3)
-+#define SUPPLY_5V_LOAD BIT(6)
-+#define SUPPLY_33V_LOAD BIT(7)
-+
-+struct laguna_board_info {
-+ char model[16];
-+ u32 config_bitmap;
-+ u32 config2_bitmap;
-+ u8 nor_flash_size;
-+ u8 spi_flash_size;
-+};
-+
-+static struct laguna_board_info laguna_info __initdata;
-+
-+/*
-+ * NOR Flash
-+ */
-+static struct mtd_partition laguna_nor_partitions[] = {
-+ {
-+ .name = "uboot",
-+ .size = SZ_256K,
-+ .offset = 0,
-+ .mask_flags = MTD_WRITEABLE,
-+ }, {
-+ .name = "params",
-+ .size = SZ_128K,
-+ .offset = SZ_256K,
-+ }, {
-+ .name = "kernel",
-+ .size = SZ_2M,
-+ .offset = SZ_256K + SZ_128K,
-+ }, {
-+ .name = "rootfs",
-+ .size = SZ_16M - SZ_256K - SZ_128K - SZ_2M,
-+ .offset = SZ_256K + SZ_128K + SZ_2M,
-+ },
-+};
-+
-+static struct physmap_flash_data laguna_nor_pdata = {
-+ .width = 2,
-+ .parts = laguna_nor_partitions,
-+ .nr_parts = ARRAY_SIZE(laguna_nor_partitions),
-+};
-+
-+static struct resource laguna_nor_res = {
-+ .start = CNS3XXX_FLASH_BASE,
-+ .end = CNS3XXX_FLASH_BASE + SZ_128M - 1,
-+ .flags = IORESOURCE_MEM | IORESOURCE_MEM_32BIT,
-+};
-+
-+static struct platform_device laguna_nor_pdev = {
-+ .name = "physmap-flash",
-+ .id = 0,
-+ .resource = &laguna_nor_res,
-+ .num_resources = 1,
-+ .dev = {
-+ .platform_data = &laguna_nor_pdata,
-+ },
-+};
-+
-+/*
-+ * SPI
-+ */
-+static struct mtd_partition laguna_spi_partitions[] = {
-+ {
-+ .name = "uboot",
-+ .size = SZ_256K,
-+ .offset = 0,
-+ .mask_flags = MTD_WRITEABLE,
-+ }, {
-+ .name = "params",
-+ .size = SZ_256K,
-+ .offset = SZ_256K,
-+ }, {
-+ .name = "kernel",
-+ .size = SZ_1M + SZ_512K,
-+ .offset = SZ_512K,
-+ }, {
-+ .name = "rootfs",
-+ .size = SZ_16M - SZ_2M,
-+ .offset = SZ_2M,
-+ },
-+};
-+
-+static struct flash_platform_data laguna_spi_pdata = {
-+ .parts = laguna_spi_partitions,
-+ .nr_parts = ARRAY_SIZE(laguna_spi_partitions),
-+};
-+
-+static struct spi_board_info __initdata laguna_spi_devices[] = {
-+ {
-+ .modalias = "m25p80",
-+ .platform_data = &laguna_spi_pdata,
-+ .max_speed_hz = 50000000,
-+ .bus_num = 1,
-+ .chip_select = 0,
-+ },
-+};
-+
-+static struct platform_device laguna_spi_controller = {
-+ .name = "cns3xxx_spi",
-+};
-+
-+/*
-+ * LED's
-+ */
-+static struct gpio_led laguna_gpio_leds[] = {
-+ {
-+ .name = "user1", /* Green Led */
-+ .gpio = 115,
-+ .active_low = 1,
-+ },{
-+ .name = "user2", /* Red Led */
-+ .gpio = 114,
-+ .active_low = 1,
-+ },{
-+ .name = "pwr1", /* Green Led */
-+ .gpio = 116,
-+ .active_low = 1,
-+ },{
-+ .name = "pwr2", /* Yellow Led */
-+ .gpio = 117,
-+ .active_low = 1,
-+ },{
-+ .name = "txd1", /* Green Led */
-+ .gpio = 118,
-+ .active_low = 1,
-+ },{
-+ .name = "txd2", /* Yellow Led */
-+ .gpio = 119,
-+ .active_low = 1,
-+ },{
-+ .name = "rxd1", /* Green Led */
-+ .gpio = 120,
-+ .active_low = 1,
-+ },{
-+ .name = "rxd2", /* Yellow Led */
-+ .gpio = 121,
-+ .active_low = 1,
-+ },{
-+ .name = "ser1", /* Green Led */
-+ .gpio = 122,
-+ .active_low = 1,
-+ },{
-+ .name = "ser2", /* Yellow Led */
-+ .gpio = 123,
-+ .active_low = 1,
-+ },{
-+ .name = "enet1", /* Green Led */
-+ .gpio = 124,
-+ .active_low = 1,
-+ },{
-+ .name = "enet2", /* Yellow Led */
-+ .gpio = 125,
-+ .active_low = 1,
-+ },{
-+ .name = "sig1_1", /* Green Led */
-+ .gpio = 126,
-+ .active_low = 1,
-+ },{
-+ .name = "sig1_2", /* Yellow Led */
-+ .gpio = 127,
-+ .active_low = 1,
-+ },{
-+ .name = "sig2_1", /* Green Led */
-+ .gpio = 128,
-+ .active_low = 1,
-+ },{
-+ .name = "sig2_2", /* Yellow Led */
-+ .gpio = 129,
-+ .active_low = 1,
-+ },{
-+ .name = "sig3_1", /* Green Led */
-+ .gpio = 130,
-+ .active_low = 1,
-+ },{
-+ .name = "sig3_2", /* Yellow Led */
-+ .gpio = 131,
-+ .active_low = 1,
-+ },{
-+ .name = "net1", /*Green Led */
-+ .gpio = 109,
-+ .active_low = 1,
-+ },{
-+ .name = "net2", /* Red Led */
-+ .gpio = 110,
-+ .active_low = 1,
-+ },{
-+ .name = "mod1", /* Green Led */
-+ .gpio = 111,
-+ .active_low = 1,
-+ },{
-+ .name = "mod2", /* Red Led */
-+ .gpio = 112,
-+ .active_low = 1,
-+ },
-+};
-+
-+static struct gpio_led_platform_data laguna_gpio_leds_data = {
-+ .num_leds = 22,
-+ .leds = laguna_gpio_leds,
-+};
-+
-+static struct platform_device laguna_gpio_leds_device = {
-+ .name = "leds-gpio",
-+ .id = -1,
-+ .dev.platform_data = &laguna_gpio_leds_data,
-+};
-+
-+/*
-+ * Ethernet
-+ */
-+static struct cns3xxx_plat_info laguna_net_data = {
-+ .ports = 0,
-+ .phy = {
-+ 0,
-+ 1,
-+ 2,
-+ },
-+};
-+
-+static struct platform_device laguna_net_device = {
-+ .name = "cns3xxx_eth",
-+ .id = 0,
-+ .dev.platform_data = &laguna_net_data,
-+};
-+
-+/*
-+ * UART
-+ */
-+static void __init laguna_early_serial_setup(void)
-+{
-+#ifdef CONFIG_SERIAL_8250_CONSOLE
-+ static struct uart_port laguna_serial_port = {
-+ .membase = (void __iomem *)CNS3XXX_UART0_BASE_VIRT,
-+ .mapbase = CNS3XXX_UART0_BASE,
-+ .irq = IRQ_CNS3XXX_UART0,
-+ .iotype = UPIO_MEM,
-+ .flags = UPF_BOOT_AUTOCONF | UPF_FIXED_TYPE,
-+ .regshift = 2,
-+ .uartclk = 24000000,
-+ .line = 0,
-+ .type = PORT_16550A,
-+ .fifosize = 16,
-+ };
-+
-+ early_serial_setup(&laguna_serial_port);
-+#endif
-+}
-+
-+static struct resource laguna_uart_resources[] = {
-+ {
-+ .start = CNS3XXX_UART0_BASE,
-+ .end = CNS3XXX_UART0_BASE + SZ_4K - 1,
-+ .flags = IORESOURCE_MEM
-+ },{
-+ .start = CNS3XXX_UART2_BASE,
-+ .end = CNS3XXX_UART2_BASE + SZ_4K - 1,
-+ .flags = IORESOURCE_MEM
-+ },{
-+ .start = CNS3XXX_UART2_BASE,
-+ .end = CNS3XXX_UART2_BASE + SZ_4K - 1,
-+ .flags = IORESOURCE_MEM
-+ },
-+};
-+
-+static struct plat_serial8250_port laguna_uart_data[] = {
-+ {
-+ .membase = (char*) (CNS3XXX_UART0_BASE_VIRT),
-+ .mapbase = (CNS3XXX_UART0_BASE),
-+ .irq = IRQ_CNS3XXX_UART0,
-+ .iotype = UPIO_MEM,
-+ .flags = UPF_BOOT_AUTOCONF | UPF_FIXED_TYPE | UPF_NO_TXEN_TEST,
-+ .regshift = 2,
-+ .uartclk = 24000000,
-+ .type = PORT_16550A,
-+ },{
-+ .membase = (char*) (CNS3XXX_UART1_BASE_VIRT),
-+ .mapbase = (CNS3XXX_UART1_BASE),
-+ .irq = IRQ_CNS3XXX_UART1,
-+ .iotype = UPIO_MEM,
-+ .flags = UPF_BOOT_AUTOCONF | UPF_FIXED_TYPE | UPF_NO_TXEN_TEST,
-+ .regshift = 2,
-+ .uartclk = 24000000,
-+ .type = PORT_16550A,
-+ },{
-+ .membase = (char*) (CNS3XXX_UART2_BASE_VIRT),
-+ .mapbase = (CNS3XXX_UART2_BASE),
-+ .irq = IRQ_CNS3XXX_UART2,
-+ .iotype = UPIO_MEM,
-+ .flags = UPF_BOOT_AUTOCONF | UPF_FIXED_TYPE | UPF_NO_TXEN_TEST,
-+ .regshift = 2,
-+ .uartclk = 24000000,
-+ .type = PORT_16550A,
-+ },
-+ { },
-+};
-+
-+static struct platform_device laguna_uart = {
-+ .name = "serial8250",
-+ .id = PLAT8250_DEV_PLATFORM,
-+ .dev.platform_data = laguna_uart_data,
-+ .num_resources = 3,
-+ .resource = laguna_uart_resources
-+};
-+
-+/*
-+ * USB
-+ */
-+static struct resource cns3xxx_usb_ehci_resources[] = {
-+ [0] = {
-+ .start = CNS3XXX_USB_BASE,
-+ .end = CNS3XXX_USB_BASE + SZ_16M - 1,
-+ .flags = IORESOURCE_MEM,
-+ },
-+ [1] = {
-+ .start = IRQ_CNS3XXX_USB_EHCI,
-+ .flags = IORESOURCE_IRQ,
-+ },
-+};
-+
-+static u64 cns3xxx_usb_ehci_dma_mask = DMA_BIT_MASK(32);
-+
-+static struct platform_device cns3xxx_usb_ehci_device = {
-+ .name = "cns3xxx-ehci",
-+ .num_resources = ARRAY_SIZE(cns3xxx_usb_ehci_resources),
-+ .resource = cns3xxx_usb_ehci_resources,
-+ .dev = {
-+ .dma_mask = &cns3xxx_usb_ehci_dma_mask,
-+ .coherent_dma_mask = DMA_BIT_MASK(32),
-+ },
-+};
-+
-+static struct resource cns3xxx_usb_ohci_resources[] = {
-+ [0] = {
-+ .start = CNS3XXX_USB_OHCI_BASE,
-+ .end = CNS3XXX_USB_OHCI_BASE + SZ_16M - 1,
-+ .flags = IORESOURCE_MEM,
-+ },
-+ [1] = {
-+ .start = IRQ_CNS3XXX_USB_OHCI,
-+ .flags = IORESOURCE_IRQ,
-+ },
-+};
-+
-+static u64 cns3xxx_usb_ohci_dma_mask = DMA_BIT_MASK(32);
-+
-+static struct platform_device cns3xxx_usb_ohci_device = {
-+ .name = "cns3xxx-ohci",
-+ .num_resources = ARRAY_SIZE(cns3xxx_usb_ohci_resources),
-+ .resource = cns3xxx_usb_ohci_resources,
-+ .dev = {
-+ .dma_mask = &cns3xxx_usb_ohci_dma_mask,
-+ .coherent_dma_mask = DMA_BIT_MASK(32),
-+ },
-+};
-+
-+static struct resource cns3xxx_usb_otg_resources[] = {
-+ [0] = {
-+ .start = CNS3XXX_USBOTG_BASE,
-+ .end = CNS3XXX_USBOTG_BASE + SZ_16M - 1,
-+ .flags = IORESOURCE_MEM,
-+ },
-+ [1] = {
-+ .start = IRQ_CNS3XXX_USB_OTG,
-+ .flags = IORESOURCE_IRQ,
-+ },
-+};
-+
-+static u64 cns3xxx_usb_otg_dma_mask = DMA_BIT_MASK(32);
-+
-+static struct platform_device cns3xxx_usb_otg_device = {
-+ .name = "dwc_otg",
-+ .num_resources = ARRAY_SIZE(cns3xxx_usb_otg_resources),
-+ .resource = cns3xxx_usb_otg_resources,
-+ .dev = {
-+ .dma_mask = &cns3xxx_usb_otg_dma_mask,
-+ .coherent_dma_mask = DMA_BIT_MASK(32),
-+ },
-+};
-+
-+/*
-+ * I2C
-+ */
-+static struct resource laguna_i2c_resource[] = {
-+ {
-+ .start = CNS3XXX_SSP_BASE + 0x20,
-+ .end = 0x7100003f,
-+ .flags = IORESOURCE_MEM,
-+ },{
-+ .start = IRQ_CNS3XXX_I2C,
-+ .flags = IORESOURCE_IRQ,
-+ },
-+};
-+
-+static struct platform_device laguna_i2c_controller = {
-+ .name = "cns3xxx-i2c",
-+ .num_resources = 2,
-+ .resource = laguna_i2c_resource,
-+};
-+
-+static struct memory_accessor *at24_mem_acc;
-+
-+static void at24_setup(struct memory_accessor *mem_acc, void *context)
-+{
-+ char buf[16];
-+
-+ at24_mem_acc = mem_acc;
-+
-+ /* Read MAC addresses */
-+ if (at24_mem_acc->read(at24_mem_acc, buf, 0x100, 6) == 6)
-+ memcpy(&laguna_net_data.hwaddr[0], buf, ETH_ALEN);
-+ if (at24_mem_acc->read(at24_mem_acc, buf, 0x106, 6) == 6)
-+ memcpy(&laguna_net_data.hwaddr[1], buf, ETH_ALEN);
-+ if (at24_mem_acc->read(at24_mem_acc, buf, 0x10C, 6) == 6)
-+ memcpy(&laguna_net_data.hwaddr[2], buf, ETH_ALEN);
-+ if (at24_mem_acc->read(at24_mem_acc, buf, 0x112, 6) == 6)
-+ memcpy(&laguna_net_data.hwaddr[3], buf, ETH_ALEN);
-+
-+ /* Read out Model Information */
-+ if (at24_mem_acc->read(at24_mem_acc, buf, 0x130, 16) == 16)
-+ memcpy(&laguna_info.model, buf, 16);
-+ if (at24_mem_acc->read(at24_mem_acc, buf, 0x140, 1) == 1)
-+ memcpy(&laguna_info.nor_flash_size, buf, 1);
-+ if (at24_mem_acc->read(at24_mem_acc, buf, 0x141, 1) == 1)
-+ memcpy(&laguna_info.spi_flash_size, buf, 1);
-+ if (at24_mem_acc->read(at24_mem_acc, buf, 0x142, 4) == 4)
-+ memcpy(&laguna_info.config_bitmap, buf, 4);
-+ if (at24_mem_acc->read(at24_mem_acc, buf, 0x146, 4) == 4)
-+ memcpy(&laguna_info.config2_bitmap, buf, 4);
-+};
-+
-+static struct at24_platform_data laguna_eeprom_info = {
-+ .byte_len = 1024,
-+ .page_size = 16,
-+ .flags = AT24_FLAG_READONLY,
-+ .setup = at24_setup,
-+};
-+
-+static struct pca953x_platform_data laguna_pca_data = {
-+ .gpio_base = 100,
-+ .irq_base = -1,
-+};
-+
-+static struct pca953x_platform_data laguna_pca2_data = {
-+ .gpio_base = 116,
-+ .irq_base = -1,
-+};
-+
-+static struct i2c_board_info __initdata laguna_i2c_devices[] = {
-+ {
-+ I2C_BOARD_INFO("pca9555", 0x23),
-+ .platform_data = &laguna_pca_data,
-+ },{
-+ I2C_BOARD_INFO("pca9555", 0x27),
-+ .platform_data = &laguna_pca2_data,
-+ },{
-+ I2C_BOARD_INFO("gsp", 0x29),
-+ },{
-+ I2C_BOARD_INFO ("24c08",0x50),
-+ .platform_data = &laguna_eeprom_info,
-+ },{
-+ I2C_BOARD_INFO("ds1672", 0x68),
-+ },
-+};
-+
-+/*
-+ * Watchdog
-+ */
-+
-+static struct resource laguna_watchdog_resources[] = {
-+ [0] = {
-+ .start = CNS3XXX_TC11MP_TWD_BASE + 0x100, // CPU0 watchdog
-+ .end = CNS3XXX_TC11MP_TWD_BASE + SZ_4K - 1,
-+ .flags = IORESOURCE_MEM,
-+ },
-+ [1] = {
-+ .start = IRQ_LOCALWDOG,
-+ .end = IRQ_LOCALWDOG,
-+ .flags = IORESOURCE_IRQ,
-+ }
-+};
-+
-+static struct platform_device laguna_watchdog = {
-+ .name = "mpcore_wdt",
-+ .id = -1,
-+ .num_resources = ARRAY_SIZE(laguna_watchdog_resources),
-+ .resource = laguna_watchdog_resources,
-+};
-+
-+/*
-+ * GPIO
-+ */
-+
-+static struct gpio laguna_gpio_gw2391[] = {
-+ { 0, GPIOF_IN , "*GPS_PPS" },
-+ { 1, GPIOF_IN , "*GSC_IRQ#" },
-+ { 2, GPIOF_IN , "*USB_FAULT#" },
-+ { 5, GPIOF_OUT_INIT_LOW , "*USB0_PCI_SEL" },
-+ { 6, GPIOF_OUT_INIT_HIGH, "*USB_VBUS_EN" },
-+ { 7, GPIOF_OUT_INIT_LOW , "*USB1_PCI_SEL" },
-+ { 8, GPIOF_OUT_INIT_HIGH, "*PERST#" },
-+ { 9, GPIOF_OUT_INIT_LOW , "*FP_SER_EN#" },
-+ { 100, GPIOF_IN , "*USER_PB#" },
-+ { 103, GPIOF_OUT_INIT_HIGH, "*V5_EN" },
-+ { 108, GPIOF_IN , "DIO0" },
-+ { 109, GPIOF_IN , "DIO1" },
-+ { 110, GPIOF_IN , "DIO2" },
-+ { 111, GPIOF_IN , "DIO3" },
-+ { 112, GPIOF_IN , "DIO4" },
-+};
-+
-+static struct gpio laguna_gpio_gw2388[] = {
-+ { 0, GPIOF_IN , "*GPS_PPS" },
-+ { 1, GPIOF_IN , "*GSC_IRQ#" },
-+ { 3, GPIOF_IN , "*USB_FAULT#" },
-+ { 6, GPIOF_OUT_INIT_HIGH, "*USB_VBUS_EN" },
-+ { 7, GPIOF_OUT_INIT_LOW , "*GSM_SEL0" },
-+ { 8, GPIOF_OUT_INIT_LOW , "*GSM_SEL1" },
-+ { 9, GPIOF_OUT_INIT_LOW , "*FP_SER_EN" },
-+ { 100, GPIOF_OUT_INIT_HIGH, "*USER_PB#" },
-+ { 108, GPIOF_IN , "DIO0" },
-+ { 109, GPIOF_IN , "DIO1" },
-+ { 110, GPIOF_IN , "DIO2" },
-+ { 111, GPIOF_IN , "DIO3" },
-+ { 112, GPIOF_IN , "DIO4" },
-+};
-+
-+static struct gpio laguna_gpio_gw2387[] = {
-+ { 0, GPIOF_IN , "*GPS_PPS" },
-+ { 1, GPIOF_IN , "*GSC_IRQ#" },
-+ { 2, GPIOF_IN , "*USB_FAULT#" },
-+ { 5, GPIOF_OUT_INIT_LOW , "*USB_PCI_SEL" },
-+ { 6, GPIOF_OUT_INIT_HIGH, "*USB_VBUS_EN" },
-+ { 7, GPIOF_OUT_INIT_LOW , "*GSM_SEL0" },
-+ { 8, GPIOF_OUT_INIT_LOW , "*GSM_SEL1" },
-+ { 9, GPIOF_OUT_INIT_LOW , "*FP_SER_EN" },
-+ { 100, GPIOF_IN , "*USER_PB#" },
-+ { 103, GPIOF_OUT_INIT_HIGH, "*V5_EN" },
-+ { 108, GPIOF_IN , "DIO0" },
-+ { 109, GPIOF_IN , "DIO1" },
-+ { 110, GPIOF_IN , "DIO2" },
-+ { 111, GPIOF_IN , "DIO3" },
-+ { 112, GPIOF_IN , "DIO4" },
-+ { 113, GPIOF_IN , "DIO5" },
-+};
-+
-+static struct gpio laguna_gpio_gw2384[] = {
-+ { 0, GPIOF_IN , "*GSC_IRQ#" },
-+ { 1, GPIOF_OUT_INIT_HIGH, "*USB_HST_VBUS_EN" },
-+ { 2, GPIOF_IN , "*USB_HST_FAULT#" },
-+ { 5, GPIOF_IN , "*USB_OTG_FAULT#" },
-+ { 6, GPIOF_OUT_INIT_LOW , "*USB_HST_PCI_SEL" },
-+ { 7, GPIOF_OUT_INIT_LOW , "*GSM_SEL0" },
-+ { 8, GPIOF_OUT_INIT_LOW , "*GSM_SEL1" },
-+ { 9, GPIOF_OUT_INIT_LOW , "*FP_SER_EN" },
-+ { 12, GPIOF_OUT_INIT_LOW , "J10_DIOLED0" },
-+ { 13, GPIOF_OUT_INIT_HIGH, "*I2CMUX_RST#" },
-+ { 14, GPIOF_OUT_INIT_LOW , "J10_DIOLED1" },
-+ { 15, GPIOF_OUT_INIT_LOW , "J10_DIOLED2" },
-+ { 100, GPIOF_IN , "*USER_PB#" },
-+ { 103, GPIOF_OUT_INIT_HIGH, "V5_EN" },
-+ { 108, GPIOF_IN , "J9_DIOGSC0" },
-+};
-+
-+static struct gpio laguna_gpio_gw2383[] = {
-+ { 0, GPIOF_IN , "*GPS_PPS" },
-+ { 1, GPIOF_IN , "*GSC_IRQ#" },
-+ { 2, GPIOF_OUT_INIT_HIGH, "*PCIE_RST#" },
-+ { 3, GPIOF_IN , "GPIO0" },
-+ { 8, GPIOF_IN , "GPIO1" },
-+ { 100, GPIOF_IN , "DIO0" },
-+ { 101, GPIOF_IN , "DIO1" },
-+};
-+
-+static struct gpio laguna_gpio_gw2382[] = {
-+ { 0, GPIOF_IN , "*GPS_PPS" },
-+ { 1, GPIOF_IN , "*GSC_IRQ#" },
-+ { 2, GPIOF_OUT_INIT_HIGH, "*PCIE_RST#" },
-+ { 3, GPIOF_IN , "GPIO0" },
-+ { 4, GPIOF_IN , "GPIO1" },
-+ { 9, GPIOF_OUT_INIT_HIGH, "*USB_VBUS_EN" },
-+ { 10, GPIOF_OUT_INIT_HIGH, "*USB_PCI_SEL#" },
-+ { 100, GPIOF_IN , "DIO0" },
-+ { 101, GPIOF_IN , "DIO1" },
-+};
-+
-+static struct gpio laguna_gpio_gw2380[] = {
-+ { 0, GPIOF_IN , "*GPS_PPS" },
-+ { 1, GPIOF_IN , "*GSC_IRQ#" },
-+ { 3, GPIOF_IN , "GPIO0" },
-+ { 8, GPIOF_IN , "GPIO1" },
-+ { 100, GPIOF_IN , "DIO0" },
-+ { 101, GPIOF_IN , "DIO1" },
-+ { 102, GPIOF_IN , "DIO2" },
-+ { 103, GPIOF_IN , "DIO3" },
-+};
-+
-+/*
-+ * Initialization
-+ */
-+static void __init laguna_init(void)
-+{
-+ cns3xxx_l2x0_init();
-+
-+ platform_device_register(&laguna_watchdog);
-+
-+ platform_device_register(&laguna_i2c_controller);
-+
-+ i2c_register_board_info(0, ARRAY_AND_SIZE(laguna_i2c_devices));
-+
-+ pm_power_off = cns3xxx_power_off;
-+}
-+
-+static struct map_desc laguna_io_desc[] __initdata = {
-+ {
-+ .virtual = CNS3XXX_UART0_BASE_VIRT,
-+ .pfn = __phys_to_pfn(CNS3XXX_UART0_BASE),
-+ .length = SZ_4K,
-+ .type = MT_DEVICE,
-+ },{
-+ .virtual = CNS3XXX_UART1_BASE_VIRT,
-+ .pfn = __phys_to_pfn(CNS3XXX_UART1_BASE),
-+ .length = SZ_4K,
-+ .type = MT_DEVICE,
-+ },{
-+ .virtual = CNS3XXX_UART2_BASE_VIRT,
-+ .pfn = __phys_to_pfn(CNS3XXX_UART2_BASE),
-+ .length = SZ_4K,
-+ .type = MT_DEVICE,
-+ },
-+};
-+
-+static void __init laguna_map_io(void)
-+{
-+ cns3xxx_common_init();
-+ cns3xxx_pcie_iotable_init(0x3);
-+ iotable_init(ARRAY_AND_SIZE(laguna_io_desc));
-+ laguna_early_serial_setup();
-+}
-+
-+static int laguna_register_gpio(struct gpio *array, size_t num)
-+{
-+ int i, err, ret;
-+
-+ ret = 0;
-+ for (i = 0; i < num; i++, array++) {
-+ const char *label = array->label;
-+ if (label[0] == '*')
-+ label++;
-+ err = gpio_request_one(array->gpio, array->flags, label);
-+ if (err)
-+ ret = err;
-+ else {
-+ err = gpio_export(array->gpio, array->label[0] != '*');
-+ }
-+ }
-+ return ret;
-+}
-+
-+static int __init laguna_model_setup(void)
-+{
-+ u32 __iomem *mem;
-+ u32 reg;
-+ u8 pcie_bitmap = 0;
-+
-+ printk("Running on Gateworks Laguna %s\n", laguna_info.model);
-+
-+ if (strncmp(laguna_info.model, "GW", 2) == 0) {
-+ if (laguna_info.config_bitmap & ETH0_LOAD)
-+ laguna_net_data.ports |= BIT(0);
-+ if (laguna_info.config_bitmap & ETH1_LOAD)
-+ laguna_net_data.ports |= BIT(1);
-+ if (laguna_info.config_bitmap & ETH2_LOAD)
-+ laguna_net_data.ports |= BIT(2);
-+ if (laguna_net_data.ports)
-+ platform_device_register(&laguna_net_device);
-+
-+ if ((laguna_info.config_bitmap & SATA0_LOAD) ||
-+ (laguna_info.config_bitmap & SATA1_LOAD))
-+ cns3xxx_ahci_init();
-+
-+ if (laguna_info.config_bitmap & (PCIE0_LOAD))
-+ pcie_bitmap |= 0x1;
-+
-+ if (laguna_info.config_bitmap & (PCIE1_LOAD))
-+ pcie_bitmap |= 0x2;
-+
-+ cns3xxx_pcie_init(pcie_bitmap);
-+
-+ if (laguna_info.config_bitmap & (USB0_LOAD)) {
-+ cns3xxx_pwr_power_up(1 << PM_PLL_HM_PD_CTRL_REG_OFFSET_PLL_USB);
-+
-+ /* DRVVBUS pins share with GPIOA */
-+ mem = (void __iomem *)(CNS3XXX_MISC_BASE_VIRT + 0x0014);
-+ reg = __raw_readl(mem);
-+ reg |= 0x8;
-+ __raw_writel(reg, mem);
-+
-+ /* Enable OTG */
-+ mem = (void __iomem *)(CNS3XXX_MISC_BASE_VIRT + 0x0808);
-+ reg = __raw_readl(mem);
-+ reg &= ~(1 << 10);
-+ __raw_writel(reg, mem);
-+
-+ platform_device_register(&cns3xxx_usb_otg_device);
-+ }
-+
-+ if (laguna_info.config_bitmap & (USB1_LOAD)) {
-+ platform_device_register(&cns3xxx_usb_ehci_device);
-+ platform_device_register(&cns3xxx_usb_ohci_device);
-+ }
-+
-+ if (laguna_info.config_bitmap & (SD_LOAD))
-+ cns3xxx_sdhci_init();
-+
-+ if (laguna_info.config_bitmap & (UART0_LOAD))
-+ laguna_uart.num_resources = 1;
-+ if (laguna_info.config_bitmap & (UART1_LOAD))
-+ laguna_uart.num_resources = 2;
-+ if (laguna_info.config_bitmap & (UART2_LOAD))
-+ laguna_uart.num_resources = 3;
-+ platform_device_register(&laguna_uart);
-+
-+ if (laguna_info.config2_bitmap & (NOR_FLASH_LOAD)) {
-+ switch (laguna_info.nor_flash_size) {
-+ case 1:
-+ laguna_nor_partitions[3].size = SZ_8M - SZ_256K - SZ_128K - SZ_2M;
-+ laguna_nor_res.end = CNS3XXX_FLASH_BASE + SZ_8M - 1;
-+ break;
-+ case 2:
-+ laguna_nor_partitions[3].size = SZ_16M - SZ_256K - SZ_128K - SZ_2M;
-+ laguna_nor_res.end = CNS3XXX_FLASH_BASE + SZ_16M - 1;
-+ break;
-+ case 3:
-+ laguna_nor_partitions[3].size = SZ_32M - SZ_256K - SZ_128K - SZ_2M;
-+ laguna_nor_res.end = CNS3XXX_FLASH_BASE + SZ_32M - 1;
-+ break;
-+ case 4:
-+ laguna_nor_partitions[3].size = SZ_64M - SZ_256K - SZ_128K - SZ_2M;
-+ laguna_nor_res.end = CNS3XXX_FLASH_BASE + SZ_64M - 1;
-+ break;
-+ case 5:
-+ laguna_nor_partitions[3].size = SZ_128M - SZ_256K - SZ_128K - SZ_2M;
-+ laguna_nor_res.end = CNS3XXX_FLASH_BASE + SZ_128M - 1;
-+ break;
-+ }
-+ platform_device_register(&laguna_nor_pdev);
-+ }
-+
-+ if (laguna_info.config2_bitmap & (SPI_FLASH_LOAD)) {
-+ switch (laguna_info.spi_flash_size) {
-+ case 1:
-+ laguna_spi_partitions[3].size = SZ_4M - SZ_2M;
-+ break;
-+ case 2:
-+ laguna_spi_partitions[3].size = SZ_8M - SZ_2M;
-+ break;
-+ case 3:
-+ laguna_spi_partitions[3].size = SZ_16M - SZ_2M;
-+ break;
-+ case 4:
-+ laguna_spi_partitions[3].size = SZ_32M - SZ_2M;
-+ break;
-+ case 5:
-+ laguna_spi_partitions[3].size = SZ_64M - SZ_2M;
-+ break;
-+ }
-+ spi_register_board_info(ARRAY_AND_SIZE(laguna_spi_devices));
-+ }
-+
-+ if ((laguna_info.config_bitmap & SPI0_LOAD) ||
-+ (laguna_info.config_bitmap & SPI1_LOAD))
-+ platform_device_register(&laguna_spi_controller);
-+
-+ /*
-+ * Do any model specific setup not known by the bitmap by matching
-+ * the first 6 characters of the model name
-+ */
-+
-+ if ( (strncmp(laguna_info.model, "GW2388", 6) == 0)
-+ || (strncmp(laguna_info.model, "GW2389", 6) == 0) )
-+ {
-+ // configure GPIO's
-+ laguna_register_gpio(ARRAY_AND_SIZE(laguna_gpio_gw2388));
-+ // configure LED's
-+ laguna_gpio_leds_data.num_leds = 2;
-+ } else if (strncmp(laguna_info.model, "GW2387", 6) == 0) {
-+ // configure GPIO's
-+ laguna_register_gpio(ARRAY_AND_SIZE(laguna_gpio_gw2387));
-+ // configure LED's
-+ laguna_gpio_leds_data.num_leds = 2;
-+ } else if (strncmp(laguna_info.model, "GW2384", 6) == 0) {
-+ // configure GPIO's
-+ laguna_register_gpio(ARRAY_AND_SIZE(laguna_gpio_gw2384));
-+ // configure LED's
-+ laguna_gpio_leds_data.num_leds = 1;
-+ } else if (strncmp(laguna_info.model, "GW2383", 6) == 0) {
-+ // configure GPIO's
-+ laguna_register_gpio(ARRAY_AND_SIZE(laguna_gpio_gw2383));
-+ // configure LED's
-+ laguna_gpio_leds[0].gpio = 107;
-+ laguna_gpio_leds_data.num_leds = 1;
-+ } else if (strncmp(laguna_info.model, "GW2382", 6) == 0) {
-+ // configure GPIO's
-+ laguna_register_gpio(ARRAY_AND_SIZE(laguna_gpio_gw2382));
-+ // configure LED's
-+ laguna_gpio_leds[0].gpio = 107;
-+ laguna_gpio_leds_data.num_leds = 1;
-+ } else if (strncmp(laguna_info.model, "GW2380", 6) == 0) {
-+ // configure GPIO's
-+ laguna_register_gpio(ARRAY_AND_SIZE(laguna_gpio_gw2380));
-+ // configure LED's
-+ laguna_gpio_leds[0].gpio = 107;
-+ laguna_gpio_leds[1].gpio = 106;
-+ laguna_gpio_leds_data.num_leds = 2;
-+ } else if (strncmp(laguna_info.model, "GW2391", 6) == 0) {
-+ // configure GPIO's
-+ laguna_register_gpio(ARRAY_AND_SIZE(laguna_gpio_gw2391));
-+ // configure LED's
-+ laguna_gpio_leds_data.num_leds = 2;
-+ }
-+ platform_device_register(&laguna_gpio_leds_device);
-+ } else {
-+ // Do some defaults here, not sure what yet
-+ }
-+ return 0;
-+}
-+
-+late_initcall(laguna_model_setup);
-+
-+MACHINE_START(GW2388, "Gateworks Corporation Laguna Platform")
-+ .atag_offset = 0x100,
-+ .map_io = laguna_map_io,
-+ .init_irq = cns3xxx_init_irq,
-+ .timer = &cns3xxx_timer,
-+ .handle_irq = gic_handle_irq,
-+ .init_machine = laguna_init,
-+ .restart = cns3xxx_restart,
-+MACHINE_END
--- a/arch/arm/mach-cns3xxx/Kconfig
+++ b/arch/arm/mach-cns3xxx/Kconfig
@@ -11,4 +11,14 @@ config MACH_CNS3420VB
+++ /dev/null
---- a/arch/arm/mach-cns3xxx/platsmp.c
-+++ b/arch/arm/mach-cns3xxx/platsmp.c
-@@ -1,18 +1,17 @@
--/* linux/arch/arm/mach-cns3xxx/platsmp.c
-+/*
-+ * linux/arch/arm/mach-cns3xxx/platsmp.c
- *
-- * Copyright 2011 Gateworks Corporation
-+ * Copyright (C) 2002 ARM Ltd.
-+ * Copyright 2012 Gateworks Corporation
- * Chris Lang <clang@gateworks.com>
-+ * Tim Harvey <tharvey@gateworks.com>
- *
-- * Cloned from linux/arch/arm/mach-vexpress/platsmp.c
-- *
-- * Copyright (C) 2002 ARM Ltd.
- * All Rights Reserved
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
--*/
--
-+ */
- #include <linux/init.h>
- #include <linux/errno.h>
- #include <linux/delay.h>
-@@ -30,11 +29,13 @@
-
- extern void cns3xxx_secondary_startup(void);
-
-+#define SCU_CPU_STATUS 0x08
-+static void __iomem *scu_base;
-+
- /*
- * control for which core is the next to come out of the secondary
- * boot "holding pen"
- */
--
- volatile int __cpuinitdata pen_release = -1;
-
- /*
-@@ -50,11 +51,6 @@ static void write_pen_release(int val)
- outer_clean_range(__pa(&pen_release), __pa(&pen_release + 1));
- }
-
--static void __iomem *scu_base_addr(void)
--{
-- return (void __iomem *)(CNS3XXX_TC11MP_SCU_BASE_VIRT);
--}
--
- static DEFINE_SPINLOCK(boot_lock);
-
- void __cpuinit platform_secondary_init(unsigned int cpu)
-@@ -128,25 +124,24 @@ int __cpuinit boot_secondary(unsigned in
- * Initialise the CPU possible map early - this describes the CPUs
- * which may be present or become present in the system.
- */
--
- void __init smp_init_cpus(void)
- {
-- void __iomem *scu_base = scu_base_addr();
- unsigned int i, ncores;
-+ unsigned int status;
-
-- ncores = scu_base ? scu_get_core_count(scu_base) : 1;
-+ scu_base = (void __iomem *) CNS3XXX_TC11MP_SCU_BASE_VIRT;
-
-- /* sanity check */
-- if (ncores > NR_CPUS) {
-- printk(KERN_WARNING
-- "cns3xxx: no. of cores (%d) greater than configured "
-- "maximum of %d - clipping\n",
-- ncores, NR_CPUS);
-- ncores = NR_CPUS;
-+ /* for CNS3xxx SCU_CPU_STATUS must be examined instead of SCU_CONFIGURATION
-+ * used in scu_get_core_count
-+ */
-+ status = __raw_readl(scu_base + SCU_CPU_STATUS);
-+ for (i = 0; i < NR_CPUS+1; i++) {
-+ if (((status >> (i*2)) & 0x3) == 0)
-+ set_cpu_possible(i, true);
-+ else
-+ break;
- }
--
-- for (i = 0; i < ncores; i++)
-- set_cpu_possible(i, true);
-+ ncores = i;
-
- set_smp_cross_call(gic_raise_softirq);
- }
-@@ -159,10 +154,14 @@ void __init platform_smp_prepare_cpus(un
- * Initialise the present map, which describes the set of CPUs
- * actually populated at the present time.
- */
-- for (i = 0; i < max_cpus; i++)
-+ for (i = 0; i < max_cpus; i++) {
- set_cpu_present(i, true);
-+ }
-
-- scu_enable(scu_base_addr());
-+ /*
-+ * enable SCU
-+ */
-+ scu_enable(scu_base);
-
- /*
- * Write the address of secondary startup into the
+obj-$(CONFIG_SMP) += platsmp.o headsmp.o cns3xxx_fiq.o
obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o
obj-$(CONFIG_LOCAL_TIMERS) += localtimer.o
---- /dev/null
-+++ b/arch/arm/mach-cns3xxx/cns3xxx_fiq.S
-@@ -0,0 +1,96 @@
-+/*
-+ * Copyright (C) 2012 Gateworks Corporation
-+ * Chris Lang <clang@gateworks.com>
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License version 2 as
-+ * published by the Free Software Foundation.
-+ */
-+#include <linux/linkage.h>
-+#include <asm/assembler.h>
-+#include <asm/asm-offsets.h>
-+
-+#define D_CACHE_LINE_SIZE 32
-+
-+ .text
-+
-+/*
-+ * R8 - DMA Start Address
-+ * R9 - DMA Length
-+ * R10 - DMA Direction
-+ * R11 - DMA type
-+ * R12 - fiq_buffer Address
-+ * R13 - DMA type Address
-+*/
-+
-+ .global cns3xxx_fiq_end
-+ENTRY(cns3xxx_fiq_start)
-+ mov r8, #0
-+ str r8, [r13]
-+
-+ ldr r9, [r12]
-+ ldr r8, [r9]
-+ add r8, r8, #1
-+ str r8, [r9]
-+
-+ ldmib r12, {r8, r9, r10}
-+ and r11, r10, #0x3000000
-+ and r10, r10, #0xff
-+
-+ teq r11, #0x1000000
-+ beq cns3xxx_dma_map_area
-+ teq r11, #0x2000000
-+ beq cns3xxx_dma_unmap_area
-+ b cns3xxx_dma_flush_range
-+
-+cns3xxx_fiq_exit:
-+ mov r8, #0
-+ str r8, [r12, #12]
-+ mcr p15, 0, r8, c7, c10, 4 @ drain write buffer
-+ subs pc, lr, #4
-+
-+cns3xxx_dma_map_area:
-+ add r9, r9, r8
-+ teq r10, #DMA_FROM_DEVICE
-+ beq cns3xxx_dma_inv_range
-+ b cns3xxx_dma_clean_range
-+
-+cns3xxx_dma_unmap_area:
-+ add r9, r9, r8
-+ teq r10, #DMA_TO_DEVICE
-+ bne cns3xxx_dma_inv_range
-+ b cns3xxx_fiq_exit
-+
-+cns3xxx_dma_flush_range:
-+ bic r8, r8, #D_CACHE_LINE_SIZE - 1
-+1:
-+ mcr p15, 0, r8, c7, c14, 1 @ clean & invalidate D line
-+ add r8, r8, #D_CACHE_LINE_SIZE
-+ cmp r8, r9
-+ blo 1b
-+ b cns3xxx_fiq_exit
-+
-+cns3xxx_dma_clean_range:
-+ bic r8, r8, #D_CACHE_LINE_SIZE - 1
-+1:
-+ mcr p15, 0, r8, c7, c10, 1 @ clean D line
-+ add r8, r8, #D_CACHE_LINE_SIZE
-+ cmp r8, r9
-+ blo 1b
-+ b cns3xxx_fiq_exit
-+
-+cns3xxx_dma_inv_range:
-+ tst r8, #D_CACHE_LINE_SIZE - 1
-+ bic r8, r8, #D_CACHE_LINE_SIZE - 1
-+ mcrne p15, 0, r8, c7, c10, 1 @ clean D line
-+ tst r9, #D_CACHE_LINE_SIZE - 1
-+ bic r9, r9, #D_CACHE_LINE_SIZE - 1
-+ mcrne p15, 0, r9, c7, c14, 1 @ clean & invalidate D line
-+1:
-+ mcr p15, 0, r8, c7, c6, 1 @ invalidate D line
-+ add r8, r8, #D_CACHE_LINE_SIZE
-+ cmp r8, r9
-+ blo 1b
-+ b cns3xxx_fiq_exit
-+
-+cns3xxx_fiq_end:
--- a/arch/arm/mach-cns3xxx/include/mach/cns3xxx.h
+++ b/arch/arm/mach-cns3xxx/include/mach/cns3xxx.h
@@ -294,6 +294,7 @@
#include <mach/cns3xxx.h>
---- /dev/null
-+++ b/arch/arm/mach-cns3xxx/include/mach/smp.h
-@@ -0,0 +1,8 @@
-+#ifndef __MACH_SMP_H
-+#define __MACH_SMP_H
-+
-+extern void smp_dma_map_area(const void *, size_t, int);
-+extern void smp_dma_unmap_area(const void *, size_t, int);
-+extern void smp_dma_flush_range(const void *, const void *);
-+
-+#endif
---- a/arch/arm/mach-cns3xxx/platsmp.c
-+++ b/arch/arm/mach-cns3xxx/platsmp.c
-@@ -24,10 +24,27 @@
- #include <asm/hardware/gic.h>
- #include <asm/smp_scu.h>
- #include <asm/unified.h>
--
-+#include <asm/fiq.h>
-+#include <mach/smp.h>
- #include <mach/cns3xxx.h>
-
-+static struct fiq_handler fh = {
-+ .name = "cns3xxx-fiq"
-+};
-+
-+static unsigned int fiq_buffer[8];
-+
-+#define FIQ_ENABLED 0x80000000
-+#define FIQ_GENERATE 0x00010000
-+#define CNS3XXX_MAP_AREA 0x01000000
-+#define CNS3XXX_UNMAP_AREA 0x02000000
-+#define CNS3XXX_FLUSH_RANGE 0x03000000
-+
- extern void cns3xxx_secondary_startup(void);
-+extern unsigned char cns3xxx_fiq_start, cns3xxx_fiq_end;
-+extern unsigned int fiq_number[2];
-+extern struct cpu_cache_fns cpu_cache;
-+struct cpu_cache_fns cpu_cache_save;
-
- #define SCU_CPU_STATUS 0x08
- static void __iomem *scu_base;
-@@ -38,12 +55,50 @@ static void __iomem *scu_base;
- */
- volatile int __cpuinitdata pen_release = -1;
-
-+static void __init cns3xxx_set_fiq_regs(void)
-+{
-+ struct pt_regs FIQ_regs;
-+ unsigned int cpu = smp_processor_id();
-+
-+ if (cpu) {
-+ FIQ_regs.ARM_ip = (unsigned int)&fiq_buffer[4];
-+ FIQ_regs.ARM_sp = (unsigned int)MISC_FIQ_CPU(0);
-+ } else {
-+ FIQ_regs.ARM_ip = (unsigned int)&fiq_buffer[0];
-+ FIQ_regs.ARM_sp = (unsigned int)MISC_FIQ_CPU(1);
-+ }
-+ set_fiq_regs(&FIQ_regs);
-+}
-+
-+static void __init cns3xxx_init_fiq(void)
-+{
-+ void *fiqhandler_start;
-+ unsigned int fiqhandler_length;
-+ int ret;
-+
-+ fiqhandler_start = &cns3xxx_fiq_start;
-+ fiqhandler_length = &cns3xxx_fiq_end - &cns3xxx_fiq_start;
-+
-+ ret = claim_fiq(&fh);
-+
-+ if (ret) {
-+ return;
-+ }
-+
-+ set_fiq_handler(fiqhandler_start, fiqhandler_length);
-+ fiq_buffer[0] = (unsigned int)&fiq_number[0];
-+ fiq_buffer[3] = 0;
-+ fiq_buffer[4] = (unsigned int)&fiq_number[1];
-+ fiq_buffer[7] = 0;
-+}
-+
-+
- /*
- * Write pen_release in a way that is guaranteed to be visible to all
- * observers, irrespective of whether they're taking part in coherency
- * or not. This is necessary for the hotplug code to work reliably.
- */
--static void write_pen_release(int val)
-+static void __cpuinit write_pen_release(int val)
- {
- pen_release = val;
- smp_wmb();
-@@ -63,12 +118,25 @@ void __cpuinit platform_secondary_init(u
- gic_secondary_init(0);
-
- /*
-+ * Setup Secondary Core FIQ regs
-+ */
-+ cns3xxx_set_fiq_regs();
-+
-+ /*
- * let the primary processor know we're out of the
- * pen, then head off into the C entry point
- */
- write_pen_release(-1);
-
- /*
-+ * Fixup DMA Operations
-+ *
-+ */
-+ cpu_cache.dma_map_area = (void *)smp_dma_map_area;
-+ cpu_cache.dma_unmap_area = (void *)smp_dma_unmap_area;
-+ cpu_cache.dma_flush_range = (void *)smp_dma_flush_range;
-+
-+ /*
- * Synchronise with the boot thread.
- */
- spin_lock(&boot_lock);
-@@ -171,4 +239,112 @@ void __init platform_smp_prepare_cpus(un
- */
- __raw_writel(virt_to_phys(cns3xxx_secondary_startup),
- (void __iomem *)(CNS3XXX_MISC_BASE_VIRT + 0x0600));
-+
-+ /*
-+ * Setup FIQ's for main cpu
-+ */
-+ cns3xxx_init_fiq();
-+ cns3xxx_set_fiq_regs();
-+ memcpy((void *)&cpu_cache_save, (void *)&cpu_cache, sizeof(struct cpu_cache_fns));
-+}
-+
-+
-+static inline unsigned long cns3xxx_cpu_id(void)
-+{
-+ unsigned long cpu;
-+
-+ asm volatile(
-+ " mrc p15, 0, %0, c0, c0, 5 @ cns3xxx_cpu_id\n"
-+ : "=r" (cpu) : : "memory", "cc");
-+ return (cpu & 0xf);
-+}
-+
-+void smp_dma_map_area(const void *addr, size_t size, int dir)
-+{
-+ unsigned int cpu;
-+ unsigned long flags;
-+ raw_local_irq_save(flags);
-+ cpu = cns3xxx_cpu_id();
-+ if (cpu) {
-+ fiq_buffer[1] = (unsigned int)addr;
-+ fiq_buffer[2] = size;
-+ fiq_buffer[3] = dir | CNS3XXX_MAP_AREA | FIQ_ENABLED;
-+ smp_mb();
-+ __raw_writel(FIQ_GENERATE, MISC_FIQ_CPU(1));
-+
-+ cpu_cache_save.dma_map_area(addr, size, dir);
-+ while ((fiq_buffer[3]) & FIQ_ENABLED) { barrier(); }
-+ } else {
-+
-+ fiq_buffer[5] = (unsigned int)addr;
-+ fiq_buffer[6] = size;
-+ fiq_buffer[7] = dir | CNS3XXX_MAP_AREA | FIQ_ENABLED;
-+ smp_mb();
-+ __raw_writel(FIQ_GENERATE, MISC_FIQ_CPU(0));
-+
-+ cpu_cache_save.dma_map_area(addr, size, dir);
-+ while ((fiq_buffer[7]) & FIQ_ENABLED) { barrier(); }
-+ }
-+ raw_local_irq_restore(flags);
-+}
-+
-+void smp_dma_unmap_area(const void *addr, size_t size, int dir)
-+{
-+ unsigned int cpu;
-+ unsigned long flags;
-+
-+ raw_local_irq_save(flags);
-+ cpu = cns3xxx_cpu_id();
-+ if (cpu) {
-+
-+ fiq_buffer[1] = (unsigned int)addr;
-+ fiq_buffer[2] = size;
-+ fiq_buffer[3] = dir | CNS3XXX_UNMAP_AREA | FIQ_ENABLED;
-+ smp_mb();
-+ __raw_writel(FIQ_GENERATE, MISC_FIQ_CPU(1));
-+
-+ cpu_cache_save.dma_unmap_area(addr, size, dir);
-+ while ((fiq_buffer[3]) & FIQ_ENABLED) { barrier(); }
-+ } else {
-+
-+ fiq_buffer[5] = (unsigned int)addr;
-+ fiq_buffer[6] = size;
-+ fiq_buffer[7] = dir | CNS3XXX_UNMAP_AREA | FIQ_ENABLED;
-+ smp_mb();
-+ __raw_writel(FIQ_GENERATE, MISC_FIQ_CPU(0));
-+
-+ cpu_cache_save.dma_unmap_area(addr, size, dir);
-+ while ((fiq_buffer[7]) & FIQ_ENABLED) { barrier(); }
-+ }
-+ raw_local_irq_restore(flags);
-+}
-+
-+void smp_dma_flush_range(const void *start, const void *end)
-+{
-+ unsigned int cpu;
-+ unsigned long flags;
-+ raw_local_irq_save(flags);
-+ cpu = cns3xxx_cpu_id();
-+ if (cpu) {
-+
-+ fiq_buffer[1] = (unsigned int)start;
-+ fiq_buffer[2] = (unsigned int)end;
-+ fiq_buffer[3] = CNS3XXX_FLUSH_RANGE | FIQ_ENABLED;
-+ smp_mb();
-+ __raw_writel(FIQ_GENERATE, MISC_FIQ_CPU(1));
-+
-+ cpu_cache_save.dma_flush_range(start, end);
-+ while ((fiq_buffer[3]) & FIQ_ENABLED) { barrier(); }
-+ } else {
-+
-+ fiq_buffer[5] = (unsigned int)start;
-+ fiq_buffer[6] = (unsigned int)end;
-+ fiq_buffer[7] = CNS3XXX_FLUSH_RANGE | FIQ_ENABLED;
-+ smp_mb();
-+ __raw_writel(FIQ_GENERATE, MISC_FIQ_CPU(0));
-+
-+ cpu_cache_save.dma_flush_range(start, end);
-+ while ((fiq_buffer[7]) & FIQ_ENABLED) { barrier(); }
-+ }
-+ raw_local_irq_restore(flags);
- }
--- a/arch/arm/mm/Kconfig
+++ b/arch/arm/mm/Kconfig
@@ -793,7 +793,7 @@ config NEEDS_SYSCALL_FOR_CMPXCHG
}
/* used by entry-macro.S */
---- /dev/null
-+++ b/arch/arm/mach-cns3xxx/gpio.c
-@@ -0,0 +1,277 @@
-+/*
-+ * Copyright 2012 Gateworks Corporation
-+ * Chris Lang <clang@gateworks.com>
-+ * Tim Harvey <tharvey@gateworks.com>
-+ *
-+ * This file is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License, Version 2, as
-+ * published by the Free Software Foundation.
-+ */
-+
-+#include <linux/module.h>
-+#include <linux/init.h>
-+#include <linux/interrupt.h>
-+#include <linux/io.h>
-+#include <linux/gpio.h>
-+#include <linux/irq.h>
-+
-+#include <asm/mach/irq.h>
-+
-+/*
-+ * Registers
-+ */
-+#define GPIO_INPUT 0x04
-+#define GPIO_DIR 0x08
-+#define GPIO_SET 0x10
-+#define GPIO_CLEAR 0x14
-+#define GPIO_INTERRUPT_ENABLE 0x20
-+#define GPIO_INTERRUPT_RAW_STATUS 0x24
-+#define GPIO_INTERRUPT_MASKED_STATUS 0x28
-+#define GPIO_INTERRUPT_MASK 0x2C
-+#define GPIO_INTERRUPT_CLEAR 0x30
-+#define GPIO_INTERRUPT_TRIGGER_METHOD 0x34
-+#define GPIO_INTERRUPT_TRIGGER_BOTH_EDGES 0x38
-+#define GPIO_INTERRUPT_TRIGGER_TYPE 0x3C
-+
-+#define GPIO_INTERRUPT_TRIGGER_METHOD_EDGE 0
-+#define GPIO_INTERRUPT_TRIGGER_METHOD_LEVEL 1
-+#define GPIO_INTERRUPT_TRIGGER_EDGE_SINGLE 0
-+#define GPIO_INTERRUPT_TRIGGER_EDGE_BOTH 1
-+#define GPIO_INTERRUPT_TRIGGER_TYPE_RISING 0
-+#define GPIO_INTERRUPT_TRIGGER_TYPE_FALLING 1
-+#define GPIO_INTERRUPT_TRIGGER_TYPE_HIGH 0
-+#define GPIO_INTERRUPT_TRIGGER_TYPE_LOW 1
-+
-+struct cns3xxx_gpio_chip {
-+ struct gpio_chip chip;
-+ spinlock_t lock;
-+ void __iomem *base;
-+ int secondary_irq_base;
-+};
-+
-+static struct cns3xxx_gpio_chip cns3xxx_gpio_chips[2];
-+static int cns3xxx_gpio_chip_count;
-+
-+static inline void
-+__set_direction(struct cns3xxx_gpio_chip *cchip, unsigned pin, int input)
-+{
-+ u32 reg;
-+
-+ reg = __raw_readl(cchip->base + GPIO_DIR);
-+ if (input)
-+ reg |= 1 << pin;
-+ else
-+ reg &= !(1 << pin);
-+ __raw_writel(reg, cchip->base + GPIO_DIR);
-+}
-+
-+/*
-+ * GENERIC_GPIO primatives
-+ */
-+static int cns3xxx_gpio_direction_input(struct gpio_chip *chip, unsigned pin)
-+{
-+ struct cns3xxx_gpio_chip *cchip =
-+ container_of(chip, struct cns3xxx_gpio_chip, chip);
-+ unsigned long flags;
-+
-+ spin_lock_irqsave(&cchip->lock, flags);
-+ __set_direction(cchip, pin, 1);
-+ spin_unlock_irqrestore(&cchip->lock, flags);
-+
-+ return 0;
-+}
-+
-+static int cns3xxx_gpio_get(struct gpio_chip *chip, unsigned pin)
-+{
-+ struct cns3xxx_gpio_chip *cchip =
-+ container_of(chip, struct cns3xxx_gpio_chip, chip);
-+ int val;
-+
-+ val = ((__raw_readl(cchip->base + GPIO_INPUT) >> pin) & 0x1);
-+
-+ return val;
-+}
-+
-+static int cns3xxx_gpio_direction_output(struct gpio_chip *chip, unsigned pin, int level)
-+{
-+ struct cns3xxx_gpio_chip *cchip =
-+ container_of(chip, struct cns3xxx_gpio_chip, chip);
-+ unsigned long flags;
-+
-+ spin_lock_irqsave(&cchip->lock, flags);
-+ if (level)
-+ __raw_writel(1 << pin, cchip->base + GPIO_SET);
-+ else
-+ __raw_writel(1 << pin, cchip->base + GPIO_CLEAR);
-+ __set_direction(cchip, pin, 0);
-+ spin_unlock_irqrestore(&cchip->lock, flags);
-+
-+ return 0;
-+}
-+
-+static void cns3xxx_gpio_set(struct gpio_chip *chip, unsigned pin,
-+ int level)
-+{
-+ struct cns3xxx_gpio_chip *cchip =
-+ container_of(chip, struct cns3xxx_gpio_chip, chip);
-+
-+ if (level)
-+ __raw_writel(1 << pin, cchip->base + GPIO_SET);
-+ else
-+ __raw_writel(1 << pin, cchip->base + GPIO_CLEAR);
-+}
-+
-+static int cns3xxx_gpio_to_irq(struct gpio_chip *chip, unsigned pin)
-+{
-+ struct cns3xxx_gpio_chip *cchip =
-+ container_of(chip, struct cns3xxx_gpio_chip, chip);
-+
-+ return cchip->secondary_irq_base + pin;
-+}
-+
-+
-+/*
-+ * IRQ support
-+ */
-+
-+/* one interrupt per GPIO controller (GPIOA/GPIOB)
-+ * this is called in task context, with IRQs enabled
-+ */
-+static void cns3xxx_gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
-+{
-+ struct cns3xxx_gpio_chip *cchip = irq_get_handler_data(irq);
-+ struct irq_chip *chip = irq_get_chip(irq);
-+ struct irq_chip_generic *gc = irq_desc_get_chip_data(desc);
-+ struct irq_chip_type *ct = gc->chip_types;
-+ u16 i;
-+ u32 reg;
-+
-+ chained_irq_enter(chip, desc); /* mask and ack the base interrupt */
-+
-+ /* see which pin(s) triggered the interrupt */
-+ reg = __raw_readl(cchip->base + GPIO_INTERRUPT_RAW_STATUS);
-+ for (i = 0; i < 32; i++) {
-+ if (reg & (1 << i)) {
-+ /* let the generic IRQ layer handle an interrupt */
-+ generic_handle_irq(cchip->secondary_irq_base + i);
-+ }
-+ }
-+
-+ chained_irq_exit(chip, desc); /* unmask the base interrupt */
-+}
-+
-+static int cns3xxx_gpio_irq_set_type(struct irq_data *d, u32 irqtype)
-+{
-+ struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
-+ struct cns3xxx_gpio_chip *cchip = gc->private;
-+ u32 gpio = d->irq - cchip->secondary_irq_base;
-+ unsigned long flags;
-+ u32 method, edges, type;
-+
-+ spin_lock_irqsave(&cchip->lock, flags);
-+ method = __raw_readl(cchip->base + GPIO_INTERRUPT_TRIGGER_METHOD);
-+ edges = __raw_readl(cchip->base + GPIO_INTERRUPT_TRIGGER_BOTH_EDGES);
-+ type = __raw_readl(cchip->base + GPIO_INTERRUPT_TRIGGER_TYPE);
-+ method &= ~(1 << gpio);
-+ edges &= ~(1 << gpio);
-+ type &= ~(1 << gpio);
-+
-+ switch(irqtype) {
-+ case IRQ_TYPE_EDGE_RISING:
-+ method |= (GPIO_INTERRUPT_TRIGGER_METHOD_EDGE << gpio);
-+ edges |= (GPIO_INTERRUPT_TRIGGER_EDGE_SINGLE << gpio);
-+ type |= (GPIO_INTERRUPT_TRIGGER_TYPE_RISING << gpio);
-+ break;
-+ case IRQ_TYPE_EDGE_FALLING:
-+ method |= (GPIO_INTERRUPT_TRIGGER_METHOD_EDGE << gpio);
-+ edges |= (GPIO_INTERRUPT_TRIGGER_EDGE_SINGLE << gpio);
-+ type |= (GPIO_INTERRUPT_TRIGGER_TYPE_FALLING << gpio);
-+ break;
-+ case IRQ_TYPE_EDGE_BOTH:
-+ method |= (GPIO_INTERRUPT_TRIGGER_METHOD_EDGE << gpio);
-+ edges |= (GPIO_INTERRUPT_TRIGGER_EDGE_BOTH << gpio);
-+ break;
-+ case IRQ_TYPE_LEVEL_LOW:
-+ method |= (GPIO_INTERRUPT_TRIGGER_METHOD_LEVEL << gpio);
-+ type |= (GPIO_INTERRUPT_TRIGGER_TYPE_LOW << gpio);
-+ break;
-+ case IRQ_TYPE_LEVEL_HIGH:
-+ method |= (GPIO_INTERRUPT_TRIGGER_METHOD_LEVEL << gpio);
-+ type |= (GPIO_INTERRUPT_TRIGGER_TYPE_HIGH << gpio);
-+ break;
-+ default:
-+ printk(KERN_WARNING "No irq type\n");
-+ spin_unlock_irqrestore(&cchip->lock, flags);
-+ return -EINVAL;
-+ }
-+
-+ __raw_writel(method, cchip->base + GPIO_INTERRUPT_TRIGGER_METHOD);
-+ __raw_writel(edges, cchip->base + GPIO_INTERRUPT_TRIGGER_BOTH_EDGES);
-+ __raw_writel(type, cchip->base + GPIO_INTERRUPT_TRIGGER_TYPE);
-+ spin_unlock_irqrestore(&cchip->lock, flags);
-+
-+ if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH))
-+ __irq_set_handler_locked(d->irq, handle_level_irq);
-+ else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
-+ __irq_set_handler_locked(d->irq, handle_edge_irq);
-+
-+ return 0;
-+}
-+
-+void __init cns3xxx_gpio_init(int gpio_base, int ngpio,
-+ u32 base, int irq, int secondary_irq_base)
-+{
-+ struct cns3xxx_gpio_chip *cchip;
-+ struct irq_chip_generic *gc;
-+ struct irq_chip_type *ct;
-+ char gc_label[16];
-+
-+ if (cns3xxx_gpio_chip_count == ARRAY_SIZE(cns3xxx_gpio_chips))
-+ return;
-+
-+ snprintf(gc_label, sizeof(gc_label), "cns3xxx_gpio%d",
-+ cns3xxx_gpio_chip_count);
-+
-+ cchip = cns3xxx_gpio_chips + cns3xxx_gpio_chip_count;
-+ cchip->chip.label = kstrdup(gc_label, GFP_KERNEL);
-+ cchip->chip.direction_input = cns3xxx_gpio_direction_input;
-+ cchip->chip.get = cns3xxx_gpio_get;
-+ cchip->chip.direction_output = cns3xxx_gpio_direction_output;
-+ cchip->chip.set = cns3xxx_gpio_set;
-+ cchip->chip.to_irq = cns3xxx_gpio_to_irq;
-+ cchip->chip.base = gpio_base;
-+ cchip->chip.ngpio = ngpio;
-+ cchip->chip.can_sleep = 0;
-+ spin_lock_init(&cchip->lock);
-+ cchip->base = (void __iomem *)base;
-+ cchip->secondary_irq_base = secondary_irq_base;
-+
-+ BUG_ON(gpiochip_add(&cchip->chip) < 0);
-+ cns3xxx_gpio_chip_count++;
-+
-+ /* clear GPIO interrupts */
-+ __raw_writel(0xffff, cchip->base + GPIO_INTERRUPT_CLEAR);
-+
-+ /*
-+ * IRQ chip init
-+ */
-+ gc = irq_alloc_generic_chip("cns3xxx_gpio_irq", 1, secondary_irq_base,
-+ cchip->base, handle_edge_irq);
-+ gc->private = cchip;
-+
-+ ct = gc->chip_types;
-+ ct->type = IRQ_TYPE_EDGE_FALLING;
-+ ct->regs.ack = GPIO_INTERRUPT_CLEAR;
-+ ct->regs.enable = GPIO_INTERRUPT_ENABLE;
-+ ct->chip.irq_ack = irq_gc_ack_set_bit;
-+ ct->chip.irq_enable = irq_gc_unmask_enable_reg;
-+ ct->chip.irq_disable = irq_gc_mask_disable_reg;
-+ ct->chip.irq_set_type = cns3xxx_gpio_irq_set_type;
-+ ct->handler = handle_edge_irq;
-+
-+ irq_setup_generic_chip(gc, IRQ_MSK(ngpio), IRQ_GC_INIT_MASK_CACHE,
-+ IRQ_NOREQUEST, 0);
-+
-+ irq_set_chained_handler(irq, cns3xxx_gpio_irq_handler);
-+ irq_set_handler_data(irq, cchip);
-+}
---- a/arch/arm/mach-cns3xxx/include/mach/gpio.h
-+++ b/arch/arm/mach-cns3xxx/include/mach/gpio.h
-@@ -1,98 +1,17 @@
- /*
- * arch/arm/mach-cns3xxx/include/mach/gpio.h
- *
-- * CNS3xxx GPIO wrappers for arch-neutral GPIO calls
-- *
-- * Copyright 2011 Gateworks Corporation
-- * Chris Lang <clang@gateworks.com>
-- *
-- * Based on IXP implementation by Milan Svoboda <msvoboda@ra.rockwell.com>
-- * Based on PXA implementation by Philipp Zabel <philipp.zabel@gmail.com>
-- *
-- * This program is free software; you can redistribute it and/or modify
-- * it under the terms of the GNU General Public License as published by
-- * the Free Software Foundation; either version 2 of the License, or
-- * (at your option) any later version.
-- *
-- * This program is distributed in the hope that it will be useful,
-- * but WITHOUT ANY WARRANTY; without even the implied warranty of
-- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- * GNU General Public License for more details.
-- *
-- * You should have received a copy of the GNU General Public License
-- * along with this program; if not, write to the Free Software
-- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-+ * This file is licensed under the terms of the GNU General Public
-+ * License version 2. This program is licensed "as is" without any
-+ * warranty of any kind, whether express or implied.
- *
- */
--
- #ifndef __ASM_ARCH_CNS3XXX_GPIO_H
- #define __ASM_ARCH_CNS3XXX_GPIO_H
-
- #include <linux/kernel.h>
--#include <linux/io.h>
--#include <mach/platform.h>
--#include <asm-generic/gpio.h> /* cansleep wrappers */
--
--#define NR_BUILTIN_GPIO 64
--
--#define CNS3XXX_GPIO_IN 0x0
--#define CNS3XXX_GPIO_OUT 0x1
--
--#define CNS3XXX_GPIO_LO 0
--#define CNS3XXX_GPIO_HI 1
--
--#define CNS3XXX_GPIO_OUTPUT 0x00
--#define CNS3XXX_GPIO_INPUT 0x04
--#define CNS3XXX_GPIO_DIR 0x08
--#define CNS3XXX_GPIO_SET 0x10
--#define CNS3XXX_GPIO_CLEAR 0x14
--
--static inline void gpio_line_get(u8 line, int *value)
--{
-- if (line < 32)
-- *value = ((__raw_readl(CNS3XXX_GPIOA_BASE_VIRT + CNS3XXX_GPIO_INPUT) >> line) & 0x1);
-- else
-- *value = ((__raw_readl(CNS3XXX_GPIOB_BASE_VIRT + CNS3XXX_GPIO_INPUT) >> (line - 32)) & 0x1);
--}
--
--static inline void gpio_line_set(u8 line, int value)
--{
-- if (line < 32) {
-- if (value)
-- __raw_writel((1 << line), CNS3XXX_GPIOA_BASE_VIRT + CNS3XXX_GPIO_SET);
-- else
-- __raw_writel((1 << line), CNS3XXX_GPIOA_BASE_VIRT + CNS3XXX_GPIO_CLEAR);
-- } else {
-- if (value)
-- __raw_writel((1 << line), CNS3XXX_GPIOB_BASE_VIRT + CNS3XXX_GPIO_SET);
-- else
-- __raw_writel((1 << line), CNS3XXX_GPIOB_BASE_VIRT + CNS3XXX_GPIO_CLEAR);
-- }
--}
--
--static inline int gpio_get_value(unsigned gpio)
--{
-- if (gpio < NR_BUILTIN_GPIO)
-- {
-- int value;
-- gpio_line_get(gpio, &value);
-- return value;
-- }
-- else
-- return __gpio_get_value(gpio);
--}
--
--static inline void gpio_set_value(unsigned gpio, int value)
--{
-- if (gpio < NR_BUILTIN_GPIO)
-- gpio_line_set(gpio, value);
-- else
-- __gpio_set_value(gpio, value);
--}
--
--#define gpio_cansleep __gpio_cansleep
-
--extern int gpio_to_irq(int gpio);
--extern int irq_to_gpio(int gpio);
-+extern void __init cns3xxx_gpio_init(int gpio_base, int ngpio,
-+ u32 base, int irq, int secondary_irq_base);
-
- #endif
---- a/arch/arm/mach-cns3xxx/laguna.c
-+++ b/arch/arm/mach-cns3xxx/laguna.c
-@@ -45,6 +45,7 @@
- #include <mach/irqs.h>
- #include <mach/platform.h>
- #include <mach/pm.h>
-+#include <mach/gpio.h>
- #include <asm/hardware/gic.h>
- #include "core.h"
- #include "devices.h"
-@@ -759,6 +760,10 @@ static int __init laguna_model_setup(voi
- u8 pcie_bitmap = 0;
-
- printk("Running on Gateworks Laguna %s\n", laguna_info.model);
-+ cns3xxx_gpio_init( 0, 32, CNS3XXX_GPIOA_BASE_VIRT, IRQ_CNS3XXX_GPIOA,
-+ NR_IRQS_CNS3XXX);
-+ cns3xxx_gpio_init(32, 32, CNS3XXX_GPIOB_BASE_VIRT, IRQ_CNS3XXX_GPIOB,
-+ NR_IRQS_CNS3XXX + 32);
-
- if (strncmp(laguna_info.model, "GW", 2) == 0) {
- if (laguna_info.config_bitmap & ETH0_LOAD)
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -366,7 +366,8 @@ config ARCH_CLPS711X
void cns3xxx_power_off(void);
void cns3xxx_restart(char, const char *);
---- a/arch/arm/mach-cns3xxx/laguna.c
-+++ b/arch/arm/mach-cns3xxx/laguna.c
-@@ -729,7 +731,7 @@ static struct map_desc laguna_io_desc[]
- static void __init laguna_map_io(void)
- {
- cns3xxx_common_init();
-- cns3xxx_pcie_iotable_init(0x3);
-+ cns3xxx_pcie_iotable_init();
- iotable_init(ARRAY_AND_SIZE(laguna_io_desc));
- laguna_early_serial_setup();
- }
-@@ -753,11 +755,19 @@ static int laguna_register_gpio(struct g
- return ret;
- }
-
-+static int __init laguna_pcie_init(void)
-+{
-+ if (!machine_is_gw2388())
-+ return 0;
-+
-+ return cns3xxx_pcie_init();
-+}
-+subsys_initcall(laguna_pcie_init);
-+
- static int __init laguna_model_setup(void)
- {
- u32 __iomem *mem;
- u32 reg;
-- u8 pcie_bitmap = 0;
-
- printk("Running on Gateworks Laguna %s\n", laguna_info.model);
- cns3xxx_gpio_init( 0, 32, CNS3XXX_GPIOA_BASE_VIRT, IRQ_CNS3XXX_GPIOA,
-@@ -779,14 +789,6 @@ static int __init laguna_model_setup(voi
- (laguna_info.config_bitmap & SATA1_LOAD))
- cns3xxx_ahci_init();
-
-- if (laguna_info.config_bitmap & (PCIE0_LOAD))
-- pcie_bitmap |= 0x1;
--
-- if (laguna_info.config_bitmap & (PCIE1_LOAD))
-- pcie_bitmap |= 0x2;
--
-- cns3xxx_pcie_init(pcie_bitmap);
--
- if (laguna_info.config_bitmap & (USB0_LOAD)) {
- cns3xxx_pwr_power_up(1 << PM_PLL_HM_PD_CTRL_REG_OFFSET_PLL_USB);
-
-@@ -926,7 +928,6 @@ static int __init laguna_model_setup(voi
- }
- return 0;
- }
--
- late_initcall(laguna_model_setup);
-
- MACHINE_START(GW2388, "Gateworks Corporation Laguna Platform")
--- a/arch/arm/mach-cns3xxx/pcie.c
+++ b/arch/arm/mach-cns3xxx/pcie.c
@@ -456,23 +456,18 @@ static int cns3xxx_pcie_abort_handler(un
projects / openwrt.git / commitdiff