#define ADMHCD_INTMASK 0x00000001 /* Interrupt mask */
#define ADMHCD_REG_HOSTCONTROL 0x10
#define ADMHCD_DMA_EN 0x00000004 /* USB host DMA enable */
#define ADMHCD_INTMASK 0x00000001 /* Interrupt mask */
#define ADMHCD_REG_HOSTCONTROL 0x10
#define ADMHCD_DMA_EN 0x00000004 /* USB host DMA enable */
+#define ADMHCD_STATE_MASK 0x00000003
#define ADMHCD_STATE_RST 0x00000000 /* bus state reset */
#define ADMHCD_STATE_RES 0x00000001 /* bus state resume */
#define ADMHCD_STATE_OP 0x00000002 /* bus state operational */
#define ADMHCD_STATE_RST 0x00000000 /* bus state reset */
#define ADMHCD_STATE_RES 0x00000001 /* bus state resume */
#define ADMHCD_STATE_OP 0x00000002 /* bus state operational */
static int admhcd_reset(struct usb_hcd *hcd)
{
struct admhcd *ahcd = hcd_to_admhcd(hcd);
static int admhcd_reset(struct usb_hcd *hcd)
{
struct admhcd *ahcd = hcd_to_admhcd(hcd);
int ret, timeout = 15; /* ms */
unsigned long t;
int ret, timeout = 15; /* ms */
unsigned long t;
return ret;
t = jiffies + msecs_to_jiffies(timeout);
return ret;
t = jiffies + msecs_to_jiffies(timeout);
- while (time_before_eq(jiffies, t)) {
- msleep(4);
spin_lock_irq(&ahcd->lock);
spin_lock_irq(&ahcd->lock);
- val = admhcd_reg_get(ahcd, ADMHCD_REG_HOSTCONTROL) & ADMHCD_STATE_RST;
+ state = admhcd_reg_get(ahcd, ADMHCD_REG_HOSTCONTROL);
spin_unlock_irq(&ahcd->lock);
spin_unlock_irq(&ahcd->lock);
+ state &= ADMHCD_STATE_MASK;
+ if (state == ADMHCD_STATE_RST)
+ msleep(4);
+ } while (time_before_eq(jiffies, t));
+
+ if (state != ADMHCD_STATE_RST) {
printk(KERN_WARNING "%s: device not ready after %dms\n",
hcd_name, timeout);
ret = -ENODEV;
}
printk(KERN_WARNING "%s: device not ready after %dms\n",
hcd_name, timeout);
ret = -ENODEV;
}