ipq806x: fix pcie tx0-term-offset setting
authornbd <nbd@3c298f89-4303-0410-b956-a3cf2f4a3e73>
Sat, 21 Nov 2015 10:54:53 +0000 (10:54 +0000)
committernbd <nbd@3c298f89-4303-0410-b956-a3cf2f4a3e73>
Sat, 21 Nov 2015 10:54:53 +0000 (10:54 +0000)
Signed-off-by: Felix Fietkau <nbd@openwrt.org>
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@47543 3c298f89-4303-0410-b956-a3cf2f4a3e73

target/linux/ipq806x/patches-3.18/112-ARM-dts-qcom-add-pcie-nodes-to-ipq806x-platforms.patch
target/linux/ipq806x/patches-3.18/165-arm-qcom-dts-Enable-NAND-node-on-IPQ8064-AP148-platform.patch
target/linux/ipq806x/patches-3.18/166-arch-qcom-dts-enable-qcom-smem-on-AP148-NAND.patch
target/linux/ipq806x/patches-3.18/707-ARM-dts-qcom-add-mdio-nodes-to-ap148-db149.patch
target/linux/ipq806x/patches-3.18/708-ARM-dts-qcom-add-gmac-nodes-to-ipq806x-platforms.patch
target/linux/ipq806x/patches-4.1/112-ARM-dts-qcom-add-pcie-nodes-to-ipq806x-platforms.patch
target/linux/ipq806x/patches-4.1/165-arm-qcom-dts-Enable-NAND-node-on-IPQ8064-AP148-platform.patch
target/linux/ipq806x/patches-4.1/166-arch-qcom-dts-enable-qcom-smem-on-AP148-NAND.patch
target/linux/ipq806x/patches-4.1/707-ARM-dts-qcom-add-mdio-nodes-to-ap148-db149.patch
target/linux/ipq806x/patches-4.1/708-ARM-dts-qcom-add-gmac-nodes-to-ipq806x-platforms.patch

index 4c53d50..b2abe10 100644 (file)
@@ -40,7 +40,7 @@ Signed-off-by: Mathieu Olivari <mathieu@codeaurora.org>
                        spi_pins: spi_pins {
                                mux {
                                        pins = "gpio18", "gpio19", "gpio21";
-@@ -115,5 +133,19 @@
+@@ -115,5 +133,21 @@
                usb30@1 {
                        status = "ok";
                };
@@ -50,6 +50,7 @@ Signed-off-by: Mathieu Olivari <mathieu@codeaurora.org>
 +                      reset-gpio = <&qcom_pinmux 3 0>;
 +                      pinctrl-0 = <&pcie0_pins>;
 +                      pinctrl-names = "default";
++                      phy-tx0-term-offset = <7>;
 +              };
 +
 +              pcie1: pci@1b700000 {
@@ -57,6 +58,7 @@ Signed-off-by: Mathieu Olivari <mathieu@codeaurora.org>
 +                      reset-gpio = <&qcom_pinmux 48 0>;
 +                      pinctrl-0 = <&pcie1_pins>;
 +                      pinctrl-names = "default";
++                      phy-tx0-term-offset = <7>;
 +              };
        };
  };
index d62564c..7456b82 100644 (file)
@@ -57,9 +57,9 @@ arch/arm/boot/dts/qcom-ipq8064-ap148.dts | 36 ++++++++++++++++++++++++++++++++
                };
  
                gsbi@16300000 {
-@@ -147,5 +172,19 @@
-                       pinctrl-0 = <&pcie1_pins>;
+@@ -149,5 +174,19 @@
                        pinctrl-names = "default";
+                       phy-tx0-term-offset = <7>;
                };
 +
 +              nand@1ac00000 {
index cae7f15..926ee0b 100644 (file)
@@ -1,6 +1,6 @@
 --- a/arch/arm/boot/dts/qcom-ipq8064-ap148.dts
 +++ b/arch/arm/boot/dts/qcom-ipq8064-ap148.dts
-@@ -181,6 +181,8 @@
+@@ -183,6 +183,8 @@
  
                        nand-ecc-strength = <4>;
                        nand-bus-width = <8>;
index fe28942..9e3a965 100644 (file)
@@ -38,7 +38,7 @@ Signed-off-by: Mathieu Olivari <mathieu@codeaurora.org>
                };
  
                gsbi@16300000 {
-@@ -184,6 +194,34 @@
+@@ -186,6 +196,34 @@
  
                        linux,part-probe = "qcom-smem";
                };
index 3455d45..d580f77 100644 (file)
@@ -29,7 +29,7 @@ Signed-off-by: Mathieu Olivari <mathieu@codeaurora.org>
                };
  
                gsbi@16300000 {
-@@ -222,6 +232,27 @@
+@@ -224,6 +234,27 @@
                                reg = <4>;
                        };
                };
index 3fbcc39..d80bc8f 100644 (file)
@@ -40,7 +40,7 @@ Signed-off-by: Mathieu Olivari <mathieu@codeaurora.org>
                        spi_pins: spi_pins {
                                mux {
                                        pins = "gpio18", "gpio19", "gpio21";
-@@ -91,5 +109,19 @@
+@@ -91,5 +109,21 @@
                sata@29000000 {
                        status = "ok";
                };
@@ -50,6 +50,7 @@ Signed-off-by: Mathieu Olivari <mathieu@codeaurora.org>
 +                      reset-gpio = <&qcom_pinmux 3 0>;
 +                      pinctrl-0 = <&pcie0_pins>;
 +                      pinctrl-names = "default";
++                      phy-tx0-term-offset = <7>;
 +              };
 +
 +              pcie1: pci@1b700000 {
@@ -57,6 +58,7 @@ Signed-off-by: Mathieu Olivari <mathieu@codeaurora.org>
 +                      reset-gpio = <&qcom_pinmux 48 0>;
 +                      pinctrl-0 = <&pcie1_pins>;
 +                      pinctrl-names = "default";
++                      phy-tx0-term-offset = <7>;
 +              };
        };
  };
index 415bf30..cb726fa 100644 (file)
@@ -54,9 +54,9 @@ arch/arm/boot/dts/qcom-ipq8064-ap148.dts | 36 ++++++++++++++++++++++++++++++++
                };
  
                gsbi@16300000 {
-@@ -123,5 +145,19 @@
-                       pinctrl-0 = <&pcie1_pins>;
+@@ -125,5 +147,19 @@
                        pinctrl-names = "default";
+                       phy-tx0-term-offset = <7>;
                };
 +
 +              nand@1ac00000 {
index 16df418..46c7e92 100644 (file)
@@ -1,6 +1,6 @@
 --- a/arch/arm/boot/dts/qcom-ipq8064-ap148.dts
 +++ b/arch/arm/boot/dts/qcom-ipq8064-ap148.dts
-@@ -154,6 +154,8 @@
+@@ -156,6 +156,8 @@
  
                        nand-ecc-strength = <4>;
                        nand-bus-width = <8>;
index 0e2b305..03fb5d9 100644 (file)
@@ -38,7 +38,7 @@ Signed-off-by: Mathieu Olivari <mathieu@codeaurora.org>
                };
  
                gsbi@16300000 {
-@@ -157,6 +167,34 @@
+@@ -159,6 +169,34 @@
  
                        linux,part-probe = "qcom-smem";
                };
index 0918634..bb4b3b2 100644 (file)
@@ -29,7 +29,7 @@ Signed-off-by: Mathieu Olivari <mathieu@codeaurora.org>
                };
  
                gsbi@16300000 {
-@@ -195,6 +205,27 @@
+@@ -197,6 +207,27 @@
                                reg = <4>;
                        };
                };