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8da664f)
Some u-boot versions for QCA955x set currently not cleared bits depending
on the used link speed. This breaks the rx/tx under OpenWrt. The mach-*.c
file is responsible to select the correct configuration bits and thus the
ath79_setup_qca955x_eth_cfg has to clear the unset.
Signed-off-by: Sven Eckelmann <sven.eckelmann@open-mesh.com>
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@49028
3c298f89-4303-0410-b956-
a3cf2f4a3e73
void __init ath79_setup_qca955x_eth_cfg(u32 mask)
{
void __iomem *base;
void __init ath79_setup_qca955x_eth_cfg(u32 mask)
{
void __iomem *base;
+ u32 t, m;
+
+ m = QCA955X_ETH_CFG_RGMII_EN |
+ QCA955X_ETH_CFG_MII_GE0 |
+ QCA955X_ETH_CFG_GMII_GE0 |
+ QCA955X_ETH_CFG_MII_GE0_MASTER |
+ QCA955X_ETH_CFG_MII_GE0_SLAVE |
+ QCA955X_ETH_CFG_GE0_ERR_EN |
+ QCA955X_ETH_CFG_GE0_SGMII |
+ QCA955X_ETH_CFG_RMII_GE0 |
+ QCA955X_ETH_CFG_MII_CNTL_SPEED |
+ QCA955X_ETH_CFG_RMII_GE0_MASTER;
base = ioremap(QCA955X_GMAC_BASE, QCA955X_GMAC_SIZE);
t = __raw_readl(base + QCA955X_GMAC_REG_ETH_CFG);
base = ioremap(QCA955X_GMAC_BASE, QCA955X_GMAC_SIZE);
t = __raw_readl(base + QCA955X_GMAC_REG_ETH_CFG);
- t &= ~(QCA955X_ETH_CFG_RGMII_EN | QCA955X_ETH_CFG_GE0_SGMII);
-
t |= mask;
__raw_writel(t, base + QCA955X_GMAC_REG_ETH_CFG);
t |= mask;
__raw_writel(t, base + QCA955X_GMAC_REG_ETH_CFG);