toolchain/binutils/patches/2.20.1/700-avr32.patch

   1 --- a/bfd/archures.c
   2 +++ b/bfd/archures.c
   3 @@ -368,6 +368,12 @@ DESCRIPTION
   4  .#define bfd_mach_avr5         5
   5  .#define bfd_mach_avr51                51
   6  .#define bfd_mach_avr6         6
   7 +.  bfd_arch_avr32,     {* Atmel AVR32 *}
   8 +.#define bfd_mach_avr32_ap     7000
   9 +.#define bfd_mach_avr32_uc     3000
  10 +.#define bfd_mach_avr32_ucr1    3001
  11 +.#define bfd_mach_avr32_ucr2    3002
  12 +.#define bfd_mach_avr32_ucr3    3003
  13  .  bfd_arch_bfin,        {* ADI Blackfin *}
  14  .#define bfd_mach_bfin          1
  15  .  bfd_arch_cr16,       {* National Semiconductor CompactRISC (ie CR16). *}
  16 @@ -465,6 +471,7 @@ extern const bfd_arch_info_type bfd_alph
  17  extern const bfd_arch_info_type bfd_arc_arch;
  18  extern const bfd_arch_info_type bfd_arm_arch;
  19  extern const bfd_arch_info_type bfd_avr_arch;
  20 +extern const bfd_arch_info_type bfd_avr32_arch;
  21  extern const bfd_arch_info_type bfd_bfin_arch;
  22  extern const bfd_arch_info_type bfd_cr16_arch;
  23  extern const bfd_arch_info_type bfd_cr16c_arch;
  24 @@ -541,6 +548,7 @@ static const bfd_arch_info_type * const
  25      &bfd_arc_arch,
  26      &bfd_arm_arch,
  27      &bfd_avr_arch,
  28 +    &bfd_avr32_arch,
  29      &bfd_bfin_arch,
  30      &bfd_cr16_arch,
  31      &bfd_cr16c_arch,
  32 --- a/bfd/config.bfd
  33 +++ b/bfd/config.bfd
  34 @@ -347,6 +347,10 @@ case "${targ}" in
  35      targ_underscore=yes
  36      ;;
  37
  38 +  avr32-*-*)
  39 +    targ_defvec=bfd_elf32_avr32_vec
  40 +    ;;
  41 +
  42    c30-*-*aout* | tic30-*-*aout*)
  43      targ_defvec=tic30_aout_vec
  44      ;;
  45 --- a/bfd/configure.in
  46 +++ b/bfd/configure.in
  47 @@ -675,6 +675,7 @@ do
  48      bfd_pei_ia64_vec)          tb="$tb pei-ia64.lo pepigen.lo cofflink.lo"; target_size=64 ;;
  49      bfd_elf32_am33lin_vec)     tb="$tb elf32-am33lin.lo elf32.lo $elf" ;;
  50      bfd_elf32_avr_vec)         tb="$tb elf32-avr.lo elf32.lo $elf" ;;
  51 +    bfd_elf32_avr32_vec)       tb="$tb elf32-avr32.lo elf32.lo $elf" ;;
  52      bfd_elf32_bfin_vec)                tb="$tb elf32-bfin.lo elf32.lo $elf" ;;
  53      bfd_elf32_bfinfdpic_vec)   tb="$tb elf32-bfin.lo elf32.lo $elf" ;;
  54      bfd_elf32_big_generic_vec)         tb="$tb elf32-gen.lo elf32.lo $elf" ;;
  55 --- /dev/null
  56 +++ b/bfd/cpu-avr32.c
  57 @@ -0,0 +1,52 @@
  58 +/* BFD library support routines for AVR32.
  59 +   Copyright 2003,2004,2005,2006,2007,2008,2009 Atmel Corporation.
  60 +
  61 +   Written by Haavard Skinnemoen, Atmel Norway, <hskinnemoen@atmel.com>
  62 +
  63 +   This is part of BFD, the Binary File Descriptor library.
  64 +
  65 +   This program is free software; you can redistribute it and/or modify
  66 +   it under the terms of the GNU General Public License as published by
  67 +   the Free Software Foundation; either version 2 of the License, or
  68 +   (at your option) any later version.
  69 +
  70 +   This program is distributed in the hope that it will be useful,
  71 +   but WITHOUT ANY WARRANTY; without even the implied warranty of
  72 +   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  73 +   GNU General Public License for more details.
  74 +
  75 +   You should have received a copy of the GNU General Public License
  76 +   along with this program; if not, write to the Free Software
  77 +   Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
  78 +
  79 +#include "bfd.h"
  80 +#include "sysdep.h"
  81 +#include "libbfd.h"
  82 +
  83 +#define N(machine, print, default, next)                       \
  84 +  {                                                            \
  85 +    32,                                /* 32 bits in a word */         \
  86 +    32,                                /* 32 bits in an address */     \
  87 +    8,                         /* 8 bits in a byte */          \
  88 +    bfd_arch_avr32,            /* architecture */              \
  89 +    machine,                   /* machine */                   \
  90 +    "avr32",                   /* arch name */                 \
  91 +    print,                     /* printable name */            \
  92 +    1,                         /* section align power */       \
  93 +    default,                   /* the default machine? */      \
  94 +    bfd_default_compatible,                                    \
  95 +    bfd_default_scan,                                          \
  96 +    next,                                                      \
  97 +  }
  98 +
  99 +static const bfd_arch_info_type cpu_info[] =
 100 +{
 101 +  N(bfd_mach_avr32_ap, "avr32:ap", FALSE, &cpu_info[1]),
 102 +  N(bfd_mach_avr32_uc, "avr32:uc", FALSE, &cpu_info[2]),
 103 +  N(bfd_mach_avr32_ucr1, "avr32:ucr1", FALSE, &cpu_info[3]),
 104 +  N(bfd_mach_avr32_ucr2, "avr32:ucr2", FALSE, &cpu_info[4]),
 105 +  N(bfd_mach_avr32_ucr3, "avr32:ucr3", FALSE, NULL),
 106 +};
 107 +
 108 +const bfd_arch_info_type bfd_avr32_arch =
 109 +  N(bfd_mach_avr32_ap, "avr32", TRUE, &cpu_info[0]);
 110 --- /dev/null
 111 +++ b/bfd/elf32-avr32.c
 112 @@ -0,0 +1,3915 @@
 113 +/* AVR32-specific support for 32-bit ELF.
 114 +   Copyright 2003,2004,2005,2006,2007,2008,2009 Atmel Corporation.
 115 +
 116 +   Written by Haavard Skinnemoen, Atmel Norway, <hskinnemoen@atmel.com>
 117 +
 118 +   This file is part of BFD, the Binary File Descriptor library.
 119 +
 120 +   This program is free software; you can redistribute it and/or modify
 121 +   it under the terms of the GNU General Public License as published by
 122 +   the Free Software Foundation; either version 2 of the License, or
 123 +   (at your option) any later version.
 124 +
 125 +   This program is distributed in the hope that it will be useful,
 126 +   but WITHOUT ANY WARRANTY; without even the implied warranty of
 127 +   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 128 +   GNU General Public License for more details.
 129 +
 130 +   You should have received a copy of the GNU General Public License
 131 +   along with this program; if not, write to the Free Software
 132 +   Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
 133 +
 134 +#include "bfd.h"
 135 +#include "sysdep.h"
 136 +#include "bfdlink.h"
 137 +#include "libbfd.h"
 138 +#include "elf-bfd.h"
 139 +#include "elf/avr32.h"
 140 +#include "elf32-avr32.h"
 141 +
 142 +#define xDEBUG
 143 +#define xRELAX_DEBUG
 144 +
 145 +#ifdef DEBUG
 146 +# define pr_debug(fmt, args...) fprintf(stderr, fmt, ##args)
 147 +#else
 148 +# define pr_debug(fmt, args...) do { } while (0)
 149 +#endif
 150 +
 151 +#ifdef RELAX_DEBUG
 152 +# define RDBG(fmt, args...) fprintf(stderr, fmt, ##args)
 153 +#else
 154 +# define RDBG(fmt, args...) do { } while (0)
 155 +#endif
 156 +
 157 +/* When things go wrong, we want it to blow up, damnit! */
 158 +#undef BFD_ASSERT
 159 +#undef abort
 160 +#define BFD_ASSERT(expr)                                       \
 161 +  do                                                           \
 162 +    {                                                          \
 163 +      if (!(expr))                                             \
 164 +       {                                                       \
 165 +         bfd_assert(__FILE__, __LINE__);                       \
 166 +         abort();                                              \
 167 +       }                                                       \
 168 +    }                                                          \
 169 +  while (0)
 170 +
 171 +/* The name of the dynamic interpreter. This is put in the .interp section. */
 172 +#define ELF_DYNAMIC_INTERPRETER                "/lib/ld.so.1"
 173 +
 174 +#define AVR32_GOT_HEADER_SIZE          8
 175 +#define AVR32_FUNCTION_STUB_SIZE       8
 176 +
 177 +#define ELF_R_INFO(x, y) ELF32_R_INFO(x, y)
 178 +#define ELF_R_TYPE(x) ELF32_R_TYPE(x)
 179 +#define ELF_R_SYM(x) ELF32_R_SYM(x)
 180 +
 181 +#define NOP_OPCODE 0xd703
 182 +
 183 +
 184 +/* Mapping between BFD relocations and ELF relocations */
 185 +
 186 +static reloc_howto_type *
 187 +bfd_elf32_bfd_reloc_type_lookup(bfd *abfd, bfd_reloc_code_real_type code);
 188 +
 189 +static reloc_howto_type *
 190 +bfd_elf32_bfd_reloc_name_lookup(bfd *abfd, const char *r_name);
 191 +
 192 +static void
 193 +avr32_info_to_howto (bfd *abfd, arelent *cache_ptr, Elf_Internal_Rela *dst);
 194 +
 195 +/* Generic HOWTO */
 196 +#define GENH(name, align, size, bitsize, pcrel, bitpos, complain, mask)        \
 197 +  HOWTO(name, align, size, bitsize, pcrel, bitpos,                     \
 198 +       complain_overflow_##complain, bfd_elf_generic_reloc, #name,     \
 199 +       FALSE, 0, mask, pcrel)
 200 +
 201 +static reloc_howto_type elf_avr32_howto_table[] = {
 202 +  /*   NAME             ALN SZ BSZ PCREL  BP COMPLAIN  MASK        */
 203 +  GENH(R_AVR32_NONE,     0, 0, 0,  FALSE, 0, dont,     0x00000000),
 204 +
 205 +  GENH(R_AVR32_32,       0, 2, 32, FALSE, 0, dont,     0xffffffff),
 206 +  GENH(R_AVR32_16,       0, 1, 16, FALSE, 0, bitfield, 0x0000ffff),
 207 +  GENH(R_AVR32_8,        0, 0,  8, FALSE, 0, bitfield, 0x000000ff),
 208 +  GENH(R_AVR32_32_PCREL,  0, 2, 32, TRUE,  0, signed,   0xffffffff),
 209 +  GENH(R_AVR32_16_PCREL,  0, 1, 16, TRUE,  0, signed,   0x0000ffff),
 210 +  GENH(R_AVR32_8_PCREL,          0, 0,  8, TRUE,  0, signed,   0x000000ff),
 211 +
 212 +  /* Difference between two symbol (sym2 - sym1).  The reloc encodes
 213 +     the value of sym1.  The field contains the difference before any
 214 +     relaxing is done.  */
 215 +  GENH(R_AVR32_DIFF32,   0, 2, 32, FALSE, 0, dont,     0xffffffff),
 216 +  GENH(R_AVR32_DIFF16,   0, 1, 16, FALSE, 0, signed,   0x0000ffff),
 217 +  GENH(R_AVR32_DIFF8,    0, 0,  8, FALSE, 0, signed,   0x000000ff),
 218 +
 219 +  GENH(R_AVR32_GOT32,    0, 2, 32, FALSE, 0, signed,   0xffffffff),
 220 +  GENH(R_AVR32_GOT16,    0, 1, 16, FALSE, 0, signed,   0x0000ffff),
 221 +  GENH(R_AVR32_GOT8,     0, 0,  8, FALSE, 0, signed,   0x000000ff),
 222 +
 223 +  GENH(R_AVR32_21S,      0, 2, 21, FALSE, 0, signed,   0x1e10ffff),
 224 +  GENH(R_AVR32_16U,      0, 2, 16, FALSE, 0, unsigned, 0x0000ffff),
 225 +  GENH(R_AVR32_16S,      0, 2, 16, FALSE, 0, signed,   0x0000ffff),
 226 +  GENH(R_AVR32_8S,       0, 1,  8, FALSE, 4, signed,   0x00000ff0),
 227 +  GENH(R_AVR32_8S_EXT,   0, 2,  8, FALSE, 0, signed,   0x000000ff),
 228 +
 229 +  GENH(R_AVR32_22H_PCREL, 1, 2, 21, TRUE,  0, signed,  0x1e10ffff),
 230 +  GENH(R_AVR32_18W_PCREL, 2, 2, 16, TRUE,  0, signed,  0x0000ffff),
 231 +  GENH(R_AVR32_16B_PCREL, 0, 2, 16, TRUE,  0, signed,  0x0000ffff),
 232 +  GENH(R_AVR32_16N_PCREL, 0, 2, 16, TRUE,  0, signed,  0x0000ffff),
 233 +  GENH(R_AVR32_14UW_PCREL, 2, 2, 12, TRUE, 0, unsigned, 0x0000f0ff),
 234 +  GENH(R_AVR32_11H_PCREL, 1, 1, 10, TRUE,  4, signed,  0x00000ff3),
 235 +  GENH(R_AVR32_10UW_PCREL, 2, 2, 8, TRUE,  0, unsigned, 0x000000ff),
 236 +  GENH(R_AVR32_9H_PCREL,  1, 1,  8, TRUE,  4, signed,  0x00000ff0),
 237 +  GENH(R_AVR32_9UW_PCREL, 2, 1,  7, TRUE,  4, unsigned,        0x000007f0),
 238 +
 239 +  GENH(R_AVR32_HI16,    16, 2, 16, FALSE, 0, dont,     0x0000ffff),
 240 +  GENH(R_AVR32_LO16,     0, 2, 16, FALSE, 0, dont,     0x0000ffff),
 241 +
 242 +  GENH(R_AVR32_GOTPC,    0, 2, 32, FALSE, 0, dont,     0xffffffff),
 243 +  GENH(R_AVR32_GOTCALL,   2, 2, 21, FALSE, 0, signed,  0x1e10ffff),
 244 +  GENH(R_AVR32_LDA_GOT,          2, 2, 21, FALSE, 0, signed,   0x1e10ffff),
 245 +  GENH(R_AVR32_GOT21S,   0, 2, 21, FALSE, 0, signed,   0x1e10ffff),
 246 +  GENH(R_AVR32_GOT18SW,          2, 2, 16, FALSE, 0, signed,   0x0000ffff),
 247 +  GENH(R_AVR32_GOT16S,   0, 2, 16, FALSE, 0, signed,   0x0000ffff),
 248 +  GENH(R_AVR32_GOT7UW,   2, 1,  5, FALSE, 4, unsigned, 0x000001f0),
 249 +
 250 +  GENH(R_AVR32_32_CPENT,  0, 2, 32, FALSE, 0, dont,    0xffffffff),
 251 +  GENH(R_AVR32_CPCALL,   2, 2, 16, TRUE,  0, signed,   0x0000ffff),
 252 +  GENH(R_AVR32_16_CP,    0, 2, 16, TRUE,  0, signed,   0x0000ffff),
 253 +  GENH(R_AVR32_9W_CP,    2, 1,  7, TRUE,  4, unsigned, 0x000007f0),
 254 +
 255 +  GENH(R_AVR32_RELATIVE,  0, 2, 32, FALSE, 0, signed,  0xffffffff),
 256 +  GENH(R_AVR32_GLOB_DAT,  0, 2, 32, FALSE, 0, dont,    0xffffffff),
 257 +  GENH(R_AVR32_JMP_SLOT,  0, 2, 32, FALSE, 0, dont,    0xffffffff),
 258 +
 259 +  GENH(R_AVR32_ALIGN,    0, 1, 0,  FALSE, 0, unsigned, 0x00000000),
 260 +
 261 +  GENH(R_AVR32_15S,      2, 2, 15, FALSE, 0, signed,   0x00007fff),
 262 +};
 263 +
 264 +struct elf_reloc_map
 265 +{
 266 +  bfd_reloc_code_real_type bfd_reloc_val;
 267 +  unsigned char elf_reloc_val;
 268 +};
 269 +
 270 +static const struct elf_reloc_map avr32_reloc_map[] =
 271 +{
 272 +  { BFD_RELOC_NONE,                    R_AVR32_NONE },
 273 +
 274 +  { BFD_RELOC_32,                      R_AVR32_32 },
 275 +  { BFD_RELOC_16,                      R_AVR32_16 },
 276 +  { BFD_RELOC_8,                       R_AVR32_8 },
 277 +  { BFD_RELOC_32_PCREL,                        R_AVR32_32_PCREL },
 278 +  { BFD_RELOC_16_PCREL,                        R_AVR32_16_PCREL },
 279 +  { BFD_RELOC_8_PCREL,                 R_AVR32_8_PCREL },
 280 +  { BFD_RELOC_AVR32_DIFF32,            R_AVR32_DIFF32 },
 281 +  { BFD_RELOC_AVR32_DIFF16,            R_AVR32_DIFF16 },
 282 +  { BFD_RELOC_AVR32_DIFF8,             R_AVR32_DIFF8 },
 283 +  { BFD_RELOC_AVR32_GOT32,             R_AVR32_GOT32 },
 284 +  { BFD_RELOC_AVR32_GOT16,             R_AVR32_GOT16 },
 285 +  { BFD_RELOC_AVR32_GOT8,              R_AVR32_GOT8 },
 286 +
 287 +  { BFD_RELOC_AVR32_21S,               R_AVR32_21S },
 288 +  { BFD_RELOC_AVR32_16U,               R_AVR32_16U },
 289 +  { BFD_RELOC_AVR32_16S,               R_AVR32_16S },
 290 +  { BFD_RELOC_AVR32_SUB5,              R_AVR32_16S },
 291 +  { BFD_RELOC_AVR32_8S_EXT,            R_AVR32_8S_EXT },
 292 +  { BFD_RELOC_AVR32_8S,                        R_AVR32_8S },
 293 +
 294 +  { BFD_RELOC_AVR32_22H_PCREL,         R_AVR32_22H_PCREL },
 295 +  { BFD_RELOC_AVR32_18W_PCREL,         R_AVR32_18W_PCREL },
 296 +  { BFD_RELOC_AVR32_16B_PCREL,         R_AVR32_16B_PCREL },
 297 +  { BFD_RELOC_AVR32_16N_PCREL,         R_AVR32_16N_PCREL },
 298 +  { BFD_RELOC_AVR32_11H_PCREL,         R_AVR32_11H_PCREL },
 299 +  { BFD_RELOC_AVR32_10UW_PCREL,                R_AVR32_10UW_PCREL },
 300 +  { BFD_RELOC_AVR32_9H_PCREL,          R_AVR32_9H_PCREL },
 301 +  { BFD_RELOC_AVR32_9UW_PCREL,         R_AVR32_9UW_PCREL },
 302 +
 303 +  { BFD_RELOC_HI16,                    R_AVR32_HI16 },
 304 +  { BFD_RELOC_LO16,                    R_AVR32_LO16 },
 305 +
 306 +  { BFD_RELOC_AVR32_GOTPC,             R_AVR32_GOTPC },
 307 +  { BFD_RELOC_AVR32_GOTCALL,           R_AVR32_GOTCALL },
 308 +  { BFD_RELOC_AVR32_LDA_GOT,           R_AVR32_LDA_GOT },
 309 +  { BFD_RELOC_AVR32_GOT21S,            R_AVR32_GOT21S },
 310 +  { BFD_RELOC_AVR32_GOT18SW,           R_AVR32_GOT18SW },
 311 +  { BFD_RELOC_AVR32_GOT16S,            R_AVR32_GOT16S },
 312 +  /* GOT7UW should never be generated by the assembler */
 313 +
 314 +  { BFD_RELOC_AVR32_32_CPENT,          R_AVR32_32_CPENT },
 315 +  { BFD_RELOC_AVR32_CPCALL,            R_AVR32_CPCALL },
 316 +  { BFD_RELOC_AVR32_16_CP,             R_AVR32_16_CP },
 317 +  { BFD_RELOC_AVR32_9W_CP,             R_AVR32_9W_CP },
 318 +
 319 +  { BFD_RELOC_AVR32_ALIGN,             R_AVR32_ALIGN },
 320 +
 321 +  { BFD_RELOC_AVR32_15S,               R_AVR32_15S },
 322 +};
 323 +
 324 +static reloc_howto_type *
 325 +bfd_elf32_bfd_reloc_type_lookup (bfd *abfd ATTRIBUTE_UNUSED,
 326 +                                bfd_reloc_code_real_type code)
 327 +{
 328 +  unsigned int i;
 329 +
 330 +  for (i = 0; i < sizeof(avr32_reloc_map) / sizeof(struct elf_reloc_map); i++)
 331 +    {
 332 +      if (avr32_reloc_map[i].bfd_reloc_val == code)
 333 +       return &elf_avr32_howto_table[avr32_reloc_map[i].elf_reloc_val];
 334 +    }
 335 +
 336 +  return NULL;
 337 +}
 338 +
 339 +static reloc_howto_type *
 340 +bfd_elf32_bfd_reloc_name_lookup (bfd *abfd ATTRIBUTE_UNUSED,
 341 +                 const char *r_name)
 342 +{
 343 +  unsigned int i;
 344 +
 345 +  for (i = 0;
 346 +       i < sizeof (elf_avr32_howto_table) / sizeof (elf_avr32_howto_table[0]);
 347 +       i++)
 348 +    if (elf_avr32_howto_table[i].name != NULL
 349 +    && strcasecmp (elf_avr32_howto_table[i].name, r_name) == 0)
 350 +      return &elf_avr32_howto_table[i];
 351 +
 352 +  return NULL;
 353 +}
 354 +
 355 +/* Set the howto pointer for an AVR32 ELF reloc.  */
 356 +static void
 357 +avr32_info_to_howto (bfd *abfd ATTRIBUTE_UNUSED,
 358 +                    arelent *cache_ptr,
 359 +                    Elf_Internal_Rela *dst)
 360 +{
 361 +  unsigned int r_type;
 362 +
 363 +  r_type = ELF32_R_TYPE (dst->r_info);
 364 +  BFD_ASSERT (r_type < (unsigned int) R_AVR32_max);
 365 +  cache_ptr->howto = &elf_avr32_howto_table[r_type];
 366 +}
 367 +
 368 +
 369 +/* AVR32 ELF linker hash table and associated hash entries. */
 370 +
 371 +static struct bfd_hash_entry *
 372 +avr32_elf_link_hash_newfunc(struct bfd_hash_entry *entry,
 373 +                           struct bfd_hash_table *table,
 374 +                           const char *string);
 375 +static void
 376 +avr32_elf_copy_indirect_symbol(struct bfd_link_info *info,
 377 +                              struct elf_link_hash_entry *dir,
 378 +                              struct elf_link_hash_entry *ind);
 379 +static struct bfd_link_hash_table *
 380 +avr32_elf_link_hash_table_create(bfd *abfd);
 381 +
 382 +/*
 383 +  Try to limit memory usage to something reasonable when sorting the
 384 +  GOT.  If just a couple of entries end up getting more references
 385 +  than this, it won't affect performance at all, but if there are many
 386 +  of them, we could end up with the wrong symbols being assigned the
 387 +  first GOT entries.
 388 +*/
 389 +#define MAX_NR_GOT_HOLES       2048
 390 +
 391 +/*
 392 +  AVR32 GOT entry.  We need to keep track of refcounts and offsets
 393 +  simultaneously, since we need the offsets during relaxation, and we
 394 +  also want to be able to drop GOT entries during relaxation. In
 395 +  addition to this, we want to keep the list of GOT entries sorted so
 396 +  that we can keep the most-used entries at the lowest offsets.
 397 +*/
 398 +struct got_entry
 399 +{
 400 +  struct got_entry *next;
 401 +  struct got_entry **pprev;
 402 +  int refcount;
 403 +  bfd_signed_vma offset;
 404 +};
 405 +
 406 +struct elf_avr32_link_hash_entry
 407 +{
 408 +  struct elf_link_hash_entry root;
 409 +
 410 +  /* Number of runtime relocations against this symbol.  */
 411 +  unsigned int possibly_dynamic_relocs;
 412 +
 413 +  /* If there are anything but R_AVR32_GOT18 relocations against this
 414 +     symbol, it means that someone may be taking the address of the
 415 +     function, and we should therefore not create a stub.  */
 416 +  bfd_boolean no_fn_stub;
 417 +
 418 +  /* If there is a R_AVR32_32 relocation in a read-only section
 419 +     against this symbol, we could be in trouble. If we're linking a
 420 +     shared library or this symbol is defined in one, it means we must
 421 +     emit a run-time reloc for it and that's not allowed in read-only
 422 +     sections.  */
 423 +  asection *readonly_reloc_sec;
 424 +  bfd_vma readonly_reloc_offset;
 425 +
 426 +  /* Record which frag (if any) contains the symbol.  This is used
 427 +     during relaxation in order to avoid having to update all symbols
 428 +     whenever we move something.  For local symbols, this information
 429 +     is in the local_sym_frag member of struct elf_obj_tdata.  */
 430 +  struct fragment *sym_frag;
 431 +};
 432 +#define avr32_elf_hash_entry(ent) ((struct elf_avr32_link_hash_entry *)(ent))
 433 +
 434 +struct elf_avr32_link_hash_table
 435 +{
 436 +  struct elf_link_hash_table root;
 437 +
 438 +  /* Shortcuts to get to dynamic linker sections.  */
 439 +  asection *sgot;
 440 +  asection *srelgot;
 441 +  asection *sstub;
 442 +
 443 +  /* We use a variation of Pigeonhole Sort to sort the GOT.  After the
 444 +     initial refcounts have been determined, we initialize
 445 +     nr_got_holes to the highest refcount ever seen and allocate an
 446 +     array of nr_got_holes entries for got_hole.  Each GOT entry is
 447 +     then stored in this array at the index given by its refcount.
 448 +
 449 +     When a GOT entry has its refcount decremented during relaxation,
 450 +     it is moved to a lower index in the got_hole array.
 451 +   */
 452 +  struct got_entry **got_hole;
 453 +  int nr_got_holes;
 454 +
 455 +  /* Dynamic relocations to local symbols.  Only used when linking a
 456 +     shared library and -Bsymbolic is not given.  */
 457 +  unsigned int local_dynamic_relocs;
 458 +
 459 +  bfd_boolean relocations_analyzed;
 460 +  bfd_boolean symbols_adjusted;
 461 +  bfd_boolean repeat_pass;
 462 +  bfd_boolean direct_data_refs;
 463 +  unsigned int relax_iteration;
 464 +  unsigned int relax_pass;
 465 +};
 466 +#define avr32_elf_hash_table(p)                                \
 467 +  ((struct elf_avr32_link_hash_table *)((p)->hash))
 468 +
 469 +static struct bfd_hash_entry *
 470 +avr32_elf_link_hash_newfunc(struct bfd_hash_entry *entry,
 471 +                           struct bfd_hash_table *table,
 472 +                           const char *string)
 473 +{
 474 +  struct elf_avr32_link_hash_entry *ret = avr32_elf_hash_entry(entry);
 475 +
 476 +  /* Allocate the structure if it hasn't already been allocated by a
 477 +     subclass */
 478 +  if (ret == NULL)
 479 +    ret = (struct elf_avr32_link_hash_entry *)
 480 +      bfd_hash_allocate(table, sizeof(struct elf_avr32_link_hash_entry));
 481 +
 482 +  if (ret == NULL)
 483 +    return NULL;
 484 +
 485 +  memset(ret, 0, sizeof(struct elf_avr32_link_hash_entry));
 486 +
 487 +  /* Give the superclass a chance */
 488 +  ret = (struct elf_avr32_link_hash_entry *)
 489 +    _bfd_elf_link_hash_newfunc((struct bfd_hash_entry *)ret, table, string);
 490 +
 491 +  return (struct bfd_hash_entry *)ret;
 492 +}
 493 +
 494 +/* Copy data from an indirect symbol to its direct symbol, hiding the
 495 +   old indirect symbol.  Process additional relocation information.
 496 +   Also called for weakdefs, in which case we just let
 497 +   _bfd_elf_link_hash_copy_indirect copy the flags for us.  */
 498 +
 499 +static void
 500 +avr32_elf_copy_indirect_symbol(struct bfd_link_info *info,
 501 +                              struct elf_link_hash_entry *dir,
 502 +                              struct elf_link_hash_entry *ind)
 503 +{
 504 +  struct elf_avr32_link_hash_entry *edir, *eind;
 505 +
 506 +  _bfd_elf_link_hash_copy_indirect (info, dir, ind);
 507 +
 508 +  if (ind->root.type != bfd_link_hash_indirect)
 509 +    return;
 510 +
 511 +  edir = (struct elf_avr32_link_hash_entry *)dir;
 512 +  eind = (struct elf_avr32_link_hash_entry *)ind;
 513 +
 514 +  edir->possibly_dynamic_relocs += eind->possibly_dynamic_relocs;
 515 +  edir->no_fn_stub = edir->no_fn_stub || eind->no_fn_stub;
 516 +}
 517 +
 518 +static struct bfd_link_hash_table *
 519 +avr32_elf_link_hash_table_create(bfd *abfd)
 520 +{
 521 +  struct elf_avr32_link_hash_table *ret;
 522 +
 523 +  ret = bfd_zmalloc(sizeof(*ret));
 524 +  if (ret == NULL)
 525 +    return NULL;
 526 +
 527 +  if (! _bfd_elf_link_hash_table_init(&ret->root, abfd,
 528 +                                     avr32_elf_link_hash_newfunc,
 529 +                      sizeof (struct elf_avr32_link_hash_entry)))
 530 +    {
 531 +      free(ret);
 532 +      return NULL;
 533 +    }
 534 +
 535 +  /* Prevent the BFD core from creating bogus got_entry pointers */
 536 +  ret->root.init_got_refcount.glist = NULL;
 537 +  ret->root.init_plt_refcount.glist = NULL;
 538 +  ret->root.init_got_offset.glist = NULL;
 539 +  ret->root.init_plt_offset.glist = NULL;
 540 +
 541 +  return &ret->root.root;
 542 +}
 543 +
 544 +
 545 +/* Initial analysis and creation of dynamic sections and symbols */
 546 +
 547 +static asection *
 548 +create_dynamic_section(bfd *dynobj, const char *name, flagword flags,
 549 +                      unsigned int align_power);
 550 +static struct elf_link_hash_entry *
 551 +create_dynamic_symbol(bfd *dynobj, struct bfd_link_info *info,
 552 +                     const char *name, asection *sec,
 553 +                     bfd_vma offset);
 554 +static bfd_boolean
 555 +avr32_elf_create_got_section (bfd *dynobj, struct bfd_link_info *info);
 556 +static bfd_boolean
 557 +avr32_elf_create_dynamic_sections (bfd *dynobj, struct bfd_link_info *info);
 558 +static bfd_boolean
 559 +avr32_check_relocs (bfd *abfd, struct bfd_link_info *info, asection *sec,
 560 +                   const Elf_Internal_Rela *relocs);
 561 +static bfd_boolean
 562 +avr32_elf_adjust_dynamic_symbol(struct bfd_link_info *info,
 563 +                               struct elf_link_hash_entry *h);
 564 +
 565 +static asection *
 566 +create_dynamic_section(bfd *dynobj, const char *name, flagword flags,
 567 +                      unsigned int align_power)
 568 +{
 569 +  asection *sec;
 570 +
 571 +  sec = bfd_make_section(dynobj, name);
 572 +  if (!sec
 573 +      || !bfd_set_section_flags(dynobj, sec, flags)
 574 +      || !bfd_set_section_alignment(dynobj, sec, align_power))
 575 +    return NULL;
 576 +
 577 +  return sec;
 578 +}
 579 +
 580 +static struct elf_link_hash_entry *
 581 +create_dynamic_symbol(bfd *dynobj, struct bfd_link_info *info,
 582 +                     const char *name, asection *sec,
 583 +                     bfd_vma offset)
 584 +{
 585 +  struct bfd_link_hash_entry *bh = NULL;
 586 +  struct elf_link_hash_entry *h;
 587 +  const struct elf_backend_data *bed = get_elf_backend_data (dynobj);
 588 +
 589 +  if (!(_bfd_generic_link_add_one_symbol
 590 +       (info, dynobj, name, BSF_GLOBAL, sec, offset, NULL, FALSE,
 591 +        bed->collect, &bh)))
 592 +    return NULL;
 593 +
 594 +  h = (struct elf_link_hash_entry *)bh;
 595 +  h->def_regular = 1;
 596 +  h->type = STT_OBJECT;
 597 +  h->other = STV_HIDDEN;
 598 +
 599 +  return h;
 600 +}
 601 +
 602 +static bfd_boolean
 603 +avr32_elf_create_got_section (bfd *dynobj, struct bfd_link_info *info)
 604 +{
 605 +  struct elf_avr32_link_hash_table *htab;
 606 +  flagword flags;
 607 +  const struct elf_backend_data *bed = get_elf_backend_data (dynobj);
 608 +
 609 +  htab = avr32_elf_hash_table(info);
 610 +  flags = bed->dynamic_sec_flags;
 611 +
 612 +  if (htab->sgot)
 613 +    return TRUE;
 614 +
 615 +  htab->sgot = create_dynamic_section(dynobj, ".got", flags, 2);
 616 +  if (!htab->srelgot)
 617 +    htab->srelgot = create_dynamic_section(dynobj, ".rela.got",
 618 +                                          flags | SEC_READONLY, 2);
 619 +
 620 +  if (!htab->sgot || !htab->srelgot)
 621 +    return FALSE;
 622 +
 623 +  htab->root.hgot = create_dynamic_symbol(dynobj, info, "_GLOBAL_OFFSET_TABLE_",
 624 +                                         htab->sgot, 0);
 625 +  if (!htab->root.hgot)
 626 +    return FALSE;
 627 +
 628 +  /* Make room for the GOT header */
 629 +  htab->sgot->size += bed->got_header_size;
 630 +
 631 +  return TRUE;
 632 +}
 633 +
 634 +/* (1) Create all dynamic (i.e. linker generated) sections that we may
 635 +   need during the link */
 636 +
 637 +static bfd_boolean
 638 +avr32_elf_create_dynamic_sections (bfd *dynobj, struct bfd_link_info *info)
 639 +{
 640 +  struct elf_avr32_link_hash_table *htab;
 641 +  flagword flags;
 642 +  const struct elf_backend_data *bed = get_elf_backend_data (dynobj);
 643 +
 644 +  pr_debug("(1) create dynamic sections\n");
 645 +
 646 +  htab = avr32_elf_hash_table(info);
 647 +  flags = bed->dynamic_sec_flags;
 648 +
 649 +  if (!avr32_elf_create_got_section (dynobj, info))
 650 +    return FALSE;
 651 +
 652 +  if (!htab->sstub)
 653 +    htab->sstub = create_dynamic_section(dynobj, ".stub",
 654 +                                        flags | SEC_READONLY | SEC_CODE, 2);
 655 +
 656 +  if (!htab->sstub)
 657 +    return FALSE;
 658 +
 659 +  return TRUE;
 660 +}
 661 +
 662 +/* (2) Go through all the relocs and count any potential GOT- or
 663 +   PLT-references to each symbol */
 664 +
 665 +static bfd_boolean
 666 +avr32_check_relocs (bfd *abfd, struct bfd_link_info *info, asection *sec,
 667 +                   const Elf_Internal_Rela *relocs)
 668 +{
 669 +  Elf_Internal_Shdr *symtab_hdr;
 670 +  struct elf_avr32_link_hash_table *htab;
 671 +  struct elf_link_hash_entry **sym_hashes;
 672 +  const Elf_Internal_Rela *rel, *rel_end;
 673 +  struct got_entry **local_got_ents;
 674 +  struct got_entry *got;
 675 +  const struct elf_backend_data *bed = get_elf_backend_data (abfd);
 676 +  asection *sgot;
 677 +  bfd *dynobj;
 678 +
 679 +  pr_debug("(2) check relocs for %s:<%s> (size 0x%lx)\n",
 680 +          abfd->filename, sec->name, sec->size);
 681 +
 682 +  if (info->relocatable)
 683 +    return TRUE;
 684 +
 685 +  dynobj = elf_hash_table(info)->dynobj;
 686 +  symtab_hdr = &elf_tdata(abfd)->symtab_hdr;
 687 +  sym_hashes = elf_sym_hashes(abfd);
 688 +  htab = avr32_elf_hash_table(info);
 689 +  local_got_ents = elf_local_got_ents(abfd);
 690 +  sgot = htab->sgot;
 691 +
 692 +  rel_end = relocs + sec->reloc_count;
 693 +  for (rel = relocs; rel < rel_end; rel++)
 694 +    {
 695 +      unsigned long r_symndx, r_type;
 696 +      struct elf_avr32_link_hash_entry *h;
 697 +
 698 +      r_symndx = ELF32_R_SYM(rel->r_info);
 699 +      r_type = ELF32_R_TYPE(rel->r_info);
 700 +
 701 +      /* Local symbols use local_got_ents, while others store the same
 702 +        information in the hash entry */
 703 +      if (r_symndx < symtab_hdr->sh_info)
 704 +       {
 705 +         pr_debug("  (2a) processing local symbol %lu\n", r_symndx);
 706 +         h = NULL;
 707 +       }
 708 +      else
 709 +       {
 710 +         h = (struct elf_avr32_link_hash_entry *)
 711 +           sym_hashes[r_symndx - symtab_hdr->sh_info];
 712 +         while (h->root.type == bfd_link_hash_indirect
 713 +                || h->root.type == bfd_link_hash_warning)
 714 +           h = (struct elf_avr32_link_hash_entry *)h->root.root.u.i.link;
 715 +         pr_debug("  (2a) processing symbol %s\n", h->root.root.root.string);
 716 +       }
 717 +
 718 +      /* Some relocs require special sections to be created.  */
 719 +      switch (r_type)
 720 +       {
 721 +       case R_AVR32_GOT32:
 722 +       case R_AVR32_GOT16:
 723 +       case R_AVR32_GOT8:
 724 +       case R_AVR32_GOT21S:
 725 +       case R_AVR32_GOT18SW:
 726 +       case R_AVR32_GOT16S:
 727 +       case R_AVR32_GOT7UW:
 728 +       case R_AVR32_LDA_GOT:
 729 +       case R_AVR32_GOTCALL:
 730 +         if (rel->r_addend)
 731 +           {
 732 +             if (info->callbacks->reloc_dangerous
 733 +                 (info, _("Non-zero addend on GOT-relative relocation"),
 734 +                  abfd, sec, rel->r_offset) == FALSE)
 735 +               return FALSE;
 736 +           }
 737 +         /* fall through */
 738 +       case R_AVR32_GOTPC:
 739 +         if (dynobj == NULL)
 740 +           elf_hash_table(info)->dynobj = dynobj = abfd;
 741 +         if (sgot == NULL && !avr32_elf_create_got_section(dynobj, info))
 742 +           return FALSE;
 743 +         break;
 744 +       case R_AVR32_32:
 745 +         /* We may need to create .rela.dyn later on.  */
 746 +         if (dynobj == NULL
 747 +             && (info->shared || h != NULL)
 748 +             && (sec->flags & SEC_ALLOC))
 749 +           elf_hash_table(info)->dynobj = dynobj = abfd;
 750 +         break;
 751 +       }
 752 +
 753 +      if (h != NULL && r_type != R_AVR32_GOT18SW)
 754 +       h->no_fn_stub = TRUE;
 755 +
 756 +      switch (r_type)
 757 +       {
 758 +       case R_AVR32_GOT32:
 759 +       case R_AVR32_GOT16:
 760 +       case R_AVR32_GOT8:
 761 +       case R_AVR32_GOT21S:
 762 +       case R_AVR32_GOT18SW:
 763 +       case R_AVR32_GOT16S:
 764 +       case R_AVR32_GOT7UW:
 765 +       case R_AVR32_LDA_GOT:
 766 +       case R_AVR32_GOTCALL:
 767 +         if (h != NULL)
 768 +           {
 769 +             got = h->root.got.glist;
 770 +             if (!got)
 771 +               {
 772 +                 got = bfd_zalloc(abfd, sizeof(struct got_entry));
 773 +                 if (!got)
 774 +                   return FALSE;
 775 +                 h->root.got.glist = got;
 776 +               }
 777 +           }
 778 +         else
 779 +           {
 780 +             if (!local_got_ents)
 781 +               {
 782 +                 bfd_size_type size;
 783 +                 bfd_size_type i;
 784 +                 struct got_entry *tmp_entry;
 785 +
 786 +                 size = symtab_hdr->sh_info;
 787 +                 size *= sizeof(struct got_entry *) + sizeof(struct got_entry);
 788 +                 local_got_ents = bfd_zalloc(abfd, size);
 789 +                 if (!local_got_ents)
 790 +                   return FALSE;
 791 +
 792 +                 elf_local_got_ents(abfd) = local_got_ents;
 793 +
 794 +                 tmp_entry = (struct got_entry *)(local_got_ents
 795 +                                                  + symtab_hdr->sh_info);
 796 +                 for (i = 0; i < symtab_hdr->sh_info; i++)
 797 +                   local_got_ents[i] = &tmp_entry[i];
 798 +               }
 799 +
 800 +             got = local_got_ents[r_symndx];
 801 +           }
 802 +
 803 +         got->refcount++;
 804 +         if (got->refcount > htab->nr_got_holes)
 805 +           htab->nr_got_holes = got->refcount;
 806 +         break;
 807 +
 808 +       case R_AVR32_32:
 809 +         if ((info->shared || h != NULL)
 810 +             && (sec->flags & SEC_ALLOC))
 811 +           {
 812 +             if (htab->srelgot == NULL)
 813 +               {
 814 +                 htab->srelgot = create_dynamic_section(dynobj, ".rela.got",
 815 +                                                        bed->dynamic_sec_flags
 816 +                                                        | SEC_READONLY, 2);
 817 +                 if (htab->srelgot == NULL)
 818 +                   return FALSE;
 819 +               }
 820 +
 821 +             if (sec->flags & SEC_READONLY
 822 +                 && !h->readonly_reloc_sec)
 823 +               {
 824 +                 h->readonly_reloc_sec = sec;
 825 +                 h->readonly_reloc_offset = rel->r_offset;
 826 +               }
 827 +
 828 +             if (h != NULL)
 829 +               {
 830 +                 pr_debug("Non-GOT reference to symbol %s\n",
 831 +                          h->root.root.root.string);
 832 +                 h->possibly_dynamic_relocs++;
 833 +               }
 834 +             else
 835 +               {
 836 +                 pr_debug("Non-GOT reference to local symbol %lu\n",
 837 +                          r_symndx);
 838 +                 htab->local_dynamic_relocs++;
 839 +               }
 840 +           }
 841 +
 842 +         break;
 843 +
 844 +         /* TODO: GNU_VTINHERIT and GNU_VTENTRY */
 845 +       }
 846 +    }
 847 +
 848 +  return TRUE;
 849 +}
 850 +
 851 +/* (3) Adjust a symbol defined by a dynamic object and referenced by a
 852 +   regular object.  The current definition is in some section of the
 853 +   dynamic object, but we're not including those sections.  We have to
 854 +   change the definition to something the rest of the link can
 855 +   understand.  */
 856 +
 857 +static bfd_boolean
 858 +avr32_elf_adjust_dynamic_symbol(struct bfd_link_info *info,
 859 +                               struct elf_link_hash_entry *h)
 860 +{
 861 +  struct elf_avr32_link_hash_table *htab;
 862 +  struct elf_avr32_link_hash_entry *havr;
 863 +  bfd *dynobj;
 864 +
 865 +  pr_debug("(3) adjust dynamic symbol %s\n", h->root.root.string);
 866 +
 867 +  htab = avr32_elf_hash_table(info);
 868 +  havr = (struct elf_avr32_link_hash_entry *)h;
 869 +  dynobj = elf_hash_table(info)->dynobj;
 870 +
 871 +  /* Make sure we know what is going on here.  */
 872 +  BFD_ASSERT (dynobj != NULL
 873 +             && (h->u.weakdef != NULL
 874 +                 || (h->def_dynamic
 875 +                     && h->ref_regular
 876 +                     && !h->def_regular)));
 877 +
 878 +  /* We don't want dynamic relocations in read-only sections. */
 879 +  if (havr->readonly_reloc_sec)
 880 +    {
 881 +      if (info->callbacks->reloc_dangerous
 882 +         (info, _("dynamic relocation in read-only section"),
 883 +          havr->readonly_reloc_sec->owner, havr->readonly_reloc_sec,
 884 +          havr->readonly_reloc_offset) == FALSE)
 885 +       return FALSE;
 886 +    }
 887 +
 888 +  /* If this is a function, create a stub if possible and set the
 889 +     symbol to the stub location.  */
 890 +  if (0 && !havr->no_fn_stub)
 891 +    {
 892 +      if (!h->def_regular)
 893 +       {
 894 +         asection *s = htab->sstub;
 895 +
 896 +         BFD_ASSERT(s != NULL);
 897 +
 898 +         h->root.u.def.section = s;
 899 +         h->root.u.def.value = s->size;
 900 +         h->plt.offset = s->size;
 901 +         s->size += AVR32_FUNCTION_STUB_SIZE;
 902 +
 903 +         return TRUE;
 904 +       }
 905 +    }
 906 +  else if (h->type == STT_FUNC)
 907 +    {
 908 +      /* This will set the entry for this symbol in the GOT to 0, and
 909 +        the dynamic linker will take care of this. */
 910 +      h->root.u.def.value = 0;
 911 +      return TRUE;
 912 +    }
 913 +
 914 +  /* If this is a weak symbol, and there is a real definition, the
 915 +     processor independent code will have arranged for us to see the
 916 +     real definition first, and we can just use the same value.  */
 917 +  if (h->u.weakdef != NULL)
 918 +    {
 919 +      BFD_ASSERT(h->u.weakdef->root.type == bfd_link_hash_defined
 920 +                || h->u.weakdef->root.type == bfd_link_hash_defweak);
 921 +      h->root.u.def.section = h->u.weakdef->root.u.def.section;
 922 +      h->root.u.def.value = h->u.weakdef->root.u.def.value;
 923 +      return TRUE;
 924 +    }
 925 +
 926 +  /* This is a reference to a symbol defined by a dynamic object which
 927 +     is not a function.  */
 928 +
 929 +  return TRUE;
 930 +}
 931 +
 932 +
 933 +/* Garbage-collection of unused sections */
 934 +
 935 +static asection *
 936 +avr32_elf_gc_mark_hook(asection *sec,
 937 +                      struct bfd_link_info *info ATTRIBUTE_UNUSED,
 938 +                      Elf_Internal_Rela *rel,
 939 +                      struct elf_link_hash_entry *h,
 940 +                      Elf_Internal_Sym *sym)
 941 +{
 942 +  if (h)
 943 +    {
 944 +      switch (ELF32_R_TYPE(rel->r_info))
 945 +       {
 946 +         /* TODO: VTINHERIT/VTENTRY */
 947 +       default:
 948 +         switch (h->root.type)
 949 +           {
 950 +           case bfd_link_hash_defined:
 951 +           case bfd_link_hash_defweak:
 952 +             return h->root.u.def.section;
 953 +
 954 +           case bfd_link_hash_common:
 955 +             return h->root.u.c.p->section;
 956 +
 957 +           default:
 958 +             break;
 959 +           }
 960 +       }
 961 +    }
 962 +  else
 963 +    return bfd_section_from_elf_index(sec->owner, sym->st_shndx);
 964 +
 965 +  return NULL;
 966 +}
 967 +
 968 +/* Update the GOT entry reference counts for the section being removed. */
 969 +static bfd_boolean
 970 +avr32_elf_gc_sweep_hook(bfd *abfd,
 971 +                       struct bfd_link_info *info ATTRIBUTE_UNUSED,
 972 +                       asection *sec,
 973 +                       const Elf_Internal_Rela *relocs)
 974 +{
 975 +  Elf_Internal_Shdr *symtab_hdr;
 976 +  struct elf_avr32_link_hash_entry **sym_hashes;
 977 +  struct got_entry **local_got_ents;
 978 +  const Elf_Internal_Rela *rel, *relend;
 979 +
 980 +  if (!(sec->flags & SEC_ALLOC))
 981 +    return TRUE;
 982 +
 983 +  symtab_hdr = &elf_tdata(abfd)->symtab_hdr;
 984 +  sym_hashes = (struct elf_avr32_link_hash_entry **)elf_sym_hashes(abfd);
 985 +  local_got_ents = elf_local_got_ents(abfd);
 986 +
 987 +  relend = relocs + sec->reloc_count;
 988 +  for (rel = relocs; rel < relend; rel++)
 989 +    {
 990 +      unsigned long r_symndx;
 991 +      unsigned int r_type;
 992 +      struct elf_avr32_link_hash_entry *h = NULL;
 993 +
 994 +      r_symndx = ELF32_R_SYM(rel->r_info);
 995 +      if (r_symndx >= symtab_hdr->sh_info)
 996 +       {
 997 +         h = sym_hashes[r_symndx - symtab_hdr->sh_info];
 998 +         while (h->root.root.type == bfd_link_hash_indirect
 999 +                || h->root.root.type == bfd_link_hash_warning)
1000 +           h = (struct elf_avr32_link_hash_entry *)h->root.root.u.i.link;
1001 +       }
1002 +
1003 +      r_type = ELF32_R_TYPE(rel->r_info);
1004 +
1005 +      switch (r_type)
1006 +       {
1007 +       case R_AVR32_GOT32:
1008 +       case R_AVR32_GOT16:
1009 +       case R_AVR32_GOT8:
1010 +       case R_AVR32_GOT21S:
1011 +       case R_AVR32_GOT18SW:
1012 +       case R_AVR32_GOT16S:
1013 +       case R_AVR32_GOT7UW:
1014 +       case R_AVR32_LDA_GOT:
1015 +       case R_AVR32_GOTCALL:
1016 +         if (h)
1017 +           h->root.got.glist->refcount--;
1018 +         else
1019 +           local_got_ents[r_symndx]->refcount--;
1020 +         break;
1021 +
1022 +       case R_AVR32_32:
1023 +         if (info->shared || h)
1024 +           {
1025 +             if (h)
1026 +               h->possibly_dynamic_relocs--;
1027 +             else
1028 +               avr32_elf_hash_table(info)->local_dynamic_relocs--;
1029 +           }
1030 +
1031 +       default:
1032 +         break;
1033 +       }
1034 +    }
1035 +
1036 +  return TRUE;
1037 +}
1038 +
1039 +/* Sizing and refcounting of dynamic sections */
1040 +
1041 +static void
1042 +insert_got_entry(struct elf_avr32_link_hash_table *htab, struct got_entry *got);
1043 +static void
1044 +unref_got_entry(struct elf_avr32_link_hash_table *htab, struct got_entry *got);
1045 +static void
1046 +ref_got_entry(struct elf_avr32_link_hash_table *htab, struct got_entry *got);
1047 +static bfd_boolean
1048 +assign_got_offsets(struct elf_avr32_link_hash_table *htab);
1049 +static bfd_boolean
1050 +allocate_dynrelocs(struct elf_link_hash_entry *h, void *_info);
1051 +static bfd_boolean
1052 +avr32_elf_size_dynamic_sections (bfd *output_bfd,
1053 +                                struct bfd_link_info *info);
1054 +
1055 +static void
1056 +insert_got_entry(struct elf_avr32_link_hash_table *htab, struct got_entry *got)
1057 +{
1058 +  /* Any entries with got_refcount > htab->nr_got_holes end up in the
1059 +   * last pigeonhole without any sorting. We expect the number of such
1060 +   * entries to be small, so it is very unlikely to affect
1061 +   * performance.  */
1062 +  int entry = got->refcount;
1063 +
1064 +  if (entry > htab->nr_got_holes)
1065 +    entry = htab->nr_got_holes;
1066 +
1067 +  got->pprev = &htab->got_hole[entry];
1068 +  got->next = htab->got_hole[entry];
1069 +
1070 +  if (got->next)
1071 +    got->next->pprev = &got->next;
1072 +
1073 +  htab->got_hole[entry] = got;
1074 +}
1075 +
1076 +/* Decrement the refcount of a GOT entry and update its position in
1077 +   the pigeonhole array.  */
1078 +static void
1079 +unref_got_entry(struct elf_avr32_link_hash_table *htab, struct got_entry *got)
1080 +{
1081 +  BFD_ASSERT(got->refcount > 0);
1082 +
1083 +  if (got->next)
1084 +    got->next->pprev = got->pprev;
1085 +
1086 +  *(got->pprev) = got->next;
1087 +  got->refcount--;
1088 +  insert_got_entry(htab, got);
1089 +}
1090 +
1091 +static void
1092 +ref_got_entry(struct elf_avr32_link_hash_table *htab, struct got_entry *got)
1093 +{
1094 +  if (got->next)
1095 +    got->next->pprev = got->pprev;
1096 +
1097 +  *(got->pprev) = got->next;
1098 +  got->refcount++;
1099 +  insert_got_entry(htab, got);
1100 +
1101 +  BFD_ASSERT(got->refcount > 0);
1102 +}
1103 +
1104 +/* Assign offsets to all GOT entries we intend to keep.  The entries
1105 +   that are referenced most often are placed at low offsets so that we
1106 +   can use compact instructions as much as possible.
1107 +
1108 +   Returns TRUE if any offsets or the total size of the GOT changed.  */
1109 +
1110 +static bfd_boolean
1111 +assign_got_offsets(struct elf_avr32_link_hash_table *htab)
1112 +{
1113 +  struct got_entry *got;
1114 +  bfd_size_type got_size = 0;
1115 +  bfd_boolean changed = FALSE;
1116 +  bfd_signed_vma offset;
1117 +  int i;
1118 +
1119 +  /* The GOT header provides the address of the DYNAMIC segment, so
1120 +     we need that even if the GOT is otherwise empty.  */
1121 +  if (htab->root.dynamic_sections_created)
1122 +    got_size = AVR32_GOT_HEADER_SIZE;
1123 +
1124 +  for (i = htab->nr_got_holes; i > 0; i--)
1125 +    {
1126 +      got = htab->got_hole[i];
1127 +      while (got)
1128 +       {
1129 +         if (got->refcount > 0)
1130 +           {
1131 +             offset = got_size;
1132 +             if (got->offset != offset)
1133 +               {
1134 +                 RDBG("GOT offset changed: %ld -> %ld\n",
1135 +                      got->offset, offset);
1136 +                 changed = TRUE;
1137 +               }
1138 +             got->offset = offset;
1139 +             got_size += 4;
1140 +           }
1141 +         got = got->next;
1142 +       }
1143 +    }
1144 +
1145 +  if (htab->sgot->size != got_size)
1146 +    {
1147 +      RDBG("GOT size changed: %lu -> %lu\n", htab->sgot->size,
1148 +          got_size);
1149 +      changed = TRUE;
1150 +    }
1151 +  htab->sgot->size = got_size;
1152 +
1153 +  RDBG("assign_got_offsets: total size %lu (%s)\n",
1154 +       got_size, changed ? "changed" : "no change");
1155 +
1156 +  return changed;
1157 +}
1158 +
1159 +static bfd_boolean
1160 +allocate_dynrelocs(struct elf_link_hash_entry *h, void *_info)
1161 +{
1162 +  struct bfd_link_info *info = _info;
1163 +  struct elf_avr32_link_hash_table *htab;
1164 +  struct elf_avr32_link_hash_entry *havr;
1165 +  struct got_entry *got;
1166 +
1167 +  pr_debug("  (4b) allocate_dynrelocs: %s\n", h->root.root.string);
1168 +
1169 +  if (h->root.type == bfd_link_hash_indirect)
1170 +    return TRUE;
1171 +
1172 +  if (h->root.type == bfd_link_hash_warning)
1173 +    /* When warning symbols are created, they **replace** the "real"
1174 +       entry in the hash table, thus we never get to see the real
1175 +       symbol in a hash traversal.  So look at it now.  */
1176 +    h = (struct elf_link_hash_entry *) h->root.u.i.link;
1177 +
1178 +  htab = avr32_elf_hash_table(info);
1179 +  havr = (struct elf_avr32_link_hash_entry *)h;
1180 +
1181 +  got = h->got.glist;
1182 +
1183 +  /* If got is NULL, the symbol is never referenced through the GOT */
1184 +  if (got && got->refcount > 0)
1185 +    {
1186 +      insert_got_entry(htab, got);
1187 +
1188 +      /* Shared libraries need relocs for all GOT entries unless the
1189 +        symbol is forced local or -Bsymbolic is used.  Others need
1190 +        relocs for everything that is not guaranteed to be defined in
1191 +        a regular object.  */
1192 +      if ((info->shared
1193 +          && !info->symbolic
1194 +          && h->dynindx != -1)
1195 +         || (htab->root.dynamic_sections_created
1196 +             && h->def_dynamic
1197 +             && !h->def_regular))
1198 +       htab->srelgot->size += sizeof(Elf32_External_Rela);
1199 +    }
1200 +
1201 +  if (havr->possibly_dynamic_relocs
1202 +      && (info->shared
1203 +         || (elf_hash_table(info)->dynamic_sections_created
1204 +             && h->def_dynamic
1205 +             && !h->def_regular)))
1206 +    {
1207 +      pr_debug("Allocating %d dynamic reloc against symbol %s...\n",
1208 +              havr->possibly_dynamic_relocs, h->root.root.string);
1209 +      htab->srelgot->size += (havr->possibly_dynamic_relocs
1210 +                             * sizeof(Elf32_External_Rela));
1211 +    }
1212 +
1213 +  return TRUE;
1214 +}
1215 +
1216 +/* (4) Calculate the sizes of the linker-generated sections and
1217 +   allocate memory for them.  */
1218 +
1219 +static bfd_boolean
1220 +avr32_elf_size_dynamic_sections (bfd *output_bfd,
1221 +                                struct bfd_link_info *info)
1222 +{
1223 +  struct elf_avr32_link_hash_table *htab;
1224 +  bfd *dynobj;
1225 +  asection *s;
1226 +  bfd *ibfd;
1227 +  bfd_boolean relocs;
1228 +
1229 +  pr_debug("(4) size dynamic sections\n");
1230 +
1231 +  htab = avr32_elf_hash_table(info);
1232 +  dynobj = htab->root.dynobj;
1233 +  BFD_ASSERT(dynobj != NULL);
1234 +
1235 +  if (htab->root.dynamic_sections_created)
1236 +    {
1237 +      /* Initialize the contents of the .interp section to the name of
1238 +        the dynamic loader */
1239 +      if (info->executable)
1240 +       {
1241 +         s = bfd_get_section_by_name(dynobj, ".interp");
1242 +         BFD_ASSERT(s != NULL);
1243 +         s->size = sizeof(ELF_DYNAMIC_INTERPRETER);
1244 +         s->contents = (unsigned char *)ELF_DYNAMIC_INTERPRETER;
1245 +       }
1246 +    }
1247 +
1248 +  if (htab->nr_got_holes > 0)
1249 +    {
1250 +      /* Allocate holes for the pigeonhole sort algorithm */
1251 +      pr_debug("Highest GOT refcount: %d\n", htab->nr_got_holes);
1252 +
1253 +      /* Limit the memory usage by clipping the number of pigeonholes
1254 +       * at a predefined maximum. All entries with a higher refcount
1255 +       * will end up in the last pigeonhole.  */
1256 +    if (htab->nr_got_holes >= MAX_NR_GOT_HOLES)
1257 +    {
1258 +        htab->nr_got_holes = MAX_NR_GOT_HOLES - 1;
1259 +
1260 +        pr_debug("Limiting maximum number of GOT pigeonholes to %u\n",
1261 +                    htab->nr_got_holes);
1262 +    }
1263 +      htab->got_hole = bfd_zalloc(output_bfd,
1264 +                                 sizeof(struct got_entry *)
1265 +                                 * (htab->nr_got_holes + 1));
1266 +      if (!htab->got_hole)
1267 +       return FALSE;
1268 +
1269 +      /* Set up .got offsets for local syms.  */
1270 +      for (ibfd = info->input_bfds; ibfd != NULL; ibfd = ibfd->link_next)
1271 +       {
1272 +         struct got_entry **local_got;
1273 +         struct got_entry **end_local_got;
1274 +         Elf_Internal_Shdr *symtab_hdr;
1275 +         bfd_size_type locsymcount;
1276 +
1277 +         pr_debug("  (4a) processing file %s...\n", ibfd->filename);
1278 +
1279 +         BFD_ASSERT(bfd_get_flavour(ibfd) == bfd_target_elf_flavour);
1280 +
1281 +         local_got = elf_local_got_ents(ibfd);
1282 +         if (!local_got)
1283 +           continue;
1284 +
1285 +         symtab_hdr = &elf_tdata(ibfd)->symtab_hdr;
1286 +         locsymcount = symtab_hdr->sh_info;
1287 +         end_local_got = local_got + locsymcount;
1288 +
1289 +         for (; local_got < end_local_got; ++local_got)
1290 +           insert_got_entry(htab, *local_got);
1291 +       }
1292 +    }
1293 +
1294 +  /* Allocate global sym .got entries and space for global sym
1295 +     dynamic relocs */
1296 +  elf_link_hash_traverse(&htab->root, allocate_dynrelocs, info);
1297 +
1298 +  /* Now that we have sorted the GOT entries, we are ready to
1299 +     assign offsets and determine the initial size of the GOT. */
1300 +  if (htab->sgot)
1301 +    assign_got_offsets(htab);
1302 +
1303 +  /* Allocate space for local sym dynamic relocs */
1304 +  BFD_ASSERT(htab->local_dynamic_relocs == 0 || info->shared);
1305 +  if (htab->local_dynamic_relocs)
1306 +    htab->srelgot->size += (htab->local_dynamic_relocs
1307 +                           * sizeof(Elf32_External_Rela));
1308 +
1309 +  /* We now have determined the sizes of the various dynamic
1310 +     sections. Allocate memory for them. */
1311 +  relocs = FALSE;
1312 +  for (s = dynobj->sections; s; s = s->next)
1313 +    {
1314 +      if ((s->flags & SEC_LINKER_CREATED) == 0)
1315 +       continue;
1316 +
1317 +      if (s == htab->sgot
1318 +         || s == htab->sstub)
1319 +       {
1320 +         /* Strip this section if we don't need it */
1321 +       }
1322 +      else if (strncmp (bfd_get_section_name(dynobj, s), ".rela", 5) == 0)
1323 +       {
1324 +         if (s->size != 0)
1325 +           relocs = TRUE;
1326 +
1327 +         s->reloc_count = 0;
1328 +       }
1329 +      else
1330 +       {
1331 +         /* It's not one of our sections */
1332 +         continue;
1333 +       }
1334 +
1335 +      if (s->size == 0)
1336 +       {
1337 +         /* Strip unneeded sections */
1338 +         pr_debug("Stripping section %s from output...\n", s->name);
1339 +         /* deleted function in 2.17
1340 +      _bfd_strip_section_from_output(info, s);
1341 +      */
1342 +         continue;
1343 +       }
1344 +
1345 +      s->contents = bfd_zalloc(dynobj, s->size);
1346 +      if (s->contents == NULL)
1347 +       return FALSE;
1348 +    }
1349 +
1350 +  if (htab->root.dynamic_sections_created)
1351 +    {
1352 +      /* Add some entries to the .dynamic section.  We fill in the
1353 +        values later, in sh_elf_finish_dynamic_sections, but we
1354 +        must add the entries now so that we get the correct size for
1355 +        the .dynamic section.  The DT_DEBUG entry is filled in by the
1356 +        dynamic linker and used by the debugger.  */
1357 +#define add_dynamic_entry(TAG, VAL) _bfd_elf_add_dynamic_entry(info, TAG, VAL)
1358 +
1359 +      if (!add_dynamic_entry(DT_PLTGOT, 0))
1360 +       return FALSE;
1361 +      if (!add_dynamic_entry(DT_AVR32_GOTSZ, 0))
1362 +       return FALSE;
1363 +
1364 +      if (info->executable)
1365 +       {
1366 +         if (!add_dynamic_entry(DT_DEBUG, 0))
1367 +           return FALSE;
1368 +       }
1369 +      if (relocs)
1370 +       {
1371 +         if (!add_dynamic_entry(DT_RELA, 0)
1372 +             || !add_dynamic_entry(DT_RELASZ, 0)
1373 +             || !add_dynamic_entry(DT_RELAENT,
1374 +                                   sizeof(Elf32_External_Rela)))
1375 +           return FALSE;
1376 +       }
1377 +    }
1378 +#undef add_dynamic_entry
1379 +
1380 +  return TRUE;
1381 +}
1382 +
1383 +
1384 +/* Access to internal relocations, section contents and symbols.
1385 +   (stolen from the xtensa port)  */
1386 +
1387 +static Elf_Internal_Rela *
1388 +retrieve_internal_relocs (bfd *abfd, asection *sec, bfd_boolean keep_memory);
1389 +static void
1390 +pin_internal_relocs (asection *sec, Elf_Internal_Rela *internal_relocs);
1391 +static void
1392 +release_internal_relocs (asection *sec, Elf_Internal_Rela *internal_relocs);
1393 +static bfd_byte *
1394 +retrieve_contents (bfd *abfd, asection *sec, bfd_boolean keep_memory);
1395 +/*
1396 +static void
1397 +pin_contents (asection *sec, bfd_byte *contents);
1398 +*/
1399 +static void
1400 +release_contents (asection *sec, bfd_byte *contents);
1401 +static Elf_Internal_Sym *
1402 +retrieve_local_syms (bfd *input_bfd, bfd_boolean keep_memory);
1403 +/*
1404 +static void
1405 +pin_local_syms (bfd *input_bfd, Elf_Internal_Sym *isymbuf);
1406 +*/
1407 +static void
1408 +release_local_syms (bfd *input_bfd, Elf_Internal_Sym *isymbuf);
1409 +
1410 +/* During relaxation, we need to modify relocations, section contents,
1411 +   and symbol definitions, and we need to keep the original values from
1412 +   being reloaded from the input files, i.e., we need to "pin" the
1413 +   modified values in memory.  We also want to continue to observe the
1414 +   setting of the "keep-memory" flag.  The following functions wrap the
1415 +   standard BFD functions to take care of this for us.  */
1416 +
1417 +static Elf_Internal_Rela *
1418 +retrieve_internal_relocs (bfd *abfd, asection *sec, bfd_boolean keep_memory)
1419 +{
1420 +  /* _bfd_elf_link_read_relocs knows about caching, so no need for us
1421 +     to be clever here.  */
1422 +  return _bfd_elf_link_read_relocs(abfd, sec, NULL, NULL, keep_memory);
1423 +}
1424 +
1425 +static void
1426 +pin_internal_relocs (asection *sec, Elf_Internal_Rela *internal_relocs)
1427 +{
1428 +  elf_section_data (sec)->relocs = internal_relocs;
1429 +}
1430 +
1431 +static void
1432 +release_internal_relocs (asection *sec, Elf_Internal_Rela *internal_relocs)
1433 +{
1434 +  if (internal_relocs
1435 +      && elf_section_data (sec)->relocs != internal_relocs)
1436 +    free (internal_relocs);
1437 +}
1438 +
1439 +static bfd_byte *
1440 +retrieve_contents (bfd *abfd, asection *sec, bfd_boolean keep_memory)
1441 +{
1442 +  bfd_byte *contents;
1443 +  bfd_size_type sec_size;
1444 +
1445 +  sec_size = bfd_get_section_limit (abfd, sec);
1446 +  contents = elf_section_data (sec)->this_hdr.contents;
1447 +
1448 +  if (contents == NULL && sec_size != 0)
1449 +    {
1450 +      if (!bfd_malloc_and_get_section (abfd, sec, &contents))
1451 +       {
1452 +         if (contents)
1453 +           free (contents);
1454 +         return NULL;
1455 +       }
1456 +      if (keep_memory)
1457 +       elf_section_data (sec)->this_hdr.contents = contents;
1458 +    }
1459 +  return contents;
1460 +}
1461 +
1462 +/*
1463 +static void
1464 +pin_contents (asection *sec, bfd_byte *contents)
1465 +{
1466 +  elf_section_data (sec)->this_hdr.contents = contents;
1467 +}
1468 +*/
1469 +static void
1470 +release_contents (asection *sec, bfd_byte *contents)
1471 +{
1472 +  if (contents && elf_section_data (sec)->this_hdr.contents != contents)
1473 +    free (contents);
1474 +}
1475 +
1476 +static Elf_Internal_Sym *
1477 +retrieve_local_syms (bfd *input_bfd, bfd_boolean keep_memory)
1478 +{
1479 +  Elf_Internal_Shdr *symtab_hdr;
1480 +  Elf_Internal_Sym *isymbuf;
1481 +  size_t locsymcount;
1482 +
1483 +  symtab_hdr = &elf_tdata (input_bfd)->symtab_hdr;
1484 +  locsymcount = symtab_hdr->sh_info;
1485 +
1486 +  isymbuf = (Elf_Internal_Sym *) symtab_hdr->contents;
1487 +  if (isymbuf == NULL && locsymcount != 0)
1488 +    {
1489 +      isymbuf = bfd_elf_get_elf_syms (input_bfd, symtab_hdr, locsymcount, 0,
1490 +                                     NULL, NULL, NULL);
1491 +      if (isymbuf && keep_memory)
1492 +       symtab_hdr->contents = (unsigned char *) isymbuf;
1493 +    }
1494 +
1495 +  return isymbuf;
1496 +}
1497 +
1498 +/*
1499 +static void
1500 +pin_local_syms (bfd *input_bfd, Elf_Internal_Sym *isymbuf)
1501 +{
1502 +  elf_tdata (input_bfd)->symtab_hdr.contents = (unsigned char *)isymbuf;
1503 +}
1504 +
1505 +*/
1506 +static void
1507 +release_local_syms (bfd *input_bfd, Elf_Internal_Sym *isymbuf)
1508 +{
1509 +  if (isymbuf && (elf_tdata (input_bfd)->symtab_hdr.contents
1510 +                 != (unsigned char *)isymbuf))
1511 +    free (isymbuf);
1512 +}
1513 +
1514 +\f/* Data structures used during relaxation. */
1515 +
1516 +enum relax_state_id {
1517 +  RS_ERROR = -1,
1518 +  RS_NONE = 0,
1519 +  RS_ALIGN,
1520 +  RS_CPENT,
1521 +  RS_PIC_CALL,
1522 +  RS_PIC_MCALL,
1523 +  RS_PIC_RCALL2,
1524 +  RS_PIC_RCALL1,
1525 +  RS_PIC_LDA,
1526 +  RS_PIC_LDW4,
1527 +  RS_PIC_LDW3,
1528 +  RS_PIC_SUB5,
1529 +  RS_NOPIC_MCALL,
1530 +  RS_NOPIC_RCALL2,
1531 +  RS_NOPIC_RCALL1,
1532 +  RS_NOPIC_LDW4,
1533 +  RS_NOPIC_LDDPC,
1534 +  RS_NOPIC_SUB5,
1535 +  RS_NOPIC_MOV2,
1536 +  RS_NOPIC_MOV1,
1537 +  RS_RCALL2,
1538 +  RS_RCALL1,
1539 +  RS_BRC2,
1540 +  RS_BRC1,
1541 +  RS_BRAL,
1542 +  RS_RJMP,
1543 +  RS_MAX,
1544 +};
1545 +
1546 +enum reference_type {
1547 +  REF_ABSOLUTE,
1548 +  REF_PCREL,
1549 +  REF_CPOOL,
1550 +  REF_GOT,
1551 +};
1552 +
1553 +struct relax_state
1554 +{
1555 +  const char *name;
1556 +  enum relax_state_id id;
1557 +  enum relax_state_id direct;
1558 +  enum relax_state_id next;
1559 +  enum relax_state_id prev;
1560 +
1561 +  enum reference_type reftype;
1562 +
1563 +  unsigned int r_type;
1564 +
1565 +  bfd_vma opcode;
1566 +  bfd_vma opcode_mask;
1567 +
1568 +  bfd_signed_vma range_min;
1569 +  bfd_signed_vma range_max;
1570 +
1571 +  bfd_size_type size;
1572 +};
1573 +
1574 +/*
1575 + * This is for relocs that
1576 + *   a) has an addend or is of type R_AVR32_DIFF32, and
1577 + *   b) references a different section than it's in, and
1578 + *   c) references a section that is relaxable
1579 + *
1580 + * as well as relocs that references the constant pool, in which case
1581 + * the add_frag member points to the frag containing the constant pool
1582 + * entry.
1583 + *
1584 + * Such relocs must be fixed up whenever we delete any code. Sections
1585 + * that don't have any relocs with all of the above properties don't
1586 + * have any additional reloc data, but sections that do will have
1587 + * additional data for all its relocs.
1588 + */
1589 +struct avr32_reloc_data
1590 +{
1591 +  struct fragment *add_frag;
1592 +  struct fragment *sub_frag;
1593 +};
1594 +
1595 +/*
1596 + * A 'fragment' is a relaxable entity, that is, code may be added or
1597 + * deleted at the end of a fragment. When this happens, all subsequent
1598 + * fragments in the list will have their offsets updated.
1599 + */
1600 +struct fragment
1601 +{
1602 +  enum relax_state_id state;
1603 +  enum relax_state_id initial_state;
1604 +
1605 +  Elf_Internal_Rela *rela;
1606 +  bfd_size_type size;
1607 +  bfd_vma offset;
1608 +  int size_adjust;
1609 +  int offset_adjust;
1610 +  bfd_boolean has_grown;
1611 +
1612 +  /* Only used by constant pool entries.  When this drops to zero, the
1613 +     frag is discarded (i.e. size_adjust is set to -4.)  */
1614 +  int refcount;
1615 +};
1616 +
1617 +struct avr32_relax_data
1618 +{
1619 +  unsigned int frag_count;
1620 +  struct fragment *frag;
1621 +  struct avr32_reloc_data *reloc_data;
1622 +
1623 +  /* TRUE if this section has one or more relaxable relocations */
1624 +  bfd_boolean is_relaxable;
1625 +  unsigned int iteration;
1626 +};
1627 +
1628 +struct avr32_section_data
1629 +{
1630 +  struct bfd_elf_section_data elf;
1631 +  struct avr32_relax_data relax_data;
1632 +};
1633 +
1634 +\f/* Relax state definitions */
1635 +
1636 +#define PIC_MOV2_OPCODE                0xe0600000
1637 +#define PIC_MOV2_MASK          0xe1e00000
1638 +#define PIC_MOV2_RANGE_MIN     (-1048576 * 4)
1639 +#define PIC_MOV2_RANGE_MAX     (1048575 * 4)
1640 +#define PIC_MCALL_OPCODE       0xf0160000
1641 +#define PIC_MCALL_MASK         0xffff0000
1642 +#define PIC_MCALL_RANGE_MIN    (-131072)
1643 +#define PIC_MCALL_RANGE_MAX    (131068)
1644 +#define RCALL2_OPCODE          0xe0a00000
1645 +#define RCALL2_MASK            0xe1ef0000
1646 +#define RCALL2_RANGE_MIN       (-2097152)
1647 +#define RCALL2_RANGE_MAX       (2097150)
1648 +#define RCALL1_OPCODE          0xc00c0000
1649 +#define RCALL1_MASK            0xf00c0000
1650 +#define RCALL1_RANGE_MIN       (-1024)
1651 +#define RCALL1_RANGE_MAX       (1022)
1652 +#define PIC_LDW4_OPCODE                0xecf00000
1653 +#define PIC_LDW4_MASK          0xfff00000
1654 +#define PIC_LDW4_RANGE_MIN     (-32768)
1655 +#define PIC_LDW4_RANGE_MAX     (32767)
1656 +#define PIC_LDW3_OPCODE                0x6c000000
1657 +#define PIC_LDW3_MASK          0xfe000000
1658 +#define PIC_LDW3_RANGE_MIN     (0)
1659 +#define PIC_LDW3_RANGE_MAX     (124)
1660 +#define SUB5_PC_OPCODE         0xfec00000
1661 +#define SUB5_PC_MASK           0xfff00000
1662 +#define SUB5_PC_RANGE_MIN      (-32768)
1663 +#define SUB5_PC_RANGE_MAX      (32767)
1664 +#define NOPIC_MCALL_OPCODE     0xf01f0000
1665 +#define NOPIC_MCALL_MASK       0xffff0000
1666 +#define NOPIC_MCALL_RANGE_MIN  PIC_MCALL_RANGE_MIN
1667 +#define NOPIC_MCALL_RANGE_MAX  PIC_MCALL_RANGE_MAX
1668 +#define NOPIC_LDW4_OPCODE      0xfef00000
1669 +#define NOPIC_LDW4_MASK                0xfff00000
1670 +#define NOPIC_LDW4_RANGE_MIN   PIC_LDW4_RANGE_MIN
1671 +#define NOPIC_LDW4_RANGE_MAX   PIC_LDW4_RANGE_MAX
1672 +#define LDDPC_OPCODE           0x48000000
1673 +#define LDDPC_MASK             0xf8000000
1674 +#define LDDPC_RANGE_MIN                0
1675 +#define LDDPC_RANGE_MAX                508
1676 +
1677 +#define NOPIC_MOV2_OPCODE  0xe0600000
1678 +#define NOPIC_MOV2_MASK        0xe1e00000
1679 +#define NOPIC_MOV2_RANGE_MIN   (-1048576)
1680 +#define NOPIC_MOV2_RANGE_MAX   (1048575)
1681 +#define NOPIC_MOV1_OPCODE  0x30000000
1682 +#define NOPIC_MOV1_MASK        0xf0000000
1683 +#define NOPIC_MOV1_RANGE_MIN   (-128)
1684 +#define NOPIC_MOV1_RANGE_MAX   (127)
1685 +
1686 +/* Only brc2 variants with cond[3] == 0 is considered, since the
1687 +   others are not relaxable.  bral is a special case and is handled
1688 +   separately.  */
1689 +#define BRC2_OPCODE            0xe0800000
1690 +#define BRC2_MASK              0xe1e80000
1691 +#define BRC2_RANGE_MIN         (-2097152)
1692 +#define BRC2_RANGE_MAX         (2097150)
1693 +#define BRC1_OPCODE            0xc0000000
1694 +#define BRC1_MASK              0xf0080000
1695 +#define BRC1_RANGE_MIN         (-256)
1696 +#define BRC1_RANGE_MAX         (254)
1697 +#define BRAL_OPCODE            0xe08f0000
1698 +#define BRAL_MASK              0xe1ef0000
1699 +#define BRAL_RANGE_MIN         BRC2_RANGE_MIN
1700 +#define BRAL_RANGE_MAX         BRC2_RANGE_MAX
1701 +#define RJMP_OPCODE            0xc0080000
1702 +#define RJMP_MASK              0xf00c0000
1703 +#define RJMP_RANGE_MIN         (-1024)
1704 +#define RJMP_RANGE_MAX         (1022)
1705 +
1706 +/* Define a relax state using the GOT  */
1707 +#define RG(id, dir, next, prev, r_type, opc, size)                     \
1708 +  { "RS_"#id, RS_##id, RS_##dir, RS_##next, RS_##prev, REF_GOT,                \
1709 +      R_AVR32_##r_type,        opc##_OPCODE, opc##_MASK,                       \
1710 +      opc##_RANGE_MIN, opc##_RANGE_MAX, size }
1711 +/* Define a relax state using the Constant Pool  */
1712 +#define RC(id, dir, next, prev, r_type, opc, size)                     \
1713 +  { "RS_"#id, RS_##id, RS_##dir, RS_##next, RS_##prev, REF_CPOOL,      \
1714 +      R_AVR32_##r_type,        opc##_OPCODE, opc##_MASK,                       \
1715 +      opc##_RANGE_MIN, opc##_RANGE_MAX, size }
1716 +
1717 +/* Define a relax state using pc-relative direct reference  */
1718 +#define RP(id, dir, next, prev, r_type, opc, size)                     \
1719 +  { "RS_"#id, RS_##id, RS_##dir, RS_##next, RS_##prev, REF_PCREL,      \
1720 +      R_AVR32_##r_type,        opc##_OPCODE, opc##_MASK,                       \
1721 +      opc##_RANGE_MIN, opc##_RANGE_MAX, size }
1722 +
1723 +/* Define a relax state using non-pc-relative direct reference */
1724 +#define RD(id, dir, next, prev, r_type, opc, size)         \
1725 +  { "RS_"#id, RS_##id, RS_##dir, RS_##next, RS_##prev, REF_ABSOLUTE,   \
1726 +      R_AVR32_##r_type,    opc##_OPCODE, opc##_MASK,           \
1727 +      opc##_RANGE_MIN, opc##_RANGE_MAX, size }
1728 +
1729 +/* Define a relax state that will be handled specially  */
1730 +#define RS(id, r_type, size)                                           \
1731 +  { "RS_"#id, RS_##id, RS_NONE, RS_NONE, RS_NONE, REF_ABSOLUTE,                \
1732 +      R_AVR32_##r_type, 0, 0, 0, 0, size }
1733 +
1734 +const struct relax_state relax_state[RS_MAX] = {
1735 +  RS(NONE, NONE, 0),
1736 +  RS(ALIGN, ALIGN, 0),
1737 +  RS(CPENT, 32_CPENT, 4),
1738 +
1739 +  RG(PIC_CALL, PIC_RCALL1, PIC_MCALL, NONE, GOTCALL, PIC_MOV2, 10),
1740 +  RG(PIC_MCALL, PIC_RCALL1, NONE, PIC_CALL, GOT18SW, PIC_MCALL, 4),
1741 +  RP(PIC_RCALL2, NONE, PIC_RCALL1, PIC_MCALL, 22H_PCREL, RCALL2, 4),
1742 +  RP(PIC_RCALL1, NONE, NONE, PIC_RCALL2, 11H_PCREL, RCALL1, 2),
1743 +
1744 +  RG(PIC_LDA, PIC_SUB5, PIC_LDW4, NONE, LDA_GOT, PIC_MOV2, 8),
1745 +  RG(PIC_LDW4, PIC_SUB5, PIC_LDW3, PIC_LDA, GOT16S, PIC_LDW4, 4),
1746 +  RG(PIC_LDW3, PIC_SUB5, NONE, PIC_LDW4, GOT7UW, PIC_LDW3, 2),
1747 +  RP(PIC_SUB5, NONE, NONE, PIC_LDW3, 16N_PCREL, SUB5_PC, 4),
1748 +
1749 +  RC(NOPIC_MCALL, NOPIC_RCALL1, NONE, NONE, CPCALL, NOPIC_MCALL, 4),
1750 +  RP(NOPIC_RCALL2, NONE, NOPIC_RCALL1, NOPIC_MCALL, 22H_PCREL, RCALL2, 4),
1751 +  RP(NOPIC_RCALL1, NONE, NONE, NOPIC_RCALL2, 11H_PCREL, RCALL1, 2),
1752 +
1753 +  RC(NOPIC_LDW4, NOPIC_MOV1, NOPIC_LDDPC, NONE, 16_CP, NOPIC_LDW4, 4),
1754 +  RC(NOPIC_LDDPC, NOPIC_MOV1, NONE, NOPIC_LDW4, 9W_CP, LDDPC, 2),
1755 +  RP(NOPIC_SUB5, NOPIC_MOV1, NONE, NOPIC_LDDPC, 16N_PCREL, SUB5_PC, 4),
1756 +  RD(NOPIC_MOV2, NONE, NOPIC_MOV1, NOPIC_SUB5, 21S, NOPIC_MOV2, 4),
1757 +  RD(NOPIC_MOV1, NONE, NONE, NOPIC_MOV2, 8S, NOPIC_MOV1, 2),
1758 +
1759 +  RP(RCALL2, NONE, RCALL1, NONE, 22H_PCREL, RCALL2, 4),
1760 +  RP(RCALL1, NONE, NONE, RCALL2, 11H_PCREL, RCALL1, 2),
1761 +  RP(BRC2, NONE, BRC1, NONE, 22H_PCREL, BRC2, 4),
1762 +  RP(BRC1, NONE, NONE, BRC2, 9H_PCREL, BRC1, 2),
1763 +  RP(BRAL, NONE, RJMP, NONE, 22H_PCREL, BRAL, 4),
1764 +  RP(RJMP, NONE, NONE, BRAL, 11H_PCREL, RJMP, 2),
1765 +};
1766 +
1767 +static bfd_boolean
1768 +avr32_elf_new_section_hook(bfd *abfd, asection *sec)
1769 +{
1770 +  struct avr32_section_data *sdata;
1771 +
1772 +  sdata = bfd_zalloc(abfd, sizeof(struct avr32_section_data));
1773 +  if (!sdata)
1774 +    return FALSE;
1775 +
1776 +  sec->used_by_bfd = sdata;
1777 +  return _bfd_elf_new_section_hook(abfd, sec);
1778 +}
1779 +
1780 +static struct avr32_relax_data *
1781 +avr32_relax_data(asection *sec)
1782 +{
1783 +  struct avr32_section_data *sdata;
1784 +
1785 +  BFD_ASSERT(sec->used_by_bfd);
1786 +
1787 +  sdata = (struct avr32_section_data *)elf_section_data(sec);
1788 +  return &sdata->relax_data;
1789 +}
1790 +
1791 +\f/* Link-time relaxation */
1792 +
1793 +static bfd_boolean
1794 +avr32_elf_relax_section(bfd *abfd, asection *sec,
1795 +                       struct bfd_link_info *info, bfd_boolean *again);
1796 +
1797 +enum relax_pass_id {
1798 +  RELAX_PASS_SIZE_FRAGS,
1799 +  RELAX_PASS_MOVE_DATA,
1800 +};
1801 +
1802 +/* Stolen from the xtensa port */
1803 +static int
1804 +internal_reloc_compare (const void *ap, const void *bp)
1805 +{
1806 +  const Elf_Internal_Rela *a = (const Elf_Internal_Rela *) ap;
1807 +  const Elf_Internal_Rela *b = (const Elf_Internal_Rela *) bp;
1808 +
1809 +  if (a->r_offset != b->r_offset)
1810 +    return (a->r_offset - b->r_offset);
1811 +
1812 +  /* We don't need to sort on these criteria for correctness,
1813 +     but enforcing a more strict ordering prevents unstable qsort
1814 +     from behaving differently with different implementations.
1815 +     Without the code below we get correct but different results
1816 +     on Solaris 2.7 and 2.8.  We would like to always produce the
1817 +     same results no matter the host.  */
1818 +
1819 +  if (a->r_info != b->r_info)
1820 +    return (a->r_info - b->r_info);
1821 +
1822 +  return (a->r_addend - b->r_addend);
1823 +}
1824 +
1825 +static enum relax_state_id
1826 +get_pcrel22_relax_state(bfd *abfd, asection *sec, struct bfd_link_info *info,
1827 +                       const Elf_Internal_Rela *rela)
1828 +{
1829 +  bfd_byte *contents;
1830 +  bfd_vma insn;
1831 +  enum relax_state_id rs = RS_NONE;
1832 +
1833 +  contents = retrieve_contents(abfd, sec, info->keep_memory);
1834 +  if (!contents)
1835 +    return RS_ERROR;
1836 +
1837 +  insn = bfd_get_32(abfd, contents + rela->r_offset);
1838 +  if ((insn & RCALL2_MASK) == RCALL2_OPCODE)
1839 +    rs = RS_RCALL2;
1840 +  else if ((insn & BRAL_MASK) == BRAL_OPCODE)
1841 +    /* Optimizing bral -> rjmp gets us into all kinds of
1842 +       trouble with jump tables. Better not do it.  */
1843 +    rs = RS_NONE;
1844 +  else if ((insn & BRC2_MASK) == BRC2_OPCODE)
1845 +    rs = RS_BRC2;
1846 +
1847 +  release_contents(sec, contents);
1848 +
1849 +  return rs;
1850 +}
1851 +
1852 +static enum relax_state_id
1853 +get_initial_relax_state(bfd *abfd, asection *sec, struct bfd_link_info *info,
1854 +                       const Elf_Internal_Rela *rela)
1855 +{
1856 +  switch (ELF_R_TYPE(rela->r_info))
1857 +    {
1858 +    case R_AVR32_GOTCALL:
1859 +      return RS_PIC_CALL;
1860 +    case R_AVR32_GOT18SW:
1861 +      return RS_PIC_MCALL;
1862 +    case R_AVR32_LDA_GOT:
1863 +      return RS_PIC_LDA;
1864 +    case R_AVR32_GOT16S:
1865 +      return RS_PIC_LDW4;
1866 +    case R_AVR32_CPCALL:
1867 +      return RS_NOPIC_MCALL;
1868 +    case R_AVR32_16_CP:
1869 +      return RS_NOPIC_LDW4;
1870 +    case R_AVR32_9W_CP:
1871 +      return RS_NOPIC_LDDPC;
1872 +    case R_AVR32_ALIGN:
1873 +      return RS_ALIGN;
1874 +    case R_AVR32_32_CPENT:
1875 +      return RS_CPENT;
1876 +    case R_AVR32_22H_PCREL:
1877 +      return get_pcrel22_relax_state(abfd, sec, info, rela);
1878 +    case R_AVR32_9H_PCREL:
1879 +      return RS_BRC1;
1880 +    default:
1881 +      return RS_NONE;
1882 +    }
1883 +}
1884 +
1885 +static bfd_boolean
1886 +reloc_is_cpool_ref(const Elf_Internal_Rela *rela)
1887 +{
1888 +  switch (ELF_R_TYPE(rela->r_info))
1889 +    {
1890 +    case R_AVR32_CPCALL:
1891 +    case R_AVR32_16_CP:
1892 +    case R_AVR32_9W_CP:
1893 +      return TRUE;
1894 +    default:
1895 +      return FALSE;
1896 +    }
1897 +}
1898 +
1899 +static struct fragment *
1900 +new_frag(bfd *abfd ATTRIBUTE_UNUSED, asection *sec,
1901 +        struct avr32_relax_data *rd, enum relax_state_id state,
1902 +        Elf_Internal_Rela *rela)
1903 +{
1904 +  struct fragment *frag;
1905 +  bfd_size_type r_size;
1906 +  bfd_vma r_offset;
1907 +  unsigned int i = rd->frag_count;
1908 +
1909 +  BFD_ASSERT(state >= RS_NONE && state < RS_MAX);
1910 +
1911 +  rd->frag_count++;
1912 +  frag = bfd_realloc(rd->frag, sizeof(struct fragment) * rd->frag_count);
1913 +  if (!frag)
1914 +    return NULL;
1915 +  rd->frag = frag;
1916 +
1917 +  frag += i;
1918 +  memset(frag, 0, sizeof(struct fragment));
1919 +
1920 +  if (state == RS_ALIGN)
1921 +    r_size = (((rela->r_offset + (1 << rela->r_addend) - 1)
1922 +              & ~((1 << rela->r_addend) - 1)) - rela->r_offset);
1923 +  else
1924 +    r_size = relax_state[state].size;
1925 +
1926 +  if (rela)
1927 +    r_offset = rela->r_offset;
1928 +  else
1929 +    r_offset = sec->size;
1930 +
1931 +  if (i == 0)
1932 +    {
1933 +      frag->offset = 0;
1934 +      frag->size = r_offset + r_size;
1935 +    }
1936 +  else
1937 +    {
1938 +      frag->offset = rd->frag[i - 1].offset + rd->frag[i - 1].size;
1939 +      frag->size = r_offset + r_size - frag->offset;
1940 +    }
1941 +
1942 +  if (state != RS_CPENT)
1943 +    /* Make sure we don't discard this frag */
1944 +    frag->refcount = 1;
1945 +
1946 +  frag->initial_state = frag->state = state;
1947 +  frag->rela = rela;
1948 +
1949 +  return frag;
1950 +}
1951 +
1952 +static struct fragment *
1953 +find_frag(asection *sec, bfd_vma offset)
1954 +{
1955 +  struct fragment *first, *last;
1956 +  struct avr32_relax_data *rd = avr32_relax_data(sec);
1957 +
1958 +  if (rd->frag_count == 0)
1959 +    return NULL;
1960 +
1961 +  first = &rd->frag[0];
1962 +  last = &rd->frag[rd->frag_count - 1];
1963 +
1964 +  /* This may be a reloc referencing the end of a section.  The last
1965 +     frag will never have a reloc associated with it, so its size will
1966 +     never change, thus the offset adjustment of the last frag will
1967 +     always be the same as the offset adjustment of the end of the
1968 +     section.  */
1969 +  if (offset == sec->size)
1970 +    {
1971 +      BFD_ASSERT(last->offset + last->size == sec->size);
1972 +      BFD_ASSERT(!last->rela);
1973 +      return last;
1974 +    }
1975 +
1976 +  while (first <= last)
1977 +    {
1978 +      struct fragment *mid;
1979 +
1980 +      mid = (last - first) / 2 + first;
1981 +      if ((mid->offset + mid->size) <= offset)
1982 +       first = mid + 1;
1983 +      else if (mid->offset > offset)
1984 +       last = mid - 1;
1985 +      else
1986 +       return mid;
1987 +    }
1988 +
1989 +  return NULL;
1990 +}
1991 +
1992 +/* Look through all relocs in a section and determine if any relocs
1993 +   may be affected by relaxation in other sections.  If so, allocate
1994 +   an array of additional relocation data which links the affected
1995 +   relocations to the frag(s) where the relaxation may occur.
1996 +
1997 +   This function also links cpool references to cpool entries and
1998 +   increments the refcount of the latter when this happens.  */
1999 +
2000 +static bfd_boolean
2001 +allocate_reloc_data(bfd *abfd, asection *sec, Elf_Internal_Rela *relocs,
2002 +                   struct bfd_link_info *info)
2003 +{
2004 +  Elf_Internal_Shdr *symtab_hdr;
2005 +  Elf_Internal_Sym *isymbuf = NULL;
2006 +  struct avr32_relax_data *rd;
2007 +  unsigned int i;
2008 +  bfd_boolean ret = FALSE;
2009 +
2010 +  symtab_hdr = &elf_tdata(abfd)->symtab_hdr;
2011 +  rd = avr32_relax_data(sec);
2012 +
2013 +  RDBG("%s<%s>: allocate_reloc_data\n", abfd->filename, sec->name);
2014 +
2015 +  for (i = 0; i < sec->reloc_count; i++)
2016 +    {
2017 +      Elf_Internal_Rela *rel = &relocs[i];
2018 +      asection *sym_sec;
2019 +      unsigned long r_symndx;
2020 +      bfd_vma sym_value;
2021 +
2022 +      if (!rel->r_addend && ELF_R_TYPE(rel->r_info) != R_AVR32_DIFF32
2023 +         && !reloc_is_cpool_ref(rel))
2024 +       continue;
2025 +
2026 +      r_symndx = ELF_R_SYM(rel->r_info);
2027 +
2028 +      if (r_symndx < symtab_hdr->sh_info)
2029 +       {
2030 +         Elf_Internal_Sym *isym;
2031 +
2032 +         if (!isymbuf)
2033 +           isymbuf = retrieve_local_syms(abfd, info->keep_memory);
2034 +         if (!isymbuf)
2035 +           return FALSE;
2036 +
2037 +         isym = &isymbuf[r_symndx];
2038 +         sym_sec = bfd_section_from_elf_index(abfd, isym->st_shndx);
2039 +         sym_value = isym->st_value;
2040 +       }
2041 +      else
2042 +       {
2043 +         struct elf_link_hash_entry *h;
2044 +
2045 +         h = elf_sym_hashes(abfd)[r_symndx - symtab_hdr->sh_info];
2046 +
2047 +         while (h->root.type == bfd_link_hash_indirect
2048 +                || h->root.type == bfd_link_hash_warning)
2049 +           h = (struct elf_link_hash_entry *)h->root.u.i.link;
2050 +
2051 +         if (h->root.type != bfd_link_hash_defined
2052 +             && h->root.type != bfd_link_hash_defweak)
2053 +           continue;
2054 +
2055 +         sym_sec = h->root.u.def.section;
2056 +         sym_value = h->root.u.def.value;
2057 +       }
2058 +
2059 +      if (sym_sec && avr32_relax_data(sym_sec)->is_relaxable)
2060 +       {
2061 +         bfd_size_type size;
2062 +         struct fragment *frag;
2063 +
2064 +         if (!rd->reloc_data)
2065 +           {
2066 +             size = sizeof(struct avr32_reloc_data) * sec->reloc_count;
2067 +             rd->reloc_data = bfd_zalloc(abfd, size);
2068 +             if (!rd->reloc_data)
2069 +               goto out;
2070 +           }
2071 +
2072 +         RDBG("[%3d] 0x%04lx: target: 0x%lx + 0x%lx",
2073 +              i, rel->r_offset, sym_value, rel->r_addend);
2074 +
2075 +         frag = find_frag(sym_sec, sym_value + rel->r_addend);
2076 +         BFD_ASSERT(frag);
2077 +         rd->reloc_data[i].add_frag = frag;
2078 +
2079 +         RDBG(" -> %s<%s>:%04lx\n", sym_sec->owner->filename, sym_sec->name,
2080 +              frag->rela ? frag->rela->r_offset : sym_sec->size);
2081 +
2082 +         if (reloc_is_cpool_ref(rel))
2083 +           {
2084 +             BFD_ASSERT(ELF_R_TYPE(frag->rela->r_info) == R_AVR32_32_CPENT);
2085 +             frag->refcount++;
2086 +           }
2087 +
2088 +         if (ELF_R_TYPE(rel->r_info) == R_AVR32_DIFF32)
2089 +           {
2090 +             bfd_byte *contents;
2091 +             bfd_signed_vma diff;
2092 +
2093 +             contents = retrieve_contents(abfd, sec, info->keep_memory);
2094 +             if (!contents)
2095 +               goto out;
2096 +
2097 +             diff = bfd_get_signed_32(abfd, contents + rel->r_offset);
2098 +             frag = find_frag(sym_sec, sym_value + rel->r_addend + diff);
2099 +             BFD_ASSERT(frag);
2100 +             rd->reloc_data[i].sub_frag = frag;
2101 +
2102 +             release_contents(sec, contents);
2103 +           }
2104 +       }
2105 +    }
2106 +
2107 +  ret = TRUE;
2108 +
2109 + out:
2110 +  release_local_syms(abfd, isymbuf);
2111 +  return ret;
2112 +}
2113 +
2114 +static bfd_boolean
2115 +global_sym_set_frag(struct elf_avr32_link_hash_entry *havr,
2116 +                   struct bfd_link_info *info ATTRIBUTE_UNUSED)
2117 +{
2118 +  struct fragment *frag;
2119 +  asection *sec;
2120 +
2121 +  if (havr->root.root.type != bfd_link_hash_defined
2122 +      && havr->root.root.type != bfd_link_hash_defweak)
2123 +    return TRUE;
2124 +
2125 +  sec = havr->root.root.u.def.section;
2126 +  if (bfd_is_const_section(sec)
2127 +      || !avr32_relax_data(sec)->is_relaxable)
2128 +    return TRUE;
2129 +
2130 +  frag = find_frag(sec, havr->root.root.u.def.value);
2131 +  if (!frag)
2132 +    {
2133 +      unsigned int i;
2134 +      struct avr32_relax_data *rd = avr32_relax_data(sec);
2135 +
2136 +      RDBG("In %s: No frag for %s <%s+%lu> (limit %lu)\n",
2137 +          sec->owner->filename, havr->root.root.root.string,
2138 +          sec->name, havr->root.root.u.def.value, sec->size);
2139 +      for (i = 0; i < rd->frag_count; i++)
2140 +       RDBG("    %8lu - %8lu\n", rd->frag[i].offset,
2141 +            rd->frag[i].offset + rd->frag[i].size);
2142 +    }
2143 +  BFD_ASSERT(frag);
2144 +
2145 +  havr->sym_frag = frag;
2146 +  return TRUE;
2147 +}
2148 +
2149 +static bfd_boolean
2150 +analyze_relocations(struct bfd_link_info *info)
2151 +{
2152 +  bfd *abfd;
2153 +  asection *sec;
2154 +
2155 +  /* Divide all relaxable sections into fragments */
2156 +  for (abfd = info->input_bfds; abfd; abfd = abfd->link_next)
2157 +    {
2158 +      if (!(elf_elfheader(abfd)->e_flags & EF_AVR32_LINKRELAX))
2159 +       {
2160 +         if (!(*info->callbacks->warning)
2161 +             (info, _("input is not relaxable"), NULL, abfd, NULL, 0))
2162 +           return FALSE;
2163 +         continue;
2164 +       }
2165 +
2166 +      for (sec = abfd->sections; sec; sec = sec->next)
2167 +       {
2168 +         struct avr32_relax_data *rd;
2169 +         struct fragment *frag;
2170 +         Elf_Internal_Rela *relocs;
2171 +         unsigned int i;
2172 +         bfd_boolean ret = TRUE;
2173 +
2174 +         if (!(sec->flags & SEC_RELOC) || sec->reloc_count == 0)
2175 +           continue;
2176 +
2177 +         rd = avr32_relax_data(sec);
2178 +
2179 +         relocs = retrieve_internal_relocs(abfd, sec, info->keep_memory);
2180 +         if (!relocs)
2181 +           return FALSE;
2182 +
2183 +         qsort(relocs, sec->reloc_count, sizeof(Elf_Internal_Rela),
2184 +               internal_reloc_compare);
2185 +
2186 +         for (i = 0; i < sec->reloc_count; i++)
2187 +           {
2188 +             enum relax_state_id state;
2189 +
2190 +             ret = FALSE;
2191 +             state = get_initial_relax_state(abfd, sec, info, &relocs[i]);
2192 +             if (state == RS_ERROR)
2193 +               break;
2194 +
2195 +             if (state)
2196 +               {
2197 +                 frag = new_frag(abfd, sec, rd, state, &relocs[i]);
2198 +                 if (!frag)
2199 +                   break;
2200 +
2201 +                 pin_internal_relocs(sec, relocs);
2202 +                 rd->is_relaxable = TRUE;
2203 +               }
2204 +
2205 +             ret = TRUE;
2206 +           }
2207 +
2208 +         release_internal_relocs(sec, relocs);
2209 +         if (!ret)
2210 +           return ret;
2211 +
2212 +         if (rd->is_relaxable)
2213 +           {
2214 +             frag = new_frag(abfd, sec, rd, RS_NONE, NULL);
2215 +             if (!frag)
2216 +               return FALSE;
2217 +           }
2218 +       }
2219 +    }
2220 +
2221 +  /* Link each global symbol to the fragment where it's defined.  */
2222 +  elf_link_hash_traverse(elf_hash_table(info), global_sym_set_frag, info);
2223 +
2224 +  /* Do the same for local symbols. */
2225 +  for (abfd = info->input_bfds; abfd; abfd = abfd->link_next)
2226 +    {
2227 +      Elf_Internal_Sym *isymbuf, *isym;
2228 +      struct fragment **local_sym_frag;
2229 +      unsigned int i, sym_count;
2230 +
2231 +      sym_count = elf_tdata(abfd)->symtab_hdr.sh_info;
2232 +      if (sym_count == 0)
2233 +       continue;
2234 +
2235 +      local_sym_frag = bfd_zalloc(abfd, sym_count * sizeof(struct fragment *));
2236 +      if (!local_sym_frag)
2237 +       return FALSE;
2238 +      elf_tdata(abfd)->local_sym_frag = local_sym_frag;
2239 +
2240 +      isymbuf = retrieve_local_syms(abfd, info->keep_memory);
2241 +      if (!isymbuf)
2242 +       return FALSE;
2243 +
2244 +      for (i = 0; i < sym_count; i++)
2245 +       {
2246 +         struct avr32_relax_data *rd;
2247 +         struct fragment *frag;
2248 +         asection *sec;
2249 +
2250 +         isym = &isymbuf[i];
2251 +
2252 +         sec = bfd_section_from_elf_index(abfd, isym->st_shndx);
2253 +         if (!sec)
2254 +           continue;
2255 +
2256 +         rd = avr32_relax_data(sec);
2257 +         if (!rd->is_relaxable)
2258 +           continue;
2259 +
2260 +         frag = find_frag(sec, isym->st_value);
2261 +         BFD_ASSERT(frag);
2262 +
2263 +         local_sym_frag[i] = frag;
2264 +       }
2265 +
2266 +      release_local_syms(abfd, isymbuf);
2267 +    }
2268 +
2269 +  /* And again for relocs with addends and constant pool references */
2270 +  for (abfd = info->input_bfds; abfd; abfd = abfd->link_next)
2271 +    for (sec = abfd->sections; sec; sec = sec->next)
2272 +      {
2273 +       Elf_Internal_Rela *relocs;
2274 +       bfd_boolean ret;
2275 +
2276 +       if (!(sec->flags & SEC_RELOC) || sec->reloc_count == 0)
2277 +         continue;
2278 +
2279 +       relocs = retrieve_internal_relocs(abfd, sec, info->keep_memory);
2280 +       if (!relocs)
2281 +         return FALSE;
2282 +
2283 +       ret = allocate_reloc_data(abfd, sec, relocs, info);
2284 +
2285 +       release_internal_relocs(sec, relocs);
2286 +       if (ret == FALSE)
2287 +         return ret;
2288 +      }
2289 +
2290 +  return TRUE;
2291 +}
2292 +
2293 +static bfd_boolean
2294 +rs_is_good_enough(const struct relax_state *rs, struct fragment *frag,
2295 +                 bfd_vma symval, bfd_vma addr, struct got_entry *got,
2296 +                 struct avr32_reloc_data *ind_data,
2297 +                 bfd_signed_vma offset_adjust)
2298 +{
2299 +  bfd_signed_vma target = 0;
2300 +
2301 +  switch (rs->reftype)
2302 +    {
2303 +    case REF_ABSOLUTE:
2304 +      target = symval;
2305 +      break;
2306 +    case REF_PCREL:
2307 +      target = symval - addr;
2308 +      break;
2309 +    case REF_CPOOL:
2310 +      /* cpool frags are always in the same section and always after
2311 +        all frags referring to it.  So it's always correct to add in
2312 +        offset_adjust here.  */
2313 +      target = (ind_data->add_frag->offset + ind_data->add_frag->offset_adjust
2314 +               + offset_adjust - frag->offset - frag->offset_adjust);
2315 +      break;
2316 +    case REF_GOT:
2317 +      target = got->offset;
2318 +      break;
2319 +    default:
2320 +      abort();
2321 +    }
2322 +
2323 +  if (target >= rs->range_min && target <= rs->range_max)
2324 +    return TRUE;
2325 +  else
2326 +    return FALSE;
2327 +}
2328 +
2329 +static bfd_boolean
2330 +avr32_size_frags(bfd *abfd, asection *sec, struct bfd_link_info *info)
2331 +{
2332 +  struct elf_avr32_link_hash_table *htab;
2333 +  struct avr32_relax_data *rd;
2334 +  Elf_Internal_Shdr *symtab_hdr;
2335 +  Elf_Internal_Rela *relocs = NULL;
2336 +  Elf_Internal_Sym *isymbuf = NULL;
2337 +  struct got_entry **local_got_ents;
2338 +  struct fragment **local_sym_frag;
2339 +  bfd_boolean ret = FALSE;
2340 +  bfd_signed_vma delta = 0;
2341 +  unsigned int i;
2342 +
2343 +  htab = avr32_elf_hash_table(info);
2344 +  rd = avr32_relax_data(sec);
2345 +
2346 +  if (sec == htab->sgot)
2347 +    {
2348 +      RDBG("Relaxing GOT section (vma: 0x%lx)\n",
2349 +          sec->output_section->vma + sec->output_offset);
2350 +      if (assign_got_offsets(htab))
2351 +       htab->repeat_pass = TRUE;
2352 +      return TRUE;
2353 +    }
2354 +
2355 +  if (!rd->is_relaxable)
2356 +    return TRUE;
2357 +
2358 +  if (!sec->rawsize)
2359 +    sec->rawsize = sec->size;
2360 +
2361 +  symtab_hdr = &elf_tdata(abfd)->symtab_hdr;
2362 +  relocs = retrieve_internal_relocs(abfd, sec, info->keep_memory);
2363 +  if (!relocs)
2364 +    goto out;
2365 +
2366 +  isymbuf = retrieve_local_syms(abfd, info->keep_memory);
2367 +  if (!isymbuf)
2368 +    goto out;
2369 +
2370 +  local_got_ents = elf_local_got_ents(abfd);
2371 +  local_sym_frag = elf_tdata(abfd)->local_sym_frag;
2372 +
2373 +  RDBG("size_frags: %s<%s>\n  vma: 0x%08lx, size: 0x%08lx\n",
2374 +       abfd->filename, sec->name,
2375 +       sec->output_section->vma + sec->output_offset, sec->size);
2376 +
2377 +  for (i = 0; i < rd->frag_count; i++)
2378 +    {
2379 +      struct fragment *frag = &rd->frag[i];
2380 +      struct avr32_reloc_data *r_data = NULL, *ind_data = NULL;
2381 +      const struct relax_state *state, *next_state;
2382 +      struct fragment *target_frag = NULL;
2383 +      asection *sym_sec = NULL;
2384 +      Elf_Internal_Rela *rela;
2385 +      struct got_entry *got;
2386 +      bfd_vma symval, r_offset, addend, addr;
2387 +      bfd_signed_vma size_adjust = 0, distance;
2388 +      unsigned long r_symndx;
2389 +      bfd_boolean defined = TRUE, dynamic = FALSE;
2390 +      unsigned char sym_type;
2391 +
2392 +      frag->offset_adjust += delta;
2393 +      state = next_state = &relax_state[frag->state];
2394 +      rela = frag->rela;
2395 +
2396 +      BFD_ASSERT(state->id == frag->state);
2397 +
2398 +      RDBG("  0x%04lx%c%d: %s [size %ld]", rela ? rela->r_offset : sec->rawsize,
2399 +          (frag->offset_adjust < 0)?'-':'+',
2400 +          abs(frag->offset_adjust), state->name, state->size);
2401 +
2402 +      if (!rela)
2403 +       {
2404 +         RDBG(": no reloc, ignoring\n");
2405 +         continue;
2406 +       }
2407 +
2408 +      BFD_ASSERT((unsigned int)(rela - relocs) < sec->reloc_count);
2409 +      BFD_ASSERT(state != RS_NONE);
2410 +
2411 +      r_offset = rela->r_offset + frag->offset_adjust;
2412 +      addr = sec->output_section->vma + sec->output_offset + r_offset;
2413 +
2414 +      switch (frag->state)
2415 +       {
2416 +       case RS_ALIGN:
2417 +         size_adjust = ((addr + (1 << rela->r_addend) - 1)
2418 +                        & ~((1 << rela->r_addend) - 1));
2419 +         size_adjust -= (sec->output_section->vma + sec->output_offset
2420 +                         + frag->offset + frag->offset_adjust
2421 +                         + frag->size + frag->size_adjust);
2422 +
2423 +         RDBG(": adjusting size %lu -> %lu\n", frag->size + frag->size_adjust,
2424 +              frag->size + frag->size_adjust + size_adjust);
2425 +         break;
2426 +
2427 +       case RS_CPENT:
2428 +         if (frag->refcount == 0 && frag->size_adjust == 0)
2429 +           {
2430 +             RDBG(": discarding frag\n");
2431 +             size_adjust = -4;
2432 +           }
2433 +         else if (frag->refcount > 0 && frag->size_adjust < 0)
2434 +           {
2435 +             RDBG(": un-discarding frag\n");
2436 +             size_adjust = 4;
2437 +           }
2438 +         break;
2439 +
2440 +       default:
2441 +         if (rd->reloc_data)
2442 +           r_data = &rd->reloc_data[frag->rela - relocs];
2443 +
2444 +         /* If this is a cpool reference, we want the symbol that the
2445 +            cpool entry refers to, not the symbol for the cpool entry
2446 +            itself, as we already know what frag it's in.  */
2447 +         if (relax_state[frag->initial_state].reftype == REF_CPOOL)
2448 +           {
2449 +             Elf_Internal_Rela *irela = r_data->add_frag->rela;
2450 +
2451 +             r_symndx = ELF_R_SYM(irela->r_info);
2452 +             addend = irela->r_addend;
2453 +
2454 +             /* The constant pool must be in the same section as the
2455 +                reloc referring to it.  */
2456 +             BFD_ASSERT((unsigned long)(irela - relocs) < sec->reloc_count);
2457 +
2458 +             ind_data = r_data;
2459 +             r_data = &rd->reloc_data[irela - relocs];
2460 +           }
2461 +         else
2462 +           {
2463 +             r_symndx = ELF_R_SYM(rela->r_info);
2464 +             addend = rela->r_addend;
2465 +           }
2466 +
2467 +         /* Get the value of the symbol referred to by the reloc.  */
2468 +         if (r_symndx < symtab_hdr->sh_info)
2469 +           {
2470 +             Elf_Internal_Sym *isym;
2471 +
2472 +             isym = isymbuf + r_symndx;
2473 +             symval = 0;
2474 +
2475 +             RDBG(" local sym %lu: ", r_symndx);
2476 +
2477 +             if (isym->st_shndx == SHN_UNDEF)
2478 +               defined = FALSE;
2479 +             else if (isym->st_shndx == SHN_ABS)
2480 +               sym_sec = bfd_abs_section_ptr;
2481 +             else if (isym->st_shndx == SHN_COMMON)
2482 +               sym_sec = bfd_com_section_ptr;
2483 +             else
2484 +               sym_sec = bfd_section_from_elf_index(abfd, isym->st_shndx);
2485 +
2486 +             symval = isym->st_value;
2487 +             sym_type = ELF_ST_TYPE(isym->st_info);
2488 +             target_frag = local_sym_frag[r_symndx];
2489 +
2490 +             if (local_got_ents)
2491 +               got = local_got_ents[r_symndx];
2492 +             else
2493 +               got = NULL;
2494 +           }
2495 +         else
2496 +           {
2497 +             /* Global symbol */
2498 +             unsigned long index;
2499 +             struct elf_link_hash_entry *h;
2500 +             struct elf_avr32_link_hash_entry *havr;
2501 +
2502 +             index = r_symndx - symtab_hdr->sh_info;
2503 +             h = elf_sym_hashes(abfd)[index];
2504 +             BFD_ASSERT(h != NULL);
2505 +
2506 +             while (h->root.type == bfd_link_hash_indirect
2507 +                    || h->root.type == bfd_link_hash_warning)
2508 +               h = (struct elf_link_hash_entry *)h->root.u.i.link;
2509 +
2510 +             havr = (struct elf_avr32_link_hash_entry *)h;
2511 +             got = h->got.glist;
2512 +
2513 +             symval = 0;
2514 +
2515 +             RDBG(" %s: ", h->root.root.string);
2516 +
2517 +             if (h->root.type != bfd_link_hash_defined
2518 +                 && h->root.type != bfd_link_hash_defweak)
2519 +               {
2520 +                 RDBG("(undef)");
2521 +                 defined = FALSE;
2522 +               }
2523 +             else if ((info->shared && !info->symbolic && h->dynindx != -1)
2524 +                      || (htab->root.dynamic_sections_created
2525 +                          && h->def_dynamic && !h->def_regular))
2526 +               {
2527 +                 RDBG("(dynamic)");
2528 +                 dynamic = TRUE;
2529 +                 sym_sec = h->root.u.def.section;
2530 +               }
2531 +             else
2532 +               {
2533 +                 sym_sec = h->root.u.def.section;
2534 +                 symval = h->root.u.def.value;
2535 +                 target_frag = havr->sym_frag;
2536 +               }
2537 +
2538 +             sym_type = h->type;
2539 +           }
2540 +
2541 +         /* Thanks to elf32-ppc for this one.  */
2542 +         if (sym_sec && sym_sec->sec_info_type == ELF_INFO_TYPE_MERGE)
2543 +           {
2544 +             /* At this stage in linking, no SEC_MERGE symbol has been
2545 +                adjusted, so all references to such symbols need to be
2546 +                passed through _bfd_merged_section_offset.  (Later, in
2547 +                relocate_section, all SEC_MERGE symbols *except* for
2548 +                section symbols have been adjusted.)
2549 +
2550 +                SEC_MERGE sections are not relaxed by us, as they
2551 +                shouldn't contain any code.  */
2552 +
2553 +             BFD_ASSERT(!target_frag && !(r_data && r_data->add_frag));
2554 +
2555 +             /* gas may reduce relocations against symbols in SEC_MERGE
2556 +                sections to a relocation against the section symbol when
2557 +                the original addend was zero.  When the reloc is against
2558 +                a section symbol we should include the addend in the
2559 +                offset passed to _bfd_merged_section_offset, since the
2560 +                location of interest is the original symbol.  On the
2561 +                other hand, an access to "sym+addend" where "sym" is not
2562 +                a section symbol should not include the addend;  Such an
2563 +                access is presumed to be an offset from "sym";  The
2564 +                location of interest is just "sym".  */
2565 +             RDBG("\n    MERGE: %s: 0x%lx+0x%lx+0x%lx -> ",
2566 +                  (sym_type == STT_SECTION)?"section":"not section",
2567 +                  sym_sec->output_section->vma + sym_sec->output_offset,
2568 +                  symval, addend);
2569 +
2570 +             if (sym_type == STT_SECTION)
2571 +               symval += addend;
2572 +
2573 +             symval = (_bfd_merged_section_offset
2574 +                       (abfd, &sym_sec,
2575 +                        elf_section_data(sym_sec)->sec_info, symval));
2576 +
2577 +             if (sym_type != STT_SECTION)
2578 +               symval += addend;
2579 +           }
2580 +         else
2581 +           symval += addend;
2582 +
2583 +         if (defined && !dynamic)
2584 +           {
2585 +             RDBG("0x%lx+0x%lx",
2586 +                  sym_sec->output_section->vma + sym_sec->output_offset,
2587 +                  symval);
2588 +             symval += sym_sec->output_section->vma + sym_sec->output_offset;
2589 +           }
2590 +
2591 +         if (r_data && r_data->add_frag)
2592 +           /* If the add_frag pointer is set, it means that this reloc
2593 +              has an addend that may be affected by relaxation.  */
2594 +           target_frag = r_data->add_frag;
2595 +
2596 +         if (target_frag)
2597 +           {
2598 +             symval += target_frag->offset_adjust;
2599 +
2600 +             /* If target_frag comes after this frag in the same
2601 +                section, we should assume that it will be moved by
2602 +                the same amount we are.  */
2603 +             if ((target_frag - rd->frag) < (int)rd->frag_count
2604 +                 && target_frag > frag)
2605 +               symval += delta;
2606 +           }
2607 +
2608 +         distance = symval - addr;
2609 +
2610 +         /* First, try to make a direct reference.  If the symbol is
2611 +            dynamic or undefined, we must take care not to change its
2612 +            reference type, that is, we can't make it direct.
2613 +
2614 +            Also, it seems like some sections may actually be resized
2615 +            after the relaxation code is done, so we can't really
2616 +            trust that our "distance" is correct.  There's really no
2617 +            easy solution to this problem, so we'll just disallow
2618 +            direct references to SEC_DATA sections.
2619 +
2620 +            Oh, and .bss isn't actually SEC_DATA, so we disallow
2621 +            !SEC_HAS_CONTENTS as well. */
2622 +         if (!dynamic && defined
2623 +             && (htab->direct_data_refs
2624 +                 || (!(sym_sec->flags & SEC_DATA)
2625 +                     && (sym_sec->flags & SEC_HAS_CONTENTS)))
2626 +             && next_state->direct)
2627 +           {
2628 +             next_state = &relax_state[next_state->direct];
2629 +             RDBG(" D-> %s", next_state->name);
2630 +           }
2631 +
2632 +         /* Iterate backwards until we find a state that fits.  */
2633 +         while (next_state->prev
2634 +                && !rs_is_good_enough(next_state, frag, symval, addr,
2635 +                                      got, ind_data, delta))
2636 +           {
2637 +             next_state = &relax_state[next_state->prev];
2638 +             RDBG(" P-> %s", next_state->name);
2639 +           }
2640 +
2641 +         /* Then try to find the best possible state.  */
2642 +         while (next_state->next)
2643 +           {
2644 +             const struct relax_state *candidate;
2645 +
2646 +             candidate = &relax_state[next_state->next];
2647 +             if (!rs_is_good_enough(candidate, frag, symval, addr, got,
2648 +                                    ind_data, delta))
2649 +               break;
2650 +
2651 +             next_state = candidate;
2652 +             RDBG(" N-> %s", next_state->name);
2653 +           }
2654 +
2655 +         RDBG(" [size %ld]\n", next_state->size);
2656 +
2657 +         BFD_ASSERT(next_state->id);
2658 +         BFD_ASSERT(!dynamic || next_state->reftype == REF_GOT);
2659 +
2660 +         size_adjust = next_state->size - state->size;
2661 +
2662 +         /* There's a theoretical possibility that shrinking one frag
2663 +            may cause another to grow, which may cause the first one to
2664 +            grow as well, and we're back where we started.  Avoid this
2665 +            scenario by disallowing a frag that has grown to ever
2666 +            shrink again.  */
2667 +         if (state->reftype == REF_GOT && next_state->reftype != REF_GOT)
2668 +           {
2669 +             if (frag->has_grown)
2670 +               next_state = state;
2671 +             else
2672 +               unref_got_entry(htab, got);
2673 +           }
2674 +         else if (state->reftype != REF_GOT && next_state->reftype == REF_GOT)
2675 +           {
2676 +             ref_got_entry(htab, got);
2677 +             frag->has_grown = TRUE;
2678 +           }
2679 +         else if (state->reftype == REF_CPOOL
2680 +                  && next_state->reftype != REF_CPOOL)
2681 +           {
2682 +             if (frag->has_grown)
2683 +               next_state = state;
2684 +             else
2685 +               ind_data->add_frag->refcount--;
2686 +           }
2687 +         else if (state->reftype != REF_CPOOL
2688 +                  && next_state->reftype == REF_CPOOL)
2689 +           {
2690 +             ind_data->add_frag->refcount++;
2691 +             frag->has_grown = TRUE;
2692 +           }
2693 +         else
2694 +           {
2695 +             if (frag->has_grown && size_adjust < 0)
2696 +               next_state = state;
2697 +             else if (size_adjust > 0)
2698 +               frag->has_grown = TRUE;
2699 +           }
2700 +
2701 +         size_adjust = next_state->size - state->size;
2702 +         frag->state = next_state->id;
2703 +
2704 +         break;
2705 +       }
2706 +
2707 +      if (size_adjust)
2708 +       htab->repeat_pass = TRUE;
2709 +
2710 +      frag->size_adjust += size_adjust;
2711 +      sec->size += size_adjust;
2712 +      delta += size_adjust;
2713 +
2714 +      BFD_ASSERT((frag->offset + frag->offset_adjust
2715 +                 + frag->size + frag->size_adjust)
2716 +                == (frag[1].offset + frag[1].offset_adjust + delta));
2717 +    }
2718 +
2719 +  ret = TRUE;
2720 +
2721 + out:
2722 +  release_local_syms(abfd, isymbuf);
2723 +  release_internal_relocs(sec, relocs);
2724 +  return ret;
2725 +}
2726 +
2727 +static bfd_boolean
2728 +adjust_global_symbol(struct elf_avr32_link_hash_entry *havr,
2729 +                    struct bfd_link_info *info ATTRIBUTE_UNUSED)
2730 +{
2731 +  struct elf_link_hash_entry *h = &havr->root;
2732 +
2733 +  if (havr->sym_frag && (h->root.type == bfd_link_hash_defined
2734 +                        || h->root.type == bfd_link_hash_defweak))
2735 +    {
2736 +      RDBG("adjust_global_symbol: %s 0x%08lx -> 0x%08lx\n",
2737 +          h->root.root.string, h->root.u.def.value,
2738 +          h->root.u.def.value + havr->sym_frag->offset_adjust);
2739 +      h->root.u.def.value += havr->sym_frag->offset_adjust;
2740 +    }
2741 +  return TRUE;
2742 +}
2743 +
2744 +static bfd_boolean
2745 +adjust_syms(struct bfd_link_info *info)
2746 +{
2747 +  struct elf_avr32_link_hash_table *htab;
2748 +  bfd *abfd;
2749 +
2750 +  htab = avr32_elf_hash_table(info);
2751 +  elf_link_hash_traverse(&htab->root, adjust_global_symbol, info);
2752 +
2753 +  for (abfd = info->input_bfds; abfd; abfd = abfd->link_next)
2754 +    {
2755 +      Elf_Internal_Sym *isymbuf;
2756 +      struct fragment **local_sym_frag, *frag;
2757 +      unsigned int i, sym_count;
2758 +
2759 +      sym_count = elf_tdata(abfd)->symtab_hdr.sh_info;
2760 +      if (sym_count == 0)
2761 +       continue;
2762 +
2763 +      isymbuf = retrieve_local_syms(abfd, info->keep_memory);
2764 +      if (!isymbuf)
2765 +       return FALSE;
2766 +
2767 +      local_sym_frag = elf_tdata(abfd)->local_sym_frag;
2768 +
2769 +      for (i = 0; i < sym_count; i++)
2770 +       {
2771 +         frag = local_sym_frag[i];
2772 +         if (frag)
2773 +           {
2774 +             RDBG("adjust_local_symbol: %s[%u] 0x%08lx -> 0x%08lx\n",
2775 +                  abfd->filename, i, isymbuf[i].st_value,
2776 +                  isymbuf[i].st_value + frag->offset_adjust);
2777 +             isymbuf[i].st_value += frag->offset_adjust;
2778 +           }
2779 +       }
2780 +
2781 +      release_local_syms(abfd, isymbuf);
2782 +    }
2783 +
2784 +  htab->symbols_adjusted = TRUE;
2785 +  return TRUE;
2786 +}
2787 +
2788 +static bfd_boolean
2789 +adjust_relocs(bfd *abfd, asection *sec, struct bfd_link_info *info)
2790 +{
2791 +  struct avr32_relax_data *rd;
2792 +  Elf_Internal_Rela *relocs;
2793 +  Elf_Internal_Shdr *symtab_hdr;
2794 +  unsigned int i;
2795 +  bfd_boolean ret = FALSE;
2796 +
2797 +  rd = avr32_relax_data(sec);
2798 +  if (!rd->reloc_data)
2799 +    return TRUE;
2800 +
2801 +  RDBG("adjust_relocs: %s<%s> (count: %u)\n", abfd->filename, sec->name,
2802 +       sec->reloc_count);
2803 +
2804 +  relocs = retrieve_internal_relocs(abfd, sec, info->keep_memory);
2805 +  if (!relocs)
2806 +    return FALSE;
2807 +
2808 +  symtab_hdr = &elf_tdata(abfd)->symtab_hdr;
2809 +
2810 +  for (i = 0; i < sec->reloc_count; i++)
2811 +    {
2812 +      Elf_Internal_Rela *rela = &relocs[i];
2813 +      struct avr32_reloc_data *r_data = &rd->reloc_data[i];
2814 +      struct fragment *sym_frag;
2815 +      unsigned long r_symndx;
2816 +
2817 +      if (r_data->add_frag)
2818 +       {
2819 +         r_symndx = ELF_R_SYM(rela->r_info);
2820 +
2821 +         if (r_symndx < symtab_hdr->sh_info)
2822 +           sym_frag = elf_tdata(abfd)->local_sym_frag[r_symndx];
2823 +         else
2824 +           {
2825 +             struct elf_link_hash_entry *h;
2826 +
2827 +             h = elf_sym_hashes(abfd)[r_symndx - symtab_hdr->sh_info];
2828 +
2829 +             while (h->root.type == bfd_link_hash_indirect
2830 +                    || h->root.type == bfd_link_hash_warning)
2831 +               h = (struct elf_link_hash_entry *)h->root.u.i.link;
2832 +
2833 +             BFD_ASSERT(h->root.type == bfd_link_hash_defined
2834 +                        || h->root.type == bfd_link_hash_defweak);
2835 +
2836 +             sym_frag = ((struct elf_avr32_link_hash_entry *)h)->sym_frag;
2837 +           }
2838 +
2839 +         RDBG("    addend: 0x%08lx -> 0x%08lx\n",
2840 +              rela->r_addend,
2841 +              rela->r_addend + r_data->add_frag->offset_adjust
2842 +              - (sym_frag ? sym_frag->offset_adjust : 0));
2843 +
2844 +         /* If this is against a section symbol, we won't find any
2845 +            sym_frag, so we'll just adjust the addend.  */
2846 +         rela->r_addend += r_data->add_frag->offset_adjust;
2847 +         if (sym_frag)
2848 +           rela->r_addend -= sym_frag->offset_adjust;
2849 +
2850 +         if (r_data->sub_frag)
2851 +           {
2852 +             bfd_byte *contents;
2853 +             bfd_signed_vma diff;
2854 +
2855 +             contents = retrieve_contents(abfd, sec, info->keep_memory);
2856 +             if (!contents)
2857 +               goto out;
2858 +
2859 +             /* I realize now that sub_frag is misnamed.  It's
2860 +                actually add_frag which is subtracted in this
2861 +                case...  */
2862 +             diff = bfd_get_signed_32(abfd, contents + rela->r_offset);
2863 +             diff += (r_data->sub_frag->offset_adjust
2864 +                      - r_data->add_frag->offset_adjust);
2865 +             bfd_put_32(abfd, diff, contents + rela->r_offset);
2866 +
2867 +             RDBG("   0x%lx: DIFF32 updated: 0x%lx\n", rela->r_offset, diff);
2868 +
2869 +             release_contents(sec, contents);
2870 +           }
2871 +       }
2872 +      else
2873 +       BFD_ASSERT(!r_data->sub_frag);
2874 +    }
2875 +
2876 +  ret = TRUE;
2877 +
2878 + out:
2879 +  release_internal_relocs(sec, relocs);
2880 +  return ret;
2881 +}
2882 +
2883 +static bfd_boolean
2884 +avr32_move_data(bfd *abfd, asection *sec, struct bfd_link_info *info)
2885 +{
2886 +  struct elf_avr32_link_hash_table *htab;
2887 +  struct avr32_relax_data *rd;
2888 +  struct fragment *frag, *fragend;
2889 +  Elf_Internal_Rela *relocs = NULL;
2890 +  bfd_byte *contents = NULL;
2891 +  unsigned int i;
2892 +  bfd_boolean ret = FALSE;
2893 +
2894 +  htab = avr32_elf_hash_table(info);
2895 +  rd = avr32_relax_data(sec);
2896 +
2897 +  if (!htab->symbols_adjusted)
2898 +    if (!adjust_syms(info))
2899 +      return FALSE;
2900 +
2901 +  if (rd->is_relaxable)
2902 +    {
2903 +      /* Resize the section first, so that we can be sure that enough
2904 +        memory is allocated in case the section has grown.  */
2905 +      if (sec->size > sec->rawsize
2906 +         && elf_section_data(sec)->this_hdr.contents)
2907 +       {
2908 +         /* We must not use cached data if the section has grown.  */
2909 +         free(elf_section_data(sec)->this_hdr.contents);
2910 +         elf_section_data(sec)->this_hdr.contents = NULL;
2911 +       }
2912 +
2913 +      relocs = retrieve_internal_relocs(abfd, sec, info->keep_memory);
2914 +      if (!relocs)
2915 +       goto out;
2916 +      contents = retrieve_contents(abfd, sec, info->keep_memory);
2917 +      if (!contents)
2918 +       goto out;
2919 +
2920 +      fragend = rd->frag + rd->frag_count;
2921 +
2922 +      RDBG("move_data: %s<%s>: relocs=%p, contents=%p\n",
2923 +          abfd->filename, sec->name, relocs, contents);
2924 +
2925 +      /* First, move the data into place. We must take care to move
2926 +        frags in the right order so that we don't accidentally
2927 +        overwrite parts of the next frag.  */
2928 +      for (frag = rd->frag; frag < fragend; frag++)
2929 +       {
2930 +         RDBG("    0x%08lx%c0x%x: size 0x%lx%c0x%x\n",
2931 +              frag->offset, frag->offset_adjust >= 0 ? '+' : '-',
2932 +              abs(frag->offset_adjust),
2933 +              frag->size, frag->size_adjust >= 0 ? '+' : '-',
2934 +              abs(frag->size_adjust));
2935 +         if (frag->offset_adjust > 0)
2936 +           {
2937 +             struct fragment *prev = frag - 1;
2938 +             struct fragment *last;
2939 +
2940 +             for (last = frag; last < fragend && last->offset_adjust > 0;
2941 +                  last++) ;
2942 +
2943 +             if (last == fragend)
2944 +               last--;
2945 +
2946 +             for (frag = last; frag != prev; frag--)
2947 +               {
2948 +                 if (frag->offset_adjust
2949 +                     && frag->size + frag->size_adjust > 0)
2950 +                   {
2951 +                     RDBG("memmove 0x%lx -> 0x%lx (size %lu)\n",
2952 +                          frag->offset, frag->offset + frag->offset_adjust,
2953 +                          frag->size + frag->size_adjust);
2954 +                     memmove(contents + frag->offset + frag->offset_adjust,
2955 +                             contents + frag->offset,
2956 +                             frag->size + frag->size_adjust);
2957 +                   }
2958 +               }
2959 +             frag = last;
2960 +           }
2961 +         else if (frag->offset_adjust && frag->size + frag->size_adjust > 0)
2962 +           {
2963 +             RDBG("memmove 0x%lx -> 0x%lx (size %lu)\n",
2964 +                  frag->offset, frag->offset + frag->offset_adjust,
2965 +                  frag->size + frag->size_adjust);
2966 +             memmove(contents + frag->offset + frag->offset_adjust,
2967 +                     contents + frag->offset,
2968 +                     frag->size + frag->size_adjust);
2969 +           }
2970 +       }
2971 +
2972 +      i = 0;
2973 +
2974 +      for (frag = rd->frag; frag < fragend; frag++)
2975 +       {
2976 +         const struct relax_state *state, *istate;
2977 +         struct avr32_reloc_data *r_data = NULL;
2978 +
2979 +         istate = &relax_state[frag->initial_state];
2980 +         state = &relax_state[frag->state];
2981 +
2982 +         if (rd->reloc_data)
2983 +           r_data = &rd->reloc_data[frag->rela - relocs];
2984 +
2985 +         BFD_ASSERT((long)(frag->size + frag->size_adjust) >= 0);
2986 +         BFD_ASSERT(state->reftype != REF_CPOOL
2987 +                    || r_data->add_frag->refcount > 0);
2988 +
2989 +         if (istate->reftype == REF_CPOOL && state->reftype != REF_CPOOL)
2990 +           {
2991 +             struct fragment *ifrag;
2992 +
2993 +             /* An indirect reference through the cpool has been
2994 +                converted to a direct reference.  We must update the
2995 +                reloc to point to the symbol itself instead of the
2996 +                constant pool entry.  The reloc type will be updated
2997 +                later.  */
2998 +             ifrag = r_data->add_frag;
2999 +             frag->rela->r_info = ifrag->rela->r_info;
3000 +             frag->rela->r_addend = ifrag->rela->r_addend;
3001 +
3002 +             /* Copy the reloc data so the addend will be adjusted
3003 +                correctly later.  */
3004 +             *r_data = rd->reloc_data[ifrag->rela - relocs];
3005 +           }
3006 +
3007 +         /* Move all relocs covered by this frag.  */
3008 +         if (frag->rela)
3009 +           BFD_ASSERT(&relocs[i] <= frag->rela);
3010 +         else
3011 +           BFD_ASSERT((frag + 1) == fragend && frag->state == RS_NONE);
3012 +
3013 +         if (frag == rd->frag)
3014 +           BFD_ASSERT(i == 0);
3015 +         else
3016 +           BFD_ASSERT(&relocs[i] > frag[-1].rela);
3017 +
3018 +         /* If non-null, frag->rela is the last relocation in the
3019 +            fragment.  frag->rela can only be null in the last
3020 +            fragment, so in that case, we'll just do the rest.  */
3021 +         for (; (i < sec->reloc_count
3022 +                 && (!frag->rela || &relocs[i] <= frag->rela)); i++)
3023 +           {
3024 +             RDBG("[%4u] r_offset 0x%08lx -> 0x%08lx\n", i, relocs[i].r_offset,
3025 +                  relocs[i].r_offset + frag->offset_adjust);
3026 +             relocs[i].r_offset += frag->offset_adjust;
3027 +           }
3028 +
3029 +         if (frag->refcount == 0)
3030 +           {
3031 +             /* If this frag is to be discarded, make sure we won't
3032 +                relocate it later on.  */
3033 +             BFD_ASSERT(frag->state == RS_CPENT);
3034 +             frag->rela->r_info = ELF_R_INFO(ELF_R_SYM(frag->rela->r_info),
3035 +                                           R_AVR32_NONE);
3036 +           }
3037 +         else if (frag->state == RS_ALIGN)
3038 +           {
3039 +             bfd_vma addr, addr_end;
3040 +
3041 +             addr = frag->rela->r_offset;
3042 +             addr_end = (frag->offset + frag->offset_adjust
3043 +                         + frag->size + frag->size_adjust);
3044 +
3045 +             /* If the section is executable, insert NOPs.
3046 +                Otherwise, insert zeroes.  */
3047 +             if (sec->flags & SEC_CODE)
3048 +               {
3049 +                 if (addr & 1)
3050 +                   {
3051 +                     bfd_put_8(abfd, 0, contents + addr);
3052 +                     addr++;
3053 +                   }
3054 +
3055 +                 BFD_ASSERT(!((addr_end - addr) & 1));
3056 +
3057 +                 while (addr < addr_end)
3058 +                   {
3059 +                     bfd_put_16(abfd, NOP_OPCODE, contents + addr);
3060 +                     addr += 2;
3061 +                   }
3062 +               }
3063 +             else
3064 +               memset(contents + addr, 0, addr_end - addr);
3065 +           }
3066 +         else if (state->opcode_mask)
3067 +           {
3068 +             bfd_vma insn;
3069 +
3070 +             /* Update the opcode and the relocation type unless it's a
3071 +                "special" relax state (i.e. RS_NONE, RS_ALIGN or
3072 +                RS_CPENT.), in which case the opcode mask is zero.  */
3073 +             insn = bfd_get_32(abfd, contents + frag->rela->r_offset);
3074 +             insn &= ~state->opcode_mask;
3075 +             insn |= state->opcode;
3076 +             RDBG("    0x%lx: inserting insn %08lx\n",
3077 +                  frag->rela->r_offset, insn);
3078 +             bfd_put_32(abfd, insn, contents + frag->rela->r_offset);
3079 +
3080 +             frag->rela->r_info = ELF_R_INFO(ELF_R_SYM(frag->rela->r_info),
3081 +                                             state->r_type);
3082 +           }
3083 +
3084 +         if ((frag + 1) == fragend)
3085 +           BFD_ASSERT((frag->offset + frag->size + frag->offset_adjust
3086 +                       + frag->size_adjust) == sec->size);
3087 +         else
3088 +           BFD_ASSERT((frag->offset + frag->size + frag->offset_adjust
3089 +                       + frag->size_adjust)
3090 +                      == (frag[1].offset + frag[1].offset_adjust));
3091 +       }
3092 +    }
3093 +
3094 +  /* Adjust reloc addends and DIFF32 differences */
3095 +  if (!adjust_relocs(abfd, sec, info))
3096 +    return FALSE;
3097 +
3098 +  ret = TRUE;
3099 +
3100 + out:
3101 +  release_contents(sec, contents);
3102 +  release_internal_relocs(sec, relocs);
3103 +  return ret;
3104 +}
3105 +
3106 +static bfd_boolean
3107 +avr32_elf_relax_section(bfd *abfd, asection *sec,
3108 +                       struct bfd_link_info *info, bfd_boolean *again)
3109 +{
3110 +  struct elf_avr32_link_hash_table *htab;
3111 +  struct avr32_relax_data *rd;
3112 +
3113 +  *again = FALSE;
3114 +  if (info->relocatable)
3115 +    return TRUE;
3116 +
3117 +  htab = avr32_elf_hash_table(info);
3118 +  if ((!(sec->flags & SEC_RELOC) || sec->reloc_count == 0)
3119 +      && sec != htab->sgot)
3120 +    return TRUE;
3121 +
3122 +  if (!htab->relocations_analyzed)
3123 +    {
3124 +      if (!analyze_relocations(info))
3125 +       return FALSE;
3126 +      htab->relocations_analyzed = TRUE;
3127 +    }
3128 +
3129 +  rd = avr32_relax_data(sec);
3130 +
3131 +  if (rd->iteration != htab->relax_iteration)
3132 +    {
3133 +      if (!htab->repeat_pass)
3134 +       htab->relax_pass++;
3135 +      htab->relax_iteration++;
3136 +      htab->repeat_pass = FALSE;
3137 +    }
3138 +
3139 +  rd->iteration++;
3140 +
3141 +  switch (htab->relax_pass)
3142 +    {
3143 +    case RELAX_PASS_SIZE_FRAGS:
3144 +      if (!avr32_size_frags(abfd, sec, info))
3145 +       return FALSE;
3146 +      *again = TRUE;
3147 +      break;
3148 +    case RELAX_PASS_MOVE_DATA:
3149 +      if (!avr32_move_data(abfd, sec, info))
3150 +       return FALSE;
3151 +      break;
3152 +  }
3153 +
3154 +  return TRUE;
3155 +}
3156 +
3157 +
3158 +/* Relocation */
3159 +
3160 +static bfd_reloc_status_type
3161 +avr32_check_reloc_value(asection *sec, Elf_Internal_Rela *rela,
3162 +                       bfd_signed_vma relocation, reloc_howto_type *howto);
3163 +static bfd_reloc_status_type
3164 +avr32_final_link_relocate(reloc_howto_type *howto, bfd *input_bfd,
3165 +                         asection *input_section, bfd_byte *contents,
3166 +                         Elf_Internal_Rela *rel, bfd_vma value);
3167 +static bfd_boolean
3168 +avr32_elf_relocate_section(bfd *output_bfd, struct bfd_link_info *info,
3169 +                          bfd *input_bfd, asection *input_section,
3170 +                          bfd_byte *contents, Elf_Internal_Rela *relocs,
3171 +                          Elf_Internal_Sym *local_syms,
3172 +                          asection **local_sections);
3173 +
3174 +
3175 +#define symbol_address(symbol) \
3176 +  symbol->value + symbol->section->output_section->vma \
3177 +  + symbol->section->output_offset
3178 +
3179 +#define avr32_elf_insert_field(size, field, abfd, reloc_entry, data)   \
3180 +  do                                                                   \
3181 +    {                                                                  \
3182 +      unsigned long x;                                                 \
3183 +      x = bfd_get_##size (abfd, data + reloc_entry->address);          \
3184 +      x &= ~reloc_entry->howto->dst_mask;                              \
3185 +      x |= field & reloc_entry->howto->dst_mask;                       \
3186 +      bfd_put_##size (abfd, (bfd_vma) x, data + reloc_entry->address); \
3187 +    }                                                                  \
3188 +  while(0)
3189 +
3190 +static bfd_reloc_status_type
3191 +avr32_check_reloc_value(asection *sec ATTRIBUTE_UNUSED,
3192 +                       Elf_Internal_Rela *rela ATTRIBUTE_UNUSED,
3193 +                       bfd_signed_vma relocation,
3194 +                       reloc_howto_type *howto)
3195 +{
3196 +  bfd_vma reloc_u;
3197 +
3198 +  /* We take "complain_overflow_dont" to mean "don't complain on
3199 +     alignment either". This way, we don't have to special-case
3200 +     R_AVR32_HI16 */
3201 +  if (howto->complain_on_overflow == complain_overflow_dont)
3202 +    return bfd_reloc_ok;
3203 +
3204 +  /* Check if the value is correctly aligned */
3205 +  if (relocation & ((1 << howto->rightshift) - 1))
3206 +    {
3207 +      RDBG("misaligned: %s<%s+%lx>: %s: 0x%lx (align %u)\n",
3208 +          sec->owner->filename, sec->name, rela->r_offset,
3209 +          howto->name, relocation, howto->rightshift);
3210 +      return bfd_reloc_overflow;
3211 +    }
3212 +
3213 +  /* Now, get rid of the unnecessary bits */
3214 +  relocation >>= howto->rightshift;
3215 +  reloc_u = (bfd_vma)relocation;
3216 +
3217 +  switch (howto->complain_on_overflow)
3218 +    {
3219 +    case complain_overflow_unsigned:
3220 +    case complain_overflow_bitfield:
3221 +      if (reloc_u > (unsigned long)((1 << howto->bitsize) - 1))
3222 +       {
3223 +         RDBG("unsigned overflow: %s<%s+%lx>: %s: 0x%lx (size %u)\n",
3224 +              sec->owner->filename, sec->name, rela->r_offset,
3225 +              howto->name, reloc_u, howto->bitsize);
3226 +         RDBG("reloc vma: 0x%lx\n",
3227 +              sec->output_section->vma + sec->output_offset + rela->r_offset);
3228 +
3229 +         return bfd_reloc_overflow;
3230 +       }
3231 +      break;
3232 +    case complain_overflow_signed:
3233 +      if (relocation > (1 << (howto->bitsize - 1)) - 1)
3234 +       {
3235 +         RDBG("signed overflow: %s<%s+%lx>: %s: 0x%lx (size %u)\n",
3236 +              sec->owner->filename, sec->name, rela->r_offset,
3237 +              howto->name, reloc_u, howto->bitsize);
3238 +         RDBG("reloc vma: 0x%lx\n",
3239 +              sec->output_section->vma + sec->output_offset + rela->r_offset);
3240 +
3241 +         return bfd_reloc_overflow;
3242 +       }
3243 +      if (relocation < -(1 << (howto->bitsize - 1)))
3244 +       {
3245 +         RDBG("signed overflow: %s<%s+%lx>: %s: -0x%lx (size %u)\n",
3246 +              sec->owner->filename, sec->name, rela->r_offset,
3247 +              howto->name, -relocation, howto->bitsize);
3248 +         RDBG("reloc vma: 0x%lx\n",
3249 +              sec->output_section->vma + sec->output_offset + rela->r_offset);
3250 +
3251 +         return bfd_reloc_overflow;
3252 +       }
3253 +      break;
3254 +    default:
3255 +      abort();
3256 +    }
3257 +
3258 +  return bfd_reloc_ok;
3259 +}
3260 +
3261 +
3262 +static bfd_reloc_status_type
3263 +avr32_final_link_relocate(reloc_howto_type *howto,
3264 +                         bfd *input_bfd,
3265 +                         asection *input_section,
3266 +                         bfd_byte *contents,
3267 +                         Elf_Internal_Rela *rel,
3268 +                         bfd_vma value)
3269 +{
3270 +  bfd_vma field;
3271 +  bfd_vma relocation;
3272 +  bfd_reloc_status_type status;
3273 +  bfd_byte *p = contents + rel->r_offset;
3274 +  unsigned long x;
3275 +
3276 +  pr_debug("  (6b) final link relocate\n");
3277 +
3278 +  /* Sanity check the address */
3279 +  if (rel->r_offset > input_section->size)
3280 +    {
3281 +      (*_bfd_error_handler)
3282 +       ("%B: %A+0x%lx: offset out of range (section size: 0x%lx)",
3283 +        input_bfd, input_section, rel->r_offset, input_section->size);
3284 +      return bfd_reloc_outofrange;
3285 +    }
3286 +
3287 +  relocation = value + rel->r_addend;
3288 +
3289 +  if (howto->pc_relative)
3290 +    {
3291 +      bfd_vma addr;
3292 +
3293 +      addr = input_section->output_section->vma
3294 +       + input_section->output_offset + rel->r_offset;
3295 +      addr &= ~0UL << howto->rightshift;
3296 +      relocation -= addr;
3297 +    }
3298 +
3299 +  switch (ELF32_R_TYPE(rel->r_info))
3300 +    {
3301 +    case R_AVR32_16N_PCREL:
3302 +      /* sub reg, pc, . - (sym + addend) */
3303 +      relocation = -relocation;
3304 +      break;
3305 +    }
3306 +
3307 +  status = avr32_check_reloc_value(input_section, rel, relocation, howto);
3308 +
3309 +  relocation >>= howto->rightshift;
3310 +  if (howto->bitsize == 21)
3311 +    field = (relocation & 0xffff)
3312 +      | ((relocation & 0x10000) << 4)
3313 +      | ((relocation & 0x1e0000) << 8);
3314 +  else if (howto->bitsize == 12)
3315 +    field = (relocation & 0xff) | ((relocation & 0xf00) << 4);
3316 +  else if (howto->bitsize == 10)
3317 +    field = ((relocation & 0xff) << 4)
3318 +      | ((relocation & 0x300) >> 8);
3319 +  else
3320 +    field = relocation << howto->bitpos;
3321 +
3322 +  switch (howto->size)
3323 +    {
3324 +    case 0:
3325 +      x = bfd_get_8 (input_bfd, p);
3326 +      x &= ~howto->dst_mask;
3327 +      x |= field & howto->dst_mask;
3328 +      bfd_put_8 (input_bfd, (bfd_vma) x, p);
3329 +      break;
3330 +    case 1:
3331 +      x = bfd_get_16 (input_bfd, p);
3332 +      x &= ~howto->dst_mask;
3333 +      x |= field & howto->dst_mask;
3334 +      bfd_put_16 (input_bfd, (bfd_vma) x, p);
3335 +      break;
3336 +    case 2:
3337 +      x = bfd_get_32 (input_bfd, p);
3338 +      x &= ~howto->dst_mask;
3339 +      x |= field & howto->dst_mask;
3340 +      bfd_put_32 (input_bfd, (bfd_vma) x, p);
3341 +      break;
3342 +    default:
3343 +      abort();
3344 +    }
3345 +
3346 +  return status;
3347 +}
3348 +
3349 +/* (6) Apply relocations to the normal (non-dynamic) sections */
3350 +
3351 +static bfd_boolean
3352 +avr32_elf_relocate_section(bfd *output_bfd, struct bfd_link_info *info,
3353 +                          bfd *input_bfd, asection *input_section,
3354 +                          bfd_byte *contents, Elf_Internal_Rela *relocs,
3355 +                          Elf_Internal_Sym *local_syms,
3356 +                          asection **local_sections)
3357 +{
3358 +  struct elf_avr32_link_hash_table *htab;
3359 +  Elf_Internal_Shdr *symtab_hdr;
3360 +  Elf_Internal_Rela *rel, *relend;
3361 +  struct elf_link_hash_entry **sym_hashes;
3362 +  struct got_entry **local_got_ents;
3363 +  asection *sgot;
3364 +  asection *srelgot;
3365 +
3366 +  pr_debug("(6) relocate section %s:<%s> (size 0x%lx)\n",
3367 +          input_bfd->filename, input_section->name, input_section->size);
3368 +
3369 +  /* If we're doing a partial link, we don't have to do anything since
3370 +     we're using RELA relocations */
3371 +  if (info->relocatable)
3372 +    return TRUE;
3373 +
3374 +  htab = avr32_elf_hash_table(info);
3375 +  symtab_hdr = &elf_tdata(input_bfd)->symtab_hdr;
3376 +  sym_hashes = elf_sym_hashes(input_bfd);
3377 +  local_got_ents = elf_local_got_ents(input_bfd);
3378 +  sgot = htab->sgot;
3379 +  srelgot = htab->srelgot;
3380 +
3381 +  relend = relocs + input_section->reloc_count;
3382 +  for (rel = relocs; rel < relend; rel++)
3383 +    {
3384 +      unsigned long r_type, r_symndx;
3385 +      reloc_howto_type *howto;
3386 +      Elf_Internal_Sym *sym = NULL;
3387 +      struct elf_link_hash_entry *h = NULL;
3388 +      asection *sec = NULL;
3389 +      bfd_vma value;
3390 +      bfd_vma offset;
3391 +      bfd_reloc_status_type status;
3392 +
3393 +      r_type = ELF32_R_TYPE(rel->r_info);
3394 +      r_symndx = ELF32_R_SYM(rel->r_info);
3395 +
3396 +      if (r_type == R_AVR32_NONE
3397 +         || r_type == R_AVR32_ALIGN
3398 +         || r_type == R_AVR32_DIFF32
3399 +         || r_type == R_AVR32_DIFF16
3400 +         || r_type == R_AVR32_DIFF8)
3401 +       continue;
3402 +
3403 +      /* Sanity check */
3404 +      if (r_type > R_AVR32_max)
3405 +       {
3406 +         bfd_set_error(bfd_error_bad_value);
3407 +         return FALSE;
3408 +       }
3409 +
3410 +      howto = &elf_avr32_howto_table[r_type];
3411 +
3412 +      if (r_symndx < symtab_hdr->sh_info)
3413 +       {
3414 +         sym = local_syms + r_symndx;
3415 +         sec = local_sections[r_symndx];
3416 +
3417 +         pr_debug("  (6a) processing %s against local symbol %lu\n",
3418 +                  howto->name, r_symndx);
3419 +
3420 +         /* The following function changes rel->r_addend behind our back. */
3421 +         value = _bfd_elf_rela_local_sym(output_bfd, sym, &sec, rel);
3422 +         pr_debug("    => value: %lx, addend: %lx\n", value, rel->r_addend);
3423 +       }
3424 +      else
3425 +       {
3426 +         if (sym_hashes == NULL)
3427 +           return FALSE;
3428 +
3429 +         h = sym_hashes[r_symndx - symtab_hdr->sh_info];
3430 +         while (h->root.type == bfd_link_hash_indirect
3431 +                || h->root.type == bfd_link_hash_warning)
3432 +           h = (struct elf_link_hash_entry *)h->root.u.i.link;
3433 +
3434 +         pr_debug("  (6a) processing %s against symbol %s\n",
3435 +                  howto->name, h->root.root.string);
3436 +
3437 +         if (h->root.type == bfd_link_hash_defined
3438 +             || h->root.type == bfd_link_hash_defweak)
3439 +           {
3440 +             bfd_boolean dyn;
3441 +
3442 +             dyn = htab->root.dynamic_sections_created;
3443 +             sec = h->root.u.def.section;
3444 +
3445 +             if (sec->output_section)
3446 +               value = (h->root.u.def.value
3447 +                        + sec->output_section->vma
3448 +                        + sec->output_offset);
3449 +             else
3450 +               value = h->root.u.def.value;
3451 +           }
3452 +         else if (h->root.type == bfd_link_hash_undefweak)
3453 +           value = 0;
3454 +         else if (info->unresolved_syms_in_objects == RM_IGNORE
3455 +                  && ELF_ST_VISIBILITY(h->other) == STV_DEFAULT)
3456 +           value = 0;
3457 +         else
3458 +           {
3459 +             bfd_boolean err;
3460 +             err = (info->unresolved_syms_in_objects == RM_GENERATE_ERROR
3461 +                    || ELF_ST_VISIBILITY(h->other) != STV_DEFAULT);
3462 +             if (!info->callbacks->undefined_symbol
3463 +                 (info, h->root.root.string, input_bfd,
3464 +                  input_section, rel->r_offset, err))
3465 +               return FALSE;
3466 +             value = 0;
3467 +           }
3468 +
3469 +         pr_debug("    => value: %lx, addend: %lx\n", value, rel->r_addend);
3470 +       }
3471 +
3472 +      switch (r_type)
3473 +       {
3474 +       case R_AVR32_GOT32:
3475 +       case R_AVR32_GOT16:
3476 +       case R_AVR32_GOT8:
3477 +       case R_AVR32_GOT21S:
3478 +       case R_AVR32_GOT18SW:
3479 +       case R_AVR32_GOT16S:
3480 +       case R_AVR32_GOT7UW:
3481 +       case R_AVR32_LDA_GOT:
3482 +       case R_AVR32_GOTCALL:
3483 +         BFD_ASSERT(sgot != NULL);
3484 +
3485 +         if (h != NULL)
3486 +           {
3487 +             BFD_ASSERT(h->got.glist->refcount > 0);
3488 +             offset = h->got.glist->offset;
3489 +
3490 +             BFD_ASSERT(offset < sgot->size);
3491 +             if (!elf_hash_table(info)->dynamic_sections_created
3492 +                 || (h->def_regular
3493 +                     && (!info->shared
3494 +                         || info->symbolic
3495 +                         || h->dynindx == -1)))
3496 +               {
3497 +                 /* This is actually a static link, or it is a
3498 +                    -Bsymbolic link and the symbol is defined
3499 +                    locally, or the symbol was forced to be local.  */
3500 +                 bfd_put_32(output_bfd, value, sgot->contents + offset);
3501 +               }
3502 +           }
3503 +         else
3504 +           {
3505 +             BFD_ASSERT(local_got_ents &&
3506 +                        local_got_ents[r_symndx]->refcount > 0);
3507 +             offset = local_got_ents[r_symndx]->offset;
3508 +
3509 +             /* Local GOT entries don't have relocs.  If this is a
3510 +                shared library, the dynamic linker will add the load
3511 +                address to the initial value at startup.  */
3512 +             BFD_ASSERT(offset < sgot->size);
3513 +             pr_debug("Initializing GOT entry at offset %lu: 0x%lx\n",
3514 +                      offset, value);
3515 +             bfd_put_32 (output_bfd, value, sgot->contents + offset);
3516 +           }
3517 +
3518 +         value = sgot->output_offset + offset;
3519 +         pr_debug("GOT reference: New value %lx\n", value);
3520 +         break;
3521 +
3522 +       case R_AVR32_GOTPC:
3523 +         /* This relocation type is for constant pool entries used in
3524 +            the calculation "Rd = PC - (PC - GOT)", where the
3525 +            constant pool supplies the constant (PC - GOT)
3526 +            offset. The symbol value + addend indicates where the
3527 +            value of PC is taken. */
3528 +         value -= sgot->output_section->vma;
3529 +         break;
3530 +
3531 +       case R_AVR32_32_PCREL:
3532 +         /* We must adjust r_offset to account for discarded data in
3533 +            the .eh_frame section.  This is probably not the right
3534 +            way to do this, since AFAICS all other architectures do
3535 +            it some other way.  I just can't figure out how...  */
3536 +         {
3537 +           bfd_vma r_offset;
3538 +
3539 +           r_offset = _bfd_elf_section_offset(output_bfd, info,
3540 +                                              input_section,
3541 +                                              rel->r_offset);
3542 +           if (r_offset == (bfd_vma)-1
3543 +               || r_offset == (bfd_vma)-2)
3544 +             continue;
3545 +           rel->r_offset = r_offset;
3546 +         }
3547 +         break;
3548 +
3549 +       case R_AVR32_32:
3550 +         /* We need to emit a run-time relocation in the following cases:
3551 +              - we're creating a shared library
3552 +              - the symbol is not defined in any regular objects
3553 +
3554 +            Of course, sections that aren't going to be part of the
3555 +            run-time image will not get any relocs, and undefined
3556 +            symbols won't have any either (only weak undefined
3557 +            symbols should get this far).  */
3558 +         if ((info->shared
3559 +              || (elf_hash_table(info)->dynamic_sections_created
3560 +                  && h != NULL
3561 +                  && h->def_dynamic
3562 +                  && !h->def_regular))
3563 +             && r_symndx != 0
3564 +             && (input_section->flags & SEC_ALLOC))
3565 +           {
3566 +             Elf_Internal_Rela outrel;
3567 +             bfd_byte *loc;
3568 +             bfd_boolean skip, relocate;
3569 +             struct elf_avr32_link_hash_entry *avrh;
3570 +
3571 +             pr_debug("Going to generate dynamic reloc...\n");
3572 +
3573 +             skip = FALSE;
3574 +             relocate = FALSE;
3575 +
3576 +             outrel.r_offset = _bfd_elf_section_offset(output_bfd, info,
3577 +                                                       input_section,
3578 +                                                       rel->r_offset);
3579 +             if (outrel.r_offset == (bfd_vma)-1)
3580 +               skip = TRUE;
3581 +             else if (outrel.r_offset == (bfd_vma)-2)
3582 +               skip = TRUE, relocate = TRUE;
3583 +
3584 +             outrel.r_offset += (input_section->output_section->vma
3585 +                                 + input_section->output_offset);
3586 +
3587 +             pr_debug("    ... offset %lx, dynindx %ld\n",
3588 +                      outrel.r_offset, h ? h->dynindx : -1);
3589 +
3590 +             if (skip)
3591 +               memset(&outrel, 0, sizeof(outrel));
3592 +             else
3593 +               {
3594 +                 avrh = (struct elf_avr32_link_hash_entry *)h;
3595 +                 /* h->dynindx may be -1 if this symbol was marked to
3596 +                    become local.  */
3597 +                 if (h == NULL
3598 +                     || ((info->symbolic || h->dynindx == -1)
3599 +                         && h->def_regular))
3600 +                   {
3601 +                     relocate = TRUE;
3602 +                     outrel.r_info = ELF32_R_INFO(0, R_AVR32_RELATIVE);
3603 +                     outrel.r_addend = value + rel->r_addend;
3604 +                     pr_debug("    ... R_AVR32_RELATIVE\n");
3605 +                   }
3606 +                 else
3607 +                   {
3608 +                     BFD_ASSERT(h->dynindx != -1);
3609 +                     relocate = TRUE;
3610 +                     outrel.r_info = ELF32_R_INFO(h->dynindx, R_AVR32_GLOB_DAT);
3611 +                     outrel.r_addend = rel->r_addend;
3612 +                     pr_debug("    ... R_AVR32_GLOB_DAT\n");
3613 +                   }
3614 +               }
3615 +
3616 +             pr_debug("srelgot reloc_count: %d, size %lu\n",
3617 +                      srelgot->reloc_count, srelgot->size);
3618 +
3619 +             loc = srelgot->contents;
3620 +             loc += srelgot->reloc_count++ * sizeof(Elf32_External_Rela);
3621 +             bfd_elf32_swap_reloca_out(output_bfd, &outrel, loc);
3622 +
3623 +             BFD_ASSERT(srelgot->reloc_count * sizeof(Elf32_External_Rela)
3624 +                        <= srelgot->size);
3625 +
3626 +             if (!relocate)
3627 +               continue;
3628 +           }
3629 +         break;
3630 +       }
3631 +
3632 +      status = avr32_final_link_relocate(howto, input_bfd, input_section,
3633 +                                        contents, rel, value);
3634 +
3635 +      switch (status)
3636 +       {
3637 +       case bfd_reloc_ok:
3638 +         break;
3639 +
3640 +       case bfd_reloc_overflow:
3641 +         {
3642 +           const char *name;
3643 +
3644 +           if (h != NULL)
3645 +             name = h->root.root.string;
3646 +           else
3647 +             {
3648 +               name = bfd_elf_string_from_elf_section(input_bfd,
3649 +                                                      symtab_hdr->sh_link,
3650 +                                                      sym->st_name);
3651 +               if (name == NULL)
3652 +                 return FALSE;
3653 +               if (*name == '\0')
3654 +                 name = bfd_section_name(input_bfd, sec);
3655 +             }
3656 +           if (!((*info->callbacks->reloc_overflow)
3657 +                 (info, (h ? &h->root : NULL), name, howto->name,
3658 +                  rel->r_addend, input_bfd, input_section, rel->r_offset)))
3659 +             return FALSE;
3660 +         }
3661 +         break;
3662 +
3663 +       case bfd_reloc_outofrange:
3664 +       default:
3665 +         abort();
3666 +       }
3667 +    }
3668 +
3669 +  return TRUE;
3670 +}
3671 +
3672 +
3673 +/* Additional processing of dynamic sections after relocation */
3674 +
3675 +static bfd_boolean
3676 +avr32_elf_finish_dynamic_symbol(bfd *output_bfd, struct bfd_link_info *info,
3677 +                               struct elf_link_hash_entry *h,
3678 +                               Elf_Internal_Sym *sym);
3679 +static bfd_boolean
3680 +avr32_elf_finish_dynamic_sections(bfd *output_bfd, struct bfd_link_info *info);
3681 +
3682 +
3683 +/* (7) Initialize the contents of a dynamic symbol and/or emit
3684 +   relocations for it */
3685 +
3686 +static bfd_boolean
3687 +avr32_elf_finish_dynamic_symbol(bfd *output_bfd, struct bfd_link_info *info,
3688 +                               struct elf_link_hash_entry *h,
3689 +                               Elf_Internal_Sym *sym)
3690 +{
3691 +  struct elf_avr32_link_hash_table *htab;
3692 +  struct got_entry *got;
3693 +
3694 +  pr_debug("(7) finish dynamic symbol: %s\n", h->root.root.string);
3695 +
3696 +  htab = avr32_elf_hash_table(info);
3697 +  got = h->got.glist;
3698 +
3699 +  if (got && got->refcount > 0)
3700 +    {
3701 +      asection *sgot;
3702 +      asection *srelgot;
3703 +      Elf_Internal_Rela rel;
3704 +      bfd_byte *loc;
3705 +
3706 +      /* This symbol has an entry in the GOT. Set it up. */
3707 +      sgot = htab->sgot;
3708 +      srelgot = htab->srelgot;
3709 +      BFD_ASSERT(sgot && srelgot);
3710 +
3711 +      rel.r_offset = (sgot->output_section->vma
3712 +                     + sgot->output_offset
3713 +                     + got->offset);
3714 +
3715 +      /* If this is a static link, or it is a -Bsymbolic link and the
3716 +        symbol is defined locally or was forced to be local because
3717 +        of a version file, we just want to emit a RELATIVE reloc. The
3718 +        entry in the global offset table will already have been
3719 +        initialized in the relocate_section function. */
3720 +      if ((info->shared
3721 +          && !info->symbolic
3722 +          && h->dynindx != -1)
3723 +         || (htab->root.dynamic_sections_created
3724 +             && h->def_dynamic
3725 +             && !h->def_regular))
3726 +       {
3727 +         bfd_put_32(output_bfd, 0, sgot->contents + got->offset);
3728 +         rel.r_info = ELF32_R_INFO(h->dynindx, R_AVR32_GLOB_DAT);
3729 +         rel.r_addend = 0;
3730 +
3731 +         pr_debug("GOT reloc R_AVR32_GLOB_DAT, dynindx: %ld\n", h->dynindx);
3732 +         pr_debug("    srelgot reloc_count: %d, size: %lu\n",
3733 +                  srelgot->reloc_count, srelgot->size);
3734 +
3735 +         loc = (srelgot->contents
3736 +                + srelgot->reloc_count++ * sizeof(Elf32_External_Rela));
3737 +         bfd_elf32_swap_reloca_out(output_bfd, &rel, loc);
3738 +
3739 +         BFD_ASSERT(srelgot->reloc_count * sizeof(Elf32_External_Rela)
3740 +                    <= srelgot->size);
3741 +       }
3742 +    }
3743 +
3744 +  /* Mark _DYNAMIC and _GLOBAL_OFFSET_TABLE_ as absolute */
3745 +  if (strcmp(h->root.root.string, "_DYNAMIC") == 0
3746 +      || strcmp(h->root.root.string, "_GLOBAL_OFFSET_TABLE_") == 0)
3747 +    sym->st_shndx = SHN_ABS;
3748 +
3749 +  return TRUE;
3750 +}
3751 +
3752 +/* (8) Do any remaining initialization of the dynamic sections */
3753 +
3754 +static bfd_boolean
3755 +avr32_elf_finish_dynamic_sections(bfd *output_bfd, struct bfd_link_info *info)
3756 +{
3757 +  struct elf_avr32_link_hash_table *htab;
3758 +  asection *sgot, *sdyn;
3759 +
3760 +  pr_debug("(8) finish dynamic sections\n");
3761 +
3762 +  htab = avr32_elf_hash_table(info);
3763 +  sgot = htab->sgot;
3764 +  sdyn = bfd_get_section_by_name(htab->root.dynobj, ".dynamic");
3765 +
3766 +  if (htab->root.dynamic_sections_created)
3767 +    {
3768 +      Elf32_External_Dyn *dyncon, *dynconend;
3769 +
3770 +      BFD_ASSERT(sdyn && sgot && sgot->size >= AVR32_GOT_HEADER_SIZE);
3771 +
3772 +      dyncon = (Elf32_External_Dyn *)sdyn->contents;
3773 +      dynconend = (Elf32_External_Dyn *)(sdyn->contents + sdyn->size);
3774 +      for (; dyncon < dynconend; dyncon++)
3775 +       {
3776 +         Elf_Internal_Dyn dyn;
3777 +         asection *s;
3778 +
3779 +         bfd_elf32_swap_dyn_in(htab->root.dynobj, dyncon, &dyn);
3780 +
3781 +         switch (dyn.d_tag)
3782 +           {
3783 +           default:
3784 +             break;
3785 +
3786 +           case DT_PLTGOT:
3787 +             s = sgot->output_section;
3788 +             BFD_ASSERT(s != NULL);
3789 +             dyn.d_un.d_ptr = s->vma;
3790 +             bfd_elf32_swap_dyn_out(output_bfd, &dyn, dyncon);
3791 +             break;
3792 +
3793 +           case DT_AVR32_GOTSZ:
3794 +             s = sgot->output_section;
3795 +             BFD_ASSERT(s != NULL);
3796 +             dyn.d_un.d_val = s->size;
3797 +             bfd_elf32_swap_dyn_out(output_bfd, &dyn, dyncon);
3798 +             break;
3799 +           }
3800 +       }
3801 +
3802 +      /* Fill in the first two entries in the global offset table */
3803 +      bfd_put_32(output_bfd,
3804 +                sdyn->output_section->vma + sdyn->output_offset,
3805 +                sgot->contents);
3806 +
3807 +      /* The runtime linker will fill this one in with the address of
3808 +        the run-time link map */
3809 +      bfd_put_32(output_bfd, 0, sgot->contents + 4);
3810 +    }
3811 +
3812 +  if (sgot)
3813 +    elf_section_data(sgot->output_section)->this_hdr.sh_entsize = 4;
3814 +
3815 +  return TRUE;
3816 +}
3817 +
3818 +
3819 +/* AVR32-specific private ELF data */
3820 +
3821 +static bfd_boolean
3822 +avr32_elf_set_private_flags(bfd *abfd, flagword flags);
3823 +static bfd_boolean
3824 +avr32_elf_copy_private_bfd_data(bfd *ibfd, bfd *obfd);
3825 +static bfd_boolean
3826 +avr32_elf_merge_private_bfd_data(bfd *ibfd, bfd *obfd);
3827 +static bfd_boolean
3828 +avr32_elf_print_private_bfd_data(bfd *abfd, void *ptr);
3829 +
3830 +static bfd_boolean
3831 +avr32_elf_set_private_flags(bfd *abfd, flagword flags)
3832 +{
3833 +  elf_elfheader(abfd)->e_flags = flags;
3834 +  elf_flags_init(abfd) = TRUE;
3835 +
3836 +  return TRUE;
3837 +}
3838 +
3839 +/* Copy backend specific data from one object module to another.  */
3840 +
3841 +static bfd_boolean
3842 +avr32_elf_copy_private_bfd_data(bfd *ibfd, bfd *obfd)
3843 +{
3844 +  elf_elfheader(obfd)->e_flags = elf_elfheader(ibfd)->e_flags;
3845 +  return TRUE;
3846 +}
3847 +
3848 +/* Merge backend specific data from an object file to the output
3849 +   object file when linking.  */
3850 +
3851 +static bfd_boolean
3852 +avr32_elf_merge_private_bfd_data(bfd *ibfd, bfd *obfd)
3853 +{
3854 +  flagword out_flags, in_flags;
3855 +
3856 +  pr_debug("(0) merge_private_bfd_data: %s -> %s\n",
3857 +          ibfd->filename, obfd->filename);
3858 +
3859 +  in_flags = elf_elfheader(ibfd)->e_flags;
3860 +  out_flags = elf_elfheader(obfd)->e_flags;
3861 +
3862 +  if (elf_flags_init(obfd))
3863 +    {
3864 +      /* If one of the inputs are non-PIC, the output must be
3865 +        considered non-PIC.  The same applies to linkrelax.  */
3866 +      if (!(in_flags & EF_AVR32_PIC))
3867 +       out_flags &= ~EF_AVR32_PIC;
3868 +      if (!(in_flags & EF_AVR32_LINKRELAX))
3869 +       out_flags &= ~EF_AVR32_LINKRELAX;
3870 +    }
3871 +  else
3872 +    {
3873 +      elf_flags_init(obfd) = TRUE;
3874 +      out_flags = in_flags;
3875 +    }
3876 +
3877 +  elf_elfheader(obfd)->e_flags = out_flags;
3878 +
3879 +  return TRUE;
3880 +}
3881 +
3882 +static bfd_boolean
3883 +avr32_elf_print_private_bfd_data(bfd *abfd, void *ptr)
3884 +{
3885 +  FILE *file = (FILE *)ptr;
3886 +  unsigned long flags;
3887 +
3888 +  BFD_ASSERT(abfd != NULL && ptr != NULL);
3889 +
3890 +  _bfd_elf_print_private_bfd_data(abfd, ptr);
3891 +
3892 +  flags = elf_elfheader(abfd)->e_flags;
3893 +
3894 +  fprintf(file, _("private flags = %lx:"), elf_elfheader(abfd)->e_flags);
3895 +
3896 +  if (flags & EF_AVR32_PIC)
3897 +    fprintf(file, " [PIC]");
3898 +  if (flags & EF_AVR32_LINKRELAX)
3899 +    fprintf(file, " [linker relaxable]");
3900 +
3901 +  flags &= ~(EF_AVR32_PIC | EF_AVR32_LINKRELAX);
3902 +
3903 +  if (flags)
3904 +    fprintf(file, _("<Unrecognized flag bits set>"));
3905 +
3906 +  fputc('\n', file);
3907 +
3908 +  return TRUE;
3909 +}
3910 +
3911 +/* Set avr32-specific linker options.  */
3912 +void bfd_elf32_avr32_set_options(struct bfd_link_info *info,
3913 +                                int direct_data_refs)
3914 +{
3915 +  struct elf_avr32_link_hash_table *htab;
3916 +
3917 +  htab = avr32_elf_hash_table (info);
3918 +  htab->direct_data_refs = !!direct_data_refs;
3919 +}
3920 +
3921 +
3922 +
3923 +/* Understanding core dumps */
3924 +
3925 +static bfd_boolean
3926 +avr32_elf_grok_prstatus(bfd *abfd, Elf_Internal_Note *note);
3927 +static bfd_boolean
3928 +avr32_elf_grok_psinfo(bfd *abfd, Elf_Internal_Note *note);
3929 +
3930 +static bfd_boolean
3931 +avr32_elf_grok_prstatus(bfd *abfd, Elf_Internal_Note *note)
3932 +{
3933 +  /* Linux/AVR32B elf_prstatus */
3934 +  if (note->descsz != 148)
3935 +    return FALSE;
3936 +
3937 +  /* pr_cursig */
3938 +  elf_tdata(abfd)->core_signal = bfd_get_16(abfd, note->descdata + 12);
3939 +
3940 +  /* pr_pid */
3941 +  elf_tdata(abfd)->core_pid = bfd_get_32(abfd, note->descdata + 24);
3942 +
3943 +  /* Make a ".reg/999" section for pr_reg. The size is for 16
3944 +     general-purpose registers, SR and r12_orig (18 * 4 = 72).  */
3945 +  return _bfd_elfcore_make_pseudosection(abfd, ".reg", 72,
3946 +                                        note->descpos + 72);
3947 +}
3948 +
3949 +static bfd_boolean
3950 +avr32_elf_grok_psinfo(bfd *abfd, Elf_Internal_Note *note)
3951 +{
3952 +  /* Linux/AVR32B elf_prpsinfo */
3953 +  if (note->descsz != 128)
3954 +    return FALSE;
3955 +
3956 +  elf_tdata(abfd)->core_program
3957 +    = _bfd_elfcore_strndup(abfd, note->descdata + 32, 16);
3958 +  elf_tdata(abfd)->core_command
3959 +    = _bfd_elfcore_strndup(abfd, note->descdata + 48, 80);
3960 +
3961 +  /* Note that for some reason, a spurious space is tacked
3962 +     onto the end of the args in some (at least one anyway)
3963 +     implementations, so strip it off if it exists.  */
3964 +
3965 +  {
3966 +    char *command = elf_tdata (abfd)->core_command;
3967 +    int n = strlen (command);
3968 +
3969 +    if (0 < n && command[n - 1] == ' ')
3970 +      command[n - 1] = '\0';
3971 +  }
3972 +
3973 +  return TRUE;
3974 +}
3975 +
3976 +
3977 +#define ELF_ARCH                       bfd_arch_avr32
3978 +#define ELF_MACHINE_CODE               EM_AVR32
3979 +#define ELF_MAXPAGESIZE                        1024
3980 +
3981 +#define TARGET_BIG_SYM                 bfd_elf32_avr32_vec
3982 +#define TARGET_BIG_NAME                        "elf32-avr32"
3983 +
3984 +#define elf_backend_grok_prstatus      avr32_elf_grok_prstatus
3985 +#define elf_backend_grok_psinfo                avr32_elf_grok_psinfo
3986 +
3987 +/* Only RELA relocations are used */
3988 +#define elf_backend_may_use_rel_p      0
3989 +#define elf_backend_may_use_rela_p     1
3990 +#define elf_backend_default_use_rela_p 1
3991 +#define elf_backend_rela_normal                1
3992 +#define elf_info_to_howto_rel          NULL
3993 +#define elf_info_to_howto              avr32_info_to_howto
3994 +
3995 +#define bfd_elf32_bfd_copy_private_bfd_data    avr32_elf_copy_private_bfd_data
3996 +#define bfd_elf32_bfd_merge_private_bfd_data   avr32_elf_merge_private_bfd_data
3997 +#define bfd_elf32_bfd_set_private_flags                avr32_elf_set_private_flags
3998 +#define bfd_elf32_bfd_print_private_bfd_data   avr32_elf_print_private_bfd_data
3999 +#define bfd_elf32_new_section_hook             avr32_elf_new_section_hook
4000 +
4001 +#define elf_backend_gc_mark_hook               avr32_elf_gc_mark_hook
4002 +#define elf_backend_gc_sweep_hook              avr32_elf_gc_sweep_hook
4003 +#define elf_backend_relocate_section   avr32_elf_relocate_section
4004 +#define elf_backend_copy_indirect_symbol avr32_elf_copy_indirect_symbol
4005 +#define elf_backend_create_dynamic_sections avr32_elf_create_dynamic_sections
4006 +#define bfd_elf32_bfd_link_hash_table_create avr32_elf_link_hash_table_create
4007 +#define elf_backend_adjust_dynamic_symbol avr32_elf_adjust_dynamic_symbol
4008 +#define elf_backend_size_dynamic_sections avr32_elf_size_dynamic_sections
4009 +#define elf_backend_finish_dynamic_symbol avr32_elf_finish_dynamic_symbol
4010 +#define elf_backend_finish_dynamic_sections avr32_elf_finish_dynamic_sections
4011 +
4012 +#define bfd_elf32_bfd_relax_section    avr32_elf_relax_section
4013 +
4014 +/* Find out which symbols need an entry in .got. */
4015 +#define elf_backend_check_relocs       avr32_check_relocs
4016 +#define elf_backend_can_refcount       1
4017 +#define elf_backend_can_gc_sections    1
4018 +#define elf_backend_plt_readonly       1
4019 +#define elf_backend_plt_not_loaded     1
4020 +#define elf_backend_want_plt_sym       0
4021 +#define elf_backend_plt_alignment      2
4022 +#define elf_backend_want_dynbss                0
4023 +#define elf_backend_want_got_plt       0
4024 +#define elf_backend_want_got_sym       1
4025 +#define elf_backend_got_header_size    AVR32_GOT_HEADER_SIZE
4026 +
4027 +#include "elf32-target.h"
4028 --- /dev/null
4029 +++ b/bfd/elf32-avr32.h
4030 @@ -0,0 +1,23 @@
4031 +/* AVR32-specific support for 32-bit ELF.
4032 +   Copyright 2007,2008,2009 Atmel Corporation.
4033 +
4034 +   Written by Haavard Skinnemoen, Atmel Norway, <hskinnemoen@atmel.com>
4035 +
4036 +   This file is part of BFD, the Binary File Descriptor library.
4037 +
4038 +   This program is free software; you can redistribute it and/or modify
4039 +   it under the terms of the GNU General Public License as published by
4040 +   the Free Software Foundation; either version 2 of the License, or
4041 +   (at your option) any later version.
4042 +
4043 +   This program is distributed in the hope that it will be useful,
4044 +   but WITHOUT ANY WARRANTY; without even the implied warranty of
4045 +   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
4046 +   GNU General Public License for more details.
4047 +
4048 +   You should have received a copy of the GNU General Public License
4049 +   along with this program; if not, write to the Free Software
4050 +   Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
4051 +
4052 +void bfd_elf32_avr32_set_options(struct bfd_link_info *info,
4053 +                                int direct_data_refs);
4054 --- a/bfd/elf-bfd.h
4055 +++ b/bfd/elf-bfd.h
4056 @@ -1503,6 +1503,10 @@ struct elf_obj_tdata
4057       find_nearest_line.  */
4058    struct mips_elf_find_line *find_line_info;
4059
4060 +  /* Used by AVR32 ELF relaxation code.  Contains an array of pointers
4061 +     for each local symbol to the fragment where it is defined.  */
4062 +  struct fragment **local_sym_frag;
4063 +
4064    /* A place to stash dwarf1 info for this bfd.  */
4065    struct dwarf1_debug *dwarf1_find_line_info;
4066
4067 --- a/bfd/Makefile.am
4068 +++ b/bfd/Makefile.am
4069 @@ -73,6 +73,7 @@ ALL_MACHINES = \
4070         cpu-arc.lo \
4071         cpu-arm.lo \
4072         cpu-avr.lo \
4073 +       cpu-avr32.lo \
4074         cpu-bfin.lo \
4075         cpu-cr16.lo \
4076         cpu-cr16c.lo \
4077 @@ -269,6 +270,7 @@ BFD32_BACKENDS = \
4078         elf32-arc.lo \
4079         elf32-arm.lo \
4080         elf32-avr.lo \
4081 +       elf32-avr32.lo \
4082         elf32-bfin.lo \
4083         elf32-cr16.lo \
4084         elf32-cr16c.lo \
4085 --- a/bfd/reloc.c
4086 +++ b/bfd/reloc.c
4087 @@ -4052,6 +4052,131 @@ ENUMDOC
4088    instructions
4089
4090  ENUM
4091 +  BFD_RELOC_AVR32_DIFF32
4092 +ENUMX
4093 +  BFD_RELOC_AVR32_DIFF16
4094 +ENUMX
4095 +  BFD_RELOC_AVR32_DIFF8
4096 +ENUMDOC
4097 +  Difference between two labels: L2 - L1. The value of L1 is encoded
4098 +  as sym + addend, while the initial difference after assembly is
4099 +  inserted into the object file by the assembler.
4100 +ENUM
4101 +  BFD_RELOC_AVR32_GOT32
4102 +ENUMX
4103 +  BFD_RELOC_AVR32_GOT16
4104 +ENUMX
4105 +  BFD_RELOC_AVR32_GOT8
4106 +ENUMDOC
4107 +  Reference to a symbol through the Global Offset Table. The linker
4108 +  will allocate an entry for symbol in the GOT and insert the offset
4109 +  of this entry as the relocation value.
4110 +ENUM
4111 +  BFD_RELOC_AVR32_21S
4112 +ENUMX
4113 +  BFD_RELOC_AVR32_16U
4114 +ENUMX
4115 +  BFD_RELOC_AVR32_16S
4116 +ENUMX
4117 +  BFD_RELOC_AVR32_SUB5
4118 +ENUMX
4119 +  BFD_RELOC_AVR32_8S_EXT
4120 +ENUMX
4121 +  BFD_RELOC_AVR32_8S
4122 +ENUMX
4123 +  BFD_RELOC_AVR32_15S
4124 +ENUMDOC
4125 +  Normal (non-pc-relative) code relocations. Alignment and signedness
4126 +  is indicated by the suffixes. S means signed, U means unsigned. W
4127 +  means word-aligned, H means halfword-aligned, neither means
4128 +  byte-aligned (no alignment.) SUB5 is the same relocation as 16S.
4129 +ENUM
4130 +  BFD_RELOC_AVR32_22H_PCREL
4131 +ENUMX
4132 +  BFD_RELOC_AVR32_18W_PCREL
4133 +ENUMX
4134 +  BFD_RELOC_AVR32_16B_PCREL
4135 +ENUMX
4136 +  BFD_RELOC_AVR32_16N_PCREL
4137 +ENUMX
4138 +  BFD_RELOC_AVR32_14UW_PCREL
4139 +ENUMX
4140 +  BFD_RELOC_AVR32_11H_PCREL
4141 +ENUMX
4142 +  BFD_RELOC_AVR32_10UW_PCREL
4143 +ENUMX
4144 +  BFD_RELOC_AVR32_9H_PCREL
4145 +ENUMX
4146 +  BFD_RELOC_AVR32_9UW_PCREL
4147 +ENUMDOC
4148 +  PC-relative relocations are signed if neither 'U' nor 'S' is
4149 +  specified. However, we explicitly tack on a 'B' to indicate no
4150 +  alignment, to avoid confusion with data relocs. All of these resolve
4151 +  to sym + addend - offset, except the one with 'N' (negated) suffix.
4152 +  This particular one resolves to offset - sym - addend.
4153 +ENUM
4154 +  BFD_RELOC_AVR32_GOTPC
4155 +ENUMDOC
4156 +  Subtract the link-time address of the GOT from (symbol + addend)
4157 +  and insert the result.
4158 +ENUM
4159 +  BFD_RELOC_AVR32_GOTCALL
4160 +ENUMX
4161 +  BFD_RELOC_AVR32_LDA_GOT
4162 +ENUMX
4163 +  BFD_RELOC_AVR32_GOT21S
4164 +ENUMX
4165 +  BFD_RELOC_AVR32_GOT18SW
4166 +ENUMX
4167 +  BFD_RELOC_AVR32_GOT16S
4168 +ENUMDOC
4169 +  Reference to a symbol through the GOT. The linker will allocate an
4170 +  entry for symbol in the GOT and insert the offset of this entry as
4171 +  the relocation value. addend must be zero. As usual, 'S' means
4172 +  signed, 'W' means word-aligned, etc.
4173 +ENUM
4174 +  BFD_RELOC_AVR32_32_CPENT
4175 +ENUMDOC
4176 +  32-bit constant pool entry. I don't think 8- and 16-bit entries make
4177 +  a whole lot of sense.
4178 +ENUM
4179 +  BFD_RELOC_AVR32_CPCALL
4180 +ENUMX
4181 +  BFD_RELOC_AVR32_16_CP
4182 +ENUMX
4183 +  BFD_RELOC_AVR32_9W_CP
4184 +ENUMDOC
4185 +  Constant pool references. Some of these relocations are signed,
4186 +  others are unsigned. It doesn't really matter, since the constant
4187 +  pool always comes after the code that references it.
4188 +ENUM
4189 +  BFD_RELOC_AVR32_ALIGN
4190 +ENUMDOC
4191 +  sym must be the absolute symbol. The addend specifies the alignment
4192 +  order, e.g. if addend is 2, the linker must add padding so that the
4193 +  next address is aligned to a 4-byte boundary.
4194 +ENUM
4195 +  BFD_RELOC_AVR32_14UW
4196 +ENUMX
4197 +  BFD_RELOC_AVR32_10UW
4198 +ENUMX
4199 +  BFD_RELOC_AVR32_10SW
4200 +ENUMX
4201 +  BFD_RELOC_AVR32_STHH_W
4202 +ENUMX
4203 +  BFD_RELOC_AVR32_7UW
4204 +ENUMX
4205 +  BFD_RELOC_AVR32_6S
4206 +ENUMX
4207 +  BFD_RELOC_AVR32_6UW
4208 +ENUMX
4209 +  BFD_RELOC_AVR32_4UH
4210 +ENUMX
4211 +  BFD_RELOC_AVR32_3U
4212 +ENUMDOC
4213 +  Code relocations that will never make it to the output file.
4214 +
4215 +ENUM
4216    BFD_RELOC_390_12
4217  ENUMDOC
4218     Direct 12 bit.
4219 --- a/bfd/targets.c
4220 +++ b/bfd/targets.c
4221 @@ -568,6 +568,7 @@ extern const bfd_target b_out_vec_big_ho
4222  extern const bfd_target b_out_vec_little_host;
4223  extern const bfd_target bfd_pei_ia64_vec;
4224  extern const bfd_target bfd_elf32_avr_vec;
4225 +extern const bfd_target bfd_elf32_avr32_vec;
4226  extern const bfd_target bfd_elf32_bfin_vec;
4227  extern const bfd_target bfd_elf32_bfinfdpic_vec;
4228  extern const bfd_target bfd_elf32_big_generic_vec;
4229 @@ -896,6 +897,7 @@ static const bfd_target * const _bfd_tar
4230         &bfd_pei_ia64_vec,
4231  #endif
4232         &bfd_elf32_avr_vec,
4233 +       &bfd_elf32_avr32_vec,
4234         &bfd_elf32_bfin_vec,
4235         &bfd_elf32_bfinfdpic_vec,
4236
4237 --- a/binutils/doc/binutils.info
4238 +++ b/binutils/doc/binutils.info
4239 @@ -1665,6 +1665,10 @@ equivalent.  At least one option from th
4240       useful when attempting to disassemble thumb code produced by other
4241       compilers.
4242
4243 +     For the AVR32 architectures that support Floating point unit (FPU),
4244 +     specifying '-M decode-fpu' will enable disassembler to print the
4245 +     floating point instruction instead of 'cop' instructions.
4246 +
4247       For the x86, some of the options duplicate functions of the `-m'
4248       switch, but allow finer grained control.  Multiple selections from
4249       the following may be specified as a comma separated string.
4250 --- a/binutils/doc/binutils.texi
4251 +++ b/binutils/doc/binutils.texi
4252 @@ -1935,6 +1935,10 @@ using the switch @option{--disassembler-
4253  useful when attempting to disassemble thumb code produced by other
4254  compilers.
4255
4256 +For the AVR32 architectures that support Floating point unit (FPU),
4257 +specifying @option{-M decode-fpu} will enable disassembler to print the
4258 +floating point instructions instead of 'cop' instructions.
4259 +
4260  For the x86, some of the options duplicate functions of the @option{-m}
4261  switch, but allow finer grained control.  Multiple selections from the
4262  following may be specified as a comma separated string.
4263 --- a/binutils/doc/objdump.1
4264 +++ b/binutils/doc/objdump.1
4265 @@ -425,6 +425,10 @@ using the switch \fB\-\-disassembler\-op
4266  useful when attempting to disassemble thumb code produced by other
4267  compilers.
4268  .Sp
4269 +For the \s-1AVR32\s0 architectures that support Floating point unit (FPU),
4270 +specifying \fB\-M decode\-fpu\fR will enable disassembler to print the
4271 +floating point instructions instead of 'cop' instructions.
4272 +.Sp
4273  For the x86, some of the options duplicate functions of the \fB\-m\fR
4274  switch, but allow finer grained control.  Multiple selections from the
4275  following may be specified as a comma separated string.
4276 --- a/binutils/readelf.c
4277 +++ b/binutils/readelf.c
4278 @@ -94,6 +94,7 @@
4279  #include "elf/arc.h"
4280  #include "elf/arm.h"
4281  #include "elf/avr.h"
4282 +#include "elf/avr32.h"
4283  #include "elf/bfin.h"
4284  #include "elf/cr16.h"
4285  #include "elf/cris.h"
4286 @@ -570,6 +571,7 @@ guess_is_rela (unsigned int e_machine)
4287      case EM_ALPHA:
4288      case EM_ALTERA_NIOS2:
4289      case EM_AVR:
4290 +    case EM_AVR32:
4291      case EM_AVR_OLD:
4292      case EM_BLACKFIN:
4293      case EM_CR16:
4294 @@ -1020,6 +1022,10 @@ dump_relocations (FILE * file,
4295           rtype = elf_avr_reloc_type (type);
4296           break;
4297
4298 +       case EM_AVR32:
4299 +         rtype = elf_avr32_reloc_type (type);
4300 +         break;
4301 +
4302         case EM_OLD_SPARCV9:
4303         case EM_SPARC32PLUS:
4304         case EM_SPARCV9:
4305 @@ -1853,6 +1859,7 @@ get_machine_name (unsigned e_machine)
4306      case EM_VAX:               return "Digital VAX";
4307      case EM_AVR_OLD:
4308      case EM_AVR:               return "Atmel AVR 8-bit microcontroller";
4309 +    case EM_AVR32:             return "Atmel AVR32 32-bit microprocessor";
4310      case EM_CRIS:              return "Axis Communications 32-bit embedded processor";
4311      case EM_JAVELIN:           return "Infineon Technologies 32-bit embedded cpu";
4312      case EM_FIREPATH:          return "Element 14 64-bit DSP processor";
4313 --- a/gas/as.c
4314 +++ b/gas/as.c
4315 @@ -445,10 +445,10 @@ parse_args (int * pargc, char *** pargv)
4316         the end of the preceeding line so that it is simpler to
4317         selectively add and remove lines from this list.  */
4318      {"alternate", no_argument, NULL, OPTION_ALTERNATE}
4319 -    /* The entry for "a" is here to prevent getopt_long_only() from
4320 -       considering that -a is an abbreviation for --alternate.  This is
4321 -       necessary because -a=<FILE> is a valid switch but getopt would
4322 -       normally reject it since --alternate does not take an argument.  */
4323 +    /* The next two entries are here to prevent getopt_long_only() from
4324 +       considering that -a or -al is an abbreviation for --alternate.
4325 +       This is necessary because -a=<FILE> is a valid switch but getopt
4326 +       would normally reject it since --alternate does not take an argument.  */
4327      ,{"a", optional_argument, NULL, 'a'}
4328      /* Handle -al=<FILE>.  */
4329      ,{"al", optional_argument, NULL, OPTION_AL}
4330 @@ -811,8 +811,15 @@ This program has absolutely no warranty.
4331         case 'a':
4332           if (optarg)
4333             {
4334 -             if (optarg != old_argv[optind] && optarg[-1] == '=')
4335 +             /* If optarg is part of the -a switch and not a separate argument
4336 +                in its own right, then scan backwards to the just after the -a.
4337 +                This means skipping over both '=' and 'l' which might have been
4338 +                taken to be part of the -a switch itself.  */
4339 +             if (optarg != old_argv[optind])
4340 +               {
4341 +                 while (optarg[-1] == '=' || optarg[-1] == 'l')
4342                 --optarg;
4343 +               }
4344
4345               if (md_parse_option (optc, optarg) != 0)
4346                 break;
4347 @@ -1245,7 +1252,7 @@ main (int argc, char ** argv)
4348      keep_it = 0;
4349
4350    if (!keep_it)
4351 -    unlink_if_ordinary (out_file_name);
4352 +    unlink (out_file_name);
4353
4354    input_scrub_end ();
4355
4356 --- a/gas/as.h
4357 +++ b/gas/as.h
4358 @@ -110,6 +110,7 @@ typedef int * va_list;
4359  #endif
4360  #define gas_assert(P) \
4361    ((void) ((P) ? 0 : (as_assert (__FILE__, __LINE__, __PRETTY_FUNCTION__), 0)))
4362 +#define assert(P)   gas_assert(P)
4363  #undef abort
4364  #define abort()                as_abort (__FILE__, __LINE__, __PRETTY_FUNCTION__)
4365
4366 --- a/gas/atof-generic.c
4367 +++ b/gas/atof-generic.c
4368 @@ -121,6 +121,21 @@ atof_generic (/* return pointer to just
4369
4370    switch (first_digit[0])
4371      {
4372 +    case 's':
4373 +    case 'S':
4374 +    case 'q':
4375 +    case 'Q':
4376 +      if (!strncasecmp ("nan", first_digit+1, 3))
4377 +       {
4378 +         address_of_generic_floating_point_number->sign = 0;
4379 +         address_of_generic_floating_point_number->exponent = 0;
4380 +         address_of_generic_floating_point_number->leader =
4381 +           address_of_generic_floating_point_number->low;
4382 +         *address_of_string_pointer = first_digit + 4;
4383 +         return 0;
4384 +       }
4385 +      break;
4386 +
4387      case 'n':
4388      case 'N':
4389        if (!strncasecmp ("nan", first_digit, 3))
4390 --- a/gas/config/atof-vax.c
4391 +++ b/gas/config/atof-vax.c
4392 @@ -268,9 +268,27 @@ flonum_gen2vax (int format_letter, /* On
4393           int exponent_skippage;
4394           LITTLENUM_TYPE word1;
4395
4396 -         /* JF: Deal with new Nan, +Inf and -Inf codes.  */
4397 +         /* JF: Deal with new +/-(q/Q/s/S)Nan, +Inf and -Inf codes.  */
4398           if (f->sign != '-' && f->sign != '+')
4399             {
4400 +          if (f->sign == 0)
4401 +            {
4402 +              /* All NaNs are 0.  */
4403 +              memset (words, 0x00, sizeof (LITTLENUM_TYPE) * precision);
4404 +            }
4405 +          else if (f->sign == 'P')
4406 +            {
4407 +              /* Positive Infinity.  */
4408 +              memset (words, 0xff, sizeof (LITTLENUM_TYPE) * precision);
4409 +              words[0] &= 0x7fff;
4410 +            }
4411 +          else if (f->sign == 'N')
4412 +            {
4413 +              /* Negative Infinity.  */
4414 +              memset (words, 0x00, sizeof (LITTLENUM_TYPE) * precision);
4415 +              words[0] = 0x0080;
4416 +            }
4417 +          else
4418               make_invalid_floating_point_number (words);
4419               return return_value;
4420             }
4421 --- /dev/null
4422 +++ b/gas/config/tc-avr32.c
4423 @@ -0,0 +1,4839 @@
4424 +/* Assembler implementation for AVR32.
4425 +   Copyright 2003,2004,2005,2006,2007,2008,2009,2010 Atmel Corporation.
4426 +
4427 +   Written by Haavard Skinnemoen, Atmel Norway, <hskinnemoen@atmel.com>
4428 +
4429 +   This file is part of GAS, the GNU Assembler.
4430 +
4431 +   GAS is free software; you can redistribute it and/or modify it
4432 +   under the terms of the GNU General Public License as published by
4433 +   the Free Software Foundation; either version 2, or (at your option)
4434 +   any later version.
4435 +
4436 +   GAS is distributed in the hope that it will be useful, but WITHOUT
4437 +   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
4438 +   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
4439 +   License for more details.
4440 +
4441 +   You should have received a copy of the GNU General Public License
4442 +   along with GAS; see the file COPYING.  If not, write to the Free
4443 +   Software Foundation, 59 Temple Place - Suite 330, Boston, MA
4444 +   02111-1307, USA.  */
4445 +
4446 +#include <stdio.h>
4447 +#include "as.h"
4448 +#include "safe-ctype.h"
4449 +#include "subsegs.h"
4450 +#include "symcat.h"
4451 +#include "opcodes/avr32-opc.h"
4452 +#include "opcodes/avr32-asm.h"
4453 +#include "elf/avr32.h"
4454 +#include "dwarf2dbg.h"
4455 +
4456 +#define xDEBUG
4457 +#define xOPC_CONSISTENCY_CHECK
4458 +
4459 +#ifdef DEBUG
4460 +# define pr_debug(fmt, args...) fprintf(stderr, fmt, ##args)
4461 +#else
4462 +# define pr_debug(fmt, args...)
4463 +#endif
4464 +
4465 +/* 3 MSB of instruction word indicate group. Group 7 -> extended */
4466 +#define AVR32_COMPACT_P(opcode) ((opcode[0] & 0xe0) != 0xe0)
4467 +
4468 +#define streq(a, b)            (strcmp(a, b) == 0)
4469 +#define skip_whitespace(str)   do { while(*(str) == ' ') ++(str); } while(0)
4470 +
4471 +/* Flags given on the command line */
4472 +static int avr32_pic   = FALSE;
4473 +int linkrelax  = FALSE;
4474 +int avr32_iarcompat    = FALSE;
4475 +
4476 +/* This array holds the chars that always start a comment. */
4477 +const char comment_chars[]             = "#";
4478 +
4479 +/* This array holds the chars that only start a comment at the
4480 +   beginning of a line.  We must include '#' here because the compiler
4481 +   may produce #APP and #NO_APP in its output.  */
4482 +const char line_comment_chars[]                = "#";
4483 +
4484 +/* These may be used instead of newline (same as ';' in C).  */
4485 +const char line_separator_chars[]      = ";";
4486 +
4487 +/* Chars that can be used to separate mantissa from exponent in
4488 +   floating point numbers.  */
4489 +const char EXP_CHARS[]                 = "eE";
4490 +
4491 +/* Chars that mean this number is a floating point constant.  */
4492 +const char FLT_CHARS[]                 = "dD";
4493 +
4494 +/* Pre-defined "_GLOBAL_OFFSET_TABLE_"  */
4495 +symbolS *GOT_symbol;
4496 +
4497 +static struct hash_control *avr32_mnemonic_htab;
4498 +
4499 +struct avr32_ifield_data
4500 +{
4501 +  bfd_vma value;
4502 +  /* FIXME: Get rid of align_order and complain. complain is never
4503 +     used, align_order is used in one place.  Try to use the relax
4504 +     table instead.  */
4505 +  unsigned int align_order;
4506 +};
4507 +
4508 +struct avr32_insn
4509 +{
4510 +  const struct avr32_syntax *syntax;
4511 +  expressionS immediate;
4512 +  int pcrel;
4513 +  int force_extended;
4514 +  unsigned int next_slot;
4515 +  bfd_reloc_code_real_type r_type;
4516 +  struct avr32_ifield_data field_value[AVR32_MAX_FIELDS];
4517 +};
4518 +
4519 +static struct avr32_insn current_insn;
4520 +
4521 +/* The target specific pseudo-ops we support. */
4522 +static void s_rseg (int);
4523 +static void s_cpool(int);
4524 +
4525 +const pseudo_typeS md_pseudo_table[] =
4526 +{
4527 +  /* Make sure that .word is 32 bits */
4528 +  { "word", cons, 4 },
4529 +  { "file", (void (*) PARAMS ((int))) dwarf2_directive_file, 0 },
4530 +  { "loc", dwarf2_directive_loc, 0 },
4531 +
4532 +  /* .lcomm requires an explicit alignment parameter */
4533 +  { "lcomm", s_lcomm, 1 },
4534 +
4535 +  /* AVR32-specific pseudo-ops */
4536 +  { "cpool", s_cpool, 0},
4537 +
4538 +  /* IAR compatible pseudo-ops */
4539 +  { "program", s_ignore, 0 },
4540 +  { "public", s_globl, 0 },
4541 +  { "extern", s_ignore, 0 },
4542 +  { "module", s_ignore, 0 },
4543 +  { "rseg", s_rseg, 0 },
4544 +  { "dc8", cons, 1 },
4545 +  { "dc16", cons, 2 },
4546 +  { "dc32", cons, 4 },
4547 +
4548 +  { NULL, NULL, 0 }
4549 +};
4550 +
4551 +/* Questionable stuff starts here */
4552 +
4553 +enum avr32_opinfo {
4554 +  AVR32_OPINFO_NONE = BFD_RELOC_NONE,
4555 +  AVR32_OPINFO_GOT,
4556 +  AVR32_OPINFO_TLSGD,
4557 +  AVR32_OPINFO_HI,
4558 +  AVR32_OPINFO_LO,
4559 +};
4560 +
4561 +enum avr32_arch {
4562 +  ARCH_TYPE_AP,
4563 +  ARCH_TYPE_UCR1,
4564 +  ARCH_TYPE_UCR2,
4565 +  ARCH_TYPE_UCR3,
4566 +  ARCH_TYPE_UCR3FP
4567 +};
4568 +
4569 +struct arch_type_s
4570 +{
4571 +  /* Architecture name */
4572 +  char *name;
4573 +  /* Instruction Set Architecture Flags */
4574 +  unsigned long isa_flags;
4575 +};
4576 +
4577 +struct part_type_s
4578 +{
4579 +  /* Part name */
4580 +  char *name;
4581 +  /* Architecture type */
4582 +  unsigned int arch;
4583 +};
4584 +
4585 +static struct arch_type_s arch_types[] =
4586 +{
4587 +    {"ap", AVR32_V1 | AVR32_SIMD | AVR32_DSP | AVR32_PICO},
4588 +    {"ucr1", AVR32_V1 | AVR32_DSP | AVR32_RMW},
4589 +    {"ucr2", AVR32_V1 | AVR32_V2 | AVR32_DSP | AVR32_RMW},
4590 +    {"ucr3", AVR32_V1 | AVR32_V2 | AVR32_V3 | AVR32_DSP | AVR32_RMW},
4591 +    {"ucr3fp", AVR32_V1 | AVR32_V2 | AVR32_V3 | AVR32_DSP | AVR32_RMW | AVR32_V3FP},
4592 +    {"all-insn", AVR32_V1 | AVR32_V2 | AVR32_V3 | AVR32_SIMD | AVR32_DSP | AVR32_RMW | AVR32_V3FP | AVR32_PICO},
4593 +    {NULL, 0}
4594 +};
4595 +
4596 +static struct part_type_s part_types[] =
4597 +{
4598 +    {"ap7000",        ARCH_TYPE_AP},
4599 +    {"ap7001",        ARCH_TYPE_AP},
4600 +    {"ap7002",        ARCH_TYPE_AP},
4601 +    {"ap7200",        ARCH_TYPE_AP},
4602 +    {"uc3a0128",      ARCH_TYPE_UCR2},
4603 +    {"uc3a0256",      ARCH_TYPE_UCR2},
4604 +    {"uc3a0512es",    ARCH_TYPE_UCR1},
4605 +    {"uc3a0512",      ARCH_TYPE_UCR2},
4606 +    {"uc3a1128",      ARCH_TYPE_UCR2},
4607 +    {"uc3a1256es",    ARCH_TYPE_UCR1},
4608 +    {"uc3a1256",      ARCH_TYPE_UCR2},
4609 +    {"uc3a1512es",    ARCH_TYPE_UCR1},
4610 +    {"uc3a1512",      ARCH_TYPE_UCR2},
4611 +    {"uc3a364",       ARCH_TYPE_UCR2},
4612 +    {"uc3a364s",      ARCH_TYPE_UCR2},
4613 +    {"uc3a3128",      ARCH_TYPE_UCR2},
4614 +    {"uc3a3128s",     ARCH_TYPE_UCR2},
4615 +    {"uc3a3256",      ARCH_TYPE_UCR2},
4616 +    {"uc3a3256s",     ARCH_TYPE_UCR2},
4617 +    {"uc3b064",       ARCH_TYPE_UCR1},
4618 +    {"uc3b0128",      ARCH_TYPE_UCR1},
4619 +    {"uc3b0256es",    ARCH_TYPE_UCR1},
4620 +    {"uc3b0256",      ARCH_TYPE_UCR1},
4621 +    {"uc3b0512",      ARCH_TYPE_UCR2},
4622 +    {"uc3b0512revc",  ARCH_TYPE_UCR2},
4623 +    {"uc3b164",       ARCH_TYPE_UCR1},
4624 +    {"uc3b1128",      ARCH_TYPE_UCR1},
4625 +    {"uc3b1256",      ARCH_TYPE_UCR1},
4626 +    {"uc3b1256es",    ARCH_TYPE_UCR1},
4627 +    {"uc3b1512",      ARCH_TYPE_UCR2},
4628 +    {"uc3b1512revc",  ARCH_TYPE_UCR2},
4629 +    {"uc3c0512crevc", ARCH_TYPE_UCR3},
4630 +    {"uc3c1512crevc", ARCH_TYPE_UCR3},
4631 +    {"uc3c2512crevc", ARCH_TYPE_UCR3},
4632 +    {"atuc3l0256",    ARCH_TYPE_UCR3},
4633 +    {"mxt768e",       ARCH_TYPE_UCR3},
4634 +    {"uc3l064",       ARCH_TYPE_UCR3},
4635 +    {"uc3l032",       ARCH_TYPE_UCR3},
4636 +    {"uc3l016",       ARCH_TYPE_UCR3},
4637 +    {"uc3l064revb",   ARCH_TYPE_UCR3},
4638 +    {"uc3c064c",  ARCH_TYPE_UCR3FP},
4639 +    {"uc3c0128c",   ARCH_TYPE_UCR3FP},
4640 +    {"uc3c0256c",   ARCH_TYPE_UCR3FP},
4641 +    {"uc3c0512c",   ARCH_TYPE_UCR3FP},
4642 +    {"uc3c164c",  ARCH_TYPE_UCR3FP},
4643 +    {"uc3c1128c",   ARCH_TYPE_UCR3FP},
4644 +    {"uc3c1256c",   ARCH_TYPE_UCR3FP},
4645 +    {"uc3c1512c",   ARCH_TYPE_UCR3FP},
4646 +    {"uc3c264c",  ARCH_TYPE_UCR3FP},
4647 +    {"uc3c2128c",   ARCH_TYPE_UCR3FP},
4648 +    {"uc3c2256c",   ARCH_TYPE_UCR3FP},
4649 +    {"uc3c2512c",   ARCH_TYPE_UCR3FP},
4650 +    {NULL, 0}
4651 +};
4652 +
4653 +/* Current architecture type.  */
4654 +static struct arch_type_s default_arch = {"all-insn", AVR32_V1 | AVR32_V2 | AVR32_V3 | AVR32_SIMD | AVR32_DSP | AVR32_RMW | AVR32_V3FP | AVR32_PICO };
4655 +static struct arch_type_s *avr32_arch = &default_arch;
4656 +
4657 +/* Display nicely formatted list of known part- and architecture names.  */
4658 +
4659 +static void
4660 +show_arch_list (FILE *stream)
4661 +{
4662 +  int i, x;
4663 +
4664 +  fprintf (stream, _("Architectures supported by the assembler:"));
4665 +  x = 1000;
4666 +
4667 +  for (i = 0; arch_types[i].name; i++)
4668 +    {
4669 +      int len = strlen (arch_types[i].name);
4670 +
4671 +      x += len + 1;
4672 +
4673 +      if (x < 75)
4674 +       fprintf (stream, " %s", arch_types[i].name);
4675 +      else
4676 +       {
4677 +         fprintf (stream, "\n  %s", arch_types[i].name);
4678 +         x = len + 2;
4679 +       }
4680 +    }
4681 +
4682 +  fprintf (stream, "\n");
4683 +}
4684 +
4685 +static void
4686 +show_part_list (FILE *stream)
4687 +{
4688 +  int i, x;
4689 +
4690 +  fprintf (stream, _("Known part names:"));
4691 +  x = 1000;
4692 +
4693 +  for (i = 0; part_types[i].name; i++)
4694 +    {
4695 +      int len = strlen(part_types[i].name);
4696 +
4697 +      x += len + 1;
4698 +
4699 +      if (x < 75)
4700 +       fprintf (stream, " %s", part_types[i].name);
4701 +      else
4702 +       {
4703 +         fprintf(stream, "\n  %s", part_types[i].name);
4704 +         x = len + 2;
4705 +       }
4706 +    }
4707 +
4708 +  fprintf (stream, "\n");
4709 +}
4710 +
4711 +const char *md_shortopts = "";
4712 +struct option md_longopts[] =
4713 +{
4714 +#define OPTION_ARCH            (OPTION_MD_BASE)
4715 +#define OPTION_PART            (OPTION_ARCH + 1)
4716 +#define OPTION_IAR             (OPTION_PART + 1)
4717 +#define OPTION_PIC             (OPTION_IAR + 1)
4718 +#define OPTION_NOPIC           (OPTION_PIC + 1)
4719 +#define OPTION_LINKRELAX       (OPTION_NOPIC + 1)
4720 +#define OPTION_NOLINKRELAX     (OPTION_LINKRELAX + 1)
4721 +#define OPTION_DIRECT_DATA_REFS (OPTION_NOLINKRELAX + 1)
4722 +  {"march",            required_argument, NULL, OPTION_ARCH},
4723 +  {"mpart",            required_argument, NULL, OPTION_PART},
4724 +  {"iar",              no_argument, NULL, OPTION_IAR},
4725 +  {"pic",              no_argument, NULL, OPTION_PIC},
4726 +  {"no-pic",           no_argument, NULL, OPTION_NOPIC},
4727 +  {"linkrelax",                no_argument, NULL, OPTION_LINKRELAX},
4728 +  {"no-linkrelax",     no_argument, NULL, OPTION_NOLINKRELAX},
4729 +  /* deprecated alias for -mpart=xxx */
4730 +  {"mcpu",             required_argument, NULL, OPTION_PART},
4731 +  {NULL,               no_argument, NULL, 0}
4732 +};
4733 +
4734 +size_t md_longopts_size = sizeof (md_longopts);
4735 +
4736 +void
4737 +md_show_usage (FILE *stream)
4738 +{
4739 +  fprintf (stream, _("\
4740 +AVR32 options:\n\
4741 +  -march=[arch-name]      Select cpu architecture. [Default `all-insn']\n\
4742 +  -mpart=[part-name]      Select specific part. [Default `none']\n\
4743 +  --pic                   Produce Position-Independent Code\n\
4744 +  --no-pic                Don't produce Position-Independent Code\n\
4745 +  --linkrelax             Produce output suitable for linker relaxing\n\
4746 +  --no-linkrelax          Don't produce output suitable for linker relaxing\n"));
4747 +  show_arch_list(stream);
4748 +}
4749 +
4750 +int
4751 +md_parse_option (int c, char *arg ATTRIBUTE_UNUSED)
4752 +{
4753 +  switch (c)
4754 +    {
4755 +    case OPTION_ARCH:
4756 +      {
4757 +       int i;
4758 +       char *s = alloca (strlen (arg) + 1);
4759 +
4760 +       {
4761 +         char *t = s;
4762 +         char *arg1 = arg;
4763 +
4764 +         do
4765 +           *t = TOLOWER (*arg1++);
4766 +         while (*t++);
4767 +       }
4768 +
4769 +        /* Add backward compability */
4770 +        if (strcmp ("uc", s)== 0)
4771 +          {
4772 +            as_warn("Deprecated arch `%s' specified. "
4773 +                    "Please use '-march=ucr1' instead. "
4774 +                    "Using to arch 'ucr1'\n",
4775 +                     s);
4776 +            s="ucr1";
4777 +          }
4778 +
4779 +       for (i = 0; arch_types[i].name; ++i)
4780 +         if (strcmp (arch_types[i].name, s) == 0)
4781 +           break;
4782 +
4783 +       if (!arch_types[i].name)
4784 +         {
4785 +           show_arch_list (stderr);
4786 +           as_fatal (_("unknown architecture: %s\n"), arg);
4787 +         }
4788 +
4789 +        avr32_arch = &arch_types[i];
4790 +       break;
4791 +      }
4792 +    case OPTION_PART:
4793 +      {
4794 +       int i;
4795 +       char *s = alloca (strlen (arg) + 1);
4796 +       char *t = s;
4797 +       char *p = arg;
4798 +
4799 +       /* If arch type has already been set, don't bother.
4800 +          -march= always overrides -mpart=  */
4801 +       if (avr32_arch != &default_arch)
4802 +         break;
4803 +
4804 +       do
4805 +         *t = TOLOWER (*p++);
4806 +       while (*t++);
4807 +
4808 +       for (i = 0; part_types[i].name; ++i)
4809 +         if (strcmp (part_types[i].name, s) == 0)
4810 +           break;
4811 +
4812 +       if (!part_types[i].name)
4813 +         {
4814 +           show_part_list (stderr);
4815 +           as_fatal (_("unknown part: %s\n"), arg);
4816 +         }
4817 +
4818 +       avr32_arch = &arch_types[part_types[i].arch];
4819 +       break;
4820 +      }
4821 +    case OPTION_IAR:
4822 +      avr32_iarcompat = 1;
4823 +      break;
4824 +    case OPTION_PIC:
4825 +      avr32_pic = 1;
4826 +      break;
4827 +    case OPTION_NOPIC:
4828 +      avr32_pic = 0;
4829 +      break;
4830 +    case OPTION_LINKRELAX:
4831 +      linkrelax = 1;
4832 +      break;
4833 +    case OPTION_NOLINKRELAX:
4834 +      linkrelax = 0;
4835 +      break;
4836 +    default:
4837 +      return 0;
4838 +    }
4839 +  return 1;
4840 +}
4841 +
4842 +/* Can't use symbol_new here, so have to create a symbol and then at
4843 +   a later date assign it a value. Thats what these functions do.
4844 +
4845 +   Shamelessly stolen from ARM.  */
4846 +
4847 +static void
4848 +symbol_locate (symbolS *    symbolP,
4849 +              const char * name,       /* It is copied, the caller can modify.  */
4850 +              segT         segment,    /* Segment identifier (SEG_<something>).  */
4851 +              valueT       valu,       /* Symbol value.  */
4852 +              fragS *      frag)       /* Associated fragment.  */
4853 +{
4854 +  unsigned int name_length;
4855 +  char * preserved_copy_of_name;
4856 +
4857 +  name_length = strlen (name) + 1;   /* +1 for \0.  */
4858 +  obstack_grow (&notes, name, name_length);
4859 +  preserved_copy_of_name = obstack_finish (&notes);
4860 +#ifdef STRIP_UNDERSCORE
4861 +  if (preserved_copy_of_name[0] == '_')
4862 +    preserved_copy_of_name++;
4863 +#endif
4864 +
4865 +#ifdef tc_canonicalize_symbol_name
4866 +  preserved_copy_of_name =
4867 +    tc_canonicalize_symbol_name (preserved_copy_of_name);
4868 +#endif
4869 +
4870 +  S_SET_NAME (symbolP, preserved_copy_of_name);
4871 +
4872 +  S_SET_SEGMENT (symbolP, segment);
4873 +  S_SET_VALUE (symbolP, valu);
4874 +  symbol_clear_list_pointers (symbolP);
4875 +
4876 +  symbol_set_frag (symbolP, frag);
4877 +
4878 +  /* Link to end of symbol chain.  */
4879 +  {
4880 +    extern int symbol_table_frozen;
4881 +
4882 +    if (symbol_table_frozen)
4883 +      abort ();
4884 +  }
4885 +
4886 +  symbol_append (symbolP, symbol_lastP, & symbol_rootP, & symbol_lastP);
4887 +
4888 +  obj_symbol_new_hook (symbolP);
4889 +
4890 +#ifdef tc_symbol_new_hook
4891 +  tc_symbol_new_hook (symbolP);
4892 +#endif
4893 +
4894 +#ifdef DEBUG_SYMS
4895 +  verify_symbol_chain (symbol_rootP, symbol_lastP);
4896 +#endif /* DEBUG_SYMS  */
4897 +}
4898 +
4899 +struct cpool_entry
4900 +{
4901 +  int                  refcount;
4902 +  offsetT              offset;
4903 +  expressionS          exp;
4904 +};
4905 +
4906 +struct cpool
4907 +{
4908 +  struct cpool         *next;
4909 +  int                  used;
4910 +  struct cpool_entry   *literals;
4911 +  unsigned int         padding;
4912 +  unsigned int         next_free_entry;
4913 +  unsigned int         id;
4914 +  symbolS              *symbol;
4915 +  segT                 section;
4916 +  subsegT              sub_section;
4917 +};
4918 +
4919 +struct cpool *cpool_list = NULL;
4920 +
4921 +static struct cpool *
4922 +find_cpool(segT section, subsegT sub_section)
4923 +{
4924 +  struct cpool *pool;
4925 +
4926 +  for (pool = cpool_list; pool != NULL; pool = pool->next)
4927 +    {
4928 +      if (!pool->used
4929 +         && pool->section == section
4930 +         && pool->sub_section == sub_section)
4931 +       break;
4932 +    }
4933 +
4934 +  return pool;
4935 +}
4936 +
4937 +static struct cpool *
4938 +find_or_make_cpool(segT section, subsegT sub_section)
4939 +{
4940 +  static unsigned int next_cpool_id = 0;
4941 +  struct cpool *pool;
4942 +
4943 +  pool = find_cpool(section, sub_section);
4944 +
4945 +  if (!pool)
4946 +    {
4947 +      pool = xmalloc(sizeof(*pool));
4948 +      if (!pool)
4949 +       return NULL;
4950 +
4951 +      pool->used = 0;
4952 +      pool->literals = NULL;
4953 +      pool->padding = 0;
4954 +      pool->next_free_entry = 0;
4955 +      pool->section = section;
4956 +      pool->sub_section = sub_section;
4957 +      pool->next = cpool_list;
4958 +      pool->symbol = NULL;
4959 +
4960 +      cpool_list = pool;
4961 +    }
4962 +
4963 +  /* NULL symbol means that the pool is new or has just been emptied.  */
4964 +  if (!pool->symbol)
4965 +    {
4966 +      pool->symbol = symbol_create(FAKE_LABEL_NAME, undefined_section,
4967 +                                  0, &zero_address_frag);
4968 +      pool->id = next_cpool_id++;
4969 +    }
4970 +
4971 +  return pool;
4972 +}
4973 +
4974 +static struct cpool *
4975 +add_to_cpool(expressionS *exp, unsigned int *index, int ref)
4976 +{
4977 +  struct cpool *pool;
4978 +  unsigned int entry;
4979 +
4980 +  pool = find_or_make_cpool(now_seg, now_subseg);
4981 +
4982 +  /* Check if this constant is already in the pool.  */
4983 +  for (entry = 0; entry < pool->next_free_entry; entry++)
4984 +    {
4985 +      if ((pool->literals[entry].exp.X_op == exp->X_op)
4986 +         && (exp->X_op == O_constant)
4987 +         && (pool->literals[entry].exp.X_add_number
4988 +             == exp->X_add_number)
4989 +         && (pool->literals[entry].exp.X_unsigned
4990 +             == exp->X_unsigned))
4991 +       break;
4992 +
4993 +      if ((pool->literals[entry].exp.X_op == exp->X_op)
4994 +         && (exp->X_op == O_symbol)
4995 +         && (pool->literals[entry].exp.X_add_number
4996 +             == exp->X_add_number)
4997 +         && (pool->literals[entry].exp.X_add_symbol
4998 +             == exp->X_add_symbol)
4999 +         && (pool->literals[entry].exp.X_op_symbol
5000 +             == exp->X_op_symbol))
5001 +       break;
5002 +    }
5003 +
5004 +  /* Create an entry if we didn't find a match */
5005 +  if (entry == pool->next_free_entry)
5006 +    {
5007 +      pool->literals = xrealloc(pool->literals,
5008 +                               sizeof(struct cpool_entry) * (entry + 1));
5009 +      pool->literals[entry].exp = *exp;
5010 +      pool->literals[entry].refcount = 0;
5011 +      pool->next_free_entry++;
5012 +    }
5013 +
5014 +  if (index)
5015 +    *index = entry;
5016 +  if (ref)
5017 +    pool->literals[entry].refcount++;
5018 +
5019 +  return pool;
5020 +}
5021 +
5022 +struct avr32_operand
5023 +{
5024 +  int id;
5025 +  int is_signed;
5026 +  int is_pcrel;
5027 +  int align_order;
5028 +  int (*match)(char *str);
5029 +  void (*parse)(const struct avr32_operand *op, char *str, int opindex);
5030 +};
5031 +
5032 +static int
5033 +match_anything(char *str ATTRIBUTE_UNUSED)
5034 +{
5035 +  return 1;
5036 +}
5037 +
5038 +static int
5039 +match_intreg(char *str)
5040 +{
5041 +  int regid, ret = 1;
5042 +
5043 +  regid = avr32_parse_intreg(str);
5044 +  if (regid < 0)
5045 +    ret = 0;
5046 +
5047 +  pr_debug("match_intreg: `%s': %d\n", str, ret);
5048 +
5049 +  return ret;
5050 +}
5051 +
5052 +static int
5053 +match_intreg_predec(char *str)
5054 +{
5055 +  int regid;
5056 +
5057 +  if (str[0] != '-' || str[1] != '-')
5058 +    return 0;
5059 +
5060 +  regid = avr32_parse_intreg(str + 2);
5061 +  if (regid < 0)
5062 +    return 0;
5063 +
5064 +  return 1;
5065 +}
5066 +
5067 +static int
5068 +match_intreg_postinc(char *str)
5069 +{
5070 +  int regid, ret = 1;
5071 +  char *p, c;
5072 +
5073 +  for (p = str; *p; p++)
5074 +    if (*p == '+')
5075 +      break;
5076 +
5077 +  if (p[0] != '+' || p[1] != '+')
5078 +    return 0;
5079 +
5080 +  c = *p, *p = 0;
5081 +  regid = avr32_parse_intreg(str);
5082 +  if (regid < 0)
5083 +    ret = 0;
5084 +
5085 +  *p = c;
5086 +  return ret;
5087 +}
5088 +
5089 +static int
5090 +match_intreg_lsl(char *str)
5091 +{
5092 +  int regid, ret = 1;
5093 +  char *p, c;
5094 +
5095 +  for (p = str; *p; p++)
5096 +    if (*p == '<')
5097 +      break;
5098 +
5099 +  if (p[0] && p[1] != '<')
5100 +    return 0;
5101 +
5102 +  c = *p, *p = 0;
5103 +  regid = avr32_parse_intreg(str);
5104 +  if (regid < 0)
5105 +    ret = 0;
5106 +
5107 +  *p = c;
5108 +  return ret;
5109 +}
5110 +
5111 +static int
5112 +match_intreg_lsr(char *str)
5113 +{
5114 +  int regid, ret = 1;
5115 +  char *p, c;
5116 +
5117 +  for (p = str; *p; p++)
5118 +    if (*p == '>')
5119 +      break;
5120 +
5121 +  if (p[0] && p[1] != '>')
5122 +    return 0;
5123 +
5124 +  c = *p, *p = 0;
5125 +
5126 +  regid = avr32_parse_intreg(str);
5127 +  if (regid < 0)
5128 +    ret = 0;
5129 +
5130 +  *p = c;
5131 +  return ret;
5132 +}
5133 +
5134 +static int
5135 +match_intreg_part(char *str)
5136 +{
5137 +  int regid, ret = 1;
5138 +  char *p, c;
5139 +
5140 +  for (p = str; *p; p++)
5141 +    if (*p == ':')
5142 +      break;
5143 +
5144 +  if (p[0] != ':' || !ISPRINT(p[1]) || p[2] != '\0')
5145 +    return 0;
5146 +
5147 +  c = *p, *p = 0;
5148 +  regid = avr32_parse_intreg(str);
5149 +  if (regid < 0)
5150 +    ret = 0;
5151 +
5152 +  *p = c;
5153 +
5154 +  return ret;
5155 +}
5156 +
5157 +#define match_intreg_disp match_anything
5158 +
5159 +static int
5160 +match_intreg_index(char *str)
5161 +{
5162 +  int regid, ret = 1;
5163 +  char *p, *end, c;
5164 +
5165 +  for (p = str; *p; p++)
5166 +    if (*p == '[')
5167 +      break;
5168 +
5169 +  /* don't allow empty displacement here (it makes no sense) */
5170 +  if (p[0] != '[')
5171 +    return 0;
5172 +
5173 +  for (end = p + 1; *end; end++) ;
5174 +  if (*(--end) != ']')
5175 +    return 0;
5176 +
5177 +  c = *end, *end = 0;
5178 +  if (!match_intreg_lsl(p + 1))
5179 +    ret = 0;
5180 +  *end = c;
5181 +
5182 +  if (ret)
5183 +    {
5184 +      c = *p, *p = 0;
5185 +      regid = avr32_parse_intreg(str);
5186 +      if (regid < 0)
5187 +       ret = 0;
5188 +      *p = c;
5189 +    }
5190 +
5191 +  return ret;
5192 +}
5193 +
5194 +static int
5195 +match_intreg_xindex(char *str)
5196 +{
5197 +  int regid, ret = 1;
5198 +  char *p, *end, c;
5199 +
5200 +  for (p = str; *p; p++)
5201 +    if (*p == '[')
5202 +      break;
5203 +
5204 +  /* empty displacement makes no sense here either */
5205 +  if (p[0] != '[')
5206 +    return 0;
5207 +
5208 +  for (end = p + 1; *end; end++)
5209 +    if (*end == '<')
5210 +      break;
5211 +
5212 +  if (!streq(end, "<<2]"))
5213 +    return 0;
5214 +
5215 +  c = *end, *end = 0;
5216 +  if (!match_intreg_part(p + 1))
5217 +    ret = 0;
5218 +  *end = c;
5219 +
5220 +  if (ret)
5221 +    {
5222 +      c = *p, *p = 0;
5223 +      regid = avr32_parse_intreg(str);
5224 +      if (regid < 0)
5225 +       ret = 0;
5226 +      *p = c;
5227 +    }
5228 +
5229 +  return ret;
5230 +}
5231 +
5232 +/* The PC_UDISP_W operator may show up as a label or as a pc[disp]
5233 +   expression.  So there's no point in attempting to match this...  */
5234 +#define match_pc_disp  match_anything
5235 +
5236 +static int
5237 +match_sp(char *str)
5238 +{
5239 +  /* SP in any form will do */
5240 +  return avr32_parse_intreg(str) == AVR32_REG_SP;
5241 +}
5242 +
5243 +static int
5244 +match_sp_disp(char *str)
5245 +{
5246 +  int regid, ret = 1;
5247 +  char *p, c;
5248 +
5249 +  for (p = str; *p; p++)
5250 +    if (*p == '[')
5251 +      break;
5252 +
5253 +  /* allow empty displacement, meaning zero */
5254 +  if (p[0] == '[')
5255 +    {
5256 +      char *end;
5257 +      for (end = p + 1; *end; end++) ;
5258 +      if (end[-1] != ']')
5259 +       return 0;
5260 +    }
5261 +
5262 +  c = *p, *p = 0;
5263 +  regid = avr32_parse_intreg(str);
5264 +  if (regid != AVR32_REG_SP)
5265 +    ret = 0;
5266 +
5267 +  *p = c;
5268 +  return ret;
5269 +}
5270 +
5271 +static int
5272 +match_cpno(char *str)
5273 +{
5274 +  if (strncasecmp(str, "cp", 2) != 0)
5275 +    return 0;
5276 +  return 1;
5277 +}
5278 +
5279 +static int
5280 +match_cpreg(char *str)
5281 +{
5282 +  if (strncasecmp(str, "cr", 2) != 0)
5283 +    return 0;
5284 +  return 1;
5285 +}
5286 +
5287 +/* We allow complex expressions, and register names may show up as
5288 +   symbols.  Just make sure immediate expressions are always matched
5289 +   last.  */
5290 +#define match_const            match_anything
5291 +#define match_jmplabel         match_anything
5292 +#define match_number           match_anything
5293 +
5294 +/* Mnemonics that take reglists never accept anything else */
5295 +#define match_reglist8         match_anything
5296 +#define match_reglist9         match_anything
5297 +#define match_reglist16                match_anything
5298 +#define match_reglist_ldm      match_anything
5299 +#define match_reglist_cp8      match_anything
5300 +#define match_reglist_cpd8     match_anything
5301 +
5302 +/* Ditto for retval, jospinc and mcall */
5303 +#define match_retval           match_anything
5304 +#define match_jospinc          match_anything
5305 +#define match_mcall            match_anything
5306 +
5307 +/* COH is used to select between two different syntaxes */
5308 +static int
5309 +match_coh(char *str)
5310 +{
5311 +  return strcasecmp(str, "coh") == 0;
5312 +}
5313 +#if 0
5314 +static int
5315 +match_fpreg(char *str)
5316 +{
5317 +  unsigned long regid;
5318 +  char *endptr;
5319 +
5320 +  if ((str[0] != 'f' && str[0] != 'F')
5321 +      || (str[1] != 'r' && str[1] != 'R'))
5322 +    return 0;
5323 +
5324 +  str += 2;
5325 +  regid = strtoul(str, &endptr, 10);
5326 +  if (!*str || *endptr)
5327 +    return 0;
5328 +
5329 +  return 1;
5330 +}
5331 +#endif
5332 +
5333 +static int
5334 +match_picoreg(char *str)
5335 +{
5336 +  int regid;
5337 +
5338 +  regid = avr32_parse_picoreg(str);
5339 +  if (regid < 0)
5340 +    return 0;
5341 +  return 1;
5342 +}
5343 +
5344 +#define match_pico_reglist_w   match_anything
5345 +#define match_pico_reglist_d   match_anything
5346 +
5347 +static int
5348 +match_pico_in(char *str)
5349 +{
5350 +  unsigned long regid;
5351 +  char *end;
5352 +
5353 +  if (strncasecmp(str, "in", 2) != 0)
5354 +    return 0;
5355 +
5356 +  str += 2;
5357 +  regid = strtoul(str, &end, 10);
5358 +  if (!*str || *end)
5359 +    return 0;
5360 +
5361 +  return 1;
5362 +}
5363 +
5364 +static int
5365 +match_pico_out0(char *str)
5366 +{
5367 +  if (strcasecmp(str, "out0") != 0)
5368 +    return 0;
5369 +  return 1;
5370 +}
5371 +
5372 +static int
5373 +match_pico_out1(char *str)
5374 +{
5375 +  if (strcasecmp(str, "out1") != 0)
5376 +    return 0;
5377 +  return 1;
5378 +}
5379 +
5380 +static int
5381 +match_pico_out2(char *str)
5382 +{
5383 +  if (strcasecmp(str, "out2") != 0)
5384 +    return 0;
5385 +  return 1;
5386 +}
5387 +
5388 +static int
5389 +match_pico_out3(char *str)
5390 +{
5391 +  if (strcasecmp(str, "out3") != 0)
5392 +    return 0;
5393 +  return 1;
5394 +}
5395 +
5396 +static void parse_nothing(const struct avr32_operand *op ATTRIBUTE_UNUSED,
5397 +                         char *str ATTRIBUTE_UNUSED,
5398 +                         int opindex ATTRIBUTE_UNUSED)
5399 +{
5400 +  /* Do nothing (this is used for "match-only" operands like COH) */
5401 +}
5402 +
5403 +static void
5404 +parse_const(const struct avr32_operand *op, char *str,
5405 +           int opindex ATTRIBUTE_UNUSED)
5406 +{
5407 +  expressionS *exp = &current_insn.immediate;
5408 +  expressionS *sym_exp;
5409 +  int slot;
5410 +  char *save;
5411 +
5412 +  pr_debug("parse_const: `%s' (signed: %d, pcrel: %d, align: %d)\n",
5413 +          str, op->is_signed, op->is_pcrel, op->align_order);
5414 +
5415 +  save = input_line_pointer;
5416 +  input_line_pointer = str;
5417 +
5418 +  expression(exp);
5419 +
5420 +  slot = current_insn.next_slot++;
5421 +  current_insn.field_value[slot].align_order = op->align_order;
5422 +  current_insn.pcrel = op->is_pcrel;
5423 +
5424 +  switch (exp->X_op)
5425 +    {
5426 +    case O_illegal:
5427 +      as_bad(_("illegal operand"));
5428 +      break;
5429 +    case O_absent:
5430 +      as_bad(_("missing operand"));
5431 +      break;
5432 +    case O_constant:
5433 +      pr_debug("  -> constant: %ld\n", (long)exp->X_add_number);
5434 +      current_insn.field_value[slot].value = exp->X_add_number;
5435 +      break;
5436 +    case O_uminus:
5437 +      pr_debug("  -> uminus\n");
5438 +      sym_exp = symbol_get_value_expression(exp->X_add_symbol);
5439 +      switch (sym_exp->X_op) {
5440 +      case O_subtract:
5441 +       pr_debug("     -> subtract: switching operands\n");
5442 +       exp->X_op_symbol = sym_exp->X_add_symbol;
5443 +       exp->X_add_symbol = sym_exp->X_op_symbol;
5444 +       exp->X_op = O_subtract;
5445 +       /* TODO: Remove the old X_add_symbol */
5446 +       break;
5447 +      default:
5448 +       as_bad(_("Expression too complex\n"));
5449 +       break;
5450 +      }
5451 +      break;
5452 +#if 0
5453 +    case O_subtract:
5454 +      /* Any expression subtracting a symbol from the current section
5455 +        can be made PC-relative by adding the right offset.  */
5456 +      if (S_GET_SEGMENT(exp->X_op_symbol) == now_seg)
5457 +       current_insn.pcrel = TRUE;
5458 +      pr_debug("  -> subtract: pcrel? %s\n",
5459 +              current_insn.pcrel ? "yes" : "no");
5460 +      /* fall through */
5461 +#endif
5462 +    default:
5463 +      pr_debug("  -> (%p <%d> %p + %d)\n",
5464 +              exp->X_add_symbol, exp->X_op, exp->X_op_symbol,
5465 +              exp->X_add_number);
5466 +      current_insn.field_value[slot].value = 0;
5467 +      break;
5468 +    }
5469 +
5470 +  input_line_pointer = save;
5471 +}
5472 +
5473 +static void
5474 +parse_jmplabel(const struct avr32_operand *op, char *str,
5475 +              int opindex ATTRIBUTE_UNUSED)
5476 +{
5477 +  expressionS *exp = &current_insn.immediate;
5478 +  int slot;
5479 +  char *save;
5480 +
5481 +  pr_debug("parse_jmplabel: `%s' (signed: %d, pcrel: %d, align: %d)\n",
5482 +          str, op->is_signed, op->is_pcrel, op->align_order);
5483 +
5484 +  save = input_line_pointer;
5485 +  input_line_pointer = str;
5486 +
5487 +  expression(exp);
5488 +
5489 +  slot = current_insn.next_slot++;
5490 +  current_insn.field_value[slot].align_order = op->align_order;
5491 +  current_insn.pcrel = TRUE;
5492 +
5493 +  switch (exp->X_op)
5494 +    {
5495 +    case O_illegal:
5496 +      as_bad(_("illegal operand"));
5497 +      break;
5498 +    case O_absent:
5499 +      as_bad(_("missing operand"));
5500 +      break;
5501 +    case O_constant:
5502 +      pr_debug("  -> constant: %ld\n", (long)exp->X_add_number);
5503 +      current_insn.field_value[slot].value = exp->X_add_number;
5504 +      current_insn.pcrel = 0;
5505 +      break;
5506 +    default:
5507 +      pr_debug("  -> (%p <%d> %p + %d)\n",
5508 +              exp->X_add_symbol, exp->X_op, exp->X_op_symbol,
5509 +              exp->X_add_number);
5510 +      current_insn.field_value[slot].value = 0;
5511 +      break;
5512 +    }
5513 +
5514 +  input_line_pointer = save;
5515 +}
5516 +
5517 +static void
5518 +parse_intreg(const struct avr32_operand *op ATTRIBUTE_UNUSED,
5519 +            char *str, int opindex ATTRIBUTE_UNUSED)
5520 +{
5521 +  int regid, slot;
5522 +
5523 +  pr_debug("parse_intreg: `%s'\n", str);
5524 +
5525 +  regid = avr32_parse_intreg(str);
5526 +  assert(regid >= 0);
5527 +
5528 +  slot = current_insn.next_slot++;
5529 +  current_insn.field_value[slot].value = regid;
5530 +  current_insn.field_value[slot].align_order = op->align_order;
5531 +}
5532 +
5533 +static void
5534 +parse_intreg_predec(const struct avr32_operand *op, char *str, int opindex)
5535 +{
5536 +  parse_intreg(op, str + 2, opindex);
5537 +}
5538 +
5539 +static void
5540 +parse_intreg_postinc(const struct avr32_operand *op, char *str, int opindex)
5541 +{
5542 +  char *p, c;
5543 +
5544 +  pr_debug("parse_intreg_postinc: `%s'\n", str);
5545 +
5546 +  for (p = str; *p != '+'; p++) ;
5547 +
5548 +  c = *p, *p = 0;
5549 +  parse_intreg(op, str, opindex);
5550 +  *p = c;
5551 +}
5552 +
5553 +static void
5554 +parse_intreg_shift(const struct avr32_operand *op ATTRIBUTE_UNUSED,
5555 +                  char *str, int opindex ATTRIBUTE_UNUSED)
5556 +{
5557 +  int regid, slot, shift = 0;
5558 +  char *p, c;
5559 +  char shiftop;
5560 +
5561 +  pr_debug("parse Ry<<sa: `%s'\n", str);
5562 +
5563 +  for (p = str; *p; p++)
5564 +    if (*p == '<' || *p == '>')
5565 +      break;
5566 +
5567 +  shiftop = *p;
5568 +
5569 +  c = *p, *p = 0;
5570 +  regid = avr32_parse_intreg(str);
5571 +  assert(regid >= 0);
5572 +  *p = c;
5573 +
5574 +  if (c)
5575 +    {
5576 +      if (p[0] != shiftop || p[1] != shiftop)
5577 +       as_bad(_("expected shift operator in `%s'"), p);
5578 +      else
5579 +       {
5580 +         expressionS exp;
5581 +         char *saved;
5582 +
5583 +         saved = input_line_pointer;
5584 +         input_line_pointer = p + 2;
5585 +         expression(&exp);
5586 +         input_line_pointer = saved;
5587 +
5588 +         if (exp.X_op != O_constant)
5589 +           as_bad(_("shift amount must be a numeric constant"));
5590 +         else
5591 +           shift = exp.X_add_number;
5592 +       }
5593 +    }
5594 +
5595 +  slot = current_insn.next_slot++;
5596 +  current_insn.field_value[slot].value = regid;
5597 +  slot = current_insn.next_slot++;
5598 +  current_insn.field_value[slot].value = shift;
5599 +}
5600 +
5601 +/* The match() function selected the right opcode, so it doesn't
5602 +   matter which way we shift any more.  */
5603 +#define parse_intreg_lsl       parse_intreg_shift
5604 +#define parse_intreg_lsr       parse_intreg_shift
5605 +
5606 +static void
5607 +parse_intreg_part(const struct avr32_operand *op, char *str,
5608 +                 int opindex ATTRIBUTE_UNUSED)
5609 +{
5610 +  static const char bparts[] = { 'b', 'l', 'u', 't' };
5611 +  static const char hparts[] = { 'b', 't' };
5612 +  unsigned int slot, sel;
5613 +  int regid;
5614 +  char *p, c;
5615 +
5616 +  pr_debug("parse reg:part `%s'\n", str);
5617 +
5618 +  for (p = str; *p; p++)
5619 +    if (*p == ':')
5620 +      break;
5621 +
5622 +  c = *p, *p = 0;
5623 +  regid = avr32_parse_intreg(str);
5624 +  assert(regid >= 0);
5625 +  *p = c;
5626 +
5627 +  assert(c == ':');
5628 +
5629 +  if (op->align_order)
5630 +    {
5631 +      for (sel = 0; sel < sizeof(hparts); sel++)
5632 +       if (TOLOWER(p[1]) == hparts[sel])
5633 +         break;
5634 +
5635 +      if (sel >= sizeof(hparts))
5636 +       {
5637 +         as_bad(_("invalid halfword selector `%c' (must be either b or t)"),
5638 +                p[1]);
5639 +         sel = 0;
5640 +       }
5641 +    }
5642 +  else
5643 +    {
5644 +      for (sel = 0; sel < sizeof(bparts); sel++)
5645 +       if (TOLOWER(p[1]) == bparts[sel])
5646 +         break;
5647 +
5648 +      if (sel >= sizeof(bparts))
5649 +       {
5650 +         as_bad(_("invalid byte selector `%c' (must be one of b,l,u,t)"),
5651 +                p[1]);
5652 +         sel = 0;
5653 +       }
5654 +    }
5655 +
5656 +  slot = current_insn.next_slot++;
5657 +  current_insn.field_value[slot].value = regid;
5658 +  slot = current_insn.next_slot++;
5659 +  current_insn.field_value[slot].value = sel;
5660 +}
5661 +
5662 +/* This is the parser for "Rp[displacement]" expressions.  In addition
5663 +   to the "official" syntax, we accept a label as a replacement for
5664 +   the register expression.  This syntax implies Rp=PC and the
5665 +   displacement is the pc-relative distance to the label.  */
5666 +static void
5667 +parse_intreg_disp(const struct avr32_operand *op, char *str, int opindex)
5668 +{
5669 +  expressionS *exp = &current_insn.immediate;
5670 +  int slot, regid;
5671 +  char *save, *p, c;
5672 +
5673 +  pr_debug("parse_intreg_disp: `%s' (signed: %d, pcrel: %d, align: %d)\n",
5674 +          str, op->is_signed, op->is_pcrel, op->align_order);
5675 +
5676 +  for (p = str; *p; p++)
5677 +    if (*p == '[')
5678 +      break;
5679 +
5680 +  slot = current_insn.next_slot++;
5681 +
5682 +  /* First, check if we have a valid register either before '[' or as
5683 +     the sole expression.  If so, we use the Rp[disp] syntax.  */
5684 +  c = *p, *p = 0;
5685 +  regid = avr32_parse_intreg(str);
5686 +  *p = c;
5687 +
5688 +  if (regid >= 0)
5689 +    {
5690 +      current_insn.field_value[slot].value = regid;
5691 +
5692 +      slot = current_insn.next_slot++;
5693 +      current_insn.field_value[slot].align_order = op->align_order;
5694 +
5695 +      if (c == '[')
5696 +       {
5697 +         save = input_line_pointer;
5698 +         input_line_pointer = p + 1;
5699 +
5700 +         expression(exp);
5701 +
5702 +         if (*input_line_pointer != ']')
5703 +           as_bad(_("junk after displacement expression"));
5704 +
5705 +         input_line_pointer = save;
5706 +
5707 +         switch (exp->X_op)
5708 +           {
5709 +           case O_illegal:
5710 +             as_bad(_("illegal displacement expression"));
5711 +             break;
5712 +           case O_absent:
5713 +             as_bad(_("missing displacement expression"));
5714 +             break;
5715 +           case O_constant:
5716 +             pr_debug("  -> constant: %ld\n", exp->X_add_number);
5717 +             current_insn.field_value[slot].value = exp->X_add_number;
5718 +             break;
5719 +#if 0
5720 +           case O_subtract:
5721 +             if (S_GET_SEGMENT(exp->X_op_symbol) == now_seg)
5722 +               current_insn.pcrel = TRUE;
5723 +             pr_debug("  -> subtract: pcrel? %s\n",
5724 +                      current_insn.pcrel ? "yes" : "no");
5725 +             /* fall through */
5726 +#endif
5727 +           default:
5728 +             pr_debug("  -> (%p <%d> %p + %d)\n",
5729 +                      exp->X_add_symbol, exp->X_op, exp->X_op_symbol,
5730 +                      exp->X_add_number);
5731 +             current_insn.field_value[slot].value = 0;
5732 +           }
5733 +       }
5734 +      else
5735 +       {
5736 +         exp->X_op = O_constant;
5737 +         exp->X_add_number = 0;
5738 +         current_insn.field_value[slot].value = 0;
5739 +       }
5740 +    }
5741 +  else
5742 +    {
5743 +      /* Didn't find a valid register.  Try parsing it as a label.  */
5744 +      current_insn.field_value[slot].value = AVR32_REG_PC;
5745 +      parse_jmplabel(op, str, opindex);
5746 +    }
5747 +}
5748 +
5749 +static void
5750 +parse_intreg_index(const struct avr32_operand *op ATTRIBUTE_UNUSED,
5751 +                  char *str, int opindex ATTRIBUTE_UNUSED)
5752 +{
5753 +  int slot, regid;
5754 +  char *p, *end, c;
5755 +
5756 +  for (p = str; *p; p++)
5757 +    if (*p == '[')
5758 +      break;
5759 +
5760 +  assert(*p);
5761 +
5762 +  c = *p, *p = 0;
5763 +  regid = avr32_parse_intreg(str);
5764 +  assert(regid >= 0);
5765 +  *p = c;
5766 +
5767 +  slot = current_insn.next_slot++;
5768 +  current_insn.field_value[slot].value = regid;
5769 +
5770 +  p++;
5771 +  for (end = p; *end; end++)
5772 +    if (*end == ']' || *end == '<')
5773 +      break;
5774 +
5775 +  assert(*end);
5776 +
5777 +  c = *end, *end = 0;
5778 +  regid = avr32_parse_intreg(p);
5779 +  assert(regid >= 0);
5780 +  *end = c;
5781 +
5782 +  slot = current_insn.next_slot++;
5783 +  current_insn.field_value[slot].value = regid;
5784 +
5785 +  slot = current_insn.next_slot++;
5786 +  current_insn.field_value[slot].value = 0;
5787 +
5788 +  if (*end == '<')
5789 +    {
5790 +      expressionS exp;
5791 +      char *save;
5792 +
5793 +      p = end + 2;
5794 +      for (end = p; *end; end++)
5795 +       if (*end == ']')
5796 +         break;
5797 +
5798 +      assert(*end == ']');
5799 +
5800 +      c = *end, *end = 0;
5801 +      save = input_line_pointer;
5802 +      input_line_pointer = p;
5803 +      expression(&exp);
5804 +
5805 +      if (*input_line_pointer)
5806 +       as_bad(_("junk after shift expression"));
5807 +
5808 +      *end = c;
5809 +      input_line_pointer = save;
5810 +
5811 +      if (exp.X_op == O_constant)
5812 +       current_insn.field_value[slot].value = exp.X_add_number;
5813 +      else
5814 +       as_bad(_("shift expression too complex"));
5815 +    }
5816 +}
5817 +
5818 +static void
5819 +parse_intreg_xindex(const struct avr32_operand *op, char *str, int opindex)
5820 +{
5821 +  int slot, regid;
5822 +  char *p, *end, c;
5823 +
5824 +  for (p = str; *p; p++)
5825 +    if (*p == '[')
5826 +      break;
5827 +
5828 +  assert(*p);
5829 +
5830 +  c = *p, *p = 0;
5831 +  regid = avr32_parse_intreg(str);
5832 +  assert(regid >= 0);
5833 +  *p = c;
5834 +
5835 +  slot = current_insn.next_slot++;
5836 +  current_insn.field_value[slot].value = regid;
5837 +
5838 +  p++;
5839 +  for (end = p; *end; end++)
5840 +    if (*end == '<')
5841 +      break;
5842 +
5843 +  assert(*end);
5844 +
5845 +  c = *end, *end = 0;
5846 +  parse_intreg_part(op, p, opindex);
5847 +  *end = c;
5848 +}
5849 +
5850 +static void
5851 +parse_pc_disp(const struct avr32_operand *op, char *str, int opindex)
5852 +{
5853 +  char *p, c;
5854 +
5855 +  for (p = str; *p; p++)
5856 +    if (*p == '[')
5857 +      break;
5858 +
5859 +  /* The lddpc instruction comes in two different syntax variants:
5860 +       lddpc reg, expression
5861 +       lddpc reg, pc[disp]
5862 +     If the operand contains a '[', we use the second form.  */
5863 +  if (*p)
5864 +    {
5865 +      int regid;
5866 +
5867 +      c = *p, *p = 0;
5868 +      regid = avr32_parse_intreg(str);
5869 +      *p = c;
5870 +      if (regid == AVR32_REG_PC)
5871 +       {
5872 +         char *end;
5873 +
5874 +         for (end = ++p; *end; end++) ;
5875 +         if (*(--end) != ']')
5876 +           as_bad(_("unrecognized form of instruction: `%s'"), str);
5877 +         else
5878 +           {
5879 +             c = *end, *end = 0;
5880 +             parse_const(op, p, opindex);
5881 +             *end = c;
5882 +             current_insn.pcrel = 0;
5883 +           }
5884 +       }
5885 +      else
5886 +       as_bad(_("unrecognized form of instruction: `%s'"), str);
5887 +    }
5888 +  else
5889 +    {
5890 +      parse_jmplabel(op, str, opindex);
5891 +    }
5892 +}
5893 +
5894 +static void parse_sp(const struct avr32_operand *op ATTRIBUTE_UNUSED,
5895 +                    char *str ATTRIBUTE_UNUSED,
5896 +                    int opindex ATTRIBUTE_UNUSED)
5897 +{
5898 +  int slot;
5899 +
5900 +  slot = current_insn.next_slot++;
5901 +  current_insn.field_value[slot].value = AVR32_REG_SP;
5902 +}
5903 +
5904 +static void
5905 +parse_sp_disp(const struct avr32_operand *op, char *str, int opindex)
5906 +{
5907 +  char *p, c;
5908 +
5909 +  for (; *str; str++)
5910 +    if (*str == '[')
5911 +      break;
5912 +
5913 +  assert(*str);
5914 +
5915 +  for (p = ++str; *p; p++)
5916 +    if (*p == ']')
5917 +      break;
5918 +
5919 +  c = *p, *p = 0;
5920 +  parse_const(op, str, opindex);
5921 +  *p = c;
5922 +}
5923 +
5924 +static void
5925 +parse_cpno(const struct avr32_operand *op ATTRIBUTE_UNUSED, char *str,
5926 +          int opindex ATTRIBUTE_UNUSED)
5927 +{
5928 +  int slot;
5929 +
5930 +  str += 2;
5931 +  if (*str == '#')
5932 +    str++;
5933 +  if (*str < '0' || *str > '7' || str[1])
5934 +    as_bad(_("invalid coprocessor `%s'"), str);
5935 +
5936 +  slot = current_insn.next_slot++;
5937 +  current_insn.field_value[slot].value = *str - '0';
5938 +}
5939 +
5940 +static void
5941 +parse_cpreg(const struct avr32_operand *op, char *str,
5942 +           int opindex ATTRIBUTE_UNUSED)
5943 +{
5944 +  unsigned int crid;
5945 +  int slot;
5946 +  char *endptr;
5947 +
5948 +  str += 2;
5949 +  crid = strtoul(str, &endptr, 10);
5950 +  if (*endptr || crid > 15 || crid & ((1 << op->align_order) - 1))
5951 +    as_bad(_("invalid coprocessor register `%s'"), str);
5952 +
5953 +  crid >>= op->align_order;
5954 +
5955 +  slot = current_insn.next_slot++;
5956 +  current_insn.field_value[slot].value = crid;
5957 +}
5958 +
5959 +static void
5960 +parse_number(const struct avr32_operand *op, char *str,
5961 +            int opindex ATTRIBUTE_UNUSED)
5962 +{
5963 +  expressionS exp;
5964 +  int slot;
5965 +  char *save;
5966 +
5967 +  save = input_line_pointer;
5968 +  input_line_pointer = str;
5969 +  expression(&exp);
5970 +  input_line_pointer = save;
5971 +
5972 +  slot = current_insn.next_slot++;
5973 +  current_insn.field_value[slot].align_order = op->align_order;
5974 +
5975 +  if (exp.X_op == O_constant)
5976 +      current_insn.field_value[slot].value = exp.X_add_number;
5977 +  else
5978 +      as_bad(_("invalid numeric expression `%s'"), str);
5979 +}
5980 +
5981 +static void
5982 +parse_reglist8(const struct avr32_operand *op ATTRIBUTE_UNUSED,
5983 +              char *str, int opindex ATTRIBUTE_UNUSED)
5984 +{
5985 +  unsigned long regmask;
5986 +  unsigned long value = 0;
5987 +  int slot;
5988 +  char *tail;
5989 +
5990 +  regmask = avr32_parse_reglist(str, &tail);
5991 +  if (*tail)
5992 +    as_bad(_("invalid register list `%s'"), str);
5993 +  else
5994 +    {
5995 +      if (avr32_make_regmask8(regmask, &value))
5996 +       as_bad(_("register list `%s' doesn't fit"), str);
5997 +    }
5998 +
5999 +  slot = current_insn.next_slot++;
6000 +  current_insn.field_value[slot].value = value;
6001 +}
6002 +
6003 +static int
6004 +parse_reglist_tail(char *str, unsigned long regmask)
6005 +{
6006 +  expressionS exp;
6007 +  char *save, *p, c;
6008 +  int regid;
6009 +
6010 +  for (p = str + 1; *p; p++)
6011 +    if (*p == '=')
6012 +      break;
6013 +
6014 +  if (!*p)
6015 +    {
6016 +      as_bad(_("invalid register list `%s'"), str);
6017 +      return -2;
6018 +    }
6019 +
6020 +  c = *p, *p = 0;
6021 +  regid = avr32_parse_intreg(str);
6022 +  *p = c;
6023 +
6024 +  if (regid != 12)
6025 +    {
6026 +      as_bad(_("invalid register list `%s'"), str);
6027 +      return -2;
6028 +    }
6029 +
6030 +  /* If we have an assignment, we must pop PC and we must _not_
6031 +     pop LR or R12 */
6032 +  if (!(regmask & (1 << AVR32_REG_PC)))
6033 +    {
6034 +      as_bad(_("return value specified for non-return instruction"));
6035 +      return -2;
6036 +    }
6037 +  else if (regmask & ((1 << AVR32_REG_R12) | (1 << AVR32_REG_LR)))
6038 +    {
6039 +      as_bad(_("can't pop LR or R12 when specifying return value"));
6040 +      return -2;
6041 +    }
6042 +
6043 +  save = input_line_pointer;
6044 +  input_line_pointer = p + 1;
6045 +  expression(&exp);
6046 +  input_line_pointer = save;
6047 +
6048 +  if (exp.X_op != O_constant
6049 +      || exp.X_add_number < -1
6050 +      || exp.X_add_number > 1)
6051 +    {
6052 +      as_bad(_("invalid return value `%s'"), str);
6053 +      return -2;
6054 +    }
6055 +
6056 +  return exp.X_add_number;
6057 +}
6058 +
6059 +static void
6060 +parse_reglist9(const struct avr32_operand *op ATTRIBUTE_UNUSED,
6061 +              char *str, int opindex ATTRIBUTE_UNUSED)
6062 +{
6063 +  unsigned long regmask;
6064 +  unsigned long value = 0, kbit = 0;
6065 +  int slot;
6066 +  char *tail;
6067 +
6068 +  regmask = avr32_parse_reglist(str, &tail);
6069 +  /* printf("parsed reglist16: %04lx, tail: `%s'\n", regmask, tail); */
6070 +  if (*tail)
6071 +    {
6072 +      int retval;
6073 +
6074 +      retval = parse_reglist_tail(tail, regmask);
6075 +
6076 +      switch (retval)
6077 +       {
6078 +       case -1:
6079 +         regmask |= 1 << AVR32_REG_LR;
6080 +         break;
6081 +       case 0:
6082 +         break;
6083 +       case 1:
6084 +         regmask |= 1 << AVR32_REG_R12;
6085 +         break;
6086 +       default:
6087 +         break;
6088 +       }
6089 +
6090 +      kbit = 1;
6091 +    }
6092 +
6093 +  if (avr32_make_regmask8(regmask, &value))
6094 +    as_bad(_("register list `%s' doesn't fit"), str);
6095 +
6096 +
6097 +  slot = current_insn.next_slot++;
6098 +  current_insn.field_value[slot].value = (value << 1) | kbit;
6099 +}
6100 +
6101 +static void
6102 +parse_reglist16(const struct avr32_operand *op ATTRIBUTE_UNUSED,
6103 +               char *str, int opindex ATTRIBUTE_UNUSED)
6104 +{
6105 +  unsigned long regmask;
6106 +  int slot;
6107 +  char *tail;
6108 +
6109 +  regmask = avr32_parse_reglist(str, &tail);
6110 +  if (*tail)
6111 +    as_bad(_("invalid register list `%s'"), str);
6112 +
6113 +  slot = current_insn.next_slot++;
6114 +  current_insn.field_value[slot].value = regmask;
6115 +}
6116 +
6117 +static void
6118 +parse_reglist_ldm(const struct avr32_operand *op ATTRIBUTE_UNUSED,
6119 +                 char *str, int opindex ATTRIBUTE_UNUSED)
6120 +{
6121 +  unsigned long regmask;
6122 +  int slot, rp, w_bit = 0;
6123 +  char *tail, *p, c;
6124 +
6125 +  for (p = str; *p && *p != ','; p++)
6126 +    if (*p == '+')
6127 +      break;
6128 +
6129 +  c = *p, *p = 0;
6130 +  rp = avr32_parse_intreg(str);
6131 +  *p = c;
6132 +  if (rp < 0)
6133 +    {
6134 +      as_bad(_("invalid destination register in `%s'"), str);
6135 +      return;
6136 +    }
6137 +
6138 +  if (p[0] == '+' && p[1] == '+')
6139 +    {
6140 +      w_bit = 1;
6141 +      p += 2;
6142 +    }
6143 +
6144 +  if (*p != ',')
6145 +    {
6146 +      as_bad(_("expected `,' after destination register in `%s'"), str);
6147 +      return;
6148 +    }
6149 +
6150 +  str = p + 1;
6151 +  regmask = avr32_parse_reglist(str, &tail);
6152 +  if (*tail)
6153 +    {
6154 +      int retval;
6155 +
6156 +      if (rp != AVR32_REG_SP)
6157 +       {
6158 +         as_bad(_("junk at end of line: `%s'"), tail);
6159 +         return;
6160 +       }
6161 +
6162 +      rp = AVR32_REG_PC;
6163 +
6164 +      retval = parse_reglist_tail(tail, regmask);
6165 +
6166 +      switch (retval)
6167 +       {
6168 +       case -1:
6169 +         regmask |= 1 << AVR32_REG_LR;
6170 +         break;
6171 +       case 0:
6172 +         break;
6173 +       case 1:
6174 +         regmask |= 1 << AVR32_REG_R12;
6175 +         break;
6176 +       default:
6177 +         return;
6178 +       }
6179 +    }
6180 +
6181 +  slot = current_insn.next_slot++;
6182 +  current_insn.field_value[slot].value = rp;
6183 +  slot = current_insn.next_slot++;
6184 +  current_insn.field_value[slot].value = w_bit;
6185 +  slot = current_insn.next_slot++;
6186 +  current_insn.field_value[slot].value = regmask;
6187 +}
6188 +
6189 +static void
6190 +parse_reglist_cp8(const struct avr32_operand *op ATTRIBUTE_UNUSED,
6191 +                 char *str, int opindex ATTRIBUTE_UNUSED)
6192 +{
6193 +  unsigned long regmask;
6194 +  int slot, h_bit = 0;
6195 +  char *tail;
6196 +
6197 +  regmask = avr32_parse_cpreglist(str, &tail);
6198 +  if (*tail)
6199 +    as_bad(_("junk at end of line: `%s'"), tail);
6200 +  else if (regmask & 0xffUL)
6201 +    {
6202 +      if (regmask & 0xff00UL)
6203 +       as_bad(_("register list `%s' doesn't fit"), str);
6204 +      regmask &= 0xff;
6205 +    }
6206 +  else if (regmask & 0xff00UL)
6207 +    {
6208 +      regmask >>= 8;
6209 +      h_bit = 1;
6210 +    }
6211 +  else
6212 +    as_warn(_("register list is empty"));
6213 +
6214 +  slot = current_insn.next_slot++;
6215 +  current_insn.field_value[slot].value = regmask;
6216 +  slot = current_insn.next_slot++;
6217 +  current_insn.field_value[slot].value = h_bit;
6218 +}
6219 +
6220 +static void
6221 +parse_reglist_cpd8(const struct avr32_operand *op ATTRIBUTE_UNUSED,
6222 +                  char *str, int opindex ATTRIBUTE_UNUSED)
6223 +{
6224 +  unsigned long regmask, regmask_d = 0;
6225 +  int slot, i;
6226 +  char *tail;
6227 +
6228 +  regmask = avr32_parse_cpreglist(str, &tail);
6229 +  if (*tail)
6230 +    as_bad(_("junk at end of line: `%s'"), tail);
6231 +
6232 +  for (i = 0; i < 8; i++)
6233 +    {
6234 +      if (regmask & 1)
6235 +       {
6236 +         if (!(regmask & 2))
6237 +           {
6238 +             as_bad(_("register list `%s' doesn't fit"), str);
6239 +             break;
6240 +           }
6241 +         regmask_d |= 1 << i;
6242 +       }
6243 +      else if (regmask & 2)
6244 +       {
6245 +         as_bad(_("register list `%s' doesn't fit"), str);
6246 +         break;
6247 +       }
6248 +
6249 +      regmask >>= 2;
6250 +    }
6251 +
6252 +  slot = current_insn.next_slot++;
6253 +  current_insn.field_value[slot].value = regmask_d;
6254 +}
6255 +
6256 +static void
6257 +parse_retval(const struct avr32_operand *op ATTRIBUTE_UNUSED,
6258 +            char *str, int opindex ATTRIBUTE_UNUSED)
6259 +{
6260 +  int regid, slot;
6261 +
6262 +  regid = avr32_parse_intreg(str);
6263 +  if (regid < 0)
6264 +    {
6265 +      expressionS exp;
6266 +      char *save;
6267 +
6268 +      regid = 0;
6269 +
6270 +      save = input_line_pointer;
6271 +      input_line_pointer = str;
6272 +      expression(&exp);
6273 +      input_line_pointer = save;
6274 +
6275 +      if (exp.X_op != O_constant)
6276 +       as_bad(_("invalid return value `%s'"), str);
6277 +      else
6278 +       switch (exp.X_add_number)
6279 +         {
6280 +         case -1:
6281 +           regid = AVR32_REG_LR;
6282 +           break;
6283 +         case 0:
6284 +           regid = AVR32_REG_SP;
6285 +           break;
6286 +         case 1:
6287 +           regid = AVR32_REG_PC;
6288 +           break;
6289 +         default:
6290 +           as_bad(_("invalid return value `%s'"), str);
6291 +           break;
6292 +         }
6293 +    }
6294 +
6295 +  slot = current_insn.next_slot++;
6296 +  current_insn.field_value[slot].value = regid;
6297 +}
6298 +
6299 +#define parse_mcall parse_intreg_disp
6300 +
6301 +static void
6302 +parse_jospinc(const struct avr32_operand *op ATTRIBUTE_UNUSED,
6303 +             char *str, int opindex ATTRIBUTE_UNUSED)
6304 +{
6305 +  expressionS exp;
6306 +  int slot;
6307 +  char *save;
6308 +
6309 +  save = input_line_pointer;
6310 +  input_line_pointer = str;
6311 +  expression(&exp);
6312 +  input_line_pointer = save;
6313 +
6314 +  slot = current_insn.next_slot++;
6315 +
6316 +  if (exp.X_op == O_constant)
6317 +    {
6318 +      if (exp.X_add_number > 0)
6319 +       exp.X_add_number--;
6320 +      current_insn.field_value[slot].value = exp.X_add_number;
6321 +    }
6322 +  else
6323 +    as_bad(_("invalid numeric expression `%s'"), str);
6324 +}
6325 +
6326 +#define parse_coh              parse_nothing
6327 +#if 0
6328 +static void
6329 +parse_fpreg(const struct avr32_operand *op,
6330 +           char *str, int opindex ATTRIBUTE_UNUSED)
6331 +{
6332 +  unsigned long regid;
6333 +  int slot;
6334 +
6335 +  regid = strtoul(str + 2, NULL, 10);
6336 +
6337 +  if ((regid >= 16) || (regid & ((1 << op->align_order) - 1)))
6338 +    as_bad(_("invalid floating-point register `%s'"), str);
6339 +
6340 +  slot = current_insn.next_slot++;
6341 +  current_insn.field_value[slot].value = regid;
6342 +  current_insn.field_value[slot].align_order = op->align_order;
6343 +}
6344 +#endif
6345 +
6346 +static void
6347 +parse_picoreg(const struct avr32_operand *op,
6348 +             char *str, int opindex ATTRIBUTE_UNUSED)
6349 +{
6350 +  unsigned long regid;
6351 +  int slot;
6352 +
6353 +  regid = avr32_parse_picoreg(str);
6354 +  if (regid & ((1 << op->align_order) - 1))
6355 +    as_bad(_("invalid double-word PiCo register `%s'"), str);
6356 +
6357 +  slot = current_insn.next_slot++;
6358 +  current_insn.field_value[slot].value = regid;
6359 +  current_insn.field_value[slot].align_order = op->align_order;
6360 +}
6361 +
6362 +static void
6363 +parse_pico_reglist_w(const struct avr32_operand *op ATTRIBUTE_UNUSED,
6364 +                    char *str, int opindex ATTRIBUTE_UNUSED)
6365 +{
6366 +  unsigned long regmask;
6367 +  int slot, h_bit = 0;
6368 +  char *tail;
6369 +
6370 +  regmask = avr32_parse_pico_reglist(str, &tail);
6371 +  if (*tail)
6372 +    as_bad(_("junk at end of line: `%s'"), tail);
6373 +
6374 +  if (regmask & 0x00ffUL)
6375 +    {
6376 +      if (regmask & 0xff00UL)
6377 +       as_bad(_("register list `%s' doesn't fit"), str);
6378 +      regmask &= 0x00ffUL;
6379 +    }
6380 +  else if (regmask & 0xff00UL)
6381 +    {
6382 +      regmask >>= 8;
6383 +      h_bit = 1;
6384 +    }
6385 +  else
6386 +    as_warn(_("register list is empty"));
6387 +
6388 +  slot = current_insn.next_slot++;
6389 +  current_insn.field_value[slot].value = regmask;
6390 +  slot = current_insn.next_slot++;
6391 +  current_insn.field_value[slot].value = h_bit;
6392 +}
6393 +
6394 +static void
6395 +parse_pico_reglist_d(const struct avr32_operand *op ATTRIBUTE_UNUSED,
6396 +                    char *str, int opindex ATTRIBUTE_UNUSED)
6397 +{
6398 +  unsigned long regmask, regmask_d = 0;
6399 +  int slot, i;
6400 +  char *tail;
6401 +
6402 +  regmask = avr32_parse_pico_reglist(str, &tail);
6403 +  if (*tail)
6404 +    as_bad(_("junk at end of line: `%s'"), tail);
6405 +
6406 +  for (i = 0; i < 8; i++)
6407 +    {
6408 +      if (regmask & 1)
6409 +       {
6410 +         if (!(regmask & 2))
6411 +           {
6412 +             as_bad(_("register list `%s' doesn't fit"), str);
6413 +             break;
6414 +           }
6415 +         regmask_d |= 1 << i;
6416 +       }
6417 +      else if (regmask & 2)
6418 +       {
6419 +         as_bad(_("register list `%s' doesn't fit"), str);
6420 +         break;
6421 +       }
6422 +
6423 +      regmask >>= 2;
6424 +    }
6425 +
6426 +  slot = current_insn.next_slot++;
6427 +  current_insn.field_value[slot].value = regmask_d;
6428 +}
6429 +
6430 +static void
6431 +parse_pico_in(const struct avr32_operand *op ATTRIBUTE_UNUSED,
6432 +             char *str, int opindex ATTRIBUTE_UNUSED)
6433 +{
6434 +  unsigned long regid;
6435 +  int slot;
6436 +
6437 +  regid = strtoul(str + 2, NULL, 10);
6438 +
6439 +  if (regid >= 12)
6440 +    as_bad(_("invalid PiCo IN register `%s'"), str);
6441 +
6442 +  slot = current_insn.next_slot++;
6443 +  current_insn.field_value[slot].value = regid;
6444 +  current_insn.field_value[slot].align_order = 0;
6445 +}
6446 +
6447 +#define parse_pico_out0                parse_nothing
6448 +#define parse_pico_out1                parse_nothing
6449 +#define parse_pico_out2                parse_nothing
6450 +#define parse_pico_out3                parse_nothing
6451 +
6452 +#define OP(name, sgn, pcrel, align, func) \
6453 +  { AVR32_OPERAND_##name, sgn, pcrel, align, match_##func, parse_##func }
6454 +
6455 +struct avr32_operand avr32_operand_table[] = {
6456 +  OP(INTREG, 0, 0, 0, intreg),
6457 +  OP(INTREG_PREDEC, 0, 0, 0, intreg_predec),
6458 +  OP(INTREG_POSTINC, 0, 0, 0, intreg_postinc),
6459 +  OP(INTREG_LSL, 0, 0, 0, intreg_lsl),
6460 +  OP(INTREG_LSR, 0, 0, 0, intreg_lsr),
6461 +  OP(INTREG_BSEL, 0, 0, 0, intreg_part),
6462 +  OP(INTREG_HSEL, 0, 0, 1, intreg_part),
6463 +  OP(INTREG_SDISP, 1, 0, 0, intreg_disp),
6464 +  OP(INTREG_SDISP_H, 1, 0, 1, intreg_disp),
6465 +  OP(INTREG_SDISP_W, 1, 0, 2, intreg_disp),
6466 +  OP(INTREG_UDISP, 0, 0, 0, intreg_disp),
6467 +  OP(INTREG_UDISP_H, 0, 0, 1, intreg_disp),
6468 +  OP(INTREG_UDISP_W, 0, 0, 2, intreg_disp),
6469 +  OP(INTREG_INDEX, 0, 0, 0, intreg_index),
6470 +  OP(INTREG_XINDEX, 0, 0, 0, intreg_xindex),
6471 +  OP(DWREG, 0, 0, 1, intreg),
6472 +  OP(PC_UDISP_W, 0, 1, 2, pc_disp),
6473 +  OP(SP, 0, 0, 0, sp),
6474 +  OP(SP_UDISP_W, 0, 0, 2, sp_disp),
6475 +  OP(CPNO, 0, 0, 0, cpno),
6476 +  OP(CPREG, 0, 0, 0, cpreg),
6477 +  OP(CPREG_D, 0, 0, 1, cpreg),
6478 +  OP(UNSIGNED_CONST, 0, 0, 0, const),
6479 +  OP(UNSIGNED_CONST_W, 0, 0, 2, const),
6480 +  OP(SIGNED_CONST, 1, 0, 0, const),
6481 +  OP(SIGNED_CONST_W, 1, 0, 2, const),
6482 +  OP(JMPLABEL, 1, 1, 1, jmplabel),
6483 +  OP(UNSIGNED_NUMBER, 0, 0, 0, number),
6484 +  OP(UNSIGNED_NUMBER_W, 0, 0, 2, number),
6485 +  OP(REGLIST8, 0, 0, 0, reglist8),
6486 +  OP(REGLIST9, 0, 0, 0, reglist9),
6487 +  OP(REGLIST16, 0, 0, 0, reglist16),
6488 +  OP(REGLIST_LDM, 0, 0, 0, reglist_ldm),
6489 +  OP(REGLIST_CP8, 0, 0, 0, reglist_cp8),
6490 +  OP(REGLIST_CPD8, 0, 0, 0, reglist_cpd8),
6491 +  OP(RETVAL, 0, 0, 0, retval),
6492 +  OP(MCALL, 1, 0, 2, mcall),
6493 +  OP(JOSPINC, 0, 0, 0, jospinc),
6494 +  OP(COH, 0, 0, 0, coh),
6495 +  OP(PICO_REG_W, 0, 0, 0, picoreg),
6496 +  OP(PICO_REG_D, 0, 0, 1, picoreg),
6497 +  OP(PICO_REGLIST_W, 0, 0, 0, pico_reglist_w),
6498 +  OP(PICO_REGLIST_D, 0, 0, 0, pico_reglist_d),
6499 +  OP(PICO_IN, 0, 0, 0, pico_in),
6500 +  OP(PICO_OUT0, 0, 0, 0, pico_out0),
6501 +  OP(PICO_OUT1, 0, 0, 0, pico_out1),
6502 +  OP(PICO_OUT2, 0, 0, 0, pico_out2),
6503 +  OP(PICO_OUT3, 0, 0, 0, pico_out3),
6504 +};
6505 +
6506 +symbolS *
6507 +md_undefined_symbol (char *name ATTRIBUTE_UNUSED)
6508 +{
6509 +  pr_debug("md_undefined_symbol: %s\n", name);
6510 +  return 0;
6511 +}
6512 +
6513 +struct avr32_relax_type
6514 +{
6515 +  long lower_bound;
6516 +  long upper_bound;
6517 +  unsigned char align;
6518 +  unsigned char length;
6519 +  signed short next;
6520 +};
6521 +
6522 +#define EMPTY { 0, 0, 0, 0, -1 }
6523 +#define C(lower, upper, align, next)                   \
6524 +  { (lower), (upper), (align), 2, AVR32_OPC_##next }
6525 +#define E(lower, upper, align)                         \
6526 +  { (lower), (upper), (align), 4, -1 }
6527 +
6528 +static const struct avr32_relax_type avr32_relax_table[] =
6529 +  {
6530 +    /* 0 */
6531 +    EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY,
6532 +    EMPTY, EMPTY, EMPTY,
6533 +    E(0, 65535, 0), E(0, 65535, 0), E(0, 65535, 0), E(0, 65535, 0),
6534 +    EMPTY,
6535 +    /* 16 */
6536 +    EMPTY, EMPTY, EMPTY, EMPTY,
6537 +
6538 +    C(-256, 254, 1, BREQ2), C(-256, 254, 1, BRNE2),
6539 +    C(-256, 254, 1, BRCC2), C(-256, 254, 1, BRCS2),
6540 +    C(-256, 254, 1, BRGE2), C(-256, 254, 1, BRLT2),
6541 +    C(-256, 254, 1, BRMI2), C(-256, 254, 1, BRPL2),
6542 +    E(-2097152, 2097150, 1), E(-2097152, 2097150, 1),
6543 +    E(-2097152, 2097150, 1), E(-2097152, 2097150, 1),
6544 +    /* 32 */
6545 +    E(-2097152, 2097150, 1), E(-2097152, 2097150, 1),
6546 +    E(-2097152, 2097150, 1), E(-2097152, 2097150, 1),
6547 +    E(-2097152, 2097150, 1), E(-2097152, 2097150, 1),
6548 +    E(-2097152, 2097150, 1), E(-2097152, 2097150, 1),
6549 +    E(-2097152, 2097150, 1), E(-2097152, 2097150, 1),
6550 +    E(-2097152, 2097150, 1), E(-2097152, 2097150, 1),
6551 +
6552 +    EMPTY, EMPTY, EMPTY, EMPTY,
6553 +    /* 48 */
6554 +    EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY,
6555 +    EMPTY, EMPTY, EMPTY,
6556 +
6557 +    C(-32, 31, 0, CP_W3), E(-1048576, 1048575, 0),
6558 +
6559 +    EMPTY, EMPTY, EMPTY,
6560 +    /* 64: csrfcz */
6561 +    EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY,
6562 +    E(0, 65535, 0), E(0, 65535, 0),
6563 +    EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY,
6564 +    E(-32768, 32767, 0),
6565 +    /* 80: LD_SB2 */
6566 +    EMPTY, EMPTY, EMPTY, EMPTY, EMPTY,
6567 +
6568 +    C(0, 7, 0, LD_UB4), E(-32768, 32767, 0),
6569 +
6570 +    EMPTY,
6571 +    EMPTY, EMPTY,
6572 +
6573 +    C(0, 14, 1, LD_SH4), E(-32768, 32767, 0),
6574 +
6575 +    EMPTY, EMPTY, EMPTY,
6576 +
6577 +    C(0, 14, 1, LD_UH4),
6578 +
6579 +    /* 96: LD_UH4 */
6580 +    E(-32768, 32767, 0),
6581 +
6582 +    EMPTY, EMPTY, EMPTY, EMPTY,
6583 +
6584 +    C(0, 124, 2, LD_W4), E(-32768, 32767, 0),
6585 +
6586 +    E(0, 1020, 2),     /* LDC_D1 */
6587 +    EMPTY, EMPTY,
6588 +    E(0, 1020, 2),     /* LDC_W1 */
6589 +    EMPTY, EMPTY,
6590 +    E(0, 16380, 2),    /* LDC0_D */
6591 +    E(0, 16380, 2),    /* LDC0_W */
6592 +    EMPTY,
6593 +
6594 +    /* 112: LDCM_D_PU */
6595 +    EMPTY, EMPTY, EMPTY,
6596 +
6597 +    C(0, 508, 2, LDDPC_EXT), E(-32768, 32767, 0),
6598 +
6599 +    EMPTY,EMPTY, EMPTY,
6600 +    EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY,
6601 +
6602 +    EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY,
6603 +    /* 134: MACHH_W */
6604 +    EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY,
6605 +    E(-131072, 131068, 2),     /* MCALL */
6606 +    E(0, 1020, 2),             /* MFDR */
6607 +    E(0, 1020, 2),             /* MFSR */
6608 +    EMPTY, EMPTY,
6609 +
6610 +    C(-128, 127, 0, MOV2), E(-1048576, 1048575, 0),
6611 +
6612 +    EMPTY, EMPTY, EMPTY,
6613 +    EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY,
6614 +    EMPTY, EMPTY, EMPTY, EMPTY, EMPTY,
6615 +
6616 +    E(-128, 127, 0),           /* MOVEQ2 */
6617 +    E(-128, 127, 0),           /* MOVNE2 */
6618 +    E(-128, 127, 0),           /* MOVCC2 */
6619 +    E(-128, 127, 0),           /* 166: MOVCS2 */
6620 +    E(-128, 127, 0),           /* MOVGE2 */
6621 +    E(-128, 127, 0),           /* MOVLT2 */
6622 +    E(-128, 127, 0),           /* MOVMI2 */
6623 +    E(-128, 127, 0),           /* MOVPL2 */
6624 +    E(-128, 127, 0),           /* MOVLS2 */
6625 +    E(-128, 127, 0),           /* MOVGT2 */
6626 +    E(-128, 127, 0),           /* MOVLE2 */
6627 +    E(-128, 127, 0),           /* MOVHI2 */
6628 +    E(-128, 127, 0),           /* MOVVS2 */
6629 +    E(-128, 127, 0),           /* MOVVC2 */
6630 +    E(-128, 127, 0),           /* MOVQS2 */
6631 +    E(-128, 127, 0),           /* MOVAL2 */
6632 +
6633 +    E(0, 1020, 2),             /* MTDR */
6634 +    E(0, 1020, 2),             /* MTSR */
6635 +    EMPTY,
6636 +    EMPTY,
6637 +    E(-128, 127, 0),           /* MUL3 */
6638 +    EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY,
6639 +    EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY,
6640 +    /* 198: MVCR_W */
6641 +    EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY,
6642 +    E(0, 65535, 0), E(0, 65535, 0),
6643 +    EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY,
6644 +    EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY,
6645 +    EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY,
6646 +    /* 230: PASR_H */
6647 +    EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY,
6648 +    EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY,
6649 +    EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY,
6650 +    EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY,
6651 +    /* 262: PUNPCKSB_H */
6652 +    EMPTY, EMPTY, EMPTY, EMPTY, EMPTY,
6653 +
6654 +    C(-1024, 1022, 1, RCALL2), E(-2097152, 2097150, 1),
6655 +
6656 +    EMPTY,
6657 +    EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY,
6658 +    EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY,
6659 +    EMPTY, EMPTY, EMPTY,
6660 +
6661 +    C(-1024, 1022, 1, BRAL),
6662 +
6663 +    EMPTY, EMPTY, EMPTY,
6664 +    E(-128, 127, 0),           /* RSUB2 */
6665 +    /* 294: SATADD_H */
6666 +    EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY,
6667 +    EMPTY, EMPTY, EMPTY, EMPTY, EMPTY,
6668 +    E(0, 255, 0),              /* SLEEP */
6669 +    EMPTY, EMPTY,
6670 +    EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY,
6671 +    EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY,
6672 +    /* 326: ST_B2 */
6673 +    EMPTY, EMPTY,
6674 +    C(0, 7, 0, ST_B4), E(-32768, 32767, 0),
6675 +    EMPTY, EMPTY, EMPTY, EMPTY,
6676 +    E(-32768, 32767, 0),
6677 +    EMPTY, EMPTY, EMPTY,
6678 +    C(0, 14, 1, ST_H4), E(-32768, 32767, 0),
6679 +    EMPTY, EMPTY,
6680 +    EMPTY,
6681 +    C(0, 60, 2, ST_W4), E(-32768, 32767, 0),
6682 +    E(0, 1020, 2),     /* STC_D1 */
6683 +    EMPTY, EMPTY,
6684 +    E(0, 1020, 2),     /* STC_W1 */
6685 +    EMPTY, EMPTY,
6686 +    E(0, 16380, 2),    /* STC0_D */
6687 +    E(0, 16380, 2),    /* STC0_W */
6688 +
6689 +    EMPTY, EMPTY, EMPTY, EMPTY, EMPTY,
6690 +    /* 358: STDSP */
6691 +    EMPTY, EMPTY,
6692 +    E(0, 1020, 2),     /* STHH_W1 */
6693 +    EMPTY, EMPTY, EMPTY, EMPTY, EMPTY,
6694 +    EMPTY, EMPTY, EMPTY,
6695 +    E(-32768, 32767, 0),
6696 +    C(-512, 508, 2, SUB4),
6697 +    C(-128, 127, 0, SUB4), E(-1048576, 1048576, 0),
6698 +    /* SUB{cond} */
6699 +    E(-128, 127, 0), E(-128, 127, 0), E(-128, 127, 0), E(-128, 127, 0),
6700 +    E(-128, 127, 0), E(-128, 127, 0), E(-128, 127, 0), E(-128, 127, 0),
6701 +    E(-128, 127, 0), E(-128, 127, 0), E(-128, 127, 0), E(-128, 127, 0),
6702 +    E(-128, 127, 0), E(-128, 127, 0), E(-128, 127, 0), E(-128, 127, 0),
6703 +    /* SUBF{cond} */
6704 +    E(-128, 127, 0), E(-128, 127, 0), E(-128, 127, 0), E(-128, 127, 0),
6705 +    E(-128, 127, 0), E(-128, 127, 0), E(-128, 127, 0), E(-128, 127, 0),
6706 +    E(-128, 127, 0), E(-128, 127, 0), E(-128, 127, 0), E(-128, 127, 0),
6707 +    E(-128, 127, 0), E(-128, 127, 0), E(-128, 127, 0), E(-128, 127, 0),
6708 +    EMPTY,
6709 +
6710 +    /* 406: SWAP_B */
6711 +    EMPTY, EMPTY, EMPTY,
6712 +    E(0, 255, 0),      /* SYNC */
6713 +    EMPTY, EMPTY, EMPTY, EMPTY,
6714 +    /* 414: TST */
6715 +    EMPTY, EMPTY, E(-65536, 65535, 2), E(-65536, 65535, 2), E(-65536, 65535, 2), EMPTY, EMPTY, EMPTY,
6716 +    /* 422: RSUB{cond} */
6717 +    E(-128, 127, 0), E(-128, 127, 0), E(-128, 127, 0), E(-128, 127, 0),
6718 +    E(-128, 127, 0), E(-128, 127, 0), E(-128, 127, 0), E(-128, 127, 0),
6719 +    E(-128, 127, 0), E(-128, 127, 0), E(-128, 127, 0), E(-128, 127, 0),
6720 +    E(-128, 127, 0), E(-128, 127, 0), E(-128, 127, 0), E(-128, 127, 0),
6721 +    /* 436: ADD{cond} */
6722 +    EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY,
6723 +    EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY,
6724 +    /* 454: SUB{cond} */
6725 +    EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY,
6726 +    EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY,
6727 +    /* 472: AND{cond} */
6728 +    EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY,
6729 +    EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY,
6730 +    /* 486: OR{cond} */
6731 +    EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY,
6732 +    EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY,
6733 +    /* 502: EOR{cond} */
6734 +    EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY,
6735 +    EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY,
6736 +    /* 518: LD.w{cond} */
6737 +    EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY,
6738 +    EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY,
6739 +    /* 534: LD.sh{cond} */
6740 +    EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY,
6741 +    EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY,
6742 +    /* 550: LD.uh{cond} */
6743 +    EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY,
6744 +    EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY,
6745 +    /* 566: LD.sb{cond} */
6746 +    EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY,
6747 +    EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY,
6748 +    /* 582: LD.ub{cond} */
6749 +    EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY,
6750 +    EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY,
6751 +    /* 596: ST.w{cond} */
6752 +    EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY,
6753 +    EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY,
6754 +    /* 614: ST.h{cond} */
6755 +    EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY,
6756 +    EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY,
6757 +    /* 630: ST.b{cond} */
6758 +    EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY,
6759 +    EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY,
6760 +    /* 646: movh */
6761 +    E(0, 65535, 0), EMPTY, EMPTY,
6762 +  /* 649: fmac.s */
6763 +  EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY,
6764 +  EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY,
6765 +  };
6766 +
6767 +#undef E
6768 +#undef C
6769 +#undef EMPTY
6770 +
6771 +#define AVR32_RS_NONE (-1)
6772 +
6773 +#define avr32_rs_size(state) (avr32_relax_table[(state)].length)
6774 +#define avr32_rs_align(state) (avr32_relax_table[(state)].align)
6775 +#define relax_more(state) (avr32_relax_table[(state)].next)
6776 +
6777 +#define opc_initial_substate(opc) ((opc)->id)
6778 +
6779 +static int need_relax(int subtype, offsetT distance)
6780 +{
6781 +  offsetT upper_bound, lower_bound;
6782 +
6783 +  upper_bound = avr32_relax_table[subtype].upper_bound;
6784 +  lower_bound = avr32_relax_table[subtype].lower_bound;
6785 +
6786 +  if (distance & ((1 << avr32_rs_align(subtype)) - 1))
6787 +    return 1;
6788 +  if ((distance > upper_bound) || (distance < lower_bound))
6789 +    return 1;
6790 +
6791 +  return 0;
6792 +}
6793 +
6794 +enum {
6795 +  LDA_SUBTYPE_MOV1,
6796 +  LDA_SUBTYPE_MOV2,
6797 +  LDA_SUBTYPE_SUB,
6798 +  LDA_SUBTYPE_LDDPC,
6799 +  LDA_SUBTYPE_LDW,
6800 +  LDA_SUBTYPE_GOTLOAD,
6801 +  LDA_SUBTYPE_GOTLOAD_LARGE,
6802 +};
6803 +
6804 +enum {
6805 +  CALL_SUBTYPE_RCALL1,
6806 +  CALL_SUBTYPE_RCALL2,
6807 +  CALL_SUBTYPE_MCALL_CP,
6808 +  CALL_SUBTYPE_MCALL_GOT,
6809 +  CALL_SUBTYPE_MCALL_LARGE,
6810 +};
6811 +
6812 +#define LDA_INITIAL_SIZE       (avr32_pic ? 4 : 2)
6813 +#define CALL_INITIAL_SIZE      2
6814 +
6815 +#define need_reloc(sym, seg, pcrel)                                    \
6816 +  (!(S_IS_DEFINED(sym)                                                 \
6817 +     && ((pcrel && S_GET_SEGMENT(sym) == seg)                          \
6818 +        || (!pcrel && S_GET_SEGMENT(sym) == absolute_section)))        \
6819 +   || S_FORCE_RELOC(sym, 1))
6820 +
6821 +/* Return an initial guess of the length by which a fragment must grow to
6822 +   hold a branch to reach its destination.
6823 +   Also updates fr_type/fr_subtype as necessary.
6824 +
6825 +   Called just before doing relaxation.
6826 +   Any symbol that is now undefined will not become defined.
6827 +   The guess for fr_var is ACTUALLY the growth beyond fr_fix.
6828 +   Whatever we do to grow fr_fix or fr_var contributes to our returned value.
6829 +   Although it may not be explicit in the frag, pretend fr_var starts with a
6830 +   0 value.  */
6831 +
6832 +static int
6833 +avr32_default_estimate_size_before_relax (fragS *fragP, segT segment)
6834 +{
6835 +  int growth = 0;
6836 +
6837 +  assert(fragP);
6838 +  assert(fragP->fr_symbol);
6839 +
6840 +  if (fragP->tc_frag_data.force_extended
6841 +      || need_reloc(fragP->fr_symbol, segment, fragP->tc_frag_data.pcrel))
6842 +    {
6843 +      int largest_state = fragP->fr_subtype;
6844 +      while (relax_more(largest_state) != AVR32_RS_NONE)
6845 +       largest_state = relax_more(largest_state);
6846 +      growth = avr32_rs_size(largest_state) - fragP->fr_var;
6847 +    }
6848 +  else
6849 +    {
6850 +      growth = avr32_rs_size(fragP->fr_subtype) - fragP->fr_var;
6851 +    }
6852 +
6853 +  pr_debug("%s:%d: md_estimate_size_before_relax: %d\n",
6854 +          fragP->fr_file, fragP->fr_line, growth);
6855 +
6856 +  return growth;
6857 +}
6858 +
6859 +static int
6860 +avr32_lda_estimate_size_before_relax(fragS *fragP, segT segment ATTRIBUTE_UNUSED)
6861 +{
6862 +  return fragP->fr_var - LDA_INITIAL_SIZE;
6863 +}
6864 +
6865 +static int
6866 +avr32_call_estimate_size_before_relax(fragS *fragP, segT segment ATTRIBUTE_UNUSED)
6867 +{
6868 +  return fragP->fr_var - CALL_INITIAL_SIZE;
6869 +}
6870 +
6871 +static int
6872 +avr32_cpool_estimate_size_before_relax(fragS *fragP,
6873 +                                      segT segment ATTRIBUTE_UNUSED)
6874 +{
6875 +  return fragP->fr_var;
6876 +}
6877 +
6878 +/* This macro may be defined to relax a frag. GAS will call this with the
6879 + * segment, the frag, and the change in size of all previous frags;
6880 + * md_relax_frag should return the change in size of the frag. */
6881 +static long
6882 +avr32_default_relax_frag (segT segment, fragS *fragP, long stretch)
6883 +{
6884 +  int state, next_state;
6885 +  symbolS *symbolP;    /* The target symbol */
6886 +  long growth = 0;
6887 +
6888 +  state = next_state = fragP->fr_subtype;
6889 +
6890 +  symbolP = fragP->fr_symbol;
6891 +
6892 +  if (fragP->tc_frag_data.force_extended
6893 +      || need_reloc(symbolP, segment, fragP->tc_frag_data.pcrel))
6894 +    {
6895 +      /* Symbol must be resolved by the linker. Emit the largest
6896 +        possible opcode. */
6897 +      while (relax_more(next_state) != AVR32_RS_NONE)
6898 +       next_state = relax_more(next_state);
6899 +    }
6900 +  else
6901 +    {
6902 +      addressT address;        /* The address of fragP */
6903 +      addressT target; /* The address of the target symbol */
6904 +      offsetT distance;        /* The distance between the insn and the symbol */
6905 +      fragS *sym_frag;
6906 +
6907 +      address = fragP->fr_address;
6908 +      target = fragP->fr_offset;
6909 +      symbolP = fragP->fr_symbol;
6910 +      sym_frag = symbol_get_frag(symbolP);
6911 +
6912 +      address += fragP->fr_fix - fragP->fr_var;
6913 +      target += S_GET_VALUE(symbolP);
6914 +
6915 +      if (stretch != 0
6916 +         && sym_frag->relax_marker != fragP->relax_marker
6917 +         && S_GET_SEGMENT(symbolP) == segment)
6918 +       /* if it was correctly aligned before, make sure it stays aligned */
6919 +       target += stretch & (~0UL << avr32_rs_align(state));
6920 +
6921 +      if (fragP->tc_frag_data.pcrel)
6922 +       distance = target - (address & (~0UL << avr32_rs_align(state)));
6923 +      else
6924 +       distance = target;
6925 +
6926 +      pr_debug("%s:%d: relax more? 0x%x - 0x%x = 0x%x (%d), align %d\n",
6927 +              fragP->fr_file, fragP->fr_line, target, address,
6928 +              distance, distance, avr32_rs_align(state));
6929 +
6930 +      if (need_relax(state, distance))
6931 +       {
6932 +         if (relax_more(state) != AVR32_RS_NONE)
6933 +           next_state = relax_more(state);
6934 +         pr_debug("%s:%d: relax more %d -> %d (%d - %d, align %d)\n",
6935 +                  fragP->fr_file, fragP->fr_line, state, next_state,
6936 +                  target, address, avr32_rs_align(state));
6937 +       }
6938 +    }
6939 +
6940 +  growth = avr32_rs_size(next_state) - avr32_rs_size(state);
6941 +  fragP->fr_subtype = next_state;
6942 +
6943 +  pr_debug("%s:%d: md_relax_frag: growth=%d, subtype=%d, opc=0x%08lx\n",
6944 +          fragP->fr_file, fragP->fr_line, growth, fragP->fr_subtype,
6945 +          avr32_opc_table[next_state].value);
6946 +
6947 +  return growth;
6948 +}
6949 +
6950 +static long
6951 +avr32_lda_relax_frag(segT segment, fragS *fragP, long stretch)
6952 +{
6953 +  struct cpool *pool= NULL;
6954 +  unsigned int entry = 0;
6955 +  addressT address, target;
6956 +  offsetT distance;
6957 +  symbolS *symbolP;
6958 +  fragS *sym_frag;
6959 +  long old_size, new_size;
6960 +
6961 +  symbolP = fragP->fr_symbol;
6962 +  old_size = fragP->fr_var;
6963 +  if (!avr32_pic)
6964 +    {
6965 +      pool = fragP->tc_frag_data.pool;
6966 +      entry = fragP->tc_frag_data.pool_entry;
6967 +    }
6968 +
6969 +  address = fragP->fr_address;
6970 +  address += fragP->fr_fix - LDA_INITIAL_SIZE;
6971 +
6972 +  if (!S_IS_DEFINED(symbolP) || S_FORCE_RELOC(symbolP, 1))
6973 +    goto relax_max;
6974 +
6975 +  target = fragP->fr_offset;
6976 +  sym_frag = symbol_get_frag(symbolP);
6977 +  target += S_GET_VALUE(symbolP);
6978 +
6979 +  if (sym_frag->relax_marker != fragP->relax_marker
6980 +      && S_GET_SEGMENT(symbolP) == segment)
6981 +    target += stretch;
6982 +
6983 +  distance = target - address;
6984 +
6985 +  pr_debug("lda_relax_frag: target: %d, address: %d, var: %d\n",
6986 +          target, address, fragP->fr_var);
6987 +
6988 +  if (!avr32_pic && S_GET_SEGMENT(symbolP) == absolute_section
6989 +      && target <= 127 && (offsetT)target >= -128)
6990 +    {
6991 +      if (fragP->fr_subtype == LDA_SUBTYPE_LDDPC
6992 +         || fragP->fr_subtype == LDA_SUBTYPE_LDW)
6993 +       pool->literals[entry].refcount--;
6994 +      new_size = 2;
6995 +      fragP->fr_subtype = LDA_SUBTYPE_MOV1;
6996 +    }
6997 +  else if (!avr32_pic && S_GET_SEGMENT(symbolP) == absolute_section
6998 +          && target <= 1048575 && (offsetT)target >= -1048576)
6999 +    {
7000 +      if (fragP->fr_subtype == LDA_SUBTYPE_LDDPC
7001 +         || fragP->fr_subtype == LDA_SUBTYPE_LDW)
7002 +       pool->literals[entry].refcount--;
7003 +      new_size = 4;
7004 +      fragP->fr_subtype = LDA_SUBTYPE_MOV2;
7005 +    }
7006 +  else if (!linkrelax && S_GET_SEGMENT(symbolP) == segment
7007 +          /* the field will be negated, so this is really -(-32768)
7008 +             and -(32767) */
7009 +          && distance <= 32768 && distance >= -32767)
7010 +    {
7011 +      if (!avr32_pic
7012 +         && (fragP->fr_subtype == LDA_SUBTYPE_LDDPC
7013 +             || fragP->fr_subtype == LDA_SUBTYPE_LDW))
7014 +       pool->literals[entry].refcount--;
7015 +      new_size = 4;
7016 +      fragP->fr_subtype = LDA_SUBTYPE_SUB;
7017 +    }
7018 +  else
7019 +    {
7020 +    relax_max:
7021 +      if (avr32_pic)
7022 +       {
7023 +         if (linkrelax)
7024 +           {
7025 +             new_size = 8;
7026 +             fragP->fr_subtype = LDA_SUBTYPE_GOTLOAD_LARGE;
7027 +           }
7028 +         else
7029 +           {
7030 +             new_size = 4;
7031 +             fragP->fr_subtype = LDA_SUBTYPE_GOTLOAD;
7032 +           }
7033 +       }
7034 +      else
7035 +       {
7036 +         if (fragP->fr_subtype != LDA_SUBTYPE_LDDPC
7037 +             && fragP->fr_subtype != LDA_SUBTYPE_LDW)
7038 +           pool->literals[entry].refcount++;
7039 +
7040 +         sym_frag = symbol_get_frag(pool->symbol);
7041 +         target = (sym_frag->fr_address + sym_frag->fr_fix
7042 +                   + pool->padding + pool->literals[entry].offset);
7043 +
7044 +         pr_debug("cpool sym address: 0x%lx\n",
7045 +                  sym_frag->fr_address + sym_frag->fr_fix);
7046 +
7047 +         know(pool->section == segment);
7048 +
7049 +         if (sym_frag->relax_marker != fragP->relax_marker)
7050 +           target += stretch;
7051 +
7052 +         distance = target - address;
7053 +         if (distance <= 508 && distance >= 0)
7054 +           {
7055 +             new_size = 2;
7056 +             fragP->fr_subtype = LDA_SUBTYPE_LDDPC;
7057 +           }
7058 +         else
7059 +           {
7060 +             new_size = 4;
7061 +             fragP->fr_subtype = LDA_SUBTYPE_LDW;
7062 +           }
7063 +
7064 +         pr_debug("lda_relax_frag (cpool): target=0x%lx, address=0x%lx, refcount=%d\n",
7065 +                  target, address, pool->literals[entry].refcount);
7066 +       }
7067 +    }
7068 +
7069 +  fragP->fr_var = new_size;
7070 +
7071 +  pr_debug("%s:%d: lda: relax pass done. subtype: %d, growth: %ld\n",
7072 +          fragP->fr_file, fragP->fr_line,
7073 +          fragP->fr_subtype, new_size - old_size);
7074 +
7075 +  return new_size - old_size;
7076 +}
7077 +
7078 +static long
7079 +avr32_call_relax_frag(segT segment, fragS *fragP, long stretch)
7080 +{
7081 +  struct cpool *pool = NULL;
7082 +  unsigned int entry = 0;
7083 +  addressT address, target;
7084 +  offsetT distance;
7085 +  symbolS *symbolP;
7086 +  fragS *sym_frag;
7087 +  long old_size, new_size;
7088 +
7089 +  symbolP = fragP->fr_symbol;
7090 +  old_size = fragP->fr_var;
7091 +  if (!avr32_pic)
7092 +    {
7093 +      pool = fragP->tc_frag_data.pool;
7094 +      entry = fragP->tc_frag_data.pool_entry;
7095 +    }
7096 +
7097 +  address = fragP->fr_address;
7098 +  address += fragP->fr_fix - CALL_INITIAL_SIZE;
7099 +
7100 +  if (need_reloc(symbolP, segment, 1))
7101 +    {
7102 +      pr_debug("call: must emit reloc\n");
7103 +      goto relax_max;
7104 +    }
7105 +
7106 +  target = fragP->fr_offset;
7107 +  sym_frag = symbol_get_frag(symbolP);
7108 +  target += S_GET_VALUE(symbolP);
7109 +
7110 +  if (sym_frag->relax_marker != fragP->relax_marker
7111 +      && S_GET_SEGMENT(symbolP) == segment)
7112 +    target += stretch;
7113 +
7114 +  distance = target - address;
7115 +
7116 +  if (distance <= 1022 && distance >= -1024)
7117 +    {
7118 +      pr_debug("call: distance is %d, emitting short rcall\n", distance);
7119 +      if (!avr32_pic && fragP->fr_subtype == CALL_SUBTYPE_MCALL_CP)
7120 +       pool->literals[entry].refcount--;
7121 +      new_size = 2;
7122 +      fragP->fr_subtype = CALL_SUBTYPE_RCALL1;
7123 +    }
7124 +  else if (distance <= 2097150 && distance >= -2097152)
7125 +    {
7126 +      pr_debug("call: distance is %d, emitting long rcall\n", distance);
7127 +      if (!avr32_pic && fragP->fr_subtype == CALL_SUBTYPE_MCALL_CP)
7128 +       pool->literals[entry].refcount--;
7129 +      new_size = 4;
7130 +      fragP->fr_subtype = CALL_SUBTYPE_RCALL2;
7131 +    }
7132 +  else
7133 +    {
7134 +      pr_debug("call: distance %d too far, emitting something big\n", distance);
7135 +
7136 +    relax_max:
7137 +      if (avr32_pic)
7138 +       {
7139 +         if (linkrelax)
7140 +           {
7141 +             new_size = 10;
7142 +             fragP->fr_subtype = CALL_SUBTYPE_MCALL_LARGE;
7143 +           }
7144 +         else
7145 +           {
7146 +             new_size = 4;
7147 +             fragP->fr_subtype = CALL_SUBTYPE_MCALL_GOT;
7148 +           }
7149 +       }
7150 +      else
7151 +       {
7152 +         if (fragP->fr_subtype != CALL_SUBTYPE_MCALL_CP)
7153 +           pool->literals[entry].refcount++;
7154 +
7155 +         new_size = 4;
7156 +         fragP->fr_subtype = CALL_SUBTYPE_MCALL_CP;
7157 +       }
7158 +    }
7159 +
7160 +  fragP->fr_var = new_size;
7161 +
7162 +  pr_debug("%s:%d: call: relax pass done, growth: %d, fr_var: %d\n",
7163 +          fragP->fr_file, fragP->fr_line,
7164 +          new_size - old_size, fragP->fr_var);
7165 +
7166 +  return new_size - old_size;
7167 +}
7168 +
7169 +static long
7170 +avr32_cpool_relax_frag(segT segment ATTRIBUTE_UNUSED,
7171 +                      fragS *fragP,
7172 +                      long stretch ATTRIBUTE_UNUSED)
7173 +{
7174 +  struct cpool *pool;
7175 +  addressT address;
7176 +  long old_size, new_size;
7177 +  unsigned int entry;
7178 +
7179 +  pool = fragP->tc_frag_data.pool;
7180 +  address = fragP->fr_address + fragP->fr_fix;
7181 +  old_size = fragP->fr_var;
7182 +  new_size = 0;
7183 +
7184 +  for (entry = 0; entry < pool->next_free_entry; entry++)
7185 +    {
7186 +      if (pool->literals[entry].refcount > 0)
7187 +       {
7188 +         pool->literals[entry].offset = new_size;
7189 +         new_size += 4;
7190 +       }
7191 +    }
7192 +
7193 +  fragP->fr_var = new_size;
7194 +
7195 +  return new_size - old_size;
7196 +}
7197 +
7198 +/* *fragP has been relaxed to its final size, and now needs to have
7199 +   the bytes inside it modified to conform to the new size.
7200 +
7201 +   Called after relaxation is finished.
7202 +   fragP->fr_type == rs_machine_dependent.
7203 +   fragP->fr_subtype is the subtype of what the address relaxed to.  */
7204 +
7205 +static void
7206 +avr32_default_convert_frag (bfd *abfd ATTRIBUTE_UNUSED,
7207 +                           segT segment ATTRIBUTE_UNUSED,
7208 +                           fragS *fragP)
7209 +{
7210 +  const struct avr32_opcode *opc;
7211 +  const struct avr32_ifield *ifield;
7212 +  bfd_reloc_code_real_type r_type;
7213 +  symbolS *symbolP;
7214 +  fixS *fixP;
7215 +  bfd_vma value;
7216 +  int subtype;
7217 +
7218 +  opc = &avr32_opc_table[fragP->fr_subtype];
7219 +  ifield = opc->fields[opc->var_field];
7220 +  symbolP = fragP->fr_symbol;
7221 +  subtype = fragP->fr_subtype;
7222 +  r_type = opc->reloc_type;
7223 +
7224 +  /* Clear the opcode bits and the bits belonging to the relaxed
7225 +     field.  We assume all other fields stay the same.  */
7226 +  value = bfd_getb32(fragP->fr_opcode);
7227 +  value &= ~(opc->mask | ifield->mask);
7228 +
7229 +  /* Insert the new opcode */
7230 +  value |= opc->value;
7231 +  bfd_putb32(value, fragP->fr_opcode);
7232 +
7233 +  fragP->fr_fix += opc->size - fragP->fr_var;
7234 +
7235 +  if (fragP->tc_frag_data.reloc_info != AVR32_OPINFO_NONE)
7236 +    {
7237 +      switch (fragP->tc_frag_data.reloc_info)
7238 +       {
7239 +       case AVR32_OPINFO_HI:
7240 +         r_type = BFD_RELOC_HI16;
7241 +         break;
7242 +       case AVR32_OPINFO_LO:
7243 +         r_type = BFD_RELOC_LO16;
7244 +         break;
7245 +       case AVR32_OPINFO_GOT:
7246 +         switch (r_type)
7247 +           {
7248 +           case BFD_RELOC_AVR32_18W_PCREL:
7249 +             r_type = BFD_RELOC_AVR32_GOT18SW;
7250 +             break;
7251 +           case BFD_RELOC_AVR32_16S:
7252 +             r_type = BFD_RELOC_AVR32_GOT16S;
7253 +             break;
7254 +           default:
7255 +             BAD_CASE(r_type);
7256 +             break;
7257 +           }
7258 +         break;
7259 +       default:
7260 +         BAD_CASE(fragP->tc_frag_data.reloc_info);
7261 +         break;
7262 +       }
7263 +    }
7264 +
7265 +  pr_debug("%s:%d: convert_frag: new %s fixup\n",
7266 +          fragP->fr_file, fragP->fr_line,
7267 +          bfd_get_reloc_code_name(r_type));
7268 +
7269 +#if 1
7270 +  fixP = fix_new_exp(fragP, fragP->fr_fix - opc->size, opc->size,
7271 +                    &fragP->tc_frag_data.exp,
7272 +                    fragP->tc_frag_data.pcrel, r_type);
7273 +#else
7274 +  fixP = fix_new(fragP, fragP->fr_fix - opc->size, opc->size, symbolP,
7275 +                fragP->fr_offset, fragP->tc_frag_data.pcrel, r_type);
7276 +#endif
7277 +
7278 +  /* Revert fix_new brain damage. "dot_value" is the value of PC at
7279 +     the point of the fixup, relative to the frag address.  fix_new()
7280 +     and friends think they are only being called during the assembly
7281 +     pass, not during relaxation or similar, so fx_dot_value, fx_file
7282 +     and fx_line are all initialized to the wrong value.  But we don't
7283 +     know the size of the fixup until now, so we really can't live up
7284 +     to the assumptions these functions make about the target.  What
7285 +     do these functions think the "where" and "frag" argument mean
7286 +     anyway?  */
7287 +  fixP->fx_dot_value = fragP->fr_fix - opc->size;
7288 +  fixP->fx_file = fragP->fr_file;
7289 +  fixP->fx_line = fragP->fr_line;
7290 +
7291 +  fixP->tc_fix_data.ifield = ifield;
7292 +  fixP->tc_fix_data.align = avr32_rs_align(subtype);
7293 +  fixP->tc_fix_data.min = avr32_relax_table[subtype].lower_bound;
7294 +  fixP->tc_fix_data.max = avr32_relax_table[subtype].upper_bound;
7295 +}
7296 +
7297 +static void
7298 +avr32_lda_convert_frag(bfd *abfd ATTRIBUTE_UNUSED,
7299 +                      segT segment ATTRIBUTE_UNUSED,
7300 +                      fragS *fragP)
7301 +{
7302 +  const struct avr32_opcode *opc;
7303 +  const struct avr32_ifield *ifield;
7304 +  bfd_reloc_code_real_type r_type;
7305 +  expressionS exp;
7306 +  struct cpool *pool;
7307 +  fixS *fixP;
7308 +  bfd_vma value;
7309 +  int regid, pcrel = 0, align = 0;
7310 +  char *p;
7311 +
7312 +  r_type = BFD_RELOC_NONE;
7313 +  regid = fragP->tc_frag_data.reloc_info;
7314 +  p = fragP->fr_opcode;
7315 +  exp.X_add_symbol = fragP->fr_symbol;
7316 +  exp.X_add_number = fragP->fr_offset;
7317 +  exp.X_op = O_symbol;
7318 +
7319 +  pr_debug("%s:%d: lda_convert_frag, subtype: %d, fix: %d, var: %d, regid: %d\n",
7320 +          fragP->fr_file, fragP->fr_line,
7321 +          fragP->fr_subtype, fragP->fr_fix, fragP->fr_var, regid);
7322 +
7323 +  switch (fragP->fr_subtype)
7324 +    {
7325 +    case LDA_SUBTYPE_MOV1:
7326 +      opc = &avr32_opc_table[AVR32_OPC_MOV1];
7327 +      opc->fields[0]->insert(opc->fields[0], p, regid);
7328 +      ifield = opc->fields[1];
7329 +      r_type = opc->reloc_type;
7330 +      break;
7331 +    case LDA_SUBTYPE_MOV2:
7332 +      opc = &avr32_opc_table[AVR32_OPC_MOV2];
7333 +      opc->fields[0]->insert(opc->fields[0], p, regid);
7334 +      ifield = opc->fields[1];
7335 +      r_type = opc->reloc_type;
7336 +      break;
7337 +    case LDA_SUBTYPE_SUB:
7338 +      opc = &avr32_opc_table[AVR32_OPC_SUB5];
7339 +      opc->fields[0]->insert(opc->fields[0], p, regid);
7340 +      opc->fields[1]->insert(opc->fields[1], p, AVR32_REG_PC);
7341 +      ifield = opc->fields[2];
7342 +      r_type = BFD_RELOC_AVR32_16N_PCREL;
7343 +
7344 +      /* Pretend that SUB5 isn't a "negated" pcrel expression for now.
7345 +        We'll have to fix it up later when we know whether to
7346 +        generate a reloc for it (in which case the linker will negate
7347 +        it, so we shouldn't). */
7348 +      pcrel = 1;
7349 +      break;
7350 +    case LDA_SUBTYPE_LDDPC:
7351 +      opc = &avr32_opc_table[AVR32_OPC_LDDPC];
7352 +      align = 2;
7353 +      r_type = BFD_RELOC_AVR32_9W_CP;
7354 +      goto cpool_common;
7355 +    case LDA_SUBTYPE_LDW:
7356 +      opc = &avr32_opc_table[AVR32_OPC_LDDPC_EXT];
7357 +      r_type = BFD_RELOC_AVR32_16_CP;
7358 +    cpool_common:
7359 +      opc->fields[0]->insert(opc->fields[0], p, regid);
7360 +      ifield = opc->fields[1];
7361 +      pool = fragP->tc_frag_data.pool;
7362 +      exp.X_add_symbol = pool->symbol;
7363 +      exp.X_add_number = pool->literals[fragP->tc_frag_data.pool_entry].offset;
7364 +      pcrel = 1;
7365 +      break;
7366 +    case LDA_SUBTYPE_GOTLOAD_LARGE:
7367 +      /* ld.w Rd, r6[Rd << 2] (last) */
7368 +      opc = &avr32_opc_table[AVR32_OPC_LD_W5];
7369 +      bfd_putb32(opc->value, p + 4);
7370 +      opc->fields[0]->insert(opc->fields[0], p + 4, regid);
7371 +      opc->fields[1]->insert(opc->fields[1], p + 4, 6);
7372 +      opc->fields[2]->insert(opc->fields[2], p + 4, regid);
7373 +      opc->fields[3]->insert(opc->fields[3], p + 4, 2);
7374 +
7375 +      /* mov Rd, (got_offset / 4) */
7376 +      opc = &avr32_opc_table[AVR32_OPC_MOV2];
7377 +      opc->fields[0]->insert(opc->fields[0], p, regid);
7378 +      ifield = opc->fields[1];
7379 +      r_type = BFD_RELOC_AVR32_LDA_GOT;
7380 +      break;
7381 +    case LDA_SUBTYPE_GOTLOAD:
7382 +      opc = &avr32_opc_table[AVR32_OPC_LD_W4];
7383 +      opc->fields[0]->insert(opc->fields[0], p, regid);
7384 +      opc->fields[1]->insert(opc->fields[1], p, 6);
7385 +      ifield = opc->fields[2];
7386 +      if (r_type == BFD_RELOC_NONE)
7387 +       r_type = BFD_RELOC_AVR32_GOT16S;
7388 +      break;
7389 +    default:
7390 +      BAD_CASE(fragP->fr_subtype);
7391 +    }
7392 +
7393 +  value = bfd_getb32(p);
7394 +  value &= ~(opc->mask | ifield->mask);
7395 +  value |= opc->value;
7396 +  bfd_putb32(value, p);
7397 +
7398 +  fragP->fr_fix += fragP->fr_var - LDA_INITIAL_SIZE;
7399 +
7400 +  if (fragP->fr_next
7401 +      && ((offsetT)(fragP->fr_next->fr_address - fragP->fr_address)
7402 +         != fragP->fr_fix))
7403 +    {
7404 +      fprintf(stderr, "LDA frag: fr_fix is wrong! fragP->fr_var = %ld, r_type = %s\n",
7405 +             fragP->fr_var, bfd_get_reloc_code_name(r_type));
7406 +      abort();
7407 +    }
7408 +
7409 +  fixP = fix_new_exp(fragP, fragP->fr_fix - fragP->fr_var, fragP->fr_var,
7410 +                    &exp, pcrel, r_type);
7411 +
7412 +  /* Revert fix_new brain damage. "dot_value" is the value of PC at
7413 +     the point of the fixup, relative to the frag address.  fix_new()
7414 +     and friends think they are only being called during the assembly
7415 +     pass, not during relaxation or similar, so fx_dot_value, fx_file
7416 +     and fx_line are all initialized to the wrong value.  But we don't
7417 +     know the size of the fixup until now, so we really can't live up
7418 +     to the assumptions these functions make about the target.  What
7419 +     do these functions think the "where" and "frag" argument mean
7420 +     anyway?  */
7421 +  fixP->fx_dot_value = fragP->fr_fix - opc->size;
7422 +  fixP->fx_file = fragP->fr_file;
7423 +  fixP->fx_line = fragP->fr_line;
7424 +
7425 +  fixP->tc_fix_data.ifield = ifield;
7426 +  fixP->tc_fix_data.align = align;
7427 +  /* these are only used if the fixup can actually be resolved */
7428 +  fixP->tc_fix_data.min = -32768;
7429 +  fixP->tc_fix_data.max = 32767;
7430 +}
7431 +
7432 +static void
7433 +avr32_call_convert_frag(bfd *abfd ATTRIBUTE_UNUSED,
7434 +                      segT segment ATTRIBUTE_UNUSED,
7435 +                      fragS *fragP)
7436 +{
7437 +  const struct avr32_opcode *opc = NULL;
7438 +  const struct avr32_ifield *ifield;
7439 +  bfd_reloc_code_real_type r_type;
7440 +  symbolS *symbol;
7441 +  offsetT offset;
7442 +  fixS *fixP;
7443 +  bfd_vma value;
7444 +  int pcrel = 0, align = 0;
7445 +  char *p;
7446 +
7447 +  symbol = fragP->fr_symbol;
7448 +  offset = fragP->fr_offset;
7449 +  r_type = BFD_RELOC_NONE;
7450 +  p = fragP->fr_opcode;
7451 +
7452 +  pr_debug("%s:%d: call_convert_frag, subtype: %d, fix: %d, var: %d\n",
7453 +          fragP->fr_file, fragP->fr_line,
7454 +          fragP->fr_subtype, fragP->fr_fix, fragP->fr_var);
7455 +
7456 +  switch (fragP->fr_subtype)
7457 +    {
7458 +    case CALL_SUBTYPE_RCALL1:
7459 +      opc = &avr32_opc_table[AVR32_OPC_RCALL1];
7460 +      /* fall through */
7461 +    case CALL_SUBTYPE_RCALL2:
7462 +      if (!opc)
7463 +       opc = &avr32_opc_table[AVR32_OPC_RCALL2];
7464 +      ifield = opc->fields[0];
7465 +      r_type = opc->reloc_type;
7466 +      pcrel = 1;
7467 +      align = 1;
7468 +      break;
7469 +    case CALL_SUBTYPE_MCALL_CP:
7470 +      opc = &avr32_opc_table[AVR32_OPC_MCALL];
7471 +      opc->fields[0]->insert(opc->fields[0], p, AVR32_REG_PC);
7472 +      ifield = opc->fields[1];
7473 +      r_type = BFD_RELOC_AVR32_CPCALL;
7474 +      symbol = fragP->tc_frag_data.pool->symbol;
7475 +      offset = fragP->tc_frag_data.pool->literals[fragP->tc_frag_data.pool_entry].offset;
7476 +      assert(fragP->tc_frag_data.pool->literals[fragP->tc_frag_data.pool_entry].refcount > 0);
7477 +      pcrel = 1;
7478 +      align = 2;
7479 +      break;
7480 +    case CALL_SUBTYPE_MCALL_GOT:
7481 +      opc = &avr32_opc_table[AVR32_OPC_MCALL];
7482 +      opc->fields[0]->insert(opc->fields[0], p, 6);
7483 +      ifield = opc->fields[1];
7484 +      r_type = BFD_RELOC_AVR32_GOT18SW;
7485 +      break;
7486 +    case CALL_SUBTYPE_MCALL_LARGE:
7487 +      assert(fragP->fr_var == 10);
7488 +      /* ld.w lr, r6[lr << 2] */
7489 +      opc = &avr32_opc_table[AVR32_OPC_LD_W5];
7490 +      bfd_putb32(opc->value, p + 4);
7491 +      opc->fields[0]->insert(opc->fields[0], p + 4, AVR32_REG_LR);
7492 +      opc->fields[1]->insert(opc->fields[1], p + 4, 6);
7493 +      opc->fields[2]->insert(opc->fields[2], p + 4, AVR32_REG_LR);
7494 +      opc->fields[3]->insert(opc->fields[3], p + 4, 2);
7495 +
7496 +      /* icall lr */
7497 +      opc = &avr32_opc_table[AVR32_OPC_ICALL];
7498 +      bfd_putb16(opc->value >> 16, p + 8);
7499 +      opc->fields[0]->insert(opc->fields[0], p + 8, AVR32_REG_LR);
7500 +
7501 +      /* mov lr, (got_offset / 4) */
7502 +      opc = &avr32_opc_table[AVR32_OPC_MOV2];
7503 +      opc->fields[0]->insert(opc->fields[0], p, AVR32_REG_LR);
7504 +      ifield = opc->fields[1];
7505 +      r_type = BFD_RELOC_AVR32_GOTCALL;
7506 +      break;
7507 +    default:
7508 +      BAD_CASE(fragP->fr_subtype);
7509 +    }
7510 +
7511 +  /* Insert the opcode and clear the variable ifield */
7512 +  value = bfd_getb32(p);
7513 +  value &= ~(opc->mask | ifield->mask);
7514 +  value |= opc->value;
7515 +  bfd_putb32(value, p);
7516 +
7517 +  fragP->fr_fix += fragP->fr_var - CALL_INITIAL_SIZE;
7518 +
7519 +  if (fragP->fr_next
7520 +      && ((offsetT)(fragP->fr_next->fr_address - fragP->fr_address)
7521 +         != fragP->fr_fix))
7522 +    {
7523 +      fprintf(stderr, "%s:%d: fr_fix %lu is wrong! fr_var=%lu, r_type=%s\n",
7524 +             fragP->fr_file, fragP->fr_line,
7525 +             fragP->fr_fix, fragP->fr_var, bfd_get_reloc_code_name(r_type));
7526 +      fprintf(stderr, "fr_fix should be %ld. next frag is %s:%d\n",
7527 +             (offsetT)(fragP->fr_next->fr_address - fragP->fr_address),
7528 +             fragP->fr_next->fr_file, fragP->fr_next->fr_line);
7529 +    }
7530 +
7531 +  fixP = fix_new(fragP, fragP->fr_fix - fragP->fr_var, fragP->fr_var,
7532 +                symbol, offset, pcrel, r_type);
7533 +
7534 +  /* Revert fix_new brain damage. "dot_value" is the value of PC at
7535 +     the point of the fixup, relative to the frag address.  fix_new()
7536 +     and friends think they are only being called during the assembly
7537 +     pass, not during relaxation or similar, so fx_dot_value, fx_file
7538 +     and fx_line are all initialized to the wrong value.  But we don't
7539 +     know the size of the fixup until now, so we really can't live up
7540 +     to the assumptions these functions make about the target.  What
7541 +     do these functions think the "where" and "frag" argument mean
7542 +     anyway?  */
7543 +  fixP->fx_dot_value = fragP->fr_fix - opc->size;
7544 +  fixP->fx_file = fragP->fr_file;
7545 +  fixP->fx_line = fragP->fr_line;
7546 +
7547 +  fixP->tc_fix_data.ifield = ifield;
7548 +  fixP->tc_fix_data.align = align;
7549 +  /* these are only used if the fixup can actually be resolved */
7550 +  fixP->tc_fix_data.min = -2097152;
7551 +  fixP->tc_fix_data.max = 2097150;
7552 +}
7553 +
7554 +static void
7555 +avr32_cpool_convert_frag(bfd *abfd ATTRIBUTE_UNUSED,
7556 +                        segT segment ATTRIBUTE_UNUSED,
7557 +                        fragS *fragP)
7558 +{
7559 +  struct cpool *pool;
7560 +  addressT address;
7561 +  unsigned int entry;
7562 +  char *p;
7563 +  char sym_name[20];
7564 +
7565 +  /* Did we get rid of the frag altogether? */
7566 +  if (!fragP->fr_var)
7567 +    return;
7568 +
7569 +  pool = fragP->tc_frag_data.pool;
7570 +  address = fragP->fr_address + fragP->fr_fix;
7571 +  p = fragP->fr_literal + fragP->fr_fix;
7572 +
7573 +  sprintf(sym_name, "$$cp_\002%x", pool->id);
7574 +  symbol_locate(pool->symbol, sym_name, pool->section, fragP->fr_fix, fragP);
7575 +  symbol_table_insert(pool->symbol);
7576 +
7577 +  for (entry = 0; entry < pool->next_free_entry; entry++)
7578 +    {
7579 +      if (pool->literals[entry].refcount > 0)
7580 +       {
7581 +         fix_new_exp(fragP, fragP->fr_fix, 4, &pool->literals[entry].exp,
7582 +                     FALSE, BFD_RELOC_AVR32_32_CPENT);
7583 +         fragP->fr_fix += 4;
7584 +       }
7585 +    }
7586 +}
7587 +
7588 +static struct avr32_relaxer avr32_default_relaxer = {
7589 +  .estimate_size       = avr32_default_estimate_size_before_relax,
7590 +  .relax_frag          = avr32_default_relax_frag,
7591 +  .convert_frag                = avr32_default_convert_frag,
7592 +};
7593 +static struct avr32_relaxer avr32_lda_relaxer = {
7594 +  .estimate_size       = avr32_lda_estimate_size_before_relax,
7595 +  .relax_frag          = avr32_lda_relax_frag,
7596 +  .convert_frag                = avr32_lda_convert_frag,
7597 +};
7598 +static struct avr32_relaxer avr32_call_relaxer = {
7599 +  .estimate_size       = avr32_call_estimate_size_before_relax,
7600 +  .relax_frag          = avr32_call_relax_frag,
7601 +  .convert_frag                = avr32_call_convert_frag,
7602 +};
7603 +static struct avr32_relaxer avr32_cpool_relaxer = {
7604 +  .estimate_size       = avr32_cpool_estimate_size_before_relax,
7605 +  .relax_frag          = avr32_cpool_relax_frag,
7606 +  .convert_frag                = avr32_cpool_convert_frag,
7607 +};
7608 +
7609 +static void s_cpool(int arg ATTRIBUTE_UNUSED)
7610 +{
7611 +  struct cpool *pool;
7612 +  unsigned int max_size;
7613 +  char *buf;
7614 +
7615 +  pool = find_cpool(now_seg, now_subseg);
7616 +  if (!pool || !pool->symbol || pool->next_free_entry == 0)
7617 +    return;
7618 +
7619 +  /* Make sure the constant pool is properly aligned */
7620 +  frag_align_code(2, 0);
7621 +  if (bfd_get_section_alignment(stdoutput, pool->section) < 2)
7622 +    bfd_set_section_alignment(stdoutput, pool->section, 2);
7623 +
7624 +  /* Assume none of the entries are discarded, and that we need the
7625 +     maximum amount of alignment.  But we're not going to allocate
7626 +     anything up front. */
7627 +  max_size = pool->next_free_entry * 4 + 2;
7628 +  frag_grow(max_size);
7629 +  buf = frag_more(0);
7630 +
7631 +  frag_now->tc_frag_data.relaxer = &avr32_cpool_relaxer;
7632 +  frag_now->tc_frag_data.pool = pool;
7633 +
7634 +  symbol_set_frag(pool->symbol, frag_now);
7635 +
7636 +  /* Assume zero initial size, allowing other relaxers to be
7637 +     optimistic about things.  */
7638 +  frag_var(rs_machine_dependent, max_size, 0,
7639 +          0, pool->symbol, 0, NULL);
7640 +
7641 +  /* Mark the pool as empty.  */
7642 +  pool->used = 1;
7643 +}
7644 +
7645 +/* The location from which a PC relative jump should be calculated,
7646 +   given a PC relative reloc.  */
7647 +
7648 +long
7649 +md_pcrel_from_section (fixS *fixP, segT sec)
7650 +{
7651 +  pr_debug("pcrel_from_section, fx_offset = %d\n", fixP->fx_offset);
7652 +
7653 +  if (fixP->fx_addsy != NULL
7654 +      && (! S_IS_DEFINED (fixP->fx_addsy)
7655 +          || S_GET_SEGMENT (fixP->fx_addsy) != sec
7656 +         || S_FORCE_RELOC(fixP->fx_addsy, 1)))
7657 +    {
7658 +      pr_debug("Unknown pcrel symbol: %s\n", S_GET_NAME(fixP->fx_addsy));
7659 +
7660 +      /* The symbol is undefined (or is defined but not in this section).
7661 +        Let the linker figure it out.  */
7662 +      return 0;
7663 +    }
7664 +
7665 +  pr_debug("pcrel from %x + %x, symbol: %s (%x)\n",
7666 +          fixP->fx_frag->fr_address, fixP->fx_where,
7667 +          fixP->fx_addsy?S_GET_NAME(fixP->fx_addsy):"(null)",
7668 +          fixP->fx_addsy?S_GET_VALUE(fixP->fx_addsy):0);
7669 +
7670 +  return ((fixP->fx_frag->fr_address + fixP->fx_where)
7671 +         & (~0UL << fixP->tc_fix_data.align));
7672 +}
7673 +
7674 +valueT
7675 +md_section_align (segT segment, valueT size)
7676 +{
7677 +  int align = bfd_get_section_alignment (stdoutput, segment);
7678 +  return ((size + (1 << align) - 1) & (-1 << align));
7679 +}
7680 +
7681 +static int syntax_matches(const struct avr32_syntax *syntax,
7682 +                         char *str)
7683 +{
7684 +  int i;
7685 +
7686 +  pr_debug("syntax %d matches `%s'?\n", syntax->id, str);
7687 +
7688 +  if (syntax->nr_operands < 0)
7689 +    {
7690 +      struct avr32_operand *op;
7691 +      int optype;
7692 +
7693 +      for (i = 0; i < (-syntax->nr_operands - 1); i++)
7694 +       {
7695 +         char *p;
7696 +         char c;
7697 +
7698 +         optype = syntax->operand[i];
7699 +         assert(optype < AVR32_NR_OPERANDS);
7700 +         op = &avr32_operand_table[optype];
7701 +
7702 +         for (p = str; *p; p++)
7703 +           if (*p == ',')
7704 +             break;
7705 +
7706 +         if (p == str)
7707 +           return 0;
7708 +
7709 +         c = *p;
7710 +         *p = 0;
7711 +
7712 +         if (!op->match(str))
7713 +           {
7714 +             *p = c;
7715 +             return 0;
7716 +           }
7717 +
7718 +         str = p;
7719 +         *p = c;
7720 +         if (c)
7721 +           str++;
7722 +       }
7723 +
7724 +      optype = syntax->operand[i];
7725 +      assert(optype < AVR32_NR_OPERANDS);
7726 +      op = &avr32_operand_table[optype];
7727 +
7728 +      if (!op->match(str))
7729 +       return 0;
7730 +      return 1;
7731 +    }
7732 +
7733 +  for (i = 0; i < syntax->nr_operands; i++)
7734 +    {
7735 +      struct avr32_operand *op;
7736 +      int optype = syntax->operand[i];
7737 +      char *p;
7738 +      char c;
7739 +
7740 +      assert(optype < AVR32_NR_OPERANDS);
7741 +      op = &avr32_operand_table[optype];
7742 +
7743 +      for (p = str; *p; p++)
7744 +       if (*p == ',')
7745 +         break;
7746 +
7747 +      if (p == str)
7748 +       return 0;
7749 +
7750 +      c = *p;
7751 +      *p = 0;
7752 +
7753 +      if (!op->match(str))
7754 +       {
7755 +         *p = c;
7756 +         return 0;
7757 +       }
7758 +
7759 +      str = p;
7760 +      *p = c;
7761 +      if (c)
7762 +       str++;
7763 +    }
7764 +
7765 +  if (*str == '\0')
7766 +    return 1;
7767 +
7768 +  if ((*str == 'e' || *str == 'E') && !str[1])
7769 +    return 1;
7770 +
7771 +  return 0;
7772 +}
7773 +
7774 +static int parse_operands(char *str)
7775 +{
7776 +  int i;
7777 +
7778 +  if (current_insn.syntax->nr_operands < 0)
7779 +    {
7780 +      int optype;
7781 +      struct avr32_operand *op;
7782 +
7783 +      for (i = 0; i < (-current_insn.syntax->nr_operands - 1); i++)
7784 +       {
7785 +         char *p;
7786 +         char c;
7787 +
7788 +         optype = current_insn.syntax->operand[i];
7789 +         op = &avr32_operand_table[optype];
7790 +
7791 +         for (p = str; *p; p++)
7792 +           if (*p == ',')
7793 +             break;
7794 +
7795 +         assert(p != str);
7796 +
7797 +         c = *p, *p = 0;
7798 +         op->parse(op, str, i);
7799 +         *p = c;
7800 +
7801 +         str = p;
7802 +         if (c) str++;
7803 +       }
7804 +
7805 +      /* give the rest of the line to the last operand */
7806 +      optype = current_insn.syntax->operand[i];
7807 +      op = &avr32_operand_table[optype];
7808 +      op->parse(op, str, i);
7809 +    }
7810 +  else
7811 +    {
7812 +      for (i = 0; i < current_insn.syntax->nr_operands; i++)
7813 +       {
7814 +         int optype = current_insn.syntax->operand[i];
7815 +         struct avr32_operand *op = &avr32_operand_table[optype];
7816 +         char *p;
7817 +         char c;
7818 +
7819 +         skip_whitespace(str);
7820 +
7821 +         for (p = str; *p; p++)
7822 +           if (*p == ',')
7823 +             break;
7824 +
7825 +         assert(p != str);
7826 +
7827 +         c = *p, *p = 0;
7828 +         op->parse(op, str, i);
7829 +         *p = c;
7830 +
7831 +         str = p;
7832 +         if (c) str++;
7833 +       }
7834 +
7835 +      if (*str == 'E' || *str == 'e')
7836 +       current_insn.force_extended = 1;
7837 +    }
7838 +
7839 +  return 0;
7840 +}
7841 +
7842 +static const char *
7843 +finish_insn(const struct avr32_opcode *opc)
7844 +{
7845 +  expressionS *exp = &current_insn.immediate;
7846 +  unsigned int i;
7847 +  int will_relax = 0;
7848 +  char *buf;
7849 +
7850 +  assert(current_insn.next_slot == opc->nr_fields);
7851 +
7852 +  pr_debug("%s:%d: finish_insn: trying opcode %d\n",
7853 +          frag_now->fr_file, frag_now->fr_line, opc->id);
7854 +
7855 +  /* Go through the relaxation stage for all instructions that can
7856 +     possibly take a symbolic immediate.  The relax code will take
7857 +     care of range checking and alignment.  */
7858 +  if (opc->var_field != -1)
7859 +    {
7860 +      int substate, largest_substate;
7861 +      symbolS *sym;
7862 +      offsetT off;
7863 +
7864 +      will_relax = 1;
7865 +      substate = largest_substate = opc_initial_substate(opc);
7866 +
7867 +      while (relax_more(largest_substate) != AVR32_RS_NONE)
7868 +       largest_substate = relax_more(largest_substate);
7869 +
7870 +      pr_debug("will relax. initial substate: %d (size %d), largest substate: %d (size %d)\n",
7871 +              substate, avr32_rs_size(substate),
7872 +              largest_substate, avr32_rs_size(largest_substate));
7873 +
7874 +      /* make sure we have enough room for the largest possible opcode */
7875 +      frag_grow(avr32_rs_size(largest_substate));
7876 +      buf = frag_more(opc->size);
7877 +
7878 +      dwarf2_emit_insn(opc->size);
7879 +
7880 +      frag_now->tc_frag_data.reloc_info = AVR32_OPINFO_NONE;
7881 +      frag_now->tc_frag_data.pcrel = current_insn.pcrel;
7882 +      frag_now->tc_frag_data.force_extended = current_insn.force_extended;
7883 +      frag_now->tc_frag_data.relaxer = &avr32_default_relaxer;
7884 +
7885 +      if (exp->X_op == O_hi)
7886 +       {
7887 +         frag_now->tc_frag_data.reloc_info = AVR32_OPINFO_HI;
7888 +         exp->X_op = exp->X_md;
7889 +       }
7890 +      else if (exp->X_op == O_lo)
7891 +       {
7892 +         frag_now->tc_frag_data.reloc_info = AVR32_OPINFO_LO;
7893 +         exp->X_op = exp->X_md;
7894 +       }
7895 +      else if (exp->X_op == O_got)
7896 +       {
7897 +         frag_now->tc_frag_data.reloc_info = AVR32_OPINFO_GOT;
7898 +         exp->X_op = O_symbol;
7899 +       }
7900 +
7901 +#if 0
7902 +      if ((opc->reloc_type == BFD_RELOC_AVR32_SUB5)
7903 +         && exp->X_op == O_subtract)
7904 +       {
7905 +         symbolS *tmp;
7906 +         tmp = exp->X_add_symbol;
7907 +         exp->X_add_symbol = exp->X_op_symbol;
7908 +         exp->X_op_symbol = tmp;
7909 +       }
7910 +#endif
7911 +
7912 +      frag_now->tc_frag_data.exp = current_insn.immediate;
7913 +
7914 +      sym = exp->X_add_symbol;
7915 +      off = exp->X_add_number;
7916 +      if (exp->X_op != O_symbol)
7917 +       {
7918 +         sym = make_expr_symbol(exp);
7919 +         off = 0;
7920 +       }
7921 +
7922 +      frag_var(rs_machine_dependent,
7923 +              avr32_rs_size(largest_substate) - opc->size,
7924 +              opc->size,
7925 +              substate, sym, off, buf);
7926 +    }
7927 +  else
7928 +    {
7929 +      assert(avr32_rs_size(opc_initial_substate(opc)) == 0);
7930 +
7931 +      /* Make sure we always have room for another whole word, as the ifield
7932 +        inserters can only write words. */
7933 +      frag_grow(4);
7934 +      buf = frag_more(opc->size);
7935 +      dwarf2_emit_insn(opc->size);
7936 +    }
7937 +
7938 +  assert(!(opc->value & ~opc->mask));
7939 +
7940 +  pr_debug("inserting opcode: 0x%lx\n", opc->value);
7941 +  bfd_putb32(opc->value, buf);
7942 +
7943 +  for (i = 0; i < opc->nr_fields; i++)
7944 +    {
7945 +      const struct avr32_ifield *f = opc->fields[i];
7946 +      const struct avr32_ifield_data *fd = &current_insn.field_value[i];
7947 +
7948 +      pr_debug("inserting field: 0x%lx & 0x%lx\n",
7949 +              fd->value >> fd->align_order, f->mask);
7950 +
7951 +      f->insert(f, buf, fd->value >> fd->align_order);
7952 +    }
7953 +
7954 +  assert(will_relax || !current_insn.immediate.X_add_symbol);
7955 +  return NULL;
7956 +}
7957 +
7958 +static const char *
7959 +finish_alias(const struct avr32_alias *alias)
7960 +{
7961 +  const struct avr32_opcode *opc;
7962 +  struct {
7963 +    unsigned long value;
7964 +    unsigned long align;
7965 +  } mapped_operand[AVR32_MAX_OPERANDS];
7966 +  unsigned int i;
7967 +
7968 +  opc = alias->opc;
7969 +
7970 +  /* Remap the operands from the alias to the real opcode */
7971 +  for (i = 0; i < opc->nr_fields; i++)
7972 +    {
7973 +      if (alias->operand_map[i].is_opindex)
7974 +       {
7975 +         struct avr32_ifield_data *fd;
7976 +         fd = &current_insn.field_value[alias->operand_map[i].value];
7977 +         mapped_operand[i].value = fd->value;
7978 +         mapped_operand[i].align = fd->align_order;
7979 +       }
7980 +      else
7981 +       {
7982 +         mapped_operand[i].value = alias->operand_map[i].value;
7983 +         mapped_operand[i].align = 0;
7984 +       }
7985 +    }
7986 +
7987 +  for (i = 0; i < opc->nr_fields; i++)
7988 +    {
7989 +      current_insn.field_value[i].value = mapped_operand[i].value;
7990 +      if (opc->id == AVR32_OPC_COP)
7991 +       current_insn.field_value[i].align_order = 0;
7992 +      else
7993 +       current_insn.field_value[i].align_order
7994 +         = mapped_operand[i].align;
7995 +    }
7996 +
7997 +  current_insn.next_slot = opc->nr_fields;
7998 +
7999 +  return finish_insn(opc);
8000 +}
8001 +
8002 +static const char *
8003 +finish_lda(const struct avr32_syntax *syntax ATTRIBUTE_UNUSED)
8004 +{
8005 +  expressionS *exp = &current_insn.immediate;
8006 +  relax_substateT initial_subtype;
8007 +  symbolS *sym;
8008 +  offsetT off;
8009 +  int initial_size, max_size;
8010 +  char *buf;
8011 +
8012 +  initial_size = LDA_INITIAL_SIZE;
8013 +
8014 +  if (avr32_pic)
8015 +    {
8016 +      initial_subtype = LDA_SUBTYPE_SUB;
8017 +      if (linkrelax)
8018 +       max_size = 8;
8019 +      else
8020 +       max_size = 4;
8021 +    }
8022 +  else
8023 +    {
8024 +      initial_subtype = LDA_SUBTYPE_MOV1;
8025 +      max_size = 4;
8026 +    }
8027 +
8028 +  frag_grow(max_size);
8029 +  buf = frag_more(initial_size);
8030 +  dwarf2_emit_insn(initial_size);
8031 +
8032 +  if (exp->X_op == O_symbol)
8033 +    {
8034 +      sym = exp->X_add_symbol;
8035 +      off = exp->X_add_number;
8036 +    }
8037 +  else
8038 +    {
8039 +      sym = make_expr_symbol(exp);
8040 +      off = 0;
8041 +    }
8042 +
8043 +  frag_now->tc_frag_data.reloc_info = current_insn.field_value[0].value;
8044 +  frag_now->tc_frag_data.relaxer = &avr32_lda_relaxer;
8045 +
8046 +  if (!avr32_pic)
8047 +    {
8048 +      /* The relaxer will bump the refcount if necessary */
8049 +      frag_now->tc_frag_data.pool
8050 +       = add_to_cpool(exp, &frag_now->tc_frag_data.pool_entry, 0);
8051 +    }
8052 +
8053 +  frag_var(rs_machine_dependent, max_size - initial_size,
8054 +          initial_size, initial_subtype, sym, off, buf);
8055 +
8056 +  return NULL;
8057 +}
8058 +
8059 +static const char *
8060 +finish_call(const struct avr32_syntax *syntax ATTRIBUTE_UNUSED)
8061 +{
8062 +  expressionS *exp = &current_insn.immediate;
8063 +  symbolS *sym;
8064 +  offsetT off;
8065 +  int initial_size, max_size;
8066 +  char *buf;
8067 +
8068 +  initial_size = CALL_INITIAL_SIZE;
8069 +
8070 +  if (avr32_pic)
8071 +    {
8072 +      if (linkrelax)
8073 +       max_size = 10;
8074 +      else
8075 +       max_size = 4;
8076 +    }
8077 +  else
8078 +    max_size = 4;
8079 +
8080 +  frag_grow(max_size);
8081 +  buf = frag_more(initial_size);
8082 +  dwarf2_emit_insn(initial_size);
8083 +
8084 +  frag_now->tc_frag_data.relaxer = &avr32_call_relaxer;
8085 +
8086 +  if (exp->X_op == O_symbol)
8087 +    {
8088 +      sym = exp->X_add_symbol;
8089 +      off = exp->X_add_number;
8090 +    }
8091 +  else
8092 +    {
8093 +      sym = make_expr_symbol(exp);
8094 +      off = 0;
8095 +    }
8096 +
8097 +  if (!avr32_pic)
8098 +    {
8099 +      /* The relaxer will bump the refcount if necessary */
8100 +      frag_now->tc_frag_data.pool
8101 +       = add_to_cpool(exp, &frag_now->tc_frag_data.pool_entry, 0);
8102 +    }
8103 +
8104 +  frag_var(rs_machine_dependent, max_size - initial_size,
8105 +          initial_size, CALL_SUBTYPE_RCALL1, sym, off, buf);
8106 +
8107 +  return NULL;
8108 +}
8109 +
8110 +void
8111 +md_begin (void)
8112 +{
8113 +  unsigned long flags = 0;
8114 +  int i;
8115 +
8116 +  avr32_mnemonic_htab = hash_new();
8117 +
8118 +  if (!avr32_mnemonic_htab)
8119 +    as_fatal(_("virtual memory exhausted"));
8120 +
8121 +  for (i = 0; i < AVR32_NR_MNEMONICS; i++)
8122 +    {
8123 +      hash_insert(avr32_mnemonic_htab, avr32_mnemonic_table[i].name,
8124 +                 (void *)&avr32_mnemonic_table[i]);
8125 +    }
8126 +
8127 +  if (linkrelax)
8128 +    flags |= EF_AVR32_LINKRELAX;
8129 +  if (avr32_pic)
8130 +    flags |= EF_AVR32_PIC;
8131 +
8132 +  bfd_set_private_flags(stdoutput, flags);
8133 +
8134 +#ifdef OPC_CONSISTENCY_CHECK
8135 +  if (sizeof(avr32_operand_table)/sizeof(avr32_operand_table[0])
8136 +      < AVR32_NR_OPERANDS)
8137 +    as_fatal(_("operand table is incomplete"));
8138 +
8139 +  for (i = 0; i < AVR32_NR_OPERANDS; i++)
8140 +    if (avr32_operand_table[i].id != i)
8141 +      as_fatal(_("operand table inconsistency found at index %d\n"), i);
8142 +  pr_debug("%d operands verified\n", AVR32_NR_OPERANDS);
8143 +
8144 +  for (i = 0; i < AVR32_NR_IFIELDS; i++)
8145 +    if (avr32_ifield_table[i].id != i)
8146 +      as_fatal(_("ifield table inconsistency found at index %d\n"), i);
8147 +  pr_debug("%d instruction fields verified\n", AVR32_NR_IFIELDS);
8148 +
8149 +  for (i = 0; i < AVR32_NR_OPCODES; i++)
8150 +    {
8151 +      if (avr32_opc_table[i].id != i)
8152 +       as_fatal(_("opcode table inconsistency found at index %d\n"), i);
8153 +      if ((avr32_opc_table[i].var_field == -1
8154 +          && avr32_relax_table[i].length != 0)
8155 +         || (avr32_opc_table[i].var_field != -1
8156 +             && avr32_relax_table[i].length == 0))
8157 +       as_fatal(_("relax table inconsistency found at index %d\n"), i);
8158 +    }
8159 +  pr_debug("%d opcodes verified\n", AVR32_NR_OPCODES);
8160 +
8161 +  for (i = 0; i < AVR32_NR_SYNTAX; i++)
8162 +    if (avr32_syntax_table[i].id != i)
8163 +      as_fatal(_("syntax table inconsistency found at index %d\n"), i);
8164 +  pr_debug("%d syntax variants verified\n", AVR32_NR_SYNTAX);
8165 +
8166 +  for (i = 0; i < AVR32_NR_ALIAS; i++)
8167 +    if (avr32_alias_table[i].id != i)
8168 +      as_fatal(_("alias table inconsistency found at index %d\n"), i);
8169 +  pr_debug("%d aliases verified\n", AVR32_NR_ALIAS);
8170 +
8171 +  for (i = 0; i < AVR32_NR_MNEMONICS; i++)
8172 +    if (avr32_mnemonic_table[i].id != i)
8173 +      as_fatal(_("mnemonic table inconsistency found at index %d\n"), i);
8174 +  pr_debug("%d mnemonics verified\n", AVR32_NR_MNEMONICS);
8175 +#endif
8176 +}
8177 +
8178 +void
8179 +md_assemble (char *str)
8180 +{
8181 +  struct avr32_mnemonic *mnemonic;
8182 +  char *p, c;
8183 +
8184 +  memset(&current_insn, 0, sizeof(current_insn));
8185 +  current_insn.immediate.X_op = O_constant;
8186 +
8187 +  skip_whitespace(str);
8188 +  for (p = str; *p; p++)
8189 +    if (*p == ' ')
8190 +      break;
8191 +  c = *p;
8192 +  *p = 0;
8193 +
8194 +  mnemonic = hash_find(avr32_mnemonic_htab, str);
8195 +  *p = c;
8196 +  if (c) p++;
8197 +
8198 +  if (mnemonic)
8199 +    {
8200 +      const struct avr32_syntax *syntax;
8201 +
8202 +      for (syntax = mnemonic->syntax; syntax; syntax = syntax->next)
8203 +       {
8204 +         const char *errmsg = NULL;
8205 +
8206 +         if (syntax_matches(syntax, p))
8207 +           {
8208 +             if (!(syntax->isa_flags & avr32_arch->isa_flags))
8209 +               {
8210 +                 as_bad(_("Selected architecture `%s'  does not support `%s'"),
8211 +                        avr32_arch->name, str);
8212 +                 return;
8213 +               }
8214 +
8215 +             current_insn.syntax = syntax;
8216 +             parse_operands(p);
8217 +
8218 +             switch (syntax->type)
8219 +               {
8220 +               case AVR32_PARSER_NORMAL:
8221 +                 errmsg = finish_insn(syntax->u.opc);
8222 +                 break;
8223 +               case AVR32_PARSER_ALIAS:
8224 +                 errmsg = finish_alias(syntax->u.alias);
8225 +                 break;
8226 +               case AVR32_PARSER_LDA:
8227 +                 errmsg = finish_lda(syntax);
8228 +                 break;
8229 +               case AVR32_PARSER_CALL:
8230 +                 errmsg = finish_call(syntax);
8231 +                 break;
8232 +               default:
8233 +                 BAD_CASE(syntax->type);
8234 +                 break;
8235 +               }
8236 +
8237 +             if (errmsg)
8238 +               as_bad("%s in `%s'", errmsg, str);
8239 +
8240 +             return;
8241 +           }
8242 +       }
8243 +
8244 +      as_bad(_("unrecognized form of instruction: `%s'"), str);
8245 +    }
8246 +  else
8247 +    as_bad(_("unrecognized instruction `%s'"), str);
8248 +}
8249 +
8250 +void avr32_cleanup(void)
8251 +{
8252 +  struct cpool *pool;
8253 +
8254 +  /* Emit any constant pools that haven't been explicitly flushed with
8255 +     a .cpool directive. */
8256 +  for (pool = cpool_list; pool; pool = pool->next)
8257 +    {
8258 +      subseg_set(pool->section, pool->sub_section);
8259 +      s_cpool(0);
8260 +    }
8261 +}
8262 +
8263 +/* Handle any PIC-related operands in data allocation pseudo-ops */
8264 +void
8265 +avr32_cons_fix_new (fragS *frag, int off, int size, expressionS *exp)
8266 +{
8267 +  bfd_reloc_code_real_type r_type = BFD_RELOC_UNUSED;
8268 +  int pcrel = 0;
8269 +
8270 +  pr_debug("%s:%u: cons_fix_new, add_sym: %s, op_sym: %s, op: %d, add_num: %d\n",
8271 +          frag->fr_file, frag->fr_line,
8272 +          exp->X_add_symbol?S_GET_NAME(exp->X_add_symbol):"(none)",
8273 +          exp->X_op_symbol?S_GET_NAME(exp->X_op_symbol):"(none)",
8274 +          exp->X_op, exp->X_add_number);
8275 +
8276 +  if (exp->X_op == O_subtract && exp->X_op_symbol)
8277 +    {
8278 +      if (exp->X_op_symbol == GOT_symbol)
8279 +       {
8280 +         if (size != 4)
8281 +           goto bad_size;
8282 +         r_type = BFD_RELOC_AVR32_GOTPC;
8283 +         exp->X_op = O_symbol;
8284 +         exp->X_op_symbol = NULL;
8285 +       }
8286 +    }
8287 +  else if (exp->X_op == O_got)
8288 +    {
8289 +      switch (size)
8290 +       {
8291 +       case 1:
8292 +         r_type = BFD_RELOC_AVR32_GOT8;
8293 +         break;
8294 +       case 2:
8295 +         r_type = BFD_RELOC_AVR32_GOT16;
8296 +         break;
8297 +       case 4:
8298 +         r_type = BFD_RELOC_AVR32_GOT32;
8299 +         break;
8300 +       default:
8301 +         goto bad_size;
8302 +       }
8303 +
8304 +      exp->X_op = O_symbol;
8305 +    }
8306 +
8307 +  if (r_type == BFD_RELOC_UNUSED)
8308 +    switch (size)
8309 +      {
8310 +      case 1:
8311 +       r_type = BFD_RELOC_8;
8312 +       break;
8313 +      case 2:
8314 +       r_type = BFD_RELOC_16;
8315 +       break;
8316 +      case 4:
8317 +       r_type = BFD_RELOC_32;
8318 +       break;
8319 +      default:
8320 +       goto bad_size;
8321 +      }
8322 +  else if (size != 4)
8323 +    {
8324 +    bad_size:
8325 +      as_bad(_("unsupported BFD relocation size %u"), size);
8326 +      r_type = BFD_RELOC_UNUSED;
8327 +    }
8328 +
8329 +  fix_new_exp (frag, off, size, exp, pcrel, r_type);
8330 +}
8331 +
8332 +static void
8333 +avr32_frob_section(bfd *abfd ATTRIBUTE_UNUSED, segT sec,
8334 +                  void *ignore ATTRIBUTE_UNUSED)
8335 +{
8336 +  segment_info_type *seginfo;
8337 +  fixS *fix;
8338 +
8339 +  seginfo = seg_info(sec);
8340 +  if (!seginfo)
8341 +    return;
8342 +
8343 +  for (fix = seginfo->fix_root; fix; fix = fix->fx_next)
8344 +    {
8345 +      if (fix->fx_done)
8346 +       continue;
8347 +
8348 +      if (fix->fx_r_type == BFD_RELOC_AVR32_SUB5
8349 +         && fix->fx_addsy && fix->fx_subsy)
8350 +       {
8351 +         if (S_GET_SEGMENT(fix->fx_addsy) != S_GET_SEGMENT(fix->fx_subsy)
8352 +             || linkrelax)
8353 +           {
8354 +             symbolS *tmp;
8355 +#ifdef DEBUG
8356 +             fprintf(stderr, "Swapping symbols in fixup:\n");
8357 +             print_fixup(fix);
8358 +#endif
8359 +             tmp = fix->fx_addsy;
8360 +             fix->fx_addsy = fix->fx_subsy;
8361 +             fix->fx_subsy = tmp;
8362 +             fix->fx_offset = -fix->fx_offset;
8363 +           }
8364 +       }
8365 +    }
8366 +}
8367 +
8368 +/* We need to look for SUB5 instructions with expressions that will be
8369 +   made PC-relative and switch fx_addsy with fx_subsy.  This has to be
8370 +   done before adjustment or the wrong symbol might be adjusted.
8371 +
8372 +   This applies to fixups that are a result of expressions like -(sym
8373 +   - .) and that will make it all the way to md_apply_fix3().  LDA
8374 +   does the right thing in convert_frag, so we must not convert
8375 +   those. */
8376 +void
8377 +avr32_frob_file(void)
8378 +{
8379 +  /* if (1 || !linkrelax)
8380 +     return; */
8381 +
8382 +  bfd_map_over_sections(stdoutput, avr32_frob_section, NULL);
8383 +}
8384 +
8385 +static bfd_boolean
8386 +convert_to_diff_reloc(fixS *fixP)
8387 +{
8388 +  switch (fixP->fx_r_type)
8389 +    {
8390 +    case BFD_RELOC_32:
8391 +      fixP->fx_r_type = BFD_RELOC_AVR32_DIFF32;
8392 +      break;
8393 +    case BFD_RELOC_16:
8394 +      fixP->fx_r_type = BFD_RELOC_AVR32_DIFF16;
8395 +      break;
8396 +    case BFD_RELOC_8:
8397 +      fixP->fx_r_type = BFD_RELOC_AVR32_DIFF8;
8398 +      break;
8399 +    default:
8400 +      return FALSE;
8401 +    }
8402 +
8403 +  return TRUE;
8404 +}
8405 +
8406 +/* Simplify a fixup.  If possible, the fixup is reduced to a single
8407 +   constant which is written to the output file.  Otherwise, a
8408 +   relocation is generated so that the linker can take care of the
8409 +   rest.
8410 +
8411 +   ELF relocations have certain constraints: They can only take a
8412 +   single symbol and a single addend.  This means that for difference
8413 +   expressions, we _must_ get rid of the fx_subsy symbol somehow.
8414 +
8415 +   The difference between two labels in the same section can be
8416 +   calculated directly unless 'linkrelax' is set, or a relocation is
8417 +   forced.  If so, we must emit a R_AVR32_DIFFxx relocation.  If there
8418 +   are addends involved at this point, we must be especially careful
8419 +   as the relocation must point exactly to the symbol being
8420 +   subtracted.
8421 +
8422 +   When subtracting a symbol defined in the same section as the fixup,
8423 +   we might be able to convert it to a PC-relative expression, unless
8424 +   linkrelax is set. If this is the case, there's no way we can make
8425 +   sure that the difference between the fixup and fx_subsy stays
8426 +   constant.  So for now, we're just going to disallow that.
8427 +   */
8428 +void
8429 +avr32_process_fixup(fixS *fixP, segT this_segment)
8430 +{
8431 +  segT add_symbol_segment = absolute_section;
8432 +  segT sub_symbol_segment = absolute_section;
8433 +  symbolS *fx_addsy, *fx_subsy;
8434 +  offsetT value = 0, fx_offset;
8435 +  bfd_boolean apply = FALSE;
8436 +
8437 +  assert(this_segment != absolute_section);
8438 +
8439 +  if (fixP->fx_r_type >= BFD_RELOC_UNUSED)
8440 +    {
8441 +      as_bad_where(fixP->fx_file, fixP->fx_line,
8442 +                  _("Bad relocation type %d\n"), fixP->fx_r_type);
8443 +      return;
8444 +    }
8445 +
8446 +  /* BFD_RELOC_AVR32_SUB5 fixups have been swapped by avr32_frob_section() */
8447 +  fx_addsy = fixP->fx_addsy;
8448 +  fx_subsy = fixP->fx_subsy;
8449 +  fx_offset = fixP->fx_offset;
8450 +
8451 +  if (fx_addsy)
8452 +    add_symbol_segment = S_GET_SEGMENT(fx_addsy);
8453 +
8454 +  if (fx_subsy)
8455 +    {
8456 +      resolve_symbol_value(fx_subsy);
8457 +      sub_symbol_segment = S_GET_SEGMENT(fx_subsy);
8458 +
8459 +      if (sub_symbol_segment == this_segment
8460 +         && (!linkrelax
8461 +             || S_GET_VALUE(fx_subsy) == (fixP->fx_frag->fr_address
8462 +                                          + fixP->fx_where)))
8463 +       {
8464 +         fixP->fx_pcrel = TRUE;
8465 +         fx_offset += (fixP->fx_frag->fr_address + fixP->fx_where
8466 +                       - S_GET_VALUE(fx_subsy));
8467 +         fx_subsy = NULL;
8468 +       }
8469 +      else if (sub_symbol_segment == absolute_section)
8470 +       {
8471 +         /* The symbol is really a constant.  */
8472 +         fx_offset -= S_GET_VALUE(fx_subsy);
8473 +         fx_subsy = NULL;
8474 +       }
8475 +      else if (SEG_NORMAL(add_symbol_segment)
8476 +              && sub_symbol_segment == add_symbol_segment
8477 +              && (!linkrelax || convert_to_diff_reloc(fixP)))
8478 +       {
8479 +         /* Difference between two labels in the same section.  */
8480 +         if (linkrelax)
8481 +           {
8482 +             /* convert_to_diff() has ensured that the reloc type is
8483 +                either DIFF32, DIFF16 or DIFF8.  */
8484 +             value = (S_GET_VALUE(fx_addsy) + fixP->fx_offset
8485 +                      - S_GET_VALUE(fx_subsy));
8486 +
8487 +             /* Try to convert it to a section symbol if possible  */
8488 +             if (!S_FORCE_RELOC(fx_addsy, 1)
8489 +                 && !(sub_symbol_segment->flags & SEC_THREAD_LOCAL))
8490 +               {
8491 +                 fx_offset = S_GET_VALUE(fx_subsy);
8492 +                 fx_addsy = section_symbol(sub_symbol_segment);
8493 +               }
8494 +             else
8495 +               {
8496 +                 fx_addsy = fx_subsy;
8497 +                 fx_offset = 0;
8498 +               }
8499 +
8500 +             fx_subsy = NULL;
8501 +             apply = TRUE;
8502 +           }
8503 +         else
8504 +           {
8505 +             fx_offset += S_GET_VALUE(fx_addsy);
8506 +             fx_offset -= S_GET_VALUE(fx_subsy);
8507 +             fx_addsy = NULL;
8508 +             fx_subsy = NULL;
8509 +           }
8510 +       }
8511 +      else
8512 +       {
8513 +         as_bad_where(fixP->fx_file, fixP->fx_line,
8514 +                      _("can't resolve `%s' {%s section} - `%s' {%s section}"),
8515 +                      fx_addsy ? S_GET_NAME (fx_addsy) : "0",
8516 +                      segment_name (add_symbol_segment),
8517 +                      S_GET_NAME (fx_subsy),
8518 +                      segment_name (sub_symbol_segment));
8519 +         return;
8520 +       }
8521 +    }
8522 +
8523 +  if (fx_addsy && !TC_FORCE_RELOCATION(fixP))
8524 +    {
8525 +      if (add_symbol_segment == this_segment
8526 +         && fixP->fx_pcrel)
8527 +       {
8528 +         value += S_GET_VALUE(fx_addsy);
8529 +         value -= md_pcrel_from_section(fixP, this_segment);
8530 +         fx_addsy = NULL;
8531 +         fixP->fx_pcrel = FALSE;
8532 +       }
8533 +      else if (add_symbol_segment == absolute_section)
8534 +       {
8535 +         fx_offset += S_GET_VALUE(fixP->fx_addsy);
8536 +         fx_addsy = NULL;
8537 +       }
8538 +    }
8539 +
8540 +  if (!fx_addsy)
8541 +    fixP->fx_done = TRUE;
8542 +
8543 +  if (fixP->fx_pcrel)
8544 +    {
8545 +      if (fx_addsy != NULL
8546 +         && S_IS_DEFINED(fx_addsy)
8547 +         && S_GET_SEGMENT(fx_addsy) != this_segment)
8548 +       value += md_pcrel_from_section(fixP, this_segment);
8549 +
8550 +      switch (fixP->fx_r_type)
8551 +       {
8552 +       case BFD_RELOC_32:
8553 +         fixP->fx_r_type = BFD_RELOC_32_PCREL;
8554 +         break;
8555 +       case BFD_RELOC_16:
8556 +         fixP->fx_r_type = BFD_RELOC_16_PCREL;
8557 +         break;
8558 +       case BFD_RELOC_8:
8559 +         fixP->fx_r_type = BFD_RELOC_8_PCREL;
8560 +         break;
8561 +       case BFD_RELOC_AVR32_SUB5:
8562 +         fixP->fx_r_type = BFD_RELOC_AVR32_16N_PCREL;
8563 +         break;
8564 +       case BFD_RELOC_AVR32_16S:
8565 +         fixP->fx_r_type = BFD_RELOC_AVR32_16B_PCREL;
8566 +         break;
8567 +       case BFD_RELOC_AVR32_14UW:
8568 +         fixP->fx_r_type = BFD_RELOC_AVR32_14UW_PCREL;
8569 +         break;
8570 +       case BFD_RELOC_AVR32_10UW:
8571 +         fixP->fx_r_type = BFD_RELOC_AVR32_10UW_PCREL;
8572 +         break;
8573 +       default:
8574 +         /* Should have been taken care of already */
8575 +         break;
8576 +       }
8577 +    }
8578 +
8579 +  if (fixP->fx_done || apply)
8580 +    {
8581 +      const struct avr32_ifield *ifield;
8582 +      char *buf = fixP->fx_where + fixP->fx_frag->fr_literal;
8583 +
8584 +      if (fixP->fx_done)
8585 +       value += fx_offset;
8586 +
8587 +      /* For hosts with longs bigger than 32-bits make sure that the top
8588 +         bits of a 32-bit negative value read in by the parser are set,
8589 +         so that the correct comparisons are made.  */
8590 +      if (value & 0x80000000)
8591 +        value |= (-1L << 31);
8592 +
8593 +      switch (fixP->fx_r_type)
8594 +       {
8595 +       case BFD_RELOC_32:
8596 +       case BFD_RELOC_16:
8597 +       case BFD_RELOC_8:
8598 +       case BFD_RELOC_AVR32_DIFF32:
8599 +       case BFD_RELOC_AVR32_DIFF16:
8600 +       case BFD_RELOC_AVR32_DIFF8:
8601 +         md_number_to_chars(buf, value, fixP->fx_size);
8602 +         break;
8603 +       case BFD_RELOC_HI16:
8604 +         value >>= 16;
8605 +       case BFD_RELOC_LO16:
8606 +         value &= 0xffff;
8607 +         md_number_to_chars(buf + 2, value, 2);
8608 +         break;
8609 +       case BFD_RELOC_AVR32_16N_PCREL:
8610 +         value = -value;
8611 +         /* fall through */
8612 +       case BFD_RELOC_AVR32_22H_PCREL:
8613 +       case BFD_RELOC_AVR32_18W_PCREL:
8614 +       case BFD_RELOC_AVR32_16B_PCREL:
8615 +       case BFD_RELOC_AVR32_11H_PCREL:
8616 +       case BFD_RELOC_AVR32_9H_PCREL:
8617 +       case BFD_RELOC_AVR32_9UW_PCREL:
8618 +       case BFD_RELOC_AVR32_3U:
8619 +       case BFD_RELOC_AVR32_4UH:
8620 +       case BFD_RELOC_AVR32_6UW:
8621 +       case BFD_RELOC_AVR32_6S:
8622 +       case BFD_RELOC_AVR32_7UW:
8623 +       case BFD_RELOC_AVR32_8S_EXT:
8624 +       case BFD_RELOC_AVR32_8S:
8625 +       case BFD_RELOC_AVR32_10UW:
8626 +       case BFD_RELOC_AVR32_10SW:
8627 +       case BFD_RELOC_AVR32_STHH_W:
8628 +       case BFD_RELOC_AVR32_14UW:
8629 +       case BFD_RELOC_AVR32_16S:
8630 +       case BFD_RELOC_AVR32_16U:
8631 +       case BFD_RELOC_AVR32_21S:
8632 +       case BFD_RELOC_AVR32_SUB5:
8633 +       case BFD_RELOC_AVR32_CPCALL:
8634 +       case BFD_RELOC_AVR32_16_CP:
8635 +       case BFD_RELOC_AVR32_9W_CP:
8636 +       case BFD_RELOC_AVR32_15S:
8637 +         ifield = fixP->tc_fix_data.ifield;
8638 +         pr_debug("insert field: %ld <= %ld <= %ld (align %u)\n",
8639 +                  fixP->tc_fix_data.min, value, fixP->tc_fix_data.max,
8640 +                  fixP->tc_fix_data.align);
8641 +         if (value < fixP->tc_fix_data.min || value > fixP->tc_fix_data.max)
8642 +           as_bad_where(fixP->fx_file, fixP->fx_line,
8643 +                        _("operand out of range (%ld not between %ld and %ld)"),
8644 +                        value, fixP->tc_fix_data.min, fixP->tc_fix_data.max);
8645 +         if (value & ((1 << fixP->tc_fix_data.align) - 1))
8646 +           as_bad_where(fixP->fx_file, fixP->fx_line,
8647 +                        _("misaligned operand (required alignment: %d)"),
8648 +                        1 << fixP->tc_fix_data.align);
8649 +         ifield->insert(ifield, buf, value >> fixP->tc_fix_data.align);
8650 +         break;
8651 +       case BFD_RELOC_AVR32_ALIGN:
8652 +         /* Nothing to do */
8653 +         fixP->fx_done = FALSE;
8654 +         break;
8655 +       default:
8656 +         as_fatal("reloc type %s not handled\n",
8657 +                  bfd_get_reloc_code_name(fixP->fx_r_type));
8658 +       }
8659 +    }
8660 +
8661 +  fixP->fx_addsy = fx_addsy;
8662 +  fixP->fx_subsy = fx_subsy;
8663 +  fixP->fx_offset = fx_offset;
8664 +
8665 +  if (!fixP->fx_done)
8666 +    {
8667 +      if (!fixP->fx_addsy)
8668 +       fixP->fx_addsy = abs_section_sym;
8669 +
8670 +      symbol_mark_used_in_reloc(fixP->fx_addsy);
8671 +      if (fixP->fx_subsy)
8672 +       abort();
8673 +    }
8674 +}
8675 +
8676 +#if 0
8677 +void
8678 +md_apply_fix3 (fixS *fixP, valueT *valP, segT seg)
8679 +{
8680 +  const struct avr32_ifield *ifield;
8681 +  offsetT      value = *valP;
8682 +  char         *buf = fixP->fx_where + fixP->fx_frag->fr_literal;
8683 +  bfd_boolean  apply;
8684 +
8685 +  pr_debug("%s:%u: apply_fix3: r_type=%d value=%lx offset=%lx\n",
8686 +          fixP->fx_file, fixP->fx_line, fixP->fx_r_type, *valP,
8687 +          fixP->fx_offset);
8688 +
8689 +  if (fixP->fx_r_type >= BFD_RELOC_UNUSED)
8690 +    {
8691 +      as_bad_where(fixP->fx_file, fixP->fx_line,
8692 +                  _("Bad relocation type %d\n"), fixP->fx_r_type);
8693 +      return;
8694 +    }
8695 +
8696 +  if (!fixP->fx_addsy && !fixP->fx_subsy)
8697 +    fixP->fx_done = 1;
8698 +
8699 +  if (fixP->fx_pcrel)
8700 +    {
8701 +      if (fixP->fx_addsy != NULL
8702 +         && S_IS_DEFINED(fixP->fx_addsy)
8703 +         && S_GET_SEGMENT(fixP->fx_addsy) != seg)
8704 +       value += md_pcrel_from_section(fixP, seg);
8705 +
8706 +      switch (fixP->fx_r_type)
8707 +       {
8708 +       case BFD_RELOC_32:
8709 +         fixP->fx_r_type = BFD_RELOC_32_PCREL;
8710 +         break;
8711 +       case BFD_RELOC_16:
8712 +       case BFD_RELOC_8:
8713 +         as_bad_where (fixP->fx_file, fixP->fx_line,
8714 +                       _("8- and 16-bit PC-relative relocations not supported"));
8715 +         break;
8716 +       case BFD_RELOC_AVR32_SUB5:
8717 +         fixP->fx_r_type = BFD_RELOC_AVR32_PCREL_SUB5;
8718 +         break;
8719 +       case BFD_RELOC_AVR32_16S:
8720 +         fixP->fx_r_type = BFD_RELOC_AVR32_16_PCREL;
8721 +         break;
8722 +       default:
8723 +         /* Should have been taken care of already */
8724 +         break;
8725 +       }
8726 +    }
8727 +
8728 +  if (fixP->fx_r_type == BFD_RELOC_32
8729 +      && fixP->fx_subsy)
8730 +    {
8731 +      fixP->fx_r_type = BFD_RELOC_AVR32_DIFF32;
8732 +
8733 +      /* Offsets are only allowed if it's a result of adjusting a
8734 +        local symbol into a section-relative offset.
8735 +        tc_fix_adjustable() should prevent any adjustment if there
8736 +        was an offset involved before.  */
8737 +      if (fixP->fx_offset && !symbol_section_p(fixP->fx_addsy))
8738 +       as_bad_where(fixP->fx_file, fixP->fx_line,
8739 +                    _("cannot represent symbol difference with an offset"));
8740 +
8741 +      value = (S_GET_VALUE(fixP->fx_addsy) + fixP->fx_offset
8742 +              - S_GET_VALUE(fixP->fx_subsy));
8743 +
8744 +      /* The difference before any relaxing takes place is written
8745 +        out, and the DIFF32 reloc identifies the address of the first
8746 +        symbol (i.e. the on that's subtracted.)  */
8747 +      *valP = value;
8748 +      fixP->fx_offset -= value;
8749 +      fixP->fx_subsy = NULL;
8750 +
8751 +      md_number_to_chars(buf, value, fixP->fx_size);
8752 +    }
8753 +
8754 +  if (fixP->fx_done)
8755 +    {
8756 +      switch (fixP->fx_r_type)
8757 +       {
8758 +       case BFD_RELOC_8:
8759 +       case BFD_RELOC_16:
8760 +       case BFD_RELOC_32:
8761 +         md_number_to_chars(buf, value, fixP->fx_size);
8762 +         break;
8763 +       case BFD_RELOC_HI16:
8764 +         value >>= 16;
8765 +       case BFD_RELOC_LO16:
8766 +         value &= 0xffff;
8767 +         *valP = value;
8768 +         md_number_to_chars(buf + 2, value, 2);
8769 +         break;
8770 +       case BFD_RELOC_AVR32_PCREL_SUB5:
8771 +         value = -value;
8772 +         /* fall through */
8773 +       case BFD_RELOC_AVR32_9_PCREL:
8774 +       case BFD_RELOC_AVR32_11_PCREL:
8775 +       case BFD_RELOC_AVR32_16_PCREL:
8776 +       case BFD_RELOC_AVR32_18_PCREL:
8777 +       case BFD_RELOC_AVR32_22_PCREL:
8778 +       case BFD_RELOC_AVR32_3U:
8779 +       case BFD_RELOC_AVR32_4UH:
8780 +       case BFD_RELOC_AVR32_6UW:
8781 +       case BFD_RELOC_AVR32_6S:
8782 +       case BFD_RELOC_AVR32_7UW:
8783 +       case BFD_RELOC_AVR32_8S:
8784 +       case BFD_RELOC_AVR32_10UW:
8785 +       case BFD_RELOC_AVR32_10SW:
8786 +       case BFD_RELOC_AVR32_14UW:
8787 +       case BFD_RELOC_AVR32_16S:
8788 +       case BFD_RELOC_AVR32_16U:
8789 +       case BFD_RELOC_AVR32_21S:
8790 +       case BFD_RELOC_AVR32_BRC1:
8791 +       case BFD_RELOC_AVR32_SUB5:
8792 +       case BFD_RELOC_AVR32_CPCALL:
8793 +       case BFD_RELOC_AVR32_16_CP:
8794 +       case BFD_RELOC_AVR32_9_CP:
8795 +       case BFD_RELOC_AVR32_15S:
8796 +         ifield = fixP->tc_fix_data.ifield;
8797 +         pr_debug("insert field: %ld <= %ld <= %ld (align %u)\n",
8798 +                  fixP->tc_fix_data.min, value, fixP->tc_fix_data.max,
8799 +                  fixP->tc_fix_data.align);
8800 +         if (value < fixP->tc_fix_data.min || value > fixP->tc_fix_data.max)
8801 +           as_bad_where(fixP->fx_file, fixP->fx_line,
8802 +                        _("operand out of range (%ld not between %ld and %ld)"),
8803 +                        value, fixP->tc_fix_data.min, fixP->tc_fix_data.max);
8804 +         if (value & ((1 << fixP->tc_fix_data.align) - 1))
8805 +           as_bad_where(fixP->fx_file, fixP->fx_line,
8806 +                        _("misaligned operand (required alignment: %d)"),
8807 +                        1 << fixP->tc_fix_data.align);
8808 +         ifield->insert(ifield, buf, value >> fixP->tc_fix_data.align);
8809 +         break;
8810 +       case BFD_RELOC_AVR32_ALIGN:
8811 +         /* Nothing to do */
8812 +         fixP->fx_done = FALSE;
8813 +         break;
8814 +       default:
8815 +         as_fatal("reloc type %s not handled\n",
8816 +                  bfd_get_reloc_code_name(fixP->fx_r_type));
8817 +       }
8818 +    }
8819 +}
8820 +#endif
8821 +
8822 +arelent *
8823 +tc_gen_reloc (asection *section ATTRIBUTE_UNUSED,
8824 +             fixS *fixp)
8825 +{
8826 +  arelent *reloc;
8827 +  bfd_reloc_code_real_type code;
8828 +
8829 +  reloc = xmalloc (sizeof (arelent));
8830 +
8831 +  reloc->sym_ptr_ptr = xmalloc (sizeof (asymbol *));
8832 +  *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
8833 +  reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
8834 +  reloc->addend = fixp->fx_offset;
8835 +  code = fixp->fx_r_type;
8836 +
8837 +  reloc->howto = bfd_reloc_type_lookup (stdoutput, code);
8838 +
8839 +  if (reloc->howto == NULL)
8840 +    {
8841 +      as_bad_where (fixp->fx_file, fixp->fx_line,
8842 +                   _("cannot represent relocation %s in this object file format"),
8843 +                   bfd_get_reloc_code_name (code));
8844 +      return NULL;
8845 +    }
8846 +
8847 +  return reloc;
8848 +}
8849 +
8850 +bfd_boolean
8851 +avr32_force_reloc(fixS *fixP)
8852 +{
8853 +  if (linkrelax && fixP->fx_addsy
8854 +      && !(S_GET_SEGMENT(fixP->fx_addsy)->flags & SEC_DEBUGGING)
8855 +      && S_GET_SEGMENT(fixP->fx_addsy) != absolute_section)
8856 +    {
8857 +      pr_debug(stderr, "force reloc: addsy=%p, r_type=%d, sec=%s\n",
8858 +              fixP->fx_addsy, fixP->fx_r_type, S_GET_SEGMENT(fixP->fx_addsy)->name);
8859 +      return 1;
8860 +    }
8861 +
8862 +  return generic_force_reloc(fixP);
8863 +}
8864 +
8865 +bfd_boolean
8866 +avr32_fix_adjustable(fixS *fixP)
8867 +{
8868 +  switch (fixP->fx_r_type)
8869 +    {
8870 +      /* GOT relocations can't have addends since BFD treats all
8871 +        references to a given symbol the same. This means that we
8872 +        must avoid section-relative references to local symbols when
8873 +        dealing with these kinds of relocs */
8874 +    case BFD_RELOC_AVR32_GOT32:
8875 +    case BFD_RELOC_AVR32_GOT16:
8876 +    case BFD_RELOC_AVR32_GOT8:
8877 +    case BFD_RELOC_AVR32_GOT21S:
8878 +    case BFD_RELOC_AVR32_GOT18SW:
8879 +    case BFD_RELOC_AVR32_GOT16S:
8880 +    case BFD_RELOC_AVR32_LDA_GOT:
8881 +    case BFD_RELOC_AVR32_GOTCALL:
8882 +      pr_debug("fix not adjustable\n");
8883 +      return 0;
8884 +
8885 +    default:
8886 +      break;
8887 +    }
8888 +
8889 +  return 1;
8890 +}
8891 +
8892 +/* When we want the linker to be able to relax the code, we need to
8893 +   output a reloc for every .align directive requesting an alignment
8894 +   to a four byte boundary or larger.  If we don't do this, the linker
8895 +   can't guarantee that the alignment is actually maintained in the
8896 +   linker output.
8897 +
8898 +   TODO: Might as well insert proper NOPs while we're at it... */
8899 +void
8900 +avr32_handle_align(fragS *frag)
8901 +{
8902 +  if (linkrelax
8903 +      && frag->fr_type == rs_align_code
8904 +      && frag->fr_address + frag->fr_fix > 0
8905 +      && frag->fr_offset > 0)
8906 +    {
8907 +      /* The alignment order (fr_offset) is stored in the addend. */
8908 +      fix_new(frag, frag->fr_fix, 2, &abs_symbol, frag->fr_offset,
8909 +             FALSE, BFD_RELOC_AVR32_ALIGN);
8910 +    }
8911 +}
8912 +
8913 +/* Relax_align. Advance location counter to next address that has 'alignment'
8914 +   lowest order bits all 0s, return size of adjustment made.  */
8915 +relax_addressT
8916 +avr32_relax_align(segT segment ATTRIBUTE_UNUSED,
8917 +                 fragS *fragP,
8918 +                 relax_addressT address)
8919 +{
8920 +  relax_addressT mask;
8921 +  relax_addressT new_address;
8922 +  int alignment;
8923 +
8924 +  alignment = fragP->fr_offset;
8925 +  mask = ~((~0) << alignment);
8926 +  new_address = (address + mask) & (~mask);
8927 +
8928 +  return new_address - address;
8929 +}
8930 +
8931 +/* Turn a string in input_line_pointer into a floating point constant
8932 +   of type type, and store the appropriate bytes in *litP.  The number
8933 +   of LITTLENUMS emitted is stored in *sizeP .  An error message is
8934 +   returned, or NULL on OK. */
8935 +
8936 +/* Equal to MAX_PRECISION in atof-ieee.c */
8937 +#define MAX_LITTLENUMS 6
8938 +
8939 +char *
8940 +md_atof (type, litP, sizeP)
8941 +char   type;
8942 +char * litP;
8943 +int *  sizeP;
8944 +{
8945 +  int              i;
8946 +  int              prec;
8947 +  LITTLENUM_TYPE   words [MAX_LITTLENUMS];
8948 +  char *           t;
8949 +
8950 +  switch (type)
8951 +  {
8952 +    case 'f':
8953 +    case 'F':
8954 +    case 's':
8955 +    case 'S':
8956 +      prec = 2;
8957 +      break;
8958 +
8959 +    case 'd':
8960 +    case 'D':
8961 +    case 'r':
8962 +    case 'R':
8963 +      prec = 4;
8964 +      break;
8965 +
8966 +      /* FIXME: Some targets allow other format chars for bigger sizes here.  */
8967 +
8968 +    default:
8969 +      * sizeP = 0;
8970 +      return _("Bad call to md_atof()");
8971 +  }
8972 +
8973 +  t = atof_ieee (input_line_pointer, type, words);
8974 +  if (t)
8975 +    input_line_pointer = t;
8976 +  * sizeP = prec * sizeof (LITTLENUM_TYPE);
8977 +
8978 +  for (i = 0; i < prec; i++)
8979 +  {
8980 +    md_number_to_chars (litP, (valueT) words[i],
8981 +                        sizeof (LITTLENUM_TYPE));
8982 +    litP += sizeof (LITTLENUM_TYPE);
8983 +  }
8984 +
8985 +  return 0;
8986 +}
8987 +
8988 +static char *avr32_end_of_match(char *cont, char *what)
8989 +{
8990 +  int len = strlen (what);
8991 +
8992 +  if (! is_part_of_name (cont[len])
8993 +      && strncasecmp (cont, what, len) == 0)
8994 +    return cont + len;
8995 +
8996 +  return NULL;
8997 +}
8998 +
8999 +int
9000 +avr32_parse_name (char const *name, expressionS *exp, char *nextchar)
9001 +{
9002 +  char *next = input_line_pointer;
9003 +  char *next_end;
9004 +
9005 +  pr_debug("parse_name: %s, nextchar=%c (%02x)\n", name, *nextchar, *nextchar);
9006 +
9007 +  if (*nextchar == '(')
9008 +    {
9009 +      if (strcasecmp(name, "hi") == 0)
9010 +       {
9011 +         *next = *nextchar;
9012 +
9013 +         expression(exp);
9014 +
9015 +         if (exp->X_op == O_constant)
9016 +           {
9017 +             pr_debug("  -> constant hi(0x%08lx) -> 0x%04lx\n",
9018 +                      exp->X_add_number, exp->X_add_number >> 16);
9019 +             exp->X_add_number = (exp->X_add_number >> 16) & 0xffff;
9020 +           }
9021 +         else
9022 +           {
9023 +             exp->X_md = exp->X_op;
9024 +             exp->X_op = O_hi;
9025 +           }
9026 +
9027 +         return 1;
9028 +       }
9029 +      else if (strcasecmp(name, "lo") == 0)
9030 +       {
9031 +         *next = *nextchar;
9032 +
9033 +         expression(exp);
9034 +
9035 +         if (exp->X_op == O_constant)
9036 +           exp->X_add_number &= 0xffff;
9037 +         else
9038 +           {
9039 +             exp->X_md = exp->X_op;
9040 +             exp->X_op = O_lo;
9041 +           }
9042 +
9043 +         return 1;
9044 +       }
9045 +    }
9046 +  else if (*nextchar == '@')
9047 +    {
9048 +      exp->X_md = exp->X_op;
9049 +
9050 +      if ((next_end = avr32_end_of_match (next + 1, "got")))
9051 +       exp->X_op = O_got;
9052 +      else if ((next_end = avr32_end_of_match (next + 1, "tlsgd")))
9053 +       exp->X_op = O_tlsgd;
9054 +      /* Add more as needed */
9055 +      else
9056 +       {
9057 +         char c;
9058 +         input_line_pointer++;
9059 +         c = get_symbol_end();
9060 +         as_bad (_("unknown relocation override `%s'"), next + 1);
9061 +         *input_line_pointer = c;
9062 +         input_line_pointer = next;
9063 +         return 0;
9064 +       }
9065 +
9066 +      exp->X_op_symbol = NULL;
9067 +      exp->X_add_symbol = symbol_find_or_make (name);
9068 +      exp->X_add_number = 0;
9069 +
9070 +      *input_line_pointer = *nextchar;
9071 +      input_line_pointer = next_end;
9072 +      *nextchar = *input_line_pointer;
9073 +      *input_line_pointer = '\0';
9074 +      return 1;
9075 +    }
9076 +  else if (strcmp (name, "_GLOBAL_OFFSET_TABLE_") == 0)
9077 +    {
9078 +      if (!GOT_symbol)
9079 +       GOT_symbol = symbol_find_or_make(name);
9080 +
9081 +      exp->X_add_symbol = GOT_symbol;
9082 +      exp->X_op = O_symbol;
9083 +      exp->X_add_number = 0;
9084 +      return 1;
9085 +    }
9086 +
9087 +  return 0;
9088 +}
9089 +
9090 +static void
9091 +s_rseg (int value ATTRIBUTE_UNUSED)
9092 +{
9093 +  /* Syntax: RSEG segment_name [:type] [NOROOT|ROOT] [(align)]
9094 +   * Defaults:
9095 +   *  - type: undocumented ("typically CODE or DATA")
9096 +   *  - ROOT
9097 +   *  - align: 1 for code, 0 for others
9098 +   *
9099 +   * TODO: NOROOT is ignored. If gas supports discardable segments, it should
9100 +   * be implemented.
9101 +   */
9102 +  char *name, *end;
9103 +  int length, type, attr;
9104 +  int align = 0;
9105 +
9106 +  SKIP_WHITESPACE();
9107 +
9108 +  end = input_line_pointer;
9109 +  while (0 == strchr ("\n\t;:( ", *end))
9110 +    end++;
9111 +  if (end == input_line_pointer)
9112 +    {
9113 +      as_warn (_("missing name"));
9114 +      ignore_rest_of_line();
9115 +      return;
9116 +    }
9117 +
9118 +  name = xmalloc (end - input_line_pointer + 1);
9119 +  memcpy (name, input_line_pointer, end - input_line_pointer);
9120 +  name[end - input_line_pointer] = '\0';
9121 +  input_line_pointer = end;
9122 +
9123 +  SKIP_WHITESPACE();
9124 +
9125 +  type = SHT_NULL;
9126 +  attr = 0;
9127 +
9128 +  if (*input_line_pointer == ':')
9129 +    {
9130 +      /* Skip the colon */
9131 +      ++input_line_pointer;
9132 +      SKIP_WHITESPACE();
9133 +
9134 +      /* Possible options at this point:
9135 +       *   - flag (ROOT or NOROOT)
9136 +       *   - a segment type
9137 +       */
9138 +      end = input_line_pointer;
9139 +      while (0 == strchr ("\n\t;:( ", *end))
9140 +       end++;
9141 +      length = end - input_line_pointer;
9142 +      if (((length == 4) && (0 == strncasecmp( input_line_pointer, "ROOT", 4))) ||
9143 +         ((length == 6) && (0 == strncasecmp( input_line_pointer, "NOROOT", 6))))
9144 +       {
9145 +         /* Ignore ROOT/NOROOT */
9146 +         input_line_pointer = end;
9147 +       }
9148 +      else
9149 +       {
9150 +         /* Must be a segment type */
9151 +         switch (*input_line_pointer)
9152 +           {
9153 +           case 'C':
9154 +           case 'c':
9155 +             if ((length == 4) &&
9156 +                 (0 == strncasecmp (input_line_pointer, "CODE", 4)))
9157 +               {
9158 +                 attr |= SHF_ALLOC | SHF_EXECINSTR;
9159 +                 type = SHT_PROGBITS;
9160 +                 align = 1;
9161 +                 break;
9162 +               }
9163 +             if ((length == 5) &&
9164 +                 (0 == strncasecmp (input_line_pointer, "CONST", 5)))
9165 +               {
9166 +                 attr |= SHF_ALLOC;
9167 +                 type = SHT_PROGBITS;
9168 +                 break;
9169 +               }
9170 +             goto de_fault;
9171 +
9172 +           case 'D':
9173 +           case 'd':
9174 +             if ((length == 4) &&
9175 +                 (0 == strncasecmp (input_line_pointer, "DATA", 4)))
9176 +               {
9177 +                 attr |= SHF_ALLOC | SHF_WRITE;
9178 +                 type = SHT_PROGBITS;
9179 +                 break;
9180 +               }
9181 +             goto de_fault;
9182 +
9183 +             /* TODO: Add FAR*, HUGE*, IDATA and NEAR* if necessary */
9184 +
9185 +           case 'U':
9186 +           case 'u':
9187 +             if ((length == 7) &&
9188 +                 (0 == strncasecmp (input_line_pointer, "UNTYPED", 7)))
9189 +               break;
9190 +             goto de_fault;
9191 +
9192 +             /* TODO: Add XDATA and ZPAGE if necessary */
9193 +
9194 +           de_fault:
9195 +           default:
9196 +             as_warn (_("unrecognized segment type"));
9197 +           }
9198 +
9199 +         input_line_pointer = end;
9200 +         SKIP_WHITESPACE();
9201 +
9202 +         if (*input_line_pointer == ':')
9203 +           {
9204 +             /*  ROOT/NOROOT */
9205 +             ++input_line_pointer;
9206 +             SKIP_WHITESPACE();
9207 +
9208 +             end = input_line_pointer;
9209 +             while (0 == strchr ("\n\t;:( ", *end))
9210 +               end++;
9211 +             length = end - input_line_pointer;
9212 +             if (! ((length == 4) &&
9213 +                    (0 == strncasecmp( input_line_pointer, "ROOT", 4))) &&
9214 +                 ! ((length == 6) &&
9215 +                    (0 == strncasecmp( input_line_pointer, "NOROOT", 6))))
9216 +               {
9217 +                 as_warn (_("unrecognized segment flag"));
9218 +               }
9219 +
9220 +             input_line_pointer = end;
9221 +             SKIP_WHITESPACE();
9222 +           }
9223 +       }
9224 +    }
9225 +
9226 +  if (*input_line_pointer == '(')
9227 +    {
9228 +      align = get_absolute_expression ();
9229 +    }
9230 +
9231 +  demand_empty_rest_of_line();
9232 +
9233 +  obj_elf_change_section (name, type, attr, 0, NULL, 0, 0);
9234 +#ifdef AVR32_DEBUG
9235 +  fprintf( stderr, "RSEG: Changed section to %s, type: 0x%x, attr: 0x%x\n",
9236 +      name, type, attr );
9237 +  fprintf( stderr, "RSEG: Aligning to 2**%d\n", align );
9238 +#endif
9239 +
9240 +  if (align > 15)
9241 +    {
9242 +      align = 15;
9243 +      as_warn (_("alignment too large: %u assumed"), align);
9244 +    }
9245 +
9246 +  /* Hope not, that is */
9247 +  assert (now_seg != absolute_section);
9248 +
9249 +  /* Only make a frag if we HAVE to... */
9250 +  if (align != 0 && !need_pass_2)
9251 +    {
9252 +      if (subseg_text_p (now_seg))
9253 +       frag_align_code (align, 0);
9254 +      else
9255 +       frag_align (align, 0, 0);
9256 +    }
9257 +
9258 +  record_alignment (now_seg, align - OCTETS_PER_BYTE_POWER);
9259 +}
9260 +
9261 +/* vim: syntax=c sw=2
9262 + */
9263 --- /dev/null
9264 +++ b/gas/config/tc-avr32.h
9265 @@ -0,0 +1,325 @@
9266 +/* Assembler definitions for AVR32.
9267 +   Copyright 2003,2004,2005,2006,2007,2008,2009 Atmel Corporation.
9268 +
9269 +   Written by Haavard Skinnemoen, Atmel Norway, <hskinnemoen@atmel.com>
9270 +
9271 +   This file is part of GAS, the GNU Assembler.
9272 +
9273 +   GAS is free software; you can redistribute it and/or modify it
9274 +   under the terms of the GNU General Public License as published by
9275 +   the Free Software Foundation; either version 2, or (at your option)
9276 +   any later version.
9277 +
9278 +   GAS is distributed in the hope that it will be useful, but WITHOUT
9279 +   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
9280 +   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
9281 +   License for more details.
9282 +
9283 +   You should have received a copy of the GNU General Public License
9284 +   along with GAS; see the file COPYING.  If not, write to the Free
9285 +   Software Foundation, 59 Temple Place - Suite 330, Boston, MA
9286 +   02111-1307, USA.  */
9287 +
9288 +#if 0
9289 +#define DEBUG
9290 +#define DEBUG1
9291 +#define DEBUG2
9292 +#define DEBUG3
9293 +#define DEBUG4
9294 +#define DEBUG5
9295 +#endif
9296 +
9297 +/* Are we trying to be compatible with the IAR assembler? (--iar) */
9298 +extern int avr32_iarcompat;
9299 +
9300 +/* By convention, you should define this macro in the `.h' file.  For
9301 +   example, `tc-m68k.h' defines `TC_M68K'.  You might have to use this
9302 +   if it is necessary to add CPU specific code to the object format
9303 +   file.  */
9304 +#define TC_AVR32
9305 +
9306 +/* This macro is the BFD target name to use when creating the output
9307 +   file.  This will normally depend upon the `OBJ_FMT' macro.  */
9308 +#define TARGET_FORMAT "elf32-avr32"
9309 +
9310 +/* This macro is the BFD architecture to pass to `bfd_set_arch_mach'.  */
9311 +#define TARGET_ARCH bfd_arch_avr32
9312 +
9313 +/* This macro is the BFD machine number to pass to
9314 +   `bfd_set_arch_mach'.  If it is not defined, GAS will use 0.  */
9315 +#define TARGET_MACH 0
9316 +
9317 +/* UNDOCUMENTED: Allow //-style comments */
9318 +#define DOUBLESLASH_LINE_COMMENTS
9319 +
9320 +/* You should define this macro to be non-zero if the target is big
9321 +   endian, and zero if the target is little endian.  */
9322 +#define TARGET_BYTES_BIG_ENDIAN 1
9323 +
9324 +/* FIXME: It seems that GAS only expects a one-byte opcode...
9325 +   #define NOP_OPCODE 0xd703 */
9326 +
9327 +/* If you define this macro, GAS will warn about the use of
9328 +   nonstandard escape sequences in a string.  */
9329 +#undef ONLY_STANDARD_ESCAPES
9330 +
9331 +#define DWARF2_FORMAT(SEC) dwarf2_format_32bit
9332 +
9333 +/* Instructions are either 2 or 4 bytes long */
9334 +/* #define DWARF2_LINE_MIN_INSN_LENGTH 2 */
9335 +
9336 +/* GAS will call this function for any expression that can not be
9337 +   recognized.  When the function is called, `input_line_pointer'
9338 +   will point to the start of the expression.  */
9339 +#define md_operand(x)
9340 +
9341 +#define md_parse_name(name, expr, mode, c) avr32_parse_name(name, expr, c)
9342 +extern int avr32_parse_name(const char *, struct expressionS *, char *);
9343 +
9344 +/* You may define this macro to generate a fixup for a data
9345 +   allocation pseudo-op.  */
9346 +#define TC_CONS_FIX_NEW(FRAG, OFF, LEN, EXP)   \
9347 +  avr32_cons_fix_new(FRAG, OFF, LEN, EXP)
9348 +void avr32_cons_fix_new (fragS *, int, int, expressionS *);
9349 +
9350 +/* `extsym - .' expressions can be emitted using PC-relative relocs */
9351 +#define DIFF_EXPR_OK
9352 +
9353 +/* This is used to construct expressions out of @gotoff, etc. The
9354 +   relocation type is stored in X_md */
9355 +#define O_got          O_md1
9356 +#define O_hi           O_md2
9357 +#define O_lo           O_md3
9358 +#define O_tlsgd                O_md4
9359 +
9360 +/* You may define this macro to parse an expression used in a data
9361 +   allocation pseudo-op such as `.word'.  You can use this to
9362 +   recognize relocation directives that may appear in such directives.  */
9363 +/* #define TC_PARSE_CONS_EXPRESSION(EXPR,N) avr_parse_cons_expression (EXPR,N)
9364 +   void avr_parse_cons_expression (expressionS *exp, int nbytes); */
9365 +
9366 +/* This should just call either `number_to_chars_bigendian' or
9367 +   `number_to_chars_littleendian', whichever is appropriate.  On
9368 +   targets like the MIPS which support options to change the
9369 +   endianness, which function to call is a runtime decision.  On
9370 +   other targets, `md_number_to_chars' can be a simple macro.  */
9371 +#define md_number_to_chars number_to_chars_bigendian
9372 +
9373 +/* `md_short_jump_size'
9374 +   `md_long_jump_size'
9375 +   `md_create_short_jump'
9376 +   `md_create_long_jump'
9377 +   If `WORKING_DOT_WORD' is defined, GAS will not do broken word
9378 +   processing (*note Broken words::.).  Otherwise, you should set
9379 +   `md_short_jump_size' to the size of a short jump (a jump that is
9380 +   just long enough to jump around a long jmp) and
9381 +   `md_long_jump_size' to the size of a long jump (a jump that can go
9382 +   anywhere in the function), You should define
9383 +   `md_create_short_jump' to create a short jump around a long jump,
9384 +   and define `md_create_long_jump' to create a long jump.  */
9385 +#define WORKING_DOT_WORD
9386 +
9387 +/* If you define this macro, it means that `tc_gen_reloc' may return
9388 +   multiple relocation entries for a single fixup.  In this case, the
9389 +   return value of `tc_gen_reloc' is a pointer to a null terminated
9390 +   array.  */
9391 +#undef RELOC_EXPANSION_POSSIBLE
9392 +
9393 +/* If you define this macro, GAS will not require pseudo-ops to start with a .
9394 +   character. */
9395 +#define NO_PSEUDO_DOT (avr32_iarcompat)
9396 +
9397 +/* The IAR assembler uses $ as the location counter. Unfortunately, we
9398 +   can't make this dependent on avr32_iarcompat... */
9399 +#define DOLLAR_DOT
9400 +
9401 +/* Values passed to md_apply_fix3 don't include the symbol value.  */
9402 +#define MD_APPLY_SYM_VALUE(FIX) 0
9403 +
9404 +/* The number of bytes to put into a word in a listing.  This affects
9405 +   the way the bytes are clumped together in the listing.  For
9406 +   example, a value of 2 might print `1234 5678' where a value of 1
9407 +   would print `12 34 56 78'.  The default value is 4.  */
9408 +#define LISTING_WORD_SIZE 4
9409 +
9410 +/* extern const struct relax_type md_relax_table[];
9411 +#define TC_GENERIC_RELAX_TABLE md_relax_table */
9412 +
9413 +/*
9414 +  An `.lcomm' directive with no explicit alignment parameter will use
9415 +  this macro to set P2VAR to the alignment that a request for SIZE
9416 +  bytes will have.  The alignment is expressed as a power of two.  If
9417 +  no alignment should take place, the macro definition should do
9418 +  nothing.  Some targets define a `.bss' directive that is also
9419 +  affected by this macro.  The default definition will set P2VAR to
9420 +  the truncated power of two of sizes up to eight bytes.
9421 +
9422 +  We want doublewords to be word-aligned, so we're going to modify the
9423 +  default definition a tiny bit.
9424 +*/
9425 +#define TC_IMPLICIT_LCOMM_ALIGNMENT(SIZE, P2VAR)       \
9426 +  do                                                   \
9427 +    {                                                  \
9428 +      if ((SIZE) >= 4)                                 \
9429 +       (P2VAR) = 2;                                    \
9430 +      else if ((SIZE) >= 2)                            \
9431 +       (P2VAR) = 1;                                    \
9432 +      else                                             \
9433 +       (P2VAR) = 0;                                    \
9434 +    }                                                  \
9435 +  while (0)
9436 +
9437 +/* When relaxing, we need to generate relocations for alignment
9438 +   directives.  */
9439 +#define HANDLE_ALIGN(frag) avr32_handle_align(frag)
9440 +extern void avr32_handle_align(fragS *);
9441 +
9442 +/* See internals doc for explanation. Oh wait...
9443 +   Now, can you guess where "alignment" comes from? ;-) */
9444 +#define MAX_MEM_FOR_RS_ALIGN_CODE ((1 << alignment) - 1)
9445 +
9446 +/* We need to stop gas from reducing certain expressions (e.g. GOT
9447 +   references) */
9448 +#define tc_fix_adjustable(fix) avr32_fix_adjustable(fix)
9449 +extern bfd_boolean avr32_fix_adjustable(struct fix *);
9450 +
9451 +/* The linker needs to be passed a little more information when relaxing. */
9452 +#define TC_FORCE_RELOCATION(fix) avr32_force_reloc(fix)
9453 +extern bfd_boolean avr32_force_reloc(struct fix *);
9454 +
9455 +/* I'm tired of working around all the madness in fixup_segment().
9456 +   This hook will do basically the same things as the generic code,
9457 +   and then it will "goto" right past it.  */
9458 +#define TC_VALIDATE_FIX(FIX, SEG, SKIP)                \
9459 +  do                                           \
9460 +    {                                          \
9461 +      avr32_process_fixup(FIX, SEG);           \
9462 +      if (!(FIX)->fx_done)                     \
9463 +       ++seg_reloc_count;                      \
9464 +      goto SKIP;                               \
9465 +    }                                          \
9466 +  while (0)
9467 +extern void avr32_process_fixup(struct fix *fixP, segT this_segment);
9468 +
9469 +/* Positive values of TC_FX_SIZE_SLACK allow a target to define
9470 +   fixups that far past the end of a frag.  Having such fixups
9471 +   is of course most most likely a bug in setting fx_size correctly.
9472 +   A negative value disables the fixup check entirely, which is
9473 +   appropriate for something like the Renesas / SuperH SH_COUNT
9474 +   reloc.  */
9475 +/* This target is buggy, and sets fix size too large.  */
9476 +#define TC_FX_SIZE_SLACK(FIX) -1
9477 +
9478 +/* We don't want the gas core to make any assumptions about our way of
9479 +   doing linkrelaxing.  */
9480 +#define TC_LINKRELAX_FIXUP(SEG)                        0
9481 +
9482 +/* ... but we do want it to insert lots of padding. */
9483 +#define LINKER_RELAXING_SHRINKS_ONLY
9484 +
9485 +/* Better do it ourselves, really... */
9486 +#define TC_RELAX_ALIGN(SEG, FRAG, ADDR)        avr32_relax_align(SEG, FRAG, ADDR)
9487 +extern relax_addressT
9488 +avr32_relax_align(segT segment, fragS *fragP, relax_addressT address);
9489 +
9490 +/* Use line number format that is amenable to linker relaxation.  */
9491 +#define DWARF2_USE_FIXED_ADVANCE_PC (linkrelax != 0)
9492 +
9493 +/* This is called by write_object_file() just before symbols are
9494 +   attempted converted into section symbols.  */
9495 +#define tc_frob_file_before_adjust()   avr32_frob_file()
9496 +extern void avr32_frob_file(void);
9497 +
9498 +/* If you define this macro, GAS will call it at the end of each input
9499 +   file.  */
9500 +#define md_cleanup() avr32_cleanup()
9501 +extern void avr32_cleanup(void);
9502 +
9503 +/* There's an AVR32-specific hack in operand() which creates O_md
9504 +   expressions when encountering HWRD or LWRD. We need to generate
9505 +   proper relocs for them */
9506 +/* #define md_cgen_record_fixup_exp avr32_cgen_record_fixup_exp */
9507 +
9508 +/* I needed to add an extra hook in gas_cgen_finish_insn() for
9509 +   conversion of O_md* operands because md_cgen_record_fixup_exp()
9510 +   isn't called for relaxable insns */
9511 +/* #define md_cgen_convert_expr(exp, opinfo) avr32_cgen_convert_expr(exp, opinfo)
9512 +   int avr32_cgen_convert_expr(expressionS *, int); */
9513 +
9514 +/* #define tc_gen_reloc gas_cgen_tc_gen_reloc */
9515 +
9516 +/* If you define this macro, it should return the position from which
9517 +   the PC relative adjustment for a PC relative fixup should be
9518 +   made. On many processors, the base of a PC relative instruction is
9519 +   the next instruction, so this macro would return the length of an
9520 +   instruction, plus the address of the PC relative fixup. The latter
9521 +   can be calculated as fixp->fx_where + fixp->fx_frag->fr_address. */
9522 +extern long md_pcrel_from_section (struct fix *, segT);
9523 +#define MD_PCREL_FROM_SECTION(FIX, SEC) md_pcrel_from_section (FIX, SEC)
9524 +
9525 +#define LOCAL_LABEL(name) (name[0] == '.' && (name[1] == 'L'))
9526 +#define LOCAL_LABELS_FB                1
9527 +
9528 +struct avr32_relaxer
9529 +{
9530 +  int (*estimate_size)(fragS *, segT);
9531 +  long (*relax_frag)(segT, fragS *, long);
9532 +  void (*convert_frag)(bfd *, segT, fragS *);
9533 +};
9534 +
9535 +/* AVR32 has quite complex instruction coding, which means we need
9536 + * lots of information in order to do the right thing during relaxing
9537 + * (basically, we need to be able to reconstruct a whole new opcode if
9538 + * necessary) */
9539 +#define TC_FRAG_TYPE struct avr32_frag_data
9540 +
9541 +struct cpool;
9542 +
9543 +struct avr32_frag_data
9544 +{
9545 +  /* TODO: Maybe add an expression object here so that we can use
9546 +     fix_new_exp() in md_convert_frag?  We may have to decide
9547 +     pcrel-ness in md_estimate_size_before_relax() as well...or we
9548 +     might do it when parsing.  Doing it while parsing may fail
9549 +     because the sub_symbol is undefined then... */
9550 +  int pcrel;
9551 +  int force_extended;
9552 +  int reloc_info;
9553 +  struct avr32_relaxer *relaxer;
9554 +  expressionS exp;
9555 +
9556 +  /* Points to associated constant pool, for use by LDA and CALL in
9557 +     non-pic mode, and when relaxing the .cpool directive */
9558 +  struct cpool *pool;
9559 +  unsigned int pool_entry;
9560 +};
9561 +
9562 +/* We will have to initialize the fields explicitly when needed */
9563 +#define TC_FRAG_INIT(fragP)
9564 +
9565 +#define md_estimate_size_before_relax(fragP, segT)                     \
9566 +  ((fragP)->tc_frag_data.relaxer->estimate_size(fragP, segT))
9567 +#define md_relax_frag(segment, fragP, stretch)                         \
9568 +  ((fragP)->tc_frag_data.relaxer->relax_frag(segment, fragP, stretch))
9569 +#define md_convert_frag(abfd, segment, fragP)                          \
9570 +  ((fragP)->tc_frag_data.relaxer->convert_frag(abfd, segment, fragP))
9571 +
9572 +#define TC_FIX_TYPE struct avr32_fix_data
9573 +
9574 +struct avr32_fix_data
9575 +{
9576 +  const struct avr32_ifield *ifield;
9577 +  unsigned int align;
9578 +  long min;
9579 +  long max;
9580 +};
9581 +
9582 +#define TC_INIT_FIX_DATA(fixP)                 \
9583 +  do                                           \
9584 +    {                                          \
9585 +      (fixP)->tc_fix_data.ifield = NULL;       \
9586 +      (fixP)->tc_fix_data.align = 0;           \
9587 +      (fixP)->tc_fix_data.min = 0;             \
9588 +      (fixP)->tc_fix_data.max = 0;             \
9589 +    }                                          \
9590 +  while (0)
9591 --- a/gas/configure.tgt
9592 +++ b/gas/configure.tgt
9593 @@ -33,6 +33,7 @@ case ${cpu} in
9594    am33_2.0)            cpu_type=mn10300 endian=little ;;
9595    arm*be|arm*b)                cpu_type=arm endian=big ;;
9596    arm*)                        cpu_type=arm endian=little ;;
9597 +  avr32*)              cpu_type=avr32 endian=big ;;
9598    bfin*)               cpu_type=bfin endian=little ;;
9599    c4x*)                        cpu_type=tic4x ;;
9600    cr16*)               cpu_type=cr16 endian=little ;;
9601 @@ -136,6 +137,9 @@ case ${generic_target} in
9602
9603    cr16-*-elf*)                         fmt=elf ;;
9604
9605 +  avr32-*-linux*)                      fmt=elf  em=linux bfd_gas=yes ;;
9606 +  avr32*)                              fmt=elf  bfd_gas=yes ;;
9607 +
9608    cris-*-linux-* | crisv32-*-linux-*)
9609                                         fmt=multi em=linux ;;
9610    cris-*-* | crisv32-*-*)              fmt=multi ;;
9611 --- a/gas/doc/all.texi
9612 +++ b/gas/doc/all.texi
9613 @@ -30,6 +30,7 @@
9614  @set ARC
9615  @set ARM
9616  @set AVR
9617 +@set AVR32
9618  @set Blackfin
9619  @set CR16
9620  @set CRIS
9621 --- a/gas/doc/asconfig.texi
9622 +++ b/gas/doc/asconfig.texi
9623 @@ -30,6 +30,7 @@
9624  @set ARC
9625  @set ARM
9626  @set AVR
9627 +@set AVR32
9628  @set Blackfin
9629  @set CR16
9630  @set CRIS
9631 --- a/gas/doc/as.texinfo
9632 +++ b/gas/doc/as.texinfo
9633 @@ -6731,6 +6731,9 @@ subject, see the hardware manufacturer's
9634  @ifset AVR
9635  * AVR-Dependent::               AVR Dependent Features
9636  @end ifset
9637 +@ifset AVR32
9638 +* AVR32-Dependent::               AVR32 Dependent Features
9639 +@end ifset
9640  @ifset Blackfin
9641  * Blackfin-Dependent::         Blackfin Dependent Features
9642  @end ifset
9643 @@ -6866,6 +6869,10 @@ subject, see the hardware manufacturer's
9644  @include c-avr.texi
9645  @end ifset
9646
9647 +@ifset AVR32
9648 +@include c-avr32.texi
9649 +@end ifset
9650 +
9651  @ifset Blackfin
9652  @include c-bfin.texi
9653  @end ifset
9654 --- /dev/null
9655 +++ b/gas/doc/c-avr32.texi
9656 @@ -0,0 +1,244 @@
9657 +@c Copyright 2005, 2006, 2007, 2008, 2009
9658 +@c Atmel Corporation
9659 +@c This is part of the GAS manual.
9660 +@c For copying conditions, see the file as.texinfo.
9661 +
9662 +@ifset GENERIC
9663 +@page
9664 +@node AVR32-Dependent
9665 +@chapter AVR32 Dependent Features
9666 +@end ifset
9667 +
9668 +@ifclear GENERIC
9669 +@node Machine Dependencies
9670 +@chapter AVR32 Dependent Features
9671 +@end ifclear
9672 +
9673 +@cindex AVR32 support
9674 +@menu
9675 +* AVR32 Options::               Options
9676 +* AVR32 Syntax::                Syntax
9677 +* AVR32 Directives::            Directives
9678 +* AVR32 Opcodes::               Opcodes
9679 +@end menu
9680 +
9681 +@node AVR32 Options
9682 +@section Options
9683 +@cindex AVR32 options
9684 +@cindex options for AVR32
9685 +
9686 +@table @code
9687 +
9688 +@cindex @code{--pic} command line option, AVR32
9689 +@cindex PIC code generation for AVR32
9690 +@item --pic
9691 +This option specifies that the output of the assembler should be marked
9692 +as position-independent code (PIC).  It will also ensure that
9693 +pseudo-instructions that deal with address calculation are output as
9694 +PIC, and that all absolute address references in the code are marked as
9695 +such.
9696 +
9697 +@cindex @code{--linkrelax} command line option, AVR32
9698 +@item --linkrelax
9699 +This option specifies that the output of the assembler should be marked
9700 +as linker-relaxable.  It will also ensure that all PC-relative operands
9701 +that may change during linker relaxation get appropriate relocations.
9702 +
9703 +@end table
9704 +
9705 +
9706 +@node AVR32 Syntax
9707 +@section Syntax
9708 +@menu
9709 +* AVR32-Chars::              Special Characters
9710 +* AVR32-Symrefs::            Symbol references
9711 +@end menu
9712 +
9713 +@node AVR32-Chars
9714 +@subsection Special Characters
9715 +
9716 +@cindex line comment character, AVR32
9717 +@cindex AVR32 line comment character
9718 +The presence of a @samp{//} on a line indicates the start of a comment
9719 +that extends to the end of the current line.  If a @samp{#} appears as
9720 +the first character of a line, the whole line is treated as a comment.
9721 +
9722 +@cindex line separator, AVR32
9723 +@cindex statement separator, AVR32
9724 +@cindex AVR32 line separator
9725 +The @samp{;} character can be used instead of a newline to separate
9726 +statements.
9727 +
9728 +@node AVR32-Symrefs
9729 +@subsection Symbol references
9730 +
9731 +The absolute value of a symbol can be obtained by simply naming the
9732 +symbol.  However, as AVR32 symbols have 32-bit values, most symbols have
9733 +values that are outside the range of any instructions.
9734 +
9735 +Instructions that take a PC-relative offset, e.g. @code{lddpc} or
9736 +@code{rcall}, can also reference a symbol by simply naming the symbol
9737 +(no explicit calculations necessary).  In this case, the assembler or
9738 +linker subtracts the address of the instruction from the symbol's value
9739 +and inserts the result into the instruction.  Note that even though an
9740 +overflow is less likely to happen for a relative reference than for an
9741 +absolute reference, the assembler or linker will generate an error if
9742 +the referenced symbol is too far away from the current location.
9743 +
9744 +Relative references can be used for data as well.  For example:
9745 +
9746 +@smallexample
9747 +        lddpc   r0, 2f
9748 +1:      add     r0, pc
9749 +        ...
9750 +        .align  2
9751 +2:      .int    @var{some_symbol} - 1b
9752 +@end smallexample
9753 +
9754 +Here, r0 will end up with the run-time address of @var{some_symbol} even
9755 +if the program was loaded at a different address than it was linked
9756 +(position-independent code).
9757 +
9758 +@subsubsection Symbol modifiers
9759 +
9760 +@table @code
9761 +
9762 +@item @code{hi(@var{symbol})}
9763 +Evaluates to the value of the symbol shifted right 16 bits.  This will
9764 +work even if @var{symbol} is defined in a different module.
9765 +
9766 +@item @code{lo(@var{symbol})}
9767 +Evaluates to the low 16 bits of the symbol's value.  This will work even
9768 +if @var{symbol} is defined in a different module.
9769 +
9770 +@item @code{@var{symbol}@@got}
9771 +Create a GOT entry for @var{symbol} and return the offset of that entry
9772 +relative to the GOT base.
9773 +
9774 +@end table
9775 +
9776 +
9777 +@node AVR32 Directives
9778 +@section Directives
9779 +@cindex machine directives, AVR32
9780 +@cindex AVR32 directives
9781 +
9782 +@table @code
9783 +
9784 +@cindex @code{.cpool} directive, AVR32
9785 +@item .cpool
9786 +This directive causes the current contents of the constant pool to be
9787 +dumped into the current section at the current location (aligned to a
9788 +word boundary).  @code{GAS} maintains a separate constant pool for each
9789 +section and each sub-section.  The @code{.cpool} directive will only
9790 +affect the constant pool of the current section and sub-section.  At the
9791 +end of assembly, all remaining, non-empty constant pools will
9792 +automatically be dumped.
9793 +
9794 +@end table
9795 +
9796 +
9797 +@node AVR32 Opcodes
9798 +@section Opcodes
9799 +@cindex AVR32 opcodes
9800 +@cindex opcodes for AVR32
9801 +
9802 +@code{@value{AS}} implements all the standard AVR32 opcodes.  It also
9803 +implements several pseudo-opcodes, which are recommended to use wherever
9804 +possible because they give the tool chain better freedom to generate
9805 +optimal code.
9806 +
9807 +@table @code
9808 +
9809 +@cindex @code{LDA.W reg, symbol} pseudo op, AVR32
9810 +@item LDA.W
9811 +@smallexample
9812 +        lda.w   @var{reg}, @var{symbol}
9813 +@end smallexample
9814 +
9815 +This instruction will load the address of @var{symbol} into
9816 +@var{reg}. The instruction will evaluate to one of the following,
9817 +depending on the relative distance to the symbol, the relative distance
9818 +to the constant pool and whether the @code{--pic} option has been
9819 +specified. If the @code{--pic} option has not been specified, the
9820 +alternatives are as follows:
9821 +@smallexample
9822 +        /* @var{symbol} evaluates to a small enough value */
9823 +        mov     @var{reg}, @var{symbol}
9824 +
9825 +        /* (. - @var{symbol}) evaluates to a small enough value */
9826 +        sub     @var{reg}, pc, . - @var{symbol}
9827 +
9828 +        /* Constant pool is close enough */
9829 +        lddpc   @var{reg}, @var{cpent}
9830 +        ...
9831 +@var{cpent}:
9832 +        .long   @var{symbol}
9833 +
9834 +        /* Otherwise (not implemented yet, probably not necessary) */
9835 +        mov     @var{reg}, lo(@var{symbol})
9836 +        orh     @var{reg}, hi(@var{symbol})
9837 +@end smallexample
9838 +
9839 +If the @code{--pic} option has been specified, the alternatives are as
9840 +follows:
9841 +@smallexample
9842 +        /* (. - @var{symbol}) evaluates to a small enough value */
9843 +        sub     @var{reg}, pc, . - @var{symbol}
9844 +
9845 +        /* If @code{--linkrelax} not specified */
9846 +        ld.w    @var{reg}, r6[@var{symbol}@@got]
9847 +
9848 +        /* Otherwise */
9849 +        mov     @var{reg}, @var{symbol}@@got / 4
9850 +        ld.w    @var{reg}, r6[@var{reg} << 2]
9851 +@end smallexample
9852 +
9853 +If @var{symbol} is not defined in the same file and section as the
9854 +@code{LDA.W} instruction, the most pessimistic alternative of the
9855 +above is selected. The linker may convert it back into the most
9856 +optimal alternative when the final value of all symbols is known.
9857 +
9858 +@cindex @code{CALL symbol} pseudo op, AVR32
9859 +@item CALL
9860 +@smallexample
9861 +        call    @var{symbol}
9862 +@end smallexample
9863 +
9864 +This instruction will insert code to call the subroutine identified by
9865 +@var{symbol}. It will evaluate to one of the following, depending on
9866 +the relative distance to the symbol as well as the @code{--linkrelax}
9867 +and @code{--pic} command-line options.
9868 +
9869 +If @var{symbol} is defined in the same section and input file, and the
9870 +distance is small enough, an @code{rcall} instruction is inserted:
9871 +@smallexample
9872 +        rcall   @var{symbol}
9873 +@end smallexample
9874 +
9875 +Otherwise, if the @code{--pic} option has not been specified:
9876 +@smallexample
9877 +        mcall   @var{cpent}
9878 +        ...
9879 +@var{cpent}:
9880 +        .long   @var{symbol}
9881 +@end smallexample
9882 +
9883 +Finally, if nothing else fits and the @code{--pic} option has been
9884 +specified, the assembler will indirect the call through the Global
9885 +Offset Table:
9886 +@smallexample
9887 +        /* If @code{--linkrelax} not specified */
9888 +        mcall   r6[@var{symbol}@@got]
9889 +
9890 +        /* If @code{--linkrelax} specified */
9891 +        mov     lr, @var{symbol}@@got / 4
9892 +        ld.w    lr, r6[lr << 2]
9893 +        icall   lr
9894 +@end smallexample
9895 +
9896 +The linker, after determining the final value of @var{symbol}, may
9897 +convert any of these into more optimal alternatives. This includes
9898 +deleting any superfluous constant pool- and GOT-entries.
9899 +
9900 +@end table
9901 --- a/gas/doc/Makefile.am
9902 +++ b/gas/doc/Makefile.am
9903 @@ -33,6 +33,7 @@ CPU_DOCS = \
9904         c-arc.texi \
9905         c-arm.texi \
9906         c-avr.texi \
9907 +       c-avr32.texi \
9908         c-bfin.texi \
9909         c-cr16.texi \
9910         c-d10v.texi \
9911 --- a/gas/Makefile.am
9912 +++ b/gas/Makefile.am
9913 @@ -43,6 +43,7 @@ CPU_TYPES = \
9914         arc \
9915         arm \
9916         avr \
9917 +       avr32 \
9918         bfin \
9919         cr16 \
9920         cris \
9921 @@ -244,6 +245,7 @@ TARGET_CPU_CFILES = \
9922         config/tc-arc.c \
9923         config/tc-arm.c \
9924         config/tc-avr.c \
9925 +       config/tc-avr32.c \
9926         config/tc-bfin.c \
9927         config/tc-cr16.c \
9928         config/tc-cris.c \
9929 @@ -307,6 +309,7 @@ TARGET_CPU_HFILES = \
9930         config/tc-arc.h \
9931         config/tc-arm.h \
9932         config/tc-avr.h \
9933 +       config/tc-avr32.h \
9934         config/tc-bfin.h \
9935         config/tc-cr16.h \
9936         config/tc-cris.h \
9937 --- /dev/null
9938 +++ b/gas/testsuite/gas/avr32/aliases.d
9939 @@ -0,0 +1,19 @@
9940 +#as:
9941 +#objdump: -dr
9942 +#name: aliases
9943 +
9944 +.*: +file format .*
9945 +
9946 +Disassembly of section \.text:
9947 +
9948 +00000000 <ld_nodisp>:
9949 +   0:  19 80      [ \t]+ld\.ub r0,r12\[0x0\]
9950 +   2:  f9 20 00 00[ \t]+ld\.sb r0,r12\[0\]
9951 +   6:  98 80      [ \t]+ld\.uh r0,r12\[0x0\]
9952 +   8:  98 00      [ \t]+ld\.sh r0,r12\[0x0\]
9953 +   a:  78 00      [ \t]+ld\.w r0,r12\[0x0\]
9954 +
9955 +0000000c <st_nodisp>:
9956 +   c:  b8 80      [ \t]+st\.b r12\[0x0\],r0
9957 +   e:  b8 00      [ \t]+st\.h r12\[0x0\],r0
9958 +  10:  99 00      [ \t]+st\.w r12\[0x0\],r0
9959 --- /dev/null
9960 +++ b/gas/testsuite/gas/avr32/aliases.s
9961 @@ -0,0 +1,14 @@
9962 +       .text
9963 +       .global ld_nodisp
9964 +ld_nodisp:
9965 +       ld.ub   r0, r12
9966 +       ld.sb   r0, r12
9967 +       ld.uh   r0, r12
9968 +       ld.sh   r0, r12
9969 +       ld.w    r0, r12
9970 +
9971 +       .global st_nodisp
9972 +st_nodisp:
9973 +       st.b    r12, r0
9974 +       st.h    r12, r0
9975 +       st.w    r12, r0
9976 --- /dev/null
9977 +++ b/gas/testsuite/gas/avr32/allinsn.d
9978 @@ -0,0 +1,2987 @@
9979 +#as:
9980 +#objdump: -dr
9981 +#name: allinsn
9982 +
9983 +.*: +file format .*
9984 +
9985 +Disassembly of section \.text:
9986 +
9987 +[0-9a-f]* <ld_d5>:
9988 + *[0-9a-f]*:   fe 0f 02 3e     ld\.d lr,pc\[pc<<0x3\]
9989 + *[0-9a-f]*:   e0 00 02 00     ld\.d r0,r0\[r0\]
9990 + *[0-9a-f]*:   ea 05 02 26     ld\.d r6,r5\[r5<<0x2\]
9991 + *[0-9a-f]*:   e8 04 02 14     ld\.d r4,r4\[r4<<0x1\]
9992 + *[0-9a-f]*:   fc 0e 02 1e     ld\.d lr,lr\[lr<<0x1\]
9993 + *[0-9a-f]*:   e6 0d 02 2a     ld\.d r10,r3\[sp<<0x2\]
9994 + *[0-9a-f]*:   f4 06 02 28     ld\.d r8,r10\[r6<<0x2\]
9995 + *[0-9a-f]*:   ee 09 02 02     ld\.d r2,r7\[r9\]
9996 +
9997 +[0-9a-f]* <ld_w5>:
9998 + *[0-9a-f]*:   fe 0f 03 0f     ld\.w pc,pc\[pc\]
9999 + *[0-9a-f]*:   f8 0c 03 3c     ld\.w r12,r12\[r12<<0x3\]
10000 + *[0-9a-f]*:   ea 05 03 25     ld\.w r5,r5\[r5<<0x2\]
10001 + *[0-9a-f]*:   e8 04 03 14     ld\.w r4,r4\[r4<<0x1\]
10002 + *[0-9a-f]*:   fc 0e 03 1e     ld\.w lr,lr\[lr<<0x1\]
10003 + *[0-9a-f]*:   f2 09 03 02     ld\.w r2,r9\[r9\]
10004 + *[0-9a-f]*:   e4 06 03 0b     ld\.w r11,r2\[r6\]
10005 + *[0-9a-f]*:   e4 0d 03 30     ld\.w r0,r2\[sp<<0x3\]
10006 +
10007 +[0-9a-f]* <ld_sh5>:
10008 + *[0-9a-f]*:   fe 0f 04 0f     ld\.sh pc,pc\[pc\]
10009 + *[0-9a-f]*:   f8 0c 04 3c     ld\.sh r12,r12\[r12<<0x3\]
10010 + *[0-9a-f]*:   ea 05 04 25     ld\.sh r5,r5\[r5<<0x2\]
10011 + *[0-9a-f]*:   e8 04 04 14     ld\.sh r4,r4\[r4<<0x1\]
10012 + *[0-9a-f]*:   fc 0e 04 1e     ld\.sh lr,lr\[lr<<0x1\]
10013 + *[0-9a-f]*:   e0 0f 04 2b     ld\.sh r11,r0\[pc<<0x2\]
10014 + *[0-9a-f]*:   fa 06 04 2a     ld\.sh r10,sp\[r6<<0x2\]
10015 + *[0-9a-f]*:   e4 02 04 0c     ld\.sh r12,r2\[r2\]
10016 +
10017 +[0-9a-f]* <ld_uh5>:
10018 + *[0-9a-f]*:   fe 0f 05 0f     ld\.uh pc,pc\[pc\]
10019 + *[0-9a-f]*:   f8 0c 05 3c     ld\.uh r12,r12\[r12<<0x3\]
10020 + *[0-9a-f]*:   ea 05 05 25     ld\.uh r5,r5\[r5<<0x2\]
10021 + *[0-9a-f]*:   e8 04 05 14     ld\.uh r4,r4\[r4<<0x1\]
10022 + *[0-9a-f]*:   fc 0e 05 1e     ld\.uh lr,lr\[lr<<0x1\]
10023 + *[0-9a-f]*:   fe 0e 05 38     ld\.uh r8,pc\[lr<<0x3\]
10024 + *[0-9a-f]*:   e2 0f 05 16     ld\.uh r6,r1\[pc<<0x1\]
10025 + *[0-9a-f]*:   fc 0d 05 16     ld\.uh r6,lr\[sp<<0x1\]
10026 +
10027 +[0-9a-f]* <ld_sb2>:
10028 + *[0-9a-f]*:   fe 0f 06 0f     ld\.sb pc,pc\[pc\]
10029 + *[0-9a-f]*:   f8 0c 06 3c     ld\.sb r12,r12\[r12<<0x3\]
10030 + *[0-9a-f]*:   ea 05 06 25     ld\.sb r5,r5\[r5<<0x2\]
10031 + *[0-9a-f]*:   e8 04 06 14     ld\.sb r4,r4\[r4<<0x1\]
10032 + *[0-9a-f]*:   fc 0e 06 1e     ld\.sb lr,lr\[lr<<0x1\]
10033 + *[0-9a-f]*:   e2 0f 06 39     ld\.sb r9,r1\[pc<<0x3\]
10034 + *[0-9a-f]*:   e6 0b 06 10     ld\.sb r0,r3\[r11<<0x1\]
10035 + *[0-9a-f]*:   ea 05 06 1a     ld\.sb r10,r5\[r5<<0x1\]
10036 +
10037 +[0-9a-f]* <ld_ub5>:
10038 + *[0-9a-f]*:   fe 0f 07 0f     ld\.ub pc,pc\[pc\]
10039 + *[0-9a-f]*:   f8 0c 07 3c     ld\.ub r12,r12\[r12<<0x3\]
10040 + *[0-9a-f]*:   ea 05 07 25     ld\.ub r5,r5\[r5<<0x2\]
10041 + *[0-9a-f]*:   e8 04 07 14     ld\.ub r4,r4\[r4<<0x1\]
10042 + *[0-9a-f]*:   fc 0e 07 1e     ld\.ub lr,lr\[lr<<0x1\]
10043 + *[0-9a-f]*:   f8 07 07 36     ld\.ub r6,r12\[r7<<0x3\]
10044 + *[0-9a-f]*:   ec 0c 07 02     ld\.ub r2,r6\[r12\]
10045 + *[0-9a-f]*:   ee 0b 07 10     ld\.ub r0,r7\[r11<<0x1\]
10046 +
10047 +[0-9a-f]* <st_d5>:
10048 + *[0-9a-f]*:   fe 0f 08 0e     st\.d pc\[pc\],lr
10049 + *[0-9a-f]*:   f8 0c 08 3c     st\.d r12\[r12<<0x3\],r12
10050 + *[0-9a-f]*:   ea 05 08 26     st\.d r5\[r5<<0x2\],r6
10051 + *[0-9a-f]*:   e8 04 08 14     st\.d r4\[r4<<0x1\],r4
10052 + *[0-9a-f]*:   fc 0e 08 1e     st\.d lr\[lr<<0x1\],lr
10053 + *[0-9a-f]*:   e2 09 08 14     st\.d r1\[r9<<0x1\],r4
10054 + *[0-9a-f]*:   f4 02 08 14     st\.d r10\[r2<<0x1\],r4
10055 + *[0-9a-f]*:   f8 06 08 0e     st\.d r12\[r6\],lr
10056 +
10057 +[0-9a-f]* <st_w5>:
10058 + *[0-9a-f]*:   fe 0f 09 0f     st\.w pc\[pc\],pc
10059 + *[0-9a-f]*:   f8 0c 09 3c     st\.w r12\[r12<<0x3\],r12
10060 + *[0-9a-f]*:   ea 05 09 25     st\.w r5\[r5<<0x2\],r5
10061 + *[0-9a-f]*:   e8 04 09 14     st\.w r4\[r4<<0x1\],r4
10062 + *[0-9a-f]*:   fc 0e 09 1e     st\.w lr\[lr<<0x1\],lr
10063 + *[0-9a-f]*:   e2 0a 09 03     st\.w r1\[r10\],r3
10064 + *[0-9a-f]*:   e0 0a 09 19     st\.w r0\[r10<<0x1\],r9
10065 + *[0-9a-f]*:   e8 05 09 3f     st\.w r4\[r5<<0x3\],pc
10066 +
10067 +[0-9a-f]* <st_h5>:
10068 + *[0-9a-f]*:   fe 0f 0a 0f     st\.h pc\[pc\],pc
10069 + *[0-9a-f]*:   f8 0c 0a 3c     st\.h r12\[r12<<0x3\],r12
10070 + *[0-9a-f]*:   ea 05 0a 25     st\.h r5\[r5<<0x2\],r5
10071 + *[0-9a-f]*:   e8 04 0a 14     st\.h r4\[r4<<0x1\],r4
10072 + *[0-9a-f]*:   fc 0e 0a 1e     st\.h lr\[lr<<0x1\],lr
10073 + *[0-9a-f]*:   e4 09 0a 0b     st\.h r2\[r9\],r11
10074 + *[0-9a-f]*:   ea 01 0a 2c     st\.h r5\[r1<<0x2\],r12
10075 + *[0-9a-f]*:   fe 08 0a 23     st\.h pc\[r8<<0x2\],r3
10076 +
10077 +[0-9a-f]* <st_b5>:
10078 + *[0-9a-f]*:   fe 0f 0b 0f     st\.b pc\[pc\],pc
10079 + *[0-9a-f]*:   f8 0c 0b 3c     st\.b r12\[r12<<0x3\],r12
10080 + *[0-9a-f]*:   ea 05 0b 25     st\.b r5\[r5<<0x2\],r5
10081 + *[0-9a-f]*:   e8 04 0b 14     st\.b r4\[r4<<0x1\],r4
10082 + *[0-9a-f]*:   fc 0e 0b 1e     st\.b lr\[lr<<0x1\],lr
10083 + *[0-9a-f]*:   e2 08 0b 16     st\.b r1\[r8<<0x1\],r6
10084 + *[0-9a-f]*:   fc 0e 0b 31     st\.b lr\[lr<<0x3\],r1
10085 + *[0-9a-f]*:   ea 00 0b 2f     st\.b r5\[r0<<0x2\],pc
10086 +
10087 +[0-9a-f]* <divs>:
10088 + *[0-9a-f]*:   fe 0f 0c 0f     divs pc,pc,pc
10089 + *[0-9a-f]*:   f8 0c 0c 0c     divs r12,r12,r12
10090 + *[0-9a-f]*:   ea 05 0c 05     divs r5,r5,r5
10091 + *[0-9a-f]*:   e8 04 0c 04     divs r4,r4,r4
10092 + *[0-9a-f]*:   fc 0e 0c 0e     divs lr,lr,lr
10093 + *[0-9a-f]*:   fe 0f 0c 03     divs r3,pc,pc
10094 + *[0-9a-f]*:   f8 02 0c 09     divs r9,r12,r2
10095 + *[0-9a-f]*:   e8 01 0c 07     divs r7,r4,r1
10096 +
10097 +[0-9a-f]* <add1>:
10098 + *[0-9a-f]*:   1e 0f           add pc,pc
10099 + *[0-9a-f]*:   18 0c           add r12,r12
10100 + *[0-9a-f]*:   0a 05           add r5,r5
10101 + *[0-9a-f]*:   08 04           add r4,r4
10102 + *[0-9a-f]*:   1c 0e           add lr,lr
10103 + *[0-9a-f]*:   12 0c           add r12,r9
10104 + *[0-9a-f]*:   06 06           add r6,r3
10105 + *[0-9a-f]*:   18 0a           add r10,r12
10106 +
10107 +[0-9a-f]* <sub1>:
10108 + *[0-9a-f]*:   1e 1f           sub pc,pc
10109 + *[0-9a-f]*:   18 1c           sub r12,r12
10110 + *[0-9a-f]*:   0a 15           sub r5,r5
10111 + *[0-9a-f]*:   08 14           sub r4,r4
10112 + *[0-9a-f]*:   1c 1e           sub lr,lr
10113 + *[0-9a-f]*:   0c 1e           sub lr,r6
10114 + *[0-9a-f]*:   1a 10           sub r0,sp
10115 + *[0-9a-f]*:   18 16           sub r6,r12
10116 +
10117 +[0-9a-f]* <rsub1>:
10118 + *[0-9a-f]*:   1e 2f           rsub pc,pc
10119 + *[0-9a-f]*:   18 2c           rsub r12,r12
10120 + *[0-9a-f]*:   0a 25           rsub r5,r5
10121 + *[0-9a-f]*:   08 24           rsub r4,r4
10122 + *[0-9a-f]*:   1c 2e           rsub lr,lr
10123 + *[0-9a-f]*:   1a 2b           rsub r11,sp
10124 + *[0-9a-f]*:   08 27           rsub r7,r4
10125 + *[0-9a-f]*:   02 29           rsub r9,r1
10126 +
10127 +[0-9a-f]* <cp1>:
10128 + *[0-9a-f]*:   1e 3f           cp\.w pc,pc
10129 + *[0-9a-f]*:   18 3c           cp\.w r12,r12
10130 + *[0-9a-f]*:   0a 35           cp\.w r5,r5
10131 + *[0-9a-f]*:   08 34           cp\.w r4,r4
10132 + *[0-9a-f]*:   1c 3e           cp\.w lr,lr
10133 + *[0-9a-f]*:   04 36           cp\.w r6,r2
10134 + *[0-9a-f]*:   12 30           cp\.w r0,r9
10135 + *[0-9a-f]*:   1a 33           cp\.w r3,sp
10136 +
10137 +[0-9a-f]* <or1>:
10138 + *[0-9a-f]*:   1e 4f           or pc,pc
10139 + *[0-9a-f]*:   18 4c           or r12,r12
10140 + *[0-9a-f]*:   0a 45           or r5,r5
10141 + *[0-9a-f]*:   08 44           or r4,r4
10142 + *[0-9a-f]*:   1c 4e           or lr,lr
10143 + *[0-9a-f]*:   12 44           or r4,r9
10144 + *[0-9a-f]*:   08 4b           or r11,r4
10145 + *[0-9a-f]*:   00 44           or r4,r0
10146 +
10147 +[0-9a-f]* <eor1>:
10148 + *[0-9a-f]*:   1e 5f           eor pc,pc
10149 + *[0-9a-f]*:   18 5c           eor r12,r12
10150 + *[0-9a-f]*:   0a 55           eor r5,r5
10151 + *[0-9a-f]*:   08 54           eor r4,r4
10152 + *[0-9a-f]*:   1c 5e           eor lr,lr
10153 + *[0-9a-f]*:   16 5c           eor r12,r11
10154 + *[0-9a-f]*:   02 50           eor r0,r1
10155 + *[0-9a-f]*:   1e 55           eor r5,pc
10156 +
10157 +[0-9a-f]* <and1>:
10158 + *[0-9a-f]*:   1e 6f           and pc,pc
10159 + *[0-9a-f]*:   18 6c           and r12,r12
10160 + *[0-9a-f]*:   0a 65           and r5,r5
10161 + *[0-9a-f]*:   08 64           and r4,r4
10162 + *[0-9a-f]*:   1c 6e           and lr,lr
10163 + *[0-9a-f]*:   02 68           and r8,r1
10164 + *[0-9a-f]*:   1a 60           and r0,sp
10165 + *[0-9a-f]*:   0a 6a           and r10,r5
10166 +
10167 +[0-9a-f]* <tst>:
10168 + *[0-9a-f]*:   1e 7f           tst pc,pc
10169 + *[0-9a-f]*:   18 7c           tst r12,r12
10170 + *[0-9a-f]*:   0a 75           tst r5,r5
10171 + *[0-9a-f]*:   08 74           tst r4,r4
10172 + *[0-9a-f]*:   1c 7e           tst lr,lr
10173 + *[0-9a-f]*:   18 70           tst r0,r12
10174 + *[0-9a-f]*:   0c 7a           tst r10,r6
10175 + *[0-9a-f]*:   08 7d           tst sp,r4
10176 +
10177 +[0-9a-f]* <andn>:
10178 + *[0-9a-f]*:   1e 8f           andn pc,pc
10179 + *[0-9a-f]*:   18 8c           andn r12,r12
10180 + *[0-9a-f]*:   0a 85           andn r5,r5
10181 + *[0-9a-f]*:   08 84           andn r4,r4
10182 + *[0-9a-f]*:   1c 8e           andn lr,lr
10183 + *[0-9a-f]*:   18 89           andn r9,r12
10184 + *[0-9a-f]*:   1a 8b           andn r11,sp
10185 + *[0-9a-f]*:   0a 8c           andn r12,r5
10186 +
10187 +[0-9a-f]* <mov3>:
10188 + *[0-9a-f]*:   1e 9f           mov pc,pc
10189 + *[0-9a-f]*:   18 9c           mov r12,r12
10190 + *[0-9a-f]*:   0a 95           mov r5,r5
10191 + *[0-9a-f]*:   08 94           mov r4,r4
10192 + *[0-9a-f]*:   1c 9e           mov lr,lr
10193 + *[0-9a-f]*:   12 95           mov r5,r9
10194 + *[0-9a-f]*:   16 9b           mov r11,r11
10195 + *[0-9a-f]*:   1c 92           mov r2,lr
10196 +
10197 +[0-9a-f]* <st_w1>:
10198 + *[0-9a-f]*:   1e af           st\.w pc\+\+,pc
10199 + *[0-9a-f]*:   18 ac           st\.w r12\+\+,r12
10200 + *[0-9a-f]*:   0a a5           st\.w r5\+\+,r5
10201 + *[0-9a-f]*:   08 a4           st\.w r4\+\+,r4
10202 + *[0-9a-f]*:   1c ae           st\.w lr\+\+,lr
10203 + *[0-9a-f]*:   02 ab           st\.w r1\+\+,r11
10204 + *[0-9a-f]*:   1a a0           st\.w sp\+\+,r0
10205 + *[0-9a-f]*:   1a a1           st\.w sp\+\+,r1
10206 +
10207 +[0-9a-f]* <st_h1>:
10208 + *[0-9a-f]*:   1e bf           st\.h pc\+\+,pc
10209 + *[0-9a-f]*:   18 bc           st\.h r12\+\+,r12
10210 + *[0-9a-f]*:   0a b5           st\.h r5\+\+,r5
10211 + *[0-9a-f]*:   08 b4           st\.h r4\+\+,r4
10212 + *[0-9a-f]*:   1c be           st\.h lr\+\+,lr
10213 + *[0-9a-f]*:   18 bd           st\.h r12\+\+,sp
10214 + *[0-9a-f]*:   0e be           st\.h r7\+\+,lr
10215 + *[0-9a-f]*:   0e b4           st\.h r7\+\+,r4
10216 +
10217 +[0-9a-f]* <st_b1>:
10218 + *[0-9a-f]*:   1e cf           st\.b pc\+\+,pc
10219 + *[0-9a-f]*:   18 cc           st\.b r12\+\+,r12
10220 + *[0-9a-f]*:   0a c5           st\.b r5\+\+,r5
10221 + *[0-9a-f]*:   08 c4           st\.b r4\+\+,r4
10222 + *[0-9a-f]*:   1c ce           st\.b lr\+\+,lr
10223 + *[0-9a-f]*:   12 cd           st\.b r9\+\+,sp
10224 + *[0-9a-f]*:   02 cd           st\.b r1\+\+,sp
10225 + *[0-9a-f]*:   00 c4           st\.b r0\+\+,r4
10226 +
10227 +[0-9a-f]* <st_w2>:
10228 + *[0-9a-f]*:   1e df           st\.w --pc,pc
10229 + *[0-9a-f]*:   18 dc           st\.w --r12,r12
10230 + *[0-9a-f]*:   0a d5           st\.w --r5,r5
10231 + *[0-9a-f]*:   08 d4           st\.w --r4,r4
10232 + *[0-9a-f]*:   1c de           st\.w --lr,lr
10233 + *[0-9a-f]*:   02 d7           st\.w --r1,r7
10234 + *[0-9a-f]*:   06 d9           st\.w --r3,r9
10235 + *[0-9a-f]*:   0a d5           st\.w --r5,r5
10236 +
10237 +[0-9a-f]* <st_h2>:
10238 + *[0-9a-f]*:   1e ef           st\.h --pc,pc
10239 + *[0-9a-f]*:   18 ec           st\.h --r12,r12
10240 + *[0-9a-f]*:   0a e5           st\.h --r5,r5
10241 + *[0-9a-f]*:   08 e4           st\.h --r4,r4
10242 + *[0-9a-f]*:   1c ee           st\.h --lr,lr
10243 + *[0-9a-f]*:   0a e7           st\.h --r5,r7
10244 + *[0-9a-f]*:   10 e8           st\.h --r8,r8
10245 + *[0-9a-f]*:   0e e2           st\.h --r7,r2
10246 +
10247 +[0-9a-f]* <st_b2>:
10248 + *[0-9a-f]*:   1e ff           st\.b --pc,pc
10249 + *[0-9a-f]*:   18 fc           st\.b --r12,r12
10250 + *[0-9a-f]*:   0a f5           st\.b --r5,r5
10251 + *[0-9a-f]*:   08 f4           st\.b --r4,r4
10252 + *[0-9a-f]*:   1c fe           st\.b --lr,lr
10253 + *[0-9a-f]*:   1a fd           st\.b --sp,sp
10254 + *[0-9a-f]*:   1a fb           st\.b --sp,r11
10255 + *[0-9a-f]*:   08 f5           st\.b --r4,r5
10256 +
10257 +[0-9a-f]* <ld_w1>:
10258 + *[0-9a-f]*:   1f 0f           ld\.w pc,pc\+\+
10259 + *[0-9a-f]*:   19 0c           ld\.w r12,r12\+\+
10260 + *[0-9a-f]*:   0b 05           ld\.w r5,r5\+\+
10261 + *[0-9a-f]*:   09 04           ld\.w r4,r4\+\+
10262 + *[0-9a-f]*:   1d 0e           ld\.w lr,lr\+\+
10263 + *[0-9a-f]*:   0f 03           ld\.w r3,r7\+\+
10264 + *[0-9a-f]*:   1d 03           ld\.w r3,lr\+\+
10265 + *[0-9a-f]*:   0b 0c           ld\.w r12,r5\+\+
10266 +
10267 +[0-9a-f]* <ld_sh1>:
10268 + *[0-9a-f]*:   1f 1f           ld\.sh pc,pc\+\+
10269 + *[0-9a-f]*:   19 1c           ld\.sh r12,r12\+\+
10270 + *[0-9a-f]*:   0b 15           ld\.sh r5,r5\+\+
10271 + *[0-9a-f]*:   09 14           ld\.sh r4,r4\+\+
10272 + *[0-9a-f]*:   1d 1e           ld\.sh lr,lr\+\+
10273 + *[0-9a-f]*:   05 1b           ld\.sh r11,r2\+\+
10274 + *[0-9a-f]*:   11 12           ld\.sh r2,r8\+\+
10275 + *[0-9a-f]*:   0d 17           ld\.sh r7,r6\+\+
10276 +
10277 +[0-9a-f]* <ld_uh1>:
10278 + *[0-9a-f]*:   1f 2f           ld\.uh pc,pc\+\+
10279 + *[0-9a-f]*:   19 2c           ld\.uh r12,r12\+\+
10280 + *[0-9a-f]*:   0b 25           ld\.uh r5,r5\+\+
10281 + *[0-9a-f]*:   09 24           ld\.uh r4,r4\+\+
10282 + *[0-9a-f]*:   1d 2e           ld\.uh lr,lr\+\+
10283 + *[0-9a-f]*:   0f 26           ld\.uh r6,r7\+\+
10284 + *[0-9a-f]*:   17 2a           ld\.uh r10,r11\+\+
10285 + *[0-9a-f]*:   09 2e           ld\.uh lr,r4\+\+
10286 +
10287 +[0-9a-f]* <ld_ub1>:
10288 + *[0-9a-f]*:   1f 3f           ld\.ub pc,pc\+\+
10289 + *[0-9a-f]*:   19 3c           ld\.ub r12,r12\+\+
10290 + *[0-9a-f]*:   0b 35           ld\.ub r5,r5\+\+
10291 + *[0-9a-f]*:   09 34           ld\.ub r4,r4\+\+
10292 + *[0-9a-f]*:   1d 3e           ld\.ub lr,lr\+\+
10293 + *[0-9a-f]*:   1d 38           ld\.ub r8,lr\+\+
10294 + *[0-9a-f]*:   19 3c           ld\.ub r12,r12\+\+
10295 + *[0-9a-f]*:   15 3b           ld\.ub r11,r10\+\+
10296 +
10297 +[0-9a-f]* <ld_w2>:
10298 + *[0-9a-f]*:   1f 4f           ld\.w pc,--pc
10299 + *[0-9a-f]*:   19 4c           ld\.w r12,--r12
10300 + *[0-9a-f]*:   0b 45           ld\.w r5,--r5
10301 + *[0-9a-f]*:   09 44           ld\.w r4,--r4
10302 + *[0-9a-f]*:   1d 4e           ld\.w lr,--lr
10303 + *[0-9a-f]*:   1d 4a           ld\.w r10,--lr
10304 + *[0-9a-f]*:   13 4c           ld\.w r12,--r9
10305 + *[0-9a-f]*:   0b 46           ld\.w r6,--r5
10306 +
10307 +[0-9a-f]* <ld_sh2>:
10308 + *[0-9a-f]*:   1f 5f           ld\.sh pc,--pc
10309 + *[0-9a-f]*:   19 5c           ld\.sh r12,--r12
10310 + *[0-9a-f]*:   0b 55           ld\.sh r5,--r5
10311 + *[0-9a-f]*:   09 54           ld\.sh r4,--r4
10312 + *[0-9a-f]*:   1d 5e           ld\.sh lr,--lr
10313 + *[0-9a-f]*:   15 5f           ld\.sh pc,--r10
10314 + *[0-9a-f]*:   07 56           ld\.sh r6,--r3
10315 + *[0-9a-f]*:   0d 54           ld\.sh r4,--r6
10316 +
10317 +[0-9a-f]* <ld_uh2>:
10318 + *[0-9a-f]*:   1f 6f           ld\.uh pc,--pc
10319 + *[0-9a-f]*:   19 6c           ld\.uh r12,--r12
10320 + *[0-9a-f]*:   0b 65           ld\.uh r5,--r5
10321 + *[0-9a-f]*:   09 64           ld\.uh r4,--r4
10322 + *[0-9a-f]*:   1d 6e           ld\.uh lr,--lr
10323 + *[0-9a-f]*:   05 63           ld\.uh r3,--r2
10324 + *[0-9a-f]*:   01 61           ld\.uh r1,--r0
10325 + *[0-9a-f]*:   13 62           ld\.uh r2,--r9
10326 +
10327 +[0-9a-f]* <ld_ub2>:
10328 + *[0-9a-f]*:   1f 7f           ld\.ub pc,--pc
10329 + *[0-9a-f]*:   19 7c           ld\.ub r12,--r12
10330 + *[0-9a-f]*:   0b 75           ld\.ub r5,--r5
10331 + *[0-9a-f]*:   09 74           ld\.ub r4,--r4
10332 + *[0-9a-f]*:   1d 7e           ld\.ub lr,--lr
10333 + *[0-9a-f]*:   03 71           ld\.ub r1,--r1
10334 + *[0-9a-f]*:   0d 70           ld\.ub r0,--r6
10335 + *[0-9a-f]*:   0f 72           ld\.ub r2,--r7
10336 +
10337 +[0-9a-f]* <ld_ub3>:
10338 + *[0-9a-f]*:   1f 8f           ld\.ub pc,pc\[0x0\]
10339 + *[0-9a-f]*:   19 fc           ld\.ub r12,r12\[0x7\]
10340 + *[0-9a-f]*:   0b c5           ld\.ub r5,r5\[0x4\]
10341 + *[0-9a-f]*:   09 b4           ld\.ub r4,r4\[0x3\]
10342 + *[0-9a-f]*:   1d 9e           ld\.ub lr,lr\[0x1\]
10343 + *[0-9a-f]*:   13 e6           ld\.ub r6,r9\[0x6\]
10344 + *[0-9a-f]*:   1d c2           ld\.ub r2,lr\[0x4\]
10345 + *[0-9a-f]*:   11 81           ld\.ub r1,r8\[0x0\]
10346 +
10347 +[0-9a-f]* <sub3_sp>:
10348 + *[0-9a-f]*:   20 0d           sub sp,0
10349 + *[0-9a-f]*:   2f fd           sub sp,-4
10350 + *[0-9a-f]*:   28 0d           sub sp,-512
10351 + *[0-9a-f]*:   27 fd           sub sp,508
10352 + *[0-9a-f]*:   20 1d           sub sp,4
10353 + *[0-9a-f]*:   20 bd           sub sp,44
10354 + *[0-9a-f]*:   20 2d           sub sp,8
10355 + *[0-9a-f]*:   25 7d           sub sp,348
10356 +
10357 +[0-9a-f]* <sub3>:
10358 + *[0-9a-f]*:   20 0f           sub pc,0
10359 + *[0-9a-f]*:   2f fc           sub r12,-1
10360 + *[0-9a-f]*:   28 05           sub r5,-128
10361 + *[0-9a-f]*:   27 f4           sub r4,127
10362 + *[0-9a-f]*:   20 1e           sub lr,1
10363 + *[0-9a-f]*:   2d 76           sub r6,-41
10364 + *[0-9a-f]*:   22 54           sub r4,37
10365 + *[0-9a-f]*:   23 8c           sub r12,56
10366 +
10367 +[0-9a-f]* <mov1>:
10368 + *[0-9a-f]*:   30 0f           mov pc,0
10369 + *[0-9a-f]*:   3f fc           mov r12,-1
10370 + *[0-9a-f]*:   38 05           mov r5,-128
10371 + *[0-9a-f]*:   37 f4           mov r4,127
10372 + *[0-9a-f]*:   30 1e           mov lr,1
10373 + *[0-9a-f]*:   30 ef           mov pc,14
10374 + *[0-9a-f]*:   39 c6           mov r6,-100
10375 + *[0-9a-f]*:   38 6e           mov lr,-122
10376 +
10377 +[0-9a-f]* <lddsp>:
10378 + *[0-9a-f]*:   40 0f           lddsp pc,sp\[0x0\]
10379 + *[0-9a-f]*:   47 fc           lddsp r12,sp\[0x1fc\]
10380 + *[0-9a-f]*:   44 05           lddsp r5,sp\[0x100\]
10381 + *[0-9a-f]*:   43 f4           lddsp r4,sp\[0xfc\]
10382 + *[0-9a-f]*:   40 1e           lddsp lr,sp\[0x4\]
10383 + *[0-9a-f]*:   44 0e           lddsp lr,sp\[0x100\]
10384 + *[0-9a-f]*:   40 5c           lddsp r12,sp\[0x14\]
10385 + *[0-9a-f]*:   47 69           lddsp r9,sp\[0x1d8\]
10386 +
10387 +[0-9a-f]* <lddpc>:
10388 + *[0-9a-f]*:   48 0f           lddpc pc,[0-9a-f]* <.*>
10389 + *[0-9a-f]*:   4f f0           lddpc r0,[0-9a-f]* <.*>
10390 + *[0-9a-f]*:   4c 08           lddpc r8,[0-9a-f]* <.*>
10391 + *[0-9a-f]*:   4b f7           lddpc r7,[0-9a-f]* <.*>
10392 + *[0-9a-f]*:   48 1e           lddpc lr,[0-9a-f]* <.*>
10393 + *[0-9a-f]*:   4f 6d           lddpc sp,[0-9a-f]* <.*>
10394 + *[0-9a-f]*:   49 e6           lddpc r6,[0-9a-f]* <.*>
10395 + *[0-9a-f]*:   48 7b           lddpc r11,[0-9a-f]* <.*>
10396 +
10397 +[0-9a-f]* <stdsp>:
10398 + *[0-9a-f]*:   50 0f           stdsp sp\[0x0\],pc
10399 + *[0-9a-f]*:   57 fc           stdsp sp\[0x1fc\],r12
10400 + *[0-9a-f]*:   54 05           stdsp sp\[0x100\],r5
10401 + *[0-9a-f]*:   53 f4           stdsp sp\[0xfc\],r4
10402 + *[0-9a-f]*:   50 1e           stdsp sp\[0x4\],lr
10403 + *[0-9a-f]*:   54 cf           stdsp sp\[0x130\],pc
10404 + *[0-9a-f]*:   54 00           stdsp sp\[0x100\],r0
10405 + *[0-9a-f]*:   55 45           stdsp sp\[0x150\],r5
10406 +
10407 +[0-9a-f]* <cp2>:
10408 + *[0-9a-f]*:   58 0f           cp.w pc,0
10409 + *[0-9a-f]*:   5b fc           cp.w r12,-1
10410 + *[0-9a-f]*:   5a 05           cp.w r5,-32
10411 + *[0-9a-f]*:   59 f4           cp.w r4,31
10412 + *[0-9a-f]*:   58 1e           cp.w lr,1
10413 + *[0-9a-f]*:   58 38           cp.w r8,3
10414 + *[0-9a-f]*:   59 0e           cp.w lr,16
10415 + *[0-9a-f]*:   5a 67           cp.w r7,-26
10416 +
10417 +[0-9a-f]* <acr>:
10418 + *[0-9a-f]*:   5c 0f           acr pc
10419 + *[0-9a-f]*:   5c 0c           acr r12
10420 + *[0-9a-f]*:   5c 05           acr r5
10421 + *[0-9a-f]*:   5c 04           acr r4
10422 + *[0-9a-f]*:   5c 0e           acr lr
10423 + *[0-9a-f]*:   5c 02           acr r2
10424 + *[0-9a-f]*:   5c 0c           acr r12
10425 + *[0-9a-f]*:   5c 0f           acr pc
10426 +
10427 +[0-9a-f]* <scr>:
10428 + *[0-9a-f]*:   5c 1f           scr pc
10429 + *[0-9a-f]*:   5c 1c           scr r12
10430 + *[0-9a-f]*:   5c 15           scr r5
10431 + *[0-9a-f]*:   5c 14           scr r4
10432 + *[0-9a-f]*:   5c 1e           scr lr
10433 + *[0-9a-f]*:   5c 1f           scr pc
10434 + *[0-9a-f]*:   5c 16           scr r6
10435 + *[0-9a-f]*:   5c 11           scr r1
10436 +
10437 +[0-9a-f]* <cpc0>:
10438 + *[0-9a-f]*:   5c 2f           cpc pc
10439 + *[0-9a-f]*:   5c 2c           cpc r12
10440 + *[0-9a-f]*:   5c 25           cpc r5
10441 + *[0-9a-f]*:   5c 24           cpc r4
10442 + *[0-9a-f]*:   5c 2e           cpc lr
10443 + *[0-9a-f]*:   5c 2f           cpc pc
10444 + *[0-9a-f]*:   5c 24           cpc r4
10445 + *[0-9a-f]*:   5c 29           cpc r9
10446 +
10447 +[0-9a-f]* <neg>:
10448 + *[0-9a-f]*:   5c 3f           neg pc
10449 + *[0-9a-f]*:   5c 3c           neg r12
10450 + *[0-9a-f]*:   5c 35           neg r5
10451 + *[0-9a-f]*:   5c 34           neg r4
10452 + *[0-9a-f]*:   5c 3e           neg lr
10453 + *[0-9a-f]*:   5c 37           neg r7
10454 + *[0-9a-f]*:   5c 31           neg r1
10455 + *[0-9a-f]*:   5c 39           neg r9
10456 +
10457 +[0-9a-f]* <abs>:
10458 + *[0-9a-f]*:   5c 4f           abs pc
10459 + *[0-9a-f]*:   5c 4c           abs r12
10460 + *[0-9a-f]*:   5c 45           abs r5
10461 + *[0-9a-f]*:   5c 44           abs r4
10462 + *[0-9a-f]*:   5c 4e           abs lr
10463 + *[0-9a-f]*:   5c 46           abs r6
10464 + *[0-9a-f]*:   5c 46           abs r6
10465 + *[0-9a-f]*:   5c 44           abs r4
10466 +
10467 +[0-9a-f]* <castu_b>:
10468 + *[0-9a-f]*:   5c 5f           castu\.b pc
10469 + *[0-9a-f]*:   5c 5c           castu\.b r12
10470 + *[0-9a-f]*:   5c 55           castu\.b r5
10471 + *[0-9a-f]*:   5c 54           castu\.b r4
10472 + *[0-9a-f]*:   5c 5e           castu\.b lr
10473 + *[0-9a-f]*:   5c 57           castu\.b r7
10474 + *[0-9a-f]*:   5c 5d           castu\.b sp
10475 + *[0-9a-f]*:   5c 59           castu\.b r9
10476 +
10477 +[0-9a-f]* <casts_b>:
10478 + *[0-9a-f]*:   5c 6f           casts\.b pc
10479 + *[0-9a-f]*:   5c 6c           casts\.b r12
10480 + *[0-9a-f]*:   5c 65           casts\.b r5
10481 + *[0-9a-f]*:   5c 64           casts\.b r4
10482 + *[0-9a-f]*:   5c 6e           casts\.b lr
10483 + *[0-9a-f]*:   5c 6b           casts\.b r11
10484 + *[0-9a-f]*:   5c 61           casts\.b r1
10485 + *[0-9a-f]*:   5c 6a           casts\.b r10
10486 +
10487 +[0-9a-f]* <castu_h>:
10488 + *[0-9a-f]*:   5c 7f           castu\.h pc
10489 + *[0-9a-f]*:   5c 7c           castu\.h r12
10490 + *[0-9a-f]*:   5c 75           castu\.h r5
10491 + *[0-9a-f]*:   5c 74           castu\.h r4
10492 + *[0-9a-f]*:   5c 7e           castu\.h lr
10493 + *[0-9a-f]*:   5c 7a           castu\.h r10
10494 + *[0-9a-f]*:   5c 7b           castu\.h r11
10495 + *[0-9a-f]*:   5c 71           castu\.h r1
10496 +
10497 +[0-9a-f]* <casts_h>:
10498 + *[0-9a-f]*:   5c 8f           casts\.h pc
10499 + *[0-9a-f]*:   5c 8c           casts\.h r12
10500 + *[0-9a-f]*:   5c 85           casts\.h r5
10501 + *[0-9a-f]*:   5c 84           casts\.h r4
10502 + *[0-9a-f]*:   5c 8e           casts\.h lr
10503 + *[0-9a-f]*:   5c 80           casts\.h r0
10504 + *[0-9a-f]*:   5c 85           casts\.h r5
10505 + *[0-9a-f]*:   5c 89           casts\.h r9
10506 +
10507 +[0-9a-f]* <brev>:
10508 + *[0-9a-f]*:   5c 9f           brev pc
10509 + *[0-9a-f]*:   5c 9c           brev r12
10510 + *[0-9a-f]*:   5c 95           brev r5
10511 + *[0-9a-f]*:   5c 94           brev r4
10512 + *[0-9a-f]*:   5c 9e           brev lr
10513 + *[0-9a-f]*:   5c 95           brev r5
10514 + *[0-9a-f]*:   5c 9a           brev r10
10515 + *[0-9a-f]*:   5c 98           brev r8
10516 +
10517 +[0-9a-f]* <swap_h>:
10518 + *[0-9a-f]*:   5c af           swap\.h pc
10519 + *[0-9a-f]*:   5c ac           swap\.h r12
10520 + *[0-9a-f]*:   5c a5           swap\.h r5
10521 + *[0-9a-f]*:   5c a4           swap\.h r4
10522 + *[0-9a-f]*:   5c ae           swap\.h lr
10523 + *[0-9a-f]*:   5c a7           swap\.h r7
10524 + *[0-9a-f]*:   5c a0           swap\.h r0
10525 + *[0-9a-f]*:   5c a8           swap\.h r8
10526 +
10527 +[0-9a-f]* <swap_b>:
10528 + *[0-9a-f]*:   5c bf           swap\.b pc
10529 + *[0-9a-f]*:   5c bc           swap\.b r12
10530 + *[0-9a-f]*:   5c b5           swap\.b r5
10531 + *[0-9a-f]*:   5c b4           swap\.b r4
10532 + *[0-9a-f]*:   5c be           swap\.b lr
10533 + *[0-9a-f]*:   5c ba           swap\.b r10
10534 + *[0-9a-f]*:   5c bc           swap\.b r12
10535 + *[0-9a-f]*:   5c b1           swap\.b r1
10536 +
10537 +[0-9a-f]* <swap_bh>:
10538 + *[0-9a-f]*:   5c cf           swap\.bh pc
10539 + *[0-9a-f]*:   5c cc           swap\.bh r12
10540 + *[0-9a-f]*:   5c c5           swap\.bh r5
10541 + *[0-9a-f]*:   5c c4           swap\.bh r4
10542 + *[0-9a-f]*:   5c ce           swap\.bh lr
10543 + *[0-9a-f]*:   5c c9           swap\.bh r9
10544 + *[0-9a-f]*:   5c c4           swap\.bh r4
10545 + *[0-9a-f]*:   5c c1           swap\.bh r1
10546 +
10547 +[0-9a-f]* <One_s_compliment>:
10548 + *[0-9a-f]*:   5c df           com pc
10549 + *[0-9a-f]*:   5c dc           com r12
10550 + *[0-9a-f]*:   5c d5           com r5
10551 + *[0-9a-f]*:   5c d4           com r4
10552 + *[0-9a-f]*:   5c de           com lr
10553 + *[0-9a-f]*:   5c d2           com r2
10554 + *[0-9a-f]*:   5c d2           com r2
10555 + *[0-9a-f]*:   5c d7           com r7
10556 +
10557 +[0-9a-f]* <tnbz>:
10558 + *[0-9a-f]*:   5c ef           tnbz pc
10559 + *[0-9a-f]*:   5c ec           tnbz r12
10560 + *[0-9a-f]*:   5c e5           tnbz r5
10561 + *[0-9a-f]*:   5c e4           tnbz r4
10562 + *[0-9a-f]*:   5c ee           tnbz lr
10563 + *[0-9a-f]*:   5c e8           tnbz r8
10564 + *[0-9a-f]*:   5c ec           tnbz r12
10565 + *[0-9a-f]*:   5c ef           tnbz pc
10566 +
10567 +[0-9a-f]* <rol>:
10568 + *[0-9a-f]*:   5c ff           rol pc
10569 + *[0-9a-f]*:   5c fc           rol r12
10570 + *[0-9a-f]*:   5c f5           rol r5
10571 + *[0-9a-f]*:   5c f4           rol r4
10572 + *[0-9a-f]*:   5c fe           rol lr
10573 + *[0-9a-f]*:   5c fa           rol r10
10574 + *[0-9a-f]*:   5c f9           rol r9
10575 + *[0-9a-f]*:   5c f5           rol r5
10576 +
10577 +[0-9a-f]* <ror>:
10578 + *[0-9a-f]*:   5d 0f           ror pc
10579 + *[0-9a-f]*:   5d 0c           ror r12
10580 + *[0-9a-f]*:   5d 05           ror r5
10581 + *[0-9a-f]*:   5d 04           ror r4
10582 + *[0-9a-f]*:   5d 0e           ror lr
10583 + *[0-9a-f]*:   5d 08           ror r8
10584 + *[0-9a-f]*:   5d 04           ror r4
10585 + *[0-9a-f]*:   5d 07           ror r7
10586 +
10587 +[0-9a-f]* <icall>:
10588 + *[0-9a-f]*:   5d 1f           icall pc
10589 + *[0-9a-f]*:   5d 1c           icall r12
10590 + *[0-9a-f]*:   5d 15           icall r5
10591 + *[0-9a-f]*:   5d 14           icall r4
10592 + *[0-9a-f]*:   5d 1e           icall lr
10593 + *[0-9a-f]*:   5d 13           icall r3
10594 + *[0-9a-f]*:   5d 11           icall r1
10595 + *[0-9a-f]*:   5d 13           icall r3
10596 +
10597 +[0-9a-f]* <mustr>:
10598 + *[0-9a-f]*:   5d 2f           mustr pc
10599 + *[0-9a-f]*:   5d 2c           mustr r12
10600 + *[0-9a-f]*:   5d 25           mustr r5
10601 + *[0-9a-f]*:   5d 24           mustr r4
10602 + *[0-9a-f]*:   5d 2e           mustr lr
10603 + *[0-9a-f]*:   5d 21           mustr r1
10604 + *[0-9a-f]*:   5d 24           mustr r4
10605 + *[0-9a-f]*:   5d 2c           mustr r12
10606 +
10607 +[0-9a-f]* <musfr>:
10608 + *[0-9a-f]*:   5d 3f           musfr pc
10609 + *[0-9a-f]*:   5d 3c           musfr r12
10610 + *[0-9a-f]*:   5d 35           musfr r5
10611 + *[0-9a-f]*:   5d 34           musfr r4
10612 + *[0-9a-f]*:   5d 3e           musfr lr
10613 + *[0-9a-f]*:   5d 3b           musfr r11
10614 + *[0-9a-f]*:   5d 3c           musfr r12
10615 + *[0-9a-f]*:   5d 32           musfr r2
10616 +
10617 +[0-9a-f]* <ret_cond>:
10618 + *[0-9a-f]*:   5e 0f           reteq 1
10619 + *[0-9a-f]*:   5e fc           retal r12
10620 + *[0-9a-f]*:   5e 85           retls r5
10621 + *[0-9a-f]*:   5e 74           retpl r4
10622 + *[0-9a-f]*:   5e 1e           retne -1
10623 + *[0-9a-f]*:   5e 90           retgt r0
10624 + *[0-9a-f]*:   5e 9c           retgt r12
10625 + *[0-9a-f]*:   5e 4a           retge r10
10626 +
10627 +[0-9a-f]* <sr_cond>:
10628 + *[0-9a-f]*:   5f 0f           sreq pc
10629 + *[0-9a-f]*:   5f fc           sral r12
10630 + *[0-9a-f]*:   5f 85           srls r5
10631 + *[0-9a-f]*:   5f 74           srpl r4
10632 + *[0-9a-f]*:   5f 1e           srne lr
10633 + *[0-9a-f]*:   5f 50           srlt r0
10634 + *[0-9a-f]*:   5f fd           sral sp
10635 + *[0-9a-f]*:   5f 49           srge r9
10636 +
10637 +[0-9a-f]* <ld_w3>:
10638 + *[0-9a-f]*:   7e 0f           ld\.w pc,pc\[0x0\]
10639 + *[0-9a-f]*:   79 fc           ld\.w r12,r12\[0x7c\]
10640 + *[0-9a-f]*:   6b 05           ld\.w r5,r5\[0x40\]
10641 + *[0-9a-f]*:   68 f4           ld\.w r4,r4\[0x3c\]
10642 + *[0-9a-f]*:   7c 1e           ld\.w lr,lr\[0x4\]
10643 + *[0-9a-f]*:   64 dd           ld\.w sp,r2\[0x34\]
10644 + *[0-9a-f]*:   62 29           ld\.w r9,r1\[0x8\]
10645 + *[0-9a-f]*:   7a f5           ld\.w r5,sp\[0x3c\]
10646 +
10647 +[0-9a-f]* <ld_sh3>:
10648 + *[0-9a-f]*:   9e 0f           ld\.sh pc,pc\[0x0\]
10649 + *[0-9a-f]*:   98 7c           ld\.sh r12,r12\[0xe\]
10650 + *[0-9a-f]*:   8a 45           ld\.sh r5,r5\[0x8\]
10651 + *[0-9a-f]*:   88 34           ld\.sh r4,r4\[0x6\]
10652 + *[0-9a-f]*:   9c 1e           ld\.sh lr,lr\[0x2\]
10653 + *[0-9a-f]*:   84 44           ld\.sh r4,r2\[0x8\]
10654 + *[0-9a-f]*:   9c 5d           ld\.sh sp,lr\[0xa\]
10655 + *[0-9a-f]*:   96 12           ld\.sh r2,r11\[0x2\]
10656 +
10657 +[0-9a-f]* <ld_uh3>:
10658 + *[0-9a-f]*:   9e 8f           ld\.uh pc,pc\[0x0\]
10659 + *[0-9a-f]*:   98 fc           ld\.uh r12,r12\[0xe\]
10660 + *[0-9a-f]*:   8a c5           ld\.uh r5,r5\[0x8\]
10661 + *[0-9a-f]*:   88 b4           ld\.uh r4,r4\[0x6\]
10662 + *[0-9a-f]*:   9c 9e           ld\.uh lr,lr\[0x2\]
10663 + *[0-9a-f]*:   80 da           ld\.uh r10,r0\[0xa\]
10664 + *[0-9a-f]*:   96 c8           ld\.uh r8,r11\[0x8\]
10665 + *[0-9a-f]*:   84 ea           ld\.uh r10,r2\[0xc\]
10666 +
10667 +[0-9a-f]* <st_w3>:
10668 + *[0-9a-f]*:   9f 0f           st\.w pc\[0x0\],pc
10669 + *[0-9a-f]*:   99 fc           st\.w r12\[0x3c\],r12
10670 + *[0-9a-f]*:   8b 85           st\.w r5\[0x20\],r5
10671 + *[0-9a-f]*:   89 74           st\.w r4\[0x1c\],r4
10672 + *[0-9a-f]*:   9d 1e           st\.w lr\[0x4\],lr
10673 + *[0-9a-f]*:   8f bb           st\.w r7\[0x2c\],r11
10674 + *[0-9a-f]*:   85 66           st\.w r2\[0x18\],r6
10675 + *[0-9a-f]*:   89 39           st\.w r4\[0xc\],r9
10676 +
10677 +[0-9a-f]* <st_h3>:
10678 + *[0-9a-f]*:   be 0f           st\.h pc\[0x0\],pc
10679 + *[0-9a-f]*:   b8 7c           st\.h r12\[0xe\],r12
10680 + *[0-9a-f]*:   aa 45           st\.h r5\[0x8\],r5
10681 + *[0-9a-f]*:   a8 34           st\.h r4\[0x6\],r4
10682 + *[0-9a-f]*:   bc 1e           st\.h lr\[0x2\],lr
10683 + *[0-9a-f]*:   bc 5c           st\.h lr\[0xa\],r12
10684 + *[0-9a-f]*:   ac 20           st\.h r6\[0x4\],r0
10685 + *[0-9a-f]*:   aa 6d           st\.h r5\[0xc\],sp
10686 +
10687 +[0-9a-f]* <st_b3>:
10688 + *[0-9a-f]*:   be 8f           st\.b pc\[0x0\],pc
10689 + *[0-9a-f]*:   b8 fc           st\.b r12\[0x7\],r12
10690 + *[0-9a-f]*:   aa c5           st\.b r5\[0x4\],r5
10691 + *[0-9a-f]*:   a8 b4           st\.b r4\[0x3\],r4
10692 + *[0-9a-f]*:   bc 9e           st\.b lr\[0x1\],lr
10693 + *[0-9a-f]*:   b8 e9           st\.b r12\[0x6\],r9
10694 + *[0-9a-f]*:   a4 be           st\.b r2\[0x3\],lr
10695 + *[0-9a-f]*:   a2 bb           st\.b r1\[0x3\],r11
10696 +
10697 +[0-9a-f]* <ldd>:
10698 + *[0-9a-f]*:   bf 00           ld\.d r0,pc
10699 + *[0-9a-f]*:   b9 0e           ld\.d lr,r12
10700 + *[0-9a-f]*:   ab 08           ld\.d r8,r5
10701 + *[0-9a-f]*:   a9 06           ld\.d r6,r4
10702 + *[0-9a-f]*:   bd 02           ld\.d r2,lr
10703 + *[0-9a-f]*:   af 0e           ld\.d lr,r7
10704 + *[0-9a-f]*:   a9 04           ld\.d r4,r4
10705 + *[0-9a-f]*:   bf 0e           ld\.d lr,pc
10706 +
10707 +[0-9a-f]* <ldd_postinc>:
10708 + *[0-9a-f]*:   bf 01           ld\.d r0,pc\+\+
10709 + *[0-9a-f]*:   b9 0f           ld\.d lr,r12\+\+
10710 + *[0-9a-f]*:   ab 09           ld\.d r8,r5\+\+
10711 + *[0-9a-f]*:   a9 07           ld\.d r6,r4\+\+
10712 + *[0-9a-f]*:   bd 03           ld\.d r2,lr\+\+
10713 + *[0-9a-f]*:   ab 0f           ld\.d lr,r5\+\+
10714 + *[0-9a-f]*:   b7 0d           ld\.d r12,r11\+\+
10715 + *[0-9a-f]*:   b9 03           ld\.d r2,r12\+\+
10716 +
10717 +[0-9a-f]* <ldd_predec>:
10718 + *[0-9a-f]*:   bf 10           ld\.d r0,--pc
10719 + *[0-9a-f]*:   b9 1e           ld\.d lr,--r12
10720 + *[0-9a-f]*:   ab 18           ld\.d r8,--r5
10721 + *[0-9a-f]*:   a9 16           ld\.d r6,--r4
10722 + *[0-9a-f]*:   bd 12           ld\.d r2,--lr
10723 + *[0-9a-f]*:   a1 18           ld\.d r8,--r0
10724 + *[0-9a-f]*:   bf 1a           ld\.d r10,--pc
10725 + *[0-9a-f]*:   a9 12           ld\.d r2,--r4
10726 +
10727 +[0-9a-f]* <std>:
10728 + *[0-9a-f]*:   bf 11           st\.d pc,r0
10729 + *[0-9a-f]*:   b9 1f           st\.d r12,lr
10730 + *[0-9a-f]*:   ab 19           st\.d r5,r8
10731 + *[0-9a-f]*:   a9 17           st\.d r4,r6
10732 + *[0-9a-f]*:   bd 13           st\.d lr,r2
10733 + *[0-9a-f]*:   a1 1d           st\.d r0,r12
10734 + *[0-9a-f]*:   bb 15           st\.d sp,r4
10735 + *[0-9a-f]*:   b9 1d           st\.d r12,r12
10736 +
10737 +[0-9a-f]* <std_postinc>:
10738 + *[0-9a-f]*:   bf 20           st\.d pc\+\+,r0
10739 + *[0-9a-f]*:   b9 2e           st\.d r12\+\+,lr
10740 + *[0-9a-f]*:   ab 28           st\.d r5\+\+,r8
10741 + *[0-9a-f]*:   a9 26           st\.d r4\+\+,r6
10742 + *[0-9a-f]*:   bd 22           st\.d lr\+\+,r2
10743 + *[0-9a-f]*:   bb 26           st\.d sp\+\+,r6
10744 + *[0-9a-f]*:   b5 26           st\.d r10\+\+,r6
10745 + *[0-9a-f]*:   af 22           st\.d r7\+\+,r2
10746 +
10747 +[0-9a-f]* <std_predec>:
10748 + *[0-9a-f]*:   bf 21           st\.d --pc,r0
10749 + *[0-9a-f]*:   b9 2f           st\.d --r12,lr
10750 + *[0-9a-f]*:   ab 29           st\.d --r5,r8
10751 + *[0-9a-f]*:   a9 27           st\.d --r4,r6
10752 + *[0-9a-f]*:   bd 23           st\.d --lr,r2
10753 + *[0-9a-f]*:   a7 27           st\.d --r3,r6
10754 + *[0-9a-f]*:   bd 23           st\.d --lr,r2
10755 + *[0-9a-f]*:   a1 25           st\.d --r0,r4
10756 +
10757 +[0-9a-f]* <mul>:
10758 + *[0-9a-f]*:   bf 3f           mul pc,pc
10759 + *[0-9a-f]*:   b9 3c           mul r12,r12
10760 + *[0-9a-f]*:   ab 35           mul r5,r5
10761 + *[0-9a-f]*:   a9 34           mul r4,r4
10762 + *[0-9a-f]*:   bd 3e           mul lr,lr
10763 + *[0-9a-f]*:   bd 3a           mul r10,lr
10764 + *[0-9a-f]*:   b1 30           mul r0,r8
10765 + *[0-9a-f]*:   ab 38           mul r8,r5
10766 +
10767 +[0-9a-f]* <asr_imm5>:
10768 + *[0-9a-f]*:   a1 4f           asr pc,0x0
10769 + *[0-9a-f]*:   bf 5c           asr r12,0x1f
10770 + *[0-9a-f]*:   b1 45           asr r5,0x10
10771 + *[0-9a-f]*:   af 54           asr r4,0xf
10772 + *[0-9a-f]*:   a1 5e           asr lr,0x1
10773 + *[0-9a-f]*:   b7 56           asr r6,0x17
10774 + *[0-9a-f]*:   b3 46           asr r6,0x12
10775 + *[0-9a-f]*:   a9 45           asr r5,0x8
10776 +
10777 +[0-9a-f]* <lsl_imm5>:
10778 + *[0-9a-f]*:   a1 6f           lsl pc,0x0
10779 + *[0-9a-f]*:   bf 7c           lsl r12,0x1f
10780 + *[0-9a-f]*:   b1 65           lsl r5,0x10
10781 + *[0-9a-f]*:   af 74           lsl r4,0xf
10782 + *[0-9a-f]*:   a1 7e           lsl lr,0x1
10783 + *[0-9a-f]*:   ad 7c           lsl r12,0xd
10784 + *[0-9a-f]*:   b1 66           lsl r6,0x10
10785 + *[0-9a-f]*:   b9 71           lsl r1,0x19
10786 +
10787 +[0-9a-f]* <lsr_imm5>:
10788 + *[0-9a-f]*:   a1 8f           lsr pc,0x0
10789 + *[0-9a-f]*:   bf 9c           lsr r12,0x1f
10790 + *[0-9a-f]*:   b1 85           lsr r5,0x10
10791 + *[0-9a-f]*:   af 94           lsr r4,0xf
10792 + *[0-9a-f]*:   a1 9e           lsr lr,0x1
10793 + *[0-9a-f]*:   a1 90           lsr r0,0x1
10794 + *[0-9a-f]*:   ab 88           lsr r8,0xa
10795 + *[0-9a-f]*:   bb 87           lsr r7,0x1a
10796 +
10797 +[0-9a-f]* <sbr>:
10798 + *[0-9a-f]*:   a1 af           sbr pc,0x0
10799 + *[0-9a-f]*:   bf bc           sbr r12,0x1f
10800 + *[0-9a-f]*:   b1 a5           sbr r5,0x10
10801 + *[0-9a-f]*:   af b4           sbr r4,0xf
10802 + *[0-9a-f]*:   a1 be           sbr lr,0x1
10803 + *[0-9a-f]*:   bf b8           sbr r8,0x1f
10804 + *[0-9a-f]*:   b7 a6           sbr r6,0x16
10805 + *[0-9a-f]*:   b7 b1           sbr r1,0x17
10806 +
10807 +[0-9a-f]* <cbr>:
10808 + *[0-9a-f]*:   a1 cf           cbr pc,0x0
10809 + *[0-9a-f]*:   bf dc           cbr r12,0x1f
10810 + *[0-9a-f]*:   b1 c5           cbr r5,0x10
10811 + *[0-9a-f]*:   af d4           cbr r4,0xf
10812 + *[0-9a-f]*:   a1 de           cbr lr,0x1
10813 + *[0-9a-f]*:   ab cc           cbr r12,0xa
10814 + *[0-9a-f]*:   b7 c7           cbr r7,0x16
10815 + *[0-9a-f]*:   a9 d8           cbr r8,0x9
10816 +
10817 +[0-9a-f]* <brc1>:
10818 + *[0-9a-f]*:   c0 00           breq [0-9a-f]* <.*>
10819 + *[0-9a-f]*:   cf f7           brpl [0-9a-f]* <.*>
10820 + *[0-9a-f]*:   c8 04           brge [0-9a-f]* <.*>
10821 + *[0-9a-f]*:   c7 f3           brcs [0-9a-f]* <.*>
10822 + *[0-9a-f]*:   c0 11           brne [0-9a-f]* <.*>
10823 + *[0-9a-f]*:   c7 33           brcs [0-9a-f]* <.*>
10824 + *[0-9a-f]*:   cf 70           breq [0-9a-f]* <.*>
10825 + *[0-9a-f]*:   c0 60           breq [0-9a-f]* <.*>
10826 +
10827 +[0-9a-f]* <rjmp>:
10828 + *[0-9a-f]*:   c0 08           rjmp [0-9a-f]* <.*>
10829 + *[0-9a-f]*:   cf fb           rjmp [0-9a-f]* <.*>
10830 + *[0-9a-f]*:   c0 0a           rjmp [0-9a-f]* <.*>
10831 + *[0-9a-f]*:   cf f9           rjmp [0-9a-f]* <.*>
10832 + *[0-9a-f]*:   c0 18           rjmp [0-9a-f]* <.*>
10833 + *[0-9a-f]*:   c1 fa           rjmp [0-9a-f]* <.*>
10834 + *[0-9a-f]*:   c0 78           rjmp [0-9a-f]* <.*>
10835 + *[0-9a-f]*:   cf ea           rjmp [0-9a-f]* <.*>
10836 +
10837 +[0-9a-f]* <rcall1>:
10838 + *[0-9a-f]*:   c0 0c           rcall [0-9a-f]* <.*>
10839 + *[0-9a-f]*:   cf ff           rcall [0-9a-f]* <.*>
10840 + *[0-9a-f]*:   c0 0e           rcall [0-9a-f]* <.*>
10841 + *[0-9a-f]*:   cf fd           rcall [0-9a-f]* <.*>
10842 + *[0-9a-f]*:   c0 1c           rcall [0-9a-f]* <.*>
10843 + *[0-9a-f]*:   c6 cc           rcall [0-9a-f]* <.*>
10844 + *[0-9a-f]*:   cf 7e           rcall [0-9a-f]* <.*>
10845 + *[0-9a-f]*:   c1 ae           rcall [0-9a-f]* <.*>
10846 +
10847 +[0-9a-f]* <acall>:
10848 + *[0-9a-f]*:   d0 00           acall 0x0
10849 + *[0-9a-f]*:   df f0           acall 0x3fc
10850 + *[0-9a-f]*:   d8 00           acall 0x200
10851 + *[0-9a-f]*:   d7 f0           acall 0x1fc
10852 + *[0-9a-f]*:   d0 10           acall 0x4
10853 + *[0-9a-f]*:   d5 90           acall 0x164
10854 + *[0-9a-f]*:   d4 c0           acall 0x130
10855 + *[0-9a-f]*:   d2 b0           acall 0xac
10856 +
10857 +[0-9a-f]* <scall>:
10858 + *[0-9a-f]*:   d7 33           scall
10859 + *[0-9a-f]*:   d7 33           scall
10860 + *[0-9a-f]*:   d7 33           scall
10861 + *[0-9a-f]*:   d7 33           scall
10862 + *[0-9a-f]*:   d7 33           scall
10863 + *[0-9a-f]*:   d7 33           scall
10864 + *[0-9a-f]*:   d7 33           scall
10865 + *[0-9a-f]*:   d7 33           scall
10866 +
10867 +[0-9a-f]* <popm>:
10868 + *[0-9a-f]*:   d8 02           popm pc
10869 + *[0-9a-f]*:   dd fa           popm r0-r11,pc,r12=-1
10870 + *[0-9a-f]*:   d4 02           popm lr
10871 + *[0-9a-f]*:   db fa           popm r0-r11,pc,r12=1
10872 + *[0-9a-f]*:   d0 12           popm r0-r3
10873 + *[0-9a-f]*:   d8 e2           popm r4-r10,pc
10874 + *[0-9a-f]*:   d9 1a           popm r0-r3,r11,pc,r12=0
10875 + *[0-9a-f]*:   d7 b2           popm r0-r7,r10-r12,lr
10876 +
10877 +[0-9a-f]* <pushm>:
10878 + *[0-9a-f]*:   d8 01           pushm pc
10879 + *[0-9a-f]*:   df f1           pushm r0-r12,lr-pc
10880 + *[0-9a-f]*:   d8 01           pushm pc
10881 + *[0-9a-f]*:   d7 f1           pushm r0-r12,lr
10882 + *[0-9a-f]*:   d0 11           pushm r0-r3
10883 + *[0-9a-f]*:   dc c1           pushm r8-r10,lr-pc
10884 + *[0-9a-f]*:   d0 91           pushm r0-r3,r10
10885 + *[0-9a-f]*:   d2 41           pushm r8-r9,r12
10886 +
10887 +[0-9a-f]* <popm_n>:
10888 +.*
10889 +.*
10890 +.*
10891 +.*
10892 +.*
10893 +.*
10894 +.*
10895 +.*
10896 +
10897 +[0-9a-f]* <pushm_n>:
10898 +.*
10899 +.*
10900 +.*
10901 +.*
10902 +.*
10903 +.*
10904 +.*
10905 +.*
10906 +
10907 +[0-9a-f]* <csrfcz>:
10908 + *[0-9a-f]*:   d0 03           csrfcz 0x0
10909 + *[0-9a-f]*:   d1 f3           csrfcz 0x1f
10910 + *[0-9a-f]*:   d1 03           csrfcz 0x10
10911 + *[0-9a-f]*:   d0 f3           csrfcz 0xf
10912 + *[0-9a-f]*:   d0 13           csrfcz 0x1
10913 + *[0-9a-f]*:   d0 53           csrfcz 0x5
10914 + *[0-9a-f]*:   d0 d3           csrfcz 0xd
10915 + *[0-9a-f]*:   d1 73           csrfcz 0x17
10916 +
10917 +[0-9a-f]* <ssrf>:
10918 + *[0-9a-f]*:   d2 03           ssrf 0x0
10919 + *[0-9a-f]*:   d3 f3           ssrf 0x1f
10920 + *[0-9a-f]*:   d3 03           ssrf 0x10
10921 + *[0-9a-f]*:   d2 f3           ssrf 0xf
10922 + *[0-9a-f]*:   d2 13           ssrf 0x1
10923 + *[0-9a-f]*:   d3 d3           ssrf 0x1d
10924 + *[0-9a-f]*:   d2 d3           ssrf 0xd
10925 + *[0-9a-f]*:   d2 d3           ssrf 0xd
10926 +
10927 +[0-9a-f]* <csrf>:
10928 + *[0-9a-f]*:   d4 03           csrf 0x0
10929 + *[0-9a-f]*:   d5 f3           csrf 0x1f
10930 + *[0-9a-f]*:   d5 03           csrf 0x10
10931 + *[0-9a-f]*:   d4 f3           csrf 0xf
10932 + *[0-9a-f]*:   d4 13           csrf 0x1
10933 + *[0-9a-f]*:   d4 a3           csrf 0xa
10934 + *[0-9a-f]*:   d4 f3           csrf 0xf
10935 + *[0-9a-f]*:   d4 b3           csrf 0xb
10936 +
10937 +[0-9a-f]* <rete>:
10938 + *[0-9a-f]*:   d6 03           rete
10939 +
10940 +[0-9a-f]* <rets>:
10941 + *[0-9a-f]*:   d6 13           rets
10942 +
10943 +[0-9a-f]* <retd>:
10944 + *[0-9a-f]*:   d6 23           retd
10945 +
10946 +[0-9a-f]* <retj>:
10947 + *[0-9a-f]*:   d6 33           retj
10948 +
10949 +[0-9a-f]* <tlbr>:
10950 + *[0-9a-f]*:   d6 43           tlbr
10951 +
10952 +[0-9a-f]* <tlbs>:
10953 + *[0-9a-f]*:   d6 53           tlbs
10954 +
10955 +[0-9a-f]* <tlbw>:
10956 + *[0-9a-f]*:   d6 63           tlbw
10957 +
10958 +[0-9a-f]* <breakpoint>:
10959 + *[0-9a-f]*:   d6 73           breakpoint
10960 +
10961 +[0-9a-f]* <incjosp>:
10962 + *[0-9a-f]*:   d6 83           incjosp 1
10963 + *[0-9a-f]*:   d6 93           incjosp 2
10964 + *[0-9a-f]*:   d6 a3           incjosp 3
10965 + *[0-9a-f]*:   d6 b3           incjosp 4
10966 + *[0-9a-f]*:   d6 c3           incjosp -4
10967 + *[0-9a-f]*:   d6 d3           incjosp -3
10968 + *[0-9a-f]*:   d6 e3           incjosp -2
10969 + *[0-9a-f]*:   d6 f3           incjosp -1
10970 +
10971 +[0-9a-f]* <nop>:
10972 + *[0-9a-f]*:   d7 03           nop
10973 +
10974 +[0-9a-f]* <popjc>:
10975 + *[0-9a-f]*:   d7 13           popjc
10976 +
10977 +[0-9a-f]* <pushjc>:
10978 + *[0-9a-f]*:   d7 23           pushjc
10979 +
10980 +[0-9a-f]* <add2>:
10981 + *[0-9a-f]*:   fe 0f 00 0f     add pc,pc,pc
10982 + *[0-9a-f]*:   f8 0c 00 3c     add r12,r12,r12<<0x3
10983 + *[0-9a-f]*:   ea 05 00 25     add r5,r5,r5<<0x2
10984 + *[0-9a-f]*:   e8 04 00 14     add r4,r4,r4<<0x1
10985 + *[0-9a-f]*:   fc 0e 00 1e     add lr,lr,lr<<0x1
10986 + *[0-9a-f]*:   f8 00 00 10     add r0,r12,r0<<0x1
10987 + *[0-9a-f]*:   f8 04 00 09     add r9,r12,r4
10988 + *[0-9a-f]*:   f8 07 00 2c     add r12,r12,r7<<0x2
10989 +
10990 +[0-9a-f]* <sub2>:
10991 + *[0-9a-f]*:   fe 0f 01 0f     sub pc,pc,pc
10992 + *[0-9a-f]*:   f8 0c 01 3c     sub r12,r12,r12<<0x3
10993 + *[0-9a-f]*:   ea 05 01 25     sub r5,r5,r5<<0x2
10994 + *[0-9a-f]*:   e8 04 01 14     sub r4,r4,r4<<0x1
10995 + *[0-9a-f]*:   fc 0e 01 1e     sub lr,lr,lr<<0x1
10996 + *[0-9a-f]*:   e6 04 01 0d     sub sp,r3,r4
10997 + *[0-9a-f]*:   ee 03 01 03     sub r3,r7,r3
10998 + *[0-9a-f]*:   f4 0d 01 1d     sub sp,r10,sp<<0x1
10999 +
11000 +[0-9a-f]* <divu>:
11001 + *[0-9a-f]*:   fe 0f 0d 0f     divu pc,pc,pc
11002 + *[0-9a-f]*:   f8 0c 0d 0c     divu r12,r12,r12
11003 + *[0-9a-f]*:   ea 05 0d 05     divu r5,r5,r5
11004 + *[0-9a-f]*:   e8 04 0d 04     divu r4,r4,r4
11005 + *[0-9a-f]*:   fc 0e 0d 0e     divu lr,lr,lr
11006 + *[0-9a-f]*:   e8 0f 0d 0d     divu sp,r4,pc
11007 + *[0-9a-f]*:   ea 0d 0d 05     divu r5,r5,sp
11008 + *[0-9a-f]*:   fa 00 0d 0a     divu r10,sp,r0
11009 +
11010 +[0-9a-f]* <addhh_w>:
11011 + *[0-9a-f]*:   fe 0f 0e 0f     addhh\.w pc,pc:b,pc:b
11012 + *[0-9a-f]*:   f8 0c 0e 3c     addhh\.w r12,r12:t,r12:t
11013 + *[0-9a-f]*:   ea 05 0e 35     addhh\.w r5,r5:t,r5:t
11014 + *[0-9a-f]*:   e8 04 0e 04     addhh\.w r4,r4:b,r4:b
11015 + *[0-9a-f]*:   fc 0e 0e 3e     addhh\.w lr,lr:t,lr:t
11016 + *[0-9a-f]*:   e0 03 0e 00     addhh\.w r0,r0:b,r3:b
11017 + *[0-9a-f]*:   f8 07 0e 2e     addhh\.w lr,r12:t,r7:b
11018 + *[0-9a-f]*:   f4 02 0e 23     addhh\.w r3,r10:t,r2:b
11019 +
11020 +[0-9a-f]* <subhh_w>:
11021 + *[0-9a-f]*:   fe 0f 0f 0f     subhh\.w pc,pc:b,pc:b
11022 + *[0-9a-f]*:   f8 0c 0f 3c     subhh\.w r12,r12:t,r12:t
11023 + *[0-9a-f]*:   ea 05 0f 35     subhh\.w r5,r5:t,r5:t
11024 + *[0-9a-f]*:   e8 04 0f 04     subhh\.w r4,r4:b,r4:b
11025 + *[0-9a-f]*:   fc 0e 0f 3e     subhh\.w lr,lr:t,lr:t
11026 + *[0-9a-f]*:   e2 07 0f 2a     subhh\.w r10,r1:t,r7:b
11027 + *[0-9a-f]*:   f4 0e 0f 3f     subhh\.w pc,r10:t,lr:t
11028 + *[0-9a-f]*:   e0 0c 0f 23     subhh\.w r3,r0:t,r12:b
11029 +
11030 +[0-9a-f]* <adc>:
11031 + *[0-9a-f]*:   fe 0f 00 4f     adc pc,pc,pc
11032 + *[0-9a-f]*:   f8 0c 00 4c     adc r12,r12,r12
11033 + *[0-9a-f]*:   ea 05 00 45     adc r5,r5,r5
11034 + *[0-9a-f]*:   e8 04 00 44     adc r4,r4,r4
11035 + *[0-9a-f]*:   fc 0e 00 4e     adc lr,lr,lr
11036 + *[0-9a-f]*:   e0 07 00 44     adc r4,r0,r7
11037 + *[0-9a-f]*:   e8 03 00 4d     adc sp,r4,r3
11038 + *[0-9a-f]*:   f8 00 00 42     adc r2,r12,r0
11039 +
11040 +[0-9a-f]* <sbc>:
11041 + *[0-9a-f]*:   fe 0f 01 4f     sbc pc,pc,pc
11042 + *[0-9a-f]*:   f8 0c 01 4c     sbc r12,r12,r12
11043 + *[0-9a-f]*:   ea 05 01 45     sbc r5,r5,r5
11044 + *[0-9a-f]*:   e8 04 01 44     sbc r4,r4,r4
11045 + *[0-9a-f]*:   fc 0e 01 4e     sbc lr,lr,lr
11046 + *[0-9a-f]*:   ee 09 01 46     sbc r6,r7,r9
11047 + *[0-9a-f]*:   f0 05 01 40     sbc r0,r8,r5
11048 + *[0-9a-f]*:   e0 04 01 41     sbc r1,r0,r4
11049 +
11050 +[0-9a-f]* <mul_2>:
11051 + *[0-9a-f]*:   fe 0f 02 4f     mul pc,pc,pc
11052 + *[0-9a-f]*:   f8 0c 02 4c     mul r12,r12,r12
11053 + *[0-9a-f]*:   ea 05 02 45     mul r5,r5,r5
11054 + *[0-9a-f]*:   e8 04 02 44     mul r4,r4,r4
11055 + *[0-9a-f]*:   fc 0e 02 4e     mul lr,lr,lr
11056 + *[0-9a-f]*:   e0 00 02 4f     mul pc,r0,r0
11057 + *[0-9a-f]*:   fe 0e 02 48     mul r8,pc,lr
11058 + *[0-9a-f]*:   f8 0f 02 44     mul r4,r12,pc
11059 +
11060 +[0-9a-f]* <mac>:
11061 + *[0-9a-f]*:   fe 0f 03 4f     mac pc,pc,pc
11062 + *[0-9a-f]*:   f8 0c 03 4c     mac r12,r12,r12
11063 + *[0-9a-f]*:   ea 05 03 45     mac r5,r5,r5
11064 + *[0-9a-f]*:   e8 04 03 44     mac r4,r4,r4
11065 + *[0-9a-f]*:   fc 0e 03 4e     mac lr,lr,lr
11066 + *[0-9a-f]*:   e8 00 03 4a     mac r10,r4,r0
11067 + *[0-9a-f]*:   fc 00 03 47     mac r7,lr,r0
11068 + *[0-9a-f]*:   f2 0c 03 42     mac r2,r9,r12
11069 +
11070 +[0-9a-f]* <mulsd>:
11071 + *[0-9a-f]*:   fe 0f 04 4f     muls\.d pc,pc,pc
11072 + *[0-9a-f]*:   f8 0c 04 4c     muls\.d r12,r12,r12
11073 + *[0-9a-f]*:   ea 05 04 45     muls\.d r5,r5,r5
11074 + *[0-9a-f]*:   e8 04 04 44     muls\.d r4,r4,r4
11075 + *[0-9a-f]*:   fc 0e 04 4e     muls\.d lr,lr,lr
11076 + *[0-9a-f]*:   f0 0e 04 42     muls\.d r2,r8,lr
11077 + *[0-9a-f]*:   e0 0b 04 44     muls\.d r4,r0,r11
11078 + *[0-9a-f]*:   fc 06 04 45     muls\.d r5,lr,r6
11079 +
11080 +[0-9a-f]* <macsd>:
11081 + *[0-9a-f]*:   fe 0f 05 40     macs\.d r0,pc,pc
11082 + *[0-9a-f]*:   f8 0c 05 4e     macs\.d lr,r12,r12
11083 + *[0-9a-f]*:   ea 05 05 48     macs\.d r8,r5,r5
11084 + *[0-9a-f]*:   e8 04 05 46     macs\.d r6,r4,r4
11085 + *[0-9a-f]*:   fc 0e 05 42     macs\.d r2,lr,lr
11086 + *[0-9a-f]*:   e2 09 05 48     macs\.d r8,r1,r9
11087 + *[0-9a-f]*:   f0 08 05 4e     macs\.d lr,r8,r8
11088 + *[0-9a-f]*:   e6 0c 05 44     macs\.d r4,r3,r12
11089 +
11090 +[0-9a-f]* <mulud>:
11091 + *[0-9a-f]*:   fe 0f 06 40     mulu\.d r0,pc,pc
11092 + *[0-9a-f]*:   f8 0c 06 4e     mulu\.d lr,r12,r12
11093 + *[0-9a-f]*:   ea 05 06 48     mulu\.d r8,r5,r5
11094 + *[0-9a-f]*:   e8 04 06 46     mulu\.d r6,r4,r4
11095 + *[0-9a-f]*:   fc 0e 06 42     mulu\.d r2,lr,lr
11096 + *[0-9a-f]*:   ea 00 06 46     mulu\.d r6,r5,r0
11097 + *[0-9a-f]*:   ec 01 06 44     mulu\.d r4,r6,r1
11098 + *[0-9a-f]*:   f0 02 06 48     mulu\.d r8,r8,r2
11099 +
11100 +[0-9a-f]* <macud>:
11101 + *[0-9a-f]*:   fe 0f 07 40     macu\.d r0,pc,pc
11102 + *[0-9a-f]*:   f8 0c 07 4e     macu\.d lr,r12,r12
11103 + *[0-9a-f]*:   ea 05 07 48     macu\.d r8,r5,r5
11104 + *[0-9a-f]*:   e8 04 07 46     macu\.d r6,r4,r4
11105 + *[0-9a-f]*:   fc 0e 07 42     macu\.d r2,lr,lr
11106 + *[0-9a-f]*:   fa 0b 07 46     macu\.d r6,sp,r11
11107 + *[0-9a-f]*:   e8 08 07 42     macu\.d r2,r4,r8
11108 + *[0-9a-f]*:   f4 09 07 46     macu\.d r6,r10,r9
11109 +
11110 +[0-9a-f]* <asr_1>:
11111 + *[0-9a-f]*:   fe 0f 08 4f     asr pc,pc,pc
11112 + *[0-9a-f]*:   f8 0c 08 4c     asr r12,r12,r12
11113 + *[0-9a-f]*:   ea 05 08 45     asr r5,r5,r5
11114 + *[0-9a-f]*:   e8 04 08 44     asr r4,r4,r4
11115 + *[0-9a-f]*:   fc 0e 08 4e     asr lr,lr,lr
11116 + *[0-9a-f]*:   ec 0f 08 4f     asr pc,r6,pc
11117 + *[0-9a-f]*:   ec 0c 08 40     asr r0,r6,r12
11118 + *[0-9a-f]*:   fa 00 08 44     asr r4,sp,r0
11119 +
11120 +[0-9a-f]* <lsl_1>:
11121 + *[0-9a-f]*:   fe 0f 09 4f     lsl pc,pc,pc
11122 + *[0-9a-f]*:   f8 0c 09 4c     lsl r12,r12,r12
11123 + *[0-9a-f]*:   ea 05 09 45     lsl r5,r5,r5
11124 + *[0-9a-f]*:   e8 04 09 44     lsl r4,r4,r4
11125 + *[0-9a-f]*:   fc 0e 09 4e     lsl lr,lr,lr
11126 + *[0-9a-f]*:   ea 0e 09 4e     lsl lr,r5,lr
11127 + *[0-9a-f]*:   fe 03 09 45     lsl r5,pc,r3
11128 + *[0-9a-f]*:   fe 09 09 41     lsl r1,pc,r9
11129 +
11130 +[0-9a-f]* <lsr_1>:
11131 + *[0-9a-f]*:   fe 0f 0a 4f     lsr pc,pc,pc
11132 + *[0-9a-f]*:   f8 0c 0a 4c     lsr r12,r12,r12
11133 + *[0-9a-f]*:   ea 05 0a 45     lsr r5,r5,r5
11134 + *[0-9a-f]*:   e8 04 0a 44     lsr r4,r4,r4
11135 + *[0-9a-f]*:   fc 0e 0a 4e     lsr lr,lr,lr
11136 + *[0-9a-f]*:   e8 01 0a 42     lsr r2,r4,r1
11137 + *[0-9a-f]*:   e2 06 0a 45     lsr r5,r1,r6
11138 + *[0-9a-f]*:   ec 07 0a 4d     lsr sp,r6,r7
11139 +
11140 +[0-9a-f]* <xchg>:
11141 + *[0-9a-f]*:   fe 0f 0b 4f     xchg pc,pc,pc
11142 + *[0-9a-f]*:   f8 0c 0b 4c     xchg r12,r12,r12
11143 + *[0-9a-f]*:   ea 05 0b 45     xchg r5,r5,r5
11144 + *[0-9a-f]*:   e8 04 0b 44     xchg r4,r4,r4
11145 + *[0-9a-f]*:   fc 0e 0b 4e     xchg lr,lr,lr
11146 + *[0-9a-f]*:   e8 0d 0b 4e     xchg lr,r4,sp
11147 + *[0-9a-f]*:   ea 0c 0b 41     xchg r1,r5,r12
11148 + *[0-9a-f]*:   f8 00 0b 4e     xchg lr,r12,r0
11149 +
11150 +[0-9a-f]* <max>:
11151 + *[0-9a-f]*:   fe 0f 0c 4f     max pc,pc,pc
11152 + *[0-9a-f]*:   f8 0c 0c 4c     max r12,r12,r12
11153 + *[0-9a-f]*:   ea 05 0c 45     max r5,r5,r5
11154 + *[0-9a-f]*:   e8 04 0c 44     max r4,r4,r4
11155 + *[0-9a-f]*:   fc 0e 0c 4e     max lr,lr,lr
11156 + *[0-9a-f]*:   e4 0d 0c 4e     max lr,r2,sp
11157 + *[0-9a-f]*:   f4 09 0c 44     max r4,r10,r9
11158 + *[0-9a-f]*:   f2 0e 0c 4e     max lr,r9,lr
11159 +
11160 +[0-9a-f]* <min>:
11161 + *[0-9a-f]*:   fe 0f 0d 4f     min pc,pc,pc
11162 + *[0-9a-f]*:   f8 0c 0d 4c     min r12,r12,r12
11163 + *[0-9a-f]*:   ea 05 0d 45     min r5,r5,r5
11164 + *[0-9a-f]*:   e8 04 0d 44     min r4,r4,r4
11165 + *[0-9a-f]*:   fc 0e 0d 4e     min lr,lr,lr
11166 + *[0-9a-f]*:   ee 08 0d 49     min r9,r7,r8
11167 + *[0-9a-f]*:   ea 05 0d 4d     min sp,r5,r5
11168 + *[0-9a-f]*:   e2 04 0d 44     min r4,r1,r4
11169 +
11170 +[0-9a-f]* <addabs>:
11171 + *[0-9a-f]*:   fe 0f 0e 4f     addabs pc,pc,pc
11172 + *[0-9a-f]*:   f8 0c 0e 4c     addabs r12,r12,r12
11173 + *[0-9a-f]*:   ea 05 0e 45     addabs r5,r5,r5
11174 + *[0-9a-f]*:   e8 04 0e 44     addabs r4,r4,r4
11175 + *[0-9a-f]*:   fc 0e 0e 4e     addabs lr,lr,lr
11176 + *[0-9a-f]*:   f4 00 0e 47     addabs r7,r10,r0
11177 + *[0-9a-f]*:   f2 07 0e 49     addabs r9,r9,r7
11178 + *[0-9a-f]*:   f0 0c 0e 42     addabs r2,r8,r12
11179 +
11180 +[0-9a-f]* <mulnhh_w>:
11181 + *[0-9a-f]*:   fe 0f 01 8f     mulnhh\.w pc,pc:b,pc:b
11182 + *[0-9a-f]*:   f8 0c 01 bc     mulnhh\.w r12,r12:t,r12:t
11183 + *[0-9a-f]*:   ea 05 01 b5     mulnhh\.w r5,r5:t,r5:t
11184 + *[0-9a-f]*:   e8 04 01 84     mulnhh\.w r4,r4:b,r4:b
11185 + *[0-9a-f]*:   fc 0e 01 be     mulnhh\.w lr,lr:t,lr:t
11186 + *[0-9a-f]*:   fa 09 01 ab     mulnhh\.w r11,sp:t,r9:b
11187 + *[0-9a-f]*:   e8 0e 01 9d     mulnhh\.w sp,r4:b,lr:t
11188 + *[0-9a-f]*:   e4 0b 01 ac     mulnhh\.w r12,r2:t,r11:b
11189 +
11190 +[0-9a-f]* <mulnwh_d>:
11191 + *[0-9a-f]*:   fe 0f 02 80     mulnwh\.d r0,pc,pc:b
11192 + *[0-9a-f]*:   f8 0c 02 9e     mulnwh\.d lr,r12,r12:t
11193 + *[0-9a-f]*:   ea 05 02 98     mulnwh\.d r8,r5,r5:t
11194 + *[0-9a-f]*:   e8 04 02 86     mulnwh\.d r6,r4,r4:b
11195 + *[0-9a-f]*:   fc 0e 02 92     mulnwh\.d r2,lr,lr:t
11196 + *[0-9a-f]*:   e6 02 02 9e     mulnwh\.d lr,r3,r2:t
11197 + *[0-9a-f]*:   ea 09 02 84     mulnwh\.d r4,r5,r9:b
11198 + *[0-9a-f]*:   e8 04 02 9c     mulnwh\.d r12,r4,r4:t
11199 +
11200 +[0-9a-f]* <machh_w>:
11201 + *[0-9a-f]*:   fe 0f 04 8f     machh\.w pc,pc:b,pc:b
11202 + *[0-9a-f]*:   f8 0c 04 bc     machh\.w r12,r12:t,r12:t
11203 + *[0-9a-f]*:   ea 05 04 b5     machh\.w r5,r5:t,r5:t
11204 + *[0-9a-f]*:   e8 04 04 84     machh\.w r4,r4:b,r4:b
11205 + *[0-9a-f]*:   fc 0e 04 be     machh\.w lr,lr:t,lr:t
11206 + *[0-9a-f]*:   ea 01 04 9e     machh\.w lr,r5:b,r1:t
11207 + *[0-9a-f]*:   ec 07 04 89     machh\.w r9,r6:b,r7:b
11208 + *[0-9a-f]*:   fc 0c 04 a5     machh\.w r5,lr:t,r12:b
11209 +
11210 +[0-9a-f]* <machh_d>:
11211 + *[0-9a-f]*:   fe 0f 05 80     machh\.d r0,pc:b,pc:b
11212 + *[0-9a-f]*:   f8 0c 05 be     machh\.d lr,r12:t,r12:t
11213 + *[0-9a-f]*:   ea 05 05 b8     machh\.d r8,r5:t,r5:t
11214 + *[0-9a-f]*:   e8 04 05 86     machh\.d r6,r4:b,r4:b
11215 + *[0-9a-f]*:   fc 0e 05 b2     machh\.d r2,lr:t,lr:t
11216 + *[0-9a-f]*:   e0 08 05 8a     machh\.d r10,r0:b,r8:b
11217 + *[0-9a-f]*:   e8 05 05 9e     machh\.d lr,r4:b,r5:t
11218 + *[0-9a-f]*:   e0 04 05 98     machh\.d r8,r0:b,r4:t
11219 +
11220 +[0-9a-f]* <macsathh_w>:
11221 + *[0-9a-f]*:   fe 0f 06 8f     macsathh\.w pc,pc:b,pc:b
11222 + *[0-9a-f]*:   f8 0c 06 bc     macsathh\.w r12,r12:t,r12:t
11223 + *[0-9a-f]*:   ea 05 06 b5     macsathh\.w r5,r5:t,r5:t
11224 + *[0-9a-f]*:   e8 04 06 84     macsathh\.w r4,r4:b,r4:b
11225 + *[0-9a-f]*:   fc 0e 06 be     macsathh\.w lr,lr:t,lr:t
11226 + *[0-9a-f]*:   ee 0f 06 b7     macsathh\.w r7,r7:t,pc:t
11227 + *[0-9a-f]*:   e4 04 06 a4     macsathh\.w r4,r2:t,r4:b
11228 + *[0-9a-f]*:   f0 03 06 b4     macsathh\.w r4,r8:t,r3:t
11229 +
11230 +[0-9a-f]* <mulhh_w>:
11231 + *[0-9a-f]*:   fe 0f 07 8f     mulhh\.w pc,pc:b,pc:b
11232 + *[0-9a-f]*:   f8 0c 07 bc     mulhh\.w r12,r12:t,r12:t
11233 + *[0-9a-f]*:   ea 05 07 b5     mulhh\.w r5,r5:t,r5:t
11234 + *[0-9a-f]*:   e8 04 07 84     mulhh\.w r4,r4:b,r4:b
11235 + *[0-9a-f]*:   fc 0e 07 be     mulhh\.w lr,lr:t,lr:t
11236 + *[0-9a-f]*:   e8 09 07 a7     mulhh\.w r7,r4:t,r9:b
11237 + *[0-9a-f]*:   e6 07 07 bf     mulhh\.w pc,r3:t,r7:t
11238 + *[0-9a-f]*:   e8 09 07 9f     mulhh\.w pc,r4:b,r9:t
11239 +
11240 +[0-9a-f]* <mulsathh_h>:
11241 + *[0-9a-f]*:   fe 0f 08 8f     mulsathh\.h pc,pc:b,pc:b
11242 + *[0-9a-f]*:   f8 0c 08 bc     mulsathh\.h r12,r12:t,r12:t
11243 + *[0-9a-f]*:   ea 05 08 b5     mulsathh\.h r5,r5:t,r5:t
11244 + *[0-9a-f]*:   e8 04 08 84     mulsathh\.h r4,r4:b,r4:b
11245 + *[0-9a-f]*:   fc 0e 08 be     mulsathh\.h lr,lr:t,lr:t
11246 + *[0-9a-f]*:   e2 0d 08 83     mulsathh\.h r3,r1:b,sp:b
11247 + *[0-9a-f]*:   fc 0b 08 ab     mulsathh\.h r11,lr:t,r11:b
11248 + *[0-9a-f]*:   f0 0b 08 98     mulsathh\.h r8,r8:b,r11:t
11249 +
11250 +[0-9a-f]* <mulsathh_w>:
11251 + *[0-9a-f]*:   fe 0f 09 8f     mulsathh\.w pc,pc:b,pc:b
11252 + *[0-9a-f]*:   f8 0c 09 bc     mulsathh\.w r12,r12:t,r12:t
11253 + *[0-9a-f]*:   ea 05 09 b5     mulsathh\.w r5,r5:t,r5:t
11254 + *[0-9a-f]*:   e8 04 09 84     mulsathh\.w r4,r4:b,r4:b
11255 + *[0-9a-f]*:   fc 0e 09 be     mulsathh\.w lr,lr:t,lr:t
11256 + *[0-9a-f]*:   f6 06 09 ae     mulsathh\.w lr,r11:t,r6:b
11257 + *[0-9a-f]*:   ec 07 09 96     mulsathh\.w r6,r6:b,r7:t
11258 + *[0-9a-f]*:   e4 03 09 8a     mulsathh\.w r10,r2:b,r3:b
11259 +
11260 +[0-9a-f]* <mulsatrndhh_h>:
11261 + *[0-9a-f]*:   fe 0f 0a 8f     mulsatrndhh\.h pc,pc:b,pc:b
11262 + *[0-9a-f]*:   f8 0c 0a bc     mulsatrndhh\.h r12,r12:t,r12:t
11263 + *[0-9a-f]*:   ea 05 0a b5     mulsatrndhh\.h r5,r5:t,r5:t
11264 + *[0-9a-f]*:   e8 04 0a 84     mulsatrndhh\.h r4,r4:b,r4:b
11265 + *[0-9a-f]*:   fc 0e 0a be     mulsatrndhh\.h lr,lr:t,lr:t
11266 + *[0-9a-f]*:   ec 09 0a 8b     mulsatrndhh\.h r11,r6:b,r9:b
11267 + *[0-9a-f]*:   e6 08 0a 9b     mulsatrndhh\.h r11,r3:b,r8:t
11268 + *[0-9a-f]*:   fa 07 0a b5     mulsatrndhh\.h r5,sp:t,r7:t
11269 +
11270 +[0-9a-f]* <mulsatrndwh_w>:
11271 + *[0-9a-f]*:   fe 0f 0b 8f     mulsatrndwh\.w pc,pc,pc:b
11272 + *[0-9a-f]*:   f8 0c 0b 9c     mulsatrndwh\.w r12,r12,r12:t
11273 + *[0-9a-f]*:   ea 05 0b 95     mulsatrndwh\.w r5,r5,r5:t
11274 + *[0-9a-f]*:   e8 04 0b 84     mulsatrndwh\.w r4,r4,r4:b
11275 + *[0-9a-f]*:   fc 0e 0b 9e     mulsatrndwh\.w lr,lr,lr:t
11276 + *[0-9a-f]*:   f8 00 0b 85     mulsatrndwh\.w r5,r12,r0:b
11277 + *[0-9a-f]*:   f4 0f 0b 87     mulsatrndwh\.w r7,r10,pc:b
11278 + *[0-9a-f]*:   f0 05 0b 9a     mulsatrndwh\.w r10,r8,r5:t
11279 +
11280 +[0-9a-f]* <macwh_d>:
11281 + *[0-9a-f]*:   fe 0f 0c 80     macwh\.d r0,pc,pc:b
11282 + *[0-9a-f]*:   f8 0c 0c 9e     macwh\.d lr,r12,r12:t
11283 + *[0-9a-f]*:   ea 05 0c 98     macwh\.d r8,r5,r5:t
11284 + *[0-9a-f]*:   e8 04 0c 86     macwh\.d r6,r4,r4:b
11285 + *[0-9a-f]*:   fc 0e 0c 92     macwh\.d r2,lr,lr:t
11286 + *[0-9a-f]*:   f4 0c 0c 94     macwh\.d r4,r10,r12:t
11287 + *[0-9a-f]*:   ee 0d 0c 84     macwh\.d r4,r7,sp:b
11288 + *[0-9a-f]*:   f2 0b 0c 8e     macwh\.d lr,r9,r11:b
11289 +
11290 +[0-9a-f]* <mulwh_d>:
11291 + *[0-9a-f]*:   fe 0f 0d 80     mulwh\.d r0,pc,pc:b
11292 + *[0-9a-f]*:   f8 0c 0d 9e     mulwh\.d lr,r12,r12:t
11293 + *[0-9a-f]*:   ea 05 0d 98     mulwh\.d r8,r5,r5:t
11294 + *[0-9a-f]*:   e8 04 0d 86     mulwh\.d r6,r4,r4:b
11295 + *[0-9a-f]*:   fc 0e 0d 92     mulwh\.d r2,lr,lr:t
11296 + *[0-9a-f]*:   ea 01 0d 8c     mulwh\.d r12,r5,r1:b
11297 + *[0-9a-f]*:   e2 03 0d 90     mulwh\.d r0,r1,r3:t
11298 + *[0-9a-f]*:   f2 02 0d 80     mulwh\.d r0,r9,r2:b
11299 +
11300 +[0-9a-f]* <mulsatwh_w>:
11301 + *[0-9a-f]*:   fe 0f 0e 8f     mulsatwh\.w pc,pc,pc:b
11302 + *[0-9a-f]*:   f8 0c 0e 9c     mulsatwh\.w r12,r12,r12:t
11303 + *[0-9a-f]*:   ea 05 0e 95     mulsatwh\.w r5,r5,r5:t
11304 + *[0-9a-f]*:   e8 04 0e 84     mulsatwh\.w r4,r4,r4:b
11305 + *[0-9a-f]*:   fc 0e 0e 9e     mulsatwh\.w lr,lr,lr:t
11306 + *[0-9a-f]*:   fe 0a 0e 9b     mulsatwh\.w r11,pc,r10:t
11307 + *[0-9a-f]*:   f8 09 0e 9d     mulsatwh\.w sp,r12,r9:t
11308 + *[0-9a-f]*:   e6 02 0e 90     mulsatwh\.w r0,r3,r2:t
11309 +
11310 +[0-9a-f]* <ldw7>:
11311 + *[0-9a-f]*:   fe 0f 0f 8f     ld\.w pc,pc\[pc:b<<2\]
11312 + *[0-9a-f]*:   f8 0c 0f bc     ld\.w r12,r12\[r12:t<<2\]
11313 + *[0-9a-f]*:   ea 05 0f a5     ld\.w r5,r5\[r5:u<<2\]
11314 + *[0-9a-f]*:   e8 04 0f 94     ld\.w r4,r4\[r4:l<<2\]
11315 + *[0-9a-f]*:   fc 0e 0f 9e     ld\.w lr,lr\[lr:l<<2\]
11316 + *[0-9a-f]*:   f4 06 0f 99     ld\.w r9,r10\[r6:l<<2\]
11317 + *[0-9a-f]*:   f4 0a 0f 82     ld\.w r2,r10\[r10:b<<2\]
11318 + *[0-9a-f]*:   ea 0f 0f 8b     ld\.w r11,r5\[pc:b<<2\]
11319 +
11320 +[0-9a-f]* <satadd_w>:
11321 + *[0-9a-f]*:   fe 0f 00 cf     satadd\.w pc,pc,pc
11322 + *[0-9a-f]*:   f8 0c 00 cc     satadd\.w r12,r12,r12
11323 + *[0-9a-f]*:   ea 05 00 c5     satadd\.w r5,r5,r5
11324 + *[0-9a-f]*:   e8 04 00 c4     satadd\.w r4,r4,r4
11325 + *[0-9a-f]*:   fc 0e 00 ce     satadd\.w lr,lr,lr
11326 + *[0-9a-f]*:   f0 0b 00 c4     satadd\.w r4,r8,r11
11327 + *[0-9a-f]*:   f8 06 00 c3     satadd\.w r3,r12,r6
11328 + *[0-9a-f]*:   fc 09 00 c3     satadd\.w r3,lr,r9
11329 +
11330 +[0-9a-f]* <satsub_w1>:
11331 + *[0-9a-f]*:   fe 0f 01 cf     satsub\.w pc,pc,pc
11332 + *[0-9a-f]*:   f8 0c 01 cc     satsub\.w r12,r12,r12
11333 + *[0-9a-f]*:   ea 05 01 c5     satsub\.w r5,r5,r5
11334 + *[0-9a-f]*:   e8 04 01 c4     satsub\.w r4,r4,r4
11335 + *[0-9a-f]*:   fc 0e 01 ce     satsub\.w lr,lr,lr
11336 + *[0-9a-f]*:   fa 00 01 c8     satsub\.w r8,sp,r0
11337 + *[0-9a-f]*:   f0 04 01 c9     satsub\.w r9,r8,r4
11338 + *[0-9a-f]*:   fc 02 01 cf     satsub\.w pc,lr,r2
11339 +
11340 +[0-9a-f]* <satadd_h>:
11341 + *[0-9a-f]*:   fe 0f 02 cf     satadd\.h pc,pc,pc
11342 + *[0-9a-f]*:   f8 0c 02 cc     satadd\.h r12,r12,r12
11343 + *[0-9a-f]*:   ea 05 02 c5     satadd\.h r5,r5,r5
11344 + *[0-9a-f]*:   e8 04 02 c4     satadd\.h r4,r4,r4
11345 + *[0-9a-f]*:   fc 0e 02 ce     satadd\.h lr,lr,lr
11346 + *[0-9a-f]*:   e6 09 02 c7     satadd\.h r7,r3,r9
11347 + *[0-9a-f]*:   e0 02 02 c1     satadd\.h r1,r0,r2
11348 + *[0-9a-f]*:   e8 0e 02 c1     satadd\.h r1,r4,lr
11349 +
11350 +[0-9a-f]* <satsub_h>:
11351 + *[0-9a-f]*:   fe 0f 03 cf     satsub\.h pc,pc,pc
11352 + *[0-9a-f]*:   f8 0c 03 cc     satsub\.h r12,r12,r12
11353 + *[0-9a-f]*:   ea 05 03 c5     satsub\.h r5,r5,r5
11354 + *[0-9a-f]*:   e8 04 03 c4     satsub\.h r4,r4,r4
11355 + *[0-9a-f]*:   fc 0e 03 ce     satsub\.h lr,lr,lr
11356 + *[0-9a-f]*:   fc 03 03 ce     satsub\.h lr,lr,r3
11357 + *[0-9a-f]*:   ec 05 03 cb     satsub\.h r11,r6,r5
11358 + *[0-9a-f]*:   fa 00 03 c3     satsub\.h r3,sp,r0
11359 +
11360 +[0-9a-f]* <mul3>:
11361 + *[0-9a-f]*:   fe 0f 10 00     mul pc,pc,0
11362 + *[0-9a-f]*:   f8 0c 10 ff     mul r12,r12,-1
11363 + *[0-9a-f]*:   ea 05 10 80     mul r5,r5,-128
11364 + *[0-9a-f]*:   e8 04 10 7f     mul r4,r4,127
11365 + *[0-9a-f]*:   fc 0e 10 01     mul lr,lr,1
11366 + *[0-9a-f]*:   e4 0c 10 f9     mul r12,r2,-7
11367 + *[0-9a-f]*:   fe 01 10 5f     mul r1,pc,95
11368 + *[0-9a-f]*:   ec 04 10 13     mul r4,r6,19
11369 +
11370 +[0-9a-f]* <rsub2>:
11371 + *[0-9a-f]*:   fe 0f 11 00     rsub pc,pc,0
11372 + *[0-9a-f]*:   f8 0c 11 ff     rsub r12,r12,-1
11373 + *[0-9a-f]*:   ea 05 11 80     rsub r5,r5,-128
11374 + *[0-9a-f]*:   e8 04 11 7f     rsub r4,r4,127
11375 + *[0-9a-f]*:   fc 0e 11 01     rsub lr,lr,1
11376 + *[0-9a-f]*:   fc 09 11 60     rsub r9,lr,96
11377 + *[0-9a-f]*:   e2 0b 11 38     rsub r11,r1,56
11378 + *[0-9a-f]*:   ee 00 11 a9     rsub r0,r7,-87
11379 +
11380 +[0-9a-f]* <clz>:
11381 + *[0-9a-f]*:   fe 0f 12 00     clz pc,pc
11382 + *[0-9a-f]*:   f8 0c 12 00     clz r12,r12
11383 + *[0-9a-f]*:   ea 05 12 00     clz r5,r5
11384 + *[0-9a-f]*:   e8 04 12 00     clz r4,r4
11385 + *[0-9a-f]*:   fc 0e 12 00     clz lr,lr
11386 + *[0-9a-f]*:   e6 02 12 00     clz r2,r3
11387 + *[0-9a-f]*:   f6 05 12 00     clz r5,r11
11388 + *[0-9a-f]*:   e6 0f 12 00     clz pc,r3
11389 +
11390 +[0-9a-f]* <cpc1>:
11391 + *[0-9a-f]*:   fe 0f 13 00     cpc pc,pc
11392 + *[0-9a-f]*:   f8 0c 13 00     cpc r12,r12
11393 + *[0-9a-f]*:   ea 05 13 00     cpc r5,r5
11394 + *[0-9a-f]*:   e8 04 13 00     cpc r4,r4
11395 + *[0-9a-f]*:   fc 0e 13 00     cpc lr,lr
11396 + *[0-9a-f]*:   e8 0f 13 00     cpc pc,r4
11397 + *[0-9a-f]*:   f2 05 13 00     cpc r5,r9
11398 + *[0-9a-f]*:   ee 06 13 00     cpc r6,r7
11399 +
11400 +[0-9a-f]* <asr3>:
11401 + *[0-9a-f]*:   fe 0f 14 00     asr pc,pc,0x0
11402 + *[0-9a-f]*:   f8 0c 14 1f     asr r12,r12,0x1f
11403 + *[0-9a-f]*:   ea 05 14 10     asr r5,r5,0x10
11404 + *[0-9a-f]*:   e8 04 14 0f     asr r4,r4,0xf
11405 + *[0-9a-f]*:   fc 0e 14 01     asr lr,lr,0x1
11406 + *[0-9a-f]*:   f6 04 14 13     asr r4,r11,0x13
11407 + *[0-9a-f]*:   fe 0d 14 1a     asr sp,pc,0x1a
11408 + *[0-9a-f]*:   fa 0b 14 08     asr r11,sp,0x8
11409 +
11410 +[0-9a-f]* <lsl3>:
11411 + *[0-9a-f]*:   fe 0f 15 00     lsl pc,pc,0x0
11412 + *[0-9a-f]*:   f8 0c 15 1f     lsl r12,r12,0x1f
11413 + *[0-9a-f]*:   ea 05 15 10     lsl r5,r5,0x10
11414 + *[0-9a-f]*:   e8 04 15 0f     lsl r4,r4,0xf
11415 + *[0-9a-f]*:   fc 0e 15 01     lsl lr,lr,0x1
11416 + *[0-9a-f]*:   f4 08 15 11     lsl r8,r10,0x11
11417 + *[0-9a-f]*:   fc 02 15 03     lsl r2,lr,0x3
11418 + *[0-9a-f]*:   f6 0e 15 0e     lsl lr,r11,0xe
11419 +
11420 +[0-9a-f]* <lsr3>:
11421 + *[0-9a-f]*:   fe 0f 16 00     lsr pc,pc,0x0
11422 + *[0-9a-f]*:   f8 0c 16 1f     lsr r12,r12,0x1f
11423 + *[0-9a-f]*:   ea 05 16 10     lsr r5,r5,0x10
11424 + *[0-9a-f]*:   e8 04 16 0f     lsr r4,r4,0xf
11425 + *[0-9a-f]*:   fc 0e 16 01     lsr lr,lr,0x1
11426 + *[0-9a-f]*:   e6 04 16 1f     lsr r4,r3,0x1f
11427 + *[0-9a-f]*:   f2 0f 16 0e     lsr pc,r9,0xe
11428 + *[0-9a-f]*:   e0 03 16 06     lsr r3,r0,0x6
11429 +
11430 +[0-9a-f]* <movc1>:
11431 + *[0-9a-f]*:   fe 0f 17 00     moveq pc,pc
11432 + *[0-9a-f]*:   f8 0c 17 f0     moval r12,r12
11433 + *[0-9a-f]*:   ea 05 17 80     movls r5,r5
11434 + *[0-9a-f]*:   e8 04 17 70     movpl r4,r4
11435 + *[0-9a-f]*:   fc 0e 17 10     movne lr,lr
11436 + *[0-9a-f]*:   f6 0f 17 10     movne pc,r11
11437 + *[0-9a-f]*:   e4 0a 17 60     movmi r10,r2
11438 + *[0-9a-f]*:   f8 08 17 80     movls r8,r12
11439 +
11440 +[0-9a-f]* <padd_h>:
11441 + *[0-9a-f]*:   fe 0f 20 0f     padd\.h pc,pc,pc
11442 + *[0-9a-f]*:   f8 0c 20 0c     padd\.h r12,r12,r12
11443 + *[0-9a-f]*:   ea 05 20 05     padd\.h r5,r5,r5
11444 + *[0-9a-f]*:   e8 04 20 04     padd\.h r4,r4,r4
11445 + *[0-9a-f]*:   fc 0e 20 0e     padd\.h lr,lr,lr
11446 + *[0-9a-f]*:   e4 07 20 08     padd\.h r8,r2,r7
11447 + *[0-9a-f]*:   e0 03 20 00     padd\.h r0,r0,r3
11448 + *[0-9a-f]*:   f6 06 20 0d     padd\.h sp,r11,r6
11449 +
11450 +[0-9a-f]* <psub_h>:
11451 + *[0-9a-f]*:   fe 0f 20 1f     psub\.h pc,pc,pc
11452 + *[0-9a-f]*:   f8 0c 20 1c     psub\.h r12,r12,r12
11453 + *[0-9a-f]*:   ea 05 20 15     psub\.h r5,r5,r5
11454 + *[0-9a-f]*:   e8 04 20 14     psub\.h r4,r4,r4
11455 + *[0-9a-f]*:   fc 0e 20 1e     psub\.h lr,lr,lr
11456 + *[0-9a-f]*:   ec 08 20 1e     psub\.h lr,r6,r8
11457 + *[0-9a-f]*:   e2 0d 20 10     psub\.h r0,r1,sp
11458 + *[0-9a-f]*:   fe 0d 20 1f     psub\.h pc,pc,sp
11459 +
11460 +[0-9a-f]* <paddx_h>:
11461 + *[0-9a-f]*:   fe 0f 20 2f     paddx\.h pc,pc,pc
11462 + *[0-9a-f]*:   f8 0c 20 2c     paddx\.h r12,r12,r12
11463 + *[0-9a-f]*:   ea 05 20 25     paddx\.h r5,r5,r5
11464 + *[0-9a-f]*:   e8 04 20 24     paddx\.h r4,r4,r4
11465 + *[0-9a-f]*:   fc 0e 20 2e     paddx\.h lr,lr,lr
11466 + *[0-9a-f]*:   fe 01 20 2f     paddx\.h pc,pc,r1
11467 + *[0-9a-f]*:   e8 05 20 2a     paddx\.h r10,r4,r5
11468 + *[0-9a-f]*:   fe 02 20 25     paddx\.h r5,pc,r2
11469 +
11470 +[0-9a-f]* <psubx_h>:
11471 + *[0-9a-f]*:   fe 0f 20 3f     psubx\.h pc,pc,pc
11472 + *[0-9a-f]*:   f8 0c 20 3c     psubx\.h r12,r12,r12
11473 + *[0-9a-f]*:   ea 05 20 35     psubx\.h r5,r5,r5
11474 + *[0-9a-f]*:   e8 04 20 34     psubx\.h r4,r4,r4
11475 + *[0-9a-f]*:   fc 0e 20 3e     psubx\.h lr,lr,lr
11476 + *[0-9a-f]*:   f8 05 20 35     psubx\.h r5,r12,r5
11477 + *[0-9a-f]*:   f0 03 20 33     psubx\.h r3,r8,r3
11478 + *[0-9a-f]*:   e4 03 20 35     psubx\.h r5,r2,r3
11479 +
11480 +[0-9a-f]* <padds_sh>:
11481 + *[0-9a-f]*:   fe 0f 20 4f     padds\.sh pc,pc,pc
11482 + *[0-9a-f]*:   f8 0c 20 4c     padds\.sh r12,r12,r12
11483 + *[0-9a-f]*:   ea 05 20 45     padds\.sh r5,r5,r5
11484 + *[0-9a-f]*:   e8 04 20 44     padds\.sh r4,r4,r4
11485 + *[0-9a-f]*:   fc 0e 20 4e     padds\.sh lr,lr,lr
11486 + *[0-9a-f]*:   fc 02 20 49     padds\.sh r9,lr,r2
11487 + *[0-9a-f]*:   f0 01 20 46     padds\.sh r6,r8,r1
11488 + *[0-9a-f]*:   e8 0a 20 46     padds\.sh r6,r4,r10
11489 +
11490 +[0-9a-f]* <psubs_sh>:
11491 + *[0-9a-f]*:   fe 0f 20 5f     psubs\.sh pc,pc,pc
11492 + *[0-9a-f]*:   f8 0c 20 5c     psubs\.sh r12,r12,r12
11493 + *[0-9a-f]*:   ea 05 20 55     psubs\.sh r5,r5,r5
11494 + *[0-9a-f]*:   e8 04 20 54     psubs\.sh r4,r4,r4
11495 + *[0-9a-f]*:   fc 0e 20 5e     psubs\.sh lr,lr,lr
11496 + *[0-9a-f]*:   fc 0b 20 56     psubs\.sh r6,lr,r11
11497 + *[0-9a-f]*:   f8 04 20 52     psubs\.sh r2,r12,r4
11498 + *[0-9a-f]*:   f2 00 20 50     psubs\.sh r0,r9,r0
11499 +
11500 +[0-9a-f]* <paddxs_sh>:
11501 + *[0-9a-f]*:   fe 0f 20 6f     paddxs\.sh pc,pc,pc
11502 + *[0-9a-f]*:   f8 0c 20 6c     paddxs\.sh r12,r12,r12
11503 + *[0-9a-f]*:   ea 05 20 65     paddxs\.sh r5,r5,r5
11504 + *[0-9a-f]*:   e8 04 20 64     paddxs\.sh r4,r4,r4
11505 + *[0-9a-f]*:   fc 0e 20 6e     paddxs\.sh lr,lr,lr
11506 + *[0-9a-f]*:   e6 09 20 60     paddxs\.sh r0,r3,r9
11507 + *[0-9a-f]*:   f4 0b 20 6f     paddxs\.sh pc,r10,r11
11508 + *[0-9a-f]*:   f4 0f 20 6f     paddxs\.sh pc,r10,pc
11509 +
11510 +[0-9a-f]* <psubxs_sh>:
11511 + *[0-9a-f]*:   fe 0f 20 7f     psubxs\.sh pc,pc,pc
11512 + *[0-9a-f]*:   f8 0c 20 7c     psubxs\.sh r12,r12,r12
11513 + *[0-9a-f]*:   ea 05 20 75     psubxs\.sh r5,r5,r5
11514 + *[0-9a-f]*:   e8 04 20 74     psubxs\.sh r4,r4,r4
11515 + *[0-9a-f]*:   fc 0e 20 7e     psubxs\.sh lr,lr,lr
11516 + *[0-9a-f]*:   e8 04 20 77     psubxs\.sh r7,r4,r4
11517 + *[0-9a-f]*:   f0 03 20 77     psubxs\.sh r7,r8,r3
11518 + *[0-9a-f]*:   ec 05 20 7f     psubxs\.sh pc,r6,r5
11519 +
11520 +[0-9a-f]* <padds_uh>:
11521 + *[0-9a-f]*:   fe 0f 20 8f     padds\.uh pc,pc,pc
11522 + *[0-9a-f]*:   f8 0c 20 8c     padds\.uh r12,r12,r12
11523 + *[0-9a-f]*:   ea 05 20 85     padds\.uh r5,r5,r5
11524 + *[0-9a-f]*:   e8 04 20 84     padds\.uh r4,r4,r4
11525 + *[0-9a-f]*:   fc 0e 20 8e     padds\.uh lr,lr,lr
11526 + *[0-9a-f]*:   f6 07 20 8c     padds\.uh r12,r11,r7
11527 + *[0-9a-f]*:   f0 0e 20 87     padds\.uh r7,r8,lr
11528 + *[0-9a-f]*:   f2 07 20 86     padds\.uh r6,r9,r7
11529 +
11530 +[0-9a-f]* <psubs_uh>:
11531 + *[0-9a-f]*:   fe 0f 20 9f     psubs\.uh pc,pc,pc
11532 + *[0-9a-f]*:   f8 0c 20 9c     psubs\.uh r12,r12,r12
11533 + *[0-9a-f]*:   ea 05 20 95     psubs\.uh r5,r5,r5
11534 + *[0-9a-f]*:   e8 04 20 94     psubs\.uh r4,r4,r4
11535 + *[0-9a-f]*:   fc 0e 20 9e     psubs\.uh lr,lr,lr
11536 + *[0-9a-f]*:   f4 06 20 9e     psubs\.uh lr,r10,r6
11537 + *[0-9a-f]*:   e4 0f 20 9d     psubs\.uh sp,r2,pc
11538 + *[0-9a-f]*:   f2 02 20 92     psubs\.uh r2,r9,r2
11539 +
11540 +[0-9a-f]* <paddxs_uh>:
11541 + *[0-9a-f]*:   fe 0f 20 af     paddxs\.uh pc,pc,pc
11542 + *[0-9a-f]*:   f8 0c 20 ac     paddxs\.uh r12,r12,r12
11543 + *[0-9a-f]*:   ea 05 20 a5     paddxs\.uh r5,r5,r5
11544 + *[0-9a-f]*:   e8 04 20 a4     paddxs\.uh r4,r4,r4
11545 + *[0-9a-f]*:   fc 0e 20 ae     paddxs\.uh lr,lr,lr
11546 + *[0-9a-f]*:   f2 05 20 a7     paddxs\.uh r7,r9,r5
11547 + *[0-9a-f]*:   e2 04 20 a9     paddxs\.uh r9,r1,r4
11548 + *[0-9a-f]*:   e4 03 20 a5     paddxs\.uh r5,r2,r3
11549 +
11550 +[0-9a-f]* <psubxs_uh>:
11551 + *[0-9a-f]*:   fe 0f 20 bf     psubxs\.uh pc,pc,pc
11552 + *[0-9a-f]*:   f8 0c 20 bc     psubxs\.uh r12,r12,r12
11553 + *[0-9a-f]*:   ea 05 20 b5     psubxs\.uh r5,r5,r5
11554 + *[0-9a-f]*:   e8 04 20 b4     psubxs\.uh r4,r4,r4
11555 + *[0-9a-f]*:   fc 0e 20 be     psubxs\.uh lr,lr,lr
11556 + *[0-9a-f]*:   ea 0d 20 bd     psubxs\.uh sp,r5,sp
11557 + *[0-9a-f]*:   ec 06 20 bd     psubxs\.uh sp,r6,r6
11558 + *[0-9a-f]*:   f6 08 20 b3     psubxs\.uh r3,r11,r8
11559 +
11560 +[0-9a-f]* <paddh_sh>:
11561 + *[0-9a-f]*:   fe 0f 20 cf     paddh\.sh pc,pc,pc
11562 + *[0-9a-f]*:   f8 0c 20 cc     paddh\.sh r12,r12,r12
11563 + *[0-9a-f]*:   ea 05 20 c5     paddh\.sh r5,r5,r5
11564 + *[0-9a-f]*:   e8 04 20 c4     paddh\.sh r4,r4,r4
11565 + *[0-9a-f]*:   fc 0e 20 ce     paddh\.sh lr,lr,lr
11566 + *[0-9a-f]*:   fa 03 20 cc     paddh\.sh r12,sp,r3
11567 + *[0-9a-f]*:   ea 03 20 cf     paddh\.sh pc,r5,r3
11568 + *[0-9a-f]*:   f0 0d 20 c8     paddh\.sh r8,r8,sp
11569 +
11570 +[0-9a-f]* <psubh_sh>:
11571 + *[0-9a-f]*:   fe 0f 20 df     psubh\.sh pc,pc,pc
11572 + *[0-9a-f]*:   f8 0c 20 dc     psubh\.sh r12,r12,r12
11573 + *[0-9a-f]*:   ea 05 20 d5     psubh\.sh r5,r5,r5
11574 + *[0-9a-f]*:   e8 04 20 d4     psubh\.sh r4,r4,r4
11575 + *[0-9a-f]*:   fc 0e 20 de     psubh\.sh lr,lr,lr
11576 + *[0-9a-f]*:   ea 08 20 d1     psubh\.sh r1,r5,r8
11577 + *[0-9a-f]*:   e6 06 20 d7     psubh\.sh r7,r3,r6
11578 + *[0-9a-f]*:   e6 03 20 d4     psubh\.sh r4,r3,r3
11579 +
11580 +[0-9a-f]* <paddxh_sh>:
11581 + *[0-9a-f]*:   fe 0f 20 ef     paddxh\.sh pc,pc,pc
11582 + *[0-9a-f]*:   f8 0c 20 ec     paddxh\.sh r12,r12,r12
11583 + *[0-9a-f]*:   ea 05 20 e5     paddxh\.sh r5,r5,r5
11584 + *[0-9a-f]*:   e8 04 20 e4     paddxh\.sh r4,r4,r4
11585 + *[0-9a-f]*:   fc 0e 20 ee     paddxh\.sh lr,lr,lr
11586 + *[0-9a-f]*:   e0 04 20 e6     paddxh\.sh r6,r0,r4
11587 + *[0-9a-f]*:   f0 09 20 e9     paddxh\.sh r9,r8,r9
11588 + *[0-9a-f]*:   e0 0d 20 e3     paddxh\.sh r3,r0,sp
11589 +
11590 +[0-9a-f]* <psubxh_sh>:
11591 + *[0-9a-f]*:   fe 0f 20 ff     psubxh\.sh pc,pc,pc
11592 + *[0-9a-f]*:   f8 0c 20 fc     psubxh\.sh r12,r12,r12
11593 + *[0-9a-f]*:   ea 05 20 f5     psubxh\.sh r5,r5,r5
11594 + *[0-9a-f]*:   e8 04 20 f4     psubxh\.sh r4,r4,r4
11595 + *[0-9a-f]*:   fc 0e 20 fe     psubxh\.sh lr,lr,lr
11596 + *[0-9a-f]*:   fe 0c 20 f4     psubxh\.sh r4,pc,r12
11597 + *[0-9a-f]*:   e8 06 20 f8     psubxh\.sh r8,r4,r6
11598 + *[0-9a-f]*:   f2 04 20 fc     psubxh\.sh r12,r9,r4
11599 +
11600 +[0-9a-f]* <paddsub_h>:
11601 + *[0-9a-f]*:   fe 0f 21 0f     paddsub\.h pc,pc:b,pc:b
11602 + *[0-9a-f]*:   f8 0c 21 3c     paddsub\.h r12,r12:t,r12:t
11603 + *[0-9a-f]*:   ea 05 21 35     paddsub\.h r5,r5:t,r5:t
11604 + *[0-9a-f]*:   e8 04 21 04     paddsub\.h r4,r4:b,r4:b
11605 + *[0-9a-f]*:   fc 0e 21 3e     paddsub\.h lr,lr:t,lr:t
11606 + *[0-9a-f]*:   e4 0e 21 25     paddsub\.h r5,r2:t,lr:b
11607 + *[0-9a-f]*:   e2 08 21 07     paddsub\.h r7,r1:b,r8:b
11608 + *[0-9a-f]*:   f4 05 21 36     paddsub\.h r6,r10:t,r5:t
11609 +
11610 +[0-9a-f]* <psubadd_h>:
11611 + *[0-9a-f]*:   fe 0f 21 4f     psubadd\.h pc,pc:b,pc:b
11612 + *[0-9a-f]*:   f8 0c 21 7c     psubadd\.h r12,r12:t,r12:t
11613 + *[0-9a-f]*:   ea 05 21 75     psubadd\.h r5,r5:t,r5:t
11614 + *[0-9a-f]*:   e8 04 21 44     psubadd\.h r4,r4:b,r4:b
11615 + *[0-9a-f]*:   fc 0e 21 7e     psubadd\.h lr,lr:t,lr:t
11616 + *[0-9a-f]*:   f6 08 21 79     psubadd\.h r9,r11:t,r8:t
11617 + *[0-9a-f]*:   ee 0e 21 7a     psubadd\.h r10,r7:t,lr:t
11618 + *[0-9a-f]*:   fe 0f 21 66     psubadd\.h r6,pc:t,pc:b
11619 +
11620 +[0-9a-f]* <paddsubs_sh>:
11621 + *[0-9a-f]*:   fe 0f 21 8f     paddsubs\.sh pc,pc:b,pc:b
11622 + *[0-9a-f]*:   f8 0c 21 bc     paddsubs\.sh r12,r12:t,r12:t
11623 + *[0-9a-f]*:   ea 05 21 b5     paddsubs\.sh r5,r5:t,r5:t
11624 + *[0-9a-f]*:   e8 04 21 84     paddsubs\.sh r4,r4:b,r4:b
11625 + *[0-9a-f]*:   fc 0e 21 be     paddsubs\.sh lr,lr:t,lr:t
11626 + *[0-9a-f]*:   fc 00 21 a0     paddsubs\.sh r0,lr:t,r0:b
11627 + *[0-9a-f]*:   e4 04 21 b9     paddsubs\.sh r9,r2:t,r4:t
11628 + *[0-9a-f]*:   f2 0d 21 bc     paddsubs\.sh r12,r9:t,sp:t
11629 +
11630 +[0-9a-f]* <psubadds_sh>:
11631 + *[0-9a-f]*:   fe 0f 21 cf     psubadds\.sh pc,pc:b,pc:b
11632 + *[0-9a-f]*:   f8 0c 21 fc     psubadds\.sh r12,r12:t,r12:t
11633 + *[0-9a-f]*:   ea 05 21 f5     psubadds\.sh r5,r5:t,r5:t
11634 + *[0-9a-f]*:   e8 04 21 c4     psubadds\.sh r4,r4:b,r4:b
11635 + *[0-9a-f]*:   fc 0e 21 fe     psubadds\.sh lr,lr:t,lr:t
11636 + *[0-9a-f]*:   fc 01 21 df     psubadds\.sh pc,lr:b,r1:t
11637 + *[0-9a-f]*:   e6 0c 21 cb     psubadds\.sh r11,r3:b,r12:b
11638 + *[0-9a-f]*:   e4 08 21 fa     psubadds\.sh r10,r2:t,r8:t
11639 +
11640 +[0-9a-f]* <paddsubs_uh>:
11641 + *[0-9a-f]*:   fe 0f 22 0f     paddsubs\.uh pc,pc:b,pc:b
11642 + *[0-9a-f]*:   f8 0c 22 3c     paddsubs\.uh r12,r12:t,r12:t
11643 + *[0-9a-f]*:   ea 05 22 35     paddsubs\.uh r5,r5:t,r5:t
11644 + *[0-9a-f]*:   e8 04 22 04     paddsubs\.uh r4,r4:b,r4:b
11645 + *[0-9a-f]*:   fc 0e 22 3e     paddsubs\.uh lr,lr:t,lr:t
11646 + *[0-9a-f]*:   e4 03 22 09     paddsubs\.uh r9,r2:b,r3:b
11647 + *[0-9a-f]*:   fa 07 22 1d     paddsubs\.uh sp,sp:b,r7:t
11648 + *[0-9a-f]*:   e0 0a 22 1e     paddsubs\.uh lr,r0:b,r10:t
11649 +
11650 +[0-9a-f]* <psubadds_uh>:
11651 + *[0-9a-f]*:   fe 0f 22 4f     psubadds\.uh pc,pc:b,pc:b
11652 + *[0-9a-f]*:   f8 0c 22 7c     psubadds\.uh r12,r12:t,r12:t
11653 + *[0-9a-f]*:   ea 05 22 75     psubadds\.uh r5,r5:t,r5:t
11654 + *[0-9a-f]*:   e8 04 22 44     psubadds\.uh r4,r4:b,r4:b
11655 + *[0-9a-f]*:   fc 0e 22 7e     psubadds\.uh lr,lr:t,lr:t
11656 + *[0-9a-f]*:   f2 0f 22 7c     psubadds\.uh r12,r9:t,pc:t
11657 + *[0-9a-f]*:   ec 08 22 48     psubadds\.uh r8,r6:b,r8:b
11658 + *[0-9a-f]*:   f0 04 22 48     psubadds\.uh r8,r8:b,r4:b
11659 +
11660 +[0-9a-f]* <paddsubh_sh>:
11661 + *[0-9a-f]*:   fe 0f 22 8f     paddsubh\.sh pc,pc:b,pc:b
11662 + *[0-9a-f]*:   f8 0c 22 bc     paddsubh\.sh r12,r12:t,r12:t
11663 + *[0-9a-f]*:   ea 05 22 b5     paddsubh\.sh r5,r5:t,r5:t
11664 + *[0-9a-f]*:   e8 04 22 84     paddsubh\.sh r4,r4:b,r4:b
11665 + *[0-9a-f]*:   fc 0e 22 be     paddsubh\.sh lr,lr:t,lr:t
11666 + *[0-9a-f]*:   f2 09 22 a8     paddsubh\.sh r8,r9:t,r9:b
11667 + *[0-9a-f]*:   fa 01 22 b0     paddsubh\.sh r0,sp:t,r1:t
11668 + *[0-9a-f]*:   e2 00 22 93     paddsubh\.sh r3,r1:b,r0:t
11669 +
11670 +[0-9a-f]* <psubaddh_sh>:
11671 + *[0-9a-f]*:   fe 0f 22 cf     psubaddh\.sh pc,pc:b,pc:b
11672 + *[0-9a-f]*:   f8 0c 22 fc     psubaddh\.sh r12,r12:t,r12:t
11673 + *[0-9a-f]*:   ea 05 22 f5     psubaddh\.sh r5,r5:t,r5:t
11674 + *[0-9a-f]*:   e8 04 22 c4     psubaddh\.sh r4,r4:b,r4:b
11675 + *[0-9a-f]*:   fc 0e 22 fe     psubaddh\.sh lr,lr:t,lr:t
11676 + *[0-9a-f]*:   e6 0a 22 e7     psubaddh\.sh r7,r3:t,r10:b
11677 + *[0-9a-f]*:   e4 01 22 f7     psubaddh\.sh r7,r2:t,r1:t
11678 + *[0-9a-f]*:   e6 06 22 cb     psubaddh\.sh r11,r3:b,r6:b
11679 +
11680 +[0-9a-f]* <padd_b>:
11681 + *[0-9a-f]*:   fe 0f 23 0f     padd\.b pc,pc,pc
11682 + *[0-9a-f]*:   f8 0c 23 0c     padd\.b r12,r12,r12
11683 + *[0-9a-f]*:   ea 05 23 05     padd\.b r5,r5,r5
11684 + *[0-9a-f]*:   e8 04 23 04     padd\.b r4,r4,r4
11685 + *[0-9a-f]*:   fc 0e 23 0e     padd\.b lr,lr,lr
11686 + *[0-9a-f]*:   ec 0f 23 02     padd\.b r2,r6,pc
11687 + *[0-9a-f]*:   f2 0c 23 08     padd\.b r8,r9,r12
11688 + *[0-9a-f]*:   f8 03 23 05     padd\.b r5,r12,r3
11689 +
11690 +[0-9a-f]* <psub_b>:
11691 + *[0-9a-f]*:   fe 0f 23 1f     psub\.b pc,pc,pc
11692 + *[0-9a-f]*:   f8 0c 23 1c     psub\.b r12,r12,r12
11693 + *[0-9a-f]*:   ea 05 23 15     psub\.b r5,r5,r5
11694 + *[0-9a-f]*:   e8 04 23 14     psub\.b r4,r4,r4
11695 + *[0-9a-f]*:   fc 0e 23 1e     psub\.b lr,lr,lr
11696 + *[0-9a-f]*:   f8 0f 23 10     psub\.b r0,r12,pc
11697 + *[0-9a-f]*:   fa 0a 23 17     psub\.b r7,sp,r10
11698 + *[0-9a-f]*:   fa 0c 23 15     psub\.b r5,sp,r12
11699 +
11700 +[0-9a-f]* <padds_sb>:
11701 + *[0-9a-f]*:   fe 0f 23 2f     padds\.sb pc,pc,pc
11702 + *[0-9a-f]*:   f8 0c 23 2c     padds\.sb r12,r12,r12
11703 + *[0-9a-f]*:   ea 05 23 25     padds\.sb r5,r5,r5
11704 + *[0-9a-f]*:   e8 04 23 24     padds\.sb r4,r4,r4
11705 + *[0-9a-f]*:   fc 0e 23 2e     padds\.sb lr,lr,lr
11706 + *[0-9a-f]*:   f6 04 23 2d     padds\.sb sp,r11,r4
11707 + *[0-9a-f]*:   f4 0b 23 2b     padds\.sb r11,r10,r11
11708 + *[0-9a-f]*:   f8 06 23 25     padds\.sb r5,r12,r6
11709 +
11710 +[0-9a-f]* <psubs_sb>:
11711 + *[0-9a-f]*:   fe 0f 23 3f     psubs\.sb pc,pc,pc
11712 + *[0-9a-f]*:   f8 0c 23 3c     psubs\.sb r12,r12,r12
11713 + *[0-9a-f]*:   ea 05 23 35     psubs\.sb r5,r5,r5
11714 + *[0-9a-f]*:   e8 04 23 34     psubs\.sb r4,r4,r4
11715 + *[0-9a-f]*:   fc 0e 23 3e     psubs\.sb lr,lr,lr
11716 + *[0-9a-f]*:   ec 08 23 37     psubs\.sb r7,r6,r8
11717 + *[0-9a-f]*:   f4 09 23 3c     psubs\.sb r12,r10,r9
11718 + *[0-9a-f]*:   f6 00 23 3f     psubs\.sb pc,r11,r0
11719 +
11720 +[0-9a-f]* <padds_ub>:
11721 + *[0-9a-f]*:   fe 0f 23 4f     padds\.ub pc,pc,pc
11722 + *[0-9a-f]*:   f8 0c 23 4c     padds\.ub r12,r12,r12
11723 + *[0-9a-f]*:   ea 05 23 45     padds\.ub r5,r5,r5
11724 + *[0-9a-f]*:   e8 04 23 44     padds\.ub r4,r4,r4
11725 + *[0-9a-f]*:   fc 0e 23 4e     padds\.ub lr,lr,lr
11726 + *[0-9a-f]*:   e4 0b 23 43     padds\.ub r3,r2,r11
11727 + *[0-9a-f]*:   f0 01 23 4a     padds\.ub r10,r8,r1
11728 + *[0-9a-f]*:   f0 0a 23 4b     padds\.ub r11,r8,r10
11729 +
11730 +[0-9a-f]* <psubs_ub>:
11731 + *[0-9a-f]*:   fe 0f 23 5f     psubs\.ub pc,pc,pc
11732 + *[0-9a-f]*:   f8 0c 23 5c     psubs\.ub r12,r12,r12
11733 + *[0-9a-f]*:   ea 05 23 55     psubs\.ub r5,r5,r5
11734 + *[0-9a-f]*:   e8 04 23 54     psubs\.ub r4,r4,r4
11735 + *[0-9a-f]*:   fc 0e 23 5e     psubs\.ub lr,lr,lr
11736 + *[0-9a-f]*:   e4 07 23 50     psubs\.ub r0,r2,r7
11737 + *[0-9a-f]*:   ea 03 23 5e     psubs\.ub lr,r5,r3
11738 + *[0-9a-f]*:   ee 09 23 56     psubs\.ub r6,r7,r9
11739 +
11740 +[0-9a-f]* <paddh_ub>:
11741 + *[0-9a-f]*:   fe 0f 23 6f     paddh\.ub pc,pc,pc
11742 + *[0-9a-f]*:   f8 0c 23 6c     paddh\.ub r12,r12,r12
11743 + *[0-9a-f]*:   ea 05 23 65     paddh\.ub r5,r5,r5
11744 + *[0-9a-f]*:   e8 04 23 64     paddh\.ub r4,r4,r4
11745 + *[0-9a-f]*:   fc 0e 23 6e     paddh\.ub lr,lr,lr
11746 + *[0-9a-f]*:   e2 00 23 6e     paddh\.ub lr,r1,r0
11747 + *[0-9a-f]*:   ee 07 23 62     paddh\.ub r2,r7,r7
11748 + *[0-9a-f]*:   e2 02 23 62     paddh\.ub r2,r1,r2
11749 +
11750 +[0-9a-f]* <psubh_ub>:
11751 + *[0-9a-f]*:   fe 0f 23 7f     psubh\.ub pc,pc,pc
11752 + *[0-9a-f]*:   f8 0c 23 7c     psubh\.ub r12,r12,r12
11753 + *[0-9a-f]*:   ea 05 23 75     psubh\.ub r5,r5,r5
11754 + *[0-9a-f]*:   e8 04 23 74     psubh\.ub r4,r4,r4
11755 + *[0-9a-f]*:   fc 0e 23 7e     psubh\.ub lr,lr,lr
11756 + *[0-9a-f]*:   e2 06 23 70     psubh\.ub r0,r1,r6
11757 + *[0-9a-f]*:   fc 0a 23 74     psubh\.ub r4,lr,r10
11758 + *[0-9a-f]*:   f0 01 23 79     psubh\.ub r9,r8,r1
11759 +
11760 +[0-9a-f]* <pmax_ub>:
11761 + *[0-9a-f]*:   fe 0f 23 8f     pmax\.ub pc,pc,pc
11762 + *[0-9a-f]*:   f8 0c 23 8c     pmax\.ub r12,r12,r12
11763 + *[0-9a-f]*:   ea 05 23 85     pmax\.ub r5,r5,r5
11764 + *[0-9a-f]*:   e8 04 23 84     pmax\.ub r4,r4,r4
11765 + *[0-9a-f]*:   fc 0e 23 8e     pmax\.ub lr,lr,lr
11766 + *[0-9a-f]*:   e4 0b 23 8f     pmax\.ub pc,r2,r11
11767 + *[0-9a-f]*:   e2 01 23 8c     pmax\.ub r12,r1,r1
11768 + *[0-9a-f]*:   e4 00 23 85     pmax\.ub r5,r2,r0
11769 +
11770 +[0-9a-f]* <pmax_sh>:
11771 + *[0-9a-f]*:   fe 0f 23 9f     pmax\.sh pc,pc,pc
11772 + *[0-9a-f]*:   f8 0c 23 9c     pmax\.sh r12,r12,r12
11773 + *[0-9a-f]*:   ea 05 23 95     pmax\.sh r5,r5,r5
11774 + *[0-9a-f]*:   e8 04 23 94     pmax\.sh r4,r4,r4
11775 + *[0-9a-f]*:   fc 0e 23 9e     pmax\.sh lr,lr,lr
11776 + *[0-9a-f]*:   ec 0c 23 9e     pmax\.sh lr,r6,r12
11777 + *[0-9a-f]*:   fe 05 23 92     pmax\.sh r2,pc,r5
11778 + *[0-9a-f]*:   e4 07 23 9f     pmax\.sh pc,r2,r7
11779 +
11780 +[0-9a-f]* <pmin_ub>:
11781 + *[0-9a-f]*:   fe 0f 23 af     pmin\.ub pc,pc,pc
11782 + *[0-9a-f]*:   f8 0c 23 ac     pmin\.ub r12,r12,r12
11783 + *[0-9a-f]*:   ea 05 23 a5     pmin\.ub r5,r5,r5
11784 + *[0-9a-f]*:   e8 04 23 a4     pmin\.ub r4,r4,r4
11785 + *[0-9a-f]*:   fc 0e 23 ae     pmin\.ub lr,lr,lr
11786 + *[0-9a-f]*:   e2 05 23 a8     pmin\.ub r8,r1,r5
11787 + *[0-9a-f]*:   f0 03 23 a1     pmin\.ub r1,r8,r3
11788 + *[0-9a-f]*:   e4 07 23 a0     pmin\.ub r0,r2,r7
11789 +
11790 +[0-9a-f]* <pmin_sh>:
11791 + *[0-9a-f]*:   fe 0f 23 bf     pmin\.sh pc,pc,pc
11792 + *[0-9a-f]*:   f8 0c 23 bc     pmin\.sh r12,r12,r12
11793 + *[0-9a-f]*:   ea 05 23 b5     pmin\.sh r5,r5,r5
11794 + *[0-9a-f]*:   e8 04 23 b4     pmin\.sh r4,r4,r4
11795 + *[0-9a-f]*:   fc 0e 23 be     pmin\.sh lr,lr,lr
11796 + *[0-9a-f]*:   e8 0a 23 b8     pmin\.sh r8,r4,r10
11797 + *[0-9a-f]*:   f4 0c 23 be     pmin\.sh lr,r10,r12
11798 + *[0-9a-f]*:   ec 02 23 b2     pmin\.sh r2,r6,r2
11799 +
11800 +[0-9a-f]* <pavg_ub>:
11801 + *[0-9a-f]*:   fe 0f 23 cf     pavg\.ub pc,pc,pc
11802 + *[0-9a-f]*:   f8 0c 23 cc     pavg\.ub r12,r12,r12
11803 + *[0-9a-f]*:   ea 05 23 c5     pavg\.ub r5,r5,r5
11804 + *[0-9a-f]*:   e8 04 23 c4     pavg\.ub r4,r4,r4
11805 + *[0-9a-f]*:   fc 0e 23 ce     pavg\.ub lr,lr,lr
11806 + *[0-9a-f]*:   e2 06 23 c0     pavg\.ub r0,r1,r6
11807 + *[0-9a-f]*:   e6 06 23 c8     pavg\.ub r8,r3,r6
11808 + *[0-9a-f]*:   f8 0a 23 cf     pavg\.ub pc,r12,r10
11809 +
11810 +[0-9a-f]* <pavg_sh>:
11811 + *[0-9a-f]*:   fe 0f 23 df     pavg\.sh pc,pc,pc
11812 + *[0-9a-f]*:   f8 0c 23 dc     pavg\.sh r12,r12,r12
11813 + *[0-9a-f]*:   ea 05 23 d5     pavg\.sh r5,r5,r5
11814 + *[0-9a-f]*:   e8 04 23 d4     pavg\.sh r4,r4,r4
11815 + *[0-9a-f]*:   fc 0e 23 de     pavg\.sh lr,lr,lr
11816 + *[0-9a-f]*:   fe 0d 23 d9     pavg\.sh r9,pc,sp
11817 + *[0-9a-f]*:   fa 03 23 df     pavg\.sh pc,sp,r3
11818 + *[0-9a-f]*:   e2 09 23 d6     pavg\.sh r6,r1,r9
11819 +
11820 +[0-9a-f]* <pabs_sb>:
11821 + *[0-9a-f]*:   e0 0f 23 ef     pabs\.sb pc,pc
11822 + *[0-9a-f]*:   e0 0c 23 ec     pabs\.sb r12,r12
11823 + *[0-9a-f]*:   e0 05 23 e5     pabs\.sb r5,r5
11824 + *[0-9a-f]*:   e0 04 23 e4     pabs\.sb r4,r4
11825 + *[0-9a-f]*:   e0 0e 23 ee     pabs\.sb lr,lr
11826 + *[0-9a-f]*:   e0 06 23 eb     pabs\.sb r11,r6
11827 + *[0-9a-f]*:   e0 09 23 ee     pabs\.sb lr,r9
11828 + *[0-9a-f]*:   e0 07 23 ed     pabs\.sb sp,r7
11829 +
11830 +[0-9a-f]* <pabs_sh>:
11831 + *[0-9a-f]*:   e0 0f 23 ff     pabs\.sh pc,pc
11832 + *[0-9a-f]*:   e0 0c 23 fc     pabs\.sh r12,r12
11833 + *[0-9a-f]*:   e0 05 23 f5     pabs\.sh r5,r5
11834 + *[0-9a-f]*:   e0 04 23 f4     pabs\.sh r4,r4
11835 + *[0-9a-f]*:   e0 0e 23 fe     pabs\.sh lr,lr
11836 + *[0-9a-f]*:   e0 03 23 ff     pabs\.sh pc,r3
11837 + *[0-9a-f]*:   e0 07 23 f5     pabs\.sh r5,r7
11838 + *[0-9a-f]*:   e0 00 23 f4     pabs\.sh r4,r0
11839 +
11840 +[0-9a-f]* <psad>:
11841 + *[0-9a-f]*:   fe 0f 24 0f     psad pc,pc,pc
11842 + *[0-9a-f]*:   f8 0c 24 0c     psad r12,r12,r12
11843 + *[0-9a-f]*:   ea 05 24 05     psad r5,r5,r5
11844 + *[0-9a-f]*:   e8 04 24 04     psad r4,r4,r4
11845 + *[0-9a-f]*:   fc 0e 24 0e     psad lr,lr,lr
11846 + *[0-9a-f]*:   f6 0b 24 09     psad r9,r11,r11
11847 + *[0-9a-f]*:   e8 0d 24 0e     psad lr,r4,sp
11848 + *[0-9a-f]*:   e8 05 24 0e     psad lr,r4,r5
11849 +
11850 +[0-9a-f]* <pasr_b>:
11851 + *[0-9a-f]*:   fe 00 24 1f     pasr\.b pc,pc,0x0
11852 + *[0-9a-f]*:   f8 07 24 1c     pasr\.b r12,r12,0x7
11853 + *[0-9a-f]*:   ea 04 24 15     pasr\.b r5,r5,0x4
11854 + *[0-9a-f]*:   e8 03 24 14     pasr\.b r4,r4,0x3
11855 + *[0-9a-f]*:   fc 01 24 1e     pasr\.b lr,lr,0x1
11856 + *[0-9a-f]*:   ee 01 24 1f     pasr\.b pc,r7,0x1
11857 + *[0-9a-f]*:   fc 06 24 1d     pasr\.b sp,lr,0x6
11858 + *[0-9a-f]*:   e6 02 24 1d     pasr\.b sp,r3,0x2
11859 +
11860 +[0-9a-f]* <plsl_b>:
11861 + *[0-9a-f]*:   fe 00 24 2f     plsl\.b pc,pc,0x0
11862 + *[0-9a-f]*:   f8 07 24 2c     plsl\.b r12,r12,0x7
11863 + *[0-9a-f]*:   ea 04 24 25     plsl\.b r5,r5,0x4
11864 + *[0-9a-f]*:   e8 03 24 24     plsl\.b r4,r4,0x3
11865 + *[0-9a-f]*:   fc 01 24 2e     plsl\.b lr,lr,0x1
11866 + *[0-9a-f]*:   f6 04 24 22     plsl\.b r2,r11,0x4
11867 + *[0-9a-f]*:   ea 07 24 28     plsl\.b r8,r5,0x7
11868 + *[0-9a-f]*:   e0 02 24 2f     plsl\.b pc,r0,0x2
11869 +
11870 +[0-9a-f]* <plsr_b>:
11871 + *[0-9a-f]*:   fe 00 24 3f     plsr\.b pc,pc,0x0
11872 + *[0-9a-f]*:   f8 07 24 3c     plsr\.b r12,r12,0x7
11873 + *[0-9a-f]*:   ea 04 24 35     plsr\.b r5,r5,0x4
11874 + *[0-9a-f]*:   e8 03 24 34     plsr\.b r4,r4,0x3
11875 + *[0-9a-f]*:   fc 01 24 3e     plsr\.b lr,lr,0x1
11876 + *[0-9a-f]*:   e2 02 24 3c     plsr\.b r12,r1,0x2
11877 + *[0-9a-f]*:   fe 07 24 36     plsr\.b r6,pc,0x7
11878 + *[0-9a-f]*:   f6 02 24 3c     plsr\.b r12,r11,0x2
11879 +
11880 +[0-9a-f]* <pasr_h>:
11881 + *[0-9a-f]*:   fe 00 24 4f     pasr\.h pc,pc,0x0
11882 + *[0-9a-f]*:   f8 0f 24 4c     pasr\.h r12,r12,0xf
11883 + *[0-9a-f]*:   ea 08 24 45     pasr\.h r5,r5,0x8
11884 + *[0-9a-f]*:   e8 07 24 44     pasr\.h r4,r4,0x7
11885 + *[0-9a-f]*:   fc 01 24 4e     pasr\.h lr,lr,0x1
11886 + *[0-9a-f]*:   f6 0a 24 40     pasr\.h r0,r11,0xa
11887 + *[0-9a-f]*:   ec 08 24 44     pasr\.h r4,r6,0x8
11888 + *[0-9a-f]*:   e4 04 24 46     pasr\.h r6,r2,0x4
11889 +
11890 +[0-9a-f]* <plsl_h>:
11891 + *[0-9a-f]*:   fe 00 24 5f     plsl\.h pc,pc,0x0
11892 + *[0-9a-f]*:   f8 0f 24 5c     plsl\.h r12,r12,0xf
11893 + *[0-9a-f]*:   ea 08 24 55     plsl\.h r5,r5,0x8
11894 + *[0-9a-f]*:   e8 07 24 54     plsl\.h r4,r4,0x7
11895 + *[0-9a-f]*:   fc 01 24 5e     plsl\.h lr,lr,0x1
11896 + *[0-9a-f]*:   f4 09 24 55     plsl\.h r5,r10,0x9
11897 + *[0-9a-f]*:   fc 08 24 5d     plsl\.h sp,lr,0x8
11898 + *[0-9a-f]*:   fc 07 24 50     plsl\.h r0,lr,0x7
11899 +
11900 +[0-9a-f]* <plsr_h>:
11901 + *[0-9a-f]*:   fe 00 24 6f     plsr\.h pc,pc,0x0
11902 + *[0-9a-f]*:   f8 0f 24 6c     plsr\.h r12,r12,0xf
11903 + *[0-9a-f]*:   ea 08 24 65     plsr\.h r5,r5,0x8
11904 + *[0-9a-f]*:   e8 07 24 64     plsr\.h r4,r4,0x7
11905 + *[0-9a-f]*:   fc 01 24 6e     plsr\.h lr,lr,0x1
11906 + *[0-9a-f]*:   e0 0f 24 6b     plsr\.h r11,r0,0xf
11907 + *[0-9a-f]*:   e6 03 24 6e     plsr\.h lr,r3,0x3
11908 + *[0-9a-f]*:   fc 0a 24 68     plsr\.h r8,lr,0xa
11909 +
11910 +[0-9a-f]* <packw_sh>:
11911 + *[0-9a-f]*:   fe 0f 24 7f     packw\.sh pc,pc,pc
11912 + *[0-9a-f]*:   f8 0c 24 7c     packw\.sh r12,r12,r12
11913 + *[0-9a-f]*:   ea 05 24 75     packw\.sh r5,r5,r5
11914 + *[0-9a-f]*:   e8 04 24 74     packw\.sh r4,r4,r4
11915 + *[0-9a-f]*:   fc 0e 24 7e     packw\.sh lr,lr,lr
11916 + *[0-9a-f]*:   f6 0a 24 7d     packw\.sh sp,r11,r10
11917 + *[0-9a-f]*:   e4 0c 24 78     packw\.sh r8,r2,r12
11918 + *[0-9a-f]*:   e2 05 24 78     packw\.sh r8,r1,r5
11919 +
11920 +[0-9a-f]* <punpckub_h>:
11921 + *[0-9a-f]*:   fe 00 24 8f     punpckub\.h pc,pc:b
11922 + *[0-9a-f]*:   f8 00 24 9c     punpckub\.h r12,r12:t
11923 + *[0-9a-f]*:   ea 00 24 95     punpckub\.h r5,r5:t
11924 + *[0-9a-f]*:   e8 00 24 84     punpckub\.h r4,r4:b
11925 + *[0-9a-f]*:   fc 00 24 9e     punpckub\.h lr,lr:t
11926 + *[0-9a-f]*:   e2 00 24 96     punpckub\.h r6,r1:t
11927 + *[0-9a-f]*:   ea 00 24 8e     punpckub\.h lr,r5:b
11928 + *[0-9a-f]*:   e4 00 24 9e     punpckub\.h lr,r2:t
11929 +
11930 +[0-9a-f]* <punpcksb_h>:
11931 + *[0-9a-f]*:   fe 00 24 af     punpcksb\.h pc,pc:b
11932 + *[0-9a-f]*:   f8 00 24 bc     punpcksb\.h r12,r12:t
11933 + *[0-9a-f]*:   ea 00 24 b5     punpcksb\.h r5,r5:t
11934 + *[0-9a-f]*:   e8 00 24 a4     punpcksb\.h r4,r4:b
11935 + *[0-9a-f]*:   fc 00 24 be     punpcksb\.h lr,lr:t
11936 + *[0-9a-f]*:   ee 00 24 b4     punpcksb\.h r4,r7:t
11937 + *[0-9a-f]*:   fc 00 24 a6     punpcksb\.h r6,lr:b
11938 + *[0-9a-f]*:   f8 00 24 bc     punpcksb\.h r12,r12:t
11939 +
11940 +[0-9a-f]* <packsh_ub>:
11941 + *[0-9a-f]*:   fe 0f 24 cf     packsh\.ub pc,pc,pc
11942 + *[0-9a-f]*:   f8 0c 24 cc     packsh\.ub r12,r12,r12
11943 + *[0-9a-f]*:   ea 05 24 c5     packsh\.ub r5,r5,r5
11944 + *[0-9a-f]*:   e8 04 24 c4     packsh\.ub r4,r4,r4
11945 + *[0-9a-f]*:   fc 0e 24 ce     packsh\.ub lr,lr,lr
11946 + *[0-9a-f]*:   ec 03 24 c3     packsh\.ub r3,r6,r3
11947 + *[0-9a-f]*:   e0 03 24 c8     packsh\.ub r8,r0,r3
11948 + *[0-9a-f]*:   e6 0e 24 c9     packsh\.ub r9,r3,lr
11949 +
11950 +[0-9a-f]* <packsh_sb>:
11951 + *[0-9a-f]*:   fe 0f 24 df     packsh\.sb pc,pc,pc
11952 + *[0-9a-f]*:   f8 0c 24 dc     packsh\.sb r12,r12,r12
11953 + *[0-9a-f]*:   ea 05 24 d5     packsh\.sb r5,r5,r5
11954 + *[0-9a-f]*:   e8 04 24 d4     packsh\.sb r4,r4,r4
11955 + *[0-9a-f]*:   fc 0e 24 de     packsh\.sb lr,lr,lr
11956 + *[0-9a-f]*:   f0 01 24 d6     packsh\.sb r6,r8,r1
11957 + *[0-9a-f]*:   f2 08 24 de     packsh\.sb lr,r9,r8
11958 + *[0-9a-f]*:   ec 06 24 dd     packsh\.sb sp,r6,r6
11959 +
11960 +[0-9a-f]* <andl>:
11961 + *[0-9a-f]*:   e0 1f 00 00     andl pc,0x0
11962 + *[0-9a-f]*:   e0 1c ff ff     andl r12,0xffff
11963 + *[0-9a-f]*:   e0 15 80 00     andl r5,0x8000
11964 + *[0-9a-f]*:   e0 14 7f ff     andl r4,0x7fff
11965 + *[0-9a-f]*:   e0 1e 00 01     andl lr,0x1
11966 + *[0-9a-f]*:   e0 1f 5a 58     andl pc,0x5a58
11967 + *[0-9a-f]*:   e0 18 b8 9e     andl r8,0xb89e
11968 + *[0-9a-f]*:   e0 17 35 97     andl r7,0x3597
11969 +
11970 +[0-9a-f]* <andl_coh>:
11971 + *[0-9a-f]*:   e2 1f 00 00     andl pc,0x0,COH
11972 + *[0-9a-f]*:   e2 1c ff ff     andl r12,0xffff,COH
11973 + *[0-9a-f]*:   e2 15 80 00     andl r5,0x8000,COH
11974 + *[0-9a-f]*:   e2 14 7f ff     andl r4,0x7fff,COH
11975 + *[0-9a-f]*:   e2 1e 00 01     andl lr,0x1,COH
11976 + *[0-9a-f]*:   e2 16 58 e1     andl r6,0x58e1,COH
11977 + *[0-9a-f]*:   e2 10 9e cd     andl r0,0x9ecd,COH
11978 + *[0-9a-f]*:   e2 14 bd c4     andl r4,0xbdc4,COH
11979 +
11980 +[0-9a-f]* <andh>:
11981 + *[0-9a-f]*:   e4 1f 00 00     andh pc,0x0
11982 + *[0-9a-f]*:   e4 1c ff ff     andh r12,0xffff
11983 + *[0-9a-f]*:   e4 15 80 00     andh r5,0x8000
11984 + *[0-9a-f]*:   e4 14 7f ff     andh r4,0x7fff
11985 + *[0-9a-f]*:   e4 1e 00 01     andh lr,0x1
11986 + *[0-9a-f]*:   e4 1c cc 58     andh r12,0xcc58
11987 + *[0-9a-f]*:   e4 13 21 e3     andh r3,0x21e3
11988 + *[0-9a-f]*:   e4 12 a7 eb     andh r2,0xa7eb
11989 +
11990 +[0-9a-f]* <andh_coh>:
11991 + *[0-9a-f]*:   e6 1f 00 00     andh pc,0x0,COH
11992 + *[0-9a-f]*:   e6 1c ff ff     andh r12,0xffff,COH
11993 + *[0-9a-f]*:   e6 15 80 00     andh r5,0x8000,COH
11994 + *[0-9a-f]*:   e6 14 7f ff     andh r4,0x7fff,COH
11995 + *[0-9a-f]*:   e6 1e 00 01     andh lr,0x1,COH
11996 + *[0-9a-f]*:   e6 1b 86 0d     andh r11,0x860d,COH
11997 + *[0-9a-f]*:   e6 18 ce f6     andh r8,0xcef6,COH
11998 + *[0-9a-f]*:   e6 1a 5c 83     andh r10,0x5c83,COH
11999 +
12000 +[0-9a-f]* <orl>:
12001 + *[0-9a-f]*:   e8 1f 00 00     orl pc,0x0
12002 + *[0-9a-f]*:   e8 1c ff ff     orl r12,0xffff
12003 + *[0-9a-f]*:   e8 15 80 00     orl r5,0x8000
12004 + *[0-9a-f]*:   e8 14 7f ff     orl r4,0x7fff
12005 + *[0-9a-f]*:   e8 1e 00 01     orl lr,0x1
12006 + *[0-9a-f]*:   e8 1d 41 7e     orl sp,0x417e
12007 + *[0-9a-f]*:   e8 10 52 bd     orl r0,0x52bd
12008 + *[0-9a-f]*:   e8 1f ac 47     orl pc,0xac47
12009 +
12010 +[0-9a-f]* <orh>:
12011 + *[0-9a-f]*:   ea 1f 00 00     orh pc,0x0
12012 + *[0-9a-f]*:   ea 1c ff ff     orh r12,0xffff
12013 + *[0-9a-f]*:   ea 15 80 00     orh r5,0x8000
12014 + *[0-9a-f]*:   ea 14 7f ff     orh r4,0x7fff
12015 + *[0-9a-f]*:   ea 1e 00 01     orh lr,0x1
12016 + *[0-9a-f]*:   ea 18 6e 7d     orh r8,0x6e7d
12017 + *[0-9a-f]*:   ea 1c 77 1c     orh r12,0x771c
12018 + *[0-9a-f]*:   ea 11 ea 1a     orh r1,0xea1a
12019 +
12020 +[0-9a-f]* <eorl>:
12021 + *[0-9a-f]*:   ec 1f 00 00     eorl pc,0x0
12022 + *[0-9a-f]*:   ec 1c ff ff     eorl r12,0xffff
12023 + *[0-9a-f]*:   ec 15 80 00     eorl r5,0x8000
12024 + *[0-9a-f]*:   ec 14 7f ff     eorl r4,0x7fff
12025 + *[0-9a-f]*:   ec 1e 00 01     eorl lr,0x1
12026 + *[0-9a-f]*:   ec 14 c7 b9     eorl r4,0xc7b9
12027 + *[0-9a-f]*:   ec 16 fb dd     eorl r6,0xfbdd
12028 + *[0-9a-f]*:   ec 11 51 b1     eorl r1,0x51b1
12029 +
12030 +[0-9a-f]* <eorh>:
12031 + *[0-9a-f]*:   ee 1f 00 00     eorh pc,0x0
12032 + *[0-9a-f]*:   ee 1c ff ff     eorh r12,0xffff
12033 + *[0-9a-f]*:   ee 15 80 00     eorh r5,0x8000
12034 + *[0-9a-f]*:   ee 14 7f ff     eorh r4,0x7fff
12035 + *[0-9a-f]*:   ee 1e 00 01     eorh lr,0x1
12036 + *[0-9a-f]*:   ee 10 2d d4     eorh r0,0x2dd4
12037 + *[0-9a-f]*:   ee 1a 94 b5     eorh r10,0x94b5
12038 + *[0-9a-f]*:   ee 19 df 2a     eorh r9,0xdf2a
12039 +
12040 +[0-9a-f]* <mcall>:
12041 + *[0-9a-f]*:   f0 1f 00 00     mcall [0-9a-f]* <.*>
12042 + *[0-9a-f]*:   f0 1c ff ff     mcall r12\[-4\]
12043 + *[0-9a-f]*:   f0 15 80 00     mcall r5\[-131072\]
12044 + *[0-9a-f]*:   f0 14 7f ff     mcall r4\[131068\]
12045 + *[0-9a-f]*:   f0 1e 00 01     mcall lr\[4\]
12046 + *[0-9a-f]*:   f0 1d 3b bf     mcall sp\[61180\]
12047 + *[0-9a-f]*:   f0 14 dd d2     mcall r4\[-35000\]
12048 + *[0-9a-f]*:   f0 10 09 b1     mcall r0\[9924\]
12049 +
12050 +[0-9a-f]* <pref>:
12051 + *[0-9a-f]*:   f2 1f 00 00     pref pc\[0\]
12052 + *[0-9a-f]*:   f2 1c ff ff     pref r12\[-1\]
12053 + *[0-9a-f]*:   f2 15 80 00     pref r5\[-32768\]
12054 + *[0-9a-f]*:   f2 14 7f ff     pref r4\[32767\]
12055 + *[0-9a-f]*:   f2 1e 00 01     pref lr\[1\]
12056 + *[0-9a-f]*:   f2 17 1e 44     pref r7\[7748\]
12057 + *[0-9a-f]*:   f2 17 e1 ed     pref r7\[-7699\]
12058 + *[0-9a-f]*:   f2 12 9a dc     pref r2\[-25892\]
12059 +
12060 +[0-9a-f]* <cache>:
12061 + *[0-9a-f]*:   f4 1f 00 00     cache pc\[0\],0x0
12062 + *[0-9a-f]*:   f4 1c ff ff     cache r12\[-1\],0x1f
12063 + *[0-9a-f]*:   f4 15 84 00     cache r5\[-1024\],0x10
12064 + *[0-9a-f]*:   f4 14 7b ff     cache r4\[1023\],0xf
12065 + *[0-9a-f]*:   f4 1e 08 01     cache lr\[1\],0x1
12066 + *[0-9a-f]*:   f4 13 8c 3c     cache r3\[-964\],0x11
12067 + *[0-9a-f]*:   f4 14 b6 89     cache r4\[-375\],0x16
12068 + *[0-9a-f]*:   f4 13 8c 88     cache r3\[-888\],0x11
12069 +
12070 +[0-9a-f]* <sub4>:
12071 + *[0-9a-f]*:   20 0f           sub pc,0
12072 + *[0-9a-f]*:   2f fc           sub r12,-1
12073 + *[0-9a-f]*:   f0 25 00 00     sub r5,-1048576
12074 + *[0-9a-f]*:   ee 34 ff ff     sub r4,1048575
12075 + *[0-9a-f]*:   20 1e           sub lr,1
12076 + *[0-9a-f]*:   f6 22 8d 6c     sub r2,-619156
12077 + *[0-9a-f]*:   e6 3e 0a cd     sub lr,461517
12078 + *[0-9a-f]*:   fc 38 2d 25     sub r8,-185051
12079 +
12080 +[0-9a-f]* <cp3>:
12081 + *[0-9a-f]*:   58 0f           cp.w pc,0
12082 + *[0-9a-f]*:   5b fc           cp.w r12,-1
12083 + *[0-9a-f]*:   f0 45 00 00     cp.w r5,-1048576
12084 + *[0-9a-f]*:   ee 54 ff ff     cp.w r4,1048575
12085 + *[0-9a-f]*:   58 1e           cp.w lr,1
12086 + *[0-9a-f]*:   e0 51 e4 ae     cp.w r1,124078
12087 + *[0-9a-f]*:   fa 40 37 e3     cp.w r0,-378909
12088 + *[0-9a-f]*:   fc 44 4a 14     cp.w r4,-243180
12089 +
12090 +[0-9a-f]* <mov2>:
12091 + *[0-9a-f]*:   30 0f           mov pc,0
12092 + *[0-9a-f]*:   3f fc           mov r12,-1
12093 + *[0-9a-f]*:   f0 65 00 00     mov r5,-1048576
12094 + *[0-9a-f]*:   ee 74 ff ff     mov r4,1048575
12095 + *[0-9a-f]*:   30 1e           mov lr,1
12096 + *[0-9a-f]*:   fa 75 29 a3     mov r5,-317021
12097 + *[0-9a-f]*:   f4 6d 91 94     mov sp,-749164
12098 + *[0-9a-f]*:   ee 65 58 93     mov r5,940179
12099 +
12100 +[0-9a-f]* <brc2>:
12101 + *[0-9a-f]*:   c0 00           breq [0-9a-f]* <.*>
12102 + *[0-9a-f]*:   fe 9f ff ff     bral [0-9a-f]* <.*>
12103 + *[0-9a-f]*:   f0 88 00 00     brls [0-9a-f]* <.*>
12104 + *[0-9a-f]*:   ee 97 ff ff     brpl [0-9a-f]* <.*>
12105 + *[0-9a-f]*:   c0 11           brne [0-9a-f]* <.*>
12106 + *[0-9a-f]*:   f2 8b 4a 4d     brhi [0-9a-f]* <.*>
12107 + *[0-9a-f]*:   ea 8e 14 cc     brqs [0-9a-f]* <.*>
12108 + *[0-9a-f]*:   fa 98 98 33     brls [0-9a-f]* <.*>
12109 +
12110 +[0-9a-f]* <rcall2>:
12111 + *[0-9a-f]*:   c0 0c           rcall [0-9a-f]* <.*>
12112 + *[0-9a-f]*:   cf ff           rcall [0-9a-f]* <.*>
12113 + *[0-9a-f]*:   f0 a0 00 00     rcall [0-9a-f]* <.*>
12114 + *[0-9a-f]*:   ee b0 ff ff     rcall [0-9a-f]* <.*>
12115 + *[0-9a-f]*:   c0 1c           rcall [0-9a-f]* <.*>
12116 + *[0-9a-f]*:   e2 b0 ca 5a     rcall [0-9a-f]* <.*>
12117 + *[0-9a-f]*:   e8 a0 47 52     rcall [0-9a-f]* <.*>
12118 + *[0-9a-f]*:   fe b0 fd ef     rcall [0-9a-f]* <.*>
12119 +
12120 +[0-9a-f]* <sub5>:
12121 + *[0-9a-f]*:   fe cf 00 00     sub pc,pc,0
12122 + *[0-9a-f]*:   f8 cc ff ff     sub r12,r12,-1
12123 + *[0-9a-f]*:   ea c5 80 00     sub r5,r5,-32768
12124 + *[0-9a-f]*:   e8 c4 7f ff     sub r4,r4,32767
12125 + *[0-9a-f]*:   fc ce 00 01     sub lr,lr,1
12126 + *[0-9a-f]*:   fe cf ce 38     sub pc,pc,-12744
12127 + *[0-9a-f]*:   ee c7 95 1b     sub r7,r7,-27365
12128 + *[0-9a-f]*:   f2 c2 bc 32     sub r2,r9,-17358
12129 +
12130 +[0-9a-f]* <satsub_w2>:
12131 + *[0-9a-f]*:   fe df 00 00     satsub\.w pc,pc,0
12132 + *[0-9a-f]*:   f8 dc ff ff     satsub\.w r12,r12,-1
12133 + *[0-9a-f]*:   ea d5 80 00     satsub\.w r5,r5,-32768
12134 + *[0-9a-f]*:   e8 d4 7f ff     satsub\.w r4,r4,32767
12135 + *[0-9a-f]*:   fc de 00 01     satsub\.w lr,lr,1
12136 + *[0-9a-f]*:   fc d2 f8 29     satsub\.w r2,lr,-2007
12137 + *[0-9a-f]*:   f8 d7 fc f0     satsub\.w r7,r12,-784
12138 + *[0-9a-f]*:   ee d4 5a 8c     satsub\.w r4,r7,23180
12139 +
12140 +[0-9a-f]* <ld_d4>:
12141 + *[0-9a-f]*:   fe e0 00 00     ld\.d r0,pc\[0\]
12142 + *[0-9a-f]*:   f8 ee ff ff     ld\.d lr,r12\[-1\]
12143 + *[0-9a-f]*:   ea e8 80 00     ld\.d r8,r5\[-32768\]
12144 + *[0-9a-f]*:   e8 e6 7f ff     ld\.d r6,r4\[32767\]
12145 + *[0-9a-f]*:   fc e2 00 01     ld\.d r2,lr\[1\]
12146 + *[0-9a-f]*:   f6 ee 39 c0     ld\.d lr,r11\[14784\]
12147 + *[0-9a-f]*:   f2 e6 b6 27     ld\.d r6,r9\[-18905\]
12148 + *[0-9a-f]*:   e6 e2 e7 2d     ld\.d r2,r3\[-6355\]
12149 +
12150 +[0-9a-f]* <ld_w4>:
12151 + *[0-9a-f]*:   7e 0f           ld\.w pc,pc\[0x0\]
12152 + *[0-9a-f]*:   f8 fc ff ff     ld\.w r12,r12\[-1\]
12153 + *[0-9a-f]*:   ea f5 80 00     ld\.w r5,r5\[-32768\]
12154 + *[0-9a-f]*:   e8 f4 7f ff     ld\.w r4,r4\[32767\]
12155 + *[0-9a-f]*:   fc fe 00 01     ld\.w lr,lr\[1\]
12156 + *[0-9a-f]*:   f8 f0 a9 8b     ld\.w r0,r12\[-22133\]
12157 + *[0-9a-f]*:   fe fd af d7     ld\.w sp,pc\[-20521\]
12158 + *[0-9a-f]*:   d7 03           nop
12159 +
12160 +[0-9a-f]* <ld_sh4>:
12161 + *[0-9a-f]*:   9e 0f           ld\.sh pc,pc\[0x0\]
12162 + *[0-9a-f]*:   f9 0c ff ff     ld\.sh r12,r12\[-1\]
12163 + *[0-9a-f]*:   eb 05 80 00     ld\.sh r5,r5\[-32768\]
12164 + *[0-9a-f]*:   e9 04 7f ff     ld\.sh r4,r4\[32767\]
12165 + *[0-9a-f]*:   fd 0e 00 01     ld\.sh lr,lr\[1\]
12166 + *[0-9a-f]*:   f5 06 78 d2     ld\.sh r6,r10\[30930\]
12167 + *[0-9a-f]*:   f5 06 55 d5     ld\.sh r6,r10\[21973\]
12168 + *[0-9a-f]*:   d7 03           nop
12169 +
12170 +[0-9a-f]* <ld_uh4>:
12171 + *[0-9a-f]*:   9e 8f           ld\.uh pc,pc\[0x0\]
12172 + *[0-9a-f]*:   f9 1c ff ff     ld\.uh r12,r12\[-1\]
12173 + *[0-9a-f]*:   eb 15 80 00     ld\.uh r5,r5\[-32768\]
12174 + *[0-9a-f]*:   e9 14 7f ff     ld\.uh r4,r4\[32767\]
12175 + *[0-9a-f]*:   fd 1e 00 01     ld\.uh lr,lr\[1\]
12176 + *[0-9a-f]*:   f3 11 cb d6     ld\.uh r1,r9\[-13354\]
12177 + *[0-9a-f]*:   f7 1e 53 59     ld\.uh lr,r11\[21337\]
12178 + *[0-9a-f]*:   d7 03           nop
12179 +
12180 +[0-9a-f]* <ld_sb1>:
12181 + *[0-9a-f]*:   ff 2f 00 00     ld\.sb pc,pc\[0\]
12182 + *[0-9a-f]*:   f9 2c ff ff     ld\.sb r12,r12\[-1\]
12183 + *[0-9a-f]*:   eb 25 80 00     ld\.sb r5,r5\[-32768\]
12184 + *[0-9a-f]*:   e9 24 7f ff     ld\.sb r4,r4\[32767\]
12185 + *[0-9a-f]*:   fd 2e 00 01     ld\.sb lr,lr\[1\]
12186 + *[0-9a-f]*:   fb 27 90 09     ld\.sb r7,sp\[-28663\]
12187 + *[0-9a-f]*:   e3 22 e9 09     ld\.sb r2,r1\[-5879\]
12188 + *[0-9a-f]*:   e7 2c 49 2e     ld\.sb r12,r3\[18734\]
12189 +
12190 +[0-9a-f]* <ld_ub4>:
12191 + *[0-9a-f]*:   1f 8f           ld\.ub pc,pc\[0x0\]
12192 + *[0-9a-f]*:   f9 3c ff ff     ld\.ub r12,r12\[-1\]
12193 + *[0-9a-f]*:   eb 35 80 00     ld\.ub r5,r5\[-32768\]
12194 + *[0-9a-f]*:   e9 34 7f ff     ld\.ub r4,r4\[32767\]
12195 + *[0-9a-f]*:   1d 9e           ld\.ub lr,lr\[0x1\]
12196 + *[0-9a-f]*:   e9 3f 20 55     ld\.ub pc,r4\[8277\]
12197 + *[0-9a-f]*:   f9 35 4a e4     ld\.ub r5,r12\[19172\]
12198 + *[0-9a-f]*:   fd 3a 66 eb     ld\.ub r10,lr\[26347\]
12199 +
12200 +[0-9a-f]* <st_d4>:
12201 + *[0-9a-f]*:   fe e1 00 00     st\.d pc\[0\],r0
12202 + *[0-9a-f]*:   f8 ef ff ff     st\.d r12\[-1\],lr
12203 + *[0-9a-f]*:   ea e9 80 00     st\.d r5\[-32768\],r8
12204 + *[0-9a-f]*:   e8 e7 7f ff     st\.d r4\[32767\],r6
12205 + *[0-9a-f]*:   fc e3 00 01     st\.d lr\[1\],r2
12206 + *[0-9a-f]*:   ea eb 33 90     st\.d r5\[13200\],r10
12207 + *[0-9a-f]*:   ea eb 24 88     st\.d r5\[9352\],r10
12208 + *[0-9a-f]*:   ea e5 7e 75     st\.d r5\[32373\],r4
12209 +
12210 +[0-9a-f]* <st_w4>:
12211 + *[0-9a-f]*:   9f 0f           st\.w pc\[0x0\],pc
12212 + *[0-9a-f]*:   f9 4c ff ff     st\.w r12\[-1\],r12
12213 + *[0-9a-f]*:   eb 45 80 00     st\.w r5\[-32768\],r5
12214 + *[0-9a-f]*:   e9 44 7f ff     st\.w r4\[32767\],r4
12215 + *[0-9a-f]*:   fd 4e 00 01     st\.w lr\[1\],lr
12216 + *[0-9a-f]*:   fb 47 17 f8     st\.w sp\[6136\],r7
12217 + *[0-9a-f]*:   ed 4c 69 cf     st\.w r6\[27087\],r12
12218 + *[0-9a-f]*:   d7 03           nop
12219 +
12220 +[0-9a-f]* <st_h4>:
12221 + *[0-9a-f]*:   be 0f           st\.h pc\[0x0\],pc
12222 + *[0-9a-f]*:   f9 5c ff ff     st\.h r12\[-1\],r12
12223 + *[0-9a-f]*:   eb 55 80 00     st\.h r5\[-32768\],r5
12224 + *[0-9a-f]*:   e9 54 7f ff     st\.h r4\[32767\],r4
12225 + *[0-9a-f]*:   fd 5e 00 01     st\.h lr\[1\],lr
12226 + *[0-9a-f]*:   e9 57 d9 16     st\.h r4\[-9962\],r7
12227 + *[0-9a-f]*:   f3 53 c0 86     st\.h r9\[-16250\],r3
12228 + *[0-9a-f]*:   d7 03           nop
12229 +
12230 +[0-9a-f]* <st_b4>:
12231 + *[0-9a-f]*:   be 8f           st\.b pc\[0x0\],pc
12232 + *[0-9a-f]*:   f9 6c ff ff     st\.b r12\[-1\],r12
12233 + *[0-9a-f]*:   eb 65 80 00     st\.b r5\[-32768\],r5
12234 + *[0-9a-f]*:   e9 64 7f ff     st\.b r4\[32767\],r4
12235 + *[0-9a-f]*:   bc 9e           st\.b lr\[0x1\],lr
12236 + *[0-9a-f]*:   f9 66 75 96     st\.b r12\[30102\],r6
12237 + *[0-9a-f]*:   eb 61 71 31     st\.b r5\[28977\],r1
12238 + *[0-9a-f]*:   e1 61 15 5e     st\.b r0\[5470\],r1
12239 +
12240 +[0-9a-f]* <mfsr>:
12241 + *[0-9a-f]*:   e1 bf 00 00     mfsr pc,0x0
12242 + *[0-9a-f]*:   e1 bc 00 ff     mfsr r12,0x3fc
12243 + *[0-9a-f]*:   e1 b5 00 80     mfsr r5,0x200
12244 + *[0-9a-f]*:   e1 b4 00 7f     mfsr r4,0x1fc
12245 + *[0-9a-f]*:   e1 be 00 01     mfsr lr,0x4
12246 + *[0-9a-f]*:   e1 b2 00 ae     mfsr r2,0x2b8
12247 + *[0-9a-f]*:   e1 b4 00 41     mfsr r4,0x104
12248 + *[0-9a-f]*:   e1 ba 00 fe     mfsr r10,0x3f8
12249 +
12250 +[0-9a-f]* <mtsr>:
12251 + *[0-9a-f]*:   e3 bf 00 00     mtsr 0x0,pc
12252 + *[0-9a-f]*:   e3 bc 00 ff     mtsr 0x3fc,r12
12253 + *[0-9a-f]*:   e3 b5 00 80     mtsr 0x200,r5
12254 + *[0-9a-f]*:   e3 b4 00 7f     mtsr 0x1fc,r4
12255 + *[0-9a-f]*:   e3 be 00 01     mtsr 0x4,lr
12256 + *[0-9a-f]*:   e3 ba 00 38     mtsr 0xe0,r10
12257 + *[0-9a-f]*:   e3 bc 00 d1     mtsr 0x344,r12
12258 + *[0-9a-f]*:   e3 b9 00 4c     mtsr 0x130,r9
12259 +
12260 +[0-9a-f]* <mfdr>:
12261 + *[0-9a-f]*:   e5 bf 00 00     mfdr pc,0x0
12262 + *[0-9a-f]*:   e5 bc 00 ff     mfdr r12,0x3fc
12263 + *[0-9a-f]*:   e5 b5 00 80     mfdr r5,0x200
12264 + *[0-9a-f]*:   e5 b4 00 7f     mfdr r4,0x1fc
12265 + *[0-9a-f]*:   e5 be 00 01     mfdr lr,0x4
12266 + *[0-9a-f]*:   e5 b6 00 e9     mfdr r6,0x3a4
12267 + *[0-9a-f]*:   e5 b5 00 09     mfdr r5,0x24
12268 + *[0-9a-f]*:   e5 b9 00 4b     mfdr r9,0x12c
12269 +
12270 +[0-9a-f]* <mtdr>:
12271 + *[0-9a-f]*:   e7 bf 00 00     mtdr 0x0,pc
12272 + *[0-9a-f]*:   e7 bc 00 ff     mtdr 0x3fc,r12
12273 + *[0-9a-f]*:   e7 b5 00 80     mtdr 0x200,r5
12274 + *[0-9a-f]*:   e7 b4 00 7f     mtdr 0x1fc,r4
12275 + *[0-9a-f]*:   e7 be 00 01     mtdr 0x4,lr
12276 + *[0-9a-f]*:   e7 b8 00 2d     mtdr 0xb4,r8
12277 + *[0-9a-f]*:   e7 ba 00 b4     mtdr 0x2d0,r10
12278 + *[0-9a-f]*:   e7 be 00 66     mtdr 0x198,lr
12279 +
12280 +[0-9a-f]* <sleep>:
12281 + *[0-9a-f]*:   e9 b0 00 00     sleep 0x0
12282 + *[0-9a-f]*:   e9 b0 00 ff     sleep 0xff
12283 + *[0-9a-f]*:   e9 b0 00 80     sleep 0x80
12284 + *[0-9a-f]*:   e9 b0 00 7f     sleep 0x7f
12285 + *[0-9a-f]*:   e9 b0 00 01     sleep 0x1
12286 + *[0-9a-f]*:   e9 b0 00 fe     sleep 0xfe
12287 + *[0-9a-f]*:   e9 b0 00 0f     sleep 0xf
12288 + *[0-9a-f]*:   e9 b0 00 2b     sleep 0x2b
12289 +
12290 +[0-9a-f]* <sync>:
12291 + *[0-9a-f]*:   eb b0 00 00     sync 0x0
12292 + *[0-9a-f]*:   eb b0 00 ff     sync 0xff
12293 + *[0-9a-f]*:   eb b0 00 80     sync 0x80
12294 + *[0-9a-f]*:   eb b0 00 7f     sync 0x7f
12295 + *[0-9a-f]*:   eb b0 00 01     sync 0x1
12296 + *[0-9a-f]*:   eb b0 00 a6     sync 0xa6
12297 + *[0-9a-f]*:   eb b0 00 e6     sync 0xe6
12298 + *[0-9a-f]*:   eb b0 00 b4     sync 0xb4
12299 +
12300 +[0-9a-f]* <bld>:
12301 + *[0-9a-f]*:   ed bf 00 00     bld pc,0x0
12302 + *[0-9a-f]*:   ed bc 00 1f     bld r12,0x1f
12303 + *[0-9a-f]*:   ed b5 00 10     bld r5,0x10
12304 + *[0-9a-f]*:   ed b4 00 0f     bld r4,0xf
12305 + *[0-9a-f]*:   ed be 00 01     bld lr,0x1
12306 + *[0-9a-f]*:   ed b9 00 0f     bld r9,0xf
12307 + *[0-9a-f]*:   ed b0 00 04     bld r0,0x4
12308 + *[0-9a-f]*:   ed be 00 1a     bld lr,0x1a
12309 +
12310 +[0-9a-f]* <bst>:
12311 + *[0-9a-f]*:   ef bf 00 00     bst pc,0x0
12312 + *[0-9a-f]*:   ef bc 00 1f     bst r12,0x1f
12313 + *[0-9a-f]*:   ef b5 00 10     bst r5,0x10
12314 + *[0-9a-f]*:   ef b4 00 0f     bst r4,0xf
12315 + *[0-9a-f]*:   ef be 00 01     bst lr,0x1
12316 + *[0-9a-f]*:   ef ba 00 1c     bst r10,0x1c
12317 + *[0-9a-f]*:   ef b0 00 03     bst r0,0x3
12318 + *[0-9a-f]*:   ef bd 00 02     bst sp,0x2
12319 +
12320 +[0-9a-f]* <sats>:
12321 + *[0-9a-f]*:   f1 bf 00 00     sats pc,0x0
12322 + *[0-9a-f]*:   f1 bc 03 ff     sats r12>>0x1f,0x1f
12323 + *[0-9a-f]*:   f1 b5 02 10     sats r5>>0x10,0x10
12324 + *[0-9a-f]*:   f1 b4 01 ef     sats r4>>0xf,0xf
12325 + *[0-9a-f]*:   f1 be 00 21     sats lr>>0x1,0x1
12326 + *[0-9a-f]*:   f1 ba 02 63     sats r10>>0x3,0x13
12327 + *[0-9a-f]*:   f1 ba 03 42     sats r10>>0x2,0x1a
12328 + *[0-9a-f]*:   f1 b1 00 34     sats r1>>0x14,0x1
12329 +
12330 +[0-9a-f]* <satu>:
12331 + *[0-9a-f]*:   f1 bf 04 00     satu pc,0x0
12332 + *[0-9a-f]*:   f1 bc 07 ff     satu r12>>0x1f,0x1f
12333 + *[0-9a-f]*:   f1 b5 06 10     satu r5>>0x10,0x10
12334 + *[0-9a-f]*:   f1 b4 05 ef     satu r4>>0xf,0xf
12335 + *[0-9a-f]*:   f1 be 04 21     satu lr>>0x1,0x1
12336 + *[0-9a-f]*:   f1 bf 04 e5     satu pc>>0x5,0x7
12337 + *[0-9a-f]*:   f1 b7 04 a5     satu r7>>0x5,0x5
12338 + *[0-9a-f]*:   f1 b2 06 7a     satu r2>>0x1a,0x13
12339 +
12340 +[0-9a-f]* <satrnds>:
12341 + *[0-9a-f]*:   f3 bf 00 00     satrnds pc,0x0
12342 + *[0-9a-f]*:   f3 bc 03 ff     satrnds r12>>0x1f,0x1f
12343 + *[0-9a-f]*:   f3 b5 02 10     satrnds r5>>0x10,0x10
12344 + *[0-9a-f]*:   f3 b4 01 ef     satrnds r4>>0xf,0xf
12345 + *[0-9a-f]*:   f3 be 00 21     satrnds lr>>0x1,0x1
12346 + *[0-9a-f]*:   f3 b0 02 75     satrnds r0>>0x15,0x13
12347 + *[0-9a-f]*:   f3 bd 00 40     satrnds sp,0x2
12348 + *[0-9a-f]*:   f3 b7 03 a6     satrnds r7>>0x6,0x1d
12349 +
12350 +[0-9a-f]* <satrndu>:
12351 + *[0-9a-f]*:   f3 bf 04 00     satrndu pc,0x0
12352 + *[0-9a-f]*:   f3 bc 07 ff     satrndu r12>>0x1f,0x1f
12353 + *[0-9a-f]*:   f3 b5 06 10     satrndu r5>>0x10,0x10
12354 + *[0-9a-f]*:   f3 b4 05 ef     satrndu r4>>0xf,0xf
12355 + *[0-9a-f]*:   f3 be 04 21     satrndu lr>>0x1,0x1
12356 + *[0-9a-f]*:   f3 bc 07 40     satrndu r12,0x1a
12357 + *[0-9a-f]*:   f3 b4 04 75     satrndu r4>>0x15,0x3
12358 + *[0-9a-f]*:   f3 ba 06 03     satrndu r10>>0x3,0x10
12359 +
12360 +[0-9a-f]* <subfc>:
12361 + *[0-9a-f]*:   f5 bf 00 00     subfeq pc,0
12362 + *[0-9a-f]*:   f5 bc 0f ff     subfal r12,-1
12363 + *[0-9a-f]*:   f5 b5 08 80     subfls r5,-128
12364 + *[0-9a-f]*:   f5 b4 07 7f     subfpl r4,127
12365 + *[0-9a-f]*:   f5 be 01 01     subfne lr,1
12366 + *[0-9a-f]*:   f5 ba 08 08     subfls r10,8
12367 + *[0-9a-f]*:   f5 bb 0d 63     subfvc r11,99
12368 + *[0-9a-f]*:   f5 b2 0c 49     subfvs r2,73
12369 +
12370 +[0-9a-f]* <subc>:
12371 + *[0-9a-f]*:   f7 bf 00 00     subeq pc,0
12372 + *[0-9a-f]*:   f7 bc 0f ff     subal r12,-1
12373 + *[0-9a-f]*:   f7 b5 08 80     subls r5,-128
12374 + *[0-9a-f]*:   f7 b4 07 7f     subpl r4,127
12375 + *[0-9a-f]*:   f7 be 01 01     subne lr,1
12376 + *[0-9a-f]*:   f7 bc 08 76     subls r12,118
12377 + *[0-9a-f]*:   f7 be 0d f4     subvc lr,-12
12378 + *[0-9a-f]*:   f7 b4 06 f3     submi r4,-13
12379 +
12380 +[0-9a-f]* <movc2>:
12381 + *[0-9a-f]*:   f9 bf 00 00     moveq pc,0
12382 + *[0-9a-f]*:   f9 bc 0f ff     moval r12,-1
12383 + *[0-9a-f]*:   f9 b5 08 80     movls r5,-128
12384 + *[0-9a-f]*:   f9 b4 07 7f     movpl r4,127
12385 + *[0-9a-f]*:   f9 be 01 01     movne lr,1
12386 + *[0-9a-f]*:   f9 b3 05 86     movlt r3,-122
12387 + *[0-9a-f]*:   f9 b8 0d 02     movvc r8,2
12388 + *[0-9a-f]*:   f9 b7 01 91     movne r7,-111
12389 +
12390 +[0-9a-f]* <cp_b>:
12391 + *[0-9a-f]*:   e0 0f 18 00     cp\.b pc,r0
12392 + *[0-9a-f]*:   fe 00 18 00     cp\.b r0,pc
12393 + *[0-9a-f]*:   f0 07 18 00     cp\.b r7,r8
12394 + *[0-9a-f]*:   ee 08 18 00     cp\.b r8,r7
12395 +
12396 +[0-9a-f]* <cp_h>:
12397 + *[0-9a-f]*:   e0 0f 19 00     cp\.h pc,r0
12398 + *[0-9a-f]*:   fe 00 19 00     cp\.h r0,pc
12399 + *[0-9a-f]*:   f0 07 19 00     cp\.h r7,r8
12400 + *[0-9a-f]*:   ee 08 19 00     cp\.h r8,r7
12401 +
12402 +[0-9a-f]* <ldm>:
12403 + *[0-9a-f]*:   e1 cf 00 7e     ldm pc,r1-r6
12404 + *[0-9a-f]*:   e1 cc ff ff     ldm r12,r0-pc
12405 + *[0-9a-f]*:   e1 c5 80 00     ldm r5,pc
12406 + *[0-9a-f]*:   e1 c4 7f ff     ldm r4,r0-lr
12407 + *[0-9a-f]*:   e1 ce 00 01     ldm lr,r0
12408 + *[0-9a-f]*:   e1 c9 40 22     ldm r9,r1,r5,lr
12409 + *[0-9a-f]*:   e1 cb 81 ec     ldm r11,r2-r3,r5-r8,pc
12410 + *[0-9a-f]*:   e1 c6 a2 09     ldm r6,r0,r3,r9,sp,pc
12411 +
12412 +[0-9a-f]* <ldm_pu>:
12413 + *[0-9a-f]*:   e3 cf 03 c0     ldm pc\+\+,r6-r9
12414 + *[0-9a-f]*:   e3 cc ff ff     ldm r12\+\+,r0-pc
12415 + *[0-9a-f]*:   e3 c5 80 00     ldm r5\+\+,pc
12416 + *[0-9a-f]*:   e3 c4 7f ff     ldm r4\+\+,r0-lr
12417 + *[0-9a-f]*:   e3 ce 00 01     ldm lr\+\+,r0
12418 + *[0-9a-f]*:   e3 cc d5 38     ldm r12\+\+,r3-r5,r8,r10,r12,lr-pc
12419 + *[0-9a-f]*:   e3 ca c0 74     ldm r10\+\+,r2,r4-r6,lr-pc
12420 + *[0-9a-f]*:   e3 c6 7e 1a     ldm r6\+\+,r1,r3-r4,r9-lr
12421 +
12422 +[0-9a-f]* <ldmts>:
12423 + *[0-9a-f]*:   e5 cf 01 80     ldmts pc,r7-r8
12424 + *[0-9a-f]*:   e5 cc ff ff     ldmts r12,r0-pc
12425 + *[0-9a-f]*:   e5 c5 80 00     ldmts r5,pc
12426 + *[0-9a-f]*:   e5 c4 7f ff     ldmts r4,r0-lr
12427 + *[0-9a-f]*:   e5 ce 00 01     ldmts lr,r0
12428 + *[0-9a-f]*:   e5 c0 18 06     ldmts r0,r1-r2,r11-r12
12429 + *[0-9a-f]*:   e5 ce 61 97     ldmts lr,r0-r2,r4,r7-r8,sp-lr
12430 + *[0-9a-f]*:   e5 cc c2 3b     ldmts r12,r0-r1,r3-r5,r9,lr-pc
12431 +
12432 +[0-9a-f]* <ldmts_pu>:
12433 + *[0-9a-f]*:   e7 cf 02 00     ldmts pc\+\+,r9
12434 + *[0-9a-f]*:   e7 cc ff ff     ldmts r12\+\+,r0-pc
12435 + *[0-9a-f]*:   e7 c5 80 00     ldmts r5\+\+,pc
12436 + *[0-9a-f]*:   e7 c4 7f ff     ldmts r4\+\+,r0-lr
12437 + *[0-9a-f]*:   e7 ce 00 01     ldmts lr\+\+,r0
12438 + *[0-9a-f]*:   e7 cd 0a bd     ldmts sp\+\+,r0,r2-r5,r7,r9,r11
12439 + *[0-9a-f]*:   e7 c5 0c 8e     ldmts r5\+\+,r1-r3,r7,r10-r11
12440 + *[0-9a-f]*:   e7 c8 a1 9c     ldmts r8\+\+,r2-r4,r7-r8,sp,pc
12441 +
12442 +[0-9a-f]* <stm>:
12443 + *[0-9a-f]*:   e9 cf 00 80     stm pc,r7
12444 + *[0-9a-f]*:   e9 cc ff ff     stm r12,r0-pc
12445 + *[0-9a-f]*:   e9 c5 80 00     stm r5,pc
12446 + *[0-9a-f]*:   e9 c4 7f ff     stm r4,r0-lr
12447 + *[0-9a-f]*:   e9 ce 00 01     stm lr,r0
12448 + *[0-9a-f]*:   e9 cd 49 2c     stm sp,r2-r3,r5,r8,r11,lr
12449 + *[0-9a-f]*:   e9 c4 4c 5f     stm r4,r0-r4,r6,r10-r11,lr
12450 + *[0-9a-f]*:   e9 c9 f2 22     stm r9,r1,r5,r9,r12-pc
12451 +
12452 +[0-9a-f]* <stm_pu>:
12453 + *[0-9a-f]*:   eb cf 00 70     stm --pc,r4-r6
12454 + *[0-9a-f]*:   eb cc ff ff     stm --r12,r0-pc
12455 + *[0-9a-f]*:   eb c5 80 00     stm --r5,pc
12456 + *[0-9a-f]*:   eb c4 7f ff     stm --r4,r0-lr
12457 + *[0-9a-f]*:   eb ce 00 01     stm --lr,r0
12458 + *[0-9a-f]*:   eb cb fb f1     stm --r11,r0,r4-r9,r11-pc
12459 + *[0-9a-f]*:   eb cb 56 09     stm --r11,r0,r3,r9-r10,r12,lr
12460 + *[0-9a-f]*:   eb c6 63 04     stm --r6,r2,r8-r9,sp-lr
12461 +
12462 +[0-9a-f]* <stmts>:
12463 + *[0-9a-f]*:   ed cf 01 00     stmts pc,r8
12464 + *[0-9a-f]*:   ed cc ff ff     stmts r12,r0-pc
12465 + *[0-9a-f]*:   ed c5 80 00     stmts r5,pc
12466 + *[0-9a-f]*:   ed c4 7f ff     stmts r4,r0-lr
12467 + *[0-9a-f]*:   ed ce 00 01     stmts lr,r0
12468 + *[0-9a-f]*:   ed c1 c6 5b     stmts r1,r0-r1,r3-r4,r6,r9-r10,lr-pc
12469 + *[0-9a-f]*:   ed c3 1d c1     stmts r3,r0,r6-r8,r10-r12
12470 + *[0-9a-f]*:   ed cb d6 d1     stmts r11,r0,r4,r6-r7,r9-r10,r12,lr-pc
12471 +
12472 +[0-9a-f]* <stmts_pu>:
12473 + *[0-9a-f]*:   ef cf 01 c0     stmts --pc,r6-r8
12474 + *[0-9a-f]*:   ef cc ff ff     stmts --r12,r0-pc
12475 + *[0-9a-f]*:   ef c5 80 00     stmts --r5,pc
12476 + *[0-9a-f]*:   ef c4 7f ff     stmts --r4,r0-lr
12477 + *[0-9a-f]*:   ef ce 00 01     stmts --lr,r0
12478 + *[0-9a-f]*:   ef c2 36 19     stmts --r2,r0,r3-r4,r9-r10,r12-sp
12479 + *[0-9a-f]*:   ef c3 c0 03     stmts --r3,r0-r1,lr-pc
12480 + *[0-9a-f]*:   ef c0 44 7d     stmts --r0,r0,r2-r6,r10,lr
12481 +
12482 +[0-9a-f]* <ldins_h>:
12483 + *[0-9a-f]*:   ff df 00 00     ldins\.h pc:b,pc\[0\]
12484 + *[0-9a-f]*:   f9 dc 1f ff     ldins\.h r12:t,r12\[-2\]
12485 + *[0-9a-f]*:   eb d5 18 00     ldins\.h r5:t,r5\[-4096\]
12486 + *[0-9a-f]*:   e9 d4 07 ff     ldins\.h r4:b,r4\[4094\]
12487 + *[0-9a-f]*:   fd de 10 01     ldins\.h lr:t,lr\[2\]
12488 + *[0-9a-f]*:   fd d0 13 c5     ldins\.h r0:t,lr\[1930\]
12489 + *[0-9a-f]*:   ef d3 0e f5     ldins\.h r3:b,r7\[-534\]
12490 + *[0-9a-f]*:   f9 d2 0b 9a     ldins\.h r2:b,r12\[-2252\]
12491 +
12492 +[0-9a-f]* <ldins_b>:
12493 + *[0-9a-f]*:   ff df 40 00     ldins\.b pc:b,pc\[0\]
12494 + *[0-9a-f]*:   f9 dc 7f ff     ldins\.b r12:t,r12\[-1\]
12495 + *[0-9a-f]*:   eb d5 68 00     ldins\.b r5:u,r5\[-2048\]
12496 + *[0-9a-f]*:   e9 d4 57 ff     ldins\.b r4:l,r4\[2047\]
12497 + *[0-9a-f]*:   fd de 50 01     ldins\.b lr:l,lr\[1\]
12498 + *[0-9a-f]*:   e9 d6 7d 6a     ldins\.b r6:t,r4\[-662\]
12499 + *[0-9a-f]*:   e3 d5 4f 69     ldins\.b r5:b,r1\[-151\]
12500 + *[0-9a-f]*:   f7 da 78 7d     ldins\.b r10:t,r11\[-1923\]
12501 +
12502 +[0-9a-f]* <ldswp_sh>:
12503 + *[0-9a-f]*:   ff df 20 00     ldswp\.sh pc,pc\[0\]
12504 + *[0-9a-f]*:   f9 dc 2f ff     ldswp\.sh r12,r12\[-2\]
12505 + *[0-9a-f]*:   eb d5 28 00     ldswp\.sh r5,r5\[-4096\]
12506 + *[0-9a-f]*:   e9 d4 27 ff     ldswp\.sh r4,r4\[4094\]
12507 + *[0-9a-f]*:   fd de 20 01     ldswp\.sh lr,lr\[2\]
12508 + *[0-9a-f]*:   f5 d9 27 84     ldswp\.sh r9,r10\[3848\]
12509 + *[0-9a-f]*:   f9 d4 2c 04     ldswp\.sh r4,r12\[-2040\]
12510 + *[0-9a-f]*:   e5 da 26 08     ldswp\.sh r10,r2\[3088\]
12511 +
12512 +[0-9a-f]* <ldswp_uh>:
12513 + *[0-9a-f]*:   ff df 30 00     ldswp\.uh pc,pc\[0\]
12514 + *[0-9a-f]*:   f9 dc 3f ff     ldswp\.uh r12,r12\[-2\]
12515 + *[0-9a-f]*:   eb d5 38 00     ldswp\.uh r5,r5\[-4096\]
12516 + *[0-9a-f]*:   e9 d4 37 ff     ldswp\.uh r4,r4\[4094\]
12517 + *[0-9a-f]*:   fd de 30 01     ldswp\.uh lr,lr\[2\]
12518 + *[0-9a-f]*:   f3 d4 37 46     ldswp\.uh r4,r9\[3724\]
12519 + *[0-9a-f]*:   fb de 3c bc     ldswp\.uh lr,sp\[-1672\]
12520 + *[0-9a-f]*:   f9 d8 38 7d     ldswp\.uh r8,r12\[-3846\]
12521 +
12522 +[0-9a-f]* <ldswp_w>:
12523 + *[0-9a-f]*:   ff df 80 00     ldswp\.w pc,pc\[0\]
12524 + *[0-9a-f]*:   f9 dc 8f ff     ldswp\.w r12,r12\[-4\]
12525 + *[0-9a-f]*:   eb d5 88 00     ldswp\.w r5,r5\[-8192\]
12526 + *[0-9a-f]*:   e9 d4 87 ff     ldswp\.w r4,r4\[8188\]
12527 + *[0-9a-f]*:   fd de 80 01     ldswp\.w lr,lr\[4\]
12528 + *[0-9a-f]*:   ef dd 81 d1     ldswp\.w sp,r7\[1860\]
12529 + *[0-9a-f]*:   eb df 8c c1     ldswp\.w pc,r5\[-3324\]
12530 + *[0-9a-f]*:   f5 dc 8c c8     ldswp\.w r12,r10\[-3296\]
12531 +
12532 +[0-9a-f]* <stswp_h>:
12533 + *[0-9a-f]*:   ff df 90 00     stswp\.h pc\[0\],pc
12534 + *[0-9a-f]*:   f9 dc 9f ff     stswp\.h r12\[-2\],r12
12535 + *[0-9a-f]*:   eb d5 98 00     stswp\.h r5\[-4096\],r5
12536 + *[0-9a-f]*:   e9 d4 97 ff     stswp\.h r4\[4094\],r4
12537 + *[0-9a-f]*:   fd de 90 01     stswp\.h lr\[2\],lr
12538 + *[0-9a-f]*:   ef da 90 20     stswp\.h r7\[64\],r10
12539 + *[0-9a-f]*:   f5 d2 95 e8     stswp\.h r10\[3024\],r2
12540 + *[0-9a-f]*:   e1 da 9b 74     stswp\.h r0\[-2328\],r10
12541 +
12542 +[0-9a-f]* <stswp_w>:
12543 + *[0-9a-f]*:   ff df a0 00     stswp\.w pc\[0\],pc
12544 + *[0-9a-f]*:   f9 dc af ff     stswp\.w r12\[-4\],r12
12545 + *[0-9a-f]*:   eb d5 a8 00     stswp\.w r5\[-8192\],r5
12546 + *[0-9a-f]*:   e9 d4 a7 ff     stswp\.w r4\[8188\],r4
12547 + *[0-9a-f]*:   fd de a0 01     stswp\.w lr\[4\],lr
12548 + *[0-9a-f]*:   ff d8 a1 21     stswp\.w pc\[1156\],r8
12549 + *[0-9a-f]*:   fb da a7 ce     stswp\.w sp\[7992\],r10
12550 + *[0-9a-f]*:   f1 d5 ae db     stswp\.w r8\[-1172\],r5
12551 +
12552 +[0-9a-f]* <and2>:
12553 + *[0-9a-f]*:   ff ef 00 0f     and pc,pc,pc
12554 + *[0-9a-f]*:   f9 ec 01 fc     and r12,r12,r12<<0x1f
12555 + *[0-9a-f]*:   eb e5 01 05     and r5,r5,r5<<0x10
12556 + *[0-9a-f]*:   e9 e4 00 f4     and r4,r4,r4<<0xf
12557 + *[0-9a-f]*:   fd ee 00 1e     and lr,lr,lr<<0x1
12558 + *[0-9a-f]*:   e5 e1 00 1a     and r10,r2,r1<<0x1
12559 + *[0-9a-f]*:   f1 eb 01 bc     and r12,r8,r11<<0x1b
12560 + *[0-9a-f]*:   ef e0 00 3a     and r10,r7,r0<<0x3
12561 +
12562 +[0-9a-f]* <and3>:
12563 + *[0-9a-f]*:   ff ef 02 0f     and pc,pc,pc
12564 + *[0-9a-f]*:   f9 ec 03 fc     and r12,r12,r12>>0x1f
12565 + *[0-9a-f]*:   eb e5 03 05     and r5,r5,r5>>0x10
12566 + *[0-9a-f]*:   e9 e4 02 f4     and r4,r4,r4>>0xf
12567 + *[0-9a-f]*:   fd ee 02 1e     and lr,lr,lr>>0x1
12568 + *[0-9a-f]*:   f1 e7 03 1c     and r12,r8,r7>>0x11
12569 + *[0-9a-f]*:   e9 e9 03 4f     and pc,r4,r9>>0x14
12570 + *[0-9a-f]*:   f3 ea 02 ca     and r10,r9,r10>>0xc
12571 +
12572 +[0-9a-f]* <or2>:
12573 + *[0-9a-f]*:   ff ef 10 0f     or pc,pc,pc
12574 + *[0-9a-f]*:   f9 ec 11 fc     or r12,r12,r12<<0x1f
12575 + *[0-9a-f]*:   eb e5 11 05     or r5,r5,r5<<0x10
12576 + *[0-9a-f]*:   e9 e4 10 f4     or r4,r4,r4<<0xf
12577 + *[0-9a-f]*:   fd ee 10 1e     or lr,lr,lr<<0x1
12578 + *[0-9a-f]*:   fb eb 11 d8     or r8,sp,r11<<0x1d
12579 + *[0-9a-f]*:   f3 e2 11 cf     or pc,r9,r2<<0x1c
12580 + *[0-9a-f]*:   e3 e2 10 35     or r5,r1,r2<<0x3
12581 +
12582 +[0-9a-f]* <or3>:
12583 + *[0-9a-f]*:   ff ef 12 0f     or pc,pc,pc
12584 + *[0-9a-f]*:   f9 ec 13 fc     or r12,r12,r12>>0x1f
12585 + *[0-9a-f]*:   eb e5 13 05     or r5,r5,r5>>0x10
12586 + *[0-9a-f]*:   e9 e4 12 f4     or r4,r4,r4>>0xf
12587 + *[0-9a-f]*:   fd ee 12 1e     or lr,lr,lr>>0x1
12588 + *[0-9a-f]*:   fb ed 12 21     or r1,sp,sp>>0x2
12589 + *[0-9a-f]*:   e3 e1 13 d0     or r0,r1,r1>>0x1d
12590 + *[0-9a-f]*:   f9 e8 12 84     or r4,r12,r8>>0x8
12591 +
12592 +[0-9a-f]* <eor2>:
12593 + *[0-9a-f]*:   ff ef 20 0f     eor pc,pc,pc
12594 + *[0-9a-f]*:   f9 ec 21 fc     eor r12,r12,r12<<0x1f
12595 + *[0-9a-f]*:   eb e5 21 05     eor r5,r5,r5<<0x10
12596 + *[0-9a-f]*:   e9 e4 20 f4     eor r4,r4,r4<<0xf
12597 + *[0-9a-f]*:   fd ee 20 1e     eor lr,lr,lr<<0x1
12598 + *[0-9a-f]*:   f3 e4 20 ba     eor r10,r9,r4<<0xb
12599 + *[0-9a-f]*:   e1 e1 21 f4     eor r4,r0,r1<<0x1f
12600 + *[0-9a-f]*:   e5 ec 20 d6     eor r6,r2,r12<<0xd
12601 +
12602 +[0-9a-f]* <eor3>:
12603 + *[0-9a-f]*:   ff ef 22 0f     eor pc,pc,pc
12604 + *[0-9a-f]*:   f9 ec 23 fc     eor r12,r12,r12>>0x1f
12605 + *[0-9a-f]*:   eb e5 23 05     eor r5,r5,r5>>0x10
12606 + *[0-9a-f]*:   e9 e4 22 f4     eor r4,r4,r4>>0xf
12607 + *[0-9a-f]*:   fd ee 22 1e     eor lr,lr,lr>>0x1
12608 + *[0-9a-f]*:   eb e5 23 65     eor r5,r5,r5>>0x16
12609 + *[0-9a-f]*:   e3 ee 22 3a     eor r10,r1,lr>>0x3
12610 + *[0-9a-f]*:   fd ed 23 a7     eor r7,lr,sp>>0x1a
12611 +
12612 +[0-9a-f]* <sthh_w2>:
12613 + *[0-9a-f]*:   ff ef 8f 0f     sthh\.w pc\[pc\],pc:b,pc:b
12614 + *[0-9a-f]*:   f9 ec bc 3c     sthh\.w r12\[r12<<0x3\],r12:t,r12:t
12615 + *[0-9a-f]*:   eb e5 b5 25     sthh\.w r5\[r5<<0x2\],r5:t,r5:t
12616 + *[0-9a-f]*:   e9 e4 84 14     sthh\.w r4\[r4<<0x1\],r4:b,r4:b
12617 + *[0-9a-f]*:   fd ee be 1e     sthh\.w lr\[lr<<0x1\],lr:t,lr:t
12618 + *[0-9a-f]*:   e3 ec b6 3d     sthh\.w sp\[r6<<0x3\],r1:t,r12:t
12619 + *[0-9a-f]*:   f3 e9 b6 06     sthh\.w r6\[r6\],r9:t,r9:t
12620 + *[0-9a-f]*:   e1 eb 93 0a     sthh\.w r10\[r3\],r0:b,r11:t
12621 +
12622 +[0-9a-f]* <sthh_w1>:
12623 + *[0-9a-f]*:   ff ef c0 0f     sthh\.w pc\[0x0\],pc:b,pc:b
12624 + *[0-9a-f]*:   f9 ec ff fc     sthh\.w r12\[0x3fc\],r12:t,r12:t
12625 + *[0-9a-f]*:   eb e5 f8 05     sthh\.w r5\[0x200\],r5:t,r5:t
12626 + *[0-9a-f]*:   e9 e4 c7 f4     sthh\.w r4\[0x1fc\],r4:b,r4:b
12627 + *[0-9a-f]*:   fd ee f0 1e     sthh\.w lr\[0x4\],lr:t,lr:t
12628 + *[0-9a-f]*:   f3 e0 e6 54     sthh\.w r4\[0x194\],r9:t,r0:b
12629 + *[0-9a-f]*:   e5 ea e5 78     sthh\.w r8\[0x15c\],r2:t,r10:b
12630 + *[0-9a-f]*:   f3 e2 c2 bd     sthh\.w sp\[0xac\],r9:b,r2:b
12631 +
12632 +[0-9a-f]* <cop>:
12633 + *[0-9a-f]*:   e1 a0 00 00     cop cp0,cr0,cr0,cr0,0x0
12634 + *[0-9a-f]*:   e7 af ff ff     cop cp7,cr15,cr15,cr15,0x7f
12635 + *[0-9a-f]*:   e3 a8 75 55     cop cp3,cr5,cr5,cr5,0x31
12636 + *[0-9a-f]*:   e3 a8 44 44     cop cp2,cr4,cr4,cr4,0x30
12637 + *[0-9a-f]*:   e5 ad a8 37     cop cp5,cr8,cr3,cr7,0x5a
12638 +
12639 +[0-9a-f]* <ldc_w1>:
12640 + *[0-9a-f]*:   e9 a0 00 00     ldc\.w cp0,cr0,r0\[0x0\]
12641 + *[0-9a-f]*:   e9 af ef ff     ldc\.w cp7,cr15,pc\[0x3fc\]
12642 + *[0-9a-f]*:   e9 a5 65 80     ldc\.w cp3,cr5,r5\[0x200\]
12643 + *[0-9a-f]*:   e9 a4 44 7f     ldc\.w cp2,cr4,r4\[0x1fc\]
12644 + *[0-9a-f]*:   e9 ad 89 24     ldc\.w cp4,cr9,sp\[0x90\]
12645 +
12646 +[0-9a-f]* <ldc_w2>:
12647 + *[0-9a-f]*:   ef a0 00 40     ldc\.w cp0,cr0,--r0
12648 + *[0-9a-f]*:   ef af ef 40     ldc\.w cp7,cr15,--pc
12649 + *[0-9a-f]*:   ef a5 65 40     ldc\.w cp3,cr5,--r5
12650 + *[0-9a-f]*:   ef a4 44 40     ldc\.w cp2,cr4,--r4
12651 + *[0-9a-f]*:   ef ad 89 40     ldc\.w cp4,cr9,--sp
12652 +
12653 +[0-9a-f]* <ldc_w3>:
12654 + *[0-9a-f]*:   ef a0 10 00     ldc\.w cp0,cr0,r0\[r0\]
12655 + *[0-9a-f]*:   ef af ff 3f     ldc\.w cp7,cr15,pc\[pc<<0x3\]
12656 + *[0-9a-f]*:   ef a5 75 24     ldc\.w cp3,cr5,r5\[r4<<0x2\]
12657 + *[0-9a-f]*:   ef a4 54 13     ldc\.w cp2,cr4,r4\[r3<<0x1\]
12658 + *[0-9a-f]*:   ef ad 99 0c     ldc\.w cp4,cr9,sp\[r12\]
12659 +
12660 +[0-9a-f]* <ldc_d1>:
12661 + *[0-9a-f]*:   e9 a0 10 00     ldc\.d cp0,cr0,r0\[0x0\]
12662 + *[0-9a-f]*:   e9 af fe ff     ldc\.d cp7,cr14,pc\[0x3fc\]
12663 + *[0-9a-f]*:   e9 a5 76 80     ldc\.d cp3,cr6,r5\[0x200\]
12664 + *[0-9a-f]*:   e9 a4 54 7f     ldc\.d cp2,cr4,r4\[0x1fc\]
12665 + *[0-9a-f]*:   e9 ad 98 24     ldc\.d cp4,cr8,sp\[0x90\]
12666 +
12667 +[0-9a-f]* <ldc_d2>:
12668 + *[0-9a-f]*:   ef a0 00 50     ldc\.d cp0,cr0,--r0
12669 + *[0-9a-f]*:   ef af ee 50     ldc\.d cp7,cr14,--pc
12670 + *[0-9a-f]*:   ef a5 66 50     ldc\.d cp3,cr6,--r5
12671 + *[0-9a-f]*:   ef a4 44 50     ldc\.d cp2,cr4,--r4
12672 + *[0-9a-f]*:   ef ad 88 50     ldc\.d cp4,cr8,--sp
12673 +
12674 +[0-9a-f]* <ldc_d3>:
12675 + *[0-9a-f]*:   ef a0 10 40     ldc\.d cp0,cr0,r0\[r0\]
12676 + *[0-9a-f]*:   ef af fe 7f     ldc\.d cp7,cr14,pc\[pc<<0x3\]
12677 + *[0-9a-f]*:   ef a5 76 64     ldc\.d cp3,cr6,r5\[r4<<0x2\]
12678 + *[0-9a-f]*:   ef a4 54 53     ldc\.d cp2,cr4,r4\[r3<<0x1\]
12679 + *[0-9a-f]*:   ef ad 98 4c     ldc\.d cp4,cr8,sp\[r12\]
12680 +
12681 +[0-9a-f]* <stc_w1>:
12682 + *[0-9a-f]*:   eb a0 00 00     stc\.w cp0,r0\[0x0\],cr0
12683 + *[0-9a-f]*:   eb af ef ff     stc\.w cp7,pc\[0x3fc\],cr15
12684 + *[0-9a-f]*:   eb a5 65 80     stc\.w cp3,r5\[0x200\],cr5
12685 + *[0-9a-f]*:   eb a4 44 7f     stc\.w cp2,r4\[0x1fc\],cr4
12686 + *[0-9a-f]*:   eb ad 89 24     stc\.w cp4,sp\[0x90\],cr9
12687 +
12688 +[0-9a-f]* <stc_w2>:
12689 + *[0-9a-f]*:   ef a0 00 60     stc\.w cp0,r0\+\+,cr0
12690 + *[0-9a-f]*:   ef af ef 60     stc\.w cp7,pc\+\+,cr15
12691 + *[0-9a-f]*:   ef a5 65 60     stc\.w cp3,r5\+\+,cr5
12692 + *[0-9a-f]*:   ef a4 44 60     stc\.w cp2,r4\+\+,cr4
12693 + *[0-9a-f]*:   ef ad 89 60     stc\.w cp4,sp\+\+,cr9
12694 +
12695 +[0-9a-f]* <stc_w3>:
12696 + *[0-9a-f]*:   ef a0 10 80     stc\.w cp0,r0\[r0\],cr0
12697 + *[0-9a-f]*:   ef af ff bf     stc\.w cp7,pc\[pc<<0x3\],cr15
12698 + *[0-9a-f]*:   ef a5 75 a4     stc\.w cp3,r5\[r4<<0x2\],cr5
12699 + *[0-9a-f]*:   ef a4 54 93     stc\.w cp2,r4\[r3<<0x1\],cr4
12700 + *[0-9a-f]*:   ef ad 99 8c     stc\.w cp4,sp\[r12\],cr9
12701 +
12702 +[0-9a-f]* <stc_d1>:
12703 + *[0-9a-f]*:   eb a0 10 00     stc\.d cp0,r0\[0x0\],cr0
12704 + *[0-9a-f]*:   eb af fe ff     stc\.d cp7,pc\[0x3fc\],cr14
12705 + *[0-9a-f]*:   eb a5 76 80     stc\.d cp3,r5\[0x200\],cr6
12706 + *[0-9a-f]*:   eb a4 54 7f     stc\.d cp2,r4\[0x1fc\],cr4
12707 + *[0-9a-f]*:   eb ad 98 24     stc\.d cp4,sp\[0x90\],cr8
12708 +
12709 +[0-9a-f]* <stc_d2>:
12710 + *[0-9a-f]*:   ef a0 00 70     stc\.d cp0,r0\+\+,cr0
12711 + *[0-9a-f]*:   ef af ee 70     stc\.d cp7,pc\+\+,cr14
12712 + *[0-9a-f]*:   ef a5 66 70     stc\.d cp3,r5\+\+,cr6
12713 + *[0-9a-f]*:   ef a4 44 70     stc\.d cp2,r4\+\+,cr4
12714 + *[0-9a-f]*:   ef ad 88 70     stc\.d cp4,sp\+\+,cr8
12715 +
12716 +[0-9a-f]* <stc_d3>:
12717 + *[0-9a-f]*:   ef a0 10 c0     stc\.d cp0,r0\[r0\],cr0
12718 + *[0-9a-f]*:   ef af fe ff     stc\.d cp7,pc\[pc<<0x3\],cr14
12719 + *[0-9a-f]*:   ef a5 76 e4     stc\.d cp3,r5\[r4<<0x2\],cr6
12720 + *[0-9a-f]*:   ef a4 54 d3     stc\.d cp2,r4\[r3<<0x1\],cr4
12721 + *[0-9a-f]*:   ef ad 98 cc     stc\.d cp4,sp\[r12\],cr8
12722 +
12723 +[0-9a-f]* <ldc0_w>:
12724 + *[0-9a-f]*:   f1 a0 00 00     ldc0\.w cr0,r0\[0x0\]
12725 + *[0-9a-f]*:   f1 af ff ff     ldc0\.w cr15,pc\[0x3ffc\]
12726 + *[0-9a-f]*:   f1 a5 85 00     ldc0\.w cr5,r5\[0x2000\]
12727 + *[0-9a-f]*:   f1 a4 74 ff     ldc0\.w cr4,r4\[0x1ffc\]
12728 + *[0-9a-f]*:   f1 ad 09 93     ldc0\.w cr9,sp\[0x24c\]
12729 +
12730 +[0-9a-f]* <ldc0_d>:
12731 + *[0-9a-f]*:   f3 a0 00 00     ldc0\.d cr0,r0\[0x0\]
12732 + *[0-9a-f]*:   f3 af fe ff     ldc0\.d cr14,pc\[0x3ffc\]
12733 + *[0-9a-f]*:   f3 a5 86 00     ldc0\.d cr6,r5\[0x2000\]
12734 + *[0-9a-f]*:   f3 a4 74 ff     ldc0\.d cr4,r4\[0x1ffc\]
12735 + *[0-9a-f]*:   f3 ad 08 93     ldc0\.d cr8,sp\[0x24c\]
12736 +
12737 +[0-9a-f]* <stc0_w>:
12738 + *[0-9a-f]*:   f5 a0 00 00     stc0\.w r0\[0x0\],cr0
12739 + *[0-9a-f]*:   f5 af ff ff     stc0\.w pc\[0x3ffc\],cr15
12740 + *[0-9a-f]*:   f5 a5 85 00     stc0\.w r5\[0x2000\],cr5
12741 + *[0-9a-f]*:   f5 a4 74 ff     stc0\.w r4\[0x1ffc\],cr4
12742 + *[0-9a-f]*:   f5 ad 09 93     stc0\.w sp\[0x24c\],cr9
12743 +
12744 +[0-9a-f]* <stc0_d>:
12745 + *[0-9a-f]*:   f7 a0 00 00     stc0\.d r0\[0x0\],cr0
12746 + *[0-9a-f]*:   f7 af fe ff     stc0\.d pc\[0x3ffc\],cr14
12747 + *[0-9a-f]*:   f7 a5 86 00     stc0\.d r5\[0x2000\],cr6
12748 + *[0-9a-f]*:   f7 a4 74 ff     stc0\.d r4\[0x1ffc\],cr4
12749 + *[0-9a-f]*:   f7 ad 08 93     stc0\.d sp\[0x24c\],cr8
12750 +
12751 +[0-9a-f]* <memc>:
12752 + *[0-9a-f]*:   f6 10 00 00     memc 0,0x0
12753 + *[0-9a-f]*:   f6 1f ff ff     memc -4,0x1f
12754 + *[0-9a-f]*:   f6 18 40 00     memc -65536,0x10
12755 + *[0-9a-f]*:   f6 17 bf ff     memc 65532,0xf
12756 +
12757 +[0-9a-f]* <mems>:
12758 + *[0-9a-f]*:   f8 10 00 00     mems 0,0x0
12759 + *[0-9a-f]*:   f8 1f ff ff     mems -4,0x1f
12760 + *[0-9a-f]*:   f8 18 40 00     mems -65536,0x10
12761 + *[0-9a-f]*:   f8 17 bf ff     mems 65532,0xf
12762 +
12763 +[0-9a-f]* <memt>:
12764 + *[0-9a-f]*:   fa 10 00 00     memt 0,0x0
12765 + *[0-9a-f]*:   fa 1f ff ff     memt -4,0x1f
12766 + *[0-9a-f]*:   fa 18 40 00     memt -65536,0x10
12767 + *[0-9a-f]*:   fa 17 bf ff     memt 65532,0xf
12768 +
12769 +[0-9a-f]* <stcond>:
12770 + *[0-9a-f]*:   e1 70 00 00     stcond r0\[0\],r0
12771 + *[0-9a-f]*:   ff 7f ff ff     stcond pc\[-1\],pc
12772 + *[0-9a-f]*:   f1 77 80 00     stcond r8\[-32768\],r7
12773 + *[0-9a-f]*:   ef 78 7f ff     stcond r7\[32767\],r8
12774 + *[0-9a-f]*:   eb 7a 12 34     stcond r5\[4660\],r10
12775 +
12776 +[0-9a-f]* <ldcm_w>:
12777 + *[0-9a-f]*:   ed af 00 ff     ldcm\.w cp0,pc,cr0-cr7
12778 + *[0-9a-f]*:   ed a0 e0 01     ldcm\.w cp7,r0,cr0
12779 + *[0-9a-f]*:   ed a4 90 7f     ldcm\.w cp4,r4\+\+,cr0-cr6
12780 + *[0-9a-f]*:   ed a7 60 80     ldcm\.w cp3,r7,cr7
12781 + *[0-9a-f]*:   ed ac 30 72     ldcm\.w cp1,r12\+\+,cr1,cr4-cr6
12782 + *[0-9a-f]*:   ed af 01 ff     ldcm\.w cp0,pc,cr8-cr15
12783 + *[0-9a-f]*:   ed a0 e1 01     ldcm\.w cp7,r0,cr8
12784 + *[0-9a-f]*:   ed a4 91 7f     ldcm\.w cp4,r4\+\+,cr8-cr14
12785 + *[0-9a-f]*:   ed a7 61 80     ldcm\.w cp3,r7,cr15
12786 + *[0-9a-f]*:   ed ac 31 72     ldcm\.w cp1,r12\+\+,cr9,cr12-cr14
12787 +
12788 +[0-9a-f]* <ldcm_d>:
12789 + *[0-9a-f]*:   ed af 04 ff     ldcm\.d cp0,pc,cr0-cr15
12790 + *[0-9a-f]*:   ed a0 e4 01     ldcm\.d cp7,r0,cr0-cr1
12791 + *[0-9a-f]*:   ed a4 94 7f     ldcm\.d cp4,r4\+\+,cr0-cr13
12792 + *[0-9a-f]*:   ed a7 64 80     ldcm\.d cp3,r7,cr14-cr15
12793 + *[0-9a-f]*:   ed ac 54 93     ldcm\.d cp2,r12\+\+,cr0-cr3,cr8-cr9,cr14-cr15
12794 +
12795 +[0-9a-f]* <stcm_w>:
12796 + *[0-9a-f]*:   ed af 02 ff     stcm\.w cp0,pc,cr0-cr7
12797 + *[0-9a-f]*:   ed a0 e2 01     stcm\.w cp7,r0,cr0
12798 + *[0-9a-f]*:   ed a4 92 7f     stcm\.w cp4,--r4,cr0-cr6
12799 + *[0-9a-f]*:   ed a7 62 80     stcm\.w cp3,r7,cr7
12800 + *[0-9a-f]*:   ed ac 32 72     stcm\.w cp1,--r12,cr1,cr4-cr6
12801 + *[0-9a-f]*:   ed af 03 ff     stcm\.w cp0,pc,cr8-cr15
12802 + *[0-9a-f]*:   ed a0 e3 01     stcm\.w cp7,r0,cr8
12803 + *[0-9a-f]*:   ed a4 93 7f     stcm\.w cp4,--r4,cr8-cr14
12804 + *[0-9a-f]*:   ed a7 63 80     stcm\.w cp3,r7,cr15
12805 + *[0-9a-f]*:   ed ac 33 72     stcm\.w cp1,--r12,cr9,cr12-cr14
12806 +
12807 +[0-9a-f]* <stcm_d>:
12808 + *[0-9a-f]*:   ed af 05 ff     stcm\.d cp0,pc,cr0-cr15
12809 + *[0-9a-f]*:   ed a0 e5 01     stcm\.d cp7,r0,cr0-cr1
12810 + *[0-9a-f]*:   ed a4 95 7f     stcm\.d cp4,--r4,cr0-cr13
12811 + *[0-9a-f]*:   ed a7 65 80     stcm\.d cp3,r7,cr14-cr15
12812 + *[0-9a-f]*:   ed ac 55 93     stcm\.d cp2,--r12,cr0-cr3,cr8-cr9,cr14-cr15
12813 +
12814 +[0-9a-f]* <mvcr_w>:
12815 + *[0-9a-f]*:   ef af ef 00     mvcr\.w cp7,pc,cr15
12816 + *[0-9a-f]*:   ef a0 00 00     mvcr\.w cp0,r0,cr0
12817 + *[0-9a-f]*:   ef af 0f 00     mvcr\.w cp0,pc,cr15
12818 + *[0-9a-f]*:   ef a0 ef 00     mvcr\.w cp7,r0,cr15
12819 + *[0-9a-f]*:   ef af e0 00     mvcr\.w cp7,pc,cr0
12820 + *[0-9a-f]*:   ef a7 88 00     mvcr\.w cp4,r7,cr8
12821 + *[0-9a-f]*:   ef a8 67 00     mvcr\.w cp3,r8,cr7
12822 +
12823 +[0-9a-f]* <mvcr_d>:
12824 + *[0-9a-f]*:   ef ae ee 10     mvcr\.d cp7,lr,cr14
12825 + *[0-9a-f]*:   ef a0 00 10     mvcr\.d cp0,r0,cr0
12826 + *[0-9a-f]*:   ef ae 0e 10     mvcr\.d cp0,lr,cr14
12827 + *[0-9a-f]*:   ef a0 ee 10     mvcr\.d cp7,r0,cr14
12828 + *[0-9a-f]*:   ef ae e0 10     mvcr\.d cp7,lr,cr0
12829 + *[0-9a-f]*:   ef a6 88 10     mvcr\.d cp4,r6,cr8
12830 + *[0-9a-f]*:   ef a8 66 10     mvcr\.d cp3,r8,cr6
12831 +
12832 +[0-9a-f]* <mvrc_w>:
12833 + *[0-9a-f]*:   ef af ef 20     mvrc\.w cp7,cr15,pc
12834 + *[0-9a-f]*:   ef a0 00 20     mvrc\.w cp0,cr0,r0
12835 + *[0-9a-f]*:   ef af 0f 20     mvrc\.w cp0,cr15,pc
12836 + *[0-9a-f]*:   ef a0 ef 20     mvrc\.w cp7,cr15,r0
12837 + *[0-9a-f]*:   ef af e0 20     mvrc\.w cp7,cr0,pc
12838 + *[0-9a-f]*:   ef a7 88 20     mvrc\.w cp4,cr8,r7
12839 + *[0-9a-f]*:   ef a8 67 20     mvrc\.w cp3,cr7,r8
12840 +
12841 +[0-9a-f]* <mvrc_d>:
12842 + *[0-9a-f]*:   ef ae ee 30     mvrc\.d cp7,cr14,lr
12843 + *[0-9a-f]*:   ef a0 00 30     mvrc\.d cp0,cr0,r0
12844 + *[0-9a-f]*:   ef ae 0e 30     mvrc\.d cp0,cr14,lr
12845 + *[0-9a-f]*:   ef a0 ee 30     mvrc\.d cp7,cr14,r0
12846 + *[0-9a-f]*:   ef ae e0 30     mvrc\.d cp7,cr0,lr
12847 + *[0-9a-f]*:   ef a6 88 30     mvrc\.d cp4,cr8,r6
12848 + *[0-9a-f]*:   ef a8 66 30     mvrc\.d cp3,cr6,r8
12849 +
12850 +[0-9a-f]* <bfexts>:
12851 + *[0-9a-f]*:   ff df b3 ff     bfexts pc,pc,0x1f,0x1f
12852 + *[0-9a-f]*:   e1 d0 b0 00     bfexts r0,r0,0x0,0x0
12853 + *[0-9a-f]*:   e1 df b3 ff     bfexts r0,pc,0x1f,0x1f
12854 + *[0-9a-f]*:   ff d0 b3 ff     bfexts pc,r0,0x1f,0x1f
12855 + *[0-9a-f]*:   ff df b0 1f     bfexts pc,pc,0x0,0x1f
12856 + *[0-9a-f]*:   ff df b3 e0     bfexts pc,pc,0x1f,0x0
12857 + *[0-9a-f]*:   ef d8 b1 f0     bfexts r7,r8,0xf,0x10
12858 + *[0-9a-f]*:   f1 d7 b2 0f     bfexts r8,r7,0x10,0xf
12859 +
12860 +[0-9a-f]* <bfextu>:
12861 + *[0-9a-f]*:   ff df c3 ff     bfextu pc,pc,0x1f,0x1f
12862 + *[0-9a-f]*:   e1 d0 c0 00     bfextu r0,r0,0x0,0x0
12863 + *[0-9a-f]*:   e1 df c3 ff     bfextu r0,pc,0x1f,0x1f
12864 + *[0-9a-f]*:   ff d0 c3 ff     bfextu pc,r0,0x1f,0x1f
12865 + *[0-9a-f]*:   ff df c0 1f     bfextu pc,pc,0x0,0x1f
12866 + *[0-9a-f]*:   ff df c3 e0     bfextu pc,pc,0x1f,0x0
12867 + *[0-9a-f]*:   ef d8 c1 f0     bfextu r7,r8,0xf,0x10
12868 + *[0-9a-f]*:   f1 d7 c2 0f     bfextu r8,r7,0x10,0xf
12869 +
12870 +[0-9a-f]* <bfins>:
12871 + *[0-9a-f]*:   ff df d3 ff     bfins pc,pc,0x1f,0x1f
12872 + *[0-9a-f]*:   e1 d0 d0 00     bfins r0,r0,0x0,0x0
12873 + *[0-9a-f]*:   e1 df d3 ff     bfins r0,pc,0x1f,0x1f
12874 + *[0-9a-f]*:   ff d0 d3 ff     bfins pc,r0,0x1f,0x1f
12875 + *[0-9a-f]*:   ff df d0 1f     bfins pc,pc,0x0,0x1f
12876 + *[0-9a-f]*:   ff df d3 e0     bfins pc,pc,0x1f,0x0
12877 + *[0-9a-f]*:   ef d8 d1 f0     bfins r7,r8,0xf,0x10
12878 + *[0-9a-f]*:   f1 d7 d2 0f     bfins r8,r7,0x10,0xf
12879 +
12880 +[0-9a-f]* <rsubc>:
12881 + *[0-9a-f]*:   fb bf 00 00     rsubeq pc,0
12882 + *[0-9a-f]*:   fb bc 0f ff     rsubal r12,-1
12883 + *[0-9a-f]*:   fb b5 08 80     rsubls r5,-128
12884 + *[0-9a-f]*:   fb b4 07 7f     rsubpl r4,127
12885 + *[0-9a-f]*:   fb be 01 01     rsubne lr,1
12886 + *[0-9a-f]*:   fb bc 08 76     rsubls r12,118
12887 + *[0-9a-f]*:   fb be 0d f4     rsubvc lr,-12
12888 + *[0-9a-f]*:   fb b4 06 f3     rsubmi r4,-13
12889 +
12890 +[0-9a-f]* <addc>:
12891 + *[0-9a-f]*:   ff df e0 0f     addeq pc,pc,pc
12892 + *[0-9a-f]*:   f9 dc ef 0c     addal r12,r12,r12
12893 + *[0-9a-f]*:   eb d5 e8 05     addls r5,r5,r5
12894 + *[0-9a-f]*:   e9 d4 e7 04     addpl r4,r4,r4
12895 + *[0-9a-f]*:   fd de e1 0e     addne lr,lr,lr
12896 + *[0-9a-f]*:   e5 d1 e8 0a     addls r10,r2,r1
12897 + *[0-9a-f]*:   f1 db ed 0c     addvc r12,r8,r11
12898 + *[0-9a-f]*:   ef d0 e6 0a     addmi r10,r7,r0
12899 +
12900 +[0-9a-f]* <subc2>:
12901 + *[0-9a-f]*:   ff df e0 1f     subeq pc,pc,pc
12902 + *[0-9a-f]*:   f9 dc ef 1c     subal r12,r12,r12
12903 + *[0-9a-f]*:   eb d5 e8 15     subls r5,r5,r5
12904 + *[0-9a-f]*:   e9 d4 e7 14     subpl r4,r4,r4
12905 + *[0-9a-f]*:   fd de e1 1e     subne lr,lr,lr
12906 + *[0-9a-f]*:   e5 d1 e8 1a     subls r10,r2,r1
12907 + *[0-9a-f]*:   f1 db ed 1c     subvc r12,r8,r11
12908 + *[0-9a-f]*:   ef d0 e6 1a     submi r10,r7,r0
12909 +
12910 +[0-9a-f]* <andc>:
12911 + *[0-9a-f]*:   ff df e0 2f     andeq pc,pc,pc
12912 + *[0-9a-f]*:   f9 dc ef 2c     andal r12,r12,r12
12913 + *[0-9a-f]*:   eb d5 e8 25     andls r5,r5,r5
12914 + *[0-9a-f]*:   e9 d4 e7 24     andpl r4,r4,r4
12915 + *[0-9a-f]*:   fd de e1 2e     andne lr,lr,lr
12916 + *[0-9a-f]*:   e5 d1 e8 2a     andls r10,r2,r1
12917 + *[0-9a-f]*:   f1 db ed 2c     andvc r12,r8,r11
12918 + *[0-9a-f]*:   ef d0 e6 2a     andmi r10,r7,r0
12919 +
12920 +[0-9a-f]* <orc>:
12921 + *[0-9a-f]*:   ff df e0 3f     oreq pc,pc,pc
12922 + *[0-9a-f]*:   f9 dc ef 3c     oral r12,r12,r12
12923 + *[0-9a-f]*:   eb d5 e8 35     orls r5,r5,r5
12924 + *[0-9a-f]*:   e9 d4 e7 34     orpl r4,r4,r4
12925 + *[0-9a-f]*:   fd de e1 3e     orne lr,lr,lr
12926 + *[0-9a-f]*:   e5 d1 e8 3a     orls r10,r2,r1
12927 + *[0-9a-f]*:   f1 db ed 3c     orvc r12,r8,r11
12928 + *[0-9a-f]*:   ef d0 e6 3a     ormi r10,r7,r0
12929 +
12930 +[0-9a-f]* <eorc>:
12931 + *[0-9a-f]*:   ff df e0 4f     eoreq pc,pc,pc
12932 + *[0-9a-f]*:   f9 dc ef 4c     eoral r12,r12,r12
12933 + *[0-9a-f]*:   eb d5 e8 45     eorls r5,r5,r5
12934 + *[0-9a-f]*:   e9 d4 e7 44     eorpl r4,r4,r4
12935 + *[0-9a-f]*:   fd de e1 4e     eorne lr,lr,lr
12936 + *[0-9a-f]*:   e5 d1 e8 4a     eorls r10,r2,r1
12937 + *[0-9a-f]*:   f1 db ed 4c     eorvc r12,r8,r11
12938 + *[0-9a-f]*:   ef d0 e6 4a     eormi r10,r7,r0
12939 +
12940 +[0-9a-f]* <ldcond>:
12941 + *[0-9a-f]*:   ff ff 01 ff     ld.weq  pc,pc[0x7fc]
12942 + *[0-9a-f]*:   f9 fc f3 ff     ld.shal r12,r12[0x3fe]
12943 + *[0-9a-f]*:   eb f5 84 00     ld.shls r5,r5[0x0]
12944 + *[0-9a-f]*:   e9 f4 79 ff     ld.ubpl r4,r4[0x1ff]
12945 + *[0-9a-f]*:   fd fe 16 00     ld.sbne lr,lr[0x0]
12946 + *[0-9a-f]*:   e5 fa 80 00     ld.wls  r10,r2[0x0]
12947 + *[0-9a-f]*:   f1 fc d3 ff     ld.shvc r12,r8[0x3fe]
12948 + *[0-9a-f]*:   ef fa 68 01     ld.ubmi r10,r7[0x1]
12949 +
12950 +[0-9a-f]* <stcond2>:
12951 + *[0-9a-f]*:   ff ff 0b ff     st.weq pc[0x7fc],pc
12952 + *[0-9a-f]*:   f9 fc fd ff     st.hal r12[0x3fe],r12
12953 + *[0-9a-f]*:   eb f5 8c 00     st.hls r5[0x0],r5
12954 + *[0-9a-f]*:   e9 f4 7f ff     st.bpl r4[0x1ff],r4
12955 + *[0-9a-f]*:   fd fe 1e 00     st.bne lr[0x0],lr
12956 + *[0-9a-f]*:   e5 fa 8a 00     st.wls r2[0x0],r10
12957 + *[0-9a-f]*:   f1 fc dd ff     st.hvc r8[0x3fe],r12
12958 + *[0-9a-f]*:   ef fa 6e 01     st.bmi r7[0x1],r10
12959 +
12960 +[0-9a-f]* <movh>:
12961 + *[0-9a-f]*:   fc 1f ff ff     movh pc,0xffff
12962 + *[0-9a-f]*:   fc 10 00 00     movh r0,0x0
12963 + *[0-9a-f]*:   fc 15 00 01     movh r5,0x1
12964 + *[0-9a-f]*:   fc 1c 7f ff     movh r12,0x7fff
12965 +
12966 --- /dev/null
12967 +++ b/gas/testsuite/gas/avr32/allinsn.exp
12968 @@ -0,0 +1,5 @@
12969 +# AVR32 assembler testsuite. -*- Tcl -*-
12970 +
12971 +if [istarget avr32-*-*] {
12972 +    run_dump_test "allinsn"
12973 +}
12974 --- /dev/null
12975 +++ b/gas/testsuite/gas/avr32/allinsn.s
12976 @@ -0,0 +1,3330 @@
12977 + .data
12978 +foodata: .word 42
12979 + .text
12980 +footext:
12981 +       .text
12982 +       .global ld_d5
12983 +ld_d5:
12984 +       ld.d lr,pc[pc<<3]
12985 +       ld.d r0,r0[r0<<0]
12986 +       ld.d r6,r5[r5<<2]
12987 +       ld.d r4,r4[r4<<1]
12988 +       ld.d lr,lr[lr<<1]
12989 +       ld.d r10,r3[sp<<2]
12990 +       ld.d r8,r10[r6<<2]
12991 +       ld.d r2,r7[r9<<0]
12992 +       .text
12993 +       .global ld_w5
12994 +ld_w5:
12995 +       ld.w pc,pc[pc<<0]
12996 +       ld.w r12,r12[r12<<3]
12997 +       ld.w r5,r5[r5<<2]
12998 +       ld.w r4,r4[r4<<1]
12999 +       ld.w lr,lr[lr<<1]
13000 +       ld.w r2,r9[r9<<0]
13001 +       ld.w r11,r2[r6<<0]
13002 +       ld.w r0,r2[sp<<3]
13003 +       .text
13004 +       .global ld_sh5
13005 +ld_sh5:
13006 +       ld.sh pc,pc[pc<<0]
13007 +       ld.sh r12,r12[r12<<3]
13008 +       ld.sh r5,r5[r5<<2]
13009 +       ld.sh r4,r4[r4<<1]
13010 +       ld.sh lr,lr[lr<<1]
13011 +       ld.sh r11,r0[pc<<2]
13012 +       ld.sh r10,sp[r6<<2]
13013 +       ld.sh r12,r2[r2<<0]
13014 +       .text
13015 +       .global ld_uh5
13016 +ld_uh5:
13017 +       ld.uh pc,pc[pc<<0]
13018 +       ld.uh r12,r12[r12<<3]
13019 +       ld.uh r5,r5[r5<<2]
13020 +       ld.uh r4,r4[r4<<1]
13021 +       ld.uh lr,lr[lr<<1]
13022 +       ld.uh r8,pc[lr<<3]
13023 +       ld.uh r6,r1[pc<<1]
13024 +       ld.uh r6,lr[sp<<1]
13025 +       .text
13026 +       .global ld_sb2
13027 +ld_sb2:
13028 +       ld.sb pc,pc[pc<<0]
13029 +       ld.sb r12,r12[r12<<3]
13030 +       ld.sb r5,r5[r5<<2]
13031 +       ld.sb r4,r4[r4<<1]
13032 +       ld.sb lr,lr[lr<<1]
13033 +       ld.sb r9,r1[pc<<3]
13034 +       ld.sb r0,r3[r11<<1]
13035 +       ld.sb r10,r5[r5<<1]
13036 +       .text
13037 +       .global ld_ub5
13038 +ld_ub5:
13039 +       ld.ub pc,pc[pc<<0]
13040 +       ld.ub r12,r12[r12<<3]
13041 +       ld.ub r5,r5[r5<<2]
13042 +       ld.ub r4,r4[r4<<1]
13043 +       ld.ub lr,lr[lr<<1]
13044 +       ld.ub r6,r12[r7<<3]
13045 +       ld.ub r2,r6[r12<<0]
13046 +       ld.ub r0,r7[r11<<1]
13047 +       .text
13048 +       .global st_d5
13049 +st_d5:
13050 +       st.d pc[pc<<0],r14
13051 +       st.d r12[r12<<3],r12
13052 +       st.d r5[r5<<2],r6
13053 +       st.d r4[r4<<1],r4
13054 +       st.d lr[lr<<1],lr
13055 +       st.d r1[r9<<1],r4
13056 +       st.d r10[r2<<1],r4
13057 +       st.d r12[r6<<0],lr
13058 +       .text
13059 +       .global st_w5
13060 +st_w5:
13061 +       st.w pc[pc<<0],pc
13062 +       st.w r12[r12<<3],r12
13063 +       st.w r5[r5<<2],r5
13064 +       st.w r4[r4<<1],r4
13065 +       st.w lr[lr<<1],lr
13066 +       st.w r1[r10<<0],r3
13067 +       st.w r0[r10<<1],r9
13068 +       st.w r4[r5<<3],pc
13069 +       .text
13070 +       .global st_h5
13071 +st_h5:
13072 +       st.h pc[pc<<0],pc
13073 +       st.h r12[r12<<3],r12
13074 +       st.h r5[r5<<2],r5
13075 +       st.h r4[r4<<1],r4
13076 +       st.h lr[lr<<1],lr
13077 +       st.h r2[r9<<0],r11
13078 +       st.h r5[r1<<2],r12
13079 +       st.h pc[r8<<2],r3
13080 +       .text
13081 +       .global st_b5
13082 +st_b5:
13083 +       st.b pc[pc<<0],pc
13084 +       st.b r12[r12<<3],r12
13085 +       st.b r5[r5<<2],r5
13086 +       st.b r4[r4<<1],r4
13087 +       st.b lr[lr<<1],lr
13088 +       st.b r1[r8<<1],r6
13089 +       st.b lr[lr<<3],r1
13090 +       st.b r5[r0<<2],pc
13091 +       .text
13092 +       .global divs
13093 +divs:
13094 +       divs pc,pc,pc
13095 +       divs r12,r12,r12
13096 +       divs r5,r5,r5
13097 +       divs r4,r4,r4
13098 +       divs lr,lr,lr
13099 +       divs r3,pc,pc
13100 +       divs r9,r12,r2
13101 +       divs r7,r4,r1
13102 +       .text
13103 +       .global add1
13104 +add1:
13105 +       add pc,pc
13106 +       add r12,r12
13107 +       add r5,r5
13108 +       add r4,r4
13109 +       add lr,lr
13110 +       add r12,r9
13111 +       add r6,r3
13112 +       add r10,r12
13113 +       .text
13114 +       .global sub1
13115 +sub1:
13116 +       sub pc,pc
13117 +       sub r12,r12
13118 +       sub r5,r5
13119 +       sub r4,r4
13120 +       sub lr,lr
13121 +       sub lr,r6
13122 +       sub r0,sp
13123 +       sub r6,r12
13124 +       .text
13125 +       .global rsub1
13126 +rsub1:
13127 +       rsub pc,pc
13128 +       rsub r12,r12
13129 +       rsub r5,r5
13130 +       rsub r4,r4
13131 +       rsub lr,lr
13132 +       rsub r11,sp
13133 +       rsub r7,r4
13134 +       rsub r9,r1
13135 +       .text
13136 +       .global cp1
13137 +cp1:
13138 +       cp pc,pc
13139 +       cp r12,r12
13140 +       cp r5,r5
13141 +       cp r4,r4
13142 +       cp lr,lr
13143 +       cp r6,r2
13144 +       cp r0,r9
13145 +       cp r3,sp
13146 +       .text
13147 +       .global or1
13148 +or1:
13149 +       or pc,pc
13150 +       or r12,r12
13151 +       or r5,r5
13152 +       or r4,r4
13153 +       or lr,lr
13154 +       or r4,r9
13155 +       or r11,r4
13156 +       or r4,r0
13157 +       .text
13158 +       .global eor1
13159 +eor1:
13160 +       eor pc,pc
13161 +       eor r12,r12
13162 +       eor r5,r5
13163 +       eor r4,r4
13164 +       eor lr,lr
13165 +       eor r12,r11
13166 +       eor r0,r1
13167 +       eor r5,pc
13168 +       .text
13169 +       .global and1
13170 +and1:
13171 +       and pc,pc
13172 +       and r12,r12
13173 +       and r5,r5
13174 +       and r4,r4
13175 +       and lr,lr
13176 +       and r8,r1
13177 +       and r0,sp
13178 +       and r10,r5
13179 +       .text
13180 +       .global tst
13181 +tst:
13182 +       tst pc,pc
13183 +       tst r12,r12
13184 +       tst r5,r5
13185 +       tst r4,r4
13186 +       tst lr,lr
13187 +       tst r0,r12
13188 +       tst r10,r6
13189 +       tst sp,r4
13190 +       .text
13191 +       .global andn
13192 +andn:
13193 +       andn pc,pc
13194 +       andn r12,r12
13195 +       andn r5,r5
13196 +       andn r4,r4
13197 +       andn lr,lr
13198 +       andn r9,r12
13199 +       andn r11,sp
13200 +       andn r12,r5
13201 +       .text
13202 +       .global mov3
13203 +mov3:
13204 +       mov pc,pc
13205 +       mov r12,r12
13206 +       mov r5,r5
13207 +       mov r4,r4
13208 +       mov lr,lr
13209 +       mov r5,r9
13210 +       mov r11,r11
13211 +       mov r2,lr
13212 +       .text
13213 +       .global st_w1
13214 +st_w1:
13215 +       st.w pc++,pc
13216 +       st.w r12++,r12
13217 +       st.w r5++,r5
13218 +       st.w r4++,r4
13219 +       st.w lr++,lr
13220 +       st.w r1++,r11
13221 +       st.w sp++,r0
13222 +       st.w sp++,r1
13223 +       .text
13224 +       .global st_h1
13225 +st_h1:
13226 +       st.h pc++,pc
13227 +       st.h r12++,r12
13228 +       st.h r5++,r5
13229 +       st.h r4++,r4
13230 +       st.h lr++,lr
13231 +       st.h r12++,sp
13232 +       st.h r7++,lr
13233 +       st.h r7++,r4
13234 +       .text
13235 +       .global st_b1
13236 +st_b1:
13237 +       st.b pc++,pc
13238 +       st.b r12++,r12
13239 +       st.b r5++,r5
13240 +       st.b r4++,r4
13241 +       st.b lr++,lr
13242 +       st.b r9++,sp
13243 +       st.b r1++,sp
13244 +       st.b r0++,r4
13245 +       .text
13246 +       .global st_w2
13247 +st_w2:
13248 +       st.w --pc,pc
13249 +       st.w --r12,r12
13250 +       st.w --r5,r5
13251 +       st.w --r4,r4
13252 +       st.w --lr,lr
13253 +       st.w --r1,r7
13254 +       st.w --r3,r9
13255 +       st.w --r5,r5
13256 +       .text
13257 +       .global st_h2
13258 +st_h2:
13259 +       st.h --pc,pc
13260 +       st.h --r12,r12
13261 +       st.h --r5,r5
13262 +       st.h --r4,r4
13263 +       st.h --lr,lr
13264 +       st.h --r5,r7
13265 +       st.h --r8,r8
13266 +       st.h --r7,r2
13267 +       .text
13268 +       .global st_b2
13269 +st_b2:
13270 +       st.b --pc,pc
13271 +       st.b --r12,r12
13272 +       st.b --r5,r5
13273 +       st.b --r4,r4
13274 +       st.b --lr,lr
13275 +       st.b --sp,sp
13276 +       st.b --sp,r11
13277 +       st.b --r4,r5
13278 +       .text
13279 +       .global ld_w1
13280 +ld_w1:
13281 +       ld.w pc,pc++
13282 +       ld.w r12,r12++
13283 +       ld.w r5,r5++
13284 +       ld.w r4,r4++
13285 +       ld.w lr,lr++
13286 +       ld.w r3,r7++
13287 +       ld.w r3,lr++
13288 +       ld.w r12,r5++
13289 +       .text
13290 +       .global ld_sh1
13291 +ld_sh1:
13292 +       ld.sh pc,pc++
13293 +       ld.sh r12,r12++
13294 +       ld.sh r5,r5++
13295 +       ld.sh r4,r4++
13296 +       ld.sh lr,lr++
13297 +       ld.sh r11,r2++
13298 +       ld.sh r2,r8++
13299 +       ld.sh r7,r6++
13300 +       .text
13301 +       .global ld_uh1
13302 +ld_uh1:
13303 +       ld.uh pc,pc++
13304 +       ld.uh r12,r12++
13305 +       ld.uh r5,r5++
13306 +       ld.uh r4,r4++
13307 +       ld.uh lr,lr++
13308 +       ld.uh r6,r7++
13309 +       ld.uh r10,r11++
13310 +       ld.uh lr,r4++
13311 +       .text
13312 +       .global ld_ub1
13313 +ld_ub1:
13314 +       ld.ub pc,pc++
13315 +       ld.ub r12,r12++
13316 +       ld.ub r5,r5++
13317 +       ld.ub r4,r4++
13318 +       ld.ub lr,lr++
13319 +       ld.ub r8,lr++
13320 +       ld.ub r12,r12++
13321 +       ld.ub r11,r10++
13322 +       .text
13323 +       .global ld_w2
13324 +ld_w2:
13325 +       ld.w pc,--pc
13326 +       ld.w r12,--r12
13327 +       ld.w r5,--r5
13328 +       ld.w r4,--r4
13329 +       ld.w lr,--lr
13330 +       ld.w r10,--lr
13331 +       ld.w r12,--r9
13332 +       ld.w r6,--r5
13333 +       .text
13334 +       .global ld_sh2
13335 +ld_sh2:
13336 +       ld.sh pc,--pc
13337 +       ld.sh r12,--r12
13338 +       ld.sh r5,--r5
13339 +       ld.sh r4,--r4
13340 +       ld.sh lr,--lr
13341 +       ld.sh pc,--r10
13342 +       ld.sh r6,--r3
13343 +       ld.sh r4,--r6
13344 +       .text
13345 +       .global ld_uh2
13346 +ld_uh2:
13347 +       ld.uh pc,--pc
13348 +       ld.uh r12,--r12
13349 +       ld.uh r5,--r5
13350 +       ld.uh r4,--r4
13351 +       ld.uh lr,--lr
13352 +       ld.uh r3,--r2
13353 +       ld.uh r1,--r0
13354 +       ld.uh r2,--r9
13355 +       .text
13356 +       .global ld_ub2
13357 +ld_ub2:
13358 +       ld.ub pc,--pc
13359 +       ld.ub r12,--r12
13360 +       ld.ub r5,--r5
13361 +       ld.ub r4,--r4
13362 +       ld.ub lr,--lr
13363 +       ld.ub r1,--r1
13364 +       ld.ub r0,--r6
13365 +       ld.ub r2,--r7
13366 +       .text
13367 +       .global ld_ub3
13368 +ld_ub3:
13369 +       ld.ub pc,pc[0]
13370 +       ld.ub r12,r12[7]
13371 +       ld.ub r5,r5[4]
13372 +       ld.ub r4,r4[3]
13373 +       ld.ub lr,lr[1]
13374 +       ld.ub r6,r9[6]
13375 +       ld.ub r2,lr[4]
13376 +       ld.ub r1,r8[0]
13377 +       .text
13378 +       .global sub3_sp
13379 +sub3_sp:
13380 +       sub sp,0
13381 +       sub sp,-4
13382 +       sub sp,-512
13383 +       sub sp,508
13384 +       sub sp,4
13385 +       sub sp,44
13386 +       sub sp,8
13387 +       sub sp,348
13388 +       .text
13389 +       .global sub3
13390 +sub3:
13391 +       sub pc,0
13392 +       sub r12,-1
13393 +       sub r5,-128
13394 +       sub r4,127
13395 +       sub lr,1
13396 +       sub r6,-41
13397 +       sub r4,37
13398 +       sub r12,56
13399 +       .text
13400 +       .global mov1
13401 +mov1:
13402 +       mov pc,0
13403 +       mov r12,-1
13404 +       mov r5,-128
13405 +       mov r4,127
13406 +       mov lr,1
13407 +       mov pc,14
13408 +       mov r6,-100
13409 +       mov lr,-122
13410 +       .text
13411 +       .global lddsp
13412 +lddsp:
13413 +       lddsp pc,sp[0]
13414 +       lddsp r12,sp[508]
13415 +       lddsp r5,sp[256]
13416 +       lddsp r4,sp[252]
13417 +       lddsp lr,sp[4]
13418 +       lddsp lr,sp[256]
13419 +       lddsp r12,sp[20]
13420 +       lddsp r9,sp[472]
13421 +       .text
13422 +       .global lddpc
13423 +lddpc:
13424 +       lddpc pc,pc[0]
13425 +       lddpc r0,pc[508]
13426 +       lddpc r8,pc[256]
13427 +       lddpc r7,pc[252]
13428 +       lddpc lr,pc[4]
13429 +       lddpc sp,pc[472]
13430 +       lddpc r6,pc[120]
13431 +       lddpc r11,pc[28]
13432 +       .text
13433 +       .global stdsp
13434 +stdsp:
13435 +       stdsp sp[0],pc
13436 +       stdsp sp[508],r12
13437 +       stdsp sp[256],r5
13438 +       stdsp sp[252],r4
13439 +       stdsp sp[4],lr
13440 +       stdsp sp[304],pc
13441 +       stdsp sp[256],r0
13442 +       stdsp sp[336],r5
13443 +       .text
13444 +       .global cp2
13445 +cp2:
13446 +       cp pc,0
13447 +       cp r12,-1
13448 +       cp r5,-32
13449 +       cp r4,31
13450 +       cp lr,1
13451 +       cp r8,3
13452 +       cp lr,16
13453 +       cp r7,-26
13454 +       .text
13455 +       .global acr
13456 +acr:
13457 +       acr pc
13458 +       acr r12
13459 +       acr r5
13460 +       acr r4
13461 +       acr lr
13462 +       acr r2
13463 +       acr r12
13464 +       acr pc
13465 +       .text
13466 +       .global scr
13467 +scr:
13468 +       scr pc
13469 +       scr r12
13470 +       scr r5
13471 +       scr r4
13472 +       scr lr
13473 +       scr pc
13474 +       scr r6
13475 +       scr r1
13476 +       .text
13477 +       .global cpc0
13478 +cpc0:
13479 +       cpc pc
13480 +       cpc r12
13481 +       cpc r5
13482 +       cpc r4
13483 +       cpc lr
13484 +       cpc pc
13485 +       cpc r4
13486 +       cpc r9
13487 +       .text
13488 +       .global neg
13489 +neg:
13490 +       neg pc
13491 +       neg r12
13492 +       neg r5
13493 +       neg r4
13494 +       neg lr
13495 +       neg r7
13496 +       neg r1
13497 +       neg r9
13498 +       .text
13499 +       .global abs
13500 +abs:
13501 +       abs pc
13502 +       abs r12
13503 +       abs r5
13504 +       abs r4
13505 +       abs lr
13506 +       abs r6
13507 +       abs r6
13508 +       abs r4
13509 +       .text
13510 +       .global castu_b
13511 +castu_b:
13512 +       castu.b pc
13513 +       castu.b r12
13514 +       castu.b r5
13515 +       castu.b r4
13516 +       castu.b lr
13517 +       castu.b r7
13518 +       castu.b sp
13519 +       castu.b r9
13520 +       .text
13521 +       .global casts_b
13522 +casts_b:
13523 +       casts.b pc
13524 +       casts.b r12
13525 +       casts.b r5
13526 +       casts.b r4
13527 +       casts.b lr
13528 +       casts.b r11
13529 +       casts.b r1
13530 +       casts.b r10
13531 +       .text
13532 +       .global castu_h
13533 +castu_h:
13534 +       castu.h pc
13535 +       castu.h r12
13536 +       castu.h r5
13537 +       castu.h r4
13538 +       castu.h lr
13539 +       castu.h r10
13540 +       castu.h r11
13541 +       castu.h r1
13542 +       .text
13543 +       .global casts_h
13544 +casts_h:
13545 +       casts.h pc
13546 +       casts.h r12
13547 +       casts.h r5
13548 +       casts.h r4
13549 +       casts.h lr
13550 +       casts.h r0
13551 +       casts.h r5
13552 +       casts.h r9
13553 +       .text
13554 +       .global brev
13555 +brev:
13556 +       brev pc
13557 +       brev r12
13558 +       brev r5
13559 +       brev r4
13560 +       brev lr
13561 +       brev r5
13562 +       brev r10
13563 +       brev r8
13564 +       .text
13565 +       .global swap_h
13566 +swap_h:
13567 +       swap.h pc
13568 +       swap.h r12
13569 +       swap.h r5
13570 +       swap.h r4
13571 +       swap.h lr
13572 +       swap.h r7
13573 +       swap.h r0
13574 +       swap.h r8
13575 +       .text
13576 +       .global swap_b
13577 +swap_b:
13578 +       swap.b pc
13579 +       swap.b r12
13580 +       swap.b r5
13581 +       swap.b r4
13582 +       swap.b lr
13583 +       swap.b r10
13584 +       swap.b r12
13585 +       swap.b r1
13586 +       .text
13587 +       .global swap_bh
13588 +swap_bh:
13589 +       swap.bh pc
13590 +       swap.bh r12
13591 +       swap.bh r5
13592 +       swap.bh r4
13593 +       swap.bh lr
13594 +       swap.bh r9
13595 +       swap.bh r4
13596 +       swap.bh r1
13597 +       .text
13598 +       .global One_s_compliment
13599 +One_s_compliment:
13600 +       com pc
13601 +       com r12
13602 +       com r5
13603 +       com r4
13604 +       com lr
13605 +       com r2
13606 +       com r2
13607 +       com r7
13608 +       .text
13609 +       .global tnbz
13610 +tnbz:
13611 +       tnbz pc
13612 +       tnbz r12
13613 +       tnbz r5
13614 +       tnbz r4
13615 +       tnbz lr
13616 +       tnbz r8
13617 +       tnbz r12
13618 +       tnbz pc
13619 +       .text
13620 +       .global rol
13621 +rol:
13622 +       rol pc
13623 +       rol r12
13624 +       rol r5
13625 +       rol r4
13626 +       rol lr
13627 +       rol r10
13628 +       rol r9
13629 +       rol r5
13630 +       .text
13631 +       .global ror
13632 +ror:
13633 +       ror pc
13634 +       ror r12
13635 +       ror r5
13636 +       ror r4
13637 +       ror lr
13638 +       ror r8
13639 +       ror r4
13640 +       ror r7
13641 +       .text
13642 +       .global icall
13643 +icall:
13644 +       icall pc
13645 +       icall r12
13646 +       icall r5
13647 +       icall r4
13648 +       icall lr
13649 +       icall r3
13650 +       icall r1
13651 +       icall r3
13652 +       .text
13653 +       .global mustr
13654 +mustr:
13655 +       mustr pc
13656 +       mustr r12
13657 +       mustr r5
13658 +       mustr r4
13659 +       mustr lr
13660 +       mustr r1
13661 +       mustr r4
13662 +       mustr r12
13663 +       .text
13664 +       .global musfr
13665 +musfr:
13666 +       musfr pc
13667 +       musfr r12
13668 +       musfr r5
13669 +       musfr r4
13670 +       musfr lr
13671 +       musfr r11
13672 +       musfr r12
13673 +       musfr r2
13674 +       .text
13675 +       .global ret_cond
13676 +ret_cond:
13677 +       reteq pc
13678 +       retal r12
13679 +       retls r5
13680 +       retpl r4
13681 +       retne lr
13682 +       retgt r0
13683 +       retgt r12
13684 +       retge r10
13685 +       .text
13686 +       .global sr_cond
13687 +sr_cond:
13688 +       sreq pc
13689 +       sral r12
13690 +       srls r5
13691 +       srpl r4
13692 +       srne lr
13693 +       srlt r0
13694 +       sral sp
13695 +       srge r9
13696 +       .text
13697 +       .global ld_w3
13698 +ld_w3:
13699 +       ld.w pc,pc[0]
13700 +       ld.w r12,r12[124]
13701 +       ld.w r5,r5[64]
13702 +       ld.w r4,r4[60]
13703 +       ld.w lr,lr[4]
13704 +       ld.w sp,r2[52]
13705 +       ld.w r9,r1[8]
13706 +       ld.w r5,sp[60]
13707 +       .text
13708 +       .global ld_sh3
13709 +ld_sh3:
13710 +       ld.sh pc,pc[0]
13711 +       ld.sh r12,r12[14]
13712 +       ld.sh r5,r5[8]
13713 +       ld.sh r4,r4[6]
13714 +       ld.sh lr,lr[2]
13715 +       ld.sh r4,r2[8]
13716 +       ld.sh sp,lr[10]
13717 +       ld.sh r2,r11[2]
13718 +       .text
13719 +       .global ld_uh3
13720 +ld_uh3:
13721 +       ld.uh pc,pc[0]
13722 +       ld.uh r12,r12[14]
13723 +       ld.uh r5,r5[8]
13724 +       ld.uh r4,r4[6]
13725 +       ld.uh lr,lr[2]
13726 +       ld.uh r10,r0[10]
13727 +       ld.uh r8,r11[8]
13728 +       ld.uh r10,r2[12]
13729 +       .text
13730 +       .global st_w3
13731 +st_w3:
13732 +       st.w pc[0],pc
13733 +       st.w r12[60],r12
13734 +       st.w r5[32],r5
13735 +       st.w r4[28],r4
13736 +       st.w lr[4],lr
13737 +       st.w r7[44],r11
13738 +       st.w r2[24],r6
13739 +       st.w r4[12],r9
13740 +       .text
13741 +       .global st_h3
13742 +st_h3:
13743 +       st.h pc[0],pc
13744 +       st.h r12[14],r12
13745 +       st.h r5[8],r5
13746 +       st.h r4[6],r4
13747 +       st.h lr[2],lr
13748 +       st.h lr[10],r12
13749 +       st.h r6[4],r0
13750 +       st.h r5[12],sp
13751 +       .text
13752 +       .global st_b3
13753 +st_b3:
13754 +       st.b pc[0],pc
13755 +       st.b r12[7],r12
13756 +       st.b r5[4],r5
13757 +       st.b r4[3],r4
13758 +       st.b lr[1],lr
13759 +       st.b r12[6],r9
13760 +       st.b r2[3],lr
13761 +       st.b r1[3],r11
13762 +       .text
13763 +       .global ldd
13764 +ldd:
13765 +       ld.d r0,pc
13766 +       ld.d r14,r12
13767 +       ld.d r8,r5
13768 +       ld.d r6,r4
13769 +       ld.d r2,lr
13770 +       ld.d r14,r7
13771 +       ld.d r4,r4
13772 +       ld.d r14,pc
13773 +       .text
13774 +       .global ldd_postinc
13775 +ldd_postinc:
13776 +       ld.d r0,pc++
13777 +       ld.d r14,r12++
13778 +       ld.d r8,r5++
13779 +       ld.d r6,r4++
13780 +       ld.d r2,lr++
13781 +       ld.d r14,r5++
13782 +       ld.d r12,r11++
13783 +       ld.d r2,r12++
13784 +       .text
13785 +       .global ldd_predec
13786 +ldd_predec:
13787 +       ld.d r0,--pc
13788 +       ld.d r14,--r12
13789 +       ld.d r8,--r5
13790 +       ld.d r6,--r4
13791 +       ld.d r2,--lr
13792 +       ld.d r8,--r0
13793 +       ld.d r10,--pc
13794 +       ld.d r2,--r4
13795 +       .text
13796 +       .global std
13797 +std:
13798 +       st.d pc,r0
13799 +       st.d r12,r14
13800 +       st.d r5,r8
13801 +       st.d r4,r6
13802 +       st.d lr,r2
13803 +       st.d r0,r12
13804 +       st.d sp,r4
13805 +       st.d r12,r12
13806 +       .text
13807 +       .global std_postinc
13808 +std_postinc:
13809 +       st.d pc++,r0
13810 +       st.d r12++,r14
13811 +       st.d r5++,r8
13812 +       st.d r4++,r6
13813 +       st.d lr++,r2
13814 +       st.d sp++,r6
13815 +       st.d r10++,r6
13816 +       st.d r7++,r2
13817 +       .text
13818 +       .global std_predec
13819 +std_predec:
13820 +       st.d --pc,r0
13821 +       st.d --r12,r14
13822 +       st.d --r5,r8
13823 +       st.d --r4,r6
13824 +       st.d --lr,r2
13825 +       st.d --r3,r6
13826 +       st.d --lr,r2
13827 +       st.d --r0,r4
13828 +       .text
13829 +       .global mul
13830 +mul:
13831 +       mul pc,pc
13832 +       mul r12,r12
13833 +       mul r5,r5
13834 +       mul r4,r4
13835 +       mul lr,lr
13836 +       mul r10,lr
13837 +       mul r0,r8
13838 +       mul r8,r5
13839 +       .text
13840 +       .global asr_imm5
13841 +asr_imm5:
13842 +       asr pc,0
13843 +       asr r12,31
13844 +       asr r5,16
13845 +       asr r4,15
13846 +       asr lr,1
13847 +       asr r6,23
13848 +       asr r6,18
13849 +       asr r5,8
13850 +       .text
13851 +       .global lsl_imm5
13852 +lsl_imm5:
13853 +       lsl pc,0
13854 +       lsl r12,31
13855 +       lsl r5,16
13856 +       lsl r4,15
13857 +       lsl lr,1
13858 +       lsl r12,13
13859 +       lsl r6,16
13860 +       lsl r1,25
13861 +       .text
13862 +       .global lsr_imm5
13863 +lsr_imm5:
13864 +       lsr pc,0
13865 +       lsr r12,31
13866 +       lsr r5,16
13867 +       lsr r4,15
13868 +       lsr lr,1
13869 +       lsr r0,1
13870 +       lsr r8,10
13871 +       lsr r7,26
13872 +       .text
13873 +       .global sbr
13874 +sbr:
13875 +       sbr pc,0
13876 +       sbr r12,31
13877 +       sbr r5,16
13878 +       sbr r4,15
13879 +       sbr lr,1
13880 +       sbr r8,31
13881 +       sbr r6,22
13882 +       sbr r1,23
13883 +       .text
13884 +       .global cbr
13885 +cbr:
13886 +       cbr pc,0
13887 +       cbr r12,31
13888 +       cbr r5,16
13889 +       cbr r4,15
13890 +       cbr lr,1
13891 +       cbr r12,10
13892 +       cbr r7,22
13893 +       cbr r8,9
13894 +       .text
13895 +       .global brc1
13896 +brc1:
13897 +       breq 0
13898 +       brpl -2
13899 +       brge -256
13900 +       brcs 254
13901 +       brne 2
13902 +       brcs 230
13903 +       breq -18
13904 +       breq 12
13905 +       .text
13906 +       .global rjmp
13907 +rjmp:
13908 +       rjmp 0
13909 +       rjmp -2
13910 +       rjmp -1024
13911 +       rjmp 1022
13912 +       rjmp 2
13913 +       rjmp -962
13914 +       rjmp 14
13915 +       rjmp -516
13916 +       .text
13917 +       .global rcall1
13918 +rcall1:
13919 +       rcall 0
13920 +       rcall -2
13921 +       rcall -1024
13922 +       rcall 1022
13923 +       rcall 2
13924 +       rcall 216
13925 +       rcall -530
13926 +       rcall -972
13927 +       .text
13928 +       .global acall
13929 +acall:
13930 +       acall 0
13931 +       acall 1020
13932 +       acall 512
13933 +       acall 508
13934 +       acall 4
13935 +       acall 356
13936 +       acall 304
13937 +       acall 172
13938 +       .text
13939 +       .global scall
13940 +scall:
13941 +       scall
13942 +       scall
13943 +       scall
13944 +       scall
13945 +       scall
13946 +       scall
13947 +       scall
13948 +       scall
13949 +       .text
13950 +       .global popm
13951 +popm:
13952 +       /* popm with no argument fails currently */
13953 +       popm pc
13954 +       popm r0-r11,pc,r12=-1
13955 +       popm lr
13956 +       popm r0-r11,pc,r12=1
13957 +       popm r0-r3
13958 +       popm r4-r10,pc
13959 +       popm r0-r3,r11,pc,r12=0
13960 +       popm r0-r7,r10-r12,lr
13961 +       .text
13962 +       .global pushm
13963 +pushm:
13964 +       pushm pc
13965 +       pushm r0-r12,lr,pc
13966 +       pushm pc
13967 +       pushm r0-r12,lr
13968 +       pushm r0-r3
13969 +       pushm r8-r10,lr,pc
13970 +       pushm r0-r3,r10
13971 +       pushm r8-r9,r12
13972 +       .text
13973 +       .global popm_n
13974 +popm_n:
13975 +       popm pc
13976 +       popm r0-r11,pc,r12=-1
13977 +       popm lr
13978 +       popm r0-r11,pc,r12=1
13979 +       popm r0-r3
13980 +       popm r4-r10,pc
13981 +       popm r0-r3,r11,pc,r12=0
13982 +       popm r0-r7,r10-r12,lr
13983 +       .text
13984 +       .global pushm_n
13985 +pushm_n:
13986 +       pushm pc
13987 +       pushm r0-r12,lr,pc
13988 +       pushm pc
13989 +       pushm r0-r12,lr
13990 +       pushm r0-r3
13991 +       pushm r8-r10,lr,pc
13992 +       pushm r0-r3,r10
13993 +       pushm r8-r9,r12
13994 +       .text
13995 +       .global csrfcz
13996 +csrfcz:
13997 +       csrfcz 0
13998 +       csrfcz 31
13999 +       csrfcz 16
14000 +       csrfcz 15
14001 +       csrfcz 1
14002 +       csrfcz 5
14003 +       csrfcz 13
14004 +       csrfcz 23
14005 +       .text
14006 +       .global ssrf
14007 +ssrf:
14008 +       ssrf 0
14009 +       ssrf 31
14010 +       ssrf 16
14011 +       ssrf 15
14012 +       ssrf 1
14013 +       ssrf 29
14014 +       ssrf 13
14015 +       ssrf 13
14016 +       .text
14017 +       .global csrf
14018 +csrf:
14019 +       csrf 0
14020 +       csrf 31
14021 +       csrf 16
14022 +       csrf 15
14023 +       csrf 1
14024 +       csrf 10
14025 +       csrf 15
14026 +       csrf 11
14027 +       .text
14028 +       .global rete
14029 +rete:
14030 +       rete
14031 +       .text
14032 +       .global rets
14033 +rets:
14034 +       rets
14035 +       .text
14036 +       .global retd
14037 +retd:
14038 +       retd
14039 +       .text
14040 +       .global retj
14041 +retj:
14042 +       retj
14043 +       .text
14044 +       .global tlbr
14045 +tlbr:
14046 +       tlbr
14047 +       .text
14048 +       .global tlbs
14049 +tlbs:
14050 +       tlbs
14051 +       .text
14052 +       .global tlbw
14053 +tlbw:
14054 +       tlbw
14055 +       .text
14056 +       .global breakpoint
14057 +breakpoint:
14058 +       breakpoint
14059 +       .text
14060 +       .global incjosp
14061 +incjosp:
14062 +       incjosp 1
14063 +       incjosp 2
14064 +       incjosp 3
14065 +       incjosp 4
14066 +       incjosp -4
14067 +       incjosp -3
14068 +       incjosp -2
14069 +       incjosp -1
14070 +       .text
14071 +       .global nop
14072 +nop:
14073 +       nop
14074 +       .text
14075 +       .global popjc
14076 +popjc:
14077 +       popjc
14078 +       .text
14079 +       .global pushjc
14080 +pushjc:
14081 +       pushjc
14082 +       .text
14083 +       .global add2
14084 +add2:
14085 +       add pc,pc,pc<<0
14086 +       add r12,r12,r12<<3
14087 +       add r5,r5,r5<<2
14088 +       add r4,r4,r4<<1
14089 +       add lr,lr,lr<<1
14090 +       add r0,r12,r0<<1
14091 +       add r9,r12,r4<<0
14092 +       add r12,r12,r7<<2
14093 +       .text
14094 +       .global sub2
14095 +sub2:
14096 +       sub pc,pc,pc<<0
14097 +       sub r12,r12,r12<<3
14098 +       sub r5,r5,r5<<2
14099 +       sub r4,r4,r4<<1
14100 +       sub lr,lr,lr<<1
14101 +       sub sp,r3,r4<<0
14102 +       sub r3,r7,r3<<0
14103 +       sub sp,r10,sp<<1
14104 +       .text
14105 +       .global divu
14106 +divu:
14107 +       divu pc,pc,pc
14108 +       divu r12,r12,r12
14109 +       divu r5,r5,r5
14110 +       divu r4,r4,r4
14111 +       divu lr,lr,lr
14112 +       divu sp,r4,pc
14113 +       divu r5,r5,sp
14114 +       divu r10,sp,r0
14115 +       .text
14116 +       .global addhh_w
14117 +addhh_w:
14118 +       addhh.w pc,pc:b,pc:b
14119 +       addhh.w r12,r12:t,r12:t
14120 +       addhh.w r5,r5:t,r5:t
14121 +       addhh.w r4,r4:b,r4:b
14122 +       addhh.w lr,lr:t,lr:t
14123 +       addhh.w r0,r0:b,r3:b
14124 +       addhh.w lr,r12:t,r7:b
14125 +       addhh.w r3,r10:t,r2:b
14126 +       .text
14127 +       .global subhh_w
14128 +subhh_w:
14129 +       subhh.w pc,pc:b,pc:b
14130 +       subhh.w r12,r12:t,r12:t
14131 +       subhh.w r5,r5:t,r5:t
14132 +       subhh.w r4,r4:b,r4:b
14133 +       subhh.w lr,lr:t,lr:t
14134 +       subhh.w r10,r1:t,r7:b
14135 +       subhh.w pc,r10:t,lr:t
14136 +       subhh.w r3,r0:t,r12:b
14137 +       .text
14138 +       .global adc
14139 +adc:
14140 +       adc pc,pc,pc
14141 +       adc r12,r12,r12
14142 +       adc r5,r5,r5
14143 +       adc r4,r4,r4
14144 +       adc lr,lr,lr
14145 +       adc r4,r0,r7
14146 +       adc sp,r4,r3
14147 +       adc r2,r12,r0
14148 +       .text
14149 +       .global sbc
14150 +sbc:
14151 +       sbc pc,pc,pc
14152 +       sbc r12,r12,r12
14153 +       sbc r5,r5,r5
14154 +       sbc r4,r4,r4
14155 +       sbc lr,lr,lr
14156 +       sbc r6,r7,r9
14157 +       sbc r0,r8,r5
14158 +       sbc r1,r0,r4
14159 +       .text
14160 +       .global mul_2
14161 +mul_2:
14162 +       mul pc,pc,pc
14163 +       mul r12,r12,r12
14164 +       mul r5,r5,r5
14165 +       mul r4,r4,r4
14166 +       mul lr,lr,lr
14167 +       mul pc,r0,r0
14168 +       mul r8,pc,lr
14169 +       mul r4,r12,pc
14170 +       .text
14171 +       .global mac
14172 +mac:
14173 +       mac pc,pc,pc
14174 +       mac r12,r12,r12
14175 +       mac r5,r5,r5
14176 +       mac r4,r4,r4
14177 +       mac lr,lr,lr
14178 +       mac r10,r4,r0
14179 +       mac r7,lr,r0
14180 +       mac r2,r9,r12
14181 +       .text
14182 +       .global mulsd
14183 +mulsd:
14184 +       muls.d pc,pc,pc
14185 +       muls.d r12,r12,r12
14186 +       muls.d r5,r5,r5
14187 +       muls.d r4,r4,r4
14188 +       muls.d lr,lr,lr
14189 +       muls.d r2,r8,lr
14190 +       muls.d r4,r0,r11
14191 +       muls.d r5,lr,r6
14192 +       .text
14193 +       .global macsd
14194 +macsd:
14195 +       macs.d r0,pc,pc
14196 +       macs.d r14,r12,r12
14197 +       macs.d r8,r5,r5
14198 +       macs.d r6,r4,r4
14199 +       macs.d r2,lr,lr
14200 +       macs.d r8,r1,r9
14201 +       macs.d r14,r8,r8
14202 +       macs.d r4,r3,r12
14203 +       .text
14204 +       .global mulud
14205 +mulud:
14206 +       mulu.d r0,pc,pc
14207 +       mulu.d r14,r12,r12
14208 +       mulu.d r8,r5,r5
14209 +       mulu.d r6,r4,r4
14210 +       mulu.d r2,lr,lr
14211 +       mulu.d r6,r5,r0
14212 +       mulu.d r4,r6,r1
14213 +       mulu.d r8,r8,r2
14214 +       .text
14215 +       .global macud
14216 +macud:
14217 +       macu.d r0,pc,pc
14218 +       macu.d r14,r12,r12
14219 +       macu.d r8,r5,r5
14220 +       macu.d r6,r4,r4
14221 +       macu.d r2,lr,lr
14222 +       macu.d r6,sp,r11
14223 +       macu.d r2,r4,r8
14224 +       macu.d r6,r10,r9
14225 +       .text
14226 +       .global asr_1
14227 +asr_1:
14228 +       asr pc,pc,pc
14229 +       asr r12,r12,r12
14230 +       asr r5,r5,r5
14231 +       asr r4,r4,r4
14232 +       asr lr,lr,lr
14233 +       asr pc,r6,pc
14234 +       asr r0,r6,r12
14235 +       asr r4,sp,r0
14236 +       .text
14237 +       .global lsl_1
14238 +lsl_1:
14239 +       lsl pc,pc,pc
14240 +       lsl r12,r12,r12
14241 +       lsl r5,r5,r5
14242 +       lsl r4,r4,r4
14243 +       lsl lr,lr,lr
14244 +       lsl lr,r5,lr
14245 +       lsl r5,pc,r3
14246 +       lsl r1,pc,r9
14247 +       .text
14248 +       .global lsr_1
14249 +lsr_1:
14250 +       lsr pc,pc,pc
14251 +       lsr r12,r12,r12
14252 +       lsr r5,r5,r5
14253 +       lsr r4,r4,r4
14254 +       lsr lr,lr,lr
14255 +       lsr r2,r4,r1
14256 +       lsr r5,r1,r6
14257 +       lsr sp,r6,r7
14258 +       .text
14259 +       .global xchg
14260 +xchg:
14261 +       xchg pc,pc,pc
14262 +       xchg r12,r12,r12
14263 +       xchg r5,r5,r5
14264 +       xchg r4,r4,r4
14265 +       xchg lr,lr,lr
14266 +       xchg lr,r4,sp
14267 +       xchg r1,r5,r12
14268 +       xchg lr,r12,r0
14269 +       .text
14270 +       .global max
14271 +max:
14272 +       max pc,pc,pc
14273 +       max r12,r12,r12
14274 +       max r5,r5,r5
14275 +       max r4,r4,r4
14276 +       max lr,lr,lr
14277 +       max lr,r2,sp
14278 +       max r4,r10,r9
14279 +       max lr,r9,lr
14280 +       .text
14281 +       .global min
14282 +min:
14283 +       min pc,pc,pc
14284 +       min r12,r12,r12
14285 +       min r5,r5,r5
14286 +       min r4,r4,r4
14287 +       min lr,lr,lr
14288 +       min r9,r7,r8
14289 +       min sp,r5,r5
14290 +       min r4,r1,r4
14291 +       .text
14292 +       .global addabs
14293 +addabs:
14294 +       addabs pc,pc,pc
14295 +       addabs r12,r12,r12
14296 +       addabs r5,r5,r5
14297 +       addabs r4,r4,r4
14298 +       addabs lr,lr,lr
14299 +       addabs r7,r10,r0
14300 +       addabs r9,r9,r7
14301 +       addabs r2,r8,r12
14302 +       .text
14303 +       .global mulnhh_w
14304 +mulnhh_w:
14305 +       mulnhh.w pc,pc:b,pc:b
14306 +       mulnhh.w r12,r12:t,r12:t
14307 +       mulnhh.w r5,r5:t,r5:t
14308 +       mulnhh.w r4,r4:b,r4:b
14309 +       mulnhh.w lr,lr:t,lr:t
14310 +       mulnhh.w r11,sp:t,r9:b
14311 +       mulnhh.w sp,r4:b,lr:t
14312 +       mulnhh.w r12,r2:t,r11:b
14313 +       .text
14314 +       .global mulnwh_d
14315 +mulnwh_d:
14316 +       mulnwh.d r0,pc,pc:b
14317 +       mulnwh.d r14,r12,r12:t
14318 +       mulnwh.d r8,r5,r5:t
14319 +       mulnwh.d r6,r4,r4:b
14320 +       mulnwh.d r2,lr,lr:t
14321 +       mulnwh.d r14,r3,r2:t
14322 +       mulnwh.d r4,r5,r9:b
14323 +       mulnwh.d r12,r4,r4:t
14324 +       .text
14325 +       .global machh_w
14326 +machh_w:
14327 +       machh.w pc,pc:b,pc:b
14328 +       machh.w r12,r12:t,r12:t
14329 +       machh.w r5,r5:t,r5:t
14330 +       machh.w r4,r4:b,r4:b
14331 +       machh.w lr,lr:t,lr:t
14332 +       machh.w lr,r5:b,r1:t
14333 +       machh.w r9,r6:b,r7:b
14334 +       machh.w r5,lr:t,r12:b
14335 +       .text
14336 +       .global machh_d
14337 +machh_d:
14338 +       machh.d r0,pc:b,pc:b
14339 +       machh.d r14,r12:t,r12:t
14340 +       machh.d r8,r5:t,r5:t
14341 +       machh.d r6,r4:b,r4:b
14342 +       machh.d r2,lr:t,lr:t
14343 +       machh.d r10,r0:b,r8:b
14344 +       machh.d r14,r4:b,r5:t
14345 +       machh.d r8,r0:b,r4:t
14346 +       .text
14347 +       .global macsathh_w
14348 +macsathh_w:
14349 +       macsathh.w pc,pc:b,pc:b
14350 +       macsathh.w r12,r12:t,r12:t
14351 +       macsathh.w r5,r5:t,r5:t
14352 +       macsathh.w r4,r4:b,r4:b
14353 +       macsathh.w lr,lr:t,lr:t
14354 +       macsathh.w r7,r7:t,pc:t
14355 +       macsathh.w r4,r2:t,r4:b
14356 +       macsathh.w r4,r8:t,r3:t
14357 +       .text
14358 +       .global mulhh_w
14359 +mulhh_w:
14360 +       mulhh.w pc,pc:b,pc:b
14361 +       mulhh.w r12,r12:t,r12:t
14362 +       mulhh.w r5,r5:t,r5:t
14363 +       mulhh.w r4,r4:b,r4:b
14364 +       mulhh.w lr,lr:t,lr:t
14365 +       mulhh.w r7,r4:t,r9:b
14366 +       mulhh.w pc,r3:t,r7:t
14367 +       mulhh.w pc,r4:b,r9:t
14368 +       .text
14369 +       .global mulsathh_h
14370 +mulsathh_h:
14371 +       mulsathh.h pc,pc:b,pc:b
14372 +       mulsathh.h r12,r12:t,r12:t
14373 +       mulsathh.h r5,r5:t,r5:t
14374 +       mulsathh.h r4,r4:b,r4:b
14375 +       mulsathh.h lr,lr:t,lr:t
14376 +       mulsathh.h r3,r1:b,sp:b
14377 +       mulsathh.h r11,lr:t,r11:b
14378 +       mulsathh.h r8,r8:b,r11:t
14379 +       .text
14380 +       .global mulsathh_w
14381 +mulsathh_w:
14382 +       mulsathh.w pc,pc:b,pc:b
14383 +       mulsathh.w r12,r12:t,r12:t
14384 +       mulsathh.w r5,r5:t,r5:t
14385 +       mulsathh.w r4,r4:b,r4:b
14386 +       mulsathh.w lr,lr:t,lr:t
14387 +       mulsathh.w lr,r11:t,r6:b
14388 +       mulsathh.w r6,r6:b,r7:t
14389 +       mulsathh.w r10,r2:b,r3:b
14390 +       .text
14391 +       .global mulsatrndhh_h
14392 +mulsatrndhh_h:
14393 +       mulsatrndhh.h pc,pc:b,pc:b
14394 +       mulsatrndhh.h r12,r12:t,r12:t
14395 +       mulsatrndhh.h r5,r5:t,r5:t
14396 +       mulsatrndhh.h r4,r4:b,r4:b
14397 +       mulsatrndhh.h lr,lr:t,lr:t
14398 +       mulsatrndhh.h r11,r6:b,r9:b
14399 +       mulsatrndhh.h r11,r3:b,r8:t
14400 +       mulsatrndhh.h r5,sp:t,r7:t
14401 +       .text
14402 +       .global mulsatrndwh_w
14403 +mulsatrndwh_w:
14404 +       mulsatrndwh.w pc,pc,pc:b
14405 +       mulsatrndwh.w r12,r12,r12:t
14406 +       mulsatrndwh.w r5,r5,r5:t
14407 +       mulsatrndwh.w r4,r4,r4:b
14408 +       mulsatrndwh.w lr,lr,lr:t
14409 +       mulsatrndwh.w r5,r12,r0:b
14410 +       mulsatrndwh.w r7,r10,pc:b
14411 +       mulsatrndwh.w r10,r8,r5:t
14412 +       .text
14413 +       .global macwh_d
14414 +macwh_d:
14415 +       macwh.d r0,pc,pc:b
14416 +       macwh.d r14,r12,r12:t
14417 +       macwh.d r8,r5,r5:t
14418 +       macwh.d r6,r4,r4:b
14419 +       macwh.d r2,lr,lr:t
14420 +       macwh.d r4,r10,r12:t
14421 +       macwh.d r4,r7,sp:b
14422 +       macwh.d r14,r9,r11:b
14423 +       .text
14424 +       .global mulwh_d
14425 +mulwh_d:
14426 +       mulwh.d r0,pc,pc:b
14427 +       mulwh.d r14,r12,r12:t
14428 +       mulwh.d r8,r5,r5:t
14429 +       mulwh.d r6,r4,r4:b
14430 +       mulwh.d r2,lr,lr:t
14431 +       mulwh.d r12,r5,r1:b
14432 +       mulwh.d r0,r1,r3:t
14433 +       mulwh.d r0,r9,r2:b
14434 +       .text
14435 +       .global mulsatwh_w
14436 +mulsatwh_w:
14437 +       mulsatwh.w pc,pc,pc:b
14438 +       mulsatwh.w r12,r12,r12:t
14439 +       mulsatwh.w r5,r5,r5:t
14440 +       mulsatwh.w r4,r4,r4:b
14441 +       mulsatwh.w lr,lr,lr:t
14442 +       mulsatwh.w r11,pc,r10:t
14443 +       mulsatwh.w sp,r12,r9:t
14444 +       mulsatwh.w r0,r3,r2:t
14445 +       .text
14446 +       .global ldw7
14447 +ldw7:
14448 +       ld.w pc,pc[pc:b<<2]
14449 +       ld.w r12,r12[r12:t<<2]
14450 +       ld.w r5,r5[r5:u<<2]
14451 +       ld.w r4,r4[r4:l<<2]
14452 +       ld.w lr,lr[lr:l<<2]
14453 +       ld.w r9,r10[r6:l<<2]
14454 +       ld.w r2,r10[r10:b<<2]
14455 +       ld.w r11,r5[pc:b<<2]
14456 +       .text
14457 +       .global satadd_w
14458 +satadd_w:
14459 +       satadd.w pc,pc,pc
14460 +       satadd.w r12,r12,r12
14461 +       satadd.w r5,r5,r5
14462 +       satadd.w r4,r4,r4
14463 +       satadd.w lr,lr,lr
14464 +       satadd.w r4,r8,r11
14465 +       satadd.w r3,r12,r6
14466 +       satadd.w r3,lr,r9
14467 +       .text
14468 +       .global satsub_w1
14469 +satsub_w1:
14470 +       satsub.w pc,pc,pc
14471 +       satsub.w r12,r12,r12
14472 +       satsub.w r5,r5,r5
14473 +       satsub.w r4,r4,r4
14474 +       satsub.w lr,lr,lr
14475 +       satsub.w r8,sp,r0
14476 +       satsub.w r9,r8,r4
14477 +       satsub.w pc,lr,r2
14478 +       .text
14479 +       .global satadd_h
14480 +satadd_h:
14481 +       satadd.h pc,pc,pc
14482 +       satadd.h r12,r12,r12
14483 +       satadd.h r5,r5,r5
14484 +       satadd.h r4,r4,r4
14485 +       satadd.h lr,lr,lr
14486 +       satadd.h r7,r3,r9
14487 +       satadd.h r1,r0,r2
14488 +       satadd.h r1,r4,lr
14489 +       .text
14490 +       .global satsub_h
14491 +satsub_h:
14492 +       satsub.h pc,pc,pc
14493 +       satsub.h r12,r12,r12
14494 +       satsub.h r5,r5,r5
14495 +       satsub.h r4,r4,r4
14496 +       satsub.h lr,lr,lr
14497 +       satsub.h lr,lr,r3
14498 +       satsub.h r11,r6,r5
14499 +       satsub.h r3,sp,r0
14500 +       .text
14501 +       .global mul3
14502 +mul3:
14503 +       mul pc,pc,0
14504 +       mul r12,r12,-1
14505 +       mul r5,r5,-128
14506 +       mul r4,r4,127
14507 +       mul lr,lr,1
14508 +       mul r12,r2,-7
14509 +       mul r1,pc,95
14510 +       mul r4,r6,19
14511 +       .text
14512 +       .global rsub2
14513 +rsub2:
14514 +       rsub pc,pc,0
14515 +       rsub r12,r12,-1
14516 +       rsub r5,r5,-128
14517 +       rsub r4,r4,127
14518 +       rsub lr,lr,1
14519 +       rsub r9,lr,96
14520 +       rsub r11,r1,56
14521 +       rsub r0,r7,-87
14522 +       .text
14523 +       .global clz
14524 +clz:
14525 +       clz pc,pc
14526 +       clz r12,r12
14527 +       clz r5,r5
14528 +       clz r4,r4
14529 +       clz lr,lr
14530 +       clz r2,r3
14531 +       clz r5,r11
14532 +       clz pc,r3
14533 +       .text
14534 +       .global cpc1
14535 +cpc1:
14536 +       cpc pc,pc
14537 +       cpc r12,r12
14538 +       cpc r5,r5
14539 +       cpc r4,r4
14540 +       cpc lr,lr
14541 +       cpc pc,r4
14542 +       cpc r5,r9
14543 +       cpc r6,r7
14544 +       .text
14545 +       .global asr3
14546 +asr3:
14547 +       asr pc,pc,0
14548 +       asr r12,r12,31
14549 +       asr r5,r5,16
14550 +       asr r4,r4,15
14551 +       asr lr,lr,1
14552 +       asr r4,r11,19
14553 +       asr sp,pc,26
14554 +       asr r11,sp,8
14555 +       .text
14556 +       .global lsl3
14557 +lsl3:
14558 +       lsl pc,pc,0
14559 +       lsl r12,r12,31
14560 +       lsl r5,r5,16
14561 +       lsl r4,r4,15
14562 +       lsl lr,lr,1
14563 +       lsl r8,r10,17
14564 +       lsl r2,lr,3
14565 +       lsl lr,r11,14
14566 +       .text
14567 +       .global lsr3
14568 +lsr3:
14569 +       lsr pc,pc,0
14570 +       lsr r12,r12,31
14571 +       lsr r5,r5,16
14572 +       lsr r4,r4,15
14573 +       lsr lr,lr,1
14574 +       lsr r4,r3,31
14575 +       lsr pc,r9,14
14576 +       lsr r3,r0,6
14577 +/*     .text
14578 +       .global extract_b
14579 +extract_b:
14580 +       extract.b pc,pc:b
14581 +       extract.b r12,r12:t
14582 +       extract.b r5,r5:u
14583 +       extract.b r4,r4:l
14584 +       extract.b lr,lr:l
14585 +       extract.b r2,r5:l
14586 +       extract.b r12,r3:l
14587 +       extract.b sp,r3:l
14588 +       .text
14589 +       .global insert_b
14590 +insert_b:
14591 +       insert.b pc:b,pc
14592 +       insert.b r12:t,r12
14593 +       insert.b r5:u,r5
14594 +       insert.b r4:l,r4
14595 +       insert.b lr:l,lr
14596 +       insert.b r12:u,r3
14597 +       insert.b r10:l,lr
14598 +       insert.b r11:l,r12
14599 +       .text
14600 +       .global extract_h
14601 +extract_h:
14602 +       extract.h pc,pc:b
14603 +       extract.h r12,r12:t
14604 +       extract.h r5,r5:t
14605 +       extract.h r4,r4:b
14606 +       extract.h lr,lr:t
14607 +       extract.h r11,lr:b
14608 +       extract.h r10,r0:b
14609 +       extract.h r11,r12:b
14610 +       .text
14611 +       .global insert_h
14612 +insert_h:
14613 +       insert.h pc:b,pc
14614 +       insert.h r12:t,r12
14615 +       insert.h r5:t,r5
14616 +       insert.h r4:b,r4
14617 +       insert.h lr:t,lr
14618 +       insert.h r12:t,r11
14619 +       insert.h r7:b,r6
14620 +       insert.h r1:t,r11 */
14621 +       .text
14622 +       .global movc1
14623 +movc1:
14624 +       moveq pc,pc
14625 +       moval r12,r12
14626 +       movls r5,r5
14627 +       movpl r4,r4
14628 +       movne lr,lr
14629 +       movne pc,r11
14630 +       movmi r10,r2
14631 +       movls r8,r12
14632 +       .text
14633 +       .global padd_h
14634 +padd_h:
14635 +       padd.h pc,pc,pc
14636 +       padd.h r12,r12,r12
14637 +       padd.h r5,r5,r5
14638 +       padd.h r4,r4,r4
14639 +       padd.h lr,lr,lr
14640 +       padd.h r8,r2,r7
14641 +       padd.h r0,r0,r3
14642 +       padd.h sp,r11,r6
14643 +       .text
14644 +       .global psub_h
14645 +psub_h:
14646 +       psub.h pc,pc,pc
14647 +       psub.h r12,r12,r12
14648 +       psub.h r5,r5,r5
14649 +       psub.h r4,r4,r4
14650 +       psub.h lr,lr,lr
14651 +       psub.h lr,r6,r8
14652 +       psub.h r0,r1,sp
14653 +       psub.h pc,pc,sp
14654 +       .text
14655 +       .global paddx_h
14656 +paddx_h:
14657 +       paddx.h pc,pc,pc
14658 +       paddx.h r12,r12,r12
14659 +       paddx.h r5,r5,r5
14660 +       paddx.h r4,r4,r4
14661 +       paddx.h lr,lr,lr
14662 +       paddx.h pc,pc,r1
14663 +       paddx.h r10,r4,r5
14664 +       paddx.h r5,pc,r2
14665 +       .text
14666 +       .global psubx_h
14667 +psubx_h:
14668 +       psubx.h pc,pc,pc
14669 +       psubx.h r12,r12,r12
14670 +       psubx.h r5,r5,r5
14671 +       psubx.h r4,r4,r4
14672 +       psubx.h lr,lr,lr
14673 +       psubx.h r5,r12,r5
14674 +       psubx.h r3,r8,r3
14675 +       psubx.h r5,r2,r3
14676 +       .text
14677 +       .global padds_sh
14678 +padds_sh:
14679 +       padds.sh pc,pc,pc
14680 +       padds.sh r12,r12,r12
14681 +       padds.sh r5,r5,r5
14682 +       padds.sh r4,r4,r4
14683 +       padds.sh lr,lr,lr
14684 +       padds.sh r9,lr,r2
14685 +       padds.sh r6,r8,r1
14686 +       padds.sh r6,r4,r10
14687 +       .text
14688 +       .global psubs_sh
14689 +psubs_sh:
14690 +       psubs.sh pc,pc,pc
14691 +       psubs.sh r12,r12,r12
14692 +       psubs.sh r5,r5,r5
14693 +       psubs.sh r4,r4,r4
14694 +       psubs.sh lr,lr,lr
14695 +       psubs.sh r6,lr,r11
14696 +       psubs.sh r2,r12,r4
14697 +       psubs.sh r0,r9,r0
14698 +       .text
14699 +       .global paddxs_sh
14700 +paddxs_sh:
14701 +       paddxs.sh pc,pc,pc
14702 +       paddxs.sh r12,r12,r12
14703 +       paddxs.sh r5,r5,r5
14704 +       paddxs.sh r4,r4,r4
14705 +       paddxs.sh lr,lr,lr
14706 +       paddxs.sh r0,r3,r9
14707 +       paddxs.sh pc,r10,r11
14708 +       paddxs.sh pc,r10,pc
14709 +       .text
14710 +       .global psubxs_sh
14711 +psubxs_sh:
14712 +       psubxs.sh pc,pc,pc
14713 +       psubxs.sh r12,r12,r12
14714 +       psubxs.sh r5,r5,r5
14715 +       psubxs.sh r4,r4,r4
14716 +       psubxs.sh lr,lr,lr
14717 +       psubxs.sh r7,r4,r4
14718 +       psubxs.sh r7,r8,r3
14719 +       psubxs.sh pc,r6,r5
14720 +       .text
14721 +       .global padds_uh
14722 +padds_uh:
14723 +       padds.uh pc,pc,pc
14724 +       padds.uh r12,r12,r12
14725 +       padds.uh r5,r5,r5
14726 +       padds.uh r4,r4,r4
14727 +       padds.uh lr,lr,lr
14728 +       padds.uh r12,r11,r7
14729 +       padds.uh r7,r8,lr
14730 +       padds.uh r6,r9,r7
14731 +       .text
14732 +       .global psubs_uh
14733 +psubs_uh:
14734 +       psubs.uh pc,pc,pc
14735 +       psubs.uh r12,r12,r12
14736 +       psubs.uh r5,r5,r5
14737 +       psubs.uh r4,r4,r4
14738 +       psubs.uh lr,lr,lr
14739 +       psubs.uh lr,r10,r6
14740 +       psubs.uh sp,r2,pc
14741 +       psubs.uh r2,r9,r2
14742 +       .text
14743 +       .global paddxs_uh
14744 +paddxs_uh:
14745 +       paddxs.uh pc,pc,pc
14746 +       paddxs.uh r12,r12,r12
14747 +       paddxs.uh r5,r5,r5
14748 +       paddxs.uh r4,r4,r4
14749 +       paddxs.uh lr,lr,lr
14750 +       paddxs.uh r7,r9,r5
14751 +       paddxs.uh r9,r1,r4
14752 +       paddxs.uh r5,r2,r3
14753 +       .text
14754 +       .global psubxs_uh
14755 +psubxs_uh:
14756 +       psubxs.uh pc,pc,pc
14757 +       psubxs.uh r12,r12,r12
14758 +       psubxs.uh r5,r5,r5
14759 +       psubxs.uh r4,r4,r4
14760 +       psubxs.uh lr,lr,lr
14761 +       psubxs.uh sp,r5,sp
14762 +       psubxs.uh sp,r6,r6
14763 +       psubxs.uh r3,r11,r8
14764 +       .text
14765 +       .global paddh_sh
14766 +paddh_sh:
14767 +       paddh.sh pc,pc,pc
14768 +       paddh.sh r12,r12,r12
14769 +       paddh.sh r5,r5,r5
14770 +       paddh.sh r4,r4,r4
14771 +       paddh.sh lr,lr,lr
14772 +       paddh.sh r12,sp,r3
14773 +       paddh.sh pc,r5,r3
14774 +       paddh.sh r8,r8,sp
14775 +       .text
14776 +       .global psubh_sh
14777 +psubh_sh:
14778 +       psubh.sh pc,pc,pc
14779 +       psubh.sh r12,r12,r12
14780 +       psubh.sh r5,r5,r5
14781 +       psubh.sh r4,r4,r4
14782 +       psubh.sh lr,lr,lr
14783 +       psubh.sh r1,r5,r8
14784 +       psubh.sh r7,r3,r6
14785 +       psubh.sh r4,r3,r3
14786 +       .text
14787 +       .global paddxh_sh
14788 +paddxh_sh:
14789 +       paddxh.sh pc,pc,pc
14790 +       paddxh.sh r12,r12,r12
14791 +       paddxh.sh r5,r5,r5
14792 +       paddxh.sh r4,r4,r4
14793 +       paddxh.sh lr,lr,lr
14794 +       paddxh.sh r6,r0,r4
14795 +       paddxh.sh r9,r8,r9
14796 +       paddxh.sh r3,r0,sp
14797 +       .text
14798 +       .global psubxh_sh
14799 +psubxh_sh:
14800 +       psubxh.sh pc,pc,pc
14801 +       psubxh.sh r12,r12,r12
14802 +       psubxh.sh r5,r5,r5
14803 +       psubxh.sh r4,r4,r4
14804 +       psubxh.sh lr,lr,lr
14805 +       psubxh.sh r4,pc,r12
14806 +       psubxh.sh r8,r4,r6
14807 +       psubxh.sh r12,r9,r4
14808 +       .text
14809 +       .global paddsub_h
14810 +paddsub_h:
14811 +       paddsub.h pc,pc:b,pc:b
14812 +       paddsub.h r12,r12:t,r12:t
14813 +       paddsub.h r5,r5:t,r5:t
14814 +       paddsub.h r4,r4:b,r4:b
14815 +       paddsub.h lr,lr:t,lr:t
14816 +       paddsub.h r5,r2:t,lr:b
14817 +       paddsub.h r7,r1:b,r8:b
14818 +       paddsub.h r6,r10:t,r5:t
14819 +       .text
14820 +       .global psubadd_h
14821 +psubadd_h:
14822 +       psubadd.h pc,pc:b,pc:b
14823 +       psubadd.h r12,r12:t,r12:t
14824 +       psubadd.h r5,r5:t,r5:t
14825 +       psubadd.h r4,r4:b,r4:b
14826 +       psubadd.h lr,lr:t,lr:t
14827 +       psubadd.h r9,r11:t,r8:t
14828 +       psubadd.h r10,r7:t,lr:t
14829 +       psubadd.h r6,pc:t,pc:b
14830 +       .text
14831 +       .global paddsubs_sh
14832 +paddsubs_sh:
14833 +       paddsubs.sh pc,pc:b,pc:b
14834 +       paddsubs.sh r12,r12:t,r12:t
14835 +       paddsubs.sh r5,r5:t,r5:t
14836 +       paddsubs.sh r4,r4:b,r4:b
14837 +       paddsubs.sh lr,lr:t,lr:t
14838 +       paddsubs.sh r0,lr:t,r0:b
14839 +       paddsubs.sh r9,r2:t,r4:t
14840 +       paddsubs.sh r12,r9:t,sp:t
14841 +       .text
14842 +       .global psubadds_sh
14843 +psubadds_sh:
14844 +       psubadds.sh pc,pc:b,pc:b
14845 +       psubadds.sh r12,r12:t,r12:t
14846 +       psubadds.sh r5,r5:t,r5:t
14847 +       psubadds.sh r4,r4:b,r4:b
14848 +       psubadds.sh lr,lr:t,lr:t
14849 +       psubadds.sh pc,lr:b,r1:t
14850 +       psubadds.sh r11,r3:b,r12:b
14851 +       psubadds.sh r10,r2:t,r8:t
14852 +       .text
14853 +       .global paddsubs_uh
14854 +paddsubs_uh:
14855 +       paddsubs.uh pc,pc:b,pc:b
14856 +       paddsubs.uh r12,r12:t,r12:t
14857 +       paddsubs.uh r5,r5:t,r5:t
14858 +       paddsubs.uh r4,r4:b,r4:b
14859 +       paddsubs.uh lr,lr:t,lr:t
14860 +       paddsubs.uh r9,r2:b,r3:b
14861 +       paddsubs.uh sp,sp:b,r7:t
14862 +       paddsubs.uh lr,r0:b,r10:t
14863 +       .text
14864 +       .global psubadds_uh
14865 +psubadds_uh:
14866 +       psubadds.uh pc,pc:b,pc:b
14867 +       psubadds.uh r12,r12:t,r12:t
14868 +       psubadds.uh r5,r5:t,r5:t
14869 +       psubadds.uh r4,r4:b,r4:b
14870 +       psubadds.uh lr,lr:t,lr:t
14871 +       psubadds.uh r12,r9:t,pc:t
14872 +       psubadds.uh r8,r6:b,r8:b
14873 +       psubadds.uh r8,r8:b,r4:b
14874 +       .text
14875 +       .global paddsubh_sh
14876 +paddsubh_sh:
14877 +       paddsubh.sh pc,pc:b,pc:b
14878 +       paddsubh.sh r12,r12:t,r12:t
14879 +       paddsubh.sh r5,r5:t,r5:t
14880 +       paddsubh.sh r4,r4:b,r4:b
14881 +       paddsubh.sh lr,lr:t,lr:t
14882 +       paddsubh.sh r8,r9:t,r9:b
14883 +       paddsubh.sh r0,sp:t,r1:t
14884 +       paddsubh.sh r3,r1:b,r0:t
14885 +       .text
14886 +       .global psubaddh_sh
14887 +psubaddh_sh:
14888 +       psubaddh.sh pc,pc:b,pc:b
14889 +       psubaddh.sh r12,r12:t,r12:t
14890 +       psubaddh.sh r5,r5:t,r5:t
14891 +       psubaddh.sh r4,r4:b,r4:b
14892 +       psubaddh.sh lr,lr:t,lr:t
14893 +       psubaddh.sh r7,r3:t,r10:b
14894 +       psubaddh.sh r7,r2:t,r1:t
14895 +       psubaddh.sh r11,r3:b,r6:b
14896 +       .text
14897 +       .global padd_b
14898 +padd_b:
14899 +       padd.b pc,pc,pc
14900 +       padd.b r12,r12,r12
14901 +       padd.b r5,r5,r5
14902 +       padd.b r4,r4,r4
14903 +       padd.b lr,lr,lr
14904 +       padd.b r2,r6,pc
14905 +       padd.b r8,r9,r12
14906 +       padd.b r5,r12,r3
14907 +       .text
14908 +       .global psub_b
14909 +psub_b:
14910 +       psub.b pc,pc,pc
14911 +       psub.b r12,r12,r12
14912 +       psub.b r5,r5,r5
14913 +       psub.b r4,r4,r4
14914 +       psub.b lr,lr,lr
14915 +       psub.b r0,r12,pc
14916 +       psub.b r7,sp,r10
14917 +       psub.b r5,sp,r12
14918 +       .text
14919 +       .global padds_sb
14920 +padds_sb:
14921 +       padds.sb pc,pc,pc
14922 +       padds.sb r12,r12,r12
14923 +       padds.sb r5,r5,r5
14924 +       padds.sb r4,r4,r4
14925 +       padds.sb lr,lr,lr
14926 +       padds.sb sp,r11,r4
14927 +       padds.sb r11,r10,r11
14928 +       padds.sb r5,r12,r6
14929 +       .text
14930 +       .global psubs_sb
14931 +psubs_sb:
14932 +       psubs.sb pc,pc,pc
14933 +       psubs.sb r12,r12,r12
14934 +       psubs.sb r5,r5,r5
14935 +       psubs.sb r4,r4,r4
14936 +       psubs.sb lr,lr,lr
14937 +       psubs.sb r7,r6,r8
14938 +       psubs.sb r12,r10,r9
14939 +       psubs.sb pc,r11,r0
14940 +       .text
14941 +       .global padds_ub
14942 +padds_ub:
14943 +       padds.ub pc,pc,pc
14944 +       padds.ub r12,r12,r12
14945 +       padds.ub r5,r5,r5
14946 +       padds.ub r4,r4,r4
14947 +       padds.ub lr,lr,lr
14948 +       padds.ub r3,r2,r11
14949 +       padds.ub r10,r8,r1
14950 +       padds.ub r11,r8,r10
14951 +       .text
14952 +       .global psubs_ub
14953 +psubs_ub:
14954 +       psubs.ub pc,pc,pc
14955 +       psubs.ub r12,r12,r12
14956 +       psubs.ub r5,r5,r5
14957 +       psubs.ub r4,r4,r4
14958 +       psubs.ub lr,lr,lr
14959 +       psubs.ub r0,r2,r7
14960 +       psubs.ub lr,r5,r3
14961 +       psubs.ub r6,r7,r9
14962 +       .text
14963 +       .global paddh_ub
14964 +paddh_ub:
14965 +       paddh.ub pc,pc,pc
14966 +       paddh.ub r12,r12,r12
14967 +       paddh.ub r5,r5,r5
14968 +       paddh.ub r4,r4,r4
14969 +       paddh.ub lr,lr,lr
14970 +       paddh.ub lr,r1,r0
14971 +       paddh.ub r2,r7,r7
14972 +       paddh.ub r2,r1,r2
14973 +       .text
14974 +       .global psubh_ub
14975 +psubh_ub:
14976 +       psubh.ub pc,pc,pc
14977 +       psubh.ub r12,r12,r12
14978 +       psubh.ub r5,r5,r5
14979 +       psubh.ub r4,r4,r4
14980 +       psubh.ub lr,lr,lr
14981 +       psubh.ub r0,r1,r6
14982 +       psubh.ub r4,lr,r10
14983 +       psubh.ub r9,r8,r1
14984 +       .text
14985 +       .global pmax_ub
14986 +pmax_ub:
14987 +       pmax.ub pc,pc,pc
14988 +       pmax.ub r12,r12,r12
14989 +       pmax.ub r5,r5,r5
14990 +       pmax.ub r4,r4,r4
14991 +       pmax.ub lr,lr,lr
14992 +       pmax.ub pc,r2,r11
14993 +       pmax.ub r12,r1,r1
14994 +       pmax.ub r5,r2,r0
14995 +       .text
14996 +       .global pmax_sh
14997 +pmax_sh:
14998 +       pmax.sh pc,pc,pc
14999 +       pmax.sh r12,r12,r12
15000 +       pmax.sh r5,r5,r5
15001 +       pmax.sh r4,r4,r4
15002 +       pmax.sh lr,lr,lr
15003 +       pmax.sh lr,r6,r12
15004 +       pmax.sh r2,pc,r5
15005 +       pmax.sh pc,r2,r7
15006 +       .text
15007 +       .global pmin_ub
15008 +pmin_ub:
15009 +       pmin.ub pc,pc,pc
15010 +       pmin.ub r12,r12,r12
15011 +       pmin.ub r5,r5,r5
15012 +       pmin.ub r4,r4,r4
15013 +       pmin.ub lr,lr,lr
15014 +       pmin.ub r8,r1,r5
15015 +       pmin.ub r1,r8,r3
15016 +       pmin.ub r0,r2,r7
15017 +       .text
15018 +       .global pmin_sh
15019 +pmin_sh:
15020 +       pmin.sh pc,pc,pc
15021 +       pmin.sh r12,r12,r12
15022 +       pmin.sh r5,r5,r5
15023 +       pmin.sh r4,r4,r4
15024 +       pmin.sh lr,lr,lr
15025 +       pmin.sh r8,r4,r10
15026 +       pmin.sh lr,r10,r12
15027 +       pmin.sh r2,r6,r2
15028 +       .text
15029 +       .global pavg_ub
15030 +pavg_ub:
15031 +       pavg.ub pc,pc,pc
15032 +       pavg.ub r12,r12,r12
15033 +       pavg.ub r5,r5,r5
15034 +       pavg.ub r4,r4,r4
15035 +       pavg.ub lr,lr,lr
15036 +       pavg.ub r0,r1,r6
15037 +       pavg.ub r8,r3,r6
15038 +       pavg.ub pc,r12,r10
15039 +       .text
15040 +       .global pavg_sh
15041 +pavg_sh:
15042 +       pavg.sh pc,pc,pc
15043 +       pavg.sh r12,r12,r12
15044 +       pavg.sh r5,r5,r5
15045 +       pavg.sh r4,r4,r4
15046 +       pavg.sh lr,lr,lr
15047 +       pavg.sh r9,pc,sp
15048 +       pavg.sh pc,sp,r3
15049 +       pavg.sh r6,r1,r9
15050 +       .text
15051 +       .global pabs_sb
15052 +pabs_sb:
15053 +       pabs.sb pc,pc
15054 +       pabs.sb r12,r12
15055 +       pabs.sb r5,r5
15056 +       pabs.sb r4,r4
15057 +       pabs.sb lr,lr
15058 +       pabs.sb r11,r6
15059 +       pabs.sb lr,r9
15060 +       pabs.sb sp,r7
15061 +       .text
15062 +       .global pabs_sh
15063 +pabs_sh:
15064 +       pabs.sh pc,pc
15065 +       pabs.sh r12,r12
15066 +       pabs.sh r5,r5
15067 +       pabs.sh r4,r4
15068 +       pabs.sh lr,lr
15069 +       pabs.sh pc,r3
15070 +       pabs.sh r5,r7
15071 +       pabs.sh r4,r0
15072 +       .text
15073 +       .global psad
15074 +psad:
15075 +       psad pc,pc,pc
15076 +       psad r12,r12,r12
15077 +       psad r5,r5,r5
15078 +       psad r4,r4,r4
15079 +       psad lr,lr,lr
15080 +       psad r9,r11,r11
15081 +       psad lr,r4,sp
15082 +       psad lr,r4,r5
15083 +       .text
15084 +       .global pasr_b
15085 +pasr_b:
15086 +       pasr.b pc,pc,0
15087 +       pasr.b r12,r12,7
15088 +       pasr.b r5,r5,4
15089 +       pasr.b r4,r4,3
15090 +       pasr.b lr,lr,1
15091 +       pasr.b pc,r7,1
15092 +       pasr.b sp,lr,6
15093 +       pasr.b sp,r3,2
15094 +       .text
15095 +       .global plsl_b
15096 +plsl_b:
15097 +       plsl.b pc,pc,0
15098 +       plsl.b r12,r12,7
15099 +       plsl.b r5,r5,4
15100 +       plsl.b r4,r4,3
15101 +       plsl.b lr,lr,1
15102 +       plsl.b r2,r11,4
15103 +       plsl.b r8,r5,7
15104 +       plsl.b pc,r0,2
15105 +       .text
15106 +       .global plsr_b
15107 +plsr_b:
15108 +       plsr.b pc,pc,0
15109 +       plsr.b r12,r12,7
15110 +       plsr.b r5,r5,4
15111 +       plsr.b r4,r4,3
15112 +       plsr.b lr,lr,1
15113 +       plsr.b r12,r1,2
15114 +       plsr.b r6,pc,7
15115 +       plsr.b r12,r11,2
15116 +       .text
15117 +       .global pasr_h
15118 +pasr_h:
15119 +       pasr.h pc,pc,0
15120 +       pasr.h r12,r12,15
15121 +       pasr.h r5,r5,8
15122 +       pasr.h r4,r4,7
15123 +       pasr.h lr,lr,1
15124 +       pasr.h r0,r11,10
15125 +       pasr.h r4,r6,8
15126 +       pasr.h r6,r2,4
15127 +       .text
15128 +       .global plsl_h
15129 +plsl_h:
15130 +       plsl.h pc,pc,0
15131 +       plsl.h r12,r12,15
15132 +       plsl.h r5,r5,8
15133 +       plsl.h r4,r4,7
15134 +       plsl.h lr,lr,1
15135 +       plsl.h r5,r10,9
15136 +       plsl.h sp,lr,8
15137 +       plsl.h r0,lr,7
15138 +       .text
15139 +       .global plsr_h
15140 +plsr_h:
15141 +       plsr.h pc,pc,0
15142 +       plsr.h r12,r12,15
15143 +       plsr.h r5,r5,8
15144 +       plsr.h r4,r4,7
15145 +       plsr.h lr,lr,1
15146 +       plsr.h r11,r0,15
15147 +       plsr.h lr,r3,3
15148 +       plsr.h r8,lr,10
15149 +       .text
15150 +       .global packw_sh
15151 +packw_sh:
15152 +       packw.sh pc,pc,pc
15153 +       packw.sh r12,r12,r12
15154 +       packw.sh r5,r5,r5
15155 +       packw.sh r4,r4,r4
15156 +       packw.sh lr,lr,lr
15157 +       packw.sh sp,r11,r10
15158 +       packw.sh r8,r2,r12
15159 +       packw.sh r8,r1,r5
15160 +       .text
15161 +       .global punpckub_h
15162 +punpckub_h:
15163 +       punpckub.h pc,pc:b
15164 +       punpckub.h r12,r12:t
15165 +       punpckub.h r5,r5:t
15166 +       punpckub.h r4,r4:b
15167 +       punpckub.h lr,lr:t
15168 +       punpckub.h r6,r1:t
15169 +       punpckub.h lr,r5:b
15170 +       punpckub.h lr,r2:t
15171 +       .text
15172 +       .global punpcksb_h
15173 +punpcksb_h:
15174 +       punpcksb.h pc,pc:b
15175 +       punpcksb.h r12,r12:t
15176 +       punpcksb.h r5,r5:t
15177 +       punpcksb.h r4,r4:b
15178 +       punpcksb.h lr,lr:t
15179 +       punpcksb.h r4,r7:t
15180 +       punpcksb.h r6,lr:b
15181 +       punpcksb.h r12,r12:t
15182 +       .text
15183 +       .global packsh_ub
15184 +packsh_ub:
15185 +       packsh.ub pc,pc,pc
15186 +       packsh.ub r12,r12,r12
15187 +       packsh.ub r5,r5,r5
15188 +       packsh.ub r4,r4,r4
15189 +       packsh.ub lr,lr,lr
15190 +       packsh.ub r3,r6,r3
15191 +       packsh.ub r8,r0,r3
15192 +       packsh.ub r9,r3,lr
15193 +       .text
15194 +       .global packsh_sb
15195 +packsh_sb:
15196 +       packsh.sb pc,pc,pc
15197 +       packsh.sb r12,r12,r12
15198 +       packsh.sb r5,r5,r5
15199 +       packsh.sb r4,r4,r4
15200 +       packsh.sb lr,lr,lr
15201 +       packsh.sb r6,r8,r1
15202 +       packsh.sb lr,r9,r8
15203 +       packsh.sb sp,r6,r6
15204 +       .text
15205 +       .global andl
15206 +andl:
15207 +       andl pc,0
15208 +       andl r12,65535
15209 +       andl r5,32768
15210 +       andl r4,32767
15211 +       andl lr,1
15212 +       andl pc,23128
15213 +       andl r8,47262
15214 +       andl r7,13719
15215 +       .text
15216 +       .global andl_coh
15217 +andl_coh:
15218 +       andl pc,0,COH
15219 +       andl r12,65535,COH
15220 +       andl r5,32768,COH
15221 +       andl r4,32767,COH
15222 +       andl lr,1,COH
15223 +       andl r6,22753,COH
15224 +       andl r0,40653,COH
15225 +       andl r4,48580,COH
15226 +       .text
15227 +       .global andh
15228 +andh:
15229 +       andh pc,0
15230 +       andh r12,65535
15231 +       andh r5,32768
15232 +       andh r4,32767
15233 +       andh lr,1
15234 +       andh r12,52312
15235 +       andh r3,8675
15236 +       andh r2,42987
15237 +       .text
15238 +       .global andh_coh
15239 +andh_coh:
15240 +       andh pc,0,COH
15241 +       andh r12,65535,COH
15242 +       andh r5,32768,COH
15243 +       andh r4,32767,COH
15244 +       andh lr,1,COH
15245 +       andh r11,34317,COH
15246 +       andh r8,52982,COH
15247 +       andh r10,23683,COH
15248 +       .text
15249 +       .global orl
15250 +orl:
15251 +       orl pc,0
15252 +       orl r12,65535
15253 +       orl r5,32768
15254 +       orl r4,32767
15255 +       orl lr,1
15256 +       orl sp,16766
15257 +       orl r0,21181
15258 +       orl pc,44103
15259 +       .text
15260 +       .global orh
15261 +orh:
15262 +       orh pc,0
15263 +       orh r12,65535
15264 +       orh r5,32768
15265 +       orh r4,32767
15266 +       orh lr,1
15267 +       orh r8,28285
15268 +       orh r12,30492
15269 +       orh r1,59930
15270 +       .text
15271 +       .global eorl
15272 +eorl:
15273 +       eorl pc,0
15274 +       eorl r12,65535
15275 +       eorl r5,32768
15276 +       eorl r4,32767
15277 +       eorl lr,1
15278 +       eorl r4,51129
15279 +       eorl r6,64477
15280 +       eorl r1,20913
15281 +       .text
15282 +       .global eorh
15283 +eorh:
15284 +       eorh pc,0
15285 +       eorh r12,65535
15286 +       eorh r5,32768
15287 +       eorh r4,32767
15288 +       eorh lr,1
15289 +       eorh r0,11732
15290 +       eorh r10,38069
15291 +       eorh r9,57130
15292 +       .text
15293 +       .global mcall
15294 +mcall:
15295 +       mcall pc[0]
15296 +       mcall r12[-4]
15297 +       mcall r5[-131072]
15298 +       mcall r4[131068]
15299 +       mcall lr[4]
15300 +       mcall sp[61180]
15301 +       mcall r4[-35000]
15302 +       mcall r0[9924]
15303 +       .text
15304 +       .global pref
15305 +pref:
15306 +       pref pc[0]
15307 +       pref r12[-1]
15308 +       pref r5[-32768]
15309 +       pref r4[32767]
15310 +       pref lr[1]
15311 +       pref r7[7748]
15312 +       pref r7[-7699]
15313 +       pref r2[-25892]
15314 +       .text
15315 +       .global cache
15316 +cache:
15317 +       cache pc[0],0
15318 +       cache r12[-1],31
15319 +       cache r5[-1024],16
15320 +       cache r4[1023],15
15321 +       cache lr[1],1
15322 +       cache r3[-964],17
15323 +       cache r4[-375],22
15324 +       cache r3[-888],17
15325 +       .text
15326 +       .global sub4
15327 +sub4:
15328 +       sub pc,0
15329 +       sub r12,-1
15330 +       sub r5,-1048576
15331 +       sub r4,1048575
15332 +       sub lr,1
15333 +       sub r2,-619156
15334 +       sub lr,461517
15335 +       sub r8,-185051
15336 +       .text
15337 +       .global cp3
15338 +cp3:
15339 +       cp pc,0
15340 +       cp r12,-1
15341 +       cp r5,-1048576
15342 +       cp r4,1048575
15343 +       cp lr,1
15344 +       cp r1,124078
15345 +       cp r0,-378909
15346 +       cp r4,-243180
15347 +       .text
15348 +       .global mov2
15349 +mov2:
15350 +       mov pc,0
15351 +       mov r12,-1
15352 +       mov r5,-1048576
15353 +       mov r4,1048575
15354 +       mov lr,1
15355 +       mov r5,-317021
15356 +       mov sp,-749164
15357 +       mov r5,940179
15358 +       .text
15359 +       .global brc2
15360 +brc2:
15361 +       breq 0
15362 +       bral -2
15363 +       brls -2097152
15364 +       brpl 2097150
15365 +       brne 2
15366 +       brhi -1796966
15367 +       brqs 1321368
15368 +       brls -577434
15369 +       .text
15370 +       .global rcall2
15371 +rcall2:
15372 +       rcall 0
15373 +       rcall -2
15374 +       rcall -2097152
15375 +       rcall 2097150
15376 +       rcall 2
15377 +       rcall 496820
15378 +       rcall 1085092
15379 +       rcall -1058
15380 +       .text
15381 +       .global sub5
15382 +sub5:
15383 +       sub pc,pc,0
15384 +       sub r12,r12,-1
15385 +       sub r5,r5,-32768
15386 +       sub r4,r4,32767
15387 +       sub lr,lr,1
15388 +       sub pc,pc,-12744
15389 +       sub r7,r7,-27365
15390 +       sub r2,r9,-17358
15391 +       .text
15392 +       .global satsub_w2
15393 +satsub_w2:
15394 +       satsub.w pc,pc,0
15395 +       satsub.w r12,r12,-1
15396 +       satsub.w r5,r5,-32768
15397 +       satsub.w r4,r4,32767
15398 +       satsub.w lr,lr,1
15399 +       satsub.w r2,lr,-2007
15400 +       satsub.w r7,r12,-784
15401 +       satsub.w r4,r7,23180
15402 +       .text
15403 +       .global ld_d4
15404 +ld_d4:
15405 +       ld.d r0,pc[0]
15406 +       ld.d r14,r12[-1]
15407 +       ld.d r8,r5[-32768]
15408 +       ld.d r6,r4[32767]
15409 +       ld.d r2,lr[1]
15410 +       ld.d r14,r11[14784]
15411 +       ld.d r6,r9[-18905]
15412 +       ld.d r2,r3[-6355]
15413 +       .text
15414 +       .global ld_w4
15415 +ld_w4:
15416 +       ld.w pc,pc[0]
15417 +       ld.w r12,r12[-1]
15418 +       ld.w r5,r5[-32768]
15419 +       ld.w r4,r4[32767]
15420 +       ld.w lr,lr[1]
15421 +       ld.w r0,r12[-22133]
15422 +       ld.w sp,pc[-20521]
15423 +       /* ld.w r3,r5[29035] */
15424 +       nop
15425 +       .text
15426 +       .global ld_sh4
15427 +ld_sh4:
15428 +       ld.sh pc,pc[0]
15429 +       ld.sh r12,r12[-1]
15430 +       ld.sh r5,r5[-32768]
15431 +       ld.sh r4,r4[32767]
15432 +       ld.sh lr,lr[1]
15433 +       ld.sh r6,r10[30930]
15434 +       ld.sh r6,r10[21973]
15435 +       /* ld.sh r11,r10[-2058] */
15436 +       nop
15437 +       .text
15438 +       .global ld_uh4
15439 +ld_uh4:
15440 +       ld.uh pc,pc[0]
15441 +       ld.uh r12,r12[-1]
15442 +       ld.uh r5,r5[-32768]
15443 +       ld.uh r4,r4[32767]
15444 +       ld.uh lr,lr[1]
15445 +       ld.uh r1,r9[-13354]
15446 +       ld.uh lr,r11[21337]
15447 +       /* ld.uh r2,lr[-25370] */
15448 +       nop
15449 +       .text
15450 +       .global ld_sb1
15451 +ld_sb1:
15452 +       ld.sb pc,pc[0]
15453 +       ld.sb r12,r12[-1]
15454 +       ld.sb r5,r5[-32768]
15455 +       ld.sb r4,r4[32767]
15456 +       ld.sb lr,lr[1]
15457 +       ld.sb r7,sp[-28663]
15458 +       ld.sb r2,r1[-5879]
15459 +       ld.sb r12,r3[18734]
15460 +       .text
15461 +       .global ld_ub4
15462 +ld_ub4:
15463 +       ld.ub pc,pc[0]
15464 +       ld.ub r12,r12[-1]
15465 +       ld.ub r5,r5[-32768]
15466 +       ld.ub r4,r4[32767]
15467 +       ld.ub lr,lr[1]
15468 +       ld.ub pc,r4[8277]
15469 +       ld.ub r5,r12[19172]
15470 +       ld.ub r10,lr[26347]
15471 +       .text
15472 +       .global st_d4
15473 +st_d4:
15474 +       st.d pc[0],r0
15475 +       st.d r12[-1],r14
15476 +       st.d r5[-32768],r8
15477 +       st.d r4[32767],r6
15478 +       st.d lr[1],r2
15479 +       st.d r5[13200],r10
15480 +       st.d r5[9352],r10
15481 +       st.d r5[32373],r4
15482 +       .text
15483 +       .global st_w4
15484 +st_w4:
15485 +       st.w pc[0],pc
15486 +       st.w r12[-1],r12
15487 +       st.w r5[-32768],r5
15488 +       st.w r4[32767],r4
15489 +       st.w lr[1],lr
15490 +       st.w sp[6136],r7
15491 +       st.w r6[27087],r12
15492 +       /* st.w r3[20143],r7 */
15493 +       nop
15494 +       .text
15495 +       .global st_h4
15496 +st_h4:
15497 +       st.h pc[0],pc
15498 +       st.h r12[-1],r12
15499 +       st.h r5[-32768],r5
15500 +       st.h r4[32767],r4
15501 +       st.h lr[1],lr
15502 +       st.h r4[-9962],r7
15503 +       st.h r9[-16250],r3
15504 +       /* st.h r8[-28810],r7 */
15505 +       nop
15506 +       .text
15507 +       .global st_b4
15508 +st_b4:
15509 +       st.b pc[0],pc
15510 +       st.b r12[-1],r12
15511 +       st.b r5[-32768],r5
15512 +       st.b r4[32767],r4
15513 +       st.b lr[1],lr
15514 +       st.b r12[30102],r6
15515 +       st.b r5[28977],r1
15516 +       st.b r0[5470],r1
15517 +       .text
15518 +       .global mfsr
15519 +mfsr:
15520 +       mfsr pc,0
15521 +       mfsr r12,1020
15522 +       mfsr r5,512
15523 +       mfsr r4,508
15524 +       mfsr lr,4
15525 +       mfsr r2,696
15526 +       mfsr r4,260
15527 +       mfsr r10,1016
15528 +       .text
15529 +       .global mtsr
15530 +mtsr:
15531 +       mtsr 0,pc
15532 +       mtsr 1020,r12
15533 +       mtsr 512,r5
15534 +       mtsr 508,r4
15535 +       mtsr 4,lr
15536 +       mtsr 224,r10
15537 +       mtsr 836,r12
15538 +       mtsr 304,r9
15539 +       .text
15540 +       .global mfdr
15541 +mfdr:
15542 +       mfdr pc,0
15543 +       mfdr r12,1020
15544 +       mfdr r5,512
15545 +       mfdr r4,508
15546 +       mfdr lr,4
15547 +       mfdr r6,932
15548 +       mfdr r5,36
15549 +       mfdr r9,300
15550 +       .text
15551 +       .global mtdr
15552 +mtdr:
15553 +       mtdr 0,pc
15554 +       mtdr 1020,r12
15555 +       mtdr 512,r5
15556 +       mtdr 508,r4
15557 +       mtdr 4,lr
15558 +       mtdr 180,r8
15559 +       mtdr 720,r10
15560 +       mtdr 408,lr
15561 +       .text
15562 +       .global sleep
15563 +sleep:
15564 +       sleep 0
15565 +       sleep 255
15566 +       sleep 128
15567 +       sleep 127
15568 +       sleep 1
15569 +       sleep 254
15570 +       sleep 15
15571 +       sleep 43
15572 +       .text
15573 +       .global sync
15574 +sync:
15575 +       sync 0
15576 +       sync 255
15577 +       sync 128
15578 +       sync 127
15579 +       sync 1
15580 +       sync 166
15581 +       sync 230
15582 +       sync 180
15583 +       .text
15584 +       .global bld
15585 +bld:
15586 +       bld pc,0
15587 +       bld r12,31
15588 +       bld r5,16
15589 +       bld r4,15
15590 +       bld lr,1
15591 +       bld r9,15
15592 +       bld r0,4
15593 +       bld lr,26
15594 +       .text
15595 +       .global bst
15596 +bst:
15597 +       bst pc,0
15598 +       bst r12,31
15599 +       bst r5,16
15600 +       bst r4,15
15601 +       bst lr,1
15602 +       bst r10,28
15603 +       bst r0,3
15604 +       bst sp,2
15605 +       .text
15606 +       .global sats
15607 +sats:
15608 +       sats pc>>0,0
15609 +       sats r12>>31,31
15610 +       sats r5>>16,16
15611 +       sats r4>>15,15
15612 +       sats lr>>1,1
15613 +       sats r10>>3,19
15614 +       sats r10>>2,26
15615 +       sats r1>>20,1
15616 +       .text
15617 +       .global satu
15618 +satu:
15619 +       satu pc>>0,0
15620 +       satu r12>>31,31
15621 +       satu r5>>16,16
15622 +       satu r4>>15,15
15623 +       satu lr>>1,1
15624 +       satu pc>>5,7
15625 +       satu r7>>5,5
15626 +       satu r2>>26,19
15627 +       .text
15628 +       .global satrnds
15629 +satrnds:
15630 +       satrnds pc>>0,0
15631 +       satrnds r12>>31,31
15632 +       satrnds r5>>16,16
15633 +       satrnds r4>>15,15
15634 +       satrnds lr>>1,1
15635 +       satrnds r0>>21,19
15636 +       satrnds sp>>0,2
15637 +       satrnds r7>>6,29
15638 +       .text
15639 +       .global satrndu
15640 +satrndu:
15641 +       satrndu pc>>0,0
15642 +       satrndu r12>>31,31
15643 +       satrndu r5>>16,16
15644 +       satrndu r4>>15,15
15645 +       satrndu lr>>1,1
15646 +       satrndu r12>>0,26
15647 +       satrndu r4>>21,3
15648 +       satrndu r10>>3,16
15649 +       .text
15650 +       .global subfc
15651 +subfc:
15652 +       subfeq pc,0
15653 +       subfal r12,-1
15654 +       subfls r5,-128
15655 +       subfpl r4,127
15656 +       subfne lr,1
15657 +       subfls r10,8
15658 +       subfvc r11,99
15659 +       subfvs r2,73
15660 +       .text
15661 +       .global subc
15662 +subc:
15663 +       subeq pc,0
15664 +       subal r12,-1
15665 +       subls r5,-128
15666 +       subpl r4,127
15667 +       subne lr,1
15668 +       subls r12,118
15669 +       subvc lr,-12
15670 +       submi r4,-13
15671 +       .text
15672 +       .global movc2
15673 +movc2:
15674 +       moveq pc,0
15675 +       moval r12,-1
15676 +       movls r5,-128
15677 +       movpl r4,127
15678 +       movne lr,1
15679 +       movlt r3,-122
15680 +       movvc r8,2
15681 +       movne r7,-111
15682 +       .text
15683 +       .global cp_b
15684 +cp_b:
15685 +       cp.b pc,r0
15686 +       cp.b r0,pc
15687 +       cp.b r7,r8
15688 +       cp.b r8,r7
15689 +       .text
15690 +       .global cp_h
15691 +cp_h:
15692 +       cp.h pc,r0
15693 +       cp.h r0,pc
15694 +       cp.h r7,r8
15695 +       cp.h r8,r7
15696 +       .text
15697 +       .global ldm
15698 +ldm:
15699 +       ldm pc,r1-r6
15700 +       ldm r12,r0-r15
15701 +       ldm r5,r15
15702 +       ldm r4,r0-r14
15703 +       ldm lr,r0
15704 +       ldm r9,r1,r5,r14
15705 +       ldm r11,r2-r3,r5-r8,r15
15706 +       ldm r6,r0,r3,r9,r13,r15
15707 +       .text
15708 +       .global ldm_pu
15709 +ldm_pu:
15710 +       ldm pc++,r6-r9
15711 +       ldm r12++,r0-r15
15712 +       ldm r5++,r15
15713 +       ldm r4++,r0-r14
15714 +       ldm lr++,r0
15715 +       ldm r12++,r3-r5,r8,r10,r12,r14-r15
15716 +       ldm r10++,r2,r4-r6,r14-r15
15717 +       ldm r6++,r1,r3-r4,r9-r14
15718 +       .text
15719 +       .global ldmts
15720 +ldmts:
15721 +       ldmts pc,r7-r8
15722 +       ldmts r12,r0-r15
15723 +       ldmts r5,r15
15724 +       ldmts r4,r0-r14
15725 +       ldmts lr,r0
15726 +       ldmts r0,r1-r2,r11-r12
15727 +       ldmts lr,r0-r2,r4,r7-r8,r13-r14
15728 +       ldmts r12,r0-r1,r3-r5,r9,r14-r15
15729 +       .text
15730 +       .global ldmts_pu
15731 +ldmts_pu:
15732 +       ldmts pc++,r9
15733 +       ldmts r12++,r0-r15
15734 +       ldmts r5++,r15
15735 +       ldmts r4++,r0-r14
15736 +       ldmts lr++,r0
15737 +       ldmts sp++,r0,r2-r5,r7,r9,r11
15738 +       ldmts r5++,r1-r3,r7,r10-r11
15739 +       ldmts r8++,r2-r4,r7-r8,r13,r15
15740 +       .text
15741 +       .global stm
15742 +stm:
15743 +       stm pc,r7
15744 +       stm r12,r0-r15
15745 +       stm r5,r15
15746 +       stm r4,r0-r14
15747 +       stm lr,r0
15748 +       stm sp,r2-r3,r5,r8,r11,r14
15749 +       stm r4,r0-r4,r6,r10-r11,r14
15750 +       stm r9,r1,r5,r9,r12-r15
15751 +       .text
15752 +       .global stm_pu
15753 +stm_pu:
15754 +       stm --pc,r4-r6
15755 +       stm --r12,r0-r15
15756 +       stm --r5,r15
15757 +       stm --r4,r0-r14
15758 +       stm --lr,r0
15759 +       stm --r11,r0,r4-r9,r11-r15
15760 +       stm --r11,r0,r3,r9-r10,r12,r14
15761 +       stm --r6,r2,r8-r9,r13-r14
15762 +       .text
15763 +       .global stmts
15764 +stmts:
15765 +       stmts pc,r8
15766 +       stmts r12,r0-r15
15767 +       stmts r5,r15
15768 +       stmts r4,r0-r14
15769 +       stmts lr,r0
15770 +       stmts r1,r0-r1,r3-r4,r6,r9-r10,r14-r15
15771 +       stmts r3,r0,r6-r8,r10-r12
15772 +       stmts r11,r0,r4,r6-r7,r9-r10,r12,r14-r15
15773 +       .text
15774 +       .global stmts_pu
15775 +stmts_pu:
15776 +       stmts --pc,r6-r8
15777 +       stmts --r12,r0-r15
15778 +       stmts --r5,r15
15779 +       stmts --r4,r0-r14
15780 +       stmts --lr,r0
15781 +       stmts --r2,r0,r3-r4,r9-r10,r12-r13
15782 +       stmts --r3,r0-r1,r14-r15
15783 +       stmts --r0,r0,r2-r6,r10,r14
15784 +       .text
15785 +       .global ldins_h
15786 +ldins_h:
15787 +       ldins.h pc:b,pc[0]
15788 +       ldins.h r12:t,r12[-2]
15789 +       ldins.h r5:t,r5[-4096]
15790 +       ldins.h r4:b,r4[4094]
15791 +       ldins.h lr:t,lr[2]
15792 +       ldins.h r0:t,lr[1930]
15793 +       ldins.h r3:b,r7[-534]
15794 +       ldins.h r2:b,r12[-2252]
15795 +       .text
15796 +       .global ldins_b
15797 +ldins_b:
15798 +       ldins.b pc:b,pc[0]
15799 +       ldins.b r12:t,r12[-1]
15800 +       ldins.b r5:u,r5[-2048]
15801 +       ldins.b r4:l,r4[2047]
15802 +       ldins.b lr:l,lr[1]
15803 +       ldins.b r6:t,r4[-662]
15804 +       ldins.b r5:b,r1[-151]
15805 +       ldins.b r10:t,r11[-1923]
15806 +       .text
15807 +       .global ldswp_sh
15808 +ldswp_sh:
15809 +       ldswp.sh pc,pc[0]
15810 +       ldswp.sh r12,r12[-2]
15811 +       ldswp.sh r5,r5[-4096]
15812 +       ldswp.sh r4,r4[4094]
15813 +       ldswp.sh lr,lr[2]
15814 +       ldswp.sh r9,r10[3848]
15815 +       ldswp.sh r4,r12[-2040]
15816 +       ldswp.sh r10,r2[3088]
15817 +       .text
15818 +       .global ldswp_uh
15819 +ldswp_uh:
15820 +       ldswp.uh pc,pc[0]
15821 +       ldswp.uh r12,r12[-2]
15822 +       ldswp.uh r5,r5[-4096]
15823 +       ldswp.uh r4,r4[4094]
15824 +       ldswp.uh lr,lr[2]
15825 +       ldswp.uh r4,r9[3724]
15826 +       ldswp.uh lr,sp[-1672]
15827 +       ldswp.uh r8,r12[-3846]
15828 +       .text
15829 +       .global ldswp_w
15830 +ldswp_w:
15831 +       ldswp.w pc,pc[0]
15832 +       ldswp.w r12,r12[-4]
15833 +       ldswp.w r5,r5[-8192]
15834 +       ldswp.w r4,r4[8188]
15835 +       ldswp.w lr,lr[4]
15836 +       ldswp.w sp,r7[1860]
15837 +       ldswp.w pc,r5[-3324]
15838 +       ldswp.w r12,r10[-3296]
15839 +       .text
15840 +       .global stswp_h
15841 +stswp_h:
15842 +       stswp.h pc[0],pc
15843 +       stswp.h r12[-2],r12
15844 +       stswp.h r5[-4096],r5
15845 +       stswp.h r4[4094],r4
15846 +       stswp.h lr[2],lr
15847 +       stswp.h r7[64],r10
15848 +       stswp.h r10[3024],r2
15849 +       stswp.h r0[-2328],r10
15850 +       .text
15851 +       .global stswp_w
15852 +stswp_w:
15853 +       stswp.w pc[0],pc
15854 +       stswp.w r12[-4],r12
15855 +       stswp.w r5[-8192],r5
15856 +       stswp.w r4[8188],r4
15857 +       stswp.w lr[4],lr
15858 +       stswp.w pc[1156],r8
15859 +       stswp.w sp[7992],r10
15860 +       stswp.w r8[-1172],r5
15861 +       .text
15862 +       .global and2
15863 +and2:
15864 +       and pc,pc,pc<<0
15865 +       and r12,r12,r12<<31
15866 +       and r5,r5,r5<<16
15867 +       and r4,r4,r4<<15
15868 +       and lr,lr,lr<<1
15869 +       and r10,r2,r1<<1
15870 +       and r12,r8,r11<<27
15871 +       and r10,r7,r0<<3
15872 +       .text
15873 +       .global and3
15874 +and3:
15875 +       and pc,pc,pc>>0
15876 +       and r12,r12,r12>>31
15877 +       and r5,r5,r5>>16
15878 +       and r4,r4,r4>>15
15879 +       and lr,lr,lr>>1
15880 +       and r12,r8,r7>>17
15881 +       and pc,r4,r9>>20
15882 +       and r10,r9,r10>>12
15883 +       .text
15884 +       .global or2
15885 +or2:
15886 +       or pc,pc,pc<<0
15887 +       or r12,r12,r12<<31
15888 +       or r5,r5,r5<<16
15889 +       or r4,r4,r4<<15
15890 +       or lr,lr,lr<<1
15891 +       or r8,sp,r11<<29
15892 +       or pc,r9,r2<<28
15893 +       or r5,r1,r2<<3
15894 +       .text
15895 +       .global or3
15896 +or3:
15897 +       or pc,pc,pc>>0
15898 +       or r12,r12,r12>>31
15899 +       or r5,r5,r5>>16
15900 +       or r4,r4,r4>>15
15901 +       or lr,lr,lr>>1
15902 +       or r1,sp,sp>>2
15903 +       or r0,r1,r1>>29
15904 +       or r4,r12,r8>>8
15905 +       .text
15906 +       .global eor2
15907 +eor2:
15908 +       eor pc,pc,pc<<0
15909 +       eor r12,r12,r12<<31
15910 +       eor r5,r5,r5<<16
15911 +       eor r4,r4,r4<<15
15912 +       eor lr,lr,lr<<1
15913 +       eor r10,r9,r4<<11
15914 +       eor r4,r0,r1<<31
15915 +       eor r6,r2,r12<<13
15916 +       .text
15917 +       .global eor3
15918 +eor3:
15919 +       eor pc,pc,pc>>0
15920 +       eor r12,r12,r12>>31
15921 +       eor r5,r5,r5>>16
15922 +       eor r4,r4,r4>>15
15923 +       eor lr,lr,lr>>1
15924 +       eor r5,r5,r5>>22
15925 +       eor r10,r1,lr>>3
15926 +       eor r7,lr,sp>>26
15927 +       .text
15928 +       .global sthh_w2
15929 +sthh_w2:
15930 +       sthh.w pc[pc<<0],pc:b,pc:b
15931 +       sthh.w r12[r12<<3],r12:t,r12:t
15932 +       sthh.w r5[r5<<2],r5:t,r5:t
15933 +       sthh.w r4[r4<<1],r4:b,r4:b
15934 +       sthh.w lr[lr<<1],lr:t,lr:t
15935 +       sthh.w sp[r6<<3],r1:t,r12:t
15936 +       sthh.w r6[r6<<0],r9:t,r9:t
15937 +       sthh.w r10[r3<<0],r0:b,r11:t
15938 +       .text
15939 +       .global sthh_w1
15940 +sthh_w1:
15941 +       sthh.w pc[0],pc:b,pc:b
15942 +       sthh.w r12[1020],r12:t,r12:t
15943 +       sthh.w r5[512],r5:t,r5:t
15944 +       sthh.w r4[508],r4:b,r4:b
15945 +       sthh.w lr[4],lr:t,lr:t
15946 +       sthh.w r4[404],r9:t,r0:b
15947 +       sthh.w r8[348],r2:t,r10:b
15948 +       sthh.w sp[172],r9:b,r2:b
15949 +       .text
15950 +       .global cop
15951 +cop:
15952 +       cop cp0,cr0,cr0,cr0,0
15953 +       cop cp7,cr15,cr15,cr15,0x7f
15954 +       cop cp3,cr5,cr5,cr5,0x31
15955 +       cop cp2,cr4,cr4,cr4,0x30
15956 +       cop cp5,cr8,cr3,cr7,0x5a
15957 +       .text
15958 +       .global ldc_w1
15959 +ldc_w1:
15960 +       ldc.w cp0,cr0,r0[0]
15961 +       ldc.w cp7,cr15,pc[255<<2]
15962 +       ldc.w cp3,cr5,r5[128<<2]
15963 +       ldc.w cp2,cr4,r4[127<<2]
15964 +       ldc.w cp4,cr9,r13[36<<2]
15965 +       .text
15966 +       .global ldc_w2
15967 +ldc_w2:
15968 +       ldc.w cp0,cr0,--r0
15969 +       ldc.w cp7,cr15,--pc
15970 +       ldc.w cp3,cr5,--r5
15971 +       ldc.w cp2,cr4,--r4
15972 +       ldc.w cp4,cr9,--r13
15973 +       .text
15974 +       .global ldc_w3
15975 +ldc_w3:
15976 +       ldc.w cp0,cr0,r0[r0]
15977 +       ldc.w cp7,cr15,pc[pc<<3]
15978 +       ldc.w cp3,cr5,r5[r4<<2]
15979 +       ldc.w cp2,cr4,r4[r3<<1]
15980 +       ldc.w cp4,cr9,r13[r12<<0]
15981 +       .text
15982 +       .global ldc_d1
15983 +ldc_d1:
15984 +       ldc.d cp0,cr0,r0[0]
15985 +       ldc.d cp7,cr14,pc[255<<2]
15986 +       ldc.d cp3,cr6,r5[128<<2]
15987 +       ldc.d cp2,cr4,r4[127<<2]
15988 +       ldc.d cp4,cr8,r13[36<<2]
15989 +       .text
15990 +       .global ldc_d2
15991 +ldc_d2:
15992 +       ldc.d cp0,cr0,--r0
15993 +       ldc.d cp7,cr14,--pc
15994 +       ldc.d cp3,cr6,--r5
15995 +       ldc.d cp2,cr4,--r4
15996 +       ldc.d cp4,cr8,--r13
15997 +       .text
15998 +       .global ldc_d3
15999 +ldc_d3:
16000 +       ldc.d cp0,cr0,r0[r0]
16001 +       ldc.d cp7,cr14,pc[pc<<3]
16002 +       ldc.d cp3,cr6,r5[r4<<2]
16003 +       ldc.d cp2,cr4,r4[r3<<1]
16004 +       ldc.d cp4,cr8,r13[r12<<0]
16005 +       .text
16006 +       .global stc_w1
16007 +stc_w1:
16008 +       stc.w cp0,r0[0],cr0
16009 +       stc.w cp7,pc[255<<2],cr15
16010 +       stc.w cp3,r5[128<<2],cr5
16011 +       stc.w cp2,r4[127<<2],cr4
16012 +       stc.w cp4,r13[36<<2],cr9
16013 +       .text
16014 +       .global stc_w2
16015 +stc_w2:
16016 +       stc.w cp0,r0++,cr0
16017 +       stc.w cp7,pc++,cr15
16018 +       stc.w cp3,r5++,cr5
16019 +       stc.w cp2,r4++,cr4
16020 +       stc.w cp4,r13++,cr9
16021 +       .text
16022 +       .global stc_w3
16023 +stc_w3:
16024 +       stc.w cp0,r0[r0],cr0
16025 +       stc.w cp7,pc[pc<<3],cr15
16026 +       stc.w cp3,r5[r4<<2],cr5
16027 +       stc.w cp2,r4[r3<<1],cr4
16028 +       stc.w cp4,r13[r12<<0],cr9
16029 +       .text
16030 +       .global stc_d1
16031 +stc_d1:
16032 +       stc.d cp0,r0[0],cr0
16033 +       stc.d cp7,pc[255<<2],cr14
16034 +       stc.d cp3,r5[128<<2],cr6
16035 +       stc.d cp2,r4[127<<2],cr4
16036 +       stc.d cp4,r13[36<<2],cr8
16037 +       .text
16038 +       .global stc_d2
16039 +stc_d2:
16040 +       stc.d cp0,r0++,cr0
16041 +       stc.d cp7,pc++,cr14
16042 +       stc.d cp3,r5++,cr6
16043 +       stc.d cp2,r4++,cr4
16044 +       stc.d cp4,r13++,cr8
16045 +       .text
16046 +       .global stc_d3
16047 +stc_d3:
16048 +       stc.d cp0,r0[r0],cr0
16049 +       stc.d cp7,pc[pc<<3],cr14
16050 +       stc.d cp3,r5[r4<<2],cr6
16051 +       stc.d cp2,r4[r3<<1],cr4
16052 +       stc.d cp4,r13[r12<<0],cr8
16053 +       .text
16054 +       .global ldc0_w
16055 +ldc0_w:
16056 +       ldc0.w cr0,r0[0]
16057 +       ldc0.w cr15,pc[4095<<2]
16058 +       ldc0.w cr5,r5[2048<<2]
16059 +       ldc0.w cr4,r4[2047<<2]
16060 +       ldc0.w cr9,r13[147<<2]
16061 +       .text
16062 +       .global ldc0_d
16063 +ldc0_d:
16064 +       ldc0.d cr0,r0[0]
16065 +       ldc0.d cr14,pc[4095<<2]
16066 +       ldc0.d cr6,r5[2048<<2]
16067 +       ldc0.d cr4,r4[2047<<2]
16068 +       ldc0.d cr8,r13[147<<2]
16069 +       .text
16070 +       .global stc0_w
16071 +stc0_w:
16072 +       stc0.w r0[0],cr0
16073 +       stc0.w pc[4095<<2],cr15
16074 +       stc0.w r5[2048<<2],cr5
16075 +       stc0.w r4[2047<<2],cr4
16076 +       stc0.w r13[147<<2],cr9
16077 +       .text
16078 +       .global stc0_d
16079 +stc0_d:
16080 +       stc0.d r0[0],cr0
16081 +       stc0.d pc[4095<<2],cr14
16082 +       stc0.d r5[2048<<2],cr6
16083 +       stc0.d r4[2047<<2],cr4
16084 +       stc0.d r13[147<<2],cr8
16085 +       .text
16086 +       .global memc
16087 +memc:
16088 +       memc 0, 0
16089 +       memc -4, 31
16090 +       memc -65536, 16
16091 +       memc 65532, 15
16092 +       .text
16093 +       .global mems
16094 +mems:
16095 +       mems 0, 0
16096 +       mems -4, 31
16097 +       mems -65536, 16
16098 +       mems 65532, 15
16099 +       .text
16100 +       .global memt
16101 +memt:
16102 +       memt 0, 0
16103 +       memt -4, 31
16104 +       memt -65536, 16
16105 +       memt 65532, 15
16106 +
16107 +       .text
16108 +       .global stcond
16109 +stcond:
16110 +       stcond r0[0], r0
16111 +       stcond pc[-1], pc
16112 +       stcond r8[-32768], r7
16113 +       stcond r7[32767], r8
16114 +       stcond r5[0x1234], r10
16115 +
16116 +ldcm_w:
16117 +       ldcm.w cp0,pc,cr0-cr7
16118 +       ldcm.w cp7,r0,cr0
16119 +       ldcm.w cp4,r4++,cr0-cr6
16120 +       ldcm.w cp3,r7,cr7
16121 +       ldcm.w cp1,r12++,cr1,cr4-cr6
16122 +       ldcm.w cp0,pc,cr8-cr15
16123 +       ldcm.w cp7,r0,cr8
16124 +       ldcm.w cp4,r4++,cr8-cr14
16125 +       ldcm.w cp3,r7,cr15
16126 +       ldcm.w cp1,r12++,cr9,cr12-cr14
16127 +
16128 +ldcm_d:
16129 +       ldcm.d cp0,pc,cr0-cr15
16130 +       ldcm.d cp7,r0,cr0,cr1
16131 +       ldcm.d cp4,r4++,cr0-cr13
16132 +       ldcm.d cp3,r7,cr14-cr15
16133 +       ldcm.d cp2,r12++,cr0-cr3,cr8-cr9,cr14-cr15
16134 +
16135 +stcm_w:
16136 +       stcm.w cp0,pc,cr0-cr7
16137 +       stcm.w cp7,r0,cr0
16138 +       stcm.w cp4,--r4,cr0-cr6
16139 +       stcm.w cp3,r7,cr7
16140 +       stcm.w cp1,--r12,cr1,cr4-cr6
16141 +       stcm.w cp0,pc,cr8-cr15
16142 +       stcm.w cp7,r0,cr8
16143 +       stcm.w cp4,--r4,cr8-cr14
16144 +       stcm.w cp3,r7,cr15
16145 +       stcm.w cp1,--r12,cr9,cr12-cr14
16146 +
16147 +stcm_d:
16148 +       stcm.d cp0,pc,cr0-cr15
16149 +       stcm.d cp7,r0,cr0,cr1
16150 +       stcm.d cp4,--r4,cr0-cr13
16151 +       stcm.d cp3,r7,cr14-cr15
16152 +       stcm.d cp2,--r12,cr0-cr3,cr8-cr9,cr14-cr15
16153 +
16154 +mvcr_w:
16155 +       mvcr.w cp7,pc,cr15
16156 +       mvcr.w cp0,r0,cr0
16157 +       mvcr.w cp0,pc,cr15
16158 +       mvcr.w cp7,r0,cr15
16159 +       mvcr.w cp7,pc,cr0
16160 +       mvcr.w cp4,r7,cr8
16161 +       mvcr.w cp3,r8,cr7
16162 +
16163 +mvcr_d:
16164 +       mvcr.d cp7,lr,cr14
16165 +       mvcr.d cp0,r0,cr0
16166 +       mvcr.d cp0,lr,cr14
16167 +       mvcr.d cp7,r0,cr14
16168 +       mvcr.d cp7,lr,cr0
16169 +       mvcr.d cp4,r6,cr8
16170 +       mvcr.d cp3,r8,cr6
16171 +
16172 +mvrc_w:
16173 +       mvrc.w cp7,cr15,pc
16174 +       mvrc.w cp0,cr0,r0
16175 +       mvrc.w cp0,cr15,pc
16176 +       mvrc.w cp7,cr15,r0
16177 +       mvrc.w cp7,cr0,pc
16178 +       mvrc.w cp4,cr8,r7
16179 +       mvrc.w cp3,cr7,r8
16180 +
16181 +mvrc_d:
16182 +       mvrc.d cp7,cr14,lr
16183 +       mvrc.d cp0,cr0,r0
16184 +       mvrc.d cp0,cr14,lr
16185 +       mvrc.d cp7,cr14,r0
16186 +       mvrc.d cp7,cr0,lr
16187 +       mvrc.d cp4,cr8,r6
16188 +       mvrc.d cp3,cr6,r8
16189 +
16190 +bfexts:
16191 +       bfexts pc,pc,31,31
16192 +       bfexts r0,r0,0,0
16193 +       bfexts r0,pc,31,31
16194 +       bfexts pc,r0,31,31
16195 +       bfexts pc,pc,0,31
16196 +       bfexts pc,pc,31,0
16197 +       bfexts r7,r8,15,16
16198 +       bfexts r8,r7,16,15
16199 +
16200 +bfextu:
16201 +       bfextu pc,pc,31,31
16202 +       bfextu r0,r0,0,0
16203 +       bfextu r0,pc,31,31
16204 +       bfextu pc,r0,31,31
16205 +       bfextu pc,pc,0,31
16206 +       bfextu pc,pc,31,0
16207 +       bfextu r7,r8,15,16
16208 +       bfextu r8,r7,16,15
16209 +
16210 +bfins:
16211 +       bfins pc,pc,31,31
16212 +       bfins r0,r0,0,0
16213 +       bfins r0,pc,31,31
16214 +       bfins pc,r0,31,31
16215 +       bfins pc,pc,0,31
16216 +       bfins pc,pc,31,0
16217 +       bfins r7,r8,15,16
16218 +       bfins r8,r7,16,15
16219 +
16220 +rsubc:
16221 +       rsubeq pc,0
16222 +       rsubal r12,-1
16223 +       rsubls r5,-128
16224 +       rsubpl r4,127
16225 +       rsubne lr,1
16226 +       rsubls r12,118
16227 +       rsubvc lr,-12
16228 +       rsubmi r4,-13
16229 +
16230 +addc:
16231 +       addeq pc,pc,pc
16232 +       addal r12,r12,r12
16233 +       addls r5,r5,r5
16234 +       addpl r4,r4,r4
16235 +       addne lr,lr,lr
16236 +       addls r10,r2,r1
16237 +       addvc r12,r8,r11
16238 +       addmi r10,r7,r0
16239 +
16240 +subc2:
16241 +       subeq pc,pc,pc
16242 +       subal r12,r12,r12
16243 +       subls r5,r5,r5
16244 +       subpl r4,r4,r4
16245 +       subne lr,lr,lr
16246 +       subls r10,r2,r1
16247 +       subvc r12,r8,r11
16248 +       submi r10,r7,r0
16249 +
16250 +andc:
16251 +       andeq pc,pc,pc
16252 +       andal r12,r12,r12
16253 +       andls r5,r5,r5
16254 +       andpl r4,r4,r4
16255 +       andne lr,lr,lr
16256 +       andls r10,r2,r1
16257 +       andvc r12,r8,r11
16258 +       andmi r10,r7,r0
16259 +
16260 +orc:
16261 +       oreq pc,pc,pc
16262 +       oral r12,r12,r12
16263 +       orls r5,r5,r5
16264 +       orpl r4,r4,r4
16265 +       orne lr,lr,lr
16266 +       orls r10,r2,r1
16267 +       orvc r12,r8,r11
16268 +       ormi r10,r7,r0
16269 +
16270 +eorc:
16271 +       eoreq pc,pc,pc
16272 +       eoral r12,r12,r12
16273 +       eorls r5,r5,r5
16274 +       eorpl r4,r4,r4
16275 +       eorne lr,lr,lr
16276 +       eorls r10,r2,r1
16277 +       eorvc r12,r8,r11
16278 +       eormi r10,r7,r0
16279 +
16280 +ldcond:
16281 +       ld.weq  pc,pc[2044]
16282 +       ld.shal r12,r12[1022]
16283 +       ld.uhls r5,r5[0]
16284 +       ld.ubpl r4,r4[511]
16285 +       ld.sbne lr,lr[0]
16286 +       ld.wls  r10,r2[0]
16287 +       ld.shvc r12,r8[0x3fe]
16288 +       ld.ubmi r10,r7[1]
16289 +
16290 +stcond2:
16291 +       st.weq pc[2044],pc
16292 +       st.hal r12[1022],r12
16293 +       st.hls r5[0],r5
16294 +       st.bpl r4[511],r4
16295 +       st.bne lr[0],lr
16296 +       st.wls r2[0],r10
16297 +       st.hvc r8[0x3fe],r12
16298 +       st.bmi r7[1],r10
16299 +
16300 +movh:
16301 +       movh    pc, 65535
16302 +       movh    r0, 0
16303 +       movh    r5, 1
16304 +       movh    r12, 32767
16305 +
16306 +
16307 --- /dev/null
16308 +++ b/gas/testsuite/gas/avr32/avr32.exp
16309 @@ -0,0 +1,23 @@
16310 +# AVR32 assembler testsuite. -*- Tcl -*-
16311 +
16312 +if [istarget avr32-*-*] {
16313 +    run_dump_test "hwrd-lwrd"
16314 +    run_dump_test "pcrel"
16315 +    run_dump_test "aliases"
16316 +    run_dump_test "dwarf2"
16317 +    run_dump_test "pic_reloc"
16318 +    run_dump_test "fpinsn"
16319 +    run_dump_test "pico"
16320 +    run_dump_test "lda_pic"
16321 +    run_dump_test "lda_pic_linkrelax"
16322 +    run_dump_test "lda_nopic"
16323 +    run_dump_test "lda_nopic_linkrelax"
16324 +    run_dump_test "call_pic"
16325 +    run_dump_test "call_pic_linkrelax"
16326 +    run_dump_test "call_nopic"
16327 +    run_dump_test "call_nopic_linkrelax"
16328 +    run_dump_test "jmptable"
16329 +    run_dump_test "jmptable_linkrelax"
16330 +    run_dump_test "symdiff"
16331 +    run_dump_test "symdiff_linkrelax"
16332 +}
16333 --- /dev/null
16334 +++ b/gas/testsuite/gas/avr32/call_nopic.d
16335 @@ -0,0 +1,36 @@
16336 +#source: call.s
16337 +#as:
16338 +#objdump: -dr
16339 +#name: call_nopic
16340 +
16341 +.*: +file format .*
16342 +
16343 +Disassembly of section \.text:
16344 +
16345 +00000000 <call_test>:
16346 +       0:      d7 03           nop
16347 +
16348 +00000002 <toofar_negative>:
16349 +       \.\.\.
16350 +  1ffffe:      00 00           add r0,r0
16351 +  200000:      f0 a0 00 00     rcall 0 <call_test>
16352 +  200004:      f0 1f 00 0c     mcall 200034 <toofar_negative\+0x200032>
16353 +  200008:      f0 1f 00 0c     mcall 200038 <toofar_negative\+0x200036>
16354 +  20000c:      f0 1f 00 0c     mcall 20003c <toofar_negative\+0x20003a>
16355 +  200010:      f0 1f 00 0c     mcall 200040 <toofar_negative\+0x20003e>
16356 +       \.\.\.
16357 +  200030:      ee b0 ff ff     rcall 40002e <far_positive>
16358 +       \.\.\.
16359 +                       200034: R_AVR32_32_CPENT        \.text\+0x2
16360 +                       200038: R_AVR32_32_CPENT        \.text\.init
16361 +                       20003c: R_AVR32_32_CPENT        undefined
16362 +                       200040: R_AVR32_32_CPENT        \.text\+0x40002c
16363 +
16364 +0040002c <toofar_positive>:
16365 +  40002c:      d7 03           nop
16366 +0040002e <far_positive>:
16367 +  40002e:      d7 03           nop
16368 +Disassembly of section \.text\.init:
16369 +
16370 +00000000 <different_section>:
16371 +   0:  e2 c0 00 00     sub r0,r1,0
16372 --- /dev/null
16373 +++ b/gas/testsuite/gas/avr32/call_nopic_linkrelax.d
16374 @@ -0,0 +1,43 @@
16375 +#source: call.s
16376 +#as: --linkrelax
16377 +#objdump: -dr
16378 +#name: call_nopic_linkrelax
16379 +
16380 +.*: +file format .*
16381 +
16382 +Disassembly of section \.text:
16383 +
16384 +00000000 <call_test>:
16385 +       0:      d7 03           nop
16386 +
16387 +00000002 <toofar_negative>:
16388 +       \.\.\.
16389 +  1ffffe:      00 00           add r0,r0
16390 +  200000:      e0 a0 00 00     rcall 200000 <toofar_negative\+0x1ffffe>
16391 +                       200000: R_AVR32_22H_PCREL       \.text
16392 +  200004:      f0 1f 00 00     mcall 200004 <toofar_negative\+0x200002>
16393 +                       200004: R_AVR32_CPCALL  \.text\+0x200034
16394 +  200008:      f0 1f 00 00     mcall 200008 <toofar_negative\+0x200006>
16395 +                       200008: R_AVR32_CPCALL  \.text\+0x200038
16396 +  20000c:      f0 1f 00 00     mcall 20000c <toofar_negative\+0x20000a>
16397 +                       20000c: R_AVR32_CPCALL  \.text\+0x20003c
16398 +  200010:      f0 1f 00 00     mcall 200010 <toofar_negative\+0x20000e>
16399 +                       200010: R_AVR32_CPCALL  \.text\+0x200040
16400 +       \.\.\.
16401 +  200030:      e0 a0 00 00     rcall 200030 <toofar_negative\+0x20002e>
16402 +                       200030: R_AVR32_22H_PCREL       \.text\+0x40002e
16403 +       \.\.\.
16404 +                       200034: R_AVR32_ALIGN   \*ABS\*\+0x2
16405 +                       200034: R_AVR32_32_CPENT        \.text\+0x2
16406 +                       200038: R_AVR32_32_CPENT        \.text\.init
16407 +                       20003c: R_AVR32_32_CPENT        undefined
16408 +                       200040: R_AVR32_32_CPENT        \.text\+0x40002c
16409 +
16410 +0040002c <toofar_positive>:
16411 +  40002c:      d7 03           nop
16412 +0040002e <far_positive>:
16413 +  40002e:      d7 03           nop
16414 +Disassembly of section \.text\.init:
16415 +
16416 +00000000 <different_section>:
16417 +   0:  e2 c0 00 00     sub r0,r1,0
16418 --- /dev/null
16419 +++ b/gas/testsuite/gas/avr32/call_pic.d
16420 @@ -0,0 +1,36 @@
16421 +#source: call.s
16422 +#as: --pic
16423 +#objdump: -dr
16424 +#name: call_pic
16425 +
16426 +.*: +file format .*
16427 +
16428 +Disassembly of section \.text:
16429 +
16430 +00000000 <call_test>:
16431 +       0:      d7 03           nop
16432 +
16433 +00000002 <toofar_negative>:
16434 +       \.\.\.
16435 +  1ffffe:      00 00           add r0,r0
16436 +  200000:      f0 a0 00 00     rcall 0 <call_test>
16437 +  200004:      f0 16 00 00     mcall r6\[0\]
16438 +                       200004: R_AVR32_GOT18SW toofar_negative
16439 +  200008:      f0 16 00 00     mcall r6\[0\]
16440 +                       200008: R_AVR32_GOT18SW different_section
16441 +  20000c:      f0 16 00 00     mcall r6\[0\]
16442 +                       20000c: R_AVR32_GOT18SW undefined
16443 +  200010:      f0 16 00 00     mcall r6\[0\]
16444 +                       200010: R_AVR32_GOT18SW toofar_positive
16445 +       \.\.\.
16446 +  200030:      ee b0 ff ff     rcall 40002e <far_positive>
16447 +       \.\.\.
16448 +
16449 +0040002c <toofar_positive>:
16450 +  40002c:      d7 03           nop
16451 +0040002e <far_positive>:
16452 +  40002e:      d7 03           nop
16453 +Disassembly of section \.text\.init:
16454 +
16455 +00000000 <different_section>:
16456 +   0:  e2 c0 00 00     sub r0,r1,0
16457 --- /dev/null
16458 +++ b/gas/testsuite/gas/avr32/call_pic_linkrelax.d
16459 @@ -0,0 +1,47 @@
16460 +#source: call.s
16461 +#as: --pic --linkrelax
16462 +#objdump: -dr
16463 +#name: call_pic_linkrelax
16464 +
16465 +.*: +file format .*
16466 +
16467 +Disassembly of section \.text:
16468 +
16469 +00000000 <call_test>:
16470 +       0:      d7 03           nop
16471 +
16472 +00000002 <toofar_negative>:
16473 +       \.\.\.
16474 +  1ffffe:      00 00           add r0,r0
16475 +  200000:      e0 a0 00 00     rcall 200000 <toofar_negative\+0x1ffffe>
16476 +                       200000: R_AVR32_22H_PCREL       \.text
16477 +  200004:      e0 6e 00 00     mov lr,0
16478 +                       200004: R_AVR32_GOTCALL toofar_negative
16479 +  200008:      ec 0e 03 2e     ld\.w lr,r6\[lr<<0x2\]
16480 +  20000c:      5d 1e           icall lr
16481 +  20000e:      e0 6e 00 00     mov lr,0
16482 +                       20000e: R_AVR32_GOTCALL different_section
16483 +  200012:      ec 0e 03 2e     ld\.w lr,r6\[lr<<0x2\]
16484 +  200016:      5d 1e           icall lr
16485 +  200018:      e0 6e 00 00     mov lr,0
16486 +                       200018: R_AVR32_GOTCALL undefined
16487 +  20001c:      ec 0e 03 2e     ld\.w lr,r6\[lr<<0x2\]
16488 +  200020:      5d 1e           icall lr
16489 +  200022:      e0 6e 00 00     mov lr,0
16490 +                       200022: R_AVR32_GOTCALL toofar_positive
16491 +  200026:      ec 0e 03 2e     ld\.w lr,r6\[lr<<0x2\]
16492 +  20002a:      5d 1e           icall lr
16493 +  20002c:      00 00           add r0,r0
16494 +  20002e:      00 00           add r0,r0
16495 +  200030:      e0 a0 00 00     rcall 200030 <toofar_negative\+0x20002e>
16496 +                       200030: R_AVR32_22H_PCREL       \.text\+0x40002e
16497 +       \.\.\.
16498 +
16499 +0040002c <toofar_positive>:
16500 +  40002c:      d7 03           nop
16501 +0040002e <far_positive>:
16502 +  40002e:      d7 03           nop
16503 +Disassembly of section \.text\.init:
16504 +
16505 +00000000 <different_section>:
16506 +   0:  e2 c0 00 00     sub r0,r1,0
16507 --- /dev/null
16508 +++ b/gas/testsuite/gas/avr32/call.s
16509 @@ -0,0 +1,30 @@
16510 +
16511 +       .text
16512 +       .global call_test
16513 +call_test:
16514 +far_negative:
16515 +       nop
16516 +toofar_negative:
16517 +
16518 +       .org    0x200000
16519 +
16520 +       call    far_negative
16521 +       call    toofar_negative
16522 +       call    different_section
16523 +       call    undefined
16524 +       call    toofar_positive
16525 +       .org    0x200030
16526 +       call    far_positive
16527 +
16528 +       .cpool
16529 +
16530 +       .org    0x40002c
16531 +
16532 +toofar_positive:
16533 +       nop
16534 +far_positive:
16535 +       nop
16536 +
16537 +       .section .text.init,"ax",@progbits
16538 +different_section:
16539 +       sub     r0, r1, 0
16540 --- /dev/null
16541 +++ b/gas/testsuite/gas/avr32/dwarf2.d
16542 @@ -0,0 +1,42 @@
16543 +#readelf: -wl
16544 +#name: dwarf2
16545 +#source: dwarf2.s
16546 +
16547 +Dump of debug contents of section \.debug_line:
16548 +
16549 +  Length:                      53
16550 +  DWARF Version:               2
16551 +  Prologue Length:             26
16552 +  Minimum Instruction Length:  1
16553 +  Initial value of 'is_stmt':  1
16554 +  Line Base:                   -5
16555 +  Line Range:                  14
16556 +  Opcode Base:                 10
16557 +  \(Pointer size:               4\)
16558 +
16559 + Opcodes:
16560 +  Opcode 1 has 0 args
16561 +  Opcode 2 has 1 args
16562 +  Opcode 3 has 1 args
16563 +  Opcode 4 has 1 args
16564 +  Opcode 5 has 1 args
16565 +  Opcode 6 has 0 args
16566 +  Opcode 7 has 0 args
16567 +  Opcode 8 has 0 args
16568 +  Opcode 9 has 1 args
16569 +
16570 + The Directory Table is empty\.
16571 +
16572 + The File Name Table:
16573 +  Entry        Dir     Time    Size    Name
16574 +  1    0       0       0       main\.c
16575 +
16576 + Line Number Statements:
16577 +  Extended opcode 2: set Address to 0x0
16578 +  Advance Line by 87 to 88
16579 +  Copy
16580 +  Advance Line by 23 to 111
16581 +  Special opcode .*: advance Address by 4 to 0x4 and Line by 0 to 111
16582 +  Special opcode .*: advance Address by 10 to 0xe and Line by 1 to 112
16583 +  Advance PC by 530 to 220
16584 +  Extended opcode 1: End of Sequence
16585 --- /dev/null
16586 +++ b/gas/testsuite/gas/avr32/dwarf2.s
16587 @@ -0,0 +1,67 @@
16588 +# Source file used to test DWARF2 information for AVR32.
16589 +
16590 +       .file   "main.c"
16591 +
16592 +       .section .debug_abbrev,"",@progbits
16593 +.Ldebug_abbrev0:
16594 +       .section .debug_info,"",@progbits
16595 +.Ldebug_info0:
16596 +       .section .debug_line,"",@progbits
16597 +.Ldebug_line0:
16598 +
16599 +       .text
16600 +       .align  1
16601 +       .globl  main
16602 +       .type   main, @function
16603 +.Ltext0:
16604 +main:
16605 +       .file 1 "main.c"
16606 +       .loc 1 88 0
16607 +       pushm   r0-r7,lr
16608 +       sub     sp, 4
16609 +       .loc 1 111 0
16610 +       lddpc   r12, .LC1
16611 +       lddpc   r7, .LC1
16612 +       icall   r7
16613 +       .loc 1 112 0
16614 +       lddpc   r6, .LC4
16615 +
16616 +       .align  2
16617 +.LC4:  .int    0
16618 +
16619 +       .fill   256, 2, 0
16620 +
16621 +       .align  2
16622 +.LC1:
16623 +       .int    0
16624 +.LC2:
16625 +       .int    0
16626 +.LC3:
16627 +       .int    0
16628 +       .size   main, . - main
16629 +
16630 +.Letext0:
16631 +
16632 +       .section .debug_info
16633 +       .int    .Ledebug_info0 - .Ldebug_info0  // size
16634 +       .short  2                               // version
16635 +       .int    .Ldebug_abbrev0                 // abbrev offset
16636 +       .byte   4                               // bytes per addr
16637 +
16638 +       .uleb128 1                              // abbrev 1
16639 +       .int    .Ldebug_line0                   // DW_AT_stmt_list
16640 +       .int    .Letext0                        // DW_AT_high_pc
16641 +       .int    .Ltext0                         // DW_AT_low_pc
16642 +
16643 +.Ledebug_info0:
16644 +
16645 +       .section .debug_abbrev
16646 +       .uleb128 0x01
16647 +       .uleb128 0x11           // DW_TAG_compile_unit
16648 +       .byte   0               // DW_CHILDREN_no
16649 +       .uleb128 0x10, 0x6      // DW_AT_stmt_list
16650 +       .uleb128 0x12, 0x1      // DW_AT_high_pc
16651 +       .uleb128 0x11, 0x1      // DW_AT_low_pc
16652 +       .uleb128 0, 0
16653 +
16654 +       .byte   0
16655 --- /dev/null
16656 +++ b/gas/testsuite/gas/avr32/fpinsn.d
16657 @@ -0,0 +1,271 @@
16658 +#as:
16659 +#objdump: -dr
16660 +#name: fpinsn
16661 +
16662 +.*: +file format .*
16663 +
16664 +Disassembly of section \.text:
16665 +
16666 +[0-9a-f]* <fadd_s>:
16667 + *[0-9a-f]*:   e1 a2 0f ff     cop cp0,cr15,cr15,cr15,0x4
16668 + *[0-9a-f]*:   e1 a2 00 00     cop cp0,cr0,cr0,cr0,0x4
16669 + *[0-9a-f]*:   e1 a2 00 ff     cop cp0,cr0,cr15,cr15,0x4
16670 + *[0-9a-f]*:   e1 a2 0f 0f     cop cp0,cr15,cr0,cr15,0x4
16671 + *[0-9a-f]*:   e1 a2 0f f0     cop cp0,cr15,cr15,cr0,0x4
16672 + *[0-9a-f]*:   e1 a2 07 88     cop cp0,cr7,cr8,cr8,0x4
16673 + *[0-9a-f]*:   e1 a2 08 78     cop cp0,cr8,cr7,cr8,0x4
16674 + *[0-9a-f]*:   e1 a2 08 87     cop cp0,cr8,cr8,cr7,0x4
16675 +
16676 +[0-9a-f]* <fsub_s>:
16677 + *[0-9a-f]*:   e1 a2 1f ff     cop cp0,cr15,cr15,cr15,0x5
16678 + *[0-9a-f]*:   e1 a2 10 00     cop cp0,cr0,cr0,cr0,0x5
16679 + *[0-9a-f]*:   e1 a2 10 ff     cop cp0,cr0,cr15,cr15,0x5
16680 + *[0-9a-f]*:   e1 a2 1f 0f     cop cp0,cr15,cr0,cr15,0x5
16681 + *[0-9a-f]*:   e1 a2 1f f0     cop cp0,cr15,cr15,cr0,0x5
16682 + *[0-9a-f]*:   e1 a2 17 88     cop cp0,cr7,cr8,cr8,0x5
16683 + *[0-9a-f]*:   e1 a2 18 78     cop cp0,cr8,cr7,cr8,0x5
16684 + *[0-9a-f]*:   e1 a2 18 87     cop cp0,cr8,cr8,cr7,0x5
16685 +
16686 +[0-9a-f]* <fmac_s>:
16687 + *[0-9a-f]*:   e1 a0 0f ff     cop cp0,cr15,cr15,cr15,0x0
16688 + *[0-9a-f]*:   e1 a0 00 00     cop cp0,cr0,cr0,cr0,0x0
16689 + *[0-9a-f]*:   e1 a0 00 ff     cop cp0,cr0,cr15,cr15,0x0
16690 + *[0-9a-f]*:   e1 a0 0f 0f     cop cp0,cr15,cr0,cr15,0x0
16691 + *[0-9a-f]*:   e1 a0 0f f0     cop cp0,cr15,cr15,cr0,0x0
16692 + *[0-9a-f]*:   e1 a0 07 88     cop cp0,cr7,cr8,cr8,0x0
16693 + *[0-9a-f]*:   e1 a0 08 78     cop cp0,cr8,cr7,cr8,0x0
16694 + *[0-9a-f]*:   e1 a0 08 87     cop cp0,cr8,cr8,cr7,0x0
16695 +
16696 +[0-9a-f]* <fnmac_s>:
16697 + *[0-9a-f]*:   e1 a0 1f ff     cop cp0,cr15,cr15,cr15,0x1
16698 + *[0-9a-f]*:   e1 a0 10 00     cop cp0,cr0,cr0,cr0,0x1
16699 + *[0-9a-f]*:   e1 a0 10 ff     cop cp0,cr0,cr15,cr15,0x1
16700 + *[0-9a-f]*:   e1 a0 1f 0f     cop cp0,cr15,cr0,cr15,0x1
16701 + *[0-9a-f]*:   e1 a0 1f f0     cop cp0,cr15,cr15,cr0,0x1
16702 + *[0-9a-f]*:   e1 a0 17 88     cop cp0,cr7,cr8,cr8,0x1
16703 + *[0-9a-f]*:   e1 a0 18 78     cop cp0,cr8,cr7,cr8,0x1
16704 + *[0-9a-f]*:   e1 a0 18 87     cop cp0,cr8,cr8,cr7,0x1
16705 +
16706 +[0-9a-f]* <fmsc_s>:
16707 + *[0-9a-f]*:   e1 a1 0f ff     cop cp0,cr15,cr15,cr15,0x2
16708 + *[0-9a-f]*:   e1 a1 00 00     cop cp0,cr0,cr0,cr0,0x2
16709 + *[0-9a-f]*:   e1 a1 00 ff     cop cp0,cr0,cr15,cr15,0x2
16710 + *[0-9a-f]*:   e1 a1 0f 0f     cop cp0,cr15,cr0,cr15,0x2
16711 + *[0-9a-f]*:   e1 a1 0f f0     cop cp0,cr15,cr15,cr0,0x2
16712 + *[0-9a-f]*:   e1 a1 07 88     cop cp0,cr7,cr8,cr8,0x2
16713 + *[0-9a-f]*:   e1 a1 08 78     cop cp0,cr8,cr7,cr8,0x2
16714 + *[0-9a-f]*:   e1 a1 08 87     cop cp0,cr8,cr8,cr7,0x2
16715 +
16716 +[0-9a-f]* <fnmsc_s>:
16717 + *[0-9a-f]*:   e1 a1 1f ff     cop cp0,cr15,cr15,cr15,0x3
16718 + *[0-9a-f]*:   e1 a1 10 00     cop cp0,cr0,cr0,cr0,0x3
16719 + *[0-9a-f]*:   e1 a1 10 ff     cop cp0,cr0,cr15,cr15,0x3
16720 + *[0-9a-f]*:   e1 a1 1f 0f     cop cp0,cr15,cr0,cr15,0x3
16721 + *[0-9a-f]*:   e1 a1 1f f0     cop cp0,cr15,cr15,cr0,0x3
16722 + *[0-9a-f]*:   e1 a1 17 88     cop cp0,cr7,cr8,cr8,0x3
16723 + *[0-9a-f]*:   e1 a1 18 78     cop cp0,cr8,cr7,cr8,0x3
16724 + *[0-9a-f]*:   e1 a1 18 87     cop cp0,cr8,cr8,cr7,0x3
16725 +
16726 +[0-9a-f]* <fmul_s>:
16727 + *[0-9a-f]*:   e1 a3 0f ff     cop cp0,cr15,cr15,cr15,0x6
16728 + *[0-9a-f]*:   e1 a3 00 00     cop cp0,cr0,cr0,cr0,0x6
16729 + *[0-9a-f]*:   e1 a3 00 ff     cop cp0,cr0,cr15,cr15,0x6
16730 + *[0-9a-f]*:   e1 a3 0f 0f     cop cp0,cr15,cr0,cr15,0x6
16731 + *[0-9a-f]*:   e1 a3 0f f0     cop cp0,cr15,cr15,cr0,0x6
16732 + *[0-9a-f]*:   e1 a3 07 88     cop cp0,cr7,cr8,cr8,0x6
16733 + *[0-9a-f]*:   e1 a3 08 78     cop cp0,cr8,cr7,cr8,0x6
16734 + *[0-9a-f]*:   e1 a3 08 87     cop cp0,cr8,cr8,cr7,0x6
16735 +
16736 +[0-9a-f]* <fnmul_s>:
16737 + *[0-9a-f]*:   e1 a3 1f ff     cop cp0,cr15,cr15,cr15,0x7
16738 + *[0-9a-f]*:   e1 a3 10 00     cop cp0,cr0,cr0,cr0,0x7
16739 + *[0-9a-f]*:   e1 a3 10 ff     cop cp0,cr0,cr15,cr15,0x7
16740 + *[0-9a-f]*:   e1 a3 1f 0f     cop cp0,cr15,cr0,cr15,0x7
16741 + *[0-9a-f]*:   e1 a3 1f f0     cop cp0,cr15,cr15,cr0,0x7
16742 + *[0-9a-f]*:   e1 a3 17 88     cop cp0,cr7,cr8,cr8,0x7
16743 + *[0-9a-f]*:   e1 a3 18 78     cop cp0,cr8,cr7,cr8,0x7
16744 + *[0-9a-f]*:   e1 a3 18 87     cop cp0,cr8,cr8,cr7,0x7
16745 +
16746 +[0-9a-f]* <fneg_s>:
16747 + *[0-9a-f]*:   e1 a4 0f f0     cop cp0,cr15,cr15,cr0,0x8
16748 + *[0-9a-f]*:   e1 a4 00 00     cop cp0,cr0,cr0,cr0,0x8
16749 + *[0-9a-f]*:   e1 a4 00 f0     cop cp0,cr0,cr15,cr0,0x8
16750 + *[0-9a-f]*:   e1 a4 0f 00     cop cp0,cr15,cr0,cr0,0x8
16751 + *[0-9a-f]*:   e1 a4 07 80     cop cp0,cr7,cr8,cr0,0x8
16752 + *[0-9a-f]*:   e1 a4 08 70     cop cp0,cr8,cr7,cr0,0x8
16753 +
16754 +[0-9a-f]* <fabs_s>:
16755 + *[0-9a-f]*:   e1 a4 1f f0     cop cp0,cr15,cr15,cr0,0x9
16756 + *[0-9a-f]*:   e1 a4 10 00     cop cp0,cr0,cr0,cr0,0x9
16757 + *[0-9a-f]*:   e1 a4 10 f0     cop cp0,cr0,cr15,cr0,0x9
16758 + *[0-9a-f]*:   e1 a4 1f 00     cop cp0,cr15,cr0,cr0,0x9
16759 + *[0-9a-f]*:   e1 a4 17 80     cop cp0,cr7,cr8,cr0,0x9
16760 + *[0-9a-f]*:   e1 a4 18 70     cop cp0,cr8,cr7,cr0,0x9
16761 +
16762 +[0-9a-f]* <fcmp_s>:
16763 + *[0-9a-f]*:   e1 a6 10 ff     cop cp0,cr0,cr15,cr15,0xd
16764 + *[0-9a-f]*:   e1 a6 10 00     cop cp0,cr0,cr0,cr0,0xd
16765 + *[0-9a-f]*:   e1 a6 10 0f     cop cp0,cr0,cr0,cr15,0xd
16766 + *[0-9a-f]*:   e1 a6 10 f0     cop cp0,cr0,cr15,cr0,0xd
16767 + *[0-9a-f]*:   e1 a6 10 78     cop cp0,cr0,cr7,cr8,0xd
16768 + *[0-9a-f]*:   e1 a6 10 87     cop cp0,cr0,cr8,cr7,0xd
16769 +
16770 +[0-9a-f]* <fadd_d>:
16771 + *[0-9a-f]*:   e5 a2 0e ee     cop cp0,cr14,cr14,cr14,0x44
16772 + *[0-9a-f]*:   e5 a2 00 00     cop cp0,cr0,cr0,cr0,0x44
16773 + *[0-9a-f]*:   e5 a2 00 ee     cop cp0,cr0,cr14,cr14,0x44
16774 + *[0-9a-f]*:   e5 a2 0e 0e     cop cp0,cr14,cr0,cr14,0x44
16775 + *[0-9a-f]*:   e5 a2 0e e0     cop cp0,cr14,cr14,cr0,0x44
16776 + *[0-9a-f]*:   e5 a2 06 88     cop cp0,cr6,cr8,cr8,0x44
16777 + *[0-9a-f]*:   e5 a2 08 68     cop cp0,cr8,cr6,cr8,0x44
16778 + *[0-9a-f]*:   e5 a2 08 86     cop cp0,cr8,cr8,cr6,0x44
16779 +
16780 +[0-9a-f]* <fsub_d>:
16781 + *[0-9a-f]*:   e5 a2 1e ee     cop cp0,cr14,cr14,cr14,0x45
16782 + *[0-9a-f]*:   e5 a2 10 00     cop cp0,cr0,cr0,cr0,0x45
16783 + *[0-9a-f]*:   e5 a2 10 ee     cop cp0,cr0,cr14,cr14,0x45
16784 + *[0-9a-f]*:   e5 a2 1e 0e     cop cp0,cr14,cr0,cr14,0x45
16785 + *[0-9a-f]*:   e5 a2 1e e0     cop cp0,cr14,cr14,cr0,0x45
16786 + *[0-9a-f]*:   e5 a2 16 88     cop cp0,cr6,cr8,cr8,0x45
16787 + *[0-9a-f]*:   e5 a2 18 68     cop cp0,cr8,cr6,cr8,0x45
16788 + *[0-9a-f]*:   e5 a2 18 86     cop cp0,cr8,cr8,cr6,0x45
16789 +
16790 +[0-9a-f]* <fmac_d>:
16791 + *[0-9a-f]*:   e5 a0 0e ee     cop cp0,cr14,cr14,cr14,0x40
16792 + *[0-9a-f]*:   e5 a0 00 00     cop cp0,cr0,cr0,cr0,0x40
16793 + *[0-9a-f]*:   e5 a0 00 ee     cop cp0,cr0,cr14,cr14,0x40
16794 + *[0-9a-f]*:   e5 a0 0e 0e     cop cp0,cr14,cr0,cr14,0x40
16795 + *[0-9a-f]*:   e5 a0 0e e0     cop cp0,cr14,cr14,cr0,0x40
16796 + *[0-9a-f]*:   e5 a0 06 88     cop cp0,cr6,cr8,cr8,0x40
16797 + *[0-9a-f]*:   e5 a0 08 68     cop cp0,cr8,cr6,cr8,0x40
16798 + *[0-9a-f]*:   e5 a0 08 86     cop cp0,cr8,cr8,cr6,0x40
16799 +
16800 +[0-9a-f]* <fnmac_d>:
16801 + *[0-9a-f]*:   e5 a0 1e ee     cop cp0,cr14,cr14,cr14,0x41
16802 + *[0-9a-f]*:   e5 a0 10 00     cop cp0,cr0,cr0,cr0,0x41
16803 + *[0-9a-f]*:   e5 a0 10 ee     cop cp0,cr0,cr14,cr14,0x41
16804 + *[0-9a-f]*:   e5 a0 1e 0e     cop cp0,cr14,cr0,cr14,0x41
16805 + *[0-9a-f]*:   e5 a0 1e e0     cop cp0,cr14,cr14,cr0,0x41
16806 + *[0-9a-f]*:   e5 a0 16 88     cop cp0,cr6,cr8,cr8,0x41
16807 + *[0-9a-f]*:   e5 a0 18 68     cop cp0,cr8,cr6,cr8,0x41
16808 + *[0-9a-f]*:   e5 a0 18 86     cop cp0,cr8,cr8,cr6,0x41
16809 +
16810 +[0-9a-f]* <fmsc_d>:
16811 + *[0-9a-f]*:   e5 a1 0e ee     cop cp0,cr14,cr14,cr14,0x42
16812 + *[0-9a-f]*:   e5 a1 00 00     cop cp0,cr0,cr0,cr0,0x42
16813 + *[0-9a-f]*:   e5 a1 00 ee     cop cp0,cr0,cr14,cr14,0x42
16814 + *[0-9a-f]*:   e5 a1 0e 0e     cop cp0,cr14,cr0,cr14,0x42
16815 + *[0-9a-f]*:   e5 a1 0e e0     cop cp0,cr14,cr14,cr0,0x42
16816 + *[0-9a-f]*:   e5 a1 06 88     cop cp0,cr6,cr8,cr8,0x42
16817 + *[0-9a-f]*:   e5 a1 08 68     cop cp0,cr8,cr6,cr8,0x42
16818 + *[0-9a-f]*:   e5 a1 08 86     cop cp0,cr8,cr8,cr6,0x42
16819 +
16820 +[0-9a-f]* <fnmsc_d>:
16821 + *[0-9a-f]*:   e5 a1 1e ee     cop cp0,cr14,cr14,cr14,0x43
16822 + *[0-9a-f]*:   e5 a1 10 00     cop cp0,cr0,cr0,cr0,0x43
16823 + *[0-9a-f]*:   e5 a1 10 ee     cop cp0,cr0,cr14,cr14,0x43
16824 + *[0-9a-f]*:   e5 a1 1e 0e     cop cp0,cr14,cr0,cr14,0x43
16825 + *[0-9a-f]*:   e5 a1 1e e0     cop cp0,cr14,cr14,cr0,0x43
16826 + *[0-9a-f]*:   e5 a1 16 88     cop cp0,cr6,cr8,cr8,0x43
16827 + *[0-9a-f]*:   e5 a1 18 68     cop cp0,cr8,cr6,cr8,0x43
16828 + *[0-9a-f]*:   e5 a1 18 86     cop cp0,cr8,cr8,cr6,0x43
16829 +
16830 +[0-9a-f]* <fmul_d>:
16831 + *[0-9a-f]*:   e5 a3 0e ee     cop cp0,cr14,cr14,cr14,0x46
16832 + *[0-9a-f]*:   e5 a3 00 00     cop cp0,cr0,cr0,cr0,0x46
16833 + *[0-9a-f]*:   e5 a3 00 ee     cop cp0,cr0,cr14,cr14,0x46
16834 + *[0-9a-f]*:   e5 a3 0e 0e     cop cp0,cr14,cr0,cr14,0x46
16835 + *[0-9a-f]*:   e5 a3 0e e0     cop cp0,cr14,cr14,cr0,0x46
16836 + *[0-9a-f]*:   e5 a3 06 88     cop cp0,cr6,cr8,cr8,0x46
16837 + *[0-9a-f]*:   e5 a3 08 68     cop cp0,cr8,cr6,cr8,0x46
16838 + *[0-9a-f]*:   e5 a3 08 86     cop cp0,cr8,cr8,cr6,0x46
16839 +
16840 +[0-9a-f]* <fnmul_d>:
16841 + *[0-9a-f]*:   e5 a3 1e ee     cop cp0,cr14,cr14,cr14,0x47
16842 + *[0-9a-f]*:   e5 a3 10 00     cop cp0,cr0,cr0,cr0,0x47
16843 + *[0-9a-f]*:   e5 a3 10 ee     cop cp0,cr0,cr14,cr14,0x47
16844 + *[0-9a-f]*:   e5 a3 1e 0e     cop cp0,cr14,cr0,cr14,0x47
16845 + *[0-9a-f]*:   e5 a3 1e e0     cop cp0,cr14,cr14,cr0,0x47
16846 + *[0-9a-f]*:   e5 a3 16 88     cop cp0,cr6,cr8,cr8,0x47
16847 + *[0-9a-f]*:   e5 a3 18 68     cop cp0,cr8,cr6,cr8,0x47
16848 + *[0-9a-f]*:   e5 a3 18 86     cop cp0,cr8,cr8,cr6,0x47
16849 +
16850 +[0-9a-f]* <fneg_d>:
16851 + *[0-9a-f]*:   e5 a4 0e e0     cop cp0,cr14,cr14,cr0,0x48
16852 + *[0-9a-f]*:   e5 a4 00 00     cop cp0,cr0,cr0,cr0,0x48
16853 + *[0-9a-f]*:   e5 a4 00 e0     cop cp0,cr0,cr14,cr0,0x48
16854 + *[0-9a-f]*:   e5 a4 0e 00     cop cp0,cr14,cr0,cr0,0x48
16855 + *[0-9a-f]*:   e5 a4 06 80     cop cp0,cr6,cr8,cr0,0x48
16856 + *[0-9a-f]*:   e5 a4 08 60     cop cp0,cr8,cr6,cr0,0x48
16857 +
16858 +[0-9a-f]* <fabs_d>:
16859 + *[0-9a-f]*:   e5 a4 1e e0     cop cp0,cr14,cr14,cr0,0x49
16860 + *[0-9a-f]*:   e5 a4 10 00     cop cp0,cr0,cr0,cr0,0x49
16861 + *[0-9a-f]*:   e5 a4 10 e0     cop cp0,cr0,cr14,cr0,0x49
16862 + *[0-9a-f]*:   e5 a4 1e 00     cop cp0,cr14,cr0,cr0,0x49
16863 + *[0-9a-f]*:   e5 a4 16 80     cop cp0,cr6,cr8,cr0,0x49
16864 + *[0-9a-f]*:   e5 a4 18 60     cop cp0,cr8,cr6,cr0,0x49
16865 +
16866 +[0-9a-f]* <fcmp_d>:
16867 + *[0-9a-f]*:   e5 a6 10 ee     cop cp0,cr0,cr14,cr14,0x4d
16868 + *[0-9a-f]*:   e5 a6 10 00     cop cp0,cr0,cr0,cr0,0x4d
16869 + *[0-9a-f]*:   e5 a6 10 0e     cop cp0,cr0,cr0,cr14,0x4d
16870 + *[0-9a-f]*:   e5 a6 10 e0     cop cp0,cr0,cr14,cr0,0x4d
16871 + *[0-9a-f]*:   e5 a6 10 68     cop cp0,cr0,cr6,cr8,0x4d
16872 + *[0-9a-f]*:   e5 a6 10 86     cop cp0,cr0,cr8,cr6,0x4d
16873 +
16874 +[0-9a-f]* <fmov_s>:
16875 + *[0-9a-f]*:   e1 a5 0f f0     cop cp0,cr15,cr15,cr0,0xa
16876 + *[0-9a-f]*:   e1 a5 00 00     cop cp0,cr0,cr0,cr0,0xa
16877 + *[0-9a-f]*:   e1 a5 0f 00     cop cp0,cr15,cr0,cr0,0xa
16878 + *[0-9a-f]*:   e1 a5 00 f0     cop cp0,cr0,cr15,cr0,0xa
16879 + *[0-9a-f]*:   e1 a5 08 70     cop cp0,cr8,cr7,cr0,0xa
16880 + *[0-9a-f]*:   e1 a5 07 80     cop cp0,cr7,cr8,cr0,0xa
16881 + *[0-9a-f]*:   ef af 0f 00     mvcr.w cp0,pc,cr15
16882 + *[0-9a-f]*:   ef a0 00 00     mvcr.w cp0,r0,cr0
16883 + *[0-9a-f]*:   ef af 00 00     mvcr.w cp0,pc,cr0
16884 + *[0-9a-f]*:   ef a0 0f 00     mvcr.w cp0,r0,cr15
16885 + *[0-9a-f]*:   ef a8 07 00     mvcr.w cp0,r8,cr7
16886 + *[0-9a-f]*:   ef a7 08 00     mvcr.w cp0,r7,cr8
16887 + *[0-9a-f]*:   ef af 0f 20     mvrc.w cp0,cr15,pc
16888 + *[0-9a-f]*:   ef a0 00 20     mvrc.w cp0,cr0,r0
16889 + *[0-9a-f]*:   ef a0 0f 20     mvrc.w cp0,cr15,r0
16890 + *[0-9a-f]*:   ef af 00 20     mvrc.w cp0,cr0,pc
16891 + *[0-9a-f]*:   ef a7 08 20     mvrc.w cp0,cr8,r7
16892 + *[0-9a-f]*:   ef a8 07 20     mvrc.w cp0,cr7,r8
16893 +
16894 +[0-9a-f]* <fmov_d>:
16895 + *[0-9a-f]*:   e5 a5 0e e0     cop cp0,cr14,cr14,cr0,0x4a
16896 + *[0-9a-f]*:   e5 a5 00 00     cop cp0,cr0,cr0,cr0,0x4a
16897 + *[0-9a-f]*:   e5 a5 0e 00     cop cp0,cr14,cr0,cr0,0x4a
16898 + *[0-9a-f]*:   e5 a5 00 e0     cop cp0,cr0,cr14,cr0,0x4a
16899 + *[0-9a-f]*:   e5 a5 08 60     cop cp0,cr8,cr6,cr0,0x4a
16900 + *[0-9a-f]*:   e5 a5 06 80     cop cp0,cr6,cr8,cr0,0x4a
16901 + *[0-9a-f]*:   ef ae 0e 10     mvcr.d cp0,lr,cr14
16902 + *[0-9a-f]*:   ef a0 00 10     mvcr.d cp0,r0,cr0
16903 + *[0-9a-f]*:   ef ae 00 10     mvcr.d cp0,lr,cr0
16904 + *[0-9a-f]*:   ef a0 0e 10     mvcr.d cp0,r0,cr14
16905 + *[0-9a-f]*:   ef a8 06 10     mvcr.d cp0,r8,cr6
16906 + *[0-9a-f]*:   ef a6 08 10     mvcr.d cp0,r6,cr8
16907 + *[0-9a-f]*:   ef ae 0e 30     mvrc.d cp0,cr14,lr
16908 + *[0-9a-f]*:   ef a0 00 30     mvrc.d cp0,cr0,r0
16909 + *[0-9a-f]*:   ef a0 0e 30     mvrc.d cp0,cr14,r0
16910 + *[0-9a-f]*:   ef ae 00 30     mvrc.d cp0,cr0,lr
16911 + *[0-9a-f]*:   ef a6 08 30     mvrc.d cp0,cr8,r6
16912 + *[0-9a-f]*:   ef a8 06 30     mvrc.d cp0,cr6,r8
16913 +
16914 +[0-9a-f]* <fcasts_d>:
16915 + *[0-9a-f]*:   e1 a7 1f e0     cop cp0,cr15,cr14,cr0,0xf
16916 + *[0-9a-f]*:   e1 a7 10 00     cop cp0,cr0,cr0,cr0,0xf
16917 + *[0-9a-f]*:   e1 a7 1f 00     cop cp0,cr15,cr0,cr0,0xf
16918 + *[0-9a-f]*:   e1 a7 10 e0     cop cp0,cr0,cr14,cr0,0xf
16919 + *[0-9a-f]*:   e1 a7 18 60     cop cp0,cr8,cr6,cr0,0xf
16920 + *[0-9a-f]*:   e1 a7 17 80     cop cp0,cr7,cr8,cr0,0xf
16921 +
16922 +[0-9a-f]* <fcastd_s>:
16923 + *[0-9a-f]*:   e1 a8 0e f0     cop cp0,cr14,cr15,cr0,0x10
16924 + *[0-9a-f]*:   e1 a8 00 00     cop cp0,cr0,cr0,cr0,0x10
16925 + *[0-9a-f]*:   e1 a8 0e 00     cop cp0,cr14,cr0,cr0,0x10
16926 + *[0-9a-f]*:   e1 a8 00 f0     cop cp0,cr0,cr15,cr0,0x10
16927 + *[0-9a-f]*:   e1 a8 08 70     cop cp0,cr8,cr7,cr0,0x10
16928 + *[0-9a-f]*:   e1 a8 06 80     cop cp0,cr6,cr8,cr0,0x10
16929 --- /dev/null
16930 +++ b/gas/testsuite/gas/avr32/fpinsn.s
16931 @@ -0,0 +1,266 @@
16932 +
16933 +       .text
16934 +       .global fadd_s
16935 +fadd_s:
16936 +       fadd.s fr15, fr15, fr15
16937 +       fadd.s fr0, fr0, fr0
16938 +       fadd.s fr0, fr15, fr15
16939 +       fadd.s fr15, fr0, fr15
16940 +       fadd.s fr15, fr15, fr0
16941 +       fadd.s fr7, fr8, fr8
16942 +       fadd.s fr8, fr7, fr8
16943 +       fadd.s fr8, fr8, fr7
16944 +       .global fsub_s
16945 +fsub_s:
16946 +       fsub.s fr15, fr15, fr15
16947 +       fsub.s fr0, fr0, fr0
16948 +       fsub.s fr0, fr15, fr15
16949 +       fsub.s fr15, fr0, fr15
16950 +       fsub.s fr15, fr15, fr0
16951 +       fsub.s fr7, fr8, fr8
16952 +       fsub.s fr8, fr7, fr8
16953 +       fsub.s fr8, fr8, fr7
16954 +       .global fmac_s
16955 +fmac_s:
16956 +       fmac.s fr15, fr15, fr15
16957 +       fmac.s fr0, fr0, fr0
16958 +       fmac.s fr0, fr15, fr15
16959 +       fmac.s fr15, fr0, fr15
16960 +       fmac.s fr15, fr15, fr0
16961 +       fmac.s fr7, fr8, fr8
16962 +       fmac.s fr8, fr7, fr8
16963 +       fmac.s fr8, fr8, fr7
16964 +       .global fnmac_s
16965 +fnmac_s:
16966 +       fnmac.s fr15, fr15, fr15
16967 +       fnmac.s fr0, fr0, fr0
16968 +       fnmac.s fr0, fr15, fr15
16969 +       fnmac.s fr15, fr0, fr15
16970 +       fnmac.s fr15, fr15, fr0
16971 +       fnmac.s fr7, fr8, fr8
16972 +       fnmac.s fr8, fr7, fr8
16973 +       fnmac.s fr8, fr8, fr7
16974 +       .global fmsc_s
16975 +fmsc_s:
16976 +       fmsc.s fr15, fr15, fr15
16977 +       fmsc.s fr0, fr0, fr0
16978 +       fmsc.s fr0, fr15, fr15
16979 +       fmsc.s fr15, fr0, fr15
16980 +       fmsc.s fr15, fr15, fr0
16981 +       fmsc.s fr7, fr8, fr8
16982 +       fmsc.s fr8, fr7, fr8
16983 +       fmsc.s fr8, fr8, fr7
16984 +       .global fnmsc_s
16985 +fnmsc_s:
16986 +       fnmsc.s fr15, fr15, fr15
16987 +       fnmsc.s fr0, fr0, fr0
16988 +       fnmsc.s fr0, fr15, fr15
16989 +       fnmsc.s fr15, fr0, fr15
16990 +       fnmsc.s fr15, fr15, fr0
16991 +       fnmsc.s fr7, fr8, fr8
16992 +       fnmsc.s fr8, fr7, fr8
16993 +       fnmsc.s fr8, fr8, fr7
16994 +       .global fmul_s
16995 +fmul_s:
16996 +       fmul.s fr15, fr15, fr15
16997 +       fmul.s fr0, fr0, fr0
16998 +       fmul.s fr0, fr15, fr15
16999 +       fmul.s fr15, fr0, fr15
17000 +       fmul.s fr15, fr15, fr0
17001 +       fmul.s fr7, fr8, fr8
17002 +       fmul.s fr8, fr7, fr8
17003 +       fmul.s fr8, fr8, fr7
17004 +       .global fnmul_s
17005 +fnmul_s:
17006 +       fnmul.s fr15, fr15, fr15
17007 +       fnmul.s fr0, fr0, fr0
17008 +       fnmul.s fr0, fr15, fr15
17009 +       fnmul.s fr15, fr0, fr15
17010 +       fnmul.s fr15, fr15, fr0
17011 +       fnmul.s fr7, fr8, fr8
17012 +       fnmul.s fr8, fr7, fr8
17013 +       fnmul.s fr8, fr8, fr7
17014 +       .global fneg_s
17015 +fneg_s:
17016 +       fneg.s fr15, fr15
17017 +       fneg.s fr0, fr0
17018 +       fneg.s fr0, fr15
17019 +       fneg.s fr15, fr0
17020 +       fneg.s fr7, fr8
17021 +       fneg.s fr8, fr7
17022 +       .global fabs_s
17023 +fabs_s:
17024 +       fabs.s fr15, fr15
17025 +       fabs.s fr0, fr0
17026 +       fabs.s fr0, fr15
17027 +       fabs.s fr15, fr0
17028 +       fabs.s fr7, fr8
17029 +       fabs.s fr8, fr7
17030 +       .global fcmp_s
17031 +fcmp_s:
17032 +       fcmp.s fr15, fr15
17033 +       fcmp.s fr0, fr0
17034 +       fcmp.s fr0, fr15
17035 +       fcmp.s fr15, fr0
17036 +       fcmp.s fr7, fr8
17037 +       fcmp.s fr8, fr7
17038 +       .global fadd_d
17039 +fadd_d:
17040 +       fadd.d fr14, fr14, fr14
17041 +       fadd.d fr0, fr0, fr0
17042 +       fadd.d fr0, fr14, fr14
17043 +       fadd.d fr14, fr0, fr14
17044 +       fadd.d fr14, fr14, fr0
17045 +       fadd.d fr6, fr8, fr8
17046 +       fadd.d fr8, fr6, fr8
17047 +       fadd.d fr8, fr8, fr6
17048 +       .global fsub_d
17049 +fsub_d:
17050 +       fsub.d fr14, fr14, fr14
17051 +       fsub.d fr0, fr0, fr0
17052 +       fsub.d fr0, fr14, fr14
17053 +       fsub.d fr14, fr0, fr14
17054 +       fsub.d fr14, fr14, fr0
17055 +       fsub.d fr6, fr8, fr8
17056 +       fsub.d fr8, fr6, fr8
17057 +       fsub.d fr8, fr8, fr6
17058 +       .global fmac_d
17059 +fmac_d:
17060 +       fmac.d fr14, fr14, fr14
17061 +       fmac.d fr0, fr0, fr0
17062 +       fmac.d fr0, fr14, fr14
17063 +       fmac.d fr14, fr0, fr14
17064 +       fmac.d fr14, fr14, fr0
17065 +       fmac.d fr6, fr8, fr8
17066 +       fmac.d fr8, fr6, fr8
17067 +       fmac.d fr8, fr8, fr6
17068 +       .global fnmac_d
17069 +fnmac_d:
17070 +       fnmac.d fr14, fr14, fr14
17071 +       fnmac.d fr0, fr0, fr0
17072 +       fnmac.d fr0, fr14, fr14
17073 +       fnmac.d fr14, fr0, fr14
17074 +       fnmac.d fr14, fr14, fr0
17075 +       fnmac.d fr6, fr8, fr8
17076 +       fnmac.d fr8, fr6, fr8
17077 +       fnmac.d fr8, fr8, fr6
17078 +       .global fmsc_d
17079 +fmsc_d:
17080 +       fmsc.d fr14, fr14, fr14
17081 +       fmsc.d fr0, fr0, fr0
17082 +       fmsc.d fr0, fr14, fr14
17083 +       fmsc.d fr14, fr0, fr14
17084 +       fmsc.d fr14, fr14, fr0
17085 +       fmsc.d fr6, fr8, fr8
17086 +       fmsc.d fr8, fr6, fr8
17087 +       fmsc.d fr8, fr8, fr6
17088 +       .global fnmsc_d
17089 +fnmsc_d:
17090 +       fnmsc.d fr14, fr14, fr14
17091 +       fnmsc.d fr0, fr0, fr0
17092 +       fnmsc.d fr0, fr14, fr14
17093 +       fnmsc.d fr14, fr0, fr14
17094 +       fnmsc.d fr14, fr14, fr0
17095 +       fnmsc.d fr6, fr8, fr8
17096 +       fnmsc.d fr8, fr6, fr8
17097 +       fnmsc.d fr8, fr8, fr6
17098 +       .global fmul_d
17099 +fmul_d:
17100 +       fmul.d fr14, fr14, fr14
17101 +       fmul.d fr0, fr0, fr0
17102 +       fmul.d fr0, fr14, fr14
17103 +       fmul.d fr14, fr0, fr14
17104 +       fmul.d fr14, fr14, fr0
17105 +       fmul.d fr6, fr8, fr8
17106 +       fmul.d fr8, fr6, fr8
17107 +       fmul.d fr8, fr8, fr6
17108 +       .global fnmul_d
17109 +fnmul_d:
17110 +       fnmul.d fr14, fr14, fr14
17111 +       fnmul.d fr0, fr0, fr0
17112 +       fnmul.d fr0, fr14, fr14
17113 +       fnmul.d fr14, fr0, fr14
17114 +       fnmul.d fr14, fr14, fr0
17115 +       fnmul.d fr6, fr8, fr8
17116 +       fnmul.d fr8, fr6, fr8
17117 +       fnmul.d fr8, fr8, fr6
17118 +       .global fneg_d
17119 +fneg_d:
17120 +       fneg.d fr14, fr14
17121 +       fneg.d fr0, fr0
17122 +       fneg.d fr0, fr14
17123 +       fneg.d fr14, fr0
17124 +       fneg.d fr6, fr8
17125 +       fneg.d fr8, fr6
17126 +       .global fabs_d
17127 +fabs_d:
17128 +       fabs.d fr14, fr14
17129 +       fabs.d fr0, fr0
17130 +       fabs.d fr0, fr14
17131 +       fabs.d fr14, fr0
17132 +       fabs.d fr6, fr8
17133 +       fabs.d fr8, fr6
17134 +       .global fcmp_d
17135 +fcmp_d:
17136 +       fcmp.d fr14, fr14
17137 +       fcmp.d fr0, fr0
17138 +       fcmp.d fr0, fr14
17139 +       fcmp.d fr14, fr0
17140 +       fcmp.d fr6, fr8
17141 +       fcmp.d fr8, fr6
17142 +       .global fmov_s
17143 +fmov_s:
17144 +       fmov.s fr15, fr15
17145 +       fmov.s fr0, fr0
17146 +       fmov.s fr15, fr0
17147 +       fmov.s fr0, fr15
17148 +       fmov.s fr8, fr7
17149 +       fmov.s fr7, fr8
17150 +       fmov.s pc, fr15
17151 +       fmov.s r0, fr0
17152 +       fmov.s pc, fr0
17153 +       fmov.s r0, fr15
17154 +       fmov.s r8, fr7
17155 +       fmov.s r7, fr8
17156 +       fmov.s fr15, pc
17157 +       fmov.s fr0, r0
17158 +       fmov.s fr15, r0
17159 +       fmov.s fr0, pc
17160 +       fmov.s fr8, r7
17161 +       fmov.s fr7, r8
17162 +       .global fmov_d
17163 +fmov_d:
17164 +       fmov.d fr14, fr14
17165 +       fmov.d fr0, fr0
17166 +       fmov.d fr14, fr0
17167 +       fmov.d fr0, fr14
17168 +       fmov.d fr8, fr6
17169 +       fmov.d fr6, fr8
17170 +       fmov.d lr, fr14
17171 +       fmov.d r0, fr0
17172 +       fmov.d lr, fr0
17173 +       fmov.d r0, fr14
17174 +       fmov.d r8, fr6
17175 +       fmov.d r6, fr8
17176 +       fmov.d fr14, lr
17177 +       fmov.d fr0, r0
17178 +       fmov.d fr14, r0
17179 +       fmov.d fr0, lr
17180 +       fmov.d fr8, r6
17181 +       fmov.d fr6, r8
17182 +       .global fcasts_d
17183 +fcasts_d:
17184 +       fcasts.d fr15, fr14
17185 +       fcasts.d fr0, fr0
17186 +       fcasts.d fr15, fr0
17187 +       fcasts.d fr0, fr14
17188 +       fcasts.d fr8, fr6
17189 +       fcasts.d fr7, fr8
17190 +       .global fcastd_s
17191 +fcastd_s:
17192 +       fcastd.s fr14, fr15
17193 +       fcastd.s fr0, fr0
17194 +       fcastd.s fr14, fr0
17195 +       fcastd.s fr0, fr15
17196 +       fcastd.s fr8, fr7
17197 +       fcastd.s fr6, fr8
17198 --- /dev/null
17199 +++ b/gas/testsuite/gas/avr32/hwrd-lwrd.d
17200 @@ -0,0 +1,47 @@
17201 +#as:
17202 +#objdump: -dr
17203 +#name: hwrd-lwrd
17204 +
17205 +.*: +file format .*
17206 +
17207 +Disassembly of section \.text:
17208 +
17209 +00000000 <test_hwrd>:
17210 +   0:  e0 60 87 65     mov r0,34661
17211 +   4:  e0 60 12 34     mov r0,4660
17212 +   8:  e0 60 00 00     mov r0,0
17213 +                       8: R_AVR32_HI16 \.text\+0x60
17214 +   c:  e0 60 00 00     mov r0,0
17215 +                       c: R_AVR32_HI16 extsym1
17216 +  10:  ea 10 87 65     orh r0,0x8765
17217 +  14:  ea 10 12 34     orh r0,0x1234
17218 +  18:  ea 10 00 00     orh r0,0x0
17219 +                       18: R_AVR32_HI16        \.text\+0x60
17220 +  1c:  ea 10 00 00     orh r0,0x0
17221 +                       1c: R_AVR32_HI16        extsym1
17222 +  20:  e4 10 87 65     andh r0,0x8765
17223 +  24:  e4 10 12 34     andh r0,0x1234
17224 +  28:  e4 10 00 00     andh r0,0x0
17225 +                       28: R_AVR32_HI16        \.text\+0x60
17226 +  2c:  e4 10 00 00     andh r0,0x0
17227 +                       2c: R_AVR32_HI16        extsym1
17228 +
17229 +00000030 <test_lwrd>:
17230 +  30:  e0 60 43 21     mov r0,17185
17231 +  34:  e0 60 56 78     mov r0,22136
17232 +  38:  e0 60 00 00     mov r0,0
17233 +                       38: R_AVR32_LO16        \.text\+0x60
17234 +  3c:  e0 60 00 00     mov r0,0
17235 +                       3c: R_AVR32_LO16        extsym1
17236 +  40:  e8 10 43 21     orl r0,0x4321
17237 +  44:  e8 10 56 78     orl r0,0x5678
17238 +  48:  e8 10 00 00     orl r0,0x0
17239 +                       48: R_AVR32_LO16        \.text\+0x60
17240 +  4c:  e8 10 00 00     orl r0,0x0
17241 +                       4c: R_AVR32_LO16        extsym1
17242 +  50:  e0 10 43 21     andl r0,0x4321
17243 +  54:  e0 10 56 78     andl r0,0x5678
17244 +  58:  e0 10 00 00     andl r0,0x0
17245 +                       58: R_AVR32_LO16        \.text\+0x60
17246 +  5c:  e0 10 00 00     andl r0,0x0
17247 +                       5c: R_AVR32_LO16        extsym1
17248 --- /dev/null
17249 +++ b/gas/testsuite/gas/avr32/hwrd-lwrd.s
17250 @@ -0,0 +1,39 @@
17251 +
17252 +        .equ    sym1, 0x12345678
17253 +
17254 +        .text
17255 +        .global test_hwrd
17256 +test_hwrd:
17257 +        mov     r0, hi(0x87654321)
17258 +        mov     r0, hi(sym1)
17259 +        mov     r0, hi(sym2)
17260 +        mov     r0, hi(extsym1)
17261 +
17262 +        orh    r0, hi(0x87654321)
17263 +        orh    r0, hi(sym1)
17264 +        orh    r0, hi(sym2)
17265 +        orh    r0, hi(extsym1)
17266 +
17267 +        andh   r0, hi(0x87654321)
17268 +        andh   r0, hi(sym1)
17269 +        andh   r0, hi(sym2)
17270 +        andh   r0, hi(extsym1)
17271 +
17272 +        .global test_lwrd
17273 +test_lwrd:
17274 +        mov     r0, lo(0x87654321)
17275 +        mov     r0, lo(sym1)
17276 +        mov     r0, lo(sym2)
17277 +        mov     r0, lo(extsym1)
17278 +
17279 +        orl    r0, lo(0x87654321)
17280 +        orl    r0, lo(sym1)
17281 +        orl    r0, lo(sym2)
17282 +        orl    r0, lo(extsym1)
17283 +
17284 +        andl   r0, lo(0x87654321)
17285 +        andl   r0, lo(sym1)
17286 +        andl   r0, lo(sym2)
17287 +        andl   r0, lo(extsym1)
17288 +
17289 +sym2:
17290 --- /dev/null
17291 +++ b/gas/testsuite/gas/avr32/jmptable.d
17292 @@ -0,0 +1,20 @@
17293 +#source: jmptable.s
17294 +#as:
17295 +#objdump: -dr
17296 +#name: jmptable
17297 +
17298 +.*: +file format .*
17299 +
17300 +Disassembly of section \.text:
17301 +
17302 +00000000 <jmptable_test>:
17303 +   0:  fe c8 ff f4     sub r8,pc,-12
17304 +   4:  f0 00 00 2f     add pc,r8,r0<<0x2
17305 +   8:  d7 03           nop
17306 +   a:  00 00           add r0,r0
17307 +   c:  c0 38           rjmp 12 <jmptable_test\+0x12>
17308 +   e:  c0 38           rjmp 14 <jmptable_test\+0x14>
17309 +  10:  c0 38           rjmp 16 <jmptable_test\+0x16>
17310 +  12:  d7 03           nop
17311 +  14:  d7 03           nop
17312 +  16:  d7 03           nop
17313 --- /dev/null
17314 +++ b/gas/testsuite/gas/avr32/jmptable_linkrelax.d
17315 @@ -0,0 +1,25 @@
17316 +#source: jmptable.s
17317 +#as: --linkrelax
17318 +#objdump: -dr
17319 +#name: jmptable_linkrelax
17320 +
17321 +.*: +file format .*
17322 +
17323 +Disassembly of section \.text:
17324 +
17325 +00000000 <jmptable_test>:
17326 +   0:  fe c8 00 00     sub r8,pc,0
17327 +                       0: R_AVR32_16N_PCREL    \.text\+0xc
17328 +   4:  f0 00 00 2f     add pc,r8,r0<<0x2
17329 +   8:  d7 03           nop
17330 +   a:  00 00           add r0,r0
17331 +                       a: R_AVR32_ALIGN        \*ABS\*\+0x2
17332 +   c:  c0 08           rjmp c <jmptable_test\+0xc>
17333 +                       c: R_AVR32_11H_PCREL    \.text\+0x12
17334 +   e:  c0 08           rjmp e <jmptable_test\+0xe>
17335 +                       e: R_AVR32_11H_PCREL    \.text\+0x14
17336 +  10:  c0 08           rjmp 10 <jmptable_test\+0x10>
17337 +                       10: R_AVR32_11H_PCREL   \.text\+0x16
17338 +  12:  d7 03           nop
17339 +  14:  d7 03           nop
17340 +  16:  d7 03           nop
17341 --- /dev/null
17342 +++ b/gas/testsuite/gas/avr32/jmptable.s
17343 @@ -0,0 +1,14 @@
17344 +
17345 +       .text
17346 +       .global jmptable_test
17347 +jmptable_test:
17348 +       sub     r8, pc, -(.L1 - .)
17349 +       add     pc, r8, r0 << 2
17350 +       nop
17351 +       .align  2
17352 +.L1:   rjmp    1f
17353 +       rjmp    2f
17354 +       rjmp    3f
17355 +1:     nop
17356 +2:     nop
17357 +3:     nop
17358 --- /dev/null
17359 +++ b/gas/testsuite/gas/avr32/lda_nopic.d
17360 @@ -0,0 +1,32 @@
17361 +#source: lda.s
17362 +#as:
17363 +#objdump: -dr
17364 +#name: lda_nopic
17365 +
17366 +.*: +file format .*
17367 +
17368 +Disassembly of section \.text:
17369 +
17370 +00000000 <lda_test>:
17371 +       0:      f2 c8 00 00     sub r8,r9,0
17372 +
17373 +00000004 <far_negative>:
17374 +       4:      f6 ca 00 00     sub r10,r11,0
17375 +       ...
17376 +    8000:      fe c0 7f fc     sub r0,pc,32764
17377 +    8004:      48 31           lddpc r1,8010 <far_negative\+0x800c>
17378 +    8006:      48 42           lddpc r2,8014 <far_negative\+0x8010>
17379 +    8008:      48 43           lddpc r3,8018 <far_negative\+0x8014>
17380 +    800a:      48 54           lddpc r4,801c <far_negative\+0x8018>
17381 +    800c:      fe c5 80 04     sub r5,pc,-32764
17382 +       ...
17383 +                       8010: R_AVR32_32_CPENT  \.text
17384 +                       8014: R_AVR32_32_CPENT  \.data
17385 +                       8018: R_AVR32_32_CPENT  undefined
17386 +                       801c: R_AVR32_32_CPENT  \.text\+0x1001c
17387 +
17388 +00010008 <far_positive>:
17389 +   10008:      fa cc 00 00     sub r12,sp,0
17390 +       ...
17391 +0001001c <toofar_positive>:
17392 +   1001c:      fe ce 00 00     sub lr,pc,0
17393 --- /dev/null
17394 +++ b/gas/testsuite/gas/avr32/lda_nopic_linkrelax.d
17395 @@ -0,0 +1,41 @@
17396 +#source: lda.s
17397 +#as: --linkrelax
17398 +#objdump: -dr
17399 +#name: lda_nopic_linkrelax
17400 +
17401 +.*: +file format .*
17402 +
17403 +Disassembly of section \.text:
17404 +
17405 +00000000 <lda_test>:
17406 +       0:      f2 c8 00 00     sub r8,r9,0
17407 +
17408 +00000004 <far_negative>:
17409 +       4:      f6 ca 00 00     sub r10,r11,0
17410 +       \.\.\.
17411 +    8000:      48 00           lddpc r0,8000 <far_negative\+0x7ffc>
17412 +                       8000: R_AVR32_9W_CP     \.text\+0x800c
17413 +    8002:      48 01           lddpc r1,8000 <far_negative\+0x7ffc>
17414 +                       8002: R_AVR32_9W_CP     \.text\+0x8010
17415 +    8004:      48 02           lddpc r2,8004 <far_negative\+0x8000>
17416 +                       8004: R_AVR32_9W_CP     \.text\+0x8014
17417 +    8006:      48 03           lddpc r3,8004 <far_negative\+0x8000>
17418 +                       8006: R_AVR32_9W_CP     \.text\+0x8018
17419 +    8008:      48 04           lddpc r4,8008 <far_negative\+0x8004>
17420 +                       8008: R_AVR32_9W_CP     \.text\+0x801c
17421 +    800a:      48 05           lddpc r5,8008 <far_negative\+0x8004>
17422 +                       800a: R_AVR32_9W_CP     \.text\+0x8020
17423 +       \.\.\.
17424 +                       800c: R_AVR32_ALIGN     \*ABS\*\+0x2
17425 +                       800c: R_AVR32_32_CPENT  \.text\+0x4
17426 +                       8010: R_AVR32_32_CPENT  \.text
17427 +                       8014: R_AVR32_32_CPENT  \.data
17428 +                       8018: R_AVR32_32_CPENT  undefined
17429 +                       801c: R_AVR32_32_CPENT  \.text\+0x10020
17430 +                       8020: R_AVR32_32_CPENT  \.text\+0x1000c
17431 +
17432 +0001000c <far_positive>:
17433 +   1000c:      fa cc 00 00     sub r12,sp,0
17434 +       \.\.\.
17435 +00010020 <toofar_positive>:
17436 +   10020:      fe ce 00 00     sub lr,pc,0
17437 --- /dev/null
17438 +++ b/gas/testsuite/gas/avr32/lda_pic.d
17439 @@ -0,0 +1,32 @@
17440 +#source: lda.s
17441 +#as: --pic
17442 +#objdump: -dr
17443 +#name: lda_pic
17444 +
17445 +.*: +file format .*
17446 +
17447 +Disassembly of section \.text:
17448 +
17449 +00000000 <lda_test>:
17450 +       0:      f2 c8 00 00     sub r8,r9,0
17451 +
17452 +00000004 <far_negative>:
17453 +       4:      f6 ca 00 00     sub r10,r11,0
17454 +       ...
17455 +    8000:      fe c0 7f fc     sub r0,pc,32764
17456 +    8004:      ec f1 00 00     ld.w r1,r6\[0\]
17457 +                       8004: R_AVR32_GOT16S    toofar_negative
17458 +    8008:      ec f2 00 00     ld.w r2,r6\[0\]
17459 +                       8008: R_AVR32_GOT16S    different_section
17460 +    800c:      ec f3 00 00     ld.w r3,r6\[0\]
17461 +                       800c: R_AVR32_GOT16S    undefined
17462 +    8010:      ec f4 00 00     ld.w r4,r6\[0\]
17463 +                       8010: R_AVR32_GOT16S    toofar_positive
17464 +    8014:      fe c5 80 14     sub r5,pc,-32748
17465 +       ...
17466 +
17467 +00010000 <far_positive>:
17468 +   10000:      fa cc 00 00     sub r12,sp,0
17469 +       ...
17470 +00010014 <toofar_positive>:
17471 +   10014:      fe ce 00 00     sub lr,pc,0
17472 --- /dev/null
17473 +++ b/gas/testsuite/gas/avr32/lda_pic_linkrelax.d
17474 @@ -0,0 +1,40 @@
17475 +#source: lda.s
17476 +#as: --pic --linkrelax
17477 +#objdump: -dr
17478 +#name: lda_pic_linkrelax
17479 +
17480 +.*: +file format .*
17481 +
17482 +Disassembly of section \.text:
17483 +
17484 +00000000 <lda_test>:
17485 +       0:      f2 c8 00 00     sub r8,r9,0
17486 +
17487 +00000004 <far_negative>:
17488 +       4:      f6 ca 00 00     sub r10,r11,0
17489 +       ...
17490 +    8000:      e0 60 00 00     mov r0,0
17491 +                       8000: R_AVR32_LDA_GOT   far_negative
17492 +    8004:      ec 00 03 20     ld\.w r0,r6\[r0<<0x2\]
17493 +    8008:      e0 61 00 00     mov r1,0
17494 +                       8008: R_AVR32_LDA_GOT   toofar_negative
17495 +    800c:      ec 01 03 21     ld\.w r1,r6\[r1<<0x2\]
17496 +    8010:      e0 62 00 00     mov r2,0
17497 +                       8010: R_AVR32_LDA_GOT   different_section
17498 +    8014:      ec 02 03 22     ld\.w r2,r6\[r2<<0x2\]
17499 +    8018:      e0 63 00 00     mov r3,0
17500 +                       8018: R_AVR32_LDA_GOT   undefined
17501 +    801c:      ec 03 03 23     ld\.w r3,r6\[r3<<0x2\]
17502 +    8020:      e0 64 00 00     mov r4,0
17503 +                       8020: R_AVR32_LDA_GOT   toofar_positive
17504 +    8024:      ec 04 03 24     ld\.w r4,r6\[r4<<0x2\]
17505 +    8028:      e0 65 00 00     mov r5,0
17506 +                       8028: R_AVR32_LDA_GOT   far_positive
17507 +    802c:      ec 05 03 25     ld\.w r5,r6\[r5<<0x2\]
17508 +       ...
17509 +
17510 +00010018 <far_positive>:
17511 +   10018:      fa cc 00 00     sub r12,sp,0
17512 +       ...
17513 +0001002c <toofar_positive>:
17514 +   1002c:      fe ce 00 00     sub lr,pc,0
17515 --- /dev/null
17516 +++ b/gas/testsuite/gas/avr32/lda.s
17517 @@ -0,0 +1,30 @@
17518 +
17519 +       .text
17520 +       .global lda_test
17521 +lda_test:
17522 +toofar_negative:
17523 +       sub     r8, r9, 0
17524 +far_negative:
17525 +       sub     r10, r11, 0
17526 +
17527 +       .fill   32760, 1, 0x00
17528 +
17529 +       lda.w   r0, far_negative
17530 +       lda.w   r1, toofar_negative
17531 +       lda.w   r2, different_section
17532 +       lda.w   r3, undefined
17533 +       lda.w   r4, toofar_positive
17534 +       lda.w   r5, far_positive
17535 +
17536 +       .cpool
17537 +
17538 +       .fill   32744, 1, 0x00
17539 +far_positive:
17540 +       sub     r12, sp, 0
17541 +       .fill   16, 1, 0x00
17542 +toofar_positive:
17543 +       sub     lr, pc, 0
17544 +
17545 +       .data
17546 +different_section:
17547 +       .long   0x12345678
17548 --- /dev/null
17549 +++ b/gas/testsuite/gas/avr32/pcrel.d
17550 @@ -0,0 +1,64 @@
17551 +#as:
17552 +#objdump: -dr
17553 +#name: pcrel
17554 +
17555 +.*: +file format .*
17556 +
17557 +Disassembly of section \.text:
17558 +
17559 +00000000 <test_rjmp>:
17560 +   0:  d7 03           nop
17561 +   2:  c0 28           rjmp 6 <test_rjmp\+0x6>
17562 +   4:  d7 03           nop
17563 +   6:  e0 8f 00 00     bral 6 <test_rjmp\+0x6>
17564 +                       6: R_AVR32_22H_PCREL    extsym10
17565 +
17566 +0000000a <test_rcall>:
17567 +   a:  d7 03           nop
17568 +0000000c <test_rcall2>:
17569 +   c:  c0 2c           rcall 10 <test_rcall2\+0x4>
17570 +   e:  d7 03           nop
17571 +  10:  e0 a0 00 00     rcall 10 <test_rcall2\+0x4>
17572 +                       10: R_AVR32_22H_PCREL   extsym21
17573 +
17574 +00000014 <test_branch>:
17575 +  14:  c0 31           brne 1a <test_branch\+0x6>
17576 +  16:  e0 8f 00 00     bral 16 <test_branch\+0x2>
17577 +                       16: R_AVR32_22H_PCREL   test_branch
17578 +  1a:  e0 80 00 00     breq 1a <test_branch\+0x6>
17579 +                       1a: R_AVR32_22H_PCREL   extsym21
17580 +
17581 +0000001e <test_lddpc>:
17582 +  1e:  48 30           lddpc r0,28 <sym1>
17583 +  20:  48 20           lddpc r0,28 <sym1>
17584 +  22:  fe f0 00 00     ld.w r0,pc\[0\]
17585 +                       22: R_AVR32_16B_PCREL   extsym16
17586 +       \.\.\.
17587 +
17588 +00000028 <sym1>:
17589 +  28:  d7 03           nop
17590 +  2a:  d7 03           nop
17591 +
17592 +0000002c <test_local>:
17593 +  2c:  48 20           lddpc r0,34 <test_local\+0x8>
17594 +  2e:  48 30           lddpc r0,38 <test_local\+0xc>
17595 +  30:  48 20           lddpc r0,38 <test_local\+0xc>
17596 +  32:  00 00           add r0,r0
17597 +  34:  d7 03           nop
17598 +  36:  d7 03           nop
17599 +  38:  d7 03           nop
17600 +  3a:  d7 03           nop
17601 +
17602 +Disassembly of section \.text\.init:
17603 +
17604 +00000000 <test_inter_section>:
17605 +   0:  e0 a0 .. ..     rcall [0-9a-f]+ <.*>
17606 +                       0: R_AVR32_22H_PCREL    test_rcall
17607 +   4:  d7 03           nop
17608 +   6:  e0 a0 .. ..     rcall [0-9a-f]+ <.*>
17609 +                       6: R_AVR32_22H_PCREL    test_rcall
17610 +   a:  e0 a0 .. ..     rcall [0-9a-z]+ <.*>
17611 +                       a: R_AVR32_22H_PCREL    \.text\+0xc
17612 +   e:  d7 03           nop
17613 +  10:  e0 a0 .. ..     rcall [0-9a-f]+ <.*>
17614 +                       10: R_AVR32_22H_PCREL   \.text\+0xc
17615 --- /dev/null
17616 +++ b/gas/testsuite/gas/avr32/pcrel.s
17617 @@ -0,0 +1,57 @@
17618 +
17619 +        .text
17620 +        .global test_rjmp
17621 +test_rjmp:
17622 +        nop
17623 +        rjmp    0f
17624 +        nop
17625 +0:      rjmp    extsym10
17626 +
17627 +        .global test_rcall
17628 +test_rcall:
17629 +        nop
17630 +test_rcall2:
17631 +        rcall   0f
17632 +        nop
17633 +0:      rcall   extsym21
17634 +
17635 +        .global test_branch
17636 +test_branch:
17637 +        brne    0f
17638 +       /* This will generate a reloc since test_branch is global */
17639 +        bral    test_branch
17640 +0:     breq    extsym21
17641 +
17642 +        .global test_lddpc
17643 +test_lddpc:
17644 +        lddpc   r0,sym1
17645 +        lddpc   r0,sym1
17646 +        lddpc   r0,extsym16
17647 +
17648 +        .align 2
17649 +sym1:   nop
17650 +        nop
17651 +
17652 +       .global test_local
17653 +test_local:
17654 +       lddpc   r0, .LC1
17655 +       lddpc   r0, .LC2
17656 +       lddpc   r0, .LC1 + 0x4
17657 +
17658 +       .align  2
17659 +.LC1:
17660 +       nop
17661 +       nop
17662 +.LC2:
17663 +       nop
17664 +       nop
17665 +
17666 +       .section .text.init,"ax"
17667 +       .global test_inter_section
17668 +test_inter_section:
17669 +       rcall   test_rcall
17670 +       nop
17671 +       rcall   test_rcall
17672 +       rcall   test_rcall2
17673 +       nop
17674 +       rcall   test_rcall2
17675 --- /dev/null
17676 +++ b/gas/testsuite/gas/avr32/pico.d
17677 @@ -0,0 +1,149 @@
17678 +#as:
17679 +#objdump: -dr
17680 +#name: pico
17681 +
17682 +.*: +file format .*
17683 +
17684 +Disassembly of section \.text:
17685 +
17686 +[0-9a-f]* <picosvmac>:
17687 + *[0-9a-f]*:   e1 a6 20 00     cop cp1,cr0,cr0,cr0,0xc
17688 + *[0-9a-f]*:   e1 a7 2b bb     cop cp1,cr11,cr11,cr11,0xe
17689 + *[0-9a-f]*:   e1 a6 3a 05     cop cp1,cr10,cr0,cr5,0xd
17690 + *[0-9a-f]*:   e1 a7 36 90     cop cp1,cr6,cr9,cr0,0xf
17691 +
17692 +[0-9a-f]* <picosvmul>:
17693 + *[0-9a-f]*:   e1 a4 20 00     cop cp1,cr0,cr0,cr0,0x8
17694 + *[0-9a-f]*:   e1 a5 2b bb     cop cp1,cr11,cr11,cr11,0xa
17695 + *[0-9a-f]*:   e1 a4 3a 05     cop cp1,cr10,cr0,cr5,0x9
17696 + *[0-9a-f]*:   e1 a5 36 90     cop cp1,cr6,cr9,cr0,0xb
17697 +
17698 +[0-9a-f]* <picovmac>:
17699 + *[0-9a-f]*:   e1 a2 20 00     cop cp1,cr0,cr0,cr0,0x4
17700 + *[0-9a-f]*:   e1 a3 2b bb     cop cp1,cr11,cr11,cr11,0x6
17701 + *[0-9a-f]*:   e1 a2 3a 05     cop cp1,cr10,cr0,cr5,0x5
17702 + *[0-9a-f]*:   e1 a3 36 90     cop cp1,cr6,cr9,cr0,0x7
17703 +
17704 +[0-9a-f]* <picovmul>:
17705 + *[0-9a-f]*:   e1 a0 20 00     cop cp1,cr0,cr0,cr0,0x0
17706 + *[0-9a-f]*:   e1 a1 2b bb     cop cp1,cr11,cr11,cr11,0x2
17707 + *[0-9a-f]*:   e1 a0 3a 05     cop cp1,cr10,cr0,cr5,0x1
17708 + *[0-9a-f]*:   e1 a1 36 90     cop cp1,cr6,cr9,cr0,0x3
17709 +
17710 +[0-9a-f]* <picold_d>:
17711 + *[0-9a-f]*:   e9 af 3e ff     ldc\.d cp1,cr14,pc\[0x3fc\]
17712 + *[0-9a-f]*:   e9 a0 30 ff     ldc\.d cp1,cr0,r0\[0x3fc\]
17713 + *[0-9a-f]*:   e9 a0 30 00     ldc\.d cp1,cr0,r0\[0x0\]
17714 + *[0-9a-f]*:   ef a8 26 50     ldc\.d cp1,cr6,--r8
17715 + *[0-9a-f]*:   ef a7 28 50     ldc\.d cp1,cr8,--r7
17716 + *[0-9a-f]*:   ef aa 32 65     ldc\.d cp1,cr2,r10\[r5<<0x2\]
17717 + *[0-9a-f]*:   ef a3 3c 46     ldc\.d cp1,cr12,r3\[r6\]
17718 +
17719 +[0-9a-f]* <picold_w>:
17720 + *[0-9a-f]*:   e9 af 2f ff     ldc\.w cp1,cr15,pc\[0x3fc\]
17721 + *[0-9a-f]*:   e9 a0 20 ff     ldc\.w cp1,cr0,r0\[0x3fc\]
17722 + *[0-9a-f]*:   e9 a0 20 00     ldc\.w cp1,cr0,r0\[0x0\]
17723 + *[0-9a-f]*:   ef a8 27 40     ldc\.w cp1,cr7,--r8
17724 + *[0-9a-f]*:   ef a7 28 40     ldc\.w cp1,cr8,--r7
17725 + *[0-9a-f]*:   ef aa 31 25     ldc\.w cp1,cr1,r10\[r5<<0x2\]
17726 + *[0-9a-f]*:   ef a3 3d 06     ldc\.w cp1,cr13,r3\[r6\]
17727 +
17728 +[0-9a-f]* <picoldm_d>:
17729 + *[0-9a-f]*:   ed af 24 ff     ldcm\.d cp1,pc,cr0-cr15
17730 + *[0-9a-f]*:   ed a0 24 01     ldcm\.d cp1,r0,cr0-cr1
17731 + *[0-9a-f]*:   ed a7 24 80     ldcm\.d cp1,r7,cr14-cr15
17732 + *[0-9a-f]*:   ed a8 24 7f     ldcm\.d cp1,r8,cr0-cr13
17733 +
17734 +[0-9a-f]* <picoldm_d_pu>:
17735 + *[0-9a-f]*:   ed af 34 ff     ldcm\.d cp1,pc\+\+,cr0-cr15
17736 + *[0-9a-f]*:   ed a0 34 01     ldcm\.d cp1,r0\+\+,cr0-cr1
17737 + *[0-9a-f]*:   ed a7 34 80     ldcm\.d cp1,r7\+\+,cr14-cr15
17738 + *[0-9a-f]*:   ed a8 34 7f     ldcm\.d cp1,r8\+\+,cr0-cr13
17739 +
17740 +[0-9a-f]* <picoldm_w>:
17741 + *[0-9a-f]*:   ed af 20 ff     ldcm\.w cp1,pc,cr0-cr7
17742 + *[0-9a-f]*:   ed a0 20 01     ldcm\.w cp1,r0,cr0
17743 + *[0-9a-f]*:   ed a7 20 80     ldcm\.w cp1,r7,cr7
17744 + *[0-9a-f]*:   ed a8 20 7f     ldcm\.w cp1,r8,cr0-cr6
17745 + *[0-9a-f]*:   ed af 21 ff     ldcm\.w cp1,pc,cr8-cr15
17746 + *[0-9a-f]*:   ed a0 21 01     ldcm\.w cp1,r0,cr8
17747 + *[0-9a-f]*:   ed a7 21 80     ldcm\.w cp1,r7,cr15
17748 + *[0-9a-f]*:   ed a8 21 7f     ldcm\.w cp1,r8,cr8-cr14
17749 +
17750 +[0-9a-f]* <picoldm_w_pu>:
17751 + *[0-9a-f]*:   ed af 30 ff     ldcm\.w cp1,pc\+\+,cr0-cr7
17752 + *[0-9a-f]*:   ed a0 30 01     ldcm\.w cp1,r0\+\+,cr0
17753 + *[0-9a-f]*:   ed a7 30 80     ldcm\.w cp1,r7\+\+,cr7
17754 + *[0-9a-f]*:   ed a8 30 7f     ldcm\.w cp1,r8\+\+,cr0-cr6
17755 + *[0-9a-f]*:   ed af 31 ff     ldcm\.w cp1,pc\+\+,cr8-cr15
17756 + *[0-9a-f]*:   ed a0 31 01     ldcm\.w cp1,r0\+\+,cr8
17757 + *[0-9a-f]*:   ed a7 31 80     ldcm\.w cp1,r7\+\+,cr15
17758 + *[0-9a-f]*:   ed a8 31 7f     ldcm\.w cp1,r8\+\+,cr8-cr14
17759 +
17760 +[0-9a-f]* <picomv_d>:
17761 + *[0-9a-f]*:   ef ae 2e 30     mvrc\.d cp1,cr14,lr
17762 + *[0-9a-f]*:   ef a0 20 30     mvrc\.d cp1,cr0,r0
17763 + *[0-9a-f]*:   ef a8 26 30     mvrc\.d cp1,cr6,r8
17764 + *[0-9a-f]*:   ef a6 28 30     mvrc\.d cp1,cr8,r6
17765 + *[0-9a-f]*:   ef ae 2e 10     mvcr\.d cp1,lr,cr14
17766 + *[0-9a-f]*:   ef a0 20 10     mvcr\.d cp1,r0,cr0
17767 + *[0-9a-f]*:   ef a8 26 10     mvcr\.d cp1,r8,cr6
17768 + *[0-9a-f]*:   ef a6 28 10     mvcr\.d cp1,r6,cr8
17769 +
17770 +[0-9a-f]* <picomv_w>:
17771 + *[0-9a-f]*:   ef af 2f 20     mvrc\.w cp1,cr15,pc
17772 + *[0-9a-f]*:   ef a0 20 20     mvrc\.w cp1,cr0,r0
17773 + *[0-9a-f]*:   ef a8 27 20     mvrc\.w cp1,cr7,r8
17774 + *[0-9a-f]*:   ef a7 28 20     mvrc\.w cp1,cr8,r7
17775 + *[0-9a-f]*:   ef af 2f 00     mvcr\.w cp1,pc,cr15
17776 + *[0-9a-f]*:   ef a0 20 00     mvcr\.w cp1,r0,cr0
17777 + *[0-9a-f]*:   ef a8 27 00     mvcr\.w cp1,r8,cr7
17778 + *[0-9a-f]*:   ef a7 28 00     mvcr\.w cp1,r7,cr8
17779 +
17780 +[0-9a-f]* <picost_d>:
17781 + *[0-9a-f]*:   eb af 3e ff     stc\.d cp1,pc\[0x3fc\],cr14
17782 + *[0-9a-f]*:   eb a0 30 00     stc\.d cp1,r0\[0x0\],cr0
17783 + *[0-9a-f]*:   ef a8 26 70     stc\.d cp1,r8\+\+,cr6
17784 + *[0-9a-f]*:   ef a7 28 70     stc\.d cp1,r7\+\+,cr8
17785 + *[0-9a-f]*:   ef aa 32 e5     stc\.d cp1,r10\[r5<<0x2\],cr2
17786 + *[0-9a-f]*:   ef a3 3c c6     stc\.d cp1,r3\[r6\],cr12
17787 +
17788 +[0-9a-f]* <picost_w>:
17789 + *[0-9a-f]*:   eb af 2f ff     stc\.w cp1,pc\[0x3fc\],cr15
17790 + *[0-9a-f]*:   eb a0 20 00     stc\.w cp1,r0\[0x0\],cr0
17791 + *[0-9a-f]*:   ef a8 27 60     stc\.w cp1,r8\+\+,cr7
17792 + *[0-9a-f]*:   ef a7 28 60     stc\.w cp1,r7\+\+,cr8
17793 + *[0-9a-f]*:   ef aa 31 a5     stc\.w cp1,r10\[r5<<0x2\],cr1
17794 + *[0-9a-f]*:   ef a3 3d 86     stc\.w cp1,r3\[r6\],cr13
17795 +
17796 +[0-9a-f]* <picostm_d>:
17797 + *[0-9a-f]*:   ed af 25 ff     stcm\.d cp1,pc,cr0-cr15
17798 + *[0-9a-f]*:   ed a0 25 01     stcm\.d cp1,r0,cr0-cr1
17799 + *[0-9a-f]*:   ed a7 25 80     stcm\.d cp1,r7,cr14-cr15
17800 + *[0-9a-f]*:   ed a8 25 7f     stcm\.d cp1,r8,cr0-cr13
17801 +
17802 +[0-9a-f]* <picostm_d_pu>:
17803 + *[0-9a-f]*:   ed af 35 ff     stcm\.d cp1,--pc,cr0-cr15
17804 + *[0-9a-f]*:   ed a0 35 01     stcm\.d cp1,--r0,cr0-cr1
17805 + *[0-9a-f]*:   ed a7 35 80     stcm\.d cp1,--r7,cr14-cr15
17806 + *[0-9a-f]*:   ed a8 35 7f     stcm\.d cp1,--r8,cr0-cr13
17807 +
17808 +[0-9a-f]* <picostm_w>:
17809 + *[0-9a-f]*:   ed af 22 ff     stcm\.w cp1,pc,cr0-cr7
17810 + *[0-9a-f]*:   ed a0 22 01     stcm\.w cp1,r0,cr0
17811 + *[0-9a-f]*:   ed a7 22 80     stcm\.w cp1,r7,cr7
17812 + *[0-9a-f]*:   ed a8 22 7f     stcm\.w cp1,r8,cr0-cr6
17813 + *[0-9a-f]*:   ed af 23 ff     stcm\.w cp1,pc,cr8-cr15
17814 + *[0-9a-f]*:   ed a0 23 01     stcm\.w cp1,r0,cr8
17815 + *[0-9a-f]*:   ed a7 23 80     stcm\.w cp1,r7,cr15
17816 + *[0-9a-f]*:   ed a8 23 7f     stcm\.w cp1,r8,cr8-cr14
17817 +
17818 +[0-9a-f]* <picostm_w_pu>:
17819 + *[0-9a-f]*:   ed af 32 ff     stcm\.w cp1,--pc,cr0-cr7
17820 + *[0-9a-f]*:   ed a0 32 01     stcm\.w cp1,--r0,cr0
17821 + *[0-9a-f]*:   ed a7 32 80     stcm\.w cp1,--r7,cr7
17822 + *[0-9a-f]*:   ed a8 32 7f     stcm\.w cp1,--r8,cr0-cr6
17823 + *[0-9a-f]*:   ed af 33 ff     stcm\.w cp1,--pc,cr8-cr15
17824 + *[0-9a-f]*:   ed a0 33 01     stcm\.w cp1,--r0,cr8
17825 + *[0-9a-f]*:   ed a7 33 80     stcm\.w cp1,--r7,cr15
17826 + *[0-9a-f]*:   ed a8 33 7f     stcm\.w cp1,--r8,cr8-cr14
17827 --- /dev/null
17828 +++ b/gas/testsuite/gas/avr32/pico.s
17829 @@ -0,0 +1,144 @@
17830 +
17831 +       .text
17832 +       .global picosvmac
17833 +picosvmac:
17834 +       picosvmac       out0, in0, in0, in0
17835 +       picosvmac       out2, in11, in11, in11
17836 +       picosvmac       out1, in10, in0, in5
17837 +       picosvmac       out3, in6, in9, in0
17838 +       .global picosvmul
17839 +picosvmul:
17840 +       picosvmul       out0, in0, in0, in0
17841 +       picosvmul       out2, in11, in11, in11
17842 +       picosvmul       out1, in10, in0, in5
17843 +       picosvmul       out3, in6, in9, in0
17844 +       .global picovmac
17845 +picovmac:
17846 +       picovmac        out0, in0, in0, in0
17847 +       picovmac        out2, in11, in11, in11
17848 +       picovmac        out1, in10, in0, in5
17849 +       picovmac        out3, in6, in9, in0
17850 +       .global picovmul
17851 +picovmul:
17852 +       picovmul        out0, in0, in0, in0
17853 +       picovmul        out2, in11, in11, in11
17854 +       picovmul        out1, in10, in0, in5
17855 +       picovmul        out3, in6, in9, in0
17856 +       .global picold_d
17857 +picold_d:
17858 +       picold.d        vmu2_out, pc[1020]
17859 +       picold.d        inpix2, r0[1020]
17860 +       picold.d        inpix2, r0[0]
17861 +       picold.d        coeff0_a, --r8
17862 +       picold.d        coeff1_a, --r7
17863 +       picold.d        inpix0, r10[r5 << 2]
17864 +       picold.d        vmu0_out, r3[r6 << 0]
17865 +       .global picold_w
17866 +picold_w:
17867 +       picold.w        config, pc[1020]
17868 +       picold.w        inpix2, r0[1020]
17869 +       picold.w        inpix2, r0[0]
17870 +       picold.w        coeff0_b, --r8
17871 +       picold.w        coeff1_a, --r7
17872 +       picold.w        inpix1, r10[r5 << 2]
17873 +       picold.w        vmu1_out, r3[r6 << 0]
17874 +       .global picoldm_d
17875 +picoldm_d:
17876 +       picoldm.d       pc, inpix2-config
17877 +       picoldm.d       r0, inpix2, inpix1
17878 +       picoldm.d       r7, vmu2_out, config
17879 +       picoldm.d       r8, inpix2-vmu1_out
17880 +       .global picoldm_d_pu
17881 +picoldm_d_pu:
17882 +       picoldm.d       pc++, inpix2, inpix1, inpix0, outpix2, outpix1, outpix0, coeff0_a, coeff0_b, coeff1_a, coeff1_b, coeff2_a, coeff2_b, vmu0_out, vmu1_out, vmu2_out, config
17883 +       picoldm.d       r0++, inpix2, inpix1
17884 +       picoldm.d       r7++, vmu2_out, config
17885 +       picoldm.d       r8++, inpix2, inpix1, inpix0, outpix2, outpix1, outpix0, coeff0_a, coeff0_b, coeff1_a, coeff1_b, coeff2_a, coeff2_b, vmu0_out, vmu1_out
17886 +       .global picoldm_w
17887 +picoldm_w:
17888 +       picoldm.w       pc, inpix2-coeff0_b
17889 +       picoldm.w       r0, inpix2
17890 +       picoldm.w       r7, coeff0_b
17891 +       picoldm.w       r8, inpix2-coeff0_a
17892 +       picoldm.w       pc, coeff1_a-config
17893 +       picoldm.w       r0, coeff1_a
17894 +       picoldm.w       r7, config
17895 +       picoldm.w       r8, coeff1_a-vmu2_out
17896 +       .global picoldm_w_pu
17897 +picoldm_w_pu:
17898 +       picoldm.w       pc++, inpix2-coeff0_b
17899 +       picoldm.w       r0++, inpix2
17900 +       picoldm.w       r7++, coeff0_b
17901 +       picoldm.w       r8++, inpix2-coeff0_a
17902 +       picoldm.w       pc++, coeff1_a-config
17903 +       picoldm.w       r0++, coeff1_a
17904 +       picoldm.w       r7++, config
17905 +       picoldm.w       r8++, coeff1_a-vmu2_out
17906 +       .global picomv_d
17907 +picomv_d:
17908 +       picomv.d        vmu2_out, lr
17909 +       picomv.d        inpix2, r0
17910 +       picomv.d        coeff0_a, r8
17911 +       picomv.d        coeff1_a, r6
17912 +       picomv.d        pc, vmu2_out
17913 +       picomv.d        r0, inpix2
17914 +       picomv.d        r8, coeff0_a
17915 +       picomv.d        r6, coeff1_a
17916 +       .global picomv_w
17917 +picomv_w:
17918 +       picomv.w        config, pc
17919 +       picomv.w        inpix2, r0
17920 +       picomv.w        coeff0_b, r8
17921 +       picomv.w        coeff1_a, r7
17922 +       picomv.w        pc, config
17923 +       picomv.w        r0, inpix2
17924 +       picomv.w        r8, coeff0_b
17925 +       picomv.w        r7, coeff1_a
17926 +       .global picost_d
17927 +picost_d:
17928 +       picost.d        pc[1020], vmu2_out
17929 +       picost.d        r0[0], inpix2
17930 +       picost.d        r8++, coeff0_a
17931 +       picost.d        r7++, coeff1_a
17932 +       picost.d        r10[r5 << 2], inpix0
17933 +       picost.d        r3[r6 << 0], vmu0_out
17934 +       .global picost_w
17935 +picost_w:
17936 +       picost.w        pc[1020], config
17937 +       picost.w        r0[0], inpix2
17938 +       picost.w        r8++, coeff0_b
17939 +       picost.w        r7++, coeff1_a
17940 +       picost.w        r10[r5 << 2], inpix1
17941 +       picost.w        r3[r6 << 0], vmu1_out
17942 +       .global picostm_d
17943 +picostm_d:
17944 +       picostm.d       pc, inpix2-config
17945 +       picostm.d       r0, inpix2, inpix1
17946 +       picostm.d       r7, vmu2_out, config
17947 +       picostm.d       r8, inpix2-vmu1_out
17948 +       .global picostm_d_pu
17949 +picostm_d_pu:
17950 +       picostm.d       --pc, inpix2, inpix1, inpix0, outpix2, outpix1, outpix0, coeff0_a, coeff0_b, coeff1_a, coeff1_b, coeff2_a, coeff2_b, vmu0_out, vmu1_out, vmu2_out, config
17951 +       picostm.d       --r0, inpix2, inpix1
17952 +       picostm.d       --r7, vmu2_out, config
17953 +       picostm.d       --r8, inpix2, inpix1, inpix0, outpix2, outpix1, outpix0, coeff0_a, coeff0_b, coeff1_a, coeff1_b, coeff2_a, coeff2_b, vmu0_out, vmu1_out
17954 +       .global picostm_w
17955 +picostm_w:
17956 +       picostm.w       pc, inpix2-coeff0_b
17957 +       picostm.w       r0, inpix2
17958 +       picostm.w       r7, coeff0_b
17959 +       picostm.w       r8, inpix2-coeff0_a
17960 +       picostm.w       pc, coeff1_a-config
17961 +       picostm.w       r0, coeff1_a
17962 +       picostm.w       r7, config
17963 +       picostm.w       r8, coeff1_a-vmu2_out
17964 +       .global picostm_w_pu
17965 +picostm_w_pu:
17966 +       picostm.w       --pc, inpix2-coeff0_b
17967 +       picostm.w       --r0, inpix2
17968 +       picostm.w       --r7, coeff0_b
17969 +       picostm.w       --r8, inpix2-coeff0_a
17970 +       picostm.w       --pc, coeff1_a-config
17971 +       picostm.w       --r0, coeff1_a
17972 +       picostm.w       --r7, config
17973 +       picostm.w       --r8, coeff1_a-vmu2_out
17974 --- /dev/null
17975 +++ b/gas/testsuite/gas/avr32/pic_reloc.d
17976 @@ -0,0 +1,27 @@
17977 +#as:
17978 +#objdump: -dr
17979 +#name: pic_reloc
17980 +
17981 +.*: +file format .*
17982 +
17983 +Disassembly of section \.text:
17984 +
17985 +00000000 <mcall_got>:
17986 +   0:  f0 16 00 00     mcall r6\[0\]
17987 +                       0: R_AVR32_GOT18SW      extfunc
17988 +   4:  f0 16 00 00     mcall r6\[0\]
17989 +                       4: R_AVR32_GOT18SW      \.L1
17990 +   8:  f0 16 00 00     mcall r6\[0\]
17991 +                       8: R_AVR32_GOT18SW      \.L2
17992 +   c:  f0 16 00 00     mcall r6\[0\]
17993 +                       c: R_AVR32_GOT18SW      mcall_got
17994 +
17995 +00000010 <ldw_got>:
17996 +  10:  ec f0 00 00     ld.w r0,r6\[0\]
17997 +                       10: R_AVR32_GOT16S      extvar
17998 +  14:  ec f0 00 00     ld.w r0,r6\[0\]
17999 +                       14: R_AVR32_GOT16S      \.L3
18000 +  18:  ec f0 00 00     ld.w r0,r6\[0\]
18001 +                       18: R_AVR32_GOT16S      \.L4
18002 +  1c:  ec f0 00 00     ld.w r0,r6\[0\]
18003 +                       1c: R_AVR32_GOT16S      ldw_got
18004 --- /dev/null
18005 +++ b/gas/testsuite/gas/avr32/pic_reloc.s
18006 @@ -0,0 +1,18 @@
18007 +
18008 +       .text
18009 +       .global mcall_got
18010 +mcall_got:
18011 +.L1:
18012 +       mcall   r6[extfunc@got]
18013 +       mcall   r6[.L1@got]
18014 +       mcall   r6[.L2@got]
18015 +       mcall   r6[mcall_got@got]
18016 +.L2:
18017 +
18018 +       .global ldw_got
18019 +ldw_got:
18020 +.L3:   ld.w    r0,r6[extvar@got]
18021 +       ld.w    r0,r6[.L3@got]
18022 +       ld.w    r0,r6[.L4@got]
18023 +       ld.w    r0,r6[ldw_got@got]
18024 +.L4:
18025 --- /dev/null
18026 +++ b/gas/testsuite/gas/avr32/symdiff.d
18027 @@ -0,0 +1,24 @@
18028 +#source: symdiff.s
18029 +#as:
18030 +#objdump: -dr
18031 +#name: symdiff
18032 +
18033 +.*: +file format .*
18034 +
18035 +Disassembly of section \.text:
18036 +
18037 +00000000 <diff32>:
18038 +   0:  00 00           add r0,r0
18039 +   2:  00 04           add r4,r0
18040 +
18041 +00000004 <diff16>:
18042 +   4:  00 04           add r4,r0
18043 +
18044 +00000006 <diff8>:
18045 +   6:  04 00           add r0,r2
18046 +
18047 +00000008 <symdiff_test>:
18048 +   8:  d7 03           nop
18049 +   a:  d7 03           nop
18050 +   c:  d7 03           nop
18051 +   e:  d7 03           nop
18052 --- /dev/null
18053 +++ b/gas/testsuite/gas/avr32/symdiff_linkrelax.d
18054 @@ -0,0 +1,28 @@
18055 +#source: symdiff.s
18056 +#as: --linkrelax
18057 +#objdump: -dr
18058 +#name: symdiff_linkrelax
18059 +
18060 +.*: +file format .*
18061 +
18062 +Disassembly of section \.text:
18063 +
18064 +00000000 <diff32>:
18065 +   0:  00 00           add r0,r0
18066 +                       0: R_AVR32_DIFF32       \.text\+0xa
18067 +   2:  00 04           add r4,r0
18068 +
18069 +00000004 <diff16>:
18070 +   4:  00 04           add r4,r0
18071 +                       4: R_AVR32_DIFF16       \.text\+0xa
18072 +
18073 +00000006 <diff8>:
18074 +   6:  04 00           add r0,r2
18075 +                       6: R_AVR32_DIFF8        \.text\+0xa
18076 +                       7: R_AVR32_ALIGN        \*ABS\*\+0x1
18077 +
18078 +00000008 <symdiff_test>:
18079 +   8:  d7 03           nop
18080 +   a:  d7 03           nop
18081 +   c:  d7 03           nop
18082 +   e:  d7 03           nop
18083 --- /dev/null
18084 +++ b/gas/testsuite/gas/avr32/symdiff.s
18085 @@ -0,0 +1,19 @@
18086 +
18087 +       .text
18088 +       .global diff32
18089 +diff32:
18090 +       .long   .L2 - .L1
18091 +       .global diff16
18092 +diff16:
18093 +       .short  .L2 - .L1
18094 +       .global diff8
18095 +diff8:
18096 +       .byte   .L2 - .L1
18097 +
18098 +       .global symdiff_test
18099 +       .align  1
18100 +symdiff_test:
18101 +       nop
18102 +.L1:   nop
18103 +       nop
18104 +.L2:   nop
18105 --- a/gas/write.c
18106 +++ b/gas/write.c
18107 @@ -2011,6 +2011,10 @@ relax_frag (segT segment, fragS *fragP,
18108
18109  #endif /* defined (TC_GENERIC_RELAX_TABLE)  */
18110
18111 +#ifdef TC_RELAX_ALIGN
18112 +#define RELAX_ALIGN(SEG, FRAG, ADDR) TC_RELAX_ALIGN(SEG, FRAG, ADDR)
18113 +#else
18114 +#define RELAX_ALIGN(SEG, FRAG, ADDR) relax_align(ADDR, (FRAG)->fr_offset)
18115  /* Relax_align. Advance location counter to next address that has 'alignment'
18116     lowest order bits all 0s, return size of adjustment made.  */
18117  static relax_addressT
18118 @@ -2030,6 +2034,7 @@ relax_align (register relax_addressT add
18119  #endif
18120    return (new_address - address);
18121  }
18122 +#endif
18123
18124  /* Now we have a segment, not a crowd of sub-segments, we can make
18125     fr_address values.
18126 @@ -2073,7 +2078,7 @@ relax_segment (struct frag *segment_frag
18127         case rs_align_code:
18128         case rs_align_test:
18129           {
18130 -           addressT offset = relax_align (address, (int) fragP->fr_offset);
18131 +           addressT offset = RELAX_ALIGN(segment, fragP, address);
18132
18133             if (fragP->fr_subtype != 0 && offset > fragP->fr_subtype)
18134               offset = 0;
18135 @@ -2280,10 +2285,10 @@ relax_segment (struct frag *segment_frag
18136                 {
18137                   addressT oldoff, newoff;
18138
18139 -                 oldoff = relax_align (was_address + fragP->fr_fix,
18140 -                                       (int) offset);
18141 -                 newoff = relax_align (address + fragP->fr_fix,
18142 -                                       (int) offset);
18143 +                 oldoff = RELAX_ALIGN (segment, fragP,
18144 +                                       was_address + fragP->fr_fix);
18145 +                 newoff = RELAX_ALIGN (segment, fragP,
18146 +                                       address + fragP->fr_fix);
18147
18148                   if (fragP->fr_subtype != 0)
18149                     {
18150 --- a/include/dis-asm.h
18151 +++ b/include/dis-asm.h
18152 @@ -222,6 +222,7 @@ typedef int (*disassembler_ftype) (bfd_v
18153
18154  extern int print_insn_alpha            (bfd_vma, disassemble_info *);
18155  extern int print_insn_avr              (bfd_vma, disassemble_info *);
18156 +extern int print_insn_avr32            (bfd_vma, disassemble_info *);
18157  extern int print_insn_bfin             (bfd_vma, disassemble_info *);
18158  extern int print_insn_big_arm          (bfd_vma, disassemble_info *);
18159  extern int print_insn_big_mips         (bfd_vma, disassemble_info *);
18160 @@ -304,7 +305,9 @@ extern void print_i386_disassembler_opti
18161  extern void print_mips_disassembler_options (FILE *);
18162  extern void print_ppc_disassembler_options (FILE *);
18163  extern void print_arm_disassembler_options (FILE *);
18164 +extern void print_avr32_disassembler_options (FILE *);
18165  extern void parse_arm_disassembler_option (char *);
18166 +extern void parse_avr32_disassembler_option (char *);
18167  extern void print_s390_disassembler_options (FILE *);
18168  extern int  get_arm_regname_num_options (void);
18169  extern int  set_arm_regname_option (int);
18170 --- /dev/null
18171 +++ b/include/elf/avr32.h
18172 @@ -0,0 +1,98 @@
18173 +/* AVR32 ELF support for BFD.
18174 +   Copyright 2003,2004,2005,2006,2007,2008,2009 Atmel Corporation.
18175 +
18176 +   Written by Haavard Skinnemoen, Atmel Norway, <hskinnemoen@atmel.com>
18177 +
18178 +   This file is part of BFD, the Binary File Descriptor library.
18179 +
18180 +   This program is free software; you can redistribute it and/or
18181 +   modify it under the terms of the GNU General Public License as
18182 +   published by the Free Software Foundation; either version 2 of the
18183 +   License, or (at your option) any later version.
18184 +
18185 +   This program is distributed in the hope that it will be useful, but
18186 +   WITHOUT ANY WARRANTY; without even the implied warranty of
18187 +   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
18188 +   General Public License for more details.
18189 +
18190 +   You should have received a copy of the GNU General Public License
18191 +   along with this program; if not, write to the Free Software
18192 +   Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA
18193 +   02111-1307, USA.  */
18194 +
18195 +#include "elf/reloc-macros.h"
18196 +
18197 +/* CPU-specific flags for the ELF header e_flags field */
18198 +#define EF_AVR32_LINKRELAX             0x01
18199 +#define EF_AVR32_PIC                   0x02
18200 +
18201 +START_RELOC_NUMBERS (elf_avr32_reloc_type)
18202 +    RELOC_NUMBER (R_AVR32_NONE,                        0)
18203 +
18204 +    /* Data Relocations */
18205 +    RELOC_NUMBER (R_AVR32_32,                  1)
18206 +    RELOC_NUMBER (R_AVR32_16,                  2)
18207 +    RELOC_NUMBER (R_AVR32_8,                   3)
18208 +    RELOC_NUMBER (R_AVR32_32_PCREL,            4)
18209 +    RELOC_NUMBER (R_AVR32_16_PCREL,            5)
18210 +    RELOC_NUMBER (R_AVR32_8_PCREL,             6)
18211 +    RELOC_NUMBER (R_AVR32_DIFF32,              7)
18212 +    RELOC_NUMBER (R_AVR32_DIFF16,              8)
18213 +    RELOC_NUMBER (R_AVR32_DIFF8,               9)
18214 +    RELOC_NUMBER (R_AVR32_GOT32,               10)
18215 +    RELOC_NUMBER (R_AVR32_GOT16,               11)
18216 +    RELOC_NUMBER (R_AVR32_GOT8,                        12)
18217 +
18218 +    /* Normal Code Relocations */
18219 +    RELOC_NUMBER (R_AVR32_21S,                 13)
18220 +    RELOC_NUMBER (R_AVR32_16U,                 14)
18221 +    RELOC_NUMBER (R_AVR32_16S,                 15)
18222 +    RELOC_NUMBER (R_AVR32_8S,                  16)
18223 +    RELOC_NUMBER (R_AVR32_8S_EXT,              17)
18224 +
18225 +    /* PC-Relative Code Relocations */
18226 +    RELOC_NUMBER (R_AVR32_22H_PCREL,           18)
18227 +    RELOC_NUMBER (R_AVR32_18W_PCREL,           19)
18228 +    RELOC_NUMBER (R_AVR32_16B_PCREL,           20)
18229 +    RELOC_NUMBER (R_AVR32_16N_PCREL,           21)
18230 +    RELOC_NUMBER (R_AVR32_14UW_PCREL,          22)
18231 +    RELOC_NUMBER (R_AVR32_11H_PCREL,           23)
18232 +    RELOC_NUMBER (R_AVR32_10UW_PCREL,          24)
18233 +    RELOC_NUMBER (R_AVR32_9H_PCREL,            25)
18234 +    RELOC_NUMBER (R_AVR32_9UW_PCREL,           26)
18235 +
18236 +    /* Special Code Relocations */
18237 +    RELOC_NUMBER (R_AVR32_HI16,                        27)
18238 +    RELOC_NUMBER (R_AVR32_LO16,                        28)
18239 +
18240 +    /* PIC Relocations */
18241 +    RELOC_NUMBER (R_AVR32_GOTPC,               29)
18242 +    RELOC_NUMBER (R_AVR32_GOTCALL,             30)
18243 +    RELOC_NUMBER (R_AVR32_LDA_GOT,             31)
18244 +    RELOC_NUMBER (R_AVR32_GOT21S,              32)
18245 +    RELOC_NUMBER (R_AVR32_GOT18SW,             33)
18246 +    RELOC_NUMBER (R_AVR32_GOT16S,              34)
18247 +    RELOC_NUMBER (R_AVR32_GOT7UW,              35)
18248 +
18249 +    /* Constant Pool Relocations */
18250 +    RELOC_NUMBER (R_AVR32_32_CPENT,            36)
18251 +    RELOC_NUMBER (R_AVR32_CPCALL,              37)
18252 +    RELOC_NUMBER (R_AVR32_16_CP,               38)
18253 +    RELOC_NUMBER (R_AVR32_9W_CP,               39)
18254 +
18255 +    /* Dynamic Relocations */
18256 +    RELOC_NUMBER (R_AVR32_RELATIVE,            40)
18257 +    RELOC_NUMBER (R_AVR32_GLOB_DAT,            41)
18258 +    RELOC_NUMBER (R_AVR32_JMP_SLOT,            42)
18259 +
18260 +    /* Linkrelax Information */
18261 +    RELOC_NUMBER (R_AVR32_ALIGN,               43)
18262 +
18263 +    RELOC_NUMBER (R_AVR32_15S,                 44)
18264 +
18265 +END_RELOC_NUMBERS (R_AVR32_max)
18266 +
18267 +/* Processor specific dynamic array tags.  */
18268 +
18269 +/* The total size in bytes of the Global Offset Table */
18270 +#define DT_AVR32_GOTSZ                 0x70000001
18271 --- a/include/elf/common.h
18272 +++ b/include/elf/common.h
18273 @@ -286,7 +286,7 @@
18274  #define EM_INTEL182    182     /* Reserved by Intel */
18275  #define EM_res183      183     /* Reserved by ARM */
18276  #define EM_res184      184     /* Reserved by ARM */
18277 -#define EM_AVR32       185     /* Atmel Corporation 32-bit microprocessor family */
18278 +#define EM_AVR32_OLD   185     /* Atmel Corporation 32-bit microprocessor family */
18279  #define EM_STM8        186     /* STMicroeletronics STM8 8-bit microcontroller */
18280  #define EM_TILE64      187     /* Tilera TILE64 multicore architecture family */
18281  #define EM_TILEPRO     188     /* Tilera TILEPro multicore architecture family */
18282 @@ -365,6 +365,9 @@
18283  /* V850 backend magic number.  Written in the absense of an ABI.  */
18284  #define EM_CYGNUS_V850         0x9080
18285
18286 +/* AVR32 magic number, picked by IAR Systems. */
18287 +#define EM_AVR32               0x18ad
18288 +
18289  /* old S/390 backend magic number. Written in the absence of an ABI.  */
18290  #define EM_S390_OLD            0xa390
18291
18292 --- a/ld/configdoc.texi
18293 +++ b/ld/configdoc.texi
18294 @@ -7,6 +7,7 @@
18295  @set H8300
18296  @set HPPA
18297  @set I960
18298 +@set AVR32
18299  @set M68HC11
18300  @set M68K
18301  @set MMIX
18302 --- a/ld/configure.tgt
18303 +++ b/ld/configure.tgt
18304 @@ -112,6 +112,9 @@ xscale-*-elf)               targ_emul=armelf
18305  avr-*-*)               targ_emul=avr2
18306                         targ_extra_emuls="avr1 avr25 avr3 avr31 avr35 avr4 avr5 avr51 avr6"
18307                         ;;
18308 +avr32-*-none)           targ_emul=avr32elf_ap7000
18309 +                        targ_extra_emuls="avr32elf_ap7001 avr32elf_ap7002 avr32elf_ap7200 avr32elf_uc3a0128 avr32elf_uc3a0256 avr32elf_uc3a0512 avr32elf_uc3a0512es avr32elf_uc3a1128 avr32elf_uc3a1256 avr32elf_uc3a1512es avr32elf_uc3a1512 avr32elf_uc3a364 avr32elf_uc3a364s avr32elf_uc3a3128 avr32elf_uc3a3128s avr32elf_uc3a3256 avr32elf_uc3a3256s avr32elf_uc3b064 avr32elf_uc3b0128 avr32elf_uc3b0256es avr32elf_uc3b0256 avr32elf_uc3b0512 avr32elf_uc3b0512revc avr32elf_uc3b164 avr32elf_uc3b1128 avr32elf_uc3b1256es avr32elf_uc3b1256 avr32elf_uc3b1512 avr32elf_uc3b1512revc avr32elf_uc3c0512crevc avr32elf_uc3c1512crevc avr32elf_uc3c2512crevc avr32elf_atuc3l0256 avr32elf_mxt768e avr32elf_uc3l064 avr32elf_uc3l032 avr32elf_uc3l016 avr32elf_uc3l064revb avr32elf_uc3c064c avr32elf_uc3c0128c avr32elf_uc3c0256c avr32elf_uc3c0512c avr32elf_uc3c164c avr32elf_uc3c1128c avr32elf_uc3c1256c avr32elf_uc3c1512c avr32elf_uc3c264c avr32elf_uc3c2128c avr32elf_uc3c2256c avr32elf_uc3c2512c" ;;
18310 +avr32-*-linux*)         targ_emul=avr32linux ;;
18311  bfin-*-elf)            targ_emul=elf32bfin;
18312                         targ_extra_emuls="elf32bfinfd"
18313                         targ_extra_libpath=$targ_extra_emuls
18314 --- /dev/null
18315 +++ b/ld/emulparams/avr32elf.sh
18316 @@ -0,0 +1,402 @@
18317 +# This script is called from ld/genscript.sh
18318 +# There is a difference on how 'bash' and POSIX handles
18319 +# the  '.' (source) command in a script.
18320 +# genscript.sh calls this script with argument ${EMULATION_NAME}
18321 +# but that will fail on POSIX compilant shells like 'sh' or 'dash'
18322 +# therefor I use the variable directly instead of $1
18323 +EMULATION=${EMULATION_NAME}
18324 +SCRIPT_NAME=avr32
18325 +TEMPLATE_NAME=elf32
18326 +EXTRA_EM_FILE=avr32elf
18327 +OUTPUT_FORMAT="elf32-avr32"
18328 +ARCH=avr32
18329 +MAXPAGESIZE=4096
18330 +ENTRY=_start
18331 +EMBEDDED=yes
18332 +NO_SMALL_DATA=yes
18333 +NOP=0xd703d703
18334 +
18335 +DATA_SEGMENT_ALIGN=8
18336 +BSS_ALIGNMENT=8
18337 +
18338 +RO_LMA_REGION="FLASH"
18339 +RO_VMA_REGION="FLASH"
18340 +RW_LMA_REGION="FLASH"
18341 +RW_VMA_REGION="CPUSRAM"
18342 +
18343 +STACK_SIZE=_stack_size
18344 +STACK_ADDR="ORIGIN(CPUSRAM) + LENGTH(CPUSRAM) - ${STACK_SIZE}"
18345 +
18346 +DATA_SEGMENT_END="
18347 +  __heap_start__ = ALIGN(8);
18348 +  . = ${STACK_ADDR};
18349 +  __heap_end__ = .;
18350 +"
18351 +
18352 +case "$EMULATION" in
18353 +avr32elf_ap*)
18354 +    MACHINE=ap
18355 +    INITIAL_READONLY_SECTIONS="
18356 +    .reset : {  *(.reset) } >FLASH AT>FLASH
18357 +    . = . & 0x9fffffff;
18358 +"
18359 +    TEXT_START_ADDR=0xa0000000
18360 +    case "$EMULATION" in
18361 +           avr32elf_ap700[0-2])
18362 +              MEMORY="
18363 +MEMORY
18364 +{
18365 +    FLASH (rxai) : ORIGIN = 0x00000000, LENGTH = 64M
18366 +    CPUSRAM (rwxa) : ORIGIN = 0x24000000, LENGTH = 32K
18367 +}
18368 +"
18369 +        ;;
18370 +    avr32elf_ap7200)
18371 +        MEMORY="
18372 +MEMORY
18373 +{
18374 +    FLASH (rxai) : ORIGIN = 0x00000000, LENGTH = 64M
18375 +    CPUSRAM (rwxa) : ORIGIN = 0x08000000, LENGTH = 64K
18376 +}
18377 +"
18378 +        ;;
18379 +    esac
18380 +    ;;
18381 +
18382 +avr32elf_mxt768e)
18383 +    MACHINE=uc
18384 +    INITIAL_READONLY_SECTIONS=".reset : {  *(.reset) } >FLASH AT>FLASH"
18385 +    TEXT_START_ADDR=0x80000000
18386 +    OTHER_SECTIONS="
18387 +  .userpage :  { *(.userpage .userpage.*)  } >USERPAGE AT>USERPAGE
18388 +  .factorypage :  { *(.factorypage .factorypage.*)  } >FACTORYPAGE AT>FACTORYPAGE
18389 +"
18390 +        MEMORY="
18391 +MEMORY
18392 +{
18393 +    FLASH (rxai!w) : ORIGIN = 0x80000000, LENGTH = 64K
18394 +    CPUSRAM (wxa!ri) : ORIGIN = 0x00000004, LENGTH = 0x3FFC
18395 +    USERPAGE : ORIGIN = 0x80800000, LENGTH = 512
18396 +    FACTORYPAGE : ORIGIN = 0x80800200, LENGTH = 512
18397 +    FLASHVAULT_FLASH_SIZE (r) : ORIGIN = 0x80800400, LENGTH = 8
18398 +    FLASHVAULT_RAM_SIZE (r) : ORIGIN = 0x80800408, LENGTH = 8
18399 +}
18400 +"
18401 +        OTHER_SECTIONS="${OTHER_SECTIONS}
18402 +  .flashvault_flash_size : { KEEP(*(.flashvault_flash_size .flashvault_flash_size.*)) } > FLASHVAULT_FLASH_SIZE
18403 +  .flashvault_ram_size   : { KEEP(*(.flashvault_ram_size .flashvault_ram_size.*)) } > FLASHVAULT_RAM_SIZE
18404 +"
18405 +      ;;
18406 +
18407 +avr32elf_atuc3*)
18408 +    MACHINE=uc
18409 +    INITIAL_READONLY_SECTIONS=".reset : {  *(.reset) } >FLASH AT>FLASH"
18410 +    TEXT_START_ADDR=0x80000000
18411 +    OTHER_SECTIONS="
18412 +  .userpage :  { *(.userpage .userpage.*)  } >USERPAGE AT>USERPAGE
18413 +  .factorypage :  { *(.factorypage .factorypage.*)  } >FACTORYPAGE AT>FACTORYPAGE
18414 +"
18415 +    case "$EMULATION" in
18416 +    avr32elf_atuc3l0256)
18417 +        MEMORY="
18418 +MEMORY
18419 +{
18420 +    FLASH (rxai!w) : ORIGIN = 0x80000000, LENGTH = 256K
18421 +    CPUSRAM (wxa!ri) : ORIGIN = 0x00000004, LENGTH = 0x3FFC
18422 +    USERPAGE : ORIGIN = 0x80800000, LENGTH = 512
18423 +    FACTORYPAGE : ORIGIN = 0x80800200, LENGTH = 512
18424 +    FLASHVAULT_FLASH_SIZE (r) : ORIGIN = 0x80800400, LENGTH = 8
18425 +    FLASHVAULT_RAM_SIZE (r) : ORIGIN = 0x80800408, LENGTH = 8
18426 +}
18427 +"
18428 +        OTHER_SECTIONS="${OTHER_SECTIONS}
18429 +  .flashvault_flash_size : { KEEP(*(.flashvault_flash_size .flashvault_flash_size.*)) } > FLASHVAULT_FLASH_SIZE
18430 +  .flashvault_ram_size   : { KEEP(*(.flashvault_ram_size .flashvault_ram_size.*)) } > FLASHVAULT_RAM_SIZE
18431 +"
18432 +        ;;
18433 +    esac
18434 +    ;;
18435 +
18436 +avr32elf_uc3*)
18437 +    MACHINE=uc
18438 +    INITIAL_READONLY_SECTIONS=".reset : {  *(.reset) } >FLASH AT>FLASH"
18439 +    TEXT_START_ADDR=0x80000000
18440 +    OTHER_SECTIONS="
18441 +  .userpage :  { *(.userpage .userpage.*)  } >USERPAGE AT>USERPAGE
18442 +  .factorypage :  { *(.factorypage .factorypage.*)  } >FACTORYPAGE AT>FACTORYPAGE
18443 +"
18444 +
18445 +    case "$EMULATION" in
18446 +    avr32elf_uc3c[012]512c)
18447 +        MEMORY="
18448 +MEMORY
18449 +{
18450 +    FLASH (rxai!w) : ORIGIN = 0x80000000, LENGTH = 512K
18451 +    CPUSRAM (wxa!ri) : ORIGIN = 0x00000004, LENGTH = 0xFFFC
18452 +    USERPAGE : ORIGIN = 0x80800000, LENGTH = 512
18453 +    FACTORYPAGE : ORIGIN = 0x80800200, LENGTH = 512
18454 +    FLASHVAULT_FLASH_SIZE (r) : ORIGIN = 0x80800400, LENGTH = 8
18455 +    FLASHVAULT_RAM_SIZE (r) : ORIGIN = 0x80800408, LENGTH = 8
18456 +}
18457 +"
18458 +        OTHER_SECTIONS="${OTHER_SECTIONS}
18459 +  .flashvault_flash_size : { KEEP(*(.flashvault_flash_size .flashvault_flash_size.*)) } > FLASHVAULT_FLASH_SIZE
18460 +  .flashvault_ram_size   : { KEEP(*(.flashvault_ram_size .flashvault_ram_size.*)) } > FLASHVAULT_RAM_SIZE
18461 +"
18462 +        ;;
18463 +
18464 +    avr32elf_uc3c[012]256c)
18465 +        MEMORY="
18466 +MEMORY
18467 +{
18468 +    FLASH (rxai!w) : ORIGIN = 0x80000000, LENGTH = 256K
18469 +    CPUSRAM (wxa!ri) : ORIGIN = 0x00000004, LENGTH = 0xFFFC
18470 +    USERPAGE : ORIGIN = 0x80800000, LENGTH = 512
18471 +    FACTORYPAGE : ORIGIN = 0x80800200, LENGTH = 512
18472 +    FLASHVAULT_FLASH_SIZE (r) : ORIGIN = 0x80800400, LENGTH = 8
18473 +    FLASHVAULT_RAM_SIZE (r) : ORIGIN = 0x80800408, LENGTH = 8
18474 +}
18475 +"
18476 +        OTHER_SECTIONS="${OTHER_SECTIONS}
18477 +  .flashvault_flash_size : { KEEP(*(.flashvault_flash_size .flashvault_flash_size.*)) } > FLASHVAULT_FLASH_SIZE
18478 +  .flashvault_ram_size   : { KEEP(*(.flashvault_ram_size .flashvault_ram_size.*)) } > FLASHVAULT_RAM_SIZE
18479 +"
18480 +        ;;
18481 +
18482 +    avr32elf_uc3c[012]128c)
18483 +        MEMORY="
18484 +MEMORY
18485 +{
18486 +    FLASH (rxai!w) : ORIGIN = 0x80000000, LENGTH = 128K
18487 +    CPUSRAM (wxa!ri) : ORIGIN = 0x00000004, LENGTH = 0x7FFC
18488 +    USERPAGE : ORIGIN = 0x80800000, LENGTH = 512
18489 +    FACTORYPAGE : ORIGIN = 0x80800200, LENGTH = 512
18490 +    FLASHVAULT_FLASH_SIZE (r) : ORIGIN = 0x80800400, LENGTH = 8
18491 +    FLASHVAULT_RAM_SIZE (r) : ORIGIN = 0x80800408, LENGTH = 8
18492 +}
18493 +"
18494 +        OTHER_SECTIONS="${OTHER_SECTIONS}
18495 +  .flashvault_flash_size : { KEEP(*(.flashvault_flash_size .flashvault_flash_size.*)) } > FLASHVAULT_FLASH_SIZE
18496 +  .flashvault_ram_size   : { KEEP(*(.flashvault_ram_size .flashvault_ram_size.*)) } > FLASHVAULT_RAM_SIZE
18497 +"
18498 +        ;;
18499 +
18500 +    avr32elf_uc3c[012]64c)
18501 +        MEMORY="
18502 +MEMORY
18503 +{
18504 +    FLASH (rxai!w) : ORIGIN = 0x80000000, LENGTH = 64K
18505 +    CPUSRAM (wxa!ri) : ORIGIN = 0x00000004, LENGTH = 0x3FFC
18506 +    USERPAGE : ORIGIN = 0x80800000, LENGTH = 512
18507 +    FACTORYPAGE : ORIGIN = 0x80800200, LENGTH = 512
18508 +    FLASHVAULT_FLASH_SIZE (r) : ORIGIN = 0x80800400, LENGTH = 8
18509 +    FLASHVAULT_RAM_SIZE (r) : ORIGIN = 0x80800408, LENGTH = 8
18510 +}
18511 +"
18512 +        OTHER_SECTIONS="${OTHER_SECTIONS}
18513 +  .flashvault_flash_size : { KEEP(*(.flashvault_flash_size .flashvault_flash_size.*)) } > FLASHVAULT_FLASH_SIZE
18514 +  .flashvault_ram_size   : { KEEP(*(.flashvault_ram_size .flashvault_ram_size.*)) } > FLASHVAULT_RAM_SIZE
18515 +"
18516 +        ;;
18517 +
18518 +   avr32elf_uc3[ac][012]512*)
18519 +       MEMORY="
18520 +MEMORY
18521 +{
18522 +    FLASH (rxai!w) : ORIGIN = 0x80000000, LENGTH = 512K
18523 +    CPUSRAM (wxa!ri) : ORIGIN = 0x00000004, LENGTH = 0xFFFC
18524 +    USERPAGE : ORIGIN = 0x80800000, LENGTH = 512
18525 +    FACTORYPAGE : ORIGIN = 0x80800200, LENGTH = 512
18526 +}
18527 +"
18528 +        ;;
18529 +
18530 +    avr32elf_uc3a[012]256*)
18531 +        MEMORY="
18532 +MEMORY
18533 +{
18534 +    FLASH (rxai!w) : ORIGIN = 0x80000000, LENGTH = 256K
18535 +    CPUSRAM (wxa!ri) : ORIGIN = 0x00000004, LENGTH = 0xFFFC
18536 +    USERPAGE : ORIGIN = 0x80800000, LENGTH = 512
18537 +    FACTORYPAGE : ORIGIN = 0x80800200, LENGTH = 512
18538 +}
18539 +"
18540 +        ;;
18541 +
18542 +    avr32elf_uc3b[01]512revc)
18543 +        MEMORY="
18544 +MEMORY
18545 +{
18546 +    FLASH (rxai!w) : ORIGIN = 0x80000000, LENGTH = 512K
18547 +    CPUSRAM (wxa!ri) : ORIGIN = 0x00000004, LENGTH = 0x17FFC
18548 +    USERPAGE : ORIGIN = 0x80800000, LENGTH = 512
18549 +    FACTORYPAGE : ORIGIN = 0x80800200, LENGTH = 512
18550 +}
18551 +"
18552 +         PADDING="
18553 +  .padding : {
18554 +  QUAD(0)
18555 +  QUAD(0)
18556 +  QUAD(0)
18557 +  QUAD(0)
18558 +  } >FLASH AT>FLASH
18559 +"
18560 +        ;;
18561 +
18562 +    avr32elf_uc3b[01]512)
18563 +        MEMORY="
18564 +MEMORY
18565 +{
18566 +    FLASH (rxai!w) : ORIGIN = 0x80000000, LENGTH = 512K
18567 +    CPUSRAM (wxa!ri) : ORIGIN = 0x00000004, LENGTH = 0x17FFC
18568 +    USERPAGE : ORIGIN = 0x80800000, LENGTH = 512
18569 +    FACTORYPAGE : ORIGIN = 0x80800200, LENGTH = 512
18570 +}
18571 +"
18572 +        ;;
18573 +
18574 +    avr32elf_uc3b[01]256*)
18575 +        MEMORY="
18576 +MEMORY
18577 +{
18578 +    FLASH (rxai!w) : ORIGIN = 0x80000000, LENGTH = 256K
18579 +    CPUSRAM (wxa!ri) : ORIGIN = 0x00000004, LENGTH = 0x7FFC
18580 +    USERPAGE : ORIGIN = 0x80800000, LENGTH = 512
18581 +    FACTORYPAGE : ORIGIN = 0x80800200, LENGTH = 512
18582 +}
18583 +"
18584 +        ;;
18585 +
18586 +    avr32elf_uc3[ab][012]128*)
18587 +        MEMORY="
18588 +MEMORY
18589 +{
18590 +    FLASH (rxai!w) : ORIGIN = 0x80000000, LENGTH = 128K
18591 +    CPUSRAM (wxa!ri) : ORIGIN = 0x00000004, LENGTH = 0x7FFC
18592 +    USERPAGE : ORIGIN = 0x80800000, LENGTH = 512
18593 +    FACTORYPAGE : ORIGIN = 0x80800200, LENGTH = 512
18594 +}
18595 +"
18596 +        ;;
18597 +
18598 +    avr32elf_uc3b[0123]64*)
18599 +        MEMORY="
18600 +MEMORY
18601 +{
18602 +    FLASH (rxai!w) : ORIGIN = 0x80000000, LENGTH = 64K
18603 +    CPUSRAM (wxa!ri) : ORIGIN = 0x00000004, LENGTH = 0x3FFC
18604 +    USERPAGE : ORIGIN = 0x80800000, LENGTH = 512
18605 +    FACTORYPAGE : ORIGIN = 0x80800200, LENGTH = 512
18606 +}
18607 +"
18608 +        ;;
18609 +
18610 +    avr32elf_uc3a3256*)
18611 +        MEMORY="
18612 +MEMORY
18613 +{
18614 +    FLASH (rxai!w) : ORIGIN = 0x80000000, LENGTH = 256K
18615 +    CPUSRAM (wxa!ri) : ORIGIN = 0x00000004, LENGTH = 0xFFFC
18616 +    HSBSRAM (wxa!ri) : ORIGIN = 0xFF000000, LENGTH = 64K
18617 +    USERPAGE : ORIGIN = 0x80800000, LENGTH = 512
18618 +    FACTORYPAGE : ORIGIN = 0x80800200, LENGTH = 512
18619 +}
18620 +"
18621 +        OTHER_SECTIONS="${OTHER_SECTIONS}
18622 +  .hsbsram       : { *(.hsbsram .hsbsram.*) } >HSBSRAM AT>FLASH :FLASH
18623 +"
18624 +
18625 +        ;;
18626 +
18627 +    avr32elf_uc3a3128*)
18628 +        MEMORY="
18629 +MEMORY
18630 +{
18631 +    FLASH (rxai!w) : ORIGIN = 0x80000000, LENGTH = 128K
18632 +    CPUSRAM (wxa!ri) : ORIGIN = 0x00000004, LENGTH = 0xFFFC
18633 +    HSBSRAM (wxa!ri) : ORIGIN = 0xFF000000, LENGTH = 64K
18634 +    USERPAGE : ORIGIN = 0x80800000, LENGTH = 512
18635 +    FACTORYPAGE : ORIGIN = 0x80800200, LENGTH = 512
18636 +}
18637 +"
18638 +        OTHER_SECTIONS="${OTHER_SECTIONS}
18639 +  .hsbsram       : { *(.hsbsram .hsbsram.*) } >HSBSRAM AT>FLASH :FLASH
18640 +"
18641 +        ;;
18642 +
18643 +    avr32elf_uc3a364*)
18644 +        MEMORY="
18645 +MEMORY
18646 +{
18647 +    FLASH (rxai!w) : ORIGIN = 0x80000000, LENGTH = 64K
18648 +    CPUSRAM (wxa!ri) : ORIGIN = 0x00000004, LENGTH = 0xFFFC
18649 +    HSBSRAM (wxa!ri) : ORIGIN = 0xFF000000, LENGTH = 64K
18650 +    USERPAGE : ORIGIN = 0x80800000, LENGTH = 512
18651 +    FACTORYPAGE : ORIGIN = 0x80800200, LENGTH = 512
18652 +}
18653 +"
18654 +        OTHER_SECTIONS="${OTHER_SECTIONS}
18655 +  .hsbsram       : { *(.hsbsram .hsbsram.*) } >HSBSRAM AT>FLASH :FLASH
18656 +"
18657 +        ;;
18658 +
18659 +
18660 +    avr32elf_uc3l[0123]64*)
18661 +        MEMORY="
18662 +MEMORY
18663 +{
18664 +    FLASH (rxai!w) : ORIGIN = 0x80000000, LENGTH = 64K
18665 +    CPUSRAM (wxa!ri) : ORIGIN = 0x00000004, LENGTH = 0x3FFC
18666 +    USERPAGE : ORIGIN = 0x80800000, LENGTH = 512
18667 +    FACTORYPAGE : ORIGIN = 0x80800200, LENGTH = 512
18668 +    FLASHVAULT_FLASH_SIZE (r) : ORIGIN = 0x80800400, LENGTH = 8
18669 +    FLASHVAULT_RAM_SIZE (r) : ORIGIN = 0x80800408, LENGTH = 8
18670 +}
18671 +"
18672 +        OTHER_SECTIONS="${OTHER_SECTIONS}
18673 +  .flashvault_flash_size : { KEEP(*(.flashvault_flash_size .flashvault_flash_size.*)) } > FLASHVAULT_FLASH_SIZE
18674 +  .flashvault_ram_size   : { KEEP(*(.flashvault_ram_size .flashvault_ram_size.*)) } > FLASHVAULT_RAM_SIZE
18675 +"
18676 +        ;;
18677 +
18678 +    avr32elf_uc3l[0123]32*)
18679 +        MEMORY="
18680 +MEMORY
18681 +{
18682 +    FLASH (rxai!w) : ORIGIN = 0x80000000, LENGTH = 32K
18683 +    CPUSRAM (wxa!ri) : ORIGIN = 0x00000004, LENGTH = 0x3FFC
18684 +    USERPAGE : ORIGIN = 0x80800000, LENGTH = 512
18685 +    FACTORYPAGE : ORIGIN = 0x80800200, LENGTH = 512
18686 +    FLASHVAULT_FLASH_SIZE (r) : ORIGIN = 0x80800400, LENGTH = 8
18687 +    FLASHVAULT_RAM_SIZE (r) : ORIGIN = 0x80800408, LENGTH = 8
18688 +}
18689 +"
18690 +        OTHER_SECTIONS="${OTHER_SECTIONS}
18691 +  .flashvault_flash_size : { KEEP(*(.flashvault_flash_size .flashvault_flash_size.*)) } > FLASHVAULT_FLASH_SIZE
18692 +  .flashvault_ram_size   : { KEEP(*(.flashvault_ram_size .flashvault_ram_size.*)) } > FLASHVAULT_RAM_SIZE
18693 +"
18694 +        ;;
18695 +
18696 +    avr32elf_uc3l[0123]16*)
18697 +        MEMORY="
18698 +MEMORY
18699 +{
18700 +    FLASH (rxai!w) : ORIGIN = 0x80000000, LENGTH = 16K
18701 +    CPUSRAM (wxa!ri) : ORIGIN = 0x00000004, LENGTH = 0x1FFC
18702 +    USERPAGE : ORIGIN = 0x80800000, LENGTH = 512
18703 +    FACTORYPAGE : ORIGIN = 0x80800200, LENGTH = 512
18704 +    FLASHVAULT_FLASH_SIZE (r) : ORIGIN = 0x80800400, LENGTH = 8
18705 +    FLASHVAULT_RAM_SIZE (r) : ORIGIN = 0x80800408, LENGTH = 8
18706 +}
18707 +"
18708 +        OTHER_SECTIONS="${OTHER_SECTIONS}
18709 +  .flashvault_flash_size : { KEEP(*(.flashvault_flash_size .flashvault_flash_size.*)) } > FLASHVAULT_FLASH_SIZE
18710 +  .flashvault_ram_size   : { KEEP(*(.flashvault_ram_size .flashvault_ram_size.*)) } > FLASHVAULT_RAM_SIZE
18711 +"
18712 +        ;;
18713 +
18714 +
18715 +    esac
18716 +    ;;
18717 +
18718 +esac
18719 --- /dev/null
18720 +++ b/ld/emulparams/avr32linux.sh
18721 @@ -0,0 +1,14 @@
18722 +ARCH=avr32
18723 +SCRIPT_NAME=elf
18724 +TEMPLATE_NAME=elf32
18725 +EXTRA_EM_FILE=avr32elf
18726 +OUTPUT_FORMAT="elf32-avr32"
18727 +GENERATE_SHLIB_SCRIPT=yes
18728 +MAXPAGESIZE=0x1000
18729 +TEXT_START_ADDR=0x00001000
18730 +NOP=0xd703d703
18731 +
18732 +# This appears to place the GOT before the data section, which is
18733 +# essential for uClinux.  We don't use those .s* sections on AVR32
18734 +# anyway, so it shouldn't hurt for regular Linux either...
18735 +NO_SMALL_DATA=yes
18736 --- /dev/null
18737 +++ b/ld/emultempl/avr32elf.em
18738 @@ -0,0 +1,162 @@
18739 +# This shell script emits a C file. -*- C -*-
18740 +#   Copyright (C) 2007,2008,2009 Atmel Corporation
18741 +#
18742 +# This file is part of GLD, the Gnu Linker.
18743 +#
18744 +# This program is free software; you can redistribute it and/or modify
18745 +# it under the terms of the GNU General Public License as published by
18746 +# the Free Software Foundation; either version 2 of the License, or
18747 +# (at your option) any later version.
18748 +#
18749 +# This program is distributed in the hope that it will be useful,
18750 +# but WITHOUT ANY WARRANTY; without even the implied warranty of
18751 +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
18752 +# GNU General Public License for more details.
18753 +#
18754 +# You should have received a copy of the GNU General Public License
18755 +# along with this program; if not, write to the Free Software
18756 +# Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
18757 +#
18758 +
18759 +# This file is sourced from elf32.em, and defines extra avr32-elf
18760 +# specific routines.
18761 +#
18762 +
18763 +# Generate linker script for writable rodata
18764 +LD_FLAG=rodata-writable
18765 +DATA_ALIGNMENT=${DATA_ALIGNMENT_}
18766 +RELOCATING=" "
18767 +WRITABLE_RODATA=" "
18768 +( echo "/* Linker script for writable rodata */"
18769 +  . ${CUSTOMIZER_SCRIPT} ${EMULATION_NAME}
18770 +  . ${srcdir}/scripttempl/${SCRIPT_NAME}.sc
18771 +) | sed -e '/^ *$/d;s/[        ]*$//' > ldscripts/${EMULATION_NAME}.xwr
18772 +
18773 +
18774 +cat >> e${EMULATION_NAME}.c <<EOF
18775 +
18776 +#include "libbfd.h"
18777 +#include "elf32-avr32.h"
18778 +
18779 +/* Whether to allow direct references (sub or mov) to SEC_DATA and
18780 +   !SEC_CONTENTS sections when optimizing.  Not enabled by default
18781 +   since it might cause link errors.  */
18782 +static int direct_data_refs = 0;
18783 +
18784 +static void avr32_elf_after_open (void)
18785 +{
18786 +  bfd_elf32_avr32_set_options (&link_info, direct_data_refs);
18787 +  gld${EMULATION_NAME}_after_open ();
18788 +}
18789 +
18790 +static int rodata_writable = 0;
18791 +
18792 +static int stack_size = 0x1000;
18793 +
18794 +static void avr32_elf_set_symbols (void)
18795 +{
18796 +  /* Glue the assignments into the abs section.  */
18797 +  lang_statement_list_type *save = stat_ptr;
18798 +
18799 +
18800 +  stat_ptr = &(abs_output_section->children);
18801 +
18802 +  lang_add_assignment (exp_assop ('=', "_stack_size",
18803 +                                  exp_intop (stack_size)));
18804 +
18805 +  stat_ptr = save;
18806 +}
18807 +
18808 +static char * gld${EMULATION_NAME}_get_script (int *isfile);
18809 +
18810 +static char * avr32_elf_get_script (int *isfile)
18811 +{
18812 +  if ( rodata_writable )
18813 +    {
18814 +EOF
18815 +if test -n "$COMPILE_IN"
18816 +then
18817 +# Scripts compiled in.
18818 +
18819 +# sed commands to quote an ld script as a C string.
18820 +sc="-f stringify.sed"
18821 +
18822 +cat >>e${EMULATION_NAME}.c <<EOF
18823 +      *isfile = 0;
18824 +      return
18825 +EOF
18826 +sed $sc ldscripts/${EMULATION_NAME}.xwr                        >> e${EMULATION_NAME}.c
18827 +echo  ';'                                              >> e${EMULATION_NAME}.c
18828 +else
18829 +# Scripts read from the filesystem.
18830 +
18831 +cat >>e${EMULATION_NAME}.c <<EOF
18832 +      *isfile = 1;
18833 +      return "ldscripts/${EMULATION_NAME}.xwr";
18834 +EOF
18835 +fi
18836 +
18837 +cat >>e${EMULATION_NAME}.c <<EOF
18838 +    }
18839 +  return gld${EMULATION_NAME}_get_script (isfile);
18840 +}
18841 +
18842 +
18843 +EOF
18844 +
18845 +# Define some shell vars to insert bits of code into the standard elf
18846 +# parse_args and list_options functions.
18847 +#
18848 +PARSE_AND_LIST_PROLOGUE='
18849 +#define OPTION_DIRECT_DATA             300
18850 +#define OPTION_NO_DIRECT_DATA          301
18851 +#define OPTION_RODATA_WRITABLE         302
18852 +#define OPTION_NO_RODATA_WRITABLE      303
18853 +#define OPTION_STACK                   304
18854 +'
18855 +
18856 +PARSE_AND_LIST_LONGOPTS='
18857 +  { "direct-data", no_argument, NULL, OPTION_DIRECT_DATA },
18858 +  { "no-direct-data", no_argument, NULL, OPTION_NO_DIRECT_DATA },
18859 +  { "rodata-writable", no_argument, NULL, OPTION_RODATA_WRITABLE },
18860 +  { "no-rodata-writable", no_argument, NULL, OPTION_NO_RODATA_WRITABLE },
18861 +  { "stack", required_argument, NULL, OPTION_STACK },
18862 +'
18863 +
18864 +PARSE_AND_LIST_OPTIONS='
18865 +  fprintf (file, _("  --direct-data\t\tAllow direct data references when optimizing\n"));
18866 +  fprintf (file, _("  --no-direct-data\tDo not allow direct data references when optimizing\n"));
18867 +  fprintf (file, _("  --rodata-writable\tPut read-only data in writable data section\n"));
18868 +  fprintf (file, _("  --no-rodata-writable\tDo not put read-only data in writable data section\n"));
18869 +  fprintf (file, _("  --stack <size>\tSet the initial size of the stack\n"));
18870 +'
18871 +
18872 +PARSE_AND_LIST_ARGS_CASES='
18873 +    case OPTION_DIRECT_DATA:
18874 +      direct_data_refs = 1;
18875 +      break;
18876 +    case OPTION_NO_DIRECT_DATA:
18877 +      direct_data_refs = 0;
18878 +      break;
18879 +    case OPTION_RODATA_WRITABLE:
18880 +      rodata_writable = 1;
18881 +      break;
18882 +    case OPTION_NO_RODATA_WRITABLE:
18883 +      rodata_writable = 0;
18884 +      break;
18885 +    case OPTION_STACK:
18886 +     {
18887 +      char *end;
18888 +      stack_size = strtoul (optarg, &end, 0);
18889 +      if (end == optarg)
18890 +        einfo (_("%P%F: invalid hex number for parameter '%s'\n"), optarg);
18891 +      optarg = end;
18892 +      break;
18893 +     }
18894 +'
18895 +
18896 +# Replace some of the standard ELF functions with our own versions.
18897 +#
18898 +LDEMUL_AFTER_OPEN=avr32_elf_after_open
18899 +LDEMUL_GET_SCRIPT=avr32_elf_get_script
18900 +LDEMUL_SET_SYMBOLS=avr32_elf_set_symbols
18901 --- a/ld/Makefile.am
18902 +++ b/ld/Makefile.am
18903 @@ -148,6 +148,58 @@ ALL_EMULATIONS = \
18904         eavr5.o \
18905         eavr51.o \
18906         eavr6.o \
18907 +       eavr32elf_ap7000.o \
18908 +       eavr32elf_ap7001.o \
18909 +       eavr32elf_ap7002.o \
18910 +       eavr32elf_ap7200.o \
18911 +       eavr32elf_uc3a0128.o \
18912 +       eavr32elf_uc3a0256.o \
18913 +       eavr32elf_uc3a0512.o \
18914 +       eavr32elf_uc3a0512es.o \
18915 +       eavr32elf_uc3a1128.o \
18916 +       eavr32elf_uc3a1256.o \
18917 +       eavr32elf_uc3a1512es.o \
18918 +       eavr32elf_uc3a1512.o \
18919 +       eavr32elf_uc3a364.o \
18920 +       eavr32elf_uc3a364s.o \
18921 +       eavr32elf_uc3a3128.o \
18922 +       eavr32elf_uc3a3128s.o \
18923 +       eavr32elf_uc3a3256.o \
18924 +       eavr32elf_uc3a3256s.o \
18925 +       eavr32elf_uc3b064.o \
18926 +       eavr32elf_uc3b0128.o \
18927 +       eavr32elf_uc3b0256es.o \
18928 +       eavr32elf_uc3b0256.o \
18929 +       eavr32elf_uc3b0512.o \
18930 +       eavr32elf_uc3b0512revc.o \
18931 +       eavr32elf_uc3b164.o \
18932 +       eavr32elf_uc3b1128.o \
18933 +       eavr32elf_uc3b1256es.o \
18934 +       eavr32elf_uc3b1256.o \
18935 +       eavr32elf_uc3b1512.o \
18936 +       eavr32elf_uc3b1512revc.o \
18937 +       eavr32elf_uc3c0512crevc.o \
18938 +       eavr32elf_uc3c1512crevc.o \
18939 +       eavr32elf_uc3c2512crevc.o \
18940 +       eavr32elf_atuc3l0256.o \
18941 +        eavr32elf_mxt768e.o \
18942 +       eavr32elf_uc3l064.o \
18943 +       eavr32elf_uc3l032.o \
18944 +       eavr32elf_uc3l016.o \
18945 +       eavr32elf_uc3l064revb.o \
18946 +       eavr32elf_uc3c064c.o \
18947 +       eavr32elf_uc3c0128c.o \
18948 +       eavr32elf_uc3c0256c.o \
18949 +       eavr32elf_uc3c0512c.o \
18950 +       eavr32elf_uc3c164c.o \
18951 +       eavr32elf_uc3c1128c.o \
18952 +       eavr32elf_uc3c1256c.o \
18953 +       eavr32elf_uc3c1512c.o \
18954 +       eavr32elf_uc3c264c.o \
18955 +       eavr32elf_uc3c2128c.o \
18956 +       eavr32elf_uc3c2256c.o \
18957 +       eavr32elf_uc3c2512c.o \
18958 +       eavr32linux.o \
18959         ecoff_i860.o \
18960         ecoff_sparc.o \
18961         eelf32_spu.o \
18962 @@ -727,6 +779,214 @@ eavr6.c: $(srcdir)/emulparams/avr6.sh $(
18963    $(ELF_DEPS) $(srcdir)/scripttempl/avr.sc \
18964    ${GEN_DEPENDS}
18965         ${GENSCRIPTS} avr6 "$(tdir_avr2)"
18966 +eavr32elf_ap7000.c: $(srcdir)/emulparams/avr32elf.sh \
18967 +  $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
18968 +  $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
18969 +       ${GENSCRIPTS} avr32elf_ap7000 "$(tdir_avr32)" avr32elf
18970 +eavr32elf_ap7001.c: $(srcdir)/emulparams/avr32elf.sh \
18971 +  $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
18972 +  $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
18973 +       ${GENSCRIPTS} avr32elf_ap7001 "$(tdir_avr32)" avr32elf
18974 +eavr32elf_ap7002.c: $(srcdir)/emulparams/avr32elf.sh \
18975 +  $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
18976 +  $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
18977 +       ${GENSCRIPTS} avr32elf_ap7002 "$(tdir_avr32)" avr32elf
18978 +eavr32elf_ap7200.c: $(srcdir)/emulparams/avr32elf.sh \
18979 +  $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
18980 +  $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
18981 +       ${GENSCRIPTS} avr32elf_ap7200 "$(tdir_avr32)" avr32elf
18982 +eavr32elf_uc3a0128.c: $(srcdir)/emulparams/avr32elf.sh \
18983 +  $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
18984 +  $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
18985 +       ${GENSCRIPTS} avr32elf_uc3a0128 "$(tdir_avr32)" avr32elf
18986 +eavr32elf_uc3a0256.c: $(srcdir)/emulparams/avr32elf.sh \
18987 +  $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
18988 +  $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
18989 +       ${GENSCRIPTS} avr32elf_uc3a0256 "$(tdir_avr32)" avr32elf
18990 +eavr32elf_uc3a0512.c: $(srcdir)/emulparams/avr32elf.sh \
18991 +  $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
18992 +  $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
18993 +       ${GENSCRIPTS} avr32elf_uc3a0512 "$(tdir_avr32)" avr32elf
18994 +eavr32elf_uc3a0512es.c: $(srcdir)/emulparams/avr32elf.sh \
18995 +  $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
18996 +  $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
18997 +       ${GENSCRIPTS} avr32elf_uc3a0512es "$(tdir_avr32)" avr32elf
18998 +eavr32elf_uc3a1128.c: $(srcdir)/emulparams/avr32elf.sh \
18999 +  $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
19000 +  $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
19001 +       ${GENSCRIPTS} avr32elf_uc3a1128 "$(tdir_avr32)" avr32elf
19002 +eavr32elf_uc3a1256.c: $(srcdir)/emulparams/avr32elf.sh \
19003 +  $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
19004 +  $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
19005 +       ${GENSCRIPTS} avr32elf_uc3a1256 "$(tdir_avr32)" avr32elf
19006 +eavr32elf_uc3a1512.c: $(srcdir)/emulparams/avr32elf.sh \
19007 +  $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
19008 +  $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
19009 +       ${GENSCRIPTS} avr32elf_uc3a1512 "$(tdir_avr32)" avr32elf
19010 +eavr32elf_uc3a1512es.c: $(srcdir)/emulparams/avr32elf.sh \
19011 +  $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
19012 +  $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
19013 +       ${GENSCRIPTS} avr32elf_uc3a1512es "$(tdir_avr32)" avr32elf
19014 +eavr32elf_uc3a364.c: $(srcdir)/emulparams/avr32elf.sh \
19015 +  $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
19016 +  $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
19017 +       ${GENSCRIPTS} avr32elf_uc3a364 "$(tdir_avr32)" avr32elf
19018 +eavr32elf_uc3a364s.c: $(srcdir)/emulparams/avr32elf.sh \
19019 +  $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
19020 +  $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
19021 +       ${GENSCRIPTS} avr32elf_uc3a364s "$(tdir_avr32)" avr32elf
19022 +eavr32elf_uc3a3128.c: $(srcdir)/emulparams/avr32elf.sh \
19023 +  $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
19024 +  $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
19025 +       ${GENSCRIPTS} avr32elf_uc3a3128 "$(tdir_avr32)" avr32elf
19026 +eavr32elf_uc3a3128s.c: $(srcdir)/emulparams/avr32elf.sh \
19027 +  $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
19028 +  $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
19029 +       ${GENSCRIPTS} avr32elf_uc3a3128s "$(tdir_avr32)" avr32elf
19030 +eavr32elf_uc3a3256.c: $(srcdir)/emulparams/avr32elf.sh \
19031 +  $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
19032 +  $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
19033 +       ${GENSCRIPTS} avr32elf_uc3a3256 "$(tdir_avr32)" avr32elf
19034 +eavr32elf_uc3a3256s.c: $(srcdir)/emulparams/avr32elf.sh \
19035 +  $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
19036 +  $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
19037 +       ${GENSCRIPTS} avr32elf_uc3a3256s "$(tdir_avr32)" avr32elf
19038 +eavr32elf_uc3b064.c: $(srcdir)/emulparams/avr32elf.sh \
19039 +  $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
19040 +  $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
19041 +       ${GENSCRIPTS} avr32elf_uc3b064 "$(tdir_avr32)" avr32elf
19042 +eavr32elf_uc3b0128.c: $(srcdir)/emulparams/avr32elf.sh \
19043 +  $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
19044 +  $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
19045 +       ${GENSCRIPTS} avr32elf_uc3b0128 "$(tdir_avr32)" avr32elf
19046 +eavr32elf_uc3b0256.c: $(srcdir)/emulparams/avr32elf.sh \
19047 +  $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
19048 +  $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
19049 +       ${GENSCRIPTS} avr32elf_uc3b0256 "$(tdir_avr32)" avr32elf
19050 +eavr32elf_uc3b0256es.c: $(srcdir)/emulparams/avr32elf.sh \
19051 +  $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
19052 +  $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
19053 +       ${GENSCRIPTS} avr32elf_uc3b0256es "$(tdir_avr32)" avr32elf
19054 +eavr32elf_uc3b0512.c: $(srcdir)/emulparams/avr32elf.sh \
19055 +  $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
19056 +  $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
19057 +       ${GENSCRIPTS} avr32elf_uc3b0512 "$(tdir_avr32)" avr32elf
19058 +eavr32elf_uc3b0512revc.c: $(srcdir)/emulparams/avr32elf.sh \
19059 +  $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
19060 +  $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
19061 +       ${GENSCRIPTS} avr32elf_uc3b0512revc "$(tdir_avr32)" avr32elf
19062 +eavr32elf_uc3b164.c: $(srcdir)/emulparams/avr32elf.sh \
19063 +  $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
19064 +  $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
19065 +       ${GENSCRIPTS} avr32elf_uc3b164 "$(tdir_avr32)" avr32elf
19066 +eavr32elf_uc3b1128.c: $(srcdir)/emulparams/avr32elf.sh \
19067 +  $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
19068 +  $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
19069 +       ${GENSCRIPTS} avr32elf_uc3b1128 "$(tdir_avr32)" avr32elf
19070 +eavr32elf_uc3b1256.c: $(srcdir)/emulparams/avr32elf.sh \
19071 +  $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
19072 +  $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
19073 +       ${GENSCRIPTS} avr32elf_uc3b1256 "$(tdir_avr32)" avr32elf
19074 +eavr32elf_uc3b1256es.c: $(srcdir)/emulparams/avr32elf.sh \
19075 +  $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
19076 +  $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
19077 +       ${GENSCRIPTS} avr32elf_uc3b1256es "$(tdir_avr32)" avr32elf
19078 +eavr32elf_uc3b1512.c: $(srcdir)/emulparams/avr32elf.sh \
19079 +  $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
19080 +  $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
19081 +       ${GENSCRIPTS} avr32elf_uc3b1512 "$(tdir_avr32)" avr32elf
19082 +eavr32elf_uc3b1512revc.c: $(srcdir)/emulparams/avr32elf.sh \
19083 +  $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
19084 +  $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
19085 +       ${GENSCRIPTS} avr32elf_uc3b1512revc "$(tdir_avr32)" avr32elf
19086 +eavr32elf_uc3c0512crevc.c: $(srcdir)/emulparams/avr32elf.sh \
19087 +  $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
19088 +  $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
19089 +       ${GENSCRIPTS} avr32elf_uc3c0512crevc "$(tdir_avr32)" avr32elf
19090 +eavr32elf_uc3c1512crevc.c: $(srcdir)/emulparams/avr32elf.sh \
19091 +  $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
19092 +  $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
19093 +       ${GENSCRIPTS} avr32elf_uc3c1512crevc "$(tdir_avr32)" avr32elf
19094 +eavr32elf_uc3c2512crevc.c: $(srcdir)/emulparams/avr32elf.sh \
19095 +  $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
19096 +  $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
19097 +       ${GENSCRIPTS} avr32elf_uc3c2512crevc "$(tdir_avr32)" avr32elf
19098 +eavr32elf_atuc3l0256.c: $(srcdir)/emulparams/avr32elf.sh \
19099 +  $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
19100 +  $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
19101 +       ${GENSCRIPTS} avr32elf_atuc3l0256 "$(tdir_avr32)" avr32elf
19102 +eavr32elf_mxt768e.c: $(srcdir)/emulparams/avr32elf.sh \
19103 +  $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
19104 +  $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
19105 +       ${GENSCRIPTS} avr32elf_mxt768e "$(tdir_avr32)" avr32elf
19106 +eavr32elf_uc3l064.c: $(srcdir)/emulparams/avr32elf.sh \
19107 +  $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
19108 +  $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
19109 +       ${GENSCRIPTS} avr32elf_uc3l064 "$(tdir_avr32)" avr32elf
19110 +eavr32elf_uc3l032.c: $(srcdir)/emulparams/avr32elf.sh \
19111 +  $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
19112 +  $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
19113 +       ${GENSCRIPTS} avr32elf_uc3l032 "$(tdir_avr32)" avr32elf
19114 +eavr32elf_uc3l016.c: $(srcdir)/emulparams/avr32elf.sh \
19115 +  $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
19116 +  $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
19117 +       ${GENSCRIPTS} avr32elf_uc3l016 "$(tdir_avr32)" avr32elf
19118 +eavr32elf_uc3l064revb.c: $(srcdir)/emulparams/avr32elf.sh \
19119 +  $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
19120 +  $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
19121 +       ${GENSCRIPTS} avr32elf_uc3l064revb "$(tdir_avr32)" avr32elf
19122 +eavr32elf_uc3c064c.c: $(srcdir)/emulparams/avr32elf.sh \
19123 +  $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
19124 +  $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
19125 +       ${GENSCRIPTS} avr32elf_uc3c064c "$(tdir_avr32)" avr32elf
19126 +eavr32elf_uc3c0128c.c: $(srcdir)/emulparams/avr32elf.sh \
19127 +  $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
19128 +  $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
19129 +       ${GENSCRIPTS} avr32elf_uc3c0128c "$(tdir_avr32)" avr32elf
19130 +eavr32elf_uc3c0256c.c: $(srcdir)/emulparams/avr32elf.sh \
19131 +  $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
19132 +  $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
19133 +       ${GENSCRIPTS} avr32elf_uc3c0256c "$(tdir_avr32)" avr32elf
19134 +eavr32elf_uc3c0512c.c: $(srcdir)/emulparams/avr32elf.sh \
19135 +  $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
19136 +  $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
19137 +       ${GENSCRIPTS} avr32elf_uc3c0512c "$(tdir_avr32)" avr32elf
19138 +eavr32elf_uc3c164c.c: $(srcdir)/emulparams/avr32elf.sh \
19139 +  $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
19140 +  $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
19141 +       ${GENSCRIPTS} avr32elf_uc3c164c "$(tdir_avr32)" avr32elf
19142 +eavr32elf_uc3c1128c.c: $(srcdir)/emulparams/avr32elf.sh \
19143 +  $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
19144 +  $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
19145 +       ${GENSCRIPTS} avr32elf_uc3c1128c "$(tdir_avr32)" avr32elf
19146 +eavr32elf_uc3c1256c.c: $(srcdir)/emulparams/avr32elf.sh \
19147 +  $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
19148 +  $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
19149 +       ${GENSCRIPTS} avr32elf_uc3c1256c "$(tdir_avr32)" avr32elf
19150 +eavr32elf_uc3c1512c.c: $(srcdir)/emulparams/avr32elf.sh \
19151 +  $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
19152 +  $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
19153 +       ${GENSCRIPTS} avr32elf_uc3c1512c "$(tdir_avr32)" avr32elf
19154 +eavr32elf_uc3c264c.c: $(srcdir)/emulparams/avr32elf.sh \
19155 +  $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
19156 +  $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
19157 +       ${GENSCRIPTS} avr32elf_uc3c264c "$(tdir_avr32)" avr32elf
19158 +eavr32elf_uc3c2128c.c: $(srcdir)/emulparams/avr32elf.sh \
19159 +  $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
19160 +  $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
19161 +       ${GENSCRIPTS} avr32elf_uc3c2128c "$(tdir_avr32)" avr32elf
19162 +eavr32elf_uc3c2256c.c: $(srcdir)/emulparams/avr32elf.sh \
19163 +  $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
19164 +  $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
19165 +       ${GENSCRIPTS} avr32elf_uc3c2256c "$(tdir_avr32)" avr32elf
19166 +eavr32elf_uc3c2512c.c: $(srcdir)/emulparams/avr32elf.sh \
19167 +  $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
19168 +  $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
19169 +       ${GENSCRIPTS} avr32elf_uc3c2512c "$(tdir_avr32)" avr32elf
19170 +eavr32linux.c: $(srcdir)/emulparams/avr32linux.sh \
19171 +  $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
19172 +  $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS}
19173 +       ${GENSCRIPTS} avr32linux "$(tdir_avr32)"
19174  ecoff_i860.c: $(srcdir)/emulparams/coff_i860.sh \
19175    $(srcdir)/emultempl/generic.em $(srcdir)/scripttempl/i860coff.sc ${GEN_DEPENDS}
19176         ${GENSCRIPTS} coff_i860 "$(tdir_coff_i860)"
19177 @@ -1964,7 +2224,9 @@ install-exec-local: ld-new$(EXEEXT)
19178           || $(LIBTOOL) --mode=install $(INSTALL_PROGRAM) ld-new$(EXEEXT) $(DESTDIR)$(tooldir)/bin/ld$(EXEEXT); \
19179         fi
19180
19181 -install-data-local:
19182 +# We want install to imply install-info as per GNU standards, despite the
19183 +# cygnus option.
19184 +install-data-local: install-info
19185         $(mkinstalldirs) $(DESTDIR)$(scriptdir)/ldscripts
19186         for f in ldscripts/*; do \
19187           $(INSTALL_DATA) $$f $(DESTDIR)$(scriptdir)/$$f ; \
19188 --- /dev/null
19189 +++ b/ld/scripttempl/avr32.sc
19190 @@ -0,0 +1,459 @@
19191 +#
19192 +# Unusual variables checked by this code:
19193 +#      NOP - four byte opcode for no-op (defaults to 0)
19194 +#      NO_SMALL_DATA - no .sbss/.sbss2/.sdata/.sdata2 sections if not
19195 +#              empty.
19196 +#      SMALL_DATA_CTOR - .ctors contains small data.
19197 +#      SMALL_DATA_DTOR - .dtors contains small data.
19198 +#      DATA_ADDR - if end-of-text-plus-one-page isn't right for data start
19199 +#      INITIAL_READONLY_SECTIONS - at start of text segment
19200 +#      OTHER_READONLY_SECTIONS - other than .text .init .rodata ...
19201 +#              (e.g., .PARISC.milli)
19202 +#      OTHER_TEXT_SECTIONS - these get put in .text when relocating
19203 +#      OTHER_READWRITE_SECTIONS - other than .data .bss .ctors .sdata ...
19204 +#              (e.g., .PARISC.global)
19205 +#      OTHER_RELRO_SECTIONS - other than .data.rel.ro ...
19206 +#              (e.g. PPC32 .fixup, .got[12])
19207 +#      OTHER_BSS_SECTIONS - other than .bss .sbss ...
19208 +#      OTHER_SECTIONS - at the end
19209 +#      EXECUTABLE_SYMBOLS - symbols that must be defined for an
19210 +#              executable (e.g., _DYNAMIC_LINK)
19211 +#       TEXT_START_ADDR - the first byte of the text segment, after any
19212 +#               headers.
19213 +#       TEXT_BASE_ADDRESS - the first byte of the text segment.
19214 +#      TEXT_START_SYMBOLS - symbols that appear at the start of the
19215 +#              .text section.
19216 +#      DATA_START_SYMBOLS - symbols that appear at the start of the
19217 +#              .data section.
19218 +#      OTHER_GOT_SYMBOLS - symbols defined just before .got.
19219 +#      OTHER_GOT_SECTIONS - sections just after .got.
19220 +#      OTHER_SDATA_SECTIONS - sections just after .sdata.
19221 +#      OTHER_BSS_SYMBOLS - symbols that appear at the start of the
19222 +#              .bss section besides __bss_start.
19223 +#      DATA_PLT - .plt should be in data segment, not text segment.
19224 +#      PLT_BEFORE_GOT - .plt just before .got when .plt is in data segement.
19225 +#      BSS_PLT - .plt should be in bss segment
19226 +#      TEXT_DYNAMIC - .dynamic in text segment, not data segment.
19227 +#      EMBEDDED - whether this is for an embedded system.
19228 +#      SHLIB_TEXT_START_ADDR - if set, add to SIZEOF_HEADERS to set
19229 +#              start address of shared library.
19230 +#      INPUT_FILES - INPUT command of files to always include
19231 +#      WRITABLE_RODATA - if set, the .rodata section should be writable
19232 +#      INIT_START, INIT_END -  statements just before and just after
19233 +#      combination of .init sections.
19234 +#      FINI_START, FINI_END - statements just before and just after
19235 +#      combination of .fini sections.
19236 +#      STACK_ADDR - start of a .stack section.
19237 +#      OTHER_END_SYMBOLS - symbols to place right at the end of the script.
19238 +#      SEPARATE_GOTPLT - if set, .got.plt should be separate output section,
19239 +#              so that .got can be in the RELRO area.  It should be set to
19240 +#              the number of bytes in the beginning of .got.plt which can be
19241 +#              in the RELRO area as well.
19242 +#
19243 +# When adding sections, do note that the names of some sections are used
19244 +# when specifying the start address of the next.
19245 +#
19246 +
19247 +#  Many sections come in three flavours.  There is the 'real' section,
19248 +#  like ".data".  Then there are the per-procedure or per-variable
19249 +#  sections, generated by -ffunction-sections and -fdata-sections in GCC,
19250 +#  and useful for --gc-sections, which for a variable "foo" might be
19251 +#  ".data.foo".  Then there are the linkonce sections, for which the linker
19252 +#  eliminates duplicates, which are named like ".gnu.linkonce.d.foo".
19253 +#  The exact correspondences are:
19254 +#
19255 +#  Section     Linkonce section
19256 +#  .text       .gnu.linkonce.t.foo
19257 +#  .rodata     .gnu.linkonce.r.foo
19258 +#  .data       .gnu.linkonce.d.foo
19259 +#  .bss                .gnu.linkonce.b.foo
19260 +#  .sdata      .gnu.linkonce.s.foo
19261 +#  .sbss       .gnu.linkonce.sb.foo
19262 +#  .sdata2     .gnu.linkonce.s2.foo
19263 +#  .sbss2      .gnu.linkonce.sb2.foo
19264 +#  .debug_info .gnu.linkonce.wi.foo
19265 +#  .tdata      .gnu.linkonce.td.foo
19266 +#  .tbss       .gnu.linkonce.tb.foo
19267 +#
19268 +#  Each of these can also have corresponding .rel.* and .rela.* sections.
19269 +
19270 +test -z "$ENTRY" && ENTRY=_start
19271 +test -z "${BIG_OUTPUT_FORMAT}" && BIG_OUTPUT_FORMAT=${OUTPUT_FORMAT}
19272 +test -z "${LITTLE_OUTPUT_FORMAT}" && LITTLE_OUTPUT_FORMAT=${OUTPUT_FORMAT}
19273 +if [ -z "$MACHINE" ]; then OUTPUT_ARCH=${ARCH}; else OUTPUT_ARCH=${ARCH}:${MACHINE}; fi
19274 +test -z "${ELFSIZE}" && ELFSIZE=32
19275 +test -z "${ALIGNMENT}" && ALIGNMENT="${ELFSIZE} / 8"
19276 +test "$LD_FLAG" = "N" && DATA_ADDR=.
19277 +test -n "$CREATE_SHLIB$CREATE_PIE" && test -n "$SHLIB_DATA_ADDR" && COMMONPAGESIZE=""
19278 +test -z "$CREATE_SHLIB$CREATE_PIE" && test -n "$DATA_ADDR" && COMMONPAGESIZE=""
19279 +test -n "$RELRO_NOW" && unset SEPARATE_GOTPLT
19280 +if test -n "$RELOCATING"; then
19281 +  RO_REGION="${RO_VMA_REGION+ >}${RO_VMA_REGION}${RO_LMA_REGION+ AT>}${RO_LMA_REGION}"
19282 +  RW_REGION="${RW_VMA_REGION+ >}${RW_VMA_REGION}${RW_LMA_REGION+ AT>}${RW_LMA_REGION}"
19283 +  RW_BSS_REGION="${RW_VMA_REGION+ >}${RW_VMA_REGION}"
19284 +else
19285 +  RO_REGION=""
19286 +  RW_REGION=""
19287 +  RW_BSS_REGION=""
19288 +fi
19289 +INTERP=".interp       ${RELOCATING-0} : { *(.interp) }${RO_REGION}"
19290 +PLT=".plt          ${RELOCATING-0} : { *(.plt) }"
19291 +if test -z "$GOT"; then
19292 +  if test -z "$SEPARATE_GOTPLT"; then
19293 +    GOT=".got          ${RELOCATING-0} : { *(.got.plt) *(.got) }"
19294 +  else
19295 +    GOT=".got          ${RELOCATING-0} : { *(.got) }"
19296 +    GOTPLT="${RELOCATING+${DATA_SEGMENT_RELRO_GOTPLT_END}}
19297 +  .got.plt      ${RELOCATING-0} : { *(.got.plt) }"
19298 +  fi
19299 +fi
19300 +DALIGN=".dalign        : { . = ALIGN(${DATA_SEGMENT_ALIGN}); PROVIDE(_data_lma = .); }${RO_REGION}"
19301 +BALIGN=".balign        : { . = ALIGN(${BSS_ALIGNMENT}); _edata = .; }${RW_REGION}"
19302 +DYNAMIC=".dynamic      ${RELOCATING-0} : { *(.dynamic) }"
19303 +RODATA=".rodata       ${RELOCATING-0} : { *(.rodata${RELOCATING+ .rodata.* .gnu.linkonce.r.*}) }"
19304 +DATARELRO=".data.rel.ro : { *(.data.rel.ro.local) *(.data.rel.ro*) }${RW_REGION}"
19305 +STACKNOTE="/DISCARD/ : { *(.note.GNU-stack) }"
19306 +if test -z "${NO_SMALL_DATA}"; then
19307 +  SBSS=".sbss         ${RELOCATING-0} :
19308 +  {
19309 +    ${RELOCATING+PROVIDE (__sbss_start = .);}
19310 +    ${RELOCATING+PROVIDE (___sbss_start = .);}
19311 +    ${CREATE_SHLIB+*(.sbss2 .sbss2.* .gnu.linkonce.sb2.*)}
19312 +    *(.dynsbss)
19313 +    *(.sbss${RELOCATING+ .sbss.* .gnu.linkonce.sb.*})
19314 +    *(.scommon)
19315 +    ${RELOCATING+PROVIDE (__sbss_end = .);}
19316 +    ${RELOCATING+PROVIDE (___sbss_end = .);}
19317 +  }${RW_BSS_REGION}"
19318 +  SBSS2=".sbss2        ${RELOCATING-0} : { *(.sbss2${RELOCATING+ .sbss2.* .gnu.linkonce.sb2.*}) }${RW_REGION}"
19319 +  SDATA="/* We want the small data sections together, so single-instruction offsets
19320 +     can access them all, and initialized data all before uninitialized, so
19321 +     we can shorten the on-disk segment size.  */
19322 +  .sdata        ${RELOCATING-0} :
19323 +  {
19324 +    ${RELOCATING+${SDATA_START_SYMBOLS}}
19325 +    ${CREATE_SHLIB+*(.sdata2 .sdata2.* .gnu.linkonce.s2.*)}
19326 +    *(.sdata${RELOCATING+ .sdata.* .gnu.linkonce.s.*})
19327 +  }${RW_REGION}"
19328 +  SDATA2=".sdata2       ${RELOCATING-0} : { *(.sdata2${RELOCATING+ .sdata2.* .gnu.linkonce.s2.*}) }${RW_REGION}"
19329 +  REL_SDATA=".rel.sdata    ${RELOCATING-0} : { *(.rel.sdata${RELOCATING+ .rel.sdata.* .rel.gnu.linkonce.s.*}) }${RO_REGION}
19330 +  .rela.sdata   ${RELOCATING-0} : { *(.rela.sdata${RELOCATING+ .rela.sdata.* .rela.gnu.linkonce.s.*}) }"
19331 +  REL_SBSS=".rel.sbss     ${RELOCATING-0} : { *(.rel.sbss${RELOCATING+ .rel.sbss.* .rel.gnu.linkonce.sb.*}) }${RO_REGION}
19332 +  .rela.sbss    ${RELOCATING-0} : { *(.rela.sbss${RELOCATING+ .rela.sbss.* .rela.gnu.linkonce.sb.*}) }${RO_REGION}"
19333 +  REL_SDATA2=".rel.sdata2   ${RELOCATING-0} : { *(.rel.sdata2${RELOCATING+ .rel.sdata2.* .rel.gnu.linkonce.s2.*}) }${RO_REGION}
19334 +  .rela.sdata2  ${RELOCATING-0} : { *(.rela.sdata2${RELOCATING+ .rela.sdata2.* .rela.gnu.linkonce.s2.*}) }${RO_REGION}"
19335 +  REL_SBSS2=".rel.sbss2    ${RELOCATING-0} : { *(.rel.sbss2${RELOCATING+ .rel.sbss2.* .rel.gnu.linkonce.sb2.*}) }${RO_REGION}
19336 +  .rela.sbss2   ${RELOCATING-0} : { *(.rela.sbss2${RELOCATING+ .rela.sbss2.* .rela.gnu.linkonce.sb2.*}) }${RO_REGION}"
19337 +else
19338 +  NO_SMALL_DATA=" "
19339 +fi
19340 +test -n "$SEPARATE_GOTPLT" && SEPARATE_GOTPLT=" "
19341 +CTOR=".ctors        ${CONSTRUCTING-0} :
19342 +  {
19343 +    ${CONSTRUCTING+${CTOR_START}}
19344 +    /* gcc uses crtbegin.o to find the start of
19345 +       the constructors, so we make sure it is
19346 +       first.  Because this is a wildcard, it
19347 +       doesn't matter if the user does not
19348 +       actually link against crtbegin.o; the
19349 +       linker won't look for a file to match a
19350 +       wildcard.  The wildcard also means that it
19351 +       doesn't matter which directory crtbegin.o
19352 +       is in.  */
19353 +
19354 +    KEEP (*crtbegin*.o(.ctors))
19355 +
19356 +    /* We don't want to include the .ctor section from
19357 +       from the crtend.o file until after the sorted ctors.
19358 +       The .ctor section from the crtend file contains the
19359 +       end of ctors marker and it must be last */
19360 +
19361 +    KEEP (*(EXCLUDE_FILE (*crtend*.o $OTHER_EXCLUDE_FILES) .ctors))
19362 +    KEEP (*(SORT(.ctors.*)))
19363 +    KEEP (*(.ctors))
19364 +    ${CONSTRUCTING+${CTOR_END}}
19365 +  }"
19366 +DTOR=".dtors        ${CONSTRUCTING-0} :
19367 +  {
19368 +    ${CONSTRUCTING+${DTOR_START}}
19369 +    KEEP (*crtbegin*.o(.dtors))
19370 +    KEEP (*(EXCLUDE_FILE (*crtend*.o $OTHER_EXCLUDE_FILES) .dtors))
19371 +    KEEP (*(SORT(.dtors.*)))
19372 +    KEEP (*(.dtors))
19373 +    ${CONSTRUCTING+${DTOR_END}}
19374 +  }"
19375 +STACK=".stack        ${RELOCATING-0}${RELOCATING+${STACK_ADDR}} :
19376 +  {
19377 +    ${RELOCATING+_stack = .;}
19378 +    *(.stack)
19379 +    ${RELOCATING+${STACK_SIZE+. = ${STACK_SIZE};}}
19380 +    ${RELOCATING+_estack = .;}
19381 +  }${RW_BSS_REGION}"
19382 +
19383 +# if this is for an embedded system, don't add SIZEOF_HEADERS.
19384 +if [ -z "$EMBEDDED" ]; then
19385 +   test -z "${TEXT_BASE_ADDRESS}" && TEXT_BASE_ADDRESS="${TEXT_START_ADDR} + SIZEOF_HEADERS"
19386 +else
19387 +   test -z "${TEXT_BASE_ADDRESS}" && TEXT_BASE_ADDRESS="${TEXT_START_ADDR}"
19388 +fi
19389 +
19390 +cat <<EOF
19391 +OUTPUT_FORMAT("${OUTPUT_FORMAT}", "${BIG_OUTPUT_FORMAT}",
19392 +             "${LITTLE_OUTPUT_FORMAT}")
19393 +OUTPUT_ARCH(${OUTPUT_ARCH})
19394 +ENTRY(${ENTRY})
19395 +
19396 +${RELOCATING+${LIB_SEARCH_DIRS}}
19397 +${RELOCATING+/* Do we need any of these for elf?
19398 +   __DYNAMIC = 0; ${STACKZERO+${STACKZERO}} ${SHLIB_PATH+${SHLIB_PATH}}  */}
19399 +${RELOCATING+${EXECUTABLE_SYMBOLS}}
19400 +${RELOCATING+${INPUT_FILES}}
19401 +${RELOCATING- /* For some reason, the Solaris linker makes bad executables
19402 +  if gld -r is used and the intermediate file has sections starting
19403 +  at non-zero addresses.  Could be a Solaris ld bug, could be a GNU ld
19404 +  bug.  But for now assigning the zero vmas works.  */}
19405 +
19406 +${RELOCATING+${MEMORY}}
19407 +
19408 +SECTIONS
19409 +{
19410 +  /* Read-only sections, merged into text segment: */
19411 +  ${CREATE_SHLIB-${CREATE_PIE-${RELOCATING+PROVIDE (__executable_start = ${TEXT_START_ADDR}); . = ${TEXT_BASE_ADDRESS};}}}
19412 +  ${PADDING}
19413 +  ${CREATE_SHLIB+${RELOCATING+. = ${SHLIB_TEXT_START_ADDR:-0} + SIZEOF_HEADERS;}}
19414 +  ${CREATE_PIE+${RELOCATING+. = ${SHLIB_TEXT_START_ADDR:-0} + SIZEOF_HEADERS;}}
19415 +  ${CREATE_SHLIB-${INTERP}}
19416 +  ${INITIAL_READONLY_SECTIONS}
19417 +  ${TEXT_DYNAMIC+${DYNAMIC}${RO_REGION}}
19418 +  .hash         ${RELOCATING-0} : { *(.hash) }${RO_REGION}
19419 +  .dynsym       ${RELOCATING-0} : { *(.dynsym) }${RO_REGION}
19420 +  .dynstr       ${RELOCATING-0} : { *(.dynstr) }${RO_REGION}
19421 +  .gnu.version  ${RELOCATING-0} : { *(.gnu.version) }${RO_REGION}
19422 +  .gnu.version_d ${RELOCATING-0}: { *(.gnu.version_d) }${RO_REGION}
19423 +  .gnu.version_r ${RELOCATING-0}: { *(.gnu.version_r) }${RO_REGION}
19424 +
19425 +EOF
19426 +if [ "x$COMBRELOC" = x ]; then
19427 +  COMBRELOCCAT=cat
19428 +else
19429 +  COMBRELOCCAT="cat > $COMBRELOC"
19430 +fi
19431 +eval $COMBRELOCCAT <<EOF
19432 +  .rel.init     ${RELOCATING-0} : { *(.rel.init) }${RO_REGION}
19433 +  .rela.init    ${RELOCATING-0} : { *(.rela.init) }${RO_REGION}
19434 +  .rel.text     ${RELOCATING-0} : { *(.rel.text${RELOCATING+ .rel.text.* .rel.gnu.linkonce.t.*}) }${RO_REGION}
19435 +  .rela.text    ${RELOCATING-0} : { *(.rela.text${RELOCATING+ .rela.text.* .rela.gnu.linkonce.t.*}) }${RO_REGION}
19436 +  .rel.fini     ${RELOCATING-0} : { *(.rel.fini) }${RO_REGION}
19437 +  .rela.fini    ${RELOCATING-0} : { *(.rela.fini) }${RO_REGION}
19438 +  .rel.rodata   ${RELOCATING-0} : { *(.rel.rodata${RELOCATING+ .rel.rodata.* .rel.gnu.linkonce.r.*}) }${RO_REGION}
19439 +  .rela.rodata  ${RELOCATING-0} : { *(.rela.rodata${RELOCATING+ .rela.rodata.* .rela.gnu.linkonce.r.*}) }${RO_REGION}
19440 +  ${OTHER_READONLY_RELOC_SECTIONS}
19441 +  .rel.data.rel.ro ${RELOCATING-0} : { *(.rel.data.rel.ro${RELOCATING+*}) }${RO_REGION}
19442 +  .rela.data.rel.ro ${RELOCATING-0} : { *(.rel.data.rel.ro${RELOCATING+*}) }${RO_REGION}
19443 +  .rel.data     ${RELOCATING-0} : { *(.rel.data${RELOCATING+ .rel.data.* .rel.gnu.linkonce.d.*}) }${RO_REGION}
19444 +  .rela.data    ${RELOCATING-0} : { *(.rela.data${RELOCATING+ .rela.data.* .rela.gnu.linkonce.d.*}) }${RO_REGION}
19445 +  .rel.tdata   ${RELOCATING-0} : { *(.rel.tdata${RELOCATING+ .rel.tdata.* .rel.gnu.linkonce.td.*}) }${RO_REGION}
19446 +  .rela.tdata  ${RELOCATING-0} : { *(.rela.tdata${RELOCATING+ .rela.tdata.* .rela.gnu.linkonce.td.*}) }${RO_REGION}
19447 +  .rel.tbss    ${RELOCATING-0} : { *(.rel.tbss${RELOCATING+ .rel.tbss.* .rel.gnu.linkonce.tb.*}) }${RO_REGION}
19448 +  .rela.tbss   ${RELOCATING-0} : { *(.rela.tbss${RELOCATING+ .rela.tbss.* .rela.gnu.linkonce.tb.*}) }${RO_REGION}
19449 +  .rel.ctors    ${RELOCATING-0} : { *(.rel.ctors) }${RO_REGION}
19450 +  .rela.ctors   ${RELOCATING-0} : { *(.rela.ctors) }${RO_REGION}
19451 +  .rel.dtors    ${RELOCATING-0} : { *(.rel.dtors) }${RO_REGION}
19452 +  .rela.dtors   ${RELOCATING-0} : { *(.rela.dtors) }${RO_REGION}
19453 +  .rel.got      ${RELOCATING-0} : { *(.rel.got) }${RO_REGION}
19454 +  .rela.got     ${RELOCATING-0} : { *(.rela.got) }${RO_REGION}
19455 +  ${OTHER_GOT_RELOC_SECTIONS}
19456 +  ${REL_SDATA}
19457 +  ${REL_SBSS}
19458 +  ${REL_SDATA2}
19459 +  ${REL_SBSS2}
19460 +  .rel.bss      ${RELOCATING-0} : { *(.rel.bss${RELOCATING+ .rel.bss.* .rel.gnu.linkonce.b.*}) }${RO_REGION}
19461 +  .rela.bss     ${RELOCATING-0} : { *(.rela.bss${RELOCATING+ .rela.bss.* .rela.gnu.linkonce.b.*}) }${RO_REGION}
19462 +EOF
19463 +if [ -n "$COMBRELOC" ]; then
19464 +cat <<EOF
19465 +  .rel.dyn      ${RELOCATING-0} :
19466 +    {
19467 +EOF
19468 +sed -e '/^[    ]*[{}][         ]*$/d;/:[       ]*$/d;/\.rela\./d;s/^.*: { *\(.*\)}$/      \1/' $COMBRELOC
19469 +cat <<EOF
19470 +    }${RO_REGION}
19471 +  .rela.dyn     ${RELOCATING-0} :
19472 +    {
19473 +EOF
19474 +sed -e '/^[    ]*[{}][         ]*$/d;/:[       ]*$/d;/\.rel\./d;s/^.*: { *\(.*\)}/      \1/' $COMBRELOC
19475 +cat <<EOF
19476 +    }${RO_REGION}
19477 +EOF
19478 +fi
19479 +cat <<EOF
19480 +  .rel.plt      ${RELOCATING-0} : { *(.rel.plt) }${RO_REGION}
19481 +  .rela.plt     ${RELOCATING-0} : { *(.rela.plt) }${RO_REGION}
19482 +  ${OTHER_PLT_RELOC_SECTIONS}
19483 +
19484 +  .init         ${RELOCATING-0} :
19485 +  {
19486 +    ${RELOCATING+${INIT_START}}
19487 +    KEEP (*(.init))
19488 +    ${RELOCATING+${INIT_END}}
19489 +  }${RO_REGION} =${NOP-0}
19490 +
19491 +  ${DATA_PLT-${BSS_PLT-${PLT}${RO_REGION}}}
19492 +  .text         ${RELOCATING-0} :
19493 +  {
19494 +    ${RELOCATING+${TEXT_START_SYMBOLS}}
19495 +    *(.text .stub${RELOCATING+ .text.* .gnu.linkonce.t.*})
19496 +    KEEP (*(.text.*personality*))
19497 +    /* .gnu.warning sections are handled specially by elf32.em.  */
19498 +    *(.gnu.warning)
19499 +    ${RELOCATING+${OTHER_TEXT_SECTIONS}}
19500 +  }${RO_REGION} =${NOP-0}
19501 +  .fini         ${RELOCATING-0} :
19502 +  {
19503 +    ${RELOCATING+${FINI_START}}
19504 +    KEEP (*(.fini))
19505 +    ${RELOCATING+${FINI_END}}
19506 +  }${RO_REGION} =${NOP-0}
19507 +  ${RELOCATING+PROVIDE (__etext = .);}
19508 +  ${RELOCATING+PROVIDE (_etext = .);}
19509 +  ${RELOCATING+PROVIDE (etext = .);}
19510 +  ${WRITABLE_RODATA-${RODATA}${RO_REGION}}
19511 +  .rodata1      ${RELOCATING-0} : { *(.rodata1) }${RO_REGION}
19512 +  ${CREATE_SHLIB-${SDATA2}}
19513 +  ${CREATE_SHLIB-${SBSS2}}
19514 +  ${OTHER_READONLY_SECTIONS}
19515 +  .eh_frame_hdr : { *(.eh_frame_hdr) }${RO_REGION}
19516 +  .eh_frame     ${RELOCATING-0} : ONLY_IF_RO { KEEP (*(.eh_frame)) }${RO_REGION}
19517 +  .gcc_except_table ${RELOCATING-0} : ONLY_IF_RO { KEEP (*(.gcc_except_table)) *(.gcc_except_table.*) }${RO_REGION}
19518 +
19519 +  ${RELOCATING+${DALIGN}}
19520 +  ${RELOCATING+PROVIDE (_data = ORIGIN(${RW_VMA_REGION}));}
19521 +  . = ORIGIN(${RW_VMA_REGION});
19522 +  /* Exception handling  */
19523 +  .eh_frame     ${RELOCATING-0} : ONLY_IF_RW { KEEP (*(.eh_frame)) }${RW_REGION}
19524 +  .gcc_except_table ${RELOCATING-0} : ONLY_IF_RW { KEEP (*(.gcc_except_table)) *(.gcc_except_table.*) }${RW_REGION}
19525 +
19526 +  /* Thread Local Storage sections  */
19527 +  .tdata       ${RELOCATING-0} : { *(.tdata${RELOCATING+ .tdata.* .gnu.linkonce.td.*}) }${RW_REGION}
19528 +  .tbss                ${RELOCATING-0} : { *(.tbss${RELOCATING+ .tbss.* .gnu.linkonce.tb.*})${RELOCATING+ *(.tcommon)} }${RW_BSS_REGION}
19529 +
19530 +  /* Ensure the __preinit_array_start label is properly aligned.  We
19531 +     could instead move the label definition inside the section, but
19532 +     the linker would then create the section even if it turns out to
19533 +     be empty, which isn't pretty.  */
19534 +  ${RELOCATING+${CREATE_SHLIB-PROVIDE (__preinit_array_start = ALIGN(${ALIGNMENT}));}}
19535 +  .preinit_array   ${RELOCATING-0} : { KEEP (*(.preinit_array)) }${RW_REGION}
19536 +  ${RELOCATING+${CREATE_SHLIB-PROVIDE (__preinit_array_end = .);}}
19537 +
19538 +  ${RELOCATING+${CREATE_SHLIB-PROVIDE (__init_array_start = .);}}
19539 +  .init_array   ${RELOCATING-0} : { KEEP (*(.init_array)) }${RW_REGION}
19540 +  ${RELOCATING+${CREATE_SHLIB-PROVIDE (__init_array_end = .);}}
19541 +
19542 +  ${RELOCATING+${CREATE_SHLIB-PROVIDE (__fini_array_start = .);}}
19543 +  .fini_array   ${RELOCATING-0} : { KEEP (*(.fini_array)) }${RW_REGION}
19544 +  ${RELOCATING+${CREATE_SHLIB-PROVIDE (__fini_array_end = .);}}
19545 +
19546 +  ${SMALL_DATA_CTOR-${RELOCATING+${CTOR}${RW_REGION}}}
19547 +  ${SMALL_DATA_DTOR-${RELOCATING+${DTOR}${RW_REGION}}}
19548 +  .jcr          ${RELOCATING-0} : { KEEP (*(.jcr)) }${RW_REGION}
19549 +
19550 +  ${RELOCATING+${DATARELRO}}
19551 +  ${OTHER_RELRO_SECTIONS}
19552 +  ${TEXT_DYNAMIC-${DYNAMIC}${RW_REGION}}
19553 +  ${NO_SMALL_DATA+${RELRO_NOW+${GOT}${RW_REGION}}}
19554 +  ${NO_SMALL_DATA+${RELRO_NOW-${SEPARATE_GOTPLT+${GOT}${RW_REGION}}}}
19555 +  ${NO_SMALL_DATA+${RELRO_NOW-${SEPARATE_GOTPLT+${GOTPLT}${RW_REGION}}}}
19556 +  ${RELOCATING+${DATA_SEGMENT_RELRO_END}}
19557 +  ${NO_SMALL_DATA+${RELRO_NOW-${SEPARATE_GOTPLT-${GOT}${RW_REGION}}}}
19558 +
19559 +  ${DATA_PLT+${PLT_BEFORE_GOT-${PLT}${RW_REGION}}}
19560 +
19561 +  .data         ${RELOCATING-0} :
19562 +  {
19563 +    ${RELOCATING+${DATA_START_SYMBOLS}}
19564 +    *(.data${RELOCATING+ .data.* .gnu.linkonce.d.*})
19565 +    KEEP (*(.gnu.linkonce.d.*personality*))
19566 +    ${CONSTRUCTING+SORT(CONSTRUCTORS)}
19567 +  }${RW_REGION}
19568 +  .data1        ${RELOCATING-0} : { *(.data1) }${RW_REGION}
19569 +  ${WRITABLE_RODATA+${RODATA}${RW_REGION}}
19570 +  ${OTHER_READWRITE_SECTIONS}
19571 +  ${SMALL_DATA_CTOR+${RELOCATING+${CTOR}${RW_REGION}}}
19572 +  ${SMALL_DATA_DTOR+${RELOCATING+${DTOR}${RW_REGION}}}
19573 +  ${DATA_PLT+${PLT_BEFORE_GOT+${PLT}${RW_REGION}}}
19574 +  ${RELOCATING+${OTHER_GOT_SYMBOLS}}
19575 +  ${NO_SMALL_DATA-${GOT}${RW_REGION}}
19576 +  ${OTHER_GOT_SECTIONS}
19577 +  ${SDATA}
19578 +  ${OTHER_SDATA_SECTIONS}
19579 +  ${RELOCATING+${BALIGN}}
19580 +  ${RELOCATING+_edata = .;}
19581 +  ${RELOCATING+PROVIDE (edata = .);}
19582 +  ${RELOCATING+__bss_start = .;}
19583 +  ${RELOCATING+${OTHER_BSS_SYMBOLS}}
19584 +  ${SBSS}
19585 +  ${BSS_PLT+${PLT}${RW_REGION}}
19586 +  .bss          ${RELOCATING-0} :
19587 +  {
19588 +   *(.dynbss)
19589 +   *(.bss${RELOCATING+ .bss.* .gnu.linkonce.b.*})
19590 +   *(COMMON)
19591 +   /* Align here to ensure that the .bss section occupies space up to
19592 +      _end.  Align after .bss to ensure correct alignment even if the
19593 +      .bss section disappears because there are no input sections.  */
19594 +   ${RELOCATING+. = ALIGN(${BSS_ALIGNMENT});}
19595 +  }${RW_BSS_REGION}
19596 +  ${OTHER_BSS_SECTIONS}
19597 +  ${RELOCATING+. = ALIGN(${BSS_ALIGNMENT});}
19598 +  ${RELOCATING+_end = .;}
19599 +  ${RELOCATING+${OTHER_BSS_END_SYMBOLS}}
19600 +  ${RELOCATING+PROVIDE (end = .);}
19601 +  ${RELOCATING+${DATA_SEGMENT_END}}
19602 +
19603 +  /* Stabs debugging sections.  */
19604 +  .stab          0 : { *(.stab) }
19605 +  .stabstr       0 : { *(.stabstr) }
19606 +  .stab.excl     0 : { *(.stab.excl) }
19607 +  .stab.exclstr  0 : { *(.stab.exclstr) }
19608 +  .stab.index    0 : { *(.stab.index) }
19609 +  .stab.indexstr 0 : { *(.stab.indexstr) }
19610 +
19611 +  .comment       0 : { *(.comment) }
19612 +
19613 +  /* DWARF debug sections.
19614 +     Symbols in the DWARF debugging sections are relative to the beginning
19615 +     of the section so we begin them at 0.  */
19616 +
19617 +  /* DWARF 1 */
19618 +  .debug          0 : { *(.debug) }
19619 +  .line           0 : { *(.line) }
19620 +
19621 +  /* GNU DWARF 1 extensions */
19622 +  .debug_srcinfo  0 : { *(.debug_srcinfo) }
19623 +  .debug_sfnames  0 : { *(.debug_sfnames) }
19624 +
19625 +  /* DWARF 1.1 and DWARF 2 */
19626 +  .debug_aranges  0 : { *(.debug_aranges) }
19627 +  .debug_pubnames 0 : { *(.debug_pubnames) }
19628 +
19629 +  /* DWARF 2 */
19630 +  .debug_info     0 : { *(.debug_info .gnu.linkonce.wi.*) }
19631 +  .debug_abbrev   0 : { *(.debug_abbrev) }
19632 +  .debug_line     0 : { *(.debug_line) }
19633 +  .debug_frame    0 : { *(.debug_frame) }
19634 +  .debug_str      0 : { *(.debug_str) }
19635 +  .debug_loc      0 : { *(.debug_loc) }
19636 +  .debug_macinfo  0 : { *(.debug_macinfo) }
19637 +
19638 +  /* SGI/MIPS DWARF 2 extensions */
19639 +  .debug_weaknames 0 : { *(.debug_weaknames) }
19640 +  .debug_funcnames 0 : { *(.debug_funcnames) }
19641 +  .debug_typenames 0 : { *(.debug_typenames) }
19642 +  .debug_varnames  0 : { *(.debug_varnames) }
19643 +
19644 +  ${STACK_ADDR+${STACK}}
19645 +  ${OTHER_SECTIONS}
19646 +  ${RELOCATING+${OTHER_END_SYMBOLS}}
19647 +  ${RELOCATING+${STACKNOTE}}
19648 +}
19649 +EOF
19650 --- /dev/null
19651 +++ b/ld/testsuite/ld-avr32/avr32.exp
19652 @@ -0,0 +1,25 @@
19653 +# Expect script for AVR32 ELF linker tests.
19654 +#   Copyright 2004-2006 Atmel Corporation.
19655 +#
19656 +# This file is free software; you can redistribute it and/or modify
19657 +# it under the terms of the GNU General Public License as published by
19658 +# the Free Software Foundation; either version 2 of the License, or
19659 +# (at your option) any later version.
19660 +#
19661 +# This program is distributed in the hope that it will be useful,
19662 +# but WITHOUT ANY WARRANTY; without even the implied warranty of
19663 +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
19664 +# GNU General Public License for more details.
19665 +#
19666 +# You should have received a copy of the GNU General Public License
19667 +# along with this program; if not, write to the Free Software
19668 +# Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
19669 +#
19670 +# Written by Haavard Skinnemoen (hskinnemoen@atmel.com)
19671 +#
19672 +
19673 +if ![istarget avr32-*-*] {
19674 +    return
19675 +}
19676 +
19677 +run_dump_test "pcrel"
19678 --- /dev/null
19679 +++ b/ld/testsuite/ld-avr32/pcrel.d
19680 @@ -0,0 +1,74 @@
19681 +#name: AVR32 ELF PC-relative external relocs
19682 +#source: symbols.s
19683 +#source: ../../../gas/testsuite/gas/avr32/pcrel.s
19684 +#ld: -T $srcdir/$subdir/pcrel.ld
19685 +#objdump: -d
19686 +
19687 +.*:     file format elf.*avr32.*
19688 +
19689 +Disassembly of section .text:
19690 +
19691 +a0000000 <_start>:
19692 +a0000000:      d7 03           nop
19693 +a0000002:      d7 03           nop
19694 +
19695 +a0000004 <test_rjmp>:
19696 +a0000004:      d7 03           nop
19697 +a0000006:      c0 28           rjmp a000000a <test_rjmp\+0x6>
19698 +a0000008:      d7 03           nop
19699 +a000000a:      e0 8f 01 fb     bral a0000400 <extsym10>
19700 +
19701 +a000000e <test_rcall>:
19702 +a000000e:      d7 03           nop
19703 +a0000010 <test_rcall2>:
19704 +a0000010:      c0 2c           rcall a0000014 <test_rcall2\+0x4>
19705 +a0000012:      d7 03           nop
19706 +a0000014:      ee b0 ff f6     rcall a0200000 <extsym21>
19707 +
19708 +a0000018 <test_branch>:
19709 +a0000018:      c0 31           brne a000001e <test_branch\+0x6>
19710 +a000001a:      fe 9f ff ff     bral a0000018 <test_branch>
19711 +a000001e:      ee 90 ff f1     breq a0200000 <extsym21>
19712 +
19713 +a0000022 <test_lddpc>:
19714 +a0000022:      48 30           lddpc r0,a000002c <sym1>
19715 +a0000024:      48 20           lddpc r0,a000002c <sym1>
19716 +a0000026:      fe f0 7f da     ld.w r0,pc\[32730\]
19717 +       ...
19718 +
19719 +a000002c <sym1>:
19720 +a000002c:      d7 03           nop
19721 +a000002e:      d7 03           nop
19722 +
19723 +a0000030 <test_local>:
19724 +a0000030:      48 20           lddpc r0,a0000038 <test_local\+0x8>
19725 +a0000032:      48 30           lddpc r0,a000003c <test_local\+0xc>
19726 +a0000034:      48 20           lddpc r0,a000003c <test_local\+0xc>
19727 +a0000036:      00 00           add r0,r0
19728 +a0000038:      d7 03           nop
19729 +a000003a:      d7 03           nop
19730 +a000003c:      d7 03           nop
19731 +a000003e:      d7 03           nop
19732 +
19733 +Disassembly of section \.text\.init:
19734 +a0000040 <test_inter_section>:
19735 +a0000040:      fe b0 ff e7     rcall a000000e <test_rcall>
19736 +a0000044:      d7 03           nop
19737 +a0000046:      fe b0 ff e4     rcall a000000e <test_rcall>
19738 +a000004a:      fe b0 ff e3     rcall a0000010 <test_rcall2>
19739 +a000004e:      d7 03           nop
19740 +a0000050:      fe b0 ff e0     rcall a0000010 <test_rcall2>
19741 +
19742 +Disassembly of section \.text\.pcrel10:
19743 +
19744 +a0000400 <extsym10>:
19745 +a0000400:      d7 03           nop
19746 +
19747 +Disassembly of section \.text\.pcrel16:
19748 +
19749 +a0008000 <extsym16>:
19750 +a0008000:      d7 03           nop
19751 +
19752 +Disassembly of section \.text\.pcrel21:
19753 +a0200000 <extsym21>:
19754 +a0200000:      d7 03           nop
19755 --- /dev/null
19756 +++ b/ld/testsuite/ld-avr32/pcrel.ld
19757 @@ -0,0 +1,23 @@
19758 +ENTRY(_start)
19759 +SECTIONS
19760 +{
19761 +       .text 0xa0000000:
19762 +       {
19763 +               *(.text)
19764 +       }
19765 +
19766 +       .text.pcrel10 0xa0000400:
19767 +       {
19768 +               *(.text.pcrel10)
19769 +       }
19770 +
19771 +       .text.pcrel16 0xa0008000:
19772 +       {
19773 +               *(.text.pcrel16)
19774 +       }
19775 +
19776 +       .text.pcrel21 0xa0200000:
19777 +       {
19778 +               *(.text.pcrel21)
19779 +       }
19780 +}
19781 --- /dev/null
19782 +++ b/ld/testsuite/ld-avr32/symbols.s
19783 @@ -0,0 +1,20 @@
19784 +       .text
19785 +       .global _start
19786 +_start:
19787 +       nop
19788 +       nop
19789 +
19790 +       .section .text.pcrel10,"ax"
19791 +       .global extsym10
19792 +extsym10:
19793 +       nop
19794 +
19795 +       .section .text.pcrel16,"ax"
19796 +       .global extsym16
19797 +extsym16:
19798 +       nop
19799 +
19800 +       .section .text.pcrel21,"ax"
19801 +       .global extsym21
19802 +extsym21:
19803 +       nop
19804 --- /dev/null
19805 +++ b/opcodes/avr32-asm.c
19806 @@ -0,0 +1,244 @@
19807 +/* Assembler interface for AVR32.
19808 +   Copyright 2005,2006,2007,2008,2009 Atmel Corporation.
19809 +
19810 +   Written by Haavard Skinnemoen, Atmel Norway, <hskinnemoen@atmel.com>
19811 +
19812 +   This file is part of libopcodes.
19813 +
19814 +   This program is free software; you can redistribute it and/or
19815 +   modify it under the terms of the GNU General Public License as
19816 +   published by the Free Software Foundation; either version 2 of the
19817 +   License, or (at your option) any later version.
19818 +
19819 +   This program is distributed in the hope that it will be useful, but
19820 +   WITHOUT ANY WARRANTY; without even the implied warranty of
19821 +   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
19822 +   General Public License for more details.
19823 +
19824 +   You should have received a copy of the GNU General Public License
19825 +   along with this program; if not, write to the Free Software
19826 +   Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA
19827 +   02111-1307, USA.  */
19828 +
19829 +#include <string.h>
19830 +
19831 +#include "avr32-opc.h"
19832 +#include "avr32-asm.h"
19833 +
19834 +/* Structure for a register hash table entry.  */
19835 +struct reg_entry
19836 +{
19837 +  const char   *name;
19838 +  int          number;
19839 +};
19840 +
19841 +/* Integer Registers.  */
19842 +static const struct reg_entry reg_table[] =
19843 +  {
19844 +    /* Primary names (used by the disassembler) */
19845 +    { "r0",   0 }, { "r1",   1 }, { "r2",   2 }, { "r3",   3 },
19846 +    { "r4",   4 }, { "r5",   5 }, { "r6",   6 }, { "r7",   7 },
19847 +    { "r8",   8 }, { "r9",   9 }, { "r10", 10 }, { "r11", 11 },
19848 +    { "r12", 12 }, { "sp",  13 }, { "lr",  14 }, { "pc",  15 },
19849 +    /* Alternatives to sp, lr and pc.  */
19850 +    { "r13", 13 }, { "r14", 14 }, { "r15", 15 },
19851 +  };
19852 +#define AVR32_NR_INTREGS (sizeof(reg_table)/sizeof(reg_table[0]))
19853 +
19854 +/* Coprocessor Registers.  */
19855 +static const struct reg_entry cr_table[] =
19856 +  {
19857 +    { "cr0",   0 }, { "cr1",   1 }, { "cr2",   2 }, { "cr3",   3 },
19858 +    { "cr4",   4 }, { "cr5",   5 }, { "cr6",   6 }, { "cr7",   7 },
19859 +    { "cr8",   8 }, { "cr9",   9 }, { "cr10", 10 }, { "cr11", 11 },
19860 +    { "cr12", 12 }, { "cr13", 13 }, { "cr14", 14 }, { "cr15", 15 },
19861 +  };
19862 +#define AVR32_NR_CPREGS (sizeof(cr_table)/sizeof(cr_table[0]))
19863 +
19864 +#define AVR32_NR_FPREGS (sizeof(fr_table)/sizeof(fr_table[0]))
19865 +
19866 +/* PiCo Registers.  */
19867 +static const struct reg_entry pico_table[] =
19868 +  {
19869 +    { "inpix2",    0 }, { "inpix1",    1 }, { "inpix0",    2 },
19870 +    { "outpix2",   3 }, { "outpix1",   4 }, { "outpix0",   5 },
19871 +    { "coeff0_a",  6 }, { "coeff0_b",  7 }, { "coeff1_a",  8 },
19872 +    { "coeff1_b",  9 }, { "coeff2_a", 10 }, { "coeff2_b", 11 },
19873 +    { "vmu0_out", 12 }, { "vmu1_out", 13 }, { "vmu2_out", 14 },
19874 +    { "config",   15 },
19875 +  };
19876 +#define AVR32_NR_PICOREGS (sizeof(pico_table)/sizeof(pico_table[0]))
19877 +
19878 +int
19879 +avr32_parse_intreg(const char *str)
19880 +{
19881 +  unsigned int i;
19882 +
19883 +  for (i = 0; i < AVR32_NR_INTREGS; i++)
19884 +    {
19885 +      if (strcasecmp(reg_table[i].name, str) == 0)
19886 +       return reg_table[i].number;
19887 +    }
19888 +
19889 +  return -1;
19890 +}
19891 +
19892 +int
19893 +avr32_parse_cpreg(const char *str)
19894 +{
19895 +  unsigned int i;
19896 +
19897 +  for (i = 0; i < AVR32_NR_CPREGS; i++)
19898 +    {
19899 +      if (strcasecmp(cr_table[i].name, str) == 0)
19900 +       return cr_table[i].number;
19901 +    }
19902 +
19903 +  return -1;
19904 +}
19905 +
19906 +
19907 +int avr32_parse_picoreg(const char *str)
19908 +{
19909 +  unsigned int i;
19910 +
19911 +  for (i = 0; i < AVR32_NR_PICOREGS; i++)
19912 +    {
19913 +      if (strcasecmp(pico_table[i].name, str) == 0)
19914 +       return pico_table[i].number;
19915 +    }
19916 +
19917 +  return -1;
19918 +}
19919 +
19920 +static unsigned long
19921 +parse_reglist(char *str, char **endptr, int (*parse_reg)(const char *))
19922 +{
19923 +  int reg_from, reg_to;
19924 +  unsigned long result = 0;
19925 +  char *p1, *p2, c;
19926 +
19927 +  while (*str)
19928 +    {
19929 +      for (p1 = str; *p1; p1++)
19930 +       if (*p1 == ',' || *p1 == '-')
19931 +         break;
19932 +
19933 +      c = *p1, *p1 = 0;
19934 +      reg_from = parse_reg(str);
19935 +      *p1 = c;
19936 +
19937 +      if (reg_from < 0)
19938 +       break;
19939 +
19940 +      if (*p1 == '-')
19941 +       {
19942 +         for (p2 = ++p1; *p2; p2++)
19943 +           if (*p2 == ',')
19944 +             break;
19945 +
19946 +         c = *p2, *p2 = 0;
19947 +         /* printf("going to parse reg_to from `%s'\n", p1); */
19948 +         reg_to = parse_reg(p1);
19949 +         *p2 = c;
19950 +
19951 +         if (reg_to < 0)
19952 +           break;
19953 +
19954 +         while (reg_from <= reg_to)
19955 +           result |= (1 << reg_from++);
19956 +         p1 = p2;
19957 +       }
19958 +      else
19959 +       result |= (1 << reg_from);
19960 +
19961 +      str = p1;
19962 +      if (*str) ++str;
19963 +    }
19964 +
19965 +  if (endptr)
19966 +    *endptr = str;
19967 +
19968 +  return result;
19969 +}
19970 +
19971 +unsigned long
19972 +avr32_parse_reglist(char *str, char **endptr)
19973 +{
19974 +  return parse_reglist(str, endptr, avr32_parse_intreg);
19975 +}
19976 +
19977 +unsigned long
19978 +avr32_parse_cpreglist(char *str, char **endptr)
19979 +{
19980 +  return parse_reglist(str, endptr, avr32_parse_cpreg);
19981 +}
19982 +
19983 +unsigned long
19984 +avr32_parse_pico_reglist(char *str, char **endptr)
19985 +{
19986 +  return parse_reglist(str, endptr, avr32_parse_picoreg);
19987 +}
19988 +
19989 +int
19990 +avr32_make_regmask8(unsigned long regmask16, unsigned long *regmask8)
19991 +{
19992 +  unsigned long result = 0;
19993 +
19994 +  /* printf("convert regmask16 0x%04lx\n", regmask16); */
19995 +
19996 +  if (regmask16 & 0xf)
19997 +    {
19998 +      if ((regmask16 & 0xf) == 0xf)
19999 +       result |= 1 << 0;
20000 +      else
20001 +       return -1;
20002 +    }
20003 +  if (regmask16 & 0xf0)
20004 +    {
20005 +      if ((regmask16 & 0xf0) == 0xf0)
20006 +       result |= 1 << 1;
20007 +      else
20008 +       return -1;
20009 +    }
20010 +  if (regmask16 & 0x300)
20011 +    {
20012 +      if ((regmask16 & 0x300) == 0x300)
20013 +       result |= 1 << 2;
20014 +      else
20015 +       return -1;
20016 +    }
20017 +  if (regmask16 & (1 << 13))
20018 +    return -1;
20019 +
20020 +  if (regmask16 & (1 << 10))
20021 +    result |= 1 << 3;
20022 +  if (regmask16 & (1 << 11))
20023 +    result |= 1 << 4;
20024 +  if (regmask16 & (1 << 12))
20025 +    result |= 1 << 5;
20026 +  if (regmask16 & (1 << 14))
20027 +    result |= 1 << 6;
20028 +  if (regmask16 & (1 << 15))
20029 +    result |= 1 << 7;
20030 +
20031 +  *regmask8 = result;
20032 +
20033 +  return 0;
20034 +}
20035 +
20036 +#if 0
20037 +struct reg_map
20038 +{
20039 +  const struct reg_entry       *names;
20040 +  int                          nr_regs;
20041 +  struct hash_control          *htab;
20042 +  const char                   *errmsg;
20043 +};
20044 +
20045 +struct reg_map all_reg_maps[] =
20046 +  {
20047 +    { reg_table, AVR32_NR_INTREGS, NULL, N_("integral register expected") },
20048 +    { cr_table,  AVR32_NR_CPREGS,  NULL, N_("coprocessor register expected") },
20049 +  };
20050 +#endif
20051 --- /dev/null
20052 +++ b/opcodes/avr32-asm.h
20053 @@ -0,0 +1,40 @@
20054 +/* Assembler interface for AVR32.
20055 +   Copyright 2005,2006,2007,2008,2009 Atmel Corporation.
20056 +
20057 +   Written by Haavard Skinnemoen, Atmel Norway, <hskinnemoen@atmel.com>
20058 +
20059 +   This file is part of libopcodes.
20060 +
20061 +   This program is free software; you can redistribute it and/or
20062 +   modify it under the terms of the GNU General Public License as
20063 +   published by the Free Software Foundation; either version 2 of the
20064 +   License, or (at your option) any later version.
20065 +
20066 +   This program is distributed in the hope that it will be useful, but
20067 +   WITHOUT ANY WARRANTY; without even the implied warranty of
20068 +   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
20069 +   General Public License for more details.
20070 +
20071 +   You should have received a copy of the GNU General Public License
20072 +   along with this program; if not, write to the Free Software
20073 +   Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA
20074 +   02111-1307, USA.  */
20075 +#ifndef __OPCODES_AVR32_ASM_H
20076 +#define __OPCODES_AVR32_ASM_H
20077 +
20078 +extern int
20079 +avr32_parse_intreg(const char *str);
20080 +extern int
20081 +avr32_parse_cpreg(const char *str);
20082 +extern int
20083 +avr32_parse_picoreg(const char *str);
20084 +extern unsigned long
20085 +avr32_parse_reglist(char *str, char **endptr);
20086 +extern unsigned long
20087 +avr32_parse_cpreglist(char *str, char **endptr);
20088 +extern unsigned long
20089 +avr32_parse_pico_reglist(char *str, char **endptr);
20090 +extern int
20091 +avr32_make_regmask8(unsigned long regmask16, unsigned long *regmask8);
20092 +
20093 +#endif /* __OPCODES_AVR32_ASM_H */
20094 --- /dev/null
20095 +++ b/opcodes/avr32-dis.c
20096 @@ -0,0 +1,916 @@
20097 +/* Print AVR32 instructions for GDB and objdump.
20098 +   Copyright 2005,2006,2007,2008,2009 Atmel Corporation.
20099 +
20100 +   Written by Haavard Skinnemoen, Atmel Norway, <hskinnemoen@atmel.com>
20101 +
20102 +   This file is part of libopcodes.
20103 +
20104 +   This program is free software; you can redistribute it and/or
20105 +   modify it under the terms of the GNU General Public License as
20106 +   published by the Free Software Foundation; either version 2 of the
20107 +   License, or (at your option) any later version.
20108 +
20109 +   This program is distributed in the hope that it will be useful, but
20110 +   WITHOUT ANY WARRANTY; without even the implied warranty of
20111 +   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
20112 +   General Public License for more details.
20113 +
20114 +   You should have received a copy of the GNU General Public License
20115 +   along with this program; if not, write to the Free Software
20116 +   Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA
20117 +   02111-1307, USA.  */
20118 +
20119 +#include "sysdep.h"
20120 +#include "dis-asm.h"
20121 +#include "avr32-opc.h"
20122 +#include "opintl.h"
20123 +#include "safe-ctype.h"
20124 +
20125 +/* TODO: Share this with -asm */
20126 +
20127 +/* Structure for a register hash table entry.  */
20128 +struct reg_entry
20129 +{
20130 +  const char   *name;
20131 +  int          number;
20132 +};
20133 +
20134 +#ifndef strneq
20135 +#define strneq(a,b,n)  (strncmp ((a), (b), (n)) == 0)
20136 +#endif
20137 +
20138 +static char avr32_opt_decode_fpu = 0;
20139 +
20140 +static const struct reg_entry reg_table[] =
20141 +  {
20142 +    /* Primary names (used by the disassembler) */
20143 +    { "r0",   0 }, { "r1",   1 }, { "r2",   2 }, { "r3",   3 },
20144 +    { "r4",   4 }, { "r5",   5 }, { "r6",   6 }, { "r7",   7 },
20145 +    { "r8",   8 }, { "r9",   9 }, { "r10", 10 }, { "r11", 11 },
20146 +    { "r12", 12 }, { "sp",  13 }, { "lr",  14 }, { "pc",  15 },
20147 +    /* Alternatives to sp, lr and pc.  */
20148 +    { "r13", 13 }, { "r14", 14 }, { "r15", 15 },
20149 +  };
20150 +#define AVR32_NR_INTREGS (sizeof(reg_table)/sizeof(reg_table[0]))
20151 +
20152 +/* Coprocessor Registers.  */
20153 +static const struct reg_entry cr_table[] =
20154 +  {
20155 +    { "cr0",   0 }, { "cr1",   1 }, { "cr2",   2 }, { "cr3",   3 },
20156 +    { "cr4",   4 }, { "cr5",   5 }, { "cr6",   6 }, { "cr7",   7 },
20157 +    { "cr8",   8 }, { "cr9",   9 }, { "cr10", 10 }, { "cr11", 11 },
20158 +    { "cr12", 12 }, { "cr13", 13 }, { "cr14", 14 }, { "cr15", 15 },
20159 +  };
20160 +#define AVR32_NR_CPREGS (sizeof(cr_table)/sizeof(cr_table[0]))
20161 +
20162 +static const char bparts[4] = { 'b', 'l', 'u', 't' };
20163 +static bfd_vma current_pc;
20164 +
20165 +struct avr32_field_value
20166 +{
20167 +  const struct avr32_ifield *ifield;
20168 +  unsigned long value;
20169 +};
20170 +
20171 +struct avr32_operand
20172 +{
20173 +  int id;
20174 +  int is_pcrel;
20175 +  int align_order;
20176 +  int (*print)(struct avr32_operand *op, struct disassemble_info *info,
20177 +              struct avr32_field_value *ifields);
20178 +};
20179 +
20180 +static signed long
20181 +get_signed_value(const struct avr32_field_value *fv)
20182 +{
20183 +  signed long value = fv->value;
20184 +
20185 +  if (fv->value & (1 << (fv->ifield->bitsize - 1)))
20186 +    value |= (~0UL << fv->ifield->bitsize);
20187 +
20188 +  return value;
20189 +}
20190 +
20191 +static void
20192 +print_reglist_range(unsigned int first, unsigned int last,
20193 +                   const struct reg_entry *reg_names,
20194 +                   int need_comma,
20195 +                   struct disassemble_info *info)
20196 +{
20197 +  if (need_comma)
20198 +    info->fprintf_func(info->stream, ",");
20199 +
20200 +  if (first == last)
20201 +    info->fprintf_func(info->stream, "%s",
20202 +                      reg_names[first].name);
20203 +  else
20204 +    info->fprintf_func(info->stream, "%s-%s",
20205 +                      reg_names[first].name, reg_names[last].name);
20206 +}
20207 +
20208 +static int
20209 +print_intreg(struct avr32_operand *op,
20210 +            struct disassemble_info *info,
20211 +            struct avr32_field_value *ifields)
20212 +{
20213 +  unsigned long regid = ifields[0].value << op->align_order;
20214 +
20215 +  info->fprintf_func(info->stream, "%s",
20216 +                    reg_table[regid].name);
20217 +  return 1;
20218 +}
20219 +
20220 +static int
20221 +print_intreg_predec(struct avr32_operand *op ATTRIBUTE_UNUSED,
20222 +                   struct disassemble_info *info,
20223 +                   struct avr32_field_value *ifields)
20224 +{
20225 +  info->fprintf_func(info->stream, "--%s",
20226 +                    reg_table[ifields[0].value].name);
20227 +  return 1;
20228 +}
20229 +
20230 +static int
20231 +print_intreg_postinc(struct avr32_operand *op ATTRIBUTE_UNUSED,
20232 +                    struct disassemble_info *info,
20233 +                    struct avr32_field_value *ifields)
20234 +{
20235 +  info->fprintf_func(info->stream, "%s++",
20236 +                    reg_table[ifields[0].value].name);
20237 +  return 1;
20238 +}
20239 +
20240 +static int
20241 +print_intreg_lsl(struct avr32_operand *op ATTRIBUTE_UNUSED,
20242 +                struct disassemble_info *info,
20243 +                struct avr32_field_value *ifields)
20244 +{
20245 +  const char *rp = reg_table[ifields[0].value].name;
20246 +  unsigned long sa = ifields[1].value;
20247 +
20248 +  if (sa)
20249 +    info->fprintf_func(info->stream, "%s<<0x%lx", rp, sa);
20250 +  else
20251 +    info->fprintf_func(info->stream, "%s", rp);
20252 +
20253 +  return 2;
20254 +}
20255 +
20256 +static int
20257 +print_intreg_lsr(struct avr32_operand *op ATTRIBUTE_UNUSED,
20258 +                struct disassemble_info *info,
20259 +                struct avr32_field_value *ifields)
20260 +{
20261 +  const char *rp = reg_table[ifields[0].value].name;
20262 +  unsigned long sa = ifields[1].value;
20263 +
20264 +  if (sa)
20265 +    info->fprintf_func(info->stream, "%s>>0x%lx", rp, sa);
20266 +  else
20267 +    info->fprintf_func(info->stream, "%s", rp);
20268 +
20269 +  return 2;
20270 +}
20271 +
20272 +static int
20273 +print_intreg_bpart(struct avr32_operand *op ATTRIBUTE_UNUSED,
20274 +                  struct disassemble_info *info,
20275 +                  struct avr32_field_value *ifields)
20276 +{
20277 +  info->fprintf_func(info->stream, "%s:%c",
20278 +                    reg_table[ifields[0].value].name,
20279 +                    bparts[ifields[1].value]);
20280 +  return 2;
20281 +}
20282 +
20283 +static int
20284 +print_intreg_hpart(struct avr32_operand *op ATTRIBUTE_UNUSED,
20285 +                  struct disassemble_info *info,
20286 +                  struct avr32_field_value *ifields)
20287 +{
20288 +  info->fprintf_func(info->stream, "%s:%c",
20289 +                    reg_table[ifields[0].value].name,
20290 +                    ifields[1].value ? 't' : 'b');
20291 +  return 2;
20292 +}
20293 +
20294 +static int
20295 +print_intreg_sdisp(struct avr32_operand *op,
20296 +                 struct disassemble_info *info,
20297 +                 struct avr32_field_value *ifields)
20298 +{
20299 +  signed long disp;
20300 +
20301 +  disp = get_signed_value(&ifields[1]) << op->align_order;
20302 +
20303 +  info->fprintf_func(info->stream, "%s[%ld]",
20304 +                    reg_table[ifields[0].value].name, disp);
20305 +  return 2;
20306 +}
20307 +
20308 +static int
20309 +print_intreg_udisp(struct avr32_operand *op,
20310 +                  struct disassemble_info *info,
20311 +                  struct avr32_field_value *ifields)
20312 +{
20313 +  info->fprintf_func(info->stream, "%s[0x%lx]",
20314 +                    reg_table[ifields[0].value].name,
20315 +                    ifields[1].value << op->align_order);
20316 +  return 2;
20317 +}
20318 +
20319 +static int
20320 +print_intreg_index(struct avr32_operand *op ATTRIBUTE_UNUSED,
20321 +                  struct disassemble_info *info,
20322 +                  struct avr32_field_value *ifields)
20323 +{
20324 +  const char *rb, *ri;
20325 +  unsigned long sa = ifields[2].value;
20326 +
20327 +  rb = reg_table[ifields[0].value].name;
20328 +  ri = reg_table[ifields[1].value].name;
20329 +
20330 +  if (sa)
20331 +    info->fprintf_func(info->stream, "%s[%s<<0x%lx]", rb, ri, sa);
20332 +  else
20333 +    info->fprintf_func(info->stream, "%s[%s]", rb, ri);
20334 +
20335 +  return 3;
20336 +}
20337 +
20338 +static int
20339 +print_intreg_xindex(struct avr32_operand *op ATTRIBUTE_UNUSED,
20340 +                   struct disassemble_info *info,
20341 +                   struct avr32_field_value *ifields)
20342 +{
20343 +  info->fprintf_func(info->stream, "%s[%s:%c<<2]",
20344 +                    reg_table[ifields[0].value].name,
20345 +                    reg_table[ifields[1].value].name,
20346 +                    bparts[ifields[2].value]);
20347 +  return 3;
20348 +}
20349 +
20350 +static int
20351 +print_jmplabel(struct avr32_operand *op,
20352 +              struct disassemble_info *info,
20353 +              struct avr32_field_value *ifields)
20354 +{
20355 +  bfd_vma address, offset;
20356 +
20357 +  offset = get_signed_value(ifields) << op->align_order;
20358 +  address = (current_pc & (~0UL << op->align_order)) + offset;
20359 +
20360 +  info->print_address_func(address, info);
20361 +
20362 +  return 1;
20363 +}
20364 +
20365 +static int
20366 +print_pc_disp(struct avr32_operand *op,
20367 +             struct disassemble_info *info,
20368 +             struct avr32_field_value *ifields)
20369 +{
20370 +  bfd_vma address, offset;
20371 +
20372 +  offset = ifields[0].value << op->align_order;
20373 +  address = (current_pc & (~0UL << op->align_order)) + offset;
20374 +
20375 +  info->print_address_func(address, info);
20376 +
20377 +  return 1;
20378 +}
20379 +
20380 +static int
20381 +print_sp(struct avr32_operand *op ATTRIBUTE_UNUSED,
20382 +        struct disassemble_info *info,
20383 +        struct avr32_field_value *ifields ATTRIBUTE_UNUSED)
20384 +{
20385 +  info->fprintf_func(info->stream, "sp");
20386 +  return 1;
20387 +}
20388 +
20389 +static int
20390 +print_sp_disp(struct avr32_operand *op,
20391 +             struct disassemble_info *info,
20392 +             struct avr32_field_value *ifields)
20393 +{
20394 +  info->fprintf_func(info->stream, "sp[0x%lx]",
20395 +                    ifields[0].value << op->align_order);
20396 +  return 1;
20397 +}
20398 +
20399 +static int
20400 +print_cpno(struct avr32_operand *op ATTRIBUTE_UNUSED,
20401 +          struct disassemble_info *info,
20402 +          struct avr32_field_value *ifields)
20403 +{
20404 +  info->fprintf_func(info->stream, "cp%lu", ifields[0].value);
20405 +  return 1;
20406 +}
20407 +
20408 +static int
20409 +print_cpreg(struct avr32_operand *op,
20410 +           struct disassemble_info *info,
20411 +           struct avr32_field_value *ifields)
20412 +{
20413 +  info->fprintf_func(info->stream, "cr%lu",
20414 +                    ifields[0].value << op->align_order);
20415 +  return 1;
20416 +}
20417 +
20418 +static int
20419 +print_uconst(struct avr32_operand *op,
20420 +            struct disassemble_info *info,
20421 +            struct avr32_field_value *ifields)
20422 +{
20423 +  info->fprintf_func(info->stream, "0x%lx",
20424 +                    ifields[0].value << op->align_order);
20425 +  return 1;
20426 +}
20427 +
20428 +static int
20429 +print_sconst(struct avr32_operand *op,
20430 +            struct disassemble_info *info,
20431 +            struct avr32_field_value *ifields)
20432 +{
20433 +  info->fprintf_func(info->stream, "%ld",
20434 +                    get_signed_value(ifields) << op->align_order);
20435 +  return 1;
20436 +}
20437 +
20438 +static int
20439 +print_reglist8_head(unsigned long regmask, int *commap,
20440 +                   struct disassemble_info *info)
20441 +{
20442 +  int first = -1, last, i = 0;
20443 +  int need_comma = 0;
20444 +
20445 +  while (i < 12)
20446 +    {
20447 +      if (first == -1 && (regmask & 1))
20448 +       {
20449 +         first = i;
20450 +       }
20451 +      else if (first != -1 && !(regmask & 1))
20452 +       {
20453 +         last = i - 1;
20454 +
20455 +         print_reglist_range(first, last, reg_table, need_comma, info);
20456 +         need_comma = 1;
20457 +         first = -1;
20458 +       }
20459 +
20460 +      if (i < 8)
20461 +       i += 4;
20462 +      else if (i < 10)
20463 +       i += 2;
20464 +      else
20465 +       i++;
20466 +      regmask >>= 1;
20467 +    }
20468 +
20469 +  *commap = need_comma;
20470 +  return first;
20471 +}
20472 +
20473 +static void
20474 +print_reglist8_tail(unsigned long regmask, int first, int need_comma,
20475 +                   struct disassemble_info *info)
20476 +{
20477 +  int last = 11;
20478 +
20479 +  if (regmask & 0x20)
20480 +    {
20481 +      if (first == -1)
20482 +       first = 12;
20483 +      last = 12;
20484 +    }
20485 +
20486 +  if (first != -1)
20487 +    {
20488 +      print_reglist_range(first, last, reg_table, need_comma, info);
20489 +      need_comma = 1;
20490 +      first = -1;
20491 +    }
20492 +
20493 +  if (regmask & 0x40)
20494 +    {
20495 +      if (first == -1)
20496 +       first = 14;
20497 +      last = 14;
20498 +    }
20499 +
20500 +  if (regmask & 0x80)
20501 +    {
20502 +      if (first == -1)
20503 +       first = 15;
20504 +      last = 15;
20505 +    }
20506 +
20507 +  if (first != -1)
20508 +    print_reglist_range(first, last, reg_table, need_comma, info);
20509 +}
20510 +
20511 +static int
20512 +print_reglist8(struct avr32_operand *op ATTRIBUTE_UNUSED,
20513 +              struct disassemble_info *info,
20514 +              struct avr32_field_value *ifields)
20515 +{
20516 +  unsigned long regmask = ifields[0].value;
20517 +  int first, need_comma;
20518 +
20519 +  first = print_reglist8_head(regmask, &need_comma, info);
20520 +  print_reglist8_tail(regmask, first, need_comma, info);
20521 +
20522 +  return 1;
20523 +}
20524 +
20525 +static int
20526 +print_reglist9(struct avr32_operand *op ATTRIBUTE_UNUSED,
20527 +              struct disassemble_info *info,
20528 +              struct avr32_field_value *ifields)
20529 +{
20530 +  unsigned long regmask = ifields[0].value >> 1;
20531 +  int first, last, need_comma;
20532 +
20533 +  first = print_reglist8_head(regmask, &need_comma, info);
20534 +
20535 +  if ((ifields[0].value & 0x101) == 0x101)
20536 +    {
20537 +      if (first != -1)
20538 +       {
20539 +         last = 11;
20540 +
20541 +         print_reglist_range(first, last, reg_table, need_comma, info);
20542 +         need_comma = 1;
20543 +         first = -1;
20544 +       }
20545 +
20546 +      print_reglist_range(15, 15, reg_table, need_comma, info);
20547 +
20548 +      regmask >>= 5;
20549 +
20550 +      if ((regmask & 3) == 0)
20551 +       info->fprintf_func(info->stream, ",r12=0");
20552 +      else if ((regmask & 3) == 1)
20553 +       info->fprintf_func(info->stream, ",r12=1");
20554 +      else
20555 +       info->fprintf_func(info->stream, ",r12=-1");
20556 +    }
20557 +  else
20558 +      print_reglist8_tail(regmask, first, need_comma, info);
20559 +
20560 +  return 1;
20561 +}
20562 +
20563 +static int
20564 +print_reglist16(struct avr32_operand *op ATTRIBUTE_UNUSED,
20565 +               struct disassemble_info *info,
20566 +               struct avr32_field_value *ifields)
20567 +{
20568 +  unsigned long regmask = ifields[0].value;
20569 +  unsigned int i = 0, first, last;
20570 +  int need_comma = 0;
20571 +
20572 +  while (i < 16)
20573 +    {
20574 +      if (regmask & 1)
20575 +       {
20576 +         first = i;
20577 +         while (i < 16)
20578 +           {
20579 +             i++;
20580 +             regmask >>= 1;
20581 +             if (!(regmask & 1))
20582 +               break;
20583 +           }
20584 +         last = i - 1;
20585 +         print_reglist_range(first, last, reg_table, need_comma, info);
20586 +         need_comma = 1;
20587 +       }
20588 +      else
20589 +       {
20590 +         i++;
20591 +         regmask >>= 1;
20592 +       }
20593 +    }
20594 +
20595 +  return 1;
20596 +}
20597 +
20598 +static int
20599 +print_reglist_ldm(struct avr32_operand *op,
20600 +                 struct disassemble_info *info,
20601 +                 struct avr32_field_value *ifields)
20602 +{
20603 +  int rp, w_bit;
20604 +  int i, first, last;
20605 +  unsigned long regmask;
20606 +
20607 +  rp = ifields[0].value;
20608 +  w_bit = ifields[1].value;
20609 +  regmask = ifields[2].value;
20610 +
20611 +  if (regmask & (1 << AVR32_REG_PC) && rp == AVR32_REG_PC)
20612 +    {
20613 +      if (w_bit)
20614 +       info->fprintf_func(info->stream, "sp++");
20615 +      else
20616 +       info->fprintf_func(info->stream, "sp");
20617 +
20618 +      for (i = 0; i < 12; )
20619 +       {
20620 +         if (regmask & (1 << i))
20621 +           {
20622 +             first = i;
20623 +             while (i < 12)
20624 +               {
20625 +                 i++;
20626 +                 if (!(regmask & (1 << i)))
20627 +                   break;
20628 +               }
20629 +             last = i - 1;
20630 +             print_reglist_range(first, last, reg_table, 1, info);
20631 +           }
20632 +         else
20633 +           i++;
20634 +       }
20635 +
20636 +      info->fprintf_func(info->stream, ",pc");
20637 +      if (regmask & (1 << AVR32_REG_LR))
20638 +       info->fprintf_func(info->stream, ",r12=-1");
20639 +      else if (regmask & (1 << AVR32_REG_R12))
20640 +       info->fprintf_func(info->stream, ",r12=1");
20641 +      else
20642 +       info->fprintf_func(info->stream, ",r12=0");
20643 +    }
20644 +  else
20645 +    {
20646 +      if (w_bit)
20647 +       info->fprintf_func(info->stream, "%s++,", reg_table[rp].name);
20648 +      else
20649 +       info->fprintf_func(info->stream, "%s,", reg_table[rp].name);
20650 +
20651 +      print_reglist16(op, info, ifields + 2);
20652 +    }
20653 +
20654 +  return 3;
20655 +}
20656 +
20657 +static int
20658 +print_reglist_cp8(struct avr32_operand *op ATTRIBUTE_UNUSED,
20659 +                 struct disassemble_info *info,
20660 +                 struct avr32_field_value *ifields)
20661 +{
20662 +  unsigned long regmask = ifields[0].value;
20663 +  unsigned int i = 0, first, last, offset = 0;
20664 +  int need_comma = 0;
20665 +
20666 +  if (ifields[1].value)
20667 +    offset = 8;
20668 +
20669 +  while (i < 8)
20670 +    {
20671 +      if (regmask & 1)
20672 +       {
20673 +         first = i;
20674 +         while (i < 8)
20675 +           {
20676 +             i++;
20677 +             regmask >>= 1;
20678 +             if (!(regmask & 1))
20679 +               break;
20680 +           }
20681 +         last = i - 1;
20682 +         print_reglist_range(offset + first, offset + last,
20683 +                             cr_table, need_comma, info);
20684 +         need_comma = 1;
20685 +       }
20686 +      else
20687 +       {
20688 +         i++;
20689 +         regmask >>= 1;
20690 +       }
20691 +    }
20692 +
20693 +  return 2;
20694 +}
20695 +
20696 +static int
20697 +print_reglist_cpd8(struct avr32_operand *op ATTRIBUTE_UNUSED,
20698 +                  struct disassemble_info *info,
20699 +                  struct avr32_field_value *ifields)
20700 +{
20701 +  unsigned long regmask = ifields[0].value;
20702 +  unsigned int i = 0, first, last;
20703 +  int need_comma = 0;
20704 +
20705 +  while (i < 8)
20706 +    {
20707 +      if (regmask & 1)
20708 +       {
20709 +         first = 2 * i;
20710 +         while (i < 8)
20711 +           {
20712 +             i++;
20713 +             regmask >>= 1;
20714 +             if (!(regmask & 1))
20715 +               break;
20716 +           }
20717 +         last = 2 * (i - 1) + 1;
20718 +         print_reglist_range(first, last, cr_table, need_comma, info);
20719 +         need_comma = 1;
20720 +       }
20721 +      else
20722 +       {
20723 +         i++;
20724 +         regmask >>= 1;
20725 +       }
20726 +    }
20727 +
20728 +  return 1;
20729 +}
20730 +
20731 +static int
20732 +print_retval(struct avr32_operand *op ATTRIBUTE_UNUSED,
20733 +            struct disassemble_info *info,
20734 +            struct avr32_field_value *ifields)
20735 +{
20736 +  unsigned long regid = ifields[0].value;
20737 +  const char *retval;
20738 +
20739 +  if (regid < AVR32_REG_SP)
20740 +    retval = reg_table[regid].name;
20741 +  else if (regid == AVR32_REG_SP)
20742 +    retval = "0";
20743 +  else if (regid == AVR32_REG_LR)
20744 +    retval = "-1";
20745 +  else
20746 +    retval = "1";
20747 +
20748 +  info->fprintf_func(info->stream, "%s", retval);
20749 +
20750 +  return 1;
20751 +}
20752 +
20753 +static int
20754 +print_mcall(struct avr32_operand *op,
20755 +           struct disassemble_info *info,
20756 +           struct avr32_field_value *ifields)
20757 +{
20758 +  unsigned long regid = ifields[0].value;
20759 +
20760 +  if (regid == AVR32_REG_PC)
20761 +    print_jmplabel(op, info, ifields + 1);
20762 +  else
20763 +    print_intreg_sdisp(op, info, ifields);
20764 +
20765 +  return 2;
20766 +}
20767 +
20768 +static int
20769 +print_jospinc(struct avr32_operand *op ATTRIBUTE_UNUSED,
20770 +             struct disassemble_info *info,
20771 +             struct avr32_field_value *ifields)
20772 +{
20773 +  signed long value = ifields[0].value;
20774 +
20775 +  if (value >= 4)
20776 +    value -= 8;
20777 +  else
20778 +    value += 1;
20779 +
20780 +  info->fprintf_func(info->stream, "%ld", value);
20781 +
20782 +  return 1;
20783 +}
20784 +
20785 +static int
20786 +print_coh(struct avr32_operand *op ATTRIBUTE_UNUSED,
20787 +         struct disassemble_info *info,
20788 +         struct avr32_field_value *ifields ATTRIBUTE_UNUSED)
20789 +{
20790 +  info->fprintf_func(info->stream, "COH");
20791 +  return 0;
20792 +}
20793 +
20794 +#define OP(name, sgn, pcrel, align, func) \
20795 +  { AVR32_OPERAND_##name, pcrel, align, print_##func }
20796 +
20797 +struct avr32_operand operand[AVR32_NR_OPERANDS] =
20798 +  {
20799 +    OP(INTREG, 0, 0, 0, intreg),
20800 +    OP(INTREG_PREDEC, 0, 0, 0, intreg_predec),
20801 +    OP(INTREG_POSTINC, 0, 0, 0, intreg_postinc),
20802 +    OP(INTREG_LSL, 0, 0, 0, intreg_lsl),
20803 +    OP(INTREG_LSR, 0, 0, 0, intreg_lsr),
20804 +    OP(INTREG_BSEL, 0, 0, 0, intreg_bpart),
20805 +    OP(INTREG_HSEL, 0, 0, 1, intreg_hpart),
20806 +    OP(INTREG_SDISP, 1, 0, 0, intreg_sdisp),
20807 +    OP(INTREG_SDISP_H, 1, 0, 1, intreg_sdisp),
20808 +    OP(INTREG_SDISP_W, 1, 0, 2, intreg_sdisp),
20809 +    OP(INTREG_UDISP, 0, 0, 0, intreg_udisp),
20810 +    OP(INTREG_UDISP_H, 0, 0, 1, intreg_udisp),
20811 +    OP(INTREG_UDISP_W, 0, 0, 2, intreg_udisp),
20812 +    OP(INTREG_INDEX, 0, 0, 0, intreg_index),
20813 +    OP(INTREG_XINDEX, 0, 0, 0, intreg_xindex),
20814 +    OP(DWREG, 0, 0, 1, intreg),
20815 +    OP(PC_UDISP_W, 0, 1, 2, pc_disp),
20816 +    OP(SP, 0, 0, 0, sp),
20817 +    OP(SP_UDISP_W, 0, 0, 2, sp_disp),
20818 +    OP(CPNO, 0, 0, 0, cpno),
20819 +    OP(CPREG, 0, 0, 0, cpreg),
20820 +    OP(CPREG_D, 0, 0, 1, cpreg),
20821 +    OP(UNSIGNED_CONST, 0, 0, 0, uconst),
20822 +    OP(UNSIGNED_CONST_W, 0, 0, 2, uconst),
20823 +    OP(SIGNED_CONST, 1, 0, 0, sconst),
20824 +    OP(SIGNED_CONST_W, 1, 0, 2, sconst),
20825 +    OP(JMPLABEL, 1, 1, 1, jmplabel),
20826 +    OP(UNSIGNED_NUMBER, 0, 0, 0, uconst),
20827 +    OP(UNSIGNED_NUMBER_W, 0, 0, 2, uconst),
20828 +    OP(REGLIST8, 0, 0, 0, reglist8),
20829 +    OP(REGLIST9, 0, 0, 0, reglist9),
20830 +    OP(REGLIST16, 0, 0, 0, reglist16),
20831 +    OP(REGLIST_LDM, 0, 0, 0, reglist_ldm),
20832 +    OP(REGLIST_CP8, 0, 0, 0, reglist_cp8),
20833 +    OP(REGLIST_CPD8, 0, 0, 0, reglist_cpd8),
20834 +    OP(RETVAL, 0, 0, 0, retval),
20835 +    OP(MCALL, 1, 0, 2, mcall),
20836 +    OP(JOSPINC, 0, 0, 0, jospinc),
20837 +    OP(COH, 0, 0, 0, coh),
20838 +  };
20839 +
20840 +static void
20841 +print_opcode(bfd_vma insn_word, const struct avr32_opcode *opc,
20842 +            bfd_vma pc, struct disassemble_info *info)
20843 +{
20844 +  const struct avr32_syntax *syntax = opc->syntax;
20845 +  struct avr32_field_value fields[AVR32_MAX_FIELDS];
20846 +  unsigned int i, next_field = 0, nr_operands;
20847 +
20848 +  for (i = 0; i < opc->nr_fields; i++)
20849 +    {
20850 +      opc->fields[i]->extract(opc->fields[i], &insn_word, &fields[i].value);
20851 +      fields[i].ifield = opc->fields[i];
20852 +    }
20853 +
20854 +  current_pc = pc;
20855 +  info->fprintf_func(info->stream, "%s", syntax->mnemonic->name);
20856 +
20857 +  if (syntax->nr_operands < 0)
20858 +    nr_operands = (unsigned int) -syntax->nr_operands;
20859 +  else
20860 +    nr_operands = (unsigned int) syntax->nr_operands;
20861 +
20862 +  for (i = 0; i < nr_operands; i++)
20863 +    {
20864 +      struct avr32_operand *op = &operand[syntax->operand[i]];
20865 +
20866 +      if (i)
20867 +       info->fprintf_func(info->stream, ",");
20868 +      else
20869 +       info->fprintf_func(info->stream, "\t");
20870 +      next_field += op->print(op, info, &fields[next_field]);
20871 +    }
20872 +}
20873 +
20874 +#define is_fpu_insn(iw) ((iw&0xf9f0e000)==0xe1a00000)
20875 +
20876 +static const struct avr32_opcode *
20877 +find_opcode(bfd_vma insn_word)
20878 +{
20879 +  int i;
20880 +
20881 +  for (i = 0; i < AVR32_NR_OPCODES; i++)
20882 +    {
20883 +      const struct avr32_opcode *opc = &avr32_opc_table[i];
20884 +
20885 +      if ((insn_word & opc->mask) == opc->value)
20886 +      {
20887 +        if (avr32_opt_decode_fpu)
20888 +        {
20889 +          if (is_fpu_insn(insn_word))
20890 +          {
20891 +            if (opc->id != AVR32_OPC_COP)
20892 +              return opc;
20893 +          }
20894 +          else
20895 +            return opc;
20896 +        }
20897 +        else
20898 +       return opc;
20899 +    }
20900 +   }
20901 +
20902 +  return NULL;
20903 +}
20904 +
20905 +static int
20906 +read_insn_word(bfd_vma pc, bfd_vma *valuep,
20907 +              struct disassemble_info *info)
20908 +{
20909 +  bfd_byte b[4];
20910 +  int status;
20911 +
20912 +  status = info->read_memory_func(pc, b, 4, info);
20913 +  if (status)
20914 +    {
20915 +      status = info->read_memory_func(pc, b, 2, info);
20916 +      if (status)
20917 +       {
20918 +         info->memory_error_func(status, pc, info);
20919 +         return -1;
20920 +       }
20921 +      b[3] = b[2] = 0;
20922 +    }
20923 +
20924 +  *valuep =  (b[0] << 24) | (b[1] << 16) | (b[2] << 8) | b[3];
20925 +  return 0;
20926 +}
20927 +
20928 +/* Parse an individual disassembler option.  */
20929 +
20930 +void
20931 +parse_avr32_disassembler_option (option)
20932 +     char * option;
20933 +{
20934 +  if (option == NULL)
20935 +    return;
20936 +
20937 +  if (!strcmp(option,"decode-fpu"))
20938 +  {
20939 +    avr32_opt_decode_fpu = 1;
20940 +    return;
20941 +  }
20942 +
20943 +  printf("\n%s--",option);
20944 +  /* XXX - should break 'option' at following delimiter.  */
20945 +  fprintf (stderr, _("Unrecognised disassembler option: %s\n"), option);
20946 +
20947 +  return;
20948 +}
20949 +
20950 +/* Parse the string of disassembler options, spliting it at whitespaces
20951 +   or commas.  (Whitespace separators supported for backwards compatibility).  */
20952 +
20953 +static void
20954 +parse_disassembler_options (char *options)
20955 +{
20956 +  if (options == NULL)
20957 +    return;
20958 +
20959 +  while (*options)
20960 +    {
20961 +      parse_avr32_disassembler_option (options);
20962 +
20963 +      /* Skip forward to next seperator.  */
20964 +      while ((*options) && (! ISSPACE (*options)) && (*options != ','))
20965 +       ++ options;
20966 +      /* Skip forward past seperators.  */
20967 +      while (ISSPACE (*options) || (*options == ','))
20968 +       ++ options;
20969 +    }
20970 +}
20971 +
20972 +int
20973 +print_insn_avr32(bfd_vma pc, struct disassemble_info *info)
20974 +{
20975 +  bfd_vma insn_word;
20976 +  const struct avr32_opcode *opc;
20977 +
20978 +  if (info->disassembler_options)
20979 +    {
20980 +      parse_disassembler_options (info->disassembler_options);
20981 +
20982 +      /* To avoid repeated parsing of these options, we remove them here.  */
20983 +      info->disassembler_options = NULL;
20984 +    }
20985 +
20986 +  info->bytes_per_chunk = 1;
20987 +  info->display_endian = BFD_ENDIAN_BIG;
20988 +
20989 +  if (read_insn_word(pc, &insn_word, info))
20990 +    return -1;
20991 +
20992 +  opc = find_opcode(insn_word);
20993 +  if (opc)
20994 +    {
20995 +      print_opcode(insn_word, opc, pc, info);
20996 +      return opc->size;
20997 +    }
20998 +  else
20999 +    {
21000 +      info->fprintf_func(info->stream, _("*unknown*"));
21001 +      return 2;
21002 +    }
21003 +
21004 +}
21005 +
21006 +void
21007 +print_avr32_disassembler_options (FILE *stream ATTRIBUTE_UNUSED)
21008 +{
21009 +  fprintf(stream, "\n AVR32 Specific Disassembler Options:\n");
21010 +  fprintf(stream, "  -M decode-fpu                  Print FPU instructions instead of 'cop' \n");
21011 +}
21012 +
21013 --- /dev/null
21014 +++ b/opcodes/avr32-opc.c
21015 @@ -0,0 +1,6906 @@
21016 +/* Opcode tables for AVR32.
21017 +   Copyright 2005,2006,2007,2008,2009 Atmel Corporation.
21018 +
21019 +   Written by Haavard Skinnemoen, Atmel Norway, <hskinnemoen@atmel.com>
21020 +
21021 +   This file is part of libopcodes.
21022 +
21023 +   This program is free software; you can redistribute it and/or
21024 +   modify it under the terms of the GNU General Public License as
21025 +   published by the Free Software Foundation; either version 2 of the
21026 +   License, or (at your option) any later version.
21027 +
21028 +   This program is distributed in the hope that it will be useful, but
21029 +   WITHOUT ANY WARRANTY; without even the implied warranty of
21030 +   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
21031 +   General Public License for more details.
21032 +
21033 +   You should have received a copy of the GNU General Public License
21034 +   along with this program; if not, write to the Free Software
21035 +   Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA
21036 +   02111-1307, USA.  */
21037 +
21038 +#include <stdlib.h>
21039 +#include <assert.h>
21040 +
21041 +#include "avr32-opc.h"
21042 +
21043 +#define PICO_CPNO      1
21044 +
21045 +void
21046 +avr32_insert_simple(const struct avr32_ifield *field,
21047 +                   void *buf, unsigned long value)
21048 +{
21049 +  bfd_vma word;
21050 +
21051 +  word = bfd_getb32(buf);
21052 +  word &= ~field->mask;
21053 +  word |= (value << field->shift) & field->mask;
21054 +  bfd_putb32(word, buf);
21055 +}
21056 +
21057 +void
21058 +avr32_insert_bit5c(const struct avr32_ifield *field ATTRIBUTE_UNUSED,
21059 +                  void *buf, unsigned long value)
21060 +{
21061 +  char *opcode = buf;
21062 +
21063 +  opcode[0] = (opcode[0] & 0xe1) | (value & 0x1e);
21064 +  opcode[1] = (opcode[1] & 0xef) | ((value & 1) << 4);
21065 +}
21066 +
21067 +void
21068 +avr32_insert_k10(const struct avr32_ifield *field ATTRIBUTE_UNUSED,
21069 +                void *buf, unsigned long value)
21070 +{
21071 +  char *opcode = buf;
21072 +
21073 +  opcode[0] = (opcode[0] & 0xf0) | ((value & 0xf0) >> 4);
21074 +  opcode[1] = ((opcode[1] & 0x0c) | ((value & 0x0f) << 4)
21075 +              | ((value & 0x300) >> 8));
21076 +}
21077 +
21078 +
21079 +void
21080 +avr32_insert_k21(const struct avr32_ifield *field,
21081 +                void *buf, unsigned long value)
21082 +{
21083 +  bfd_vma word;
21084 +  bfd_vma k21;
21085 +
21086 +  word = bfd_getb32(buf);
21087 +  word &= ~field->mask;
21088 +  k21 = ((value & 0xffff) | ((value & 0x10000) << 4)
21089 +        | ((value & 0x1e0000) << 8));
21090 +  assert(!(k21 & ~field->mask));
21091 +  word |= k21;
21092 +  bfd_putb32(word, buf);
21093 +}
21094 +
21095 +void
21096 +avr32_insert_cpop(const struct avr32_ifield *field,
21097 +                 void *buf, unsigned long value)
21098 +{
21099 +  bfd_vma word;
21100 +
21101 +  word = bfd_getb32(buf);
21102 +  word &= ~field->mask;
21103 +  word |= (((value & 0x1e) << 15) | ((value & 0x60) << 20)
21104 +          | ((value & 0x01) << 12));
21105 +  bfd_putb32(word, buf);
21106 +}
21107 +
21108 +void
21109 +avr32_insert_k12cp(const struct avr32_ifield *field,
21110 +                  void *buf, unsigned long value)
21111 +{
21112 +  bfd_vma word;
21113 +
21114 +  word = bfd_getb32(buf);
21115 +  word &= ~field->mask;
21116 +  word |= ((value & 0xf00) << 4) | (value & 0xff);
21117 +  bfd_putb32(word, buf);
21118 +}
21119 +
21120 +void avr32_extract_simple(const struct avr32_ifield *field,
21121 +                         void *buf, unsigned long *value)
21122 +{
21123 +  /* XXX: The disassembler has done any necessary byteswapping already */
21124 +  bfd_vma word = *(bfd_vma *)buf;
21125 +
21126 +  *value = (word & field->mask) >> field->shift;
21127 +}
21128 +
21129 +void avr32_extract_bit5c(const struct avr32_ifield *field ATTRIBUTE_UNUSED,
21130 +                        void *buf, unsigned long *value)
21131 +{
21132 +  bfd_vma word = *(bfd_vma *)buf;
21133 +
21134 +  *value = ((word >> 20) & 1) | ((word >> 24) & 0x1e);
21135 +}
21136 +
21137 +void avr32_extract_k10(const struct avr32_ifield *field ATTRIBUTE_UNUSED,
21138 +                      void *buf, unsigned long *value)
21139 +{
21140 +  bfd_vma word = *(bfd_vma *)buf;
21141 +
21142 +  *value = ((word >> 8) & 0x300) | ((word >> 20) & 0xff);
21143 +}
21144 +
21145 +void avr32_extract_k21(const struct avr32_ifield *field ATTRIBUTE_UNUSED,
21146 +                      void *buf, unsigned long *value)
21147 +{
21148 +  bfd_vma word = *(bfd_vma *)buf;
21149 +
21150 +  *value = ((word & 0xffff) | ((word >> 4) & 0x10000)
21151 +           | ((word >> 8) & 0x1e0000));
21152 +}
21153 +
21154 +void avr32_extract_cpop(const struct avr32_ifield *field ATTRIBUTE_UNUSED,
21155 +                       void *buf, unsigned long *value)
21156 +{
21157 +  bfd_vma word = *(bfd_vma *)buf;
21158 +
21159 +  *value = (((word >> 12) & 1) | ((word >> 15) & 0x1e)
21160 +           | ((word >> 20) & 0x60));
21161 +}
21162 +
21163 +void avr32_extract_k12cp(const struct avr32_ifield *field ATTRIBUTE_UNUSED,
21164 +                        void *buf, unsigned long *value)
21165 +{
21166 +  bfd_vma word = *(bfd_vma *)buf;
21167 +
21168 +  *value = ((word >> 4) & 0xf00) | (word & 0xff);
21169 +}
21170 +
21171 +
21172 +#define IFLD(id, bitsz, shift, mask, func) \
21173 +  { AVR32_IFIELD_##id, bitsz, shift, mask, \
21174 +    avr32_insert_##func, avr32_extract_##func }
21175 +
21176 +const struct avr32_ifield avr32_ifield_table[] =
21177 +  {
21178 +    IFLD(RX, 4, 25, 0x1e000000, simple),
21179 +    IFLD(RY, 4, 16, 0x000f0000, simple),
21180 +    IFLD(COND4C, 4, 20, 0x00f00000, simple),
21181 +    IFLD(K8C, 8, 20, 0x0ff00000, simple),
21182 +    IFLD(K7C, 7, 20, 0x07f00000, simple),
21183 +    IFLD(K5C, 5, 20, 0x01f00000, simple),
21184 +    IFLD(K3, 3, 20, 0x00700000, simple),
21185 +    IFLD(RY_DW, 3, 17, 0x000e0000, simple),
21186 +    IFLD(COND4E, 4, 8, 0x00000f00, simple),
21187 +    IFLD(K8E, 8, 0, 0x000000ff, simple),
21188 +    IFLD(BIT5C, 5, 20, 0x1e100000, bit5c),
21189 +    IFLD(COND3, 3, 16, 0x00070000, simple),
21190 +    IFLD(K10, 10, 16, 0x0ff30000, k10),
21191 +    IFLD(POPM, 9, 19, 0x0ff80000, simple),
21192 +    IFLD(K2, 2, 4, 0x00000030, simple),
21193 +    IFLD(RD_E, 4, 0, 0x0000000f, simple),
21194 +    IFLD(RD_DW, 3, 1, 0x0000000e, simple),
21195 +    IFLD(X, 1, 5, 0x00000020, simple),
21196 +    IFLD(Y, 1, 4, 0x00000010, simple),
21197 +    IFLD(X2, 1, 13, 0x00002000, simple),
21198 +    IFLD(Y2, 1, 12, 0x00001000, simple),
21199 +    IFLD(K5E, 5, 0, 0x0000001f, simple),
21200 +    IFLD(PART2, 2, 0, 0x00000003, simple),
21201 +    IFLD(PART1, 1, 0, 0x00000001, simple),
21202 +    IFLD(K16, 16, 0, 0x0000ffff, simple),
21203 +    IFLD(CACHEOP, 5, 11, 0x0000f800, simple),
21204 +    IFLD(K11, 11, 0, 0x000007ff, simple),
21205 +    IFLD(K21, 21, 0, 0x1e10ffff, k21),
21206 +    IFLD(CPOP, 7, 12, 0x060f1000, cpop),
21207 +    IFLD(CPNO, 3, 13, 0x0000e000, simple),
21208 +    IFLD(CRD_RI, 4, 8, 0x00000f00, simple),
21209 +    IFLD(CRX, 4, 4, 0x000000f0, simple),
21210 +    IFLD(CRY, 4, 0, 0x0000000f, simple),
21211 +    IFLD(K7E, 7, 0, 0x0000007f, simple),
21212 +    IFLD(CRD_DW, 3, 9, 0x00000e00, simple),
21213 +    IFLD(PART1_K12, 1, 12, 0x00001000, simple),
21214 +    IFLD(PART2_K12, 2, 12, 0x00003000, simple),
21215 +    IFLD(K12, 12, 0, 0x00000fff, simple),
21216 +    IFLD(S5, 5, 5, 0x000003e0, simple),
21217 +    IFLD(K5E2, 5, 4, 0x000001f0, simple),
21218 +    IFLD(K4, 4, 20, 0x00f00000, simple),
21219 +    IFLD(COND4E2, 4, 4, 0x000000f0, simple),
21220 +    IFLD(K8E2, 8, 4, 0x00000ff0, simple),
21221 +    IFLD(K6, 6, 20, 0x03f00000, simple),
21222 +    IFLD(MEM15, 15, 0, 0x00007fff, simple),
21223 +    IFLD(MEMB5, 5, 15, 0x000f8000, simple),
21224 +    IFLD(W, 1, 25, 0x02000000, simple),
21225 +    /* Coprocessor Multiple High/Low */
21226 +    IFLD(CM_HL, 1, 8, 0x00000100, simple),
21227 +    IFLD(K12CP, 12 ,0, 0x0000f0ff, k12cp),
21228 +    IFLD(K9E, 9 ,0, 0x000001ff, simple),
21229 +    IFLD (FP_RX, 4,  4, 0x000000F0, simple),
21230 +    IFLD (FP_RY, 4,  0, 0x0000000F, simple),
21231 +    IFLD (FP_RD, 4,  8, 0x00000F00, simple),
21232 +    IFLD (FP_RA, 4, 16, 0x000F0000, simple)
21233 +  };
21234 +#undef IFLD
21235 +
21236 +
21237 +struct avr32_opcode avr32_opc_table[] =
21238 +  {
21239 +    {
21240 +      AVR32_OPC_ABS, 2, 0x5c400000, 0xfff00000,
21241 +      &avr32_syntax_table[AVR32_SYNTAX_ABS],
21242 +      BFD_RELOC_UNUSED, 1, -1,
21243 +      {
21244 +       &avr32_ifield_table[AVR32_IFIELD_RY],
21245 +      }
21246 +    },
21247 +    {
21248 +      AVR32_OPC_ACALL, 2, 0xd0000000, 0xf00f0000,
21249 +      &avr32_syntax_table[AVR32_SYNTAX_ACALL],
21250 +      BFD_RELOC_UNUSED, 1, -1,
21251 +      {
21252 +       &avr32_ifield_table[AVR32_IFIELD_K8C],
21253 +      },
21254 +    },
21255 +    {
21256 +      AVR32_OPC_ACR, 2, 0x5c000000, 0xfff00000,
21257 +      &avr32_syntax_table[AVR32_SYNTAX_ACR],
21258 +      BFD_RELOC_UNUSED, 1, -1,
21259 +      {
21260 +       &avr32_ifield_table[AVR32_IFIELD_RY],
21261 +      },
21262 +    },
21263 +    {
21264 +      AVR32_OPC_ADC, 4, 0xe0000040, 0xe1f0fff0,
21265 +      &avr32_syntax_table[AVR32_SYNTAX_ADC],
21266 +      BFD_RELOC_UNUSED, 3, -1,
21267 +      {
21268 +       &avr32_ifield_table[AVR32_IFIELD_RD_E],
21269 +       &avr32_ifield_table[AVR32_IFIELD_RX],
21270 +       &avr32_ifield_table[AVR32_IFIELD_RY],
21271 +      },
21272 +    },
21273 +    {
21274 +      AVR32_OPC_ADD1, 2, 0x00000000, 0xe1f00000,
21275 +      &avr32_syntax_table[AVR32_SYNTAX_ADD1],
21276 +      BFD_RELOC_UNUSED, 2, -1,
21277 +      {
21278 +       &avr32_ifield_table[AVR32_IFIELD_RY],
21279 +       &avr32_ifield_table[AVR32_IFIELD_RX],
21280 +      },
21281 +    },
21282 +    {
21283 +      AVR32_OPC_ADD2, 4, 0xe0000000, 0xe1f0ffc0,
21284 +      &avr32_syntax_table[AVR32_SYNTAX_ADD2],
21285 +      BFD_RELOC_UNUSED, 4, -1,
21286 +      {
21287 +       &avr32_ifield_table[AVR32_IFIELD_RD_E],
21288 +       &avr32_ifield_table[AVR32_IFIELD_RX],
21289 +       &avr32_ifield_table[AVR32_IFIELD_RY],
21290 +       &avr32_ifield_table[AVR32_IFIELD_K2],
21291 +      },
21292 +    },
21293 +    {
21294 +      AVR32_OPC_ADDABS, 4, 0xe0000e40, 0xe1f0fff0,
21295 +      &avr32_syntax_table[AVR32_SYNTAX_ADDABS],
21296 +      BFD_RELOC_UNUSED, 3, -1,
21297 +      {
21298 +       &avr32_ifield_table[AVR32_IFIELD_RD_E],
21299 +       &avr32_ifield_table[AVR32_IFIELD_RX],
21300 +       &avr32_ifield_table[AVR32_IFIELD_RY],
21301 +      },
21302 +    },
21303 +    {
21304 +      AVR32_OPC_ADDHH_W, 4, 0xe0000e00, 0xe1f0ffc0,
21305 +      &avr32_syntax_table[AVR32_SYNTAX_ADDHH_W],
21306 +      BFD_RELOC_UNUSED, 5, -1,
21307 +      {
21308 +       &avr32_ifield_table[AVR32_IFIELD_RD_E],
21309 +       &avr32_ifield_table[AVR32_IFIELD_RX],
21310 +       &avr32_ifield_table[AVR32_IFIELD_X],
21311 +       &avr32_ifield_table[AVR32_IFIELD_RY],
21312 +       &avr32_ifield_table[AVR32_IFIELD_Y],
21313 +      },
21314 +    },
21315 +    {
21316 +      AVR32_OPC_AND1, 2, 0x00600000, 0xe1f00000,
21317 +      &avr32_syntax_table[AVR32_SYNTAX_AND1],
21318 +      BFD_RELOC_UNUSED, 2, -1,
21319 +      {
21320 +       &avr32_ifield_table[AVR32_IFIELD_RY],
21321 +       &avr32_ifield_table[AVR32_IFIELD_RX],
21322 +      },
21323 +    },
21324 +    {
21325 +      AVR32_OPC_AND2, 4, 0xe1e00000, 0xe1f0fe00,
21326 +      &avr32_syntax_table[AVR32_SYNTAX_AND2],
21327 +      BFD_RELOC_UNUSED, 4, -1,
21328 +      {
21329 +       &avr32_ifield_table[AVR32_IFIELD_RD_E],
21330 +       &avr32_ifield_table[AVR32_IFIELD_RX],
21331 +       &avr32_ifield_table[AVR32_IFIELD_RY],
21332 +       &avr32_ifield_table[AVR32_IFIELD_K5E2],
21333 +      },
21334 +    },
21335 +    {
21336 +      AVR32_OPC_AND3, 4, 0xe1e00200, 0xe1f0fe00,
21337 +      &avr32_syntax_table[AVR32_SYNTAX_AND3],
21338 +      BFD_RELOC_UNUSED, 4, -1,
21339 +      {
21340 +       &avr32_ifield_table[AVR32_IFIELD_RD_E],
21341 +       &avr32_ifield_table[AVR32_IFIELD_RX],
21342 +       &avr32_ifield_table[AVR32_IFIELD_RY],
21343 +       &avr32_ifield_table[AVR32_IFIELD_K5E2],
21344 +      },
21345 +    },
21346 +    {
21347 +      AVR32_OPC_ANDH, 4, 0xe4100000, 0xfff00000,
21348 +      &avr32_syntax_table[AVR32_SYNTAX_ANDH],
21349 +      BFD_RELOC_AVR32_16U, 2, 1,
21350 +      {
21351 +       &avr32_ifield_table[AVR32_IFIELD_RY],
21352 +       &avr32_ifield_table[AVR32_IFIELD_K16],
21353 +      },
21354 +    },
21355 +    {
21356 +      AVR32_OPC_ANDH_COH, 4, 0xe6100000, 0xfff00000,
21357 +      &avr32_syntax_table[AVR32_SYNTAX_ANDH_COH],
21358 +      BFD_RELOC_AVR32_16U, 2, 1,
21359 +      {
21360 +       &avr32_ifield_table[AVR32_IFIELD_RY],
21361 +       &avr32_ifield_table[AVR32_IFIELD_K16],
21362 +      },
21363 +    },
21364 +    {
21365 +      AVR32_OPC_ANDL, 4, 0xe0100000, 0xfff00000,
21366 +      &avr32_syntax_table[AVR32_SYNTAX_ANDL],
21367 +      BFD_RELOC_AVR32_16U, 2, 1,
21368 +      {
21369 +       &avr32_ifield_table[AVR32_IFIELD_RY],
21370 +       &avr32_ifield_table[AVR32_IFIELD_K16],
21371 +      },
21372 +    },
21373 +    {
21374 +      AVR32_OPC_ANDL_COH, 4, 0xe2100000, 0xfff00000,
21375 +      &avr32_syntax_table[AVR32_SYNTAX_ANDL_COH],
21376 +      BFD_RELOC_AVR32_16U, 2, 1,
21377 +      {
21378 +       &avr32_ifield_table[AVR32_IFIELD_RY],
21379 +       &avr32_ifield_table[AVR32_IFIELD_K16],
21380 +      },
21381 +    },
21382 +    {
21383 +      AVR32_OPC_ANDN, 2, 0x00800000, 0xe1f00000,
21384 +      &avr32_syntax_table[AVR32_SYNTAX_ANDN],
21385 +      BFD_RELOC_UNUSED, 2, -1,
21386 +      {
21387 +       &avr32_ifield_table[AVR32_IFIELD_RY],
21388 +       &avr32_ifield_table[AVR32_IFIELD_RX],
21389 +      },
21390 +    },
21391 +    {
21392 +      AVR32_OPC_ASR1, 4, 0xe0000840, 0xe1f0fff0,
21393 +      &avr32_syntax_table[AVR32_SYNTAX_ASR1],
21394 +      BFD_RELOC_UNUSED, 3, -1,
21395 +      {
21396 +       &avr32_ifield_table[AVR32_IFIELD_RD_E],
21397 +       &avr32_ifield_table[AVR32_IFIELD_RX],
21398 +       &avr32_ifield_table[AVR32_IFIELD_RY],
21399 +      },
21400 +    },
21401 +    {
21402 +      AVR32_OPC_ASR3, 4, 0xe0001400, 0xe1f0ffe0,
21403 +      &avr32_syntax_table[AVR32_SYNTAX_ASR3],
21404 +      BFD_RELOC_UNUSED, 3, -1,
21405 +      {
21406 +       &avr32_ifield_table[AVR32_IFIELD_RY],
21407 +       &avr32_ifield_table[AVR32_IFIELD_RX],
21408 +       &avr32_ifield_table[AVR32_IFIELD_K5E],
21409 +      },
21410 +    },
21411 +    {
21412 +      AVR32_OPC_ASR2, 2, 0xa1400000, 0xe1e00000,
21413 +      &avr32_syntax_table[AVR32_SYNTAX_ASR2],
21414 +      BFD_RELOC_UNUSED, 2, -1,
21415 +      {
21416 +       &avr32_ifield_table[AVR32_IFIELD_RY],
21417 +       &avr32_ifield_table[AVR32_IFIELD_BIT5C],
21418 +      },
21419 +    },
21420 +    {
21421 +      AVR32_OPC_BLD, 4, 0xedb00000, 0xfff0ffe0,
21422 +      &avr32_syntax_table[AVR32_SYNTAX_BLD],
21423 +      BFD_RELOC_UNUSED, 2, -1,
21424 +      {
21425 +       &avr32_ifield_table[AVR32_IFIELD_RY],
21426 +       &avr32_ifield_table[AVR32_IFIELD_K5E],
21427 +      },
21428 +    },
21429 +    {
21430 +      AVR32_OPC_BREQ1, 2, 0xc0000000, 0xf00f0000,
21431 +      &avr32_syntax_table[AVR32_SYNTAX_BREQ1],
21432 +      BFD_RELOC_AVR32_9H_PCREL, 1, 0,
21433 +      {
21434 +       &avr32_ifield_table[AVR32_IFIELD_K8C],
21435 +      },
21436 +    },
21437 +    {
21438 +      AVR32_OPC_BRNE1, 2, 0xc0010000, 0xf00f0000,
21439 +      &avr32_syntax_table[AVR32_SYNTAX_BRNE1],
21440 +      BFD_RELOC_AVR32_9H_PCREL, 1, 0,
21441 +      {
21442 +       &avr32_ifield_table[AVR32_IFIELD_K8C],
21443 +      },
21444 +    },
21445 +    {
21446 +      AVR32_OPC_BRCC1, 2, 0xc0020000, 0xf00f0000,
21447 +      &avr32_syntax_table[AVR32_SYNTAX_BRCC1],
21448 +      BFD_RELOC_AVR32_9H_PCREL, 1, 0,
21449 +      {
21450 +       &avr32_ifield_table[AVR32_IFIELD_K8C],
21451 +      },
21452 +    },
21453 +    {
21454 +      AVR32_OPC_BRCS1, 2, 0xc0030000, 0xf00f0000,
21455 +      &avr32_syntax_table[AVR32_SYNTAX_BRCS1],
21456 +      BFD_RELOC_AVR32_9H_PCREL, 1, 0,
21457 +      {
21458 +       &avr32_ifield_table[AVR32_IFIELD_K8C],
21459 +      },
21460 +    },
21461 +    {
21462 +      AVR32_OPC_BRGE1, 2, 0xc0040000, 0xf00f0000,
21463 +      &avr32_syntax_table[AVR32_SYNTAX_BRGE1],
21464 +      BFD_RELOC_AVR32_9H_PCREL, 1, 0,
21465 +      {
21466 +       &avr32_ifield_table[AVR32_IFIELD_K8C],
21467 +      },
21468 +    },
21469 +    {
21470 +      AVR32_OPC_BRLT1, 2, 0xc0050000, 0xf00f0000,
21471 +      &avr32_syntax_table[AVR32_SYNTAX_BRLT1],
21472 +      BFD_RELOC_AVR32_9H_PCREL, 1, 0,
21473 +      {
21474 +       &avr32_ifield_table[AVR32_IFIELD_K8C],
21475 +      },
21476 +    },
21477 +    {
21478 +      AVR32_OPC_BRMI1, 2, 0xc0060000, 0xf00f0000,
21479 +      &avr32_syntax_table[AVR32_SYNTAX_BRMI1],
21480 +      BFD_RELOC_AVR32_9H_PCREL, 1, 0,
21481 +      {
21482 +       &avr32_ifield_table[AVR32_IFIELD_K8C],
21483 +      },
21484 +    },
21485 +    {
21486 +      AVR32_OPC_BRPL1, 2, 0xc0070000, 0xf00f0000,
21487 +      &avr32_syntax_table[AVR32_SYNTAX_BRPL1],
21488 +      BFD_RELOC_AVR32_9H_PCREL, 1, 0,
21489 +      {
21490 +       &avr32_ifield_table[AVR32_IFIELD_K8C],
21491 +      },
21492 +    },
21493 +    {
21494 +      AVR32_OPC_BREQ2, 4, 0xe0800000, 0xe1ef0000,
21495 +      &avr32_syntax_table[AVR32_SYNTAX_BREQ2],
21496 +      BFD_RELOC_AVR32_22H_PCREL, 1, 0,
21497 +      {
21498 +       &avr32_ifield_table[AVR32_IFIELD_K21],
21499 +      },
21500 +    },
21501 +    {
21502 +      AVR32_OPC_BRNE2, 4, 0xe0810000, 0xe1ef0000,
21503 +      &avr32_syntax_table[AVR32_SYNTAX_BRNE2],
21504 +      BFD_RELOC_AVR32_22H_PCREL, 1, 0,
21505 +      {
21506 +       &avr32_ifield_table[AVR32_IFIELD_K21],
21507 +      },
21508 +    },
21509 +    {
21510 +      AVR32_OPC_BRCC2, 4, 0xe0820000, 0xe1ef0000,
21511 +      &avr32_syntax_table[AVR32_SYNTAX_BRHS2],
21512 +      BFD_RELOC_AVR32_22H_PCREL, 1, 0,
21513 +      {
21514 +       &avr32_ifield_table[AVR32_IFIELD_K21],
21515 +      },
21516 +    },
21517 +    {
21518 +      AVR32_OPC_BRCS2, 4, 0xe0830000, 0xe1ef0000,
21519 +      &avr32_syntax_table[AVR32_SYNTAX_BRLO2],
21520 +      BFD_RELOC_AVR32_22H_PCREL, 1, 0,
21521 +      {
21522 +       &avr32_ifield_table[AVR32_IFIELD_K21],
21523 +      },
21524 +    },
21525 +    {
21526 +      AVR32_OPC_BRGE2, 4, 0xe0840000, 0xe1ef0000,
21527 +      &avr32_syntax_table[AVR32_SYNTAX_BRGE2],
21528 +      BFD_RELOC_AVR32_22H_PCREL, 1, 0,
21529 +      {
21530 +       &avr32_ifield_table[AVR32_IFIELD_K21],
21531 +      },
21532 +    },
21533 +    {
21534 +      AVR32_OPC_BRLT2, 4, 0xe0850000, 0xe1ef0000,
21535 +      &avr32_syntax_table[AVR32_SYNTAX_BRLT2],
21536 +      BFD_RELOC_AVR32_22H_PCREL, 1, 0,
21537 +      {
21538 +       &avr32_ifield_table[AVR32_IFIELD_K21],
21539 +      },
21540 +    },
21541 +    {
21542 +      AVR32_OPC_BRMI2, 4, 0xe0860000, 0xe1ef0000,
21543 +      &avr32_syntax_table[AVR32_SYNTAX_BRMI2],
21544 +      BFD_RELOC_AVR32_22H_PCREL, 1, 0,
21545 +      {
21546 +       &avr32_ifield_table[AVR32_IFIELD_K21],
21547 +      },
21548 +    },
21549 +    {
21550 +      AVR32_OPC_BRPL2, 4, 0xe0870000, 0xe1ef0000,
21551 +      &avr32_syntax_table[AVR32_SYNTAX_BRPL2],
21552 +      BFD_RELOC_AVR32_22H_PCREL, 1, 0,
21553 +      {
21554 +       &avr32_ifield_table[AVR32_IFIELD_K21],
21555 +      },
21556 +    },
21557 +    {
21558 +      AVR32_OPC_BRLS, 4, 0xe0880000, 0xe1ef0000,
21559 +      &avr32_syntax_table[AVR32_SYNTAX_BRLS],
21560 +      BFD_RELOC_AVR32_22H_PCREL, 1, 0,
21561 +      {
21562 +       &avr32_ifield_table[AVR32_IFIELD_K21],
21563 +      },
21564 +    },
21565 +    {
21566 +      AVR32_OPC_BRGT, 4, 0xe0890000, 0xe1ef0000,
21567 +      &avr32_syntax_table[AVR32_SYNTAX_BRGT],
21568 +      BFD_RELOC_AVR32_22H_PCREL, 1, 0,
21569 +      {
21570 +       &avr32_ifield_table[AVR32_IFIELD_K21],
21571 +      },
21572 +    },
21573 +    {
21574 +      AVR32_OPC_BRLE, 4, 0xe08a0000, 0xe1ef0000,
21575 +      &avr32_syntax_table[AVR32_SYNTAX_BRLE],
21576 +      BFD_RELOC_AVR32_22H_PCREL, 1, 0,
21577 +      {
21578 +       &avr32_ifield_table[AVR32_IFIELD_K21],
21579 +      },
21580 +    },
21581 +    {
21582 +      AVR32_OPC_BRHI, 4, 0xe08b0000, 0xe1ef0000,
21583 +      &avr32_syntax_table[AVR32_SYNTAX_BRHI],
21584 +      BFD_RELOC_AVR32_22H_PCREL, 1, 0,
21585 +      {
21586 +       &avr32_ifield_table[AVR32_IFIELD_K21],
21587 +      },
21588 +    },
21589 +    {
21590 +      AVR32_OPC_BRVS, 4, 0xe08c0000, 0xe1ef0000,
21591 +      &avr32_syntax_table[AVR32_SYNTAX_BRVS],
21592 +      BFD_RELOC_AVR32_22H_PCREL, 1, 0,
21593 +      {
21594 +       &avr32_ifield_table[AVR32_IFIELD_K21],
21595 +      },
21596 +    },
21597 +    {
21598 +      AVR32_OPC_BRVC, 4, 0xe08d0000, 0xe1ef0000,
21599 +      &avr32_syntax_table[AVR32_SYNTAX_BRVC],
21600 +      BFD_RELOC_AVR32_22H_PCREL, 1, 0,
21601 +      {
21602 +       &avr32_ifield_table[AVR32_IFIELD_K21],
21603 +      },
21604 +    },
21605 +    {
21606 +      AVR32_OPC_BRQS, 4, 0xe08e0000, 0xe1ef0000,
21607 +      &avr32_syntax_table[AVR32_SYNTAX_BRQS],
21608 +      BFD_RELOC_AVR32_22H_PCREL, 1, 0,
21609 +      {
21610 +       &avr32_ifield_table[AVR32_IFIELD_K21],
21611 +      },
21612 +    },
21613 +    {
21614 +      AVR32_OPC_BRAL, 4, 0xe08f0000, 0xe1ef0000,
21615 +      &avr32_syntax_table[AVR32_SYNTAX_BRAL],
21616 +      BFD_RELOC_AVR32_22H_PCREL, 1, 0,
21617 +      {
21618 +       &avr32_ifield_table[AVR32_IFIELD_K21],
21619 +      },
21620 +    },
21621 +    {
21622 +      AVR32_OPC_BREAKPOINT, 2, 0xd6730000, 0xffff0000,
21623 +      &avr32_syntax_table[AVR32_SYNTAX_BREAKPOINT],
21624 +      BFD_RELOC_UNUSED, 0, -1, { NULL },
21625 +    },
21626 +    {
21627 +      AVR32_OPC_BREV, 2, 0x5c900000, 0xfff00000,
21628 +      &avr32_syntax_table[AVR32_SYNTAX_BREV],
21629 +      BFD_RELOC_UNUSED, 1, -1,
21630 +      {
21631 +       &avr32_ifield_table[AVR32_IFIELD_RY],
21632 +      },
21633 +    },
21634 +    {
21635 +      AVR32_OPC_BST, 4, 0xefb00000, 0xfff0ffe0,
21636 +      &avr32_syntax_table[AVR32_SYNTAX_BST],
21637 +      BFD_RELOC_UNUSED, 2, -1,
21638 +      {
21639 +       &avr32_ifield_table[AVR32_IFIELD_RY],
21640 +       &avr32_ifield_table[AVR32_IFIELD_K5E],
21641 +      },
21642 +    },
21643 +    {
21644 +      AVR32_OPC_CACHE, 4, 0xf4100000, 0xfff00000,
21645 +      &avr32_syntax_table[AVR32_SYNTAX_CACHE],
21646 +      BFD_RELOC_UNUSED, 3, -1,
21647 +      {
21648 +       &avr32_ifield_table[AVR32_IFIELD_RY],
21649 +       &avr32_ifield_table[AVR32_IFIELD_K11],
21650 +       &avr32_ifield_table[AVR32_IFIELD_CACHEOP],
21651 +      },
21652 +    },
21653 +    {
21654 +      AVR32_OPC_CASTS_B, 2, 0x5c600000, 0xfff00000,
21655 +      &avr32_syntax_table[AVR32_SYNTAX_CASTS_B],
21656 +      BFD_RELOC_UNUSED, 1, -1,
21657 +      {
21658 +       &avr32_ifield_table[AVR32_IFIELD_RY],
21659 +      },
21660 +    },
21661 +    {
21662 +      AVR32_OPC_CASTS_H, 2, 0x5c800000, 0xfff00000,
21663 +      &avr32_syntax_table[AVR32_SYNTAX_CASTS_H],
21664 +      BFD_RELOC_UNUSED, 1, -1,
21665 +      {
21666 +       &avr32_ifield_table[AVR32_IFIELD_RY],
21667 +      },
21668 +    },
21669 +    {
21670 +      AVR32_OPC_CASTU_B, 2, 0x5c500000, 0xfff00000,
21671 +      &avr32_syntax_table[AVR32_SYNTAX_CASTU_B],
21672 +      BFD_RELOC_UNUSED, 1, -1,
21673 +      {
21674 +       &avr32_ifield_table[AVR32_IFIELD_RY],
21675 +      },
21676 +    },
21677 +    {
21678 +      AVR32_OPC_CASTU_H, 2, 0x5c700000, 0xfff00000,
21679 +      &avr32_syntax_table[AVR32_SYNTAX_CASTU_H],
21680 +      BFD_RELOC_UNUSED, 1, -1,
21681 +      {
21682 +       &avr32_ifield_table[AVR32_IFIELD_RY],
21683 +      },
21684 +    },
21685 +    {
21686 +      AVR32_OPC_CBR, 2, 0xa1c00000, 0xe1e00000,
21687 +      &avr32_syntax_table[AVR32_SYNTAX_CBR],
21688 +      BFD_RELOC_UNUSED, 2, -1,
21689 +      {
21690 +       &avr32_ifield_table[AVR32_IFIELD_RY],
21691 +       &avr32_ifield_table[AVR32_IFIELD_BIT5C],
21692 +      },
21693 +    },
21694 +    {
21695 +      AVR32_OPC_CLZ, 4, 0xe0001200, 0xe1f0ffff,
21696 +      &avr32_syntax_table[AVR32_SYNTAX_CLZ],
21697 +      BFD_RELOC_UNUSED, 2, -1,
21698 +      {
21699 +       &avr32_ifield_table[AVR32_IFIELD_RY],
21700 +       &avr32_ifield_table[AVR32_IFIELD_RX],
21701 +      },
21702 +    },
21703 +    {
21704 +      AVR32_OPC_COM, 2, 0x5cd00000, 0xfff00000,
21705 +      &avr32_syntax_table[AVR32_SYNTAX_COM],
21706 +      BFD_RELOC_UNUSED, 1, -1,
21707 +      {
21708 +       &avr32_ifield_table[AVR32_IFIELD_RY],
21709 +      },
21710 +    },
21711 +    {
21712 +      AVR32_OPC_COP, 4, 0xe1a00000, 0xf9f00000,
21713 +      &avr32_syntax_table[AVR32_SYNTAX_COP],
21714 +      BFD_RELOC_UNUSED, 5, -1,
21715 +      {
21716 +       &avr32_ifield_table[AVR32_IFIELD_CPNO],
21717 +       &avr32_ifield_table[AVR32_IFIELD_CRD_RI],
21718 +       &avr32_ifield_table[AVR32_IFIELD_CRX],
21719 +       &avr32_ifield_table[AVR32_IFIELD_CRY],
21720 +       &avr32_ifield_table[AVR32_IFIELD_CPOP],
21721 +      },
21722 +    },
21723 +    {
21724 +      AVR32_OPC_CP_B, 4, 0xe0001800, 0xe1f0ffff,
21725 +      &avr32_syntax_table[AVR32_SYNTAX_CP_B],
21726 +      BFD_RELOC_UNUSED, 2, -1,
21727 +      {
21728 +       &avr32_ifield_table[AVR32_IFIELD_RY],
21729 +       &avr32_ifield_table[AVR32_IFIELD_RX],
21730 +      },
21731 +    },
21732 +    {
21733 +      AVR32_OPC_CP_H, 4, 0xe0001900, 0xe1f0ffff,
21734 +      &avr32_syntax_table[AVR32_SYNTAX_CP_H],
21735 +      BFD_RELOC_UNUSED, 2, -1,
21736 +      {
21737 +       &avr32_ifield_table[AVR32_IFIELD_RY],
21738 +       &avr32_ifield_table[AVR32_IFIELD_RX],
21739 +      },
21740 +    },
21741 +    {
21742 +      AVR32_OPC_CP_W1, 2, 0x00300000, 0xe1f00000,
21743 +      &avr32_syntax_table[AVR32_SYNTAX_CP_W1],
21744 +      BFD_RELOC_UNUSED, 2, -1,
21745 +      {
21746 +       &avr32_ifield_table[AVR32_IFIELD_RY],
21747 +       &avr32_ifield_table[AVR32_IFIELD_RX],
21748 +      },
21749 +    },
21750 +    {
21751 +      AVR32_OPC_CP_W2, 2, 0x58000000, 0xfc000000,
21752 +      &avr32_syntax_table[AVR32_SYNTAX_CP_W2],
21753 +      BFD_RELOC_AVR32_6S, 2, 1,
21754 +      {
21755 +       &avr32_ifield_table[AVR32_IFIELD_RY],
21756 +       &avr32_ifield_table[AVR32_IFIELD_K6],
21757 +      },
21758 +    },
21759 +    {
21760 +      AVR32_OPC_CP_W3, 4, 0xe0400000, 0xe1e00000,
21761 +      &avr32_syntax_table[AVR32_SYNTAX_CP_W3],
21762 +      BFD_RELOC_AVR32_21S, 2, 1,
21763 +      {
21764 +       &avr32_ifield_table[AVR32_IFIELD_RY],
21765 +       &avr32_ifield_table[AVR32_IFIELD_K21],
21766 +      },
21767 +    },
21768 +    {
21769 +      AVR32_OPC_CPC1, 4, 0xe0001300, 0xe1f0ffff,
21770 +      &avr32_syntax_table[AVR32_SYNTAX_CPC1],
21771 +      BFD_RELOC_UNUSED, 2, -1,
21772 +      {
21773 +       &avr32_ifield_table[AVR32_IFIELD_RY],
21774 +       &avr32_ifield_table[AVR32_IFIELD_RX],
21775 +      },
21776 +    },
21777 +    {
21778 +      AVR32_OPC_CPC2, 2, 0x5c200000, 0xfff00000,
21779 +      &avr32_syntax_table[AVR32_SYNTAX_CPC2],
21780 +      BFD_RELOC_UNUSED, 1, -1,
21781 +      {
21782 +       &avr32_ifield_table[AVR32_IFIELD_RY],
21783 +      },
21784 +    },
21785 +    {
21786 +      AVR32_OPC_CSRF, 2, 0xd4030000, 0xfe0f0000,
21787 +      &avr32_syntax_table[AVR32_SYNTAX_CSRF],
21788 +      BFD_RELOC_UNUSED, 1, -1,
21789 +      {
21790 +       &avr32_ifield_table[AVR32_IFIELD_K5C],
21791 +      },
21792 +    },
21793 +    {
21794 +      AVR32_OPC_CSRFCZ, 2, 0xd0030000, 0xfe0f0000,
21795 +      &avr32_syntax_table[AVR32_SYNTAX_CSRFCZ],
21796 +      BFD_RELOC_UNUSED, 1, -1,
21797 +      {
21798 +       &avr32_ifield_table[AVR32_IFIELD_K5C],
21799 +      },
21800 +    },
21801 +    {
21802 +      AVR32_OPC_DIVS, 4, 0xe0000c00, 0xe1f0ffc0,
21803 +      &avr32_syntax_table[AVR32_SYNTAX_DIVS],
21804 +      BFD_RELOC_UNUSED, 3, -1,
21805 +      {
21806 +       &avr32_ifield_table[AVR32_IFIELD_RD_E],
21807 +       &avr32_ifield_table[AVR32_IFIELD_RX],
21808 +       &avr32_ifield_table[AVR32_IFIELD_RY],
21809 +      },
21810 +    },
21811 +    {
21812 +      AVR32_OPC_DIVU, 4, 0xe0000d00, 0xe1f0ffc0,
21813 +      &avr32_syntax_table[AVR32_SYNTAX_DIVU],
21814 +      BFD_RELOC_UNUSED, 3, -1,
21815 +      {
21816 +       &avr32_ifield_table[AVR32_IFIELD_RD_E],
21817 +       &avr32_ifield_table[AVR32_IFIELD_RX],
21818 +       &avr32_ifield_table[AVR32_IFIELD_RY],
21819 +      },
21820 +    },
21821 +    {
21822 +      AVR32_OPC_EOR1, 2, 0x00500000, 0xe1f00000,
21823 +      &avr32_syntax_table[AVR32_SYNTAX_EOR1],
21824 +      BFD_RELOC_UNUSED, 2, -1,
21825 +      {
21826 +       &avr32_ifield_table[AVR32_IFIELD_RY],
21827 +       &avr32_ifield_table[AVR32_IFIELD_RX],
21828 +      },
21829 +    },
21830 +    {
21831 +      AVR32_OPC_EOR2, 4, 0xe1e02000, 0xe1f0fe00,
21832 +      &avr32_syntax_table[AVR32_SYNTAX_EOR2],
21833 +      BFD_RELOC_UNUSED, 4, -1,
21834 +      {
21835 +       &avr32_ifield_table[AVR32_IFIELD_RD_E],
21836 +       &avr32_ifield_table[AVR32_IFIELD_RX],
21837 +       &avr32_ifield_table[AVR32_IFIELD_RY],
21838 +       &avr32_ifield_table[AVR32_IFIELD_K5E2],
21839 +      }
21840 +    },
21841 +    {
21842 +      AVR32_OPC_EOR3, 4, 0xe1e02200, 0xe1f0fe00,
21843 +      &avr32_syntax_table[AVR32_SYNTAX_EOR3],
21844 +      BFD_RELOC_UNUSED, 4, -1,
21845 +      {
21846 +       &avr32_ifield_table[AVR32_IFIELD_RD_E],
21847 +       &avr32_ifield_table[AVR32_IFIELD_RX],
21848 +       &avr32_ifield_table[AVR32_IFIELD_RY],
21849 +       &avr32_ifield_table[AVR32_IFIELD_K5E2],
21850 +      }
21851 +    },
21852 +    {
21853 +      AVR32_OPC_EORL, 4, 0xec100000, 0xfff00000,
21854 +      &avr32_syntax_table[AVR32_SYNTAX_EORL],
21855 +      BFD_RELOC_AVR32_16U, 2, 1,
21856 +      {
21857 +       &avr32_ifield_table[AVR32_IFIELD_RY],
21858 +       &avr32_ifield_table[AVR32_IFIELD_K16],
21859 +      },
21860 +    },
21861 +    {
21862 +      AVR32_OPC_EORH, 4, 0xee100000, 0xfff00000,
21863 +      &avr32_syntax_table[AVR32_SYNTAX_EORH],
21864 +      BFD_RELOC_AVR32_16U, 2, 1,
21865 +      {
21866 +       &avr32_ifield_table[AVR32_IFIELD_RY],
21867 +       &avr32_ifield_table[AVR32_IFIELD_K16],
21868 +      },
21869 +    },
21870 +    {
21871 +      AVR32_OPC_FRS, 2, 0xd7430000, 0xffff0000,
21872 +      &avr32_syntax_table[AVR32_SYNTAX_FRS],
21873 +      BFD_RELOC_UNUSED, 0, -1, { NULL },
21874 +    },
21875 +    {
21876 +      AVR32_OPC_ICALL, 2, 0x5d100000, 0xfff00000,
21877 +      &avr32_syntax_table[AVR32_SYNTAX_ICALL],
21878 +      BFD_RELOC_UNUSED, 1, -1,
21879 +      {
21880 +       &avr32_ifield_table[AVR32_IFIELD_RY],
21881 +      },
21882 +    },
21883 +    {
21884 +      AVR32_OPC_INCJOSP, 2, 0xd6830000, 0xff8f0000,
21885 +      &avr32_syntax_table[AVR32_SYNTAX_INCJOSP],
21886 +      BFD_RELOC_UNUSED, 1, -1,
21887 +      {
21888 +       &avr32_ifield_table[AVR32_IFIELD_K3],
21889 +      },
21890 +    },
21891 +    {
21892 +      AVR32_OPC_LD_D1, 2, 0xa1010000, 0xe1f10000,
21893 +      &avr32_syntax_table[AVR32_SYNTAX_LD_D1],
21894 +      BFD_RELOC_UNUSED, 2, -1,
21895 +      {
21896 +       &avr32_ifield_table[AVR32_IFIELD_RY_DW],
21897 +       &avr32_ifield_table[AVR32_IFIELD_RX],
21898 +      },
21899 +    },
21900 +    {
21901 +      AVR32_OPC_LD_D2, 2, 0xa1100000, 0xe1f10000,
21902 +      &avr32_syntax_table[AVR32_SYNTAX_LD_D2],
21903 +      BFD_RELOC_UNUSED, 2, -1,
21904 +      {
21905 +       &avr32_ifield_table[AVR32_IFIELD_RY_DW],
21906 +       &avr32_ifield_table[AVR32_IFIELD_RX],
21907 +      },
21908 +    },
21909 +    {
21910 +      AVR32_OPC_LD_D3, 2, 0xa1000000, 0xe1f10000,
21911 +      &avr32_syntax_table[AVR32_SYNTAX_LD_D3],
21912 +      BFD_RELOC_UNUSED, 2, -1,
21913 +      {
21914 +       &avr32_ifield_table[AVR32_IFIELD_RY_DW],
21915 +       &avr32_ifield_table[AVR32_IFIELD_RX],
21916 +      },
21917 +    },
21918 +    {
21919 +      AVR32_OPC_LD_D5, 4, 0xe0000200, 0xe1f0ffc1,
21920 +      &avr32_syntax_table[AVR32_SYNTAX_LD_D5],
21921 +      BFD_RELOC_UNUSED, 4, -1,
21922 +      {
21923 +       &avr32_ifield_table[AVR32_IFIELD_RD_DW],
21924 +       &avr32_ifield_table[AVR32_IFIELD_RX],
21925 +       &avr32_ifield_table[AVR32_IFIELD_RY],
21926 +       &avr32_ifield_table[AVR32_IFIELD_K2],
21927 +      },
21928 +    },
21929 +    {
21930 +      AVR32_OPC_LD_D4, 4, 0xe0e00000, 0xe1f10000,
21931 +      &avr32_syntax_table[AVR32_SYNTAX_LD_D4],
21932 +      BFD_RELOC_AVR32_16S, 3, 2,
21933 +      {
21934 +       &avr32_ifield_table[AVR32_IFIELD_RY_DW],
21935 +       &avr32_ifield_table[AVR32_IFIELD_RX],
21936 +       &avr32_ifield_table[AVR32_IFIELD_K16],
21937 +      },
21938 +    },
21939 +    {
21940 +      AVR32_OPC_LD_SB2, 4, 0xe0000600, 0xe1f0ffc0,
21941 +      &avr32_syntax_table[AVR32_SYNTAX_LD_SB2],
21942 +      BFD_RELOC_UNUSED, 4, -1,
21943 +      {
21944 +       &avr32_ifield_table[AVR32_IFIELD_RD_E],
21945 +       &avr32_ifield_table[AVR32_IFIELD_RX],
21946 +       &avr32_ifield_table[AVR32_IFIELD_RY],
21947 +       &avr32_ifield_table[AVR32_IFIELD_K2],
21948 +      },
21949 +    },
21950 +    {
21951 +      AVR32_OPC_LD_SB1, 4, 0xe1200000, 0xe1f00000,
21952 +      &avr32_syntax_table[AVR32_SYNTAX_LD_SB1],
21953 +      BFD_RELOC_AVR32_16S, 3, -1,
21954 +      {
21955 +       &avr32_ifield_table[AVR32_IFIELD_RY],
21956 +       &avr32_ifield_table[AVR32_IFIELD_RX],
21957 +       &avr32_ifield_table[AVR32_IFIELD_K16],
21958 +      },
21959 +    },
21960 +    {
21961 +      AVR32_OPC_LD_UB1, 2, 0x01300000, 0xe1f00000,
21962 +      &avr32_syntax_table[AVR32_SYNTAX_LD_UB1],
21963 +      BFD_RELOC_UNUSED, 2, -1,
21964 +      {
21965 +       &avr32_ifield_table[AVR32_IFIELD_RY],
21966 +       &avr32_ifield_table[AVR32_IFIELD_RX],
21967 +      },
21968 +    },
21969 +    {
21970 +      AVR32_OPC_LD_UB2, 2, 0x01700000, 0xe1f00000,
21971 +      &avr32_syntax_table[AVR32_SYNTAX_LD_UB2],
21972 +      BFD_RELOC_UNUSED, 2, -1,
21973 +      {
21974 +       &avr32_ifield_table[AVR32_IFIELD_RY],
21975 +       &avr32_ifield_table[AVR32_IFIELD_RX],
21976 +      },
21977 +    },
21978 +    {
21979 +      AVR32_OPC_LD_UB5, 4, 0xe0000700, 0xe1f0ffc0,
21980 +      &avr32_syntax_table[AVR32_SYNTAX_LD_UB5],
21981 +      BFD_RELOC_UNUSED, 4, -1,
21982 +      {
21983 +       &avr32_ifield_table[AVR32_IFIELD_RD_E],
21984 +       &avr32_ifield_table[AVR32_IFIELD_RX],
21985 +       &avr32_ifield_table[AVR32_IFIELD_RY],
21986 +       &avr32_ifield_table[AVR32_IFIELD_K2],
21987 +      },
21988 +    },
21989 +    {
21990 +      AVR32_OPC_LD_UB3, 2, 0x01800000, 0xe1800000,
21991 +      &avr32_syntax_table[AVR32_SYNTAX_LD_UB3],
21992 +      BFD_RELOC_AVR32_3U, 3, 2,
21993 +      {
21994 +       &avr32_ifield_table[AVR32_IFIELD_RY],
21995 +       &avr32_ifield_table[AVR32_IFIELD_RX],
21996 +       &avr32_ifield_table[AVR32_IFIELD_K3],
21997 +      },
21998 +    },
21999 +    {
22000 +      AVR32_OPC_LD_UB4, 4, 0xe1300000, 0xe1f00000,
22001 +      &avr32_syntax_table[AVR32_SYNTAX_LD_UB4],
22002 +      BFD_RELOC_AVR32_16S, 3, 2,
22003 +      {
22004 +       &avr32_ifield_table[AVR32_IFIELD_RY],
22005 +       &avr32_ifield_table[AVR32_IFIELD_RX],
22006 +       &avr32_ifield_table[AVR32_IFIELD_K16],
22007 +      },
22008 +    },
22009 +    {
22010 +      AVR32_OPC_LD_SH1, 2, 0x01100000, 0xe1f00000,
22011 +      &avr32_syntax_table[AVR32_SYNTAX_LD_SH1],
22012 +      BFD_RELOC_UNUSED, 2, -1,
22013 +      {
22014 +       &avr32_ifield_table[AVR32_IFIELD_RY],
22015 +       &avr32_ifield_table[AVR32_IFIELD_RX],
22016 +      },
22017 +    },
22018 +    {
22019 +      AVR32_OPC_LD_SH2, 2, 0x01500000, 0xe1f00000,
22020 +      &avr32_syntax_table[AVR32_SYNTAX_LD_SH2],
22021 +      BFD_RELOC_UNUSED, 2, -1,
22022 +      {
22023 +       &avr32_ifield_table[AVR32_IFIELD_RY],
22024 +       &avr32_ifield_table[AVR32_IFIELD_RX],
22025 +      },
22026 +    },
22027 +    {
22028 +      AVR32_OPC_LD_SH5, 4, 0xe0000400, 0xe1f0ffc0,
22029 +      &avr32_syntax_table[AVR32_SYNTAX_LD_SH5],
22030 +      BFD_RELOC_UNUSED, 4, -1,
22031 +      {
22032 +       &avr32_ifield_table[AVR32_IFIELD_RD_E],
22033 +       &avr32_ifield_table[AVR32_IFIELD_RX],
22034 +       &avr32_ifield_table[AVR32_IFIELD_RY],
22035 +       &avr32_ifield_table[AVR32_IFIELD_K2],
22036 +      },
22037 +    },
22038 +    {
22039 +      AVR32_OPC_LD_SH3, 2, 0x80000000, 0xe1800000,
22040 +      &avr32_syntax_table[AVR32_SYNTAX_LD_SH3],
22041 +      BFD_RELOC_AVR32_4UH, 3, 2,
22042 +      {
22043 +       &avr32_ifield_table[AVR32_IFIELD_RY],
22044 +       &avr32_ifield_table[AVR32_IFIELD_RX],
22045 +       &avr32_ifield_table[AVR32_IFIELD_K3],
22046 +      },
22047 +    },
22048 +    {
22049 +      AVR32_OPC_LD_SH4, 4, 0xe1000000, 0xe1f00000,
22050 +      &avr32_syntax_table[AVR32_SYNTAX_LD_SH4],
22051 +      BFD_RELOC_AVR32_16S, 3, 2,
22052 +      {
22053 +       &avr32_ifield_table[AVR32_IFIELD_RY],
22054 +       &avr32_ifield_table[AVR32_IFIELD_RX],
22055 +       &avr32_ifield_table[AVR32_IFIELD_K16],
22056 +      },
22057 +    },
22058 +    {
22059 +      AVR32_OPC_LD_UH1, 2, 0x01200000, 0xe1f00000,
22060 +      &avr32_syntax_table[AVR32_SYNTAX_LD_UH1],
22061 +      BFD_RELOC_UNUSED, 2, -1,
22062 +      {
22063 +       &avr32_ifield_table[AVR32_IFIELD_RY],
22064 +       &avr32_ifield_table[AVR32_IFIELD_RX],
22065 +      },
22066 +    },
22067 +    {
22068 +      AVR32_OPC_LD_UH2, 2, 0x01600000, 0xe1f00000,
22069 +      &avr32_syntax_table[AVR32_SYNTAX_LD_UH2],
22070 +      BFD_RELOC_UNUSED, 2, -1,
22071 +      {
22072 +       &avr32_ifield_table[AVR32_IFIELD_RY],
22073 +       &avr32_ifield_table[AVR32_IFIELD_RX],
22074 +      },
22075 +    },
22076 +    {
22077 +      AVR32_OPC_LD_UH5, 4, 0xe0000500, 0xe1f0ffc0,
22078 +      &avr32_syntax_table[AVR32_SYNTAX_LD_UH5],
22079 +      BFD_RELOC_UNUSED, 4, -1,
22080 +      {
22081 +       &avr32_ifield_table[AVR32_IFIELD_RD_E],
22082 +       &avr32_ifield_table[AVR32_IFIELD_RX],
22083 +       &avr32_ifield_table[AVR32_IFIELD_RY],
22084 +       &avr32_ifield_table[AVR32_IFIELD_K2],
22085 +      },
22086 +    },
22087 +    {
22088 +      AVR32_OPC_LD_UH3, 2, 0x80800000, 0xe1800000,
22089 +      &avr32_syntax_table[AVR32_SYNTAX_LD_UH3],
22090 +      BFD_RELOC_AVR32_4UH, 3, 2,
22091 +      {
22092 +       &avr32_ifield_table[AVR32_IFIELD_RY],
22093 +       &avr32_ifield_table[AVR32_IFIELD_RX],
22094 +       &avr32_ifield_table[AVR32_IFIELD_K3],
22095 +      },
22096 +    },
22097 +    {
22098 +      AVR32_OPC_LD_UH4, 4, 0xe1100000, 0xe1f00000,
22099 +      &avr32_syntax_table[AVR32_SYNTAX_LD_UH4],
22100 +      BFD_RELOC_AVR32_16S, 3, 2,
22101 +      {
22102 +       &avr32_ifield_table[AVR32_IFIELD_RY],
22103 +       &avr32_ifield_table[AVR32_IFIELD_RX],
22104 +       &avr32_ifield_table[AVR32_IFIELD_K16],
22105 +      },
22106 +    },
22107 +    {
22108 +      AVR32_OPC_LD_W1, 2, 0x01000000, 0xe1f00000,
22109 +      &avr32_syntax_table[AVR32_SYNTAX_LD_W1],
22110 +      BFD_RELOC_UNUSED, 2, -1,
22111 +      {
22112 +       &avr32_ifield_table[AVR32_IFIELD_RY],
22113 +       &avr32_ifield_table[AVR32_IFIELD_RX],
22114 +      },
22115 +    },
22116 +    {
22117 +      AVR32_OPC_LD_W2, 2, 0x01400000, 0xe1f00000,
22118 +      &avr32_syntax_table[AVR32_SYNTAX_LD_W2],
22119 +      BFD_RELOC_UNUSED, 2, -1,
22120 +      {
22121 +       &avr32_ifield_table[AVR32_IFIELD_RY],
22122 +       &avr32_ifield_table[AVR32_IFIELD_RX],
22123 +      },
22124 +    },
22125 +    {
22126 +      AVR32_OPC_LD_W5, 4, 0xe0000300, 0xe1f0ffc0,
22127 +      &avr32_syntax_table[AVR32_SYNTAX_LD_W5],
22128 +      BFD_RELOC_UNUSED, 4, -1,
22129 +      {
22130 +       &avr32_ifield_table[AVR32_IFIELD_RD_E],
22131 +       &avr32_ifield_table[AVR32_IFIELD_RX],
22132 +       &avr32_ifield_table[AVR32_IFIELD_RY],
22133 +       &avr32_ifield_table[AVR32_IFIELD_K2],
22134 +      },
22135 +    },
22136 +    {
22137 +      AVR32_OPC_LD_W6, 4, 0xe0000f80, 0xe1f0ffc0,
22138 +      &avr32_syntax_table[AVR32_SYNTAX_LD_W6],
22139 +      BFD_RELOC_UNUSED, 4, -1,
22140 +      {
22141 +       &avr32_ifield_table[AVR32_IFIELD_RD_E],
22142 +       &avr32_ifield_table[AVR32_IFIELD_RX],
22143 +       &avr32_ifield_table[AVR32_IFIELD_RY],
22144 +       &avr32_ifield_table[AVR32_IFIELD_K2],
22145 +      },
22146 +    },
22147 +    {
22148 +      AVR32_OPC_LD_W3, 2, 0x60000000, 0xe0000000,
22149 +      &avr32_syntax_table[AVR32_SYNTAX_LD_W3],
22150 +      BFD_RELOC_AVR32_7UW, 3, 2,
22151 +      {
22152 +       &avr32_ifield_table[AVR32_IFIELD_RY],
22153 +       &avr32_ifield_table[AVR32_IFIELD_RX],
22154 +       &avr32_ifield_table[AVR32_IFIELD_K5C],
22155 +      },
22156 +    },
22157 +    {
22158 +      AVR32_OPC_LD_W4, 4, 0xe0f00000, 0xe1f00000,
22159 +      &avr32_syntax_table[AVR32_SYNTAX_LD_W4],
22160 +      BFD_RELOC_AVR32_16S, 3, 2,
22161 +      {
22162 +       &avr32_ifield_table[AVR32_IFIELD_RY],
22163 +       &avr32_ifield_table[AVR32_IFIELD_RX],
22164 +       &avr32_ifield_table[AVR32_IFIELD_K16],
22165 +      },
22166 +    },
22167 +    {
22168 +      AVR32_OPC_LDC_D1, 4, 0xe9a01000, 0xfff01100,
22169 +      &avr32_syntax_table[AVR32_SYNTAX_LDC_D1],
22170 +      BFD_RELOC_AVR32_10UW, 4, 3,
22171 +      {
22172 +       &avr32_ifield_table[AVR32_IFIELD_CPNO],
22173 +       &avr32_ifield_table[AVR32_IFIELD_CRD_DW],
22174 +       &avr32_ifield_table[AVR32_IFIELD_RY],
22175 +       &avr32_ifield_table[AVR32_IFIELD_K8E],
22176 +      },
22177 +    },
22178 +    {
22179 +      AVR32_OPC_LDC_D2, 4, 0xefa00050, 0xfff011ff,
22180 +      &avr32_syntax_table[AVR32_SYNTAX_LDC_D2],
22181 +      BFD_RELOC_UNUSED, 3, -1,
22182 +      {
22183 +       &avr32_ifield_table[AVR32_IFIELD_CPNO],
22184 +       &avr32_ifield_table[AVR32_IFIELD_CRD_DW],
22185 +       &avr32_ifield_table[AVR32_IFIELD_RY],
22186 +      },
22187 +    },
22188 +    {
22189 +      AVR32_OPC_LDC_D3, 4, 0xefa01040, 0xfff011c0,
22190 +      &avr32_syntax_table[AVR32_SYNTAX_LDC_D3],
22191 +      BFD_RELOC_UNUSED, 5, -1,
22192 +      {
22193 +       &avr32_ifield_table[AVR32_IFIELD_CPNO],
22194 +       &avr32_ifield_table[AVR32_IFIELD_CRD_DW],
22195 +       &avr32_ifield_table[AVR32_IFIELD_RY],
22196 +       &avr32_ifield_table[AVR32_IFIELD_RD_E],
22197 +       &avr32_ifield_table[AVR32_IFIELD_K2],
22198 +      },
22199 +    },
22200 +    {
22201 +      AVR32_OPC_LDC_W1, 4, 0xe9a00000, 0xfff01000,
22202 +      &avr32_syntax_table[AVR32_SYNTAX_LDC_W1],
22203 +      BFD_RELOC_AVR32_10UW, 4, 3,
22204 +      {
22205 +       &avr32_ifield_table[AVR32_IFIELD_CPNO],
22206 +       &avr32_ifield_table[AVR32_IFIELD_CRD_RI],
22207 +       &avr32_ifield_table[AVR32_IFIELD_RY],
22208 +       &avr32_ifield_table[AVR32_IFIELD_K8E],
22209 +      },
22210 +    },
22211 +    {
22212 +      AVR32_OPC_LDC_W2, 4, 0xefa00040, 0xfff010ff,
22213 +      &avr32_syntax_table[AVR32_SYNTAX_LDC_W2],
22214 +      BFD_RELOC_UNUSED, 3, -1,
22215 +      {
22216 +       &avr32_ifield_table[AVR32_IFIELD_CPNO],
22217 +       &avr32_ifield_table[AVR32_IFIELD_CRD_RI],
22218 +       &avr32_ifield_table[AVR32_IFIELD_RY],
22219 +      },
22220 +    },
22221 +    {
22222 +      AVR32_OPC_LDC_W3, 4, 0xefa01000, 0xfff010c0,
22223 +      &avr32_syntax_table[AVR32_SYNTAX_LDC_W3],
22224 +      BFD_RELOC_UNUSED, 5, -1,
22225 +      {
22226 +       &avr32_ifield_table[AVR32_IFIELD_CPNO],
22227 +       &avr32_ifield_table[AVR32_IFIELD_CRD_RI],
22228 +       &avr32_ifield_table[AVR32_IFIELD_RY],
22229 +       &avr32_ifield_table[AVR32_IFIELD_RD_E],
22230 +       &avr32_ifield_table[AVR32_IFIELD_K2],
22231 +      },
22232 +    },
22233 +    {
22234 +      AVR32_OPC_LDC0_D, 4, 0xf3a00000, 0xfff00100,
22235 +      &avr32_syntax_table[AVR32_SYNTAX_LDC0_D],
22236 +      BFD_RELOC_AVR32_14UW, 3, 2,
22237 +      {
22238 +       &avr32_ifield_table[AVR32_IFIELD_CRD_DW],
22239 +       &avr32_ifield_table[AVR32_IFIELD_RY],
22240 +       &avr32_ifield_table[AVR32_IFIELD_K12CP],
22241 +      },
22242 +    },
22243 +    {
22244 +      AVR32_OPC_LDC0_W, 4, 0xf1a00000, 0xfff00000,
22245 +      &avr32_syntax_table[AVR32_SYNTAX_LDC0_W],
22246 +      BFD_RELOC_AVR32_14UW, 3, 2,
22247 +      {
22248 +       &avr32_ifield_table[AVR32_IFIELD_CRD_RI],
22249 +       &avr32_ifield_table[AVR32_IFIELD_RY],
22250 +       &avr32_ifield_table[AVR32_IFIELD_K12CP],
22251 +      },
22252 +    },
22253 +    {
22254 +      AVR32_OPC_LDCM_D, 4, 0xeda00400, 0xfff01f00,
22255 +      &avr32_syntax_table[AVR32_SYNTAX_LDCM_D],
22256 +      BFD_RELOC_UNUSED, 3, -1,
22257 +      {
22258 +       &avr32_ifield_table[AVR32_IFIELD_CPNO],
22259 +       &avr32_ifield_table[AVR32_IFIELD_RY],
22260 +       &avr32_ifield_table[AVR32_IFIELD_K8E],
22261 +      },
22262 +    },
22263 +    {
22264 +      AVR32_OPC_LDCM_D_PU, 4, 0xeda01400, 0xfff01f00,
22265 +      &avr32_syntax_table[AVR32_SYNTAX_LDCM_D_PU],
22266 +      BFD_RELOC_UNUSED, 3, -1,
22267 +      {
22268 +       &avr32_ifield_table[AVR32_IFIELD_CPNO],
22269 +       &avr32_ifield_table[AVR32_IFIELD_RY],
22270 +       &avr32_ifield_table[AVR32_IFIELD_K8E],
22271 +      },
22272 +    },
22273 +    {
22274 +      AVR32_OPC_LDCM_W, 4, 0xeda00000, 0xfff01e00,
22275 +      &avr32_syntax_table[AVR32_SYNTAX_LDCM_W],
22276 +      BFD_RELOC_UNUSED, 4, -1,
22277 +      {
22278 +       &avr32_ifield_table[AVR32_IFIELD_CPNO],
22279 +       &avr32_ifield_table[AVR32_IFIELD_RY],
22280 +       &avr32_ifield_table[AVR32_IFIELD_K8E],
22281 +       &avr32_ifield_table[AVR32_IFIELD_CM_HL],
22282 +      },
22283 +    },
22284 +    {
22285 +      AVR32_OPC_LDCM_W_PU, 4, 0xeda01000, 0xfff01e00,
22286 +      &avr32_syntax_table[AVR32_SYNTAX_LDCM_W_PU],
22287 +      BFD_RELOC_UNUSED, 4, -1,
22288 +      {
22289 +       &avr32_ifield_table[AVR32_IFIELD_CPNO],
22290 +       &avr32_ifield_table[AVR32_IFIELD_RY],
22291 +       &avr32_ifield_table[AVR32_IFIELD_K8E],
22292 +       &avr32_ifield_table[AVR32_IFIELD_CM_HL],
22293 +      },
22294 +    },
22295 +    {
22296 +      AVR32_OPC_LDDPC, 2, 0x48000000, 0xf8000000,
22297 +      &avr32_syntax_table[AVR32_SYNTAX_LDDPC],
22298 +      BFD_RELOC_AVR32_9UW_PCREL, 2, 1,
22299 +      {
22300 +       &avr32_ifield_table[AVR32_IFIELD_RY],
22301 +       &avr32_ifield_table[AVR32_IFIELD_K7C],
22302 +      },
22303 +    },
22304 +    {
22305 +      AVR32_OPC_LDDPC_EXT, 4, 0xfef00000, 0xfff00000,
22306 +      &avr32_syntax_table[AVR32_SYNTAX_LDDPC_EXT],
22307 +      BFD_RELOC_AVR32_16B_PCREL, 2, 1,
22308 +      {
22309 +       &avr32_ifield_table[AVR32_IFIELD_RY],
22310 +       &avr32_ifield_table[AVR32_IFIELD_K16],
22311 +      },
22312 +    },
22313 +    {
22314 +      AVR32_OPC_LDDSP, 2, 0x40000000, 0xf8000000,
22315 +      &avr32_syntax_table[AVR32_SYNTAX_LDDSP],
22316 +      BFD_RELOC_UNUSED, 2, -1,
22317 +      {
22318 +       &avr32_ifield_table[AVR32_IFIELD_RY],
22319 +       &avr32_ifield_table[AVR32_IFIELD_K7C],
22320 +      },
22321 +    },
22322 +    {
22323 +      AVR32_OPC_LDINS_B, 4, 0xe1d04000, 0xe1f0c000,
22324 +      &avr32_syntax_table[AVR32_SYNTAX_LDINS_B],
22325 +      BFD_RELOC_UNUSED, 4, -1,
22326 +      {
22327 +       &avr32_ifield_table[AVR32_IFIELD_RY],
22328 +       &avr32_ifield_table[AVR32_IFIELD_PART2_K12],
22329 +       &avr32_ifield_table[AVR32_IFIELD_RX],
22330 +       &avr32_ifield_table[AVR32_IFIELD_K12],
22331 +      },
22332 +    },
22333 +    {
22334 +      AVR32_OPC_LDINS_H, 4, 0xe1d00000, 0xe1f0e000,
22335 +      &avr32_syntax_table[AVR32_SYNTAX_LDINS_H],
22336 +      BFD_RELOC_UNUSED, 4, -1,
22337 +      {
22338 +       &avr32_ifield_table[AVR32_IFIELD_RY],
22339 +       &avr32_ifield_table[AVR32_IFIELD_PART1_K12],
22340 +       &avr32_ifield_table[AVR32_IFIELD_RX],
22341 +       &avr32_ifield_table[AVR32_IFIELD_K12],
22342 +      },
22343 +    },
22344 +    {
22345 +      AVR32_OPC_LDM, 4, 0xe1c00000, 0xfdf00000,
22346 +      &avr32_syntax_table[AVR32_SYNTAX_LDM],
22347 +      BFD_RELOC_UNUSED, 3, -1,
22348 +      {
22349 +       &avr32_ifield_table[AVR32_IFIELD_RY],
22350 +       &avr32_ifield_table[AVR32_IFIELD_W],
22351 +       &avr32_ifield_table[AVR32_IFIELD_K16],
22352 +      },
22353 +    },
22354 +    {
22355 +      AVR32_OPC_LDMTS, 4, 0xe5c00000, 0xfff00000,
22356 +      &avr32_syntax_table[AVR32_SYNTAX_LDMTS],
22357 +      BFD_RELOC_UNUSED, 2, -1,
22358 +      {
22359 +       &avr32_ifield_table[AVR32_IFIELD_RY],
22360 +       &avr32_ifield_table[AVR32_IFIELD_K16],
22361 +      },
22362 +    },
22363 +    {
22364 +      AVR32_OPC_LDMTS_PU, 4, 0xe7c00000, 0xfff00000,
22365 +      &avr32_syntax_table[AVR32_SYNTAX_LDMTS_PU],
22366 +      BFD_RELOC_UNUSED, 2, -1,
22367 +      {
22368 +       &avr32_ifield_table[AVR32_IFIELD_RY],
22369 +       &avr32_ifield_table[AVR32_IFIELD_K16],
22370 +      },
22371 +    },
22372 +    {
22373 +      AVR32_OPC_LDSWP_SH, 4, 0xe1d02000, 0xe1f0f000,
22374 +      &avr32_syntax_table[AVR32_SYNTAX_LDSWP_SH],
22375 +      BFD_RELOC_UNUSED, 3, -1,
22376 +      {
22377 +       &avr32_ifield_table[AVR32_IFIELD_RY],
22378 +       &avr32_ifield_table[AVR32_IFIELD_RX],
22379 +       &avr32_ifield_table[AVR32_IFIELD_K12],
22380 +      },
22381 +    },
22382 +    {
22383 +      AVR32_OPC_LDSWP_UH, 4, 0xe1d03000, 0xe1f0f000,
22384 +      &avr32_syntax_table[AVR32_SYNTAX_LDSWP_UH],
22385 +      BFD_RELOC_UNUSED, 3, -1,
22386 +      {
22387 +       &avr32_ifield_table[AVR32_IFIELD_RY],
22388 +       &avr32_ifield_table[AVR32_IFIELD_RX],
22389 +       &avr32_ifield_table[AVR32_IFIELD_K12],
22390 +      },
22391 +    },
22392 +    {
22393 +      AVR32_OPC_LDSWP_W, 4, 0xe1d08000, 0xe1f0f000,
22394 +      &avr32_syntax_table[AVR32_SYNTAX_LDSWP_W],
22395 +      BFD_RELOC_UNUSED, 3, -1,
22396 +      {
22397 +       &avr32_ifield_table[AVR32_IFIELD_RY],
22398 +       &avr32_ifield_table[AVR32_IFIELD_RX],
22399 +       &avr32_ifield_table[AVR32_IFIELD_K12],
22400 +      },
22401 +    },
22402 +    {
22403 +      AVR32_OPC_LSL1, 4, 0xe0000940, 0xe1f0fff0,
22404 +      &avr32_syntax_table[AVR32_SYNTAX_LSL1],
22405 +      BFD_RELOC_UNUSED, 3, -1,
22406 +      {
22407 +       &avr32_ifield_table[AVR32_IFIELD_RD_E],
22408 +       &avr32_ifield_table[AVR32_IFIELD_RX],
22409 +       &avr32_ifield_table[AVR32_IFIELD_RY],
22410 +      },
22411 +    },
22412 +    {
22413 +      AVR32_OPC_LSL3, 4, 0xe0001500, 0xe1f0ffe0,
22414 +      &avr32_syntax_table[AVR32_SYNTAX_LSL3],
22415 +      BFD_RELOC_UNUSED, 3, -1,
22416 +      {
22417 +       &avr32_ifield_table[AVR32_IFIELD_RY],
22418 +       &avr32_ifield_table[AVR32_IFIELD_RX],
22419 +       &avr32_ifield_table[AVR32_IFIELD_K5E],
22420 +      },
22421 +    },
22422 +    {
22423 +      AVR32_OPC_LSL2, 2, 0xa1600000, 0xe1e00000,
22424 +      &avr32_syntax_table[AVR32_SYNTAX_LSL2],
22425 +      BFD_RELOC_UNUSED, 2, -1,
22426 +      {
22427 +       &avr32_ifield_table[AVR32_IFIELD_RY],
22428 +       &avr32_ifield_table[AVR32_IFIELD_BIT5C],
22429 +      },
22430 +    },
22431 +    {
22432 +      AVR32_OPC_LSR1, 4, 0xe0000a40, 0xe1f0fff0,
22433 +      &avr32_syntax_table[AVR32_SYNTAX_LSR1],
22434 +      BFD_RELOC_UNUSED, 3, -1,
22435 +      {
22436 +       &avr32_ifield_table[AVR32_IFIELD_RD_E],
22437 +       &avr32_ifield_table[AVR32_IFIELD_RX],
22438 +       &avr32_ifield_table[AVR32_IFIELD_RY],
22439 +      },
22440 +    },
22441 +    {
22442 +      AVR32_OPC_LSR3, 4, 0xe0001600, 0xe1f0ffe0,
22443 +      &avr32_syntax_table[AVR32_SYNTAX_LSR3],
22444 +      BFD_RELOC_UNUSED, 3, -1,
22445 +      {
22446 +       &avr32_ifield_table[AVR32_IFIELD_RY],
22447 +       &avr32_ifield_table[AVR32_IFIELD_RX],
22448 +       &avr32_ifield_table[AVR32_IFIELD_K5E],
22449 +      },
22450 +    },
22451 +    {
22452 +      AVR32_OPC_LSR2, 2, 0xa1800000, 0xe1e00000,
22453 +      &avr32_syntax_table[AVR32_SYNTAX_LSR2],
22454 +      BFD_RELOC_UNUSED, 2, -1,
22455 +      {
22456 +       &avr32_ifield_table[AVR32_IFIELD_RY],
22457 +       &avr32_ifield_table[AVR32_IFIELD_BIT5C],
22458 +      },
22459 +    },
22460 +    {
22461 +      AVR32_OPC_MAC, 4, 0xe0000340, 0xe1f0fff0,
22462 +      &avr32_syntax_table[AVR32_SYNTAX_MAC],
22463 +      BFD_RELOC_UNUSED, 3, -1,
22464 +      {
22465 +       &avr32_ifield_table[AVR32_IFIELD_RD_E],
22466 +       &avr32_ifield_table[AVR32_IFIELD_RX],
22467 +       &avr32_ifield_table[AVR32_IFIELD_RY],
22468 +      },
22469 +    },
22470 +    {
22471 +      AVR32_OPC_MACHH_D, 4, 0xe0000580, 0xe1f0ffc1,
22472 +      &avr32_syntax_table[AVR32_SYNTAX_MACHH_D],
22473 +      BFD_RELOC_UNUSED, 5, -1,
22474 +      {
22475 +       &avr32_ifield_table[AVR32_IFIELD_RD_E],
22476 +       &avr32_ifield_table[AVR32_IFIELD_RX],
22477 +       &avr32_ifield_table[AVR32_IFIELD_X],
22478 +       &avr32_ifield_table[AVR32_IFIELD_RY],
22479 +       &avr32_ifield_table[AVR32_IFIELD_Y],
22480 +      },
22481 +    },
22482 +    {
22483 +      AVR32_OPC_MACHH_W, 4, 0xe0000480, 0xe1f0ffc0,
22484 +      &avr32_syntax_table[AVR32_SYNTAX_MACHH_W],
22485 +      BFD_RELOC_UNUSED, 5, -1,
22486 +      {
22487 +       &avr32_ifield_table[AVR32_IFIELD_RD_E],
22488 +       &avr32_ifield_table[AVR32_IFIELD_RX],
22489 +       &avr32_ifield_table[AVR32_IFIELD_X],
22490 +       &avr32_ifield_table[AVR32_IFIELD_RY],
22491 +       &avr32_ifield_table[AVR32_IFIELD_Y],
22492 +      },
22493 +    },
22494 +    {
22495 +      AVR32_OPC_MACS_D, 4, 0xe0000540, 0xe1f0fff1,
22496 +      &avr32_syntax_table[AVR32_SYNTAX_MACS_D],
22497 +      BFD_RELOC_UNUSED, 3, -1,
22498 +      {
22499 +       &avr32_ifield_table[AVR32_IFIELD_RD_E],
22500 +       &avr32_ifield_table[AVR32_IFIELD_RX],
22501 +       &avr32_ifield_table[AVR32_IFIELD_RY],
22502 +      },
22503 +    },
22504 +    {
22505 +      AVR32_OPC_MACSATHH_W, 4, 0xe0000680, 0xe1f0ffc0,
22506 +      &avr32_syntax_table[AVR32_SYNTAX_MACSATHH_W],
22507 +      BFD_RELOC_UNUSED, 5, -1,
22508 +      {
22509 +       &avr32_ifield_table[AVR32_IFIELD_RD_E],
22510 +       &avr32_ifield_table[AVR32_IFIELD_RX],
22511 +       &avr32_ifield_table[AVR32_IFIELD_X],
22512 +       &avr32_ifield_table[AVR32_IFIELD_RY],
22513 +       &avr32_ifield_table[AVR32_IFIELD_Y],
22514 +      },
22515 +    },
22516 +    {
22517 +      AVR32_OPC_MACUD, 4, 0xe0000740, 0xe1f0fff1,
22518 +      &avr32_syntax_table[AVR32_SYNTAX_MACUD],
22519 +      BFD_RELOC_UNUSED, 3, -1,
22520 +      {
22521 +       &avr32_ifield_table[AVR32_IFIELD_RD_E],
22522 +       &avr32_ifield_table[AVR32_IFIELD_RX],
22523 +       &avr32_ifield_table[AVR32_IFIELD_RY],
22524 +      },
22525 +    },
22526 +    {
22527 +      AVR32_OPC_MACWH_D, 4, 0xe0000c80, 0xe1f0ffe1,
22528 +      &avr32_syntax_table[AVR32_SYNTAX_MACWH_D],
22529 +      BFD_RELOC_UNUSED, 4, -1,
22530 +      {
22531 +       &avr32_ifield_table[AVR32_IFIELD_RD_E],
22532 +       &avr32_ifield_table[AVR32_IFIELD_RX],
22533 +       &avr32_ifield_table[AVR32_IFIELD_RY],
22534 +       &avr32_ifield_table[AVR32_IFIELD_Y],
22535 +      },
22536 +    },
22537 +    {
22538 +      AVR32_OPC_MAX, 4, 0xe0000c40, 0xe1f0fff0,
22539 +      &avr32_syntax_table[AVR32_SYNTAX_MAX],
22540 +      BFD_RELOC_UNUSED, 3, -1,
22541 +      {
22542 +       &avr32_ifield_table[AVR32_IFIELD_RD_E],
22543 +       &avr32_ifield_table[AVR32_IFIELD_RX],
22544 +       &avr32_ifield_table[AVR32_IFIELD_RY],
22545 +      },
22546 +    },
22547 +    {
22548 +      AVR32_OPC_MCALL, 4, 0xf0100000, 0xfff00000,
22549 +      &avr32_syntax_table[AVR32_SYNTAX_MCALL],
22550 +      BFD_RELOC_AVR32_18W_PCREL, 2, 1,
22551 +      {
22552 +       &avr32_ifield_table[AVR32_IFIELD_RY],
22553 +       &avr32_ifield_table[AVR32_IFIELD_K16],
22554 +      },
22555 +    },
22556 +    {
22557 +      AVR32_OPC_MFDR, 4, 0xe5b00000, 0xfff0ff00,
22558 +      &avr32_syntax_table[AVR32_SYNTAX_MFDR],
22559 +      BFD_RELOC_AVR32_8S_EXT, 2, 1,
22560 +      {
22561 +       &avr32_ifield_table[AVR32_IFIELD_RY],
22562 +       &avr32_ifield_table[AVR32_IFIELD_K8E],
22563 +      },
22564 +    },
22565 +    {
22566 +      AVR32_OPC_MFSR, 4, 0xe1b00000, 0xfff0ff00,
22567 +      &avr32_syntax_table[AVR32_SYNTAX_MFSR],
22568 +      BFD_RELOC_AVR32_8S_EXT, 2, 1,
22569 +      {
22570 +       &avr32_ifield_table[AVR32_IFIELD_RY],
22571 +       &avr32_ifield_table[AVR32_IFIELD_K8E],
22572 +      },
22573 +    },
22574 +    {
22575 +      AVR32_OPC_MIN, 4, 0xe0000d40, 0xe1f0fff0,
22576 +      &avr32_syntax_table[AVR32_SYNTAX_MIN],
22577 +      BFD_RELOC_UNUSED, 3, -1,
22578 +      {
22579 +       &avr32_ifield_table[AVR32_IFIELD_RD_E],
22580 +       &avr32_ifield_table[AVR32_IFIELD_RX],
22581 +       &avr32_ifield_table[AVR32_IFIELD_RY],
22582 +      },
22583 +    },
22584 +    {
22585 +      AVR32_OPC_MOV3, 2, 0x00900000, 0xe1f00000,
22586 +      &avr32_syntax_table[AVR32_SYNTAX_MOV3],
22587 +      BFD_RELOC_NONE, 2, -1,
22588 +      {
22589 +       &avr32_ifield_table[AVR32_IFIELD_RY],
22590 +       &avr32_ifield_table[AVR32_IFIELD_RX],
22591 +      },
22592 +    },
22593 +    {
22594 +      AVR32_OPC_MOV1, 2, 0x30000000, 0xf0000000,
22595 +      &avr32_syntax_table[AVR32_SYNTAX_MOV1],
22596 +      BFD_RELOC_AVR32_8S, 2, 1,
22597 +      {
22598 +       &avr32_ifield_table[AVR32_IFIELD_RY],
22599 +       &avr32_ifield_table[AVR32_IFIELD_K8C],
22600 +      },
22601 +    },
22602 +    {
22603 +      AVR32_OPC_MOV2, 4, 0xe0600000, 0xe1e00000,
22604 +      &avr32_syntax_table[AVR32_SYNTAX_MOV2],
22605 +      BFD_RELOC_AVR32_21S, 2, 1,
22606 +      {
22607 +       &avr32_ifield_table[AVR32_IFIELD_RY],
22608 +       &avr32_ifield_table[AVR32_IFIELD_K21],
22609 +      },
22610 +    },
22611 +    {
22612 +      AVR32_OPC_MOVEQ1, 4, 0xe0001700, 0xe1f0ffff,
22613 +      &avr32_syntax_table[AVR32_SYNTAX_MOVEQ1],
22614 +      BFD_RELOC_UNUSED, 2, -1,
22615 +      {
22616 +       &avr32_ifield_table[AVR32_IFIELD_RY],
22617 +       &avr32_ifield_table[AVR32_IFIELD_RX],
22618 +      },
22619 +    },
22620 +    {
22621 +      AVR32_OPC_MOVNE1, 4, 0xe0001710, 0xe1f0ffff,
22622 +      &avr32_syntax_table[AVR32_SYNTAX_MOVNE1],
22623 +      BFD_RELOC_UNUSED, 2, -1,
22624 +      {
22625 +       &avr32_ifield_table[AVR32_IFIELD_RY],
22626 +       &avr32_ifield_table[AVR32_IFIELD_RX],
22627 +      },
22628 +    },
22629 +    {
22630 +      AVR32_OPC_MOVCC1, 4, 0xe0001720, 0xe1f0ffff,
22631 +      &avr32_syntax_table[AVR32_SYNTAX_MOVHS1],
22632 +      BFD_RELOC_UNUSED, 2, -1,
22633 +      {
22634 +       &avr32_ifield_table[AVR32_IFIELD_RY],
22635 +       &avr32_ifield_table[AVR32_IFIELD_RX],
22636 +      },
22637 +    },
22638 +    {
22639 +      AVR32_OPC_MOVCS1, 4, 0xe0001730, 0xe1f0ffff,
22640 +      &avr32_syntax_table[AVR32_SYNTAX_MOVLO1],
22641 +      BFD_RELOC_UNUSED, 2, -1,
22642 +      {
22643 +       &avr32_ifield_table[AVR32_IFIELD_RY],
22644 +       &avr32_ifield_table[AVR32_IFIELD_RX],
22645 +      },
22646 +    },
22647 +    {
22648 +      AVR32_OPC_MOVGE1, 4, 0xe0001740, 0xe1f0ffff,
22649 +      &avr32_syntax_table[AVR32_SYNTAX_MOVGE1],
22650 +      BFD_RELOC_UNUSED, 2, -1,
22651 +      {
22652 +       &avr32_ifield_table[AVR32_IFIELD_RY],
22653 +       &avr32_ifield_table[AVR32_IFIELD_RX],
22654 +      },
22655 +    },
22656 +    {
22657 +      AVR32_OPC_MOVLT1, 4, 0xe0001750, 0xe1f0ffff,
22658 +      &avr32_syntax_table[AVR32_SYNTAX_MOVLT1],
22659 +      BFD_RELOC_UNUSED, 2, -1,
22660 +      {
22661 +       &avr32_ifield_table[AVR32_IFIELD_RY],
22662 +       &avr32_ifield_table[AVR32_IFIELD_RX],
22663 +      },
22664 +    },
22665 +    {
22666 +      AVR32_OPC_MOVMI1, 4, 0xe0001760, 0xe1f0ffff,
22667 +      &avr32_syntax_table[AVR32_SYNTAX_MOVMI1],
22668 +      BFD_RELOC_UNUSED, 2, -1,
22669 +      {
22670 +       &avr32_ifield_table[AVR32_IFIELD_RY],
22671 +       &avr32_ifield_table[AVR32_IFIELD_RX],
22672 +      },
22673 +    },
22674 +    {
22675 +      AVR32_OPC_MOVPL1, 4, 0xe0001770, 0xe1f0ffff,
22676 +      &avr32_syntax_table[AVR32_SYNTAX_MOVPL1],
22677 +      BFD_RELOC_UNUSED, 2, -1,
22678 +      {
22679 +       &avr32_ifield_table[AVR32_IFIELD_RY],
22680 +       &avr32_ifield_table[AVR32_IFIELD_RX],
22681 +      },
22682 +    },
22683 +    {
22684 +      AVR32_OPC_MOVLS1, 4, 0xe0001780, 0xe1f0ffff,
22685 +      &avr32_syntax_table[AVR32_SYNTAX_MOVLS1],
22686 +      BFD_RELOC_UNUSED, 2, -1,
22687 +      {
22688 +       &avr32_ifield_table[AVR32_IFIELD_RY],
22689 +       &avr32_ifield_table[AVR32_IFIELD_RX],
22690 +      },
22691 +    },
22692 +    {
22693 +      AVR32_OPC_MOVGT1, 4, 0xe0001790, 0xe1f0ffff,
22694 +      &avr32_syntax_table[AVR32_SYNTAX_MOVGT1],
22695 +      BFD_RELOC_UNUSED, 2, -1,
22696 +      {
22697 +       &avr32_ifield_table[AVR32_IFIELD_RY],
22698 +       &avr32_ifield_table[AVR32_IFIELD_RX],
22699 +      },
22700 +    },
22701 +    {
22702 +      AVR32_OPC_MOVLE1, 4, 0xe00017a0, 0xe1f0ffff,
22703 +      &avr32_syntax_table[AVR32_SYNTAX_MOVLE1],
22704 +      BFD_RELOC_UNUSED, 2, -1,
22705 +      {
22706 +       &avr32_ifield_table[AVR32_IFIELD_RY],
22707 +       &avr32_ifield_table[AVR32_IFIELD_RX],
22708 +      },
22709 +    },
22710 +    {
22711 +      AVR32_OPC_MOVHI1, 4, 0xe00017b0, 0xe1f0ffff,
22712 +      &avr32_syntax_table[AVR32_SYNTAX_MOVHI1],
22713 +      BFD_RELOC_UNUSED, 2, -1,
22714 +      {
22715 +       &avr32_ifield_table[AVR32_IFIELD_RY],
22716 +       &avr32_ifield_table[AVR32_IFIELD_RX],
22717 +      },
22718 +    },
22719 +    {
22720 +      AVR32_OPC_MOVVS1, 4, 0xe00017c0, 0xe1f0ffff,
22721 +      &avr32_syntax_table[AVR32_SYNTAX_MOVVS1],
22722 +      BFD_RELOC_UNUSED, 2, -1,
22723 +      {
22724 +       &avr32_ifield_table[AVR32_IFIELD_RY],
22725 +       &avr32_ifield_table[AVR32_IFIELD_RX],
22726 +      },
22727 +    },
22728 +    {
22729 +      AVR32_OPC_MOVVC1, 4, 0xe00017d0, 0xe1f0ffff,
22730 +      &avr32_syntax_table[AVR32_SYNTAX_MOVVC1],
22731 +      BFD_RELOC_UNUSED, 2, -1,
22732 +      {
22733 +       &avr32_ifield_table[AVR32_IFIELD_RY],
22734 +       &avr32_ifield_table[AVR32_IFIELD_RX],
22735 +      },
22736 +    },
22737 +    {
22738 +      AVR32_OPC_MOVQS1, 4, 0xe00017e0, 0xe1f0ffff,
22739 +      &avr32_syntax_table[AVR32_SYNTAX_MOVQS1],
22740 +      BFD_RELOC_UNUSED, 2, -1,
22741 +      {
22742 +       &avr32_ifield_table[AVR32_IFIELD_RY],
22743 +       &avr32_ifield_table[AVR32_IFIELD_RX],
22744 +      },
22745 +    },
22746 +    {
22747 +      AVR32_OPC_MOVAL1, 4, 0xe00017f0, 0xe1f0ffff,
22748 +      &avr32_syntax_table[AVR32_SYNTAX_MOVAL1],
22749 +      BFD_RELOC_UNUSED, 2, -1,
22750 +      {
22751 +       &avr32_ifield_table[AVR32_IFIELD_RY],
22752 +       &avr32_ifield_table[AVR32_IFIELD_RX],
22753 +      },
22754 +    },
22755 +    {
22756 +      AVR32_OPC_MOVEQ2, 4, 0xf9b00000, 0xfff0ff00,
22757 +      &avr32_syntax_table[AVR32_SYNTAX_MOVEQ2],
22758 +      BFD_RELOC_AVR32_8S_EXT, 2, 1,
22759 +      {
22760 +       &avr32_ifield_table[AVR32_IFIELD_RY],
22761 +       &avr32_ifield_table[AVR32_IFIELD_K8E],
22762 +      },
22763 +    },
22764 +    {
22765 +      AVR32_OPC_MOVNE2, 4, 0xf9b00100, 0xfff0ff00,
22766 +      &avr32_syntax_table[AVR32_SYNTAX_MOVNE2],
22767 +      BFD_RELOC_AVR32_8S_EXT, 2, 1,
22768 +      {
22769 +       &avr32_ifield_table[AVR32_IFIELD_RY],
22770 +       &avr32_ifield_table[AVR32_IFIELD_K8E],
22771 +      },
22772 +    },
22773 +    {
22774 +      AVR32_OPC_MOVCC2, 4, 0xf9b00200, 0xfff0ff00,
22775 +      &avr32_syntax_table[AVR32_SYNTAX_MOVHS2],
22776 +      BFD_RELOC_AVR32_8S_EXT, 2, 1,
22777 +      {
22778 +       &avr32_ifield_table[AVR32_IFIELD_RY],
22779 +       &avr32_ifield_table[AVR32_IFIELD_K8E],
22780 +      },
22781 +    },
22782 +    {
22783 +      AVR32_OPC_MOVCS2, 4, 0xf9b00300, 0xfff0ff00,
22784 +      &avr32_syntax_table[AVR32_SYNTAX_MOVLO2],
22785 +      BFD_RELOC_AVR32_8S_EXT, 2, 1,
22786 +      {
22787 +       &avr32_ifield_table[AVR32_IFIELD_RY],
22788 +       &avr32_ifield_table[AVR32_IFIELD_K8E],
22789 +      },
22790 +    },
22791 +    {
22792 +      AVR32_OPC_MOVGE2, 4, 0xf9b00400, 0xfff0ff00,
22793 +      &avr32_syntax_table[AVR32_SYNTAX_MOVGE2],
22794 +      BFD_RELOC_AVR32_8S_EXT, 2, 1,
22795 +      {
22796 +       &avr32_ifield_table[AVR32_IFIELD_RY],
22797 +       &avr32_ifield_table[AVR32_IFIELD_K8E],
22798 +      },
22799 +    },
22800 +    {
22801 +      AVR32_OPC_MOVLT2, 4, 0xf9b00500, 0xfff0ff00,
22802 +      &avr32_syntax_table[AVR32_SYNTAX_MOVLT2],
22803 +      BFD_RELOC_AVR32_8S_EXT, 2, 1,
22804 +      {
22805 +       &avr32_ifield_table[AVR32_IFIELD_RY],
22806 +       &avr32_ifield_table[AVR32_IFIELD_K8E],
22807 +      },
22808 +    },
22809 +    {
22810 +      AVR32_OPC_MOVMI2, 4, 0xf9b00600, 0xfff0ff00,
22811 +      &avr32_syntax_table[AVR32_SYNTAX_MOVMI2],
22812 +      BFD_RELOC_AVR32_8S_EXT, 2, 1,
22813 +      {
22814 +       &avr32_ifield_table[AVR32_IFIELD_RY],
22815 +       &avr32_ifield_table[AVR32_IFIELD_K8E],
22816 +      },
22817 +    },
22818 +    {
22819 +      AVR32_OPC_MOVPL2, 4, 0xf9b00700, 0xfff0ff00,
22820 +      &avr32_syntax_table[AVR32_SYNTAX_MOVPL2],
22821 +      BFD_RELOC_AVR32_8S_EXT, 2, 1,
22822 +      {
22823 +       &avr32_ifield_table[AVR32_IFIELD_RY],
22824 +       &avr32_ifield_table[AVR32_IFIELD_K8E],
22825 +      },
22826 +    },
22827 +    {
22828 +      AVR32_OPC_MOVLS2, 4, 0xf9b00800, 0xfff0ff00,
22829 +      &avr32_syntax_table[AVR32_SYNTAX_MOVLS2],
22830 +      BFD_RELOC_AVR32_8S_EXT, 2, 1,
22831 +      {
22832 +       &avr32_ifield_table[AVR32_IFIELD_RY],
22833 +       &avr32_ifield_table[AVR32_IFIELD_K8E],
22834 +      },
22835 +    },
22836 +    {
22837 +      AVR32_OPC_MOVGT2, 4, 0xf9b00900, 0xfff0ff00,
22838 +      &avr32_syntax_table[AVR32_SYNTAX_MOVGT2],
22839 +      BFD_RELOC_AVR32_8S_EXT, 2, 1,
22840 +      {
22841 +       &avr32_ifield_table[AVR32_IFIELD_RY],
22842 +       &avr32_ifield_table[AVR32_IFIELD_K8E],
22843 +      },
22844 +    },
22845 +    {
22846 +      AVR32_OPC_MOVLE2, 4, 0xf9b00a00, 0xfff0ff00,
22847 +      &avr32_syntax_table[AVR32_SYNTAX_MOVLE2],
22848 +      BFD_RELOC_AVR32_8S_EXT, 2, 1,
22849 +      {
22850 +       &avr32_ifield_table[AVR32_IFIELD_RY],
22851 +       &avr32_ifield_table[AVR32_IFIELD_K8E],
22852 +      },
22853 +    },
22854 +    {
22855 +      AVR32_OPC_MOVHI2, 4, 0xf9b00b00, 0xfff0ff00,
22856 +      &avr32_syntax_table[AVR32_SYNTAX_MOVHI2],
22857 +      BFD_RELOC_AVR32_8S_EXT, 2, 1,
22858 +      {
22859 +       &avr32_ifield_table[AVR32_IFIELD_RY],
22860 +       &avr32_ifield_table[AVR32_IFIELD_K8E],
22861 +      },
22862 +    },
22863 +    {
22864 +      AVR32_OPC_MOVVS2, 4, 0xf9b00c00, 0xfff0ff00,
22865 +      &avr32_syntax_table[AVR32_SYNTAX_MOVVS2],
22866 +      BFD_RELOC_AVR32_8S_EXT, 2, 1,
22867 +      {
22868 +       &avr32_ifield_table[AVR32_IFIELD_RY],
22869 +       &avr32_ifield_table[AVR32_IFIELD_K8E],
22870 +      },
22871 +    },
22872 +    {
22873 +      AVR32_OPC_MOVVC2, 4, 0xf9b00d00, 0xfff0ff00,
22874 +      &avr32_syntax_table[AVR32_SYNTAX_MOVVC2],
22875 +      BFD_RELOC_AVR32_8S_EXT, 2, 1,
22876 +      {
22877 +       &avr32_ifield_table[AVR32_IFIELD_RY],
22878 +       &avr32_ifield_table[AVR32_IFIELD_K8E],
22879 +      },
22880 +    },
22881 +    {
22882 +      AVR32_OPC_MOVQS2, 4, 0xf9b00e00, 0xfff0ff00,
22883 +      &avr32_syntax_table[AVR32_SYNTAX_MOVQS2],
22884 +      BFD_RELOC_AVR32_8S_EXT, 2, 1,
22885 +      {
22886 +       &avr32_ifield_table[AVR32_IFIELD_RY],
22887 +       &avr32_ifield_table[AVR32_IFIELD_K8E],
22888 +      },
22889 +    },
22890 +    {
22891 +      AVR32_OPC_MOVAL2, 4, 0xf9b00f00, 0xfff0ff00,
22892 +      &avr32_syntax_table[AVR32_SYNTAX_MOVAL2],
22893 +      BFD_RELOC_AVR32_8S_EXT, 2, 1,
22894 +      {
22895 +       &avr32_ifield_table[AVR32_IFIELD_RY],
22896 +       &avr32_ifield_table[AVR32_IFIELD_K8E],
22897 +      },
22898 +    },
22899 +    {
22900 +      AVR32_OPC_MTDR, 4, 0xe7b00000, 0xfff0ff00,
22901 +      &avr32_syntax_table[AVR32_SYNTAX_MTDR],
22902 +      BFD_RELOC_AVR32_8S_EXT, 2, 0,
22903 +      {
22904 +       &avr32_ifield_table[AVR32_IFIELD_K8E],
22905 +       &avr32_ifield_table[AVR32_IFIELD_RY],
22906 +      },
22907 +    },
22908 +    {
22909 +      AVR32_OPC_MTSR, 4, 0xe3b00000, 0xfff0ff00,
22910 +      &avr32_syntax_table[AVR32_SYNTAX_MTSR],
22911 +      BFD_RELOC_AVR32_8S_EXT, 2, 0,
22912 +      {
22913 +       &avr32_ifield_table[AVR32_IFIELD_K8E],
22914 +       &avr32_ifield_table[AVR32_IFIELD_RY],
22915 +      },
22916 +    },
22917 +    {
22918 +      AVR32_OPC_MUL1, 2, 0xa1300000, 0xe1f00000,
22919 +      &avr32_syntax_table[AVR32_SYNTAX_MUL1],
22920 +      BFD_RELOC_UNUSED, 2, -1,
22921 +      {
22922 +       &avr32_ifield_table[AVR32_IFIELD_RY],
22923 +       &avr32_ifield_table[AVR32_IFIELD_RX],
22924 +      },
22925 +    },
22926 +    {
22927 +      AVR32_OPC_MUL2, 4, 0xe0000240, 0xe1f0fff0,
22928 +      &avr32_syntax_table[AVR32_SYNTAX_MUL2],
22929 +      BFD_RELOC_UNUSED, 3, -1,
22930 +      {
22931 +       &avr32_ifield_table[AVR32_IFIELD_RD_E],
22932 +       &avr32_ifield_table[AVR32_IFIELD_RX],
22933 +       &avr32_ifield_table[AVR32_IFIELD_RY],
22934 +      },
22935 +    },
22936 +    {
22937 +      AVR32_OPC_MUL3, 4, 0xe0001000, 0xe1f0ff00,
22938 +      &avr32_syntax_table[AVR32_SYNTAX_MUL3],
22939 +      BFD_RELOC_AVR32_8S_EXT, 3, 2,
22940 +      {
22941 +       &avr32_ifield_table[AVR32_IFIELD_RY],
22942 +       &avr32_ifield_table[AVR32_IFIELD_RX],
22943 +       &avr32_ifield_table[AVR32_IFIELD_K8E],
22944 +      },
22945 +    },
22946 +    {
22947 +      AVR32_OPC_MULHH_W, 4, 0xe0000780, 0xe1f0ffc0,
22948 +      &avr32_syntax_table[AVR32_SYNTAX_MULHH_W],
22949 +      BFD_RELOC_UNUSED, 5, -1,
22950 +      {
22951 +       &avr32_ifield_table[AVR32_IFIELD_RD_E],
22952 +       &avr32_ifield_table[AVR32_IFIELD_RX],
22953 +       &avr32_ifield_table[AVR32_IFIELD_X],
22954 +       &avr32_ifield_table[AVR32_IFIELD_RY],
22955 +       &avr32_ifield_table[AVR32_IFIELD_Y],
22956 +      },
22957 +    },
22958 +    {
22959 +      AVR32_OPC_MULNHH_W, 4, 0xe0000180, 0xe1f0ffc0,
22960 +      &avr32_syntax_table[AVR32_SYNTAX_MULNHH_W],
22961 +      BFD_RELOC_UNUSED, 5, -1,
22962 +      {
22963 +       &avr32_ifield_table[AVR32_IFIELD_RD_E],
22964 +       &avr32_ifield_table[AVR32_IFIELD_RX],
22965 +       &avr32_ifield_table[AVR32_IFIELD_X],
22966 +       &avr32_ifield_table[AVR32_IFIELD_RY],
22967 +       &avr32_ifield_table[AVR32_IFIELD_Y],
22968 +      },
22969 +    },
22970 +    {
22971 +      AVR32_OPC_MULNWH_D, 4, 0xe0000280, 0xe1f0ffe1,
22972 +      &avr32_syntax_table[AVR32_SYNTAX_MULNWH_D],
22973 +      BFD_RELOC_UNUSED, 4, -1,
22974 +      {
22975 +       &avr32_ifield_table[AVR32_IFIELD_RD_E],
22976 +       &avr32_ifield_table[AVR32_IFIELD_RX],
22977 +       &avr32_ifield_table[AVR32_IFIELD_RY],
22978 +       &avr32_ifield_table[AVR32_IFIELD_Y],
22979 +      },
22980 +    },
22981 +    {
22982 +      AVR32_OPC_MULSD, 4, 0xe0000440, 0xe1f0fff0,
22983 +      &avr32_syntax_table[AVR32_SYNTAX_MULSD],
22984 +      BFD_RELOC_UNUSED, 3, -1,
22985 +      {
22986 +       &avr32_ifield_table[AVR32_IFIELD_RD_E],
22987 +       &avr32_ifield_table[AVR32_IFIELD_RX],
22988 +       &avr32_ifield_table[AVR32_IFIELD_RY],
22989 +      },
22990 +    },
22991 +    {
22992 +      AVR32_OPC_MULSATHH_H, 4, 0xe0000880, 0xe1f0ffc0,
22993 +      &avr32_syntax_table[AVR32_SYNTAX_MULSATHH_H],
22994 +      BFD_RELOC_UNUSED, 5, -1,
22995 +      {
22996 +       &avr32_ifield_table[AVR32_IFIELD_RD_E],
22997 +       &avr32_ifield_table[AVR32_IFIELD_RX],
22998 +       &avr32_ifield_table[AVR32_IFIELD_X],
22999 +       &avr32_ifield_table[AVR32_IFIELD_RY],
23000 +       &avr32_ifield_table[AVR32_IFIELD_Y],
23001 +      },
23002 +    },
23003 +    {
23004 +      AVR32_OPC_MULSATHH_W, 4, 0xe0000980, 0xe1f0ffc0,
23005 +      &avr32_syntax_table[AVR32_SYNTAX_MULSATHH_W],
23006 +      BFD_RELOC_UNUSED, 5, -1,
23007 +      {
23008 +       &avr32_ifield_table[AVR32_IFIELD_RD_E],
23009 +       &avr32_ifield_table[AVR32_IFIELD_RX],
23010 +       &avr32_ifield_table[AVR32_IFIELD_X],
23011 +       &avr32_ifield_table[AVR32_IFIELD_RY],
23012 +       &avr32_ifield_table[AVR32_IFIELD_Y],
23013 +      },
23014 +    },
23015 +    {
23016 +      AVR32_OPC_MULSATRNDHH_H, 4, 0xe0000a80, 0xe1f0ffc0,
23017 +      &avr32_syntax_table[AVR32_SYNTAX_MULSATRNDHH_H],
23018 +      BFD_RELOC_UNUSED, 5, -1,
23019 +      {
23020 +       &avr32_ifield_table[AVR32_IFIELD_RD_E],
23021 +       &avr32_ifield_table[AVR32_IFIELD_RX],
23022 +       &avr32_ifield_table[AVR32_IFIELD_X],
23023 +       &avr32_ifield_table[AVR32_IFIELD_RY],
23024 +       &avr32_ifield_table[AVR32_IFIELD_Y],
23025 +      },
23026 +    },
23027 +    {
23028 +      AVR32_OPC_MULSATRNDWH_W, 4, 0xe0000b80, 0xe1f0ffe0,
23029 +      &avr32_syntax_table[AVR32_SYNTAX_MULSATRNDWH_W],
23030 +      BFD_RELOC_UNUSED, 4, -1,
23031 +      {
23032 +       &avr32_ifield_table[AVR32_IFIELD_RD_E],
23033 +       &avr32_ifield_table[AVR32_IFIELD_RX],
23034 +       &avr32_ifield_table[AVR32_IFIELD_RY],
23035 +       &avr32_ifield_table[AVR32_IFIELD_Y],
23036 +      },
23037 +    },
23038 +    {
23039 +      AVR32_OPC_MULSATWH_W, 4, 0xe0000e80, 0xe1f0ffe0,
23040 +      &avr32_syntax_table[AVR32_SYNTAX_MULSATWH_W],
23041 +      BFD_RELOC_UNUSED, 4, -1,
23042 +      {
23043 +       &avr32_ifield_table[AVR32_IFIELD_RD_E],
23044 +       &avr32_ifield_table[AVR32_IFIELD_RX],
23045 +       &avr32_ifield_table[AVR32_IFIELD_RY],
23046 +       &avr32_ifield_table[AVR32_IFIELD_Y],
23047 +      },
23048 +    },
23049 +    {
23050 +      AVR32_OPC_MULU_D, 4, 0xe0000640, 0xe1f0fff1,
23051 +      &avr32_syntax_table[AVR32_SYNTAX_MULU_D],
23052 +      BFD_RELOC_UNUSED, 3, -1,
23053 +      {
23054 +       &avr32_ifield_table[AVR32_IFIELD_RD_E],
23055 +       &avr32_ifield_table[AVR32_IFIELD_RX],
23056 +       &avr32_ifield_table[AVR32_IFIELD_RY],
23057 +      },
23058 +    },
23059 +    {
23060 +      AVR32_OPC_MULWH_D, 4, 0xe0000d80, 0xe1f0ffe1,
23061 +      &avr32_syntax_table[AVR32_SYNTAX_MULWH_D],
23062 +      BFD_RELOC_UNUSED, 4, -1,
23063 +      {
23064 +       &avr32_ifield_table[AVR32_IFIELD_RD_E],
23065 +       &avr32_ifield_table[AVR32_IFIELD_RX],
23066 +       &avr32_ifield_table[AVR32_IFIELD_RY],
23067 +       &avr32_ifield_table[AVR32_IFIELD_Y],
23068 +      },
23069 +    },
23070 +    {
23071 +      AVR32_OPC_MUSFR, 2, 0x5d300000, 0xfff00000,
23072 +      &avr32_syntax_table[AVR32_SYNTAX_MUSFR],
23073 +      BFD_RELOC_UNUSED, 1, -1,
23074 +      {
23075 +       &avr32_ifield_table[AVR32_IFIELD_RY],
23076 +      }
23077 +    },
23078 +    {
23079 +      AVR32_OPC_MUSTR, 2, 0x5d200000, 0xfff00000,
23080 +      &avr32_syntax_table[AVR32_SYNTAX_MUSTR],
23081 +      BFD_RELOC_UNUSED, 1, -1,
23082 +      {
23083 +       &avr32_ifield_table[AVR32_IFIELD_RY],
23084 +      }
23085 +    },
23086 +    {
23087 +      AVR32_OPC_MVCR_D, 4, 0xefa00010, 0xfff111ff,
23088 +      &avr32_syntax_table[AVR32_SYNTAX_MVCR_D],
23089 +      BFD_RELOC_UNUSED, 3, -1,
23090 +      {
23091 +       &avr32_ifield_table[AVR32_IFIELD_CPNO],
23092 +       &avr32_ifield_table[AVR32_IFIELD_RY_DW],
23093 +       &avr32_ifield_table[AVR32_IFIELD_CRD_DW],
23094 +      },
23095 +    },
23096 +    {
23097 +      AVR32_OPC_MVCR_W, 4, 0xefa00000, 0xfff010ff,
23098 +      &avr32_syntax_table[AVR32_SYNTAX_MVCR_W],
23099 +      BFD_RELOC_UNUSED, 3, -1,
23100 +      {
23101 +       &avr32_ifield_table[AVR32_IFIELD_CPNO],
23102 +       &avr32_ifield_table[AVR32_IFIELD_RY],
23103 +       &avr32_ifield_table[AVR32_IFIELD_CRD_RI],
23104 +      },
23105 +    },
23106 +    {
23107 +      AVR32_OPC_MVRC_D, 4, 0xefa00030, 0xfff111ff,
23108 +      &avr32_syntax_table[AVR32_SYNTAX_MVRC_D],
23109 +      BFD_RELOC_UNUSED, 3, -1,
23110 +      {
23111 +       &avr32_ifield_table[AVR32_IFIELD_CPNO],
23112 +       &avr32_ifield_table[AVR32_IFIELD_CRD_DW],
23113 +       &avr32_ifield_table[AVR32_IFIELD_RY_DW],
23114 +      },
23115 +    },
23116 +    {
23117 +      AVR32_OPC_MVRC_W, 4, 0xefa00020, 0xfff010ff,
23118 +      &avr32_syntax_table[AVR32_SYNTAX_MVRC_W],
23119 +      BFD_RELOC_UNUSED, 3, -1,
23120 +      {
23121 +       &avr32_ifield_table[AVR32_IFIELD_CPNO],
23122 +       &avr32_ifield_table[AVR32_IFIELD_CRD_RI],
23123 +       &avr32_ifield_table[AVR32_IFIELD_RY],
23124 +      },
23125 +    },
23126 +    {
23127 +      AVR32_OPC_NEG, 2, 0x5c300000, 0xfff00000,
23128 +      &avr32_syntax_table[AVR32_SYNTAX_NEG],
23129 +      BFD_RELOC_UNUSED, 1, -1,
23130 +      {
23131 +       &avr32_ifield_table[AVR32_IFIELD_RY],
23132 +      }
23133 +    },
23134 +    {
23135 +      AVR32_OPC_NOP, 2, 0xd7030000, 0xffff0000,
23136 +      &avr32_syntax_table[AVR32_SYNTAX_NOP],
23137 +      BFD_RELOC_UNUSED, 0, -1, { NULL },
23138 +    },
23139 +    {
23140 +      AVR32_OPC_OR1, 2, 0x00400000, 0xe1f00000,
23141 +      &avr32_syntax_table[AVR32_SYNTAX_OR1],
23142 +      BFD_RELOC_UNUSED, 2, -1,
23143 +      {
23144 +       &avr32_ifield_table[AVR32_IFIELD_RY],
23145 +       &avr32_ifield_table[AVR32_IFIELD_RX],
23146 +      },
23147 +    },
23148 +    {
23149 +      AVR32_OPC_OR2, 4, 0xe1e01000, 0xe1f0fe00,
23150 +      &avr32_syntax_table[AVR32_SYNTAX_OR2],
23151 +      BFD_RELOC_UNUSED, 4, -1,
23152 +      {
23153 +       &avr32_ifield_table[AVR32_IFIELD_RD_E],
23154 +       &avr32_ifield_table[AVR32_IFIELD_RX],
23155 +       &avr32_ifield_table[AVR32_IFIELD_RY],
23156 +       &avr32_ifield_table[AVR32_IFIELD_K5E2],
23157 +      },
23158 +    },
23159 +    {
23160 +      AVR32_OPC_OR3, 4, 0xe1e01200, 0xe1f0fe00,
23161 +      &avr32_syntax_table[AVR32_SYNTAX_OR3],
23162 +      BFD_RELOC_UNUSED, 4, -1,
23163 +      {
23164 +       &avr32_ifield_table[AVR32_IFIELD_RD_E],
23165 +       &avr32_ifield_table[AVR32_IFIELD_RX],
23166 +       &avr32_ifield_table[AVR32_IFIELD_RY],
23167 +       &avr32_ifield_table[AVR32_IFIELD_K5E2],
23168 +      },
23169 +    },
23170 +    {
23171 +      AVR32_OPC_ORH, 4, 0xea100000, 0xfff00000,
23172 +      &avr32_syntax_table[AVR32_SYNTAX_ORH],
23173 +      BFD_RELOC_AVR32_16U, 2, 1,
23174 +      {
23175 +       &avr32_ifield_table[AVR32_IFIELD_RY],
23176 +       &avr32_ifield_table[AVR32_IFIELD_K16],
23177 +      },
23178 +    },
23179 +    {
23180 +      AVR32_OPC_ORL, 4, 0xe8100000, 0xfff00000,
23181 +      &avr32_syntax_table[AVR32_SYNTAX_ORL],
23182 +      BFD_RELOC_AVR32_16U, 2, 1,
23183 +      {
23184 +       &avr32_ifield_table[AVR32_IFIELD_RY],
23185 +       &avr32_ifield_table[AVR32_IFIELD_K16],
23186 +      },
23187 +    },
23188 +    {
23189 +      AVR32_OPC_PABS_SB, 4, 0xe00023e0, 0xfff0fff0,
23190 +      &avr32_syntax_table[AVR32_SYNTAX_PABS_SB],
23191 +      BFD_RELOC_UNUSED, 2, -1,
23192 +      {
23193 +       &avr32_ifield_table[AVR32_IFIELD_RD_E],
23194 +       &avr32_ifield_table[AVR32_IFIELD_RY],
23195 +      },
23196 +    },
23197 +    {
23198 +      AVR32_OPC_PABS_SH, 4, 0xe00023f0, 0xfff0fff0,
23199 +      &avr32_syntax_table[AVR32_SYNTAX_PABS_SH],
23200 +      BFD_RELOC_UNUSED, 2, -1,
23201 +      {
23202 +       &avr32_ifield_table[AVR32_IFIELD_RD_E],
23203 +       &avr32_ifield_table[AVR32_IFIELD_RY],
23204 +      },
23205 +    },
23206 +    {
23207 +      AVR32_OPC_PACKSH_SB, 4, 0xe00024d0, 0xe1f0fff0,
23208 +      &avr32_syntax_table[AVR32_SYNTAX_PACKSH_SB],
23209 +      BFD_RELOC_UNUSED, 3, -1,
23210 +      {
23211 +       &avr32_ifield_table[AVR32_IFIELD_RD_E],
23212 +       &avr32_ifield_table[AVR32_IFIELD_RX],
23213 +       &avr32_ifield_table[AVR32_IFIELD_RY],
23214 +      },
23215 +    },
23216 +    {
23217 +      AVR32_OPC_PACKSH_UB, 4, 0xe00024c0, 0xe1f0fff0,
23218 +      &avr32_syntax_table[AVR32_SYNTAX_PACKSH_UB],
23219 +      BFD_RELOC_UNUSED, 3, -1,
23220 +      {
23221 +       &avr32_ifield_table[AVR32_IFIELD_RD_E],
23222 +       &avr32_ifield_table[AVR32_IFIELD_RX],
23223 +       &avr32_ifield_table[AVR32_IFIELD_RY],
23224 +      },
23225 +    },
23226 +    {
23227 +      AVR32_OPC_PACKW_SH, 4, 0xe0002470, 0xe1f0fff0,
23228 +      &avr32_syntax_table[AVR32_SYNTAX_PACKW_SH],
23229 +      BFD_RELOC_UNUSED, 3, -1,
23230 +      {
23231 +       &avr32_ifield_table[AVR32_IFIELD_RD_E],
23232 +       &avr32_ifield_table[AVR32_IFIELD_RX],
23233 +       &avr32_ifield_table[AVR32_IFIELD_RY],
23234 +      },
23235 +    },
23236 +    {
23237 +      AVR32_OPC_PADD_B, 4, 0xe0002300, 0xe1f0fff0,
23238 +      &avr32_syntax_table[AVR32_SYNTAX_PADD_B],
23239 +      BFD_RELOC_UNUSED, 3, -1,
23240 +      {
23241 +       &avr32_ifield_table[AVR32_IFIELD_RD_E],
23242 +       &avr32_ifield_table[AVR32_IFIELD_RX],
23243 +       &avr32_ifield_table[AVR32_IFIELD_RY],
23244 +      },
23245 +    },
23246 +    {
23247 +      AVR32_OPC_PADD_H, 4, 0xe0002000, 0xe1f0fff0,
23248 +      &avr32_syntax_table[AVR32_SYNTAX_PADD_H],
23249 +      BFD_RELOC_UNUSED, 3, -1,
23250 +      {
23251 +       &avr32_ifield_table[AVR32_IFIELD_RD_E],
23252 +       &avr32_ifield_table[AVR32_IFIELD_RX],
23253 +       &avr32_ifield_table[AVR32_IFIELD_RY],
23254 +      },
23255 +    },
23256 +    {
23257 +      AVR32_OPC_PADDH_SH, 4, 0xe00020c0, 0xe1f0fff0,
23258 +      &avr32_syntax_table[AVR32_SYNTAX_PADDH_SH],
23259 +      BFD_RELOC_UNUSED, 3, -1,
23260 +      {
23261 +       &avr32_ifield_table[AVR32_IFIELD_RD_E],
23262 +       &avr32_ifield_table[AVR32_IFIELD_RX],
23263 +       &avr32_ifield_table[AVR32_IFIELD_RY],
23264 +      },
23265 +    },
23266 +    {
23267 +      AVR32_OPC_PADDH_UB, 4, 0xe0002360, 0xe1f0fff0,
23268 +      &avr32_syntax_table[AVR32_SYNTAX_PADDH_UB],
23269 +      BFD_RELOC_UNUSED, 3, -1,
23270 +      {
23271 +       &avr32_ifield_table[AVR32_IFIELD_RD_E],
23272 +       &avr32_ifield_table[AVR32_IFIELD_RX],
23273 +       &avr32_ifield_table[AVR32_IFIELD_RY],
23274 +      },
23275 +    },
23276 +    {
23277 +      AVR32_OPC_PADDS_SB, 4, 0xe0002320, 0xe1f0fff0,
23278 +      &avr32_syntax_table[AVR32_SYNTAX_PADDS_SB],
23279 +      BFD_RELOC_UNUSED, 3, -1,
23280 +      {
23281 +       &avr32_ifield_table[AVR32_IFIELD_RD_E],
23282 +       &avr32_ifield_table[AVR32_IFIELD_RX],
23283 +       &avr32_ifield_table[AVR32_IFIELD_RY],
23284 +      },
23285 +    },
23286 +    {
23287 +      AVR32_OPC_PADDS_SH, 4, 0xe0002040, 0xe1f0fff0,
23288 +      &avr32_syntax_table[AVR32_SYNTAX_PADDS_SH],
23289 +      BFD_RELOC_UNUSED, 3, -1,
23290 +      {
23291 +       &avr32_ifield_table[AVR32_IFIELD_RD_E],
23292 +       &avr32_ifield_table[AVR32_IFIELD_RX],
23293 +       &avr32_ifield_table[AVR32_IFIELD_RY],
23294 +      },
23295 +    },
23296 +    {
23297 +      AVR32_OPC_PADDS_UB, 4, 0xe0002340, 0xe1f0fff0,
23298 +      &avr32_syntax_table[AVR32_SYNTAX_PADDS_UB],
23299 +      BFD_RELOC_UNUSED, 3, -1,
23300 +      {
23301 +       &avr32_ifield_table[AVR32_IFIELD_RD_E],
23302 +       &avr32_ifield_table[AVR32_IFIELD_RX],
23303 +       &avr32_ifield_table[AVR32_IFIELD_RY],
23304 +      },
23305 +    },
23306 +    {
23307 +      AVR32_OPC_PADDS_UH, 4, 0xe0002080, 0xe1f0fff0,
23308 +      &avr32_syntax_table[AVR32_SYNTAX_PADDS_UH],
23309 +      BFD_RELOC_UNUSED, 3, -1,
23310 +      {
23311 +       &avr32_ifield_table[AVR32_IFIELD_RD_E],
23312 +       &avr32_ifield_table[AVR32_IFIELD_RX],
23313 +       &avr32_ifield_table[AVR32_IFIELD_RY],
23314 +      },
23315 +    },
23316 +    {
23317 +      AVR32_OPC_PADDSUB_H, 4, 0xe0002100, 0xe1f0ffc0,
23318 +      &avr32_syntax_table[AVR32_SYNTAX_PADDSUB_H],
23319 +      BFD_RELOC_UNUSED, 5, -1,
23320 +      {
23321 +       &avr32_ifield_table[AVR32_IFIELD_RD_E],
23322 +       &avr32_ifield_table[AVR32_IFIELD_RX],
23323 +       &avr32_ifield_table[AVR32_IFIELD_X],
23324 +       &avr32_ifield_table[AVR32_IFIELD_RY],
23325 +       &avr32_ifield_table[AVR32_IFIELD_Y],
23326 +      },
23327 +    },
23328 +    {
23329 +      AVR32_OPC_PADDSUBH_SH, 4, 0xe0002280, 0xe1f0ffc0,
23330 +      &avr32_syntax_table[AVR32_SYNTAX_PADDSUBH_SH],
23331 +      BFD_RELOC_UNUSED, 5, -1,
23332 +      {
23333 +       &avr32_ifield_table[AVR32_IFIELD_RD_E],
23334 +       &avr32_ifield_table[AVR32_IFIELD_RX],
23335 +       &avr32_ifield_table[AVR32_IFIELD_X],
23336 +       &avr32_ifield_table[AVR32_IFIELD_RY],
23337 +       &avr32_ifield_table[AVR32_IFIELD_Y],
23338 +      },
23339 +    },
23340 +    {
23341 +      AVR32_OPC_PADDSUBS_SH, 4, 0xe0002180, 0xe1f0ffc0,
23342 +      &avr32_syntax_table[AVR32_SYNTAX_PADDSUBS_SH],
23343 +      BFD_RELOC_UNUSED, 5, -1,
23344 +      {
23345 +       &avr32_ifield_table[AVR32_IFIELD_RD_E],
23346 +       &avr32_ifield_table[AVR32_IFIELD_RX],
23347 +       &avr32_ifield_table[AVR32_IFIELD_X],
23348 +       &avr32_ifield_table[AVR32_IFIELD_RY],
23349 +       &avr32_ifield_table[AVR32_IFIELD_Y],
23350 +      },
23351 +    },
23352 +    {
23353 +      AVR32_OPC_PADDSUBS_UH, 4, 0xe0002200, 0xe1f0ffc0,
23354 +      &avr32_syntax_table[AVR32_SYNTAX_PADDSUBS_UH],
23355 +      BFD_RELOC_UNUSED, 5, -1,
23356 +      {
23357 +       &avr32_ifield_table[AVR32_IFIELD_RD_E],
23358 +       &avr32_ifield_table[AVR32_IFIELD_RX],
23359 +       &avr32_ifield_table[AVR32_IFIELD_X],
23360 +       &avr32_ifield_table[AVR32_IFIELD_RY],
23361 +       &avr32_ifield_table[AVR32_IFIELD_Y],
23362 +      },
23363 +    },
23364 +    {
23365 +      AVR32_OPC_PADDX_H, 4, 0xe0002020, 0xe1f0fff0,
23366 +      &avr32_syntax_table[AVR32_SYNTAX_PADDX_H],
23367 +      BFD_RELOC_UNUSED, 3, -1,
23368 +      {
23369 +       &avr32_ifield_table[AVR32_IFIELD_RD_E],
23370 +       &avr32_ifield_table[AVR32_IFIELD_RX],
23371 +       &avr32_ifield_table[AVR32_IFIELD_RY],
23372 +      },
23373 +    },
23374 +    {
23375 +      AVR32_OPC_PADDXH_SH, 4, 0xe00020e0, 0xe1f0fff0,
23376 +      &avr32_syntax_table[AVR32_SYNTAX_PADDXH_SH],
23377 +      BFD_RELOC_UNUSED, 3, -1,
23378 +      {
23379 +       &avr32_ifield_table[AVR32_IFIELD_RD_E],
23380 +       &avr32_ifield_table[AVR32_IFIELD_RX],
23381 +       &avr32_ifield_table[AVR32_IFIELD_RY],
23382 +      },
23383 +    },
23384 +    {
23385 +      AVR32_OPC_PADDXS_SH, 4, 0xe0002060, 0xe1f0fff0,
23386 +      &avr32_syntax_table[AVR32_SYNTAX_PADDXS_SH],
23387 +      BFD_RELOC_UNUSED, 3, -1,
23388 +      {
23389 +       &avr32_ifield_table[AVR32_IFIELD_RD_E],
23390 +       &avr32_ifield_table[AVR32_IFIELD_RX],
23391 +       &avr32_ifield_table[AVR32_IFIELD_RY],
23392 +      },
23393 +    },
23394 +    {
23395 +      AVR32_OPC_PADDXS_UH, 4, 0xe00020a0, 0xe1f0fff0,
23396 +      &avr32_syntax_table[AVR32_SYNTAX_PADDXS_UH],
23397 +      BFD_RELOC_UNUSED, 3, -1,
23398 +      {
23399 +       &avr32_ifield_table[AVR32_IFIELD_RD_E],
23400 +       &avr32_ifield_table[AVR32_IFIELD_RX],
23401 +       &avr32_ifield_table[AVR32_IFIELD_RY],
23402 +      },
23403 +    },
23404 +    {
23405 +      AVR32_OPC_PASR_B, 4, 0xe0002410, 0xe1f8fff0,
23406 +      &avr32_syntax_table[AVR32_SYNTAX_PASR_B],
23407 +      BFD_RELOC_UNUSED, 3, -1,
23408 +      {
23409 +       &avr32_ifield_table[AVR32_IFIELD_RD_E],
23410 +       &avr32_ifield_table[AVR32_IFIELD_RX],
23411 +       &avr32_ifield_table[AVR32_IFIELD_COND3],
23412 +      },
23413 +    },
23414 +    {
23415 +      AVR32_OPC_PASR_H, 4, 0xe0002440, 0xe1f0fff0,
23416 +      &avr32_syntax_table[AVR32_SYNTAX_PASR_H],
23417 +      BFD_RELOC_UNUSED, 3, -1,
23418 +      {
23419 +       &avr32_ifield_table[AVR32_IFIELD_RD_E],
23420 +       &avr32_ifield_table[AVR32_IFIELD_RX],
23421 +       &avr32_ifield_table[AVR32_IFIELD_RY],
23422 +      },
23423 +    },
23424 +    {
23425 +      AVR32_OPC_PAVG_SH, 4, 0xe00023d0, 0xe1f0fff0,
23426 +      &avr32_syntax_table[AVR32_SYNTAX_PAVG_SH],
23427 +      BFD_RELOC_UNUSED, 3, -1,
23428 +      {
23429 +       &avr32_ifield_table[AVR32_IFIELD_RD_E],
23430 +       &avr32_ifield_table[AVR32_IFIELD_RX],
23431 +       &avr32_ifield_table[AVR32_IFIELD_RY],
23432 +      },
23433 +    },
23434 +    {
23435 +      AVR32_OPC_PAVG_UB, 4, 0xe00023c0, 0xe1f0fff0,
23436 +      &avr32_syntax_table[AVR32_SYNTAX_PAVG_UB],
23437 +      BFD_RELOC_UNUSED, 3, -1,
23438 +      {
23439 +       &avr32_ifield_table[AVR32_IFIELD_RD_E],
23440 +       &avr32_ifield_table[AVR32_IFIELD_RX],
23441 +       &avr32_ifield_table[AVR32_IFIELD_RY],
23442 +      },
23443 +    },
23444 +    {
23445 +      AVR32_OPC_PLSL_B, 4, 0xe0002420, 0xe1f8fff0,
23446 +      &avr32_syntax_table[AVR32_SYNTAX_PLSL_B],
23447 +      BFD_RELOC_UNUSED, 3, -1,
23448 +      {
23449 +       &avr32_ifield_table[AVR32_IFIELD_RD_E],
23450 +       &avr32_ifield_table[AVR32_IFIELD_RX],
23451 +       &avr32_ifield_table[AVR32_IFIELD_COND3],
23452 +      },
23453 +    },
23454 +    {
23455 +      AVR32_OPC_PLSL_H, 4, 0xe0002450, 0xe1f0fff0,
23456 +      &avr32_syntax_table[AVR32_SYNTAX_PLSL_H],
23457 +      BFD_RELOC_UNUSED, 3, -1,
23458 +      {
23459 +       &avr32_ifield_table[AVR32_IFIELD_RD_E],
23460 +       &avr32_ifield_table[AVR32_IFIELD_RX],
23461 +       &avr32_ifield_table[AVR32_IFIELD_RY],
23462 +      },
23463 +    },
23464 +    {
23465 +      AVR32_OPC_PLSR_B, 4, 0xe0002430, 0xe1f8fff0,
23466 +      &avr32_syntax_table[AVR32_SYNTAX_PLSR_B],
23467 +      BFD_RELOC_UNUSED, 3, -1,
23468 +      {
23469 +       &avr32_ifield_table[AVR32_IFIELD_RD_E],
23470 +       &avr32_ifield_table[AVR32_IFIELD_RX],
23471 +       &avr32_ifield_table[AVR32_IFIELD_COND3],
23472 +      },
23473 +    },
23474 +    {
23475 +      AVR32_OPC_PLSR_H, 4, 0xe0002460, 0xe1f0fff0,
23476 +      &avr32_syntax_table[AVR32_SYNTAX_PLSR_H],
23477 +      BFD_RELOC_UNUSED, 3, -1,
23478 +      {
23479 +       &avr32_ifield_table[AVR32_IFIELD_RD_E],
23480 +       &avr32_ifield_table[AVR32_IFIELD_RX],
23481 +       &avr32_ifield_table[AVR32_IFIELD_RY],
23482 +      },
23483 +    },
23484 +    {
23485 +      AVR32_OPC_PMAX_SH, 4, 0xe0002390, 0xe1f0fff0,
23486 +      &avr32_syntax_table[AVR32_SYNTAX_PMAX_SH],
23487 +      BFD_RELOC_UNUSED, 3, -1,
23488 +      {
23489 +       &avr32_ifield_table[AVR32_IFIELD_RD_E],
23490 +       &avr32_ifield_table[AVR32_IFIELD_RX],
23491 +       &avr32_ifield_table[AVR32_IFIELD_RY],
23492 +      },
23493 +    },
23494 +    {
23495 +      AVR32_OPC_PMAX_UB, 4, 0xe0002380, 0xe1f0fff0,
23496 +      &avr32_syntax_table[AVR32_SYNTAX_PMAX_UB],
23497 +      BFD_RELOC_UNUSED, 3, -1,
23498 +      {
23499 +       &avr32_ifield_table[AVR32_IFIELD_RD_E],
23500 +       &avr32_ifield_table[AVR32_IFIELD_RX],
23501 +       &avr32_ifield_table[AVR32_IFIELD_RY],
23502 +      },
23503 +    },
23504 +    {
23505 +      AVR32_OPC_PMIN_SH, 4, 0xe00023b0, 0xe1f0fff0,
23506 +      &avr32_syntax_table[AVR32_SYNTAX_PMIN_SH],
23507 +      BFD_RELOC_UNUSED, 3, -1,
23508 +      {
23509 +       &avr32_ifield_table[AVR32_IFIELD_RD_E],
23510 +       &avr32_ifield_table[AVR32_IFIELD_RX],
23511 +       &avr32_ifield_table[AVR32_IFIELD_RY],
23512 +      },
23513 +    },
23514 +    {
23515 +      AVR32_OPC_PMIN_UB, 4, 0xe00023a0, 0xe1f0fff0,
23516 +      &avr32_syntax_table[AVR32_SYNTAX_PMIN_UB],
23517 +      BFD_RELOC_UNUSED, 3, -1,
23518 +      {
23519 +       &avr32_ifield_table[AVR32_IFIELD_RD_E],
23520 +       &avr32_ifield_table[AVR32_IFIELD_RX],
23521 +       &avr32_ifield_table[AVR32_IFIELD_RY],
23522 +      },
23523 +    },
23524 +    {
23525 +      AVR32_OPC_POPJC, 2, 0xd7130000, 0xffff0000,
23526 +      &avr32_syntax_table[AVR32_SYNTAX_POPJC],
23527 +      BFD_RELOC_UNUSED, 0, -1, { NULL },
23528 +    },
23529 +    {
23530 +      AVR32_OPC_POPM, 2, 0xd0020000, 0xf0070000,
23531 +      &avr32_syntax_table[AVR32_SYNTAX_POPM],
23532 +      BFD_RELOC_UNUSED, 1, -1,
23533 +      {
23534 +       &avr32_ifield_table[AVR32_IFIELD_POPM],
23535 +      },
23536 +    },
23537 +    {
23538 +      AVR32_OPC_POPM_E, 4, 0xe3cd0000, 0xffff0000,
23539 +      &avr32_syntax_table[AVR32_SYNTAX_POPM_E],
23540 +      BFD_RELOC_UNUSED, 1, -1,
23541 +      {
23542 +       &avr32_ifield_table[AVR32_IFIELD_K16],
23543 +      },
23544 +    },
23545 +    {
23546 +      AVR32_OPC_PREF, 4, 0xf2100000, 0xfff00000,
23547 +      &avr32_syntax_table[AVR32_SYNTAX_PREF],
23548 +      BFD_RELOC_AVR32_16S, 2, -1,
23549 +      {
23550 +       &avr32_ifield_table[AVR32_IFIELD_RY],
23551 +       &avr32_ifield_table[AVR32_IFIELD_K16],
23552 +      },
23553 +    },
23554 +    {
23555 +      AVR32_OPC_PSAD, 4, 0xe0002400, 0xe1f0fff0,
23556 +      &avr32_syntax_table[AVR32_SYNTAX_PSAD],
23557 +      BFD_RELOC_UNUSED, 3, -1,
23558 +      {
23559 +       &avr32_ifield_table[AVR32_IFIELD_RD_E],
23560 +       &avr32_ifield_table[AVR32_IFIELD_RX],
23561 +       &avr32_ifield_table[AVR32_IFIELD_RY],
23562 +      },
23563 +    },
23564 +    {
23565 +      AVR32_OPC_PSUB_B, 4, 0xe0002310, 0xe1f0fff0,
23566 +      &avr32_syntax_table[AVR32_SYNTAX_PSUB_B],
23567 +      BFD_RELOC_UNUSED, 3, -1,
23568 +      {
23569 +       &avr32_ifield_table[AVR32_IFIELD_RD_E],
23570 +       &avr32_ifield_table[AVR32_IFIELD_RX],
23571 +       &avr32_ifield_table[AVR32_IFIELD_RY],
23572 +      },
23573 +    },
23574 +    {
23575 +      AVR32_OPC_PSUB_H, 4, 0xe0002010, 0xe1f0fff0,
23576 +      &avr32_syntax_table[AVR32_SYNTAX_PSUB_H],
23577 +      BFD_RELOC_UNUSED, 3, -1,
23578 +      {
23579 +       &avr32_ifield_table[AVR32_IFIELD_RD_E],
23580 +       &avr32_ifield_table[AVR32_IFIELD_RX],
23581 +       &avr32_ifield_table[AVR32_IFIELD_RY],
23582 +      },
23583 +    },
23584 +    {
23585 +      AVR32_OPC_PSUBADD_H, 4, 0xe0002140, 0xe1f0ffc0,
23586 +      &avr32_syntax_table[AVR32_SYNTAX_PSUBADD_H],
23587 +      BFD_RELOC_UNUSED, 5, -1,
23588 +      {
23589 +       &avr32_ifield_table[AVR32_IFIELD_RD_E],
23590 +       &avr32_ifield_table[AVR32_IFIELD_RX],
23591 +       &avr32_ifield_table[AVR32_IFIELD_X],
23592 +       &avr32_ifield_table[AVR32_IFIELD_RY],
23593 +       &avr32_ifield_table[AVR32_IFIELD_Y],
23594 +      },
23595 +    },
23596 +    {
23597 +      AVR32_OPC_PSUBADDH_SH, 4, 0xe00022c0, 0xe1f0ffc0,
23598 +      &avr32_syntax_table[AVR32_SYNTAX_PSUBADDH_SH],
23599 +      BFD_RELOC_UNUSED, 5, -1,
23600 +      {
23601 +       &avr32_ifield_table[AVR32_IFIELD_RD_E],
23602 +       &avr32_ifield_table[AVR32_IFIELD_RX],
23603 +       &avr32_ifield_table[AVR32_IFIELD_X],
23604 +       &avr32_ifield_table[AVR32_IFIELD_RY],
23605 +       &avr32_ifield_table[AVR32_IFIELD_Y],
23606 +      },
23607 +    },
23608 +    {
23609 +      AVR32_OPC_PSUBADDS_SH, 4, 0xe00021c0, 0xe1f0ffc0,
23610 +      &avr32_syntax_table[AVR32_SYNTAX_PSUBADDS_SH],
23611 +      BFD_RELOC_UNUSED, 5, -1,
23612 +      {
23613 +       &avr32_ifield_table[AVR32_IFIELD_RD_E],
23614 +       &avr32_ifield_table[AVR32_IFIELD_RX],
23615 +       &avr32_ifield_table[AVR32_IFIELD_X],
23616 +       &avr32_ifield_table[AVR32_IFIELD_RY],
23617 +       &avr32_ifield_table[AVR32_IFIELD_Y],
23618 +      },
23619 +    },
23620 +    {
23621 +      AVR32_OPC_PSUBADDS_UH, 4, 0xe0002240, 0xe1f0ffc0,
23622 +      &avr32_syntax_table[AVR32_SYNTAX_PSUBADDS_UH],
23623 +      BFD_RELOC_UNUSED, 5, -1,
23624 +      {
23625 +       &avr32_ifield_table[AVR32_IFIELD_RD_E],
23626 +       &avr32_ifield_table[AVR32_IFIELD_RX],
23627 +       &avr32_ifield_table[AVR32_IFIELD_X],
23628 +       &avr32_ifield_table[AVR32_IFIELD_RY],
23629 +       &avr32_ifield_table[AVR32_IFIELD_Y],
23630 +      },
23631 +    },
23632 +    {
23633 +      AVR32_OPC_PSUBH_SH, 4, 0xe00020d0, 0xe1f0fff0,
23634 +      &avr32_syntax_table[AVR32_SYNTAX_PSUBH_SH],
23635 +      BFD_RELOC_UNUSED, 3, -1,
23636 +      {
23637 +       &avr32_ifield_table[AVR32_IFIELD_RD_E],
23638 +       &avr32_ifield_table[AVR32_IFIELD_RX],
23639 +       &avr32_ifield_table[AVR32_IFIELD_RY],
23640 +      },
23641 +    },
23642 +    {
23643 +      AVR32_OPC_PSUBH_UB, 4, 0xe0002370, 0xe1f0fff0,
23644 +      &avr32_syntax_table[AVR32_SYNTAX_PSUBH_UB],
23645 +      BFD_RELOC_UNUSED, 3, -1,
23646 +      {
23647 +       &avr32_ifield_table[AVR32_IFIELD_RD_E],
23648 +       &avr32_ifield_table[AVR32_IFIELD_RX],
23649 +       &avr32_ifield_table[AVR32_IFIELD_RY],
23650 +      },
23651 +    },
23652 +    {
23653 +      AVR32_OPC_PSUBS_SB, 4, 0xe0002330, 0xe1f0fff0,
23654 +      &avr32_syntax_table[AVR32_SYNTAX_PSUBS_SB],
23655 +      BFD_RELOC_UNUSED, 3, -1,
23656 +      {
23657 +       &avr32_ifield_table[AVR32_IFIELD_RD_E],
23658 +       &avr32_ifield_table[AVR32_IFIELD_RX],
23659 +       &avr32_ifield_table[AVR32_IFIELD_RY],
23660 +      },
23661 +    },
23662 +    {
23663 +      AVR32_OPC_PSUBS_SH, 4, 0xe0002050, 0xe1f0fff0,
23664 +      &avr32_syntax_table[AVR32_SYNTAX_PSUBS_SH],
23665 +      BFD_RELOC_UNUSED, 3, -1,
23666 +      {
23667 +       &avr32_ifield_table[AVR32_IFIELD_RD_E],
23668 +       &avr32_ifield_table[AVR32_IFIELD_RX],
23669 +       &avr32_ifield_table[AVR32_IFIELD_RY],
23670 +      },
23671 +    },
23672 +    {
23673 +      AVR32_OPC_PSUBS_UB, 4, 0xe0002350, 0xe1f0fff0,
23674 +      &avr32_syntax_table[AVR32_SYNTAX_PSUBS_UB],
23675 +      BFD_RELOC_UNUSED, 3, -1,
23676 +      {
23677 +       &avr32_ifield_table[AVR32_IFIELD_RD_E],
23678 +       &avr32_ifield_table[AVR32_IFIELD_RX],
23679 +       &avr32_ifield_table[AVR32_IFIELD_RY],
23680 +      },
23681 +    },
23682 +    {
23683 +      AVR32_OPC_PSUBS_UH, 4, 0xe0002090, 0xe1f0fff0,
23684 +      &avr32_syntax_table[AVR32_SYNTAX_PSUBS_UH],
23685 +      BFD_RELOC_UNUSED, 3, -1,
23686 +      {
23687 +       &avr32_ifield_table[AVR32_IFIELD_RD_E],
23688 +       &avr32_ifield_table[AVR32_IFIELD_RX],
23689 +       &avr32_ifield_table[AVR32_IFIELD_RY],
23690 +      },
23691 +    },
23692 +    {
23693 +      AVR32_OPC_PSUBX_H, 4, 0xe0002030, 0xe1f0fff0,
23694 +      &avr32_syntax_table[AVR32_SYNTAX_PSUBX_H],
23695 +      BFD_RELOC_UNUSED, 3, -1,
23696 +      {
23697 +       &avr32_ifield_table[AVR32_IFIELD_RD_E],
23698 +       &avr32_ifield_table[AVR32_IFIELD_RX],
23699 +       &avr32_ifield_table[AVR32_IFIELD_RY],
23700 +      },
23701 +    },
23702 +    {
23703 +      AVR32_OPC_PSUBXH_SH, 4, 0xe00020f0, 0xe1f0fff0,
23704 +      &avr32_syntax_table[AVR32_SYNTAX_PSUBXH_SH],
23705 +      BFD_RELOC_UNUSED, 3, -1,
23706 +      {
23707 +       &avr32_ifield_table[AVR32_IFIELD_RD_E],
23708 +       &avr32_ifield_table[AVR32_IFIELD_RX],
23709 +       &avr32_ifield_table[AVR32_IFIELD_RY],
23710 +      },
23711 +    },
23712 +    {
23713 +      AVR32_OPC_PSUBXS_SH, 4, 0xe0002070, 0xe1f0fff0,
23714 +      &avr32_syntax_table[AVR32_SYNTAX_PSUBXS_SH],
23715 +      BFD_RELOC_UNUSED, 3, -1,
23716 +      {
23717 +       &avr32_ifield_table[AVR32_IFIELD_RD_E],
23718 +       &avr32_ifield_table[AVR32_IFIELD_RX],
23719 +       &avr32_ifield_table[AVR32_IFIELD_RY],
23720 +      },
23721 +    },
23722 +    {
23723 +      AVR32_OPC_PSUBXS_UH, 4, 0xe00020b0, 0xe1f0fff0,
23724 +      &avr32_syntax_table[AVR32_SYNTAX_PSUBXS_UH],
23725 +      BFD_RELOC_UNUSED, 3, -1,
23726 +      {
23727 +       &avr32_ifield_table[AVR32_IFIELD_RD_E],
23728 +       &avr32_ifield_table[AVR32_IFIELD_RX],
23729 +       &avr32_ifield_table[AVR32_IFIELD_RY],
23730 +      },
23731 +    },
23732 +    {
23733 +      AVR32_OPC_PUNPCKSB_H, 4, 0xe00024a0, 0xe1ffffe0,
23734 +      &avr32_syntax_table[AVR32_SYNTAX_PUNPCKSB_H],
23735 +      BFD_RELOC_UNUSED, 3, -1,
23736 +      {
23737 +       &avr32_ifield_table[AVR32_IFIELD_RD_E],
23738 +       &avr32_ifield_table[AVR32_IFIELD_RX],
23739 +       &avr32_ifield_table[AVR32_IFIELD_Y],
23740 +      },
23741 +    },
23742 +    {
23743 +      AVR32_OPC_PUNPCKUB_H, 4, 0xe0002480, 0xe1ffffe0,
23744 +      &avr32_syntax_table[AVR32_SYNTAX_PUNPCKUB_H],
23745 +      BFD_RELOC_UNUSED, 3, -1,
23746 +      {
23747 +       &avr32_ifield_table[AVR32_IFIELD_RD_E],
23748 +       &avr32_ifield_table[AVR32_IFIELD_RX],
23749 +       &avr32_ifield_table[AVR32_IFIELD_Y],
23750 +      },
23751 +    },
23752 +    {
23753 +      AVR32_OPC_PUSHJC, 2, 0xd7230000, 0xffff0000,
23754 +      &avr32_syntax_table[AVR32_SYNTAX_PUSHJC],
23755 +      BFD_RELOC_UNUSED, 0, -1, { NULL },
23756 +    },
23757 +    {
23758 +      AVR32_OPC_PUSHM, 2, 0xd0010000, 0xf00f0000,
23759 +      &avr32_syntax_table[AVR32_SYNTAX_PUSHM],
23760 +      BFD_RELOC_UNUSED, 1, -1,
23761 +      {
23762 +       &avr32_ifield_table[AVR32_IFIELD_K8C],
23763 +      },
23764 +    },
23765 +    {
23766 +      AVR32_OPC_PUSHM_E, 4, 0xebcd0000, 0xffff0000,
23767 +      &avr32_syntax_table[AVR32_SYNTAX_PUSHM_E],
23768 +      BFD_RELOC_UNUSED, 1, -1,
23769 +      {
23770 +       &avr32_ifield_table[AVR32_IFIELD_K16],
23771 +      },
23772 +    },
23773 +    {
23774 +      AVR32_OPC_RCALL1, 2, 0xc00c0000, 0xf00c0000,
23775 +      &avr32_syntax_table[AVR32_SYNTAX_RCALL1],
23776 +      BFD_RELOC_AVR32_11H_PCREL, 1, 0,
23777 +      {
23778 +       &avr32_ifield_table[AVR32_IFIELD_K10],
23779 +      },
23780 +    },
23781 +    {
23782 +      AVR32_OPC_RCALL2, 4, 0xe0a00000, 0xe1ef0000,
23783 +      &avr32_syntax_table[AVR32_SYNTAX_RCALL2],
23784 +      BFD_RELOC_AVR32_22H_PCREL, 1, 0,
23785 +      {
23786 +       &avr32_ifield_table[AVR32_IFIELD_K21],
23787 +      },
23788 +    },
23789 +    {
23790 +      AVR32_OPC_RETEQ, 2, 0x5e000000, 0xfff00000,
23791 +      &avr32_syntax_table[AVR32_SYNTAX_RETEQ],
23792 +      BFD_RELOC_NONE, 1, -1,
23793 +      {
23794 +       &avr32_ifield_table[AVR32_IFIELD_RY],
23795 +      },
23796 +    },
23797 +    {
23798 +      AVR32_OPC_RETNE, 2, 0x5e100000, 0xfff00000,
23799 +      &avr32_syntax_table[AVR32_SYNTAX_RETNE],
23800 +      BFD_RELOC_NONE, 1, -1,
23801 +      {
23802 +       &avr32_ifield_table[AVR32_IFIELD_RY],
23803 +      },
23804 +    },
23805 +    {
23806 +      AVR32_OPC_RETCC, 2, 0x5e200000, 0xfff00000,
23807 +      &avr32_syntax_table[AVR32_SYNTAX_RETHS],
23808 +      BFD_RELOC_NONE, 1, -1,
23809 +      {
23810 +       &avr32_ifield_table[AVR32_IFIELD_RY],
23811 +      },
23812 +    },
23813 +    {
23814 +      AVR32_OPC_RETCS, 2, 0x5e300000, 0xfff00000,
23815 +      &avr32_syntax_table[AVR32_SYNTAX_RETLO],
23816 +      BFD_RELOC_NONE, 1, -1,
23817 +      {
23818 +       &avr32_ifield_table[AVR32_IFIELD_RY],
23819 +      },
23820 +    },
23821 +    {
23822 +      AVR32_OPC_RETGE, 2, 0x5e400000, 0xfff00000,
23823 +      &avr32_syntax_table[AVR32_SYNTAX_RETGE],
23824 +      BFD_RELOC_NONE, 1, -1,
23825 +      {
23826 +       &avr32_ifield_table[AVR32_IFIELD_RY],
23827 +      },
23828 +    },
23829 +    {
23830 +      AVR32_OPC_RETLT, 2, 0x5e500000, 0xfff00000,
23831 +      &avr32_syntax_table[AVR32_SYNTAX_RETLT],
23832 +      BFD_RELOC_NONE, 1, -1,
23833 +      {
23834 +       &avr32_ifield_table[AVR32_IFIELD_RY],
23835 +      },
23836 +    },
23837 +    {
23838 +      AVR32_OPC_RETMI, 2, 0x5e600000, 0xfff00000,
23839 +      &avr32_syntax_table[AVR32_SYNTAX_RETMI],
23840 +      BFD_RELOC_NONE, 1, -1,
23841 +      {
23842 +       &avr32_ifield_table[AVR32_IFIELD_RY],
23843 +      },
23844 +    },
23845 +    {
23846 +      AVR32_OPC_RETPL, 2, 0x5e700000, 0xfff00000,
23847 +      &avr32_syntax_table[AVR32_SYNTAX_RETPL],
23848 +      BFD_RELOC_NONE, 1, -1,
23849 +      {
23850 +       &avr32_ifield_table[AVR32_IFIELD_RY],
23851 +      },
23852 +    },
23853 +    {
23854 +      AVR32_OPC_RETLS, 2, 0x5e800000, 0xfff00000,
23855 +      &avr32_syntax_table[AVR32_SYNTAX_RETLS],
23856 +      BFD_RELOC_NONE, 1, -1,
23857 +      {
23858 +       &avr32_ifield_table[AVR32_IFIELD_RY],
23859 +      },
23860 +    },
23861 +    {
23862 +      AVR32_OPC_RETGT, 2, 0x5e900000, 0xfff00000,
23863 +      &avr32_syntax_table[AVR32_SYNTAX_RETGT],
23864 +      BFD_RELOC_NONE, 1, -1,
23865 +      {
23866 +       &avr32_ifield_table[AVR32_IFIELD_RY],
23867 +      },
23868 +    },
23869 +    {
23870 +      AVR32_OPC_RETLE, 2, 0x5ea00000, 0xfff00000,
23871 +      &avr32_syntax_table[AVR32_SYNTAX_RETLE],
23872 +      BFD_RELOC_NONE, 1, -1,
23873 +      {
23874 +       &avr32_ifield_table[AVR32_IFIELD_RY],
23875 +      },
23876 +    },
23877 +    {
23878 +      AVR32_OPC_RETHI, 2, 0x5eb00000, 0xfff00000,
23879 +      &avr32_syntax_table[AVR32_SYNTAX_RETHI],
23880 +      BFD_RELOC_NONE, 1, -1,
23881 +      {
23882 +       &avr32_ifield_table[AVR32_IFIELD_RY],
23883 +      },
23884 +    },
23885 +    {
23886 +      AVR32_OPC_RETVS, 2, 0x5ec00000, 0xfff00000,
23887 +      &avr32_syntax_table[AVR32_SYNTAX_RETVS],
23888 +      BFD_RELOC_NONE, 1, -1,
23889 +      {
23890 +       &avr32_ifield_table[AVR32_IFIELD_RY],
23891 +      },
23892 +    },
23893 +    {
23894 +      AVR32_OPC_RETVC, 2, 0x5ed00000, 0xfff00000,
23895 +      &avr32_syntax_table[AVR32_SYNTAX_RETVC],
23896 +      BFD_RELOC_NONE, 1, -1,
23897 +      {
23898 +       &avr32_ifield_table[AVR32_IFIELD_RY],
23899 +      },
23900 +    },
23901 +    {
23902 +      AVR32_OPC_RETQS, 2, 0x5ee00000, 0xfff00000,
23903 +      &avr32_syntax_table[AVR32_SYNTAX_RETQS],
23904 +      BFD_RELOC_NONE, 1, -1,
23905 +      {
23906 +       &avr32_ifield_table[AVR32_IFIELD_RY],
23907 +      },
23908 +    },
23909 +    {
23910 +      AVR32_OPC_RETAL, 2, 0x5ef00000, 0xfff00000,
23911 +      &avr32_syntax_table[AVR32_SYNTAX_RETAL],
23912 +      BFD_RELOC_NONE, 1, -1,
23913 +      {
23914 +       &avr32_ifield_table[AVR32_IFIELD_RY],
23915 +      },
23916 +    },
23917 +    {
23918 +      AVR32_OPC_RETD, 2, 0xd6230000, 0xffff0000,
23919 +      &avr32_syntax_table[AVR32_SYNTAX_RETD],
23920 +      BFD_RELOC_NONE, 0, -1, { NULL },
23921 +    },
23922 +    {
23923 +      AVR32_OPC_RETE, 2, 0xd6030000, 0xffff0000,
23924 +      &avr32_syntax_table[AVR32_SYNTAX_RETE],
23925 +      BFD_RELOC_NONE, 0, -1, { NULL },
23926 +    },
23927 +    {
23928 +      AVR32_OPC_RETJ, 2, 0xd6330000, 0xffff0000,
23929 +      &avr32_syntax_table[AVR32_SYNTAX_RETJ],
23930 +      BFD_RELOC_NONE, 0, -1, { NULL },
23931 +    },
23932 +    {
23933 +      AVR32_OPC_RETS, 2, 0xd6130000, 0xffff0000,
23934 +      &avr32_syntax_table[AVR32_SYNTAX_RETS],
23935 +      BFD_RELOC_NONE, 0, -1, { NULL },
23936 +    },
23937 +    {
23938 +      AVR32_OPC_RJMP, 2, 0xc0080000, 0xf00c0000,
23939 +      &avr32_syntax_table[AVR32_SYNTAX_RJMP],
23940 +      BFD_RELOC_AVR32_11H_PCREL, 1, 0,
23941 +      {
23942 +       &avr32_ifield_table[AVR32_IFIELD_K10],
23943 +      },
23944 +    },
23945 +    {
23946 +      AVR32_OPC_ROL, 2, 0x5cf00000, 0xfff00000,
23947 +      &avr32_syntax_table[AVR32_SYNTAX_ROL],
23948 +      BFD_RELOC_UNUSED, 1, -1,
23949 +      {
23950 +       &avr32_ifield_table[AVR32_IFIELD_RY],
23951 +      }
23952 +    },
23953 +    {
23954 +      AVR32_OPC_ROR, 2, 0x5d000000, 0xfff00000,
23955 +      &avr32_syntax_table[AVR32_SYNTAX_ROR],
23956 +      BFD_RELOC_UNUSED, 1, -1,
23957 +      {
23958 +       &avr32_ifield_table[AVR32_IFIELD_RY],
23959 +      }
23960 +    },
23961 +    {
23962 +      AVR32_OPC_RSUB1, 2, 0x00200000, 0xe1f00000,
23963 +      &avr32_syntax_table[AVR32_SYNTAX_RSUB1],
23964 +      BFD_RELOC_UNUSED, 2, -1,
23965 +      {
23966 +       &avr32_ifield_table[AVR32_IFIELD_RY],
23967 +       &avr32_ifield_table[AVR32_IFIELD_RX],
23968 +      },
23969 +    },
23970 +    {
23971 +      AVR32_OPC_RSUB2, 4, 0xe0001100, 0xe1f0ff00,
23972 +      &avr32_syntax_table[AVR32_SYNTAX_RSUB2],
23973 +      BFD_RELOC_AVR32_8S_EXT, 3, 2,
23974 +      {
23975 +       &avr32_ifield_table[AVR32_IFIELD_RY],
23976 +       &avr32_ifield_table[AVR32_IFIELD_RX],
23977 +       &avr32_ifield_table[AVR32_IFIELD_K8E],
23978 +      },
23979 +    },
23980 +    {
23981 +      AVR32_OPC_SATADD_H, 4, 0xe00002c0, 0xe1f0fff0,
23982 +      &avr32_syntax_table[AVR32_SYNTAX_SATADD_H],
23983 +      BFD_RELOC_UNUSED, 3, -1,
23984 +      {
23985 +       &avr32_ifield_table[AVR32_IFIELD_RD_E],
23986 +       &avr32_ifield_table[AVR32_IFIELD_RX],
23987 +       &avr32_ifield_table[AVR32_IFIELD_RY],
23988 +      },
23989 +    },
23990 +    {
23991 +      AVR32_OPC_SATADD_W, 4, 0xe00000c0, 0xe1f0fff0,
23992 +      &avr32_syntax_table[AVR32_SYNTAX_SATADD_W],
23993 +      BFD_RELOC_UNUSED, 3, -1,
23994 +      {
23995 +       &avr32_ifield_table[AVR32_IFIELD_RD_E],
23996 +       &avr32_ifield_table[AVR32_IFIELD_RX],
23997 +       &avr32_ifield_table[AVR32_IFIELD_RY],
23998 +      },
23999 +    },
24000 +    {
24001 +      AVR32_OPC_SATRNDS, 4, 0xf3b00000, 0xfff0fc00,
24002 +      &avr32_syntax_table[AVR32_SYNTAX_SATRNDS],
24003 +      BFD_RELOC_UNUSED, 3, -1,
24004 +      {
24005 +       &avr32_ifield_table[AVR32_IFIELD_RY],
24006 +       &avr32_ifield_table[AVR32_IFIELD_K5E],
24007 +       &avr32_ifield_table[AVR32_IFIELD_S5],
24008 +      },
24009 +    },
24010 +    {
24011 +      AVR32_OPC_SATRNDU, 4, 0xf3b00400, 0xfff0fc00,
24012 +      &avr32_syntax_table[AVR32_SYNTAX_SATRNDU],
24013 +      BFD_RELOC_UNUSED, 3, -1,
24014 +      {
24015 +       &avr32_ifield_table[AVR32_IFIELD_RY],
24016 +       &avr32_ifield_table[AVR32_IFIELD_K5E],
24017 +       &avr32_ifield_table[AVR32_IFIELD_S5],
24018 +      },
24019 +    },
24020 +    {
24021 +      AVR32_OPC_SATS, 4, 0xf1b00000, 0xfff0fc00,
24022 +      &avr32_syntax_table[AVR32_SYNTAX_SATS],
24023 +      BFD_RELOC_UNUSED, 3, -1,
24024 +      {
24025 +       &avr32_ifield_table[AVR32_IFIELD_RY],
24026 +       &avr32_ifield_table[AVR32_IFIELD_K5E],
24027 +       &avr32_ifield_table[AVR32_IFIELD_S5],
24028 +      },
24029 +    },
24030 +    {
24031 +      AVR32_OPC_SATSUB_H, 4, 0xe00003c0, 0xe1f0fff0,
24032 +      &avr32_syntax_table[AVR32_SYNTAX_SATSUB_H],
24033 +      BFD_RELOC_UNUSED, 3, -1,
24034 +      {
24035 +       &avr32_ifield_table[AVR32_IFIELD_RD_E],
24036 +       &avr32_ifield_table[AVR32_IFIELD_RX],
24037 +       &avr32_ifield_table[AVR32_IFIELD_RY],
24038 +      },
24039 +    },
24040 +    {
24041 +      AVR32_OPC_SATSUB_W1, 4, 0xe00001c0, 0xe1f0fff0,
24042 +      &avr32_syntax_table[AVR32_SYNTAX_SATSUB_W1],
24043 +      BFD_RELOC_UNUSED, 3, -1,
24044 +      {
24045 +       &avr32_ifield_table[AVR32_IFIELD_RD_E],
24046 +       &avr32_ifield_table[AVR32_IFIELD_RX],
24047 +       &avr32_ifield_table[AVR32_IFIELD_RY],
24048 +      },
24049 +    },
24050 +    {
24051 +      AVR32_OPC_SATSUB_W2, 4, 0xe0d00000, 0xe1f00000,
24052 +      &avr32_syntax_table[AVR32_SYNTAX_SATSUB_W2],
24053 +      BFD_RELOC_UNUSED, 3, -1,
24054 +      {
24055 +       &avr32_ifield_table[AVR32_IFIELD_RY],
24056 +       &avr32_ifield_table[AVR32_IFIELD_RX],
24057 +       &avr32_ifield_table[AVR32_IFIELD_K16],
24058 +      },
24059 +    },
24060 +    {
24061 +      AVR32_OPC_SATU, 4, 0xf1b00400, 0xfff0fc00,
24062 +      &avr32_syntax_table[AVR32_SYNTAX_SATU],
24063 +      BFD_RELOC_UNUSED, 3, -1,
24064 +      {
24065 +       &avr32_ifield_table[AVR32_IFIELD_RY],
24066 +       &avr32_ifield_table[AVR32_IFIELD_K5E],
24067 +       &avr32_ifield_table[AVR32_IFIELD_S5],
24068 +      },
24069 +    },
24070 +    {
24071 +      AVR32_OPC_SBC, 4, 0xe0000140, 0xe1f0fff0,
24072 +      &avr32_syntax_table[AVR32_SYNTAX_SBC],
24073 +      BFD_RELOC_UNUSED, 3, -1,
24074 +      {
24075 +       &avr32_ifield_table[AVR32_IFIELD_RD_E],
24076 +       &avr32_ifield_table[AVR32_IFIELD_RX],
24077 +       &avr32_ifield_table[AVR32_IFIELD_RY],
24078 +      },
24079 +    },
24080 +    {
24081 +      AVR32_OPC_SBR, 2, 0xa1a00000, 0xe1e00000,
24082 +      &avr32_syntax_table[AVR32_SYNTAX_SBR],
24083 +      BFD_RELOC_UNUSED, 2, -1,
24084 +      {
24085 +       &avr32_ifield_table[AVR32_IFIELD_RY],
24086 +       &avr32_ifield_table[AVR32_IFIELD_BIT5C],
24087 +      },
24088 +    },
24089 +    {
24090 +      AVR32_OPC_SCALL, 2, 0xd7330000, 0xffff0000,
24091 +      &avr32_syntax_table[AVR32_SYNTAX_SCALL],
24092 +      BFD_RELOC_UNUSED, 0, -1, { NULL },
24093 +    },
24094 +    {
24095 +      AVR32_OPC_SCR, 2, 0x5c100000, 0xfff00000,
24096 +      &avr32_syntax_table[AVR32_SYNTAX_SCR],
24097 +      BFD_RELOC_UNUSED, 1, -1,
24098 +      {
24099 +       &avr32_ifield_table[AVR32_IFIELD_RY],
24100 +      },
24101 +    },
24102 +    {
24103 +      AVR32_OPC_SLEEP, 4, 0xe9b00000, 0xffffff00,
24104 +      &avr32_syntax_table[AVR32_SYNTAX_SLEEP],
24105 +      BFD_RELOC_AVR32_8S_EXT, 1, 0,
24106 +      {
24107 +       &avr32_ifield_table[AVR32_IFIELD_K8E],
24108 +      },
24109 +    },
24110 +    {
24111 +      AVR32_OPC_SREQ, 2, 0x5f000000, 0xfff00000,
24112 +      &avr32_syntax_table[AVR32_SYNTAX_SREQ],
24113 +      BFD_RELOC_UNUSED, 1, -1,
24114 +      {
24115 +       &avr32_ifield_table[AVR32_IFIELD_RY],
24116 +      },
24117 +    },
24118 +    {
24119 +      AVR32_OPC_SRNE, 2, 0x5f100000, 0xfff00000,
24120 +      &avr32_syntax_table[AVR32_SYNTAX_SRNE],
24121 +      BFD_RELOC_UNUSED, 1, -1,
24122 +      {
24123 +       &avr32_ifield_table[AVR32_IFIELD_RY],
24124 +      },
24125 +    },
24126 +    {
24127 +      AVR32_OPC_SRCC, 2, 0x5f200000, 0xfff00000,
24128 +      &avr32_syntax_table[AVR32_SYNTAX_SRHS],
24129 +      BFD_RELOC_UNUSED, 1, -1,
24130 +      {
24131 +       &avr32_ifield_table[AVR32_IFIELD_RY],
24132 +      },
24133 +    },
24134 +    {
24135 +      AVR32_OPC_SRCS, 2, 0x5f300000, 0xfff00000,
24136 +      &avr32_syntax_table[AVR32_SYNTAX_SRLO],
24137 +      BFD_RELOC_UNUSED, 1, -1,
24138 +      {
24139 +       &avr32_ifield_table[AVR32_IFIELD_RY],
24140 +      },
24141 +    },
24142 +    {
24143 +      AVR32_OPC_SRGE, 2, 0x5f400000, 0xfff00000,
24144 +      &avr32_syntax_table[AVR32_SYNTAX_SRGE],
24145 +      BFD_RELOC_UNUSED, 1, -1,
24146 +      {
24147 +       &avr32_ifield_table[AVR32_IFIELD_RY],
24148 +      },
24149 +    },
24150 +    {
24151 +      AVR32_OPC_SRLT, 2, 0x5f500000, 0xfff00000,
24152 +      &avr32_syntax_table[AVR32_SYNTAX_SRLT],
24153 +      BFD_RELOC_UNUSED, 1, -1,
24154 +      {
24155 +       &avr32_ifield_table[AVR32_IFIELD_RY],
24156 +      },
24157 +    },
24158 +    {
24159 +      AVR32_OPC_SRMI, 2, 0x5f600000, 0xfff00000,
24160 +      &avr32_syntax_table[AVR32_SYNTAX_SRMI],
24161 +      BFD_RELOC_UNUSED, 1, -1,
24162 +      {
24163 +       &avr32_ifield_table[AVR32_IFIELD_RY],
24164 +      },
24165 +    },
24166 +    {
24167 +      AVR32_OPC_SRPL, 2, 0x5f700000, 0xfff00000,
24168 +      &avr32_syntax_table[AVR32_SYNTAX_SRPL],
24169 +      BFD_RELOC_UNUSED, 1, -1,
24170 +      {
24171 +       &avr32_ifield_table[AVR32_IFIELD_RY],
24172 +      },
24173 +    },
24174 +    {
24175 +      AVR32_OPC_SRLS, 2, 0x5f800000, 0xfff00000,
24176 +      &avr32_syntax_table[AVR32_SYNTAX_SRLS],
24177 +      BFD_RELOC_UNUSED, 1, -1,
24178 +      {
24179 +       &avr32_ifield_table[AVR32_IFIELD_RY],
24180 +      },
24181 +    },
24182 +    {
24183 +      AVR32_OPC_SRGT, 2, 0x5f900000, 0xfff00000,
24184 +      &avr32_syntax_table[AVR32_SYNTAX_SRGT],
24185 +      BFD_RELOC_UNUSED, 1, -1,
24186 +      {
24187 +       &avr32_ifield_table[AVR32_IFIELD_RY],
24188 +      },
24189 +    },
24190 +    {
24191 +      AVR32_OPC_SRLE, 2, 0x5fa00000, 0xfff00000,
24192 +      &avr32_syntax_table[AVR32_SYNTAX_SRLE],
24193 +      BFD_RELOC_UNUSED, 1, -1,
24194 +      {
24195 +       &avr32_ifield_table[AVR32_IFIELD_RY],
24196 +      },
24197 +    },
24198 +    {
24199 +      AVR32_OPC_SRHI, 2, 0x5fb00000, 0xfff00000,
24200 +      &avr32_syntax_table[AVR32_SYNTAX_SRHI],
24201 +      BFD_RELOC_UNUSED, 1, -1,
24202 +      {
24203 +       &avr32_ifield_table[AVR32_IFIELD_RY],
24204 +      },
24205 +    },
24206 +    {
24207 +      AVR32_OPC_SRVS, 2, 0x5fc00000, 0xfff00000,
24208 +      &avr32_syntax_table[AVR32_SYNTAX_SRVS],
24209 +      BFD_RELOC_UNUSED, 1, -1,
24210 +      {
24211 +       &avr32_ifield_table[AVR32_IFIELD_RY],
24212 +      },
24213 +    },
24214 +    {
24215 +      AVR32_OPC_SRVC, 2, 0x5fd00000, 0xfff00000,
24216 +      &avr32_syntax_table[AVR32_SYNTAX_SRVC],
24217 +      BFD_RELOC_UNUSED, 1, -1,
24218 +      {
24219 +       &avr32_ifield_table[AVR32_IFIELD_RY],
24220 +      },
24221 +    },
24222 +    {
24223 +      AVR32_OPC_SRQS, 2, 0x5fe00000, 0xfff00000,
24224 +      &avr32_syntax_table[AVR32_SYNTAX_SRQS],
24225 +      BFD_RELOC_UNUSED, 1, -1,
24226 +      {
24227 +       &avr32_ifield_table[AVR32_IFIELD_RY],
24228 +      },
24229 +    },
24230 +    {
24231 +      AVR32_OPC_SRAL, 2, 0x5ff00000, 0xfff00000,
24232 +      &avr32_syntax_table[AVR32_SYNTAX_SRAL],
24233 +      BFD_RELOC_UNUSED, 1, -1,
24234 +      {
24235 +       &avr32_ifield_table[AVR32_IFIELD_RY],
24236 +      },
24237 +    },
24238 +    {
24239 +      AVR32_OPC_SSRF, 2, 0xd2030000, 0xfe0f0000,
24240 +      &avr32_syntax_table[AVR32_SYNTAX_SSRF],
24241 +      BFD_RELOC_UNUSED, 1, -1,
24242 +      {
24243 +       &avr32_ifield_table[AVR32_IFIELD_K5C],
24244 +      },
24245 +    },
24246 +    {
24247 +      AVR32_OPC_ST_B1, 2, 0x00c00000, 0xe1f00000,
24248 +      &avr32_syntax_table[AVR32_SYNTAX_ST_B1],
24249 +      BFD_RELOC_UNUSED, 2, -1,
24250 +      {
24251 +       &avr32_ifield_table[AVR32_IFIELD_RX],
24252 +       &avr32_ifield_table[AVR32_IFIELD_RY],
24253 +      },
24254 +    },
24255 +    {
24256 +      AVR32_OPC_ST_B2, 2, 0x00f00000, 0xe1f00000,
24257 +      &avr32_syntax_table[AVR32_SYNTAX_ST_B2],
24258 +      BFD_RELOC_UNUSED, 2, -1,
24259 +      {
24260 +       &avr32_ifield_table[AVR32_IFIELD_RX],
24261 +       &avr32_ifield_table[AVR32_IFIELD_RY],
24262 +      },
24263 +    },
24264 +    {
24265 +      AVR32_OPC_ST_B5, 4, 0xe0000b00, 0xe1f0ffc0,
24266 +      &avr32_syntax_table[AVR32_SYNTAX_ST_B5],
24267 +      BFD_RELOC_UNUSED, 4, -1,
24268 +      {
24269 +       &avr32_ifield_table[AVR32_IFIELD_RX],
24270 +       &avr32_ifield_table[AVR32_IFIELD_RY],
24271 +       &avr32_ifield_table[AVR32_IFIELD_K2],
24272 +       &avr32_ifield_table[AVR32_IFIELD_RD_E],
24273 +      },
24274 +    },
24275 +    {
24276 +      AVR32_OPC_ST_B3, 2, 0xa0800000, 0xe1800000,
24277 +      &avr32_syntax_table[AVR32_SYNTAX_ST_B3],
24278 +      BFD_RELOC_AVR32_3U, 3, 1,
24279 +      {
24280 +       &avr32_ifield_table[AVR32_IFIELD_RX],
24281 +       &avr32_ifield_table[AVR32_IFIELD_K3],
24282 +       &avr32_ifield_table[AVR32_IFIELD_RY],
24283 +      },
24284 +    },
24285 +    {
24286 +      AVR32_OPC_ST_B4, 4, 0xe1600000, 0xe1f00000,
24287 +      &avr32_syntax_table[AVR32_SYNTAX_ST_B4],
24288 +      BFD_RELOC_AVR32_16S, 3, 1,
24289 +      {
24290 +       &avr32_ifield_table[AVR32_IFIELD_RX],
24291 +       &avr32_ifield_table[AVR32_IFIELD_K16],
24292 +       &avr32_ifield_table[AVR32_IFIELD_RY],
24293 +      },
24294 +    },
24295 +    {
24296 +      AVR32_OPC_ST_D1, 2, 0xa1200000, 0xe1f10000,
24297 +      &avr32_syntax_table[AVR32_SYNTAX_ST_D1],
24298 +      BFD_RELOC_UNUSED, 2, -1,
24299 +      {
24300 +       &avr32_ifield_table[AVR32_IFIELD_RX],
24301 +       &avr32_ifield_table[AVR32_IFIELD_RY_DW],
24302 +      },
24303 +    },
24304 +    {
24305 +      AVR32_OPC_ST_D2, 2, 0xa1210000, 0xe1f10000,
24306 +      &avr32_syntax_table[AVR32_SYNTAX_ST_D2],
24307 +      BFD_RELOC_UNUSED, 2, -1,
24308 +      {
24309 +       &avr32_ifield_table[AVR32_IFIELD_RX],
24310 +       &avr32_ifield_table[AVR32_IFIELD_RY_DW],
24311 +      },
24312 +    },
24313 +    {
24314 +      AVR32_OPC_ST_D3, 2, 0xa1110000, 0xe1f10000,
24315 +      &avr32_syntax_table[AVR32_SYNTAX_ST_D3],
24316 +      BFD_RELOC_UNUSED, 2, -1,
24317 +      {
24318 +       &avr32_ifield_table[AVR32_IFIELD_RX],
24319 +       &avr32_ifield_table[AVR32_IFIELD_RY_DW],
24320 +      },
24321 +    },
24322 +    {
24323 +      AVR32_OPC_ST_D5, 4, 0xe0000800, 0xe1f0ffc1,
24324 +      &avr32_syntax_table[AVR32_SYNTAX_ST_D5],
24325 +      BFD_RELOC_UNUSED, 4, -1,
24326 +      {
24327 +       &avr32_ifield_table[AVR32_IFIELD_RX],
24328 +       &avr32_ifield_table[AVR32_IFIELD_RY],
24329 +       &avr32_ifield_table[AVR32_IFIELD_K2],
24330 +       &avr32_ifield_table[AVR32_IFIELD_RD_DW],
24331 +      },
24332 +    },
24333 +    {
24334 +      AVR32_OPC_ST_D4, 4, 0xe0e10000, 0xe1f10000,
24335 +      &avr32_syntax_table[AVR32_SYNTAX_ST_D4],
24336 +      BFD_RELOC_AVR32_16S, 3, 1,
24337 +      {
24338 +       &avr32_ifield_table[AVR32_IFIELD_RX],
24339 +       &avr32_ifield_table[AVR32_IFIELD_K16],
24340 +       &avr32_ifield_table[AVR32_IFIELD_RY_DW],
24341 +      },
24342 +    },
24343 +    {
24344 +      AVR32_OPC_ST_H1, 2, 0x00b00000, 0xe1f00000,
24345 +      &avr32_syntax_table[AVR32_SYNTAX_ST_H1],
24346 +      BFD_RELOC_UNUSED, 2, -1,
24347 +      {
24348 +       &avr32_ifield_table[AVR32_IFIELD_RX],
24349 +       &avr32_ifield_table[AVR32_IFIELD_RY],
24350 +      },
24351 +    },
24352 +    {
24353 +      AVR32_OPC_ST_H2, 2, 0x00e00000, 0xe1f00000,
24354 +      &avr32_syntax_table[AVR32_SYNTAX_ST_H2],
24355 +      BFD_RELOC_UNUSED, 2, -1,
24356 +      {
24357 +       &avr32_ifield_table[AVR32_IFIELD_RX],
24358 +       &avr32_ifield_table[AVR32_IFIELD_RY],
24359 +      },
24360 +    },
24361 +    {
24362 +      AVR32_OPC_ST_H5, 4, 0xe0000a00, 0xe1f0ffc0,
24363 +      &avr32_syntax_table[AVR32_SYNTAX_ST_H5],
24364 +      BFD_RELOC_UNUSED, 4, -1,
24365 +      {
24366 +       &avr32_ifield_table[AVR32_IFIELD_RX],
24367 +       &avr32_ifield_table[AVR32_IFIELD_RY],
24368 +       &avr32_ifield_table[AVR32_IFIELD_K2],
24369 +       &avr32_ifield_table[AVR32_IFIELD_RD_E],
24370 +      },
24371 +    },
24372 +    {
24373 +      AVR32_OPC_ST_H3, 2, 0xa0000000, 0xe1800000,
24374 +      &avr32_syntax_table[AVR32_SYNTAX_ST_H3],
24375 +      BFD_RELOC_AVR32_4UH, 3, 1,
24376 +      {
24377 +       &avr32_ifield_table[AVR32_IFIELD_RX],
24378 +       &avr32_ifield_table[AVR32_IFIELD_K3],
24379 +       &avr32_ifield_table[AVR32_IFIELD_RY],
24380 +      },
24381 +    },
24382 +    {
24383 +      AVR32_OPC_ST_H4, 4, 0xe1500000, 0xe1f00000,
24384 +      &avr32_syntax_table[AVR32_SYNTAX_ST_H4],
24385 +      BFD_RELOC_AVR32_16S, 3, 1,
24386 +      {
24387 +       &avr32_ifield_table[AVR32_IFIELD_RX],
24388 +       &avr32_ifield_table[AVR32_IFIELD_K16],
24389 +       &avr32_ifield_table[AVR32_IFIELD_RY],
24390 +      },
24391 +    },
24392 +    {
24393 +      AVR32_OPC_ST_W1, 2, 0x00a00000, 0xe1f00000,
24394 +      &avr32_syntax_table[AVR32_SYNTAX_ST_W1],
24395 +      BFD_RELOC_UNUSED, 2, -1,
24396 +      {
24397 +       &avr32_ifield_table[AVR32_IFIELD_RX],
24398 +       &avr32_ifield_table[AVR32_IFIELD_RY],
24399 +      },
24400 +    },
24401 +    {
24402 +      AVR32_OPC_ST_W2, 2, 0x00d00000, 0xe1f00000,
24403 +      &avr32_syntax_table[AVR32_SYNTAX_ST_W2],
24404 +      BFD_RELOC_UNUSED, 2, -1,
24405 +      {
24406 +       &avr32_ifield_table[AVR32_IFIELD_RX],
24407 +       &avr32_ifield_table[AVR32_IFIELD_RY],
24408 +      },
24409 +    },
24410 +    {
24411 +      AVR32_OPC_ST_W5, 4, 0xe0000900, 0xe1f0ffc0,
24412 +      &avr32_syntax_table[AVR32_SYNTAX_ST_W5],
24413 +      BFD_RELOC_UNUSED, 4, -1,
24414 +      {
24415 +       &avr32_ifield_table[AVR32_IFIELD_RX],
24416 +       &avr32_ifield_table[AVR32_IFIELD_RY],
24417 +       &avr32_ifield_table[AVR32_IFIELD_K2],
24418 +       &avr32_ifield_table[AVR32_IFIELD_RD_E],
24419 +      },
24420 +    },
24421 +    {
24422 +      AVR32_OPC_ST_W3, 2, 0x81000000, 0xe1000000,
24423 +      &avr32_syntax_table[AVR32_SYNTAX_ST_W3],
24424 +      BFD_RELOC_AVR32_6UW, 3, 1,
24425 +      {
24426 +       &avr32_ifield_table[AVR32_IFIELD_RX],
24427 +       &avr32_ifield_table[AVR32_IFIELD_K4],
24428 +       &avr32_ifield_table[AVR32_IFIELD_RY],
24429 +      },
24430 +    },
24431 +    {
24432 +      AVR32_OPC_ST_W4, 4, 0xe1400000, 0xe1f00000,
24433 +      &avr32_syntax_table[AVR32_SYNTAX_ST_W4],
24434 +      BFD_RELOC_AVR32_16S, 3, 1,
24435 +      {
24436 +       &avr32_ifield_table[AVR32_IFIELD_RX],
24437 +       &avr32_ifield_table[AVR32_IFIELD_K16],
24438 +       &avr32_ifield_table[AVR32_IFIELD_RY],
24439 +      },
24440 +    },
24441 +    {
24442 +      AVR32_OPC_STC_D1, 4, 0xeba01000, 0xfff01100,
24443 +      &avr32_syntax_table[AVR32_SYNTAX_STC_D1],
24444 +      BFD_RELOC_AVR32_10UW, 4, 2,
24445 +      {
24446 +       &avr32_ifield_table[AVR32_IFIELD_CPNO],
24447 +       &avr32_ifield_table[AVR32_IFIELD_RY],
24448 +       &avr32_ifield_table[AVR32_IFIELD_K8E],
24449 +       &avr32_ifield_table[AVR32_IFIELD_CRD_DW],
24450 +      },
24451 +    },
24452 +    {
24453 +      AVR32_OPC_STC_D2, 4, 0xefa00070, 0xfff011f0,
24454 +      &avr32_syntax_table[AVR32_SYNTAX_STC_D2],
24455 +      BFD_RELOC_UNUSED, 3, -1,
24456 +      {
24457 +       &avr32_ifield_table[AVR32_IFIELD_CPNO],
24458 +       &avr32_ifield_table[AVR32_IFIELD_RY],
24459 +       &avr32_ifield_table[AVR32_IFIELD_CRD_DW],
24460 +      },
24461 +    },
24462 +    {
24463 +      AVR32_OPC_STC_D3, 4, 0xefa010c0, 0xfff011c0,
24464 +      &avr32_syntax_table[AVR32_SYNTAX_STC_D3],
24465 +      BFD_RELOC_UNUSED, 5, -1,
24466 +      {
24467 +       &avr32_ifield_table[AVR32_IFIELD_CPNO],
24468 +       &avr32_ifield_table[AVR32_IFIELD_RY],
24469 +       &avr32_ifield_table[AVR32_IFIELD_RD_E],
24470 +       &avr32_ifield_table[AVR32_IFIELD_K2],
24471 +       &avr32_ifield_table[AVR32_IFIELD_CRD_DW],
24472 +      },
24473 +    },
24474 +    {
24475 +      AVR32_OPC_STC_W1, 4, 0xeba00000, 0xfff01000,
24476 +      &avr32_syntax_table[AVR32_SYNTAX_STC_W1],
24477 +      BFD_RELOC_AVR32_10UW, 4, 2,
24478 +      {
24479 +       &avr32_ifield_table[AVR32_IFIELD_CPNO],
24480 +       &avr32_ifield_table[AVR32_IFIELD_RY],
24481 +       &avr32_ifield_table[AVR32_IFIELD_K8E],
24482 +       &avr32_ifield_table[AVR32_IFIELD_CRD_RI],
24483 +      },
24484 +    },
24485 +    {
24486 +      AVR32_OPC_STC_W2, 4, 0xefa00060, 0xfff010ff,
24487 +      &avr32_syntax_table[AVR32_SYNTAX_STC_W2],
24488 +      BFD_RELOC_UNUSED, 3, -1,
24489 +      {
24490 +       &avr32_ifield_table[AVR32_IFIELD_CPNO],
24491 +       &avr32_ifield_table[AVR32_IFIELD_RY],
24492 +       &avr32_ifield_table[AVR32_IFIELD_CRD_RI],
24493 +      },
24494 +    },
24495 +    {
24496 +      AVR32_OPC_STC_W3, 4, 0xefa01080, 0xfff010c0,
24497 +      &avr32_syntax_table[AVR32_SYNTAX_STC_W3],
24498 +      BFD_RELOC_UNUSED, 5, -1,
24499 +      {
24500 +       &avr32_ifield_table[AVR32_IFIELD_CPNO],
24501 +       &avr32_ifield_table[AVR32_IFIELD_RY],
24502 +       &avr32_ifield_table[AVR32_IFIELD_RD_E],
24503 +       &avr32_ifield_table[AVR32_IFIELD_K2],
24504 +       &avr32_ifield_table[AVR32_IFIELD_CRD_RI],
24505 +      },
24506 +    },
24507 +    {
24508 +      AVR32_OPC_STC0_D, 4, 0xf7a00000, 0xfff00100,
24509 +      &avr32_syntax_table[AVR32_SYNTAX_STC0_D],
24510 +      BFD_RELOC_AVR32_14UW, 3, 1,
24511 +      {
24512 +       &avr32_ifield_table[AVR32_IFIELD_RY],
24513 +       &avr32_ifield_table[AVR32_IFIELD_K12CP],
24514 +       &avr32_ifield_table[AVR32_IFIELD_CRD_DW],
24515 +      },
24516 +    },
24517 +    {
24518 +      AVR32_OPC_STC0_W, 4, 0xf5a00000, 0xfff00000,
24519 +      &avr32_syntax_table[AVR32_SYNTAX_STC0_W],
24520 +      BFD_RELOC_AVR32_14UW, 3, 1,
24521 +      {
24522 +       &avr32_ifield_table[AVR32_IFIELD_RY],
24523 +       &avr32_ifield_table[AVR32_IFIELD_K12CP],
24524 +       &avr32_ifield_table[AVR32_IFIELD_CRD_RI],
24525 +      },
24526 +    },
24527 +    {
24528 +      AVR32_OPC_STCM_D, 4, 0xeda00500, 0xfff01f00,
24529 +      &avr32_syntax_table[AVR32_SYNTAX_STCM_D],
24530 +      BFD_RELOC_UNUSED, 3, -1,
24531 +      {
24532 +       &avr32_ifield_table[AVR32_IFIELD_CPNO],
24533 +       &avr32_ifield_table[AVR32_IFIELD_RY],
24534 +       &avr32_ifield_table[AVR32_IFIELD_K8E],
24535 +      },
24536 +    },
24537 +    {
24538 +      AVR32_OPC_STCM_D_PU, 4, 0xeda01500, 0xfff01f00,
24539 +      &avr32_syntax_table[AVR32_SYNTAX_STCM_D_PU],
24540 +      BFD_RELOC_UNUSED, 3, -1,
24541 +      {
24542 +       &avr32_ifield_table[AVR32_IFIELD_CPNO],
24543 +       &avr32_ifield_table[AVR32_IFIELD_RY],
24544 +       &avr32_ifield_table[AVR32_IFIELD_K8E],
24545 +      },
24546 +    },
24547 +    {
24548 +      AVR32_OPC_STCM_W, 4, 0xeda00200, 0xfff01e00,
24549 +      &avr32_syntax_table[AVR32_SYNTAX_STCM_W],
24550 +      BFD_RELOC_UNUSED, 4, -1,
24551 +      {
24552 +       &avr32_ifield_table[AVR32_IFIELD_CPNO],
24553 +       &avr32_ifield_table[AVR32_IFIELD_RY],
24554 +       &avr32_ifield_table[AVR32_IFIELD_K8E],
24555 +       &avr32_ifield_table[AVR32_IFIELD_CM_HL],
24556 +      },
24557 +    },
24558 +    {
24559 +      AVR32_OPC_STCM_W_PU, 4, 0xeda01200, 0xfff01e00,
24560 +      &avr32_syntax_table[AVR32_SYNTAX_STCM_W_PU],
24561 +      BFD_RELOC_UNUSED, 4, -1,
24562 +      {
24563 +       &avr32_ifield_table[AVR32_IFIELD_CPNO],
24564 +       &avr32_ifield_table[AVR32_IFIELD_RY],
24565 +       &avr32_ifield_table[AVR32_IFIELD_K8E],
24566 +       &avr32_ifield_table[AVR32_IFIELD_CM_HL],
24567 +      },
24568 +    },
24569 +    {
24570 +      AVR32_OPC_STCOND, 4, 0xe1700000, 0xe1f00000,
24571 +      &avr32_syntax_table[AVR32_SYNTAX_STCOND],
24572 +      BFD_RELOC_UNUSED, 3, -1,
24573 +      {
24574 +       &avr32_ifield_table[AVR32_IFIELD_RX],
24575 +       &avr32_ifield_table[AVR32_IFIELD_K16],
24576 +       &avr32_ifield_table[AVR32_IFIELD_RY],
24577 +      },
24578 +    },
24579 +    {
24580 +      AVR32_OPC_STDSP, 2, 0x50000000, 0xf8000000,
24581 +      &avr32_syntax_table[AVR32_SYNTAX_STDSP],
24582 +      BFD_RELOC_UNUSED, 2, -1,
24583 +      {
24584 +       &avr32_ifield_table[AVR32_IFIELD_K7C],
24585 +       &avr32_ifield_table[AVR32_IFIELD_RY],
24586 +      },
24587 +    },
24588 +    {
24589 +      AVR32_OPC_STHH_W2, 4, 0xe1e08000, 0xe1f0c0c0,
24590 +      &avr32_syntax_table[AVR32_SYNTAX_STHH_W2],
24591 +      BFD_RELOC_UNUSED, 7, -1,
24592 +      {
24593 +       &avr32_ifield_table[AVR32_IFIELD_RD_E],
24594 +       &avr32_ifield_table[AVR32_IFIELD_CRD_RI],
24595 +       &avr32_ifield_table[AVR32_IFIELD_K2],
24596 +       &avr32_ifield_table[AVR32_IFIELD_RX],
24597 +       &avr32_ifield_table[AVR32_IFIELD_X2],
24598 +       &avr32_ifield_table[AVR32_IFIELD_RY],
24599 +       &avr32_ifield_table[AVR32_IFIELD_Y2],
24600 +      },
24601 +    },
24602 +    {
24603 +      AVR32_OPC_STHH_W1, 4, 0xe1e0c000, 0xe1f0c000,
24604 +      &avr32_syntax_table[AVR32_SYNTAX_STHH_W1],
24605 +      BFD_RELOC_AVR32_STHH_W, 6, 1,
24606 +      {
24607 +       &avr32_ifield_table[AVR32_IFIELD_RD_E],
24608 +       &avr32_ifield_table[AVR32_IFIELD_K8E2],
24609 +       &avr32_ifield_table[AVR32_IFIELD_RX],
24610 +       &avr32_ifield_table[AVR32_IFIELD_X2],
24611 +       &avr32_ifield_table[AVR32_IFIELD_RY],
24612 +       &avr32_ifield_table[AVR32_IFIELD_Y2],
24613 +      },
24614 +    },
24615 +    {
24616 +      AVR32_OPC_STM, 4, 0xe9c00000, 0xfff00000,
24617 +      &avr32_syntax_table[AVR32_SYNTAX_STM],
24618 +      BFD_RELOC_UNUSED, 2, -1,
24619 +      {
24620 +       &avr32_ifield_table[AVR32_IFIELD_RY],
24621 +       &avr32_ifield_table[AVR32_IFIELD_K16],
24622 +      },
24623 +    },
24624 +    {
24625 +      AVR32_OPC_STM_PU, 4, 0xebc00000, 0xfff00000,
24626 +      &avr32_syntax_table[AVR32_SYNTAX_STM_PU],
24627 +      BFD_RELOC_UNUSED, 2, -1,
24628 +      {
24629 +       &avr32_ifield_table[AVR32_IFIELD_RY],
24630 +       &avr32_ifield_table[AVR32_IFIELD_K16],
24631 +      },
24632 +    },
24633 +    {
24634 +      AVR32_OPC_STMTS, 4, 0xedc00000, 0xfff00000,
24635 +      &avr32_syntax_table[AVR32_SYNTAX_STMTS],
24636 +      BFD_RELOC_UNUSED, 2, -1,
24637 +      {
24638 +       &avr32_ifield_table[AVR32_IFIELD_RY],
24639 +       &avr32_ifield_table[AVR32_IFIELD_K16],
24640 +      },
24641 +    },
24642 +    {
24643 +      AVR32_OPC_STMTS_PU, 4, 0xefc00000, 0xfff00000,
24644 +      &avr32_syntax_table[AVR32_SYNTAX_STMTS_PU],
24645 +      BFD_RELOC_UNUSED, 2, -1,
24646 +      {
24647 +       &avr32_ifield_table[AVR32_IFIELD_RY],
24648 +       &avr32_ifield_table[AVR32_IFIELD_K16],
24649 +      },
24650 +    },
24651 +    {
24652 +      AVR32_OPC_STSWP_H, 4, 0xe1d09000, 0xe1f0f000,
24653 +      &avr32_syntax_table[AVR32_SYNTAX_STSWP_H],
24654 +      BFD_RELOC_UNUSED, 3, -1,
24655 +      {
24656 +       &avr32_ifield_table[AVR32_IFIELD_RX],
24657 +       &avr32_ifield_table[AVR32_IFIELD_K12],
24658 +       &avr32_ifield_table[AVR32_IFIELD_RY],
24659 +      },
24660 +    },
24661 +    {
24662 +      AVR32_OPC_STSWP_W, 4, 0xe1d0a000, 0xe1f0f000,
24663 +      &avr32_syntax_table[AVR32_SYNTAX_STSWP_W],
24664 +      BFD_RELOC_UNUSED, 3, -1,
24665 +      {
24666 +       &avr32_ifield_table[AVR32_IFIELD_RX],
24667 +       &avr32_ifield_table[AVR32_IFIELD_K12],
24668 +       &avr32_ifield_table[AVR32_IFIELD_RY],
24669 +      },
24670 +    },
24671 +    {
24672 +      AVR32_OPC_SUB1, 2, 0x00100000, 0xe1f00000,
24673 +      &avr32_syntax_table[AVR32_SYNTAX_SUB1],
24674 +      BFD_RELOC_UNUSED, 2, -1,
24675 +      {
24676 +       &avr32_ifield_table[AVR32_IFIELD_RY],
24677 +       &avr32_ifield_table[AVR32_IFIELD_RX],
24678 +      },
24679 +    },
24680 +    {
24681 +      AVR32_OPC_SUB2, 4, 0xe0000100, 0xe1f0ffc0,
24682 +      &avr32_syntax_table[AVR32_SYNTAX_SUB2],
24683 +      BFD_RELOC_UNUSED, 4, -1,
24684 +      {
24685 +       &avr32_ifield_table[AVR32_IFIELD_RD_E],
24686 +       &avr32_ifield_table[AVR32_IFIELD_RX],
24687 +       &avr32_ifield_table[AVR32_IFIELD_RY],
24688 +       &avr32_ifield_table[AVR32_IFIELD_K2],
24689 +      },
24690 +    },
24691 +    {
24692 +      AVR32_OPC_SUB5, 4, 0xe0c00000, 0xe1f00000,
24693 +      &avr32_syntax_table[AVR32_SYNTAX_SUB5],
24694 +      BFD_RELOC_AVR32_SUB5, 3, 2,
24695 +      {
24696 +       &avr32_ifield_table[AVR32_IFIELD_RY],
24697 +       &avr32_ifield_table[AVR32_IFIELD_RX],
24698 +       &avr32_ifield_table[AVR32_IFIELD_K16],
24699 +      },
24700 +    },
24701 +    {
24702 +      AVR32_OPC_SUB3_SP, 2, 0x200d0000, 0xf00f0000,
24703 +      &avr32_syntax_table[AVR32_SYNTAX_SUB3_SP],
24704 +      BFD_RELOC_AVR32_10SW, 2, 1,
24705 +      {
24706 +       &avr32_ifield_table[AVR32_IFIELD_RY],
24707 +       &avr32_ifield_table[AVR32_IFIELD_K8C],
24708 +      },
24709 +    },
24710 +    {
24711 +      AVR32_OPC_SUB3, 2, 0x20000000, 0xf0000000,
24712 +      &avr32_syntax_table[AVR32_SYNTAX_SUB3],
24713 +      BFD_RELOC_AVR32_8S, 2, 1,
24714 +      {
24715 +       &avr32_ifield_table[AVR32_IFIELD_RY],
24716 +       &avr32_ifield_table[AVR32_IFIELD_K8C],
24717 +      },
24718 +    },
24719 +    {
24720 +      AVR32_OPC_SUB4, 4, 0xe0200000, 0xe1e00000,
24721 +      &avr32_syntax_table[AVR32_SYNTAX_SUB4],
24722 +      BFD_RELOC_AVR32_21S, 2, 1,
24723 +      {
24724 +       &avr32_ifield_table[AVR32_IFIELD_RY],
24725 +       &avr32_ifield_table[AVR32_IFIELD_K21],
24726 +      },
24727 +    },
24728 +    {
24729 +      AVR32_OPC_SUBEQ, 4, 0xf7b00000, 0xfff0ff00,
24730 +      &avr32_syntax_table[AVR32_SYNTAX_SUBEQ],
24731 +      BFD_RELOC_AVR32_8S_EXT, 2, 1,
24732 +      {
24733 +       &avr32_ifield_table[AVR32_IFIELD_RY],
24734 +       &avr32_ifield_table[AVR32_IFIELD_K8E],
24735 +      },
24736 +    },
24737 +    {
24738 +      AVR32_OPC_SUBNE, 4, 0xf7b00100, 0xfff0ff00,
24739 +      &avr32_syntax_table[AVR32_SYNTAX_SUBNE],
24740 +      BFD_RELOC_AVR32_8S_EXT, 2, 1,
24741 +      {
24742 +       &avr32_ifield_table[AVR32_IFIELD_RY],
24743 +       &avr32_ifield_table[AVR32_IFIELD_K8E],
24744 +      },
24745 +    },
24746 +    {
24747 +      AVR32_OPC_SUBCC, 4, 0xf7b00200, 0xfff0ff00,
24748 +      &avr32_syntax_table[AVR32_SYNTAX_SUBHS],
24749 +      BFD_RELOC_AVR32_8S_EXT, 2, 1,
24750 +      {
24751 +       &avr32_ifield_table[AVR32_IFIELD_RY],
24752 +       &avr32_ifield_table[AVR32_IFIELD_K8E],
24753 +      },
24754 +    },
24755 +    {
24756 +      AVR32_OPC_SUBCS, 4, 0xf7b00300, 0xfff0ff00,
24757 +      &avr32_syntax_table[AVR32_SYNTAX_SUBLO],
24758 +      BFD_RELOC_AVR32_8S_EXT, 2, 1,
24759 +      {
24760 +       &avr32_ifield_table[AVR32_IFIELD_RY],
24761 +       &avr32_ifield_table[AVR32_IFIELD_K8E],
24762 +      },
24763 +    },
24764 +    {
24765 +      AVR32_OPC_SUBGE, 4, 0xf7b00400, 0xfff0ff00,
24766 +      &avr32_syntax_table[AVR32_SYNTAX_SUBGE],
24767 +      BFD_RELOC_AVR32_8S_EXT, 2, 1,
24768 +      {
24769 +       &avr32_ifield_table[AVR32_IFIELD_RY],
24770 +       &avr32_ifield_table[AVR32_IFIELD_K8E],
24771 +      },
24772 +    },
24773 +    {
24774 +      AVR32_OPC_SUBLT, 4, 0xf7b00500, 0xfff0ff00,
24775 +      &avr32_syntax_table[AVR32_SYNTAX_SUBLT],
24776 +      BFD_RELOC_AVR32_8S_EXT, 2, 1,
24777 +      {
24778 +       &avr32_ifield_table[AVR32_IFIELD_RY],
24779 +       &avr32_ifield_table[AVR32_IFIELD_K8E],
24780 +      },
24781 +    },
24782 +    {
24783 +      AVR32_OPC_SUBMI, 4, 0xf7b00600, 0xfff0ff00,
24784 +      &avr32_syntax_table[AVR32_SYNTAX_SUBMI],
24785 +      BFD_RELOC_AVR32_8S_EXT, 2, 1,
24786 +      {
24787 +       &avr32_ifield_table[AVR32_IFIELD_RY],
24788 +       &avr32_ifield_table[AVR32_IFIELD_K8E],
24789 +      },
24790 +    },
24791 +    {
24792 +      AVR32_OPC_SUBPL, 4, 0xf7b00700, 0xfff0ff00,
24793 +      &avr32_syntax_table[AVR32_SYNTAX_SUBPL],
24794 +      BFD_RELOC_AVR32_8S_EXT, 2, 1,
24795 +      {
24796 +       &avr32_ifield_table[AVR32_IFIELD_RY],
24797 +       &avr32_ifield_table[AVR32_IFIELD_K8E],
24798 +      },
24799 +    },
24800 +    {
24801 +      AVR32_OPC_SUBLS, 4, 0xf7b00800, 0xfff0ff00,
24802 +      &avr32_syntax_table[AVR32_SYNTAX_SUBLS],
24803 +      BFD_RELOC_AVR32_8S_EXT, 2, 1,
24804 +      {
24805 +       &avr32_ifield_table[AVR32_IFIELD_RY],
24806 +       &avr32_ifield_table[AVR32_IFIELD_K8E],
24807 +      },
24808 +    },
24809 +    {
24810 +      AVR32_OPC_SUBGT, 4, 0xf7b00900, 0xfff0ff00,
24811 +      &avr32_syntax_table[AVR32_SYNTAX_SUBGT],
24812 +      BFD_RELOC_AVR32_8S_EXT, 2, 1,
24813 +      {
24814 +       &avr32_ifield_table[AVR32_IFIELD_RY],
24815 +       &avr32_ifield_table[AVR32_IFIELD_K8E],
24816 +      },
24817 +    },
24818 +    {
24819 +      AVR32_OPC_SUBLE, 4, 0xf7b00a00, 0xfff0ff00,
24820 +      &avr32_syntax_table[AVR32_SYNTAX_SUBLE],
24821 +      BFD_RELOC_AVR32_8S_EXT, 2, 1,
24822 +      {
24823 +       &avr32_ifield_table[AVR32_IFIELD_RY],
24824 +       &avr32_ifield_table[AVR32_IFIELD_K8E],
24825 +      },
24826 +    },
24827 +    {
24828 +      AVR32_OPC_SUBHI, 4, 0xf7b00b00, 0xfff0ff00,
24829 +      &avr32_syntax_table[AVR32_SYNTAX_SUBHI],
24830 +      BFD_RELOC_AVR32_8S_EXT, 2, 1,
24831 +      {
24832 +       &avr32_ifield_table[AVR32_IFIELD_RY],
24833 +       &avr32_ifield_table[AVR32_IFIELD_K8E],
24834 +      },
24835 +    },
24836 +    {
24837 +      AVR32_OPC_SUBVS, 4, 0xf7b00c00, 0xfff0ff00,
24838 +      &avr32_syntax_table[AVR32_SYNTAX_SUBVS],
24839 +      BFD_RELOC_AVR32_8S_EXT, 2, 1,
24840 +      {
24841 +       &avr32_ifield_table[AVR32_IFIELD_RY],
24842 +       &avr32_ifield_table[AVR32_IFIELD_K8E],
24843 +      },
24844 +    },
24845 +    {
24846 +      AVR32_OPC_SUBVC, 4, 0xf7b00d00, 0xfff0ff00,
24847 +      &avr32_syntax_table[AVR32_SYNTAX_SUBVC],
24848 +      BFD_RELOC_AVR32_8S_EXT, 2, 1,
24849 +      {
24850 +       &avr32_ifield_table[AVR32_IFIELD_RY],
24851 +       &avr32_ifield_table[AVR32_IFIELD_K8E],
24852 +      },
24853 +    },
24854 +    {
24855 +      AVR32_OPC_SUBQS, 4, 0xf7b00e00, 0xfff0ff00,
24856 +      &avr32_syntax_table[AVR32_SYNTAX_SUBQS],
24857 +      BFD_RELOC_AVR32_8S_EXT, 2, 1,
24858 +      {
24859 +       &avr32_ifield_table[AVR32_IFIELD_RY],
24860 +       &avr32_ifield_table[AVR32_IFIELD_K8E],
24861 +      },
24862 +    },
24863 +    {
24864 +      AVR32_OPC_SUBAL, 4, 0xf7b00f00, 0xfff0ff00,
24865 +      &avr32_syntax_table[AVR32_SYNTAX_SUBAL],
24866 +      BFD_RELOC_AVR32_8S_EXT, 2, 1,
24867 +      {
24868 +       &avr32_ifield_table[AVR32_IFIELD_RY],
24869 +       &avr32_ifield_table[AVR32_IFIELD_K8E],
24870 +      },
24871 +    },
24872 +    {
24873 +      AVR32_OPC_SUBFEQ, 4, 0xf5b00000, 0xfff0ff00,
24874 +      &avr32_syntax_table[AVR32_SYNTAX_SUBFEQ],
24875 +      BFD_RELOC_AVR32_8S_EXT, 2, 1,
24876 +      {
24877 +       &avr32_ifield_table[AVR32_IFIELD_RY],
24878 +       &avr32_ifield_table[AVR32_IFIELD_K8E],
24879 +      },
24880 +    },
24881 +    {
24882 +      AVR32_OPC_SUBFNE, 4, 0xf5b00100, 0xfff0ff00,
24883 +      &avr32_syntax_table[AVR32_SYNTAX_SUBFNE],
24884 +      BFD_RELOC_AVR32_8S_EXT, 2, 1,
24885 +      {
24886 +       &avr32_ifield_table[AVR32_IFIELD_RY],
24887 +       &avr32_ifield_table[AVR32_IFIELD_K8E],
24888 +      },
24889 +    },
24890 +    {
24891 +      AVR32_OPC_SUBFCC, 4, 0xf5b00200, 0xfff0ff00,
24892 +      &avr32_syntax_table[AVR32_SYNTAX_SUBFHS],
24893 +      BFD_RELOC_AVR32_8S_EXT, 2, 1,
24894 +      {
24895 +       &avr32_ifield_table[AVR32_IFIELD_RY],
24896 +       &avr32_ifield_table[AVR32_IFIELD_K8E],
24897 +      },
24898 +    },
24899 +    {
24900 +      AVR32_OPC_SUBFCS, 4, 0xf5b00300, 0xfff0ff00,
24901 +      &avr32_syntax_table[AVR32_SYNTAX_SUBFLO],
24902 +      BFD_RELOC_AVR32_8S_EXT, 2, 1,
24903 +      {
24904 +       &avr32_ifield_table[AVR32_IFIELD_RY],
24905 +       &avr32_ifield_table[AVR32_IFIELD_K8E],
24906 +      },
24907 +    },
24908 +    {
24909 +      AVR32_OPC_SUBFGE, 4, 0xf5b00400, 0xfff0ff00,
24910 +      &avr32_syntax_table[AVR32_SYNTAX_SUBFGE],
24911 +      BFD_RELOC_AVR32_8S_EXT, 2, 1,
24912 +      {
24913 +       &avr32_ifield_table[AVR32_IFIELD_RY],
24914 +       &avr32_ifield_table[AVR32_IFIELD_K8E],
24915 +      },
24916 +    },
24917 +    {
24918 +      AVR32_OPC_SUBFLT, 4, 0xf5b00500, 0xfff0ff00,
24919 +      &avr32_syntax_table[AVR32_SYNTAX_SUBFLT],
24920 +      BFD_RELOC_AVR32_8S_EXT, 2, 1,
24921 +      {
24922 +       &avr32_ifield_table[AVR32_IFIELD_RY],
24923 +       &avr32_ifield_table[AVR32_IFIELD_K8E],
24924 +      },
24925 +    },
24926 +    {
24927 +      AVR32_OPC_SUBFMI, 4, 0xf5b00600, 0xfff0ff00,
24928 +      &avr32_syntax_table[AVR32_SYNTAX_SUBFMI],
24929 +      BFD_RELOC_AVR32_8S_EXT, 2, 1,
24930 +      {
24931 +       &avr32_ifield_table[AVR32_IFIELD_RY],
24932 +       &avr32_ifield_table[AVR32_IFIELD_K8E],
24933 +      },
24934 +    },
24935 +    {
24936 +      AVR32_OPC_SUBFPL, 4, 0xf5b00700, 0xfff0ff00,
24937 +      &avr32_syntax_table[AVR32_SYNTAX_SUBFPL],
24938 +      BFD_RELOC_AVR32_8S_EXT, 2, 1,
24939 +      {
24940 +       &avr32_ifield_table[AVR32_IFIELD_RY],
24941 +       &avr32_ifield_table[AVR32_IFIELD_K8E],
24942 +      },
24943 +    },
24944 +    {
24945 +      AVR32_OPC_SUBFLS, 4, 0xf5b00800, 0xfff0ff00,
24946 +      &avr32_syntax_table[AVR32_SYNTAX_SUBFLS],
24947 +      BFD_RELOC_AVR32_8S_EXT, 2, 1,
24948 +      {
24949 +       &avr32_ifield_table[AVR32_IFIELD_RY],
24950 +       &avr32_ifield_table[AVR32_IFIELD_K8E],
24951 +      },
24952 +    },
24953 +    {
24954 +      AVR32_OPC_SUBFGT, 4, 0xf5b00900, 0xfff0ff00,
24955 +      &avr32_syntax_table[AVR32_SYNTAX_SUBFGT],
24956 +      BFD_RELOC_AVR32_8S_EXT, 2, 1,
24957 +      {
24958 +       &avr32_ifield_table[AVR32_IFIELD_RY],
24959 +       &avr32_ifield_table[AVR32_IFIELD_K8E],
24960 +      },
24961 +    },
24962 +    {
24963 +      AVR32_OPC_SUBFLE, 4, 0xf5b00a00, 0xfff0ff00,
24964 +      &avr32_syntax_table[AVR32_SYNTAX_SUBFLE],
24965 +      BFD_RELOC_AVR32_8S_EXT, 2, 1,
24966 +      {
24967 +       &avr32_ifield_table[AVR32_IFIELD_RY],
24968 +       &avr32_ifield_table[AVR32_IFIELD_K8E],
24969 +      },
24970 +    },
24971 +    {
24972 +      AVR32_OPC_SUBFHI, 4, 0xf5b00b00, 0xfff0ff00,
24973 +      &avr32_syntax_table[AVR32_SYNTAX_SUBFHI],
24974 +      BFD_RELOC_AVR32_8S_EXT, 2, 1,
24975 +      {
24976 +       &avr32_ifield_table[AVR32_IFIELD_RY],
24977 +       &avr32_ifield_table[AVR32_IFIELD_K8E],
24978 +      },
24979 +    },
24980 +    {
24981 +      AVR32_OPC_SUBFVS, 4, 0xf5b00c00, 0xfff0ff00,
24982 +      &avr32_syntax_table[AVR32_SYNTAX_SUBFVS],
24983 +      BFD_RELOC_AVR32_8S_EXT, 2, 1,
24984 +      {
24985 +       &avr32_ifield_table[AVR32_IFIELD_RY],
24986 +       &avr32_ifield_table[AVR32_IFIELD_K8E],
24987 +      },
24988 +    },
24989 +    {
24990 +      AVR32_OPC_SUBFVC, 4, 0xf5b00d00, 0xfff0ff00,
24991 +      &avr32_syntax_table[AVR32_SYNTAX_SUBFVC],
24992 +      BFD_RELOC_AVR32_8S_EXT, 2, 1,
24993 +      {
24994 +       &avr32_ifield_table[AVR32_IFIELD_RY],
24995 +       &avr32_ifield_table[AVR32_IFIELD_K8E],
24996 +      },
24997 +    },
24998 +    {
24999 +      AVR32_OPC_SUBFQS, 4, 0xf5b00e00, 0xfff0ff00,
25000 +      &avr32_syntax_table[AVR32_SYNTAX_SUBFQS],
25001 +      BFD_RELOC_AVR32_8S_EXT, 2, 1,
25002 +      {
25003 +       &avr32_ifield_table[AVR32_IFIELD_RY],
25004 +       &avr32_ifield_table[AVR32_IFIELD_K8E],
25005 +      },
25006 +    },
25007 +    {
25008 +      AVR32_OPC_SUBFAL, 4, 0xf5b00f00, 0xfff0ff00,
25009 +      &avr32_syntax_table[AVR32_SYNTAX_SUBFAL],
25010 +      BFD_RELOC_AVR32_8S_EXT, 2, 1,
25011 +      {
25012 +       &avr32_ifield_table[AVR32_IFIELD_RY],
25013 +       &avr32_ifield_table[AVR32_IFIELD_K8E],
25014 +      },
25015 +    },
25016 +    {
25017 +      AVR32_OPC_SUBHH_W, 4, 0xe0000f00, 0xe1f0ffc0,
25018 +      &avr32_syntax_table[AVR32_SYNTAX_SUBHH_W],
25019 +      BFD_RELOC_UNUSED, 5, -1,
25020 +      {
25021 +       &avr32_ifield_table[AVR32_IFIELD_RD_E],
25022 +       &avr32_ifield_table[AVR32_IFIELD_RX],
25023 +       &avr32_ifield_table[AVR32_IFIELD_X],
25024 +       &avr32_ifield_table[AVR32_IFIELD_RY],
25025 +       &avr32_ifield_table[AVR32_IFIELD_Y],
25026 +      },
25027 +    },
25028 +    {
25029 +      AVR32_OPC_SWAP_B, 2, 0x5cb00000, 0xfff00000,
25030 +      &avr32_syntax_table[AVR32_SYNTAX_SWAP_B],
25031 +      BFD_RELOC_UNUSED, 1, -1,
25032 +      {
25033 +       &avr32_ifield_table[AVR32_IFIELD_RY],
25034 +      }
25035 +    },
25036 +    {
25037 +      AVR32_OPC_SWAP_BH, 2, 0x5cc00000, 0xfff00000,
25038 +      &avr32_syntax_table[AVR32_SYNTAX_SWAP_BH],
25039 +      BFD_RELOC_UNUSED, 1, -1,
25040 +      {
25041 +       &avr32_ifield_table[AVR32_IFIELD_RY],
25042 +      }
25043 +    },
25044 +    {
25045 +      AVR32_OPC_SWAP_H, 2, 0x5ca00000, 0xfff00000,
25046 +      &avr32_syntax_table[AVR32_SYNTAX_SWAP_H],
25047 +      BFD_RELOC_UNUSED, 1, -1,
25048 +      {
25049 +       &avr32_ifield_table[AVR32_IFIELD_RY],
25050 +      }
25051 +    },
25052 +    {
25053 +      AVR32_OPC_SYNC, 4, 0xebb00000, 0xffffff00,
25054 +      &avr32_syntax_table[AVR32_SYNTAX_SYNC],
25055 +      BFD_RELOC_AVR32_8S_EXT, 1, 0,
25056 +      {
25057 +       &avr32_ifield_table[AVR32_IFIELD_K8E],
25058 +      }
25059 +    },
25060 +    {
25061 +      AVR32_OPC_TLBR, 2, 0xd6430000, 0xffff0000,
25062 +      &avr32_syntax_table[AVR32_SYNTAX_TLBR],
25063 +      BFD_RELOC_UNUSED, 0, -1, { NULL },
25064 +    },
25065 +    {
25066 +      AVR32_OPC_TLBS, 2, 0xd6530000, 0xffff0000,
25067 +      &avr32_syntax_table[AVR32_SYNTAX_TLBS],
25068 +      BFD_RELOC_UNUSED, 0, -1, { NULL },
25069 +    },
25070 +    {
25071 +      AVR32_OPC_TLBW, 2, 0xd6630000, 0xffff0000,
25072 +      &avr32_syntax_table[AVR32_SYNTAX_TLBW],
25073 +      BFD_RELOC_UNUSED, 0, -1, { NULL },
25074 +    },
25075 +    {
25076 +      AVR32_OPC_TNBZ, 2, 0x5ce00000, 0xfff00000,
25077 +      &avr32_syntax_table[AVR32_SYNTAX_TNBZ],
25078 +      BFD_RELOC_UNUSED, 1, -1,
25079 +      {
25080 +       &avr32_ifield_table[AVR32_IFIELD_RY],
25081 +      }
25082 +    },
25083 +    {
25084 +      AVR32_OPC_TST, 2, 0x00700000, 0xe1f00000,
25085 +      &avr32_syntax_table[AVR32_SYNTAX_TST],
25086 +      BFD_RELOC_UNUSED, 2, -1,
25087 +      {
25088 +       &avr32_ifield_table[AVR32_IFIELD_RY],
25089 +       &avr32_ifield_table[AVR32_IFIELD_RX],
25090 +      },
25091 +    },
25092 +    {
25093 +      AVR32_OPC_XCHG, 4, 0xe0000b40, 0xe1f0fff0,
25094 +      &avr32_syntax_table[AVR32_SYNTAX_XCHG],
25095 +      BFD_RELOC_UNUSED, 3, -1,
25096 +      {
25097 +       &avr32_ifield_table[AVR32_IFIELD_RD_E],
25098 +       &avr32_ifield_table[AVR32_IFIELD_RX],
25099 +       &avr32_ifield_table[AVR32_IFIELD_RY],
25100 +      },
25101 +    },
25102 +    {
25103 +      AVR32_OPC_MEMC, 4, 0xf6100000, 0xfff00000,
25104 +      &avr32_syntax_table[AVR32_SYNTAX_MEMC],
25105 +      BFD_RELOC_AVR32_15S, 2, 0,
25106 +      {
25107 +       &avr32_ifield_table[AVR32_IFIELD_MEM15],
25108 +       &avr32_ifield_table[AVR32_IFIELD_MEMB5],
25109 +      },
25110 +    },
25111 +    {
25112 +      AVR32_OPC_MEMS, 4, 0xf8100000, 0xfff00000,
25113 +      &avr32_syntax_table[AVR32_SYNTAX_MEMS],
25114 +      BFD_RELOC_AVR32_15S, 2, 0,
25115 +      {
25116 +       &avr32_ifield_table[AVR32_IFIELD_MEM15],
25117 +       &avr32_ifield_table[AVR32_IFIELD_MEMB5],
25118 +      },
25119 +    },
25120 +    {
25121 +      AVR32_OPC_MEMT, 4, 0xfa100000, 0xfff00000,
25122 +      &avr32_syntax_table[AVR32_SYNTAX_MEMT],
25123 +      BFD_RELOC_AVR32_15S, 2, 0,
25124 +      {
25125 +       &avr32_ifield_table[AVR32_IFIELD_MEM15],
25126 +       &avr32_ifield_table[AVR32_IFIELD_MEMB5],
25127 +      },
25128 +    },
25129 +    {
25130 +      AVR32_OPC_BFEXTS, 4, 0xe1d0b000, 0xe1f0fc00,
25131 +      &avr32_syntax_table[AVR32_SYNTAX_BFEXTS],
25132 +      BFD_RELOC_UNUSED, 4, -1,
25133 +      {
25134 +       &avr32_ifield_table[AVR32_IFIELD_RX],
25135 +       &avr32_ifield_table[AVR32_IFIELD_RY],
25136 +       &avr32_ifield_table[AVR32_IFIELD_S5],
25137 +       &avr32_ifield_table[AVR32_IFIELD_K5E],
25138 +      },
25139 +    },
25140 +    {
25141 +      AVR32_OPC_BFEXTU, 4, 0xe1d0c000, 0xe1f0fc00,
25142 +      &avr32_syntax_table[AVR32_SYNTAX_BFEXTU],
25143 +      BFD_RELOC_UNUSED, 4, -1,
25144 +      {
25145 +       &avr32_ifield_table[AVR32_IFIELD_RX],
25146 +       &avr32_ifield_table[AVR32_IFIELD_RY],
25147 +       &avr32_ifield_table[AVR32_IFIELD_S5],
25148 +       &avr32_ifield_table[AVR32_IFIELD_K5E],
25149 +      },
25150 +    },
25151 +    {
25152 +      AVR32_OPC_BFINS, 4, 0xe1d0d000, 0xe1f0fc00,
25153 +      &avr32_syntax_table[AVR32_SYNTAX_BFINS],
25154 +      BFD_RELOC_UNUSED, 4, -1,
25155 +      {
25156 +       &avr32_ifield_table[AVR32_IFIELD_RX],
25157 +       &avr32_ifield_table[AVR32_IFIELD_RY],
25158 +       &avr32_ifield_table[AVR32_IFIELD_S5],
25159 +       &avr32_ifield_table[AVR32_IFIELD_K5E],
25160 +      },
25161 +    },
25162 +#define AVR32_OPCODE_RSUBCOND(cond_name, cond_field)                    \
25163 +    {                                                                   \
25164 +      AVR32_OPC_RSUB ## cond_name , 4,                                  \
25165 +      0xfbb00000 | (cond_field << 8), 0xfff0ff00,                       \
25166 +      &avr32_syntax_table[AVR32_SYNTAX_RSUB ## cond_name ],             \
25167 +      BFD_RELOC_AVR32_8S_EXT, 2, 1,                                     \
25168 +      {                                                                 \
25169 +       &avr32_ifield_table[AVR32_IFIELD_RY],                           \
25170 +       &avr32_ifield_table[AVR32_IFIELD_K8E],                          \
25171 +      },                                                                \
25172 +    },
25173 +
25174 +    AVR32_OPCODE_RSUBCOND (EQ, 0)
25175 +    AVR32_OPCODE_RSUBCOND (NE, 1)
25176 +    AVR32_OPCODE_RSUBCOND (CC, 2)
25177 +    AVR32_OPCODE_RSUBCOND (CS, 3)
25178 +    AVR32_OPCODE_RSUBCOND (GE, 4)
25179 +    AVR32_OPCODE_RSUBCOND (LT, 5)
25180 +    AVR32_OPCODE_RSUBCOND (MI, 6)
25181 +    AVR32_OPCODE_RSUBCOND (PL, 7)
25182 +    AVR32_OPCODE_RSUBCOND (LS, 8)
25183 +    AVR32_OPCODE_RSUBCOND (GT, 9)
25184 +    AVR32_OPCODE_RSUBCOND (LE, 10)
25185 +    AVR32_OPCODE_RSUBCOND (HI, 11)
25186 +    AVR32_OPCODE_RSUBCOND (VS, 12)
25187 +    AVR32_OPCODE_RSUBCOND (VC, 13)
25188 +    AVR32_OPCODE_RSUBCOND (QS, 14)
25189 +    AVR32_OPCODE_RSUBCOND (AL, 15)
25190 +
25191 +#define AVR32_OPCODE_OP3_COND(op_name, op_field, cond_name, cond_field) \
25192 +    {                                                                   \
25193 +      AVR32_OPC_ ## op_name ## cond_name , 4,                           \
25194 +      0xe1d0e000 | (cond_field << 8) | (op_field << 4), 0xe1f0fff0,     \
25195 +      &avr32_syntax_table[AVR32_SYNTAX_ ## op_name ## cond_name ],      \
25196 +      BFD_RELOC_UNUSED, 3, -1,                                          \
25197 +      {                                                                 \
25198 +       &avr32_ifield_table[AVR32_IFIELD_RD_E],                         \
25199 +       &avr32_ifield_table[AVR32_IFIELD_RX],                           \
25200 +       &avr32_ifield_table[AVR32_IFIELD_RY],                           \
25201 +      },                                                                \
25202 +    },
25203 +
25204 +    AVR32_OPCODE_OP3_COND (ADD, 0, EQ, 0)
25205 +    AVR32_OPCODE_OP3_COND (ADD, 0, NE, 1)
25206 +    AVR32_OPCODE_OP3_COND (ADD, 0, CC, 2)
25207 +    AVR32_OPCODE_OP3_COND (ADD, 0, CS, 3)
25208 +    AVR32_OPCODE_OP3_COND (ADD, 0, GE, 4)
25209 +    AVR32_OPCODE_OP3_COND (ADD, 0, LT, 5)
25210 +    AVR32_OPCODE_OP3_COND (ADD, 0, MI, 6)
25211 +    AVR32_OPCODE_OP3_COND (ADD, 0, PL, 7)
25212 +    AVR32_OPCODE_OP3_COND (ADD, 0, LS, 8)
25213 +    AVR32_OPCODE_OP3_COND (ADD, 0, GT, 9)
25214 +    AVR32_OPCODE_OP3_COND (ADD, 0, LE, 10)
25215 +    AVR32_OPCODE_OP3_COND (ADD, 0, HI, 11)
25216 +    AVR32_OPCODE_OP3_COND (ADD, 0, VS, 12)
25217 +    AVR32_OPCODE_OP3_COND (ADD, 0, VC, 13)
25218 +    AVR32_OPCODE_OP3_COND (ADD, 0, QS, 14)
25219 +    AVR32_OPCODE_OP3_COND (ADD, 0, AL, 15)
25220 +
25221 +    AVR32_OPCODE_OP3_COND (SUB2, 1, EQ, 0)
25222 +    AVR32_OPCODE_OP3_COND (SUB2, 1, NE, 1)
25223 +    AVR32_OPCODE_OP3_COND (SUB2, 1, CC, 2)
25224 +    AVR32_OPCODE_OP3_COND (SUB2, 1, CS, 3)
25225 +    AVR32_OPCODE_OP3_COND (SUB2, 1, GE, 4)
25226 +    AVR32_OPCODE_OP3_COND (SUB2, 1, LT, 5)
25227 +    AVR32_OPCODE_OP3_COND (SUB2, 1, MI, 6)
25228 +    AVR32_OPCODE_OP3_COND (SUB2, 1, PL, 7)
25229 +    AVR32_OPCODE_OP3_COND (SUB2, 1, LS, 8)
25230 +    AVR32_OPCODE_OP3_COND (SUB2, 1, GT, 9)
25231 +    AVR32_OPCODE_OP3_COND (SUB2, 1, LE, 10)
25232 +    AVR32_OPCODE_OP3_COND (SUB2, 1, HI, 11)
25233 +    AVR32_OPCODE_OP3_COND (SUB2, 1, VS, 12)
25234 +    AVR32_OPCODE_OP3_COND (SUB2, 1, VC, 13)
25235 +    AVR32_OPCODE_OP3_COND (SUB2, 1, QS, 14)
25236 +    AVR32_OPCODE_OP3_COND (SUB2, 1, AL, 15)
25237 +
25238 +    AVR32_OPCODE_OP3_COND (AND, 2, EQ, 0)
25239 +    AVR32_OPCODE_OP3_COND (AND, 2, NE, 1)
25240 +    AVR32_OPCODE_OP3_COND (AND, 2, CC, 2)
25241 +    AVR32_OPCODE_OP3_COND (AND, 2, CS, 3)
25242 +    AVR32_OPCODE_OP3_COND (AND, 2, GE, 4)
25243 +    AVR32_OPCODE_OP3_COND (AND, 2, LT, 5)
25244 +    AVR32_OPCODE_OP3_COND (AND, 2, MI, 6)
25245 +    AVR32_OPCODE_OP3_COND (AND, 2, PL, 7)
25246 +    AVR32_OPCODE_OP3_COND (AND, 2, LS, 8)
25247 +    AVR32_OPCODE_OP3_COND (AND, 2, GT, 9)
25248 +    AVR32_OPCODE_OP3_COND (AND, 2, LE, 10)
25249 +    AVR32_OPCODE_OP3_COND (AND, 2, HI, 11)
25250 +    AVR32_OPCODE_OP3_COND (AND, 2, VS, 12)
25251 +    AVR32_OPCODE_OP3_COND (AND, 2, VC, 13)
25252 +    AVR32_OPCODE_OP3_COND (AND, 2, QS, 14)
25253 +    AVR32_OPCODE_OP3_COND (AND, 2, AL, 15)
25254 +
25255 +    AVR32_OPCODE_OP3_COND (OR, 3, EQ, 0)
25256 +    AVR32_OPCODE_OP3_COND (OR, 3, NE, 1)
25257 +    AVR32_OPCODE_OP3_COND (OR, 3, CC, 2)
25258 +    AVR32_OPCODE_OP3_COND (OR, 3, CS, 3)
25259 +    AVR32_OPCODE_OP3_COND (OR, 3, GE, 4)
25260 +    AVR32_OPCODE_OP3_COND (OR, 3, LT, 5)
25261 +    AVR32_OPCODE_OP3_COND (OR, 3, MI, 6)
25262 +    AVR32_OPCODE_OP3_COND (OR, 3, PL, 7)
25263 +    AVR32_OPCODE_OP3_COND (OR, 3, LS, 8)
25264 +    AVR32_OPCODE_OP3_COND (OR, 3, GT, 9)
25265 +    AVR32_OPCODE_OP3_COND (OR, 3, LE, 10)
25266 +    AVR32_OPCODE_OP3_COND (OR, 3, HI, 11)
25267 +    AVR32_OPCODE_OP3_COND (OR, 3, VS, 12)
25268 +    AVR32_OPCODE_OP3_COND (OR, 3, VC, 13)
25269 +    AVR32_OPCODE_OP3_COND (OR, 3, QS, 14)
25270 +    AVR32_OPCODE_OP3_COND (OR, 3, AL, 15)
25271 +
25272 +    AVR32_OPCODE_OP3_COND (EOR, 4, EQ, 0)
25273 +    AVR32_OPCODE_OP3_COND (EOR, 4, NE, 1)
25274 +    AVR32_OPCODE_OP3_COND (EOR, 4, CC, 2)
25275 +    AVR32_OPCODE_OP3_COND (EOR, 4, CS, 3)
25276 +    AVR32_OPCODE_OP3_COND (EOR, 4, GE, 4)
25277 +    AVR32_OPCODE_OP3_COND (EOR, 4, LT, 5)
25278 +    AVR32_OPCODE_OP3_COND (EOR, 4, MI, 6)
25279 +    AVR32_OPCODE_OP3_COND (EOR, 4, PL, 7)
25280 +    AVR32_OPCODE_OP3_COND (EOR, 4, LS, 8)
25281 +    AVR32_OPCODE_OP3_COND (EOR, 4, GT, 9)
25282 +    AVR32_OPCODE_OP3_COND (EOR, 4, LE, 10)
25283 +    AVR32_OPCODE_OP3_COND (EOR, 4, HI, 11)
25284 +    AVR32_OPCODE_OP3_COND (EOR, 4, VS, 12)
25285 +    AVR32_OPCODE_OP3_COND (EOR, 4, VC, 13)
25286 +    AVR32_OPCODE_OP3_COND (EOR, 4, QS, 14)
25287 +    AVR32_OPCODE_OP3_COND (EOR, 4, AL, 15)
25288 +
25289 +#define AVR32_OPCODE_LD_COND(op_name, op_field, cond_name, cond_field)  \
25290 +    {                                                                   \
25291 +      AVR32_OPC_ ## op_name ## cond_name , 4,                           \
25292 +      0xe1f00000 | (cond_field << 12) | (op_field  << 9), 0xe1f0fe00,   \
25293 +      &avr32_syntax_table[AVR32_SYNTAX_ ## op_name ## cond_name ],      \
25294 +      BFD_RELOC_UNUSED, 3, -1,                                          \
25295 +      {                                                                 \
25296 +       &avr32_ifield_table[AVR32_IFIELD_RY],                           \
25297 +       &avr32_ifield_table[AVR32_IFIELD_RX],                           \
25298 +       &avr32_ifield_table[AVR32_IFIELD_K9E],                          \
25299 +      },                                                                \
25300 +    },
25301 +
25302 +#define AVR32_OPCODE_ST_COND(op_name, op_field, cond_name, cond_field)  \
25303 +    {                                                                   \
25304 +      AVR32_OPC_ ## op_name ## cond_name , 4,                           \
25305 +      0xe1f00000 | (cond_field << 12) | (op_field  << 9), 0xe1f0fe00,   \
25306 +      &avr32_syntax_table[AVR32_SYNTAX_ ## op_name ## cond_name ],      \
25307 +      BFD_RELOC_UNUSED, 3, -1,                                          \
25308 +      {                                                                 \
25309 +       &avr32_ifield_table[AVR32_IFIELD_RX],                           \
25310 +       &avr32_ifield_table[AVR32_IFIELD_K9E],                          \
25311 +       &avr32_ifield_table[AVR32_IFIELD_RY],                           \
25312 +      },                                                                \
25313 +    },
25314 +
25315 +    AVR32_OPCODE_LD_COND (LD_W, 0, EQ, 0)
25316 +    AVR32_OPCODE_LD_COND (LD_W, 0, NE, 1)
25317 +    AVR32_OPCODE_LD_COND (LD_W, 0, CC, 2)
25318 +    AVR32_OPCODE_LD_COND (LD_W, 0, CS, 3)
25319 +    AVR32_OPCODE_LD_COND (LD_W, 0, GE, 4)
25320 +    AVR32_OPCODE_LD_COND (LD_W, 0, LT, 5)
25321 +    AVR32_OPCODE_LD_COND (LD_W, 0, MI, 6)
25322 +    AVR32_OPCODE_LD_COND (LD_W, 0, PL, 7)
25323 +    AVR32_OPCODE_LD_COND (LD_W, 0, LS, 8)
25324 +    AVR32_OPCODE_LD_COND (LD_W, 0, GT, 9)
25325 +    AVR32_OPCODE_LD_COND (LD_W, 0, LE, 10)
25326 +    AVR32_OPCODE_LD_COND (LD_W, 0, HI, 11)
25327 +    AVR32_OPCODE_LD_COND (LD_W, 0, VS, 12)
25328 +    AVR32_OPCODE_LD_COND (LD_W, 0, VC, 13)
25329 +    AVR32_OPCODE_LD_COND (LD_W, 0, QS, 14)
25330 +    AVR32_OPCODE_LD_COND (LD_W, 0, AL, 15)
25331 +
25332 +    AVR32_OPCODE_LD_COND (LD_SH, 1, EQ, 0)
25333 +    AVR32_OPCODE_LD_COND (LD_SH, 1, NE, 1)
25334 +    AVR32_OPCODE_LD_COND (LD_SH, 1, CC, 2)
25335 +    AVR32_OPCODE_LD_COND (LD_SH, 1, CS, 3)
25336 +    AVR32_OPCODE_LD_COND (LD_SH, 1, GE, 4)
25337 +    AVR32_OPCODE_LD_COND (LD_SH, 1, LT, 5)
25338 +    AVR32_OPCODE_LD_COND (LD_SH, 1, MI, 6)
25339 +    AVR32_OPCODE_LD_COND (LD_SH, 1, PL, 7)
25340 +    AVR32_OPCODE_LD_COND (LD_SH, 1, LS, 8)
25341 +    AVR32_OPCODE_LD_COND (LD_SH, 1, GT, 9)
25342 +    AVR32_OPCODE_LD_COND (LD_SH, 1, LE, 10)
25343 +    AVR32_OPCODE_LD_COND (LD_SH, 1, HI, 11)
25344 +    AVR32_OPCODE_LD_COND (LD_SH, 1, VS, 12)
25345 +    AVR32_OPCODE_LD_COND (LD_SH, 1, VC, 13)
25346 +    AVR32_OPCODE_LD_COND (LD_SH, 1, QS, 14)
25347 +    AVR32_OPCODE_LD_COND (LD_SH, 1, AL, 15)
25348 +
25349 +    AVR32_OPCODE_LD_COND (LD_UH, 2, EQ, 0)
25350 +    AVR32_OPCODE_LD_COND (LD_UH, 2, NE, 1)
25351 +    AVR32_OPCODE_LD_COND (LD_UH, 2, CC, 2)
25352 +    AVR32_OPCODE_LD_COND (LD_UH, 2, CS, 3)
25353 +    AVR32_OPCODE_LD_COND (LD_UH, 2, GE, 4)
25354 +    AVR32_OPCODE_LD_COND (LD_UH, 2, LT, 5)
25355 +    AVR32_OPCODE_LD_COND (LD_UH, 2, MI, 6)
25356 +    AVR32_OPCODE_LD_COND (LD_UH, 2, PL, 7)
25357 +    AVR32_OPCODE_LD_COND (LD_SH, 2, LS, 8)
25358 +    AVR32_OPCODE_LD_COND (LD_SH, 2, GT, 9)
25359 +    AVR32_OPCODE_LD_COND (LD_SH, 2, LE, 10)
25360 +    AVR32_OPCODE_LD_COND (LD_SH, 2, HI, 11)
25361 +    AVR32_OPCODE_LD_COND (LD_SH, 2, VS, 12)
25362 +    AVR32_OPCODE_LD_COND (LD_SH, 2, VC, 13)
25363 +    AVR32_OPCODE_LD_COND (LD_SH, 2, QS, 14)
25364 +    AVR32_OPCODE_LD_COND (LD_SH, 2, AL, 15)
25365 +
25366 +    AVR32_OPCODE_LD_COND (LD_SB, 3, EQ, 0)
25367 +    AVR32_OPCODE_LD_COND (LD_SB, 3, NE, 1)
25368 +    AVR32_OPCODE_LD_COND (LD_SB, 3, CC, 2)
25369 +    AVR32_OPCODE_LD_COND (LD_SB, 3, CS, 3)
25370 +    AVR32_OPCODE_LD_COND (LD_SB, 3, GE, 4)
25371 +    AVR32_OPCODE_LD_COND (LD_SB, 3, LT, 5)
25372 +    AVR32_OPCODE_LD_COND (LD_SB, 3, MI, 6)
25373 +    AVR32_OPCODE_LD_COND (LD_SB, 3, PL, 7)
25374 +    AVR32_OPCODE_LD_COND (LD_SB, 3, LS, 8)
25375 +    AVR32_OPCODE_LD_COND (LD_SB, 3, GT, 9)
25376 +    AVR32_OPCODE_LD_COND (LD_SB, 3, LE, 10)
25377 +    AVR32_OPCODE_LD_COND (LD_SB, 3, HI, 11)
25378 +    AVR32_OPCODE_LD_COND (LD_SB, 3, VS, 12)
25379 +    AVR32_OPCODE_LD_COND (LD_SB, 3, VC, 13)
25380 +    AVR32_OPCODE_LD_COND (LD_SB, 3, QS, 14)
25381 +    AVR32_OPCODE_LD_COND (LD_SB, 3, AL, 15)
25382 +
25383 +    AVR32_OPCODE_LD_COND (LD_UB, 4, EQ, 0)
25384 +    AVR32_OPCODE_LD_COND (LD_UB, 4, NE, 1)
25385 +    AVR32_OPCODE_LD_COND (LD_UB, 4, CC, 2)
25386 +    AVR32_OPCODE_LD_COND (LD_UB, 4, CS, 3)
25387 +    AVR32_OPCODE_LD_COND (LD_UB, 4, GE, 4)
25388 +    AVR32_OPCODE_LD_COND (LD_UB, 4, LT, 5)
25389 +    AVR32_OPCODE_LD_COND (LD_UB, 4, MI, 6)
25390 +    AVR32_OPCODE_LD_COND (LD_UB, 4, PL, 7)
25391 +    AVR32_OPCODE_LD_COND (LD_UB, 4, LS, 8)
25392 +    AVR32_OPCODE_LD_COND (LD_UB, 4, GT, 9)
25393 +    AVR32_OPCODE_LD_COND (LD_UB, 4, LE, 10)
25394 +    AVR32_OPCODE_LD_COND (LD_UB, 4, HI, 11)
25395 +    AVR32_OPCODE_LD_COND (LD_UB, 4, VS, 12)
25396 +    AVR32_OPCODE_LD_COND (LD_UB, 4, VC, 13)
25397 +    AVR32_OPCODE_LD_COND (LD_UB, 4, QS, 14)
25398 +    AVR32_OPCODE_LD_COND (LD_UB, 4, AL, 15)
25399 +
25400 +    AVR32_OPCODE_ST_COND (ST_W, 5, EQ, 0)
25401 +    AVR32_OPCODE_ST_COND (ST_W, 5, NE, 1)
25402 +    AVR32_OPCODE_ST_COND (ST_W, 5, CC, 2)
25403 +    AVR32_OPCODE_ST_COND (ST_W, 5, CS, 3)
25404 +    AVR32_OPCODE_ST_COND (ST_W, 5, GE, 4)
25405 +    AVR32_OPCODE_ST_COND (ST_W, 5, LT, 5)
25406 +    AVR32_OPCODE_ST_COND (ST_W, 5, MI, 6)
25407 +    AVR32_OPCODE_ST_COND (ST_W, 5, PL, 7)
25408 +    AVR32_OPCODE_ST_COND (ST_W, 5, LS, 8)
25409 +    AVR32_OPCODE_ST_COND (ST_W, 5, GT, 9)
25410 +    AVR32_OPCODE_ST_COND (ST_W, 5, LE, 10)
25411 +    AVR32_OPCODE_ST_COND (ST_W, 5, HI, 11)
25412 +    AVR32_OPCODE_ST_COND (ST_W, 5, VS, 12)
25413 +    AVR32_OPCODE_ST_COND (ST_W, 5, VC, 13)
25414 +    AVR32_OPCODE_ST_COND (ST_W, 5, QS, 14)
25415 +    AVR32_OPCODE_ST_COND (ST_W, 5, AL, 15)
25416 +
25417 +    AVR32_OPCODE_ST_COND (ST_H, 6, EQ, 0)
25418 +    AVR32_OPCODE_ST_COND (ST_H, 6, NE, 1)
25419 +    AVR32_OPCODE_ST_COND (ST_H, 6, CC, 2)
25420 +    AVR32_OPCODE_ST_COND (ST_H, 6, CS, 3)
25421 +    AVR32_OPCODE_ST_COND (ST_H, 6, GE, 4)
25422 +    AVR32_OPCODE_ST_COND (ST_H, 6, LT, 5)
25423 +    AVR32_OPCODE_ST_COND (ST_H, 6, MI, 6)
25424 +    AVR32_OPCODE_ST_COND (ST_H, 6, PL, 7)
25425 +    AVR32_OPCODE_ST_COND (ST_H, 6, LS, 8)
25426 +    AVR32_OPCODE_ST_COND (ST_H, 6, GT, 9)
25427 +    AVR32_OPCODE_ST_COND (ST_H, 6, LE, 10)
25428 +    AVR32_OPCODE_ST_COND (ST_H, 6, HI, 11)
25429 +    AVR32_OPCODE_ST_COND (ST_H, 6, VS, 12)
25430 +    AVR32_OPCODE_ST_COND (ST_H, 6, VC, 13)
25431 +    AVR32_OPCODE_ST_COND (ST_H, 6, QS, 14)
25432 +    AVR32_OPCODE_ST_COND (ST_H, 6, AL, 15)
25433 +
25434 +    AVR32_OPCODE_ST_COND (ST_B, 7, EQ, 0)
25435 +    AVR32_OPCODE_ST_COND (ST_B, 7, NE, 1)
25436 +    AVR32_OPCODE_ST_COND (ST_B, 7, CC, 2)
25437 +    AVR32_OPCODE_ST_COND (ST_B, 7, CS, 3)
25438 +    AVR32_OPCODE_ST_COND (ST_B, 7, GE, 4)
25439 +    AVR32_OPCODE_ST_COND (ST_B, 7, LT, 5)
25440 +    AVR32_OPCODE_ST_COND (ST_B, 7, MI, 6)
25441 +    AVR32_OPCODE_ST_COND (ST_B, 7, PL, 7)
25442 +    AVR32_OPCODE_ST_COND (ST_B, 7, LS, 8)
25443 +    AVR32_OPCODE_ST_COND (ST_B, 7, GT, 9)
25444 +    AVR32_OPCODE_ST_COND (ST_B, 7, LE, 10)
25445 +    AVR32_OPCODE_ST_COND (ST_B, 7, HI, 11)
25446 +    AVR32_OPCODE_ST_COND (ST_B, 7, VS, 12)
25447 +    AVR32_OPCODE_ST_COND (ST_B, 7, VC, 13)
25448 +    AVR32_OPCODE_ST_COND (ST_B, 7, QS, 14)
25449 +    AVR32_OPCODE_ST_COND (ST_B, 7, AL, 15)
25450 +
25451 +    {
25452 +      AVR32_OPC_MOVH, 4, 0xfc100000, 0xfff00000,
25453 +      &avr32_syntax_table[AVR32_SYNTAX_MOVH],
25454 +      BFD_RELOC_AVR32_16U,  2, 1,
25455 +      {
25456 +       &avr32_ifield_table[AVR32_IFIELD_RY],
25457 +       &avr32_ifield_table[AVR32_IFIELD_K16],
25458 +      },
25459 +    },
25460 +    {
25461 +      AVR32_OPC_SSCALL, 2, 0xd7530000, 0xffff0000,
25462 +      &avr32_syntax_table[AVR32_SYNTAX_SSCALL],
25463 +      BFD_RELOC_UNUSED, 0, -1, { NULL },
25464 +    },
25465 +    {
25466 +      AVR32_OPC_RETSS, 2, 0xd7630000, 0xffff0000,
25467 +      &avr32_syntax_table[AVR32_SYNTAX_RETSS],
25468 +      BFD_RELOC_UNUSED, 0, -1, { NULL },
25469 +    },
25470 +
25471 +  {
25472 +    AVR32_OPC_FMAC_S, 4, 0xE1A00000, 0xFFF0F000,
25473 +    &avr32_syntax_table[AVR32_SYNTAX_FMAC_S],
25474 +    BFD_RELOC_UNUSED, 4, -1,
25475 +    {
25476 +      &avr32_ifield_table[AVR32_IFIELD_FP_RD],
25477 +      &avr32_ifield_table[AVR32_IFIELD_FP_RA],
25478 +      &avr32_ifield_table[AVR32_IFIELD_FP_RX],
25479 +      &avr32_ifield_table[AVR32_IFIELD_FP_RY]
25480 +    }
25481 +  },
25482 +  {
25483 +    AVR32_OPC_FNMAC_S, 4, 0xE1A01000, 0xFFF0F000,
25484 +    &avr32_syntax_table[AVR32_SYNTAX_FNMAC_S],
25485 +    BFD_RELOC_UNUSED, 4, -1,
25486 +    {
25487 +      &avr32_ifield_table[AVR32_IFIELD_FP_RD],
25488 +      &avr32_ifield_table[AVR32_IFIELD_FP_RA],
25489 +      &avr32_ifield_table[AVR32_IFIELD_FP_RX],
25490 +      &avr32_ifield_table[AVR32_IFIELD_FP_RY]
25491 +    }
25492 +  },
25493 +  {
25494 +    AVR32_OPC_FMSC_S, 4, 0xE3A00000, 0xFFF0F000,
25495 +    &avr32_syntax_table[AVR32_SYNTAX_FMSC_S],
25496 +    BFD_RELOC_UNUSED, 4, -1,
25497 +    {
25498 +      &avr32_ifield_table[AVR32_IFIELD_FP_RD],
25499 +      &avr32_ifield_table[AVR32_IFIELD_FP_RA],
25500 +      &avr32_ifield_table[AVR32_IFIELD_FP_RX],
25501 +      &avr32_ifield_table[AVR32_IFIELD_FP_RY]
25502 +    }
25503 +  },
25504 +  {
25505 +    AVR32_OPC_FNMSC_S, 4, 0xE3A01000, 0xFFF0F000,
25506 +    &avr32_syntax_table[AVR32_SYNTAX_FNMSC_S],
25507 +    BFD_RELOC_UNUSED, 4, -1,
25508 +    {
25509 +      &avr32_ifield_table[AVR32_IFIELD_FP_RD],
25510 +      &avr32_ifield_table[AVR32_IFIELD_FP_RA],
25511 +      &avr32_ifield_table[AVR32_IFIELD_FP_RX],
25512 +      &avr32_ifield_table[AVR32_IFIELD_FP_RY]
25513 +    }
25514 +  },
25515 +  {
25516 +    AVR32_OPC_FMUL_S, 4, 0xE5A20000, 0xFFFFF000,
25517 +    &avr32_syntax_table[AVR32_SYNTAX_FMUL_S],
25518 +    BFD_RELOC_UNUSED, 3, -1,
25519 +    {
25520 +      &avr32_ifield_table[AVR32_IFIELD_FP_RD],
25521 +      &avr32_ifield_table[AVR32_IFIELD_FP_RX],
25522 +      &avr32_ifield_table[AVR32_IFIELD_FP_RY]
25523 +    }
25524 +  },
25525 +  {
25526 +    AVR32_OPC_FNMUL_S, 4, 0xE5A30000, 0xFFFFF000,
25527 +    &avr32_syntax_table[AVR32_SYNTAX_FNMUL_S],
25528 +    BFD_RELOC_UNUSED, 3, -1,
25529 +    {
25530 +      &avr32_ifield_table[AVR32_IFIELD_FP_RD],
25531 +      &avr32_ifield_table[AVR32_IFIELD_FP_RX],
25532 +      &avr32_ifield_table[AVR32_IFIELD_FP_RY]
25533 +    }
25534 +  },
25535 +  {
25536 +    AVR32_OPC_FADD_S, 4, 0xE5A00000, 0xFFFFF000,
25537 +    &avr32_syntax_table[AVR32_SYNTAX_FADD_S],
25538 +    BFD_RELOC_UNUSED, 3, -1,
25539 +    {
25540 +      &avr32_ifield_table[AVR32_IFIELD_FP_RD],
25541 +      &avr32_ifield_table[AVR32_IFIELD_FP_RX],
25542 +      &avr32_ifield_table[AVR32_IFIELD_FP_RY]
25543 +    }
25544 +  },
25545 +  {
25546 +    AVR32_OPC_FSUB_S, 4, 0xE5A10000, 0xFFFFF000,
25547 +    &avr32_syntax_table[AVR32_SYNTAX_FSUB_S],
25548 +    BFD_RELOC_UNUSED, 3, -1,
25549 +    {
25550 +      &avr32_ifield_table[AVR32_IFIELD_FP_RD],
25551 +      &avr32_ifield_table[AVR32_IFIELD_FP_RX],
25552 +      &avr32_ifield_table[AVR32_IFIELD_FP_RY]
25553 +    }
25554 +  },
25555 +  {
25556 +    AVR32_OPC_FCASTRS_SW, 4, 0xE5AB0000, 0xFFFFF0F0,
25557 +    &avr32_syntax_table[AVR32_SYNTAX_FCASTRS_SW],
25558 +    BFD_RELOC_UNUSED, 2, -1,
25559 +    {
25560 +      &avr32_ifield_table[AVR32_IFIELD_FP_RD],
25561 +      &avr32_ifield_table[AVR32_IFIELD_FP_RY]
25562 +    }
25563 +  },
25564 +  {
25565 +    AVR32_OPC_FCASTRS_UW, 4, 0xE5A90000, 0xFFFFF0F0,
25566 +    &avr32_syntax_table[AVR32_SYNTAX_FCASTRS_UW],
25567 +    BFD_RELOC_UNUSED, 2, -1,
25568 +    {
25569 +      &avr32_ifield_table[AVR32_IFIELD_FP_RD],
25570 +      &avr32_ifield_table[AVR32_IFIELD_FP_RY]
25571 +    }
25572 +  },
25573 +  {
25574 +    AVR32_OPC_FCASTSW_S, 4, 0xE5A60000, 0xFFFFF0F0,
25575 +    &avr32_syntax_table[AVR32_SYNTAX_FCASTSW_S],
25576 +    BFD_RELOC_UNUSED, 2, -1,
25577 +    {
25578 +      &avr32_ifield_table[AVR32_IFIELD_FP_RD],
25579 +      &avr32_ifield_table[AVR32_IFIELD_FP_RY]
25580 +    }
25581 +  },
25582 +  {
25583 +    AVR32_OPC_FCASTUW_S, 4, 0xE5A40000, 0xFFFFF0F0,
25584 +    &avr32_syntax_table[AVR32_SYNTAX_FCASTUW_S],
25585 +    BFD_RELOC_UNUSED, 2, -1,
25586 +    {
25587 +      &avr32_ifield_table[AVR32_IFIELD_FP_RD],
25588 +      &avr32_ifield_table[AVR32_IFIELD_FP_RY]
25589 +    }
25590 +  },
25591 +  {
25592 +    AVR32_OPC_FCMP_S, 4, 0xE5AC0000, 0xFFFFFF00,
25593 +    &avr32_syntax_table[AVR32_SYNTAX_FCMP_S],
25594 +    BFD_RELOC_UNUSED, 2, -1,
25595 +    {
25596 +      &avr32_ifield_table[AVR32_IFIELD_FP_RX],
25597 +      &avr32_ifield_table[AVR32_IFIELD_FP_RY]
25598 +    }
25599 +  },
25600 +  {
25601 +    AVR32_OPC_FCHK_S, 4, 0xE5AD0000, 0xFFFFFFF0,
25602 +    &avr32_syntax_table[AVR32_SYNTAX_FCHK_S],
25603 +    BFD_RELOC_UNUSED, 1, -1,
25604 +    {
25605 +      &avr32_ifield_table[AVR32_IFIELD_FP_RY]
25606 +    }
25607 +  },
25608 +  {
25609 +    AVR32_OPC_FRCPA_S, 4, 0xE5AE0000, 0xFFFFF0F0,
25610 +    &avr32_syntax_table[AVR32_SYNTAX_FRCPA_S],
25611 +    BFD_RELOC_UNUSED, 2, -1,
25612 +    {
25613 +      &avr32_ifield_table[AVR32_IFIELD_FP_RD],
25614 +      &avr32_ifield_table[AVR32_IFIELD_FP_RY]
25615 +    }
25616 +  },
25617 +  {
25618 +    AVR32_OPC_FRSQRTA_S, 4, 0xE5AF0000, 0xFFFFF0F0,
25619 +    &avr32_syntax_table[AVR32_SYNTAX_FRSQRTA_S],
25620 +    BFD_RELOC_UNUSED, 2, -1,
25621 +    {
25622 +      &avr32_ifield_table[AVR32_IFIELD_FP_RD],
25623 +      &avr32_ifield_table[AVR32_IFIELD_FP_RY]
25624 +    }
25625 +  }
25626 +
25627 +};
25628 +
25629 +
25630 +const struct avr32_alias avr32_alias_table[] =
25631 +  {
25632 +    {
25633 +      AVR32_ALIAS_PICOSVMAC0,
25634 +      &avr32_opc_table[AVR32_OPC_COP],
25635 +      {
25636 +       { 0, PICO_CPNO },
25637 +       { 1, 0 }, { 1, 1 }, { 1, 2 },
25638 +       { 0, 0x0c },
25639 +      },
25640 +    },
25641 +    {
25642 +      AVR32_ALIAS_PICOSVMAC1,
25643 +      &avr32_opc_table[AVR32_OPC_COP],
25644 +      {
25645 +       { 0, PICO_CPNO },
25646 +       { 1, 0 }, { 1, 1 }, { 1, 2 },
25647 +       { 0, 0x0d },
25648 +      },
25649 +    },
25650 +    {
25651 +      AVR32_ALIAS_PICOSVMAC2,
25652 +      &avr32_opc_table[AVR32_OPC_COP],
25653 +      {
25654 +       { 0, PICO_CPNO },
25655 +       { 1, 0 }, { 1, 1 }, { 1, 2 },
25656 +       { 0, 0x0e },
25657 +      },
25658 +    },
25659 +    {
25660 +      AVR32_ALIAS_PICOSVMAC3,
25661 +      &avr32_opc_table[AVR32_OPC_COP],
25662 +      {
25663 +       { 0, PICO_CPNO },
25664 +       { 1, 0 }, { 1, 1 }, { 1, 2 },
25665 +       { 0, 0x0f },
25666 +      },
25667 +    },
25668 +    {
25669 +      AVR32_ALIAS_PICOSVMUL0,
25670 +      &avr32_opc_table[AVR32_OPC_COP],
25671 +      {
25672 +       { 0, PICO_CPNO },
25673 +       { 1, 0 }, { 1, 1 }, { 1, 2 },
25674 +       { 0, 0x08 },
25675 +      },
25676 +    },
25677 +    {
25678 +      AVR32_ALIAS_PICOSVMUL1,
25679 +      &avr32_opc_table[AVR32_OPC_COP],
25680 +      {
25681 +       { 0, PICO_CPNO },
25682 +       { 1, 0 }, { 1, 1 }, { 1, 2 },
25683 +       { 0, 0x09 },
25684 +      },
25685 +    },
25686 +    {
25687 +      AVR32_ALIAS_PICOSVMUL2,
25688 +      &avr32_opc_table[AVR32_OPC_COP],
25689 +      {
25690 +       { 0, PICO_CPNO },
25691 +       { 1, 0 }, { 1, 1 }, { 1, 2 },
25692 +       { 0, 0x0a },
25693 +      },
25694 +    },
25695 +    {
25696 +      AVR32_ALIAS_PICOSVMUL3,
25697 +      &avr32_opc_table[AVR32_OPC_COP],
25698 +      {
25699 +       { 0, PICO_CPNO },
25700 +       { 1, 0 }, { 1, 1 }, { 1, 2 },
25701 +       { 0, 0x0b },
25702 +      },
25703 +    },
25704 +    {
25705 +      AVR32_ALIAS_PICOVMAC0,
25706 +      &avr32_opc_table[AVR32_OPC_COP],
25707 +      {
25708 +       { 0, PICO_CPNO },
25709 +       { 1, 0 }, { 1, 1 }, { 1, 2 },
25710 +       { 0, 0x04 },
25711 +      },
25712 +    },
25713 +    {
25714 +      AVR32_ALIAS_PICOVMAC1,
25715 +      &avr32_opc_table[AVR32_OPC_COP],
25716 +      {
25717 +       { 0, PICO_CPNO },
25718 +       { 1, 0 }, { 1, 1 }, { 1, 2 },
25719 +       { 0, 0x05 },
25720 +      },
25721 +    },
25722 +    {
25723 +      AVR32_ALIAS_PICOVMAC2,
25724 +      &avr32_opc_table[AVR32_OPC_COP],
25725 +      {
25726 +       { 0, PICO_CPNO },
25727 +       { 1, 0 }, { 1, 1 }, { 1, 2 },
25728 +       { 0, 0x06 },
25729 +      },
25730 +    },
25731 +    {
25732 +      AVR32_ALIAS_PICOVMAC3,
25733 +      &avr32_opc_table[AVR32_OPC_COP],
25734 +      {
25735 +       { 0, PICO_CPNO },
25736 +       { 1, 0 }, { 1, 1 }, { 1, 2 },
25737 +       { 0, 0x07 },
25738 +      },
25739 +    },
25740 +    {
25741 +      AVR32_ALIAS_PICOVMUL0,
25742 +      &avr32_opc_table[AVR32_OPC_COP],
25743 +      {
25744 +       { 0, PICO_CPNO },
25745 +       { 1, 0 }, { 1, 1 }, { 1, 2 },
25746 +       { 0, 0x00 },
25747 +      },
25748 +    },
25749 +    {
25750 +      AVR32_ALIAS_PICOVMUL1,
25751 +      &avr32_opc_table[AVR32_OPC_COP],
25752 +      {
25753 +       { 0, PICO_CPNO },
25754 +       { 1, 0 }, { 1, 1 }, { 1, 2 },
25755 +       { 0, 0x01 },
25756 +      },
25757 +    },
25758 +    {
25759 +      AVR32_ALIAS_PICOVMUL2,
25760 +      &avr32_opc_table[AVR32_OPC_COP],
25761 +      {
25762 +       { 0, PICO_CPNO },
25763 +       { 1, 0 }, { 1, 1 }, { 1, 2 },
25764 +       { 0, 0x02 },
25765 +      },
25766 +    },
25767 +    {
25768 +      AVR32_ALIAS_PICOVMUL3,
25769 +      &avr32_opc_table[AVR32_OPC_COP],
25770 +      {
25771 +       { 0, PICO_CPNO },
25772 +       { 1, 0 }, { 1, 1 }, { 1, 2 },
25773 +       { 0, 0x03 },
25774 +      },
25775 +    },
25776 +    {
25777 +      AVR32_ALIAS_PICOLD_D1,
25778 +      &avr32_opc_table[AVR32_OPC_LDC_D1],
25779 +      {
25780 +       { 0, PICO_CPNO },
25781 +       { 1, 0 }, { 1, 1 },
25782 +      },
25783 +    },
25784 +    {
25785 +      AVR32_ALIAS_PICOLD_D2,
25786 +      &avr32_opc_table[AVR32_OPC_LDC_D2],
25787 +      {
25788 +       { 0, PICO_CPNO },
25789 +       { 1, 0 }, { 1, 1 },
25790 +      },
25791 +    },
25792 +    {
25793 +      AVR32_ALIAS_PICOLD_D3,
25794 +      &avr32_opc_table[AVR32_OPC_LDC_D3],
25795 +      {
25796 +       { 0, PICO_CPNO },
25797 +       { 1, 0 }, { 1, 1 }, { 1, 2 }, { 1, 3 },
25798 +      },
25799 +    },
25800 +    {
25801 +      AVR32_ALIAS_PICOLD_W1,
25802 +      &avr32_opc_table[AVR32_OPC_LDC_W1],
25803 +      {
25804 +       { 0, PICO_CPNO },
25805 +       { 1, 0 }, { 1, 1 },
25806 +      },
25807 +    },
25808 +    {
25809 +      AVR32_ALIAS_PICOLD_W2,
25810 +      &avr32_opc_table[AVR32_OPC_LDC_W2],
25811 +      {
25812 +       { 0, PICO_CPNO },
25813 +       { 1, 0 }, { 1, 1 },
25814 +      },
25815 +    },
25816 +    {
25817 +      AVR32_ALIAS_PICOLD_W3,
25818 +      &avr32_opc_table[AVR32_OPC_LDC_W3],
25819 +      {
25820 +       { 0, PICO_CPNO },
25821 +       { 1, 0 }, { 1, 1 }, { 1, 2 }, { 1, 3 },
25822 +      },
25823 +    },
25824 +    {
25825 +      AVR32_ALIAS_PICOLDM_D,
25826 +      &avr32_opc_table[AVR32_OPC_LDCM_D],
25827 +      {
25828 +       { 0, PICO_CPNO },
25829 +       { 1, 0 }, { 1, 1 },
25830 +      },
25831 +    },
25832 +    {
25833 +      AVR32_ALIAS_PICOLDM_D_PU,
25834 +      &avr32_opc_table[AVR32_OPC_LDCM_D_PU],
25835 +      {
25836 +       { 0, PICO_CPNO },
25837 +       { 1, 0 }, { 1, 1 },
25838 +      },
25839 +    },
25840 +    {
25841 +      AVR32_ALIAS_PICOLDM_W,
25842 +      &avr32_opc_table[AVR32_OPC_LDCM_W],
25843 +      {
25844 +       { 0, PICO_CPNO },
25845 +       { 1, 0 }, { 1, 1 }, { 1, 2 },
25846 +      },
25847 +    },
25848 +    {
25849 +      AVR32_ALIAS_PICOLDM_W_PU,
25850 +      &avr32_opc_table[AVR32_OPC_LDCM_W_PU],
25851 +      {
25852 +       { 0, PICO_CPNO },
25853 +       { 1, 0 }, { 1, 1 }, { 1, 2 },
25854 +      },
25855 +    },
25856 +    {
25857 +      AVR32_ALIAS_PICOMV_D1,
25858 +      &avr32_opc_table[AVR32_OPC_MVCR_D],
25859 +      {
25860 +       { 0, PICO_CPNO },
25861 +       { 1, 0 }, { 1, 1 },
25862 +      },
25863 +    },
25864 +    {
25865 +      AVR32_ALIAS_PICOMV_D2,
25866 +      &avr32_opc_table[AVR32_OPC_MVRC_D],
25867 +      {
25868 +       { 0, PICO_CPNO },
25869 +       { 1, 0 }, { 1, 1 },
25870 +      },
25871 +    },
25872 +    {
25873 +      AVR32_ALIAS_PICOMV_W1,
25874 +      &avr32_opc_table[AVR32_OPC_MVCR_W],
25875 +      {
25876 +       { 0, PICO_CPNO },
25877 +       { 1, 0 }, { 1, 1 },
25878 +      },
25879 +    },
25880 +    {
25881 +      AVR32_ALIAS_PICOMV_W2,
25882 +      &avr32_opc_table[AVR32_OPC_MVRC_W],
25883 +      {
25884 +       { 0, PICO_CPNO },
25885 +       { 1, 0 }, { 1, 1 },
25886 +      },
25887 +    },
25888 +    {
25889 +      AVR32_ALIAS_PICOST_D1,
25890 +      &avr32_opc_table[AVR32_OPC_STC_D1],
25891 +      {
25892 +       { 0, PICO_CPNO },
25893 +       { 1, 0 }, { 1, 1 }, { 1, 2 },
25894 +      },
25895 +    },
25896 +    {
25897 +      AVR32_ALIAS_PICOST_D2,
25898 +      &avr32_opc_table[AVR32_OPC_STC_D2],
25899 +      {
25900 +       { 0, PICO_CPNO },
25901 +       { 1, 0 }, { 1, 1 },
25902 +      },
25903 +    },
25904 +    {
25905 +      AVR32_ALIAS_PICOST_D3,
25906 +      &avr32_opc_table[AVR32_OPC_STC_D3],
25907 +      {
25908 +       { 0, PICO_CPNO },
25909 +       { 1, 0 }, { 1, 1 }, { 1, 2 }, { 1, 3 },
25910 +      },
25911 +    },
25912 +    {
25913 +      AVR32_ALIAS_PICOST_W1,
25914 +      &avr32_opc_table[AVR32_OPC_STC_W1],
25915 +      {
25916 +       { 0, PICO_CPNO },
25917 +       { 1, 0 }, { 1, 1 }, { 1, 2 },
25918 +      },
25919 +    },
25920 +    {
25921 +      AVR32_ALIAS_PICOST_W2,
25922 +      &avr32_opc_table[AVR32_OPC_STC_W2],
25923 +      {
25924 +       { 0, PICO_CPNO },
25925 +       { 1, 0 }, { 1, 1 },
25926 +      },
25927 +    },
25928 +    {
25929 +      AVR32_ALIAS_PICOST_W3,
25930 +      &avr32_opc_table[AVR32_OPC_STC_W3],
25931 +      {
25932 +       { 0, PICO_CPNO },
25933 +       { 1, 0 }, { 1, 1 }, { 1, 2 }, { 1, 3 },
25934 +      },
25935 +    },
25936 +    {
25937 +      AVR32_ALIAS_PICOSTM_D,
25938 +      &avr32_opc_table[AVR32_OPC_STCM_D],
25939 +      {
25940 +       { 0, PICO_CPNO },
25941 +       { 1, 0 }, { 1, 1 },
25942 +      },
25943 +    },
25944 +    {
25945 +      AVR32_ALIAS_PICOSTM_D_PU,
25946 +      &avr32_opc_table[AVR32_OPC_STCM_D_PU],
25947 +      {
25948 +       { 0, PICO_CPNO },
25949 +       { 1, 0 }, { 1, 1 },
25950 +      },
25951 +    },
25952 +    {
25953 +      AVR32_ALIAS_PICOSTM_W,
25954 +      &avr32_opc_table[AVR32_OPC_STCM_W],
25955 +      {
25956 +       { 0, PICO_CPNO },
25957 +       { 1, 0 }, { 1, 1 }, { 1, 2 },
25958 +      },
25959 +    },
25960 +    {
25961 +      AVR32_ALIAS_PICOSTM_W_PU,
25962 +      &avr32_opc_table[AVR32_OPC_STCM_W_PU],
25963 +      {
25964 +       { 0, PICO_CPNO },
25965 +       { 1, 0 }, { 1, 1 }, { 1, 2 },
25966 +      },
25967 +    },
25968 +  };
25969 +
25970 +
25971 +#define SYNTAX_NORMAL0(id, mne, opc, arch)                     \
25972 +  {                                                    \
25973 +    AVR32_SYNTAX_##id, arch,                   \
25974 +    &avr32_mnemonic_table[AVR32_MNEMONIC_##mne],       \
25975 +    AVR32_PARSER_NORMAL,                                       \
25976 +    { &avr32_opc_table[AVR32_OPC_##opc], },            \
25977 +    NULL, 0, { }                                       \
25978 +  }
25979 +#define SYNTAX_NORMAL1(id, mne, opc, op0, arch)                \
25980 +  {                                                    \
25981 +    AVR32_SYNTAX_##id, arch,                   \
25982 +    &avr32_mnemonic_table[AVR32_MNEMONIC_##mne],       \
25983 +    AVR32_PARSER_NORMAL,                                       \
25984 +    { &avr32_opc_table[AVR32_OPC_##opc], },            \
25985 +    NULL, 1,                                           \
25986 +    {                                                  \
25987 +      AVR32_OPERAND_##op0,                             \
25988 +    }                                                  \
25989 +  }
25990 +#define SYNTAX_NORMALM1(id, mne, opc, op0, arch)               \
25991 +  {                                                    \
25992 +    AVR32_SYNTAX_##id, arch,                   \
25993 +    &avr32_mnemonic_table[AVR32_MNEMONIC_##mne],       \
25994 +    AVR32_PARSER_NORMAL,                                       \
25995 +    { &avr32_opc_table[AVR32_OPC_##opc], },                    \
25996 +    NULL, -1,                                          \
25997 +    {                                                  \
25998 +      AVR32_OPERAND_##op0,                             \
25999 +    }                                                  \
26000 +  }
26001 +#define SYNTAX_NORMAL2(id, mne, opc, op0, op1, arch)           \
26002 +  {                                                    \
26003 +    AVR32_SYNTAX_##id, arch,                   \
26004 +    &avr32_mnemonic_table[AVR32_MNEMONIC_##mne],       \
26005 +    AVR32_PARSER_NORMAL,                                       \
26006 +    { &avr32_opc_table[AVR32_OPC_##opc], },                    \
26007 +    NULL, 2,                                           \
26008 +    {                                                  \
26009 +      AVR32_OPERAND_##op0, AVR32_OPERAND_##op1,                \
26010 +    }                                                  \
26011 +  }
26012 +#define SYNTAX_NORMALM2(id, mne, opc, op0, op1, arch)          \
26013 +  {                                                    \
26014 +    AVR32_SYNTAX_##id, arch,                   \
26015 +    &avr32_mnemonic_table[AVR32_MNEMONIC_##mne],       \
26016 +    AVR32_PARSER_NORMAL,                                       \
26017 +    { &avr32_opc_table[AVR32_OPC_##opc], },                    \
26018 +    NULL, -2,                                          \
26019 +    {                                                  \
26020 +      AVR32_OPERAND_##op0, AVR32_OPERAND_##op1,                \
26021 +    }                                                  \
26022 +  }
26023 +#define SYNTAX_NORMAL3(id, mne, opc, op0, op1, op2, arch)      \
26024 +  {                                                    \
26025 +    AVR32_SYNTAX_##id, arch,                   \
26026 +    &avr32_mnemonic_table[AVR32_MNEMONIC_##mne],       \
26027 +    AVR32_PARSER_NORMAL,                                       \
26028 +    { &avr32_opc_table[AVR32_OPC_##opc], },                    \
26029 +    NULL, 3,                                           \
26030 +    {                                                  \
26031 +      AVR32_OPERAND_##op0, AVR32_OPERAND_##op1,                \
26032 +      AVR32_OPERAND_##op2,                             \
26033 +    }                                                  \
26034 +  }
26035 +#define SYNTAX_NORMALM3(id, mne, opc, op0, op1, op2, arch)     \
26036 +  {                                                    \
26037 +    AVR32_SYNTAX_##id, arch,                   \
26038 +    &avr32_mnemonic_table[AVR32_MNEMONIC_##mne],       \
26039 +    AVR32_PARSER_NORMAL,                                       \
26040 +    { &avr32_opc_table[AVR32_OPC_##opc], },                    \
26041 +    NULL, -3,                                          \
26042 +    {                                                  \
26043 +      AVR32_OPERAND_##op0, AVR32_OPERAND_##op1,                \
26044 +      AVR32_OPERAND_##op2,                             \
26045 +    }                                                  \
26046 +  }
26047 +#define SYNTAX_NORMAL4(id, mne, opc, op0, op1, op2, op3, arch)\
26048 +  {                                                    \
26049 +    AVR32_SYNTAX_##id, arch,                   \
26050 +    &avr32_mnemonic_table[AVR32_MNEMONIC_##mne],       \
26051 +    AVR32_PARSER_NORMAL,                                       \
26052 +    { &avr32_opc_table[AVR32_OPC_##opc], },                    \
26053 +    NULL, 4,                                           \
26054 +    {                                                  \
26055 +      AVR32_OPERAND_##op0, AVR32_OPERAND_##op1,                \
26056 +      AVR32_OPERAND_##op2, AVR32_OPERAND_##op3,                \
26057 +    }                                                  \
26058 +  }
26059 +#define SYNTAX_NORMAL5(id, mne, opc, op0, op1, op2, op3, op4, arch)    \
26060 +  {                                                            \
26061 +    AVR32_SYNTAX_##id, arch,                           \
26062 +    &avr32_mnemonic_table[AVR32_MNEMONIC_##mne],               \
26063 +    AVR32_PARSER_NORMAL,                                               \
26064 +    { &avr32_opc_table[AVR32_OPC_##opc], },                            \
26065 +    NULL, 5,                                                   \
26066 +    {                                                          \
26067 +      AVR32_OPERAND_##op0, AVR32_OPERAND_##op1,                        \
26068 +      AVR32_OPERAND_##op2, AVR32_OPERAND_##op3,                        \
26069 +      AVR32_OPERAND_##op4,                                     \
26070 +    }                                                          \
26071 +  }
26072 +
26073 +#define SYNTAX_NORMAL_C1(id, mne, opc, nxt, op0, arch) \
26074 +  {                                                    \
26075 +    AVR32_SYNTAX_##id, arch,                   \
26076 +    &avr32_mnemonic_table[AVR32_MNEMONIC_##mne],       \
26077 +    AVR32_PARSER_NORMAL,                                       \
26078 +    { &avr32_opc_table[AVR32_OPC_##opc], },                    \
26079 +    &avr32_syntax_table[AVR32_SYNTAX_##nxt], 1,                \
26080 +    {                                                  \
26081 +      AVR32_OPERAND_##op0,                             \
26082 +    }                                                  \
26083 +  }
26084 +#define SYNTAX_NORMAL_CM1(id, mne, opc, nxt, op0, arch)        \
26085 +  {                                                    \
26086 +    AVR32_SYNTAX_##id, arch,                   \
26087 +    &avr32_mnemonic_table[AVR32_MNEMONIC_##mne],       \
26088 +    AVR32_PARSER_NORMAL,                                       \
26089 +    { &avr32_opc_table[AVR32_OPC_##opc], },                    \
26090 +    &avr32_syntax_table[AVR32_SYNTAX_##nxt], -1,       \
26091 +    {                                                  \
26092 +      AVR32_OPERAND_##op0,                             \
26093 +    }                                                  \
26094 +  }
26095 +#define SYNTAX_NORMAL_C2(id, mne, opc, nxt, op0, op1, arch)    \
26096 +  {                                                    \
26097 +    AVR32_SYNTAX_##id, arch,                   \
26098 +    &avr32_mnemonic_table[AVR32_MNEMONIC_##mne],       \
26099 +    AVR32_PARSER_NORMAL,                                       \
26100 +    { &avr32_opc_table[AVR32_OPC_##opc], },                    \
26101 +    &avr32_syntax_table[AVR32_SYNTAX_##nxt], 2,                \
26102 +    {                                                  \
26103 +      AVR32_OPERAND_##op0, AVR32_OPERAND_##op1,                \
26104 +    }                                                  \
26105 +  }
26106 +#define SYNTAX_NORMAL_CM2(id, mne, opc, nxt, op0, op1, arch)   \
26107 +  {                                                    \
26108 +    AVR32_SYNTAX_##id, arch,                   \
26109 +    &avr32_mnemonic_table[AVR32_MNEMONIC_##mne],       \
26110 +    AVR32_PARSER_NORMAL,                                       \
26111 +    { &avr32_opc_table[AVR32_OPC_##opc], },                    \
26112 +    &avr32_syntax_table[AVR32_SYNTAX_##nxt], -2,       \
26113 +    {                                                  \
26114 +      AVR32_OPERAND_##op0, AVR32_OPERAND_##op1,                \
26115 +    }                                                  \
26116 +  }
26117 +#define SYNTAX_NORMAL_C3(id, mne, opc, nxt, op0, op1, op2, arch)       \
26118 +  {                                                            \
26119 +    AVR32_SYNTAX_##id, arch,                           \
26120 +    &avr32_mnemonic_table[AVR32_MNEMONIC_##mne],               \
26121 +    AVR32_PARSER_NORMAL,                                               \
26122 +    { &avr32_opc_table[AVR32_OPC_##opc], },                            \
26123 +    &avr32_syntax_table[AVR32_SYNTAX_##nxt], 3,                        \
26124 +    {                                                          \
26125 +      AVR32_OPERAND_##op0, AVR32_OPERAND_##op1,                        \
26126 +      AVR32_OPERAND_##op2,                                     \
26127 +    }                                                          \
26128 +  }
26129 +#define SYNTAX_NORMAL_CM3(id, mne, opc, nxt, op0, op1, op2, arch)      \
26130 +  {                                                            \
26131 +    AVR32_SYNTAX_##id, arch,                           \
26132 +    &avr32_mnemonic_table[AVR32_MNEMONIC_##mne],               \
26133 +    AVR32_PARSER_NORMAL,                                               \
26134 +    { &avr32_opc_table[AVR32_OPC_##opc], },                            \
26135 +    &avr32_syntax_table[AVR32_SYNTAX_##nxt], -3,               \
26136 +    {                                                          \
26137 +      AVR32_OPERAND_##op0, AVR32_OPERAND_##op1,                        \
26138 +      AVR32_OPERAND_##op2,                                     \
26139 +    }                                                          \
26140 +  }
26141 +
26142 +
26143 +const struct avr32_syntax avr32_syntax_table[] =
26144 +  {
26145 +    SYNTAX_NORMAL1(ABS, ABS, ABS, INTREG, AVR32_V1),
26146 +    SYNTAX_NORMAL1(ACALL, ACALL, ACALL, UNSIGNED_CONST_W, AVR32_V1),
26147 +    SYNTAX_NORMAL1(ACR, ACR, ACR, INTREG,AVR32_V1),
26148 +    SYNTAX_NORMAL3(ADC, ADC, ADC, INTREG, INTREG, INTREG, AVR32_V1),
26149 +    SYNTAX_NORMAL_C2(ADD1, ADD, ADD1, ADD2, INTREG, INTREG, AVR32_V1),
26150 +    SYNTAX_NORMAL3(ADD2, ADD, ADD2, INTREG, INTREG, INTREG_LSL, AVR32_V1),
26151 +    SYNTAX_NORMAL3(ADDABS, ADDABS, ADDABS, INTREG, INTREG, INTREG, AVR32_V1),
26152 +    SYNTAX_NORMAL3(ADDHH_W, ADDHH_W, ADDHH_W, INTREG, INTREG_HSEL, INTREG_HSEL, AVR32_DSP),
26153 +    SYNTAX_NORMAL_C2(AND1, AND, AND1, AND2, INTREG, INTREG, AVR32_V1),
26154 +    SYNTAX_NORMAL_C3(AND2, AND, AND2, AND3, INTREG, INTREG, INTREG_LSL, AVR32_V1),
26155 +    SYNTAX_NORMAL3(AND3, AND, AND3, INTREG, INTREG, INTREG_LSR, AVR32_V1),
26156 +    SYNTAX_NORMAL_C2(ANDH, ANDH, ANDH, ANDH_COH, INTREG, UNSIGNED_CONST, AVR32_V1),
26157 +    SYNTAX_NORMAL3(ANDH_COH, ANDH, ANDH_COH, INTREG, UNSIGNED_CONST, COH, AVR32_V1),
26158 +    SYNTAX_NORMAL_C2(ANDL, ANDL, ANDL, ANDL_COH, INTREG, UNSIGNED_CONST, AVR32_V1),
26159 +    SYNTAX_NORMAL3(ANDL_COH, ANDL, ANDL_COH, INTREG, UNSIGNED_CONST, COH, AVR32_V1),
26160 +    SYNTAX_NORMAL2(ANDN, ANDN, ANDN, INTREG, INTREG, AVR32_V1),
26161 +    SYNTAX_NORMAL_C3(ASR1, ASR, ASR1, ASR3, INTREG, INTREG, INTREG, AVR32_V1),
26162 +    SYNTAX_NORMAL_C3(ASR3, ASR, ASR3, ASR2, INTREG, INTREG, UNSIGNED_NUMBER, AVR32_V1),
26163 +    SYNTAX_NORMAL2(ASR2, ASR, ASR2, INTREG, UNSIGNED_NUMBER, AVR32_V1),
26164 +    SYNTAX_NORMAL4(BFEXTS, BFEXTS, BFEXTS, INTREG, INTREG, UNSIGNED_NUMBER, UNSIGNED_NUMBER, AVR32_V1),
26165 +    SYNTAX_NORMAL4(BFEXTU, BFEXTU, BFEXTU, INTREG, INTREG, UNSIGNED_NUMBER, UNSIGNED_NUMBER, AVR32_V1),
26166 +    SYNTAX_NORMAL4(BFINS, BFINS, BFINS, INTREG, INTREG, UNSIGNED_NUMBER, UNSIGNED_NUMBER, AVR32_V1),
26167 +    SYNTAX_NORMAL2(BLD, BLD, BLD, INTREG, UNSIGNED_NUMBER, AVR32_V1),
26168 +    SYNTAX_NORMAL_C1(BREQ1, BREQ, BREQ1, BREQ2, JMPLABEL, AVR32_V1),
26169 +    SYNTAX_NORMAL_C1(BRNE1, BRNE, BRNE1, BRNE2, JMPLABEL, AVR32_V1),
26170 +    SYNTAX_NORMAL_C1(BRCC1, BRCC, BRCC1, BRCC2, JMPLABEL, AVR32_V1),
26171 +    SYNTAX_NORMAL_C1(BRCS1, BRCS, BRCS1, BRCS2, JMPLABEL, AVR32_V1),
26172 +    SYNTAX_NORMAL_C1(BRGE1, BRGE, BRGE1, BRGE2, JMPLABEL, AVR32_V1),
26173 +    SYNTAX_NORMAL_C1(BRLT1, BRLT, BRLT1, BRLT2, JMPLABEL, AVR32_V1),
26174 +    SYNTAX_NORMAL_C1(BRMI1, BRMI, BRMI1, BRMI2, JMPLABEL, AVR32_V1),
26175 +    SYNTAX_NORMAL_C1(BRPL1, BRPL, BRPL1, BRPL2, JMPLABEL, AVR32_V1),
26176 +    SYNTAX_NORMAL_C1(BRHS1, BRHS, BRCC1, BRHS2, JMPLABEL, AVR32_V1),
26177 +    SYNTAX_NORMAL_C1(BRLO1, BRLO, BRCS1, BRLO2, JMPLABEL, AVR32_V1),
26178 +    SYNTAX_NORMAL1(BREQ2, BREQ, BREQ2, JMPLABEL, AVR32_V1),
26179 +    SYNTAX_NORMAL1(BRNE2, BRNE, BRNE2, JMPLABEL, AVR32_V1),
26180 +    SYNTAX_NORMAL1(BRCC2, BRCC, BRCC2, JMPLABEL, AVR32_V1),
26181 +    SYNTAX_NORMAL1(BRCS2, BRCS, BRCS2, JMPLABEL, AVR32_V1),
26182 +    SYNTAX_NORMAL1(BRGE2, BRGE, BRGE2, JMPLABEL, AVR32_V1),
26183 +    SYNTAX_NORMAL1(BRLT2, BRLT, BRLT2, JMPLABEL, AVR32_V1),
26184 +    SYNTAX_NORMAL1(BRMI2, BRMI, BRMI2, JMPLABEL, AVR32_V1),
26185 +    SYNTAX_NORMAL1(BRPL2, BRPL, BRPL2, JMPLABEL, AVR32_V1),
26186 +    SYNTAX_NORMAL1(BRLS, BRLS, BRLS, JMPLABEL, AVR32_V1),
26187 +    SYNTAX_NORMAL1(BRGT, BRGT, BRGT, JMPLABEL, AVR32_V1),
26188 +    SYNTAX_NORMAL1(BRLE, BRLE, BRLE, JMPLABEL, AVR32_V1),
26189 +    SYNTAX_NORMAL1(BRHI, BRHI, BRHI, JMPLABEL, AVR32_V1),
26190 +    SYNTAX_NORMAL1(BRVS, BRVS, BRVS, JMPLABEL, AVR32_V1),
26191 +    SYNTAX_NORMAL1(BRVC, BRVC, BRVC, JMPLABEL, AVR32_V1),
26192 +    SYNTAX_NORMAL1(BRQS, BRQS, BRQS, JMPLABEL, AVR32_V1),
26193 +    SYNTAX_NORMAL1(BRAL, BRAL, BRAL, JMPLABEL, AVR32_V1),
26194 +    SYNTAX_NORMAL1(BRHS2, BRHS, BRCC2, JMPLABEL, AVR32_V1),
26195 +    SYNTAX_NORMAL1(BRLO2, BRLO, BRCS2, JMPLABEL, AVR32_V1),
26196 +    SYNTAX_NORMAL0(BREAKPOINT, BREAKPOINT, BREAKPOINT, AVR32_V1),
26197 +    SYNTAX_NORMAL1(BREV, BREV, BREV, INTREG, AVR32_V1),
26198 +    SYNTAX_NORMAL2(BST, BST, BST, INTREG, UNSIGNED_NUMBER, AVR32_V1),
26199 +    SYNTAX_NORMAL2(CACHE, CACHE, CACHE, INTREG_SDISP, UNSIGNED_NUMBER, AVR32_V1),
26200 +    SYNTAX_NORMAL1(CASTS_B, CASTS_B, CASTS_B, INTREG, AVR32_V1),
26201 +    SYNTAX_NORMAL1(CASTS_H, CASTS_H, CASTS_H, INTREG, AVR32_V1),
26202 +    SYNTAX_NORMAL1(CASTU_B, CASTU_B, CASTU_B, INTREG, AVR32_V1),
26203 +    SYNTAX_NORMAL1(CASTU_H, CASTU_H, CASTU_H, INTREG, AVR32_V1),
26204 +    SYNTAX_NORMAL2(CBR, CBR, CBR, INTREG, UNSIGNED_NUMBER, AVR32_V1),
26205 +    SYNTAX_NORMAL2(CLZ, CLZ, CLZ, INTREG, INTREG, AVR32_V1),
26206 +    SYNTAX_NORMAL1(COM, COM, COM, INTREG, AVR32_V1),
26207 +    SYNTAX_NORMAL5(COP, COP, COP, CPNO, CPREG, CPREG, CPREG, UNSIGNED_NUMBER, AVR32_V1),
26208 +    SYNTAX_NORMAL2(CP_B, CP_B, CP_B, INTREG, INTREG, AVR32_V1),
26209 +    SYNTAX_NORMAL2(CP_H, CP_H, CP_H, INTREG, INTREG, AVR32_V1),
26210 +    SYNTAX_NORMAL_C2(CP_W1, CP_W, CP_W1, CP_W2, INTREG, INTREG, AVR32_V1),
26211 +    SYNTAX_NORMAL_C2(CP_W2, CP_W, CP_W2, CP_W3, INTREG, SIGNED_CONST, AVR32_V1),
26212 +    SYNTAX_NORMAL2(CP_W3, CP_W, CP_W3, INTREG, SIGNED_CONST, AVR32_V1),
26213 +    SYNTAX_NORMAL_C2(CPC1, CPC, CPC1, CPC2, INTREG, INTREG, AVR32_V1),
26214 +    SYNTAX_NORMAL1(CPC2, CPC, CPC2, INTREG, AVR32_V1),
26215 +    SYNTAX_NORMAL1(CSRF, CSRF, CSRF, UNSIGNED_NUMBER, AVR32_V1),
26216 +    SYNTAX_NORMAL1(CSRFCZ, CSRFCZ, CSRFCZ, UNSIGNED_NUMBER, AVR32_V1),
26217 +    SYNTAX_NORMAL3(DIVS, DIVS, DIVS, INTREG, INTREG, INTREG, AVR32_V1),
26218 +    SYNTAX_NORMAL3(DIVU, DIVU, DIVU, INTREG, INTREG, INTREG, AVR32_V1),
26219 +    SYNTAX_NORMAL_C2(EOR1, EOR, EOR1, EOR2, INTREG, INTREG, AVR32_V1),
26220 +    SYNTAX_NORMAL_C3(EOR2, EOR, EOR2, EOR3, INTREG, INTREG, INTREG_LSL, AVR32_V1),
26221 +    SYNTAX_NORMAL3(EOR3, EOR, EOR3, INTREG, INTREG, INTREG_LSR, AVR32_V1),
26222 +    SYNTAX_NORMAL2(EORL, EORL, EORL, INTREG, UNSIGNED_CONST, AVR32_V1),
26223 +    SYNTAX_NORMAL2(EORH, EORH, EORH, INTREG, UNSIGNED_CONST, AVR32_V1),
26224 +    SYNTAX_NORMAL0(FRS, FRS, FRS, AVR32_V1),
26225 +    SYNTAX_NORMAL0(SSCALL, SSCALL, SSCALL, AVR32_V3),
26226 +    SYNTAX_NORMAL0(RETSS, RETSS, RETSS, AVR32_V3),
26227 +    SYNTAX_NORMAL1(ICALL, ICALL, ICALL, INTREG, AVR32_V1),
26228 +    SYNTAX_NORMAL1(INCJOSP, INCJOSP, INCJOSP, JOSPINC, AVR32_V1),
26229 +    SYNTAX_NORMAL_C2(LD_D1, LD_D, LD_D1, LD_D2, DWREG, INTREG_POSTINC, AVR32_V1),
26230 +    SYNTAX_NORMAL_C2(LD_D2, LD_D, LD_D2, LD_D3, DWREG, INTREG_PREDEC, AVR32_V1),
26231 +    SYNTAX_NORMAL_C2(LD_D3, LD_D, LD_D3, LD_D5, DWREG, INTREG, AVR32_V1),
26232 +    SYNTAX_NORMAL_C2(LD_D5, LD_D, LD_D5, LD_D4, DWREG, INTREG_INDEX, AVR32_V1),
26233 +    SYNTAX_NORMAL2(LD_D4, LD_D, LD_D4, DWREG, INTREG_SDISP, AVR32_V1),
26234 +    SYNTAX_NORMAL_C2(LD_SB2, LD_SB, LD_SB2, LD_SB1, INTREG, INTREG_INDEX, AVR32_V1),
26235 +    SYNTAX_NORMAL2(LD_SB1, LD_SB, LD_SB1, INTREG, INTREG_SDISP, AVR32_V1),
26236 +    SYNTAX_NORMAL_C2(LD_UB1, LD_UB, LD_UB1, LD_UB2, INTREG, INTREG_POSTINC, AVR32_V1),
26237 +    SYNTAX_NORMAL_C2(LD_UB2, LD_UB, LD_UB2, LD_UB5, INTREG, INTREG_PREDEC, AVR32_V1),
26238 +    SYNTAX_NORMAL_C2(LD_UB5, LD_UB, LD_UB5, LD_UB3, INTREG, INTREG_INDEX, AVR32_V1),
26239 +    SYNTAX_NORMAL_C2(LD_UB3, LD_UB, LD_UB3, LD_UB4, INTREG, INTREG_UDISP, AVR32_V1),
26240 +    SYNTAX_NORMAL2(LD_UB4, LD_UB, LD_UB4, INTREG, INTREG_SDISP, AVR32_V1),
26241 +    SYNTAX_NORMAL_C2(LD_SH1, LD_SH, LD_SH1, LD_SH2, INTREG, INTREG_POSTINC, AVR32_V1),
26242 +    SYNTAX_NORMAL_C2(LD_SH2, LD_SH, LD_SH2, LD_SH5, INTREG, INTREG_PREDEC, AVR32_V1),
26243 +    SYNTAX_NORMAL_C2(LD_SH5, LD_SH, LD_SH5, LD_SH3, INTREG, INTREG_INDEX, AVR32_V1),
26244 +    SYNTAX_NORMAL_C2(LD_SH3, LD_SH, LD_SH3, LD_SH4, INTREG, INTREG_UDISP_H, AVR32_V1),
26245 +    SYNTAX_NORMAL2(LD_SH4, LD_SH, LD_SH4, INTREG, INTREG_SDISP, AVR32_V1),
26246 +    SYNTAX_NORMAL_C2(LD_UH1, LD_UH, LD_UH1, LD_UH2, INTREG, INTREG_POSTINC, AVR32_V1),
26247 +    SYNTAX_NORMAL_C2(LD_UH2, LD_UH, LD_UH2, LD_UH5, INTREG, INTREG_PREDEC, AVR32_V1),
26248 +    SYNTAX_NORMAL_C2(LD_UH5, LD_UH, LD_UH5, LD_UH3, INTREG, INTREG_INDEX, AVR32_V1),
26249 +    SYNTAX_NORMAL_C2(LD_UH3, LD_UH, LD_UH3, LD_UH4, INTREG, INTREG_UDISP_H, AVR32_V1),
26250 +    SYNTAX_NORMAL2(LD_UH4, LD_UH, LD_UH4, INTREG, INTREG_SDISP, AVR32_V1),
26251 +    SYNTAX_NORMAL_C2(LD_W1, LD_W, LD_W1, LD_W2, INTREG, INTREG_POSTINC, AVR32_V1),
26252 +    SYNTAX_NORMAL_C2(LD_W2, LD_W, LD_W2, LD_W5, INTREG, INTREG_PREDEC, AVR32_V1),
26253 +    SYNTAX_NORMAL_C2(LD_W5, LD_W, LD_W5, LD_W6, INTREG, INTREG_INDEX, AVR32_V1),
26254 +    SYNTAX_NORMAL_C2(LD_W6, LD_W, LD_W6, LD_W3, INTREG, INTREG_XINDEX, AVR32_V1),
26255 +    SYNTAX_NORMAL_C2(LD_W3, LD_W, LD_W3, LD_W4, INTREG, INTREG_UDISP_W, AVR32_V1),
26256 +    SYNTAX_NORMAL2(LD_W4, LD_W, LD_W4, INTREG, INTREG_SDISP, AVR32_V1),
26257 +    SYNTAX_NORMAL3(LDC_D1, LDC_D, LDC_D1, CPNO, CPREG_D, INTREG_UDISP_W, AVR32_V1),
26258 +    SYNTAX_NORMAL_C3(LDC_D2, LDC_D, LDC_D2, LDC_D1, CPNO, CPREG_D, INTREG_PREDEC, AVR32_V1),
26259 +    SYNTAX_NORMAL_C3(LDC_D3, LDC_D, LDC_D3, LDC_D2, CPNO, CPREG_D, INTREG_INDEX, AVR32_V1),
26260 +    SYNTAX_NORMAL3(LDC_W1, LDC_W, LDC_W1, CPNO, CPREG, INTREG_UDISP_W, AVR32_V1),
26261 +    SYNTAX_NORMAL_C3(LDC_W2, LDC_W, LDC_W2, LDC_W1, CPNO, CPREG, INTREG_PREDEC, AVR32_V1),
26262 +    SYNTAX_NORMAL_C3(LDC_W3, LDC_W, LDC_W3, LDC_W2, CPNO, CPREG, INTREG_INDEX, AVR32_V1),
26263 +    SYNTAX_NORMAL2(LDC0_D, LDC0_D, LDC0_D, CPREG_D, INTREG_UDISP_W, AVR32_V1),
26264 +    SYNTAX_NORMAL2(LDC0_W, LDC0_W, LDC0_W, CPREG, INTREG_UDISP_W, AVR32_V1),
26265 +    SYNTAX_NORMAL_CM3(LDCM_D, LDCM_D, LDCM_D, LDCM_D_PU, CPNO, INTREG, REGLIST_CPD8, AVR32_V1),
26266 +    SYNTAX_NORMALM3(LDCM_D_PU, LDCM_D, LDCM_D_PU, CPNO, INTREG_POSTINC, REGLIST_CPD8, AVR32_V1),
26267 +    SYNTAX_NORMAL_CM3(LDCM_W, LDCM_W, LDCM_W, LDCM_W_PU, CPNO, INTREG, REGLIST_CP8, AVR32_V1),
26268 +    SYNTAX_NORMALM3(LDCM_W_PU, LDCM_W, LDCM_W_PU, CPNO, INTREG_POSTINC, REGLIST_CP8, AVR32_V1),
26269 +    SYNTAX_NORMAL2(LDDPC, LDDPC, LDDPC, INTREG, PC_UDISP_W, AVR32_V1),
26270 +    SYNTAX_NORMAL2(LDDPC_EXT, LDDPC, LDDPC_EXT, INTREG, SIGNED_CONST, AVR32_V1),
26271 +    SYNTAX_NORMAL2(LDDSP, LDDSP, LDDSP, INTREG, SP_UDISP_W, AVR32_V1),
26272 +    SYNTAX_NORMAL2(LDINS_B, LDINS_B, LDINS_B, INTREG_BSEL, INTREG_SDISP, AVR32_V1),
26273 +    SYNTAX_NORMAL2(LDINS_H, LDINS_H, LDINS_H, INTREG_HSEL, INTREG_SDISP_H, AVR32_V1),
26274 +    SYNTAX_NORMALM1(LDM, LDM, LDM, REGLIST_LDM, AVR32_V1),
26275 +    SYNTAX_NORMAL_CM2(LDMTS, LDMTS, LDMTS, LDMTS_PU, INTREG, REGLIST16, AVR32_V1),
26276 +    SYNTAX_NORMALM2(LDMTS_PU, LDMTS, LDMTS_PU, INTREG_POSTINC, REGLIST16, AVR32_V1),
26277 +    SYNTAX_NORMAL2(LDSWP_SH, LDSWP_SH, LDSWP_SH, INTREG, INTREG_SDISP_H, AVR32_V1),
26278 +    SYNTAX_NORMAL2(LDSWP_UH, LDSWP_UH, LDSWP_UH, INTREG, INTREG_SDISP_H, AVR32_V1),
26279 +    SYNTAX_NORMAL2(LDSWP_W, LDSWP_W, LDSWP_W, INTREG, INTREG_SDISP_W, AVR32_V1),
26280 +    SYNTAX_NORMAL_C3(LSL1, LSL, LSL1, LSL3, INTREG, INTREG, INTREG, AVR32_V1),
26281 +    SYNTAX_NORMAL_C3(LSL3, LSL, LSL3, LSL2, INTREG, INTREG, UNSIGNED_NUMBER, AVR32_V1),
26282 +    SYNTAX_NORMAL2(LSL2, LSL, LSL2, INTREG, UNSIGNED_NUMBER, AVR32_V1),
26283 +    SYNTAX_NORMAL_C3(LSR1, LSR, LSR1, LSR3, INTREG, INTREG, INTREG, AVR32_V1),
26284 +    SYNTAX_NORMAL_C3(LSR3, LSR, LSR3, LSR2, INTREG, INTREG, UNSIGNED_NUMBER, AVR32_V1),
26285 +    SYNTAX_NORMAL2(LSR2, LSR, LSR2, INTREG, UNSIGNED_NUMBER, AVR32_V1),
26286 +    SYNTAX_NORMAL3(MAC, MAC, MAC, INTREG, INTREG, INTREG, AVR32_V1),
26287 +    SYNTAX_NORMAL3(MACHH_D, MACHH_D, MACHH_D, INTREG, INTREG_HSEL, INTREG_HSEL, AVR32_DSP),
26288 +    SYNTAX_NORMAL3(MACHH_W, MACHH_W, MACHH_W, INTREG, INTREG_HSEL, INTREG_HSEL, AVR32_DSP),
26289 +    SYNTAX_NORMAL3(MACS_D, MACS_D, MACS_D, INTREG, INTREG, INTREG, AVR32_V1),
26290 +    SYNTAX_NORMAL3(MACSATHH_W, MACSATHH_W, MACSATHH_W, INTREG, INTREG_HSEL, INTREG_HSEL, AVR32_DSP),
26291 +    SYNTAX_NORMAL3(MACUD, MACU_D, MACUD, INTREG, INTREG, INTREG, AVR32_V1),
26292 +    SYNTAX_NORMAL3(MACWH_D, MACWH_D, MACWH_D, INTREG, INTREG, INTREG_HSEL, AVR32_DSP),
26293 +    SYNTAX_NORMAL3(MAX, MAX, MAX, INTREG, INTREG, INTREG, AVR32_V1),
26294 +    SYNTAX_NORMAL1(MCALL, MCALL, MCALL, MCALL, AVR32_V1),
26295 +    SYNTAX_NORMAL2(MFDR, MFDR, MFDR, INTREG, UNSIGNED_CONST_W, AVR32_V1),
26296 +    SYNTAX_NORMAL2(MFSR, MFSR, MFSR, INTREG, UNSIGNED_CONST_W, AVR32_V1),
26297 +    SYNTAX_NORMAL3(MIN, MIN, MIN, INTREG, INTREG, INTREG, AVR32_V1),
26298 +    SYNTAX_NORMAL_C2(MOV3, MOV, MOV3, MOV1, INTREG, INTREG, AVR32_V1),
26299 +    SYNTAX_NORMAL_C2(MOV1, MOV, MOV1, MOV2, INTREG, SIGNED_CONST, AVR32_V1),
26300 +    SYNTAX_NORMAL2(MOV2, MOV, MOV2,INTREG, SIGNED_CONST, AVR32_V1),
26301 +    SYNTAX_NORMAL_C2(MOVEQ1, MOVEQ, MOVEQ1, MOVEQ2, INTREG, INTREG, AVR32_V1),
26302 +    SYNTAX_NORMAL_C2(MOVNE1, MOVNE, MOVNE1, MOVNE2, INTREG, INTREG, AVR32_V1),
26303 +    SYNTAX_NORMAL_C2(MOVCC1, MOVCC, MOVCC1, MOVCC2, INTREG, INTREG, AVR32_V1),
26304 +    SYNTAX_NORMAL_C2(MOVCS1, MOVCS, MOVCS1, MOVCS2, INTREG, INTREG, AVR32_V1),
26305 +    SYNTAX_NORMAL_C2(MOVGE1, MOVGE, MOVGE1, MOVGE2, INTREG, INTREG, AVR32_V1),
26306 +    SYNTAX_NORMAL_C2(MOVLT1, MOVLT, MOVLT1, MOVLT2, INTREG, INTREG, AVR32_V1),
26307 +    SYNTAX_NORMAL_C2(MOVMI1, MOVMI, MOVMI1, MOVMI2, INTREG, INTREG, AVR32_V1),
26308 +    SYNTAX_NORMAL_C2(MOVPL1, MOVPL, MOVPL1, MOVPL2, INTREG, INTREG, AVR32_V1),
26309 +    SYNTAX_NORMAL_C2(MOVLS1, MOVLS, MOVLS1, MOVLS2, INTREG, INTREG, AVR32_V1),
26310 +    SYNTAX_NORMAL_C2(MOVGT1, MOVGT, MOVGT1, MOVGT2, INTREG, INTREG, AVR32_V1),
26311 +    SYNTAX_NORMAL_C2(MOVLE1, MOVLE, MOVLE1, MOVLE2, INTREG, INTREG, AVR32_V1),
26312 +    SYNTAX_NORMAL_C2(MOVHI1, MOVHI, MOVHI1, MOVHI2, INTREG, INTREG, AVR32_V1),
26313 +    SYNTAX_NORMAL_C2(MOVVS1, MOVVS, MOVVS1, MOVVS2, INTREG, INTREG, AVR32_V1),
26314 +    SYNTAX_NORMAL_C2(MOVVC1, MOVVC, MOVVC1, MOVVC2, INTREG, INTREG, AVR32_V1),
26315 +    SYNTAX_NORMAL_C2(MOVQS1, MOVQS, MOVQS1, MOVQS2, INTREG, INTREG, AVR32_V1),
26316 +    SYNTAX_NORMAL_C2(MOVAL1, MOVAL, MOVAL1, MOVAL2, INTREG, INTREG, AVR32_V1),
26317 +    SYNTAX_NORMAL_C2(MOVHS1, MOVHS, MOVCC1, MOVHS2, INTREG, INTREG, AVR32_V1),
26318 +    SYNTAX_NORMAL_C2(MOVLO1, MOVLO, MOVCS1, MOVLO2, INTREG, INTREG, AVR32_V1),
26319 +    SYNTAX_NORMAL2(MOVEQ2, MOVEQ, MOVEQ2, INTREG, SIGNED_CONST, AVR32_V1),
26320 +    SYNTAX_NORMAL2(MOVNE2, MOVNE, MOVNE2, INTREG, SIGNED_CONST, AVR32_V1),
26321 +    SYNTAX_NORMAL2(MOVCC2, MOVCC, MOVCC2, INTREG, SIGNED_CONST, AVR32_V1),
26322 +    SYNTAX_NORMAL2(MOVCS2, MOVCS, MOVCS2, INTREG, SIGNED_CONST, AVR32_V1),
26323 +    SYNTAX_NORMAL2(MOVGE2, MOVGE, MOVGE2, INTREG, SIGNED_CONST, AVR32_V1),
26324 +    SYNTAX_NORMAL2(MOVLT2, MOVLT, MOVLT2, INTREG, SIGNED_CONST, AVR32_V1),
26325 +    SYNTAX_NORMAL2(MOVMI2, MOVMI, MOVMI2, INTREG, SIGNED_CONST, AVR32_V1),
26326 +    SYNTAX_NORMAL2(MOVPL2, MOVPL, MOVPL2, INTREG, SIGNED_CONST, AVR32_V1),
26327 +    SYNTAX_NORMAL2(MOVLS2, MOVLS, MOVLS2, INTREG, SIGNED_CONST, AVR32_V1),
26328 +    SYNTAX_NORMAL2(MOVGT2, MOVGT, MOVGT2, INTREG, SIGNED_CONST, AVR32_V1),
26329 +    SYNTAX_NORMAL2(MOVLE2, MOVLE, MOVLE2, INTREG, SIGNED_CONST, AVR32_V1),
26330 +    SYNTAX_NORMAL2(MOVHI2, MOVHI, MOVHI2, INTREG, SIGNED_CONST, AVR32_V1),
26331 +    SYNTAX_NORMAL2(MOVVS2, MOVVS, MOVVS2, INTREG, SIGNED_CONST, AVR32_V1),
26332 +    SYNTAX_NORMAL2(MOVVC2, MOVVC, MOVVC2, INTREG, SIGNED_CONST, AVR32_V1),
26333 +    SYNTAX_NORMAL2(MOVQS2, MOVQS, MOVQS2, INTREG, SIGNED_CONST, AVR32_V1),
26334 +    SYNTAX_NORMAL2(MOVAL2, MOVAL, MOVAL2, INTREG, SIGNED_CONST, AVR32_V1),
26335 +    SYNTAX_NORMAL2(MOVHS2, MOVHS, MOVCC2, INTREG, SIGNED_CONST, AVR32_V1),
26336 +    SYNTAX_NORMAL2(MOVLO2, MOVLO, MOVCS2, INTREG, SIGNED_CONST, AVR32_V1),
26337 +    SYNTAX_NORMAL2(MTDR, MTDR, MTDR, UNSIGNED_CONST_W, INTREG, AVR32_V1),
26338 +    SYNTAX_NORMAL2(MTSR, MTSR, MTSR, UNSIGNED_CONST_W, INTREG, AVR32_V1),
26339 +    SYNTAX_NORMAL_C2(MUL1, MUL, MUL1, MUL2, INTREG, INTREG, AVR32_V1),
26340 +    SYNTAX_NORMAL_C3(MUL2, MUL, MUL2, MUL3, INTREG, INTREG, INTREG, AVR32_V1),
26341 +    SYNTAX_NORMAL3(MUL3, MUL, MUL3, INTREG, INTREG, SIGNED_CONST, AVR32_V1),
26342 +    SYNTAX_NORMAL3(MULHH_W, MULHH_W, MULHH_W, INTREG, INTREG_HSEL, INTREG_HSEL, AVR32_DSP),
26343 +    SYNTAX_NORMAL3(MULNHH_W, MULNHH_W, MULNHH_W, INTREG, INTREG_HSEL, INTREG_HSEL, AVR32_DSP),
26344 +    SYNTAX_NORMAL3(MULNWH_D, MULNWH_D, MULNWH_D, INTREG, INTREG, INTREG_HSEL, AVR32_DSP),
26345 +    SYNTAX_NORMAL3(MULSD, MULS_D, MULSD, INTREG, INTREG, INTREG, AVR32_V1),
26346 +    SYNTAX_NORMAL3(MULSATHH_H, MULSATHH_H, MULSATHH_H, INTREG, INTREG_HSEL, INTREG_HSEL, AVR32_DSP),
26347 +    SYNTAX_NORMAL3(MULSATHH_W, MULSATHH_W, MULSATHH_W, INTREG, INTREG_HSEL, INTREG_HSEL, AVR32_DSP),
26348 +    SYNTAX_NORMAL3(MULSATRNDHH_H, MULSATRNDHH_H, MULSATRNDHH_H, INTREG, INTREG_HSEL, INTREG_HSEL, AVR32_DSP),
26349 +    SYNTAX_NORMAL3(MULSATRNDWH_W, MULSATRNDWH_W, MULSATRNDWH_W, INTREG, INTREG, INTREG_HSEL, AVR32_DSP),
26350 +    SYNTAX_NORMAL3(MULSATWH_W, MULSATWH_W, MULSATWH_W, INTREG, INTREG, INTREG_HSEL, AVR32_DSP),
26351 +    SYNTAX_NORMAL3(MULU_D, MULU_D, MULU_D, INTREG, INTREG, INTREG, AVR32_V1),
26352 +    SYNTAX_NORMAL3(MULWH_D, MULWH_D, MULWH_D, INTREG, INTREG, INTREG_HSEL, AVR32_DSP),
26353 +    SYNTAX_NORMAL1(MUSFR, MUSFR, MUSFR, INTREG, AVR32_V1),
26354 +    SYNTAX_NORMAL1(MUSTR, MUSTR, MUSTR, INTREG, AVR32_V1),
26355 +    SYNTAX_NORMAL3(MVCR_D, MVCR_D, MVCR_D, CPNO, DWREG, CPREG_D, AVR32_V1),
26356 +    SYNTAX_NORMAL3(MVCR_W, MVCR_W, MVCR_W, CPNO, INTREG, CPREG, AVR32_V1),
26357 +    SYNTAX_NORMAL3(MVRC_D, MVRC_D, MVRC_D, CPNO, CPREG_D, DWREG, AVR32_V1),
26358 +    SYNTAX_NORMAL3(MVRC_W, MVRC_W, MVRC_W, CPNO, CPREG, INTREG, AVR32_V1),
26359 +    SYNTAX_NORMAL1(NEG, NEG, NEG, INTREG, AVR32_V1),
26360 +    SYNTAX_NORMAL0(NOP, NOP, NOP, AVR32_V1),
26361 +    SYNTAX_NORMAL_C2(OR1, OR, OR1, OR2, INTREG, INTREG, AVR32_V1),
26362 +    SYNTAX_NORMAL_C3(OR2, OR, OR2, OR3, INTREG, INTREG, INTREG_LSL, AVR32_V1),
26363 +    SYNTAX_NORMAL3(OR3, OR, OR3, INTREG, INTREG, INTREG_LSR, AVR32_V1),
26364 +    SYNTAX_NORMAL2(ORH, ORH, ORH, INTREG, UNSIGNED_CONST, AVR32_V1),
26365 +    SYNTAX_NORMAL2(ORL, ORL, ORL, INTREG, UNSIGNED_CONST, AVR32_V1),
26366 +    SYNTAX_NORMAL2(PABS_SB, PABS_SB, PABS_SB, INTREG, INTREG, AVR32_SIMD),
26367 +    SYNTAX_NORMAL2(PABS_SH, PABS_SH, PABS_SH, INTREG, INTREG, AVR32_SIMD),
26368 +    SYNTAX_NORMAL3(PACKSH_SB, PACKSH_SB, PACKSH_SB, INTREG, INTREG, INTREG, AVR32_SIMD),
26369 +    SYNTAX_NORMAL3(PACKSH_UB, PACKSH_UB, PACKSH_UB, INTREG, INTREG, INTREG, AVR32_SIMD),
26370 +    SYNTAX_NORMAL3(PACKW_SH, PACKW_SH, PACKW_SH, INTREG, INTREG, INTREG, AVR32_SIMD),
26371 +    SYNTAX_NORMAL3(PADD_B, PADD_B, PADD_B, INTREG, INTREG, INTREG, AVR32_SIMD),
26372 +    SYNTAX_NORMAL3(PADD_H, PADD_H, PADD_H, INTREG, INTREG, INTREG, AVR32_SIMD),
26373 +    SYNTAX_NORMAL3(PADDH_SH, PADDH_SH, PADDH_SH, INTREG, INTREG, INTREG, AVR32_SIMD),
26374 +    SYNTAX_NORMAL3(PADDH_UB, PADDH_UB, PADDH_UB, INTREG, INTREG, INTREG, AVR32_SIMD),
26375 +    SYNTAX_NORMAL3(PADDS_SB, PADDS_SB, PADDS_SB, INTREG, INTREG, INTREG, AVR32_SIMD),
26376 +    SYNTAX_NORMAL3(PADDS_SH, PADDS_SH, PADDS_SH, INTREG, INTREG, INTREG, AVR32_SIMD),
26377 +    SYNTAX_NORMAL3(PADDS_UB, PADDS_UB, PADDS_UB, INTREG, INTREG, INTREG, AVR32_SIMD),
26378 +    SYNTAX_NORMAL3(PADDS_UH, PADDS_UH, PADDS_UH, INTREG, INTREG, INTREG, AVR32_SIMD),
26379 +    SYNTAX_NORMAL3(PADDSUB_H, PADDSUB_H, PADDSUB_H, INTREG, INTREG_HSEL, INTREG_HSEL, AVR32_SIMD),
26380 +    SYNTAX_NORMAL3(PADDSUBH_SH, PADDSUBH_SH, PADDSUBH_SH, INTREG, INTREG_HSEL, INTREG_HSEL, AVR32_SIMD),
26381 +    SYNTAX_NORMAL3(PADDSUBS_SH, PADDSUBS_SH, PADDSUBS_SH, INTREG, INTREG_HSEL, INTREG_HSEL, AVR32_SIMD),
26382 +    SYNTAX_NORMAL3(PADDSUBS_UH, PADDSUBS_UH, PADDSUBS_UH, INTREG, INTREG_HSEL, INTREG_HSEL, AVR32_SIMD),
26383 +    SYNTAX_NORMAL3(PADDX_H, PADDX_H, PADDX_H, INTREG, INTREG, INTREG, AVR32_SIMD),
26384 +    SYNTAX_NORMAL3(PADDXH_SH, PADDXH_SH, PADDXH_SH, INTREG, INTREG, INTREG, AVR32_SIMD),
26385 +    SYNTAX_NORMAL3(PADDXS_SH, PADDXS_SH, PADDXS_SH, INTREG, INTREG, INTREG, AVR32_SIMD),
26386 +    SYNTAX_NORMAL3(PADDXS_UH, PADDXS_UH, PADDXS_UH, INTREG, INTREG, INTREG, AVR32_SIMD),
26387 +    SYNTAX_NORMAL3(PASR_B, PASR_B, PASR_B, INTREG, INTREG, UNSIGNED_NUMBER, AVR32_SIMD),
26388 +    SYNTAX_NORMAL3(PASR_H, PASR_H, PASR_H, INTREG, INTREG, UNSIGNED_NUMBER, AVR32_SIMD),
26389 +    SYNTAX_NORMAL3(PAVG_SH, PAVG_SH, PAVG_SH, INTREG, INTREG, INTREG, AVR32_SIMD),
26390 +    SYNTAX_NORMAL3(PAVG_UB, PAVG_UB, PAVG_UB, INTREG, INTREG, INTREG, AVR32_SIMD),
26391 +    SYNTAX_NORMAL3(PLSL_B, PLSL_B, PLSL_B, INTREG, INTREG, UNSIGNED_NUMBER, AVR32_SIMD),
26392 +    SYNTAX_NORMAL3(PLSL_H, PLSL_H, PLSL_H, INTREG, INTREG, UNSIGNED_NUMBER, AVR32_SIMD),
26393 +    SYNTAX_NORMAL3(PLSR_B, PLSR_B, PLSR_B, INTREG, INTREG, UNSIGNED_NUMBER, AVR32_SIMD),
26394 +    SYNTAX_NORMAL3(PLSR_H, PLSR_H, PLSR_H, INTREG, INTREG, UNSIGNED_NUMBER, AVR32_SIMD),
26395 +    SYNTAX_NORMAL3(PMAX_SH, PMAX_SH, PMAX_SH, INTREG, INTREG, INTREG, AVR32_SIMD),
26396 +    SYNTAX_NORMAL3(PMAX_UB, PMAX_UB, PMAX_UB, INTREG, INTREG, INTREG, AVR32_SIMD),
26397 +    SYNTAX_NORMAL3(PMIN_SH, PMIN_SH, PMIN_SH, INTREG, INTREG, INTREG, AVR32_SIMD),
26398 +    SYNTAX_NORMAL3(PMIN_UB, PMIN_UB, PMIN_UB, INTREG, INTREG, INTREG, AVR32_SIMD),
26399 +    SYNTAX_NORMAL0(POPJC, POPJC, POPJC, AVR32_V1),
26400 +    SYNTAX_NORMAL_CM1(POPM, POPM, POPM, POPM_E, REGLIST9, AVR32_V1),
26401 +    SYNTAX_NORMALM1(POPM_E, POPM, POPM_E, REGLIST16, AVR32_V1),
26402 +    SYNTAX_NORMAL1(PREF, PREF, PREF, INTREG_SDISP, AVR32_V1),
26403 +    SYNTAX_NORMAL3(PSAD, PSAD, PSAD, INTREG, INTREG, INTREG, AVR32_SIMD),
26404 +    SYNTAX_NORMAL3(PSUB_B, PSUB_B, PSUB_B, INTREG, INTREG, INTREG, AVR32_SIMD),
26405 +    SYNTAX_NORMAL3(PSUB_H, PSUB_H, PSUB_H, INTREG, INTREG, INTREG, AVR32_SIMD),
26406 +    SYNTAX_NORMAL3(PSUBADD_H, PSUBADD_H, PSUBADD_H, INTREG, INTREG_HSEL, INTREG_HSEL, AVR32_SIMD),
26407 +    SYNTAX_NORMAL3(PSUBADDH_SH, PSUBADDH_SH, PSUBADDH_SH, INTREG, INTREG_HSEL, INTREG_HSEL, AVR32_SIMD),
26408 +    SYNTAX_NORMAL3(PSUBADDS_SH, PSUBADDS_SH, PSUBADDS_SH, INTREG, INTREG_HSEL, INTREG_HSEL, AVR32_SIMD),
26409 +    SYNTAX_NORMAL3(PSUBADDS_UH, PSUBADDS_UH, PSUBADDS_UH, INTREG, INTREG_HSEL, INTREG_HSEL, AVR32_SIMD),
26410 +    SYNTAX_NORMAL3(PSUBH_SH, PSUBH_SH, PSUBH_SH, INTREG, INTREG, INTREG, AVR32_SIMD),
26411 +    SYNTAX_NORMAL3(PSUBH_UB, PSUBH_UB, PSUBH_UB, INTREG, INTREG, INTREG, AVR32_SIMD),
26412 +    SYNTAX_NORMAL3(PSUBS_SB, PSUBS_SB, PSUBS_SB, INTREG, INTREG, INTREG, AVR32_SIMD),
26413 +    SYNTAX_NORMAL3(PSUBS_SH, PSUBS_SH, PSUBS_SH, INTREG, INTREG, INTREG, AVR32_SIMD),
26414 +    SYNTAX_NORMAL3(PSUBS_UB, PSUBS_UB, PSUBS_UB, INTREG, INTREG, INTREG, AVR32_SIMD),
26415 +    SYNTAX_NORMAL3(PSUBS_UH, PSUBS_UH, PSUBS_UH, INTREG, INTREG, INTREG, AVR32_SIMD),
26416 +    SYNTAX_NORMAL3(PSUBX_H, PSUBX_H, PSUBX_H, INTREG, INTREG, INTREG, AVR32_SIMD),
26417 +    SYNTAX_NORMAL3(PSUBXH_SH, PSUBXH_SH, PSUBXH_SH, INTREG, INTREG, INTREG, AVR32_SIMD),
26418 +    SYNTAX_NORMAL3(PSUBXS_SH, PSUBXS_SH, PSUBXS_SH, INTREG, INTREG, INTREG, AVR32_SIMD),
26419 +    SYNTAX_NORMAL3(PSUBXS_UH, PSUBXS_UH, PSUBXS_UH, INTREG, INTREG, INTREG, AVR32_SIMD),
26420 +    SYNTAX_NORMAL2(PUNPCKSB_H, PUNPCKSB_H, PUNPCKSB_H, INTREG, INTREG_HSEL, AVR32_SIMD),
26421 +    SYNTAX_NORMAL2(PUNPCKUB_H, PUNPCKUB_H, PUNPCKUB_H, INTREG, INTREG_HSEL, AVR32_SIMD),
26422 +    SYNTAX_NORMAL0(PUSHJC, PUSHJC, PUSHJC, AVR32_V1),
26423 +    SYNTAX_NORMAL_CM1(PUSHM, PUSHM, PUSHM, PUSHM_E, REGLIST8, AVR32_V1),
26424 +    SYNTAX_NORMALM1(PUSHM_E, PUSHM, PUSHM_E, REGLIST16, AVR32_V1),
26425 +    SYNTAX_NORMAL_C1(RCALL1, RCALL, RCALL1, RCALL2, JMPLABEL, AVR32_V1),
26426 +    SYNTAX_NORMAL1(RCALL2, RCALL, RCALL2, JMPLABEL, AVR32_V1),
26427 +    SYNTAX_NORMAL1(RETEQ, RETEQ, RETEQ, RETVAL, AVR32_V1),
26428 +    SYNTAX_NORMAL1(RETNE, RETNE, RETNE, RETVAL, AVR32_V1),
26429 +    SYNTAX_NORMAL1(RETCC, RETCC, RETCC, RETVAL, AVR32_V1),
26430 +    SYNTAX_NORMAL1(RETCS, RETCS, RETCS, RETVAL, AVR32_V1),
26431 +    SYNTAX_NORMAL1(RETGE, RETGE, RETGE, RETVAL, AVR32_V1),
26432 +    SYNTAX_NORMAL1(RETLT, RETLT, RETLT, RETVAL, AVR32_V1),
26433 +    SYNTAX_NORMAL1(RETMI, RETMI, RETMI, RETVAL, AVR32_V1),
26434 +    SYNTAX_NORMAL1(RETPL, RETPL, RETPL, RETVAL, AVR32_V1),
26435 +    SYNTAX_NORMAL1(RETLS, RETLS, RETLS, RETVAL, AVR32_V1),
26436 +    SYNTAX_NORMAL1(RETGT, RETGT, RETGT, RETVAL, AVR32_V1),
26437 +    SYNTAX_NORMAL1(RETLE, RETLE, RETLE, RETVAL, AVR32_V1),
26438 +    SYNTAX_NORMAL1(RETHI, RETHI, RETHI, RETVAL, AVR32_V1),
26439 +    SYNTAX_NORMAL1(RETVS, RETVS, RETVS, RETVAL, AVR32_V1),
26440 +    SYNTAX_NORMAL1(RETVC, RETVC, RETVC, RETVAL, AVR32_V1),
26441 +    SYNTAX_NORMAL1(RETQS, RETQS, RETQS, RETVAL, AVR32_V1),
26442 +    SYNTAX_NORMAL1(RETAL, RETAL, RETAL, RETVAL, AVR32_V1),
26443 +    SYNTAX_NORMAL1(RETHS, RETHS, RETCC, RETVAL, AVR32_V1),
26444 +    SYNTAX_NORMAL1(RETLO, RETLO, RETCS, RETVAL, AVR32_V1),
26445 +    SYNTAX_NORMAL0(RETD, RETD, RETD, AVR32_V1),
26446 +    SYNTAX_NORMAL0(RETE, RETE, RETE, AVR32_V1),
26447 +    SYNTAX_NORMAL0(RETJ, RETJ, RETJ, AVR32_V1),
26448 +    SYNTAX_NORMAL0(RETS, RETS, RETS, AVR32_V1),
26449 +    SYNTAX_NORMAL1(RJMP, RJMP, RJMP, JMPLABEL, AVR32_V1),
26450 +    SYNTAX_NORMAL1(ROL, ROL, ROL, INTREG, AVR32_V1),
26451 +    SYNTAX_NORMAL1(ROR, ROR, ROR, INTREG, AVR32_V1),
26452 +    SYNTAX_NORMAL_C2(RSUB1, RSUB, RSUB1, RSUB2, INTREG, INTREG, AVR32_V1),
26453 +    SYNTAX_NORMAL3(RSUB2, RSUB, RSUB2, INTREG, INTREG, SIGNED_CONST, AVR32_V1),
26454 +    SYNTAX_NORMAL3(SATADD_H, SATADD_H, SATADD_H, INTREG, INTREG, INTREG,  AVR32_DSP),
26455 +    SYNTAX_NORMAL3(SATADD_W, SATADD_W, SATADD_W, INTREG, INTREG, INTREG, AVR32_DSP),
26456 +    SYNTAX_NORMAL2(SATRNDS, SATRNDS, SATRNDS, INTREG_LSR, UNSIGNED_NUMBER, AVR32_DSP),
26457 +    SYNTAX_NORMAL2(SATRNDU, SATRNDU, SATRNDU, INTREG_LSR, UNSIGNED_NUMBER, AVR32_DSP),
26458 +    SYNTAX_NORMAL2(SATS, SATS, SATS, INTREG_LSR, UNSIGNED_NUMBER, AVR32_DSP),
26459 +    SYNTAX_NORMAL3(SATSUB_H, SATSUB_H, SATSUB_H, INTREG, INTREG, INTREG, AVR32_DSP),
26460 +    SYNTAX_NORMAL_C3(SATSUB_W1, SATSUB_W, SATSUB_W1, SATSUB_W2, INTREG, INTREG, INTREG, AVR32_DSP),
26461 +    SYNTAX_NORMAL3(SATSUB_W2, SATSUB_W, SATSUB_W2, INTREG, INTREG, SIGNED_CONST, AVR32_DSP),
26462 +    SYNTAX_NORMAL2(SATU, SATU, SATU, INTREG_LSR, UNSIGNED_NUMBER, AVR32_V1),
26463 +    SYNTAX_NORMAL3(SBC, SBC, SBC, INTREG, INTREG, INTREG, AVR32_V1),
26464 +    SYNTAX_NORMAL2(SBR, SBR, SBR, INTREG, UNSIGNED_NUMBER, AVR32_V1),
26465 +    SYNTAX_NORMAL0(SCALL, SCALL, SCALL, AVR32_V1),
26466 +    SYNTAX_NORMAL1(SCR, SCR, SCR, INTREG, AVR32_V1),
26467 +    SYNTAX_NORMAL1(SLEEP, SLEEP, SLEEP, UNSIGNED_CONST, AVR32_V1),
26468 +    SYNTAX_NORMAL1(SREQ, SREQ, SREQ, INTREG, AVR32_V1),
26469 +    SYNTAX_NORMAL1(SRNE, SRNE, SRNE, INTREG, AVR32_V1),
26470 +    SYNTAX_NORMAL1(SRCC, SRCC, SRCC, INTREG, AVR32_V1),
26471 +    SYNTAX_NORMAL1(SRCS, SRCS, SRCS, INTREG, AVR32_V1),
26472 +    SYNTAX_NORMAL1(SRGE, SRGE, SRGE, INTREG, AVR32_V1),
26473 +    SYNTAX_NORMAL1(SRLT, SRLT, SRLT, INTREG, AVR32_V1),
26474 +    SYNTAX_NORMAL1(SRMI, SRMI, SRMI, INTREG, AVR32_V1),
26475 +    SYNTAX_NORMAL1(SRPL, SRPL, SRPL, INTREG, AVR32_V1),
26476 +    SYNTAX_NORMAL1(SRLS, SRLS, SRLS, INTREG, AVR32_V1),
26477 +    SYNTAX_NORMAL1(SRGT, SRGT, SRGT, INTREG, AVR32_V1),
26478 +    SYNTAX_NORMAL1(SRLE, SRLE, SRLE, INTREG, AVR32_V1),
26479 +    SYNTAX_NORMAL1(SRHI, SRHI, SRHI, INTREG, AVR32_V1),
26480 +    SYNTAX_NORMAL1(SRVS, SRVS, SRVS, INTREG, AVR32_V1),
26481 +    SYNTAX_NORMAL1(SRVC, SRVC, SRVC, INTREG, AVR32_V1),
26482 +    SYNTAX_NORMAL1(SRQS, SRQS, SRQS, INTREG, AVR32_V1),
26483 +    SYNTAX_NORMAL1(SRAL, SRAL, SRAL, INTREG, AVR32_V1),
26484 +    SYNTAX_NORMAL1(SRHS, SRHS, SRCC, INTREG, AVR32_V1),
26485 +    SYNTAX_NORMAL1(SRLO, SRLO, SRCS, INTREG, AVR32_V1),
26486 +    SYNTAX_NORMAL1(SSRF, SSRF, SSRF, UNSIGNED_NUMBER, AVR32_V1),
26487 +    SYNTAX_NORMAL_C2(ST_B1, ST_B, ST_B1, ST_B2, INTREG_POSTINC, INTREG, AVR32_V1),
26488 +    SYNTAX_NORMAL_C2(ST_B2, ST_B, ST_B2, ST_B5, INTREG_PREDEC, INTREG, AVR32_V1),
26489 +    SYNTAX_NORMAL_C2(ST_B5, ST_B, ST_B5, ST_B3, INTREG_INDEX, INTREG, AVR32_V1),
26490 +    SYNTAX_NORMAL_C2(ST_B3, ST_B, ST_B3, ST_B4, INTREG_UDISP, INTREG, AVR32_V1),
26491 +    SYNTAX_NORMAL2(ST_B4, ST_B, ST_B4, INTREG_SDISP, INTREG, AVR32_V1),
26492 +    SYNTAX_NORMAL_C2(ST_D1, ST_D, ST_D1, ST_D2, INTREG_POSTINC, DWREG, AVR32_V1),
26493 +    SYNTAX_NORMAL_C2(ST_D2, ST_D, ST_D2, ST_D3, INTREG_PREDEC, DWREG, AVR32_V1),
26494 +    SYNTAX_NORMAL_C2(ST_D3, ST_D, ST_D3, ST_D5, INTREG, DWREG, AVR32_V1),
26495 +    SYNTAX_NORMAL_C2(ST_D5, ST_D, ST_D5, ST_D4, INTREG_INDEX, DWREG, AVR32_V1),
26496 +    SYNTAX_NORMAL2(ST_D4, ST_D, ST_D4, INTREG_SDISP, DWREG, AVR32_V1),
26497 +    SYNTAX_NORMAL_C2(ST_H1, ST_H, ST_H1, ST_H2, INTREG_POSTINC, INTREG, AVR32_V1),
26498 +    SYNTAX_NORMAL_C2(ST_H2, ST_H, ST_H2, ST_H5, INTREG_PREDEC, INTREG, AVR32_V1),
26499 +    SYNTAX_NORMAL_C2(ST_H5, ST_H, ST_H5, ST_H3, INTREG_INDEX, INTREG, AVR32_V1),
26500 +    SYNTAX_NORMAL_C2(ST_H3, ST_H, ST_H3, ST_H4, INTREG_UDISP_H, INTREG, AVR32_V1),
26501 +    SYNTAX_NORMAL2(ST_H4, ST_H, ST_H4, INTREG_SDISP, INTREG, AVR32_V1),
26502 +    SYNTAX_NORMAL_C2(ST_W1, ST_W, ST_W1, ST_W2, INTREG_POSTINC, INTREG, AVR32_V1),
26503 +    SYNTAX_NORMAL_C2(ST_W2, ST_W, ST_W2, ST_W5, INTREG_PREDEC, INTREG, AVR32_V1),
26504 +    SYNTAX_NORMAL_C2(ST_W5, ST_W, ST_W5, ST_W3, INTREG_INDEX, INTREG, AVR32_V1),
26505 +    SYNTAX_NORMAL_C2(ST_W3, ST_W, ST_W3, ST_W4, INTREG_UDISP_W, INTREG, AVR32_V1),
26506 +    SYNTAX_NORMAL2(ST_W4, ST_W, ST_W4, INTREG_SDISP, INTREG, AVR32_V1),
26507 +    SYNTAX_NORMAL3(STC_D1, STC_D, STC_D1, CPNO, INTREG_UDISP_W, CPREG_D, AVR32_V1),
26508 +    SYNTAX_NORMAL_C3(STC_D2, STC_D, STC_D2, STC_D1, CPNO, INTREG_POSTINC, CPREG_D, AVR32_V1),
26509 +    SYNTAX_NORMAL_C3(STC_D3, STC_D, STC_D3, STC_D2, CPNO, INTREG_INDEX, CPREG_D, AVR32_V1),
26510 +    SYNTAX_NORMAL3(STC_W1, STC_W, STC_W1, CPNO, INTREG_UDISP_W, CPREG, AVR32_V1),
26511 +    SYNTAX_NORMAL_C3(STC_W2, STC_W, STC_W2, STC_W1, CPNO, INTREG_POSTINC, CPREG, AVR32_V1),
26512 +    SYNTAX_NORMAL_C3(STC_W3, STC_W, STC_W3, STC_W2, CPNO, INTREG_INDEX, CPREG, AVR32_V1),
26513 +    SYNTAX_NORMAL2(STC0_D, STC0_D, STC0_D, INTREG_UDISP_W, CPREG_D, AVR32_V1),
26514 +    SYNTAX_NORMAL2(STC0_W, STC0_W, STC0_W, INTREG_UDISP_W, CPREG, AVR32_V1),
26515 +    SYNTAX_NORMAL_CM3(STCM_D, STCM_D, STCM_D, STCM_D_PU, CPNO, INTREG, REGLIST_CPD8, AVR32_V1),
26516 +    SYNTAX_NORMALM3(STCM_D_PU, STCM_D, STCM_D_PU, CPNO, INTREG_PREDEC, REGLIST_CPD8, AVR32_V1),
26517 +    SYNTAX_NORMAL_CM3(STCM_W, STCM_W, STCM_W, STCM_W_PU, CPNO, INTREG, REGLIST_CP8, AVR32_V1),
26518 +    SYNTAX_NORMALM3(STCM_W_PU, STCM_W, STCM_W_PU, CPNO, INTREG_PREDEC, REGLIST_CP8, AVR32_V1),
26519 +    SYNTAX_NORMAL2(STCOND, STCOND, STCOND, INTREG_SDISP, INTREG, AVR32_V1),
26520 +    SYNTAX_NORMAL2(STDSP, STDSP, STDSP, SP_UDISP_W, INTREG, AVR32_V1),
26521 +    SYNTAX_NORMAL_C3(STHH_W2, STHH_W, STHH_W2, STHH_W1, INTREG_INDEX, INTREG_HSEL, INTREG_HSEL, AVR32_V1),
26522 +    SYNTAX_NORMAL3(STHH_W1, STHH_W, STHH_W1, INTREG_UDISP_W, INTREG_HSEL, INTREG_HSEL, AVR32_V1),
26523 +    SYNTAX_NORMAL_CM2(STM, STM, STM, STM_PU, INTREG, REGLIST16, AVR32_V1),
26524 +    SYNTAX_NORMALM2(STM_PU, STM, STM_PU, INTREG_PREDEC, REGLIST16, AVR32_V1),
26525 +    SYNTAX_NORMAL_CM2(STMTS, STMTS, STMTS, STMTS_PU, INTREG, REGLIST16, AVR32_V1),
26526 +    SYNTAX_NORMALM2(STMTS_PU, STMTS, STMTS_PU, INTREG_PREDEC, REGLIST16, AVR32_V1),
26527 +    SYNTAX_NORMAL2(STSWP_H, STSWP_H, STSWP_H, INTREG_SDISP_H, INTREG, AVR32_V1),
26528 +    SYNTAX_NORMAL2(STSWP_W, STSWP_W, STSWP_W, INTREG_SDISP_W, INTREG, AVR32_V1),
26529 +    SYNTAX_NORMAL_C2(SUB1, SUB, SUB1, SUB2, INTREG, INTREG, AVR32_V1),
26530 +    SYNTAX_NORMAL_C3(SUB2, SUB, SUB2, SUB5, INTREG, INTREG, INTREG_LSL, AVR32_V1),
26531 +    SYNTAX_NORMAL_C3(SUB5, SUB, SUB5, SUB3_SP, INTREG, INTREG, SIGNED_CONST, AVR32_V1),
26532 +    SYNTAX_NORMAL_C2(SUB3_SP, SUB, SUB3_SP, SUB3, SP, SIGNED_CONST_W, AVR32_V1),
26533 +    SYNTAX_NORMAL_C2(SUB3, SUB, SUB3, SUB4, INTREG, SIGNED_CONST, AVR32_V1),
26534 +    SYNTAX_NORMAL2(SUB4, SUB, SUB4, INTREG, SIGNED_CONST, AVR32_V1),
26535 +    SYNTAX_NORMAL_C2(SUBEQ, SUBEQ, SUBEQ, SUB2EQ, INTREG, SIGNED_CONST, AVR32_V1),
26536 +    SYNTAX_NORMAL_C2(SUBNE, SUBNE, SUBNE, SUB2NE, INTREG, SIGNED_CONST, AVR32_V1),
26537 +    SYNTAX_NORMAL_C2(SUBCC, SUBCC, SUBCC, SUB2CC, INTREG, SIGNED_CONST, AVR32_V1),
26538 +    SYNTAX_NORMAL_C2(SUBCS, SUBCS, SUBCS, SUB2CS, INTREG, SIGNED_CONST, AVR32_V1),
26539 +    SYNTAX_NORMAL_C2(SUBGE, SUBGE, SUBGE, SUB2GE, INTREG, SIGNED_CONST, AVR32_V1),
26540 +    SYNTAX_NORMAL_C2(SUBLT, SUBLT, SUBLT, SUB2LT, INTREG, SIGNED_CONST, AVR32_V1),
26541 +    SYNTAX_NORMAL_C2(SUBMI, SUBMI, SUBMI, SUB2MI, INTREG, SIGNED_CONST, AVR32_V1),
26542 +    SYNTAX_NORMAL_C2(SUBPL, SUBPL, SUBPL, SUB2PL, INTREG, SIGNED_CONST, AVR32_V1),
26543 +    SYNTAX_NORMAL_C2(SUBLS, SUBLS, SUBLS, SUB2LS, INTREG, SIGNED_CONST, AVR32_V1),
26544 +    SYNTAX_NORMAL_C2(SUBGT, SUBGT, SUBGT, SUB2GT, INTREG, SIGNED_CONST, AVR32_V1),
26545 +    SYNTAX_NORMAL_C2(SUBLE, SUBLE, SUBLE, SUB2LE, INTREG, SIGNED_CONST, AVR32_V1),
26546 +    SYNTAX_NORMAL_C2(SUBHI, SUBHI, SUBHI, SUB2HI, INTREG, SIGNED_CONST, AVR32_V1),
26547 +    SYNTAX_NORMAL_C2(SUBVS, SUBVS, SUBVS, SUB2VS, INTREG, SIGNED_CONST, AVR32_V1),
26548 +    SYNTAX_NORMAL_C2(SUBVC, SUBVC, SUBVC, SUB2VC, INTREG, SIGNED_CONST, AVR32_V1),
26549 +    SYNTAX_NORMAL_C2(SUBQS, SUBQS, SUBQS, SUB2QS, INTREG, SIGNED_CONST, AVR32_V1),
26550 +    SYNTAX_NORMAL_C2(SUBAL, SUBAL, SUBAL, SUB2AL, INTREG, SIGNED_CONST, AVR32_V1),
26551 +    SYNTAX_NORMAL_C2(SUBHS, SUBHS, SUBCC, SUB2CC, INTREG, SIGNED_CONST, AVR32_V1),
26552 +    SYNTAX_NORMAL_C2(SUBLO, SUBLO, SUBCS, SUB2CS, INTREG, SIGNED_CONST, AVR32_V1),
26553 +    SYNTAX_NORMAL2(SUBFEQ, SUBFEQ, SUBFEQ, INTREG, SIGNED_CONST, AVR32_V1),
26554 +    SYNTAX_NORMAL2(SUBFNE, SUBFNE, SUBFNE, INTREG, SIGNED_CONST, AVR32_V1),
26555 +    SYNTAX_NORMAL2(SUBFCC, SUBFCC, SUBFCC, INTREG, SIGNED_CONST, AVR32_V1),
26556 +    SYNTAX_NORMAL2(SUBFCS, SUBFCS, SUBFCS, INTREG, SIGNED_CONST, AVR32_V1),
26557 +    SYNTAX_NORMAL2(SUBFGE, SUBFGE, SUBFGE, INTREG, SIGNED_CONST, AVR32_V1),
26558 +    SYNTAX_NORMAL2(SUBFLT, SUBFLT, SUBFLT, INTREG, SIGNED_CONST, AVR32_V1),
26559 +    SYNTAX_NORMAL2(SUBFMI, SUBFMI, SUBFMI, INTREG, SIGNED_CONST, AVR32_V1),
26560 +    SYNTAX_NORMAL2(SUBFPL, SUBFPL, SUBFPL, INTREG, SIGNED_CONST, AVR32_V1),
26561 +    SYNTAX_NORMAL2(SUBFLS, SUBFLS, SUBFLS, INTREG, SIGNED_CONST, AVR32_V1),
26562 +    SYNTAX_NORMAL2(SUBFGT, SUBFGT, SUBFGT, INTREG, SIGNED_CONST, AVR32_V1),
26563 +    SYNTAX_NORMAL2(SUBFLE, SUBFLE, SUBFLE, INTREG, SIGNED_CONST, AVR32_V1),
26564 +    SYNTAX_NORMAL2(SUBFHI, SUBFHI, SUBFHI, INTREG, SIGNED_CONST, AVR32_V1),
26565 +    SYNTAX_NORMAL2(SUBFVS, SUBFVS, SUBFVS, INTREG, SIGNED_CONST, AVR32_V1),
26566 +    SYNTAX_NORMAL2(SUBFVC, SUBFVC, SUBFVC, INTREG, SIGNED_CONST, AVR32_V1),
26567 +    SYNTAX_NORMAL2(SUBFQS, SUBFQS, SUBFQS, INTREG, SIGNED_CONST, AVR32_V1),
26568 +    SYNTAX_NORMAL2(SUBFAL, SUBFAL, SUBFAL, INTREG, SIGNED_CONST, AVR32_V1),
26569 +    SYNTAX_NORMAL2(SUBFHS, SUBFHS, SUBFCC, INTREG, SIGNED_CONST, AVR32_V1),
26570 +    SYNTAX_NORMAL2(SUBFLO, SUBFLO, SUBFCS, INTREG, SIGNED_CONST, AVR32_V1),
26571 +    SYNTAX_NORMAL3(SUBHH_W, SUBHH_W, SUBHH_W, INTREG, INTREG_HSEL, INTREG_HSEL, AVR32_DSP),
26572 +    SYNTAX_NORMAL1(SWAP_B, SWAP_B, SWAP_B, INTREG, AVR32_V1),
26573 +    SYNTAX_NORMAL1(SWAP_BH, SWAP_BH, SWAP_BH, INTREG, AVR32_V1),
26574 +    SYNTAX_NORMAL1(SWAP_H, SWAP_H, SWAP_H, INTREG, AVR32_V1),
26575 +    SYNTAX_NORMAL1(SYNC, SYNC, SYNC, UNSIGNED_CONST, AVR32_V1),
26576 +    SYNTAX_NORMAL0(TLBR, TLBR, TLBR, AVR32_V1),
26577 +    SYNTAX_NORMAL0(TLBS, TLBS, TLBS, AVR32_V1),
26578 +    SYNTAX_NORMAL0(TLBW, TLBW, TLBW, AVR32_V1),
26579 +    SYNTAX_NORMAL1(TNBZ, TNBZ, TNBZ, INTREG, AVR32_V1),
26580 +    SYNTAX_NORMAL2(TST, TST, TST, INTREG, INTREG, AVR32_V1),
26581 +    SYNTAX_NORMAL3(XCHG, XCHG, XCHG, INTREG, INTREG, INTREG, AVR32_V1),
26582 +    SYNTAX_NORMAL2(MEMC, MEMC, MEMC, SIGNED_CONST_W, UNSIGNED_NUMBER, AVR32_RMW),
26583 +    SYNTAX_NORMAL2(MEMS, MEMS, MEMS, SIGNED_CONST_W, UNSIGNED_NUMBER, AVR32_RMW),
26584 +    SYNTAX_NORMAL2(MEMT, MEMT, MEMT, SIGNED_CONST_W, UNSIGNED_NUMBER, AVR32_RMW),
26585 +  SYNTAX_NORMAL4 (FMAC_S,  FMAC_S,  FMAC_S,  INTREG, INTREG, INTREG, INTREG,
26586 +                  AVR32_V3FP),
26587 +  SYNTAX_NORMAL4 (FNMAC_S, FNMAC_S, FNMAC_S, INTREG, INTREG, INTREG, INTREG,
26588 +                  AVR32_V3FP),
26589 +  SYNTAX_NORMAL4 (FMSC_S,  FMSC_S,  FMSC_S,  INTREG, INTREG, INTREG, INTREG,
26590 +                  AVR32_V3FP),
26591 +  SYNTAX_NORMAL4 (FNMSC_S, FNMSC_S, FNMSC_S, INTREG, INTREG, INTREG, INTREG,
26592 +                  AVR32_V3FP),
26593 +  SYNTAX_NORMAL3 (FMUL_S,  FMUL_S,  FMUL_S,  INTREG, INTREG, INTREG, AVR32_V3FP),
26594 +  SYNTAX_NORMAL3 (FNMUL_S, FNMUL_S, FNMUL_S, INTREG, INTREG, INTREG, AVR32_V3FP),
26595 +  SYNTAX_NORMAL3 (FADD_S,  FADD_S,  FADD_S,  INTREG, INTREG, INTREG, AVR32_V3FP),
26596 +  SYNTAX_NORMAL3 (FSUB_S,  FSUB_S,  FSUB_S,  INTREG, INTREG, INTREG, AVR32_V3FP),
26597 +  SYNTAX_NORMAL2 (FCASTRS_SW, FCASTRS_SW, FCASTRS_SW, INTREG, INTREG, AVR32_V3FP),
26598 +  SYNTAX_NORMAL2 (FCASTRS_UW, FCASTRS_UW, FCASTRS_UW, INTREG, INTREG, AVR32_V3FP),
26599 +  SYNTAX_NORMAL2 (FCASTSW_S,  FCASTSW_S,  FCASTSW_S,  INTREG, INTREG, AVR32_V3FP),
26600 +  SYNTAX_NORMAL2 (FCASTUW_S,  FCASTUW_S,  FCASTUW_S,  INTREG, INTREG, AVR32_V3FP),
26601 +  SYNTAX_NORMAL2 (FCMP_S, FCMP_S, FCMP_S, INTREG, INTREG, AVR32_V3FP),
26602 +  SYNTAX_NORMAL1 (FCHK_S, FCHK_S, FCHK_S, INTREG, AVR32_V3FP),
26603 +  SYNTAX_NORMAL2 (FRCPA_S,   FRCPA_S,   FRCPA_S,   INTREG, INTREG, AVR32_V3FP),
26604 +  SYNTAX_NORMAL2 (FRSQRTA_S, FRSQRTA_S, FRSQRTA_S, INTREG, INTREG, AVR32_V3FP),
26605 +    {
26606 +      AVR32_SYNTAX_LDA_W,
26607 +      AVR32_V1, NULL, AVR32_PARSER_LDA,
26608 +      { NULL }, NULL,
26609 +      2,
26610 +      {
26611 +       AVR32_OPERAND_INTREG,
26612 +       AVR32_OPERAND_SIGNED_CONST,
26613 +      },
26614 +    },
26615 +    {
26616 +      AVR32_SYNTAX_CALL,
26617 +      AVR32_V1, NULL, AVR32_PARSER_CALL,
26618 +      { NULL }, NULL,
26619 +      1,
26620 +      {
26621 +       AVR32_OPERAND_JMPLABEL,
26622 +      },
26623 +    },
26624 +    {
26625 +      AVR32_SYNTAX_PICOSVMAC0,
26626 +      AVR32_PICO, &avr32_mnemonic_table[AVR32_MNEMONIC_PICOSVMAC], AVR32_PARSER_ALIAS,
26627 +      { .alias = &avr32_alias_table[AVR32_ALIAS_PICOSVMAC0] },
26628 +      &avr32_syntax_table[AVR32_SYNTAX_PICOSVMAC1], 4,
26629 +      {
26630 +       AVR32_OPERAND_PICO_OUT0,
26631 +       AVR32_OPERAND_PICO_IN,
26632 +       AVR32_OPERAND_PICO_IN,
26633 +       AVR32_OPERAND_PICO_IN,
26634 +      },
26635 +    },
26636 +    {
26637 +      AVR32_SYNTAX_PICOSVMAC1,
26638 +      AVR32_PICO, &avr32_mnemonic_table[AVR32_MNEMONIC_PICOSVMAC], AVR32_PARSER_ALIAS,
26639 +      { .alias = &avr32_alias_table[AVR32_ALIAS_PICOSVMAC1] },
26640 +      &avr32_syntax_table[AVR32_SYNTAX_PICOSVMAC2], 4,
26641 +      {
26642 +       AVR32_OPERAND_PICO_OUT1,
26643 +       AVR32_OPERAND_PICO_IN,
26644 +       AVR32_OPERAND_PICO_IN,
26645 +       AVR32_OPERAND_PICO_IN,
26646 +      },
26647 +    },
26648 +    {
26649 +      AVR32_SYNTAX_PICOSVMAC2,
26650 +      AVR32_PICO, &avr32_mnemonic_table[AVR32_MNEMONIC_PICOSVMAC], AVR32_PARSER_ALIAS,
26651 +      { .alias = &avr32_alias_table[AVR32_ALIAS_PICOSVMAC2] },
26652 +      &avr32_syntax_table[AVR32_SYNTAX_PICOSVMAC3], 4,
26653 +      {
26654 +       AVR32_OPERAND_PICO_OUT2,
26655 +       AVR32_OPERAND_PICO_IN,
26656 +       AVR32_OPERAND_PICO_IN,
26657 +       AVR32_OPERAND_PICO_IN,
26658 +      },
26659 +    },
26660 +    {
26661 +      AVR32_SYNTAX_PICOSVMAC3,
26662 +      AVR32_PICO, &avr32_mnemonic_table[AVR32_MNEMONIC_PICOSVMAC], AVR32_PARSER_ALIAS,
26663 +      { .alias = &avr32_alias_table[AVR32_ALIAS_PICOSVMAC3] },
26664 +      NULL, 4,
26665 +      {
26666 +       AVR32_OPERAND_PICO_OUT3,
26667 +       AVR32_OPERAND_PICO_IN,
26668 +       AVR32_OPERAND_PICO_IN,
26669 +       AVR32_OPERAND_PICO_IN,
26670 +      },
26671 +    },
26672 +    {
26673 +      AVR32_SYNTAX_PICOSVMUL0,
26674 +      AVR32_PICO, &avr32_mnemonic_table[AVR32_MNEMONIC_PICOSVMUL], AVR32_PARSER_ALIAS,
26675 +      { .alias = &avr32_alias_table[AVR32_ALIAS_PICOSVMUL0] },
26676 +      &avr32_syntax_table[AVR32_SYNTAX_PICOSVMUL1], 4,
26677 +      {
26678 +       AVR32_OPERAND_PICO_OUT0,
26679 +       AVR32_OPERAND_PICO_IN,
26680 +       AVR32_OPERAND_PICO_IN,
26681 +       AVR32_OPERAND_PICO_IN,
26682 +      },
26683 +    },
26684 +    {
26685 +      AVR32_SYNTAX_PICOSVMUL1,
26686 +      AVR32_PICO, &avr32_mnemonic_table[AVR32_MNEMONIC_PICOSVMUL], AVR32_PARSER_ALIAS,
26687 +      { .alias = &avr32_alias_table[AVR32_ALIAS_PICOSVMUL1] },
26688 +      &avr32_syntax_table[AVR32_SYNTAX_PICOSVMUL2], 4,
26689 +      {
26690 +       AVR32_OPERAND_PICO_OUT1,
26691 +       AVR32_OPERAND_PICO_IN,
26692 +       AVR32_OPERAND_PICO_IN,
26693 +       AVR32_OPERAND_PICO_IN,
26694 +      },
26695 +    },
26696 +    {
26697 +      AVR32_SYNTAX_PICOSVMUL2,
26698 +      AVR32_PICO, &avr32_mnemonic_table[AVR32_MNEMONIC_PICOSVMUL], AVR32_PARSER_ALIAS,
26699 +      { .alias = &avr32_alias_table[AVR32_ALIAS_PICOSVMUL2] },
26700 +      &avr32_syntax_table[AVR32_SYNTAX_PICOSVMUL3], 4,
26701 +      {
26702 +       AVR32_OPERAND_PICO_OUT2,
26703 +       AVR32_OPERAND_PICO_IN,
26704 +       AVR32_OPERAND_PICO_IN,
26705 +       AVR32_OPERAND_PICO_IN,
26706 +      },
26707 +    },
26708 +    {
26709 +      AVR32_SYNTAX_PICOSVMUL3,
26710 +      AVR32_PICO, &avr32_mnemonic_table[AVR32_MNEMONIC_PICOSVMUL], AVR32_PARSER_ALIAS,
26711 +      { .alias = &avr32_alias_table[AVR32_ALIAS_PICOSVMUL3] },
26712 +      NULL, 4,
26713 +      {
26714 +       AVR32_OPERAND_PICO_OUT3,
26715 +       AVR32_OPERAND_PICO_IN,
26716 +       AVR32_OPERAND_PICO_IN,
26717 +       AVR32_OPERAND_PICO_IN,
26718 +      },
26719 +    },
26720 +    {
26721 +      AVR32_SYNTAX_PICOVMAC0,
26722 +      AVR32_PICO, &avr32_mnemonic_table[AVR32_MNEMONIC_PICOVMAC], AVR32_PARSER_ALIAS,
26723 +      { .alias = &avr32_alias_table[AVR32_ALIAS_PICOVMAC0] },
26724 +      &avr32_syntax_table[AVR32_SYNTAX_PICOVMAC1], 4,
26725 +      {
26726 +       AVR32_OPERAND_PICO_OUT0,
26727 +       AVR32_OPERAND_PICO_IN,
26728 +       AVR32_OPERAND_PICO_IN,
26729 +       AVR32_OPERAND_PICO_IN,
26730 +      },
26731 +    },
26732 +    {
26733 +      AVR32_SYNTAX_PICOVMAC1,
26734 +      AVR32_PICO, &avr32_mnemonic_table[AVR32_MNEMONIC_PICOVMAC], AVR32_PARSER_ALIAS,
26735 +      { .alias = &avr32_alias_table[AVR32_ALIAS_PICOVMAC1] },
26736 +      &avr32_syntax_table[AVR32_SYNTAX_PICOVMAC2], 4,
26737 +      {
26738 +       AVR32_OPERAND_PICO_OUT1,
26739 +       AVR32_OPERAND_PICO_IN,
26740 +       AVR32_OPERAND_PICO_IN,
26741 +       AVR32_OPERAND_PICO_IN,
26742 +      },
26743 +    },
26744 +    {
26745 +      AVR32_SYNTAX_PICOVMAC2,
26746 +      AVR32_PICO, &avr32_mnemonic_table[AVR32_MNEMONIC_PICOVMAC], AVR32_PARSER_ALIAS,
26747 +      { .alias = &avr32_alias_table[AVR32_ALIAS_PICOVMAC2] },
26748 +      &avr32_syntax_table[AVR32_SYNTAX_PICOVMAC3], 4,
26749 +      {
26750 +       AVR32_OPERAND_PICO_OUT2,
26751 +       AVR32_OPERAND_PICO_IN,
26752 +       AVR32_OPERAND_PICO_IN,
26753 +       AVR32_OPERAND_PICO_IN,
26754 +      },
26755 +    },
26756 +    {
26757 +      AVR32_SYNTAX_PICOVMAC3,
26758 +      AVR32_PICO, &avr32_mnemonic_table[AVR32_MNEMONIC_PICOVMAC], AVR32_PARSER_ALIAS,
26759 +      { .alias = &avr32_alias_table[AVR32_ALIAS_PICOVMAC3] },
26760 +      NULL, 4,
26761 +      {
26762 +       AVR32_OPERAND_PICO_OUT3,
26763 +       AVR32_OPERAND_PICO_IN,
26764 +       AVR32_OPERAND_PICO_IN,
26765 +       AVR32_OPERAND_PICO_IN,
26766 +      },
26767 +    },
26768 +    {
26769 +      AVR32_SYNTAX_PICOVMUL0,
26770 +      AVR32_PICO, &avr32_mnemonic_table[AVR32_MNEMONIC_PICOVMUL], AVR32_PARSER_ALIAS,
26771 +      { .alias = &avr32_alias_table[AVR32_ALIAS_PICOVMUL0] },
26772 +      &avr32_syntax_table[AVR32_SYNTAX_PICOVMUL1], 4,
26773 +      {
26774 +       AVR32_OPERAND_PICO_OUT0,
26775 +       AVR32_OPERAND_PICO_IN,
26776 +       AVR32_OPERAND_PICO_IN,
26777 +       AVR32_OPERAND_PICO_IN,
26778 +      },
26779 +    },
26780 +    {
26781 +      AVR32_SYNTAX_PICOVMUL1,
26782 +      AVR32_PICO, &avr32_mnemonic_table[AVR32_MNEMONIC_PICOVMUL], AVR32_PARSER_ALIAS,
26783 +      { .alias = &avr32_alias_table[AVR32_ALIAS_PICOVMUL1] },
26784 +      &avr32_syntax_table[AVR32_SYNTAX_PICOVMUL2], 4,
26785 +      {
26786 +       AVR32_OPERAND_PICO_OUT1,
26787 +       AVR32_OPERAND_PICO_IN,
26788 +       AVR32_OPERAND_PICO_IN,
26789 +       AVR32_OPERAND_PICO_IN,
26790 +      },
26791 +    },
26792 +    {
26793 +      AVR32_SYNTAX_PICOVMUL2,
26794 +      AVR32_PICO, &avr32_mnemonic_table[AVR32_MNEMONIC_PICOVMUL], AVR32_PARSER_ALIAS,
26795 +      { .alias = &avr32_alias_table[AVR32_ALIAS_PICOVMUL2] },
26796 +      &avr32_syntax_table[AVR32_SYNTAX_PICOVMUL3], 4,
26797 +      {
26798 +       AVR32_OPERAND_PICO_OUT2,
26799 +       AVR32_OPERAND_PICO_IN,
26800 +       AVR32_OPERAND_PICO_IN,
26801 +       AVR32_OPERAND_PICO_IN,
26802 +      },
26803 +    },
26804 +    {
26805 +      AVR32_SYNTAX_PICOVMUL3,
26806 +      AVR32_PICO, &avr32_mnemonic_table[AVR32_MNEMONIC_PICOVMUL], AVR32_PARSER_ALIAS,
26807 +      { .alias = &avr32_alias_table[AVR32_ALIAS_PICOVMUL3] },
26808 +      NULL, 4,
26809 +      {
26810 +       AVR32_OPERAND_PICO_OUT3,
26811 +       AVR32_OPERAND_PICO_IN,
26812 +       AVR32_OPERAND_PICO_IN,
26813 +       AVR32_OPERAND_PICO_IN,
26814 +      },
26815 +    },
26816 +    {
26817 +      AVR32_SYNTAX_PICOLD_D2,
26818 +      AVR32_PICO, &avr32_mnemonic_table[AVR32_MNEMONIC_PICOLD_D], AVR32_PARSER_ALIAS,
26819 +      { .alias = &avr32_alias_table[AVR32_ALIAS_PICOLD_D2] },
26820 +      &avr32_syntax_table[AVR32_SYNTAX_PICOLD_D3], 2,
26821 +      {
26822 +       AVR32_OPERAND_PICO_REG_D,
26823 +       AVR32_OPERAND_INTREG_PREDEC,
26824 +      },
26825 +    },
26826 +    {
26827 +      AVR32_SYNTAX_PICOLD_D3,
26828 +      AVR32_PICO, &avr32_mnemonic_table[AVR32_MNEMONIC_PICOLD_D], AVR32_PARSER_ALIAS,
26829 +      { .alias = &avr32_alias_table[AVR32_ALIAS_PICOLD_D3] },
26830 +      &avr32_syntax_table[AVR32_SYNTAX_PICOLD_D1], 2,
26831 +      {
26832 +       AVR32_OPERAND_PICO_REG_D,
26833 +       AVR32_OPERAND_INTREG_INDEX,
26834 +      },
26835 +    },
26836 +    {
26837 +      AVR32_SYNTAX_PICOLD_D1,
26838 +      AVR32_PICO, &avr32_mnemonic_table[AVR32_MNEMONIC_PICOLD_D], AVR32_PARSER_ALIAS,
26839 +      { .alias = &avr32_alias_table[AVR32_ALIAS_PICOLD_D1] },
26840 +      NULL, 2,
26841 +      {
26842 +       AVR32_OPERAND_PICO_REG_D,
26843 +       AVR32_OPERAND_INTREG_UDISP_W,
26844 +      },
26845 +    },
26846 +    {
26847 +      AVR32_SYNTAX_PICOLD_W2,
26848 +      AVR32_PICO, &avr32_mnemonic_table[AVR32_MNEMONIC_PICOLD_W], AVR32_PARSER_ALIAS,
26849 +      { .alias = &avr32_alias_table[AVR32_ALIAS_PICOLD_W2] },
26850 +      &avr32_syntax_table[AVR32_SYNTAX_PICOLD_W3], 2,
26851 +      {
26852 +       AVR32_OPERAND_PICO_REG_W,
26853 +       AVR32_OPERAND_INTREG_PREDEC,
26854 +      },
26855 +    },
26856 +    {
26857 +      AVR32_SYNTAX_PICOLD_W3,
26858 +      AVR32_PICO, &avr32_mnemonic_table[AVR32_MNEMONIC_PICOLD_W], AVR32_PARSER_ALIAS,
26859 +      { .alias = &avr32_alias_table[AVR32_ALIAS_PICOLD_W3] },
26860 +      &avr32_syntax_table[AVR32_SYNTAX_PICOLD_W1], 2,
26861 +      {
26862 +       AVR32_OPERAND_PICO_REG_W,
26863 +       AVR32_OPERAND_INTREG_INDEX,
26864 +      },
26865 +    },
26866 +    {
26867 +      AVR32_SYNTAX_PICOLD_W1,
26868 +      AVR32_PICO, &avr32_mnemonic_table[AVR32_MNEMONIC_PICOLD_W], AVR32_PARSER_ALIAS,
26869 +      { .alias = &avr32_alias_table[AVR32_ALIAS_PICOLD_W1] },
26870 +      NULL, 2,
26871 +      {
26872 +       AVR32_OPERAND_PICO_REG_W,
26873 +       AVR32_OPERAND_INTREG_UDISP_W,
26874 +      },
26875 +    },
26876 +    {
26877 +      AVR32_SYNTAX_PICOLDM_D,
26878 +      AVR32_PICO, &avr32_mnemonic_table[AVR32_MNEMONIC_PICOLDM_D], AVR32_PARSER_ALIAS,
26879 +      { .alias = &avr32_alias_table[AVR32_ALIAS_PICOLDM_D] },
26880 +      &avr32_syntax_table[AVR32_SYNTAX_PICOLDM_D_PU], -2,
26881 +      {
26882 +       AVR32_OPERAND_INTREG,
26883 +       AVR32_OPERAND_PICO_REGLIST_D,
26884 +      },
26885 +    },
26886 +    {
26887 +      AVR32_SYNTAX_PICOLDM_D_PU,
26888 +      AVR32_PICO, &avr32_mnemonic_table[AVR32_MNEMONIC_PICOLDM_D], AVR32_PARSER_ALIAS,
26889 +      { .alias = &avr32_alias_table[AVR32_ALIAS_PICOLDM_D_PU] },
26890 +      NULL, -2,
26891 +      {
26892 +       AVR32_OPERAND_INTREG_POSTINC,
26893 +       AVR32_OPERAND_PICO_REGLIST_D,
26894 +      },
26895 +    },
26896 +    {
26897 +      AVR32_SYNTAX_PICOLDM_W,
26898 +      AVR32_PICO, &avr32_mnemonic_table[AVR32_MNEMONIC_PICOLDM_W], AVR32_PARSER_ALIAS,
26899 +      { .alias = &avr32_alias_table[AVR32_ALIAS_PICOLDM_W] },
26900 +      &avr32_syntax_table[AVR32_SYNTAX_PICOLDM_W_PU], -2,
26901 +      {
26902 +       AVR32_OPERAND_INTREG,
26903 +       AVR32_OPERAND_PICO_REGLIST_W,
26904 +      },
26905 +    },
26906 +    {
26907 +      AVR32_SYNTAX_PICOLDM_W_PU,
26908 +      AVR32_PICO, &avr32_mnemonic_table[AVR32_MNEMONIC_PICOLDM_W], AVR32_PARSER_ALIAS,
26909 +      { .alias = &avr32_alias_table[AVR32_ALIAS_PICOLDM_W_PU] },
26910 +      NULL, -2,
26911 +      {
26912 +       AVR32_OPERAND_INTREG_POSTINC,
26913 +       AVR32_OPERAND_PICO_REGLIST_W,
26914 +      },
26915 +    },
26916 +    {
26917 +      AVR32_SYNTAX_PICOMV_D1,
26918 +      AVR32_PICO, &avr32_mnemonic_table[AVR32_MNEMONIC_PICOMV_D], AVR32_PARSER_ALIAS,
26919 +      { .alias = &avr32_alias_table[AVR32_ALIAS_PICOMV_D1] },
26920 +      &avr32_syntax_table[AVR32_SYNTAX_PICOMV_D2], 2,
26921 +      {
26922 +       AVR32_OPERAND_DWREG,
26923 +       AVR32_OPERAND_PICO_REG_D,
26924 +      },
26925 +    },
26926 +    {
26927 +      AVR32_SYNTAX_PICOMV_D2,
26928 +      AVR32_PICO, &avr32_mnemonic_table[AVR32_MNEMONIC_PICOMV_D], AVR32_PARSER_ALIAS,
26929 +      { .alias = &avr32_alias_table[AVR32_ALIAS_PICOMV_D2] },
26930 +      NULL, 2,
26931 +      {
26932 +       AVR32_OPERAND_PICO_REG_D,
26933 +       AVR32_OPERAND_DWREG,
26934 +      },
26935 +    },
26936 +    {
26937 +      AVR32_SYNTAX_PICOMV_W1,
26938 +      AVR32_PICO, &avr32_mnemonic_table[AVR32_MNEMONIC_PICOMV_W], AVR32_PARSER_ALIAS,
26939 +      { .alias = &avr32_alias_table[AVR32_ALIAS_PICOMV_W1] },
26940 +      &avr32_syntax_table[AVR32_SYNTAX_PICOMV_W2], 2,
26941 +      {
26942 +       AVR32_OPERAND_INTREG,
26943 +       AVR32_OPERAND_PICO_REG_W,
26944 +      },
26945 +    },
26946 +    {
26947 +      AVR32_SYNTAX_PICOMV_W2,
26948 +      AVR32_PICO, &avr32_mnemonic_table[AVR32_MNEMONIC_PICOMV_W], AVR32_PARSER_ALIAS,
26949 +      { .alias = &avr32_alias_table[AVR32_ALIAS_PICOMV_W2] },
26950 +      NULL, 2,
26951 +      {
26952 +       AVR32_OPERAND_PICO_REG_W,
26953 +       AVR32_OPERAND_INTREG,
26954 +      },
26955 +    },
26956 +    {
26957 +      AVR32_SYNTAX_PICOST_D2,
26958 +      AVR32_PICO, &avr32_mnemonic_table[AVR32_MNEMONIC_PICOST_D], AVR32_PARSER_ALIAS,
26959 +      { .alias = &avr32_alias_table[AVR32_ALIAS_PICOST_D2] },
26960 +      &avr32_syntax_table[AVR32_SYNTAX_PICOST_D3], 2,
26961 +      {
26962 +       AVR32_OPERAND_INTREG_POSTINC,
26963 +       AVR32_OPERAND_PICO_REG_D,
26964 +      },
26965 +    },
26966 +    {
26967 +      AVR32_SYNTAX_PICOST_D3,
26968 +      AVR32_PICO, &avr32_mnemonic_table[AVR32_MNEMONIC_PICOST_D], AVR32_PARSER_ALIAS,
26969 +      { .alias = &avr32_alias_table[AVR32_ALIAS_PICOST_D3] },
26970 +      &avr32_syntax_table[AVR32_SYNTAX_PICOST_D1], 2,
26971 +      {
26972 +       AVR32_OPERAND_INTREG_INDEX,
26973 +       AVR32_OPERAND_PICO_REG_D,
26974 +      },
26975 +    },
26976 +    {
26977 +      AVR32_SYNTAX_PICOST_D1,
26978 +      AVR32_PICO, &avr32_mnemonic_table[AVR32_MNEMONIC_PICOST_D], AVR32_PARSER_ALIAS,
26979 +      { .alias = &avr32_alias_table[AVR32_ALIAS_PICOST_D1] },
26980 +      NULL, 2,
26981 +      {
26982 +       AVR32_OPERAND_INTREG_UDISP_W,
26983 +       AVR32_OPERAND_PICO_REG_D,
26984 +      },
26985 +    },
26986 +    {
26987 +      AVR32_SYNTAX_PICOST_W2,
26988 +      AVR32_PICO, &avr32_mnemonic_table[AVR32_MNEMONIC_PICOST_W], AVR32_PARSER_ALIAS,
26989 +      { .alias = &avr32_alias_table[AVR32_ALIAS_PICOST_W2] },
26990 +      &avr32_syntax_table[AVR32_SYNTAX_PICOST_W3], 2,
26991 +      {
26992 +       AVR32_OPERAND_INTREG_POSTINC,
26993 +       AVR32_OPERAND_PICO_REG_W,
26994 +      },
26995 +    },
26996 +    {
26997 +      AVR32_SYNTAX_PICOST_W3,
26998 +      AVR32_PICO, &avr32_mnemonic_table[AVR32_MNEMONIC_PICOST_W], AVR32_PARSER_ALIAS,
26999 +      { .alias = &avr32_alias_table[AVR32_ALIAS_PICOST_W3] },
27000 +      &avr32_syntax_table[AVR32_SYNTAX_PICOST_W1], 2,
27001 +      {
27002 +       AVR32_OPERAND_INTREG_INDEX,
27003 +       AVR32_OPERAND_PICO_REG_W,
27004 +      },
27005 +    },
27006 +    {
27007 +      AVR32_SYNTAX_PICOST_W1,
27008 +      AVR32_PICO, &avr32_mnemonic_table[AVR32_MNEMONIC_PICOST_W], AVR32_PARSER_ALIAS,
27009 +      { .alias = &avr32_alias_table[AVR32_ALIAS_PICOST_W1] },
27010 +      NULL, 2,
27011 +      {
27012 +       AVR32_OPERAND_INTREG_UDISP_W,
27013 +       AVR32_OPERAND_PICO_REG_W,
27014 +      },
27015 +    },
27016 +    {
27017 +      AVR32_SYNTAX_PICOSTM_D,
27018 +      AVR32_PICO, &avr32_mnemonic_table[AVR32_MNEMONIC_PICOSTM_D], AVR32_PARSER_ALIAS,
27019 +      { .alias = &avr32_alias_table[AVR32_ALIAS_PICOSTM_D] },
27020 +      &avr32_syntax_table[AVR32_SYNTAX_PICOSTM_D_PU], -2,
27021 +      {
27022 +       AVR32_OPERAND_INTREG,
27023 +       AVR32_OPERAND_PICO_REGLIST_D,
27024 +      },
27025 +    },
27026 +    {
27027 +      AVR32_SYNTAX_PICOSTM_D_PU,
27028 +      AVR32_PICO, &avr32_mnemonic_table[AVR32_MNEMONIC_PICOSTM_D], AVR32_PARSER_ALIAS,
27029 +      { .alias = &avr32_alias_table[AVR32_ALIAS_PICOSTM_D_PU] },
27030 +      NULL, -2,
27031 +      {
27032 +       AVR32_OPERAND_INTREG_PREDEC,
27033 +       AVR32_OPERAND_PICO_REGLIST_D,
27034 +      },
27035 +    },
27036 +    {
27037 +      AVR32_SYNTAX_PICOSTM_W,
27038 +      AVR32_PICO, &avr32_mnemonic_table[AVR32_MNEMONIC_PICOSTM_W], AVR32_PARSER_ALIAS,
27039 +      { .alias = &avr32_alias_table[AVR32_ALIAS_PICOSTM_W] },
27040 +      &avr32_syntax_table[AVR32_SYNTAX_PICOSTM_W_PU], -2,
27041 +      {
27042 +       AVR32_OPERAND_INTREG,
27043 +       AVR32_OPERAND_PICO_REGLIST_W,
27044 +      },
27045 +    },
27046 +    {
27047 +      AVR32_SYNTAX_PICOSTM_W_PU,
27048 +      AVR32_PICO, &avr32_mnemonic_table[AVR32_MNEMONIC_PICOSTM_W], AVR32_PARSER_ALIAS,
27049 +      { .alias = &avr32_alias_table[AVR32_ALIAS_PICOSTM_W_PU] },
27050 +      NULL, -2,
27051 +      {
27052 +       AVR32_OPERAND_INTREG_PREDEC,
27053 +       AVR32_OPERAND_PICO_REGLIST_W,
27054 +      },
27055 +    },
27056 +    SYNTAX_NORMAL2(RSUBEQ, RSUBEQ, RSUBEQ, INTREG, SIGNED_CONST, AVR32_V1),
27057 +    SYNTAX_NORMAL2(RSUBNE, RSUBNE, RSUBNE, INTREG, SIGNED_CONST, AVR32_V2),
27058 +    SYNTAX_NORMAL2(RSUBCC, RSUBCC, RSUBCC, INTREG, SIGNED_CONST, AVR32_V2),
27059 +    SYNTAX_NORMAL2(RSUBCS, RSUBCS, RSUBCS, INTREG, SIGNED_CONST, AVR32_V2),
27060 +    SYNTAX_NORMAL2(RSUBGE, RSUBGE, RSUBGE, INTREG, SIGNED_CONST, AVR32_V2),
27061 +    SYNTAX_NORMAL2(RSUBLT, RSUBLT, RSUBLT, INTREG, SIGNED_CONST, AVR32_V2),
27062 +    SYNTAX_NORMAL2(RSUBMI, RSUBMI, RSUBMI, INTREG, SIGNED_CONST, AVR32_V2),
27063 +    SYNTAX_NORMAL2(RSUBPL, RSUBPL, RSUBPL, INTREG, SIGNED_CONST, AVR32_V2),
27064 +    SYNTAX_NORMAL2(RSUBLS, RSUBLS, RSUBLS, INTREG, SIGNED_CONST, AVR32_V2),
27065 +    SYNTAX_NORMAL2(RSUBGT, RSUBGT, RSUBGT, INTREG, SIGNED_CONST, AVR32_V2),
27066 +    SYNTAX_NORMAL2(RSUBLE, RSUBLE, RSUBLE, INTREG, SIGNED_CONST, AVR32_V2),
27067 +    SYNTAX_NORMAL2(RSUBHI, RSUBHI, RSUBHI, INTREG, SIGNED_CONST, AVR32_V2),
27068 +    SYNTAX_NORMAL2(RSUBVS, RSUBVS, RSUBVS, INTREG, SIGNED_CONST, AVR32_V2),
27069 +    SYNTAX_NORMAL2(RSUBVC, RSUBVC, RSUBVC, INTREG, SIGNED_CONST, AVR32_V2),
27070 +    SYNTAX_NORMAL2(RSUBQS, RSUBQS, RSUBQS, INTREG, SIGNED_CONST, AVR32_V2),
27071 +    SYNTAX_NORMAL2(RSUBAL, RSUBAL, RSUBAL, INTREG, SIGNED_CONST, AVR32_V2),
27072 +    SYNTAX_NORMAL2(RSUBHS, RSUBHS, RSUBCC, INTREG, SIGNED_CONST, AVR32_V2),
27073 +    SYNTAX_NORMAL2(RSUBLO, RSUBLO, RSUBCS, INTREG, SIGNED_CONST, AVR32_V2),
27074 +    SYNTAX_NORMAL3(ADDEQ, ADDEQ, ADDEQ, INTREG, INTREG, INTREG, AVR32_V2),
27075 +    SYNTAX_NORMAL3(ADDNE, ADDNE, ADDNE, INTREG, INTREG, INTREG, AVR32_V2),
27076 +    SYNTAX_NORMAL3(ADDCC, ADDCC, ADDCC, INTREG, INTREG, INTREG, AVR32_V2),
27077 +    SYNTAX_NORMAL3(ADDCS, ADDCS, ADDCS, INTREG, INTREG, INTREG, AVR32_V2),
27078 +    SYNTAX_NORMAL3(ADDGE, ADDGE, ADDGE, INTREG, INTREG, INTREG, AVR32_V2),
27079 +    SYNTAX_NORMAL3(ADDLT, ADDLT, ADDLT, INTREG, INTREG, INTREG, AVR32_V2),
27080 +    SYNTAX_NORMAL3(ADDMI, ADDMI, ADDMI, INTREG, INTREG, INTREG, AVR32_V2),
27081 +    SYNTAX_NORMAL3(ADDPL, ADDPL, ADDPL, INTREG, INTREG, INTREG, AVR32_V2),
27082 +    SYNTAX_NORMAL3(ADDLS, ADDLS, ADDLS, INTREG, INTREG, INTREG, AVR32_V2),
27083 +    SYNTAX_NORMAL3(ADDGT, ADDGT, ADDGT, INTREG, INTREG, INTREG, AVR32_V2),
27084 +    SYNTAX_NORMAL3(ADDLE, ADDLE, ADDLE, INTREG, INTREG, INTREG, AVR32_V2),
27085 +    SYNTAX_NORMAL3(ADDHI, ADDHI, ADDHI, INTREG, INTREG, INTREG, AVR32_V2),
27086 +    SYNTAX_NORMAL3(ADDVS, ADDVS, ADDVS, INTREG, INTREG, INTREG, AVR32_V2),
27087 +    SYNTAX_NORMAL3(ADDVC, ADDVC, ADDVC, INTREG, INTREG, INTREG, AVR32_V2),
27088 +    SYNTAX_NORMAL3(ADDQS, ADDQS, ADDQS, INTREG, INTREG, INTREG, AVR32_V2),
27089 +    SYNTAX_NORMAL3(ADDAL, ADDAL, ADDAL, INTREG, INTREG, INTREG, AVR32_V2),
27090 +    SYNTAX_NORMAL3(ADDHS, ADDHS, ADDCC, INTREG, INTREG, INTREG, AVR32_V2),
27091 +    SYNTAX_NORMAL3(ADDLO, ADDLO, ADDCS, INTREG, INTREG, INTREG, AVR32_V2),
27092 +    SYNTAX_NORMAL3(SUB2EQ, SUBEQ, SUB2EQ, INTREG, INTREG, INTREG, AVR32_V2),
27093 +    SYNTAX_NORMAL3(SUB2NE, SUBNE, SUB2NE, INTREG, INTREG, INTREG, AVR32_V2),
27094 +    SYNTAX_NORMAL3(SUB2CC, SUBCC, SUB2CC, INTREG, INTREG, INTREG, AVR32_V2),
27095 +    SYNTAX_NORMAL3(SUB2CS, SUBCS, SUB2CS, INTREG, INTREG, INTREG, AVR32_V2),
27096 +    SYNTAX_NORMAL3(SUB2GE, SUBGE, SUB2GE, INTREG, INTREG, INTREG, AVR32_V2),
27097 +    SYNTAX_NORMAL3(SUB2LT, SUBLT, SUB2LT, INTREG, INTREG, INTREG, AVR32_V2),
27098 +    SYNTAX_NORMAL3(SUB2MI, SUBMI, SUB2MI, INTREG, INTREG, INTREG, AVR32_V2),
27099 +    SYNTAX_NORMAL3(SUB2PL, SUBPL, SUB2PL, INTREG, INTREG, INTREG, AVR32_V2),
27100 +    SYNTAX_NORMAL3(SUB2LS, SUBLS, SUB2LS, INTREG, INTREG, INTREG, AVR32_V2),
27101 +    SYNTAX_NORMAL3(SUB2GT, SUBGT, SUB2GT, INTREG, INTREG, INTREG, AVR32_V2),
27102 +    SYNTAX_NORMAL3(SUB2LE, SUBLE, SUB2LE, INTREG, INTREG, INTREG, AVR32_V2),
27103 +    SYNTAX_NORMAL3(SUB2HI, SUBHI, SUB2HI, INTREG, INTREG, INTREG, AVR32_V2),
27104 +    SYNTAX_NORMAL3(SUB2VS, SUBVS, SUB2VS, INTREG, INTREG, INTREG, AVR32_V2),
27105 +    SYNTAX_NORMAL3(SUB2VC, SUBVC, SUB2VC, INTREG, INTREG, INTREG, AVR32_V2),
27106 +    SYNTAX_NORMAL3(SUB2QS, SUBQS, SUB2QS, INTREG, INTREG, INTREG, AVR32_V2),
27107 +    SYNTAX_NORMAL3(SUB2AL, SUBAL, SUB2AL, INTREG, INTREG, INTREG, AVR32_V2),
27108 +    SYNTAX_NORMAL3(SUB2HS, SUBHS, SUB2CC, INTREG, INTREG, INTREG, AVR32_V2),
27109 +    SYNTAX_NORMAL3(SUB2LO, SUBLO, SUB2CS, INTREG, INTREG, INTREG, AVR32_V2),
27110 +    SYNTAX_NORMAL3(ANDEQ, ANDEQ, ANDEQ, INTREG, INTREG, INTREG, AVR32_V2),
27111 +    SYNTAX_NORMAL3(ANDNE, ANDNE, ANDNE, INTREG, INTREG, INTREG, AVR32_V2),
27112 +    SYNTAX_NORMAL3(ANDCC, ANDCC, ANDCC, INTREG, INTREG, INTREG, AVR32_V2),
27113 +    SYNTAX_NORMAL3(ANDCS, ANDCS, ANDCS, INTREG, INTREG, INTREG, AVR32_V2),
27114 +    SYNTAX_NORMAL3(ANDGE, ANDGE, ANDGE, INTREG, INTREG, INTREG, AVR32_V2),
27115 +    SYNTAX_NORMAL3(ANDLT, ANDLT, ANDLT, INTREG, INTREG, INTREG, AVR32_V2),
27116 +    SYNTAX_NORMAL3(ANDMI, ANDMI, ANDMI, INTREG, INTREG, INTREG, AVR32_V2),
27117 +    SYNTAX_NORMAL3(ANDPL, ANDPL, ANDPL, INTREG, INTREG, INTREG, AVR32_V2),
27118 +    SYNTAX_NORMAL3(ANDLS, ANDLS, ANDLS, INTREG, INTREG, INTREG, AVR32_V2),
27119 +    SYNTAX_NORMAL3(ANDGT, ANDGT, ANDGT, INTREG, INTREG, INTREG, AVR32_V2),
27120 +    SYNTAX_NORMAL3(ANDLE, ANDLE, ANDLE, INTREG, INTREG, INTREG, AVR32_V2),
27121 +    SYNTAX_NORMAL3(ANDHI, ANDHI, ANDHI, INTREG, INTREG, INTREG, AVR32_V2),
27122 +    SYNTAX_NORMAL3(ANDVS, ANDVS, ANDVS, INTREG, INTREG, INTREG, AVR32_V2),
27123 +    SYNTAX_NORMAL3(ANDVC, ANDVC, ANDVC, INTREG, INTREG, INTREG, AVR32_V2),
27124 +    SYNTAX_NORMAL3(ANDQS, ANDQS, ANDQS, INTREG, INTREG, INTREG, AVR32_V2),
27125 +    SYNTAX_NORMAL3(ANDAL, ANDAL, ANDAL, INTREG, INTREG, INTREG, AVR32_V2),
27126 +    SYNTAX_NORMAL3(ANDHS, ANDHS, ANDCC, INTREG, INTREG, INTREG, AVR32_V2),
27127 +    SYNTAX_NORMAL3(ANDLO, ANDLO, ANDCS, INTREG, INTREG, INTREG, AVR32_V2),
27128 +    SYNTAX_NORMAL3(OREQ, OREQ, OREQ, INTREG, INTREG, INTREG, AVR32_V2),
27129 +    SYNTAX_NORMAL3(ORNE, ORNE, ORNE, INTREG, INTREG, INTREG, AVR32_V2),
27130 +    SYNTAX_NORMAL3(ORCC, ORCC, ORCC, INTREG, INTREG, INTREG, AVR32_V2),
27131 +    SYNTAX_NORMAL3(ORCS, ORCS, ORCS, INTREG, INTREG, INTREG, AVR32_V2),
27132 +    SYNTAX_NORMAL3(ORGE, ORGE, ORGE, INTREG, INTREG, INTREG, AVR32_V2),
27133 +    SYNTAX_NORMAL3(ORLT, ORLT, ORLT, INTREG, INTREG, INTREG, AVR32_V2),
27134 +    SYNTAX_NORMAL3(ORMI, ORMI, ORMI, INTREG, INTREG, INTREG, AVR32_V2),
27135 +    SYNTAX_NORMAL3(ORPL, ORPL, ORPL, INTREG, INTREG, INTREG, AVR32_V2),
27136 +    SYNTAX_NORMAL3(ORLS, ORLS, ORLS, INTREG, INTREG, INTREG, AVR32_V2),
27137 +    SYNTAX_NORMAL3(ORGT, ORGT, ORGT, INTREG, INTREG, INTREG, AVR32_V2),
27138 +    SYNTAX_NORMAL3(ORLE, ORLE, ORLE, INTREG, INTREG, INTREG, AVR32_V2),
27139 +    SYNTAX_NORMAL3(ORHI, ORHI, ORHI, INTREG, INTREG, INTREG, AVR32_V2),
27140 +    SYNTAX_NORMAL3(ORVS, ORVS, ORVS, INTREG, INTREG, INTREG, AVR32_V2),
27141 +    SYNTAX_NORMAL3(ORVC, ORVC, ORVC, INTREG, INTREG, INTREG, AVR32_V2),
27142 +    SYNTAX_NORMAL3(ORQS, ORQS, ORQS, INTREG, INTREG, INTREG, AVR32_V2),
27143 +    SYNTAX_NORMAL3(ORAL, ORAL, ORAL, INTREG, INTREG, INTREG, AVR32_V2),
27144 +    SYNTAX_NORMAL3(ORHS, ORHS, ORCC, INTREG, INTREG, INTREG, AVR32_V2),
27145 +    SYNTAX_NORMAL3(ORLO, ORLO, ORCS, INTREG, INTREG, INTREG, AVR32_V2),
27146 +    SYNTAX_NORMAL3(EOREQ, EOREQ, EOREQ, INTREG, INTREG, INTREG, AVR32_V2),
27147 +    SYNTAX_NORMAL3(EORNE, EORNE, EORNE, INTREG, INTREG, INTREG, AVR32_V2),
27148 +    SYNTAX_NORMAL3(EORCC, EORCC, EORCC, INTREG, INTREG, INTREG, AVR32_V2),
27149 +    SYNTAX_NORMAL3(EORCS, EORCS, EORCS, INTREG, INTREG, INTREG, AVR32_V2),
27150 +    SYNTAX_NORMAL3(EORGE, EORGE, EORGE, INTREG, INTREG, INTREG, AVR32_V2),
27151 +    SYNTAX_NORMAL3(EORLT, EORLT, EORLT, INTREG, INTREG, INTREG, AVR32_V2),
27152 +    SYNTAX_NORMAL3(EORMI, EORMI, EORMI, INTREG, INTREG, INTREG, AVR32_V2),
27153 +    SYNTAX_NORMAL3(EORPL, EORPL, EORPL, INTREG, INTREG, INTREG, AVR32_V2),
27154 +    SYNTAX_NORMAL3(EORLS, EORLS, EORLS, INTREG, INTREG, INTREG, AVR32_V2),
27155 +    SYNTAX_NORMAL3(EORGT, EORGT, EORGT, INTREG, INTREG, INTREG, AVR32_V2),
27156 +    SYNTAX_NORMAL3(EORLE, EORLE, EORLE, INTREG, INTREG, INTREG, AVR32_V2),
27157 +    SYNTAX_NORMAL3(EORHI, EORHI, EORHI, INTREG, INTREG, INTREG, AVR32_V2),
27158 +    SYNTAX_NORMAL3(EORVS, EORVS, EORVS, INTREG, INTREG, INTREG, AVR32_V2),
27159 +    SYNTAX_NORMAL3(EORVC, EORVC, EORVC, INTREG, INTREG, INTREG, AVR32_V2),
27160 +    SYNTAX_NORMAL3(EORQS, EORQS, EORQS, INTREG, INTREG, INTREG, AVR32_V2),
27161 +    SYNTAX_NORMAL3(EORAL, EORAL, EORAL, INTREG, INTREG, INTREG, AVR32_V2),
27162 +    SYNTAX_NORMAL3(EORHS, EORHS, EORCC, INTREG, INTREG, INTREG, AVR32_V2),
27163 +    SYNTAX_NORMAL3(EORLO, EORLO, EORCS, INTREG, INTREG, INTREG, AVR32_V2),
27164 +    SYNTAX_NORMAL2(LD_WEQ, LD_WEQ, LD_WEQ, INTREG, INTREG_UDISP_W, AVR32_V2),
27165 +    SYNTAX_NORMAL2(LD_WNE, LD_WNE, LD_WNE, INTREG, INTREG_UDISP_W, AVR32_V2),
27166 +    SYNTAX_NORMAL2(LD_WCC, LD_WCC, LD_WCC, INTREG, INTREG_UDISP_W, AVR32_V2),
27167 +    SYNTAX_NORMAL2(LD_WCS, LD_WCS, LD_WCS, INTREG, INTREG_UDISP_W, AVR32_V2),
27168 +    SYNTAX_NORMAL2(LD_WGE, LD_WGE, LD_WGE, INTREG, INTREG_UDISP_W, AVR32_V2),
27169 +    SYNTAX_NORMAL2(LD_WLT, LD_WLT, LD_WLT, INTREG, INTREG_UDISP_W, AVR32_V2),
27170 +    SYNTAX_NORMAL2(LD_WMI, LD_WMI, LD_WMI, INTREG, INTREG_UDISP_W, AVR32_V2),
27171 +    SYNTAX_NORMAL2(LD_WPL, LD_WPL, LD_WPL, INTREG, INTREG_UDISP_W, AVR32_V2),
27172 +    SYNTAX_NORMAL2(LD_WLS, LD_WLS, LD_WLS, INTREG, INTREG_UDISP_W, AVR32_V2),
27173 +    SYNTAX_NORMAL2(LD_WGT, LD_WGT, LD_WGT, INTREG, INTREG_UDISP_W, AVR32_V2),
27174 +    SYNTAX_NORMAL2(LD_WLE, LD_WLE, LD_WLE, INTREG, INTREG_UDISP_W, AVR32_V2),
27175 +    SYNTAX_NORMAL2(LD_WHI, LD_WHI, LD_WHI, INTREG, INTREG_UDISP_W, AVR32_V2),
27176 +    SYNTAX_NORMAL2(LD_WVS, LD_WVS, LD_WVS, INTREG, INTREG_UDISP_W, AVR32_V2),
27177 +    SYNTAX_NORMAL2(LD_WVC, LD_WVC, LD_WVC, INTREG, INTREG_UDISP_W, AVR32_V2),
27178 +    SYNTAX_NORMAL2(LD_WQS, LD_WQS, LD_WQS, INTREG, INTREG_UDISP_W, AVR32_V2),
27179 +    SYNTAX_NORMAL2(LD_WAL, LD_WAL, LD_WAL, INTREG, INTREG_UDISP_W, AVR32_V2),
27180 +    SYNTAX_NORMAL2(LD_WHS, LD_WHS, LD_WCC, INTREG, INTREG_UDISP_W, AVR32_V2),
27181 +    SYNTAX_NORMAL2(LD_WLO, LD_WLO, LD_WCS, INTREG, INTREG_UDISP_W, AVR32_V2),
27182 +    SYNTAX_NORMAL2(LD_SHEQ, LD_SHEQ, LD_SHEQ, INTREG, INTREG_UDISP_H, AVR32_V2),
27183 +    SYNTAX_NORMAL2(LD_SHNE, LD_SHNE, LD_SHNE, INTREG, INTREG_UDISP_H, AVR32_V2),
27184 +    SYNTAX_NORMAL2(LD_SHCC, LD_SHCC, LD_SHCC, INTREG, INTREG_UDISP_H, AVR32_V2),
27185 +    SYNTAX_NORMAL2(LD_SHCS, LD_SHCS, LD_SHCS, INTREG, INTREG_UDISP_H, AVR32_V2),
27186 +    SYNTAX_NORMAL2(LD_SHGE, LD_SHGE, LD_SHGE, INTREG, INTREG_UDISP_H, AVR32_V2),
27187 +    SYNTAX_NORMAL2(LD_SHLT, LD_SHLT, LD_SHLT, INTREG, INTREG_UDISP_H, AVR32_V2),
27188 +    SYNTAX_NORMAL2(LD_SHMI, LD_SHMI, LD_SHMI, INTREG, INTREG_UDISP_H, AVR32_V2),
27189 +    SYNTAX_NORMAL2(LD_SHPL, LD_SHPL, LD_SHPL, INTREG, INTREG_UDISP_H, AVR32_V2),
27190 +    SYNTAX_NORMAL2(LD_SHLS, LD_SHLS, LD_SHLS, INTREG, INTREG_UDISP_H, AVR32_V2),
27191 +    SYNTAX_NORMAL2(LD_SHGT, LD_SHGT, LD_SHGT, INTREG, INTREG_UDISP_H, AVR32_V2),
27192 +    SYNTAX_NORMAL2(LD_SHLE, LD_SHLE, LD_SHLE, INTREG, INTREG_UDISP_H, AVR32_V2),
27193 +    SYNTAX_NORMAL2(LD_SHHI, LD_SHHI, LD_SHHI, INTREG, INTREG_UDISP_H, AVR32_V2),
27194 +    SYNTAX_NORMAL2(LD_SHVS, LD_SHVS, LD_SHVS, INTREG, INTREG_UDISP_H, AVR32_V2),
27195 +    SYNTAX_NORMAL2(LD_SHVC, LD_SHVC, LD_SHVC, INTREG, INTREG_UDISP_H, AVR32_V2),
27196 +    SYNTAX_NORMAL2(LD_SHQS, LD_SHQS, LD_SHQS, INTREG, INTREG_UDISP_H, AVR32_V2),
27197 +    SYNTAX_NORMAL2(LD_SHAL, LD_SHAL, LD_SHAL, INTREG, INTREG_UDISP_H, AVR32_V2),
27198 +    SYNTAX_NORMAL2(LD_SHHS, LD_SHHS, LD_SHCC, INTREG, INTREG_UDISP_H, AVR32_V2),
27199 +    SYNTAX_NORMAL2(LD_SHLO, LD_SHLO, LD_SHCS, INTREG, INTREG_UDISP_H, AVR32_V2),
27200 +    SYNTAX_NORMAL2(LD_UHEQ, LD_UHEQ, LD_UHEQ, INTREG, INTREG_UDISP_H, AVR32_V2),
27201 +    SYNTAX_NORMAL2(LD_UHNE, LD_UHNE, LD_UHNE, INTREG, INTREG_UDISP_H, AVR32_V2),
27202 +    SYNTAX_NORMAL2(LD_UHCC, LD_UHCC, LD_UHCC, INTREG, INTREG_UDISP_H, AVR32_V2),
27203 +    SYNTAX_NORMAL2(LD_UHCS, LD_UHCS, LD_UHCS, INTREG, INTREG_UDISP_H, AVR32_V2),
27204 +    SYNTAX_NORMAL2(LD_UHGE, LD_UHGE, LD_UHGE, INTREG, INTREG_UDISP_H, AVR32_V2),
27205 +    SYNTAX_NORMAL2(LD_UHLT, LD_UHLT, LD_UHLT, INTREG, INTREG_UDISP_H, AVR32_V2),
27206 +    SYNTAX_NORMAL2(LD_UHMI, LD_UHMI, LD_UHMI, INTREG, INTREG_UDISP_H, AVR32_V2),
27207 +    SYNTAX_NORMAL2(LD_UHPL, LD_UHPL, LD_UHPL, INTREG, INTREG_UDISP_H, AVR32_V2),
27208 +    SYNTAX_NORMAL2(LD_UHLS, LD_UHLS, LD_UHLS, INTREG, INTREG_UDISP_H, AVR32_V2),
27209 +    SYNTAX_NORMAL2(LD_UHGT, LD_UHGT, LD_UHGT, INTREG, INTREG_UDISP_H, AVR32_V2),
27210 +    SYNTAX_NORMAL2(LD_UHLE, LD_UHLE, LD_UHLE, INTREG, INTREG_UDISP_H, AVR32_V2),
27211 +    SYNTAX_NORMAL2(LD_UHHI, LD_UHHI, LD_UHHI, INTREG, INTREG_UDISP_H, AVR32_V2),
27212 +    SYNTAX_NORMAL2(LD_UHVS, LD_UHVS, LD_UHVS, INTREG, INTREG_UDISP_H, AVR32_V2),
27213 +    SYNTAX_NORMAL2(LD_UHVC, LD_UHVC, LD_UHVC, INTREG, INTREG_UDISP_H, AVR32_V2),
27214 +    SYNTAX_NORMAL2(LD_UHQS, LD_UHQS, LD_UHQS, INTREG, INTREG_UDISP_H, AVR32_V2),
27215 +    SYNTAX_NORMAL2(LD_UHAL, LD_UHAL, LD_UHAL, INTREG, INTREG_UDISP_H, AVR32_V2),
27216 +    SYNTAX_NORMAL2(LD_UHHS, LD_UHHS, LD_UHCC, INTREG, INTREG_UDISP_H, AVR32_V2),
27217 +    SYNTAX_NORMAL2(LD_UHLO, LD_UHLO, LD_UHCS, INTREG, INTREG_UDISP_H, AVR32_V2),
27218 +    SYNTAX_NORMAL2(LD_SBEQ, LD_SBEQ, LD_SBEQ, INTREG, INTREG_UDISP, AVR32_V2),
27219 +    SYNTAX_NORMAL2(LD_SBNE, LD_SBNE, LD_SBNE, INTREG, INTREG_UDISP, AVR32_V2),
27220 +    SYNTAX_NORMAL2(LD_SBCC, LD_SBCC, LD_SBCC, INTREG, INTREG_UDISP, AVR32_V2),
27221 +    SYNTAX_NORMAL2(LD_SBCS, LD_SBCS, LD_SBCS, INTREG, INTREG_UDISP, AVR32_V2),
27222 +    SYNTAX_NORMAL2(LD_SBGE, LD_SBGE, LD_SBGE, INTREG, INTREG_UDISP, AVR32_V2),
27223 +    SYNTAX_NORMAL2(LD_SBLT, LD_SBLT, LD_SBLT, INTREG, INTREG_UDISP, AVR32_V2),
27224 +    SYNTAX_NORMAL2(LD_SBMI, LD_SBMI, LD_SBMI, INTREG, INTREG_UDISP, AVR32_V2),
27225 +    SYNTAX_NORMAL2(LD_SBPL, LD_SBPL, LD_SBPL, INTREG, INTREG_UDISP, AVR32_V2),
27226 +    SYNTAX_NORMAL2(LD_SBLS, LD_SBLS, LD_SBLS, INTREG, INTREG_UDISP, AVR32_V2),
27227 +    SYNTAX_NORMAL2(LD_SBGT, LD_SBGT, LD_SBGT, INTREG, INTREG_UDISP, AVR32_V2),
27228 +    SYNTAX_NORMAL2(LD_SBLE, LD_SBLE, LD_SBLE, INTREG, INTREG_UDISP, AVR32_V2),
27229 +    SYNTAX_NORMAL2(LD_SBHI, LD_SBHI, LD_SBHI, INTREG, INTREG_UDISP, AVR32_V2),
27230 +    SYNTAX_NORMAL2(LD_SBVS, LD_SBVS, LD_SBVS, INTREG, INTREG_UDISP, AVR32_V2),
27231 +    SYNTAX_NORMAL2(LD_SBVC, LD_SBVC, LD_SBVC, INTREG, INTREG_UDISP, AVR32_V2),
27232 +    SYNTAX_NORMAL2(LD_SBQS, LD_SBQS, LD_SBQS, INTREG, INTREG_UDISP, AVR32_V2),
27233 +    SYNTAX_NORMAL2(LD_SBAL, LD_SBAL, LD_SBAL, INTREG, INTREG_UDISP, AVR32_V2),
27234 +    SYNTAX_NORMAL2(LD_SBHS, LD_SBHS, LD_SBCC, INTREG, INTREG_UDISP, AVR32_V2),
27235 +    SYNTAX_NORMAL2(LD_SBLO, LD_SBLO, LD_SBCS, INTREG, INTREG_UDISP, AVR32_V2),
27236 +    SYNTAX_NORMAL2(LD_UBEQ, LD_UBEQ, LD_UBEQ, INTREG, INTREG_UDISP, AVR32_V2),
27237 +    SYNTAX_NORMAL2(LD_UBNE, LD_UBNE, LD_UBNE, INTREG, INTREG_UDISP, AVR32_V2),
27238 +    SYNTAX_NORMAL2(LD_UBCC, LD_UBCC, LD_UBCC, INTREG, INTREG_UDISP, AVR32_V2),
27239 +    SYNTAX_NORMAL2(LD_UBCS, LD_UBCS, LD_UBCS, INTREG, INTREG_UDISP, AVR32_V2),
27240 +    SYNTAX_NORMAL2(LD_UBGE, LD_UBGE, LD_UBGE, INTREG, INTREG_UDISP, AVR32_V2),
27241 +    SYNTAX_NORMAL2(LD_UBLT, LD_UBLT, LD_UBLT, INTREG, INTREG_UDISP, AVR32_V2),
27242 +    SYNTAX_NORMAL2(LD_UBMI, LD_UBMI, LD_UBMI, INTREG, INTREG_UDISP, AVR32_V2),
27243 +    SYNTAX_NORMAL2(LD_UBPL, LD_UBPL, LD_UBPL, INTREG, INTREG_UDISP, AVR32_V2),
27244 +    SYNTAX_NORMAL2(LD_UBLS, LD_UBLS, LD_UBLS, INTREG, INTREG_UDISP, AVR32_V2),
27245 +    SYNTAX_NORMAL2(LD_UBGT, LD_UBGT, LD_UBGT, INTREG, INTREG_UDISP, AVR32_V2),
27246 +    SYNTAX_NORMAL2(LD_UBLE, LD_UBLE, LD_UBLE, INTREG, INTREG_UDISP, AVR32_V2),
27247 +    SYNTAX_NORMAL2(LD_UBHI, LD_UBHI, LD_UBHI, INTREG, INTREG_UDISP, AVR32_V2),
27248 +    SYNTAX_NORMAL2(LD_UBVS, LD_UBVS, LD_UBVS, INTREG, INTREG_UDISP, AVR32_V2),
27249 +    SYNTAX_NORMAL2(LD_UBVC, LD_UBVC, LD_UBVC, INTREG, INTREG_UDISP, AVR32_V2),
27250 +    SYNTAX_NORMAL2(LD_UBQS, LD_UBQS, LD_UBQS, INTREG, INTREG_UDISP, AVR32_V2),
27251 +    SYNTAX_NORMAL2(LD_UBAL, LD_UBAL, LD_UBAL, INTREG, INTREG_UDISP, AVR32_V2),
27252 +    SYNTAX_NORMAL2(LD_UBHS, LD_UBHS, LD_UBCC, INTREG, INTREG_UDISP, AVR32_V2),
27253 +    SYNTAX_NORMAL2(LD_UBLO, LD_UBLO, LD_UBCS, INTREG, INTREG_UDISP, AVR32_V2),
27254 +    SYNTAX_NORMAL2(ST_WEQ, ST_WEQ, ST_WEQ, INTREG_UDISP_W, INTREG, AVR32_V2),
27255 +    SYNTAX_NORMAL2(ST_WNE, ST_WNE, ST_WNE, INTREG_UDISP_W, INTREG, AVR32_V2),
27256 +    SYNTAX_NORMAL2(ST_WCC, ST_WCC, ST_WCC, INTREG_UDISP_W, INTREG, AVR32_V2),
27257 +    SYNTAX_NORMAL2(ST_WCS, ST_WCS, ST_WCS, INTREG_UDISP_W, INTREG, AVR32_V2),
27258 +    SYNTAX_NORMAL2(ST_WGE, ST_WGE, ST_WGE, INTREG_UDISP_W, INTREG, AVR32_V2),
27259 +    SYNTAX_NORMAL2(ST_WLT, ST_WLT, ST_WLT, INTREG_UDISP_W, INTREG, AVR32_V2),
27260 +    SYNTAX_NORMAL2(ST_WMI, ST_WMI, ST_WMI, INTREG_UDISP_W, INTREG, AVR32_V2),
27261 +    SYNTAX_NORMAL2(ST_WPL, ST_WPL, ST_WPL, INTREG_UDISP_W, INTREG, AVR32_V2),
27262 +    SYNTAX_NORMAL2(ST_WLS, ST_WLS, ST_WLS, INTREG_UDISP_W, INTREG, AVR32_V2),
27263 +    SYNTAX_NORMAL2(ST_WGT, ST_WGT, ST_WGT, INTREG_UDISP_W, INTREG, AVR32_V2),
27264 +    SYNTAX_NORMAL2(ST_WLE, ST_WLE, ST_WLE, INTREG_UDISP_W, INTREG, AVR32_V2),
27265 +    SYNTAX_NORMAL2(ST_WHI, ST_WHI, ST_WHI, INTREG_UDISP_W, INTREG, AVR32_V2),
27266 +    SYNTAX_NORMAL2(ST_WVS, ST_WVS, ST_WVS, INTREG_UDISP_W, INTREG, AVR32_V2),
27267 +    SYNTAX_NORMAL2(ST_WVC, ST_WVC, ST_WVC, INTREG_UDISP_W, INTREG, AVR32_V2),
27268 +    SYNTAX_NORMAL2(ST_WQS, ST_WQS, ST_WQS, INTREG_UDISP_W, INTREG, AVR32_V2),
27269 +    SYNTAX_NORMAL2(ST_WAL, ST_WAL, ST_WAL, INTREG_UDISP_W, INTREG, AVR32_V2),
27270 +    SYNTAX_NORMAL2(ST_WHS, ST_WHS, ST_WCC, INTREG_UDISP_W, INTREG, AVR32_V2),
27271 +    SYNTAX_NORMAL2(ST_WLO, ST_WLO, ST_WCS, INTREG_UDISP_W, INTREG, AVR32_V2),
27272 +    SYNTAX_NORMAL2(ST_HEQ, ST_HEQ, ST_HEQ, INTREG_UDISP_H, INTREG, AVR32_V2),
27273 +    SYNTAX_NORMAL2(ST_HNE, ST_HNE, ST_HNE, INTREG_UDISP_H, INTREG, AVR32_V2),
27274 +    SYNTAX_NORMAL2(ST_HCC, ST_HCC, ST_HCC, INTREG_UDISP_H, INTREG, AVR32_V2),
27275 +    SYNTAX_NORMAL2(ST_HCS, ST_HCS, ST_HCS, INTREG_UDISP_H, INTREG, AVR32_V2),
27276 +    SYNTAX_NORMAL2(ST_HGE, ST_HGE, ST_HGE, INTREG_UDISP_H, INTREG, AVR32_V2),
27277 +    SYNTAX_NORMAL2(ST_HLT, ST_HLT, ST_HLT, INTREG_UDISP_H, INTREG, AVR32_V2),
27278 +    SYNTAX_NORMAL2(ST_HMI, ST_HMI, ST_HMI, INTREG_UDISP_H, INTREG, AVR32_V2),
27279 +    SYNTAX_NORMAL2(ST_HPL, ST_HPL, ST_HPL, INTREG_UDISP_H, INTREG, AVR32_V2),
27280 +    SYNTAX_NORMAL2(ST_HLS, ST_HLS, ST_HLS, INTREG_UDISP_H, INTREG, AVR32_V2),
27281 +    SYNTAX_NORMAL2(ST_HGT, ST_HGT, ST_HGT, INTREG_UDISP_H, INTREG, AVR32_V2),
27282 +    SYNTAX_NORMAL2(ST_HLE, ST_HLE, ST_HLE, INTREG_UDISP_H, INTREG, AVR32_V2),
27283 +    SYNTAX_NORMAL2(ST_HHI, ST_HHI, ST_HHI, INTREG_UDISP_H, INTREG, AVR32_V2),
27284 +    SYNTAX_NORMAL2(ST_HVS, ST_HVS, ST_HVS, INTREG_UDISP_H, INTREG, AVR32_V2),
27285 +    SYNTAX_NORMAL2(ST_HVC, ST_HVC, ST_HVC, INTREG_UDISP_H, INTREG, AVR32_V2),
27286 +    SYNTAX_NORMAL2(ST_HQS, ST_HQS, ST_HQS, INTREG_UDISP_H, INTREG, AVR32_V2),
27287 +    SYNTAX_NORMAL2(ST_HAL, ST_HAL, ST_HAL, INTREG_UDISP_H, INTREG, AVR32_V2),
27288 +    SYNTAX_NORMAL2(ST_HHS, ST_HHS, ST_HCC, INTREG_UDISP_H, INTREG, AVR32_V2),
27289 +    SYNTAX_NORMAL2(ST_HLO, ST_HLO, ST_HCS, INTREG_UDISP_H, INTREG, AVR32_V2),
27290 +    SYNTAX_NORMAL2(ST_BEQ, ST_BEQ, ST_BEQ, INTREG_UDISP, INTREG, AVR32_V2),
27291 +    SYNTAX_NORMAL2(ST_BNE, ST_BNE, ST_BNE, INTREG_UDISP, INTREG, AVR32_V2),
27292 +    SYNTAX_NORMAL2(ST_BCC, ST_BCC, ST_BCC, INTREG_UDISP, INTREG, AVR32_V2),
27293 +    SYNTAX_NORMAL2(ST_BCS, ST_BCS, ST_BCS, INTREG_UDISP, INTREG, AVR32_V2),
27294 +    SYNTAX_NORMAL2(ST_BGE, ST_BGE, ST_BGE, INTREG_UDISP, INTREG, AVR32_V2),
27295 +    SYNTAX_NORMAL2(ST_BLT, ST_BLT, ST_BLT, INTREG_UDISP, INTREG, AVR32_V2),
27296 +    SYNTAX_NORMAL2(ST_BMI, ST_BMI, ST_BMI, INTREG_UDISP, INTREG, AVR32_V2),
27297 +    SYNTAX_NORMAL2(ST_BPL, ST_BPL, ST_BPL, INTREG_UDISP, INTREG, AVR32_V2),
27298 +    SYNTAX_NORMAL2(ST_BLS, ST_BLS, ST_BLS, INTREG_UDISP, INTREG, AVR32_V2),
27299 +    SYNTAX_NORMAL2(ST_BGT, ST_BGT, ST_BGT, INTREG_UDISP, INTREG, AVR32_V2),
27300 +    SYNTAX_NORMAL2(ST_BLE, ST_BLE, ST_BLE, INTREG_UDISP, INTREG, AVR32_V2),
27301 +    SYNTAX_NORMAL2(ST_BHI, ST_BHI, ST_BHI, INTREG_UDISP, INTREG, AVR32_V2),
27302 +    SYNTAX_NORMAL2(ST_BVS, ST_BVS, ST_BVS, INTREG_UDISP, INTREG, AVR32_V2),
27303 +    SYNTAX_NORMAL2(ST_BVC, ST_BVC, ST_BVC, INTREG_UDISP, INTREG, AVR32_V2),
27304 +    SYNTAX_NORMAL2(ST_BQS, ST_BQS, ST_BQS, INTREG_UDISP, INTREG, AVR32_V2),
27305 +    SYNTAX_NORMAL2(ST_BAL, ST_BAL, ST_BAL, INTREG_UDISP, INTREG, AVR32_V2),
27306 +    SYNTAX_NORMAL2(ST_BHS, ST_BHS, ST_BCC, INTREG_UDISP, INTREG, AVR32_V2),
27307 +    SYNTAX_NORMAL2(ST_BLO, ST_BLO, ST_BCS, INTREG_UDISP, INTREG, AVR32_V2),
27308 +    SYNTAX_NORMAL2(MOVH, MOVH, MOVH, INTREG, UNSIGNED_CONST, AVR32_V2),
27309 +
27310 +  };
27311 +
27312 +#define NORMAL_MNEMONIC(name, syntax, str)             \
27313 +  {                                                    \
27314 +    AVR32_MNEMONIC_##name, str,                                \
27315 +    &avr32_syntax_table[AVR32_SYNTAX_##syntax],                \
27316 +  }
27317 +#define FP_MNEMONIC(name, syntax, str)                 \
27318 +  NORMAL_MNEMONIC(name##_S, syntax##_S, str ".s"),     \
27319 +  NORMAL_MNEMONIC(name##_D, syntax##_D, str ".d")
27320 +
27321 +const struct avr32_mnemonic avr32_mnemonic_table[] =
27322 +  {
27323 +    NORMAL_MNEMONIC(ABS, ABS, "abs"),
27324 +    NORMAL_MNEMONIC(ACALL, ACALL, "acall"),
27325 +    NORMAL_MNEMONIC(ACR, ACR, "acr"),
27326 +    NORMAL_MNEMONIC(ADC, ADC, "adc"),
27327 +    NORMAL_MNEMONIC(ADD, ADD1, "add"),
27328 +    NORMAL_MNEMONIC(ADDABS, ADDABS, "addabs"),
27329 +    NORMAL_MNEMONIC(ADDHH_W, ADDHH_W, "addhh.w"),
27330 +    NORMAL_MNEMONIC(AND, AND1, "and"),
27331 +    NORMAL_MNEMONIC(ANDH, ANDH, "andh"),
27332 +    NORMAL_MNEMONIC(ANDL, ANDL, "andl"),
27333 +    NORMAL_MNEMONIC(ANDN, ANDN, "andn"),
27334 +    NORMAL_MNEMONIC(ASR, ASR1, "asr"),
27335 +    NORMAL_MNEMONIC(BFEXTS, BFEXTS, "bfexts"),
27336 +    NORMAL_MNEMONIC(BFEXTU, BFEXTU, "bfextu"),
27337 +    NORMAL_MNEMONIC(BFINS, BFINS, "bfins"),
27338 +    NORMAL_MNEMONIC(BLD, BLD, "bld"),
27339 +    NORMAL_MNEMONIC(BREQ, BREQ1, "breq"),
27340 +    NORMAL_MNEMONIC(BRNE, BRNE1, "brne"),
27341 +    NORMAL_MNEMONIC(BRCC, BRCC1, "brcc"),
27342 +    NORMAL_MNEMONIC(BRCS, BRCS1, "brcs"),
27343 +    NORMAL_MNEMONIC(BRGE, BRGE1, "brge"),
27344 +    NORMAL_MNEMONIC(BRLT, BRLT1, "brlt"),
27345 +    NORMAL_MNEMONIC(BRMI, BRMI1, "brmi"),
27346 +    NORMAL_MNEMONIC(BRPL, BRPL1, "brpl"),
27347 +    NORMAL_MNEMONIC(BRHS, BRHS1, "brhs"),
27348 +    NORMAL_MNEMONIC(BRLO, BRLO1, "brlo"),
27349 +    NORMAL_MNEMONIC(BRLS, BRLS, "brls"),
27350 +    NORMAL_MNEMONIC(BRGT, BRGT, "brgt"),
27351 +    NORMAL_MNEMONIC(BRLE, BRLE, "brle"),
27352 +    NORMAL_MNEMONIC(BRHI, BRHI, "brhi"),
27353 +    NORMAL_MNEMONIC(BRVS, BRVS, "brvs"),
27354 +    NORMAL_MNEMONIC(BRVC, BRVC, "brvc"),
27355 +    NORMAL_MNEMONIC(BRQS, BRQS, "brqs"),
27356 +    NORMAL_MNEMONIC(BRAL, BRAL, "bral"),
27357 +    NORMAL_MNEMONIC(BREAKPOINT, BREAKPOINT, "breakpoint"),
27358 +    NORMAL_MNEMONIC(BREV, BREV, "brev"),
27359 +    NORMAL_MNEMONIC(BST, BST, "bst"),
27360 +    NORMAL_MNEMONIC(CACHE, CACHE, "cache"),
27361 +    NORMAL_MNEMONIC(CASTS_B, CASTS_B, "casts.b"),
27362 +    NORMAL_MNEMONIC(CASTS_H, CASTS_H, "casts.h"),
27363 +    NORMAL_MNEMONIC(CASTU_B, CASTU_B, "castu.b"),
27364 +    NORMAL_MNEMONIC(CASTU_H, CASTU_H, "castu.h"),
27365 +    NORMAL_MNEMONIC(CBR, CBR, "cbr"),
27366 +    NORMAL_MNEMONIC(CLZ, CLZ, "clz"),
27367 +    NORMAL_MNEMONIC(COM, COM, "com"),
27368 +    NORMAL_MNEMONIC(COP, COP, "cop"),
27369 +    NORMAL_MNEMONIC(CP_B, CP_B, "cp.b"),
27370 +    NORMAL_MNEMONIC(CP_H, CP_H, "cp.h"),
27371 +    NORMAL_MNEMONIC(CP_W, CP_W1, "cp.w"),
27372 +    NORMAL_MNEMONIC(CP, CP_W1, "cp"),
27373 +    NORMAL_MNEMONIC(CPC, CPC1, "cpc"),
27374 +    NORMAL_MNEMONIC(CSRF, CSRF, "csrf"),
27375 +    NORMAL_MNEMONIC(CSRFCZ, CSRFCZ, "csrfcz"),
27376 +    NORMAL_MNEMONIC(DIVS, DIVS, "divs"),
27377 +    NORMAL_MNEMONIC(DIVU, DIVU, "divu"),
27378 +    NORMAL_MNEMONIC(EOR, EOR1, "eor"),
27379 +    NORMAL_MNEMONIC(EORL, EORL, "eorl"),
27380 +    NORMAL_MNEMONIC(EORH, EORH, "eorh"),
27381 +    NORMAL_MNEMONIC(FRS, FRS, "frs"),
27382 +    NORMAL_MNEMONIC(SSCALL, SSCALL, "sscall"),
27383 +    NORMAL_MNEMONIC(RETSS, RETSS, "retss"),
27384 +    NORMAL_MNEMONIC(ICALL, ICALL, "icall"),
27385 +    NORMAL_MNEMONIC(INCJOSP, INCJOSP, "incjosp"),
27386 +    NORMAL_MNEMONIC(LD_D, LD_D1, "ld.d"),
27387 +    NORMAL_MNEMONIC(LD_SB, LD_SB2, "ld.sb"),
27388 +    NORMAL_MNEMONIC(LD_UB, LD_UB1, "ld.ub"),
27389 +    NORMAL_MNEMONIC(LD_SH, LD_SH1, "ld.sh"),
27390 +    NORMAL_MNEMONIC(LD_UH, LD_UH1, "ld.uh"),
27391 +    NORMAL_MNEMONIC(LD_W, LD_W1, "ld.w"),
27392 +    NORMAL_MNEMONIC(LDC_D, LDC_D3, "ldc.d"),
27393 +    NORMAL_MNEMONIC(LDC_W, LDC_W3, "ldc.w"),
27394 +    NORMAL_MNEMONIC(LDC0_D, LDC0_D, "ldc0.d"),
27395 +    NORMAL_MNEMONIC(LDC0_W, LDC0_W, "ldc0.w"),
27396 +    NORMAL_MNEMONIC(LDCM_D, LDCM_D, "ldcm.d"),
27397 +    NORMAL_MNEMONIC(LDCM_W, LDCM_W, "ldcm.w"),
27398 +    NORMAL_MNEMONIC(LDDPC, LDDPC, "lddpc"),
27399 +    NORMAL_MNEMONIC(LDDSP, LDDSP, "lddsp"),
27400 +    NORMAL_MNEMONIC(LDINS_B, LDINS_B, "ldins.b"),
27401 +    NORMAL_MNEMONIC(LDINS_H, LDINS_H, "ldins.h"),
27402 +    NORMAL_MNEMONIC(LDM, LDM, "ldm"),
27403 +    NORMAL_MNEMONIC(LDMTS, LDMTS, "ldmts"),
27404 +    NORMAL_MNEMONIC(LDSWP_SH, LDSWP_SH, "ldswp.sh"),
27405 +    NORMAL_MNEMONIC(LDSWP_UH, LDSWP_UH, "ldswp.uh"),
27406 +    NORMAL_MNEMONIC(LDSWP_W, LDSWP_W, "ldswp.w"),
27407 +    NORMAL_MNEMONIC(LSL, LSL1, "lsl"),
27408 +    NORMAL_MNEMONIC(LSR, LSR1, "lsr"),
27409 +    NORMAL_MNEMONIC(MAC, MAC, "mac"),
27410 +    NORMAL_MNEMONIC(MACHH_D, MACHH_D, "machh.d"),
27411 +    NORMAL_MNEMONIC(MACHH_W, MACHH_W, "machh.w"),
27412 +    NORMAL_MNEMONIC(MACS_D, MACS_D, "macs.d"),
27413 +    NORMAL_MNEMONIC(MACSATHH_W, MACSATHH_W, "macsathh.w"),
27414 +    NORMAL_MNEMONIC(MACU_D, MACUD, "macu.d"),
27415 +    NORMAL_MNEMONIC(MACWH_D, MACWH_D, "macwh.d"),
27416 +    NORMAL_MNEMONIC(MAX, MAX, "max"),
27417 +    NORMAL_MNEMONIC(MCALL, MCALL, "mcall"),
27418 +    NORMAL_MNEMONIC(MFDR, MFDR, "mfdr"),
27419 +    NORMAL_MNEMONIC(MFSR, MFSR, "mfsr"),
27420 +    NORMAL_MNEMONIC(MIN, MIN, "min"),
27421 +    NORMAL_MNEMONIC(MOV, MOV3, "mov"),
27422 +    NORMAL_MNEMONIC(MOVEQ, MOVEQ1, "moveq"),
27423 +    NORMAL_MNEMONIC(MOVNE, MOVNE1, "movne"),
27424 +    NORMAL_MNEMONIC(MOVCC, MOVCC1, "movcc"),
27425 +    NORMAL_MNEMONIC(MOVCS, MOVCS1, "movcs"),
27426 +    NORMAL_MNEMONIC(MOVGE, MOVGE1, "movge"),
27427 +    NORMAL_MNEMONIC(MOVLT, MOVLT1, "movlt"),
27428 +    NORMAL_MNEMONIC(MOVMI, MOVMI1, "movmi"),
27429 +    NORMAL_MNEMONIC(MOVPL, MOVPL1, "movpl"),
27430 +    NORMAL_MNEMONIC(MOVLS, MOVLS1, "movls"),
27431 +    NORMAL_MNEMONIC(MOVGT, MOVGT1, "movgt"),
27432 +    NORMAL_MNEMONIC(MOVLE, MOVLE1, "movle"),
27433 +    NORMAL_MNEMONIC(MOVHI, MOVHI1, "movhi"),
27434 +    NORMAL_MNEMONIC(MOVVS, MOVVS1, "movvs"),
27435 +    NORMAL_MNEMONIC(MOVVC, MOVVC1, "movvc"),
27436 +    NORMAL_MNEMONIC(MOVQS, MOVQS1, "movqs"),
27437 +    NORMAL_MNEMONIC(MOVAL, MOVAL1, "moval"),
27438 +    NORMAL_MNEMONIC(MOVHS, MOVHS1, "movhs"),
27439 +    NORMAL_MNEMONIC(MOVLO, MOVLO1, "movlo"),
27440 +    NORMAL_MNEMONIC(MTDR, MTDR, "mtdr"),
27441 +    NORMAL_MNEMONIC(MTSR, MTSR, "mtsr"),
27442 +    NORMAL_MNEMONIC(MUL, MUL1, "mul"),
27443 +    NORMAL_MNEMONIC(MULHH_W, MULHH_W, "mulhh.w"),
27444 +    NORMAL_MNEMONIC(MULNHH_W, MULNHH_W, "mulnhh.w"),
27445 +    NORMAL_MNEMONIC(MULNWH_D, MULNWH_D, "mulnwh.d"),
27446 +    NORMAL_MNEMONIC(MULS_D, MULSD, "muls.d"),
27447 +    NORMAL_MNEMONIC(MULSATHH_H, MULSATHH_H, "mulsathh.h"),
27448 +    NORMAL_MNEMONIC(MULSATHH_W, MULSATHH_W, "mulsathh.w"),
27449 +    NORMAL_MNEMONIC(MULSATRNDHH_H, MULSATRNDHH_H, "mulsatrndhh.h"),
27450 +    NORMAL_MNEMONIC(MULSATRNDWH_W, MULSATRNDWH_W, "mulsatrndwh.w"),
27451 +    NORMAL_MNEMONIC(MULSATWH_W, MULSATWH_W, "mulsatwh.w"),
27452 +    NORMAL_MNEMONIC(MULU_D, MULU_D, "mulu.d"),
27453 +    NORMAL_MNEMONIC(MULWH_D, MULWH_D, "mulwh.d"),
27454 +    NORMAL_MNEMONIC(MUSFR, MUSFR, "musfr"),
27455 +    NORMAL_MNEMONIC(MUSTR, MUSTR, "mustr"),
27456 +    NORMAL_MNEMONIC(MVCR_D, MVCR_D, "mvcr.d"),
27457 +    NORMAL_MNEMONIC(MVCR_W, MVCR_W, "mvcr.w"),
27458 +    NORMAL_MNEMONIC(MVRC_D, MVRC_D, "mvrc.d"),
27459 +    NORMAL_MNEMONIC(MVRC_W, MVRC_W, "mvrc.w"),
27460 +    NORMAL_MNEMONIC(NEG, NEG, "neg"),
27461 +    NORMAL_MNEMONIC(NOP, NOP, "nop"),
27462 +    NORMAL_MNEMONIC(OR, OR1, "or"),
27463 +    NORMAL_MNEMONIC(ORH, ORH, "orh"),
27464 +    NORMAL_MNEMONIC(ORL, ORL, "orl"),
27465 +    NORMAL_MNEMONIC(PABS_SB, PABS_SB, "pabs.sb"),
27466 +    NORMAL_MNEMONIC(PABS_SH, PABS_SH, "pabs.sh"),
27467 +    NORMAL_MNEMONIC(PACKSH_SB, PACKSH_SB, "packsh.sb"),
27468 +    NORMAL_MNEMONIC(PACKSH_UB, PACKSH_UB, "packsh.ub"),
27469 +    NORMAL_MNEMONIC(PACKW_SH, PACKW_SH, "packw.sh"),
27470 +    NORMAL_MNEMONIC(PADD_B, PADD_B, "padd.b"),
27471 +    NORMAL_MNEMONIC(PADD_H, PADD_H, "padd.h"),
27472 +    NORMAL_MNEMONIC(PADDH_SH, PADDH_SH, "paddh.sh"),
27473 +    NORMAL_MNEMONIC(PADDH_UB, PADDH_UB, "paddh.ub"),
27474 +    NORMAL_MNEMONIC(PADDS_SB, PADDS_SB, "padds.sb"),
27475 +    NORMAL_MNEMONIC(PADDS_SH, PADDS_SH, "padds.sh"),
27476 +    NORMAL_MNEMONIC(PADDS_UB, PADDS_UB, "padds.ub"),
27477 +    NORMAL_MNEMONIC(PADDS_UH, PADDS_UH, "padds.uh"),
27478 +    NORMAL_MNEMONIC(PADDSUB_H, PADDSUB_H, "paddsub.h"),
27479 +    NORMAL_MNEMONIC(PADDSUBH_SH, PADDSUBH_SH, "paddsubh.sh"),
27480 +    NORMAL_MNEMONIC(PADDSUBS_SH, PADDSUBS_SH, "paddsubs.sh"),
27481 +    NORMAL_MNEMONIC(PADDSUBS_UH, PADDSUBS_UH, "paddsubs.uh"),
27482 +    NORMAL_MNEMONIC(PADDX_H, PADDX_H, "paddx.h"),
27483 +    NORMAL_MNEMONIC(PADDXH_SH, PADDXH_SH, "paddxh.sh"),
27484 +    NORMAL_MNEMONIC(PADDXS_SH, PADDXS_SH, "paddxs.sh"),
27485 +    NORMAL_MNEMONIC(PADDXS_UH, PADDXS_UH, "paddxs.uh"),
27486 +    NORMAL_MNEMONIC(PASR_B, PASR_B, "pasr.b"),
27487 +    NORMAL_MNEMONIC(PASR_H, PASR_H, "pasr.h"),
27488 +    NORMAL_MNEMONIC(PAVG_SH, PAVG_SH, "pavg.sh"),
27489 +    NORMAL_MNEMONIC(PAVG_UB, PAVG_UB, "pavg.ub"),
27490 +    NORMAL_MNEMONIC(PLSL_B, PLSL_B, "plsl.b"),
27491 +    NORMAL_MNEMONIC(PLSL_H, PLSL_H, "plsl.h"),
27492 +    NORMAL_MNEMONIC(PLSR_B, PLSR_B, "plsr.b"),
27493 +    NORMAL_MNEMONIC(PLSR_H, PLSR_H, "plsr.h"),
27494 +    NORMAL_MNEMONIC(PMAX_SH, PMAX_SH, "pmax.sh"),
27495 +    NORMAL_MNEMONIC(PMAX_UB, PMAX_UB, "pmax.ub"),
27496 +    NORMAL_MNEMONIC(PMIN_SH, PMIN_SH, "pmin.sh"),
27497 +    NORMAL_MNEMONIC(PMIN_UB, PMIN_UB, "pmin.ub"),
27498 +    NORMAL_MNEMONIC(POPJC, POPJC, "popjc"),
27499 +    NORMAL_MNEMONIC(POPM, POPM, "popm"),
27500 +    NORMAL_MNEMONIC(PREF, PREF, "pref"),
27501 +    NORMAL_MNEMONIC(PSAD, PSAD, "psad"),
27502 +    NORMAL_MNEMONIC(PSUB_B, PSUB_B, "psub.b"),
27503 +    NORMAL_MNEMONIC(PSUB_H, PSUB_H, "psub.h"),
27504 +    NORMAL_MNEMONIC(PSUBADD_H, PSUBADD_H, "psubadd.h"),
27505 +    NORMAL_MNEMONIC(PSUBADDH_SH, PSUBADDH_SH, "psubaddh.sh"),
27506 +    NORMAL_MNEMONIC(PSUBADDS_SH, PSUBADDS_SH, "psubadds.sh"),
27507 +    NORMAL_MNEMONIC(PSUBADDS_UH, PSUBADDS_UH, "psubadds.uh"),
27508 +    NORMAL_MNEMONIC(PSUBH_SH, PSUBH_SH, "psubh.sh"),
27509 +    NORMAL_MNEMONIC(PSUBH_UB, PSUBH_UB, "psubh.ub"),
27510 +    NORMAL_MNEMONIC(PSUBS_SB, PSUBS_SB, "psubs.sb"),
27511 +    NORMAL_MNEMONIC(PSUBS_SH, PSUBS_SH, "psubs.sh"),
27512 +    NORMAL_MNEMONIC(PSUBS_UB, PSUBS_UB, "psubs.ub"),
27513 +    NORMAL_MNEMONIC(PSUBS_UH, PSUBS_UH, "psubs.uh"),
27514 +    NORMAL_MNEMONIC(PSUBX_H, PSUBX_H, "psubx.h"),
27515 +    NORMAL_MNEMONIC(PSUBXH_SH, PSUBXH_SH, "psubxh.sh"),
27516 +    NORMAL_MNEMONIC(PSUBXS_SH, PSUBXS_SH, "psubxs.sh"),
27517 +    NORMAL_MNEMONIC(PSUBXS_UH, PSUBXS_UH, "psubxs.uh"),
27518 +    NORMAL_MNEMONIC(PUNPCKSB_H, PUNPCKSB_H, "punpcksb.h"),
27519 +    NORMAL_MNEMONIC(PUNPCKUB_H, PUNPCKUB_H, "punpckub.h"),
27520 +    NORMAL_MNEMONIC(PUSHJC, PUSHJC, "pushjc"),
27521 +    NORMAL_MNEMONIC(PUSHM, PUSHM, "pushm"),
27522 +    NORMAL_MNEMONIC(RCALL, RCALL1, "rcall"),
27523 +    NORMAL_MNEMONIC(RETEQ, RETEQ, "reteq"),
27524 +    NORMAL_MNEMONIC(RETNE, RETNE, "retne"),
27525 +    NORMAL_MNEMONIC(RETCC, RETCC, "retcc"),
27526 +    NORMAL_MNEMONIC(RETCS, RETCS, "retcs"),
27527 +    NORMAL_MNEMONIC(RETGE, RETGE, "retge"),
27528 +    NORMAL_MNEMONIC(RETLT, RETLT, "retlt"),
27529 +    NORMAL_MNEMONIC(RETMI, RETMI, "retmi"),
27530 +    NORMAL_MNEMONIC(RETPL, RETPL, "retpl"),
27531 +    NORMAL_MNEMONIC(RETLS, RETLS, "retls"),
27532 +    NORMAL_MNEMONIC(RETGT, RETGT, "retgt"),
27533 +    NORMAL_MNEMONIC(RETLE, RETLE, "retle"),
27534 +    NORMAL_MNEMONIC(RETHI, RETHI, "rethi"),
27535 +    NORMAL_MNEMONIC(RETVS, RETVS, "retvs"),
27536 +    NORMAL_MNEMONIC(RETVC, RETVC, "retvc"),
27537 +    NORMAL_MNEMONIC(RETQS, RETQS, "retqs"),
27538 +    NORMAL_MNEMONIC(RETAL, RETAL, "retal"),
27539 +    NORMAL_MNEMONIC(RETHS, RETHS, "reths"),
27540 +    NORMAL_MNEMONIC(RETLO, RETLO, "retlo"),
27541 +    NORMAL_MNEMONIC(RET, RETAL, "ret"),
27542 +    NORMAL_MNEMONIC(RETD, RETD, "retd"),
27543 +    NORMAL_MNEMONIC(RETE, RETE, "rete"),
27544 +    NORMAL_MNEMONIC(RETJ, RETJ, "retj"),
27545 +    NORMAL_MNEMONIC(RETS, RETS, "rets"),
27546 +    NORMAL_MNEMONIC(RJMP, RJMP, "rjmp"),
27547 +    NORMAL_MNEMONIC(ROL, ROL, "rol"),
27548 +    NORMAL_MNEMONIC(ROR, ROR, "ror"),
27549 +    NORMAL_MNEMONIC(RSUB, RSUB1, "rsub"),
27550 +    NORMAL_MNEMONIC(SATADD_H, SATADD_H, "satadd.h"),
27551 +    NORMAL_MNEMONIC(SATADD_W, SATADD_W, "satadd.w"),
27552 +    NORMAL_MNEMONIC(SATRNDS, SATRNDS, "satrnds"),
27553 +    NORMAL_MNEMONIC(SATRNDU, SATRNDU, "satrndu"),
27554 +    NORMAL_MNEMONIC(SATS, SATS, "sats"),
27555 +    NORMAL_MNEMONIC(SATSUB_H, SATSUB_H, "satsub.h"),
27556 +    NORMAL_MNEMONIC(SATSUB_W, SATSUB_W1, "satsub.w"),
27557 +    NORMAL_MNEMONIC(SATU, SATU, "satu"),
27558 +    NORMAL_MNEMONIC(SBC, SBC, "sbc"),
27559 +    NORMAL_MNEMONIC(SBR, SBR, "sbr"),
27560 +    NORMAL_MNEMONIC(SCALL, SCALL, "scall"),
27561 +    NORMAL_MNEMONIC(SCR, SCR, "scr"),
27562 +    NORMAL_MNEMONIC(SLEEP, SLEEP, "sleep"),
27563 +    NORMAL_MNEMONIC(SREQ, SREQ, "sreq"),
27564 +    NORMAL_MNEMONIC(SRNE, SRNE, "srne"),
27565 +    NORMAL_MNEMONIC(SRCC, SRCC, "srcc"),
27566 +    NORMAL_MNEMONIC(SRCS, SRCS, "srcs"),
27567 +    NORMAL_MNEMONIC(SRGE, SRGE, "srge"),
27568 +    NORMAL_MNEMONIC(SRLT, SRLT, "srlt"),
27569 +    NORMAL_MNEMONIC(SRMI, SRMI, "srmi"),
27570 +    NORMAL_MNEMONIC(SRPL, SRPL, "srpl"),
27571 +    NORMAL_MNEMONIC(SRLS, SRLS, "srls"),
27572 +    NORMAL_MNEMONIC(SRGT, SRGT, "srgt"),
27573 +    NORMAL_MNEMONIC(SRLE, SRLE, "srle"),
27574 +    NORMAL_MNEMONIC(SRHI, SRHI, "srhi"),
27575 +    NORMAL_MNEMONIC(SRVS, SRVS, "srvs"),
27576 +    NORMAL_MNEMONIC(SRVC, SRVC, "srvc"),
27577 +    NORMAL_MNEMONIC(SRQS, SRQS, "srqs"),
27578 +    NORMAL_MNEMONIC(SRAL, SRAL, "sral"),
27579 +    NORMAL_MNEMONIC(SRHS, SRHS, "srhs"),
27580 +    NORMAL_MNEMONIC(SRLO, SRLO, "srlo"),
27581 +    NORMAL_MNEMONIC(SSRF, SSRF, "ssrf"),
27582 +    NORMAL_MNEMONIC(ST_B, ST_B1, "st.b"),
27583 +    NORMAL_MNEMONIC(ST_D, ST_D1, "st.d"),
27584 +    NORMAL_MNEMONIC(ST_H, ST_H1, "st.h"),
27585 +    NORMAL_MNEMONIC(ST_W, ST_W1, "st.w"),
27586 +    NORMAL_MNEMONIC(STC_D, STC_D3, "stc.d"),
27587 +    NORMAL_MNEMONIC(STC_W, STC_W3, "stc.w"),
27588 +    NORMAL_MNEMONIC(STC0_D, STC0_D, "stc0.d"),
27589 +    NORMAL_MNEMONIC(STC0_W, STC0_W, "stc0.w"),
27590 +    NORMAL_MNEMONIC(STCM_D, STCM_D, "stcm.d"),
27591 +    NORMAL_MNEMONIC(STCM_W, STCM_W, "stcm.w"),
27592 +    NORMAL_MNEMONIC(STCOND, STCOND, "stcond"),
27593 +    NORMAL_MNEMONIC(STDSP, STDSP, "stdsp"),
27594 +    NORMAL_MNEMONIC(STHH_W, STHH_W2, "sthh.w"),
27595 +    NORMAL_MNEMONIC(STM, STM, "stm"),
27596 +    NORMAL_MNEMONIC(STMTS, STMTS, "stmts"),
27597 +    NORMAL_MNEMONIC(STSWP_H, STSWP_H, "stswp.h"),
27598 +    NORMAL_MNEMONIC(STSWP_W, STSWP_W, "stswp.w"),
27599 +    NORMAL_MNEMONIC(SUB, SUB1, "sub"),
27600 +    NORMAL_MNEMONIC(SUBEQ, SUBEQ, "subeq"),
27601 +    NORMAL_MNEMONIC(SUBNE, SUBNE, "subne"),
27602 +    NORMAL_MNEMONIC(SUBCC, SUBCC, "subcc"),
27603 +    NORMAL_MNEMONIC(SUBCS, SUBCS, "subcs"),
27604 +    NORMAL_MNEMONIC(SUBGE, SUBGE, "subge"),
27605 +    NORMAL_MNEMONIC(SUBLT, SUBLT, "sublt"),
27606 +    NORMAL_MNEMONIC(SUBMI, SUBMI, "submi"),
27607 +    NORMAL_MNEMONIC(SUBPL, SUBPL, "subpl"),
27608 +    NORMAL_MNEMONIC(SUBLS, SUBLS, "subls"),
27609 +    NORMAL_MNEMONIC(SUBGT, SUBGT, "subgt"),
27610 +    NORMAL_MNEMONIC(SUBLE, SUBLE, "suble"),
27611 +    NORMAL_MNEMONIC(SUBHI, SUBHI, "subhi"),
27612 +    NORMAL_MNEMONIC(SUBVS, SUBVS, "subvs"),
27613 +    NORMAL_MNEMONIC(SUBVC, SUBVC, "subvc"),
27614 +    NORMAL_MNEMONIC(SUBQS, SUBQS, "subqs"),
27615 +    NORMAL_MNEMONIC(SUBAL, SUBAL, "subal"),
27616 +    NORMAL_MNEMONIC(SUBHS, SUBHS, "subhs"),
27617 +    NORMAL_MNEMONIC(SUBLO, SUBLO, "sublo"),
27618 +    NORMAL_MNEMONIC(SUBFEQ, SUBFEQ, "subfeq"),
27619 +    NORMAL_MNEMONIC(SUBFNE, SUBFNE, "subfne"),
27620 +    NORMAL_MNEMONIC(SUBFCC, SUBFCC, "subfcc"),
27621 +    NORMAL_MNEMONIC(SUBFCS, SUBFCS, "subfcs"),
27622 +    NORMAL_MNEMONIC(SUBFGE, SUBFGE, "subfge"),
27623 +    NORMAL_MNEMONIC(SUBFLT, SUBFLT, "subflt"),
27624 +    NORMAL_MNEMONIC(SUBFMI, SUBFMI, "subfmi"),
27625 +    NORMAL_MNEMONIC(SUBFPL, SUBFPL, "subfpl"),
27626 +    NORMAL_MNEMONIC(SUBFLS, SUBFLS, "subfls"),
27627 +    NORMAL_MNEMONIC(SUBFGT, SUBFGT, "subfgt"),
27628 +    NORMAL_MNEMONIC(SUBFLE, SUBFLE, "subfle"),
27629 +    NORMAL_MNEMONIC(SUBFHI, SUBFHI, "subfhi"),
27630 +    NORMAL_MNEMONIC(SUBFVS, SUBFVS, "subfvs"),
27631 +    NORMAL_MNEMONIC(SUBFVC, SUBFVC, "subfvc"),
27632 +    NORMAL_MNEMONIC(SUBFQS, SUBFQS, "subfqs"),
27633 +    NORMAL_MNEMONIC(SUBFAL, SUBFAL, "subfal"),
27634 +    NORMAL_MNEMONIC(SUBFHS, SUBFHS, "subfhs"),
27635 +    NORMAL_MNEMONIC(SUBFLO, SUBFLO, "subflo"),
27636 +    NORMAL_MNEMONIC(SUBHH_W, SUBHH_W, "subhh.w"),
27637 +    NORMAL_MNEMONIC(SWAP_B, SWAP_B, "swap.b"),
27638 +    NORMAL_MNEMONIC(SWAP_BH, SWAP_BH, "swap.bh"),
27639 +    NORMAL_MNEMONIC(SWAP_H, SWAP_H, "swap.h"),
27640 +    NORMAL_MNEMONIC(SYNC, SYNC, "sync"),
27641 +    NORMAL_MNEMONIC(TLBR, TLBR, "tlbr"),
27642 +    NORMAL_MNEMONIC(TLBS, TLBS, "tlbs"),
27643 +    NORMAL_MNEMONIC(TLBW, TLBW, "tlbw"),
27644 +    NORMAL_MNEMONIC(TNBZ, TNBZ, "tnbz"),
27645 +    NORMAL_MNEMONIC(TST, TST, "tst"),
27646 +    NORMAL_MNEMONIC(XCHG, XCHG, "xchg"),
27647 +    NORMAL_MNEMONIC(MEMC, MEMC, "memc"),
27648 +    NORMAL_MNEMONIC(MEMS, MEMS, "mems"),
27649 +    NORMAL_MNEMONIC(MEMT, MEMT, "memt"),
27650 +  NORMAL_MNEMONIC (FMAC_S,     FMAC_S,     "fmac.s"),
27651 +  NORMAL_MNEMONIC (FNMAC_S,    FNMAC_S,    "fnmac.s"),
27652 +  NORMAL_MNEMONIC (FMSC_S,     FMSC_S,     "fmsc.s"),
27653 +  NORMAL_MNEMONIC (FNMSC_S,    FNMSC_S,    "fnmsc.s"),
27654 +  NORMAL_MNEMONIC (FMUL_S,     FMUL_S,     "fmul.s"),
27655 +  NORMAL_MNEMONIC (FNMUL_S,    FNMUL_S,    "fnmul.s"),
27656 +  NORMAL_MNEMONIC (FADD_S,     FADD_S,     "fadd.s"),
27657 +  NORMAL_MNEMONIC (FSUB_S,     FSUB_S,     "fsub.s"),
27658 +  NORMAL_MNEMONIC (FCASTRS_SW, FCASTRS_SW, "fcastrs.sw"),
27659 +  NORMAL_MNEMONIC (FCASTRS_UW, FCASTRS_UW, "fcastrs.uw"),
27660 +  NORMAL_MNEMONIC (FCASTSW_S,  FCASTSW_S,  "fcastsw.s"),
27661 +  NORMAL_MNEMONIC (FCASTUW_S,  FCASTUW_S,  "fcastuw.s"),
27662 +  NORMAL_MNEMONIC (FCMP_S,     FCMP_S,     "fcmp.s"),
27663 +  NORMAL_MNEMONIC (FCHK_S,     FCHK_S,     "fchk.s"),
27664 +  NORMAL_MNEMONIC (FRCPA_S,    FRCPA_S,    "frcpa.s"),
27665 +  NORMAL_MNEMONIC (FRSQRTA_S,  FRSQRTA_S,  "frsqrta.s"),
27666 +    NORMAL_MNEMONIC(LDA_W, LDA_W, "lda.w"),
27667 +    NORMAL_MNEMONIC(CALL, CALL, "call"),
27668 +    NORMAL_MNEMONIC(PICOSVMAC, PICOSVMAC0, "picosvmac"),
27669 +    NORMAL_MNEMONIC(PICOSVMUL, PICOSVMUL0, "picosvmul"),
27670 +    NORMAL_MNEMONIC(PICOVMAC, PICOVMAC0, "picovmac"),
27671 +    NORMAL_MNEMONIC(PICOVMUL, PICOVMUL0, "picovmul"),
27672 +    NORMAL_MNEMONIC(PICOLD_D, PICOLD_D2, "picold.d"),
27673 +    NORMAL_MNEMONIC(PICOLD_W, PICOLD_W2, "picold.w"),
27674 +    NORMAL_MNEMONIC(PICOLDM_D, PICOLDM_D, "picoldm.d"),
27675 +    NORMAL_MNEMONIC(PICOLDM_W, PICOLDM_W, "picoldm.w"),
27676 +    NORMAL_MNEMONIC(PICOMV_D, PICOMV_D1, "picomv.d"),
27677 +    NORMAL_MNEMONIC(PICOMV_W, PICOMV_W1, "picomv.w"),
27678 +    NORMAL_MNEMONIC(PICOST_D, PICOST_D2, "picost.d"),
27679 +    NORMAL_MNEMONIC(PICOST_W, PICOST_W2, "picost.w"),
27680 +    NORMAL_MNEMONIC(PICOSTM_D, PICOSTM_D, "picostm.d"),
27681 +    NORMAL_MNEMONIC(PICOSTM_W, PICOSTM_W, "picostm.w"),
27682 +    NORMAL_MNEMONIC(RSUBEQ, RSUBEQ, "rsubeq"),
27683 +    NORMAL_MNEMONIC(RSUBNE, RSUBNE, "rsubne"),
27684 +    NORMAL_MNEMONIC(RSUBCC, RSUBCC, "rsubcc"),
27685 +    NORMAL_MNEMONIC(RSUBCS, RSUBCS, "rsubcs"),
27686 +    NORMAL_MNEMONIC(RSUBGE, RSUBGE, "rsubge"),
27687 +    NORMAL_MNEMONIC(RSUBLT, RSUBLT, "rsublt"),
27688 +    NORMAL_MNEMONIC(RSUBMI, RSUBMI, "rsubmi"),
27689 +    NORMAL_MNEMONIC(RSUBPL, RSUBPL, "rsubpl"),
27690 +    NORMAL_MNEMONIC(RSUBLS, RSUBLS, "rsubls"),
27691 +    NORMAL_MNEMONIC(RSUBGT, RSUBGT, "rsubgt"),
27692 +    NORMAL_MNEMONIC(RSUBLE, RSUBLE, "rsuble"),
27693 +    NORMAL_MNEMONIC(RSUBHI, RSUBHI, "rsubhi"),
27694 +    NORMAL_MNEMONIC(RSUBVS, RSUBVS, "rsubvs"),
27695 +    NORMAL_MNEMONIC(RSUBVC, RSUBVC, "rsubvc"),
27696 +    NORMAL_MNEMONIC(RSUBQS, RSUBQS, "rsubqs"),
27697 +    NORMAL_MNEMONIC(RSUBAL, RSUBAL, "rsubal"),
27698 +    NORMAL_MNEMONIC(RSUBHS, RSUBHS, "rsubhs"),
27699 +    NORMAL_MNEMONIC(RSUBLO, RSUBLO, "rsublo"),
27700 +    NORMAL_MNEMONIC(ADDEQ, ADDEQ, "addeq"),
27701 +    NORMAL_MNEMONIC(ADDNE, ADDNE, "addne"),
27702 +    NORMAL_MNEMONIC(ADDCC, ADDCC, "addcc"),
27703 +    NORMAL_MNEMONIC(ADDCS, ADDCS, "addcs"),
27704 +    NORMAL_MNEMONIC(ADDGE, ADDGE, "addge"),
27705 +    NORMAL_MNEMONIC(ADDLT, ADDLT, "addlt"),
27706 +    NORMAL_MNEMONIC(ADDMI, ADDMI, "addmi"),
27707 +    NORMAL_MNEMONIC(ADDPL, ADDPL, "addpl"),
27708 +    NORMAL_MNEMONIC(ADDLS, ADDLS, "addls"),
27709 +    NORMAL_MNEMONIC(ADDGT, ADDGT, "addgt"),
27710 +    NORMAL_MNEMONIC(ADDLE, ADDLE, "addle"),
27711 +    NORMAL_MNEMONIC(ADDHI, ADDHI, "addhi"),
27712 +    NORMAL_MNEMONIC(ADDVS, ADDVS, "addvs"),
27713 +    NORMAL_MNEMONIC(ADDVC, ADDVC, "addvc"),
27714 +    NORMAL_MNEMONIC(ADDQS, ADDQS, "addqs"),
27715 +    NORMAL_MNEMONIC(ADDAL, ADDAL, "addal"),
27716 +    NORMAL_MNEMONIC(ADDHS, ADDHS, "addhs"),
27717 +    NORMAL_MNEMONIC(ADDLO, ADDLO, "addlo"),
27718 +    NORMAL_MNEMONIC(ANDEQ, ANDEQ, "andeq"),
27719 +    NORMAL_MNEMONIC(ANDNE, ANDNE, "andne"),
27720 +    NORMAL_MNEMONIC(ANDCC, ANDCC, "andcc"),
27721 +    NORMAL_MNEMONIC(ANDCS, ANDCS, "andcs"),
27722 +    NORMAL_MNEMONIC(ANDGE, ANDGE, "andge"),
27723 +    NORMAL_MNEMONIC(ANDLT, ANDLT, "andlt"),
27724 +    NORMAL_MNEMONIC(ANDMI, ANDMI, "andmi"),
27725 +    NORMAL_MNEMONIC(ANDPL, ANDPL, "andpl"),
27726 +    NORMAL_MNEMONIC(ANDLS, ANDLS, "andls"),
27727 +    NORMAL_MNEMONIC(ANDGT, ANDGT, "andgt"),
27728 +    NORMAL_MNEMONIC(ANDLE, ANDLE, "andle"),
27729 +    NORMAL_MNEMONIC(ANDHI, ANDHI, "andhi"),
27730 +    NORMAL_MNEMONIC(ANDVS, ANDVS, "andvs"),
27731 +    NORMAL_MNEMONIC(ANDVC, ANDVC, "andvc"),
27732 +    NORMAL_MNEMONIC(ANDQS, ANDQS, "andqs"),
27733 +    NORMAL_MNEMONIC(ANDAL, ANDAL, "andal"),
27734 +    NORMAL_MNEMONIC(ANDHS, ANDHS, "andhs"),
27735 +    NORMAL_MNEMONIC(ANDLO, ANDLO, "andlo"),
27736 +    NORMAL_MNEMONIC(OREQ, OREQ, "oreq"),
27737 +    NORMAL_MNEMONIC(ORNE, ORNE, "orne"),
27738 +    NORMAL_MNEMONIC(ORCC, ORCC, "orcc"),
27739 +    NORMAL_MNEMONIC(ORCS, ORCS, "orcs"),
27740 +    NORMAL_MNEMONIC(ORGE, ORGE, "orge"),
27741 +    NORMAL_MNEMONIC(ORLT, ORLT, "orlt"),
27742 +    NORMAL_MNEMONIC(ORMI, ORMI, "ormi"),
27743 +    NORMAL_MNEMONIC(ORPL, ORPL, "orpl"),
27744 +    NORMAL_MNEMONIC(ORLS, ORLS, "orls"),
27745 +    NORMAL_MNEMONIC(ORGT, ORGT, "orgt"),
27746 +    NORMAL_MNEMONIC(ORLE, ORLE, "orle"),
27747 +    NORMAL_MNEMONIC(ORHI, ORHI, "orhi"),
27748 +    NORMAL_MNEMONIC(ORVS, ORVS, "orvs"),
27749 +    NORMAL_MNEMONIC(ORVC, ORVC, "orvc"),
27750 +    NORMAL_MNEMONIC(ORQS, ORQS, "orqs"),
27751 +    NORMAL_MNEMONIC(ORAL, ORAL, "oral"),
27752 +    NORMAL_MNEMONIC(ORHS, ORHS, "orhs"),
27753 +    NORMAL_MNEMONIC(ORLO, ORLO, "orlo"),
27754 +    NORMAL_MNEMONIC(EOREQ, EOREQ, "eoreq"),
27755 +    NORMAL_MNEMONIC(EORNE, EORNE, "eorne"),
27756 +    NORMAL_MNEMONIC(EORCC, EORCC, "eorcc"),
27757 +    NORMAL_MNEMONIC(EORCS, EORCS, "eorcs"),
27758 +    NORMAL_MNEMONIC(EORGE, EORGE, "eorge"),
27759 +    NORMAL_MNEMONIC(EORLT, EORLT, "eorlt"),
27760 +    NORMAL_MNEMONIC(EORMI, EORMI, "eormi"),
27761 +    NORMAL_MNEMONIC(EORPL, EORPL, "eorpl"),
27762 +    NORMAL_MNEMONIC(EORLS, EORLS, "eorls"),
27763 +    NORMAL_MNEMONIC(EORGT, EORGT, "eorgt"),
27764 +    NORMAL_MNEMONIC(EORLE, EORLE, "eorle"),
27765 +    NORMAL_MNEMONIC(EORHI, EORHI, "eorhi"),
27766 +    NORMAL_MNEMONIC(EORVS, EORVS, "eorvs"),
27767 +    NORMAL_MNEMONIC(EORVC, EORVC, "eorvc"),
27768 +    NORMAL_MNEMONIC(EORQS, EORQS, "eorqs"),
27769 +    NORMAL_MNEMONIC(EORAL, EORAL, "eoral"),
27770 +    NORMAL_MNEMONIC(EORHS, EORHS, "eorhs"),
27771 +    NORMAL_MNEMONIC(EORLO, EORLO, "eorlo"),
27772 +    NORMAL_MNEMONIC(LD_WEQ, LD_WEQ, "ld.weq"),
27773 +    NORMAL_MNEMONIC(LD_WNE, LD_WNE, "ld.wne"),
27774 +    NORMAL_MNEMONIC(LD_WCC, LD_WCC, "ld.wcc"),
27775 +    NORMAL_MNEMONIC(LD_WCS, LD_WCS, "ld.wcs"),
27776 +    NORMAL_MNEMONIC(LD_WGE, LD_WGE, "ld.wge"),
27777 +    NORMAL_MNEMONIC(LD_WLT, LD_WLT, "ld.wlt"),
27778 +    NORMAL_MNEMONIC(LD_WMI, LD_WMI, "ld.wmi"),
27779 +    NORMAL_MNEMONIC(LD_WPL, LD_WPL, "ld.wpl"),
27780 +    NORMAL_MNEMONIC(LD_WLS, LD_WLS, "ld.wls"),
27781 +    NORMAL_MNEMONIC(LD_WGT, LD_WGT, "ld.wgt"),
27782 +    NORMAL_MNEMONIC(LD_WLE, LD_WLE, "ld.wle"),
27783 +    NORMAL_MNEMONIC(LD_WHI, LD_WHI, "ld.whi"),
27784 +    NORMAL_MNEMONIC(LD_WVS, LD_WVS, "ld.wvs"),
27785 +    NORMAL_MNEMONIC(LD_WVC, LD_WVC, "ld.wvc"),
27786 +    NORMAL_MNEMONIC(LD_WQS, LD_WQS, "ld.wqs"),
27787 +    NORMAL_MNEMONIC(LD_WAL, LD_WAL, "ld.wal"),
27788 +    NORMAL_MNEMONIC(LD_WHS, LD_WHS, "ld.whs"),
27789 +    NORMAL_MNEMONIC(LD_WLO, LD_WLO, "ld.wlo"),
27790 +    NORMAL_MNEMONIC(LD_SHEQ, LD_SHEQ, "ld.sheq"),
27791 +    NORMAL_MNEMONIC(LD_SHNE, LD_SHNE, "ld.shne"),
27792 +    NORMAL_MNEMONIC(LD_SHCC, LD_SHCC, "ld.shcc"),
27793 +    NORMAL_MNEMONIC(LD_SHCS, LD_SHCS, "ld.shcs"),
27794 +    NORMAL_MNEMONIC(LD_SHGE, LD_SHGE, "ld.shge"),
27795 +    NORMAL_MNEMONIC(LD_SHLT, LD_SHLT, "ld.shlt"),
27796 +    NORMAL_MNEMONIC(LD_SHMI, LD_SHMI, "ld.shmi"),
27797 +    NORMAL_MNEMONIC(LD_SHPL, LD_SHPL, "ld.shpl"),
27798 +    NORMAL_MNEMONIC(LD_SHLS, LD_SHLS, "ld.shls"),
27799 +    NORMAL_MNEMONIC(LD_SHGT, LD_SHGT, "ld.shgt"),
27800 +    NORMAL_MNEMONIC(LD_SHLE, LD_SHLE, "ld.shle"),
27801 +    NORMAL_MNEMONIC(LD_SHHI, LD_SHHI, "ld.shhi"),
27802 +    NORMAL_MNEMONIC(LD_SHVS, LD_SHVS, "ld.shvs"),
27803 +    NORMAL_MNEMONIC(LD_SHVC, LD_SHVC, "ld.shvc"),
27804 +    NORMAL_MNEMONIC(LD_SHQS, LD_SHQS, "ld.shqs"),
27805 +    NORMAL_MNEMONIC(LD_SHAL, LD_SHAL, "ld.shal"),
27806 +    NORMAL_MNEMONIC(LD_SHHS, LD_SHHS, "ld.shhs"),
27807 +    NORMAL_MNEMONIC(LD_SHLO, LD_SHLO, "ld.shlo"),
27808 +    NORMAL_MNEMONIC(LD_UHEQ, LD_UHEQ, "ld.uheq"),
27809 +    NORMAL_MNEMONIC(LD_UHNE, LD_UHNE, "ld.uhne"),
27810 +    NORMAL_MNEMONIC(LD_UHCC, LD_UHCC, "ld.uhcc"),
27811 +    NORMAL_MNEMONIC(LD_UHCS, LD_UHCS, "ld.uhcs"),
27812 +    NORMAL_MNEMONIC(LD_UHGE, LD_UHGE, "ld.uhge"),
27813 +    NORMAL_MNEMONIC(LD_UHLT, LD_UHLT, "ld.uhlt"),
27814 +    NORMAL_MNEMONIC(LD_UHMI, LD_UHMI, "ld.uhmi"),
27815 +    NORMAL_MNEMONIC(LD_UHPL, LD_UHPL, "ld.uhpl"),
27816 +    NORMAL_MNEMONIC(LD_UHLS, LD_UHLS, "ld.uhls"),
27817 +    NORMAL_MNEMONIC(LD_UHGT, LD_UHGT, "ld.uhgt"),
27818 +    NORMAL_MNEMONIC(LD_UHLE, LD_UHLE, "ld.uhle"),
27819 +    NORMAL_MNEMONIC(LD_UHHI, LD_UHHI, "ld.uhhi"),
27820 +    NORMAL_MNEMONIC(LD_UHVS, LD_UHVS, "ld.uhvs"),
27821 +    NORMAL_MNEMONIC(LD_UHVC, LD_UHVC, "ld.uhvc"),
27822 +    NORMAL_MNEMONIC(LD_UHQS, LD_UHQS, "ld.uhqs"),
27823 +    NORMAL_MNEMONIC(LD_UHAL, LD_UHAL, "ld.uhal"),
27824 +    NORMAL_MNEMONIC(LD_UHHS, LD_UHHS, "ld.uhhs"),
27825 +    NORMAL_MNEMONIC(LD_UHLO, LD_UHLO, "ld.uhlo"),
27826 +    NORMAL_MNEMONIC(LD_SBEQ, LD_SBEQ, "ld.sbeq"),
27827 +    NORMAL_MNEMONIC(LD_SBNE, LD_SBNE, "ld.sbne"),
27828 +    NORMAL_MNEMONIC(LD_SBCC, LD_SBCC, "ld.sbcc"),
27829 +    NORMAL_MNEMONIC(LD_SBCS, LD_SBCS, "ld.sbcs"),
27830 +    NORMAL_MNEMONIC(LD_SBGE, LD_SBGE, "ld.sbge"),
27831 +    NORMAL_MNEMONIC(LD_SBLT, LD_SBLT, "ld.sblt"),
27832 +    NORMAL_MNEMONIC(LD_SBMI, LD_SBMI, "ld.sbmi"),
27833 +    NORMAL_MNEMONIC(LD_SBPL, LD_SBPL, "ld.sbpl"),
27834 +    NORMAL_MNEMONIC(LD_SBLS, LD_SBLS, "ld.sbls"),
27835 +    NORMAL_MNEMONIC(LD_SBGT, LD_SBGT, "ld.sbgt"),
27836 +    NORMAL_MNEMONIC(LD_SBLE, LD_SBLE, "ld.sble"),
27837 +    NORMAL_MNEMONIC(LD_SBHI, LD_SBHI, "ld.sbhi"),
27838 +    NORMAL_MNEMONIC(LD_SBVS, LD_SBVS, "ld.sbvs"),
27839 +    NORMAL_MNEMONIC(LD_SBVC, LD_SBVC, "ld.sbvc"),
27840 +    NORMAL_MNEMONIC(LD_SBQS, LD_SBQS, "ld.sbqs"),
27841 +    NORMAL_MNEMONIC(LD_SBAL, LD_SBAL, "ld.sbal"),
27842 +    NORMAL_MNEMONIC(LD_SBHS, LD_SBHS, "ld.sbhs"),
27843 +    NORMAL_MNEMONIC(LD_SBLO, LD_SBLO, "ld.sblo"),
27844 +    NORMAL_MNEMONIC(LD_UBEQ, LD_UBEQ, "ld.ubeq"),
27845 +    NORMAL_MNEMONIC(LD_UBNE, LD_UBNE, "ld.ubne"),
27846 +    NORMAL_MNEMONIC(LD_UBCC, LD_UBCC, "ld.ubcc"),
27847 +    NORMAL_MNEMONIC(LD_UBCS, LD_UBCS, "ld.ubcs"),
27848 +    NORMAL_MNEMONIC(LD_UBGE, LD_UBGE, "ld.ubge"),
27849 +    NORMAL_MNEMONIC(LD_UBLT, LD_UBLT, "ld.ublt"),
27850 +    NORMAL_MNEMONIC(LD_UBMI, LD_UBMI, "ld.ubmi"),
27851 +    NORMAL_MNEMONIC(LD_UBPL, LD_UBPL, "ld.ubpl"),
27852 +    NORMAL_MNEMONIC(LD_UBLS, LD_UBLS, "ld.ubls"),
27853 +    NORMAL_MNEMONIC(LD_UBGT, LD_UBGT, "ld.ubgt"),
27854 +    NORMAL_MNEMONIC(LD_UBLE, LD_UBLE, "ld.uble"),
27855 +    NORMAL_MNEMONIC(LD_UBHI, LD_UBHI, "ld.ubhi"),
27856 +    NORMAL_MNEMONIC(LD_UBVS, LD_UBVS, "ld.ubvs"),
27857 +    NORMAL_MNEMONIC(LD_UBVC, LD_UBVC, "ld.ubvc"),
27858 +    NORMAL_MNEMONIC(LD_UBQS, LD_UBQS, "ld.ubqs"),
27859 +    NORMAL_MNEMONIC(LD_UBAL, LD_UBAL, "ld.ubal"),
27860 +    NORMAL_MNEMONIC(LD_UBHS, LD_UBHS, "ld.ubhs"),
27861 +    NORMAL_MNEMONIC(LD_UBLO, LD_UBLO, "ld.ublo"),
27862 +    NORMAL_MNEMONIC(ST_WEQ, ST_WEQ, "st.weq"),
27863 +    NORMAL_MNEMONIC(ST_WNE, ST_WNE, "st.wne"),
27864 +    NORMAL_MNEMONIC(ST_WCC, ST_WCC, "st.wcc"),
27865 +    NORMAL_MNEMONIC(ST_WCS, ST_WCS, "st.wcs"),
27866 +    NORMAL_MNEMONIC(ST_WGE, ST_WGE, "st.wge"),
27867 +    NORMAL_MNEMONIC(ST_WLT, ST_WLT, "st.wlt"),
27868 +    NORMAL_MNEMONIC(ST_WMI, ST_WMI, "st.wmi"),
27869 +    NORMAL_MNEMONIC(ST_WPL, ST_WPL, "st.wpl"),
27870 +    NORMAL_MNEMONIC(ST_WLS, ST_WLS, "st.wls"),
27871 +    NORMAL_MNEMONIC(ST_WGT, ST_WGT, "st.wgt"),
27872 +    NORMAL_MNEMONIC(ST_WLE, ST_WLE, "st.wle"),
27873 +    NORMAL_MNEMONIC(ST_WHI, ST_WHI, "st.whi"),
27874 +    NORMAL_MNEMONIC(ST_WVS, ST_WVS, "st.wvs"),
27875 +    NORMAL_MNEMONIC(ST_WVC, ST_WVC, "st.wvc"),
27876 +    NORMAL_MNEMONIC(ST_WQS, ST_WQS, "st.wqs"),
27877 +    NORMAL_MNEMONIC(ST_WAL, ST_WAL, "st.wal"),
27878 +    NORMAL_MNEMONIC(ST_WHS, ST_WHS, "st.whs"),
27879 +    NORMAL_MNEMONIC(ST_WLO, ST_WLO, "st.wlo"),
27880 +    NORMAL_MNEMONIC(ST_HEQ, ST_HEQ, "st.heq"),
27881 +    NORMAL_MNEMONIC(ST_HNE, ST_HNE, "st.hne"),
27882 +    NORMAL_MNEMONIC(ST_HCC, ST_HCC, "st.hcc"),
27883 +    NORMAL_MNEMONIC(ST_HCS, ST_HCS, "st.hcs"),
27884 +    NORMAL_MNEMONIC(ST_HGE, ST_HGE, "st.hge"),
27885 +    NORMAL_MNEMONIC(ST_HLT, ST_HLT, "st.hlt"),
27886 +    NORMAL_MNEMONIC(ST_HMI, ST_HMI, "st.hmi"),
27887 +    NORMAL_MNEMONIC(ST_HPL, ST_HPL, "st.hpl"),
27888 +    NORMAL_MNEMONIC(ST_HLS, ST_HLS, "st.hls"),
27889 +    NORMAL_MNEMONIC(ST_HGT, ST_HGT, "st.hgt"),
27890 +    NORMAL_MNEMONIC(ST_HLE, ST_HLE, "st.hle"),
27891 +    NORMAL_MNEMONIC(ST_HHI, ST_HHI, "st.hhi"),
27892 +    NORMAL_MNEMONIC(ST_HVS, ST_HVS, "st.hvs"),
27893 +    NORMAL_MNEMONIC(ST_HVC, ST_HVC, "st.hvc"),
27894 +    NORMAL_MNEMONIC(ST_HQS, ST_HQS, "st.hqs"),
27895 +    NORMAL_MNEMONIC(ST_HAL, ST_HAL, "st.hal"),
27896 +    NORMAL_MNEMONIC(ST_HHS, ST_HHS, "st.hhs"),
27897 +    NORMAL_MNEMONIC(ST_HLO, ST_HLO, "st.hlo"),
27898 +    NORMAL_MNEMONIC(ST_BEQ, ST_BEQ, "st.beq"),
27899 +    NORMAL_MNEMONIC(ST_BNE, ST_BNE, "st.bne"),
27900 +    NORMAL_MNEMONIC(ST_BCC, ST_BCC, "st.bcc"),
27901 +    NORMAL_MNEMONIC(ST_BCS, ST_BCS, "st.bcs"),
27902 +    NORMAL_MNEMONIC(ST_BGE, ST_BGE, "st.bge"),
27903 +    NORMAL_MNEMONIC(ST_BLT, ST_BLT, "st.blt"),
27904 +    NORMAL_MNEMONIC(ST_BMI, ST_BMI, "st.bmi"),
27905 +    NORMAL_MNEMONIC(ST_BPL, ST_BPL, "st.bpl"),
27906 +    NORMAL_MNEMONIC(ST_BLS, ST_BLS, "st.bls"),
27907 +    NORMAL_MNEMONIC(ST_BGT, ST_BGT, "st.bgt"),
27908 +    NORMAL_MNEMONIC(ST_BLE, ST_BLE, "st.ble"),
27909 +    NORMAL_MNEMONIC(ST_BHI, ST_BHI, "st.bhi"),
27910 +    NORMAL_MNEMONIC(ST_BVS, ST_BVS, "st.bvs"),
27911 +    NORMAL_MNEMONIC(ST_BVC, ST_BVC, "st.bvc"),
27912 +    NORMAL_MNEMONIC(ST_BQS, ST_BQS, "st.bqs"),
27913 +    NORMAL_MNEMONIC(ST_BAL, ST_BAL, "st.bal"),
27914 +    NORMAL_MNEMONIC(ST_BHS, ST_BHS, "st.bhs"),
27915 +    NORMAL_MNEMONIC(ST_BLO, ST_BLO, "st.blo"),
27916 +    NORMAL_MNEMONIC(MOVH, MOVH, "movh"),
27917 +
27918 +  };
27919 +#undef NORMAL_MNEMONIC
27920 +#undef ALIAS_MNEMONIC
27921 +#undef FP_MNEMONIC
27922 --- /dev/null
27923 +++ b/opcodes/avr32-opc.h
27924 @@ -0,0 +1,2341 @@
27925 +/* Opcode tables for AVR32.
27926 +   Copyright 2005,2006,2007,2008,2009 Atmel Corporation.
27927 +
27928 +   Written by Haavard Skinnemoen, Atmel Norway, <hskinnemoen@atmel.com>
27929 +
27930 +   This file is part of libopcodes.
27931 +
27932 +   This program is free software; you can redistribute it and/or
27933 +   modify it under the terms of the GNU General Public License as
27934 +   published by the Free Software Foundation; either version 2 of the
27935 +   License, or (at your option) any later version.
27936 +
27937 +   This program is distributed in the hope that it will be useful, but
27938 +   WITHOUT ANY WARRANTY; without even the implied warranty of
27939 +   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
27940 +   General Public License for more details.
27941 +
27942 +   You should have received a copy of the GNU General Public License
27943 +   along with this program; if not, write to the Free Software
27944 +   Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA
27945 +   02111-1307, USA.  */
27946 +
27947 +#include "bfd.h"
27948 +
27949 +#define AVR32_MAX_OPERANDS     8
27950 +#define AVR32_MAX_FIELDS       8
27951 +
27952 +#define AVR32_V1               (1 << 1)
27953 +#define AVR32_SIMD             (1 << 2)
27954 +#define AVR32_DSP              (1 << 3)
27955 +#define AVR32_RMW              (1 << 4)
27956 +#define AVR32_V2               (1 << 5)
27957 +#define AVR32_V3               (1 << 6)
27958 +#define AVR32_V3FP             (1 << 7)
27959 +#define AVR32_PICO             (1 << 17)
27960 +
27961 +/* Registers we commonly refer to */
27962 +#define AVR32_REG_R12          12
27963 +#define AVR32_REG_SP           13
27964 +#define AVR32_REG_LR           14
27965 +#define AVR32_REG_PC           15
27966 +
27967 +struct avr32_ifield
27968 +{
27969 +  int id;
27970 +  unsigned short bitsize;
27971 +  unsigned short shift;
27972 +  unsigned long mask;
27973 +
27974 +  /* If the value doesn't fit, it will be truncated with no warning */
27975 +  void (*insert)(const struct avr32_ifield *, void *, unsigned long);
27976 +  void (*extract)(const struct avr32_ifield *, void *, unsigned long *);
27977 +};
27978 +
27979 +struct avr32_opcode
27980 +{
27981 +  int id;
27982 +  int size;
27983 +  unsigned long value;
27984 +  unsigned long mask;
27985 +  const struct avr32_syntax *syntax;
27986 +  bfd_reloc_code_real_type reloc_type;
27987 +  unsigned int nr_fields;
27988 +  /* if relaxable, which field is variable, otherwise -1 */
27989 +  int var_field;
27990 +  const struct avr32_ifield *fields[AVR32_MAX_FIELDS];
27991 +};
27992 +
27993 +struct avr32_alias
27994 +{
27995 +  int id;
27996 +  const struct avr32_opcode *opc;
27997 +  struct {
27998 +    int is_opindex;
27999 +    unsigned long value;
28000 +  } operand_map[AVR32_MAX_OPERANDS];
28001 +};
28002 +
28003 +struct avr32_syntax
28004 +{
28005 +  int id;
28006 +  unsigned long isa_flags;
28007 +  const struct avr32_mnemonic *mnemonic;
28008 +  int type;
28009 +  union {
28010 +    const struct avr32_opcode *opc;
28011 +    const struct avr32_alias *alias;
28012 +  } u;
28013 +  const struct avr32_syntax *next;
28014 +  /* negative means "vararg" */
28015 +  int nr_operands;
28016 +  int operand[AVR32_MAX_OPERANDS];
28017 +};
28018 +
28019 +#if 0
28020 +#define AVR32_ALIAS_MAKE_CONST(val) ((val) | 0x80000000UL)
28021 +#define AVR32_ALIAS_IS_CONST(mapval) (((mapval) & 0x80000000UL) != 0)
28022 +#define AVR32_ALIAS_GET_CONST(mapval) ((mapval) & ~0x80000000UL)
28023 +#endif
28024 +
28025 +struct avr32_mnemonic
28026 +{
28027 +  int id;
28028 +  const char *name;
28029 +  const struct avr32_syntax *syntax;
28030 +};
28031 +
28032 +extern const struct avr32_ifield avr32_ifield_table[];
28033 +extern struct avr32_opcode avr32_opc_table[];
28034 +extern const struct avr32_syntax avr32_syntax_table[];
28035 +extern const struct avr32_alias avr32_alias_table[];
28036 +extern const struct avr32_mnemonic avr32_mnemonic_table[];
28037 +
28038 +extern void avr32_insert_simple(const struct avr32_ifield *field,
28039 +                               void *buf, unsigned long value);
28040 +extern void avr32_insert_bit5c(const struct avr32_ifield *field,
28041 +                              void *buf, unsigned long value);
28042 +extern void avr32_insert_k10(const struct avr32_ifield *field,
28043 +                            void *buf, unsigned long value);
28044 +extern void avr32_insert_k21(const struct avr32_ifield *field,
28045 +                            void *buf, unsigned long value);
28046 +extern void avr32_insert_cpop(const struct avr32_ifield *field,
28047 +                             void *buf, unsigned long value);
28048 +extern void avr32_insert_k12cp(const struct avr32_ifield *field,
28049 +                              void *buf, unsigned long value);
28050 +
28051 +extern void avr32_extract_simple(const struct avr32_ifield *field,
28052 +                                void *buf, unsigned long *value);
28053 +extern void avr32_extract_bit5c(const struct avr32_ifield *field,
28054 +                               void *buf, unsigned long *value);
28055 +extern void avr32_extract_k10(const struct avr32_ifield *field,
28056 +                             void *buf, unsigned long *value);
28057 +extern void avr32_extract_k21(const struct avr32_ifield *field,
28058 +                             void *buf, unsigned long *value);
28059 +extern void avr32_extract_cpop(const struct avr32_ifield *field,
28060 +                              void *buf, unsigned long *value);
28061 +extern void avr32_extract_k12cp(const struct avr32_ifield *field,
28062 +                               void *buf, unsigned long *value);
28063 +
28064 +enum avr32_operand_type
28065 +{
28066 +  AVR32_OPERAND_INTREG,                /* just a register */
28067 +  AVR32_OPERAND_INTREG_PREDEC, /* register with pre-decrement */
28068 +  AVR32_OPERAND_INTREG_POSTINC,        /* register with post-increment */
28069 +  AVR32_OPERAND_INTREG_LSL,    /* register with left shift */
28070 +  AVR32_OPERAND_INTREG_LSR,    /* register with right shift */
28071 +  AVR32_OPERAND_INTREG_BSEL,   /* register with byte selector */
28072 +  AVR32_OPERAND_INTREG_HSEL,   /* register with halfword selector */
28073 +  AVR32_OPERAND_INTREG_SDISP,  /* Rp[signed disp] */
28074 +  AVR32_OPERAND_INTREG_SDISP_H,        /* Rp[signed hword-aligned disp] */
28075 +  AVR32_OPERAND_INTREG_SDISP_W,        /* Rp[signed word-aligned disp] */
28076 +  AVR32_OPERAND_INTREG_UDISP,  /* Rp[unsigned disp] */
28077 +  AVR32_OPERAND_INTREG_UDISP_H,        /* Rp[unsigned hword-aligned disp] */
28078 +  AVR32_OPERAND_INTREG_UDISP_W, /* Rp[unsigned word-aligned disp] */
28079 +  AVR32_OPERAND_INTREG_INDEX,  /* Rp[Ri << sa] */
28080 +  AVR32_OPERAND_INTREG_XINDEX, /* Rp[Ri:bytesel << 2] */
28081 +  AVR32_OPERAND_DWREG,         /* Even-numbered register */
28082 +  AVR32_OPERAND_PC_UDISP_W,    /* PC[unsigned word-aligned disp] or label */
28083 +  AVR32_OPERAND_SP,            /* Just SP */
28084 +  AVR32_OPERAND_SP_UDISP_W,    /* SP[unsigned word-aligned disp] */
28085 +  AVR32_OPERAND_CPNO,
28086 +  AVR32_OPERAND_CPREG,
28087 +  AVR32_OPERAND_CPREG_D,
28088 +  AVR32_OPERAND_UNSIGNED_CONST,
28089 +  AVR32_OPERAND_UNSIGNED_CONST_W,
28090 +  AVR32_OPERAND_SIGNED_CONST,
28091 +  AVR32_OPERAND_SIGNED_CONST_W,
28092 +  AVR32_OPERAND_JMPLABEL,
28093 +  AVR32_OPERAND_UNSIGNED_NUMBER,
28094 +  AVR32_OPERAND_UNSIGNED_NUMBER_W,
28095 +  AVR32_OPERAND_REGLIST8,
28096 +  AVR32_OPERAND_REGLIST9,
28097 +  AVR32_OPERAND_REGLIST16,
28098 +  AVR32_OPERAND_REGLIST_LDM,
28099 +  AVR32_OPERAND_REGLIST_CP8,
28100 +  AVR32_OPERAND_REGLIST_CPD8,
28101 +  AVR32_OPERAND_RETVAL,
28102 +  AVR32_OPERAND_MCALL,
28103 +  AVR32_OPERAND_JOSPINC,
28104 +  AVR32_OPERAND_COH,
28105 +  AVR32_OPERAND_PICO_REG_W,
28106 +  AVR32_OPERAND_PICO_REG_D,
28107 +  AVR32_OPERAND_PICO_REGLIST_W,
28108 +  AVR32_OPERAND_PICO_REGLIST_D,
28109 +  AVR32_OPERAND_PICO_IN,
28110 +  AVR32_OPERAND_PICO_OUT0,
28111 +  AVR32_OPERAND_PICO_OUT1,
28112 +  AVR32_OPERAND_PICO_OUT2,
28113 +  AVR32_OPERAND_PICO_OUT3,
28114 +  AVR32_OPERAND__END_
28115 +};
28116 +#define AVR32_OPERAND_UNKNOWN AVR32_OPERAND__END_
28117 +#define AVR32_NR_OPERANDS AVR32_OPERAND__END_
28118 +
28119 +enum avr32_ifield_type
28120 +{
28121 +  AVR32_IFIELD_RX,
28122 +  AVR32_IFIELD_RY,
28123 +  AVR32_IFIELD_COND4C,
28124 +  AVR32_IFIELD_K8C,
28125 +  AVR32_IFIELD_K7C,
28126 +  AVR32_IFIELD_K5C,
28127 +  AVR32_IFIELD_K3,
28128 +  AVR32_IFIELD_RY_DW,
28129 +  AVR32_IFIELD_COND4E,
28130 +  AVR32_IFIELD_K8E,
28131 +  AVR32_IFIELD_BIT5C,
28132 +  AVR32_IFIELD_COND3,
28133 +  AVR32_IFIELD_K10,
28134 +  AVR32_IFIELD_POPM,
28135 +  AVR32_IFIELD_K2,
28136 +  AVR32_IFIELD_RD_E,
28137 +  AVR32_IFIELD_RD_DW,
28138 +  AVR32_IFIELD_X,
28139 +  AVR32_IFIELD_Y,
28140 +  AVR32_IFIELD_X2,
28141 +  AVR32_IFIELD_Y2,
28142 +  AVR32_IFIELD_K5E,
28143 +  AVR32_IFIELD_PART2,
28144 +  AVR32_IFIELD_PART1,
28145 +  AVR32_IFIELD_K16,
28146 +  AVR32_IFIELD_CACHEOP,
28147 +  AVR32_IFIELD_K11,
28148 +  AVR32_IFIELD_K21,
28149 +  AVR32_IFIELD_CPOP,
28150 +  AVR32_IFIELD_CPNO,
28151 +  AVR32_IFIELD_CRD_RI,
28152 +  AVR32_IFIELD_CRX,
28153 +  AVR32_IFIELD_CRY,
28154 +  AVR32_IFIELD_K7E,
28155 +  AVR32_IFIELD_CRD_DW,
28156 +  AVR32_IFIELD_PART1_K12,
28157 +  AVR32_IFIELD_PART2_K12,
28158 +  AVR32_IFIELD_K12,
28159 +  AVR32_IFIELD_S5,
28160 +  AVR32_IFIELD_K5E2,
28161 +  AVR32_IFIELD_K4,
28162 +  AVR32_IFIELD_COND4E2,
28163 +  AVR32_IFIELD_K8E2,
28164 +  AVR32_IFIELD_K6,
28165 +  AVR32_IFIELD_MEM15,
28166 +  AVR32_IFIELD_MEMB5,
28167 +  AVR32_IFIELD_W,
28168 +  AVR32_IFIELD_CM_HL,
28169 +  AVR32_IFIELD_K12CP,
28170 +  AVR32_IFIELD_K9E,
28171 +  AVR32_IFIELD_FP_RX,
28172 +  AVR32_IFIELD_FP_RY,
28173 +  AVR32_IFIELD_FP_RD,
28174 +  AVR32_IFIELD_FP_RA,
28175 +  AVR32_IFIELD__END_,
28176 +};
28177 +#define AVR32_NR_IFIELDS AVR32_IFIELD__END_
28178 +
28179 +enum avr32_opc_type
28180 +{
28181 +  AVR32_OPC_ABS,
28182 +  AVR32_OPC_ACALL,
28183 +  AVR32_OPC_ACR,
28184 +  AVR32_OPC_ADC,
28185 +  AVR32_OPC_ADD1,
28186 +  AVR32_OPC_ADD2,
28187 +  AVR32_OPC_ADDABS,
28188 +  AVR32_OPC_ADDHH_W,
28189 +  AVR32_OPC_AND1,
28190 +  AVR32_OPC_AND2,
28191 +  AVR32_OPC_AND3,
28192 +  AVR32_OPC_ANDH,
28193 +  AVR32_OPC_ANDH_COH,
28194 +  AVR32_OPC_ANDL,
28195 +  AVR32_OPC_ANDL_COH,
28196 +  AVR32_OPC_ANDN,
28197 +  AVR32_OPC_ASR1,
28198 +  AVR32_OPC_ASR3,
28199 +  AVR32_OPC_ASR2,
28200 +  AVR32_OPC_BLD,
28201 +  AVR32_OPC_BREQ1,
28202 +  AVR32_OPC_BRNE1,
28203 +  AVR32_OPC_BRCC1,
28204 +  AVR32_OPC_BRCS1,
28205 +  AVR32_OPC_BRGE1,
28206 +  AVR32_OPC_BRLT1,
28207 +  AVR32_OPC_BRMI1,
28208 +  AVR32_OPC_BRPL1,
28209 +  AVR32_OPC_BREQ2,
28210 +  AVR32_OPC_BRNE2,
28211 +  AVR32_OPC_BRCC2,
28212 +  AVR32_OPC_BRCS2,
28213 +  AVR32_OPC_BRGE2,
28214 +  AVR32_OPC_BRLT2,
28215 +  AVR32_OPC_BRMI2,
28216 +  AVR32_OPC_BRPL2,
28217 +  AVR32_OPC_BRLS,
28218 +  AVR32_OPC_BRGT,
28219 +  AVR32_OPC_BRLE,
28220 +  AVR32_OPC_BRHI,
28221 +  AVR32_OPC_BRVS,
28222 +  AVR32_OPC_BRVC,
28223 +  AVR32_OPC_BRQS,
28224 +  AVR32_OPC_BRAL,
28225 +  AVR32_OPC_BREAKPOINT,
28226 +  AVR32_OPC_BREV,
28227 +  AVR32_OPC_BST,
28228 +  AVR32_OPC_CACHE,
28229 +  AVR32_OPC_CASTS_B,
28230 +  AVR32_OPC_CASTS_H,
28231 +  AVR32_OPC_CASTU_B,
28232 +  AVR32_OPC_CASTU_H,
28233 +  AVR32_OPC_CBR,
28234 +  AVR32_OPC_CLZ,
28235 +  AVR32_OPC_COM,
28236 +  AVR32_OPC_COP,
28237 +  AVR32_OPC_CP_B,
28238 +  AVR32_OPC_CP_H,
28239 +  AVR32_OPC_CP_W1,
28240 +  AVR32_OPC_CP_W2,
28241 +  AVR32_OPC_CP_W3,
28242 +  AVR32_OPC_CPC1,
28243 +  AVR32_OPC_CPC2,
28244 +  AVR32_OPC_CSRF,
28245 +  AVR32_OPC_CSRFCZ,
28246 +  AVR32_OPC_DIVS,
28247 +  AVR32_OPC_DIVU,
28248 +  AVR32_OPC_EOR1,
28249 +  AVR32_OPC_EOR2,
28250 +  AVR32_OPC_EOR3,
28251 +  AVR32_OPC_EORL,
28252 +  AVR32_OPC_EORH,
28253 +  AVR32_OPC_FRS,
28254 +  AVR32_OPC_ICALL,
28255 +  AVR32_OPC_INCJOSP,
28256 +  AVR32_OPC_LD_D1,
28257 +  AVR32_OPC_LD_D2,
28258 +  AVR32_OPC_LD_D3,
28259 +  AVR32_OPC_LD_D5,
28260 +  AVR32_OPC_LD_D4,
28261 +  AVR32_OPC_LD_SB2,
28262 +  AVR32_OPC_LD_SB1,
28263 +  AVR32_OPC_LD_UB1,
28264 +  AVR32_OPC_LD_UB2,
28265 +  AVR32_OPC_LD_UB5,
28266 +  AVR32_OPC_LD_UB3,
28267 +  AVR32_OPC_LD_UB4,
28268 +  AVR32_OPC_LD_SH1,
28269 +  AVR32_OPC_LD_SH2,
28270 +  AVR32_OPC_LD_SH5,
28271 +  AVR32_OPC_LD_SH3,
28272 +  AVR32_OPC_LD_SH4,
28273 +  AVR32_OPC_LD_UH1,
28274 +  AVR32_OPC_LD_UH2,
28275 +  AVR32_OPC_LD_UH5,
28276 +  AVR32_OPC_LD_UH3,
28277 +  AVR32_OPC_LD_UH4,
28278 +  AVR32_OPC_LD_W1,
28279 +  AVR32_OPC_LD_W2,
28280 +  AVR32_OPC_LD_W5,
28281 +  AVR32_OPC_LD_W6,
28282 +  AVR32_OPC_LD_W3,
28283 +  AVR32_OPC_LD_W4,
28284 +  AVR32_OPC_LDC_D1,
28285 +  AVR32_OPC_LDC_D2,
28286 +  AVR32_OPC_LDC_D3,
28287 +  AVR32_OPC_LDC_W1,
28288 +  AVR32_OPC_LDC_W2,
28289 +  AVR32_OPC_LDC_W3,
28290 +  AVR32_OPC_LDC0_D,
28291 +  AVR32_OPC_LDC0_W,
28292 +  AVR32_OPC_LDCM_D,
28293 +  AVR32_OPC_LDCM_D_PU,
28294 +  AVR32_OPC_LDCM_W,
28295 +  AVR32_OPC_LDCM_W_PU,
28296 +  AVR32_OPC_LDDPC,
28297 +  AVR32_OPC_LDDPC_EXT,
28298 +  AVR32_OPC_LDDSP,
28299 +  AVR32_OPC_LDINS_B,
28300 +  AVR32_OPC_LDINS_H,
28301 +  AVR32_OPC_LDM,
28302 +  AVR32_OPC_LDMTS,
28303 +  AVR32_OPC_LDMTS_PU,
28304 +  AVR32_OPC_LDSWP_SH,
28305 +  AVR32_OPC_LDSWP_UH,
28306 +  AVR32_OPC_LDSWP_W,
28307 +  AVR32_OPC_LSL1,
28308 +  AVR32_OPC_LSL3,
28309 +  AVR32_OPC_LSL2,
28310 +  AVR32_OPC_LSR1,
28311 +  AVR32_OPC_LSR3,
28312 +  AVR32_OPC_LSR2,
28313 +  AVR32_OPC_MAC,
28314 +  AVR32_OPC_MACHH_D,
28315 +  AVR32_OPC_MACHH_W,
28316 +  AVR32_OPC_MACS_D,
28317 +  AVR32_OPC_MACSATHH_W,
28318 +  AVR32_OPC_MACUD,
28319 +  AVR32_OPC_MACWH_D,
28320 +  AVR32_OPC_MAX,
28321 +  AVR32_OPC_MCALL,
28322 +  AVR32_OPC_MFDR,
28323 +  AVR32_OPC_MFSR,
28324 +  AVR32_OPC_MIN,
28325 +  AVR32_OPC_MOV3,
28326 +  AVR32_OPC_MOV1,
28327 +  AVR32_OPC_MOV2,
28328 +  AVR32_OPC_MOVEQ1,
28329 +  AVR32_OPC_MOVNE1,
28330 +  AVR32_OPC_MOVCC1,
28331 +  AVR32_OPC_MOVCS1,
28332 +  AVR32_OPC_MOVGE1,
28333 +  AVR32_OPC_MOVLT1,
28334 +  AVR32_OPC_MOVMI1,
28335 +  AVR32_OPC_MOVPL1,
28336 +  AVR32_OPC_MOVLS1,
28337 +  AVR32_OPC_MOVGT1,
28338 +  AVR32_OPC_MOVLE1,
28339 +  AVR32_OPC_MOVHI1,
28340 +  AVR32_OPC_MOVVS1,
28341 +  AVR32_OPC_MOVVC1,
28342 +  AVR32_OPC_MOVQS1,
28343 +  AVR32_OPC_MOVAL1,
28344 +  AVR32_OPC_MOVEQ2,
28345 +  AVR32_OPC_MOVNE2,
28346 +  AVR32_OPC_MOVCC2,
28347 +  AVR32_OPC_MOVCS2,
28348 +  AVR32_OPC_MOVGE2,
28349 +  AVR32_OPC_MOVLT2,
28350 +  AVR32_OPC_MOVMI2,
28351 +  AVR32_OPC_MOVPL2,
28352 +  AVR32_OPC_MOVLS2,
28353 +  AVR32_OPC_MOVGT2,
28354 +  AVR32_OPC_MOVLE2,
28355 +  AVR32_OPC_MOVHI2,
28356 +  AVR32_OPC_MOVVS2,
28357 +  AVR32_OPC_MOVVC2,
28358 +  AVR32_OPC_MOVQS2,
28359 +  AVR32_OPC_MOVAL2,
28360 +  AVR32_OPC_MTDR,
28361 +  AVR32_OPC_MTSR,
28362 +  AVR32_OPC_MUL1,
28363 +  AVR32_OPC_MUL2,
28364 +  AVR32_OPC_MUL3,
28365 +  AVR32_OPC_MULHH_W,
28366 +  AVR32_OPC_MULNHH_W,
28367 +  AVR32_OPC_MULNWH_D,
28368 +  AVR32_OPC_MULSD,
28369 +  AVR32_OPC_MULSATHH_H,
28370 +  AVR32_OPC_MULSATHH_W,
28371 +  AVR32_OPC_MULSATRNDHH_H,
28372 +  AVR32_OPC_MULSATRNDWH_W,
28373 +  AVR32_OPC_MULSATWH_W,
28374 +  AVR32_OPC_MULU_D,
28375 +  AVR32_OPC_MULWH_D,
28376 +  AVR32_OPC_MUSFR,
28377 +  AVR32_OPC_MUSTR,
28378 +  AVR32_OPC_MVCR_D,
28379 +  AVR32_OPC_MVCR_W,
28380 +  AVR32_OPC_MVRC_D,
28381 +  AVR32_OPC_MVRC_W,
28382 +  AVR32_OPC_NEG,
28383 +  AVR32_OPC_NOP,
28384 +  AVR32_OPC_OR1,
28385 +  AVR32_OPC_OR2,
28386 +  AVR32_OPC_OR3,
28387 +  AVR32_OPC_ORH,
28388 +  AVR32_OPC_ORL,
28389 +  AVR32_OPC_PABS_SB,
28390 +  AVR32_OPC_PABS_SH,
28391 +  AVR32_OPC_PACKSH_SB,
28392 +  AVR32_OPC_PACKSH_UB,
28393 +  AVR32_OPC_PACKW_SH,
28394 +  AVR32_OPC_PADD_B,
28395 +  AVR32_OPC_PADD_H,
28396 +  AVR32_OPC_PADDH_SH,
28397 +  AVR32_OPC_PADDH_UB,
28398 +  AVR32_OPC_PADDS_SB,
28399 +  AVR32_OPC_PADDS_SH,
28400 +  AVR32_OPC_PADDS_UB,
28401 +  AVR32_OPC_PADDS_UH,
28402 +  AVR32_OPC_PADDSUB_H,
28403 +  AVR32_OPC_PADDSUBH_SH,
28404 +  AVR32_OPC_PADDSUBS_SH,
28405 +  AVR32_OPC_PADDSUBS_UH,
28406 +  AVR32_OPC_PADDX_H,
28407 +  AVR32_OPC_PADDXH_SH,
28408 +  AVR32_OPC_PADDXS_SH,
28409 +  AVR32_OPC_PADDXS_UH,
28410 +  AVR32_OPC_PASR_B,
28411 +  AVR32_OPC_PASR_H,
28412 +  AVR32_OPC_PAVG_SH,
28413 +  AVR32_OPC_PAVG_UB,
28414 +  AVR32_OPC_PLSL_B,
28415 +  AVR32_OPC_PLSL_H,
28416 +  AVR32_OPC_PLSR_B,
28417 +  AVR32_OPC_PLSR_H,
28418 +  AVR32_OPC_PMAX_SH,
28419 +  AVR32_OPC_PMAX_UB,
28420 +  AVR32_OPC_PMIN_SH,
28421 +  AVR32_OPC_PMIN_UB,
28422 +  AVR32_OPC_POPJC,
28423 +  AVR32_OPC_POPM,
28424 +  AVR32_OPC_POPM_E,
28425 +  AVR32_OPC_PREF,
28426 +  AVR32_OPC_PSAD,
28427 +  AVR32_OPC_PSUB_B,
28428 +  AVR32_OPC_PSUB_H,
28429 +  AVR32_OPC_PSUBADD_H,
28430 +  AVR32_OPC_PSUBADDH_SH,
28431 +  AVR32_OPC_PSUBADDS_SH,
28432 +  AVR32_OPC_PSUBADDS_UH,
28433 +  AVR32_OPC_PSUBH_SH,
28434 +  AVR32_OPC_PSUBH_UB,
28435 +  AVR32_OPC_PSUBS_SB,
28436 +  AVR32_OPC_PSUBS_SH,
28437 +  AVR32_OPC_PSUBS_UB,
28438 +  AVR32_OPC_PSUBS_UH,
28439 +  AVR32_OPC_PSUBX_H,
28440 +  AVR32_OPC_PSUBXH_SH,
28441 +  AVR32_OPC_PSUBXS_SH,
28442 +  AVR32_OPC_PSUBXS_UH,
28443 +  AVR32_OPC_PUNPCKSB_H,
28444 +  AVR32_OPC_PUNPCKUB_H,
28445 +  AVR32_OPC_PUSHJC,
28446 +  AVR32_OPC_PUSHM,
28447 +  AVR32_OPC_PUSHM_E,
28448 +  AVR32_OPC_RCALL1,
28449 +  AVR32_OPC_RCALL2,
28450 +  AVR32_OPC_RETEQ,
28451 +  AVR32_OPC_RETNE,
28452 +  AVR32_OPC_RETCC,
28453 +  AVR32_OPC_RETCS,
28454 +  AVR32_OPC_RETGE,
28455 +  AVR32_OPC_RETLT,
28456 +  AVR32_OPC_RETMI,
28457 +  AVR32_OPC_RETPL,
28458 +  AVR32_OPC_RETLS,
28459 +  AVR32_OPC_RETGT,
28460 +  AVR32_OPC_RETLE,
28461 +  AVR32_OPC_RETHI,
28462 +  AVR32_OPC_RETVS,
28463 +  AVR32_OPC_RETVC,
28464 +  AVR32_OPC_RETQS,
28465 +  AVR32_OPC_RETAL,
28466 +  AVR32_OPC_RETD,
28467 +  AVR32_OPC_RETE,
28468 +  AVR32_OPC_RETJ,
28469 +  AVR32_OPC_RETS,
28470 +  AVR32_OPC_RJMP,
28471 +  AVR32_OPC_ROL,
28472 +  AVR32_OPC_ROR,
28473 +  AVR32_OPC_RSUB1,
28474 +  AVR32_OPC_RSUB2,
28475 +  AVR32_OPC_SATADD_H,
28476 +  AVR32_OPC_SATADD_W,
28477 +  AVR32_OPC_SATRNDS,
28478 +  AVR32_OPC_SATRNDU,
28479 +  AVR32_OPC_SATS,
28480 +  AVR32_OPC_SATSUB_H,
28481 +  AVR32_OPC_SATSUB_W1,
28482 +  AVR32_OPC_SATSUB_W2,
28483 +  AVR32_OPC_SATU,
28484 +  AVR32_OPC_SBC,
28485 +  AVR32_OPC_SBR,
28486 +  AVR32_OPC_SCALL,
28487 +  AVR32_OPC_SCR,
28488 +  AVR32_OPC_SLEEP,
28489 +  AVR32_OPC_SREQ,
28490 +  AVR32_OPC_SRNE,
28491 +  AVR32_OPC_SRCC,
28492 +  AVR32_OPC_SRCS,
28493 +  AVR32_OPC_SRGE,
28494 +  AVR32_OPC_SRLT,
28495 +  AVR32_OPC_SRMI,
28496 +  AVR32_OPC_SRPL,
28497 +  AVR32_OPC_SRLS,
28498 +  AVR32_OPC_SRGT,
28499 +  AVR32_OPC_SRLE,
28500 +  AVR32_OPC_SRHI,
28501 +  AVR32_OPC_SRVS,
28502 +  AVR32_OPC_SRVC,
28503 +  AVR32_OPC_SRQS,
28504 +  AVR32_OPC_SRAL,
28505 +  AVR32_OPC_SSRF,
28506 +  AVR32_OPC_ST_B1,
28507 +  AVR32_OPC_ST_B2,
28508 +  AVR32_OPC_ST_B5,
28509 +  AVR32_OPC_ST_B3,
28510 +  AVR32_OPC_ST_B4,
28511 +  AVR32_OPC_ST_D1,
28512 +  AVR32_OPC_ST_D2,
28513 +  AVR32_OPC_ST_D3,
28514 +  AVR32_OPC_ST_D5,
28515 +  AVR32_OPC_ST_D4,
28516 +  AVR32_OPC_ST_H1,
28517 +  AVR32_OPC_ST_H2,
28518 +  AVR32_OPC_ST_H5,
28519 +  AVR32_OPC_ST_H3,
28520 +  AVR32_OPC_ST_H4,
28521 +  AVR32_OPC_ST_W1,
28522 +  AVR32_OPC_ST_W2,
28523 +  AVR32_OPC_ST_W5,
28524 +  AVR32_OPC_ST_W3,
28525 +  AVR32_OPC_ST_W4,
28526 +  AVR32_OPC_STC_D1,
28527 +  AVR32_OPC_STC_D2,
28528 +  AVR32_OPC_STC_D3,
28529 +  AVR32_OPC_STC_W1,
28530 +  AVR32_OPC_STC_W2,
28531 +  AVR32_OPC_STC_W3,
28532 +  AVR32_OPC_STC0_D,
28533 +  AVR32_OPC_STC0_W,
28534 +  AVR32_OPC_STCM_D,
28535 +  AVR32_OPC_STCM_D_PU,
28536 +  AVR32_OPC_STCM_W,
28537 +  AVR32_OPC_STCM_W_PU,
28538 +  AVR32_OPC_STCOND,
28539 +  AVR32_OPC_STDSP,
28540 +  AVR32_OPC_STHH_W2,
28541 +  AVR32_OPC_STHH_W1,
28542 +  AVR32_OPC_STM,
28543 +  AVR32_OPC_STM_PU,
28544 +  AVR32_OPC_STMTS,
28545 +  AVR32_OPC_STMTS_PU,
28546 +  AVR32_OPC_STSWP_H,
28547 +  AVR32_OPC_STSWP_W,
28548 +  AVR32_OPC_SUB1,
28549 +  AVR32_OPC_SUB2,
28550 +  AVR32_OPC_SUB5,
28551 +  AVR32_OPC_SUB3_SP,
28552 +  AVR32_OPC_SUB3,
28553 +  AVR32_OPC_SUB4,
28554 +  AVR32_OPC_SUBEQ,
28555 +  AVR32_OPC_SUBNE,
28556 +  AVR32_OPC_SUBCC,
28557 +  AVR32_OPC_SUBCS,
28558 +  AVR32_OPC_SUBGE,
28559 +  AVR32_OPC_SUBLT,
28560 +  AVR32_OPC_SUBMI,
28561 +  AVR32_OPC_SUBPL,
28562 +  AVR32_OPC_SUBLS,
28563 +  AVR32_OPC_SUBGT,
28564 +  AVR32_OPC_SUBLE,
28565 +  AVR32_OPC_SUBHI,
28566 +  AVR32_OPC_SUBVS,
28567 +  AVR32_OPC_SUBVC,
28568 +  AVR32_OPC_SUBQS,
28569 +  AVR32_OPC_SUBAL,
28570 +  AVR32_OPC_SUBFEQ,
28571 +  AVR32_OPC_SUBFNE,
28572 +  AVR32_OPC_SUBFCC,
28573 +  AVR32_OPC_SUBFCS,
28574 +  AVR32_OPC_SUBFGE,
28575 +  AVR32_OPC_SUBFLT,
28576 +  AVR32_OPC_SUBFMI,
28577 +  AVR32_OPC_SUBFPL,
28578 +  AVR32_OPC_SUBFLS,
28579 +  AVR32_OPC_SUBFGT,
28580 +  AVR32_OPC_SUBFLE,
28581 +  AVR32_OPC_SUBFHI,
28582 +  AVR32_OPC_SUBFVS,
28583 +  AVR32_OPC_SUBFVC,
28584 +  AVR32_OPC_SUBFQS,
28585 +  AVR32_OPC_SUBFAL,
28586 +  AVR32_OPC_SUBHH_W,
28587 +  AVR32_OPC_SWAP_B,
28588 +  AVR32_OPC_SWAP_BH,
28589 +  AVR32_OPC_SWAP_H,
28590 +  AVR32_OPC_SYNC,
28591 +  AVR32_OPC_TLBR,
28592 +  AVR32_OPC_TLBS,
28593 +  AVR32_OPC_TLBW,
28594 +  AVR32_OPC_TNBZ,
28595 +  AVR32_OPC_TST,
28596 +  AVR32_OPC_XCHG,
28597 +  AVR32_OPC_MEMC,
28598 +  AVR32_OPC_MEMS,
28599 +  AVR32_OPC_MEMT,
28600 +  AVR32_OPC_BFEXTS,
28601 +  AVR32_OPC_BFEXTU,
28602 +  AVR32_OPC_BFINS,
28603 +  AVR32_OPC_RSUBEQ,
28604 +  AVR32_OPC_RSUBNE,
28605 +  AVR32_OPC_RSUBCC,
28606 +  AVR32_OPC_RSUBCS,
28607 +  AVR32_OPC_RSUBGE,
28608 +  AVR32_OPC_RSUBLT,
28609 +  AVR32_OPC_RSUBMI,
28610 +  AVR32_OPC_RSUBPL,
28611 +  AVR32_OPC_RSUBLS,
28612 +  AVR32_OPC_RSUBGT,
28613 +  AVR32_OPC_RSUBLE,
28614 +  AVR32_OPC_RSUBHI,
28615 +  AVR32_OPC_RSUBVS,
28616 +  AVR32_OPC_RSUBVC,
28617 +  AVR32_OPC_RSUBQS,
28618 +  AVR32_OPC_RSUBAL,
28619 +  AVR32_OPC_ADDEQ,
28620 +  AVR32_OPC_ADDNE,
28621 +  AVR32_OPC_ADDCC,
28622 +  AVR32_OPC_ADDCS,
28623 +  AVR32_OPC_ADDGE,
28624 +  AVR32_OPC_ADDLT,
28625 +  AVR32_OPC_ADDMI,
28626 +  AVR32_OPC_ADDPL,
28627 +  AVR32_OPC_ADDLS,
28628 +  AVR32_OPC_ADDGT,
28629 +  AVR32_OPC_ADDLE,
28630 +  AVR32_OPC_ADDHI,
28631 +  AVR32_OPC_ADDVS,
28632 +  AVR32_OPC_ADDVC,
28633 +  AVR32_OPC_ADDQS,
28634 +  AVR32_OPC_ADDAL,
28635 +  AVR32_OPC_SUB2EQ,
28636 +  AVR32_OPC_SUB2NE,
28637 +  AVR32_OPC_SUB2CC,
28638 +  AVR32_OPC_SUB2CS,
28639 +  AVR32_OPC_SUB2GE,
28640 +  AVR32_OPC_SUB2LT,
28641 +  AVR32_OPC_SUB2MI,
28642 +  AVR32_OPC_SUB2PL,
28643 +  AVR32_OPC_SUB2LS,
28644 +  AVR32_OPC_SUB2GT,
28645 +  AVR32_OPC_SUB2LE,
28646 +  AVR32_OPC_SUB2HI,
28647 +  AVR32_OPC_SUB2VS,
28648 +  AVR32_OPC_SUB2VC,
28649 +  AVR32_OPC_SUB2QS,
28650 +  AVR32_OPC_SUB2AL,
28651 +  AVR32_OPC_ANDEQ,
28652 +  AVR32_OPC_ANDNE,
28653 +  AVR32_OPC_ANDCC,
28654 +  AVR32_OPC_ANDCS,
28655 +  AVR32_OPC_ANDGE,
28656 +  AVR32_OPC_ANDLT,
28657 +  AVR32_OPC_ANDMI,
28658 +  AVR32_OPC_ANDPL,
28659 +  AVR32_OPC_ANDLS,
28660 +  AVR32_OPC_ANDGT,
28661 +  AVR32_OPC_ANDLE,
28662 +  AVR32_OPC_ANDHI,
28663 +  AVR32_OPC_ANDVS,
28664 +  AVR32_OPC_ANDVC,
28665 +  AVR32_OPC_ANDQS,
28666 +  AVR32_OPC_ANDAL,
28667 +  AVR32_OPC_OREQ,
28668 +  AVR32_OPC_ORNE,
28669 +  AVR32_OPC_ORCC,
28670 +  AVR32_OPC_ORCS,
28671 +  AVR32_OPC_ORGE,
28672 +  AVR32_OPC_ORLT,
28673 +  AVR32_OPC_ORMI,
28674 +  AVR32_OPC_ORPL,
28675 +  AVR32_OPC_ORLS,
28676 +  AVR32_OPC_ORGT,
28677 +  AVR32_OPC_ORLE,
28678 +  AVR32_OPC_ORHI,
28679 +  AVR32_OPC_ORVS,
28680 +  AVR32_OPC_ORVC,
28681 +  AVR32_OPC_ORQS,
28682 +  AVR32_OPC_ORAL,
28683 +  AVR32_OPC_EOREQ,
28684 +  AVR32_OPC_EORNE,
28685 +  AVR32_OPC_EORCC,
28686 +  AVR32_OPC_EORCS,
28687 +  AVR32_OPC_EORGE,
28688 +  AVR32_OPC_EORLT,
28689 +  AVR32_OPC_EORMI,
28690 +  AVR32_OPC_EORPL,
28691 +  AVR32_OPC_EORLS,
28692 +  AVR32_OPC_EORGT,
28693 +  AVR32_OPC_EORLE,
28694 +  AVR32_OPC_EORHI,
28695 +  AVR32_OPC_EORVS,
28696 +  AVR32_OPC_EORVC,
28697 +  AVR32_OPC_EORQS,
28698 +  AVR32_OPC_EORAL,
28699 +  AVR32_OPC_LD_WEQ,
28700 +  AVR32_OPC_LD_WNE,
28701 +  AVR32_OPC_LD_WCC,
28702 +  AVR32_OPC_LD_WCS,
28703 +  AVR32_OPC_LD_WGE,
28704 +  AVR32_OPC_LD_WLT,
28705 +  AVR32_OPC_LD_WMI,
28706 +  AVR32_OPC_LD_WPL,
28707 +  AVR32_OPC_LD_WLS,
28708 +  AVR32_OPC_LD_WGT,
28709 +  AVR32_OPC_LD_WLE,
28710 +  AVR32_OPC_LD_WHI,
28711 +  AVR32_OPC_LD_WVS,
28712 +  AVR32_OPC_LD_WVC,
28713 +  AVR32_OPC_LD_WQS,
28714 +  AVR32_OPC_LD_WAL,
28715 +  AVR32_OPC_LD_SHEQ,
28716 +  AVR32_OPC_LD_SHNE,
28717 +  AVR32_OPC_LD_SHCC,
28718 +  AVR32_OPC_LD_SHCS,
28719 +  AVR32_OPC_LD_SHGE,
28720 +  AVR32_OPC_LD_SHLT,
28721 +  AVR32_OPC_LD_SHMI,
28722 +  AVR32_OPC_LD_SHPL,
28723 +  AVR32_OPC_LD_SHLS,
28724 +  AVR32_OPC_LD_SHGT,
28725 +  AVR32_OPC_LD_SHLE,
28726 +  AVR32_OPC_LD_SHHI,
28727 +  AVR32_OPC_LD_SHVS,
28728 +  AVR32_OPC_LD_SHVC,
28729 +  AVR32_OPC_LD_SHQS,
28730 +  AVR32_OPC_LD_SHAL,
28731 +  AVR32_OPC_LD_UHEQ,
28732 +  AVR32_OPC_LD_UHNE,
28733 +  AVR32_OPC_LD_UHCC,
28734 +  AVR32_OPC_LD_UHCS,
28735 +  AVR32_OPC_LD_UHGE,
28736 +  AVR32_OPC_LD_UHLT,
28737 +  AVR32_OPC_LD_UHMI,
28738 +  AVR32_OPC_LD_UHPL,
28739 +  AVR32_OPC_LD_UHLS,
28740 +  AVR32_OPC_LD_UHGT,
28741 +  AVR32_OPC_LD_UHLE,
28742 +  AVR32_OPC_LD_UHHI,
28743 +  AVR32_OPC_LD_UHVS,
28744 +  AVR32_OPC_LD_UHVC,
28745 +  AVR32_OPC_LD_UHQS,
28746 +  AVR32_OPC_LD_UHAL,
28747 +  AVR32_OPC_LD_SBEQ,
28748 +  AVR32_OPC_LD_SBNE,
28749 +  AVR32_OPC_LD_SBCC,
28750 +  AVR32_OPC_LD_SBCS,
28751 +  AVR32_OPC_LD_SBGE,
28752 +  AVR32_OPC_LD_SBLT,
28753 +  AVR32_OPC_LD_SBMI,
28754 +  AVR32_OPC_LD_SBPL,
28755 +  AVR32_OPC_LD_SBLS,
28756 +  AVR32_OPC_LD_SBGT,
28757 +  AVR32_OPC_LD_SBLE,
28758 +  AVR32_OPC_LD_SBHI,
28759 +  AVR32_OPC_LD_SBVS,
28760 +  AVR32_OPC_LD_SBVC,
28761 +  AVR32_OPC_LD_SBQS,
28762 +  AVR32_OPC_LD_SBAL,
28763 +  AVR32_OPC_LD_UBEQ,
28764 +  AVR32_OPC_LD_UBNE,
28765 +  AVR32_OPC_LD_UBCC,
28766 +  AVR32_OPC_LD_UBCS,
28767 +  AVR32_OPC_LD_UBGE,
28768 +  AVR32_OPC_LD_UBLT,
28769 +  AVR32_OPC_LD_UBMI,
28770 +  AVR32_OPC_LD_UBPL,
28771 +  AVR32_OPC_LD_UBLS,
28772 +  AVR32_OPC_LD_UBGT,
28773 +  AVR32_OPC_LD_UBLE,
28774 +  AVR32_OPC_LD_UBHI,
28775 +  AVR32_OPC_LD_UBVS,
28776 +  AVR32_OPC_LD_UBVC,
28777 +  AVR32_OPC_LD_UBQS,
28778 +  AVR32_OPC_LD_UBAL,
28779 +  AVR32_OPC_ST_WEQ,
28780 +  AVR32_OPC_ST_WNE,
28781 +  AVR32_OPC_ST_WCC,
28782 +  AVR32_OPC_ST_WCS,
28783 +  AVR32_OPC_ST_WGE,
28784 +  AVR32_OPC_ST_WLT,
28785 +  AVR32_OPC_ST_WMI,
28786 +  AVR32_OPC_ST_WPL,
28787 +  AVR32_OPC_ST_WLS,
28788 +  AVR32_OPC_ST_WGT,
28789 +  AVR32_OPC_ST_WLE,
28790 +  AVR32_OPC_ST_WHI,
28791 +  AVR32_OPC_ST_WVS,
28792 +  AVR32_OPC_ST_WVC,
28793 +  AVR32_OPC_ST_WQS,
28794 +  AVR32_OPC_ST_WAL,
28795 +  AVR32_OPC_ST_HEQ,
28796 +  AVR32_OPC_ST_HNE,
28797 +  AVR32_OPC_ST_HCC,
28798 +  AVR32_OPC_ST_HCS,
28799 +  AVR32_OPC_ST_HGE,
28800 +  AVR32_OPC_ST_HLT,
28801 +  AVR32_OPC_ST_HMI,
28802 +  AVR32_OPC_ST_HPL,
28803 +  AVR32_OPC_ST_HLS,
28804 +  AVR32_OPC_ST_HGT,
28805 +  AVR32_OPC_ST_HLE,
28806 +  AVR32_OPC_ST_HHI,
28807 +  AVR32_OPC_ST_HVS,
28808 +  AVR32_OPC_ST_HVC,
28809 +  AVR32_OPC_ST_HQS,
28810 +  AVR32_OPC_ST_HAL,
28811 +  AVR32_OPC_ST_BEQ,
28812 +  AVR32_OPC_ST_BNE,
28813 +  AVR32_OPC_ST_BCC,
28814 +  AVR32_OPC_ST_BCS,
28815 +  AVR32_OPC_ST_BGE,
28816 +  AVR32_OPC_ST_BLT,
28817 +  AVR32_OPC_ST_BMI,
28818 +  AVR32_OPC_ST_BPL,
28819 +  AVR32_OPC_ST_BLS,
28820 +  AVR32_OPC_ST_BGT,
28821 +  AVR32_OPC_ST_BLE,
28822 +  AVR32_OPC_ST_BHI,
28823 +  AVR32_OPC_ST_BVS,
28824 +  AVR32_OPC_ST_BVC,
28825 +  AVR32_OPC_ST_BQS,
28826 +  AVR32_OPC_ST_BAL,
28827 +  AVR32_OPC_MOVH,
28828 +  AVR32_OPC_SSCALL,
28829 +  AVR32_OPC_RETSS,
28830 +  AVR32_OPC_FMAC_S,
28831 +  AVR32_OPC_FNMAC_S,
28832 +  AVR32_OPC_FMSC_S,
28833 +  AVR32_OPC_FNMSC_S,
28834 +  AVR32_OPC_FMUL_S,
28835 +  AVR32_OPC_FNMUL_S,
28836 +  AVR32_OPC_FADD_S,
28837 +  AVR32_OPC_FSUB_S,
28838 +  AVR32_OPC_FCASTRS_SW,
28839 +  AVR32_OPC_FCASTRS_UW,
28840 +  AVR32_OPC_FCASTSW_S,
28841 +  AVR32_OPC_FCASTUW_S,
28842 +  AVR32_OPC_FCMP_S,
28843 +  AVR32_OPC_FCHK_S,
28844 +  AVR32_OPC_FRCPA_S,
28845 +  AVR32_OPC_FRSQRTA_S,
28846 +  AVR32_OPC__END_
28847 +};
28848 +#define AVR32_NR_OPCODES AVR32_OPC__END_
28849 +
28850 +enum avr32_syntax_type
28851 +{
28852 +  AVR32_SYNTAX_ABS,
28853 +  AVR32_SYNTAX_ACALL,
28854 +  AVR32_SYNTAX_ACR,
28855 +  AVR32_SYNTAX_ADC,
28856 +  AVR32_SYNTAX_ADD1,
28857 +  AVR32_SYNTAX_ADD2,
28858 +  AVR32_SYNTAX_ADDABS,
28859 +  AVR32_SYNTAX_ADDHH_W,
28860 +  AVR32_SYNTAX_AND1,
28861 +  AVR32_SYNTAX_AND2,
28862 +  AVR32_SYNTAX_AND3,
28863 +  AVR32_SYNTAX_ANDH,
28864 +  AVR32_SYNTAX_ANDH_COH,
28865 +  AVR32_SYNTAX_ANDL,
28866 +  AVR32_SYNTAX_ANDL_COH,
28867 +  AVR32_SYNTAX_ANDN,
28868 +  AVR32_SYNTAX_ASR1,
28869 +  AVR32_SYNTAX_ASR3,
28870 +  AVR32_SYNTAX_ASR2,
28871 +  AVR32_SYNTAX_BFEXTS,
28872 +  AVR32_SYNTAX_BFEXTU,
28873 +  AVR32_SYNTAX_BFINS,
28874 +  AVR32_SYNTAX_BLD,
28875 +  AVR32_SYNTAX_BREQ1,
28876 +  AVR32_SYNTAX_BRNE1,
28877 +  AVR32_SYNTAX_BRCC1,
28878 +  AVR32_SYNTAX_BRCS1,
28879 +  AVR32_SYNTAX_BRGE1,
28880 +  AVR32_SYNTAX_BRLT1,
28881 +  AVR32_SYNTAX_BRMI1,
28882 +  AVR32_SYNTAX_BRPL1,
28883 +  AVR32_SYNTAX_BRHS1,
28884 +  AVR32_SYNTAX_BRLO1,
28885 +  AVR32_SYNTAX_BREQ2,
28886 +  AVR32_SYNTAX_BRNE2,
28887 +  AVR32_SYNTAX_BRCC2,
28888 +  AVR32_SYNTAX_BRCS2,
28889 +  AVR32_SYNTAX_BRGE2,
28890 +  AVR32_SYNTAX_BRLT2,
28891 +  AVR32_SYNTAX_BRMI2,
28892 +  AVR32_SYNTAX_BRPL2,
28893 +  AVR32_SYNTAX_BRLS,
28894 +  AVR32_SYNTAX_BRGT,
28895 +  AVR32_SYNTAX_BRLE,
28896 +  AVR32_SYNTAX_BRHI,
28897 +  AVR32_SYNTAX_BRVS,
28898 +  AVR32_SYNTAX_BRVC,
28899 +  AVR32_SYNTAX_BRQS,
28900 +  AVR32_SYNTAX_BRAL,
28901 +  AVR32_SYNTAX_BRHS2,
28902 +  AVR32_SYNTAX_BRLO2,
28903 +  AVR32_SYNTAX_BREAKPOINT,
28904 +  AVR32_SYNTAX_BREV,
28905 +  AVR32_SYNTAX_BST,
28906 +  AVR32_SYNTAX_CACHE,
28907 +  AVR32_SYNTAX_CASTS_B,
28908 +  AVR32_SYNTAX_CASTS_H,
28909 +  AVR32_SYNTAX_CASTU_B,
28910 +  AVR32_SYNTAX_CASTU_H,
28911 +  AVR32_SYNTAX_CBR,
28912 +  AVR32_SYNTAX_CLZ,
28913 +  AVR32_SYNTAX_COM,
28914 +  AVR32_SYNTAX_COP,
28915 +  AVR32_SYNTAX_CP_B,
28916 +  AVR32_SYNTAX_CP_H,
28917 +  AVR32_SYNTAX_CP_W1,
28918 +  AVR32_SYNTAX_CP_W2,
28919 +  AVR32_SYNTAX_CP_W3,
28920 +  AVR32_SYNTAX_CPC1,
28921 +  AVR32_SYNTAX_CPC2,
28922 +  AVR32_SYNTAX_CSRF,
28923 +  AVR32_SYNTAX_CSRFCZ,
28924 +  AVR32_SYNTAX_DIVS,
28925 +  AVR32_SYNTAX_DIVU,
28926 +  AVR32_SYNTAX_EOR1,
28927 +  AVR32_SYNTAX_EOR2,
28928 +  AVR32_SYNTAX_EOR3,
28929 +  AVR32_SYNTAX_EORL,
28930 +  AVR32_SYNTAX_EORH,
28931 +  AVR32_SYNTAX_FRS,
28932 +  AVR32_SYNTAX_SSCALL,
28933 +  AVR32_SYNTAX_RETSS,
28934 +  AVR32_SYNTAX_ICALL,
28935 +  AVR32_SYNTAX_INCJOSP,
28936 +  AVR32_SYNTAX_LD_D1,
28937 +  AVR32_SYNTAX_LD_D2,
28938 +  AVR32_SYNTAX_LD_D3,
28939 +  AVR32_SYNTAX_LD_D5,
28940 +  AVR32_SYNTAX_LD_D4,
28941 +  AVR32_SYNTAX_LD_SB2,
28942 +  AVR32_SYNTAX_LD_SB1,
28943 +  AVR32_SYNTAX_LD_UB1,
28944 +  AVR32_SYNTAX_LD_UB2,
28945 +  AVR32_SYNTAX_LD_UB5,
28946 +  AVR32_SYNTAX_LD_UB3,
28947 +  AVR32_SYNTAX_LD_UB4,
28948 +  AVR32_SYNTAX_LD_SH1,
28949 +  AVR32_SYNTAX_LD_SH2,
28950 +  AVR32_SYNTAX_LD_SH5,
28951 +  AVR32_SYNTAX_LD_SH3,
28952 +  AVR32_SYNTAX_LD_SH4,
28953 +  AVR32_SYNTAX_LD_UH1,
28954 +  AVR32_SYNTAX_LD_UH2,
28955 +  AVR32_SYNTAX_LD_UH5,
28956 +  AVR32_SYNTAX_LD_UH3,
28957 +  AVR32_SYNTAX_LD_UH4,
28958 +  AVR32_SYNTAX_LD_W1,
28959 +  AVR32_SYNTAX_LD_W2,
28960 +  AVR32_SYNTAX_LD_W5,
28961 +  AVR32_SYNTAX_LD_W6,
28962 +  AVR32_SYNTAX_LD_W3,
28963 +  AVR32_SYNTAX_LD_W4,
28964 +  AVR32_SYNTAX_LDC_D1,
28965 +  AVR32_SYNTAX_LDC_D2,
28966 +  AVR32_SYNTAX_LDC_D3,
28967 +  AVR32_SYNTAX_LDC_W1,
28968 +  AVR32_SYNTAX_LDC_W2,
28969 +  AVR32_SYNTAX_LDC_W3,
28970 +  AVR32_SYNTAX_LDC0_D,
28971 +  AVR32_SYNTAX_LDC0_W,
28972 +  AVR32_SYNTAX_LDCM_D,
28973 +  AVR32_SYNTAX_LDCM_D_PU,
28974 +  AVR32_SYNTAX_LDCM_W,
28975 +  AVR32_SYNTAX_LDCM_W_PU,
28976 +  AVR32_SYNTAX_LDDPC,
28977 +  AVR32_SYNTAX_LDDPC_EXT,
28978 +  AVR32_SYNTAX_LDDSP,
28979 +  AVR32_SYNTAX_LDINS_B,
28980 +  AVR32_SYNTAX_LDINS_H,
28981 +  AVR32_SYNTAX_LDM,
28982 +  AVR32_SYNTAX_LDMTS,
28983 +  AVR32_SYNTAX_LDMTS_PU,
28984 +  AVR32_SYNTAX_LDSWP_SH,
28985 +  AVR32_SYNTAX_LDSWP_UH,
28986 +  AVR32_SYNTAX_LDSWP_W,
28987 +  AVR32_SYNTAX_LSL1,
28988 +  AVR32_SYNTAX_LSL3,
28989 +  AVR32_SYNTAX_LSL2,
28990 +  AVR32_SYNTAX_LSR1,
28991 +  AVR32_SYNTAX_LSR3,
28992 +  AVR32_SYNTAX_LSR2,
28993 +  AVR32_SYNTAX_MAC,
28994 +  AVR32_SYNTAX_MACHH_D,
28995 +  AVR32_SYNTAX_MACHH_W,
28996 +  AVR32_SYNTAX_MACS_D,
28997 +  AVR32_SYNTAX_MACSATHH_W,
28998 +  AVR32_SYNTAX_MACUD,
28999 +  AVR32_SYNTAX_MACWH_D,
29000 +  AVR32_SYNTAX_MAX,
29001 +  AVR32_SYNTAX_MCALL,
29002 +  AVR32_SYNTAX_MFDR,
29003 +  AVR32_SYNTAX_MFSR,
29004 +  AVR32_SYNTAX_MIN,
29005 +  AVR32_SYNTAX_MOV3,
29006 +  AVR32_SYNTAX_MOV1,
29007 +  AVR32_SYNTAX_MOV2,
29008 +  AVR32_SYNTAX_MOVEQ1,
29009 +  AVR32_SYNTAX_MOVNE1,
29010 +  AVR32_SYNTAX_MOVCC1,
29011 +  AVR32_SYNTAX_MOVCS1,
29012 +  AVR32_SYNTAX_MOVGE1,
29013 +  AVR32_SYNTAX_MOVLT1,
29014 +  AVR32_SYNTAX_MOVMI1,
29015 +  AVR32_SYNTAX_MOVPL1,
29016 +  AVR32_SYNTAX_MOVLS1,
29017 +  AVR32_SYNTAX_MOVGT1,
29018 +  AVR32_SYNTAX_MOVLE1,
29019 +  AVR32_SYNTAX_MOVHI1,
29020 +  AVR32_SYNTAX_MOVVS1,
29021 +  AVR32_SYNTAX_MOVVC1,
29022 +  AVR32_SYNTAX_MOVQS1,
29023 +  AVR32_SYNTAX_MOVAL1,
29024 +  AVR32_SYNTAX_MOVHS1,
29025 +  AVR32_SYNTAX_MOVLO1,
29026 +  AVR32_SYNTAX_MOVEQ2,
29027 +  AVR32_SYNTAX_MOVNE2,
29028 +  AVR32_SYNTAX_MOVCC2,
29029 +  AVR32_SYNTAX_MOVCS2,
29030 +  AVR32_SYNTAX_MOVGE2,
29031 +  AVR32_SYNTAX_MOVLT2,
29032 +  AVR32_SYNTAX_MOVMI2,
29033 +  AVR32_SYNTAX_MOVPL2,
29034 +  AVR32_SYNTAX_MOVLS2,
29035 +  AVR32_SYNTAX_MOVGT2,
29036 +  AVR32_SYNTAX_MOVLE2,
29037 +  AVR32_SYNTAX_MOVHI2,
29038 +  AVR32_SYNTAX_MOVVS2,
29039 +  AVR32_SYNTAX_MOVVC2,
29040 +  AVR32_SYNTAX_MOVQS2,
29041 +  AVR32_SYNTAX_MOVAL2,
29042 +  AVR32_SYNTAX_MOVHS2,
29043 +  AVR32_SYNTAX_MOVLO2,
29044 +  AVR32_SYNTAX_MTDR,
29045 +  AVR32_SYNTAX_MTSR,
29046 +  AVR32_SYNTAX_MUL1,
29047 +  AVR32_SYNTAX_MUL2,
29048 +  AVR32_SYNTAX_MUL3,
29049 +  AVR32_SYNTAX_MULHH_W,
29050 +  AVR32_SYNTAX_MULNHH_W,
29051 +  AVR32_SYNTAX_MULNWH_D,
29052 +  AVR32_SYNTAX_MULSD,
29053 +  AVR32_SYNTAX_MULSATHH_H,
29054 +  AVR32_SYNTAX_MULSATHH_W,
29055 +  AVR32_SYNTAX_MULSATRNDHH_H,
29056 +  AVR32_SYNTAX_MULSATRNDWH_W,
29057 +  AVR32_SYNTAX_MULSATWH_W,
29058 +  AVR32_SYNTAX_MULU_D,
29059 +  AVR32_SYNTAX_MULWH_D,
29060 +  AVR32_SYNTAX_MUSFR,
29061 +  AVR32_SYNTAX_MUSTR,
29062 +  AVR32_SYNTAX_MVCR_D,
29063 +  AVR32_SYNTAX_MVCR_W,
29064 +  AVR32_SYNTAX_MVRC_D,
29065 +  AVR32_SYNTAX_MVRC_W,
29066 +  AVR32_SYNTAX_NEG,
29067 +  AVR32_SYNTAX_NOP,
29068 +  AVR32_SYNTAX_OR1,
29069 +  AVR32_SYNTAX_OR2,
29070 +  AVR32_SYNTAX_OR3,
29071 +  AVR32_SYNTAX_ORH,
29072 +  AVR32_SYNTAX_ORL,
29073 +  AVR32_SYNTAX_PABS_SB,
29074 +  AVR32_SYNTAX_PABS_SH,
29075 +  AVR32_SYNTAX_PACKSH_SB,
29076 +  AVR32_SYNTAX_PACKSH_UB,
29077 +  AVR32_SYNTAX_PACKW_SH,
29078 +  AVR32_SYNTAX_PADD_B,
29079 +  AVR32_SYNTAX_PADD_H,
29080 +  AVR32_SYNTAX_PADDH_SH,
29081 +  AVR32_SYNTAX_PADDH_UB,
29082 +  AVR32_SYNTAX_PADDS_SB,
29083 +  AVR32_SYNTAX_PADDS_SH,
29084 +  AVR32_SYNTAX_PADDS_UB,
29085 +  AVR32_SYNTAX_PADDS_UH,
29086 +  AVR32_SYNTAX_PADDSUB_H,
29087 +  AVR32_SYNTAX_PADDSUBH_SH,
29088 +  AVR32_SYNTAX_PADDSUBS_SH,
29089 +  AVR32_SYNTAX_PADDSUBS_UH,
29090 +  AVR32_SYNTAX_PADDX_H,
29091 +  AVR32_SYNTAX_PADDXH_SH,
29092 +  AVR32_SYNTAX_PADDXS_SH,
29093 +  AVR32_SYNTAX_PADDXS_UH,
29094 +  AVR32_SYNTAX_PASR_B,
29095 +  AVR32_SYNTAX_PASR_H,
29096 +  AVR32_SYNTAX_PAVG_SH,
29097 +  AVR32_SYNTAX_PAVG_UB,
29098 +  AVR32_SYNTAX_PLSL_B,
29099 +  AVR32_SYNTAX_PLSL_H,
29100 +  AVR32_SYNTAX_PLSR_B,
29101 +  AVR32_SYNTAX_PLSR_H,
29102 +  AVR32_SYNTAX_PMAX_SH,
29103 +  AVR32_SYNTAX_PMAX_UB,
29104 +  AVR32_SYNTAX_PMIN_SH,
29105 +  AVR32_SYNTAX_PMIN_UB,
29106 +  AVR32_SYNTAX_POPJC,
29107 +  AVR32_SYNTAX_POPM,
29108 +  AVR32_SYNTAX_POPM_E,
29109 +  AVR32_SYNTAX_PREF,
29110 +  AVR32_SYNTAX_PSAD,
29111 +  AVR32_SYNTAX_PSUB_B,
29112 +  AVR32_SYNTAX_PSUB_H,
29113 +  AVR32_SYNTAX_PSUBADD_H,
29114 +  AVR32_SYNTAX_PSUBADDH_SH,
29115 +  AVR32_SYNTAX_PSUBADDS_SH,
29116 +  AVR32_SYNTAX_PSUBADDS_UH,
29117 +  AVR32_SYNTAX_PSUBH_SH,
29118 +  AVR32_SYNTAX_PSUBH_UB,
29119 +  AVR32_SYNTAX_PSUBS_SB,
29120 +  AVR32_SYNTAX_PSUBS_SH,
29121 +  AVR32_SYNTAX_PSUBS_UB,
29122 +  AVR32_SYNTAX_PSUBS_UH,
29123 +  AVR32_SYNTAX_PSUBX_H,
29124 +  AVR32_SYNTAX_PSUBXH_SH,
29125 +  AVR32_SYNTAX_PSUBXS_SH,
29126 +  AVR32_SYNTAX_PSUBXS_UH,
29127 +  AVR32_SYNTAX_PUNPCKSB_H,
29128 +  AVR32_SYNTAX_PUNPCKUB_H,
29129 +  AVR32_SYNTAX_PUSHJC,
29130 +  AVR32_SYNTAX_PUSHM,
29131 +  AVR32_SYNTAX_PUSHM_E,
29132 +  AVR32_SYNTAX_RCALL1,
29133 +  AVR32_SYNTAX_RCALL2,
29134 +  AVR32_SYNTAX_RETEQ,
29135 +  AVR32_SYNTAX_RETNE,
29136 +  AVR32_SYNTAX_RETCC,
29137 +  AVR32_SYNTAX_RETCS,
29138 +  AVR32_SYNTAX_RETGE,
29139 +  AVR32_SYNTAX_RETLT,
29140 +  AVR32_SYNTAX_RETMI,
29141 +  AVR32_SYNTAX_RETPL,
29142 +  AVR32_SYNTAX_RETLS,
29143 +  AVR32_SYNTAX_RETGT,
29144 +  AVR32_SYNTAX_RETLE,
29145 +  AVR32_SYNTAX_RETHI,
29146 +  AVR32_SYNTAX_RETVS,
29147 +  AVR32_SYNTAX_RETVC,
29148 +  AVR32_SYNTAX_RETQS,
29149 +  AVR32_SYNTAX_RETAL,
29150 +  AVR32_SYNTAX_RETHS,
29151 +  AVR32_SYNTAX_RETLO,
29152 +  AVR32_SYNTAX_RETD,
29153 +  AVR32_SYNTAX_RETE,
29154 +  AVR32_SYNTAX_RETJ,
29155 +  AVR32_SYNTAX_RETS,
29156 +  AVR32_SYNTAX_RJMP,
29157 +  AVR32_SYNTAX_ROL,
29158 +  AVR32_SYNTAX_ROR,
29159 +  AVR32_SYNTAX_RSUB1,
29160 +  AVR32_SYNTAX_RSUB2,
29161 +  AVR32_SYNTAX_SATADD_H,
29162 +  AVR32_SYNTAX_SATADD_W,
29163 +  AVR32_SYNTAX_SATRNDS,
29164 +  AVR32_SYNTAX_SATRNDU,
29165 +  AVR32_SYNTAX_SATS,
29166 +  AVR32_SYNTAX_SATSUB_H,
29167 +  AVR32_SYNTAX_SATSUB_W1,
29168 +  AVR32_SYNTAX_SATSUB_W2,
29169 +  AVR32_SYNTAX_SATU,
29170 +  AVR32_SYNTAX_SBC,
29171 +  AVR32_SYNTAX_SBR,
29172 +  AVR32_SYNTAX_SCALL,
29173 +  AVR32_SYNTAX_SCR,
29174 +  AVR32_SYNTAX_SLEEP,
29175 +  AVR32_SYNTAX_SREQ,
29176 +  AVR32_SYNTAX_SRNE,
29177 +  AVR32_SYNTAX_SRCC,
29178 +  AVR32_SYNTAX_SRCS,
29179 +  AVR32_SYNTAX_SRGE,
29180 +  AVR32_SYNTAX_SRLT,
29181 +  AVR32_SYNTAX_SRMI,
29182 +  AVR32_SYNTAX_SRPL,
29183 +  AVR32_SYNTAX_SRLS,
29184 +  AVR32_SYNTAX_SRGT,
29185 +  AVR32_SYNTAX_SRLE,
29186 +  AVR32_SYNTAX_SRHI,
29187 +  AVR32_SYNTAX_SRVS,
29188 +  AVR32_SYNTAX_SRVC,
29189 +  AVR32_SYNTAX_SRQS,
29190 +  AVR32_SYNTAX_SRAL,
29191 +  AVR32_SYNTAX_SRHS,
29192 +  AVR32_SYNTAX_SRLO,
29193 +  AVR32_SYNTAX_SSRF,
29194 +  AVR32_SYNTAX_ST_B1,
29195 +  AVR32_SYNTAX_ST_B2,
29196 +  AVR32_SYNTAX_ST_B5,
29197 +  AVR32_SYNTAX_ST_B3,
29198 +  AVR32_SYNTAX_ST_B4,
29199 +  AVR32_SYNTAX_ST_D1,
29200 +  AVR32_SYNTAX_ST_D2,
29201 +  AVR32_SYNTAX_ST_D3,
29202 +  AVR32_SYNTAX_ST_D5,
29203 +  AVR32_SYNTAX_ST_D4,
29204 +  AVR32_SYNTAX_ST_H1,
29205 +  AVR32_SYNTAX_ST_H2,
29206 +  AVR32_SYNTAX_ST_H5,
29207 +  AVR32_SYNTAX_ST_H3,
29208 +  AVR32_SYNTAX_ST_H4,
29209 +  AVR32_SYNTAX_ST_W1,
29210 +  AVR32_SYNTAX_ST_W2,
29211 +  AVR32_SYNTAX_ST_W5,
29212 +  AVR32_SYNTAX_ST_W3,
29213 +  AVR32_SYNTAX_ST_W4,
29214 +  AVR32_SYNTAX_STC_D1,
29215 +  AVR32_SYNTAX_STC_D2,
29216 +  AVR32_SYNTAX_STC_D3,
29217 +  AVR32_SYNTAX_STC_W1,
29218 +  AVR32_SYNTAX_STC_W2,
29219 +  AVR32_SYNTAX_STC_W3,
29220 +  AVR32_SYNTAX_STC0_D,
29221 +  AVR32_SYNTAX_STC0_W,
29222 +  AVR32_SYNTAX_STCM_D,
29223 +  AVR32_SYNTAX_STCM_D_PU,
29224 +  AVR32_SYNTAX_STCM_W,
29225 +  AVR32_SYNTAX_STCM_W_PU,
29226 +  AVR32_SYNTAX_STCOND,
29227 +  AVR32_SYNTAX_STDSP,
29228 +  AVR32_SYNTAX_STHH_W2,
29229 +  AVR32_SYNTAX_STHH_W1,
29230 +  AVR32_SYNTAX_STM,
29231 +  AVR32_SYNTAX_STM_PU,
29232 +  AVR32_SYNTAX_STMTS,
29233 +  AVR32_SYNTAX_STMTS_PU,
29234 +  AVR32_SYNTAX_STSWP_H,
29235 +  AVR32_SYNTAX_STSWP_W,
29236 +  AVR32_SYNTAX_SUB1,
29237 +  AVR32_SYNTAX_SUB2,
29238 +  AVR32_SYNTAX_SUB5,
29239 +  AVR32_SYNTAX_SUB3_SP,
29240 +  AVR32_SYNTAX_SUB3,
29241 +  AVR32_SYNTAX_SUB4,
29242 +  AVR32_SYNTAX_SUBEQ,
29243 +  AVR32_SYNTAX_SUBNE,
29244 +  AVR32_SYNTAX_SUBCC,
29245 +  AVR32_SYNTAX_SUBCS,
29246 +  AVR32_SYNTAX_SUBGE,
29247 +  AVR32_SYNTAX_SUBLT,
29248 +  AVR32_SYNTAX_SUBMI,
29249 +  AVR32_SYNTAX_SUBPL,
29250 +  AVR32_SYNTAX_SUBLS,
29251 +  AVR32_SYNTAX_SUBGT,
29252 +  AVR32_SYNTAX_SUBLE,
29253 +  AVR32_SYNTAX_SUBHI,
29254 +  AVR32_SYNTAX_SUBVS,
29255 +  AVR32_SYNTAX_SUBVC,
29256 +  AVR32_SYNTAX_SUBQS,
29257 +  AVR32_SYNTAX_SUBAL,
29258 +  AVR32_SYNTAX_SUBHS,
29259 +  AVR32_SYNTAX_SUBLO,
29260 +  AVR32_SYNTAX_SUBFEQ,
29261 +  AVR32_SYNTAX_SUBFNE,
29262 +  AVR32_SYNTAX_SUBFCC,
29263 +  AVR32_SYNTAX_SUBFCS,
29264 +  AVR32_SYNTAX_SUBFGE,
29265 +  AVR32_SYNTAX_SUBFLT,
29266 +  AVR32_SYNTAX_SUBFMI,
29267 +  AVR32_SYNTAX_SUBFPL,
29268 +  AVR32_SYNTAX_SUBFLS,
29269 +  AVR32_SYNTAX_SUBFGT,
29270 +  AVR32_SYNTAX_SUBFLE,
29271 +  AVR32_SYNTAX_SUBFHI,
29272 +  AVR32_SYNTAX_SUBFVS,
29273 +  AVR32_SYNTAX_SUBFVC,
29274 +  AVR32_SYNTAX_SUBFQS,
29275 +  AVR32_SYNTAX_SUBFAL,
29276 +  AVR32_SYNTAX_SUBFHS,
29277 +  AVR32_SYNTAX_SUBFLO,
29278 +  AVR32_SYNTAX_SUBHH_W,
29279 +  AVR32_SYNTAX_SWAP_B,
29280 +  AVR32_SYNTAX_SWAP_BH,
29281 +  AVR32_SYNTAX_SWAP_H,
29282 +  AVR32_SYNTAX_SYNC,
29283 +  AVR32_SYNTAX_TLBR,
29284 +  AVR32_SYNTAX_TLBS,
29285 +  AVR32_SYNTAX_TLBW,
29286 +  AVR32_SYNTAX_TNBZ,
29287 +  AVR32_SYNTAX_TST,
29288 +  AVR32_SYNTAX_XCHG,
29289 +  AVR32_SYNTAX_MEMC,
29290 +  AVR32_SYNTAX_MEMS,
29291 +  AVR32_SYNTAX_MEMT,
29292 +  AVR32_SYNTAX_FMAC_S,
29293 +  AVR32_SYNTAX_FNMAC_S,
29294 +  AVR32_SYNTAX_FMSC_S,
29295 +  AVR32_SYNTAX_FNMSC_S,
29296 +  AVR32_SYNTAX_FMUL_S,
29297 +  AVR32_SYNTAX_FNMUL_S,
29298 +  AVR32_SYNTAX_FADD_S,
29299 +  AVR32_SYNTAX_FSUB_S,
29300 +  AVR32_SYNTAX_FCASTRS_SW,
29301 +  AVR32_SYNTAX_FCASTRS_UW,
29302 +  AVR32_SYNTAX_FCASTSW_S,
29303 +  AVR32_SYNTAX_FCASTUW_S,
29304 +  AVR32_SYNTAX_FCMP_S,
29305 +  AVR32_SYNTAX_FCHK_S,
29306 +  AVR32_SYNTAX_FRCPA_S,
29307 +  AVR32_SYNTAX_FRSQRTA_S,
29308 +  AVR32_SYNTAX_LDA_W,
29309 +  AVR32_SYNTAX_CALL,
29310 +  AVR32_SYNTAX_PICOSVMAC0,
29311 +  AVR32_SYNTAX_PICOSVMAC1,
29312 +  AVR32_SYNTAX_PICOSVMAC2,
29313 +  AVR32_SYNTAX_PICOSVMAC3,
29314 +  AVR32_SYNTAX_PICOSVMUL0,
29315 +  AVR32_SYNTAX_PICOSVMUL1,
29316 +  AVR32_SYNTAX_PICOSVMUL2,
29317 +  AVR32_SYNTAX_PICOSVMUL3,
29318 +  AVR32_SYNTAX_PICOVMAC0,
29319 +  AVR32_SYNTAX_PICOVMAC1,
29320 +  AVR32_SYNTAX_PICOVMAC2,
29321 +  AVR32_SYNTAX_PICOVMAC3,
29322 +  AVR32_SYNTAX_PICOVMUL0,
29323 +  AVR32_SYNTAX_PICOVMUL1,
29324 +  AVR32_SYNTAX_PICOVMUL2,
29325 +  AVR32_SYNTAX_PICOVMUL3,
29326 +  AVR32_SYNTAX_PICOLD_D2,
29327 +  AVR32_SYNTAX_PICOLD_D3,
29328 +  AVR32_SYNTAX_PICOLD_D1,
29329 +  AVR32_SYNTAX_PICOLD_W2,
29330 +  AVR32_SYNTAX_PICOLD_W3,
29331 +  AVR32_SYNTAX_PICOLD_W1,
29332 +  AVR32_SYNTAX_PICOLDM_D,
29333 +  AVR32_SYNTAX_PICOLDM_D_PU,
29334 +  AVR32_SYNTAX_PICOLDM_W,
29335 +  AVR32_SYNTAX_PICOLDM_W_PU,
29336 +  AVR32_SYNTAX_PICOMV_D1,
29337 +  AVR32_SYNTAX_PICOMV_D2,
29338 +  AVR32_SYNTAX_PICOMV_W1,
29339 +  AVR32_SYNTAX_PICOMV_W2,
29340 +  AVR32_SYNTAX_PICOST_D2,
29341 +  AVR32_SYNTAX_PICOST_D3,
29342 +  AVR32_SYNTAX_PICOST_D1,
29343 +  AVR32_SYNTAX_PICOST_W2,
29344 +  AVR32_SYNTAX_PICOST_W3,
29345 +  AVR32_SYNTAX_PICOST_W1,
29346 +  AVR32_SYNTAX_PICOSTM_D,
29347 +  AVR32_SYNTAX_PICOSTM_D_PU,
29348 +  AVR32_SYNTAX_PICOSTM_W,
29349 +  AVR32_SYNTAX_PICOSTM_W_PU,
29350 +  AVR32_SYNTAX_RSUBEQ,
29351 +  AVR32_SYNTAX_RSUBNE,
29352 +  AVR32_SYNTAX_RSUBCC,
29353 +  AVR32_SYNTAX_RSUBCS,
29354 +  AVR32_SYNTAX_RSUBGE,
29355 +  AVR32_SYNTAX_RSUBLT,
29356 +  AVR32_SYNTAX_RSUBMI,
29357 +  AVR32_SYNTAX_RSUBPL,
29358 +  AVR32_SYNTAX_RSUBLS,
29359 +  AVR32_SYNTAX_RSUBGT,
29360 +  AVR32_SYNTAX_RSUBLE,
29361 +  AVR32_SYNTAX_RSUBHI,
29362 +  AVR32_SYNTAX_RSUBVS,
29363 +  AVR32_SYNTAX_RSUBVC,
29364 +  AVR32_SYNTAX_RSUBQS,
29365 +  AVR32_SYNTAX_RSUBAL,
29366 +  AVR32_SYNTAX_RSUBHS,
29367 +  AVR32_SYNTAX_RSUBLO,
29368 +  AVR32_SYNTAX_ADDEQ,
29369 +  AVR32_SYNTAX_ADDNE,
29370 +  AVR32_SYNTAX_ADDCC,
29371 +  AVR32_SYNTAX_ADDCS,
29372 +  AVR32_SYNTAX_ADDGE,
29373 +  AVR32_SYNTAX_ADDLT,
29374 +  AVR32_SYNTAX_ADDMI,
29375 +  AVR32_SYNTAX_ADDPL,
29376 +  AVR32_SYNTAX_ADDLS,
29377 +  AVR32_SYNTAX_ADDGT,
29378 +  AVR32_SYNTAX_ADDLE,
29379 +  AVR32_SYNTAX_ADDHI,
29380 +  AVR32_SYNTAX_ADDVS,
29381 +  AVR32_SYNTAX_ADDVC,
29382 +  AVR32_SYNTAX_ADDQS,
29383 +  AVR32_SYNTAX_ADDAL,
29384 +  AVR32_SYNTAX_ADDHS,
29385 +  AVR32_SYNTAX_ADDLO,
29386 +  AVR32_SYNTAX_SUB2EQ,
29387 +  AVR32_SYNTAX_SUB2NE,
29388 +  AVR32_SYNTAX_SUB2CC,
29389 +  AVR32_SYNTAX_SUB2CS,
29390 +  AVR32_SYNTAX_SUB2GE,
29391 +  AVR32_SYNTAX_SUB2LT,
29392 +  AVR32_SYNTAX_SUB2MI,
29393 +  AVR32_SYNTAX_SUB2PL,
29394 +  AVR32_SYNTAX_SUB2LS,
29395 +  AVR32_SYNTAX_SUB2GT,
29396 +  AVR32_SYNTAX_SUB2LE,
29397 +  AVR32_SYNTAX_SUB2HI,
29398 +  AVR32_SYNTAX_SUB2VS,
29399 +  AVR32_SYNTAX_SUB2VC,
29400 +  AVR32_SYNTAX_SUB2QS,
29401 +  AVR32_SYNTAX_SUB2AL,
29402 +  AVR32_SYNTAX_SUB2HS,
29403 +  AVR32_SYNTAX_SUB2LO,
29404 +  AVR32_SYNTAX_ANDEQ,
29405 +  AVR32_SYNTAX_ANDNE,
29406 +  AVR32_SYNTAX_ANDCC,
29407 +  AVR32_SYNTAX_ANDCS,
29408 +  AVR32_SYNTAX_ANDGE,
29409 +  AVR32_SYNTAX_ANDLT,
29410 +  AVR32_SYNTAX_ANDMI,
29411 +  AVR32_SYNTAX_ANDPL,
29412 +  AVR32_SYNTAX_ANDLS,
29413 +  AVR32_SYNTAX_ANDGT,
29414 +  AVR32_SYNTAX_ANDLE,
29415 +  AVR32_SYNTAX_ANDHI,
29416 +  AVR32_SYNTAX_ANDVS,
29417 +  AVR32_SYNTAX_ANDVC,
29418 +  AVR32_SYNTAX_ANDQS,
29419 +  AVR32_SYNTAX_ANDAL,
29420 +  AVR32_SYNTAX_ANDHS,
29421 +  AVR32_SYNTAX_ANDLO,
29422 +  AVR32_SYNTAX_OREQ,
29423 +  AVR32_SYNTAX_ORNE,
29424 +  AVR32_SYNTAX_ORCC,
29425 +  AVR32_SYNTAX_ORCS,
29426 +  AVR32_SYNTAX_ORGE,
29427 +  AVR32_SYNTAX_ORLT,
29428 +  AVR32_SYNTAX_ORMI,
29429 +  AVR32_SYNTAX_ORPL,
29430 +  AVR32_SYNTAX_ORLS,
29431 +  AVR32_SYNTAX_ORGT,
29432 +  AVR32_SYNTAX_ORLE,
29433 +  AVR32_SYNTAX_ORHI,
29434 +  AVR32_SYNTAX_ORVS,
29435 +  AVR32_SYNTAX_ORVC,
29436 +  AVR32_SYNTAX_ORQS,
29437 +  AVR32_SYNTAX_ORAL,
29438 +  AVR32_SYNTAX_ORHS,
29439 +  AVR32_SYNTAX_ORLO,
29440 +  AVR32_SYNTAX_EOREQ,
29441 +  AVR32_SYNTAX_EORNE,
29442 +  AVR32_SYNTAX_EORCC,
29443 +  AVR32_SYNTAX_EORCS,
29444 +  AVR32_SYNTAX_EORGE,
29445 +  AVR32_SYNTAX_EORLT,
29446 +  AVR32_SYNTAX_EORMI,
29447 +  AVR32_SYNTAX_EORPL,
29448 +  AVR32_SYNTAX_EORLS,
29449 +  AVR32_SYNTAX_EORGT,
29450 +  AVR32_SYNTAX_EORLE,
29451 +  AVR32_SYNTAX_EORHI,
29452 +  AVR32_SYNTAX_EORVS,
29453 +  AVR32_SYNTAX_EORVC,
29454 +  AVR32_SYNTAX_EORQS,
29455 +  AVR32_SYNTAX_EORAL,
29456 +  AVR32_SYNTAX_EORHS,
29457 +  AVR32_SYNTAX_EORLO,
29458 +  AVR32_SYNTAX_LD_WEQ,
29459 +  AVR32_SYNTAX_LD_WNE,
29460 +  AVR32_SYNTAX_LD_WCC,
29461 +  AVR32_SYNTAX_LD_WCS,
29462 +  AVR32_SYNTAX_LD_WGE,
29463 +  AVR32_SYNTAX_LD_WLT,
29464 +  AVR32_SYNTAX_LD_WMI,
29465 +  AVR32_SYNTAX_LD_WPL,
29466 +  AVR32_SYNTAX_LD_WLS,
29467 +  AVR32_SYNTAX_LD_WGT,
29468 +  AVR32_SYNTAX_LD_WLE,
29469 +  AVR32_SYNTAX_LD_WHI,
29470 +  AVR32_SYNTAX_LD_WVS,
29471 +  AVR32_SYNTAX_LD_WVC,
29472 +  AVR32_SYNTAX_LD_WQS,
29473 +  AVR32_SYNTAX_LD_WAL,
29474 +  AVR32_SYNTAX_LD_WHS,
29475 +  AVR32_SYNTAX_LD_WLO,
29476 +  AVR32_SYNTAX_LD_SHEQ,
29477 +  AVR32_SYNTAX_LD_SHNE,
29478 +  AVR32_SYNTAX_LD_SHCC,
29479 +  AVR32_SYNTAX_LD_SHCS,
29480 +  AVR32_SYNTAX_LD_SHGE,
29481 +  AVR32_SYNTAX_LD_SHLT,
29482 +  AVR32_SYNTAX_LD_SHMI,
29483 +  AVR32_SYNTAX_LD_SHPL,
29484 +  AVR32_SYNTAX_LD_SHLS,
29485 +  AVR32_SYNTAX_LD_SHGT,
29486 +  AVR32_SYNTAX_LD_SHLE,
29487 +  AVR32_SYNTAX_LD_SHHI,
29488 +  AVR32_SYNTAX_LD_SHVS,
29489 +  AVR32_SYNTAX_LD_SHVC,
29490 +  AVR32_SYNTAX_LD_SHQS,
29491 +  AVR32_SYNTAX_LD_SHAL,
29492 +  AVR32_SYNTAX_LD_SHHS,
29493 +  AVR32_SYNTAX_LD_SHLO,
29494 +  AVR32_SYNTAX_LD_UHEQ,
29495 +  AVR32_SYNTAX_LD_UHNE,
29496 +  AVR32_SYNTAX_LD_UHCC,
29497 +  AVR32_SYNTAX_LD_UHCS,
29498 +  AVR32_SYNTAX_LD_UHGE,
29499 +  AVR32_SYNTAX_LD_UHLT,
29500 +  AVR32_SYNTAX_LD_UHMI,
29501 +  AVR32_SYNTAX_LD_UHPL,
29502 +  AVR32_SYNTAX_LD_UHLS,
29503 +  AVR32_SYNTAX_LD_UHGT,
29504 +  AVR32_SYNTAX_LD_UHLE,
29505 +  AVR32_SYNTAX_LD_UHHI,
29506 +  AVR32_SYNTAX_LD_UHVS,
29507 +  AVR32_SYNTAX_LD_UHVC,
29508 +  AVR32_SYNTAX_LD_UHQS,
29509 +  AVR32_SYNTAX_LD_UHAL,
29510 +  AVR32_SYNTAX_LD_UHHS,
29511 +  AVR32_SYNTAX_LD_UHLO,
29512 +  AVR32_SYNTAX_LD_SBEQ,
29513 +  AVR32_SYNTAX_LD_SBNE,
29514 +  AVR32_SYNTAX_LD_SBCC,
29515 +  AVR32_SYNTAX_LD_SBCS,
29516 +  AVR32_SYNTAX_LD_SBGE,
29517 +  AVR32_SYNTAX_LD_SBLT,
29518 +  AVR32_SYNTAX_LD_SBMI,
29519 +  AVR32_SYNTAX_LD_SBPL,
29520 +  AVR32_SYNTAX_LD_SBLS,
29521 +  AVR32_SYNTAX_LD_SBGT,
29522 +  AVR32_SYNTAX_LD_SBLE,
29523 +  AVR32_SYNTAX_LD_SBHI,
29524 +  AVR32_SYNTAX_LD_SBVS,
29525 +  AVR32_SYNTAX_LD_SBVC,
29526 +  AVR32_SYNTAX_LD_SBQS,
29527 +  AVR32_SYNTAX_LD_SBAL,
29528 +  AVR32_SYNTAX_LD_SBHS,
29529 +  AVR32_SYNTAX_LD_SBLO,
29530 +  AVR32_SYNTAX_LD_UBEQ,
29531 +  AVR32_SYNTAX_LD_UBNE,
29532 +  AVR32_SYNTAX_LD_UBCC,
29533 +  AVR32_SYNTAX_LD_UBCS,
29534 +  AVR32_SYNTAX_LD_UBGE,
29535 +  AVR32_SYNTAX_LD_UBLT,
29536 +  AVR32_SYNTAX_LD_UBMI,
29537 +  AVR32_SYNTAX_LD_UBPL,
29538 +  AVR32_SYNTAX_LD_UBLS,
29539 +  AVR32_SYNTAX_LD_UBGT,
29540 +  AVR32_SYNTAX_LD_UBLE,
29541 +  AVR32_SYNTAX_LD_UBHI,
29542 +  AVR32_SYNTAX_LD_UBVS,
29543 +  AVR32_SYNTAX_LD_UBVC,
29544 +  AVR32_SYNTAX_LD_UBQS,
29545 +  AVR32_SYNTAX_LD_UBAL,
29546 +  AVR32_SYNTAX_LD_UBHS,
29547 +  AVR32_SYNTAX_LD_UBLO,
29548 +  AVR32_SYNTAX_ST_WEQ,
29549 +  AVR32_SYNTAX_ST_WNE,
29550 +  AVR32_SYNTAX_ST_WCC,
29551 +  AVR32_SYNTAX_ST_WCS,
29552 +  AVR32_SYNTAX_ST_WGE,
29553 +  AVR32_SYNTAX_ST_WLT,
29554 +  AVR32_SYNTAX_ST_WMI,
29555 +  AVR32_SYNTAX_ST_WPL,
29556 +  AVR32_SYNTAX_ST_WLS,
29557 +  AVR32_SYNTAX_ST_WGT,
29558 +  AVR32_SYNTAX_ST_WLE,
29559 +  AVR32_SYNTAX_ST_WHI,
29560 +  AVR32_SYNTAX_ST_WVS,
29561 +  AVR32_SYNTAX_ST_WVC,
29562 +  AVR32_SYNTAX_ST_WQS,
29563 +  AVR32_SYNTAX_ST_WAL,
29564 +  AVR32_SYNTAX_ST_WHS,
29565 +  AVR32_SYNTAX_ST_WLO,
29566 +  AVR32_SYNTAX_ST_HEQ,
29567 +  AVR32_SYNTAX_ST_HNE,
29568 +  AVR32_SYNTAX_ST_HCC,
29569 +  AVR32_SYNTAX_ST_HCS,
29570 +  AVR32_SYNTAX_ST_HGE,
29571 +  AVR32_SYNTAX_ST_HLT,
29572 +  AVR32_SYNTAX_ST_HMI,
29573 +  AVR32_SYNTAX_ST_HPL,
29574 +  AVR32_SYNTAX_ST_HLS,
29575 +  AVR32_SYNTAX_ST_HGT,
29576 +  AVR32_SYNTAX_ST_HLE,
29577 +  AVR32_SYNTAX_ST_HHI,
29578 +  AVR32_SYNTAX_ST_HVS,
29579 +  AVR32_SYNTAX_ST_HVC,
29580 +  AVR32_SYNTAX_ST_HQS,
29581 +  AVR32_SYNTAX_ST_HAL,
29582 +  AVR32_SYNTAX_ST_HHS,
29583 +  AVR32_SYNTAX_ST_HLO,
29584 +  AVR32_SYNTAX_ST_BEQ,
29585 +  AVR32_SYNTAX_ST_BNE,
29586 +  AVR32_SYNTAX_ST_BCC,
29587 +  AVR32_SYNTAX_ST_BCS,
29588 +  AVR32_SYNTAX_ST_BGE,
29589 +  AVR32_SYNTAX_ST_BLT,
29590 +  AVR32_SYNTAX_ST_BMI,
29591 +  AVR32_SYNTAX_ST_BPL,
29592 +  AVR32_SYNTAX_ST_BLS,
29593 +  AVR32_SYNTAX_ST_BGT,
29594 +  AVR32_SYNTAX_ST_BLE,
29595 +  AVR32_SYNTAX_ST_BHI,
29596 +  AVR32_SYNTAX_ST_BVS,
29597 +  AVR32_SYNTAX_ST_BVC,
29598 +  AVR32_SYNTAX_ST_BQS,
29599 +  AVR32_SYNTAX_ST_BAL,
29600 +  AVR32_SYNTAX_ST_BHS,
29601 +  AVR32_SYNTAX_ST_BLO,
29602 +  AVR32_SYNTAX_MOVH,
29603 +  AVR32_SYNTAX__END_
29604 +};
29605 +#define AVR32_NR_SYNTAX AVR32_SYNTAX__END_
29606 +
29607 +enum avr32_alias_type
29608 +  {
29609 +    AVR32_ALIAS_PICOSVMAC0,
29610 +    AVR32_ALIAS_PICOSVMAC1,
29611 +    AVR32_ALIAS_PICOSVMAC2,
29612 +    AVR32_ALIAS_PICOSVMAC3,
29613 +    AVR32_ALIAS_PICOSVMUL0,
29614 +    AVR32_ALIAS_PICOSVMUL1,
29615 +    AVR32_ALIAS_PICOSVMUL2,
29616 +    AVR32_ALIAS_PICOSVMUL3,
29617 +    AVR32_ALIAS_PICOVMAC0,
29618 +    AVR32_ALIAS_PICOVMAC1,
29619 +    AVR32_ALIAS_PICOVMAC2,
29620 +    AVR32_ALIAS_PICOVMAC3,
29621 +    AVR32_ALIAS_PICOVMUL0,
29622 +    AVR32_ALIAS_PICOVMUL1,
29623 +    AVR32_ALIAS_PICOVMUL2,
29624 +    AVR32_ALIAS_PICOVMUL3,
29625 +    AVR32_ALIAS_PICOLD_D1,
29626 +    AVR32_ALIAS_PICOLD_D2,
29627 +    AVR32_ALIAS_PICOLD_D3,
29628 +    AVR32_ALIAS_PICOLD_W1,
29629 +    AVR32_ALIAS_PICOLD_W2,
29630 +    AVR32_ALIAS_PICOLD_W3,
29631 +    AVR32_ALIAS_PICOLDM_D,
29632 +    AVR32_ALIAS_PICOLDM_D_PU,
29633 +    AVR32_ALIAS_PICOLDM_W,
29634 +    AVR32_ALIAS_PICOLDM_W_PU,
29635 +    AVR32_ALIAS_PICOMV_D1,
29636 +    AVR32_ALIAS_PICOMV_D2,
29637 +    AVR32_ALIAS_PICOMV_W1,
29638 +    AVR32_ALIAS_PICOMV_W2,
29639 +    AVR32_ALIAS_PICOST_D1,
29640 +    AVR32_ALIAS_PICOST_D2,
29641 +    AVR32_ALIAS_PICOST_D3,
29642 +    AVR32_ALIAS_PICOST_W1,
29643 +    AVR32_ALIAS_PICOST_W2,
29644 +    AVR32_ALIAS_PICOST_W3,
29645 +    AVR32_ALIAS_PICOSTM_D,
29646 +    AVR32_ALIAS_PICOSTM_D_PU,
29647 +    AVR32_ALIAS_PICOSTM_W,
29648 +    AVR32_ALIAS_PICOSTM_W_PU,
29649 +    AVR32_ALIAS__END_
29650 +  };
29651 +#define AVR32_NR_ALIAS AVR32_ALIAS__END_
29652 +
29653 +enum avr32_mnemonic_type
29654 +{
29655 +  AVR32_MNEMONIC_ABS,
29656 +  AVR32_MNEMONIC_ACALL,
29657 +  AVR32_MNEMONIC_ACR,
29658 +  AVR32_MNEMONIC_ADC,
29659 +  AVR32_MNEMONIC_ADD,
29660 +  AVR32_MNEMONIC_ADDABS,
29661 +  AVR32_MNEMONIC_ADDHH_W,
29662 +  AVR32_MNEMONIC_AND,
29663 +  AVR32_MNEMONIC_ANDH,
29664 +  AVR32_MNEMONIC_ANDL,
29665 +  AVR32_MNEMONIC_ANDN,
29666 +  AVR32_MNEMONIC_ASR,
29667 +  AVR32_MNEMONIC_BFEXTS,
29668 +  AVR32_MNEMONIC_BFEXTU,
29669 +  AVR32_MNEMONIC_BFINS,
29670 +  AVR32_MNEMONIC_BLD,
29671 +  AVR32_MNEMONIC_BREQ,
29672 +  AVR32_MNEMONIC_BRNE,
29673 +  AVR32_MNEMONIC_BRCC,
29674 +  AVR32_MNEMONIC_BRCS,
29675 +  AVR32_MNEMONIC_BRGE,
29676 +  AVR32_MNEMONIC_BRLT,
29677 +  AVR32_MNEMONIC_BRMI,
29678 +  AVR32_MNEMONIC_BRPL,
29679 +  AVR32_MNEMONIC_BRHS,
29680 +  AVR32_MNEMONIC_BRLO,
29681 +  AVR32_MNEMONIC_BRLS,
29682 +  AVR32_MNEMONIC_BRGT,
29683 +  AVR32_MNEMONIC_BRLE,
29684 +  AVR32_MNEMONIC_BRHI,
29685 +  AVR32_MNEMONIC_BRVS,
29686 +  AVR32_MNEMONIC_BRVC,
29687 +  AVR32_MNEMONIC_BRQS,
29688 +  AVR32_MNEMONIC_BRAL,
29689 +  AVR32_MNEMONIC_BREAKPOINT,
29690 +  AVR32_MNEMONIC_BREV,
29691 +  AVR32_MNEMONIC_BST,
29692 +  AVR32_MNEMONIC_CACHE,
29693 +  AVR32_MNEMONIC_CASTS_B,
29694 +  AVR32_MNEMONIC_CASTS_H,
29695 +  AVR32_MNEMONIC_CASTU_B,
29696 +  AVR32_MNEMONIC_CASTU_H,
29697 +  AVR32_MNEMONIC_CBR,
29698 +  AVR32_MNEMONIC_CLZ,
29699 +  AVR32_MNEMONIC_COM,
29700 +  AVR32_MNEMONIC_COP,
29701 +  AVR32_MNEMONIC_CP_B,
29702 +  AVR32_MNEMONIC_CP_H,
29703 +  AVR32_MNEMONIC_CP_W,
29704 +  AVR32_MNEMONIC_CP,
29705 +  AVR32_MNEMONIC_CPC,
29706 +  AVR32_MNEMONIC_CSRF,
29707 +  AVR32_MNEMONIC_CSRFCZ,
29708 +  AVR32_MNEMONIC_DIVS,
29709 +  AVR32_MNEMONIC_DIVU,
29710 +  AVR32_MNEMONIC_EOR,
29711 +  AVR32_MNEMONIC_EORL,
29712 +  AVR32_MNEMONIC_EORH,
29713 +  AVR32_MNEMONIC_FRS,
29714 +  AVR32_MNEMONIC_SSCALL,
29715 +  AVR32_MNEMONIC_RETSS,
29716 +  AVR32_MNEMONIC_ICALL,
29717 +  AVR32_MNEMONIC_INCJOSP,
29718 +  AVR32_MNEMONIC_LD_D,
29719 +  AVR32_MNEMONIC_LD_SB,
29720 +  AVR32_MNEMONIC_LD_UB,
29721 +  AVR32_MNEMONIC_LD_SH,
29722 +  AVR32_MNEMONIC_LD_UH,
29723 +  AVR32_MNEMONIC_LD_W,
29724 +  AVR32_MNEMONIC_LDC_D,
29725 +  AVR32_MNEMONIC_LDC_W,
29726 +  AVR32_MNEMONIC_LDC0_D,
29727 +  AVR32_MNEMONIC_LDC0_W,
29728 +  AVR32_MNEMONIC_LDCM_D,
29729 +  AVR32_MNEMONIC_LDCM_W,
29730 +  AVR32_MNEMONIC_LDDPC,
29731 +  AVR32_MNEMONIC_LDDSP,
29732 +  AVR32_MNEMONIC_LDINS_B,
29733 +  AVR32_MNEMONIC_LDINS_H,
29734 +  AVR32_MNEMONIC_LDM,
29735 +  AVR32_MNEMONIC_LDMTS,
29736 +  AVR32_MNEMONIC_LDSWP_SH,
29737 +  AVR32_MNEMONIC_LDSWP_UH,
29738 +  AVR32_MNEMONIC_LDSWP_W,
29739 +  AVR32_MNEMONIC_LSL,
29740 +  AVR32_MNEMONIC_LSR,
29741 +  AVR32_MNEMONIC_MAC,
29742 +  AVR32_MNEMONIC_MACHH_D,
29743 +  AVR32_MNEMONIC_MACHH_W,
29744 +  AVR32_MNEMONIC_MACS_D,
29745 +  AVR32_MNEMONIC_MACSATHH_W,
29746 +  AVR32_MNEMONIC_MACU_D,
29747 +  AVR32_MNEMONIC_MACWH_D,
29748 +  AVR32_MNEMONIC_MAX,
29749 +  AVR32_MNEMONIC_MCALL,
29750 +  AVR32_MNEMONIC_MFDR,
29751 +  AVR32_MNEMONIC_MFSR,
29752 +  AVR32_MNEMONIC_MIN,
29753 +  AVR32_MNEMONIC_MOV,
29754 +  AVR32_MNEMONIC_MOVEQ,
29755 +  AVR32_MNEMONIC_MOVNE,
29756 +  AVR32_MNEMONIC_MOVCC,
29757 +  AVR32_MNEMONIC_MOVCS,
29758 +  AVR32_MNEMONIC_MOVGE,
29759 +  AVR32_MNEMONIC_MOVLT,
29760 +  AVR32_MNEMONIC_MOVMI,
29761 +  AVR32_MNEMONIC_MOVPL,
29762 +  AVR32_MNEMONIC_MOVLS,
29763 +  AVR32_MNEMONIC_MOVGT,
29764 +  AVR32_MNEMONIC_MOVLE,
29765 +  AVR32_MNEMONIC_MOVHI,
29766 +  AVR32_MNEMONIC_MOVVS,
29767 +  AVR32_MNEMONIC_MOVVC,
29768 +  AVR32_MNEMONIC_MOVQS,
29769 +  AVR32_MNEMONIC_MOVAL,
29770 +  AVR32_MNEMONIC_MOVHS,
29771 +  AVR32_MNEMONIC_MOVLO,
29772 +  AVR32_MNEMONIC_MTDR,
29773 +  AVR32_MNEMONIC_MTSR,
29774 +  AVR32_MNEMONIC_MUL,
29775 +  AVR32_MNEMONIC_MULHH_W,
29776 +  AVR32_MNEMONIC_MULNHH_W,
29777 +  AVR32_MNEMONIC_MULNWH_D,
29778 +  AVR32_MNEMONIC_MULS_D,
29779 +  AVR32_MNEMONIC_MULSATHH_H,
29780 +  AVR32_MNEMONIC_MULSATHH_W,
29781 +  AVR32_MNEMONIC_MULSATRNDHH_H,
29782 +  AVR32_MNEMONIC_MULSATRNDWH_W,
29783 +  AVR32_MNEMONIC_MULSATWH_W,
29784 +  AVR32_MNEMONIC_MULU_D,
29785 +  AVR32_MNEMONIC_MULWH_D,
29786 +  AVR32_MNEMONIC_MUSFR,
29787 +  AVR32_MNEMONIC_MUSTR,
29788 +  AVR32_MNEMONIC_MVCR_D,
29789 +  AVR32_MNEMONIC_MVCR_W,
29790 +  AVR32_MNEMONIC_MVRC_D,
29791 +  AVR32_MNEMONIC_MVRC_W,
29792 +  AVR32_MNEMONIC_NEG,
29793 +  AVR32_MNEMONIC_NOP,
29794 +  AVR32_MNEMONIC_OR,
29795 +  AVR32_MNEMONIC_ORH,
29796 +  AVR32_MNEMONIC_ORL,
29797 +  AVR32_MNEMONIC_PABS_SB,
29798 +  AVR32_MNEMONIC_PABS_SH,
29799 +  AVR32_MNEMONIC_PACKSH_SB,
29800 +  AVR32_MNEMONIC_PACKSH_UB,
29801 +  AVR32_MNEMONIC_PACKW_SH,
29802 +  AVR32_MNEMONIC_PADD_B,
29803 +  AVR32_MNEMONIC_PADD_H,
29804 +  AVR32_MNEMONIC_PADDH_SH,
29805 +  AVR32_MNEMONIC_PADDH_UB,
29806 +  AVR32_MNEMONIC_PADDS_SB,
29807 +  AVR32_MNEMONIC_PADDS_SH,
29808 +  AVR32_MNEMONIC_PADDS_UB,
29809 +  AVR32_MNEMONIC_PADDS_UH,
29810 +  AVR32_MNEMONIC_PADDSUB_H,
29811 +  AVR32_MNEMONIC_PADDSUBH_SH,
29812 +  AVR32_MNEMONIC_PADDSUBS_SH,
29813 +  AVR32_MNEMONIC_PADDSUBS_UH,
29814 +  AVR32_MNEMONIC_PADDX_H,
29815 +  AVR32_MNEMONIC_PADDXH_SH,
29816 +  AVR32_MNEMONIC_PADDXS_SH,
29817 +  AVR32_MNEMONIC_PADDXS_UH,
29818 +  AVR32_MNEMONIC_PASR_B,
29819 +  AVR32_MNEMONIC_PASR_H,
29820 +  AVR32_MNEMONIC_PAVG_SH,
29821 +  AVR32_MNEMONIC_PAVG_UB,
29822 +  AVR32_MNEMONIC_PLSL_B,
29823 +  AVR32_MNEMONIC_PLSL_H,
29824 +  AVR32_MNEMONIC_PLSR_B,
29825 +  AVR32_MNEMONIC_PLSR_H,
29826 +  AVR32_MNEMONIC_PMAX_SH,
29827 +  AVR32_MNEMONIC_PMAX_UB,
29828 +  AVR32_MNEMONIC_PMIN_SH,
29829 +  AVR32_MNEMONIC_PMIN_UB,
29830 +  AVR32_MNEMONIC_POPJC,
29831 +  AVR32_MNEMONIC_POPM,
29832 +  AVR32_MNEMONIC_PREF,
29833 +  AVR32_MNEMONIC_PSAD,
29834 +  AVR32_MNEMONIC_PSUB_B,
29835 +  AVR32_MNEMONIC_PSUB_H,
29836 +  AVR32_MNEMONIC_PSUBADD_H,
29837 +  AVR32_MNEMONIC_PSUBADDH_SH,
29838 +  AVR32_MNEMONIC_PSUBADDS_SH,
29839 +  AVR32_MNEMONIC_PSUBADDS_UH,
29840 +  AVR32_MNEMONIC_PSUBH_SH,
29841 +  AVR32_MNEMONIC_PSUBH_UB,
29842 +  AVR32_MNEMONIC_PSUBS_SB,
29843 +  AVR32_MNEMONIC_PSUBS_SH,
29844 +  AVR32_MNEMONIC_PSUBS_UB,
29845 +  AVR32_MNEMONIC_PSUBS_UH,
29846 +  AVR32_MNEMONIC_PSUBX_H,
29847 +  AVR32_MNEMONIC_PSUBXH_SH,
29848 +  AVR32_MNEMONIC_PSUBXS_SH,
29849 +  AVR32_MNEMONIC_PSUBXS_UH,
29850 +  AVR32_MNEMONIC_PUNPCKSB_H,
29851 +  AVR32_MNEMONIC_PUNPCKUB_H,
29852 +  AVR32_MNEMONIC_PUSHJC,
29853 +  AVR32_MNEMONIC_PUSHM,
29854 +  AVR32_MNEMONIC_RCALL,
29855 +  AVR32_MNEMONIC_RETEQ,
29856 +  AVR32_MNEMONIC_RETNE,
29857 +  AVR32_MNEMONIC_RETCC,
29858 +  AVR32_MNEMONIC_RETCS,
29859 +  AVR32_MNEMONIC_RETGE,
29860 +  AVR32_MNEMONIC_RETLT,
29861 +  AVR32_MNEMONIC_RETMI,
29862 +  AVR32_MNEMONIC_RETPL,
29863 +  AVR32_MNEMONIC_RETLS,
29864 +  AVR32_MNEMONIC_RETGT,
29865 +  AVR32_MNEMONIC_RETLE,
29866 +  AVR32_MNEMONIC_RETHI,
29867 +  AVR32_MNEMONIC_RETVS,
29868 +  AVR32_MNEMONIC_RETVC,
29869 +  AVR32_MNEMONIC_RETQS,
29870 +  AVR32_MNEMONIC_RETAL,
29871 +  AVR32_MNEMONIC_RETHS,
29872 +  AVR32_MNEMONIC_RETLO,
29873 +  AVR32_MNEMONIC_RET,
29874 +  AVR32_MNEMONIC_RETD,
29875 +  AVR32_MNEMONIC_RETE,
29876 +  AVR32_MNEMONIC_RETJ,
29877 +  AVR32_MNEMONIC_RETS,
29878 +  AVR32_MNEMONIC_RJMP,
29879 +  AVR32_MNEMONIC_ROL,
29880 +  AVR32_MNEMONIC_ROR,
29881 +  AVR32_MNEMONIC_RSUB,
29882 +  AVR32_MNEMONIC_SATADD_H,
29883 +  AVR32_MNEMONIC_SATADD_W,
29884 +  AVR32_MNEMONIC_SATRNDS,
29885 +  AVR32_MNEMONIC_SATRNDU,
29886 +  AVR32_MNEMONIC_SATS,
29887 +  AVR32_MNEMONIC_SATSUB_H,
29888 +  AVR32_MNEMONIC_SATSUB_W,
29889 +  AVR32_MNEMONIC_SATU,
29890 +  AVR32_MNEMONIC_SBC,
29891 +  AVR32_MNEMONIC_SBR,
29892 +  AVR32_MNEMONIC_SCALL,
29893 +  AVR32_MNEMONIC_SCR,
29894 +  AVR32_MNEMONIC_SLEEP,
29895 +  AVR32_MNEMONIC_SREQ,
29896 +  AVR32_MNEMONIC_SRNE,
29897 +  AVR32_MNEMONIC_SRCC,
29898 +  AVR32_MNEMONIC_SRCS,
29899 +  AVR32_MNEMONIC_SRGE,
29900 +  AVR32_MNEMONIC_SRLT,
29901 +  AVR32_MNEMONIC_SRMI,
29902 +  AVR32_MNEMONIC_SRPL,
29903 +  AVR32_MNEMONIC_SRLS,
29904 +  AVR32_MNEMONIC_SRGT,
29905 +  AVR32_MNEMONIC_SRLE,
29906 +  AVR32_MNEMONIC_SRHI,
29907 +  AVR32_MNEMONIC_SRVS,
29908 +  AVR32_MNEMONIC_SRVC,
29909 +  AVR32_MNEMONIC_SRQS,
29910 +  AVR32_MNEMONIC_SRAL,
29911 +  AVR32_MNEMONIC_SRHS,
29912 +  AVR32_MNEMONIC_SRLO,
29913 +  AVR32_MNEMONIC_SSRF,
29914 +  AVR32_MNEMONIC_ST_B,
29915 +  AVR32_MNEMONIC_ST_D,
29916 +  AVR32_MNEMONIC_ST_H,
29917 +  AVR32_MNEMONIC_ST_W,
29918 +  AVR32_MNEMONIC_STC_D,
29919 +  AVR32_MNEMONIC_STC_W,
29920 +  AVR32_MNEMONIC_STC0_D,
29921 +  AVR32_MNEMONIC_STC0_W,
29922 +  AVR32_MNEMONIC_STCM_D,
29923 +  AVR32_MNEMONIC_STCM_W,
29924 +  AVR32_MNEMONIC_STCOND,
29925 +  AVR32_MNEMONIC_STDSP,
29926 +  AVR32_MNEMONIC_STHH_W,
29927 +  AVR32_MNEMONIC_STM,
29928 +  AVR32_MNEMONIC_STMTS,
29929 +  AVR32_MNEMONIC_STSWP_H,
29930 +  AVR32_MNEMONIC_STSWP_W,
29931 +  AVR32_MNEMONIC_SUB,
29932 +  AVR32_MNEMONIC_SUBEQ,
29933 +  AVR32_MNEMONIC_SUBNE,
29934 +  AVR32_MNEMONIC_SUBCC,
29935 +  AVR32_MNEMONIC_SUBCS,
29936 +  AVR32_MNEMONIC_SUBGE,
29937 +  AVR32_MNEMONIC_SUBLT,
29938 +  AVR32_MNEMONIC_SUBMI,
29939 +  AVR32_MNEMONIC_SUBPL,
29940 +  AVR32_MNEMONIC_SUBLS,
29941 +  AVR32_MNEMONIC_SUBGT,
29942 +  AVR32_MNEMONIC_SUBLE,
29943 +  AVR32_MNEMONIC_SUBHI,
29944 +  AVR32_MNEMONIC_SUBVS,
29945 +  AVR32_MNEMONIC_SUBVC,
29946 +  AVR32_MNEMONIC_SUBQS,
29947 +  AVR32_MNEMONIC_SUBAL,
29948 +  AVR32_MNEMONIC_SUBHS,
29949 +  AVR32_MNEMONIC_SUBLO,
29950 +  AVR32_MNEMONIC_SUBFEQ,
29951 +  AVR32_MNEMONIC_SUBFNE,
29952 +  AVR32_MNEMONIC_SUBFCC,
29953 +  AVR32_MNEMONIC_SUBFCS,
29954 +  AVR32_MNEMONIC_SUBFGE,
29955 +  AVR32_MNEMONIC_SUBFLT,
29956 +  AVR32_MNEMONIC_SUBFMI,
29957 +  AVR32_MNEMONIC_SUBFPL,
29958 +  AVR32_MNEMONIC_SUBFLS,
29959 +  AVR32_MNEMONIC_SUBFGT,
29960 +  AVR32_MNEMONIC_SUBFLE,
29961 +  AVR32_MNEMONIC_SUBFHI,
29962 +  AVR32_MNEMONIC_SUBFVS,
29963 +  AVR32_MNEMONIC_SUBFVC,
29964 +  AVR32_MNEMONIC_SUBFQS,
29965 +  AVR32_MNEMONIC_SUBFAL,
29966 +  AVR32_MNEMONIC_SUBFHS,
29967 +  AVR32_MNEMONIC_SUBFLO,
29968 +  AVR32_MNEMONIC_SUBHH_W,
29969 +  AVR32_MNEMONIC_SWAP_B,
29970 +  AVR32_MNEMONIC_SWAP_BH,
29971 +  AVR32_MNEMONIC_SWAP_H,
29972 +  AVR32_MNEMONIC_SYNC,
29973 +  AVR32_MNEMONIC_TLBR,
29974 +  AVR32_MNEMONIC_TLBS,
29975 +  AVR32_MNEMONIC_TLBW,
29976 +  AVR32_MNEMONIC_TNBZ,
29977 +  AVR32_MNEMONIC_TST,
29978 +  AVR32_MNEMONIC_XCHG,
29979 +  AVR32_MNEMONIC_MEMC,
29980 +  AVR32_MNEMONIC_MEMS,
29981 +  AVR32_MNEMONIC_MEMT,
29982 +  AVR32_MNEMONIC_FMAC_S,
29983 +  AVR32_MNEMONIC_FNMAC_S,
29984 +  AVR32_MNEMONIC_FMSC_S,
29985 +  AVR32_MNEMONIC_FNMSC_S,
29986 +  AVR32_MNEMONIC_FMUL_S,
29987 +  AVR32_MNEMONIC_FNMUL_S,
29988 +  AVR32_MNEMONIC_FADD_S,
29989 +  AVR32_MNEMONIC_FSUB_S,
29990 +  AVR32_MNEMONIC_FCASTRS_SW,
29991 +  AVR32_MNEMONIC_FCASTRS_UW,
29992 +  AVR32_MNEMONIC_FCASTSW_S,
29993 +  AVR32_MNEMONIC_FCASTUW_S,
29994 +  AVR32_MNEMONIC_FCMP_S,
29995 +  AVR32_MNEMONIC_FCHK_S,
29996 +  AVR32_MNEMONIC_FRCPA_S,
29997 +  AVR32_MNEMONIC_FRSQRTA_S,
29998 +  /* AVR32_MNEMONIC_FLD_S,
29999 +     AVR32_MNEMONIC_FLD_D,
30000 +     AVR32_MNEMONIC_FST_S,
30001 +     AVR32_MNEMONIC_FST_D, */
30002 +  AVR32_MNEMONIC_LDA_W,
30003 +  AVR32_MNEMONIC_CALL,
30004 +  AVR32_MNEMONIC_PICOSVMAC,
30005 +  AVR32_MNEMONIC_PICOSVMUL,
30006 +  AVR32_MNEMONIC_PICOVMAC,
30007 +  AVR32_MNEMONIC_PICOVMUL,
30008 +  AVR32_MNEMONIC_PICOLD_D,
30009 +  AVR32_MNEMONIC_PICOLD_W,
30010 +  AVR32_MNEMONIC_PICOLDM_D,
30011 +  AVR32_MNEMONIC_PICOLDM_W,
30012 +  AVR32_MNEMONIC_PICOMV_D,
30013 +  AVR32_MNEMONIC_PICOMV_W,
30014 +  AVR32_MNEMONIC_PICOST_D,
30015 +  AVR32_MNEMONIC_PICOST_W,
30016 +  AVR32_MNEMONIC_PICOSTM_D,
30017 +  AVR32_MNEMONIC_PICOSTM_W,
30018 +  AVR32_MNEMONIC_RSUBEQ,
30019 +  AVR32_MNEMONIC_RSUBNE,
30020 +  AVR32_MNEMONIC_RSUBCC,
30021 +  AVR32_MNEMONIC_RSUBCS,
30022 +  AVR32_MNEMONIC_RSUBGE,
30023 +  AVR32_MNEMONIC_RSUBLT,
30024 +  AVR32_MNEMONIC_RSUBMI,
30025 +  AVR32_MNEMONIC_RSUBPL,
30026 +  AVR32_MNEMONIC_RSUBLS,
30027 +  AVR32_MNEMONIC_RSUBGT,
30028 +  AVR32_MNEMONIC_RSUBLE,
30029 +  AVR32_MNEMONIC_RSUBHI,
30030 +  AVR32_MNEMONIC_RSUBVS,
30031 +  AVR32_MNEMONIC_RSUBVC,
30032 +  AVR32_MNEMONIC_RSUBQS,
30033 +  AVR32_MNEMONIC_RSUBAL,
30034 +  AVR32_MNEMONIC_RSUBHS,
30035 +  AVR32_MNEMONIC_RSUBLO,
30036 +  AVR32_MNEMONIC_ADDEQ,
30037 +  AVR32_MNEMONIC_ADDNE,
30038 +  AVR32_MNEMONIC_ADDCC,
30039 +  AVR32_MNEMONIC_ADDCS,
30040 +  AVR32_MNEMONIC_ADDGE,
30041 +  AVR32_MNEMONIC_ADDLT,
30042 +  AVR32_MNEMONIC_ADDMI,
30043 +  AVR32_MNEMONIC_ADDPL,
30044 +  AVR32_MNEMONIC_ADDLS,
30045 +  AVR32_MNEMONIC_ADDGT,
30046 +  AVR32_MNEMONIC_ADDLE,
30047 +  AVR32_MNEMONIC_ADDHI,
30048 +  AVR32_MNEMONIC_ADDVS,
30049 +  AVR32_MNEMONIC_ADDVC,
30050 +  AVR32_MNEMONIC_ADDQS,
30051 +  AVR32_MNEMONIC_ADDAL,
30052 +  AVR32_MNEMONIC_ADDHS,
30053 +  AVR32_MNEMONIC_ADDLO,
30054 +  AVR32_MNEMONIC_ANDEQ,
30055 +  AVR32_MNEMONIC_ANDNE,
30056 +  AVR32_MNEMONIC_ANDCC,
30057 +  AVR32_MNEMONIC_ANDCS,
30058 +  AVR32_MNEMONIC_ANDGE,
30059 +  AVR32_MNEMONIC_ANDLT,
30060 +  AVR32_MNEMONIC_ANDMI,
30061 +  AVR32_MNEMONIC_ANDPL,
30062 +  AVR32_MNEMONIC_ANDLS,
30063 +  AVR32_MNEMONIC_ANDGT,
30064 +  AVR32_MNEMONIC_ANDLE,
30065 +  AVR32_MNEMONIC_ANDHI,
30066 +  AVR32_MNEMONIC_ANDVS,
30067 +  AVR32_MNEMONIC_ANDVC,
30068 +  AVR32_MNEMONIC_ANDQS,
30069 +  AVR32_MNEMONIC_ANDAL,
30070 +  AVR32_MNEMONIC_ANDHS,
30071 +  AVR32_MNEMONIC_ANDLO,
30072 +  AVR32_MNEMONIC_OREQ,
30073 +  AVR32_MNEMONIC_ORNE,
30074 +  AVR32_MNEMONIC_ORCC,
30075 +  AVR32_MNEMONIC_ORCS,
30076 +  AVR32_MNEMONIC_ORGE,
30077 +  AVR32_MNEMONIC_ORLT,
30078 +  AVR32_MNEMONIC_ORMI,
30079 +  AVR32_MNEMONIC_ORPL,
30080 +  AVR32_MNEMONIC_ORLS,
30081 +  AVR32_MNEMONIC_ORGT,
30082 +  AVR32_MNEMONIC_ORLE,
30083 +  AVR32_MNEMONIC_ORHI,
30084 +  AVR32_MNEMONIC_ORVS,
30085 +  AVR32_MNEMONIC_ORVC,
30086 +  AVR32_MNEMONIC_ORQS,
30087 +  AVR32_MNEMONIC_ORAL,
30088 +  AVR32_MNEMONIC_ORHS,
30089 +  AVR32_MNEMONIC_ORLO,
30090 +  AVR32_MNEMONIC_EOREQ,
30091 +  AVR32_MNEMONIC_EORNE,
30092 +  AVR32_MNEMONIC_EORCC,
30093 +  AVR32_MNEMONIC_EORCS,
30094 +  AVR32_MNEMONIC_EORGE,
30095 +  AVR32_MNEMONIC_EORLT,
30096 +  AVR32_MNEMONIC_EORMI,
30097 +  AVR32_MNEMONIC_EORPL,
30098 +  AVR32_MNEMONIC_EORLS,
30099 +  AVR32_MNEMONIC_EORGT,
30100 +  AVR32_MNEMONIC_EORLE,
30101 +  AVR32_MNEMONIC_EORHI,
30102 +  AVR32_MNEMONIC_EORVS,
30103 +  AVR32_MNEMONIC_EORVC,
30104 +  AVR32_MNEMONIC_EORQS,
30105 +  AVR32_MNEMONIC_EORAL,
30106 +  AVR32_MNEMONIC_EORHS,
30107 +  AVR32_MNEMONIC_EORLO,
30108 +  AVR32_MNEMONIC_LD_WEQ,
30109 +  AVR32_MNEMONIC_LD_WNE,
30110 +  AVR32_MNEMONIC_LD_WCC,
30111 +  AVR32_MNEMONIC_LD_WCS,
30112 +  AVR32_MNEMONIC_LD_WGE,
30113 +  AVR32_MNEMONIC_LD_WLT,
30114 +  AVR32_MNEMONIC_LD_WMI,
30115 +  AVR32_MNEMONIC_LD_WPL,
30116 +  AVR32_MNEMONIC_LD_WLS,
30117 +  AVR32_MNEMONIC_LD_WGT,
30118 +  AVR32_MNEMONIC_LD_WLE,
30119 +  AVR32_MNEMONIC_LD_WHI,
30120 +  AVR32_MNEMONIC_LD_WVS,
30121 +  AVR32_MNEMONIC_LD_WVC,
30122 +  AVR32_MNEMONIC_LD_WQS,
30123 +  AVR32_MNEMONIC_LD_WAL,
30124 +  AVR32_MNEMONIC_LD_WHS,
30125 +  AVR32_MNEMONIC_LD_WLO,
30126 +  AVR32_MNEMONIC_LD_SHEQ,
30127 +  AVR32_MNEMONIC_LD_SHNE,
30128 +  AVR32_MNEMONIC_LD_SHCC,
30129 +  AVR32_MNEMONIC_LD_SHCS,
30130 +  AVR32_MNEMONIC_LD_SHGE,
30131 +  AVR32_MNEMONIC_LD_SHLT,
30132 +  AVR32_MNEMONIC_LD_SHMI,
30133 +  AVR32_MNEMONIC_LD_SHPL,
30134 +  AVR32_MNEMONIC_LD_SHLS,
30135 +  AVR32_MNEMONIC_LD_SHGT,
30136 +  AVR32_MNEMONIC_LD_SHLE,
30137 +  AVR32_MNEMONIC_LD_SHHI,
30138 +  AVR32_MNEMONIC_LD_SHVS,
30139 +  AVR32_MNEMONIC_LD_SHVC,
30140 +  AVR32_MNEMONIC_LD_SHQS,
30141 +  AVR32_MNEMONIC_LD_SHAL,
30142 +  AVR32_MNEMONIC_LD_SHHS,
30143 +  AVR32_MNEMONIC_LD_SHLO,
30144 +  AVR32_MNEMONIC_LD_UHEQ,
30145 +  AVR32_MNEMONIC_LD_UHNE,
30146 +  AVR32_MNEMONIC_LD_UHCC,
30147 +  AVR32_MNEMONIC_LD_UHCS,
30148 +  AVR32_MNEMONIC_LD_UHGE,
30149 +  AVR32_MNEMONIC_LD_UHLT,
30150 +  AVR32_MNEMONIC_LD_UHMI,
30151 +  AVR32_MNEMONIC_LD_UHPL,
30152 +  AVR32_MNEMONIC_LD_UHLS,
30153 +  AVR32_MNEMONIC_LD_UHGT,
30154 +  AVR32_MNEMONIC_LD_UHLE,
30155 +  AVR32_MNEMONIC_LD_UHHI,
30156 +  AVR32_MNEMONIC_LD_UHVS,
30157 +  AVR32_MNEMONIC_LD_UHVC,
30158 +  AVR32_MNEMONIC_LD_UHQS,
30159 +  AVR32_MNEMONIC_LD_UHAL,
30160 +  AVR32_MNEMONIC_LD_UHHS,
30161 +  AVR32_MNEMONIC_LD_UHLO,
30162 +  AVR32_MNEMONIC_LD_SBEQ,
30163 +  AVR32_MNEMONIC_LD_SBNE,
30164 +  AVR32_MNEMONIC_LD_SBCC,
30165 +  AVR32_MNEMONIC_LD_SBCS,
30166 +  AVR32_MNEMONIC_LD_SBGE,
30167 +  AVR32_MNEMONIC_LD_SBLT,
30168 +  AVR32_MNEMONIC_LD_SBMI,
30169 +  AVR32_MNEMONIC_LD_SBPL,
30170 +  AVR32_MNEMONIC_LD_SBLS,
30171 +  AVR32_MNEMONIC_LD_SBGT,
30172 +  AVR32_MNEMONIC_LD_SBLE,
30173 +  AVR32_MNEMONIC_LD_SBHI,
30174 +  AVR32_MNEMONIC_LD_SBVS,
30175 +  AVR32_MNEMONIC_LD_SBVC,
30176 +  AVR32_MNEMONIC_LD_SBQS,
30177 +  AVR32_MNEMONIC_LD_SBAL,
30178 +  AVR32_MNEMONIC_LD_SBHS,
30179 +  AVR32_MNEMONIC_LD_SBLO,
30180 +  AVR32_MNEMONIC_LD_UBEQ,
30181 +  AVR32_MNEMONIC_LD_UBNE,
30182 +  AVR32_MNEMONIC_LD_UBCC,
30183 +  AVR32_MNEMONIC_LD_UBCS,
30184 +  AVR32_MNEMONIC_LD_UBGE,
30185 +  AVR32_MNEMONIC_LD_UBLT,
30186 +  AVR32_MNEMONIC_LD_UBMI,
30187 +  AVR32_MNEMONIC_LD_UBPL,
30188 +  AVR32_MNEMONIC_LD_UBLS,
30189 +  AVR32_MNEMONIC_LD_UBGT,
30190 +  AVR32_MNEMONIC_LD_UBLE,
30191 +  AVR32_MNEMONIC_LD_UBHI,
30192 +  AVR32_MNEMONIC_LD_UBVS,
30193 +  AVR32_MNEMONIC_LD_UBVC,
30194 +  AVR32_MNEMONIC_LD_UBQS,
30195 +  AVR32_MNEMONIC_LD_UBAL,
30196 +  AVR32_MNEMONIC_LD_UBHS,
30197 +  AVR32_MNEMONIC_LD_UBLO,
30198 +  AVR32_MNEMONIC_ST_WEQ,
30199 +  AVR32_MNEMONIC_ST_WNE,
30200 +  AVR32_MNEMONIC_ST_WCC,
30201 +  AVR32_MNEMONIC_ST_WCS,
30202 +  AVR32_MNEMONIC_ST_WGE,
30203 +  AVR32_MNEMONIC_ST_WLT,
30204 +  AVR32_MNEMONIC_ST_WMI,
30205 +  AVR32_MNEMONIC_ST_WPL,
30206 +  AVR32_MNEMONIC_ST_WLS,
30207 +  AVR32_MNEMONIC_ST_WGT,
30208 +  AVR32_MNEMONIC_ST_WLE,
30209 +  AVR32_MNEMONIC_ST_WHI,
30210 +  AVR32_MNEMONIC_ST_WVS,
30211 +  AVR32_MNEMONIC_ST_WVC,
30212 +  AVR32_MNEMONIC_ST_WQS,
30213 +  AVR32_MNEMONIC_ST_WAL,
30214 +  AVR32_MNEMONIC_ST_WHS,
30215 +  AVR32_MNEMONIC_ST_WLO,
30216 +  AVR32_MNEMONIC_ST_HEQ,
30217 +  AVR32_MNEMONIC_ST_HNE,
30218 +  AVR32_MNEMONIC_ST_HCC,
30219 +  AVR32_MNEMONIC_ST_HCS,
30220 +  AVR32_MNEMONIC_ST_HGE,
30221 +  AVR32_MNEMONIC_ST_HLT,
30222 +  AVR32_MNEMONIC_ST_HMI,
30223 +  AVR32_MNEMONIC_ST_HPL,
30224 +  AVR32_MNEMONIC_ST_HLS,
30225 +  AVR32_MNEMONIC_ST_HGT,
30226 +  AVR32_MNEMONIC_ST_HLE,
30227 +  AVR32_MNEMONIC_ST_HHI,
30228 +  AVR32_MNEMONIC_ST_HVS,
30229 +  AVR32_MNEMONIC_ST_HVC,
30230 +  AVR32_MNEMONIC_ST_HQS,
30231 +  AVR32_MNEMONIC_ST_HAL,
30232 +  AVR32_MNEMONIC_ST_HHS,
30233 +  AVR32_MNEMONIC_ST_HLO,
30234 +  AVR32_MNEMONIC_ST_BEQ,
30235 +  AVR32_MNEMONIC_ST_BNE,
30236 +  AVR32_MNEMONIC_ST_BCC,
30237 +  AVR32_MNEMONIC_ST_BCS,
30238 +  AVR32_MNEMONIC_ST_BGE,
30239 +  AVR32_MNEMONIC_ST_BLT,
30240 +  AVR32_MNEMONIC_ST_BMI,
30241 +  AVR32_MNEMONIC_ST_BPL,
30242 +  AVR32_MNEMONIC_ST_BLS,
30243 +  AVR32_MNEMONIC_ST_BGT,
30244 +  AVR32_MNEMONIC_ST_BLE,
30245 +  AVR32_MNEMONIC_ST_BHI,
30246 +  AVR32_MNEMONIC_ST_BVS,
30247 +  AVR32_MNEMONIC_ST_BVC,
30248 +  AVR32_MNEMONIC_ST_BQS,
30249 +  AVR32_MNEMONIC_ST_BAL,
30250 +  AVR32_MNEMONIC_ST_BHS,
30251 +  AVR32_MNEMONIC_ST_BLO,
30252 +  AVR32_MNEMONIC_MOVH,
30253 +  AVR32_MNEMONIC__END_
30254 +};
30255 +#define AVR32_NR_MNEMONICS AVR32_MNEMONIC__END_
30256 +
30257 +enum avr32_syntax_parser
30258 +  {
30259 +    AVR32_PARSER_NORMAL,
30260 +    AVR32_PARSER_ALIAS,
30261 +    AVR32_PARSER_LDA,
30262 +    AVR32_PARSER_CALL,
30263 +    AVR32_PARSER__END_
30264 +  };
30265 +#define AVR32_NR_PARSERS AVR32_PARSER__END_
30266 --- a/opcodes/configure.in
30267 +++ b/opcodes/configure.in
30268 @@ -223,6 +223,7 @@ if test x${all_targets} = xfalse ; then
30269         bfd_arc_arch)           ta="$ta arc-dis.lo arc-opc.lo arc-ext.lo" ;;
30270         bfd_arm_arch)           ta="$ta arm-dis.lo" ;;
30271         bfd_avr_arch)           ta="$ta avr-dis.lo" ;;
30272 +       bfd_avr32_arch)         ta="$ta avr32-asm.lo avr32-dis.lo avr32-opc.lo" ;;
30273         bfd_bfin_arch)          ta="$ta bfin-dis.lo" ;;
30274         bfd_cr16_arch)          ta="$ta cr16-dis.lo cr16-opc.lo" ;;
30275         bfd_cris_arch)          ta="$ta cris-dis.lo cris-opc.lo cgen-bitset.lo" ;;
30276 @@ -285,7 +286,7 @@ if test x${all_targets} = xfalse ; then
30277                                 ta="$ta sh64-dis.lo sh64-opc.lo"
30278                                 archdefs="$archdefs -DINCLUDE_SHMEDIA"
30279                                 break;;
30280 -           esac;
30281 +           esac
30282           done
30283                                 ta="$ta sh-dis.lo cgen-bitset.lo" ;;
30284         bfd_sparc_arch)         ta="$ta sparc-dis.lo sparc-opc.lo" ;;
30285 --- a/opcodes/disassemble.c
30286 +++ b/opcodes/disassemble.c
30287 @@ -27,6 +27,7 @@
30288  #define ARCH_arc
30289  #define ARCH_arm
30290  #define ARCH_avr
30291 +#define ARCH_avr32
30292  #define ARCH_bfin
30293  #define ARCH_cr16
30294  #define ARCH_cris
30295 @@ -131,6 +132,11 @@ disassembler (abfd)
30296        disassemble = print_insn_avr;
30297        break;
30298  #endif
30299 +#ifdef ARCH_avr32
30300 +    case bfd_arch_avr32:
30301 +      disassemble = print_insn_avr32;
30302 +      break;
30303 +#endif
30304  #ifdef ARCH_bfin
30305      case bfd_arch_bfin:
30306        disassemble = print_insn_bfin;
30307 @@ -485,6 +491,9 @@ disassembler_usage (stream)
30308  #ifdef ARCH_i386
30309    print_i386_disassembler_options (stream);
30310  #endif
30311 +#ifdef ARCH_avr32
30312 +  print_avr32_disassembler_options (stream);
30313 +#endif
30314  #ifdef ARCH_s390
30315    print_s390_disassembler_options (stream);
30316  #endif
30317 --- a/bfd/configure
30318 +++ b/bfd/configure
30319 @@ -14787,6 +14787,7 @@ do
30320      bfd_pei_ia64_vec)          tb="$tb pei-ia64.lo pepigen.lo cofflink.lo"; target_size=64 ;;
30321      bfd_elf32_am33lin_vec)     tb="$tb elf32-am33lin.lo elf32.lo $elf" ;;
30322      bfd_elf32_avr_vec)         tb="$tb elf32-avr.lo elf32.lo $elf" ;;
30323 +    bfd_elf32_avr32_vec)       tb="$tb elf32-avr32.lo elf32.lo $elf" ;;
30324      bfd_elf32_bfin_vec)                tb="$tb elf32-bfin.lo elf32.lo $elf" ;;
30325      bfd_elf32_bfinfdpic_vec)   tb="$tb elf32-bfin.lo elf32.lo $elf" ;;
30326      bfd_elf32_big_generic_vec)         tb="$tb elf32-gen.lo elf32.lo $elf" ;;
30327 --- a/opcodes/configure
30328 +++ b/opcodes/configure
30329 @@ -12284,6 +12284,7 @@ if test x${all_targets} = xfalse ; then
30330         bfd_arc_arch)           ta="$ta arc-dis.lo arc-opc.lo arc-ext.lo" ;;
30331         bfd_arm_arch)           ta="$ta arm-dis.lo" ;;
30332         bfd_avr_arch)           ta="$ta avr-dis.lo" ;;
30333 +       bfd_avr32_arch)         ta="$ta avr32-asm.lo avr32-dis.lo avr32-opc.lo" ;;
30334         bfd_bfin_arch)          ta="$ta bfin-dis.lo" ;;
30335         bfd_cr16_arch)          ta="$ta cr16-dis.lo cr16-opc.lo" ;;
30336         bfd_cris_arch)          ta="$ta cris-dis.lo cris-opc.lo cgen-bitset.lo" ;;
30337 --- a/bfd/libbfd.h
30338 +++ b/bfd/libbfd.h
30339 @@ -1646,6 +1646,48 @@ static const char *const bfd_reloc_code_
30340    "BFD_RELOC_AVR_LDI",
30341    "BFD_RELOC_AVR_6",
30342    "BFD_RELOC_AVR_6_ADIW",
30343 +  "BFD_RELOC_AVR32_DIFF32",
30344 +  "BFD_RELOC_AVR32_DIFF16",
30345 +  "BFD_RELOC_AVR32_DIFF8",
30346 +  "BFD_RELOC_AVR32_GOT32",
30347 +  "BFD_RELOC_AVR32_GOT16",
30348 +  "BFD_RELOC_AVR32_GOT8",
30349 +  "BFD_RELOC_AVR32_21S",
30350 +  "BFD_RELOC_AVR32_16U",
30351 +  "BFD_RELOC_AVR32_16S",
30352 +  "BFD_RELOC_AVR32_SUB5",
30353 +  "BFD_RELOC_AVR32_8S_EXT",
30354 +  "BFD_RELOC_AVR32_8S",
30355 +  "BFD_RELOC_AVR32_15S",
30356 +  "BFD_RELOC_AVR32_22H_PCREL",
30357 +  "BFD_RELOC_AVR32_18W_PCREL",
30358 +  "BFD_RELOC_AVR32_16B_PCREL",
30359 +  "BFD_RELOC_AVR32_16N_PCREL",
30360 +  "BFD_RELOC_AVR32_14UW_PCREL",
30361 +  "BFD_RELOC_AVR32_11H_PCREL",
30362 +  "BFD_RELOC_AVR32_10UW_PCREL",
30363 +  "BFD_RELOC_AVR32_9H_PCREL",
30364 +  "BFD_RELOC_AVR32_9UW_PCREL",
30365 +  "BFD_RELOC_AVR32_GOTPC",
30366 +  "BFD_RELOC_AVR32_GOTCALL",
30367 +  "BFD_RELOC_AVR32_LDA_GOT",
30368 +  "BFD_RELOC_AVR32_GOT21S",
30369 +  "BFD_RELOC_AVR32_GOT18SW",
30370 +  "BFD_RELOC_AVR32_GOT16S",
30371 +  "BFD_RELOC_AVR32_32_CPENT",
30372 +  "BFD_RELOC_AVR32_CPCALL",
30373 +  "BFD_RELOC_AVR32_16_CP",
30374 +  "BFD_RELOC_AVR32_9W_CP",
30375 +  "BFD_RELOC_AVR32_ALIGN",
30376 +  "BFD_RELOC_AVR32_14UW",
30377 +  "BFD_RELOC_AVR32_10UW",
30378 +  "BFD_RELOC_AVR32_10SW",
30379 +  "BFD_RELOC_AVR32_STHH_W",
30380 +  "BFD_RELOC_AVR32_7UW",
30381 +  "BFD_RELOC_AVR32_6S",
30382 +  "BFD_RELOC_AVR32_6UW",
30383 +  "BFD_RELOC_AVR32_4UH",
30384 +  "BFD_RELOC_AVR32_3U",
30385    "BFD_RELOC_390_12",
30386    "BFD_RELOC_390_GOT12",
30387    "BFD_RELOC_390_PLT32",
30388 --- a/ld/Makefile.in
30389 +++ b/ld/Makefile.in
30390 @@ -434,6 +434,53 @@ ALL_EMULATIONS = \
30391         eavr5.o \
30392         eavr51.o \
30393         eavr6.o \
30394 +       eavr32elf_ap7000.o \
30395 +       eavr32elf_ap7001.o \
30396 +       eavr32elf_ap7002.o \
30397 +       eavr32elf_ap7200.o \
30398 +       eavr32elf_uc3a0128.o \
30399 +       eavr32elf_uc3a0256.o \
30400 +       eavr32elf_uc3a0512.o \
30401 +       eavr32elf_uc3a0512es.o \
30402 +       eavr32elf_uc3a1128.o \
30403 +       eavr32elf_uc3a1256.o \
30404 +       eavr32elf_uc3a1512es.o \
30405 +       eavr32elf_uc3a1512.o \
30406 +       eavr32elf_uc3a364.o \
30407 +       eavr32elf_uc3a364s.o \
30408 +       eavr32elf_uc3a3128.o \
30409 +       eavr32elf_uc3a3128s.o \
30410 +       eavr32elf_uc3a3256.o \
30411 +       eavr32elf_uc3a3256s.o \
30412 +       eavr32elf_uc3b064.o \
30413 +       eavr32elf_uc3b0128.o \
30414 +       eavr32elf_uc3b0256es.o \
30415 +       eavr32elf_uc3b0256.o \
30416 +       eavr32elf_uc3b0512.o \
30417 +       eavr32elf_uc3b0512revc.o \
30418 +       eavr32elf_uc3b164.o \
30419 +       eavr32elf_uc3b1128.o \
30420 +       eavr32elf_uc3b1256es.o \
30421 +       eavr32elf_uc3b1256.o \
30422 +       eavr32elf_uc3b1512.o \
30423 +       eavr32elf_uc3b1512revc.o \
30424 +       eavr32elf_uc3c064c.o \
30425 +       eavr32elf_uc3c0128c.o \
30426 +       eavr32elf_uc3c0256c.o \
30427 +       eavr32elf_uc3c0512crevc.o \
30428 +       eavr32elf_uc3c164c.o \
30429 +       eavr32elf_uc3c1128c.o \
30430 +       eavr32elf_uc3c1256c.o \
30431 +       eavr32elf_uc3c1512crevc.o \
30432 +       eavr32elf_uc3c264c.o \
30433 +       eavr32elf_uc3c2128c.o \
30434 +       eavr32elf_uc3c2256c.o \
30435 +       eavr32elf_uc3c2512crevc.o \
30436 +       eavr32elf_uc3l064.o \
30437 +       eavr32elf_uc3l032.o \
30438 +       eavr32elf_uc3l016.o \
30439 +       eavr32elf_uc3l064revb.o \
30440 +       eavr32linux.o \
30441         ecoff_i860.o \
30442         ecoff_sparc.o \
30443         eelf32_spu.o \
30444 @@ -2069,6 +2116,194 @@ eavr6.c: $(srcdir)/emulparams/avr6.sh $(
30445    $(ELF_DEPS) $(srcdir)/scripttempl/avr.sc \
30446    ${GEN_DEPENDS}
30447         ${GENSCRIPTS} avr6 "$(tdir_avr2)"
30448 +eavr32elf_ap7000.c: $(srcdir)/emulparams/avr32elf.sh \
30449 +  $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
30450 +  $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
30451 +       ${GENSCRIPTS} avr32elf_ap7000 "$(tdir_avr32)" avr32elf
30452 +eavr32elf_ap7001.c: $(srcdir)/emulparams/avr32elf.sh \
30453 +  $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
30454 +  $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
30455 +       ${GENSCRIPTS} avr32elf_ap7001 "$(tdir_avr32)" avr32elf
30456 +eavr32elf_ap7002.c: $(srcdir)/emulparams/avr32elf.sh \
30457 +  $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
30458 +  $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
30459 +       ${GENSCRIPTS} avr32elf_ap7002 "$(tdir_avr32)" avr32elf
30460 +eavr32elf_ap7200.c: $(srcdir)/emulparams/avr32elf.sh \
30461 +  $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
30462 +  $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
30463 +       ${GENSCRIPTS} avr32elf_ap7200 "$(tdir_avr32)" avr32elf
30464 +eavr32elf_uc3a0128.c: $(srcdir)/emulparams/avr32elf.sh \
30465 +  $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
30466 +  $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
30467 +       ${GENSCRIPTS} avr32elf_uc3a0128 "$(tdir_avr32)" avr32elf
30468 +eavr32elf_uc3a0256.c: $(srcdir)/emulparams/avr32elf.sh \
30469 +  $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
30470 +  $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
30471 +       ${GENSCRIPTS} avr32elf_uc3a0256 "$(tdir_avr32)" avr32elf
30472 +eavr32elf_uc3a0512.c: $(srcdir)/emulparams/avr32elf.sh \
30473 +  $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
30474 +  $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
30475 +       ${GENSCRIPTS} avr32elf_uc3a0512 "$(tdir_avr32)" avr32elf
30476 +eavr32elf_uc3a0512es.c: $(srcdir)/emulparams/avr32elf.sh \
30477 +  $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
30478 +  $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
30479 +       ${GENSCRIPTS} avr32elf_uc3a0512es "$(tdir_avr32)" avr32elf
30480 +eavr32elf_uc3a1128.c: $(srcdir)/emulparams/avr32elf.sh \
30481 +  $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
30482 +  $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
30483 +       ${GENSCRIPTS} avr32elf_uc3a1128 "$(tdir_avr32)" avr32elf
30484 +eavr32elf_uc3a1256.c: $(srcdir)/emulparams/avr32elf.sh \
30485 +  $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
30486 +  $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
30487 +       ${GENSCRIPTS} avr32elf_uc3a1256 "$(tdir_avr32)" avr32elf
30488 +eavr32elf_uc3a1512.c: $(srcdir)/emulparams/avr32elf.sh \
30489 +  $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
30490 +  $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
30491 +       ${GENSCRIPTS} avr32elf_uc3a1512 "$(tdir_avr32)" avr32elf
30492 +eavr32elf_uc3a1512es.c: $(srcdir)/emulparams/avr32elf.sh \
30493 +  $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
30494 +  $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
30495 +       ${GENSCRIPTS} avr32elf_uc3a1512es "$(tdir_avr32)" avr32elf
30496 +eavr32elf_uc3a364.c: $(srcdir)/emulparams/avr32elf.sh \
30497 +  $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
30498 +  $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
30499 +       ${GENSCRIPTS} avr32elf_uc3a364 "$(tdir_avr32)" avr32elf
30500 +eavr32elf_uc3a364s.c: $(srcdir)/emulparams/avr32elf.sh \
30501 +  $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
30502 +  $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
30503 +       ${GENSCRIPTS} avr32elf_uc3a364s "$(tdir_avr32)" avr32elf
30504 +eavr32elf_uc3a3128.c: $(srcdir)/emulparams/avr32elf.sh \
30505 +  $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
30506 +  $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
30507 +       ${GENSCRIPTS} avr32elf_uc3a3128 "$(tdir_avr32)" avr32elf
30508 +eavr32elf_uc3a3128s.c: $(srcdir)/emulparams/avr32elf.sh \
30509 +  $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
30510 +  $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
30511 +       ${GENSCRIPTS} avr32elf_uc3a3128s "$(tdir_avr32)" avr32elf
30512 +eavr32elf_uc3a3256.c: $(srcdir)/emulparams/avr32elf.sh \
30513 +  $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
30514 +  $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
30515 +       ${GENSCRIPTS} avr32elf_uc3a3256 "$(tdir_avr32)" avr32elf
30516 +eavr32elf_uc3a3256s.c: $(srcdir)/emulparams/avr32elf.sh \
30517 +  $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
30518 +  $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
30519 +       ${GENSCRIPTS} avr32elf_uc3a3256s "$(tdir_avr32)" avr32elf
30520 +eavr32elf_uc3b064.c: $(srcdir)/emulparams/avr32elf.sh \
30521 +  $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
30522 +  $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
30523 +       ${GENSCRIPTS} avr32elf_uc3b064 "$(tdir_avr32)" avr32elf
30524 +eavr32elf_uc3b0128.c: $(srcdir)/emulparams/avr32elf.sh \
30525 +  $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
30526 +  $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
30527 +       ${GENSCRIPTS} avr32elf_uc3b0128 "$(tdir_avr32)" avr32elf
30528 +eavr32elf_uc3b0256.c: $(srcdir)/emulparams/avr32elf.sh \
30529 +  $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
30530 +  $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
30531 +       ${GENSCRIPTS} avr32elf_uc3b0256 "$(tdir_avr32)" avr32elf
30532 +eavr32elf_uc3b0256es.c: $(srcdir)/emulparams/avr32elf.sh \
30533 +  $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
30534 +  $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
30535 +       ${GENSCRIPTS} avr32elf_uc3b0256es "$(tdir_avr32)" avr32elf
30536 +eavr32elf_uc3b0512.c: $(srcdir)/emulparams/avr32elf.sh \
30537 +  $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
30538 +  $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
30539 +       ${GENSCRIPTS} avr32elf_uc3b0512 "$(tdir_avr32)" avr32elf
30540 +eavr32elf_uc3b0512revc.c: $(srcdir)/emulparams/avr32elf.sh \
30541 +  $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
30542 +  $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
30543 +       ${GENSCRIPTS} avr32elf_uc3b0512revc "$(tdir_avr32)" avr32elf
30544 +eavr32elf_uc3b164.c: $(srcdir)/emulparams/avr32elf.sh \
30545 +  $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
30546 +  $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
30547 +       ${GENSCRIPTS} avr32elf_uc3b164 "$(tdir_avr32)" avr32elf
30548 +eavr32elf_uc3b1128.c: $(srcdir)/emulparams/avr32elf.sh \
30549 +  $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
30550 +  $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
30551 +       ${GENSCRIPTS} avr32elf_uc3b1128 "$(tdir_avr32)" avr32elf
30552 +eavr32elf_uc3b1256.c: $(srcdir)/emulparams/avr32elf.sh \
30553 +  $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
30554 +  $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
30555 +       ${GENSCRIPTS} avr32elf_uc3b1256 "$(tdir_avr32)" avr32elf
30556 +eavr32elf_uc3b1256es.c: $(srcdir)/emulparams/avr32elf.sh \
30557 +  $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
30558 +  $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
30559 +       ${GENSCRIPTS} avr32elf_uc3b1256es "$(tdir_avr32)" avr32elf
30560 +eavr32elf_uc3b1512.c: $(srcdir)/emulparams/avr32elf.sh \
30561 +  $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
30562 +  $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
30563 +       ${GENSCRIPTS} avr32elf_uc3b1512 "$(tdir_avr32)" avr32elf
30564 +eavr32elf_uc3b1512revc.c: $(srcdir)/emulparams/avr32elf.sh \
30565 +  $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
30566 +  $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
30567 +       ${GENSCRIPTS} avr32elf_uc3b1512revc "$(tdir_avr32)" avr32elf
30568 +eavr32elf_uc3c064c.c: $(srcdir)/emulparams/avr32elf.sh \
30569 +  $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
30570 +  $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
30571 +       ${GENSCRIPTS} avr32elf_uc3c064c "$(tdir_avr32)" avr32elf
30572 +eavr32elf_uc3c0128c.c: $(srcdir)/emulparams/avr32elf.sh \
30573 +  $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
30574 +  $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
30575 +       ${GENSCRIPTS} avr32elf_uc3c0128c "$(tdir_avr32)" avr32elf
30576 +eavr32elf_uc3c0256c.c: $(srcdir)/emulparams/avr32elf.sh \
30577 +  $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
30578 +  $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
30579 +       ${GENSCRIPTS} avr32elf_uc3c0256c "$(tdir_avr32)" avr32elf
30580 +eavr32elf_uc3c0512crevc.c: $(srcdir)/emulparams/avr32elf.sh \
30581 +  $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
30582 +  $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
30583 +       ${GENSCRIPTS} avr32elf_uc3c0512crevc "$(tdir_avr32)" avr32elf
30584 +eavr32elf_uc3c164c.c: $(srcdir)/emulparams/avr32elf.sh \
30585 +  $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
30586 +  $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
30587 +       ${GENSCRIPTS} avr32elf_uc3c164c "$(tdir_avr32)" avr32elf
30588 +eavr32elf_uc3c1128c.c: $(srcdir)/emulparams/avr32elf.sh \
30589 +  $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
30590 +  $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
30591 +       ${GENSCRIPTS} avr32elf_uc3c1128c "$(tdir_avr32)" avr32elf
30592 +eavr32elf_uc3c1256c.c: $(srcdir)/emulparams/avr32elf.sh \
30593 +  $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
30594 +  $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
30595 +       ${GENSCRIPTS} avr32elf_uc3c1256c "$(tdir_avr32)" avr32elf
30596 +eavr32elf_uc3c1512crevc.c: $(srcdir)/emulparams/avr32elf.sh \
30597 +  $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
30598 +  $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
30599 +       ${GENSCRIPTS} avr32elf_uc3c1512crevc "$(tdir_avr32)" avr32elf
30600 +eavr32elf_uc3c264c.c: $(srcdir)/emulparams/avr32elf.sh \
30601 +  $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
30602 +  $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
30603 +       ${GENSCRIPTS} avr32elf_uc3c264c "$(tdir_avr32)" avr32elf
30604 +eavr32elf_uc3c2128c.c: $(srcdir)/emulparams/avr32elf.sh \
30605 +  $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
30606 +  $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
30607 +       ${GENSCRIPTS} avr32elf_uc3c2128c "$(tdir_avr32)" avr32elf
30608 +eavr32elf_uc3c2256c.c: $(srcdir)/emulparams/avr32elf.sh \
30609 +  $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
30610 +  $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
30611 +       ${GENSCRIPTS} avr32elf_uc3c2256c "$(tdir_avr32)" avr32elf
30612 +eavr32elf_uc3c2512crevc.c: $(srcdir)/emulparams/avr32elf.sh \
30613 +  $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
30614 +  $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
30615 +       ${GENSCRIPTS} avr32elf_uc3c2512crevc "$(tdir_avr32)" avr32elf
30616 +eavr32elf_uc3l064.c: $(srcdir)/emulparams/avr32elf.sh \
30617 +  $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
30618 +  $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
30619 +       ${GENSCRIPTS} avr32elf_uc3l064 "$(tdir_avr32)" avr32elf
30620 +eavr32elf_uc3l032.c: $(srcdir)/emulparams/avr32elf.sh \
30621 +  $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
30622 +  $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
30623 +       ${GENSCRIPTS} avr32elf_uc3l032 "$(tdir_avr32)" avr32elf
30624 +eavr32elf_uc3l016.c: $(srcdir)/emulparams/avr32elf.sh \
30625 +  $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
30626 +  $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
30627 +       ${GENSCRIPTS} avr32elf_uc3l016 "$(tdir_avr32)" avr32elf
30628 +eavr32elf_uc3l064revb.c: $(srcdir)/emulparams/avr32elf.sh \
30629 +  $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
30630 +  $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
30631 +       ${GENSCRIPTS} avr32elf_uc3l064revb "$(tdir_avr32)" avr32elf
30632 +eavr32linux.c: $(srcdir)/emulparams/avr32linux.sh \
30633 +  $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
30634 +  $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS}
30635 +       ${GENSCRIPTS} avr32linux "$(tdir_avr32)"
30636  ecoff_i860.c: $(srcdir)/emulparams/coff_i860.sh \
30637    $(srcdir)/emultempl/generic.em $(srcdir)/scripttempl/i860coff.sc ${GEN_DEPENDS}
30638         ${GENSCRIPTS} coff_i860 "$(tdir_coff_i860)"
30639 --- a/gas/Makefile.in
30640 +++ b/gas/Makefile.in
30641 @@ -309,6 +309,7 @@ CPU_TYPES = \
30642         arc \
30643         arm \
30644         avr \
30645 +       avr32 \
30646         bfin \
30647         cr16 \
30648         cris \
30649 @@ -508,6 +509,7 @@ TARGET_CPU_CFILES = \
30650         config/tc-arc.c \
30651         config/tc-arm.c \
30652         config/tc-avr.c \
30653 +       config/tc-avr32.c \
30654         config/tc-bfin.c \
30655         config/tc-cr16.c \
30656         config/tc-cris.c \
30657 @@ -571,6 +573,7 @@ TARGET_CPU_HFILES = \
30658         config/tc-arc.h \
30659         config/tc-arm.h \
30660         config/tc-avr.h \
30661 +       config/tc-avr32.h \
30662         config/tc-bfin.h \
30663         config/tc-cr16.h \
30664         config/tc-cris.h \
30665 @@ -949,6 +952,7 @@ distclean-compile:
30666  @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/tc-arc.Po@am__quote@
30667  @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/tc-arm.Po@am__quote@
30668  @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/tc-avr.Po@am__quote@
30669 +@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/tc-avr32.Po@am__quote@
30670  @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/tc-bfin.Po@am__quote@
30671  @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/tc-cr16.Po@am__quote@
30672  @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/tc-cris.Po@am__quote@
30673 @@ -1086,6 +1090,20 @@ tc-avr.obj: config/tc-avr.c
30674  @AMDEP_TRUE@@am__fastdepCC_FALSE@      DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
30675  @am__fastdepCC_FALSE@  $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS) -c -o tc-avr.obj `if test -f 'config/tc-avr.c'; then $(CYGPATH_W) 'config/tc-avr.c'; else $(CYGPATH_W) '$(srcdir)/config/tc-avr.c'; fi`
30676
30677 +tc-avr32.o: config/tc-avr32.c
30678 +@am__fastdepCC_TRUE@   $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS) -MT tc-avr32.o -MD -MP -MF $(DEPDIR)/tc-avr32.Tpo -c -o tc-avr32.o `test -f 'config/tc-avr32.c' || echo '$(srcdir)/'`config/tc-avr32.c
30679 +@am__fastdepCC_TRUE@   $(am__mv) $(DEPDIR)/tc-avr32.Tpo $(DEPDIR)/tc-avr32.Po
30680 +@AMDEP_TRUE@@am__fastdepCC_FALSE@      source='config/tc-avr32.c' object='tc-avr32.o' libtool=no @AMDEPBACKSLASH@
30681 +@AMDEP_TRUE@@am__fastdepCC_FALSE@      DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
30682 +@am__fastdepCC_FALSE@  $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS) -c -o tc-avr32.o `test -f 'config/tc-avr32.c' || echo '$(srcdir)/'`config/tc-avr32.c
30683 +
30684 +tc-avr32.obj: config/tc-avr32.c
30685 +@am__fastdepCC_TRUE@   $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS) -MT tc-avr32.obj -MD -MP -MF $(DEPDIR)/tc-avr32.Tpo -c -o tc-avr32.obj `if test -f 'config/tc-avr32.c'; then $(CYGPATH_W) 'config/tc-avr32.c'; else $(CYGPATH_W) '$(srcdir)/config/tc-avr32.c'; fi`
30686 +@am__fastdepCC_TRUE@   $(am__mv) $(DEPDIR)/tc-avr32.Tpo $(DEPDIR)/tc-avr32.Po
30687 +@AMDEP_TRUE@@am__fastdepCC_FALSE@      source='config/tc-avr32.c' object='tc-avr32.obj' libtool=no @AMDEPBACKSLASH@
30688 +@AMDEP_TRUE@@am__fastdepCC_FALSE@      DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
30689 +@am__fastdepCC_FALSE@  $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS) -c -o tc-avr32.obj `if test -f 'config/tc-avr32.c'; then $(CYGPATH_W) 'config/tc-avr32.c'; else $(CYGPATH_W) '$(srcdir)/config/tc-avr32.c'; fi`
30690 +
30691  tc-bfin.o: config/tc-bfin.c
30692  @am__fastdepCC_TRUE@   $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS) -MT tc-bfin.o -MD -MP -MF $(DEPDIR)/tc-bfin.Tpo -c -o tc-bfin.o `test -f 'config/tc-bfin.c' || echo '$(srcdir)/'`config/tc-bfin.c
30693  @am__fastdepCC_TRUE@   $(am__mv) $(DEPDIR)/tc-bfin.Tpo $(DEPDIR)/tc-bfin.Po
30694 --- a/bfd/bfd-in2.h
30695 +++ b/bfd/bfd-in2.h
30696 @@ -2042,6 +2042,12 @@ enum bfd_architecture
30697  #define bfd_mach_avr5          5
30698  #define bfd_mach_avr51         51
30699  #define bfd_mach_avr6          6
30700 +  bfd_arch_avr32,     /* Atmel AVR32 */
30701 +#define bfd_mach_avr32_ap      7000
30702 +#define bfd_mach_avr32_uc      3000
30703 +#define bfd_mach_avr32_ucr1    3001
30704 +#define bfd_mach_avr32_ucr2    3002
30705 +#define bfd_mach_avr32_ucr3    3003
30706    bfd_arch_bfin,        /* ADI Blackfin */
30707  #define bfd_mach_bfin          1
30708    bfd_arch_cr16,       /* National Semiconductor CompactRISC (ie CR16). */
30709 @@ -3851,6 +3857,88 @@ instructions  */
30710  instructions  */
30711    BFD_RELOC_AVR_6_ADIW,
30712
30713 +/* Difference between two labels: L2 - L1. The value of L1 is encoded
30714 +as sym + addend, while the initial difference after assembly is
30715 +inserted into the object file by the assembler.  */
30716 +  BFD_RELOC_AVR32_DIFF32,
30717 +  BFD_RELOC_AVR32_DIFF16,
30718 +  BFD_RELOC_AVR32_DIFF8,
30719 +
30720 +/* Reference to a symbol through the Global Offset Table. The linker
30721 +will allocate an entry for symbol in the GOT and insert the offset
30722 +of this entry as the relocation value.  */
30723 +  BFD_RELOC_AVR32_GOT32,
30724 +  BFD_RELOC_AVR32_GOT16,
30725 +  BFD_RELOC_AVR32_GOT8,
30726 +
30727 +/* Normal (non-pc-relative) code relocations. Alignment and signedness
30728 +is indicated by the suffixes. S means signed, U means unsigned. W
30729 +means word-aligned, H means halfword-aligned, neither means
30730 +byte-aligned (no alignment.) SUB5 is the same relocation as 16S.  */
30731 +  BFD_RELOC_AVR32_21S,
30732 +  BFD_RELOC_AVR32_16U,
30733 +  BFD_RELOC_AVR32_16S,
30734 +  BFD_RELOC_AVR32_SUB5,
30735 +  BFD_RELOC_AVR32_8S_EXT,
30736 +  BFD_RELOC_AVR32_8S,
30737 +  BFD_RELOC_AVR32_15S,
30738 +
30739 +/* PC-relative relocations are signed if neither 'U' nor 'S' is
30740 +specified. However, we explicitly tack on a 'B' to indicate no
30741 +alignment, to avoid confusion with data relocs. All of these resolve
30742 +to sym + addend - offset, except the one with 'N' (negated) suffix.
30743 +This particular one resolves to offset - sym - addend.  */
30744 +  BFD_RELOC_AVR32_22H_PCREL,
30745 +  BFD_RELOC_AVR32_18W_PCREL,
30746 +  BFD_RELOC_AVR32_16B_PCREL,
30747 +  BFD_RELOC_AVR32_16N_PCREL,
30748 +  BFD_RELOC_AVR32_14UW_PCREL,
30749 +  BFD_RELOC_AVR32_11H_PCREL,
30750 +  BFD_RELOC_AVR32_10UW_PCREL,
30751 +  BFD_RELOC_AVR32_9H_PCREL,
30752 +  BFD_RELOC_AVR32_9UW_PCREL,
30753 +
30754 +/* Subtract the link-time address of the GOT from (symbol + addend)
30755 +and insert the result.  */
30756 +  BFD_RELOC_AVR32_GOTPC,
30757 +
30758 +/* Reference to a symbol through the GOT. The linker will allocate an
30759 +entry for symbol in the GOT and insert the offset of this entry as
30760 +the relocation value. addend must be zero. As usual, 'S' means
30761 +signed, 'W' means word-aligned, etc.  */
30762 +  BFD_RELOC_AVR32_GOTCALL,
30763 +  BFD_RELOC_AVR32_LDA_GOT,
30764 +  BFD_RELOC_AVR32_GOT21S,
30765 +  BFD_RELOC_AVR32_GOT18SW,
30766 +  BFD_RELOC_AVR32_GOT16S,
30767 +
30768 +/* 32-bit constant pool entry. I don't think 8- and 16-bit entries make
30769 +a whole lot of sense.  */
30770 +  BFD_RELOC_AVR32_32_CPENT,
30771 +
30772 +/* Constant pool references. Some of these relocations are signed,
30773 +others are unsigned. It doesn't really matter, since the constant
30774 +pool always comes after the code that references it.  */
30775 +  BFD_RELOC_AVR32_CPCALL,
30776 +  BFD_RELOC_AVR32_16_CP,
30777 +  BFD_RELOC_AVR32_9W_CP,
30778 +
30779 +/* sym must be the absolute symbol. The addend specifies the alignment
30780 +order, e.g. if addend is 2, the linker must add padding so that the
30781 +next address is aligned to a 4-byte boundary.  */
30782 +  BFD_RELOC_AVR32_ALIGN,
30783 +
30784 +/* Code relocations that will never make it to the output file.  */
30785 +  BFD_RELOC_AVR32_14UW,
30786 +  BFD_RELOC_AVR32_10UW,
30787 +  BFD_RELOC_AVR32_10SW,
30788 +  BFD_RELOC_AVR32_STHH_W,
30789 +  BFD_RELOC_AVR32_7UW,
30790 +  BFD_RELOC_AVR32_6S,
30791 +  BFD_RELOC_AVR32_6UW,
30792 +  BFD_RELOC_AVR32_4UH,
30793 +  BFD_RELOC_AVR32_3U,
30794 +
30795  /* Direct 12 bit.  */
30796    BFD_RELOC_390_12,
30797