toolchain/binutils/patches/2.19.1/700-avr32.patch

   1 --- a/bfd/archures.c
   2 +++ b/bfd/archures.c
   3 @@ -357,6 +357,12 @@ DESCRIPTION
   4  .#define bfd_mach_avr5         5
   5  .#define bfd_mach_avr51                51
   6  .#define bfd_mach_avr6         6
   7 +.  bfd_arch_avr32,     {* Atmel AVR32 *}
   8 +.#define bfd_mach_avr32_ap     7000
   9 +.#define bfd_mach_avr32_uc     3000
  10 +.#define bfd_mach_avr32_ucr1    3001
  11 +.#define bfd_mach_avr32_ucr2    3002
  12 +.#define bfd_mach_avr32_ucr3    3003
  13  .  bfd_arch_bfin,        {* ADI Blackfin *}
  14  .#define bfd_mach_bfin          1
  15  .  bfd_arch_cr16,       {* National Semiconductor CompactRISC (ie CR16). *}
  16 @@ -454,6 +460,7 @@ extern const bfd_arch_info_type bfd_alph
  17  extern const bfd_arch_info_type bfd_arc_arch;
  18  extern const bfd_arch_info_type bfd_arm_arch;
  19  extern const bfd_arch_info_type bfd_avr_arch;
  20 +extern const bfd_arch_info_type bfd_avr32_arch;
  21  extern const bfd_arch_info_type bfd_bfin_arch;
  22  extern const bfd_arch_info_type bfd_cr16_arch;
  23  extern const bfd_arch_info_type bfd_cr16c_arch;
  24 @@ -526,6 +533,7 @@ static const bfd_arch_info_type * const
  25      &bfd_arc_arch,
  26      &bfd_arm_arch,
  27      &bfd_avr_arch,
  28 +    &bfd_avr32_arch,
  29      &bfd_bfin_arch,
  30      &bfd_cr16_arch,
  31      &bfd_cr16c_arch,
  32 --- a/bfd/bfd-in2.h
  33 +++ b/bfd/bfd-in2.h
  34 @@ -1979,6 +1979,12 @@ enum bfd_architecture
  35  #define bfd_mach_avr5          5
  36  #define bfd_mach_avr51         51
  37  #define bfd_mach_avr6          6
  38 +  bfd_arch_avr32,     /* Atmel AVR32 */
  39 +#define bfd_mach_avr32_ap      7000
  40 +#define bfd_mach_avr32_uc      3000
  41 +#define bfd_mach_avr32_ucr1    3001
  42 +#define bfd_mach_avr32_ucr2    3002
  43 +#define bfd_mach_avr32_ucr3    3003
  44    bfd_arch_bfin,        /* ADI Blackfin */
  45  #define bfd_mach_bfin          1
  46    bfd_arch_cr16,       /* National Semiconductor CompactRISC (ie CR16). */
  47 @@ -3748,6 +3754,88 @@ instructions  */
  48  instructions  */
  49    BFD_RELOC_AVR_6_ADIW,
  50
  51 +/* Difference between two labels: L2 - L1. The value of L1 is encoded
  52 +as sym + addend, while the initial difference after assembly is
  53 +inserted into the object file by the assembler.  */
  54 +  BFD_RELOC_AVR32_DIFF32,
  55 +  BFD_RELOC_AVR32_DIFF16,
  56 +  BFD_RELOC_AVR32_DIFF8,
  57 +
  58 +/* Reference to a symbol through the Global Offset Table. The linker
  59 +will allocate an entry for symbol in the GOT and insert the offset
  60 +of this entry as the relocation value.  */
  61 +  BFD_RELOC_AVR32_GOT32,
  62 +  BFD_RELOC_AVR32_GOT16,
  63 +  BFD_RELOC_AVR32_GOT8,
  64 +
  65 +/* Normal (non-pc-relative) code relocations. Alignment and signedness
  66 +is indicated by the suffixes. S means signed, U means unsigned. W
  67 +means word-aligned, H means halfword-aligned, neither means
  68 +byte-aligned (no alignment.) SUB5 is the same relocation as 16S.  */
  69 +  BFD_RELOC_AVR32_21S,
  70 +  BFD_RELOC_AVR32_16U,
  71 +  BFD_RELOC_AVR32_16S,
  72 +  BFD_RELOC_AVR32_SUB5,
  73 +  BFD_RELOC_AVR32_8S_EXT,
  74 +  BFD_RELOC_AVR32_8S,
  75 +  BFD_RELOC_AVR32_15S,
  76 +
  77 +/* PC-relative relocations are signed if neither 'U' nor 'S' is
  78 +specified. However, we explicitly tack on a 'B' to indicate no
  79 +alignment, to avoid confusion with data relocs. All of these resolve
  80 +to sym + addend - offset, except the one with 'N' (negated) suffix.
  81 +This particular one resolves to offset - sym - addend.  */
  82 +  BFD_RELOC_AVR32_22H_PCREL,
  83 +  BFD_RELOC_AVR32_18W_PCREL,
  84 +  BFD_RELOC_AVR32_16B_PCREL,
  85 +  BFD_RELOC_AVR32_16N_PCREL,
  86 +  BFD_RELOC_AVR32_14UW_PCREL,
  87 +  BFD_RELOC_AVR32_11H_PCREL,
  88 +  BFD_RELOC_AVR32_10UW_PCREL,
  89 +  BFD_RELOC_AVR32_9H_PCREL,
  90 +  BFD_RELOC_AVR32_9UW_PCREL,
  91 +
  92 +/* Subtract the link-time address of the GOT from (symbol + addend)
  93 +and insert the result.  */
  94 +  BFD_RELOC_AVR32_GOTPC,
  95 +
  96 +/* Reference to a symbol through the GOT. The linker will allocate an
  97 +entry for symbol in the GOT and insert the offset of this entry as
  98 +the relocation value. addend must be zero. As usual, 'S' means
  99 +signed, 'W' means word-aligned, etc.  */
 100 +  BFD_RELOC_AVR32_GOTCALL,
 101 +  BFD_RELOC_AVR32_LDA_GOT,
 102 +  BFD_RELOC_AVR32_GOT21S,
 103 +  BFD_RELOC_AVR32_GOT18SW,
 104 +  BFD_RELOC_AVR32_GOT16S,
 105 +
 106 +/* 32-bit constant pool entry. I don't think 8- and 16-bit entries make
 107 +a whole lot of sense.  */
 108 +  BFD_RELOC_AVR32_32_CPENT,
 109 +
 110 +/* Constant pool references. Some of these relocations are signed,
 111 +others are unsigned. It doesn't really matter, since the constant
 112 +pool always comes after the code that references it.  */
 113 +  BFD_RELOC_AVR32_CPCALL,
 114 +  BFD_RELOC_AVR32_16_CP,
 115 +  BFD_RELOC_AVR32_9W_CP,
 116 +
 117 +/* sym must be the absolute symbol. The addend specifies the alignment
 118 +order, e.g. if addend is 2, the linker must add padding so that the
 119 +next address is aligned to a 4-byte boundary.  */
 120 +  BFD_RELOC_AVR32_ALIGN,
 121 +
 122 +/* Code relocations that will never make it to the output file.  */
 123 +  BFD_RELOC_AVR32_14UW,
 124 +  BFD_RELOC_AVR32_10UW,
 125 +  BFD_RELOC_AVR32_10SW,
 126 +  BFD_RELOC_AVR32_STHH_W,
 127 +  BFD_RELOC_AVR32_7UW,
 128 +  BFD_RELOC_AVR32_6S,
 129 +  BFD_RELOC_AVR32_6UW,
 130 +  BFD_RELOC_AVR32_4UH,
 131 +  BFD_RELOC_AVR32_3U,
 132 +
 133  /* Direct 12 bit.  */
 134    BFD_RELOC_390_12,
 135
 136 --- a/bfd/config.bfd
 137 +++ b/bfd/config.bfd
 138 @@ -336,6 +336,10 @@ case "${targ}" in
 139      targ_underscore=yes
 140      ;;
 141
 142 +  avr32-*-*)
 143 +    targ_defvec=bfd_elf32_avr32_vec
 144 +    ;;
 145 +
 146    c30-*-*aout* | tic30-*-*aout*)
 147      targ_defvec=tic30_aout_vec
 148      ;;
 149 --- a/bfd/configure
 150 +++ b/bfd/configure
 151 @@ -19639,6 +19639,7 @@ do
 152      bfd_efi_rtdrv_ia64_vec)    tb="$tb efi-rtdrv-ia64.lo pepigen.lo cofflink.lo"; target_size=64 ;;
 153      bfd_elf32_am33lin_vec)     tb="$tb elf32-am33lin.lo elf32.lo $elf" ;;
 154      bfd_elf32_avr_vec)         tb="$tb elf32-avr.lo elf32.lo $elf" ;;
 155 +    bfd_elf32_avr32_vec)       tb="$tb elf32-avr32.lo elf32.lo $elf" ;;
 156      bfd_elf32_bfin_vec)                tb="$tb elf32-bfin.lo elf32.lo $elf" ;;
 157      bfd_elf32_bfinfdpic_vec)   tb="$tb elf32-bfin.lo elf32.lo $elf" ;;
 158      bfd_elf32_big_generic_vec)         tb="$tb elf32-gen.lo elf32.lo $elf" ;;
 159 --- a/bfd/configure.in
 160 +++ b/bfd/configure.in
 161 @@ -632,6 +632,7 @@ do
 162      bfd_efi_rtdrv_ia64_vec)    tb="$tb efi-rtdrv-ia64.lo pepigen.lo cofflink.lo"; target_size=64 ;;
 163      bfd_elf32_am33lin_vec)     tb="$tb elf32-am33lin.lo elf32.lo $elf" ;;
 164      bfd_elf32_avr_vec)         tb="$tb elf32-avr.lo elf32.lo $elf" ;;
 165 +    bfd_elf32_avr32_vec)       tb="$tb elf32-avr32.lo elf32.lo $elf" ;;
 166      bfd_elf32_bfin_vec)                tb="$tb elf32-bfin.lo elf32.lo $elf" ;;
 167      bfd_elf32_bfinfdpic_vec)   tb="$tb elf32-bfin.lo elf32.lo $elf" ;;
 168      bfd_elf32_big_generic_vec)         tb="$tb elf32-gen.lo elf32.lo $elf" ;;
 169 --- /dev/null
 170 +++ b/bfd/cpu-avr32.c
 171 @@ -0,0 +1,52 @@
 172 +/* BFD library support routines for AVR32.
 173 +   Copyright 2003,2004,2005,2006,2007,2008,2009 Atmel Corporation.
 174 +
 175 +   Written by Haavard Skinnemoen, Atmel Norway, <hskinnemoen@atmel.com>
 176 +
 177 +   This is part of BFD, the Binary File Descriptor library.
 178 +
 179 +   This program is free software; you can redistribute it and/or modify
 180 +   it under the terms of the GNU General Public License as published by
 181 +   the Free Software Foundation; either version 2 of the License, or
 182 +   (at your option) any later version.
 183 +
 184 +   This program is distributed in the hope that it will be useful,
 185 +   but WITHOUT ANY WARRANTY; without even the implied warranty of
 186 +   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 187 +   GNU General Public License for more details.
 188 +
 189 +   You should have received a copy of the GNU General Public License
 190 +   along with this program; if not, write to the Free Software
 191 +   Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
 192 +
 193 +#include "bfd.h"
 194 +#include "sysdep.h"
 195 +#include "libbfd.h"
 196 +
 197 +#define N(machine, print, default, next)                       \
 198 +  {                                                            \
 199 +    32,                                /* 32 bits in a word */         \
 200 +    32,                                /* 32 bits in an address */     \
 201 +    8,                         /* 8 bits in a byte */          \
 202 +    bfd_arch_avr32,            /* architecture */              \
 203 +    machine,                   /* machine */                   \
 204 +    "avr32",                   /* arch name */                 \
 205 +    print,                     /* printable name */            \
 206 +    1,                         /* section align power */       \
 207 +    default,                   /* the default machine? */      \
 208 +    bfd_default_compatible,                                    \
 209 +    bfd_default_scan,                                          \
 210 +    next,                                                      \
 211 +  }
 212 +
 213 +static const bfd_arch_info_type cpu_info[] =
 214 +{
 215 +  N(bfd_mach_avr32_ap, "avr32:ap", FALSE, &cpu_info[1]),
 216 +  N(bfd_mach_avr32_uc, "avr32:uc", FALSE, &cpu_info[2]),
 217 +  N(bfd_mach_avr32_ucr1, "avr32:ucr1", FALSE, &cpu_info[3]),
 218 +  N(bfd_mach_avr32_ucr2, "avr32:ucr2", FALSE, &cpu_info[4]),
 219 +  N(bfd_mach_avr32_ucr3, "avr32:ucr3", FALSE, NULL),
 220 +};
 221 +
 222 +const bfd_arch_info_type bfd_avr32_arch =
 223 +  N(bfd_mach_avr32_ap, "avr32", TRUE, &cpu_info[0]);
 224 --- /dev/null
 225 +++ b/bfd/elf32-avr32.c
 226 @@ -0,0 +1,3915 @@
 227 +/* AVR32-specific support for 32-bit ELF.
 228 +   Copyright 2003,2004,2005,2006,2007,2008,2009 Atmel Corporation.
 229 +
 230 +   Written by Haavard Skinnemoen, Atmel Norway, <hskinnemoen@atmel.com>
 231 +
 232 +   This file is part of BFD, the Binary File Descriptor library.
 233 +
 234 +   This program is free software; you can redistribute it and/or modify
 235 +   it under the terms of the GNU General Public License as published by
 236 +   the Free Software Foundation; either version 2 of the License, or
 237 +   (at your option) any later version.
 238 +
 239 +   This program is distributed in the hope that it will be useful,
 240 +   but WITHOUT ANY WARRANTY; without even the implied warranty of
 241 +   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 242 +   GNU General Public License for more details.
 243 +
 244 +   You should have received a copy of the GNU General Public License
 245 +   along with this program; if not, write to the Free Software
 246 +   Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
 247 +
 248 +#include "bfd.h"
 249 +#include "sysdep.h"
 250 +#include "bfdlink.h"
 251 +#include "libbfd.h"
 252 +#include "elf-bfd.h"
 253 +#include "elf/avr32.h"
 254 +#include "elf32-avr32.h"
 255 +
 256 +#define xDEBUG
 257 +#define xRELAX_DEBUG
 258 +
 259 +#ifdef DEBUG
 260 +# define pr_debug(fmt, args...) fprintf(stderr, fmt, ##args)
 261 +#else
 262 +# define pr_debug(fmt, args...) do { } while (0)
 263 +#endif
 264 +
 265 +#ifdef RELAX_DEBUG
 266 +# define RDBG(fmt, args...) fprintf(stderr, fmt, ##args)
 267 +#else
 268 +# define RDBG(fmt, args...) do { } while (0)
 269 +#endif
 270 +
 271 +/* When things go wrong, we want it to blow up, damnit! */
 272 +#undef BFD_ASSERT
 273 +#undef abort
 274 +#define BFD_ASSERT(expr)                                       \
 275 +  do                                                           \
 276 +    {                                                          \
 277 +      if (!(expr))                                             \
 278 +       {                                                       \
 279 +         bfd_assert(__FILE__, __LINE__);                       \
 280 +         abort();                                              \
 281 +       }                                                       \
 282 +    }                                                          \
 283 +  while (0)
 284 +
 285 +/* The name of the dynamic interpreter. This is put in the .interp section. */
 286 +#define ELF_DYNAMIC_INTERPRETER                "/lib/ld.so.1"
 287 +
 288 +#define AVR32_GOT_HEADER_SIZE          8
 289 +#define AVR32_FUNCTION_STUB_SIZE       8
 290 +
 291 +#define ELF_R_INFO(x, y) ELF32_R_INFO(x, y)
 292 +#define ELF_R_TYPE(x) ELF32_R_TYPE(x)
 293 +#define ELF_R_SYM(x) ELF32_R_SYM(x)
 294 +
 295 +#define NOP_OPCODE 0xd703
 296 +
 297 +
 298 +/* Mapping between BFD relocations and ELF relocations */
 299 +
 300 +static reloc_howto_type *
 301 +bfd_elf32_bfd_reloc_type_lookup(bfd *abfd, bfd_reloc_code_real_type code);
 302 +
 303 +static reloc_howto_type *
 304 +bfd_elf32_bfd_reloc_name_lookup(bfd *abfd, const char *r_name);
 305 +
 306 +static void
 307 +avr32_info_to_howto (bfd *abfd, arelent *cache_ptr, Elf_Internal_Rela *dst);
 308 +
 309 +/* Generic HOWTO */
 310 +#define GENH(name, align, size, bitsize, pcrel, bitpos, complain, mask)        \
 311 +  HOWTO(name, align, size, bitsize, pcrel, bitpos,                     \
 312 +       complain_overflow_##complain, bfd_elf_generic_reloc, #name,     \
 313 +       FALSE, 0, mask, pcrel)
 314 +
 315 +static reloc_howto_type elf_avr32_howto_table[] = {
 316 +  /*   NAME             ALN SZ BSZ PCREL  BP COMPLAIN  MASK        */
 317 +  GENH(R_AVR32_NONE,     0, 0, 0,  FALSE, 0, dont,     0x00000000),
 318 +
 319 +  GENH(R_AVR32_32,       0, 2, 32, FALSE, 0, dont,     0xffffffff),
 320 +  GENH(R_AVR32_16,       0, 1, 16, FALSE, 0, bitfield, 0x0000ffff),
 321 +  GENH(R_AVR32_8,        0, 0,  8, FALSE, 0, bitfield, 0x000000ff),
 322 +  GENH(R_AVR32_32_PCREL,  0, 2, 32, TRUE,  0, signed,   0xffffffff),
 323 +  GENH(R_AVR32_16_PCREL,  0, 1, 16, TRUE,  0, signed,   0x0000ffff),
 324 +  GENH(R_AVR32_8_PCREL,          0, 0,  8, TRUE,  0, signed,   0x000000ff),
 325 +
 326 +  /* Difference between two symbol (sym2 - sym1).  The reloc encodes
 327 +     the value of sym1.  The field contains the difference before any
 328 +     relaxing is done.  */
 329 +  GENH(R_AVR32_DIFF32,   0, 2, 32, FALSE, 0, dont,     0xffffffff),
 330 +  GENH(R_AVR32_DIFF16,   0, 1, 16, FALSE, 0, signed,   0x0000ffff),
 331 +  GENH(R_AVR32_DIFF8,    0, 0,  8, FALSE, 0, signed,   0x000000ff),
 332 +
 333 +  GENH(R_AVR32_GOT32,    0, 2, 32, FALSE, 0, signed,   0xffffffff),
 334 +  GENH(R_AVR32_GOT16,    0, 1, 16, FALSE, 0, signed,   0x0000ffff),
 335 +  GENH(R_AVR32_GOT8,     0, 0,  8, FALSE, 0, signed,   0x000000ff),
 336 +
 337 +  GENH(R_AVR32_21S,      0, 2, 21, FALSE, 0, signed,   0x1e10ffff),
 338 +  GENH(R_AVR32_16U,      0, 2, 16, FALSE, 0, unsigned, 0x0000ffff),
 339 +  GENH(R_AVR32_16S,      0, 2, 16, FALSE, 0, signed,   0x0000ffff),
 340 +  GENH(R_AVR32_8S,       0, 1,  8, FALSE, 4, signed,   0x00000ff0),
 341 +  GENH(R_AVR32_8S_EXT,   0, 2,  8, FALSE, 0, signed,   0x000000ff),
 342 +
 343 +  GENH(R_AVR32_22H_PCREL, 1, 2, 21, TRUE,  0, signed,  0x1e10ffff),
 344 +  GENH(R_AVR32_18W_PCREL, 2, 2, 16, TRUE,  0, signed,  0x0000ffff),
 345 +  GENH(R_AVR32_16B_PCREL, 0, 2, 16, TRUE,  0, signed,  0x0000ffff),
 346 +  GENH(R_AVR32_16N_PCREL, 0, 2, 16, TRUE,  0, signed,  0x0000ffff),
 347 +  GENH(R_AVR32_14UW_PCREL, 2, 2, 12, TRUE, 0, unsigned, 0x0000f0ff),
 348 +  GENH(R_AVR32_11H_PCREL, 1, 1, 10, TRUE,  4, signed,  0x00000ff3),
 349 +  GENH(R_AVR32_10UW_PCREL, 2, 2, 8, TRUE,  0, unsigned, 0x000000ff),
 350 +  GENH(R_AVR32_9H_PCREL,  1, 1,  8, TRUE,  4, signed,  0x00000ff0),
 351 +  GENH(R_AVR32_9UW_PCREL, 2, 1,  7, TRUE,  4, unsigned,        0x000007f0),
 352 +
 353 +  GENH(R_AVR32_HI16,    16, 2, 16, FALSE, 0, dont,     0x0000ffff),
 354 +  GENH(R_AVR32_LO16,     0, 2, 16, FALSE, 0, dont,     0x0000ffff),
 355 +
 356 +  GENH(R_AVR32_GOTPC,    0, 2, 32, FALSE, 0, dont,     0xffffffff),
 357 +  GENH(R_AVR32_GOTCALL,   2, 2, 21, FALSE, 0, signed,  0x1e10ffff),
 358 +  GENH(R_AVR32_LDA_GOT,          2, 2, 21, FALSE, 0, signed,   0x1e10ffff),
 359 +  GENH(R_AVR32_GOT21S,   0, 2, 21, FALSE, 0, signed,   0x1e10ffff),
 360 +  GENH(R_AVR32_GOT18SW,          2, 2, 16, FALSE, 0, signed,   0x0000ffff),
 361 +  GENH(R_AVR32_GOT16S,   0, 2, 16, FALSE, 0, signed,   0x0000ffff),
 362 +  GENH(R_AVR32_GOT7UW,   2, 1,  5, FALSE, 4, unsigned, 0x000001f0),
 363 +
 364 +  GENH(R_AVR32_32_CPENT,  0, 2, 32, FALSE, 0, dont,    0xffffffff),
 365 +  GENH(R_AVR32_CPCALL,   2, 2, 16, TRUE,  0, signed,   0x0000ffff),
 366 +  GENH(R_AVR32_16_CP,    0, 2, 16, TRUE,  0, signed,   0x0000ffff),
 367 +  GENH(R_AVR32_9W_CP,    2, 1,  7, TRUE,  4, unsigned, 0x000007f0),
 368 +
 369 +  GENH(R_AVR32_RELATIVE,  0, 2, 32, FALSE, 0, signed,  0xffffffff),
 370 +  GENH(R_AVR32_GLOB_DAT,  0, 2, 32, FALSE, 0, dont,    0xffffffff),
 371 +  GENH(R_AVR32_JMP_SLOT,  0, 2, 32, FALSE, 0, dont,    0xffffffff),
 372 +
 373 +  GENH(R_AVR32_ALIGN,    0, 1, 0,  FALSE, 0, unsigned, 0x00000000),
 374 +
 375 +  GENH(R_AVR32_15S,      2, 2, 15, FALSE, 0, signed,   0x00007fff),
 376 +};
 377 +
 378 +struct elf_reloc_map
 379 +{
 380 +  bfd_reloc_code_real_type bfd_reloc_val;
 381 +  unsigned char elf_reloc_val;
 382 +};
 383 +
 384 +static const struct elf_reloc_map avr32_reloc_map[] =
 385 +{
 386 +  { BFD_RELOC_NONE,                    R_AVR32_NONE },
 387 +
 388 +  { BFD_RELOC_32,                      R_AVR32_32 },
 389 +  { BFD_RELOC_16,                      R_AVR32_16 },
 390 +  { BFD_RELOC_8,                       R_AVR32_8 },
 391 +  { BFD_RELOC_32_PCREL,                        R_AVR32_32_PCREL },
 392 +  { BFD_RELOC_16_PCREL,                        R_AVR32_16_PCREL },
 393 +  { BFD_RELOC_8_PCREL,                 R_AVR32_8_PCREL },
 394 +  { BFD_RELOC_AVR32_DIFF32,            R_AVR32_DIFF32 },
 395 +  { BFD_RELOC_AVR32_DIFF16,            R_AVR32_DIFF16 },
 396 +  { BFD_RELOC_AVR32_DIFF8,             R_AVR32_DIFF8 },
 397 +  { BFD_RELOC_AVR32_GOT32,             R_AVR32_GOT32 },
 398 +  { BFD_RELOC_AVR32_GOT16,             R_AVR32_GOT16 },
 399 +  { BFD_RELOC_AVR32_GOT8,              R_AVR32_GOT8 },
 400 +
 401 +  { BFD_RELOC_AVR32_21S,               R_AVR32_21S },
 402 +  { BFD_RELOC_AVR32_16U,               R_AVR32_16U },
 403 +  { BFD_RELOC_AVR32_16S,               R_AVR32_16S },
 404 +  { BFD_RELOC_AVR32_SUB5,              R_AVR32_16S },
 405 +  { BFD_RELOC_AVR32_8S_EXT,            R_AVR32_8S_EXT },
 406 +  { BFD_RELOC_AVR32_8S,                        R_AVR32_8S },
 407 +
 408 +  { BFD_RELOC_AVR32_22H_PCREL,         R_AVR32_22H_PCREL },
 409 +  { BFD_RELOC_AVR32_18W_PCREL,         R_AVR32_18W_PCREL },
 410 +  { BFD_RELOC_AVR32_16B_PCREL,         R_AVR32_16B_PCREL },
 411 +  { BFD_RELOC_AVR32_16N_PCREL,         R_AVR32_16N_PCREL },
 412 +  { BFD_RELOC_AVR32_11H_PCREL,         R_AVR32_11H_PCREL },
 413 +  { BFD_RELOC_AVR32_10UW_PCREL,                R_AVR32_10UW_PCREL },
 414 +  { BFD_RELOC_AVR32_9H_PCREL,          R_AVR32_9H_PCREL },
 415 +  { BFD_RELOC_AVR32_9UW_PCREL,         R_AVR32_9UW_PCREL },
 416 +
 417 +  { BFD_RELOC_HI16,                    R_AVR32_HI16 },
 418 +  { BFD_RELOC_LO16,                    R_AVR32_LO16 },
 419 +
 420 +  { BFD_RELOC_AVR32_GOTPC,             R_AVR32_GOTPC },
 421 +  { BFD_RELOC_AVR32_GOTCALL,           R_AVR32_GOTCALL },
 422 +  { BFD_RELOC_AVR32_LDA_GOT,           R_AVR32_LDA_GOT },
 423 +  { BFD_RELOC_AVR32_GOT21S,            R_AVR32_GOT21S },
 424 +  { BFD_RELOC_AVR32_GOT18SW,           R_AVR32_GOT18SW },
 425 +  { BFD_RELOC_AVR32_GOT16S,            R_AVR32_GOT16S },
 426 +  /* GOT7UW should never be generated by the assembler */
 427 +
 428 +  { BFD_RELOC_AVR32_32_CPENT,          R_AVR32_32_CPENT },
 429 +  { BFD_RELOC_AVR32_CPCALL,            R_AVR32_CPCALL },
 430 +  { BFD_RELOC_AVR32_16_CP,             R_AVR32_16_CP },
 431 +  { BFD_RELOC_AVR32_9W_CP,             R_AVR32_9W_CP },
 432 +
 433 +  { BFD_RELOC_AVR32_ALIGN,             R_AVR32_ALIGN },
 434 +
 435 +  { BFD_RELOC_AVR32_15S,               R_AVR32_15S },
 436 +};
 437 +
 438 +static reloc_howto_type *
 439 +bfd_elf32_bfd_reloc_type_lookup (bfd *abfd ATTRIBUTE_UNUSED,
 440 +                                bfd_reloc_code_real_type code)
 441 +{
 442 +  unsigned int i;
 443 +
 444 +  for (i = 0; i < sizeof(avr32_reloc_map) / sizeof(struct elf_reloc_map); i++)
 445 +    {
 446 +      if (avr32_reloc_map[i].bfd_reloc_val == code)
 447 +       return &elf_avr32_howto_table[avr32_reloc_map[i].elf_reloc_val];
 448 +    }
 449 +
 450 +  return NULL;
 451 +}
 452 +
 453 +static reloc_howto_type *
 454 +bfd_elf32_bfd_reloc_name_lookup (bfd *abfd ATTRIBUTE_UNUSED,
 455 +                 const char *r_name)
 456 +{
 457 +  unsigned int i;
 458 +
 459 +  for (i = 0;
 460 +       i < sizeof (elf_avr32_howto_table) / sizeof (elf_avr32_howto_table[0]);
 461 +       i++)
 462 +    if (elf_avr32_howto_table[i].name != NULL
 463 +    && strcasecmp (elf_avr32_howto_table[i].name, r_name) == 0)
 464 +      return &elf_avr32_howto_table[i];
 465 +
 466 +  return NULL;
 467 +}
 468 +
 469 +/* Set the howto pointer for an AVR32 ELF reloc.  */
 470 +static void
 471 +avr32_info_to_howto (bfd *abfd ATTRIBUTE_UNUSED,
 472 +                    arelent *cache_ptr,
 473 +                    Elf_Internal_Rela *dst)
 474 +{
 475 +  unsigned int r_type;
 476 +
 477 +  r_type = ELF32_R_TYPE (dst->r_info);
 478 +  BFD_ASSERT (r_type < (unsigned int) R_AVR32_max);
 479 +  cache_ptr->howto = &elf_avr32_howto_table[r_type];
 480 +}
 481 +
 482 +
 483 +/* AVR32 ELF linker hash table and associated hash entries. */
 484 +
 485 +static struct bfd_hash_entry *
 486 +avr32_elf_link_hash_newfunc(struct bfd_hash_entry *entry,
 487 +                           struct bfd_hash_table *table,
 488 +                           const char *string);
 489 +static void
 490 +avr32_elf_copy_indirect_symbol(struct bfd_link_info *info,
 491 +                              struct elf_link_hash_entry *dir,
 492 +                              struct elf_link_hash_entry *ind);
 493 +static struct bfd_link_hash_table *
 494 +avr32_elf_link_hash_table_create(bfd *abfd);
 495 +
 496 +/*
 497 +  Try to limit memory usage to something reasonable when sorting the
 498 +  GOT.  If just a couple of entries end up getting more references
 499 +  than this, it won't affect performance at all, but if there are many
 500 +  of them, we could end up with the wrong symbols being assigned the
 501 +  first GOT entries.
 502 +*/
 503 +#define MAX_NR_GOT_HOLES       2048
 504 +
 505 +/*
 506 +  AVR32 GOT entry.  We need to keep track of refcounts and offsets
 507 +  simultaneously, since we need the offsets during relaxation, and we
 508 +  also want to be able to drop GOT entries during relaxation. In
 509 +  addition to this, we want to keep the list of GOT entries sorted so
 510 +  that we can keep the most-used entries at the lowest offsets.
 511 +*/
 512 +struct got_entry
 513 +{
 514 +  struct got_entry *next;
 515 +  struct got_entry **pprev;
 516 +  int refcount;
 517 +  bfd_signed_vma offset;
 518 +};
 519 +
 520 +struct elf_avr32_link_hash_entry
 521 +{
 522 +  struct elf_link_hash_entry root;
 523 +
 524 +  /* Number of runtime relocations against this symbol.  */
 525 +  unsigned int possibly_dynamic_relocs;
 526 +
 527 +  /* If there are anything but R_AVR32_GOT18 relocations against this
 528 +     symbol, it means that someone may be taking the address of the
 529 +     function, and we should therefore not create a stub.  */
 530 +  bfd_boolean no_fn_stub;
 531 +
 532 +  /* If there is a R_AVR32_32 relocation in a read-only section
 533 +     against this symbol, we could be in trouble. If we're linking a
 534 +     shared library or this symbol is defined in one, it means we must
 535 +     emit a run-time reloc for it and that's not allowed in read-only
 536 +     sections.  */
 537 +  asection *readonly_reloc_sec;
 538 +  bfd_vma readonly_reloc_offset;
 539 +
 540 +  /* Record which frag (if any) contains the symbol.  This is used
 541 +     during relaxation in order to avoid having to update all symbols
 542 +     whenever we move something.  For local symbols, this information
 543 +     is in the local_sym_frag member of struct elf_obj_tdata.  */
 544 +  struct fragment *sym_frag;
 545 +};
 546 +#define avr32_elf_hash_entry(ent) ((struct elf_avr32_link_hash_entry *)(ent))
 547 +
 548 +struct elf_avr32_link_hash_table
 549 +{
 550 +  struct elf_link_hash_table root;
 551 +
 552 +  /* Shortcuts to get to dynamic linker sections.  */
 553 +  asection *sgot;
 554 +  asection *srelgot;
 555 +  asection *sstub;
 556 +
 557 +  /* We use a variation of Pigeonhole Sort to sort the GOT.  After the
 558 +     initial refcounts have been determined, we initialize
 559 +     nr_got_holes to the highest refcount ever seen and allocate an
 560 +     array of nr_got_holes entries for got_hole.  Each GOT entry is
 561 +     then stored in this array at the index given by its refcount.
 562 +
 563 +     When a GOT entry has its refcount decremented during relaxation,
 564 +     it is moved to a lower index in the got_hole array.
 565 +   */
 566 +  struct got_entry **got_hole;
 567 +  int nr_got_holes;
 568 +
 569 +  /* Dynamic relocations to local symbols.  Only used when linking a
 570 +     shared library and -Bsymbolic is not given.  */
 571 +  unsigned int local_dynamic_relocs;
 572 +
 573 +  bfd_boolean relocations_analyzed;
 574 +  bfd_boolean symbols_adjusted;
 575 +  bfd_boolean repeat_pass;
 576 +  bfd_boolean direct_data_refs;
 577 +  unsigned int relax_iteration;
 578 +  unsigned int relax_pass;
 579 +};
 580 +#define avr32_elf_hash_table(p)                                \
 581 +  ((struct elf_avr32_link_hash_table *)((p)->hash))
 582 +
 583 +static struct bfd_hash_entry *
 584 +avr32_elf_link_hash_newfunc(struct bfd_hash_entry *entry,
 585 +                           struct bfd_hash_table *table,
 586 +                           const char *string)
 587 +{
 588 +  struct elf_avr32_link_hash_entry *ret = avr32_elf_hash_entry(entry);
 589 +
 590 +  /* Allocate the structure if it hasn't already been allocated by a
 591 +     subclass */
 592 +  if (ret == NULL)
 593 +    ret = (struct elf_avr32_link_hash_entry *)
 594 +      bfd_hash_allocate(table, sizeof(struct elf_avr32_link_hash_entry));
 595 +
 596 +  if (ret == NULL)
 597 +    return NULL;
 598 +
 599 +  memset(ret, 0, sizeof(struct elf_avr32_link_hash_entry));
 600 +
 601 +  /* Give the superclass a chance */
 602 +  ret = (struct elf_avr32_link_hash_entry *)
 603 +    _bfd_elf_link_hash_newfunc((struct bfd_hash_entry *)ret, table, string);
 604 +
 605 +  return (struct bfd_hash_entry *)ret;
 606 +}
 607 +
 608 +/* Copy data from an indirect symbol to its direct symbol, hiding the
 609 +   old indirect symbol.  Process additional relocation information.
 610 +   Also called for weakdefs, in which case we just let
 611 +   _bfd_elf_link_hash_copy_indirect copy the flags for us.  */
 612 +
 613 +static void
 614 +avr32_elf_copy_indirect_symbol(struct bfd_link_info *info,
 615 +                              struct elf_link_hash_entry *dir,
 616 +                              struct elf_link_hash_entry *ind)
 617 +{
 618 +  struct elf_avr32_link_hash_entry *edir, *eind;
 619 +
 620 +  _bfd_elf_link_hash_copy_indirect (info, dir, ind);
 621 +
 622 +  if (ind->root.type != bfd_link_hash_indirect)
 623 +    return;
 624 +
 625 +  edir = (struct elf_avr32_link_hash_entry *)dir;
 626 +  eind = (struct elf_avr32_link_hash_entry *)ind;
 627 +
 628 +  edir->possibly_dynamic_relocs += eind->possibly_dynamic_relocs;
 629 +  edir->no_fn_stub = edir->no_fn_stub || eind->no_fn_stub;
 630 +}
 631 +
 632 +static struct bfd_link_hash_table *
 633 +avr32_elf_link_hash_table_create(bfd *abfd)
 634 +{
 635 +  struct elf_avr32_link_hash_table *ret;
 636 +
 637 +  ret = bfd_zmalloc(sizeof(*ret));
 638 +  if (ret == NULL)
 639 +    return NULL;
 640 +
 641 +  if (! _bfd_elf_link_hash_table_init(&ret->root, abfd,
 642 +                                     avr32_elf_link_hash_newfunc,
 643 +                      sizeof (struct elf_avr32_link_hash_entry)))
 644 +    {
 645 +      free(ret);
 646 +      return NULL;
 647 +    }
 648 +
 649 +  /* Prevent the BFD core from creating bogus got_entry pointers */
 650 +  ret->root.init_got_refcount.glist = NULL;
 651 +  ret->root.init_plt_refcount.glist = NULL;
 652 +  ret->root.init_got_offset.glist = NULL;
 653 +  ret->root.init_plt_offset.glist = NULL;
 654 +
 655 +  return &ret->root.root;
 656 +}
 657 +
 658 +
 659 +/* Initial analysis and creation of dynamic sections and symbols */
 660 +
 661 +static asection *
 662 +create_dynamic_section(bfd *dynobj, const char *name, flagword flags,
 663 +                      unsigned int align_power);
 664 +static struct elf_link_hash_entry *
 665 +create_dynamic_symbol(bfd *dynobj, struct bfd_link_info *info,
 666 +                     const char *name, asection *sec,
 667 +                     bfd_vma offset);
 668 +static bfd_boolean
 669 +avr32_elf_create_got_section (bfd *dynobj, struct bfd_link_info *info);
 670 +static bfd_boolean
 671 +avr32_elf_create_dynamic_sections (bfd *dynobj, struct bfd_link_info *info);
 672 +static bfd_boolean
 673 +avr32_check_relocs (bfd *abfd, struct bfd_link_info *info, asection *sec,
 674 +                   const Elf_Internal_Rela *relocs);
 675 +static bfd_boolean
 676 +avr32_elf_adjust_dynamic_symbol(struct bfd_link_info *info,
 677 +                               struct elf_link_hash_entry *h);
 678 +
 679 +static asection *
 680 +create_dynamic_section(bfd *dynobj, const char *name, flagword flags,
 681 +                      unsigned int align_power)
 682 +{
 683 +  asection *sec;
 684 +
 685 +  sec = bfd_make_section(dynobj, name);
 686 +  if (!sec
 687 +      || !bfd_set_section_flags(dynobj, sec, flags)
 688 +      || !bfd_set_section_alignment(dynobj, sec, align_power))
 689 +    return NULL;
 690 +
 691 +  return sec;
 692 +}
 693 +
 694 +static struct elf_link_hash_entry *
 695 +create_dynamic_symbol(bfd *dynobj, struct bfd_link_info *info,
 696 +                     const char *name, asection *sec,
 697 +                     bfd_vma offset)
 698 +{
 699 +  struct bfd_link_hash_entry *bh = NULL;
 700 +  struct elf_link_hash_entry *h;
 701 +  const struct elf_backend_data *bed = get_elf_backend_data (dynobj);
 702 +
 703 +  if (!(_bfd_generic_link_add_one_symbol
 704 +       (info, dynobj, name, BSF_GLOBAL, sec, offset, NULL, FALSE,
 705 +        bed->collect, &bh)))
 706 +    return NULL;
 707 +
 708 +  h = (struct elf_link_hash_entry *)bh;
 709 +  h->def_regular = 1;
 710 +  h->type = STT_OBJECT;
 711 +  h->other = STV_HIDDEN;
 712 +
 713 +  return h;
 714 +}
 715 +
 716 +static bfd_boolean
 717 +avr32_elf_create_got_section (bfd *dynobj, struct bfd_link_info *info)
 718 +{
 719 +  struct elf_avr32_link_hash_table *htab;
 720 +  flagword flags;
 721 +  const struct elf_backend_data *bed = get_elf_backend_data (dynobj);
 722 +
 723 +  htab = avr32_elf_hash_table(info);
 724 +  flags = bed->dynamic_sec_flags;
 725 +
 726 +  if (htab->sgot)
 727 +    return TRUE;
 728 +
 729 +  htab->sgot = create_dynamic_section(dynobj, ".got", flags, 2);
 730 +  if (!htab->srelgot)
 731 +    htab->srelgot = create_dynamic_section(dynobj, ".rela.got",
 732 +                                          flags | SEC_READONLY, 2);
 733 +
 734 +  if (!htab->sgot || !htab->srelgot)
 735 +    return FALSE;
 736 +
 737 +  htab->root.hgot = create_dynamic_symbol(dynobj, info, "_GLOBAL_OFFSET_TABLE_",
 738 +                                         htab->sgot, 0);
 739 +  if (!htab->root.hgot)
 740 +    return FALSE;
 741 +
 742 +  /* Make room for the GOT header */
 743 +  htab->sgot->size += bed->got_header_size;
 744 +
 745 +  return TRUE;
 746 +}
 747 +
 748 +/* (1) Create all dynamic (i.e. linker generated) sections that we may
 749 +   need during the link */
 750 +
 751 +static bfd_boolean
 752 +avr32_elf_create_dynamic_sections (bfd *dynobj, struct bfd_link_info *info)
 753 +{
 754 +  struct elf_avr32_link_hash_table *htab;
 755 +  flagword flags;
 756 +  const struct elf_backend_data *bed = get_elf_backend_data (dynobj);
 757 +
 758 +  pr_debug("(1) create dynamic sections\n");
 759 +
 760 +  htab = avr32_elf_hash_table(info);
 761 +  flags = bed->dynamic_sec_flags;
 762 +
 763 +  if (!avr32_elf_create_got_section (dynobj, info))
 764 +    return FALSE;
 765 +
 766 +  if (!htab->sstub)
 767 +    htab->sstub = create_dynamic_section(dynobj, ".stub",
 768 +                                        flags | SEC_READONLY | SEC_CODE, 2);
 769 +
 770 +  if (!htab->sstub)
 771 +    return FALSE;
 772 +
 773 +  return TRUE;
 774 +}
 775 +
 776 +/* (2) Go through all the relocs and count any potential GOT- or
 777 +   PLT-references to each symbol */
 778 +
 779 +static bfd_boolean
 780 +avr32_check_relocs (bfd *abfd, struct bfd_link_info *info, asection *sec,
 781 +                   const Elf_Internal_Rela *relocs)
 782 +{
 783 +  Elf_Internal_Shdr *symtab_hdr;
 784 +  struct elf_avr32_link_hash_table *htab;
 785 +  struct elf_link_hash_entry **sym_hashes;
 786 +  const Elf_Internal_Rela *rel, *rel_end;
 787 +  struct got_entry **local_got_ents;
 788 +  struct got_entry *got;
 789 +  const struct elf_backend_data *bed = get_elf_backend_data (abfd);
 790 +  asection *sgot;
 791 +  bfd *dynobj;
 792 +
 793 +  pr_debug("(2) check relocs for %s:<%s> (size 0x%lx)\n",
 794 +          abfd->filename, sec->name, sec->size);
 795 +
 796 +  if (info->relocatable)
 797 +    return TRUE;
 798 +
 799 +  dynobj = elf_hash_table(info)->dynobj;
 800 +  symtab_hdr = &elf_tdata(abfd)->symtab_hdr;
 801 +  sym_hashes = elf_sym_hashes(abfd);
 802 +  htab = avr32_elf_hash_table(info);
 803 +  local_got_ents = elf_local_got_ents(abfd);
 804 +  sgot = htab->sgot;
 805 +
 806 +  rel_end = relocs + sec->reloc_count;
 807 +  for (rel = relocs; rel < rel_end; rel++)
 808 +    {
 809 +      unsigned long r_symndx, r_type;
 810 +      struct elf_avr32_link_hash_entry *h;
 811 +
 812 +      r_symndx = ELF32_R_SYM(rel->r_info);
 813 +      r_type = ELF32_R_TYPE(rel->r_info);
 814 +
 815 +      /* Local symbols use local_got_ents, while others store the same
 816 +        information in the hash entry */
 817 +      if (r_symndx < symtab_hdr->sh_info)
 818 +       {
 819 +         pr_debug("  (2a) processing local symbol %lu\n", r_symndx);
 820 +         h = NULL;
 821 +       }
 822 +      else
 823 +       {
 824 +         h = (struct elf_avr32_link_hash_entry *)
 825 +           sym_hashes[r_symndx - symtab_hdr->sh_info];
 826 +         while (h->root.type == bfd_link_hash_indirect
 827 +                || h->root.type == bfd_link_hash_warning)
 828 +           h = (struct elf_avr32_link_hash_entry *)h->root.root.u.i.link;
 829 +         pr_debug("  (2a) processing symbol %s\n", h->root.root.root.string);
 830 +       }
 831 +
 832 +      /* Some relocs require special sections to be created.  */
 833 +      switch (r_type)
 834 +       {
 835 +       case R_AVR32_GOT32:
 836 +       case R_AVR32_GOT16:
 837 +       case R_AVR32_GOT8:
 838 +       case R_AVR32_GOT21S:
 839 +       case R_AVR32_GOT18SW:
 840 +       case R_AVR32_GOT16S:
 841 +       case R_AVR32_GOT7UW:
 842 +       case R_AVR32_LDA_GOT:
 843 +       case R_AVR32_GOTCALL:
 844 +         if (rel->r_addend)
 845 +           {
 846 +             if (info->callbacks->reloc_dangerous
 847 +                 (info, _("Non-zero addend on GOT-relative relocation"),
 848 +                  abfd, sec, rel->r_offset) == FALSE)
 849 +               return FALSE;
 850 +           }
 851 +         /* fall through */
 852 +       case R_AVR32_GOTPC:
 853 +         if (dynobj == NULL)
 854 +           elf_hash_table(info)->dynobj = dynobj = abfd;
 855 +         if (sgot == NULL && !avr32_elf_create_got_section(dynobj, info))
 856 +           return FALSE;
 857 +         break;
 858 +       case R_AVR32_32:
 859 +         /* We may need to create .rela.dyn later on.  */
 860 +         if (dynobj == NULL
 861 +             && (info->shared || h != NULL)
 862 +             && (sec->flags & SEC_ALLOC))
 863 +           elf_hash_table(info)->dynobj = dynobj = abfd;
 864 +         break;
 865 +       }
 866 +
 867 +      if (h != NULL && r_type != R_AVR32_GOT18SW)
 868 +       h->no_fn_stub = TRUE;
 869 +
 870 +      switch (r_type)
 871 +       {
 872 +       case R_AVR32_GOT32:
 873 +       case R_AVR32_GOT16:
 874 +       case R_AVR32_GOT8:
 875 +       case R_AVR32_GOT21S:
 876 +       case R_AVR32_GOT18SW:
 877 +       case R_AVR32_GOT16S:
 878 +       case R_AVR32_GOT7UW:
 879 +       case R_AVR32_LDA_GOT:
 880 +       case R_AVR32_GOTCALL:
 881 +         if (h != NULL)
 882 +           {
 883 +             got = h->root.got.glist;
 884 +             if (!got)
 885 +               {
 886 +                 got = bfd_zalloc(abfd, sizeof(struct got_entry));
 887 +                 if (!got)
 888 +                   return FALSE;
 889 +                 h->root.got.glist = got;
 890 +               }
 891 +           }
 892 +         else
 893 +           {
 894 +             if (!local_got_ents)
 895 +               {
 896 +                 bfd_size_type size;
 897 +                 bfd_size_type i;
 898 +                 struct got_entry *tmp_entry;
 899 +
 900 +                 size = symtab_hdr->sh_info;
 901 +                 size *= sizeof(struct got_entry *) + sizeof(struct got_entry);
 902 +                 local_got_ents = bfd_zalloc(abfd, size);
 903 +                 if (!local_got_ents)
 904 +                   return FALSE;
 905 +
 906 +                 elf_local_got_ents(abfd) = local_got_ents;
 907 +
 908 +                 tmp_entry = (struct got_entry *)(local_got_ents
 909 +                                                  + symtab_hdr->sh_info);
 910 +                 for (i = 0; i < symtab_hdr->sh_info; i++)
 911 +                   local_got_ents[i] = &tmp_entry[i];
 912 +               }
 913 +
 914 +             got = local_got_ents[r_symndx];
 915 +           }
 916 +
 917 +         got->refcount++;
 918 +         if (got->refcount > htab->nr_got_holes)
 919 +           htab->nr_got_holes = got->refcount;
 920 +         break;
 921 +
 922 +       case R_AVR32_32:
 923 +         if ((info->shared || h != NULL)
 924 +             && (sec->flags & SEC_ALLOC))
 925 +           {
 926 +             if (htab->srelgot == NULL)
 927 +               {
 928 +                 htab->srelgot = create_dynamic_section(dynobj, ".rela.got",
 929 +                                                        bed->dynamic_sec_flags
 930 +                                                        | SEC_READONLY, 2);
 931 +                 if (htab->srelgot == NULL)
 932 +                   return FALSE;
 933 +               }
 934 +
 935 +             if (sec->flags & SEC_READONLY
 936 +                 && !h->readonly_reloc_sec)
 937 +               {
 938 +                 h->readonly_reloc_sec = sec;
 939 +                 h->readonly_reloc_offset = rel->r_offset;
 940 +               }
 941 +
 942 +             if (h != NULL)
 943 +               {
 944 +                 pr_debug("Non-GOT reference to symbol %s\n",
 945 +                          h->root.root.root.string);
 946 +                 h->possibly_dynamic_relocs++;
 947 +               }
 948 +             else
 949 +               {
 950 +                 pr_debug("Non-GOT reference to local symbol %lu\n",
 951 +                          r_symndx);
 952 +                 htab->local_dynamic_relocs++;
 953 +               }
 954 +           }
 955 +
 956 +         break;
 957 +
 958 +         /* TODO: GNU_VTINHERIT and GNU_VTENTRY */
 959 +       }
 960 +    }
 961 +
 962 +  return TRUE;
 963 +}
 964 +
 965 +/* (3) Adjust a symbol defined by a dynamic object and referenced by a
 966 +   regular object.  The current definition is in some section of the
 967 +   dynamic object, but we're not including those sections.  We have to
 968 +   change the definition to something the rest of the link can
 969 +   understand.  */
 970 +
 971 +static bfd_boolean
 972 +avr32_elf_adjust_dynamic_symbol(struct bfd_link_info *info,
 973 +                               struct elf_link_hash_entry *h)
 974 +{
 975 +  struct elf_avr32_link_hash_table *htab;
 976 +  struct elf_avr32_link_hash_entry *havr;
 977 +  bfd *dynobj;
 978 +
 979 +  pr_debug("(3) adjust dynamic symbol %s\n", h->root.root.string);
 980 +
 981 +  htab = avr32_elf_hash_table(info);
 982 +  havr = (struct elf_avr32_link_hash_entry *)h;
 983 +  dynobj = elf_hash_table(info)->dynobj;
 984 +
 985 +  /* Make sure we know what is going on here.  */
 986 +  BFD_ASSERT (dynobj != NULL
 987 +             && (h->u.weakdef != NULL
 988 +                 || (h->def_dynamic
 989 +                     && h->ref_regular
 990 +                     && !h->def_regular)));
 991 +
 992 +  /* We don't want dynamic relocations in read-only sections. */
 993 +  if (havr->readonly_reloc_sec)
 994 +    {
 995 +      if (info->callbacks->reloc_dangerous
 996 +         (info, _("dynamic relocation in read-only section"),
 997 +          havr->readonly_reloc_sec->owner, havr->readonly_reloc_sec,
 998 +          havr->readonly_reloc_offset) == FALSE)
 999 +       return FALSE;
1000 +    }
1001 +
1002 +  /* If this is a function, create a stub if possible and set the
1003 +     symbol to the stub location.  */
1004 +  if (0 && !havr->no_fn_stub)
1005 +    {
1006 +      if (!h->def_regular)
1007 +       {
1008 +         asection *s = htab->sstub;
1009 +
1010 +         BFD_ASSERT(s != NULL);
1011 +
1012 +         h->root.u.def.section = s;
1013 +         h->root.u.def.value = s->size;
1014 +         h->plt.offset = s->size;
1015 +         s->size += AVR32_FUNCTION_STUB_SIZE;
1016 +
1017 +         return TRUE;
1018 +       }
1019 +    }
1020 +  else if (h->type == STT_FUNC)
1021 +    {
1022 +      /* This will set the entry for this symbol in the GOT to 0, and
1023 +        the dynamic linker will take care of this. */
1024 +      h->root.u.def.value = 0;
1025 +      return TRUE;
1026 +    }
1027 +
1028 +  /* If this is a weak symbol, and there is a real definition, the
1029 +     processor independent code will have arranged for us to see the
1030 +     real definition first, and we can just use the same value.  */
1031 +  if (h->u.weakdef != NULL)
1032 +    {
1033 +      BFD_ASSERT(h->u.weakdef->root.type == bfd_link_hash_defined
1034 +                || h->u.weakdef->root.type == bfd_link_hash_defweak);
1035 +      h->root.u.def.section = h->u.weakdef->root.u.def.section;
1036 +      h->root.u.def.value = h->u.weakdef->root.u.def.value;
1037 +      return TRUE;
1038 +    }
1039 +
1040 +  /* This is a reference to a symbol defined by a dynamic object which
1041 +     is not a function.  */
1042 +
1043 +  return TRUE;
1044 +}
1045 +
1046 +
1047 +/* Garbage-collection of unused sections */
1048 +
1049 +static asection *
1050 +avr32_elf_gc_mark_hook(asection *sec,
1051 +                      struct bfd_link_info *info ATTRIBUTE_UNUSED,
1052 +                      Elf_Internal_Rela *rel,
1053 +                      struct elf_link_hash_entry *h,
1054 +                      Elf_Internal_Sym *sym)
1055 +{
1056 +  if (h)
1057 +    {
1058 +      switch (ELF32_R_TYPE(rel->r_info))
1059 +       {
1060 +         /* TODO: VTINHERIT/VTENTRY */
1061 +       default:
1062 +         switch (h->root.type)
1063 +           {
1064 +           case bfd_link_hash_defined:
1065 +           case bfd_link_hash_defweak:
1066 +             return h->root.u.def.section;
1067 +
1068 +           case bfd_link_hash_common:
1069 +             return h->root.u.c.p->section;
1070 +
1071 +           default:
1072 +             break;
1073 +           }
1074 +       }
1075 +    }
1076 +  else
1077 +    return bfd_section_from_elf_index(sec->owner, sym->st_shndx);
1078 +
1079 +  return NULL;
1080 +}
1081 +
1082 +/* Update the GOT entry reference counts for the section being removed. */
1083 +static bfd_boolean
1084 +avr32_elf_gc_sweep_hook(bfd *abfd,
1085 +                       struct bfd_link_info *info ATTRIBUTE_UNUSED,
1086 +                       asection *sec,
1087 +                       const Elf_Internal_Rela *relocs)
1088 +{
1089 +  Elf_Internal_Shdr *symtab_hdr;
1090 +  struct elf_avr32_link_hash_entry **sym_hashes;
1091 +  struct got_entry **local_got_ents;
1092 +  const Elf_Internal_Rela *rel, *relend;
1093 +
1094 +  if (!(sec->flags & SEC_ALLOC))
1095 +    return TRUE;
1096 +
1097 +  symtab_hdr = &elf_tdata(abfd)->symtab_hdr;
1098 +  sym_hashes = (struct elf_avr32_link_hash_entry **)elf_sym_hashes(abfd);
1099 +  local_got_ents = elf_local_got_ents(abfd);
1100 +
1101 +  relend = relocs + sec->reloc_count;
1102 +  for (rel = relocs; rel < relend; rel++)
1103 +    {
1104 +      unsigned long r_symndx;
1105 +      unsigned int r_type;
1106 +      struct elf_avr32_link_hash_entry *h = NULL;
1107 +
1108 +      r_symndx = ELF32_R_SYM(rel->r_info);
1109 +      if (r_symndx >= symtab_hdr->sh_info)
1110 +       {
1111 +         h = sym_hashes[r_symndx - symtab_hdr->sh_info];
1112 +         while (h->root.root.type == bfd_link_hash_indirect
1113 +                || h->root.root.type == bfd_link_hash_warning)
1114 +           h = (struct elf_avr32_link_hash_entry *)h->root.root.u.i.link;
1115 +       }
1116 +
1117 +      r_type = ELF32_R_TYPE(rel->r_info);
1118 +
1119 +      switch (r_type)
1120 +       {
1121 +       case R_AVR32_GOT32:
1122 +       case R_AVR32_GOT16:
1123 +       case R_AVR32_GOT8:
1124 +       case R_AVR32_GOT21S:
1125 +       case R_AVR32_GOT18SW:
1126 +       case R_AVR32_GOT16S:
1127 +       case R_AVR32_GOT7UW:
1128 +       case R_AVR32_LDA_GOT:
1129 +       case R_AVR32_GOTCALL:
1130 +         if (h)
1131 +           h->root.got.glist->refcount--;
1132 +         else
1133 +           local_got_ents[r_symndx]->refcount--;
1134 +         break;
1135 +
1136 +       case R_AVR32_32:
1137 +         if (info->shared || h)
1138 +           {
1139 +             if (h)
1140 +               h->possibly_dynamic_relocs--;
1141 +             else
1142 +               avr32_elf_hash_table(info)->local_dynamic_relocs--;
1143 +           }
1144 +
1145 +       default:
1146 +         break;
1147 +       }
1148 +    }
1149 +
1150 +  return TRUE;
1151 +}
1152 +
1153 +/* Sizing and refcounting of dynamic sections */
1154 +
1155 +static void
1156 +insert_got_entry(struct elf_avr32_link_hash_table *htab, struct got_entry *got);
1157 +static void
1158 +unref_got_entry(struct elf_avr32_link_hash_table *htab, struct got_entry *got);
1159 +static void
1160 +ref_got_entry(struct elf_avr32_link_hash_table *htab, struct got_entry *got);
1161 +static bfd_boolean
1162 +assign_got_offsets(struct elf_avr32_link_hash_table *htab);
1163 +static bfd_boolean
1164 +allocate_dynrelocs(struct elf_link_hash_entry *h, void *_info);
1165 +static bfd_boolean
1166 +avr32_elf_size_dynamic_sections (bfd *output_bfd,
1167 +                                struct bfd_link_info *info);
1168 +
1169 +static void
1170 +insert_got_entry(struct elf_avr32_link_hash_table *htab, struct got_entry *got)
1171 +{
1172 +  /* Any entries with got_refcount > htab->nr_got_holes end up in the
1173 +   * last pigeonhole without any sorting. We expect the number of such
1174 +   * entries to be small, so it is very unlikely to affect
1175 +   * performance.  */
1176 +  int entry = got->refcount;
1177 +
1178 +  if (entry > htab->nr_got_holes)
1179 +    entry = htab->nr_got_holes;
1180 +
1181 +  got->pprev = &htab->got_hole[entry];
1182 +  got->next = htab->got_hole[entry];
1183 +
1184 +  if (got->next)
1185 +    got->next->pprev = &got->next;
1186 +
1187 +  htab->got_hole[entry] = got;
1188 +}
1189 +
1190 +/* Decrement the refcount of a GOT entry and update its position in
1191 +   the pigeonhole array.  */
1192 +static void
1193 +unref_got_entry(struct elf_avr32_link_hash_table *htab, struct got_entry *got)
1194 +{
1195 +  BFD_ASSERT(got->refcount > 0);
1196 +
1197 +  if (got->next)
1198 +    got->next->pprev = got->pprev;
1199 +
1200 +  *(got->pprev) = got->next;
1201 +  got->refcount--;
1202 +  insert_got_entry(htab, got);
1203 +}
1204 +
1205 +static void
1206 +ref_got_entry(struct elf_avr32_link_hash_table *htab, struct got_entry *got)
1207 +{
1208 +  if (got->next)
1209 +    got->next->pprev = got->pprev;
1210 +
1211 +  *(got->pprev) = got->next;
1212 +  got->refcount++;
1213 +  insert_got_entry(htab, got);
1214 +
1215 +  BFD_ASSERT(got->refcount > 0);
1216 +}
1217 +
1218 +/* Assign offsets to all GOT entries we intend to keep.  The entries
1219 +   that are referenced most often are placed at low offsets so that we
1220 +   can use compact instructions as much as possible.
1221 +
1222 +   Returns TRUE if any offsets or the total size of the GOT changed.  */
1223 +
1224 +static bfd_boolean
1225 +assign_got_offsets(struct elf_avr32_link_hash_table *htab)
1226 +{
1227 +  struct got_entry *got;
1228 +  bfd_size_type got_size = 0;
1229 +  bfd_boolean changed = FALSE;
1230 +  bfd_signed_vma offset;
1231 +  int i;
1232 +
1233 +  /* The GOT header provides the address of the DYNAMIC segment, so
1234 +     we need that even if the GOT is otherwise empty.  */
1235 +  if (htab->root.dynamic_sections_created)
1236 +    got_size = AVR32_GOT_HEADER_SIZE;
1237 +
1238 +  for (i = htab->nr_got_holes; i > 0; i--)
1239 +    {
1240 +      got = htab->got_hole[i];
1241 +      while (got)
1242 +       {
1243 +         if (got->refcount > 0)
1244 +           {
1245 +             offset = got_size;
1246 +             if (got->offset != offset)
1247 +               {
1248 +                 RDBG("GOT offset changed: %ld -> %ld\n",
1249 +                      got->offset, offset);
1250 +                 changed = TRUE;
1251 +               }
1252 +             got->offset = offset;
1253 +             got_size += 4;
1254 +           }
1255 +         got = got->next;
1256 +       }
1257 +    }
1258 +
1259 +  if (htab->sgot->size != got_size)
1260 +    {
1261 +      RDBG("GOT size changed: %lu -> %lu\n", htab->sgot->size,
1262 +          got_size);
1263 +      changed = TRUE;
1264 +    }
1265 +  htab->sgot->size = got_size;
1266 +
1267 +  RDBG("assign_got_offsets: total size %lu (%s)\n",
1268 +       got_size, changed ? "changed" : "no change");
1269 +
1270 +  return changed;
1271 +}
1272 +
1273 +static bfd_boolean
1274 +allocate_dynrelocs(struct elf_link_hash_entry *h, void *_info)
1275 +{
1276 +  struct bfd_link_info *info = _info;
1277 +  struct elf_avr32_link_hash_table *htab;
1278 +  struct elf_avr32_link_hash_entry *havr;
1279 +  struct got_entry *got;
1280 +
1281 +  pr_debug("  (4b) allocate_dynrelocs: %s\n", h->root.root.string);
1282 +
1283 +  if (h->root.type == bfd_link_hash_indirect)
1284 +    return TRUE;
1285 +
1286 +  if (h->root.type == bfd_link_hash_warning)
1287 +    /* When warning symbols are created, they **replace** the "real"
1288 +       entry in the hash table, thus we never get to see the real
1289 +       symbol in a hash traversal.  So look at it now.  */
1290 +    h = (struct elf_link_hash_entry *) h->root.u.i.link;
1291 +
1292 +  htab = avr32_elf_hash_table(info);
1293 +  havr = (struct elf_avr32_link_hash_entry *)h;
1294 +
1295 +  got = h->got.glist;
1296 +
1297 +  /* If got is NULL, the symbol is never referenced through the GOT */
1298 +  if (got && got->refcount > 0)
1299 +    {
1300 +      insert_got_entry(htab, got);
1301 +
1302 +      /* Shared libraries need relocs for all GOT entries unless the
1303 +        symbol is forced local or -Bsymbolic is used.  Others need
1304 +        relocs for everything that is not guaranteed to be defined in
1305 +        a regular object.  */
1306 +      if ((info->shared
1307 +          && !info->symbolic
1308 +          && h->dynindx != -1)
1309 +         || (htab->root.dynamic_sections_created
1310 +             && h->def_dynamic
1311 +             && !h->def_regular))
1312 +       htab->srelgot->size += sizeof(Elf32_External_Rela);
1313 +    }
1314 +
1315 +  if (havr->possibly_dynamic_relocs
1316 +      && (info->shared
1317 +         || (elf_hash_table(info)->dynamic_sections_created
1318 +             && h->def_dynamic
1319 +             && !h->def_regular)))
1320 +    {
1321 +      pr_debug("Allocating %d dynamic reloc against symbol %s...\n",
1322 +              havr->possibly_dynamic_relocs, h->root.root.string);
1323 +      htab->srelgot->size += (havr->possibly_dynamic_relocs
1324 +                             * sizeof(Elf32_External_Rela));
1325 +    }
1326 +
1327 +  return TRUE;
1328 +}
1329 +
1330 +/* (4) Calculate the sizes of the linker-generated sections and
1331 +   allocate memory for them.  */
1332 +
1333 +static bfd_boolean
1334 +avr32_elf_size_dynamic_sections (bfd *output_bfd,
1335 +                                struct bfd_link_info *info)
1336 +{
1337 +  struct elf_avr32_link_hash_table *htab;
1338 +  bfd *dynobj;
1339 +  asection *s;
1340 +  bfd *ibfd;
1341 +  bfd_boolean relocs;
1342 +
1343 +  pr_debug("(4) size dynamic sections\n");
1344 +
1345 +  htab = avr32_elf_hash_table(info);
1346 +  dynobj = htab->root.dynobj;
1347 +  BFD_ASSERT(dynobj != NULL);
1348 +
1349 +  if (htab->root.dynamic_sections_created)
1350 +    {
1351 +      /* Initialize the contents of the .interp section to the name of
1352 +        the dynamic loader */
1353 +      if (info->executable)
1354 +       {
1355 +         s = bfd_get_section_by_name(dynobj, ".interp");
1356 +         BFD_ASSERT(s != NULL);
1357 +         s->size = sizeof(ELF_DYNAMIC_INTERPRETER);
1358 +         s->contents = (unsigned char *)ELF_DYNAMIC_INTERPRETER;
1359 +       }
1360 +    }
1361 +
1362 +  if (htab->nr_got_holes > 0)
1363 +    {
1364 +      /* Allocate holes for the pigeonhole sort algorithm */
1365 +      pr_debug("Highest GOT refcount: %d\n", htab->nr_got_holes);
1366 +
1367 +      /* Limit the memory usage by clipping the number of pigeonholes
1368 +       * at a predefined maximum. All entries with a higher refcount
1369 +       * will end up in the last pigeonhole.  */
1370 +    if (htab->nr_got_holes >= MAX_NR_GOT_HOLES)
1371 +    {
1372 +        htab->nr_got_holes = MAX_NR_GOT_HOLES - 1;
1373 +
1374 +        pr_debug("Limiting maximum number of GOT pigeonholes to %u\n",
1375 +                    htab->nr_got_holes);
1376 +    }
1377 +      htab->got_hole = bfd_zalloc(output_bfd,
1378 +                                 sizeof(struct got_entry *)
1379 +                                 * (htab->nr_got_holes + 1));
1380 +      if (!htab->got_hole)
1381 +       return FALSE;
1382 +
1383 +      /* Set up .got offsets for local syms.  */
1384 +      for (ibfd = info->input_bfds; ibfd != NULL; ibfd = ibfd->link_next)
1385 +       {
1386 +         struct got_entry **local_got;
1387 +         struct got_entry **end_local_got;
1388 +         Elf_Internal_Shdr *symtab_hdr;
1389 +         bfd_size_type locsymcount;
1390 +
1391 +         pr_debug("  (4a) processing file %s...\n", ibfd->filename);
1392 +
1393 +         BFD_ASSERT(bfd_get_flavour(ibfd) == bfd_target_elf_flavour);
1394 +
1395 +         local_got = elf_local_got_ents(ibfd);
1396 +         if (!local_got)
1397 +           continue;
1398 +
1399 +         symtab_hdr = &elf_tdata(ibfd)->symtab_hdr;
1400 +         locsymcount = symtab_hdr->sh_info;
1401 +         end_local_got = local_got + locsymcount;
1402 +
1403 +         for (; local_got < end_local_got; ++local_got)
1404 +           insert_got_entry(htab, *local_got);
1405 +       }
1406 +    }
1407 +
1408 +  /* Allocate global sym .got entries and space for global sym
1409 +     dynamic relocs */
1410 +  elf_link_hash_traverse(&htab->root, allocate_dynrelocs, info);
1411 +
1412 +  /* Now that we have sorted the GOT entries, we are ready to
1413 +     assign offsets and determine the initial size of the GOT. */
1414 +  if (htab->sgot)
1415 +    assign_got_offsets(htab);
1416 +
1417 +  /* Allocate space for local sym dynamic relocs */
1418 +  BFD_ASSERT(htab->local_dynamic_relocs == 0 || info->shared);
1419 +  if (htab->local_dynamic_relocs)
1420 +    htab->srelgot->size += (htab->local_dynamic_relocs
1421 +                           * sizeof(Elf32_External_Rela));
1422 +
1423 +  /* We now have determined the sizes of the various dynamic
1424 +     sections. Allocate memory for them. */
1425 +  relocs = FALSE;
1426 +  for (s = dynobj->sections; s; s = s->next)
1427 +    {
1428 +      if ((s->flags & SEC_LINKER_CREATED) == 0)
1429 +       continue;
1430 +
1431 +      if (s == htab->sgot
1432 +         || s == htab->sstub)
1433 +       {
1434 +         /* Strip this section if we don't need it */
1435 +       }
1436 +      else if (strncmp (bfd_get_section_name(dynobj, s), ".rela", 5) == 0)
1437 +       {
1438 +         if (s->size != 0)
1439 +           relocs = TRUE;
1440 +
1441 +         s->reloc_count = 0;
1442 +       }
1443 +      else
1444 +       {
1445 +         /* It's not one of our sections */
1446 +         continue;
1447 +       }
1448 +
1449 +      if (s->size == 0)
1450 +       {
1451 +         /* Strip unneeded sections */
1452 +         pr_debug("Stripping section %s from output...\n", s->name);
1453 +         /* deleted function in 2.17
1454 +      _bfd_strip_section_from_output(info, s);
1455 +      */
1456 +         continue;
1457 +       }
1458 +
1459 +      s->contents = bfd_zalloc(dynobj, s->size);
1460 +      if (s->contents == NULL)
1461 +       return FALSE;
1462 +    }
1463 +
1464 +  if (htab->root.dynamic_sections_created)
1465 +    {
1466 +      /* Add some entries to the .dynamic section.  We fill in the
1467 +        values later, in sh_elf_finish_dynamic_sections, but we
1468 +        must add the entries now so that we get the correct size for
1469 +        the .dynamic section.  The DT_DEBUG entry is filled in by the
1470 +        dynamic linker and used by the debugger.  */
1471 +#define add_dynamic_entry(TAG, VAL) _bfd_elf_add_dynamic_entry(info, TAG, VAL)
1472 +
1473 +      if (!add_dynamic_entry(DT_PLTGOT, 0))
1474 +       return FALSE;
1475 +      if (!add_dynamic_entry(DT_AVR32_GOTSZ, 0))
1476 +       return FALSE;
1477 +
1478 +      if (info->executable)
1479 +       {
1480 +         if (!add_dynamic_entry(DT_DEBUG, 0))
1481 +           return FALSE;
1482 +       }
1483 +      if (relocs)
1484 +       {
1485 +         if (!add_dynamic_entry(DT_RELA, 0)
1486 +             || !add_dynamic_entry(DT_RELASZ, 0)
1487 +             || !add_dynamic_entry(DT_RELAENT,
1488 +                                   sizeof(Elf32_External_Rela)))
1489 +           return FALSE;
1490 +       }
1491 +    }
1492 +#undef add_dynamic_entry
1493 +
1494 +  return TRUE;
1495 +}
1496 +
1497 +
1498 +/* Access to internal relocations, section contents and symbols.
1499 +   (stolen from the xtensa port)  */
1500 +
1501 +static Elf_Internal_Rela *
1502 +retrieve_internal_relocs (bfd *abfd, asection *sec, bfd_boolean keep_memory);
1503 +static void
1504 +pin_internal_relocs (asection *sec, Elf_Internal_Rela *internal_relocs);
1505 +static void
1506 +release_internal_relocs (asection *sec, Elf_Internal_Rela *internal_relocs);
1507 +static bfd_byte *
1508 +retrieve_contents (bfd *abfd, asection *sec, bfd_boolean keep_memory);
1509 +/*
1510 +static void
1511 +pin_contents (asection *sec, bfd_byte *contents);
1512 +*/
1513 +static void
1514 +release_contents (asection *sec, bfd_byte *contents);
1515 +static Elf_Internal_Sym *
1516 +retrieve_local_syms (bfd *input_bfd, bfd_boolean keep_memory);
1517 +/*
1518 +static void
1519 +pin_local_syms (bfd *input_bfd, Elf_Internal_Sym *isymbuf);
1520 +*/
1521 +static void
1522 +release_local_syms (bfd *input_bfd, Elf_Internal_Sym *isymbuf);
1523 +
1524 +/* During relaxation, we need to modify relocations, section contents,
1525 +   and symbol definitions, and we need to keep the original values from
1526 +   being reloaded from the input files, i.e., we need to "pin" the
1527 +   modified values in memory.  We also want to continue to observe the
1528 +   setting of the "keep-memory" flag.  The following functions wrap the
1529 +   standard BFD functions to take care of this for us.  */
1530 +
1531 +static Elf_Internal_Rela *
1532 +retrieve_internal_relocs (bfd *abfd, asection *sec, bfd_boolean keep_memory)
1533 +{
1534 +  /* _bfd_elf_link_read_relocs knows about caching, so no need for us
1535 +     to be clever here.  */
1536 +  return _bfd_elf_link_read_relocs(abfd, sec, NULL, NULL, keep_memory);
1537 +}
1538 +
1539 +static void
1540 +pin_internal_relocs (asection *sec, Elf_Internal_Rela *internal_relocs)
1541 +{
1542 +  elf_section_data (sec)->relocs = internal_relocs;
1543 +}
1544 +
1545 +static void
1546 +release_internal_relocs (asection *sec, Elf_Internal_Rela *internal_relocs)
1547 +{
1548 +  if (internal_relocs
1549 +      && elf_section_data (sec)->relocs != internal_relocs)
1550 +    free (internal_relocs);
1551 +}
1552 +
1553 +static bfd_byte *
1554 +retrieve_contents (bfd *abfd, asection *sec, bfd_boolean keep_memory)
1555 +{
1556 +  bfd_byte *contents;
1557 +  bfd_size_type sec_size;
1558 +
1559 +  sec_size = bfd_get_section_limit (abfd, sec);
1560 +  contents = elf_section_data (sec)->this_hdr.contents;
1561 +
1562 +  if (contents == NULL && sec_size != 0)
1563 +    {
1564 +      if (!bfd_malloc_and_get_section (abfd, sec, &contents))
1565 +       {
1566 +         if (contents)
1567 +           free (contents);
1568 +         return NULL;
1569 +       }
1570 +      if (keep_memory)
1571 +       elf_section_data (sec)->this_hdr.contents = contents;
1572 +    }
1573 +  return contents;
1574 +}
1575 +
1576 +/*
1577 +static void
1578 +pin_contents (asection *sec, bfd_byte *contents)
1579 +{
1580 +  elf_section_data (sec)->this_hdr.contents = contents;
1581 +}
1582 +*/
1583 +static void
1584 +release_contents (asection *sec, bfd_byte *contents)
1585 +{
1586 +  if (contents && elf_section_data (sec)->this_hdr.contents != contents)
1587 +    free (contents);
1588 +}
1589 +
1590 +static Elf_Internal_Sym *
1591 +retrieve_local_syms (bfd *input_bfd, bfd_boolean keep_memory)
1592 +{
1593 +  Elf_Internal_Shdr *symtab_hdr;
1594 +  Elf_Internal_Sym *isymbuf;
1595 +  size_t locsymcount;
1596 +
1597 +  symtab_hdr = &elf_tdata (input_bfd)->symtab_hdr;
1598 +  locsymcount = symtab_hdr->sh_info;
1599 +
1600 +  isymbuf = (Elf_Internal_Sym *) symtab_hdr->contents;
1601 +  if (isymbuf == NULL && locsymcount != 0)
1602 +    {
1603 +      isymbuf = bfd_elf_get_elf_syms (input_bfd, symtab_hdr, locsymcount, 0,
1604 +                                     NULL, NULL, NULL);
1605 +      if (isymbuf && keep_memory)
1606 +       symtab_hdr->contents = (unsigned char *) isymbuf;
1607 +    }
1608 +
1609 +  return isymbuf;
1610 +}
1611 +
1612 +/*
1613 +static void
1614 +pin_local_syms (bfd *input_bfd, Elf_Internal_Sym *isymbuf)
1615 +{
1616 +  elf_tdata (input_bfd)->symtab_hdr.contents = (unsigned char *)isymbuf;
1617 +}
1618 +
1619 +*/
1620 +static void
1621 +release_local_syms (bfd *input_bfd, Elf_Internal_Sym *isymbuf)
1622 +{
1623 +  if (isymbuf && (elf_tdata (input_bfd)->symtab_hdr.contents
1624 +                 != (unsigned char *)isymbuf))
1625 +    free (isymbuf);
1626 +}
1627 +
1628 +\f/* Data structures used during relaxation. */
1629 +
1630 +enum relax_state_id {
1631 +  RS_ERROR = -1,
1632 +  RS_NONE = 0,
1633 +  RS_ALIGN,
1634 +  RS_CPENT,
1635 +  RS_PIC_CALL,
1636 +  RS_PIC_MCALL,
1637 +  RS_PIC_RCALL2,
1638 +  RS_PIC_RCALL1,
1639 +  RS_PIC_LDA,
1640 +  RS_PIC_LDW4,
1641 +  RS_PIC_LDW3,
1642 +  RS_PIC_SUB5,
1643 +  RS_NOPIC_MCALL,
1644 +  RS_NOPIC_RCALL2,
1645 +  RS_NOPIC_RCALL1,
1646 +  RS_NOPIC_LDW4,
1647 +  RS_NOPIC_LDDPC,
1648 +  RS_NOPIC_SUB5,
1649 +  RS_NOPIC_MOV2,
1650 +  RS_NOPIC_MOV1,
1651 +  RS_RCALL2,
1652 +  RS_RCALL1,
1653 +  RS_BRC2,
1654 +  RS_BRC1,
1655 +  RS_BRAL,
1656 +  RS_RJMP,
1657 +  RS_MAX,
1658 +};
1659 +
1660 +enum reference_type {
1661 +  REF_ABSOLUTE,
1662 +  REF_PCREL,
1663 +  REF_CPOOL,
1664 +  REF_GOT,
1665 +};
1666 +
1667 +struct relax_state
1668 +{
1669 +  const char *name;
1670 +  enum relax_state_id id;
1671 +  enum relax_state_id direct;
1672 +  enum relax_state_id next;
1673 +  enum relax_state_id prev;
1674 +
1675 +  enum reference_type reftype;
1676 +
1677 +  unsigned int r_type;
1678 +
1679 +  bfd_vma opcode;
1680 +  bfd_vma opcode_mask;
1681 +
1682 +  bfd_signed_vma range_min;
1683 +  bfd_signed_vma range_max;
1684 +
1685 +  bfd_size_type size;
1686 +};
1687 +
1688 +/*
1689 + * This is for relocs that
1690 + *   a) has an addend or is of type R_AVR32_DIFF32, and
1691 + *   b) references a different section than it's in, and
1692 + *   c) references a section that is relaxable
1693 + *
1694 + * as well as relocs that references the constant pool, in which case
1695 + * the add_frag member points to the frag containing the constant pool
1696 + * entry.
1697 + *
1698 + * Such relocs must be fixed up whenever we delete any code. Sections
1699 + * that don't have any relocs with all of the above properties don't
1700 + * have any additional reloc data, but sections that do will have
1701 + * additional data for all its relocs.
1702 + */
1703 +struct avr32_reloc_data
1704 +{
1705 +  struct fragment *add_frag;
1706 +  struct fragment *sub_frag;
1707 +};
1708 +
1709 +/*
1710 + * A 'fragment' is a relaxable entity, that is, code may be added or
1711 + * deleted at the end of a fragment. When this happens, all subsequent
1712 + * fragments in the list will have their offsets updated.
1713 + */
1714 +struct fragment
1715 +{
1716 +  enum relax_state_id state;
1717 +  enum relax_state_id initial_state;
1718 +
1719 +  Elf_Internal_Rela *rela;
1720 +  bfd_size_type size;
1721 +  bfd_vma offset;
1722 +  int size_adjust;
1723 +  int offset_adjust;
1724 +  bfd_boolean has_grown;
1725 +
1726 +  /* Only used by constant pool entries.  When this drops to zero, the
1727 +     frag is discarded (i.e. size_adjust is set to -4.)  */
1728 +  int refcount;
1729 +};
1730 +
1731 +struct avr32_relax_data
1732 +{
1733 +  unsigned int frag_count;
1734 +  struct fragment *frag;
1735 +  struct avr32_reloc_data *reloc_data;
1736 +
1737 +  /* TRUE if this section has one or more relaxable relocations */
1738 +  bfd_boolean is_relaxable;
1739 +  unsigned int iteration;
1740 +};
1741 +
1742 +struct avr32_section_data
1743 +{
1744 +  struct bfd_elf_section_data elf;
1745 +  struct avr32_relax_data relax_data;
1746 +};
1747 +
1748 +\f/* Relax state definitions */
1749 +
1750 +#define PIC_MOV2_OPCODE                0xe0600000
1751 +#define PIC_MOV2_MASK          0xe1e00000
1752 +#define PIC_MOV2_RANGE_MIN     (-1048576 * 4)
1753 +#define PIC_MOV2_RANGE_MAX     (1048575 * 4)
1754 +#define PIC_MCALL_OPCODE       0xf0160000
1755 +#define PIC_MCALL_MASK         0xffff0000
1756 +#define PIC_MCALL_RANGE_MIN    (-131072)
1757 +#define PIC_MCALL_RANGE_MAX    (131068)
1758 +#define RCALL2_OPCODE          0xe0a00000
1759 +#define RCALL2_MASK            0xe1ef0000
1760 +#define RCALL2_RANGE_MIN       (-2097152)
1761 +#define RCALL2_RANGE_MAX       (2097150)
1762 +#define RCALL1_OPCODE          0xc00c0000
1763 +#define RCALL1_MASK            0xf00c0000
1764 +#define RCALL1_RANGE_MIN       (-1024)
1765 +#define RCALL1_RANGE_MAX       (1022)
1766 +#define PIC_LDW4_OPCODE                0xecf00000
1767 +#define PIC_LDW4_MASK          0xfff00000
1768 +#define PIC_LDW4_RANGE_MIN     (-32768)
1769 +#define PIC_LDW4_RANGE_MAX     (32767)
1770 +#define PIC_LDW3_OPCODE                0x6c000000
1771 +#define PIC_LDW3_MASK          0xfe000000
1772 +#define PIC_LDW3_RANGE_MIN     (0)
1773 +#define PIC_LDW3_RANGE_MAX     (124)
1774 +#define SUB5_PC_OPCODE         0xfec00000
1775 +#define SUB5_PC_MASK           0xfff00000
1776 +#define SUB5_PC_RANGE_MIN      (-32768)
1777 +#define SUB5_PC_RANGE_MAX      (32767)
1778 +#define NOPIC_MCALL_OPCODE     0xf01f0000
1779 +#define NOPIC_MCALL_MASK       0xffff0000
1780 +#define NOPIC_MCALL_RANGE_MIN  PIC_MCALL_RANGE_MIN
1781 +#define NOPIC_MCALL_RANGE_MAX  PIC_MCALL_RANGE_MAX
1782 +#define NOPIC_LDW4_OPCODE      0xfef00000
1783 +#define NOPIC_LDW4_MASK                0xfff00000
1784 +#define NOPIC_LDW4_RANGE_MIN   PIC_LDW4_RANGE_MIN
1785 +#define NOPIC_LDW4_RANGE_MAX   PIC_LDW4_RANGE_MAX
1786 +#define LDDPC_OPCODE           0x48000000
1787 +#define LDDPC_MASK             0xf8000000
1788 +#define LDDPC_RANGE_MIN                0
1789 +#define LDDPC_RANGE_MAX                508
1790 +
1791 +#define NOPIC_MOV2_OPCODE  0xe0600000
1792 +#define NOPIC_MOV2_MASK        0xe1e00000
1793 +#define NOPIC_MOV2_RANGE_MIN   (-1048576)
1794 +#define NOPIC_MOV2_RANGE_MAX   (1048575)
1795 +#define NOPIC_MOV1_OPCODE  0x30000000
1796 +#define NOPIC_MOV1_MASK        0xf0000000
1797 +#define NOPIC_MOV1_RANGE_MIN   (-128)
1798 +#define NOPIC_MOV1_RANGE_MAX   (127)
1799 +
1800 +/* Only brc2 variants with cond[3] == 0 is considered, since the
1801 +   others are not relaxable.  bral is a special case and is handled
1802 +   separately.  */
1803 +#define BRC2_OPCODE            0xe0800000
1804 +#define BRC2_MASK              0xe1e80000
1805 +#define BRC2_RANGE_MIN         (-2097152)
1806 +#define BRC2_RANGE_MAX         (2097150)
1807 +#define BRC1_OPCODE            0xc0000000
1808 +#define BRC1_MASK              0xf0080000
1809 +#define BRC1_RANGE_MIN         (-256)
1810 +#define BRC1_RANGE_MAX         (254)
1811 +#define BRAL_OPCODE            0xe08f0000
1812 +#define BRAL_MASK              0xe1ef0000
1813 +#define BRAL_RANGE_MIN         BRC2_RANGE_MIN
1814 +#define BRAL_RANGE_MAX         BRC2_RANGE_MAX
1815 +#define RJMP_OPCODE            0xc0080000
1816 +#define RJMP_MASK              0xf00c0000
1817 +#define RJMP_RANGE_MIN         (-1024)
1818 +#define RJMP_RANGE_MAX         (1022)
1819 +
1820 +/* Define a relax state using the GOT  */
1821 +#define RG(id, dir, next, prev, r_type, opc, size)                     \
1822 +  { "RS_"#id, RS_##id, RS_##dir, RS_##next, RS_##prev, REF_GOT,                \
1823 +      R_AVR32_##r_type,        opc##_OPCODE, opc##_MASK,                       \
1824 +      opc##_RANGE_MIN, opc##_RANGE_MAX, size }
1825 +/* Define a relax state using the Constant Pool  */
1826 +#define RC(id, dir, next, prev, r_type, opc, size)                     \
1827 +  { "RS_"#id, RS_##id, RS_##dir, RS_##next, RS_##prev, REF_CPOOL,      \
1828 +      R_AVR32_##r_type,        opc##_OPCODE, opc##_MASK,                       \
1829 +      opc##_RANGE_MIN, opc##_RANGE_MAX, size }
1830 +
1831 +/* Define a relax state using pc-relative direct reference  */
1832 +#define RP(id, dir, next, prev, r_type, opc, size)                     \
1833 +  { "RS_"#id, RS_##id, RS_##dir, RS_##next, RS_##prev, REF_PCREL,      \
1834 +      R_AVR32_##r_type,        opc##_OPCODE, opc##_MASK,                       \
1835 +      opc##_RANGE_MIN, opc##_RANGE_MAX, size }
1836 +
1837 +/* Define a relax state using non-pc-relative direct reference */
1838 +#define RD(id, dir, next, prev, r_type, opc, size)         \
1839 +  { "RS_"#id, RS_##id, RS_##dir, RS_##next, RS_##prev, REF_ABSOLUTE,   \
1840 +      R_AVR32_##r_type,    opc##_OPCODE, opc##_MASK,           \
1841 +      opc##_RANGE_MIN, opc##_RANGE_MAX, size }
1842 +
1843 +/* Define a relax state that will be handled specially  */
1844 +#define RS(id, r_type, size)                                           \
1845 +  { "RS_"#id, RS_##id, RS_NONE, RS_NONE, RS_NONE, REF_ABSOLUTE,                \
1846 +      R_AVR32_##r_type, 0, 0, 0, 0, size }
1847 +
1848 +const struct relax_state relax_state[RS_MAX] = {
1849 +  RS(NONE, NONE, 0),
1850 +  RS(ALIGN, ALIGN, 0),
1851 +  RS(CPENT, 32_CPENT, 4),
1852 +
1853 +  RG(PIC_CALL, PIC_RCALL1, PIC_MCALL, NONE, GOTCALL, PIC_MOV2, 10),
1854 +  RG(PIC_MCALL, PIC_RCALL1, NONE, PIC_CALL, GOT18SW, PIC_MCALL, 4),
1855 +  RP(PIC_RCALL2, NONE, PIC_RCALL1, PIC_MCALL, 22H_PCREL, RCALL2, 4),
1856 +  RP(PIC_RCALL1, NONE, NONE, PIC_RCALL2, 11H_PCREL, RCALL1, 2),
1857 +
1858 +  RG(PIC_LDA, PIC_SUB5, PIC_LDW4, NONE, LDA_GOT, PIC_MOV2, 8),
1859 +  RG(PIC_LDW4, PIC_SUB5, PIC_LDW3, PIC_LDA, GOT16S, PIC_LDW4, 4),
1860 +  RG(PIC_LDW3, PIC_SUB5, NONE, PIC_LDW4, GOT7UW, PIC_LDW3, 2),
1861 +  RP(PIC_SUB5, NONE, NONE, PIC_LDW3, 16N_PCREL, SUB5_PC, 4),
1862 +
1863 +  RC(NOPIC_MCALL, NOPIC_RCALL1, NONE, NONE, CPCALL, NOPIC_MCALL, 4),
1864 +  RP(NOPIC_RCALL2, NONE, NOPIC_RCALL1, NOPIC_MCALL, 22H_PCREL, RCALL2, 4),
1865 +  RP(NOPIC_RCALL1, NONE, NONE, NOPIC_RCALL2, 11H_PCREL, RCALL1, 2),
1866 +
1867 +  RC(NOPIC_LDW4, NOPIC_MOV1, NOPIC_LDDPC, NONE, 16_CP, NOPIC_LDW4, 4),
1868 +  RC(NOPIC_LDDPC, NOPIC_MOV1, NONE, NOPIC_LDW4, 9W_CP, LDDPC, 2),
1869 +  RP(NOPIC_SUB5, NOPIC_MOV1, NONE, NOPIC_LDDPC, 16N_PCREL, SUB5_PC, 4),
1870 +  RD(NOPIC_MOV2, NONE, NOPIC_MOV1, NOPIC_SUB5, 21S, NOPIC_MOV2, 4),
1871 +  RD(NOPIC_MOV1, NONE, NONE, NOPIC_MOV2, 8S, NOPIC_MOV1, 2),
1872 +
1873 +  RP(RCALL2, NONE, RCALL1, NONE, 22H_PCREL, RCALL2, 4),
1874 +  RP(RCALL1, NONE, NONE, RCALL2, 11H_PCREL, RCALL1, 2),
1875 +  RP(BRC2, NONE, BRC1, NONE, 22H_PCREL, BRC2, 4),
1876 +  RP(BRC1, NONE, NONE, BRC2, 9H_PCREL, BRC1, 2),
1877 +  RP(BRAL, NONE, RJMP, NONE, 22H_PCREL, BRAL, 4),
1878 +  RP(RJMP, NONE, NONE, BRAL, 11H_PCREL, RJMP, 2),
1879 +};
1880 +
1881 +static bfd_boolean
1882 +avr32_elf_new_section_hook(bfd *abfd, asection *sec)
1883 +{
1884 +  struct avr32_section_data *sdata;
1885 +
1886 +  sdata = bfd_zalloc(abfd, sizeof(struct avr32_section_data));
1887 +  if (!sdata)
1888 +    return FALSE;
1889 +
1890 +  sec->used_by_bfd = sdata;
1891 +  return _bfd_elf_new_section_hook(abfd, sec);
1892 +}
1893 +
1894 +static struct avr32_relax_data *
1895 +avr32_relax_data(asection *sec)
1896 +{
1897 +  struct avr32_section_data *sdata;
1898 +
1899 +  BFD_ASSERT(sec->used_by_bfd);
1900 +
1901 +  sdata = (struct avr32_section_data *)elf_section_data(sec);
1902 +  return &sdata->relax_data;
1903 +}
1904 +
1905 +\f/* Link-time relaxation */
1906 +
1907 +static bfd_boolean
1908 +avr32_elf_relax_section(bfd *abfd, asection *sec,
1909 +                       struct bfd_link_info *info, bfd_boolean *again);
1910 +
1911 +enum relax_pass_id {
1912 +  RELAX_PASS_SIZE_FRAGS,
1913 +  RELAX_PASS_MOVE_DATA,
1914 +};
1915 +
1916 +/* Stolen from the xtensa port */
1917 +static int
1918 +internal_reloc_compare (const void *ap, const void *bp)
1919 +{
1920 +  const Elf_Internal_Rela *a = (const Elf_Internal_Rela *) ap;
1921 +  const Elf_Internal_Rela *b = (const Elf_Internal_Rela *) bp;
1922 +
1923 +  if (a->r_offset != b->r_offset)
1924 +    return (a->r_offset - b->r_offset);
1925 +
1926 +  /* We don't need to sort on these criteria for correctness,
1927 +     but enforcing a more strict ordering prevents unstable qsort
1928 +     from behaving differently with different implementations.
1929 +     Without the code below we get correct but different results
1930 +     on Solaris 2.7 and 2.8.  We would like to always produce the
1931 +     same results no matter the host.  */
1932 +
1933 +  if (a->r_info != b->r_info)
1934 +    return (a->r_info - b->r_info);
1935 +
1936 +  return (a->r_addend - b->r_addend);
1937 +}
1938 +
1939 +static enum relax_state_id
1940 +get_pcrel22_relax_state(bfd *abfd, asection *sec, struct bfd_link_info *info,
1941 +                       const Elf_Internal_Rela *rela)
1942 +{
1943 +  bfd_byte *contents;
1944 +  bfd_vma insn;
1945 +  enum relax_state_id rs = RS_NONE;
1946 +
1947 +  contents = retrieve_contents(abfd, sec, info->keep_memory);
1948 +  if (!contents)
1949 +    return RS_ERROR;
1950 +
1951 +  insn = bfd_get_32(abfd, contents + rela->r_offset);
1952 +  if ((insn & RCALL2_MASK) == RCALL2_OPCODE)
1953 +    rs = RS_RCALL2;
1954 +  else if ((insn & BRAL_MASK) == BRAL_OPCODE)
1955 +    /* Optimizing bral -> rjmp gets us into all kinds of
1956 +       trouble with jump tables. Better not do it.  */
1957 +    rs = RS_NONE;
1958 +  else if ((insn & BRC2_MASK) == BRC2_OPCODE)
1959 +    rs = RS_BRC2;
1960 +
1961 +  release_contents(sec, contents);
1962 +
1963 +  return rs;
1964 +}
1965 +
1966 +static enum relax_state_id
1967 +get_initial_relax_state(bfd *abfd, asection *sec, struct bfd_link_info *info,
1968 +                       const Elf_Internal_Rela *rela)
1969 +{
1970 +  switch (ELF_R_TYPE(rela->r_info))
1971 +    {
1972 +    case R_AVR32_GOTCALL:
1973 +      return RS_PIC_CALL;
1974 +    case R_AVR32_GOT18SW:
1975 +      return RS_PIC_MCALL;
1976 +    case R_AVR32_LDA_GOT:
1977 +      return RS_PIC_LDA;
1978 +    case R_AVR32_GOT16S:
1979 +      return RS_PIC_LDW4;
1980 +    case R_AVR32_CPCALL:
1981 +      return RS_NOPIC_MCALL;
1982 +    case R_AVR32_16_CP:
1983 +      return RS_NOPIC_LDW4;
1984 +    case R_AVR32_9W_CP:
1985 +      return RS_NOPIC_LDDPC;
1986 +    case R_AVR32_ALIGN:
1987 +      return RS_ALIGN;
1988 +    case R_AVR32_32_CPENT:
1989 +      return RS_CPENT;
1990 +    case R_AVR32_22H_PCREL:
1991 +      return get_pcrel22_relax_state(abfd, sec, info, rela);
1992 +    case R_AVR32_9H_PCREL:
1993 +      return RS_BRC1;
1994 +    default:
1995 +      return RS_NONE;
1996 +    }
1997 +}
1998 +
1999 +static bfd_boolean
2000 +reloc_is_cpool_ref(const Elf_Internal_Rela *rela)
2001 +{
2002 +  switch (ELF_R_TYPE(rela->r_info))
2003 +    {
2004 +    case R_AVR32_CPCALL:
2005 +    case R_AVR32_16_CP:
2006 +    case R_AVR32_9W_CP:
2007 +      return TRUE;
2008 +    default:
2009 +      return FALSE;
2010 +    }
2011 +}
2012 +
2013 +static struct fragment *
2014 +new_frag(bfd *abfd ATTRIBUTE_UNUSED, asection *sec,
2015 +        struct avr32_relax_data *rd, enum relax_state_id state,
2016 +        Elf_Internal_Rela *rela)
2017 +{
2018 +  struct fragment *frag;
2019 +  bfd_size_type r_size;
2020 +  bfd_vma r_offset;
2021 +  unsigned int i = rd->frag_count;
2022 +
2023 +  BFD_ASSERT(state >= RS_NONE && state < RS_MAX);
2024 +
2025 +  rd->frag_count++;
2026 +  frag = bfd_realloc(rd->frag, sizeof(struct fragment) * rd->frag_count);
2027 +  if (!frag)
2028 +    return NULL;
2029 +  rd->frag = frag;
2030 +
2031 +  frag += i;
2032 +  memset(frag, 0, sizeof(struct fragment));
2033 +
2034 +  if (state == RS_ALIGN)
2035 +    r_size = (((rela->r_offset + (1 << rela->r_addend) - 1)
2036 +              & ~((1 << rela->r_addend) - 1)) - rela->r_offset);
2037 +  else
2038 +    r_size = relax_state[state].size;
2039 +
2040 +  if (rela)
2041 +    r_offset = rela->r_offset;
2042 +  else
2043 +    r_offset = sec->size;
2044 +
2045 +  if (i == 0)
2046 +    {
2047 +      frag->offset = 0;
2048 +      frag->size = r_offset + r_size;
2049 +    }
2050 +  else
2051 +    {
2052 +      frag->offset = rd->frag[i - 1].offset + rd->frag[i - 1].size;
2053 +      frag->size = r_offset + r_size - frag->offset;
2054 +    }
2055 +
2056 +  if (state != RS_CPENT)
2057 +    /* Make sure we don't discard this frag */
2058 +    frag->refcount = 1;
2059 +
2060 +  frag->initial_state = frag->state = state;
2061 +  frag->rela = rela;
2062 +
2063 +  return frag;
2064 +}
2065 +
2066 +static struct fragment *
2067 +find_frag(asection *sec, bfd_vma offset)
2068 +{
2069 +  struct fragment *first, *last;
2070 +  struct avr32_relax_data *rd = avr32_relax_data(sec);
2071 +
2072 +  if (rd->frag_count == 0)
2073 +    return NULL;
2074 +
2075 +  first = &rd->frag[0];
2076 +  last = &rd->frag[rd->frag_count - 1];
2077 +
2078 +  /* This may be a reloc referencing the end of a section.  The last
2079 +     frag will never have a reloc associated with it, so its size will
2080 +     never change, thus the offset adjustment of the last frag will
2081 +     always be the same as the offset adjustment of the end of the
2082 +     section.  */
2083 +  if (offset == sec->size)
2084 +    {
2085 +      BFD_ASSERT(last->offset + last->size == sec->size);
2086 +      BFD_ASSERT(!last->rela);
2087 +      return last;
2088 +    }
2089 +
2090 +  while (first <= last)
2091 +    {
2092 +      struct fragment *mid;
2093 +
2094 +      mid = (last - first) / 2 + first;
2095 +      if ((mid->offset + mid->size) <= offset)
2096 +       first = mid + 1;
2097 +      else if (mid->offset > offset)
2098 +       last = mid - 1;
2099 +      else
2100 +       return mid;
2101 +    }
2102 +
2103 +  return NULL;
2104 +}
2105 +
2106 +/* Look through all relocs in a section and determine if any relocs
2107 +   may be affected by relaxation in other sections.  If so, allocate
2108 +   an array of additional relocation data which links the affected
2109 +   relocations to the frag(s) where the relaxation may occur.
2110 +
2111 +   This function also links cpool references to cpool entries and
2112 +   increments the refcount of the latter when this happens.  */
2113 +
2114 +static bfd_boolean
2115 +allocate_reloc_data(bfd *abfd, asection *sec, Elf_Internal_Rela *relocs,
2116 +                   struct bfd_link_info *info)
2117 +{
2118 +  Elf_Internal_Shdr *symtab_hdr;
2119 +  Elf_Internal_Sym *isymbuf = NULL;
2120 +  struct avr32_relax_data *rd;
2121 +  unsigned int i;
2122 +  bfd_boolean ret = FALSE;
2123 +
2124 +  symtab_hdr = &elf_tdata(abfd)->symtab_hdr;
2125 +  rd = avr32_relax_data(sec);
2126 +
2127 +  RDBG("%s<%s>: allocate_reloc_data\n", abfd->filename, sec->name);
2128 +
2129 +  for (i = 0; i < sec->reloc_count; i++)
2130 +    {
2131 +      Elf_Internal_Rela *rel = &relocs[i];
2132 +      asection *sym_sec;
2133 +      unsigned long r_symndx;
2134 +      bfd_vma sym_value;
2135 +
2136 +      if (!rel->r_addend && ELF_R_TYPE(rel->r_info) != R_AVR32_DIFF32
2137 +         && !reloc_is_cpool_ref(rel))
2138 +       continue;
2139 +
2140 +      r_symndx = ELF_R_SYM(rel->r_info);
2141 +
2142 +      if (r_symndx < symtab_hdr->sh_info)
2143 +       {
2144 +         Elf_Internal_Sym *isym;
2145 +
2146 +         if (!isymbuf)
2147 +           isymbuf = retrieve_local_syms(abfd, info->keep_memory);
2148 +         if (!isymbuf)
2149 +           return FALSE;
2150 +
2151 +         isym = &isymbuf[r_symndx];
2152 +         sym_sec = bfd_section_from_elf_index(abfd, isym->st_shndx);
2153 +         sym_value = isym->st_value;
2154 +       }
2155 +      else
2156 +       {
2157 +         struct elf_link_hash_entry *h;
2158 +
2159 +         h = elf_sym_hashes(abfd)[r_symndx - symtab_hdr->sh_info];
2160 +
2161 +         while (h->root.type == bfd_link_hash_indirect
2162 +                || h->root.type == bfd_link_hash_warning)
2163 +           h = (struct elf_link_hash_entry *)h->root.u.i.link;
2164 +
2165 +         if (h->root.type != bfd_link_hash_defined
2166 +             && h->root.type != bfd_link_hash_defweak)
2167 +           continue;
2168 +
2169 +         sym_sec = h->root.u.def.section;
2170 +         sym_value = h->root.u.def.value;
2171 +       }
2172 +
2173 +      if (sym_sec && avr32_relax_data(sym_sec)->is_relaxable)
2174 +       {
2175 +         bfd_size_type size;
2176 +         struct fragment *frag;
2177 +
2178 +         if (!rd->reloc_data)
2179 +           {
2180 +             size = sizeof(struct avr32_reloc_data) * sec->reloc_count;
2181 +             rd->reloc_data = bfd_zalloc(abfd, size);
2182 +             if (!rd->reloc_data)
2183 +               goto out;
2184 +           }
2185 +
2186 +         RDBG("[%3d] 0x%04lx: target: 0x%lx + 0x%lx",
2187 +              i, rel->r_offset, sym_value, rel->r_addend);
2188 +
2189 +         frag = find_frag(sym_sec, sym_value + rel->r_addend);
2190 +         BFD_ASSERT(frag);
2191 +         rd->reloc_data[i].add_frag = frag;
2192 +
2193 +         RDBG(" -> %s<%s>:%04lx\n", sym_sec->owner->filename, sym_sec->name,
2194 +              frag->rela ? frag->rela->r_offset : sym_sec->size);
2195 +
2196 +         if (reloc_is_cpool_ref(rel))
2197 +           {
2198 +             BFD_ASSERT(ELF_R_TYPE(frag->rela->r_info) == R_AVR32_32_CPENT);
2199 +             frag->refcount++;
2200 +           }
2201 +
2202 +         if (ELF_R_TYPE(rel->r_info) == R_AVR32_DIFF32)
2203 +           {
2204 +             bfd_byte *contents;
2205 +             bfd_signed_vma diff;
2206 +
2207 +             contents = retrieve_contents(abfd, sec, info->keep_memory);
2208 +             if (!contents)
2209 +               goto out;
2210 +
2211 +             diff = bfd_get_signed_32(abfd, contents + rel->r_offset);
2212 +             frag = find_frag(sym_sec, sym_value + rel->r_addend + diff);
2213 +             BFD_ASSERT(frag);
2214 +             rd->reloc_data[i].sub_frag = frag;
2215 +
2216 +             release_contents(sec, contents);
2217 +           }
2218 +       }
2219 +    }
2220 +
2221 +  ret = TRUE;
2222 +
2223 + out:
2224 +  release_local_syms(abfd, isymbuf);
2225 +  return ret;
2226 +}
2227 +
2228 +static bfd_boolean
2229 +global_sym_set_frag(struct elf_avr32_link_hash_entry *havr,
2230 +                   struct bfd_link_info *info ATTRIBUTE_UNUSED)
2231 +{
2232 +  struct fragment *frag;
2233 +  asection *sec;
2234 +
2235 +  if (havr->root.root.type != bfd_link_hash_defined
2236 +      && havr->root.root.type != bfd_link_hash_defweak)
2237 +    return TRUE;
2238 +
2239 +  sec = havr->root.root.u.def.section;
2240 +  if (bfd_is_const_section(sec)
2241 +      || !avr32_relax_data(sec)->is_relaxable)
2242 +    return TRUE;
2243 +
2244 +  frag = find_frag(sec, havr->root.root.u.def.value);
2245 +  if (!frag)
2246 +    {
2247 +      unsigned int i;
2248 +      struct avr32_relax_data *rd = avr32_relax_data(sec);
2249 +
2250 +      RDBG("In %s: No frag for %s <%s+%lu> (limit %lu)\n",
2251 +          sec->owner->filename, havr->root.root.root.string,
2252 +          sec->name, havr->root.root.u.def.value, sec->size);
2253 +      for (i = 0; i < rd->frag_count; i++)
2254 +       RDBG("    %8lu - %8lu\n", rd->frag[i].offset,
2255 +            rd->frag[i].offset + rd->frag[i].size);
2256 +    }
2257 +  BFD_ASSERT(frag);
2258 +
2259 +  havr->sym_frag = frag;
2260 +  return TRUE;
2261 +}
2262 +
2263 +static bfd_boolean
2264 +analyze_relocations(struct bfd_link_info *info)
2265 +{
2266 +  bfd *abfd;
2267 +  asection *sec;
2268 +
2269 +  /* Divide all relaxable sections into fragments */
2270 +  for (abfd = info->input_bfds; abfd; abfd = abfd->link_next)
2271 +    {
2272 +      if (!(elf_elfheader(abfd)->e_flags & EF_AVR32_LINKRELAX))
2273 +       {
2274 +         if (!(*info->callbacks->warning)
2275 +             (info, _("input is not relaxable"), NULL, abfd, NULL, 0))
2276 +           return FALSE;
2277 +         continue;
2278 +       }
2279 +
2280 +      for (sec = abfd->sections; sec; sec = sec->next)
2281 +       {
2282 +         struct avr32_relax_data *rd;
2283 +         struct fragment *frag;
2284 +         Elf_Internal_Rela *relocs;
2285 +         unsigned int i;
2286 +         bfd_boolean ret = TRUE;
2287 +
2288 +         if (!(sec->flags & SEC_RELOC) || sec->reloc_count == 0)
2289 +           continue;
2290 +
2291 +         rd = avr32_relax_data(sec);
2292 +
2293 +         relocs = retrieve_internal_relocs(abfd, sec, info->keep_memory);
2294 +         if (!relocs)
2295 +           return FALSE;
2296 +
2297 +         qsort(relocs, sec->reloc_count, sizeof(Elf_Internal_Rela),
2298 +               internal_reloc_compare);
2299 +
2300 +         for (i = 0; i < sec->reloc_count; i++)
2301 +           {
2302 +             enum relax_state_id state;
2303 +
2304 +             ret = FALSE;
2305 +             state = get_initial_relax_state(abfd, sec, info, &relocs[i]);
2306 +             if (state == RS_ERROR)
2307 +               break;
2308 +
2309 +             if (state)
2310 +               {
2311 +                 frag = new_frag(abfd, sec, rd, state, &relocs[i]);
2312 +                 if (!frag)
2313 +                   break;
2314 +
2315 +                 pin_internal_relocs(sec, relocs);
2316 +                 rd->is_relaxable = TRUE;
2317 +               }
2318 +
2319 +             ret = TRUE;
2320 +           }
2321 +
2322 +         release_internal_relocs(sec, relocs);
2323 +         if (!ret)
2324 +           return ret;
2325 +
2326 +         if (rd->is_relaxable)
2327 +           {
2328 +             frag = new_frag(abfd, sec, rd, RS_NONE, NULL);
2329 +             if (!frag)
2330 +               return FALSE;
2331 +           }
2332 +       }
2333 +    }
2334 +
2335 +  /* Link each global symbol to the fragment where it's defined.  */
2336 +  elf_link_hash_traverse(elf_hash_table(info), global_sym_set_frag, info);
2337 +
2338 +  /* Do the same for local symbols. */
2339 +  for (abfd = info->input_bfds; abfd; abfd = abfd->link_next)
2340 +    {
2341 +      Elf_Internal_Sym *isymbuf, *isym;
2342 +      struct fragment **local_sym_frag;
2343 +      unsigned int i, sym_count;
2344 +
2345 +      sym_count = elf_tdata(abfd)->symtab_hdr.sh_info;
2346 +      if (sym_count == 0)
2347 +       continue;
2348 +
2349 +      local_sym_frag = bfd_zalloc(abfd, sym_count * sizeof(struct fragment *));
2350 +      if (!local_sym_frag)
2351 +       return FALSE;
2352 +      elf_tdata(abfd)->local_sym_frag = local_sym_frag;
2353 +
2354 +      isymbuf = retrieve_local_syms(abfd, info->keep_memory);
2355 +      if (!isymbuf)
2356 +       return FALSE;
2357 +
2358 +      for (i = 0; i < sym_count; i++)
2359 +       {
2360 +         struct avr32_relax_data *rd;
2361 +         struct fragment *frag;
2362 +         asection *sec;
2363 +
2364 +         isym = &isymbuf[i];
2365 +
2366 +         sec = bfd_section_from_elf_index(abfd, isym->st_shndx);
2367 +         if (!sec)
2368 +           continue;
2369 +
2370 +         rd = avr32_relax_data(sec);
2371 +         if (!rd->is_relaxable)
2372 +           continue;
2373 +
2374 +         frag = find_frag(sec, isym->st_value);
2375 +         BFD_ASSERT(frag);
2376 +
2377 +         local_sym_frag[i] = frag;
2378 +       }
2379 +
2380 +      release_local_syms(abfd, isymbuf);
2381 +    }
2382 +
2383 +  /* And again for relocs with addends and constant pool references */
2384 +  for (abfd = info->input_bfds; abfd; abfd = abfd->link_next)
2385 +    for (sec = abfd->sections; sec; sec = sec->next)
2386 +      {
2387 +       Elf_Internal_Rela *relocs;
2388 +       bfd_boolean ret;
2389 +
2390 +       if (!(sec->flags & SEC_RELOC) || sec->reloc_count == 0)
2391 +         continue;
2392 +
2393 +       relocs = retrieve_internal_relocs(abfd, sec, info->keep_memory);
2394 +       if (!relocs)
2395 +         return FALSE;
2396 +
2397 +       ret = allocate_reloc_data(abfd, sec, relocs, info);
2398 +
2399 +       release_internal_relocs(sec, relocs);
2400 +       if (ret == FALSE)
2401 +         return ret;
2402 +      }
2403 +
2404 +  return TRUE;
2405 +}
2406 +
2407 +static bfd_boolean
2408 +rs_is_good_enough(const struct relax_state *rs, struct fragment *frag,
2409 +                 bfd_vma symval, bfd_vma addr, struct got_entry *got,
2410 +                 struct avr32_reloc_data *ind_data,
2411 +                 bfd_signed_vma offset_adjust)
2412 +{
2413 +  bfd_signed_vma target = 0;
2414 +
2415 +  switch (rs->reftype)
2416 +    {
2417 +    case REF_ABSOLUTE:
2418 +      target = symval;
2419 +      break;
2420 +    case REF_PCREL:
2421 +      target = symval - addr;
2422 +      break;
2423 +    case REF_CPOOL:
2424 +      /* cpool frags are always in the same section and always after
2425 +        all frags referring to it.  So it's always correct to add in
2426 +        offset_adjust here.  */
2427 +      target = (ind_data->add_frag->offset + ind_data->add_frag->offset_adjust
2428 +               + offset_adjust - frag->offset - frag->offset_adjust);
2429 +      break;
2430 +    case REF_GOT:
2431 +      target = got->offset;
2432 +      break;
2433 +    default:
2434 +      abort();
2435 +    }
2436 +
2437 +  if (target >= rs->range_min && target <= rs->range_max)
2438 +    return TRUE;
2439 +  else
2440 +    return FALSE;
2441 +}
2442 +
2443 +static bfd_boolean
2444 +avr32_size_frags(bfd *abfd, asection *sec, struct bfd_link_info *info)
2445 +{
2446 +  struct elf_avr32_link_hash_table *htab;
2447 +  struct avr32_relax_data *rd;
2448 +  Elf_Internal_Shdr *symtab_hdr;
2449 +  Elf_Internal_Rela *relocs = NULL;
2450 +  Elf_Internal_Sym *isymbuf = NULL;
2451 +  struct got_entry **local_got_ents;
2452 +  struct fragment **local_sym_frag;
2453 +  bfd_boolean ret = FALSE;
2454 +  bfd_signed_vma delta = 0;
2455 +  unsigned int i;
2456 +
2457 +  htab = avr32_elf_hash_table(info);
2458 +  rd = avr32_relax_data(sec);
2459 +
2460 +  if (sec == htab->sgot)
2461 +    {
2462 +      RDBG("Relaxing GOT section (vma: 0x%lx)\n",
2463 +          sec->output_section->vma + sec->output_offset);
2464 +      if (assign_got_offsets(htab))
2465 +       htab->repeat_pass = TRUE;
2466 +      return TRUE;
2467 +    }
2468 +
2469 +  if (!rd->is_relaxable)
2470 +    return TRUE;
2471 +
2472 +  if (!sec->rawsize)
2473 +    sec->rawsize = sec->size;
2474 +
2475 +  symtab_hdr = &elf_tdata(abfd)->symtab_hdr;
2476 +  relocs = retrieve_internal_relocs(abfd, sec, info->keep_memory);
2477 +  if (!relocs)
2478 +    goto out;
2479 +
2480 +  isymbuf = retrieve_local_syms(abfd, info->keep_memory);
2481 +  if (!isymbuf)
2482 +    goto out;
2483 +
2484 +  local_got_ents = elf_local_got_ents(abfd);
2485 +  local_sym_frag = elf_tdata(abfd)->local_sym_frag;
2486 +
2487 +  RDBG("size_frags: %s<%s>\n  vma: 0x%08lx, size: 0x%08lx\n",
2488 +       abfd->filename, sec->name,
2489 +       sec->output_section->vma + sec->output_offset, sec->size);
2490 +
2491 +  for (i = 0; i < rd->frag_count; i++)
2492 +    {
2493 +      struct fragment *frag = &rd->frag[i];
2494 +      struct avr32_reloc_data *r_data = NULL, *ind_data = NULL;
2495 +      const struct relax_state *state, *next_state;
2496 +      struct fragment *target_frag = NULL;
2497 +      asection *sym_sec = NULL;
2498 +      Elf_Internal_Rela *rela;
2499 +      struct got_entry *got;
2500 +      bfd_vma symval, r_offset, addend, addr;
2501 +      bfd_signed_vma size_adjust = 0, distance;
2502 +      unsigned long r_symndx;
2503 +      bfd_boolean defined = TRUE, dynamic = FALSE;
2504 +      unsigned char sym_type;
2505 +
2506 +      frag->offset_adjust += delta;
2507 +      state = next_state = &relax_state[frag->state];
2508 +      rela = frag->rela;
2509 +
2510 +      BFD_ASSERT(state->id == frag->state);
2511 +
2512 +      RDBG("  0x%04lx%c%d: %s [size %ld]", rela ? rela->r_offset : sec->rawsize,
2513 +          (frag->offset_adjust < 0)?'-':'+',
2514 +          abs(frag->offset_adjust), state->name, state->size);
2515 +
2516 +      if (!rela)
2517 +       {
2518 +         RDBG(": no reloc, ignoring\n");
2519 +         continue;
2520 +       }
2521 +
2522 +      BFD_ASSERT((unsigned int)(rela - relocs) < sec->reloc_count);
2523 +      BFD_ASSERT(state != RS_NONE);
2524 +
2525 +      r_offset = rela->r_offset + frag->offset_adjust;
2526 +      addr = sec->output_section->vma + sec->output_offset + r_offset;
2527 +
2528 +      switch (frag->state)
2529 +       {
2530 +       case RS_ALIGN:
2531 +         size_adjust = ((addr + (1 << rela->r_addend) - 1)
2532 +                        & ~((1 << rela->r_addend) - 1));
2533 +         size_adjust -= (sec->output_section->vma + sec->output_offset
2534 +                         + frag->offset + frag->offset_adjust
2535 +                         + frag->size + frag->size_adjust);
2536 +
2537 +         RDBG(": adjusting size %lu -> %lu\n", frag->size + frag->size_adjust,
2538 +              frag->size + frag->size_adjust + size_adjust);
2539 +         break;
2540 +
2541 +       case RS_CPENT:
2542 +         if (frag->refcount == 0 && frag->size_adjust == 0)
2543 +           {
2544 +             RDBG(": discarding frag\n");
2545 +             size_adjust = -4;
2546 +           }
2547 +         else if (frag->refcount > 0 && frag->size_adjust < 0)
2548 +           {
2549 +             RDBG(": un-discarding frag\n");
2550 +             size_adjust = 4;
2551 +           }
2552 +         break;
2553 +
2554 +       default:
2555 +         if (rd->reloc_data)
2556 +           r_data = &rd->reloc_data[frag->rela - relocs];
2557 +
2558 +         /* If this is a cpool reference, we want the symbol that the
2559 +            cpool entry refers to, not the symbol for the cpool entry
2560 +            itself, as we already know what frag it's in.  */
2561 +         if (relax_state[frag->initial_state].reftype == REF_CPOOL)
2562 +           {
2563 +             Elf_Internal_Rela *irela = r_data->add_frag->rela;
2564 +
2565 +             r_symndx = ELF_R_SYM(irela->r_info);
2566 +             addend = irela->r_addend;
2567 +
2568 +             /* The constant pool must be in the same section as the
2569 +                reloc referring to it.  */
2570 +             BFD_ASSERT((unsigned long)(irela - relocs) < sec->reloc_count);
2571 +
2572 +             ind_data = r_data;
2573 +             r_data = &rd->reloc_data[irela - relocs];
2574 +           }
2575 +         else
2576 +           {
2577 +             r_symndx = ELF_R_SYM(rela->r_info);
2578 +             addend = rela->r_addend;
2579 +           }
2580 +
2581 +         /* Get the value of the symbol referred to by the reloc.  */
2582 +         if (r_symndx < symtab_hdr->sh_info)
2583 +           {
2584 +             Elf_Internal_Sym *isym;
2585 +
2586 +             isym = isymbuf + r_symndx;
2587 +             symval = 0;
2588 +
2589 +             RDBG(" local sym %lu: ", r_symndx);
2590 +
2591 +             if (isym->st_shndx == SHN_UNDEF)
2592 +               defined = FALSE;
2593 +             else if (isym->st_shndx == SHN_ABS)
2594 +               sym_sec = bfd_abs_section_ptr;
2595 +             else if (isym->st_shndx == SHN_COMMON)
2596 +               sym_sec = bfd_com_section_ptr;
2597 +             else
2598 +               sym_sec = bfd_section_from_elf_index(abfd, isym->st_shndx);
2599 +
2600 +             symval = isym->st_value;
2601 +             sym_type = ELF_ST_TYPE(isym->st_info);
2602 +             target_frag = local_sym_frag[r_symndx];
2603 +
2604 +             if (local_got_ents)
2605 +               got = local_got_ents[r_symndx];
2606 +             else
2607 +               got = NULL;
2608 +           }
2609 +         else
2610 +           {
2611 +             /* Global symbol */
2612 +             unsigned long index;
2613 +             struct elf_link_hash_entry *h;
2614 +             struct elf_avr32_link_hash_entry *havr;
2615 +
2616 +             index = r_symndx - symtab_hdr->sh_info;
2617 +             h = elf_sym_hashes(abfd)[index];
2618 +             BFD_ASSERT(h != NULL);
2619 +
2620 +             while (h->root.type == bfd_link_hash_indirect
2621 +                    || h->root.type == bfd_link_hash_warning)
2622 +               h = (struct elf_link_hash_entry *)h->root.u.i.link;
2623 +
2624 +             havr = (struct elf_avr32_link_hash_entry *)h;
2625 +             got = h->got.glist;
2626 +
2627 +             symval = 0;
2628 +
2629 +             RDBG(" %s: ", h->root.root.string);
2630 +
2631 +             if (h->root.type != bfd_link_hash_defined
2632 +                 && h->root.type != bfd_link_hash_defweak)
2633 +               {
2634 +                 RDBG("(undef)");
2635 +                 defined = FALSE;
2636 +               }
2637 +             else if ((info->shared && !info->symbolic && h->dynindx != -1)
2638 +                      || (htab->root.dynamic_sections_created
2639 +                          && h->def_dynamic && !h->def_regular))
2640 +               {
2641 +                 RDBG("(dynamic)");
2642 +                 dynamic = TRUE;
2643 +                 sym_sec = h->root.u.def.section;
2644 +               }
2645 +             else
2646 +               {
2647 +                 sym_sec = h->root.u.def.section;
2648 +                 symval = h->root.u.def.value;
2649 +                 target_frag = havr->sym_frag;
2650 +               }
2651 +
2652 +             sym_type = h->type;
2653 +           }
2654 +
2655 +         /* Thanks to elf32-ppc for this one.  */
2656 +         if (sym_sec && sym_sec->sec_info_type == ELF_INFO_TYPE_MERGE)
2657 +           {
2658 +             /* At this stage in linking, no SEC_MERGE symbol has been
2659 +                adjusted, so all references to such symbols need to be
2660 +                passed through _bfd_merged_section_offset.  (Later, in
2661 +                relocate_section, all SEC_MERGE symbols *except* for
2662 +                section symbols have been adjusted.)
2663 +
2664 +                SEC_MERGE sections are not relaxed by us, as they
2665 +                shouldn't contain any code.  */
2666 +
2667 +             BFD_ASSERT(!target_frag && !(r_data && r_data->add_frag));
2668 +
2669 +             /* gas may reduce relocations against symbols in SEC_MERGE
2670 +                sections to a relocation against the section symbol when
2671 +                the original addend was zero.  When the reloc is against
2672 +                a section symbol we should include the addend in the
2673 +                offset passed to _bfd_merged_section_offset, since the
2674 +                location of interest is the original symbol.  On the
2675 +                other hand, an access to "sym+addend" where "sym" is not
2676 +                a section symbol should not include the addend;  Such an
2677 +                access is presumed to be an offset from "sym";  The
2678 +                location of interest is just "sym".  */
2679 +             RDBG("\n    MERGE: %s: 0x%lx+0x%lx+0x%lx -> ",
2680 +                  (sym_type == STT_SECTION)?"section":"not section",
2681 +                  sym_sec->output_section->vma + sym_sec->output_offset,
2682 +                  symval, addend);
2683 +
2684 +             if (sym_type == STT_SECTION)
2685 +               symval += addend;
2686 +
2687 +             symval = (_bfd_merged_section_offset
2688 +                       (abfd, &sym_sec,
2689 +                        elf_section_data(sym_sec)->sec_info, symval));
2690 +
2691 +             if (sym_type != STT_SECTION)
2692 +               symval += addend;
2693 +           }
2694 +         else
2695 +           symval += addend;
2696 +
2697 +         if (defined && !dynamic)
2698 +           {
2699 +             RDBG("0x%lx+0x%lx",
2700 +                  sym_sec->output_section->vma + sym_sec->output_offset,
2701 +                  symval);
2702 +             symval += sym_sec->output_section->vma + sym_sec->output_offset;
2703 +           }
2704 +
2705 +         if (r_data && r_data->add_frag)
2706 +           /* If the add_frag pointer is set, it means that this reloc
2707 +              has an addend that may be affected by relaxation.  */
2708 +           target_frag = r_data->add_frag;
2709 +
2710 +         if (target_frag)
2711 +           {
2712 +             symval += target_frag->offset_adjust;
2713 +
2714 +             /* If target_frag comes after this frag in the same
2715 +                section, we should assume that it will be moved by
2716 +                the same amount we are.  */
2717 +             if ((target_frag - rd->frag) < (int)rd->frag_count
2718 +                 && target_frag > frag)
2719 +               symval += delta;
2720 +           }
2721 +
2722 +         distance = symval - addr;
2723 +
2724 +         /* First, try to make a direct reference.  If the symbol is
2725 +            dynamic or undefined, we must take care not to change its
2726 +            reference type, that is, we can't make it direct.
2727 +
2728 +            Also, it seems like some sections may actually be resized
2729 +            after the relaxation code is done, so we can't really
2730 +            trust that our "distance" is correct.  There's really no
2731 +            easy solution to this problem, so we'll just disallow
2732 +            direct references to SEC_DATA sections.
2733 +
2734 +            Oh, and .bss isn't actually SEC_DATA, so we disallow
2735 +            !SEC_HAS_CONTENTS as well. */
2736 +         if (!dynamic && defined
2737 +             && (htab->direct_data_refs
2738 +                 || (!(sym_sec->flags & SEC_DATA)
2739 +                     && (sym_sec->flags & SEC_HAS_CONTENTS)))
2740 +             && next_state->direct)
2741 +           {
2742 +             next_state = &relax_state[next_state->direct];
2743 +             RDBG(" D-> %s", next_state->name);
2744 +           }
2745 +
2746 +         /* Iterate backwards until we find a state that fits.  */
2747 +         while (next_state->prev
2748 +                && !rs_is_good_enough(next_state, frag, symval, addr,
2749 +                                      got, ind_data, delta))
2750 +           {
2751 +             next_state = &relax_state[next_state->prev];
2752 +             RDBG(" P-> %s", next_state->name);
2753 +           }
2754 +
2755 +         /* Then try to find the best possible state.  */
2756 +         while (next_state->next)
2757 +           {
2758 +             const struct relax_state *candidate;
2759 +
2760 +             candidate = &relax_state[next_state->next];
2761 +             if (!rs_is_good_enough(candidate, frag, symval, addr, got,
2762 +                                    ind_data, delta))
2763 +               break;
2764 +
2765 +             next_state = candidate;
2766 +             RDBG(" N-> %s", next_state->name);
2767 +           }
2768 +
2769 +         RDBG(" [size %ld]\n", next_state->size);
2770 +
2771 +         BFD_ASSERT(next_state->id);
2772 +         BFD_ASSERT(!dynamic || next_state->reftype == REF_GOT);
2773 +
2774 +         size_adjust = next_state->size - state->size;
2775 +
2776 +         /* There's a theoretical possibility that shrinking one frag
2777 +            may cause another to grow, which may cause the first one to
2778 +            grow as well, and we're back where we started.  Avoid this
2779 +            scenario by disallowing a frag that has grown to ever
2780 +            shrink again.  */
2781 +         if (state->reftype == REF_GOT && next_state->reftype != REF_GOT)
2782 +           {
2783 +             if (frag->has_grown)
2784 +               next_state = state;
2785 +             else
2786 +               unref_got_entry(htab, got);
2787 +           }
2788 +         else if (state->reftype != REF_GOT && next_state->reftype == REF_GOT)
2789 +           {
2790 +             ref_got_entry(htab, got);
2791 +             frag->has_grown = TRUE;
2792 +           }
2793 +         else if (state->reftype == REF_CPOOL
2794 +                  && next_state->reftype != REF_CPOOL)
2795 +           {
2796 +             if (frag->has_grown)
2797 +               next_state = state;
2798 +             else
2799 +               ind_data->add_frag->refcount--;
2800 +           }
2801 +         else if (state->reftype != REF_CPOOL
2802 +                  && next_state->reftype == REF_CPOOL)
2803 +           {
2804 +             ind_data->add_frag->refcount++;
2805 +             frag->has_grown = TRUE;
2806 +           }
2807 +         else
2808 +           {
2809 +             if (frag->has_grown && size_adjust < 0)
2810 +               next_state = state;
2811 +             else if (size_adjust > 0)
2812 +               frag->has_grown = TRUE;
2813 +           }
2814 +
2815 +         size_adjust = next_state->size - state->size;
2816 +         frag->state = next_state->id;
2817 +
2818 +         break;
2819 +       }
2820 +
2821 +      if (size_adjust)
2822 +       htab->repeat_pass = TRUE;
2823 +
2824 +      frag->size_adjust += size_adjust;
2825 +      sec->size += size_adjust;
2826 +      delta += size_adjust;
2827 +
2828 +      BFD_ASSERT((frag->offset + frag->offset_adjust
2829 +                 + frag->size + frag->size_adjust)
2830 +                == (frag[1].offset + frag[1].offset_adjust + delta));
2831 +    }
2832 +
2833 +  ret = TRUE;
2834 +
2835 + out:
2836 +  release_local_syms(abfd, isymbuf);
2837 +  release_internal_relocs(sec, relocs);
2838 +  return ret;
2839 +}
2840 +
2841 +static bfd_boolean
2842 +adjust_global_symbol(struct elf_avr32_link_hash_entry *havr,
2843 +                    struct bfd_link_info *info ATTRIBUTE_UNUSED)
2844 +{
2845 +  struct elf_link_hash_entry *h = &havr->root;
2846 +
2847 +  if (havr->sym_frag && (h->root.type == bfd_link_hash_defined
2848 +                        || h->root.type == bfd_link_hash_defweak))
2849 +    {
2850 +      RDBG("adjust_global_symbol: %s 0x%08lx -> 0x%08lx\n",
2851 +          h->root.root.string, h->root.u.def.value,
2852 +          h->root.u.def.value + havr->sym_frag->offset_adjust);
2853 +      h->root.u.def.value += havr->sym_frag->offset_adjust;
2854 +    }
2855 +  return TRUE;
2856 +}
2857 +
2858 +static bfd_boolean
2859 +adjust_syms(struct bfd_link_info *info)
2860 +{
2861 +  struct elf_avr32_link_hash_table *htab;
2862 +  bfd *abfd;
2863 +
2864 +  htab = avr32_elf_hash_table(info);
2865 +  elf_link_hash_traverse(&htab->root, adjust_global_symbol, info);
2866 +
2867 +  for (abfd = info->input_bfds; abfd; abfd = abfd->link_next)
2868 +    {
2869 +      Elf_Internal_Sym *isymbuf;
2870 +      struct fragment **local_sym_frag, *frag;
2871 +      unsigned int i, sym_count;
2872 +
2873 +      sym_count = elf_tdata(abfd)->symtab_hdr.sh_info;
2874 +      if (sym_count == 0)
2875 +       continue;
2876 +
2877 +      isymbuf = retrieve_local_syms(abfd, info->keep_memory);
2878 +      if (!isymbuf)
2879 +       return FALSE;
2880 +
2881 +      local_sym_frag = elf_tdata(abfd)->local_sym_frag;
2882 +
2883 +      for (i = 0; i < sym_count; i++)
2884 +       {
2885 +         frag = local_sym_frag[i];
2886 +         if (frag)
2887 +           {
2888 +             RDBG("adjust_local_symbol: %s[%u] 0x%08lx -> 0x%08lx\n",
2889 +                  abfd->filename, i, isymbuf[i].st_value,
2890 +                  isymbuf[i].st_value + frag->offset_adjust);
2891 +             isymbuf[i].st_value += frag->offset_adjust;
2892 +           }
2893 +       }
2894 +
2895 +      release_local_syms(abfd, isymbuf);
2896 +    }
2897 +
2898 +  htab->symbols_adjusted = TRUE;
2899 +  return TRUE;
2900 +}
2901 +
2902 +static bfd_boolean
2903 +adjust_relocs(bfd *abfd, asection *sec, struct bfd_link_info *info)
2904 +{
2905 +  struct avr32_relax_data *rd;
2906 +  Elf_Internal_Rela *relocs;
2907 +  Elf_Internal_Shdr *symtab_hdr;
2908 +  unsigned int i;
2909 +  bfd_boolean ret = FALSE;
2910 +
2911 +  rd = avr32_relax_data(sec);
2912 +  if (!rd->reloc_data)
2913 +    return TRUE;
2914 +
2915 +  RDBG("adjust_relocs: %s<%s> (count: %u)\n", abfd->filename, sec->name,
2916 +       sec->reloc_count);
2917 +
2918 +  relocs = retrieve_internal_relocs(abfd, sec, info->keep_memory);
2919 +  if (!relocs)
2920 +    return FALSE;
2921 +
2922 +  symtab_hdr = &elf_tdata(abfd)->symtab_hdr;
2923 +
2924 +  for (i = 0; i < sec->reloc_count; i++)
2925 +    {
2926 +      Elf_Internal_Rela *rela = &relocs[i];
2927 +      struct avr32_reloc_data *r_data = &rd->reloc_data[i];
2928 +      struct fragment *sym_frag;
2929 +      unsigned long r_symndx;
2930 +
2931 +      if (r_data->add_frag)
2932 +       {
2933 +         r_symndx = ELF_R_SYM(rela->r_info);
2934 +
2935 +         if (r_symndx < symtab_hdr->sh_info)
2936 +           sym_frag = elf_tdata(abfd)->local_sym_frag[r_symndx];
2937 +         else
2938 +           {
2939 +             struct elf_link_hash_entry *h;
2940 +
2941 +             h = elf_sym_hashes(abfd)[r_symndx - symtab_hdr->sh_info];
2942 +
2943 +             while (h->root.type == bfd_link_hash_indirect
2944 +                    || h->root.type == bfd_link_hash_warning)
2945 +               h = (struct elf_link_hash_entry *)h->root.u.i.link;
2946 +
2947 +             BFD_ASSERT(h->root.type == bfd_link_hash_defined
2948 +                        || h->root.type == bfd_link_hash_defweak);
2949 +
2950 +             sym_frag = ((struct elf_avr32_link_hash_entry *)h)->sym_frag;
2951 +           }
2952 +
2953 +         RDBG("    addend: 0x%08lx -> 0x%08lx\n",
2954 +              rela->r_addend,
2955 +              rela->r_addend + r_data->add_frag->offset_adjust
2956 +              - (sym_frag ? sym_frag->offset_adjust : 0));
2957 +
2958 +         /* If this is against a section symbol, we won't find any
2959 +            sym_frag, so we'll just adjust the addend.  */
2960 +         rela->r_addend += r_data->add_frag->offset_adjust;
2961 +         if (sym_frag)
2962 +           rela->r_addend -= sym_frag->offset_adjust;
2963 +
2964 +         if (r_data->sub_frag)
2965 +           {
2966 +             bfd_byte *contents;
2967 +             bfd_signed_vma diff;
2968 +
2969 +             contents = retrieve_contents(abfd, sec, info->keep_memory);
2970 +             if (!contents)
2971 +               goto out;
2972 +
2973 +             /* I realize now that sub_frag is misnamed.  It's
2974 +                actually add_frag which is subtracted in this
2975 +                case...  */
2976 +             diff = bfd_get_signed_32(abfd, contents + rela->r_offset);
2977 +             diff += (r_data->sub_frag->offset_adjust
2978 +                      - r_data->add_frag->offset_adjust);
2979 +             bfd_put_32(abfd, diff, contents + rela->r_offset);
2980 +
2981 +             RDBG("   0x%lx: DIFF32 updated: 0x%lx\n", rela->r_offset, diff);
2982 +
2983 +             release_contents(sec, contents);
2984 +           }
2985 +       }
2986 +      else
2987 +       BFD_ASSERT(!r_data->sub_frag);
2988 +    }
2989 +
2990 +  ret = TRUE;
2991 +
2992 + out:
2993 +  release_internal_relocs(sec, relocs);
2994 +  return ret;
2995 +}
2996 +
2997 +static bfd_boolean
2998 +avr32_move_data(bfd *abfd, asection *sec, struct bfd_link_info *info)
2999 +{
3000 +  struct elf_avr32_link_hash_table *htab;
3001 +  struct avr32_relax_data *rd;
3002 +  struct fragment *frag, *fragend;
3003 +  Elf_Internal_Rela *relocs = NULL;
3004 +  bfd_byte *contents = NULL;
3005 +  unsigned int i;
3006 +  bfd_boolean ret = FALSE;
3007 +
3008 +  htab = avr32_elf_hash_table(info);
3009 +  rd = avr32_relax_data(sec);
3010 +
3011 +  if (!htab->symbols_adjusted)
3012 +    if (!adjust_syms(info))
3013 +      return FALSE;
3014 +
3015 +  if (rd->is_relaxable)
3016 +    {
3017 +      /* Resize the section first, so that we can be sure that enough
3018 +        memory is allocated in case the section has grown.  */
3019 +      if (sec->size > sec->rawsize
3020 +         && elf_section_data(sec)->this_hdr.contents)
3021 +       {
3022 +         /* We must not use cached data if the section has grown.  */
3023 +         free(elf_section_data(sec)->this_hdr.contents);
3024 +         elf_section_data(sec)->this_hdr.contents = NULL;
3025 +       }
3026 +
3027 +      relocs = retrieve_internal_relocs(abfd, sec, info->keep_memory);
3028 +      if (!relocs)
3029 +       goto out;
3030 +      contents = retrieve_contents(abfd, sec, info->keep_memory);
3031 +      if (!contents)
3032 +       goto out;
3033 +
3034 +      fragend = rd->frag + rd->frag_count;
3035 +
3036 +      RDBG("move_data: %s<%s>: relocs=%p, contents=%p\n",
3037 +          abfd->filename, sec->name, relocs, contents);
3038 +
3039 +      /* First, move the data into place. We must take care to move
3040 +        frags in the right order so that we don't accidentally
3041 +        overwrite parts of the next frag.  */
3042 +      for (frag = rd->frag; frag < fragend; frag++)
3043 +       {
3044 +         RDBG("    0x%08lx%c0x%x: size 0x%lx%c0x%x\n",
3045 +              frag->offset, frag->offset_adjust >= 0 ? '+' : '-',
3046 +              abs(frag->offset_adjust),
3047 +              frag->size, frag->size_adjust >= 0 ? '+' : '-',
3048 +              abs(frag->size_adjust));
3049 +         if (frag->offset_adjust > 0)
3050 +           {
3051 +             struct fragment *prev = frag - 1;
3052 +             struct fragment *last;
3053 +
3054 +             for (last = frag; last < fragend && last->offset_adjust > 0;
3055 +                  last++) ;
3056 +
3057 +             if (last == fragend)
3058 +               last--;
3059 +
3060 +             for (frag = last; frag != prev; frag--)
3061 +               {
3062 +                 if (frag->offset_adjust
3063 +                     && frag->size + frag->size_adjust > 0)
3064 +                   {
3065 +                     RDBG("memmove 0x%lx -> 0x%lx (size %lu)\n",
3066 +                          frag->offset, frag->offset + frag->offset_adjust,
3067 +                          frag->size + frag->size_adjust);
3068 +                     memmove(contents + frag->offset + frag->offset_adjust,
3069 +                             contents + frag->offset,
3070 +                             frag->size + frag->size_adjust);
3071 +                   }
3072 +               }
3073 +             frag = last;
3074 +           }
3075 +         else if (frag->offset_adjust && frag->size + frag->size_adjust > 0)
3076 +           {
3077 +             RDBG("memmove 0x%lx -> 0x%lx (size %lu)\n",
3078 +                  frag->offset, frag->offset + frag->offset_adjust,
3079 +                  frag->size + frag->size_adjust);
3080 +             memmove(contents + frag->offset + frag->offset_adjust,
3081 +                     contents + frag->offset,
3082 +                     frag->size + frag->size_adjust);
3083 +           }
3084 +       }
3085 +
3086 +      i = 0;
3087 +
3088 +      for (frag = rd->frag; frag < fragend; frag++)
3089 +       {
3090 +         const struct relax_state *state, *istate;
3091 +         struct avr32_reloc_data *r_data = NULL;
3092 +
3093 +         istate = &relax_state[frag->initial_state];
3094 +         state = &relax_state[frag->state];
3095 +
3096 +         if (rd->reloc_data)
3097 +           r_data = &rd->reloc_data[frag->rela - relocs];
3098 +
3099 +         BFD_ASSERT((long)(frag->size + frag->size_adjust) >= 0);
3100 +         BFD_ASSERT(state->reftype != REF_CPOOL
3101 +                    || r_data->add_frag->refcount > 0);
3102 +
3103 +         if (istate->reftype == REF_CPOOL && state->reftype != REF_CPOOL)
3104 +           {
3105 +             struct fragment *ifrag;
3106 +
3107 +             /* An indirect reference through the cpool has been
3108 +                converted to a direct reference.  We must update the
3109 +                reloc to point to the symbol itself instead of the
3110 +                constant pool entry.  The reloc type will be updated
3111 +                later.  */
3112 +             ifrag = r_data->add_frag;
3113 +             frag->rela->r_info = ifrag->rela->r_info;
3114 +             frag->rela->r_addend = ifrag->rela->r_addend;
3115 +
3116 +             /* Copy the reloc data so the addend will be adjusted
3117 +                correctly later.  */
3118 +             *r_data = rd->reloc_data[ifrag->rela - relocs];
3119 +           }
3120 +
3121 +         /* Move all relocs covered by this frag.  */
3122 +         if (frag->rela)
3123 +           BFD_ASSERT(&relocs[i] <= frag->rela);
3124 +         else
3125 +           BFD_ASSERT((frag + 1) == fragend && frag->state == RS_NONE);
3126 +
3127 +         if (frag == rd->frag)
3128 +           BFD_ASSERT(i == 0);
3129 +         else
3130 +           BFD_ASSERT(&relocs[i] > frag[-1].rela);
3131 +
3132 +         /* If non-null, frag->rela is the last relocation in the
3133 +            fragment.  frag->rela can only be null in the last
3134 +            fragment, so in that case, we'll just do the rest.  */
3135 +         for (; (i < sec->reloc_count
3136 +                 && (!frag->rela || &relocs[i] <= frag->rela)); i++)
3137 +           {
3138 +             RDBG("[%4u] r_offset 0x%08lx -> 0x%08lx\n", i, relocs[i].r_offset,
3139 +                  relocs[i].r_offset + frag->offset_adjust);
3140 +             relocs[i].r_offset += frag->offset_adjust;
3141 +           }
3142 +
3143 +         if (frag->refcount == 0)
3144 +           {
3145 +             /* If this frag is to be discarded, make sure we won't
3146 +                relocate it later on.  */
3147 +             BFD_ASSERT(frag->state == RS_CPENT);
3148 +             frag->rela->r_info = ELF_R_INFO(ELF_R_SYM(frag->rela->r_info),
3149 +                                           R_AVR32_NONE);
3150 +           }
3151 +         else if (frag->state == RS_ALIGN)
3152 +           {
3153 +             bfd_vma addr, addr_end;
3154 +
3155 +             addr = frag->rela->r_offset;
3156 +             addr_end = (frag->offset + frag->offset_adjust
3157 +                         + frag->size + frag->size_adjust);
3158 +
3159 +             /* If the section is executable, insert NOPs.
3160 +                Otherwise, insert zeroes.  */
3161 +             if (sec->flags & SEC_CODE)
3162 +               {
3163 +                 if (addr & 1)
3164 +                   {
3165 +                     bfd_put_8(abfd, 0, contents + addr);
3166 +                     addr++;
3167 +                   }
3168 +
3169 +                 BFD_ASSERT(!((addr_end - addr) & 1));
3170 +
3171 +                 while (addr < addr_end)
3172 +                   {
3173 +                     bfd_put_16(abfd, NOP_OPCODE, contents + addr);
3174 +                     addr += 2;
3175 +                   }
3176 +               }
3177 +             else
3178 +               memset(contents + addr, 0, addr_end - addr);
3179 +           }
3180 +         else if (state->opcode_mask)
3181 +           {
3182 +             bfd_vma insn;
3183 +
3184 +             /* Update the opcode and the relocation type unless it's a
3185 +                "special" relax state (i.e. RS_NONE, RS_ALIGN or
3186 +                RS_CPENT.), in which case the opcode mask is zero.  */
3187 +             insn = bfd_get_32(abfd, contents + frag->rela->r_offset);
3188 +             insn &= ~state->opcode_mask;
3189 +             insn |= state->opcode;
3190 +             RDBG("    0x%lx: inserting insn %08lx\n",
3191 +                  frag->rela->r_offset, insn);
3192 +             bfd_put_32(abfd, insn, contents + frag->rela->r_offset);
3193 +
3194 +             frag->rela->r_info = ELF_R_INFO(ELF_R_SYM(frag->rela->r_info),
3195 +                                             state->r_type);
3196 +           }
3197 +
3198 +         if ((frag + 1) == fragend)
3199 +           BFD_ASSERT((frag->offset + frag->size + frag->offset_adjust
3200 +                       + frag->size_adjust) == sec->size);
3201 +         else
3202 +           BFD_ASSERT((frag->offset + frag->size + frag->offset_adjust
3203 +                       + frag->size_adjust)
3204 +                      == (frag[1].offset + frag[1].offset_adjust));
3205 +       }
3206 +    }
3207 +
3208 +  /* Adjust reloc addends and DIFF32 differences */
3209 +  if (!adjust_relocs(abfd, sec, info))
3210 +    return FALSE;
3211 +
3212 +  ret = TRUE;
3213 +
3214 + out:
3215 +  release_contents(sec, contents);
3216 +  release_internal_relocs(sec, relocs);
3217 +  return ret;
3218 +}
3219 +
3220 +static bfd_boolean
3221 +avr32_elf_relax_section(bfd *abfd, asection *sec,
3222 +                       struct bfd_link_info *info, bfd_boolean *again)
3223 +{
3224 +  struct elf_avr32_link_hash_table *htab;
3225 +  struct avr32_relax_data *rd;
3226 +
3227 +  *again = FALSE;
3228 +  if (info->relocatable)
3229 +    return TRUE;
3230 +
3231 +  htab = avr32_elf_hash_table(info);
3232 +  if ((!(sec->flags & SEC_RELOC) || sec->reloc_count == 0)
3233 +      && sec != htab->sgot)
3234 +    return TRUE;
3235 +
3236 +  if (!htab->relocations_analyzed)
3237 +    {
3238 +      if (!analyze_relocations(info))
3239 +       return FALSE;
3240 +      htab->relocations_analyzed = TRUE;
3241 +    }
3242 +
3243 +  rd = avr32_relax_data(sec);
3244 +
3245 +  if (rd->iteration != htab->relax_iteration)
3246 +    {
3247 +      if (!htab->repeat_pass)
3248 +       htab->relax_pass++;
3249 +      htab->relax_iteration++;
3250 +      htab->repeat_pass = FALSE;
3251 +    }
3252 +
3253 +  rd->iteration++;
3254 +
3255 +  switch (htab->relax_pass)
3256 +    {
3257 +    case RELAX_PASS_SIZE_FRAGS:
3258 +      if (!avr32_size_frags(abfd, sec, info))
3259 +       return FALSE;
3260 +      *again = TRUE;
3261 +      break;
3262 +    case RELAX_PASS_MOVE_DATA:
3263 +      if (!avr32_move_data(abfd, sec, info))
3264 +       return FALSE;
3265 +      break;
3266 +  }
3267 +
3268 +  return TRUE;
3269 +}
3270 +
3271 +
3272 +/* Relocation */
3273 +
3274 +static bfd_reloc_status_type
3275 +avr32_check_reloc_value(asection *sec, Elf_Internal_Rela *rela,
3276 +                       bfd_signed_vma relocation, reloc_howto_type *howto);
3277 +static bfd_reloc_status_type
3278 +avr32_final_link_relocate(reloc_howto_type *howto, bfd *input_bfd,
3279 +                         asection *input_section, bfd_byte *contents,
3280 +                         Elf_Internal_Rela *rel, bfd_vma value);
3281 +static bfd_boolean
3282 +avr32_elf_relocate_section(bfd *output_bfd, struct bfd_link_info *info,
3283 +                          bfd *input_bfd, asection *input_section,
3284 +                          bfd_byte *contents, Elf_Internal_Rela *relocs,
3285 +                          Elf_Internal_Sym *local_syms,
3286 +                          asection **local_sections);
3287 +
3288 +
3289 +#define symbol_address(symbol) \
3290 +  symbol->value + symbol->section->output_section->vma \
3291 +  + symbol->section->output_offset
3292 +
3293 +#define avr32_elf_insert_field(size, field, abfd, reloc_entry, data)   \
3294 +  do                                                                   \
3295 +    {                                                                  \
3296 +      unsigned long x;                                                 \
3297 +      x = bfd_get_##size (abfd, data + reloc_entry->address);          \
3298 +      x &= ~reloc_entry->howto->dst_mask;                              \
3299 +      x |= field & reloc_entry->howto->dst_mask;                       \
3300 +      bfd_put_##size (abfd, (bfd_vma) x, data + reloc_entry->address); \
3301 +    }                                                                  \
3302 +  while(0)
3303 +
3304 +static bfd_reloc_status_type
3305 +avr32_check_reloc_value(asection *sec ATTRIBUTE_UNUSED,
3306 +                       Elf_Internal_Rela *rela ATTRIBUTE_UNUSED,
3307 +                       bfd_signed_vma relocation,
3308 +                       reloc_howto_type *howto)
3309 +{
3310 +  bfd_vma reloc_u;
3311 +
3312 +  /* We take "complain_overflow_dont" to mean "don't complain on
3313 +     alignment either". This way, we don't have to special-case
3314 +     R_AVR32_HI16 */
3315 +  if (howto->complain_on_overflow == complain_overflow_dont)
3316 +    return bfd_reloc_ok;
3317 +
3318 +  /* Check if the value is correctly aligned */
3319 +  if (relocation & ((1 << howto->rightshift) - 1))
3320 +    {
3321 +      RDBG("misaligned: %s<%s+%lx>: %s: 0x%lx (align %u)\n",
3322 +          sec->owner->filename, sec->name, rela->r_offset,
3323 +          howto->name, relocation, howto->rightshift);
3324 +      return bfd_reloc_overflow;
3325 +    }
3326 +
3327 +  /* Now, get rid of the unnecessary bits */
3328 +  relocation >>= howto->rightshift;
3329 +  reloc_u = (bfd_vma)relocation;
3330 +
3331 +  switch (howto->complain_on_overflow)
3332 +    {
3333 +    case complain_overflow_unsigned:
3334 +    case complain_overflow_bitfield:
3335 +      if (reloc_u > (unsigned long)((1 << howto->bitsize) - 1))
3336 +       {
3337 +         RDBG("unsigned overflow: %s<%s+%lx>: %s: 0x%lx (size %u)\n",
3338 +              sec->owner->filename, sec->name, rela->r_offset,
3339 +              howto->name, reloc_u, howto->bitsize);
3340 +         RDBG("reloc vma: 0x%lx\n",
3341 +              sec->output_section->vma + sec->output_offset + rela->r_offset);
3342 +
3343 +         return bfd_reloc_overflow;
3344 +       }
3345 +      break;
3346 +    case complain_overflow_signed:
3347 +      if (relocation > (1 << (howto->bitsize - 1)) - 1)
3348 +       {
3349 +         RDBG("signed overflow: %s<%s+%lx>: %s: 0x%lx (size %u)\n",
3350 +              sec->owner->filename, sec->name, rela->r_offset,
3351 +              howto->name, reloc_u, howto->bitsize);
3352 +         RDBG("reloc vma: 0x%lx\n",
3353 +              sec->output_section->vma + sec->output_offset + rela->r_offset);
3354 +
3355 +         return bfd_reloc_overflow;
3356 +       }
3357 +      if (relocation < -(1 << (howto->bitsize - 1)))
3358 +       {
3359 +         RDBG("signed overflow: %s<%s+%lx>: %s: -0x%lx (size %u)\n",
3360 +              sec->owner->filename, sec->name, rela->r_offset,
3361 +              howto->name, -relocation, howto->bitsize);
3362 +         RDBG("reloc vma: 0x%lx\n",
3363 +              sec->output_section->vma + sec->output_offset + rela->r_offset);
3364 +
3365 +         return bfd_reloc_overflow;
3366 +       }
3367 +      break;
3368 +    default:
3369 +      abort();
3370 +    }
3371 +
3372 +  return bfd_reloc_ok;
3373 +}
3374 +
3375 +
3376 +static bfd_reloc_status_type
3377 +avr32_final_link_relocate(reloc_howto_type *howto,
3378 +                         bfd *input_bfd,
3379 +                         asection *input_section,
3380 +                         bfd_byte *contents,
3381 +                         Elf_Internal_Rela *rel,
3382 +                         bfd_vma value)
3383 +{
3384 +  bfd_vma field;
3385 +  bfd_vma relocation;
3386 +  bfd_reloc_status_type status;
3387 +  bfd_byte *p = contents + rel->r_offset;
3388 +  unsigned long x;
3389 +
3390 +  pr_debug("  (6b) final link relocate\n");
3391 +
3392 +  /* Sanity check the address */
3393 +  if (rel->r_offset > input_section->size)
3394 +    {
3395 +      (*_bfd_error_handler)
3396 +       ("%B: %A+0x%lx: offset out of range (section size: 0x%lx)",
3397 +        input_bfd, input_section, rel->r_offset, input_section->size);
3398 +      return bfd_reloc_outofrange;
3399 +    }
3400 +
3401 +  relocation = value + rel->r_addend;
3402 +
3403 +  if (howto->pc_relative)
3404 +    {
3405 +      bfd_vma addr;
3406 +
3407 +      addr = input_section->output_section->vma
3408 +       + input_section->output_offset + rel->r_offset;
3409 +      addr &= ~0UL << howto->rightshift;
3410 +      relocation -= addr;
3411 +    }
3412 +
3413 +  switch (ELF32_R_TYPE(rel->r_info))
3414 +    {
3415 +    case R_AVR32_16N_PCREL:
3416 +      /* sub reg, pc, . - (sym + addend) */
3417 +      relocation = -relocation;
3418 +      break;
3419 +    }
3420 +
3421 +  status = avr32_check_reloc_value(input_section, rel, relocation, howto);
3422 +
3423 +  relocation >>= howto->rightshift;
3424 +  if (howto->bitsize == 21)
3425 +    field = (relocation & 0xffff)
3426 +      | ((relocation & 0x10000) << 4)
3427 +      | ((relocation & 0x1e0000) << 8);
3428 +  else if (howto->bitsize == 12)
3429 +    field = (relocation & 0xff) | ((relocation & 0xf00) << 4);
3430 +  else if (howto->bitsize == 10)
3431 +    field = ((relocation & 0xff) << 4)
3432 +      | ((relocation & 0x300) >> 8);
3433 +  else
3434 +    field = relocation << howto->bitpos;
3435 +
3436 +  switch (howto->size)
3437 +    {
3438 +    case 0:
3439 +      x = bfd_get_8 (input_bfd, p);
3440 +      x &= ~howto->dst_mask;
3441 +      x |= field & howto->dst_mask;
3442 +      bfd_put_8 (input_bfd, (bfd_vma) x, p);
3443 +      break;
3444 +    case 1:
3445 +      x = bfd_get_16 (input_bfd, p);
3446 +      x &= ~howto->dst_mask;
3447 +      x |= field & howto->dst_mask;
3448 +      bfd_put_16 (input_bfd, (bfd_vma) x, p);
3449 +      break;
3450 +    case 2:
3451 +      x = bfd_get_32 (input_bfd, p);
3452 +      x &= ~howto->dst_mask;
3453 +      x |= field & howto->dst_mask;
3454 +      bfd_put_32 (input_bfd, (bfd_vma) x, p);
3455 +      break;
3456 +    default:
3457 +      abort();
3458 +    }
3459 +
3460 +  return status;
3461 +}
3462 +
3463 +/* (6) Apply relocations to the normal (non-dynamic) sections */
3464 +
3465 +static bfd_boolean
3466 +avr32_elf_relocate_section(bfd *output_bfd, struct bfd_link_info *info,
3467 +                          bfd *input_bfd, asection *input_section,
3468 +                          bfd_byte *contents, Elf_Internal_Rela *relocs,
3469 +                          Elf_Internal_Sym *local_syms,
3470 +                          asection **local_sections)
3471 +{
3472 +  struct elf_avr32_link_hash_table *htab;
3473 +  Elf_Internal_Shdr *symtab_hdr;
3474 +  Elf_Internal_Rela *rel, *relend;
3475 +  struct elf_link_hash_entry **sym_hashes;
3476 +  struct got_entry **local_got_ents;
3477 +  asection *sgot;
3478 +  asection *srelgot;
3479 +
3480 +  pr_debug("(6) relocate section %s:<%s> (size 0x%lx)\n",
3481 +          input_bfd->filename, input_section->name, input_section->size);
3482 +
3483 +  /* If we're doing a partial link, we don't have to do anything since
3484 +     we're using RELA relocations */
3485 +  if (info->relocatable)
3486 +    return TRUE;
3487 +
3488 +  htab = avr32_elf_hash_table(info);
3489 +  symtab_hdr = &elf_tdata(input_bfd)->symtab_hdr;
3490 +  sym_hashes = elf_sym_hashes(input_bfd);
3491 +  local_got_ents = elf_local_got_ents(input_bfd);
3492 +  sgot = htab->sgot;
3493 +  srelgot = htab->srelgot;
3494 +
3495 +  relend = relocs + input_section->reloc_count;
3496 +  for (rel = relocs; rel < relend; rel++)
3497 +    {
3498 +      unsigned long r_type, r_symndx;
3499 +      reloc_howto_type *howto;
3500 +      Elf_Internal_Sym *sym = NULL;
3501 +      struct elf_link_hash_entry *h = NULL;
3502 +      asection *sec = NULL;
3503 +      bfd_vma value;
3504 +      bfd_vma offset;
3505 +      bfd_reloc_status_type status;
3506 +
3507 +      r_type = ELF32_R_TYPE(rel->r_info);
3508 +      r_symndx = ELF32_R_SYM(rel->r_info);
3509 +
3510 +      if (r_type == R_AVR32_NONE
3511 +         || r_type == R_AVR32_ALIGN
3512 +         || r_type == R_AVR32_DIFF32
3513 +         || r_type == R_AVR32_DIFF16
3514 +         || r_type == R_AVR32_DIFF8)
3515 +       continue;
3516 +
3517 +      /* Sanity check */
3518 +      if (r_type > R_AVR32_max)
3519 +       {
3520 +         bfd_set_error(bfd_error_bad_value);
3521 +         return FALSE;
3522 +       }
3523 +
3524 +      howto = &elf_avr32_howto_table[r_type];
3525 +
3526 +      if (r_symndx < symtab_hdr->sh_info)
3527 +       {
3528 +         sym = local_syms + r_symndx;
3529 +         sec = local_sections[r_symndx];
3530 +
3531 +         pr_debug("  (6a) processing %s against local symbol %lu\n",
3532 +                  howto->name, r_symndx);
3533 +
3534 +         /* The following function changes rel->r_addend behind our back. */
3535 +         value = _bfd_elf_rela_local_sym(output_bfd, sym, &sec, rel);
3536 +         pr_debug("    => value: %lx, addend: %lx\n", value, rel->r_addend);
3537 +       }
3538 +      else
3539 +       {
3540 +         if (sym_hashes == NULL)
3541 +           return FALSE;
3542 +
3543 +         h = sym_hashes[r_symndx - symtab_hdr->sh_info];
3544 +         while (h->root.type == bfd_link_hash_indirect
3545 +                || h->root.type == bfd_link_hash_warning)
3546 +           h = (struct elf_link_hash_entry *)h->root.u.i.link;
3547 +
3548 +         pr_debug("  (6a) processing %s against symbol %s\n",
3549 +                  howto->name, h->root.root.string);
3550 +
3551 +         if (h->root.type == bfd_link_hash_defined
3552 +             || h->root.type == bfd_link_hash_defweak)
3553 +           {
3554 +             bfd_boolean dyn;
3555 +
3556 +             dyn = htab->root.dynamic_sections_created;
3557 +             sec = h->root.u.def.section;
3558 +
3559 +             if (sec->output_section)
3560 +               value = (h->root.u.def.value
3561 +                        + sec->output_section->vma
3562 +                        + sec->output_offset);
3563 +             else
3564 +               value = h->root.u.def.value;
3565 +           }
3566 +         else if (h->root.type == bfd_link_hash_undefweak)
3567 +           value = 0;
3568 +         else if (info->unresolved_syms_in_objects == RM_IGNORE
3569 +                  && ELF_ST_VISIBILITY(h->other) == STV_DEFAULT)
3570 +           value = 0;
3571 +         else
3572 +           {
3573 +             bfd_boolean err;
3574 +             err = (info->unresolved_syms_in_objects == RM_GENERATE_ERROR
3575 +                    || ELF_ST_VISIBILITY(h->other) != STV_DEFAULT);
3576 +             if (!info->callbacks->undefined_symbol
3577 +                 (info, h->root.root.string, input_bfd,
3578 +                  input_section, rel->r_offset, err))
3579 +               return FALSE;
3580 +             value = 0;
3581 +           }
3582 +
3583 +         pr_debug("    => value: %lx, addend: %lx\n", value, rel->r_addend);
3584 +       }
3585 +
3586 +      switch (r_type)
3587 +       {
3588 +       case R_AVR32_GOT32:
3589 +       case R_AVR32_GOT16:
3590 +       case R_AVR32_GOT8:
3591 +       case R_AVR32_GOT21S:
3592 +       case R_AVR32_GOT18SW:
3593 +       case R_AVR32_GOT16S:
3594 +       case R_AVR32_GOT7UW:
3595 +       case R_AVR32_LDA_GOT:
3596 +       case R_AVR32_GOTCALL:
3597 +         BFD_ASSERT(sgot != NULL);
3598 +
3599 +         if (h != NULL)
3600 +           {
3601 +             BFD_ASSERT(h->got.glist->refcount > 0);
3602 +             offset = h->got.glist->offset;
3603 +
3604 +             BFD_ASSERT(offset < sgot->size);
3605 +             if (!elf_hash_table(info)->dynamic_sections_created
3606 +                 || (h->def_regular
3607 +                     && (!info->shared
3608 +                         || info->symbolic
3609 +                         || h->dynindx == -1)))
3610 +               {
3611 +                 /* This is actually a static link, or it is a
3612 +                    -Bsymbolic link and the symbol is defined
3613 +                    locally, or the symbol was forced to be local.  */
3614 +                 bfd_put_32(output_bfd, value, sgot->contents + offset);
3615 +               }
3616 +           }
3617 +         else
3618 +           {
3619 +             BFD_ASSERT(local_got_ents &&
3620 +                        local_got_ents[r_symndx]->refcount > 0);
3621 +             offset = local_got_ents[r_symndx]->offset;
3622 +
3623 +             /* Local GOT entries don't have relocs.  If this is a
3624 +                shared library, the dynamic linker will add the load
3625 +                address to the initial value at startup.  */
3626 +             BFD_ASSERT(offset < sgot->size);
3627 +             pr_debug("Initializing GOT entry at offset %lu: 0x%lx\n",
3628 +                      offset, value);
3629 +             bfd_put_32 (output_bfd, value, sgot->contents + offset);
3630 +           }
3631 +
3632 +         value = sgot->output_offset + offset;
3633 +         pr_debug("GOT reference: New value %lx\n", value);
3634 +         break;
3635 +
3636 +       case R_AVR32_GOTPC:
3637 +         /* This relocation type is for constant pool entries used in
3638 +            the calculation "Rd = PC - (PC - GOT)", where the
3639 +            constant pool supplies the constant (PC - GOT)
3640 +            offset. The symbol value + addend indicates where the
3641 +            value of PC is taken. */
3642 +         value -= sgot->output_section->vma;
3643 +         break;
3644 +
3645 +       case R_AVR32_32_PCREL:
3646 +         /* We must adjust r_offset to account for discarded data in
3647 +            the .eh_frame section.  This is probably not the right
3648 +            way to do this, since AFAICS all other architectures do
3649 +            it some other way.  I just can't figure out how...  */
3650 +         {
3651 +           bfd_vma r_offset;
3652 +
3653 +           r_offset = _bfd_elf_section_offset(output_bfd, info,
3654 +                                              input_section,
3655 +                                              rel->r_offset);
3656 +           if (r_offset == (bfd_vma)-1
3657 +               || r_offset == (bfd_vma)-2)
3658 +             continue;
3659 +           rel->r_offset = r_offset;
3660 +         }
3661 +         break;
3662 +
3663 +       case R_AVR32_32:
3664 +         /* We need to emit a run-time relocation in the following cases:
3665 +              - we're creating a shared library
3666 +              - the symbol is not defined in any regular objects
3667 +
3668 +            Of course, sections that aren't going to be part of the
3669 +            run-time image will not get any relocs, and undefined
3670 +            symbols won't have any either (only weak undefined
3671 +            symbols should get this far).  */
3672 +         if ((info->shared
3673 +              || (elf_hash_table(info)->dynamic_sections_created
3674 +                  && h != NULL
3675 +                  && h->def_dynamic
3676 +                  && !h->def_regular))
3677 +             && r_symndx != 0
3678 +             && (input_section->flags & SEC_ALLOC))
3679 +           {
3680 +             Elf_Internal_Rela outrel;
3681 +             bfd_byte *loc;
3682 +             bfd_boolean skip, relocate;
3683 +             struct elf_avr32_link_hash_entry *avrh;
3684 +
3685 +             pr_debug("Going to generate dynamic reloc...\n");
3686 +
3687 +             skip = FALSE;
3688 +             relocate = FALSE;
3689 +
3690 +             outrel.r_offset = _bfd_elf_section_offset(output_bfd, info,
3691 +                                                       input_section,
3692 +                                                       rel->r_offset);
3693 +             if (outrel.r_offset == (bfd_vma)-1)
3694 +               skip = TRUE;
3695 +             else if (outrel.r_offset == (bfd_vma)-2)
3696 +               skip = TRUE, relocate = TRUE;
3697 +
3698 +             outrel.r_offset += (input_section->output_section->vma
3699 +                                 + input_section->output_offset);
3700 +
3701 +             pr_debug("    ... offset %lx, dynindx %ld\n",
3702 +                      outrel.r_offset, h ? h->dynindx : -1);
3703 +
3704 +             if (skip)
3705 +               memset(&outrel, 0, sizeof(outrel));
3706 +             else
3707 +               {
3708 +                 avrh = (struct elf_avr32_link_hash_entry *)h;
3709 +                 /* h->dynindx may be -1 if this symbol was marked to
3710 +                    become local.  */
3711 +                 if (h == NULL
3712 +                     || ((info->symbolic || h->dynindx == -1)
3713 +                         && h->def_regular))
3714 +                   {
3715 +                     relocate = TRUE;
3716 +                     outrel.r_info = ELF32_R_INFO(0, R_AVR32_RELATIVE);
3717 +                     outrel.r_addend = value + rel->r_addend;
3718 +                     pr_debug("    ... R_AVR32_RELATIVE\n");
3719 +                   }
3720 +                 else
3721 +                   {
3722 +                     BFD_ASSERT(h->dynindx != -1);
3723 +                     relocate = TRUE;
3724 +                     outrel.r_info = ELF32_R_INFO(h->dynindx, R_AVR32_GLOB_DAT);
3725 +                     outrel.r_addend = rel->r_addend;
3726 +                     pr_debug("    ... R_AVR32_GLOB_DAT\n");
3727 +                   }
3728 +               }
3729 +
3730 +             pr_debug("srelgot reloc_count: %d, size %lu\n",
3731 +                      srelgot->reloc_count, srelgot->size);
3732 +
3733 +             loc = srelgot->contents;
3734 +             loc += srelgot->reloc_count++ * sizeof(Elf32_External_Rela);
3735 +             bfd_elf32_swap_reloca_out(output_bfd, &outrel, loc);
3736 +
3737 +             BFD_ASSERT(srelgot->reloc_count * sizeof(Elf32_External_Rela)
3738 +                        <= srelgot->size);
3739 +
3740 +             if (!relocate)
3741 +               continue;
3742 +           }
3743 +         break;
3744 +       }
3745 +
3746 +      status = avr32_final_link_relocate(howto, input_bfd, input_section,
3747 +                                        contents, rel, value);
3748 +
3749 +      switch (status)
3750 +       {
3751 +       case bfd_reloc_ok:
3752 +         break;
3753 +
3754 +       case bfd_reloc_overflow:
3755 +         {
3756 +           const char *name;
3757 +
3758 +           if (h != NULL)
3759 +             name = h->root.root.string;
3760 +           else
3761 +             {
3762 +               name = bfd_elf_string_from_elf_section(input_bfd,
3763 +                                                      symtab_hdr->sh_link,
3764 +                                                      sym->st_name);
3765 +               if (name == NULL)
3766 +                 return FALSE;
3767 +               if (*name == '\0')
3768 +                 name = bfd_section_name(input_bfd, sec);
3769 +             }
3770 +           if (!((*info->callbacks->reloc_overflow)
3771 +                 (info, (h ? &h->root : NULL), name, howto->name,
3772 +                  rel->r_addend, input_bfd, input_section, rel->r_offset)))
3773 +             return FALSE;
3774 +         }
3775 +         break;
3776 +
3777 +       case bfd_reloc_outofrange:
3778 +       default:
3779 +         abort();
3780 +       }
3781 +    }
3782 +
3783 +  return TRUE;
3784 +}
3785 +
3786 +
3787 +/* Additional processing of dynamic sections after relocation */
3788 +
3789 +static bfd_boolean
3790 +avr32_elf_finish_dynamic_symbol(bfd *output_bfd, struct bfd_link_info *info,
3791 +                               struct elf_link_hash_entry *h,
3792 +                               Elf_Internal_Sym *sym);
3793 +static bfd_boolean
3794 +avr32_elf_finish_dynamic_sections(bfd *output_bfd, struct bfd_link_info *info);
3795 +
3796 +
3797 +/* (7) Initialize the contents of a dynamic symbol and/or emit
3798 +   relocations for it */
3799 +
3800 +static bfd_boolean
3801 +avr32_elf_finish_dynamic_symbol(bfd *output_bfd, struct bfd_link_info *info,
3802 +                               struct elf_link_hash_entry *h,
3803 +                               Elf_Internal_Sym *sym)
3804 +{
3805 +  struct elf_avr32_link_hash_table *htab;
3806 +  struct got_entry *got;
3807 +
3808 +  pr_debug("(7) finish dynamic symbol: %s\n", h->root.root.string);
3809 +
3810 +  htab = avr32_elf_hash_table(info);
3811 +  got = h->got.glist;
3812 +
3813 +  if (got && got->refcount > 0)
3814 +    {
3815 +      asection *sgot;
3816 +      asection *srelgot;
3817 +      Elf_Internal_Rela rel;
3818 +      bfd_byte *loc;
3819 +
3820 +      /* This symbol has an entry in the GOT. Set it up. */
3821 +      sgot = htab->sgot;
3822 +      srelgot = htab->srelgot;
3823 +      BFD_ASSERT(sgot && srelgot);
3824 +
3825 +      rel.r_offset = (sgot->output_section->vma
3826 +                     + sgot->output_offset
3827 +                     + got->offset);
3828 +
3829 +      /* If this is a static link, or it is a -Bsymbolic link and the
3830 +        symbol is defined locally or was forced to be local because
3831 +        of a version file, we just want to emit a RELATIVE reloc. The
3832 +        entry in the global offset table will already have been
3833 +        initialized in the relocate_section function. */
3834 +      if ((info->shared
3835 +          && !info->symbolic
3836 +          && h->dynindx != -1)
3837 +         || (htab->root.dynamic_sections_created
3838 +             && h->def_dynamic
3839 +             && !h->def_regular))
3840 +       {
3841 +         bfd_put_32(output_bfd, 0, sgot->contents + got->offset);
3842 +         rel.r_info = ELF32_R_INFO(h->dynindx, R_AVR32_GLOB_DAT);
3843 +         rel.r_addend = 0;
3844 +
3845 +         pr_debug("GOT reloc R_AVR32_GLOB_DAT, dynindx: %ld\n", h->dynindx);
3846 +         pr_debug("    srelgot reloc_count: %d, size: %lu\n",
3847 +                  srelgot->reloc_count, srelgot->size);
3848 +
3849 +         loc = (srelgot->contents
3850 +                + srelgot->reloc_count++ * sizeof(Elf32_External_Rela));
3851 +         bfd_elf32_swap_reloca_out(output_bfd, &rel, loc);
3852 +
3853 +         BFD_ASSERT(srelgot->reloc_count * sizeof(Elf32_External_Rela)
3854 +                    <= srelgot->size);
3855 +       }
3856 +    }
3857 +
3858 +  /* Mark _DYNAMIC and _GLOBAL_OFFSET_TABLE_ as absolute */
3859 +  if (strcmp(h->root.root.string, "_DYNAMIC") == 0
3860 +      || strcmp(h->root.root.string, "_GLOBAL_OFFSET_TABLE_") == 0)
3861 +    sym->st_shndx = SHN_ABS;
3862 +
3863 +  return TRUE;
3864 +}
3865 +
3866 +/* (8) Do any remaining initialization of the dynamic sections */
3867 +
3868 +static bfd_boolean
3869 +avr32_elf_finish_dynamic_sections(bfd *output_bfd, struct bfd_link_info *info)
3870 +{
3871 +  struct elf_avr32_link_hash_table *htab;
3872 +  asection *sgot, *sdyn;
3873 +
3874 +  pr_debug("(8) finish dynamic sections\n");
3875 +
3876 +  htab = avr32_elf_hash_table(info);
3877 +  sgot = htab->sgot;
3878 +  sdyn = bfd_get_section_by_name(htab->root.dynobj, ".dynamic");
3879 +
3880 +  if (htab->root.dynamic_sections_created)
3881 +    {
3882 +      Elf32_External_Dyn *dyncon, *dynconend;
3883 +
3884 +      BFD_ASSERT(sdyn && sgot && sgot->size >= AVR32_GOT_HEADER_SIZE);
3885 +
3886 +      dyncon = (Elf32_External_Dyn *)sdyn->contents;
3887 +      dynconend = (Elf32_External_Dyn *)(sdyn->contents + sdyn->size);
3888 +      for (; dyncon < dynconend; dyncon++)
3889 +       {
3890 +         Elf_Internal_Dyn dyn;
3891 +         asection *s;
3892 +
3893 +         bfd_elf32_swap_dyn_in(htab->root.dynobj, dyncon, &dyn);
3894 +
3895 +         switch (dyn.d_tag)
3896 +           {
3897 +           default:
3898 +             break;
3899 +
3900 +           case DT_PLTGOT:
3901 +             s = sgot->output_section;
3902 +             BFD_ASSERT(s != NULL);
3903 +             dyn.d_un.d_ptr = s->vma;
3904 +             bfd_elf32_swap_dyn_out(output_bfd, &dyn, dyncon);
3905 +             break;
3906 +
3907 +           case DT_AVR32_GOTSZ:
3908 +             s = sgot->output_section;
3909 +             BFD_ASSERT(s != NULL);
3910 +             dyn.d_un.d_val = s->size;
3911 +             bfd_elf32_swap_dyn_out(output_bfd, &dyn, dyncon);
3912 +             break;
3913 +           }
3914 +       }
3915 +
3916 +      /* Fill in the first two entries in the global offset table */
3917 +      bfd_put_32(output_bfd,
3918 +                sdyn->output_section->vma + sdyn->output_offset,
3919 +                sgot->contents);
3920 +
3921 +      /* The runtime linker will fill this one in with the address of
3922 +        the run-time link map */
3923 +      bfd_put_32(output_bfd, 0, sgot->contents + 4);
3924 +    }
3925 +
3926 +  if (sgot)
3927 +    elf_section_data(sgot->output_section)->this_hdr.sh_entsize = 4;
3928 +
3929 +  return TRUE;
3930 +}
3931 +
3932 +
3933 +/* AVR32-specific private ELF data */
3934 +
3935 +static bfd_boolean
3936 +avr32_elf_set_private_flags(bfd *abfd, flagword flags);
3937 +static bfd_boolean
3938 +avr32_elf_copy_private_bfd_data(bfd *ibfd, bfd *obfd);
3939 +static bfd_boolean
3940 +avr32_elf_merge_private_bfd_data(bfd *ibfd, bfd *obfd);
3941 +static bfd_boolean
3942 +avr32_elf_print_private_bfd_data(bfd *abfd, void *ptr);
3943 +
3944 +static bfd_boolean
3945 +avr32_elf_set_private_flags(bfd *abfd, flagword flags)
3946 +{
3947 +  elf_elfheader(abfd)->e_flags = flags;
3948 +  elf_flags_init(abfd) = TRUE;
3949 +
3950 +  return TRUE;
3951 +}
3952 +
3953 +/* Copy backend specific data from one object module to another.  */
3954 +
3955 +static bfd_boolean
3956 +avr32_elf_copy_private_bfd_data(bfd *ibfd, bfd *obfd)
3957 +{
3958 +  elf_elfheader(obfd)->e_flags = elf_elfheader(ibfd)->e_flags;
3959 +  return TRUE;
3960 +}
3961 +
3962 +/* Merge backend specific data from an object file to the output
3963 +   object file when linking.  */
3964 +
3965 +static bfd_boolean
3966 +avr32_elf_merge_private_bfd_data(bfd *ibfd, bfd *obfd)
3967 +{
3968 +  flagword out_flags, in_flags;
3969 +
3970 +  pr_debug("(0) merge_private_bfd_data: %s -> %s\n",
3971 +          ibfd->filename, obfd->filename);
3972 +
3973 +  in_flags = elf_elfheader(ibfd)->e_flags;
3974 +  out_flags = elf_elfheader(obfd)->e_flags;
3975 +
3976 +  if (elf_flags_init(obfd))
3977 +    {
3978 +      /* If one of the inputs are non-PIC, the output must be
3979 +        considered non-PIC.  The same applies to linkrelax.  */
3980 +      if (!(in_flags & EF_AVR32_PIC))
3981 +       out_flags &= ~EF_AVR32_PIC;
3982 +      if (!(in_flags & EF_AVR32_LINKRELAX))
3983 +       out_flags &= ~EF_AVR32_LINKRELAX;
3984 +    }
3985 +  else
3986 +    {
3987 +      elf_flags_init(obfd) = TRUE;
3988 +      out_flags = in_flags;
3989 +    }
3990 +
3991 +  elf_elfheader(obfd)->e_flags = out_flags;
3992 +
3993 +  return TRUE;
3994 +}
3995 +
3996 +static bfd_boolean
3997 +avr32_elf_print_private_bfd_data(bfd *abfd, void *ptr)
3998 +{
3999 +  FILE *file = (FILE *)ptr;
4000 +  unsigned long flags;
4001 +
4002 +  BFD_ASSERT(abfd != NULL && ptr != NULL);
4003 +
4004 +  _bfd_elf_print_private_bfd_data(abfd, ptr);
4005 +
4006 +  flags = elf_elfheader(abfd)->e_flags;
4007 +
4008 +  fprintf(file, _("private flags = %lx:"), elf_elfheader(abfd)->e_flags);
4009 +
4010 +  if (flags & EF_AVR32_PIC)
4011 +    fprintf(file, " [PIC]");
4012 +  if (flags & EF_AVR32_LINKRELAX)
4013 +    fprintf(file, " [linker relaxable]");
4014 +
4015 +  flags &= ~(EF_AVR32_PIC | EF_AVR32_LINKRELAX);
4016 +
4017 +  if (flags)
4018 +    fprintf(file, _("<Unrecognized flag bits set>"));
4019 +
4020 +  fputc('\n', file);
4021 +
4022 +  return TRUE;
4023 +}
4024 +
4025 +/* Set avr32-specific linker options.  */
4026 +void bfd_elf32_avr32_set_options(struct bfd_link_info *info,
4027 +                                int direct_data_refs)
4028 +{
4029 +  struct elf_avr32_link_hash_table *htab;
4030 +
4031 +  htab = avr32_elf_hash_table (info);
4032 +  htab->direct_data_refs = !!direct_data_refs;
4033 +}
4034 +
4035 +
4036 +
4037 +/* Understanding core dumps */
4038 +
4039 +static bfd_boolean
4040 +avr32_elf_grok_prstatus(bfd *abfd, Elf_Internal_Note *note);
4041 +static bfd_boolean
4042 +avr32_elf_grok_psinfo(bfd *abfd, Elf_Internal_Note *note);
4043 +
4044 +static bfd_boolean
4045 +avr32_elf_grok_prstatus(bfd *abfd, Elf_Internal_Note *note)
4046 +{
4047 +  /* Linux/AVR32B elf_prstatus */
4048 +  if (note->descsz != 148)
4049 +    return FALSE;
4050 +
4051 +  /* pr_cursig */
4052 +  elf_tdata(abfd)->core_signal = bfd_get_16(abfd, note->descdata + 12);
4053 +
4054 +  /* pr_pid */
4055 +  elf_tdata(abfd)->core_pid = bfd_get_32(abfd, note->descdata + 24);
4056 +
4057 +  /* Make a ".reg/999" section for pr_reg. The size is for 16
4058 +     general-purpose registers, SR and r12_orig (18 * 4 = 72).  */
4059 +  return _bfd_elfcore_make_pseudosection(abfd, ".reg", 72,
4060 +                                        note->descpos + 72);
4061 +}
4062 +
4063 +static bfd_boolean
4064 +avr32_elf_grok_psinfo(bfd *abfd, Elf_Internal_Note *note)
4065 +{
4066 +  /* Linux/AVR32B elf_prpsinfo */
4067 +  if (note->descsz != 128)
4068 +    return FALSE;
4069 +
4070 +  elf_tdata(abfd)->core_program
4071 +    = _bfd_elfcore_strndup(abfd, note->descdata + 32, 16);
4072 +  elf_tdata(abfd)->core_command
4073 +    = _bfd_elfcore_strndup(abfd, note->descdata + 48, 80);
4074 +
4075 +  /* Note that for some reason, a spurious space is tacked
4076 +     onto the end of the args in some (at least one anyway)
4077 +     implementations, so strip it off if it exists.  */
4078 +
4079 +  {
4080 +    char *command = elf_tdata (abfd)->core_command;
4081 +    int n = strlen (command);
4082 +
4083 +    if (0 < n && command[n - 1] == ' ')
4084 +      command[n - 1] = '\0';
4085 +  }
4086 +
4087 +  return TRUE;
4088 +}
4089 +
4090 +
4091 +#define ELF_ARCH                       bfd_arch_avr32
4092 +#define ELF_MACHINE_CODE               EM_AVR32
4093 +#define ELF_MAXPAGESIZE                        1024
4094 +
4095 +#define TARGET_BIG_SYM                 bfd_elf32_avr32_vec
4096 +#define TARGET_BIG_NAME                        "elf32-avr32"
4097 +
4098 +#define elf_backend_grok_prstatus      avr32_elf_grok_prstatus
4099 +#define elf_backend_grok_psinfo                avr32_elf_grok_psinfo
4100 +
4101 +/* Only RELA relocations are used */
4102 +#define elf_backend_may_use_rel_p      0
4103 +#define elf_backend_may_use_rela_p     1
4104 +#define elf_backend_default_use_rela_p 1
4105 +#define elf_backend_rela_normal                1
4106 +#define elf_info_to_howto_rel          NULL
4107 +#define elf_info_to_howto              avr32_info_to_howto
4108 +
4109 +#define bfd_elf32_bfd_copy_private_bfd_data    avr32_elf_copy_private_bfd_data
4110 +#define bfd_elf32_bfd_merge_private_bfd_data   avr32_elf_merge_private_bfd_data
4111 +#define bfd_elf32_bfd_set_private_flags                avr32_elf_set_private_flags
4112 +#define bfd_elf32_bfd_print_private_bfd_data   avr32_elf_print_private_bfd_data
4113 +#define bfd_elf32_new_section_hook             avr32_elf_new_section_hook
4114 +
4115 +#define elf_backend_gc_mark_hook               avr32_elf_gc_mark_hook
4116 +#define elf_backend_gc_sweep_hook              avr32_elf_gc_sweep_hook
4117 +#define elf_backend_relocate_section   avr32_elf_relocate_section
4118 +#define elf_backend_copy_indirect_symbol avr32_elf_copy_indirect_symbol
4119 +#define elf_backend_create_dynamic_sections avr32_elf_create_dynamic_sections
4120 +#define bfd_elf32_bfd_link_hash_table_create avr32_elf_link_hash_table_create
4121 +#define elf_backend_adjust_dynamic_symbol avr32_elf_adjust_dynamic_symbol
4122 +#define elf_backend_size_dynamic_sections avr32_elf_size_dynamic_sections
4123 +#define elf_backend_finish_dynamic_symbol avr32_elf_finish_dynamic_symbol
4124 +#define elf_backend_finish_dynamic_sections avr32_elf_finish_dynamic_sections
4125 +
4126 +#define bfd_elf32_bfd_relax_section    avr32_elf_relax_section
4127 +
4128 +/* Find out which symbols need an entry in .got. */
4129 +#define elf_backend_check_relocs       avr32_check_relocs
4130 +#define elf_backend_can_refcount       1
4131 +#define elf_backend_can_gc_sections    1
4132 +#define elf_backend_plt_readonly       1
4133 +#define elf_backend_plt_not_loaded     1
4134 +#define elf_backend_want_plt_sym       0
4135 +#define elf_backend_plt_alignment      2
4136 +#define elf_backend_want_dynbss                0
4137 +#define elf_backend_want_got_plt       0
4138 +#define elf_backend_want_got_sym       1
4139 +#define elf_backend_got_header_size    AVR32_GOT_HEADER_SIZE
4140 +
4141 +#include "elf32-target.h"
4142 --- /dev/null
4143 +++ b/bfd/elf32-avr32.h
4144 @@ -0,0 +1,23 @@
4145 +/* AVR32-specific support for 32-bit ELF.
4146 +   Copyright 2007,2008,2009 Atmel Corporation.
4147 +
4148 +   Written by Haavard Skinnemoen, Atmel Norway, <hskinnemoen@atmel.com>
4149 +
4150 +   This file is part of BFD, the Binary File Descriptor library.
4151 +
4152 +   This program is free software; you can redistribute it and/or modify
4153 +   it under the terms of the GNU General Public License as published by
4154 +   the Free Software Foundation; either version 2 of the License, or
4155 +   (at your option) any later version.
4156 +
4157 +   This program is distributed in the hope that it will be useful,
4158 +   but WITHOUT ANY WARRANTY; without even the implied warranty of
4159 +   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
4160 +   GNU General Public License for more details.
4161 +
4162 +   You should have received a copy of the GNU General Public License
4163 +   along with this program; if not, write to the Free Software
4164 +   Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
4165 +
4166 +void bfd_elf32_avr32_set_options(struct bfd_link_info *info,
4167 +                                int direct_data_refs);
4168 --- a/bfd/elf-bfd.h
4169 +++ b/bfd/elf-bfd.h
4170 @@ -1498,6 +1498,10 @@ struct elf_obj_tdata
4171       find_nearest_line.  */
4172    struct mips_elf_find_line *find_line_info;
4173
4174 +  /* Used by AVR32 ELF relaxation code.  Contains an array of pointers
4175 +     for each local symbol to the fragment where it is defined.  */
4176 +  struct fragment **local_sym_frag;
4177 +
4178    /* A place to stash dwarf1 info for this bfd.  */
4179    struct dwarf1_debug *dwarf1_find_line_info;
4180
4181 --- a/bfd/libbfd.h
4182 +++ b/bfd/libbfd.h
4183 @@ -1614,6 +1614,48 @@ static const char *const bfd_reloc_code_
4184    "BFD_RELOC_AVR_LDI",
4185    "BFD_RELOC_AVR_6",
4186    "BFD_RELOC_AVR_6_ADIW",
4187 +  "BFD_RELOC_AVR32_DIFF32",
4188 +  "BFD_RELOC_AVR32_DIFF16",
4189 +  "BFD_RELOC_AVR32_DIFF8",
4190 +  "BFD_RELOC_AVR32_GOT32",
4191 +  "BFD_RELOC_AVR32_GOT16",
4192 +  "BFD_RELOC_AVR32_GOT8",
4193 +  "BFD_RELOC_AVR32_21S",
4194 +  "BFD_RELOC_AVR32_16U",
4195 +  "BFD_RELOC_AVR32_16S",
4196 +  "BFD_RELOC_AVR32_SUB5",
4197 +  "BFD_RELOC_AVR32_8S_EXT",
4198 +  "BFD_RELOC_AVR32_8S",
4199 +  "BFD_RELOC_AVR32_15S",
4200 +  "BFD_RELOC_AVR32_22H_PCREL",
4201 +  "BFD_RELOC_AVR32_18W_PCREL",
4202 +  "BFD_RELOC_AVR32_16B_PCREL",
4203 +  "BFD_RELOC_AVR32_16N_PCREL",
4204 +  "BFD_RELOC_AVR32_14UW_PCREL",
4205 +  "BFD_RELOC_AVR32_11H_PCREL",
4206 +  "BFD_RELOC_AVR32_10UW_PCREL",
4207 +  "BFD_RELOC_AVR32_9H_PCREL",
4208 +  "BFD_RELOC_AVR32_9UW_PCREL",
4209 +  "BFD_RELOC_AVR32_GOTPC",
4210 +  "BFD_RELOC_AVR32_GOTCALL",
4211 +  "BFD_RELOC_AVR32_LDA_GOT",
4212 +  "BFD_RELOC_AVR32_GOT21S",
4213 +  "BFD_RELOC_AVR32_GOT18SW",
4214 +  "BFD_RELOC_AVR32_GOT16S",
4215 +  "BFD_RELOC_AVR32_32_CPENT",
4216 +  "BFD_RELOC_AVR32_CPCALL",
4217 +  "BFD_RELOC_AVR32_16_CP",
4218 +  "BFD_RELOC_AVR32_9W_CP",
4219 +  "BFD_RELOC_AVR32_ALIGN",
4220 +  "BFD_RELOC_AVR32_14UW",
4221 +  "BFD_RELOC_AVR32_10UW",
4222 +  "BFD_RELOC_AVR32_10SW",
4223 +  "BFD_RELOC_AVR32_STHH_W",
4224 +  "BFD_RELOC_AVR32_7UW",
4225 +  "BFD_RELOC_AVR32_6S",
4226 +  "BFD_RELOC_AVR32_6UW",
4227 +  "BFD_RELOC_AVR32_4UH",
4228 +  "BFD_RELOC_AVR32_3U",
4229    "BFD_RELOC_390_12",
4230    "BFD_RELOC_390_GOT12",
4231    "BFD_RELOC_390_PLT32",
4232 --- a/bfd/Makefile.am
4233 +++ b/bfd/Makefile.am
4234 @@ -63,6 +63,7 @@ ALL_MACHINES = \
4235         cpu-arc.lo \
4236         cpu-arm.lo \
4237         cpu-avr.lo \
4238 +       cpu-avr32.lo \
4239         cpu-bfin.lo \
4240         cpu-cr16.lo \
4241         cpu-cr16c.lo \
4242 @@ -247,6 +248,7 @@ BFD32_BACKENDS = \
4243         elf32-arc.lo \
4244         elf32-arm.lo \
4245         elf32-avr.lo \
4246 +       elf32-avr32.lo \
4247         elf32-bfin.lo \
4248         elf32-cr16.lo \
4249         elf32-cr16c.lo \
4250 @@ -1355,6 +1357,10 @@ elf32-cr16.lo: elf32-cr16.c $(INCDIR)/fi
4251    $(INCDIR)/hashtab.h $(INCDIR)/libiberty.h elf-bfd.h \
4252    $(INCDIR)/elf/common.h $(INCDIR)/elf/external.h $(INCDIR)/elf/internal.h \
4253    $(INCDIR)/elf/cr16.h $(INCDIR)/elf/reloc-macros.h elf32-target.h
4254 +elf32-avr32.lo: elf32-avr32.c $(INCDIR)/filenames.h elf-bfd.h \
4255 +  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
4256 +  $(INCDIR)/bfdlink.h $(INCDIR)/elf/avr32.h $(INCDIR)/elf/reloc-macros.h \
4257 +  elf32-target.h
4258  elf32-cr16c.lo: elf32-cr16c.c $(INCDIR)/filenames.h \
4259    $(INCDIR)/hashtab.h $(INCDIR)/bfdlink.h $(INCDIR)/elf/cr16c.h \
4260    $(INCDIR)/elf/reloc-macros.h elf-bfd.h $(INCDIR)/elf/common.h \
4261 --- a/bfd/Makefile.in
4262 +++ b/bfd/Makefile.in
4263 @@ -316,6 +316,7 @@ ALL_MACHINES = \
4264         cpu-arc.lo \
4265         cpu-arm.lo \
4266         cpu-avr.lo \
4267 +       cpu-avr32.lo \
4268         cpu-bfin.lo \
4269         cpu-cr16.lo \
4270         cpu-cr16c.lo \
4271 @@ -501,6 +502,7 @@ BFD32_BACKENDS = \
4272         elf32-arc.lo \
4273         elf32-arm.lo \
4274         elf32-avr.lo \
4275 +       elf32-avr32.lo \
4276         elf32-bfin.lo \
4277         elf32-cr16.lo \
4278         elf32-cr16c.lo \
4279 @@ -1939,6 +1941,10 @@ elf32-cr16.lo: elf32-cr16.c $(INCDIR)/fi
4280    $(INCDIR)/hashtab.h $(INCDIR)/libiberty.h elf-bfd.h \
4281    $(INCDIR)/elf/common.h $(INCDIR)/elf/external.h $(INCDIR)/elf/internal.h \
4282    $(INCDIR)/elf/cr16.h $(INCDIR)/elf/reloc-macros.h elf32-target.h
4283 +elf32-avr32.lo: elf32-avr32.c $(INCDIR)/filenames.h elf-bfd.h \
4284 +  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
4285 +  $(INCDIR)/bfdlink.h $(INCDIR)/elf/avr32.h $(INCDIR)/elf/reloc-macros.h \
4286 +  elf32-target.h
4287  elf32-cr16c.lo: elf32-cr16c.c $(INCDIR)/filenames.h \
4288    $(INCDIR)/hashtab.h $(INCDIR)/bfdlink.h $(INCDIR)/elf/cr16c.h \
4289    $(INCDIR)/elf/reloc-macros.h elf-bfd.h $(INCDIR)/elf/common.h \
4290 --- a/bfd/reloc.c
4291 +++ b/bfd/reloc.c
4292 @@ -3982,6 +3982,131 @@ ENUMDOC
4293    instructions
4294
4295  ENUM
4296 +  BFD_RELOC_AVR32_DIFF32
4297 +ENUMX
4298 +  BFD_RELOC_AVR32_DIFF16
4299 +ENUMX
4300 +  BFD_RELOC_AVR32_DIFF8
4301 +ENUMDOC
4302 +  Difference between two labels: L2 - L1. The value of L1 is encoded
4303 +  as sym + addend, while the initial difference after assembly is
4304 +  inserted into the object file by the assembler.
4305 +ENUM
4306 +  BFD_RELOC_AVR32_GOT32
4307 +ENUMX
4308 +  BFD_RELOC_AVR32_GOT16
4309 +ENUMX
4310 +  BFD_RELOC_AVR32_GOT8
4311 +ENUMDOC
4312 +  Reference to a symbol through the Global Offset Table. The linker
4313 +  will allocate an entry for symbol in the GOT and insert the offset
4314 +  of this entry as the relocation value.
4315 +ENUM
4316 +  BFD_RELOC_AVR32_21S
4317 +ENUMX
4318 +  BFD_RELOC_AVR32_16U
4319 +ENUMX
4320 +  BFD_RELOC_AVR32_16S
4321 +ENUMX
4322 +  BFD_RELOC_AVR32_SUB5
4323 +ENUMX
4324 +  BFD_RELOC_AVR32_8S_EXT
4325 +ENUMX
4326 +  BFD_RELOC_AVR32_8S
4327 +ENUMX
4328 +  BFD_RELOC_AVR32_15S
4329 +ENUMDOC
4330 +  Normal (non-pc-relative) code relocations. Alignment and signedness
4331 +  is indicated by the suffixes. S means signed, U means unsigned. W
4332 +  means word-aligned, H means halfword-aligned, neither means
4333 +  byte-aligned (no alignment.) SUB5 is the same relocation as 16S.
4334 +ENUM
4335 +  BFD_RELOC_AVR32_22H_PCREL
4336 +ENUMX
4337 +  BFD_RELOC_AVR32_18W_PCREL
4338 +ENUMX
4339 +  BFD_RELOC_AVR32_16B_PCREL
4340 +ENUMX
4341 +  BFD_RELOC_AVR32_16N_PCREL
4342 +ENUMX
4343 +  BFD_RELOC_AVR32_14UW_PCREL
4344 +ENUMX
4345 +  BFD_RELOC_AVR32_11H_PCREL
4346 +ENUMX
4347 +  BFD_RELOC_AVR32_10UW_PCREL
4348 +ENUMX
4349 +  BFD_RELOC_AVR32_9H_PCREL
4350 +ENUMX
4351 +  BFD_RELOC_AVR32_9UW_PCREL
4352 +ENUMDOC
4353 +  PC-relative relocations are signed if neither 'U' nor 'S' is
4354 +  specified. However, we explicitly tack on a 'B' to indicate no
4355 +  alignment, to avoid confusion with data relocs. All of these resolve
4356 +  to sym + addend - offset, except the one with 'N' (negated) suffix.
4357 +  This particular one resolves to offset - sym - addend.
4358 +ENUM
4359 +  BFD_RELOC_AVR32_GOTPC
4360 +ENUMDOC
4361 +  Subtract the link-time address of the GOT from (symbol + addend)
4362 +  and insert the result.
4363 +ENUM
4364 +  BFD_RELOC_AVR32_GOTCALL
4365 +ENUMX
4366 +  BFD_RELOC_AVR32_LDA_GOT
4367 +ENUMX
4368 +  BFD_RELOC_AVR32_GOT21S
4369 +ENUMX
4370 +  BFD_RELOC_AVR32_GOT18SW
4371 +ENUMX
4372 +  BFD_RELOC_AVR32_GOT16S
4373 +ENUMDOC
4374 +  Reference to a symbol through the GOT. The linker will allocate an
4375 +  entry for symbol in the GOT and insert the offset of this entry as
4376 +  the relocation value. addend must be zero. As usual, 'S' means
4377 +  signed, 'W' means word-aligned, etc.
4378 +ENUM
4379 +  BFD_RELOC_AVR32_32_CPENT
4380 +ENUMDOC
4381 +  32-bit constant pool entry. I don't think 8- and 16-bit entries make
4382 +  a whole lot of sense.
4383 +ENUM
4384 +  BFD_RELOC_AVR32_CPCALL
4385 +ENUMX
4386 +  BFD_RELOC_AVR32_16_CP
4387 +ENUMX
4388 +  BFD_RELOC_AVR32_9W_CP
4389 +ENUMDOC
4390 +  Constant pool references. Some of these relocations are signed,
4391 +  others are unsigned. It doesn't really matter, since the constant
4392 +  pool always comes after the code that references it.
4393 +ENUM
4394 +  BFD_RELOC_AVR32_ALIGN
4395 +ENUMDOC
4396 +  sym must be the absolute symbol. The addend specifies the alignment
4397 +  order, e.g. if addend is 2, the linker must add padding so that the
4398 +  next address is aligned to a 4-byte boundary.
4399 +ENUM
4400 +  BFD_RELOC_AVR32_14UW
4401 +ENUMX
4402 +  BFD_RELOC_AVR32_10UW
4403 +ENUMX
4404 +  BFD_RELOC_AVR32_10SW
4405 +ENUMX
4406 +  BFD_RELOC_AVR32_STHH_W
4407 +ENUMX
4408 +  BFD_RELOC_AVR32_7UW
4409 +ENUMX
4410 +  BFD_RELOC_AVR32_6S
4411 +ENUMX
4412 +  BFD_RELOC_AVR32_6UW
4413 +ENUMX
4414 +  BFD_RELOC_AVR32_4UH
4415 +ENUMX
4416 +  BFD_RELOC_AVR32_3U
4417 +ENUMDOC
4418 +  Code relocations that will never make it to the output file.
4419 +
4420 +ENUM
4421    BFD_RELOC_390_12
4422  ENUMDOC
4423     Direct 12 bit.
4424 --- a/bfd/targets.c
4425 +++ b/bfd/targets.c
4426 @@ -570,6 +570,7 @@ extern const bfd_target bfd_efi_app_ia64
4427  extern const bfd_target bfd_efi_bsdrv_ia64_vec;
4428  extern const bfd_target bfd_efi_rtdrv_ia64_vec;
4429  extern const bfd_target bfd_elf32_avr_vec;
4430 +extern const bfd_target bfd_elf32_avr32_vec;
4431  extern const bfd_target bfd_elf32_bfin_vec;
4432  extern const bfd_target bfd_elf32_bfinfdpic_vec;
4433  extern const bfd_target bfd_elf32_big_generic_vec;
4434 @@ -898,6 +899,7 @@ static const bfd_target * const _bfd_tar
4435         &bfd_efi_rtdrv_ia64_vec,
4436  #endif
4437         &bfd_elf32_avr_vec,
4438 +       &bfd_elf32_avr32_vec,
4439         &bfd_elf32_bfin_vec,
4440         &bfd_elf32_bfinfdpic_vec,
4441
4442 --- a/gas/as.c
4443 +++ b/gas/as.c
4444 @@ -445,10 +445,10 @@ parse_args (int * pargc, char *** pargv)
4445         the end of the preceeding line so that it is simpler to
4446         selectively add and remove lines from this list.  */
4447      {"alternate", no_argument, NULL, OPTION_ALTERNATE}
4448 -    /* The entry for "a" is here to prevent getopt_long_only() from
4449 -       considering that -a is an abbreviation for --alternate.  This is
4450 -       necessary because -a=<FILE> is a valid switch but getopt would
4451 -       normally reject it since --alternate does not take an argument.  */
4452 +    /* The next two entries are here to prevent getopt_long_only() from
4453 +       considering that -a or -al is an abbreviation for --alternate.
4454 +       This is necessary because -a=<FILE> is a valid switch but getopt
4455 +       would normally reject it since --alternate does not take an argument.  */
4456      ,{"a", optional_argument, NULL, 'a'}
4457      /* Handle -al=<FILE>.  */
4458      ,{"al", optional_argument, NULL, OPTION_AL}
4459 @@ -810,8 +810,15 @@ This program has absolutely no warranty.
4460         case 'a':
4461           if (optarg)
4462             {
4463 -             if (optarg != old_argv[optind] && optarg[-1] == '=')
4464 +             /* If optarg is part of the -a switch and not a separate argument
4465 +                in its own right, then scan backwards to the just after the -a.
4466 +                This means skipping over both '=' and 'l' which might have been
4467 +                taken to be part of the -a switch itself.  */
4468 +             if (optarg != old_argv[optind])
4469 +               {
4470 +                 while (optarg[-1] == '=' || optarg[-1] == 'l')
4471                 --optarg;
4472 +               }
4473
4474               if (md_parse_option (optc, optarg) != 0)
4475                 break;
4476 @@ -1248,7 +1255,7 @@ main (int argc, char ** argv)
4477      keep_it = 0;
4478
4479    if (!keep_it)
4480 -    unlink_if_ordinary (out_file_name);
4481 +    unlink (out_file_name);
4482
4483    input_scrub_end ();
4484
4485 --- /dev/null
4486 +++ b/gas/config/tc-avr32.c
4487 @@ -0,0 +1,4829 @@
4488 +/* Assembler implementation for AVR32.
4489 +   Copyright 2003,2004,2005,2006,2007,2008,2009 Atmel Corporation.
4490 +
4491 +   Written by Haavard Skinnemoen, Atmel Norway, <hskinnemoen@atmel.com>
4492 +
4493 +   This file is part of GAS, the GNU Assembler.
4494 +
4495 +   GAS is free software; you can redistribute it and/or modify it
4496 +   under the terms of the GNU General Public License as published by
4497 +   the Free Software Foundation; either version 2, or (at your option)
4498 +   any later version.
4499 +
4500 +   GAS is distributed in the hope that it will be useful, but WITHOUT
4501 +   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
4502 +   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
4503 +   License for more details.
4504 +
4505 +   You should have received a copy of the GNU General Public License
4506 +   along with GAS; see the file COPYING.  If not, write to the Free
4507 +   Software Foundation, 59 Temple Place - Suite 330, Boston, MA
4508 +   02111-1307, USA.  */
4509 +
4510 +#include <stdio.h>
4511 +#include "as.h"
4512 +#include "safe-ctype.h"
4513 +#include "subsegs.h"
4514 +#include "symcat.h"
4515 +#include "opcodes/avr32-opc.h"
4516 +#include "opcodes/avr32-asm.h"
4517 +#include "elf/avr32.h"
4518 +#include "dwarf2dbg.h"
4519 +
4520 +#define xDEBUG
4521 +#define xOPC_CONSISTENCY_CHECK
4522 +
4523 +#ifdef DEBUG
4524 +# define pr_debug(fmt, args...) fprintf(stderr, fmt, ##args)
4525 +#else
4526 +# define pr_debug(fmt, args...)
4527 +#endif
4528 +
4529 +/* 3 MSB of instruction word indicate group. Group 7 -> extended */
4530 +#define AVR32_COMPACT_P(opcode) ((opcode[0] & 0xe0) != 0xe0)
4531 +
4532 +#define streq(a, b)            (strcmp(a, b) == 0)
4533 +#define skip_whitespace(str)   do { while(*(str) == ' ') ++(str); } while(0)
4534 +
4535 +/* Flags given on the command line */
4536 +static int avr32_pic   = FALSE;
4537 +int linkrelax  = FALSE;
4538 +int avr32_iarcompat    = FALSE;
4539 +
4540 +/* This array holds the chars that always start a comment. */
4541 +const char comment_chars[]             = "#";
4542 +
4543 +/* This array holds the chars that only start a comment at the
4544 +   beginning of a line.  We must include '#' here because the compiler
4545 +   may produce #APP and #NO_APP in its output.  */
4546 +const char line_comment_chars[]                = "#";
4547 +
4548 +/* These may be used instead of newline (same as ';' in C).  */
4549 +const char line_separator_chars[]      = ";";
4550 +
4551 +/* Chars that can be used to separate mantissa from exponent in
4552 +   floating point numbers.  */
4553 +const char EXP_CHARS[]                 = "eE";
4554 +
4555 +/* Chars that mean this number is a floating point constant.  */
4556 +const char FLT_CHARS[]                 = "dD";
4557 +
4558 +/* Pre-defined "_GLOBAL_OFFSET_TABLE_"  */
4559 +symbolS *GOT_symbol;
4560 +
4561 +static struct hash_control *avr32_mnemonic_htab;
4562 +
4563 +struct avr32_ifield_data
4564 +{
4565 +  bfd_vma value;
4566 +  /* FIXME: Get rid of align_order and complain. complain is never
4567 +     used, align_order is used in one place.  Try to use the relax
4568 +     table instead.  */
4569 +  unsigned int align_order;
4570 +};
4571 +
4572 +struct avr32_insn
4573 +{
4574 +  const struct avr32_syntax *syntax;
4575 +  expressionS immediate;
4576 +  int pcrel;
4577 +  int force_extended;
4578 +  unsigned int next_slot;
4579 +  bfd_reloc_code_real_type r_type;
4580 +  struct avr32_ifield_data field_value[AVR32_MAX_FIELDS];
4581 +};
4582 +
4583 +static struct avr32_insn current_insn;
4584 +
4585 +/* The target specific pseudo-ops we support. */
4586 +static void s_rseg (int);
4587 +static void s_cpool(int);
4588 +
4589 +const pseudo_typeS md_pseudo_table[] =
4590 +{
4591 +  /* Make sure that .word is 32 bits */
4592 +  { "word", cons, 4 },
4593 +  { "file", (void (*) PARAMS ((int))) dwarf2_directive_file, 0 },
4594 +  { "loc", dwarf2_directive_loc, 0 },
4595 +
4596 +  /* .lcomm requires an explicit alignment parameter */
4597 +  { "lcomm", s_lcomm, 1 },
4598 +
4599 +  /* AVR32-specific pseudo-ops */
4600 +  { "cpool", s_cpool, 0},
4601 +
4602 +  /* IAR compatible pseudo-ops */
4603 +  { "program", s_ignore, 0 },
4604 +  { "public", s_globl, 0 },
4605 +  { "extern", s_ignore, 0 },
4606 +  { "module", s_ignore, 0 },
4607 +  { "rseg", s_rseg, 0 },
4608 +  { "dc8", cons, 1 },
4609 +  { "dc16", cons, 2 },
4610 +  { "dc32", cons, 4 },
4611 +
4612 +  { NULL, NULL, 0 }
4613 +};
4614 +
4615 +/* Questionable stuff starts here */
4616 +
4617 +enum avr32_opinfo {
4618 +  AVR32_OPINFO_NONE = BFD_RELOC_NONE,
4619 +  AVR32_OPINFO_GOT,
4620 +  AVR32_OPINFO_TLSGD,
4621 +  AVR32_OPINFO_HI,
4622 +  AVR32_OPINFO_LO,
4623 +};
4624 +
4625 +enum avr32_arch {
4626 +  ARCH_TYPE_AP,
4627 +  ARCH_TYPE_UCR1,
4628 +  ARCH_TYPE_UCR2,
4629 +  ARCH_TYPE_UCR3,
4630 +};
4631 +
4632 +struct arch_type_s
4633 +{
4634 +  /* Architecture name */
4635 +  char *name;
4636 +  /* Instruction Set Architecture Flags */
4637 +  unsigned long isa_flags;
4638 +};
4639 +
4640 +struct part_type_s
4641 +{
4642 +  /* Part name */
4643 +  char *name;
4644 +  /* Architecture type */
4645 +  unsigned int arch;
4646 +};
4647 +
4648 +static struct arch_type_s arch_types[] =
4649 +{
4650 +    {"ap", AVR32_V1 | AVR32_SIMD | AVR32_DSP | AVR32_PICO},
4651 +    {"ucr1", AVR32_V1 | AVR32_DSP | AVR32_RMW},
4652 +    {"ucr2", AVR32_V1 | AVR32_V2 | AVR32_DSP | AVR32_RMW},
4653 +    {"ucr3", AVR32_V1 | AVR32_V2 | AVR32_V3 | AVR32_DSP | AVR32_RMW},
4654 +    {"all-insn", AVR32_V1 | AVR32_V2 | AVR32_V3 | AVR32_SIMD | AVR32_DSP | AVR32_RMW | AVR32_FP | AVR32_PICO},
4655 +    {NULL, 0}
4656 +};
4657 +
4658 +static struct part_type_s part_types[] =
4659 +{
4660 +    {"ap7000",        ARCH_TYPE_AP},
4661 +    {"ap7001",        ARCH_TYPE_AP},
4662 +    {"ap7002",        ARCH_TYPE_AP},
4663 +    {"ap7200",        ARCH_TYPE_AP},
4664 +    {"uc3a0128",      ARCH_TYPE_UCR2},
4665 +    {"uc3a0256",      ARCH_TYPE_UCR2},
4666 +    {"uc3a0512es",    ARCH_TYPE_UCR1},
4667 +    {"uc3a0512",      ARCH_TYPE_UCR2},
4668 +    {"uc3a1128",      ARCH_TYPE_UCR2},
4669 +    {"uc3a1256es",    ARCH_TYPE_UCR1},
4670 +    {"uc3a1256",      ARCH_TYPE_UCR2},
4671 +    {"uc3a1512es",    ARCH_TYPE_UCR1},
4672 +    {"uc3a1512",      ARCH_TYPE_UCR2},
4673 +    {"uc3a364",       ARCH_TYPE_UCR2},
4674 +    {"uc3a364s",      ARCH_TYPE_UCR2},
4675 +    {"uc3a3128",      ARCH_TYPE_UCR2},
4676 +    {"uc3a3128s",     ARCH_TYPE_UCR2},
4677 +    {"uc3a3256",      ARCH_TYPE_UCR2},
4678 +    {"uc3a3256s",     ARCH_TYPE_UCR2},
4679 +    {"uc3b064",       ARCH_TYPE_UCR1},
4680 +    {"uc3b0128",      ARCH_TYPE_UCR1},
4681 +    {"uc3b0256es",    ARCH_TYPE_UCR1},
4682 +    {"uc3b0256",      ARCH_TYPE_UCR1},
4683 +    {"uc3b0512",      ARCH_TYPE_UCR2},
4684 +    {"uc3b0512revc",  ARCH_TYPE_UCR2},
4685 +    {"uc3b164",       ARCH_TYPE_UCR1},
4686 +    {"uc3b1128",      ARCH_TYPE_UCR1},
4687 +    {"uc3b1256",      ARCH_TYPE_UCR1},
4688 +    {"uc3b1256es",    ARCH_TYPE_UCR1},
4689 +    {"uc3b1512",      ARCH_TYPE_UCR2},
4690 +    {"uc3b1512revc",  ARCH_TYPE_UCR2},
4691 +    {"uc3c064c",      ARCH_TYPE_UCR3},
4692 +    {"uc3c0128c",     ARCH_TYPE_UCR3},
4693 +    {"uc3c0256c",     ARCH_TYPE_UCR3},
4694 +    {"uc3c0512crevc", ARCH_TYPE_UCR3},
4695 +    {"uc3c164c",      ARCH_TYPE_UCR3},
4696 +    {"uc3c1128c",     ARCH_TYPE_UCR3},
4697 +    {"uc3c1256c",     ARCH_TYPE_UCR3},
4698 +    {"uc3c1512crevc", ARCH_TYPE_UCR3},
4699 +    {"uc3c264c",      ARCH_TYPE_UCR3},
4700 +    {"uc3c2128c",     ARCH_TYPE_UCR3},
4701 +    {"uc3c2256c",     ARCH_TYPE_UCR3},
4702 +    {"uc3c2512crevc", ARCH_TYPE_UCR3},
4703 +    {"uc3l064",       ARCH_TYPE_UCR3},
4704 +    {"uc3l032",       ARCH_TYPE_UCR3},
4705 +    {"uc3l016",       ARCH_TYPE_UCR3},
4706 +    {"uc3l064revb",   ARCH_TYPE_UCR3},
4707 +    {NULL, 0}
4708 +};
4709 +
4710 +/* Current architecture type.  */
4711 +static struct arch_type_s default_arch = {"all-insn", AVR32_V1 | AVR32_V2 | AVR32_V3 | AVR32_SIMD | AVR32_DSP | AVR32_RMW | AVR32_FP | AVR32_PICO };
4712 +static struct arch_type_s *avr32_arch = &default_arch;
4713 +
4714 +/* Display nicely formatted list of known part- and architecture names.  */
4715 +
4716 +static void
4717 +show_arch_list (FILE *stream)
4718 +{
4719 +  int i, x;
4720 +
4721 +  fprintf (stream, _("Known architecture names:"));
4722 +  x = 1000;
4723 +
4724 +  for (i = 0; arch_types[i].name; i++)
4725 +    {
4726 +      int len = strlen (arch_types[i].name);
4727 +
4728 +      x += len + 1;
4729 +
4730 +      if (x < 75)
4731 +       fprintf (stream, " %s", arch_types[i].name);
4732 +      else
4733 +       {
4734 +         fprintf (stream, "\n  %s", arch_types[i].name);
4735 +         x = len + 2;
4736 +       }
4737 +    }
4738 +
4739 +  fprintf (stream, "\n");
4740 +}
4741 +
4742 +static void
4743 +show_part_list (FILE *stream)
4744 +{
4745 +  int i, x;
4746 +
4747 +  fprintf (stream, _("Known part names:"));
4748 +  x = 1000;
4749 +
4750 +  for (i = 0; part_types[i].name; i++)
4751 +    {
4752 +      int len = strlen(part_types[i].name);
4753 +
4754 +      x += len + 1;
4755 +
4756 +      if (x < 75)
4757 +       fprintf (stream, " %s", part_types[i].name);
4758 +      else
4759 +       {
4760 +         fprintf(stream, "\n  %s", part_types[i].name);
4761 +         x = len + 2;
4762 +       }
4763 +    }
4764 +
4765 +  fprintf (stream, "\n");
4766 +}
4767 +
4768 +const char *md_shortopts = "";
4769 +struct option md_longopts[] =
4770 +{
4771 +#define OPTION_ARCH            (OPTION_MD_BASE)
4772 +#define OPTION_PART            (OPTION_ARCH + 1)
4773 +#define OPTION_IAR             (OPTION_PART + 1)
4774 +#define OPTION_PIC             (OPTION_IAR + 1)
4775 +#define OPTION_NOPIC           (OPTION_PIC + 1)
4776 +#define OPTION_LINKRELAX       (OPTION_NOPIC + 1)
4777 +#define OPTION_NOLINKRELAX     (OPTION_LINKRELAX + 1)
4778 +#define OPTION_DIRECT_DATA_REFS (OPTION_NOLINKRELAX + 1)
4779 +  {"march",            required_argument, NULL, OPTION_ARCH},
4780 +  {"mpart",            required_argument, NULL, OPTION_PART},
4781 +  {"iar",              no_argument, NULL, OPTION_IAR},
4782 +  {"pic",              no_argument, NULL, OPTION_PIC},
4783 +  {"no-pic",           no_argument, NULL, OPTION_NOPIC},
4784 +  {"linkrelax",                no_argument, NULL, OPTION_LINKRELAX},
4785 +  {"no-linkrelax",     no_argument, NULL, OPTION_NOLINKRELAX},
4786 +  /* deprecated alias for -mpart=xxx */
4787 +  {"mcpu",             required_argument, NULL, OPTION_PART},
4788 +  {NULL,               no_argument, NULL, 0}
4789 +};
4790 +
4791 +size_t md_longopts_size = sizeof (md_longopts);
4792 +
4793 +void
4794 +md_show_usage (FILE *stream)
4795 +{
4796 +  fprintf (stream, _("\
4797 +AVR32 options:\n\
4798 +  -march=[arch-name]      Select cpu architecture. [Default `all-insn']\n\
4799 +  -mpart=[part-name]      Select specific part. [Default `none']\n\
4800 +  --pic                   Produce Position-Independent Code\n\
4801 +  --no-pic                Don't produce Position-Independent Code\n\
4802 +  --linkrelax             Produce output suitable for linker relaxing\n\
4803 +  --no-linkrelax          Don't produce output suitable for linker relaxing\n"));
4804 +  show_arch_list(stream);
4805 +}
4806 +
4807 +int
4808 +md_parse_option (int c, char *arg ATTRIBUTE_UNUSED)
4809 +{
4810 +  switch (c)
4811 +    {
4812 +    case OPTION_ARCH:
4813 +      {
4814 +       int i;
4815 +       char *s = alloca (strlen (arg) + 1);
4816 +
4817 +       {
4818 +         char *t = s;
4819 +         char *arg1 = arg;
4820 +
4821 +         do
4822 +           *t = TOLOWER (*arg1++);
4823 +         while (*t++);
4824 +       }
4825 +
4826 +        /* Add backward compability */
4827 +        if (strcmp ("uc", s)== 0)
4828 +          {
4829 +            as_warn("Deprecated arch `%s' specified. "
4830 +                    "Please use '-march=ucr1' instead. "
4831 +                    "Converting to arch 'ucr1'\n",
4832 +                     s);
4833 +            s="ucr1";
4834 +          }
4835 +
4836 +       for (i = 0; arch_types[i].name; ++i)
4837 +         if (strcmp (arch_types[i].name, s) == 0)
4838 +           break;
4839 +
4840 +       if (!arch_types[i].name)
4841 +         {
4842 +           show_arch_list (stderr);
4843 +           as_fatal (_("unknown architecture: %s\n"), arg);
4844 +         }
4845 +
4846 +        avr32_arch = &arch_types[i];
4847 +       break;
4848 +      }
4849 +    case OPTION_PART:
4850 +      {
4851 +       int i;
4852 +       char *s = alloca (strlen (arg) + 1);
4853 +       char *t = s;
4854 +       char *p = arg;
4855 +
4856 +       /* If arch type has already been set, don't bother.
4857 +          -march= always overrides -mpart=  */
4858 +       if (avr32_arch != &default_arch)
4859 +         break;
4860 +
4861 +       do
4862 +         *t = TOLOWER (*p++);
4863 +       while (*t++);
4864 +
4865 +       for (i = 0; part_types[i].name; ++i)
4866 +         if (strcmp (part_types[i].name, s) == 0)
4867 +           break;
4868 +
4869 +       if (!part_types[i].name)
4870 +         {
4871 +           show_part_list (stderr);
4872 +           as_fatal (_("unknown part: %s\n"), arg);
4873 +         }
4874 +
4875 +       avr32_arch = &arch_types[part_types[i].arch];
4876 +       break;
4877 +      }
4878 +    case OPTION_IAR:
4879 +      avr32_iarcompat = 1;
4880 +      break;
4881 +    case OPTION_PIC:
4882 +      avr32_pic = 1;
4883 +      break;
4884 +    case OPTION_NOPIC:
4885 +      avr32_pic = 0;
4886 +      break;
4887 +    case OPTION_LINKRELAX:
4888 +      linkrelax = 1;
4889 +      break;
4890 +    case OPTION_NOLINKRELAX:
4891 +      linkrelax = 0;
4892 +      break;
4893 +    default:
4894 +      return 0;
4895 +    }
4896 +  return 1;
4897 +}
4898 +
4899 +/* Can't use symbol_new here, so have to create a symbol and then at
4900 +   a later date assign it a value. Thats what these functions do.
4901 +
4902 +   Shamelessly stolen from ARM.  */
4903 +
4904 +static void
4905 +symbol_locate (symbolS *    symbolP,
4906 +              const char * name,       /* It is copied, the caller can modify.  */
4907 +              segT         segment,    /* Segment identifier (SEG_<something>).  */
4908 +              valueT       valu,       /* Symbol value.  */
4909 +              fragS *      frag)       /* Associated fragment.  */
4910 +{
4911 +  unsigned int name_length;
4912 +  char * preserved_copy_of_name;
4913 +
4914 +  name_length = strlen (name) + 1;   /* +1 for \0.  */
4915 +  obstack_grow (&notes, name, name_length);
4916 +  preserved_copy_of_name = obstack_finish (&notes);
4917 +#ifdef STRIP_UNDERSCORE
4918 +  if (preserved_copy_of_name[0] == '_')
4919 +    preserved_copy_of_name++;
4920 +#endif
4921 +
4922 +#ifdef tc_canonicalize_symbol_name
4923 +  preserved_copy_of_name =
4924 +    tc_canonicalize_symbol_name (preserved_copy_of_name);
4925 +#endif
4926 +
4927 +  S_SET_NAME (symbolP, preserved_copy_of_name);
4928 +
4929 +  S_SET_SEGMENT (symbolP, segment);
4930 +  S_SET_VALUE (symbolP, valu);
4931 +  symbol_clear_list_pointers (symbolP);
4932 +
4933 +  symbol_set_frag (symbolP, frag);
4934 +
4935 +  /* Link to end of symbol chain.  */
4936 +  {
4937 +    extern int symbol_table_frozen;
4938 +
4939 +    if (symbol_table_frozen)
4940 +      abort ();
4941 +  }
4942 +
4943 +  symbol_append (symbolP, symbol_lastP, & symbol_rootP, & symbol_lastP);
4944 +
4945 +  obj_symbol_new_hook (symbolP);
4946 +
4947 +#ifdef tc_symbol_new_hook
4948 +  tc_symbol_new_hook (symbolP);
4949 +#endif
4950 +
4951 +#ifdef DEBUG_SYMS
4952 +  verify_symbol_chain (symbol_rootP, symbol_lastP);
4953 +#endif /* DEBUG_SYMS  */
4954 +}
4955 +
4956 +struct cpool_entry
4957 +{
4958 +  int                  refcount;
4959 +  offsetT              offset;
4960 +  expressionS          exp;
4961 +};
4962 +
4963 +struct cpool
4964 +{
4965 +  struct cpool         *next;
4966 +  int                  used;
4967 +  struct cpool_entry   *literals;
4968 +  unsigned int         padding;
4969 +  unsigned int         next_free_entry;
4970 +  unsigned int         id;
4971 +  symbolS              *symbol;
4972 +  segT                 section;
4973 +  subsegT              sub_section;
4974 +};
4975 +
4976 +struct cpool *cpool_list = NULL;
4977 +
4978 +static struct cpool *
4979 +find_cpool(segT section, subsegT sub_section)
4980 +{
4981 +  struct cpool *pool;
4982 +
4983 +  for (pool = cpool_list; pool != NULL; pool = pool->next)
4984 +    {
4985 +      if (!pool->used
4986 +         && pool->section == section
4987 +         && pool->sub_section == sub_section)
4988 +       break;
4989 +    }
4990 +
4991 +  return pool;
4992 +}
4993 +
4994 +static struct cpool *
4995 +find_or_make_cpool(segT section, subsegT sub_section)
4996 +{
4997 +  static unsigned int next_cpool_id = 0;
4998 +  struct cpool *pool;
4999 +
5000 +  pool = find_cpool(section, sub_section);
5001 +
5002 +  if (!pool)
5003 +    {
5004 +      pool = xmalloc(sizeof(*pool));
5005 +      if (!pool)
5006 +       return NULL;
5007 +
5008 +      pool->used = 0;
5009 +      pool->literals = NULL;
5010 +      pool->padding = 0;
5011 +      pool->next_free_entry = 0;
5012 +      pool->section = section;
5013 +      pool->sub_section = sub_section;
5014 +      pool->next = cpool_list;
5015 +      pool->symbol = NULL;
5016 +
5017 +      cpool_list = pool;
5018 +    }
5019 +
5020 +  /* NULL symbol means that the pool is new or has just been emptied.  */
5021 +  if (!pool->symbol)
5022 +    {
5023 +      pool->symbol = symbol_create(FAKE_LABEL_NAME, undefined_section,
5024 +                                  0, &zero_address_frag);
5025 +      pool->id = next_cpool_id++;
5026 +    }
5027 +
5028 +  return pool;
5029 +}
5030 +
5031 +static struct cpool *
5032 +add_to_cpool(expressionS *exp, unsigned int *index, int ref)
5033 +{
5034 +  struct cpool *pool;
5035 +  unsigned int entry;
5036 +
5037 +  pool = find_or_make_cpool(now_seg, now_subseg);
5038 +
5039 +  /* Check if this constant is already in the pool.  */
5040 +  for (entry = 0; entry < pool->next_free_entry; entry++)
5041 +    {
5042 +      if ((pool->literals[entry].exp.X_op == exp->X_op)
5043 +         && (exp->X_op == O_constant)
5044 +         && (pool->literals[entry].exp.X_add_number
5045 +             == exp->X_add_number)
5046 +         && (pool->literals[entry].exp.X_unsigned
5047 +             == exp->X_unsigned))
5048 +       break;
5049 +
5050 +      if ((pool->literals[entry].exp.X_op == exp->X_op)
5051 +         && (exp->X_op == O_symbol)
5052 +         && (pool->literals[entry].exp.X_add_number
5053 +             == exp->X_add_number)
5054 +         && (pool->literals[entry].exp.X_add_symbol
5055 +             == exp->X_add_symbol)
5056 +         && (pool->literals[entry].exp.X_op_symbol
5057 +             == exp->X_op_symbol))
5058 +       break;
5059 +    }
5060 +
5061 +  /* Create an entry if we didn't find a match */
5062 +  if (entry == pool->next_free_entry)
5063 +    {
5064 +      pool->literals = xrealloc(pool->literals,
5065 +                               sizeof(struct cpool_entry) * (entry + 1));
5066 +      pool->literals[entry].exp = *exp;
5067 +      pool->literals[entry].refcount = 0;
5068 +      pool->next_free_entry++;
5069 +    }
5070 +
5071 +  if (index)
5072 +    *index = entry;
5073 +  if (ref)
5074 +    pool->literals[entry].refcount++;
5075 +
5076 +  return pool;
5077 +}
5078 +
5079 +struct avr32_operand
5080 +{
5081 +  int id;
5082 +  int is_signed;
5083 +  int is_pcrel;
5084 +  int align_order;
5085 +  int (*match)(char *str);
5086 +  void (*parse)(const struct avr32_operand *op, char *str, int opindex);
5087 +};
5088 +
5089 +static int
5090 +match_anything(char *str ATTRIBUTE_UNUSED)
5091 +{
5092 +  return 1;
5093 +}
5094 +
5095 +static int
5096 +match_intreg(char *str)
5097 +{
5098 +  int regid, ret = 1;
5099 +
5100 +  regid = avr32_parse_intreg(str);
5101 +  if (regid < 0)
5102 +    ret = 0;
5103 +
5104 +  pr_debug("match_intreg: `%s': %d\n", str, ret);
5105 +
5106 +  return ret;
5107 +}
5108 +
5109 +static int
5110 +match_intreg_predec(char *str)
5111 +{
5112 +  int regid;
5113 +
5114 +  if (str[0] != '-' || str[1] != '-')
5115 +    return 0;
5116 +
5117 +  regid = avr32_parse_intreg(str + 2);
5118 +  if (regid < 0)
5119 +    return 0;
5120 +
5121 +  return 1;
5122 +}
5123 +
5124 +static int
5125 +match_intreg_postinc(char *str)
5126 +{
5127 +  int regid, ret = 1;
5128 +  char *p, c;
5129 +
5130 +  for (p = str; *p; p++)
5131 +    if (*p == '+')
5132 +      break;
5133 +
5134 +  if (p[0] != '+' || p[1] != '+')
5135 +    return 0;
5136 +
5137 +  c = *p, *p = 0;
5138 +  regid = avr32_parse_intreg(str);
5139 +  if (regid < 0)
5140 +    ret = 0;
5141 +
5142 +  *p = c;
5143 +  return ret;
5144 +}
5145 +
5146 +static int
5147 +match_intreg_lsl(char *str)
5148 +{
5149 +  int regid, ret = 1;
5150 +  char *p, c;
5151 +
5152 +  for (p = str; *p; p++)
5153 +    if (*p == '<')
5154 +      break;
5155 +
5156 +  if (p[0] && p[1] != '<')
5157 +    return 0;
5158 +
5159 +  c = *p, *p = 0;
5160 +  regid = avr32_parse_intreg(str);
5161 +  if (regid < 0)
5162 +    ret = 0;
5163 +
5164 +  *p = c;
5165 +  return ret;
5166 +}
5167 +
5168 +static int
5169 +match_intreg_lsr(char *str)
5170 +{
5171 +  int regid, ret = 1;
5172 +  char *p, c;
5173 +
5174 +  for (p = str; *p; p++)
5175 +    if (*p == '>')
5176 +      break;
5177 +
5178 +  if (p[0] && p[1] != '>')
5179 +    return 0;
5180 +
5181 +  c = *p, *p = 0;
5182 +
5183 +  regid = avr32_parse_intreg(str);
5184 +  if (regid < 0)
5185 +    ret = 0;
5186 +
5187 +  *p = c;
5188 +  return ret;
5189 +}
5190 +
5191 +static int
5192 +match_intreg_part(char *str)
5193 +{
5194 +  int regid, ret = 1;
5195 +  char *p, c;
5196 +
5197 +  for (p = str; *p; p++)
5198 +    if (*p == ':')
5199 +      break;
5200 +
5201 +  if (p[0] != ':' || !ISPRINT(p[1]) || p[2] != '\0')
5202 +    return 0;
5203 +
5204 +  c = *p, *p = 0;
5205 +  regid = avr32_parse_intreg(str);
5206 +  if (regid < 0)
5207 +    ret = 0;
5208 +
5209 +  *p = c;
5210 +
5211 +  return ret;
5212 +}
5213 +
5214 +#define match_intreg_disp match_anything
5215 +
5216 +static int
5217 +match_intreg_index(char *str)
5218 +{
5219 +  int regid, ret = 1;
5220 +  char *p, *end, c;
5221 +
5222 +  for (p = str; *p; p++)
5223 +    if (*p == '[')
5224 +      break;
5225 +
5226 +  /* don't allow empty displacement here (it makes no sense) */
5227 +  if (p[0] != '[')
5228 +    return 0;
5229 +
5230 +  for (end = p + 1; *end; end++) ;
5231 +  if (*(--end) != ']')
5232 +    return 0;
5233 +
5234 +  c = *end, *end = 0;
5235 +  if (!match_intreg_lsl(p + 1))
5236 +    ret = 0;
5237 +  *end = c;
5238 +
5239 +  if (ret)
5240 +    {
5241 +      c = *p, *p = 0;
5242 +      regid = avr32_parse_intreg(str);
5243 +      if (regid < 0)
5244 +       ret = 0;
5245 +      *p = c;
5246 +    }
5247 +
5248 +  return ret;
5249 +}
5250 +
5251 +static int
5252 +match_intreg_xindex(char *str)
5253 +{
5254 +  int regid, ret = 1;
5255 +  char *p, *end, c;
5256 +
5257 +  for (p = str; *p; p++)
5258 +    if (*p == '[')
5259 +      break;
5260 +
5261 +  /* empty displacement makes no sense here either */
5262 +  if (p[0] != '[')
5263 +    return 0;
5264 +
5265 +  for (end = p + 1; *end; end++)
5266 +    if (*end == '<')
5267 +      break;
5268 +
5269 +  if (!streq(end, "<<2]"))
5270 +    return 0;
5271 +
5272 +  c = *end, *end = 0;
5273 +  if (!match_intreg_part(p + 1))
5274 +    ret = 0;
5275 +  *end = c;
5276 +
5277 +  if (ret)
5278 +    {
5279 +      c = *p, *p = 0;
5280 +      regid = avr32_parse_intreg(str);
5281 +      if (regid < 0)
5282 +       ret = 0;
5283 +      *p = c;
5284 +    }
5285 +
5286 +  return ret;
5287 +}
5288 +
5289 +/* The PC_UDISP_W operator may show up as a label or as a pc[disp]
5290 +   expression.  So there's no point in attempting to match this...  */
5291 +#define match_pc_disp  match_anything
5292 +
5293 +static int
5294 +match_sp(char *str)
5295 +{
5296 +  /* SP in any form will do */
5297 +  return avr32_parse_intreg(str) == AVR32_REG_SP;
5298 +}
5299 +
5300 +static int
5301 +match_sp_disp(char *str)
5302 +{
5303 +  int regid, ret = 1;
5304 +  char *p, c;
5305 +
5306 +  for (p = str; *p; p++)
5307 +    if (*p == '[')
5308 +      break;
5309 +
5310 +  /* allow empty displacement, meaning zero */
5311 +  if (p[0] == '[')
5312 +    {
5313 +      char *end;
5314 +      for (end = p + 1; *end; end++) ;
5315 +      if (end[-1] != ']')
5316 +       return 0;
5317 +    }
5318 +
5319 +  c = *p, *p = 0;
5320 +  regid = avr32_parse_intreg(str);
5321 +  if (regid != AVR32_REG_SP)
5322 +    ret = 0;
5323 +
5324 +  *p = c;
5325 +  return ret;
5326 +}
5327 +
5328 +static int
5329 +match_cpno(char *str)
5330 +{
5331 +  if (strncasecmp(str, "cp", 2) != 0)
5332 +    return 0;
5333 +  return 1;
5334 +}
5335 +
5336 +static int
5337 +match_cpreg(char *str)
5338 +{
5339 +  if (strncasecmp(str, "cr", 2) != 0)
5340 +    return 0;
5341 +  return 1;
5342 +}
5343 +
5344 +/* We allow complex expressions, and register names may show up as
5345 +   symbols.  Just make sure immediate expressions are always matched
5346 +   last.  */
5347 +#define match_const            match_anything
5348 +#define match_jmplabel         match_anything
5349 +#define match_number           match_anything
5350 +
5351 +/* Mnemonics that take reglists never accept anything else */
5352 +#define match_reglist8         match_anything
5353 +#define match_reglist9         match_anything
5354 +#define match_reglist16                match_anything
5355 +#define match_reglist_ldm      match_anything
5356 +#define match_reglist_cp8      match_anything
5357 +#define match_reglist_cpd8     match_anything
5358 +
5359 +/* Ditto for retval, jospinc and mcall */
5360 +#define match_retval           match_anything
5361 +#define match_jospinc          match_anything
5362 +#define match_mcall            match_anything
5363 +
5364 +/* COH is used to select between two different syntaxes */
5365 +static int
5366 +match_coh(char *str)
5367 +{
5368 +  return strcasecmp(str, "coh") == 0;
5369 +}
5370 +
5371 +static int
5372 +match_fpreg(char *str)
5373 +{
5374 +  unsigned long regid;
5375 +  char *endptr;
5376 +
5377 +  if ((str[0] != 'f' && str[0] != 'F')
5378 +      || (str[1] != 'r' && str[1] != 'R'))
5379 +    return 0;
5380 +
5381 +  str += 2;
5382 +  regid = strtoul(str, &endptr, 10);
5383 +  if (!*str || *endptr)
5384 +    return 0;
5385 +
5386 +  return 1;
5387 +}
5388 +
5389 +static int
5390 +match_picoreg(char *str)
5391 +{
5392 +  int regid;
5393 +
5394 +  regid = avr32_parse_picoreg(str);
5395 +  if (regid < 0)
5396 +    return 0;
5397 +  return 1;
5398 +}
5399 +
5400 +#define match_pico_reglist_w   match_anything
5401 +#define match_pico_reglist_d   match_anything
5402 +
5403 +static int
5404 +match_pico_in(char *str)
5405 +{
5406 +  unsigned long regid;
5407 +  char *end;
5408 +
5409 +  if (strncasecmp(str, "in", 2) != 0)
5410 +    return 0;
5411 +
5412 +  str += 2;
5413 +  regid = strtoul(str, &end, 10);
5414 +  if (!*str || *end)
5415 +    return 0;
5416 +
5417 +  return 1;
5418 +}
5419 +
5420 +static int
5421 +match_pico_out0(char *str)
5422 +{
5423 +  if (strcasecmp(str, "out0") != 0)
5424 +    return 0;
5425 +  return 1;
5426 +}
5427 +
5428 +static int
5429 +match_pico_out1(char *str)
5430 +{
5431 +  if (strcasecmp(str, "out1") != 0)
5432 +    return 0;
5433 +  return 1;
5434 +}
5435 +
5436 +static int
5437 +match_pico_out2(char *str)
5438 +{
5439 +  if (strcasecmp(str, "out2") != 0)
5440 +    return 0;
5441 +  return 1;
5442 +}
5443 +
5444 +static int
5445 +match_pico_out3(char *str)
5446 +{
5447 +  if (strcasecmp(str, "out3") != 0)
5448 +    return 0;
5449 +  return 1;
5450 +}
5451 +
5452 +static void parse_nothing(const struct avr32_operand *op ATTRIBUTE_UNUSED,
5453 +                         char *str ATTRIBUTE_UNUSED,
5454 +                         int opindex ATTRIBUTE_UNUSED)
5455 +{
5456 +  /* Do nothing (this is used for "match-only" operands like COH) */
5457 +}
5458 +
5459 +static void
5460 +parse_const(const struct avr32_operand *op, char *str,
5461 +           int opindex ATTRIBUTE_UNUSED)
5462 +{
5463 +  expressionS *exp = &current_insn.immediate;
5464 +  expressionS *sym_exp;
5465 +  int slot;
5466 +  char *save;
5467 +
5468 +  pr_debug("parse_const: `%s' (signed: %d, pcrel: %d, align: %d)\n",
5469 +          str, op->is_signed, op->is_pcrel, op->align_order);
5470 +
5471 +  save = input_line_pointer;
5472 +  input_line_pointer = str;
5473 +
5474 +  expression(exp);
5475 +
5476 +  slot = current_insn.next_slot++;
5477 +  current_insn.field_value[slot].align_order = op->align_order;
5478 +  current_insn.pcrel = op->is_pcrel;
5479 +
5480 +  switch (exp->X_op)
5481 +    {
5482 +    case O_illegal:
5483 +      as_bad(_("illegal operand"));
5484 +      break;
5485 +    case O_absent:
5486 +      as_bad(_("missing operand"));
5487 +      break;
5488 +    case O_constant:
5489 +      pr_debug("  -> constant: %ld\n", (long)exp->X_add_number);
5490 +      current_insn.field_value[slot].value = exp->X_add_number;
5491 +      break;
5492 +    case O_uminus:
5493 +      pr_debug("  -> uminus\n");
5494 +      sym_exp = symbol_get_value_expression(exp->X_add_symbol);
5495 +      switch (sym_exp->X_op) {
5496 +      case O_subtract:
5497 +       pr_debug("     -> subtract: switching operands\n");
5498 +       exp->X_op_symbol = sym_exp->X_add_symbol;
5499 +       exp->X_add_symbol = sym_exp->X_op_symbol;
5500 +       exp->X_op = O_subtract;
5501 +       /* TODO: Remove the old X_add_symbol */
5502 +       break;
5503 +      default:
5504 +       as_bad(_("Expression too complex\n"));
5505 +       break;
5506 +      }
5507 +      break;
5508 +#if 0
5509 +    case O_subtract:
5510 +      /* Any expression subtracting a symbol from the current section
5511 +        can be made PC-relative by adding the right offset.  */
5512 +      if (S_GET_SEGMENT(exp->X_op_symbol) == now_seg)
5513 +       current_insn.pcrel = TRUE;
5514 +      pr_debug("  -> subtract: pcrel? %s\n",
5515 +              current_insn.pcrel ? "yes" : "no");
5516 +      /* fall through */
5517 +#endif
5518 +    default:
5519 +      pr_debug("  -> (%p <%d> %p + %d)\n",
5520 +              exp->X_add_symbol, exp->X_op, exp->X_op_symbol,
5521 +              exp->X_add_number);
5522 +      current_insn.field_value[slot].value = 0;
5523 +      break;
5524 +    }
5525 +
5526 +  input_line_pointer = save;
5527 +}
5528 +
5529 +static void
5530 +parse_jmplabel(const struct avr32_operand *op, char *str,
5531 +              int opindex ATTRIBUTE_UNUSED)
5532 +{
5533 +  expressionS *exp = &current_insn.immediate;
5534 +  int slot;
5535 +  char *save;
5536 +
5537 +  pr_debug("parse_jmplabel: `%s' (signed: %d, pcrel: %d, align: %d)\n",
5538 +          str, op->is_signed, op->is_pcrel, op->align_order);
5539 +
5540 +  save = input_line_pointer;
5541 +  input_line_pointer = str;
5542 +
5543 +  expression(exp);
5544 +
5545 +  slot = current_insn.next_slot++;
5546 +  current_insn.field_value[slot].align_order = op->align_order;
5547 +  current_insn.pcrel = TRUE;
5548 +
5549 +  switch (exp->X_op)
5550 +    {
5551 +    case O_illegal:
5552 +      as_bad(_("illegal operand"));
5553 +      break;
5554 +    case O_absent:
5555 +      as_bad(_("missing operand"));
5556 +      break;
5557 +    case O_constant:
5558 +      pr_debug("  -> constant: %ld\n", (long)exp->X_add_number);
5559 +      current_insn.field_value[slot].value = exp->X_add_number;
5560 +      current_insn.pcrel = 0;
5561 +      break;
5562 +    default:
5563 +      pr_debug("  -> (%p <%d> %p + %d)\n",
5564 +              exp->X_add_symbol, exp->X_op, exp->X_op_symbol,
5565 +              exp->X_add_number);
5566 +      current_insn.field_value[slot].value = 0;
5567 +      break;
5568 +    }
5569 +
5570 +  input_line_pointer = save;
5571 +}
5572 +
5573 +static void
5574 +parse_intreg(const struct avr32_operand *op ATTRIBUTE_UNUSED,
5575 +            char *str, int opindex ATTRIBUTE_UNUSED)
5576 +{
5577 +  int regid, slot;
5578 +
5579 +  pr_debug("parse_intreg: `%s'\n", str);
5580 +
5581 +  regid = avr32_parse_intreg(str);
5582 +  assert(regid >= 0);
5583 +
5584 +  slot = current_insn.next_slot++;
5585 +  current_insn.field_value[slot].value = regid;
5586 +  current_insn.field_value[slot].align_order = op->align_order;
5587 +}
5588 +
5589 +static void
5590 +parse_intreg_predec(const struct avr32_operand *op, char *str, int opindex)
5591 +{
5592 +  parse_intreg(op, str + 2, opindex);
5593 +}
5594 +
5595 +static void
5596 +parse_intreg_postinc(const struct avr32_operand *op, char *str, int opindex)
5597 +{
5598 +  char *p, c;
5599 +
5600 +  pr_debug("parse_intreg_postinc: `%s'\n", str);
5601 +
5602 +  for (p = str; *p != '+'; p++) ;
5603 +
5604 +  c = *p, *p = 0;
5605 +  parse_intreg(op, str, opindex);
5606 +  *p = c;
5607 +}
5608 +
5609 +static void
5610 +parse_intreg_shift(const struct avr32_operand *op ATTRIBUTE_UNUSED,
5611 +                  char *str, int opindex ATTRIBUTE_UNUSED)
5612 +{
5613 +  int regid, slot, shift = 0;
5614 +  char *p, c;
5615 +  char shiftop;
5616 +
5617 +  pr_debug("parse Ry<<sa: `%s'\n", str);
5618 +
5619 +  for (p = str; *p; p++)
5620 +    if (*p == '<' || *p == '>')
5621 +      break;
5622 +
5623 +  shiftop = *p;
5624 +
5625 +  c = *p, *p = 0;
5626 +  regid = avr32_parse_intreg(str);
5627 +  assert(regid >= 0);
5628 +  *p = c;
5629 +
5630 +  if (c)
5631 +    {
5632 +      if (p[0] != shiftop || p[1] != shiftop)
5633 +       as_bad(_("expected shift operator in `%s'"), p);
5634 +      else
5635 +       {
5636 +         expressionS exp;
5637 +         char *saved;
5638 +
5639 +         saved = input_line_pointer;
5640 +         input_line_pointer = p + 2;
5641 +         expression(&exp);
5642 +         input_line_pointer = saved;
5643 +
5644 +         if (exp.X_op != O_constant)
5645 +           as_bad(_("shift amount must be a numeric constant"));
5646 +         else
5647 +           shift = exp.X_add_number;
5648 +       }
5649 +    }
5650 +
5651 +  slot = current_insn.next_slot++;
5652 +  current_insn.field_value[slot].value = regid;
5653 +  slot = current_insn.next_slot++;
5654 +  current_insn.field_value[slot].value = shift;
5655 +}
5656 +
5657 +/* The match() function selected the right opcode, so it doesn't
5658 +   matter which way we shift any more.  */
5659 +#define parse_intreg_lsl       parse_intreg_shift
5660 +#define parse_intreg_lsr       parse_intreg_shift
5661 +
5662 +static void
5663 +parse_intreg_part(const struct avr32_operand *op, char *str,
5664 +                 int opindex ATTRIBUTE_UNUSED)
5665 +{
5666 +  static const char bparts[] = { 'b', 'l', 'u', 't' };
5667 +  static const char hparts[] = { 'b', 't' };
5668 +  unsigned int slot, sel;
5669 +  int regid;
5670 +  char *p, c;
5671 +
5672 +  pr_debug("parse reg:part `%s'\n", str);
5673 +
5674 +  for (p = str; *p; p++)
5675 +    if (*p == ':')
5676 +      break;
5677 +
5678 +  c = *p, *p = 0;
5679 +  regid = avr32_parse_intreg(str);
5680 +  assert(regid >= 0);
5681 +  *p = c;
5682 +
5683 +  assert(c == ':');
5684 +
5685 +  if (op->align_order)
5686 +    {
5687 +      for (sel = 0; sel < sizeof(hparts); sel++)
5688 +       if (TOLOWER(p[1]) == hparts[sel])
5689 +         break;
5690 +
5691 +      if (sel >= sizeof(hparts))
5692 +       {
5693 +         as_bad(_("invalid halfword selector `%c' (must be either b or t)"),
5694 +                p[1]);
5695 +         sel = 0;
5696 +       }
5697 +    }
5698 +  else
5699 +    {
5700 +      for (sel = 0; sel < sizeof(bparts); sel++)
5701 +       if (TOLOWER(p[1]) == bparts[sel])
5702 +         break;
5703 +
5704 +      if (sel >= sizeof(bparts))
5705 +       {
5706 +         as_bad(_("invalid byte selector `%c' (must be one of b,l,u,t)"),
5707 +                p[1]);
5708 +         sel = 0;
5709 +       }
5710 +    }
5711 +
5712 +  slot = current_insn.next_slot++;
5713 +  current_insn.field_value[slot].value = regid;
5714 +  slot = current_insn.next_slot++;
5715 +  current_insn.field_value[slot].value = sel;
5716 +}
5717 +
5718 +/* This is the parser for "Rp[displacement]" expressions.  In addition
5719 +   to the "official" syntax, we accept a label as a replacement for
5720 +   the register expression.  This syntax implies Rp=PC and the
5721 +   displacement is the pc-relative distance to the label.  */
5722 +static void
5723 +parse_intreg_disp(const struct avr32_operand *op, char *str, int opindex)
5724 +{
5725 +  expressionS *exp = &current_insn.immediate;
5726 +  int slot, regid;
5727 +  char *save, *p, c;
5728 +
5729 +  pr_debug("parse_intreg_disp: `%s' (signed: %d, pcrel: %d, align: %d)\n",
5730 +          str, op->is_signed, op->is_pcrel, op->align_order);
5731 +
5732 +  for (p = str; *p; p++)
5733 +    if (*p == '[')
5734 +      break;
5735 +
5736 +  slot = current_insn.next_slot++;
5737 +
5738 +  /* First, check if we have a valid register either before '[' or as
5739 +     the sole expression.  If so, we use the Rp[disp] syntax.  */
5740 +  c = *p, *p = 0;
5741 +  regid = avr32_parse_intreg(str);
5742 +  *p = c;
5743 +
5744 +  if (regid >= 0)
5745 +    {
5746 +      current_insn.field_value[slot].value = regid;
5747 +
5748 +      slot = current_insn.next_slot++;
5749 +      current_insn.field_value[slot].align_order = op->align_order;
5750 +
5751 +      if (c == '[')
5752 +       {
5753 +         save = input_line_pointer;
5754 +         input_line_pointer = p + 1;
5755 +
5756 +         expression(exp);
5757 +
5758 +         if (*input_line_pointer != ']')
5759 +           as_bad(_("junk after displacement expression"));
5760 +
5761 +         input_line_pointer = save;
5762 +
5763 +         switch (exp->X_op)
5764 +           {
5765 +           case O_illegal:
5766 +             as_bad(_("illegal displacement expression"));
5767 +             break;
5768 +           case O_absent:
5769 +             as_bad(_("missing displacement expression"));
5770 +             break;
5771 +           case O_constant:
5772 +             pr_debug("  -> constant: %ld\n", exp->X_add_number);
5773 +             current_insn.field_value[slot].value = exp->X_add_number;
5774 +             break;
5775 +#if 0
5776 +           case O_subtract:
5777 +             if (S_GET_SEGMENT(exp->X_op_symbol) == now_seg)
5778 +               current_insn.pcrel = TRUE;
5779 +             pr_debug("  -> subtract: pcrel? %s\n",
5780 +                      current_insn.pcrel ? "yes" : "no");
5781 +             /* fall through */
5782 +#endif
5783 +           default:
5784 +             pr_debug("  -> (%p <%d> %p + %d)\n",
5785 +                      exp->X_add_symbol, exp->X_op, exp->X_op_symbol,
5786 +                      exp->X_add_number);
5787 +             current_insn.field_value[slot].value = 0;
5788 +           }
5789 +       }
5790 +      else
5791 +       {
5792 +         exp->X_op = O_constant;
5793 +         exp->X_add_number = 0;
5794 +         current_insn.field_value[slot].value = 0;
5795 +       }
5796 +    }
5797 +  else
5798 +    {
5799 +      /* Didn't find a valid register.  Try parsing it as a label.  */
5800 +      current_insn.field_value[slot].value = AVR32_REG_PC;
5801 +      parse_jmplabel(op, str, opindex);
5802 +    }
5803 +}
5804 +
5805 +static void
5806 +parse_intreg_index(const struct avr32_operand *op ATTRIBUTE_UNUSED,
5807 +                  char *str, int opindex ATTRIBUTE_UNUSED)
5808 +{
5809 +  int slot, regid;
5810 +  char *p, *end, c;
5811 +
5812 +  for (p = str; *p; p++)
5813 +    if (*p == '[')
5814 +      break;
5815 +
5816 +  assert(*p);
5817 +
5818 +  c = *p, *p = 0;
5819 +  regid = avr32_parse_intreg(str);
5820 +  assert(regid >= 0);
5821 +  *p = c;
5822 +
5823 +  slot = current_insn.next_slot++;
5824 +  current_insn.field_value[slot].value = regid;
5825 +
5826 +  p++;
5827 +  for (end = p; *end; end++)
5828 +    if (*end == ']' || *end == '<')
5829 +      break;
5830 +
5831 +  assert(*end);
5832 +
5833 +  c = *end, *end = 0;
5834 +  regid = avr32_parse_intreg(p);
5835 +  assert(regid >= 0);
5836 +  *end = c;
5837 +
5838 +  slot = current_insn.next_slot++;
5839 +  current_insn.field_value[slot].value = regid;
5840 +
5841 +  slot = current_insn.next_slot++;
5842 +  current_insn.field_value[slot].value = 0;
5843 +
5844 +  if (*end == '<')
5845 +    {
5846 +      expressionS exp;
5847 +      char *save;
5848 +
5849 +      p = end + 2;
5850 +      for (end = p; *end; end++)
5851 +       if (*end == ']')
5852 +         break;
5853 +
5854 +      assert(*end == ']');
5855 +
5856 +      c = *end, *end = 0;
5857 +      save = input_line_pointer;
5858 +      input_line_pointer = p;
5859 +      expression(&exp);
5860 +
5861 +      if (*input_line_pointer)
5862 +       as_bad(_("junk after shift expression"));
5863 +
5864 +      *end = c;
5865 +      input_line_pointer = save;
5866 +
5867 +      if (exp.X_op == O_constant)
5868 +       current_insn.field_value[slot].value = exp.X_add_number;
5869 +      else
5870 +       as_bad(_("shift expression too complex"));
5871 +    }
5872 +}
5873 +
5874 +static void
5875 +parse_intreg_xindex(const struct avr32_operand *op, char *str, int opindex)
5876 +{
5877 +  int slot, regid;
5878 +  char *p, *end, c;
5879 +
5880 +  for (p = str; *p; p++)
5881 +    if (*p == '[')
5882 +      break;
5883 +
5884 +  assert(*p);
5885 +
5886 +  c = *p, *p = 0;
5887 +  regid = avr32_parse_intreg(str);
5888 +  assert(regid >= 0);
5889 +  *p = c;
5890 +
5891 +  slot = current_insn.next_slot++;
5892 +  current_insn.field_value[slot].value = regid;
5893 +
5894 +  p++;
5895 +  for (end = p; *end; end++)
5896 +    if (*end == '<')
5897 +      break;
5898 +
5899 +  assert(*end);
5900 +
5901 +  c = *end, *end = 0;
5902 +  parse_intreg_part(op, p, opindex);
5903 +  *end = c;
5904 +}
5905 +
5906 +static void
5907 +parse_pc_disp(const struct avr32_operand *op, char *str, int opindex)
5908 +{
5909 +  char *p, c;
5910 +
5911 +  for (p = str; *p; p++)
5912 +    if (*p == '[')
5913 +      break;
5914 +
5915 +  /* The lddpc instruction comes in two different syntax variants:
5916 +       lddpc reg, expression
5917 +       lddpc reg, pc[disp]
5918 +     If the operand contains a '[', we use the second form.  */
5919 +  if (*p)
5920 +    {
5921 +      int regid;
5922 +
5923 +      c = *p, *p = 0;
5924 +      regid = avr32_parse_intreg(str);
5925 +      *p = c;
5926 +      if (regid == AVR32_REG_PC)
5927 +       {
5928 +         char *end;
5929 +
5930 +         for (end = ++p; *end; end++) ;
5931 +         if (*(--end) != ']')
5932 +           as_bad(_("unrecognized form of instruction: `%s'"), str);
5933 +         else
5934 +           {
5935 +             c = *end, *end = 0;
5936 +             parse_const(op, p, opindex);
5937 +             *end = c;
5938 +             current_insn.pcrel = 0;
5939 +           }
5940 +       }
5941 +      else
5942 +       as_bad(_("unrecognized form of instruction: `%s'"), str);
5943 +    }
5944 +  else
5945 +    {
5946 +      parse_jmplabel(op, str, opindex);
5947 +    }
5948 +}
5949 +
5950 +static void parse_sp(const struct avr32_operand *op ATTRIBUTE_UNUSED,
5951 +                    char *str ATTRIBUTE_UNUSED,
5952 +                    int opindex ATTRIBUTE_UNUSED)
5953 +{
5954 +  int slot;
5955 +
5956 +  slot = current_insn.next_slot++;
5957 +  current_insn.field_value[slot].value = AVR32_REG_SP;
5958 +}
5959 +
5960 +static void
5961 +parse_sp_disp(const struct avr32_operand *op, char *str, int opindex)
5962 +{
5963 +  char *p, c;
5964 +
5965 +  for (; *str; str++)
5966 +    if (*str == '[')
5967 +      break;
5968 +
5969 +  assert(*str);
5970 +
5971 +  for (p = ++str; *p; p++)
5972 +    if (*p == ']')
5973 +      break;
5974 +
5975 +  c = *p, *p = 0;
5976 +  parse_const(op, str, opindex);
5977 +  *p = c;
5978 +}
5979 +
5980 +static void
5981 +parse_cpno(const struct avr32_operand *op ATTRIBUTE_UNUSED, char *str,
5982 +          int opindex ATTRIBUTE_UNUSED)
5983 +{
5984 +  int slot;
5985 +
5986 +  str += 2;
5987 +  if (*str == '#')
5988 +    str++;
5989 +  if (*str < '0' || *str > '7' || str[1])
5990 +    as_bad(_("invalid coprocessor `%s'"), str);
5991 +
5992 +  slot = current_insn.next_slot++;
5993 +  current_insn.field_value[slot].value = *str - '0';
5994 +}
5995 +
5996 +static void
5997 +parse_cpreg(const struct avr32_operand *op, char *str,
5998 +           int opindex ATTRIBUTE_UNUSED)
5999 +{
6000 +  unsigned int crid;
6001 +  int slot;
6002 +  char *endptr;
6003 +
6004 +  str += 2;
6005 +  crid = strtoul(str, &endptr, 10);
6006 +  if (*endptr || crid > 15 || crid & ((1 << op->align_order) - 1))
6007 +    as_bad(_("invalid coprocessor register `%s'"), str);
6008 +
6009 +  crid >>= op->align_order;
6010 +
6011 +  slot = current_insn.next_slot++;
6012 +  current_insn.field_value[slot].value = crid;
6013 +}
6014 +
6015 +static void
6016 +parse_number(const struct avr32_operand *op, char *str,
6017 +            int opindex ATTRIBUTE_UNUSED)
6018 +{
6019 +  expressionS exp;
6020 +  int slot;
6021 +  char *save;
6022 +
6023 +  save = input_line_pointer;
6024 +  input_line_pointer = str;
6025 +  expression(&exp);
6026 +  input_line_pointer = save;
6027 +
6028 +  slot = current_insn.next_slot++;
6029 +  current_insn.field_value[slot].align_order = op->align_order;
6030 +
6031 +  if (exp.X_op == O_constant)
6032 +      current_insn.field_value[slot].value = exp.X_add_number;
6033 +  else
6034 +      as_bad(_("invalid numeric expression `%s'"), str);
6035 +}
6036 +
6037 +static void
6038 +parse_reglist8(const struct avr32_operand *op ATTRIBUTE_UNUSED,
6039 +              char *str, int opindex ATTRIBUTE_UNUSED)
6040 +{
6041 +  unsigned long regmask;
6042 +  unsigned long value = 0;
6043 +  int slot;
6044 +  char *tail;
6045 +
6046 +  regmask = avr32_parse_reglist(str, &tail);
6047 +  if (*tail)
6048 +    as_bad(_("invalid register list `%s'"), str);
6049 +  else
6050 +    {
6051 +      if (avr32_make_regmask8(regmask, &value))
6052 +       as_bad(_("register list `%s' doesn't fit"), str);
6053 +    }
6054 +
6055 +  slot = current_insn.next_slot++;
6056 +  current_insn.field_value[slot].value = value;
6057 +}
6058 +
6059 +static int
6060 +parse_reglist_tail(char *str, unsigned long regmask)
6061 +{
6062 +  expressionS exp;
6063 +  char *save, *p, c;
6064 +  int regid;
6065 +
6066 +  for (p = str + 1; *p; p++)
6067 +    if (*p == '=')
6068 +      break;
6069 +
6070 +  if (!*p)
6071 +    {
6072 +      as_bad(_("invalid register list `%s'"), str);
6073 +      return -2;
6074 +    }
6075 +
6076 +  c = *p, *p = 0;
6077 +  regid = avr32_parse_intreg(str);
6078 +  *p = c;
6079 +
6080 +  if (regid != 12)
6081 +    {
6082 +      as_bad(_("invalid register list `%s'"), str);
6083 +      return -2;
6084 +    }
6085 +
6086 +  /* If we have an assignment, we must pop PC and we must _not_
6087 +     pop LR or R12 */
6088 +  if (!(regmask & (1 << AVR32_REG_PC)))
6089 +    {
6090 +      as_bad(_("return value specified for non-return instruction"));
6091 +      return -2;
6092 +    }
6093 +  else if (regmask & ((1 << AVR32_REG_R12) | (1 << AVR32_REG_LR)))
6094 +    {
6095 +      as_bad(_("can't pop LR or R12 when specifying return value"));
6096 +      return -2;
6097 +    }
6098 +
6099 +  save = input_line_pointer;
6100 +  input_line_pointer = p + 1;
6101 +  expression(&exp);
6102 +  input_line_pointer = save;
6103 +
6104 +  if (exp.X_op != O_constant
6105 +      || exp.X_add_number < -1
6106 +      || exp.X_add_number > 1)
6107 +    {
6108 +      as_bad(_("invalid return value `%s'"), str);
6109 +      return -2;
6110 +    }
6111 +
6112 +  return exp.X_add_number;
6113 +}
6114 +
6115 +static void
6116 +parse_reglist9(const struct avr32_operand *op ATTRIBUTE_UNUSED,
6117 +              char *str, int opindex ATTRIBUTE_UNUSED)
6118 +{
6119 +  unsigned long regmask;
6120 +  unsigned long value = 0, kbit = 0;
6121 +  int slot;
6122 +  char *tail;
6123 +
6124 +  regmask = avr32_parse_reglist(str, &tail);
6125 +  /* printf("parsed reglist16: %04lx, tail: `%s'\n", regmask, tail); */
6126 +  if (*tail)
6127 +    {
6128 +      int retval;
6129 +
6130 +      retval = parse_reglist_tail(tail, regmask);
6131 +
6132 +      switch (retval)
6133 +       {
6134 +       case -1:
6135 +         regmask |= 1 << AVR32_REG_LR;
6136 +         break;
6137 +       case 0:
6138 +         break;
6139 +       case 1:
6140 +         regmask |= 1 << AVR32_REG_R12;
6141 +         break;
6142 +       default:
6143 +         break;
6144 +       }
6145 +
6146 +      kbit = 1;
6147 +    }
6148 +
6149 +  if (avr32_make_regmask8(regmask, &value))
6150 +    as_bad(_("register list `%s' doesn't fit"), str);
6151 +
6152 +
6153 +  slot = current_insn.next_slot++;
6154 +  current_insn.field_value[slot].value = (value << 1) | kbit;
6155 +}
6156 +
6157 +static void
6158 +parse_reglist16(const struct avr32_operand *op ATTRIBUTE_UNUSED,
6159 +               char *str, int opindex ATTRIBUTE_UNUSED)
6160 +{
6161 +  unsigned long regmask;
6162 +  int slot;
6163 +  char *tail;
6164 +
6165 +  regmask = avr32_parse_reglist(str, &tail);
6166 +  if (*tail)
6167 +    as_bad(_("invalid register list `%s'"), str);
6168 +
6169 +  slot = current_insn.next_slot++;
6170 +  current_insn.field_value[slot].value = regmask;
6171 +}
6172 +
6173 +static void
6174 +parse_reglist_ldm(const struct avr32_operand *op ATTRIBUTE_UNUSED,
6175 +                 char *str, int opindex ATTRIBUTE_UNUSED)
6176 +{
6177 +  unsigned long regmask;
6178 +  int slot, rp, w_bit = 0;
6179 +  char *tail, *p, c;
6180 +
6181 +  for (p = str; *p && *p != ','; p++)
6182 +    if (*p == '+')
6183 +      break;
6184 +
6185 +  c = *p, *p = 0;
6186 +  rp = avr32_parse_intreg(str);
6187 +  *p = c;
6188 +  if (rp < 0)
6189 +    {
6190 +      as_bad(_("invalid destination register in `%s'"), str);
6191 +      return;
6192 +    }
6193 +
6194 +  if (p[0] == '+' && p[1] == '+')
6195 +    {
6196 +      w_bit = 1;
6197 +      p += 2;
6198 +    }
6199 +
6200 +  if (*p != ',')
6201 +    {
6202 +      as_bad(_("expected `,' after destination register in `%s'"), str);
6203 +      return;
6204 +    }
6205 +
6206 +  str = p + 1;
6207 +  regmask = avr32_parse_reglist(str, &tail);
6208 +  if (*tail)
6209 +    {
6210 +      int retval;
6211 +
6212 +      if (rp != AVR32_REG_SP)
6213 +       {
6214 +         as_bad(_("junk at end of line: `%s'"), tail);
6215 +         return;
6216 +       }
6217 +
6218 +      rp = AVR32_REG_PC;
6219 +
6220 +      retval = parse_reglist_tail(tail, regmask);
6221 +
6222 +      switch (retval)
6223 +       {
6224 +       case -1:
6225 +         regmask |= 1 << AVR32_REG_LR;
6226 +         break;
6227 +       case 0:
6228 +         break;
6229 +       case 1:
6230 +         regmask |= 1 << AVR32_REG_R12;
6231 +         break;
6232 +       default:
6233 +         return;
6234 +       }
6235 +    }
6236 +
6237 +  slot = current_insn.next_slot++;
6238 +  current_insn.field_value[slot].value = rp;
6239 +  slot = current_insn.next_slot++;
6240 +  current_insn.field_value[slot].value = w_bit;
6241 +  slot = current_insn.next_slot++;
6242 +  current_insn.field_value[slot].value = regmask;
6243 +}
6244 +
6245 +static void
6246 +parse_reglist_cp8(const struct avr32_operand *op ATTRIBUTE_UNUSED,
6247 +                 char *str, int opindex ATTRIBUTE_UNUSED)
6248 +{
6249 +  unsigned long regmask;
6250 +  int slot, h_bit = 0;
6251 +  char *tail;
6252 +
6253 +  regmask = avr32_parse_cpreglist(str, &tail);
6254 +  if (*tail)
6255 +    as_bad(_("junk at end of line: `%s'"), tail);
6256 +  else if (regmask & 0xffUL)
6257 +    {
6258 +      if (regmask & 0xff00UL)
6259 +       as_bad(_("register list `%s' doesn't fit"), str);
6260 +      regmask &= 0xff;
6261 +    }
6262 +  else if (regmask & 0xff00UL)
6263 +    {
6264 +      regmask >>= 8;
6265 +      h_bit = 1;
6266 +    }
6267 +  else
6268 +    as_warn(_("register list is empty"));
6269 +
6270 +  slot = current_insn.next_slot++;
6271 +  current_insn.field_value[slot].value = regmask;
6272 +  slot = current_insn.next_slot++;
6273 +  current_insn.field_value[slot].value = h_bit;
6274 +}
6275 +
6276 +static void
6277 +parse_reglist_cpd8(const struct avr32_operand *op ATTRIBUTE_UNUSED,
6278 +                  char *str, int opindex ATTRIBUTE_UNUSED)
6279 +{
6280 +  unsigned long regmask, regmask_d = 0;
6281 +  int slot, i;
6282 +  char *tail;
6283 +
6284 +  regmask = avr32_parse_cpreglist(str, &tail);
6285 +  if (*tail)
6286 +    as_bad(_("junk at end of line: `%s'"), tail);
6287 +
6288 +  for (i = 0; i < 8; i++)
6289 +    {
6290 +      if (regmask & 1)
6291 +       {
6292 +         if (!(regmask & 2))
6293 +           {
6294 +             as_bad(_("register list `%s' doesn't fit"), str);
6295 +             break;
6296 +           }
6297 +         regmask_d |= 1 << i;
6298 +       }
6299 +      else if (regmask & 2)
6300 +       {
6301 +         as_bad(_("register list `%s' doesn't fit"), str);
6302 +         break;
6303 +       }
6304 +
6305 +      regmask >>= 2;
6306 +    }
6307 +
6308 +  slot = current_insn.next_slot++;
6309 +  current_insn.field_value[slot].value = regmask_d;
6310 +}
6311 +
6312 +static void
6313 +parse_retval(const struct avr32_operand *op ATTRIBUTE_UNUSED,
6314 +            char *str, int opindex ATTRIBUTE_UNUSED)
6315 +{
6316 +  int regid, slot;
6317 +
6318 +  regid = avr32_parse_intreg(str);
6319 +  if (regid < 0)
6320 +    {
6321 +      expressionS exp;
6322 +      char *save;
6323 +
6324 +      regid = 0;
6325 +
6326 +      save = input_line_pointer;
6327 +      input_line_pointer = str;
6328 +      expression(&exp);
6329 +      input_line_pointer = save;
6330 +
6331 +      if (exp.X_op != O_constant)
6332 +       as_bad(_("invalid return value `%s'"), str);
6333 +      else
6334 +       switch (exp.X_add_number)
6335 +         {
6336 +         case -1:
6337 +           regid = AVR32_REG_LR;
6338 +           break;
6339 +         case 0:
6340 +           regid = AVR32_REG_SP;
6341 +           break;
6342 +         case 1:
6343 +           regid = AVR32_REG_PC;
6344 +           break;
6345 +         default:
6346 +           as_bad(_("invalid return value `%s'"), str);
6347 +           break;
6348 +         }
6349 +    }
6350 +
6351 +  slot = current_insn.next_slot++;
6352 +  current_insn.field_value[slot].value = regid;
6353 +}
6354 +
6355 +#define parse_mcall parse_intreg_disp
6356 +
6357 +static void
6358 +parse_jospinc(const struct avr32_operand *op ATTRIBUTE_UNUSED,
6359 +             char *str, int opindex ATTRIBUTE_UNUSED)
6360 +{
6361 +  expressionS exp;
6362 +  int slot;
6363 +  char *save;
6364 +
6365 +  save = input_line_pointer;
6366 +  input_line_pointer = str;
6367 +  expression(&exp);
6368 +  input_line_pointer = save;
6369 +
6370 +  slot = current_insn.next_slot++;
6371 +
6372 +  if (exp.X_op == O_constant)
6373 +    {
6374 +      if (exp.X_add_number > 0)
6375 +       exp.X_add_number--;
6376 +      current_insn.field_value[slot].value = exp.X_add_number;
6377 +    }
6378 +  else
6379 +    as_bad(_("invalid numeric expression `%s'"), str);
6380 +}
6381 +
6382 +#define parse_coh              parse_nothing
6383 +
6384 +static void
6385 +parse_fpreg(const struct avr32_operand *op,
6386 +           char *str, int opindex ATTRIBUTE_UNUSED)
6387 +{
6388 +  unsigned long regid;
6389 +  int slot;
6390 +
6391 +  regid = strtoul(str + 2, NULL, 10);
6392 +
6393 +  if ((regid >= 16) || (regid & ((1 << op->align_order) - 1)))
6394 +    as_bad(_("invalid floating-point register `%s'"), str);
6395 +
6396 +  slot = current_insn.next_slot++;
6397 +  current_insn.field_value[slot].value = regid;
6398 +  current_insn.field_value[slot].align_order = op->align_order;
6399 +}
6400 +
6401 +static void
6402 +parse_picoreg(const struct avr32_operand *op,
6403 +             char *str, int opindex ATTRIBUTE_UNUSED)
6404 +{
6405 +  unsigned long regid;
6406 +  int slot;
6407 +
6408 +  regid = avr32_parse_picoreg(str);
6409 +  if (regid & ((1 << op->align_order) - 1))
6410 +    as_bad(_("invalid double-word PiCo register `%s'"), str);
6411 +
6412 +  slot = current_insn.next_slot++;
6413 +  current_insn.field_value[slot].value = regid;
6414 +  current_insn.field_value[slot].align_order = op->align_order;
6415 +}
6416 +
6417 +static void
6418 +parse_pico_reglist_w(const struct avr32_operand *op ATTRIBUTE_UNUSED,
6419 +                    char *str, int opindex ATTRIBUTE_UNUSED)
6420 +{
6421 +  unsigned long regmask;
6422 +  int slot, h_bit = 0;
6423 +  char *tail;
6424 +
6425 +  regmask = avr32_parse_pico_reglist(str, &tail);
6426 +  if (*tail)
6427 +    as_bad(_("junk at end of line: `%s'"), tail);
6428 +
6429 +  if (regmask & 0x00ffUL)
6430 +    {
6431 +      if (regmask & 0xff00UL)
6432 +       as_bad(_("register list `%s' doesn't fit"), str);
6433 +      regmask &= 0x00ffUL;
6434 +    }
6435 +  else if (regmask & 0xff00UL)
6436 +    {
6437 +      regmask >>= 8;
6438 +      h_bit = 1;
6439 +    }
6440 +  else
6441 +    as_warn(_("register list is empty"));
6442 +
6443 +  slot = current_insn.next_slot++;
6444 +  current_insn.field_value[slot].value = regmask;
6445 +  slot = current_insn.next_slot++;
6446 +  current_insn.field_value[slot].value = h_bit;
6447 +}
6448 +
6449 +static void
6450 +parse_pico_reglist_d(const struct avr32_operand *op ATTRIBUTE_UNUSED,
6451 +                    char *str, int opindex ATTRIBUTE_UNUSED)
6452 +{
6453 +  unsigned long regmask, regmask_d = 0;
6454 +  int slot, i;
6455 +  char *tail;
6456 +
6457 +  regmask = avr32_parse_pico_reglist(str, &tail);
6458 +  if (*tail)
6459 +    as_bad(_("junk at end of line: `%s'"), tail);
6460 +
6461 +  for (i = 0; i < 8; i++)
6462 +    {
6463 +      if (regmask & 1)
6464 +       {
6465 +         if (!(regmask & 2))
6466 +           {
6467 +             as_bad(_("register list `%s' doesn't fit"), str);
6468 +             break;
6469 +           }
6470 +         regmask_d |= 1 << i;
6471 +       }
6472 +      else if (regmask & 2)
6473 +       {
6474 +         as_bad(_("register list `%s' doesn't fit"), str);
6475 +         break;
6476 +       }
6477 +
6478 +      regmask >>= 2;
6479 +    }
6480 +
6481 +  slot = current_insn.next_slot++;
6482 +  current_insn.field_value[slot].value = regmask_d;
6483 +}
6484 +
6485 +static void
6486 +parse_pico_in(const struct avr32_operand *op ATTRIBUTE_UNUSED,
6487 +             char *str, int opindex ATTRIBUTE_UNUSED)
6488 +{
6489 +  unsigned long regid;
6490 +  int slot;
6491 +
6492 +  regid = strtoul(str + 2, NULL, 10);
6493 +
6494 +  if (regid >= 12)
6495 +    as_bad(_("invalid PiCo IN register `%s'"), str);
6496 +
6497 +  slot = current_insn.next_slot++;
6498 +  current_insn.field_value[slot].value = regid;
6499 +  current_insn.field_value[slot].align_order = 0;
6500 +}
6501 +
6502 +#define parse_pico_out0                parse_nothing
6503 +#define parse_pico_out1                parse_nothing
6504 +#define parse_pico_out2                parse_nothing
6505 +#define parse_pico_out3                parse_nothing
6506 +
6507 +#define OP(name, sgn, pcrel, align, func) \
6508 +  { AVR32_OPERAND_##name, sgn, pcrel, align, match_##func, parse_##func }
6509 +
6510 +struct avr32_operand avr32_operand_table[] = {
6511 +  OP(INTREG, 0, 0, 0, intreg),
6512 +  OP(INTREG_PREDEC, 0, 0, 0, intreg_predec),
6513 +  OP(INTREG_POSTINC, 0, 0, 0, intreg_postinc),
6514 +  OP(INTREG_LSL, 0, 0, 0, intreg_lsl),
6515 +  OP(INTREG_LSR, 0, 0, 0, intreg_lsr),
6516 +  OP(INTREG_BSEL, 0, 0, 0, intreg_part),
6517 +  OP(INTREG_HSEL, 0, 0, 1, intreg_part),
6518 +  OP(INTREG_SDISP, 1, 0, 0, intreg_disp),
6519 +  OP(INTREG_SDISP_H, 1, 0, 1, intreg_disp),
6520 +  OP(INTREG_SDISP_W, 1, 0, 2, intreg_disp),
6521 +  OP(INTREG_UDISP, 0, 0, 0, intreg_disp),
6522 +  OP(INTREG_UDISP_H, 0, 0, 1, intreg_disp),
6523 +  OP(INTREG_UDISP_W, 0, 0, 2, intreg_disp),
6524 +  OP(INTREG_INDEX, 0, 0, 0, intreg_index),
6525 +  OP(INTREG_XINDEX, 0, 0, 0, intreg_xindex),
6526 +  OP(DWREG, 0, 0, 1, intreg),
6527 +  OP(PC_UDISP_W, 0, 1, 2, pc_disp),
6528 +  OP(SP, 0, 0, 0, sp),
6529 +  OP(SP_UDISP_W, 0, 0, 2, sp_disp),
6530 +  OP(CPNO, 0, 0, 0, cpno),
6531 +  OP(CPREG, 0, 0, 0, cpreg),
6532 +  OP(CPREG_D, 0, 0, 1, cpreg),
6533 +  OP(UNSIGNED_CONST, 0, 0, 0, const),
6534 +  OP(UNSIGNED_CONST_W, 0, 0, 2, const),
6535 +  OP(SIGNED_CONST, 1, 0, 0, const),
6536 +  OP(SIGNED_CONST_W, 1, 0, 2, const),
6537 +  OP(JMPLABEL, 1, 1, 1, jmplabel),
6538 +  OP(UNSIGNED_NUMBER, 0, 0, 0, number),
6539 +  OP(UNSIGNED_NUMBER_W, 0, 0, 2, number),
6540 +  OP(REGLIST8, 0, 0, 0, reglist8),
6541 +  OP(REGLIST9, 0, 0, 0, reglist9),
6542 +  OP(REGLIST16, 0, 0, 0, reglist16),
6543 +  OP(REGLIST_LDM, 0, 0, 0, reglist_ldm),
6544 +  OP(REGLIST_CP8, 0, 0, 0, reglist_cp8),
6545 +  OP(REGLIST_CPD8, 0, 0, 0, reglist_cpd8),
6546 +  OP(RETVAL, 0, 0, 0, retval),
6547 +  OP(MCALL, 1, 0, 2, mcall),
6548 +  OP(JOSPINC, 0, 0, 0, jospinc),
6549 +  OP(COH, 0, 0, 0, coh),
6550 +  OP(FPREG_S, 0, 0, 0, fpreg),
6551 +  OP(FPREG_D, 0, 0, 1, fpreg),
6552 +  OP(PICO_REG_W, 0, 0, 0, picoreg),
6553 +  OP(PICO_REG_D, 0, 0, 1, picoreg),
6554 +  OP(PICO_REGLIST_W, 0, 0, 0, pico_reglist_w),
6555 +  OP(PICO_REGLIST_D, 0, 0, 0, pico_reglist_d),
6556 +  OP(PICO_IN, 0, 0, 0, pico_in),
6557 +  OP(PICO_OUT0, 0, 0, 0, pico_out0),
6558 +  OP(PICO_OUT1, 0, 0, 0, pico_out1),
6559 +  OP(PICO_OUT2, 0, 0, 0, pico_out2),
6560 +  OP(PICO_OUT3, 0, 0, 0, pico_out3),
6561 +};
6562 +
6563 +symbolS *
6564 +md_undefined_symbol (char *name ATTRIBUTE_UNUSED)
6565 +{
6566 +  pr_debug("md_undefined_symbol: %s\n", name);
6567 +  return 0;
6568 +}
6569 +
6570 +struct avr32_relax_type
6571 +{
6572 +  long lower_bound;
6573 +  long upper_bound;
6574 +  unsigned char align;
6575 +  unsigned char length;
6576 +  signed short next;
6577 +};
6578 +
6579 +#define EMPTY { 0, 0, 0, 0, -1 }
6580 +#define C(lower, upper, align, next)                   \
6581 +  { (lower), (upper), (align), 2, AVR32_OPC_##next }
6582 +#define E(lower, upper, align)                         \
6583 +  { (lower), (upper), (align), 4, -1 }
6584 +
6585 +static const struct avr32_relax_type avr32_relax_table[] =
6586 +  {
6587 +    /* 0 */
6588 +    EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY,
6589 +    EMPTY, EMPTY, EMPTY,
6590 +    E(0, 65535, 0), E(0, 65535, 0), E(0, 65535, 0), E(0, 65535, 0),
6591 +    EMPTY,
6592 +    /* 16 */
6593 +    EMPTY, EMPTY, EMPTY, EMPTY,
6594 +
6595 +    C(-256, 254, 1, BREQ2), C(-256, 254, 1, BRNE2),
6596 +    C(-256, 254, 1, BRCC2), C(-256, 254, 1, BRCS2),
6597 +    C(-256, 254, 1, BRGE2), C(-256, 254, 1, BRLT2),
6598 +    C(-256, 254, 1, BRMI2), C(-256, 254, 1, BRPL2),
6599 +    E(-2097152, 2097150, 1), E(-2097152, 2097150, 1),
6600 +    E(-2097152, 2097150, 1), E(-2097152, 2097150, 1),
6601 +    /* 32 */
6602 +    E(-2097152, 2097150, 1), E(-2097152, 2097150, 1),
6603 +    E(-2097152, 2097150, 1), E(-2097152, 2097150, 1),
6604 +    E(-2097152, 2097150, 1), E(-2097152, 2097150, 1),
6605 +    E(-2097152, 2097150, 1), E(-2097152, 2097150, 1),
6606 +    E(-2097152, 2097150, 1), E(-2097152, 2097150, 1),
6607 +    E(-2097152, 2097150, 1), E(-2097152, 2097150, 1),
6608 +
6609 +    EMPTY, EMPTY, EMPTY, EMPTY,
6610 +    /* 48 */
6611 +    EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY,
6612 +    EMPTY, EMPTY, EMPTY,
6613 +
6614 +    C(-32, 31, 0, CP_W3), E(-1048576, 1048575, 0),
6615 +
6616 +    EMPTY, EMPTY, EMPTY,
6617 +    /* 64: csrfcz */
6618 +    EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY,
6619 +    E(0, 65535, 0), E(0, 65535, 0),
6620 +    EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY,
6621 +    E(-32768, 32767, 0),
6622 +    /* 80: LD_SB2 */
6623 +    EMPTY, EMPTY, EMPTY, EMPTY, EMPTY,
6624 +
6625 +    C(0, 7, 0, LD_UB4), E(-32768, 32767, 0),
6626 +
6627 +    EMPTY,
6628 +    EMPTY, EMPTY,
6629 +
6630 +    C(0, 14, 1, LD_SH4), E(-32768, 32767, 0),
6631 +
6632 +    EMPTY, EMPTY, EMPTY,
6633 +
6634 +    C(0, 14, 1, LD_UH4),
6635 +
6636 +    /* 96: LD_UH4 */
6637 +    E(-32768, 32767, 0),
6638 +
6639 +    EMPTY, EMPTY, EMPTY, EMPTY,
6640 +
6641 +    C(0, 124, 2, LD_W4), E(-32768, 32767, 0),
6642 +
6643 +    E(0, 1020, 2),     /* LDC_D1 */
6644 +    EMPTY, EMPTY,
6645 +    E(0, 1020, 2),     /* LDC_W1 */
6646 +    EMPTY, EMPTY,
6647 +    E(0, 16380, 2),    /* LDC0_D */
6648 +    E(0, 16380, 2),    /* LDC0_W */
6649 +    EMPTY,
6650 +
6651 +    /* 112: LDCM_D_PU */
6652 +    EMPTY, EMPTY, EMPTY,
6653 +
6654 +    C(0, 508, 2, LDDPC_EXT), E(-32768, 32767, 0),
6655 +
6656 +    EMPTY,EMPTY, EMPTY,
6657 +    EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY,
6658 +
6659 +    EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY,
6660 +    /* 134: MACHH_W */
6661 +    EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY,
6662 +    E(-131072, 131068, 2),     /* MCALL */
6663 +    E(0, 1020, 2),             /* MFDR */
6664 +    E(0, 1020, 2),             /* MFSR */
6665 +    EMPTY, EMPTY,
6666 +
6667 +    C(-128, 127, 0, MOV2), E(-1048576, 1048575, 0),
6668 +
6669 +    EMPTY, EMPTY, EMPTY,
6670 +    EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY,
6671 +    EMPTY, EMPTY, EMPTY, EMPTY, EMPTY,
6672 +
6673 +    E(-128, 127, 0),           /* MOVEQ2 */
6674 +    E(-128, 127, 0),           /* MOVNE2 */
6675 +    E(-128, 127, 0),           /* MOVCC2 */
6676 +    E(-128, 127, 0),           /* 166: MOVCS2 */
6677 +    E(-128, 127, 0),           /* MOVGE2 */
6678 +    E(-128, 127, 0),           /* MOVLT2 */
6679 +    E(-128, 127, 0),           /* MOVMI2 */
6680 +    E(-128, 127, 0),           /* MOVPL2 */
6681 +    E(-128, 127, 0),           /* MOVLS2 */
6682 +    E(-128, 127, 0),           /* MOVGT2 */
6683 +    E(-128, 127, 0),           /* MOVLE2 */
6684 +    E(-128, 127, 0),           /* MOVHI2 */
6685 +    E(-128, 127, 0),           /* MOVVS2 */
6686 +    E(-128, 127, 0),           /* MOVVC2 */
6687 +    E(-128, 127, 0),           /* MOVQS2 */
6688 +    E(-128, 127, 0),           /* MOVAL2 */
6689 +
6690 +    E(0, 1020, 2),             /* MTDR */
6691 +    E(0, 1020, 2),             /* MTSR */
6692 +    EMPTY,
6693 +    EMPTY,
6694 +    E(-128, 127, 0),           /* MUL3 */
6695 +    EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY,
6696 +    EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY,
6697 +    /* 198: MVCR_W */
6698 +    EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY,
6699 +    E(0, 65535, 0), E(0, 65535, 0),
6700 +    EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY,
6701 +    EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY,
6702 +    EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY,
6703 +    /* 230: PASR_H */
6704 +    EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY,
6705 +    EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY,
6706 +    EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY,
6707 +    EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY,
6708 +    /* 262: PUNPCKSB_H */
6709 +    EMPTY, EMPTY, EMPTY, EMPTY, EMPTY,
6710 +
6711 +    C(-1024, 1022, 1, RCALL2), E(-2097152, 2097150, 1),
6712 +
6713 +    EMPTY,
6714 +    EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY,
6715 +    EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY,
6716 +    EMPTY, EMPTY, EMPTY,
6717 +
6718 +    C(-1024, 1022, 1, BRAL),
6719 +
6720 +    EMPTY, EMPTY, EMPTY,
6721 +    E(-128, 127, 0),           /* RSUB2 */
6722 +    /* 294: SATADD_H */
6723 +    EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY,
6724 +    EMPTY, EMPTY, EMPTY, EMPTY, EMPTY,
6725 +    E(0, 255, 0),              /* SLEEP */
6726 +    EMPTY, EMPTY,
6727 +    EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY,
6728 +    EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY,
6729 +    /* 326: ST_B2 */
6730 +    EMPTY, EMPTY,
6731 +    C(0, 7, 0, ST_B4), E(-32768, 32767, 0),
6732 +    EMPTY, EMPTY, EMPTY, EMPTY,
6733 +    E(-32768, 32767, 0),
6734 +    EMPTY, EMPTY, EMPTY,
6735 +    C(0, 14, 1, ST_H4), E(-32768, 32767, 0),
6736 +    EMPTY, EMPTY,
6737 +    EMPTY,
6738 +    C(0, 60, 2, ST_W4), E(-32768, 32767, 0),
6739 +    E(0, 1020, 2),     /* STC_D1 */
6740 +    EMPTY, EMPTY,
6741 +    E(0, 1020, 2),     /* STC_W1 */
6742 +    EMPTY, EMPTY,
6743 +    E(0, 16380, 2),    /* STC0_D */
6744 +    E(0, 16380, 2),    /* STC0_W */
6745 +
6746 +    EMPTY, EMPTY, EMPTY, EMPTY, EMPTY,
6747 +    /* 358: STDSP */
6748 +    EMPTY, EMPTY,
6749 +    E(0, 1020, 2),     /* STHH_W1 */
6750 +    EMPTY, EMPTY, EMPTY, EMPTY, EMPTY,
6751 +    EMPTY, EMPTY, EMPTY,
6752 +    E(-32768, 32767, 0),
6753 +    C(-512, 508, 2, SUB4),
6754 +    C(-128, 127, 0, SUB4), E(-1048576, 1048576, 0),
6755 +    /* SUB{cond} */
6756 +    E(-128, 127, 0), E(-128, 127, 0), E(-128, 127, 0), E(-128, 127, 0),
6757 +    E(-128, 127, 0), E(-128, 127, 0), E(-128, 127, 0), E(-128, 127, 0),
6758 +    E(-128, 127, 0), E(-128, 127, 0), E(-128, 127, 0), E(-128, 127, 0),
6759 +    E(-128, 127, 0), E(-128, 127, 0), E(-128, 127, 0), E(-128, 127, 0),
6760 +    /* SUBF{cond} */
6761 +    E(-128, 127, 0), E(-128, 127, 0), E(-128, 127, 0), E(-128, 127, 0),
6762 +    E(-128, 127, 0), E(-128, 127, 0), E(-128, 127, 0), E(-128, 127, 0),
6763 +    E(-128, 127, 0), E(-128, 127, 0), E(-128, 127, 0), E(-128, 127, 0),
6764 +    E(-128, 127, 0), E(-128, 127, 0), E(-128, 127, 0), E(-128, 127, 0),
6765 +    EMPTY,
6766 +
6767 +    /* 406: SWAP_B */
6768 +    EMPTY, EMPTY, EMPTY,
6769 +    E(0, 255, 0),      /* SYNC */
6770 +    EMPTY, EMPTY, EMPTY, EMPTY,
6771 +    /* 414: TST */
6772 +    EMPTY, EMPTY, E(-65536, 65535, 2), E(-65536, 65535, 2), E(-65536, 65535, 2), EMPTY, EMPTY, EMPTY,
6773 +    /* 422: RSUB{cond} */
6774 +    E(-128, 127, 0), E(-128, 127, 0), E(-128, 127, 0), E(-128, 127, 0),
6775 +    E(-128, 127, 0), E(-128, 127, 0), E(-128, 127, 0), E(-128, 127, 0),
6776 +    E(-128, 127, 0), E(-128, 127, 0), E(-128, 127, 0), E(-128, 127, 0),
6777 +    E(-128, 127, 0), E(-128, 127, 0), E(-128, 127, 0), E(-128, 127, 0),
6778 +    /* 436: ADD{cond} */
6779 +    EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY,
6780 +    EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY,
6781 +    /* 454: SUB{cond} */
6782 +    EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY,
6783 +    EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY,
6784 +    /* 472: AND{cond} */
6785 +    EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY,
6786 +    EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY,
6787 +    /* 486: OR{cond} */
6788 +    EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY,
6789 +    EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY,
6790 +    /* 502: EOR{cond} */
6791 +    EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY,
6792 +    EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY,
6793 +    /* 518: LD.w{cond} */
6794 +    EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY,
6795 +    EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY,
6796 +    /* 534: LD.sh{cond} */
6797 +    EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY,
6798 +    EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY,
6799 +    /* 550: LD.uh{cond} */
6800 +    EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY,
6801 +    EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY,
6802 +    /* 566: LD.sb{cond} */
6803 +    EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY,
6804 +    EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY,
6805 +    /* 582: LD.ub{cond} */
6806 +    EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY,
6807 +    EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY,
6808 +    /* 596: ST.w{cond} */
6809 +    EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY,
6810 +    EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY,
6811 +    /* 614: ST.h{cond} */
6812 +    EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY,
6813 +    EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY,
6814 +    /* 630: ST.b{cond} */
6815 +    EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY,
6816 +    EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY,
6817 +    /* 646: movh */
6818 +    E(0, 65535, 0), EMPTY, EMPTY,
6819 +  };
6820 +
6821 +#undef E
6822 +#undef C
6823 +#undef EMPTY
6824 +
6825 +#define AVR32_RS_NONE (-1)
6826 +
6827 +#define avr32_rs_size(state) (avr32_relax_table[(state)].length)
6828 +#define avr32_rs_align(state) (avr32_relax_table[(state)].align)
6829 +#define relax_more(state) (avr32_relax_table[(state)].next)
6830 +
6831 +#define opc_initial_substate(opc) ((opc)->id)
6832 +
6833 +static int need_relax(int subtype, offsetT distance)
6834 +{
6835 +  offsetT upper_bound, lower_bound;
6836 +
6837 +  upper_bound = avr32_relax_table[subtype].upper_bound;
6838 +  lower_bound = avr32_relax_table[subtype].lower_bound;
6839 +
6840 +  if (distance & ((1 << avr32_rs_align(subtype)) - 1))
6841 +    return 1;
6842 +  if ((distance > upper_bound) || (distance < lower_bound))
6843 +    return 1;
6844 +
6845 +  return 0;
6846 +}
6847 +
6848 +enum {
6849 +  LDA_SUBTYPE_MOV1,
6850 +  LDA_SUBTYPE_MOV2,
6851 +  LDA_SUBTYPE_SUB,
6852 +  LDA_SUBTYPE_LDDPC,
6853 +  LDA_SUBTYPE_LDW,
6854 +  LDA_SUBTYPE_GOTLOAD,
6855 +  LDA_SUBTYPE_GOTLOAD_LARGE,
6856 +};
6857 +
6858 +enum {
6859 +  CALL_SUBTYPE_RCALL1,
6860 +  CALL_SUBTYPE_RCALL2,
6861 +  CALL_SUBTYPE_MCALL_CP,
6862 +  CALL_SUBTYPE_MCALL_GOT,
6863 +  CALL_SUBTYPE_MCALL_LARGE,
6864 +};
6865 +
6866 +#define LDA_INITIAL_SIZE       (avr32_pic ? 4 : 2)
6867 +#define CALL_INITIAL_SIZE      2
6868 +
6869 +#define need_reloc(sym, seg, pcrel)                                    \
6870 +  (!(S_IS_DEFINED(sym)                                                 \
6871 +     && ((pcrel && S_GET_SEGMENT(sym) == seg)                          \
6872 +        || (!pcrel && S_GET_SEGMENT(sym) == absolute_section)))        \
6873 +   || S_FORCE_RELOC(sym, 1))
6874 +
6875 +/* Return an initial guess of the length by which a fragment must grow to
6876 +   hold a branch to reach its destination.
6877 +   Also updates fr_type/fr_subtype as necessary.
6878 +
6879 +   Called just before doing relaxation.
6880 +   Any symbol that is now undefined will not become defined.
6881 +   The guess for fr_var is ACTUALLY the growth beyond fr_fix.
6882 +   Whatever we do to grow fr_fix or fr_var contributes to our returned value.
6883 +   Although it may not be explicit in the frag, pretend fr_var starts with a
6884 +   0 value.  */
6885 +
6886 +static int
6887 +avr32_default_estimate_size_before_relax (fragS *fragP, segT segment)
6888 +{
6889 +  int growth = 0;
6890 +
6891 +  assert(fragP);
6892 +  assert(fragP->fr_symbol);
6893 +
6894 +  if (fragP->tc_frag_data.force_extended
6895 +      || need_reloc(fragP->fr_symbol, segment, fragP->tc_frag_data.pcrel))
6896 +    {
6897 +      int largest_state = fragP->fr_subtype;
6898 +      while (relax_more(largest_state) != AVR32_RS_NONE)
6899 +       largest_state = relax_more(largest_state);
6900 +      growth = avr32_rs_size(largest_state) - fragP->fr_var;
6901 +    }
6902 +  else
6903 +    {
6904 +      growth = avr32_rs_size(fragP->fr_subtype) - fragP->fr_var;
6905 +    }
6906 +
6907 +  pr_debug("%s:%d: md_estimate_size_before_relax: %d\n",
6908 +          fragP->fr_file, fragP->fr_line, growth);
6909 +
6910 +  return growth;
6911 +}
6912 +
6913 +static int
6914 +avr32_lda_estimate_size_before_relax(fragS *fragP, segT segment ATTRIBUTE_UNUSED)
6915 +{
6916 +  return fragP->fr_var - LDA_INITIAL_SIZE;
6917 +}
6918 +
6919 +static int
6920 +avr32_call_estimate_size_before_relax(fragS *fragP, segT segment ATTRIBUTE_UNUSED)
6921 +{
6922 +  return fragP->fr_var - CALL_INITIAL_SIZE;
6923 +}
6924 +
6925 +static int
6926 +avr32_cpool_estimate_size_before_relax(fragS *fragP,
6927 +                                      segT segment ATTRIBUTE_UNUSED)
6928 +{
6929 +  return fragP->fr_var;
6930 +}
6931 +
6932 +/* This macro may be defined to relax a frag. GAS will call this with the
6933 + * segment, the frag, and the change in size of all previous frags;
6934 + * md_relax_frag should return the change in size of the frag. */
6935 +static long
6936 +avr32_default_relax_frag (segT segment, fragS *fragP, long stretch)
6937 +{
6938 +  int state, next_state;
6939 +  symbolS *symbolP;    /* The target symbol */
6940 +  long growth = 0;
6941 +
6942 +  state = next_state = fragP->fr_subtype;
6943 +
6944 +  symbolP = fragP->fr_symbol;
6945 +
6946 +  if (fragP->tc_frag_data.force_extended
6947 +      || need_reloc(symbolP, segment, fragP->tc_frag_data.pcrel))
6948 +    {
6949 +      /* Symbol must be resolved by the linker. Emit the largest
6950 +        possible opcode. */
6951 +      while (relax_more(next_state) != AVR32_RS_NONE)
6952 +       next_state = relax_more(next_state);
6953 +    }
6954 +  else
6955 +    {
6956 +      addressT address;        /* The address of fragP */
6957 +      addressT target; /* The address of the target symbol */
6958 +      offsetT distance;        /* The distance between the insn and the symbol */
6959 +      fragS *sym_frag;
6960 +
6961 +      address = fragP->fr_address;
6962 +      target = fragP->fr_offset;
6963 +      symbolP = fragP->fr_symbol;
6964 +      sym_frag = symbol_get_frag(symbolP);
6965 +
6966 +      address += fragP->fr_fix - fragP->fr_var;
6967 +      target += S_GET_VALUE(symbolP);
6968 +
6969 +      if (stretch != 0
6970 +         && sym_frag->relax_marker != fragP->relax_marker
6971 +         && S_GET_SEGMENT(symbolP) == segment)
6972 +       /* if it was correctly aligned before, make sure it stays aligned */
6973 +       target += stretch & (~0UL << avr32_rs_align(state));
6974 +
6975 +      if (fragP->tc_frag_data.pcrel)
6976 +       distance = target - (address & (~0UL << avr32_rs_align(state)));
6977 +      else
6978 +       distance = target;
6979 +
6980 +      pr_debug("%s:%d: relax more? 0x%x - 0x%x = 0x%x (%d), align %d\n",
6981 +              fragP->fr_file, fragP->fr_line, target, address,
6982 +              distance, distance, avr32_rs_align(state));
6983 +
6984 +      if (need_relax(state, distance))
6985 +       {
6986 +         if (relax_more(state) != AVR32_RS_NONE)
6987 +           next_state = relax_more(state);
6988 +         pr_debug("%s:%d: relax more %d -> %d (%d - %d, align %d)\n",
6989 +                  fragP->fr_file, fragP->fr_line, state, next_state,
6990 +                  target, address, avr32_rs_align(state));
6991 +       }
6992 +    }
6993 +
6994 +  growth = avr32_rs_size(next_state) - avr32_rs_size(state);
6995 +  fragP->fr_subtype = next_state;
6996 +
6997 +  pr_debug("%s:%d: md_relax_frag: growth=%d, subtype=%d, opc=0x%08lx\n",
6998 +          fragP->fr_file, fragP->fr_line, growth, fragP->fr_subtype,
6999 +          avr32_opc_table[next_state].value);
7000 +
7001 +  return growth;
7002 +}
7003 +
7004 +static long
7005 +avr32_lda_relax_frag(segT segment, fragS *fragP, long stretch)
7006 +{
7007 +  struct cpool *pool= NULL;
7008 +  unsigned int entry = 0;
7009 +  addressT address, target;
7010 +  offsetT distance;
7011 +  symbolS *symbolP;
7012 +  fragS *sym_frag;
7013 +  long old_size, new_size;
7014 +
7015 +  symbolP = fragP->fr_symbol;
7016 +  old_size = fragP->fr_var;
7017 +  if (!avr32_pic)
7018 +    {
7019 +      pool = fragP->tc_frag_data.pool;
7020 +      entry = fragP->tc_frag_data.pool_entry;
7021 +    }
7022 +
7023 +  address = fragP->fr_address;
7024 +  address += fragP->fr_fix - LDA_INITIAL_SIZE;
7025 +
7026 +  if (!S_IS_DEFINED(symbolP) || S_FORCE_RELOC(symbolP, 1))
7027 +    goto relax_max;
7028 +
7029 +  target = fragP->fr_offset;
7030 +  sym_frag = symbol_get_frag(symbolP);
7031 +  target += S_GET_VALUE(symbolP);
7032 +
7033 +  if (sym_frag->relax_marker != fragP->relax_marker
7034 +      && S_GET_SEGMENT(symbolP) == segment)
7035 +    target += stretch;
7036 +
7037 +  distance = target - address;
7038 +
7039 +  pr_debug("lda_relax_frag: target: %d, address: %d, var: %d\n",
7040 +          target, address, fragP->fr_var);
7041 +
7042 +  if (!avr32_pic && S_GET_SEGMENT(symbolP) == absolute_section
7043 +      && target <= 127 && (offsetT)target >= -128)
7044 +    {
7045 +      if (fragP->fr_subtype == LDA_SUBTYPE_LDDPC
7046 +         || fragP->fr_subtype == LDA_SUBTYPE_LDW)
7047 +       pool->literals[entry].refcount--;
7048 +      new_size = 2;
7049 +      fragP->fr_subtype = LDA_SUBTYPE_MOV1;
7050 +    }
7051 +  else if (!avr32_pic && S_GET_SEGMENT(symbolP) == absolute_section
7052 +          && target <= 1048575 && (offsetT)target >= -1048576)
7053 +    {
7054 +      if (fragP->fr_subtype == LDA_SUBTYPE_LDDPC
7055 +         || fragP->fr_subtype == LDA_SUBTYPE_LDW)
7056 +       pool->literals[entry].refcount--;
7057 +      new_size = 4;
7058 +      fragP->fr_subtype = LDA_SUBTYPE_MOV2;
7059 +    }
7060 +  else if (!linkrelax && S_GET_SEGMENT(symbolP) == segment
7061 +          /* the field will be negated, so this is really -(-32768)
7062 +             and -(32767) */
7063 +          && distance <= 32768 && distance >= -32767)
7064 +    {
7065 +      if (!avr32_pic
7066 +         && (fragP->fr_subtype == LDA_SUBTYPE_LDDPC
7067 +             || fragP->fr_subtype == LDA_SUBTYPE_LDW))
7068 +       pool->literals[entry].refcount--;
7069 +      new_size = 4;
7070 +      fragP->fr_subtype = LDA_SUBTYPE_SUB;
7071 +    }
7072 +  else
7073 +    {
7074 +    relax_max:
7075 +      if (avr32_pic)
7076 +       {
7077 +         if (linkrelax)
7078 +           {
7079 +             new_size = 8;
7080 +             fragP->fr_subtype = LDA_SUBTYPE_GOTLOAD_LARGE;
7081 +           }
7082 +         else
7083 +           {
7084 +             new_size = 4;
7085 +             fragP->fr_subtype = LDA_SUBTYPE_GOTLOAD;
7086 +           }
7087 +       }
7088 +      else
7089 +       {
7090 +         if (fragP->fr_subtype != LDA_SUBTYPE_LDDPC
7091 +             && fragP->fr_subtype != LDA_SUBTYPE_LDW)
7092 +           pool->literals[entry].refcount++;
7093 +
7094 +         sym_frag = symbol_get_frag(pool->symbol);
7095 +         target = (sym_frag->fr_address + sym_frag->fr_fix
7096 +                   + pool->padding + pool->literals[entry].offset);
7097 +
7098 +         pr_debug("cpool sym address: 0x%lx\n",
7099 +                  sym_frag->fr_address + sym_frag->fr_fix);
7100 +
7101 +         know(pool->section == segment);
7102 +
7103 +         if (sym_frag->relax_marker != fragP->relax_marker)
7104 +           target += stretch;
7105 +
7106 +         distance = target - address;
7107 +         if (distance <= 508 && distance >= 0)
7108 +           {
7109 +             new_size = 2;
7110 +             fragP->fr_subtype = LDA_SUBTYPE_LDDPC;
7111 +           }
7112 +         else
7113 +           {
7114 +             new_size = 4;
7115 +             fragP->fr_subtype = LDA_SUBTYPE_LDW;
7116 +           }
7117 +
7118 +         pr_debug("lda_relax_frag (cpool): target=0x%lx, address=0x%lx, refcount=%d\n",
7119 +                  target, address, pool->literals[entry].refcount);
7120 +       }
7121 +    }
7122 +
7123 +  fragP->fr_var = new_size;
7124 +
7125 +  pr_debug("%s:%d: lda: relax pass done. subtype: %d, growth: %ld\n",
7126 +          fragP->fr_file, fragP->fr_line,
7127 +          fragP->fr_subtype, new_size - old_size);
7128 +
7129 +  return new_size - old_size;
7130 +}
7131 +
7132 +static long
7133 +avr32_call_relax_frag(segT segment, fragS *fragP, long stretch)
7134 +{
7135 +  struct cpool *pool = NULL;
7136 +  unsigned int entry = 0;
7137 +  addressT address, target;
7138 +  offsetT distance;
7139 +  symbolS *symbolP;
7140 +  fragS *sym_frag;
7141 +  long old_size, new_size;
7142 +
7143 +  symbolP = fragP->fr_symbol;
7144 +  old_size = fragP->fr_var;
7145 +  if (!avr32_pic)
7146 +    {
7147 +      pool = fragP->tc_frag_data.pool;
7148 +      entry = fragP->tc_frag_data.pool_entry;
7149 +    }
7150 +
7151 +  address = fragP->fr_address;
7152 +  address += fragP->fr_fix - CALL_INITIAL_SIZE;
7153 +
7154 +  if (need_reloc(symbolP, segment, 1))
7155 +    {
7156 +      pr_debug("call: must emit reloc\n");
7157 +      goto relax_max;
7158 +    }
7159 +
7160 +  target = fragP->fr_offset;
7161 +  sym_frag = symbol_get_frag(symbolP);
7162 +  target += S_GET_VALUE(symbolP);
7163 +
7164 +  if (sym_frag->relax_marker != fragP->relax_marker
7165 +      && S_GET_SEGMENT(symbolP) == segment)
7166 +    target += stretch;
7167 +
7168 +  distance = target - address;
7169 +
7170 +  if (distance <= 1022 && distance >= -1024)
7171 +    {
7172 +      pr_debug("call: distance is %d, emitting short rcall\n", distance);
7173 +      if (!avr32_pic && fragP->fr_subtype == CALL_SUBTYPE_MCALL_CP)
7174 +       pool->literals[entry].refcount--;
7175 +      new_size = 2;
7176 +      fragP->fr_subtype = CALL_SUBTYPE_RCALL1;
7177 +    }
7178 +  else if (distance <= 2097150 && distance >= -2097152)
7179 +    {
7180 +      pr_debug("call: distance is %d, emitting long rcall\n", distance);
7181 +      if (!avr32_pic && fragP->fr_subtype == CALL_SUBTYPE_MCALL_CP)
7182 +       pool->literals[entry].refcount--;
7183 +      new_size = 4;
7184 +      fragP->fr_subtype = CALL_SUBTYPE_RCALL2;
7185 +    }
7186 +  else
7187 +    {
7188 +      pr_debug("call: distance %d too far, emitting something big\n", distance);
7189 +
7190 +    relax_max:
7191 +      if (avr32_pic)
7192 +       {
7193 +         if (linkrelax)
7194 +           {
7195 +             new_size = 10;
7196 +             fragP->fr_subtype = CALL_SUBTYPE_MCALL_LARGE;
7197 +           }
7198 +         else
7199 +           {
7200 +             new_size = 4;
7201 +             fragP->fr_subtype = CALL_SUBTYPE_MCALL_GOT;
7202 +           }
7203 +       }
7204 +      else
7205 +       {
7206 +         if (fragP->fr_subtype != CALL_SUBTYPE_MCALL_CP)
7207 +           pool->literals[entry].refcount++;
7208 +
7209 +         new_size = 4;
7210 +         fragP->fr_subtype = CALL_SUBTYPE_MCALL_CP;
7211 +       }
7212 +    }
7213 +
7214 +  fragP->fr_var = new_size;
7215 +
7216 +  pr_debug("%s:%d: call: relax pass done, growth: %d, fr_var: %d\n",
7217 +          fragP->fr_file, fragP->fr_line,
7218 +          new_size - old_size, fragP->fr_var);
7219 +
7220 +  return new_size - old_size;
7221 +}
7222 +
7223 +static long
7224 +avr32_cpool_relax_frag(segT segment ATTRIBUTE_UNUSED,
7225 +                      fragS *fragP,
7226 +                      long stretch ATTRIBUTE_UNUSED)
7227 +{
7228 +  struct cpool *pool;
7229 +  addressT address;
7230 +  long old_size, new_size;
7231 +  unsigned int entry;
7232 +
7233 +  pool = fragP->tc_frag_data.pool;
7234 +  address = fragP->fr_address + fragP->fr_fix;
7235 +  old_size = fragP->fr_var;
7236 +  new_size = 0;
7237 +
7238 +  for (entry = 0; entry < pool->next_free_entry; entry++)
7239 +    {
7240 +      if (pool->literals[entry].refcount > 0)
7241 +       {
7242 +         pool->literals[entry].offset = new_size;
7243 +         new_size += 4;
7244 +       }
7245 +    }
7246 +
7247 +  fragP->fr_var = new_size;
7248 +
7249 +  return new_size - old_size;
7250 +}
7251 +
7252 +/* *fragP has been relaxed to its final size, and now needs to have
7253 +   the bytes inside it modified to conform to the new size.
7254 +
7255 +   Called after relaxation is finished.
7256 +   fragP->fr_type == rs_machine_dependent.
7257 +   fragP->fr_subtype is the subtype of what the address relaxed to.  */
7258 +
7259 +static void
7260 +avr32_default_convert_frag (bfd *abfd ATTRIBUTE_UNUSED,
7261 +                           segT segment ATTRIBUTE_UNUSED,
7262 +                           fragS *fragP)
7263 +{
7264 +  const struct avr32_opcode *opc;
7265 +  const struct avr32_ifield *ifield;
7266 +  bfd_reloc_code_real_type r_type;
7267 +  symbolS *symbolP;
7268 +  fixS *fixP;
7269 +  bfd_vma value;
7270 +  int subtype;
7271 +
7272 +  opc = &avr32_opc_table[fragP->fr_subtype];
7273 +  ifield = opc->fields[opc->var_field];
7274 +  symbolP = fragP->fr_symbol;
7275 +  subtype = fragP->fr_subtype;
7276 +  r_type = opc->reloc_type;
7277 +
7278 +  /* Clear the opcode bits and the bits belonging to the relaxed
7279 +     field.  We assume all other fields stay the same.  */
7280 +  value = bfd_getb32(fragP->fr_opcode);
7281 +  value &= ~(opc->mask | ifield->mask);
7282 +
7283 +  /* Insert the new opcode */
7284 +  value |= opc->value;
7285 +  bfd_putb32(value, fragP->fr_opcode);
7286 +
7287 +  fragP->fr_fix += opc->size - fragP->fr_var;
7288 +
7289 +  if (fragP->tc_frag_data.reloc_info != AVR32_OPINFO_NONE)
7290 +    {
7291 +      switch (fragP->tc_frag_data.reloc_info)
7292 +       {
7293 +       case AVR32_OPINFO_HI:
7294 +         r_type = BFD_RELOC_HI16;
7295 +         break;
7296 +       case AVR32_OPINFO_LO:
7297 +         r_type = BFD_RELOC_LO16;
7298 +         break;
7299 +       case AVR32_OPINFO_GOT:
7300 +         switch (r_type)
7301 +           {
7302 +           case BFD_RELOC_AVR32_18W_PCREL:
7303 +             r_type = BFD_RELOC_AVR32_GOT18SW;
7304 +             break;
7305 +           case BFD_RELOC_AVR32_16S:
7306 +             r_type = BFD_RELOC_AVR32_GOT16S;
7307 +             break;
7308 +           default:
7309 +             BAD_CASE(r_type);
7310 +             break;
7311 +           }
7312 +         break;
7313 +       default:
7314 +         BAD_CASE(fragP->tc_frag_data.reloc_info);
7315 +         break;
7316 +       }
7317 +    }
7318 +
7319 +  pr_debug("%s:%d: convert_frag: new %s fixup\n",
7320 +          fragP->fr_file, fragP->fr_line,
7321 +          bfd_get_reloc_code_name(r_type));
7322 +
7323 +#if 1
7324 +  fixP = fix_new_exp(fragP, fragP->fr_fix - opc->size, opc->size,
7325 +                    &fragP->tc_frag_data.exp,
7326 +                    fragP->tc_frag_data.pcrel, r_type);
7327 +#else
7328 +  fixP = fix_new(fragP, fragP->fr_fix - opc->size, opc->size, symbolP,
7329 +                fragP->fr_offset, fragP->tc_frag_data.pcrel, r_type);
7330 +#endif
7331 +
7332 +  /* Revert fix_new brain damage. "dot_value" is the value of PC at
7333 +     the point of the fixup, relative to the frag address.  fix_new()
7334 +     and friends think they are only being called during the assembly
7335 +     pass, not during relaxation or similar, so fx_dot_value, fx_file
7336 +     and fx_line are all initialized to the wrong value.  But we don't
7337 +     know the size of the fixup until now, so we really can't live up
7338 +     to the assumptions these functions make about the target.  What
7339 +     do these functions think the "where" and "frag" argument mean
7340 +     anyway?  */
7341 +  fixP->fx_dot_value = fragP->fr_fix - opc->size;
7342 +  fixP->fx_file = fragP->fr_file;
7343 +  fixP->fx_line = fragP->fr_line;
7344 +
7345 +  fixP->tc_fix_data.ifield = ifield;
7346 +  fixP->tc_fix_data.align = avr32_rs_align(subtype);
7347 +  fixP->tc_fix_data.min = avr32_relax_table[subtype].lower_bound;
7348 +  fixP->tc_fix_data.max = avr32_relax_table[subtype].upper_bound;
7349 +}
7350 +
7351 +static void
7352 +avr32_lda_convert_frag(bfd *abfd ATTRIBUTE_UNUSED,
7353 +                      segT segment ATTRIBUTE_UNUSED,
7354 +                      fragS *fragP)
7355 +{
7356 +  const struct avr32_opcode *opc;
7357 +  const struct avr32_ifield *ifield;
7358 +  bfd_reloc_code_real_type r_type;
7359 +  expressionS exp;
7360 +  struct cpool *pool;
7361 +  fixS *fixP;
7362 +  bfd_vma value;
7363 +  int regid, pcrel = 0, align = 0;
7364 +  char *p;
7365 +
7366 +  r_type = BFD_RELOC_NONE;
7367 +  regid = fragP->tc_frag_data.reloc_info;
7368 +  p = fragP->fr_opcode;
7369 +  exp.X_add_symbol = fragP->fr_symbol;
7370 +  exp.X_add_number = fragP->fr_offset;
7371 +  exp.X_op = O_symbol;
7372 +
7373 +  pr_debug("%s:%d: lda_convert_frag, subtype: %d, fix: %d, var: %d, regid: %d\n",
7374 +          fragP->fr_file, fragP->fr_line,
7375 +          fragP->fr_subtype, fragP->fr_fix, fragP->fr_var, regid);
7376 +
7377 +  switch (fragP->fr_subtype)
7378 +    {
7379 +    case LDA_SUBTYPE_MOV1:
7380 +      opc = &avr32_opc_table[AVR32_OPC_MOV1];
7381 +      opc->fields[0]->insert(opc->fields[0], p, regid);
7382 +      ifield = opc->fields[1];
7383 +      r_type = opc->reloc_type;
7384 +      break;
7385 +    case LDA_SUBTYPE_MOV2:
7386 +      opc = &avr32_opc_table[AVR32_OPC_MOV2];
7387 +      opc->fields[0]->insert(opc->fields[0], p, regid);
7388 +      ifield = opc->fields[1];
7389 +      r_type = opc->reloc_type;
7390 +      break;
7391 +    case LDA_SUBTYPE_SUB:
7392 +      opc = &avr32_opc_table[AVR32_OPC_SUB5];
7393 +      opc->fields[0]->insert(opc->fields[0], p, regid);
7394 +      opc->fields[1]->insert(opc->fields[1], p, AVR32_REG_PC);
7395 +      ifield = opc->fields[2];
7396 +      r_type = BFD_RELOC_AVR32_16N_PCREL;
7397 +
7398 +      /* Pretend that SUB5 isn't a "negated" pcrel expression for now.
7399 +        We'll have to fix it up later when we know whether to
7400 +        generate a reloc for it (in which case the linker will negate
7401 +        it, so we shouldn't). */
7402 +      pcrel = 1;
7403 +      break;
7404 +    case LDA_SUBTYPE_LDDPC:
7405 +      opc = &avr32_opc_table[AVR32_OPC_LDDPC];
7406 +      align = 2;
7407 +      r_type = BFD_RELOC_AVR32_9W_CP;
7408 +      goto cpool_common;
7409 +    case LDA_SUBTYPE_LDW:
7410 +      opc = &avr32_opc_table[AVR32_OPC_LDDPC_EXT];
7411 +      r_type = BFD_RELOC_AVR32_16_CP;
7412 +    cpool_common:
7413 +      opc->fields[0]->insert(opc->fields[0], p, regid);
7414 +      ifield = opc->fields[1];
7415 +      pool = fragP->tc_frag_data.pool;
7416 +      exp.X_add_symbol = pool->symbol;
7417 +      exp.X_add_number = pool->literals[fragP->tc_frag_data.pool_entry].offset;
7418 +      pcrel = 1;
7419 +      break;
7420 +    case LDA_SUBTYPE_GOTLOAD_LARGE:
7421 +      /* ld.w Rd, r6[Rd << 2] (last) */
7422 +      opc = &avr32_opc_table[AVR32_OPC_LD_W5];
7423 +      bfd_putb32(opc->value, p + 4);
7424 +      opc->fields[0]->insert(opc->fields[0], p + 4, regid);
7425 +      opc->fields[1]->insert(opc->fields[1], p + 4, 6);
7426 +      opc->fields[2]->insert(opc->fields[2], p + 4, regid);
7427 +      opc->fields[3]->insert(opc->fields[3], p + 4, 2);
7428 +
7429 +      /* mov Rd, (got_offset / 4) */
7430 +      opc = &avr32_opc_table[AVR32_OPC_MOV2];
7431 +      opc->fields[0]->insert(opc->fields[0], p, regid);
7432 +      ifield = opc->fields[1];
7433 +      r_type = BFD_RELOC_AVR32_LDA_GOT;
7434 +      break;
7435 +    case LDA_SUBTYPE_GOTLOAD:
7436 +      opc = &avr32_opc_table[AVR32_OPC_LD_W4];
7437 +      opc->fields[0]->insert(opc->fields[0], p, regid);
7438 +      opc->fields[1]->insert(opc->fields[1], p, 6);
7439 +      ifield = opc->fields[2];
7440 +      if (r_type == BFD_RELOC_NONE)
7441 +       r_type = BFD_RELOC_AVR32_GOT16S;
7442 +      break;
7443 +    default:
7444 +      BAD_CASE(fragP->fr_subtype);
7445 +    }
7446 +
7447 +  value = bfd_getb32(p);
7448 +  value &= ~(opc->mask | ifield->mask);
7449 +  value |= opc->value;
7450 +  bfd_putb32(value, p);
7451 +
7452 +  fragP->fr_fix += fragP->fr_var - LDA_INITIAL_SIZE;
7453 +
7454 +  if (fragP->fr_next
7455 +      && ((offsetT)(fragP->fr_next->fr_address - fragP->fr_address)
7456 +         != fragP->fr_fix))
7457 +    {
7458 +      fprintf(stderr, "LDA frag: fr_fix is wrong! fragP->fr_var = %ld, r_type = %s\n",
7459 +             fragP->fr_var, bfd_get_reloc_code_name(r_type));
7460 +      abort();
7461 +    }
7462 +
7463 +  fixP = fix_new_exp(fragP, fragP->fr_fix - fragP->fr_var, fragP->fr_var,
7464 +                    &exp, pcrel, r_type);
7465 +
7466 +  /* Revert fix_new brain damage. "dot_value" is the value of PC at
7467 +     the point of the fixup, relative to the frag address.  fix_new()
7468 +     and friends think they are only being called during the assembly
7469 +     pass, not during relaxation or similar, so fx_dot_value, fx_file
7470 +     and fx_line are all initialized to the wrong value.  But we don't
7471 +     know the size of the fixup until now, so we really can't live up
7472 +     to the assumptions these functions make about the target.  What
7473 +     do these functions think the "where" and "frag" argument mean
7474 +     anyway?  */
7475 +  fixP->fx_dot_value = fragP->fr_fix - opc->size;
7476 +  fixP->fx_file = fragP->fr_file;
7477 +  fixP->fx_line = fragP->fr_line;
7478 +
7479 +  fixP->tc_fix_data.ifield = ifield;
7480 +  fixP->tc_fix_data.align = align;
7481 +  /* these are only used if the fixup can actually be resolved */
7482 +  fixP->tc_fix_data.min = -32768;
7483 +  fixP->tc_fix_data.max = 32767;
7484 +}
7485 +
7486 +static void
7487 +avr32_call_convert_frag(bfd *abfd ATTRIBUTE_UNUSED,
7488 +                      segT segment ATTRIBUTE_UNUSED,
7489 +                      fragS *fragP)
7490 +{
7491 +  const struct avr32_opcode *opc = NULL;
7492 +  const struct avr32_ifield *ifield;
7493 +  bfd_reloc_code_real_type r_type;
7494 +  symbolS *symbol;
7495 +  offsetT offset;
7496 +  fixS *fixP;
7497 +  bfd_vma value;
7498 +  int pcrel = 0, align = 0;
7499 +  char *p;
7500 +
7501 +  symbol = fragP->fr_symbol;
7502 +  offset = fragP->fr_offset;
7503 +  r_type = BFD_RELOC_NONE;
7504 +  p = fragP->fr_opcode;
7505 +
7506 +  pr_debug("%s:%d: call_convert_frag, subtype: %d, fix: %d, var: %d\n",
7507 +          fragP->fr_file, fragP->fr_line,
7508 +          fragP->fr_subtype, fragP->fr_fix, fragP->fr_var);
7509 +
7510 +  switch (fragP->fr_subtype)
7511 +    {
7512 +    case CALL_SUBTYPE_RCALL1:
7513 +      opc = &avr32_opc_table[AVR32_OPC_RCALL1];
7514 +      /* fall through */
7515 +    case CALL_SUBTYPE_RCALL2:
7516 +      if (!opc)
7517 +       opc = &avr32_opc_table[AVR32_OPC_RCALL2];
7518 +      ifield = opc->fields[0];
7519 +      r_type = opc->reloc_type;
7520 +      pcrel = 1;
7521 +      align = 1;
7522 +      break;
7523 +    case CALL_SUBTYPE_MCALL_CP:
7524 +      opc = &avr32_opc_table[AVR32_OPC_MCALL];
7525 +      opc->fields[0]->insert(opc->fields[0], p, AVR32_REG_PC);
7526 +      ifield = opc->fields[1];
7527 +      r_type = BFD_RELOC_AVR32_CPCALL;
7528 +      symbol = fragP->tc_frag_data.pool->symbol;
7529 +      offset = fragP->tc_frag_data.pool->literals[fragP->tc_frag_data.pool_entry].offset;
7530 +      assert(fragP->tc_frag_data.pool->literals[fragP->tc_frag_data.pool_entry].refcount > 0);
7531 +      pcrel = 1;
7532 +      align = 2;
7533 +      break;
7534 +    case CALL_SUBTYPE_MCALL_GOT:
7535 +      opc = &avr32_opc_table[AVR32_OPC_MCALL];
7536 +      opc->fields[0]->insert(opc->fields[0], p, 6);
7537 +      ifield = opc->fields[1];
7538 +      r_type = BFD_RELOC_AVR32_GOT18SW;
7539 +      break;
7540 +    case CALL_SUBTYPE_MCALL_LARGE:
7541 +      assert(fragP->fr_var == 10);
7542 +      /* ld.w lr, r6[lr << 2] */
7543 +      opc = &avr32_opc_table[AVR32_OPC_LD_W5];
7544 +      bfd_putb32(opc->value, p + 4);
7545 +      opc->fields[0]->insert(opc->fields[0], p + 4, AVR32_REG_LR);
7546 +      opc->fields[1]->insert(opc->fields[1], p + 4, 6);
7547 +      opc->fields[2]->insert(opc->fields[2], p + 4, AVR32_REG_LR);
7548 +      opc->fields[3]->insert(opc->fields[3], p + 4, 2);
7549 +
7550 +      /* icall lr */
7551 +      opc = &avr32_opc_table[AVR32_OPC_ICALL];
7552 +      bfd_putb16(opc->value >> 16, p + 8);
7553 +      opc->fields[0]->insert(opc->fields[0], p + 8, AVR32_REG_LR);
7554 +
7555 +      /* mov lr, (got_offset / 4) */
7556 +      opc = &avr32_opc_table[AVR32_OPC_MOV2];
7557 +      opc->fields[0]->insert(opc->fields[0], p, AVR32_REG_LR);
7558 +      ifield = opc->fields[1];
7559 +      r_type = BFD_RELOC_AVR32_GOTCALL;
7560 +      break;
7561 +    default:
7562 +      BAD_CASE(fragP->fr_subtype);
7563 +    }
7564 +
7565 +  /* Insert the opcode and clear the variable ifield */
7566 +  value = bfd_getb32(p);
7567 +  value &= ~(opc->mask | ifield->mask);
7568 +  value |= opc->value;
7569 +  bfd_putb32(value, p);
7570 +
7571 +  fragP->fr_fix += fragP->fr_var - CALL_INITIAL_SIZE;
7572 +
7573 +  if (fragP->fr_next
7574 +      && ((offsetT)(fragP->fr_next->fr_address - fragP->fr_address)
7575 +         != fragP->fr_fix))
7576 +    {
7577 +      fprintf(stderr, "%s:%d: fr_fix %lu is wrong! fr_var=%lu, r_type=%s\n",
7578 +             fragP->fr_file, fragP->fr_line,
7579 +             fragP->fr_fix, fragP->fr_var, bfd_get_reloc_code_name(r_type));
7580 +      fprintf(stderr, "fr_fix should be %ld. next frag is %s:%d\n",
7581 +             (offsetT)(fragP->fr_next->fr_address - fragP->fr_address),
7582 +             fragP->fr_next->fr_file, fragP->fr_next->fr_line);
7583 +    }
7584 +
7585 +  fixP = fix_new(fragP, fragP->fr_fix - fragP->fr_var, fragP->fr_var,
7586 +                symbol, offset, pcrel, r_type);
7587 +
7588 +  /* Revert fix_new brain damage. "dot_value" is the value of PC at
7589 +     the point of the fixup, relative to the frag address.  fix_new()
7590 +     and friends think they are only being called during the assembly
7591 +     pass, not during relaxation or similar, so fx_dot_value, fx_file
7592 +     and fx_line are all initialized to the wrong value.  But we don't
7593 +     know the size of the fixup until now, so we really can't live up
7594 +     to the assumptions these functions make about the target.  What
7595 +     do these functions think the "where" and "frag" argument mean
7596 +     anyway?  */
7597 +  fixP->fx_dot_value = fragP->fr_fix - opc->size;
7598 +  fixP->fx_file = fragP->fr_file;
7599 +  fixP->fx_line = fragP->fr_line;
7600 +
7601 +  fixP->tc_fix_data.ifield = ifield;
7602 +  fixP->tc_fix_data.align = align;
7603 +  /* these are only used if the fixup can actually be resolved */
7604 +  fixP->tc_fix_data.min = -2097152;
7605 +  fixP->tc_fix_data.max = 2097150;
7606 +}
7607 +
7608 +static void
7609 +avr32_cpool_convert_frag(bfd *abfd ATTRIBUTE_UNUSED,
7610 +                        segT segment ATTRIBUTE_UNUSED,
7611 +                        fragS *fragP)
7612 +{
7613 +  struct cpool *pool;
7614 +  addressT address;
7615 +  unsigned int entry;
7616 +  char *p;
7617 +  char sym_name[20];
7618 +
7619 +  /* Did we get rid of the frag altogether? */
7620 +  if (!fragP->fr_var)
7621 +    return;
7622 +
7623 +  pool = fragP->tc_frag_data.pool;
7624 +  address = fragP->fr_address + fragP->fr_fix;
7625 +  p = fragP->fr_literal + fragP->fr_fix;
7626 +
7627 +  sprintf(sym_name, "$$cp_\002%x", pool->id);
7628 +  symbol_locate(pool->symbol, sym_name, pool->section, fragP->fr_fix, fragP);
7629 +  symbol_table_insert(pool->symbol);
7630 +
7631 +  for (entry = 0; entry < pool->next_free_entry; entry++)
7632 +    {
7633 +      if (pool->literals[entry].refcount > 0)
7634 +       {
7635 +         fix_new_exp(fragP, fragP->fr_fix, 4, &pool->literals[entry].exp,
7636 +                     FALSE, BFD_RELOC_AVR32_32_CPENT);
7637 +         fragP->fr_fix += 4;
7638 +       }
7639 +    }
7640 +}
7641 +
7642 +static struct avr32_relaxer avr32_default_relaxer = {
7643 +  .estimate_size       = avr32_default_estimate_size_before_relax,
7644 +  .relax_frag          = avr32_default_relax_frag,
7645 +  .convert_frag                = avr32_default_convert_frag,
7646 +};
7647 +static struct avr32_relaxer avr32_lda_relaxer = {
7648 +  .estimate_size       = avr32_lda_estimate_size_before_relax,
7649 +  .relax_frag          = avr32_lda_relax_frag,
7650 +  .convert_frag                = avr32_lda_convert_frag,
7651 +};
7652 +static struct avr32_relaxer avr32_call_relaxer = {
7653 +  .estimate_size       = avr32_call_estimate_size_before_relax,
7654 +  .relax_frag          = avr32_call_relax_frag,
7655 +  .convert_frag                = avr32_call_convert_frag,
7656 +};
7657 +static struct avr32_relaxer avr32_cpool_relaxer = {
7658 +  .estimate_size       = avr32_cpool_estimate_size_before_relax,
7659 +  .relax_frag          = avr32_cpool_relax_frag,
7660 +  .convert_frag                = avr32_cpool_convert_frag,
7661 +};
7662 +
7663 +static void s_cpool(int arg ATTRIBUTE_UNUSED)
7664 +{
7665 +  struct cpool *pool;
7666 +  unsigned int max_size;
7667 +  char *buf;
7668 +
7669 +  pool = find_cpool(now_seg, now_subseg);
7670 +  if (!pool || !pool->symbol || pool->next_free_entry == 0)
7671 +    return;
7672 +
7673 +  /* Make sure the constant pool is properly aligned */
7674 +  frag_align_code(2, 0);
7675 +  if (bfd_get_section_alignment(stdoutput, pool->section) < 2)
7676 +    bfd_set_section_alignment(stdoutput, pool->section, 2);
7677 +
7678 +  /* Assume none of the entries are discarded, and that we need the
7679 +     maximum amount of alignment.  But we're not going to allocate
7680 +     anything up front. */
7681 +  max_size = pool->next_free_entry * 4 + 2;
7682 +  frag_grow(max_size);
7683 +  buf = frag_more(0);
7684 +
7685 +  frag_now->tc_frag_data.relaxer = &avr32_cpool_relaxer;
7686 +  frag_now->tc_frag_data.pool = pool;
7687 +
7688 +  symbol_set_frag(pool->symbol, frag_now);
7689 +
7690 +  /* Assume zero initial size, allowing other relaxers to be
7691 +     optimistic about things.  */
7692 +  frag_var(rs_machine_dependent, max_size, 0,
7693 +          0, pool->symbol, 0, NULL);
7694 +
7695 +  /* Mark the pool as empty.  */
7696 +  pool->used = 1;
7697 +}
7698 +
7699 +/* The location from which a PC relative jump should be calculated,
7700 +   given a PC relative reloc.  */
7701 +
7702 +long
7703 +md_pcrel_from_section (fixS *fixP, segT sec)
7704 +{
7705 +  pr_debug("pcrel_from_section, fx_offset = %d\n", fixP->fx_offset);
7706 +
7707 +  if (fixP->fx_addsy != NULL
7708 +      && (! S_IS_DEFINED (fixP->fx_addsy)
7709 +          || S_GET_SEGMENT (fixP->fx_addsy) != sec
7710 +         || S_FORCE_RELOC(fixP->fx_addsy, 1)))
7711 +    {
7712 +      pr_debug("Unknown pcrel symbol: %s\n", S_GET_NAME(fixP->fx_addsy));
7713 +
7714 +      /* The symbol is undefined (or is defined but not in this section).
7715 +        Let the linker figure it out.  */
7716 +      return 0;
7717 +    }
7718 +
7719 +  pr_debug("pcrel from %x + %x, symbol: %s (%x)\n",
7720 +          fixP->fx_frag->fr_address, fixP->fx_where,
7721 +          fixP->fx_addsy?S_GET_NAME(fixP->fx_addsy):"(null)",
7722 +          fixP->fx_addsy?S_GET_VALUE(fixP->fx_addsy):0);
7723 +
7724 +  return ((fixP->fx_frag->fr_address + fixP->fx_where)
7725 +         & (~0UL << fixP->tc_fix_data.align));
7726 +}
7727 +
7728 +valueT
7729 +md_section_align (segT segment, valueT size)
7730 +{
7731 +  int align = bfd_get_section_alignment (stdoutput, segment);
7732 +  return ((size + (1 << align) - 1) & (-1 << align));
7733 +}
7734 +
7735 +static int syntax_matches(const struct avr32_syntax *syntax,
7736 +                         char *str)
7737 +{
7738 +  int i;
7739 +
7740 +  pr_debug("syntax %d matches `%s'?\n", syntax->id, str);
7741 +
7742 +  if (syntax->nr_operands < 0)
7743 +    {
7744 +      struct avr32_operand *op;
7745 +      int optype;
7746 +
7747 +      for (i = 0; i < (-syntax->nr_operands - 1); i++)
7748 +       {
7749 +         char *p;
7750 +         char c;
7751 +
7752 +         optype = syntax->operand[i];
7753 +         assert(optype < AVR32_NR_OPERANDS);
7754 +         op = &avr32_operand_table[optype];
7755 +
7756 +         for (p = str; *p; p++)
7757 +           if (*p == ',')
7758 +             break;
7759 +
7760 +         if (p == str)
7761 +           return 0;
7762 +
7763 +         c = *p;
7764 +         *p = 0;
7765 +
7766 +         if (!op->match(str))
7767 +           {
7768 +             *p = c;
7769 +             return 0;
7770 +           }
7771 +
7772 +         str = p;
7773 +         *p = c;
7774 +         if (c)
7775 +           str++;
7776 +       }
7777 +
7778 +      optype = syntax->operand[i];
7779 +      assert(optype < AVR32_NR_OPERANDS);
7780 +      op = &avr32_operand_table[optype];
7781 +
7782 +      if (!op->match(str))
7783 +       return 0;
7784 +      return 1;
7785 +    }
7786 +
7787 +  for (i = 0; i < syntax->nr_operands; i++)
7788 +    {
7789 +      struct avr32_operand *op;
7790 +      int optype = syntax->operand[i];
7791 +      char *p;
7792 +      char c;
7793 +
7794 +      assert(optype < AVR32_NR_OPERANDS);
7795 +      op = &avr32_operand_table[optype];
7796 +
7797 +      for (p = str; *p; p++)
7798 +       if (*p == ',')
7799 +         break;
7800 +
7801 +      if (p == str)
7802 +       return 0;
7803 +
7804 +      c = *p;
7805 +      *p = 0;
7806 +
7807 +      if (!op->match(str))
7808 +       {
7809 +         *p = c;
7810 +         return 0;
7811 +       }
7812 +
7813 +      str = p;
7814 +      *p = c;
7815 +      if (c)
7816 +       str++;
7817 +    }
7818 +
7819 +  if (*str == '\0')
7820 +    return 1;
7821 +
7822 +  if ((*str == 'e' || *str == 'E') && !str[1])
7823 +    return 1;
7824 +
7825 +  return 0;
7826 +}
7827 +
7828 +static int parse_operands(char *str)
7829 +{
7830 +  int i;
7831 +
7832 +  if (current_insn.syntax->nr_operands < 0)
7833 +    {
7834 +      int optype;
7835 +      struct avr32_operand *op;
7836 +
7837 +      for (i = 0; i < (-current_insn.syntax->nr_operands - 1); i++)
7838 +       {
7839 +         char *p;
7840 +         char c;
7841 +
7842 +         optype = current_insn.syntax->operand[i];
7843 +         op = &avr32_operand_table[optype];
7844 +
7845 +         for (p = str; *p; p++)
7846 +           if (*p == ',')
7847 +             break;
7848 +
7849 +         assert(p != str);
7850 +
7851 +         c = *p, *p = 0;
7852 +         op->parse(op, str, i);
7853 +         *p = c;
7854 +
7855 +         str = p;
7856 +         if (c) str++;
7857 +       }
7858 +
7859 +      /* give the rest of the line to the last operand */
7860 +      optype = current_insn.syntax->operand[i];
7861 +      op = &avr32_operand_table[optype];
7862 +      op->parse(op, str, i);
7863 +    }
7864 +  else
7865 +    {
7866 +      for (i = 0; i < current_insn.syntax->nr_operands; i++)
7867 +       {
7868 +         int optype = current_insn.syntax->operand[i];
7869 +         struct avr32_operand *op = &avr32_operand_table[optype];
7870 +         char *p;
7871 +         char c;
7872 +
7873 +         skip_whitespace(str);
7874 +
7875 +         for (p = str; *p; p++)
7876 +           if (*p == ',')
7877 +             break;
7878 +
7879 +         assert(p != str);
7880 +
7881 +         c = *p, *p = 0;
7882 +         op->parse(op, str, i);
7883 +         *p = c;
7884 +
7885 +         str = p;
7886 +         if (c) str++;
7887 +       }
7888 +
7889 +      if (*str == 'E' || *str == 'e')
7890 +       current_insn.force_extended = 1;
7891 +    }
7892 +
7893 +  return 0;
7894 +}
7895 +
7896 +static const char *
7897 +finish_insn(const struct avr32_opcode *opc)
7898 +{
7899 +  expressionS *exp = &current_insn.immediate;
7900 +  unsigned int i;
7901 +  int will_relax = 0;
7902 +  char *buf;
7903 +
7904 +  assert(current_insn.next_slot == opc->nr_fields);
7905 +
7906 +  pr_debug("%s:%d: finish_insn: trying opcode %d\n",
7907 +          frag_now->fr_file, frag_now->fr_line, opc->id);
7908 +
7909 +  /* Go through the relaxation stage for all instructions that can
7910 +     possibly take a symbolic immediate.  The relax code will take
7911 +     care of range checking and alignment.  */
7912 +  if (opc->var_field != -1)
7913 +    {
7914 +      int substate, largest_substate;
7915 +      symbolS *sym;
7916 +      offsetT off;
7917 +
7918 +      will_relax = 1;
7919 +      substate = largest_substate = opc_initial_substate(opc);
7920 +
7921 +      while (relax_more(largest_substate) != AVR32_RS_NONE)
7922 +       largest_substate = relax_more(largest_substate);
7923 +
7924 +      pr_debug("will relax. initial substate: %d (size %d), largest substate: %d (size %d)\n",
7925 +              substate, avr32_rs_size(substate),
7926 +              largest_substate, avr32_rs_size(largest_substate));
7927 +
7928 +      /* make sure we have enough room for the largest possible opcode */
7929 +      frag_grow(avr32_rs_size(largest_substate));
7930 +      buf = frag_more(opc->size);
7931 +
7932 +      dwarf2_emit_insn(opc->size);
7933 +
7934 +      frag_now->tc_frag_data.reloc_info = AVR32_OPINFO_NONE;
7935 +      frag_now->tc_frag_data.pcrel = current_insn.pcrel;
7936 +      frag_now->tc_frag_data.force_extended = current_insn.force_extended;
7937 +      frag_now->tc_frag_data.relaxer = &avr32_default_relaxer;
7938 +
7939 +      if (exp->X_op == O_hi)
7940 +       {
7941 +         frag_now->tc_frag_data.reloc_info = AVR32_OPINFO_HI;
7942 +         exp->X_op = exp->X_md;
7943 +       }
7944 +      else if (exp->X_op == O_lo)
7945 +       {
7946 +         frag_now->tc_frag_data.reloc_info = AVR32_OPINFO_LO;
7947 +         exp->X_op = exp->X_md;
7948 +       }
7949 +      else if (exp->X_op == O_got)
7950 +       {
7951 +         frag_now->tc_frag_data.reloc_info = AVR32_OPINFO_GOT;
7952 +         exp->X_op = O_symbol;
7953 +       }
7954 +
7955 +#if 0
7956 +      if ((opc->reloc_type == BFD_RELOC_AVR32_SUB5)
7957 +         && exp->X_op == O_subtract)
7958 +       {
7959 +         symbolS *tmp;
7960 +         tmp = exp->X_add_symbol;
7961 +         exp->X_add_symbol = exp->X_op_symbol;
7962 +         exp->X_op_symbol = tmp;
7963 +       }
7964 +#endif
7965 +
7966 +      frag_now->tc_frag_data.exp = current_insn.immediate;
7967 +
7968 +      sym = exp->X_add_symbol;
7969 +      off = exp->X_add_number;
7970 +      if (exp->X_op != O_symbol)
7971 +       {
7972 +         sym = make_expr_symbol(exp);
7973 +         off = 0;
7974 +       }
7975 +
7976 +      frag_var(rs_machine_dependent,
7977 +              avr32_rs_size(largest_substate) - opc->size,
7978 +              opc->size,
7979 +              substate, sym, off, buf);
7980 +    }
7981 +  else
7982 +    {
7983 +      assert(avr32_rs_size(opc_initial_substate(opc)) == 0);
7984 +
7985 +      /* Make sure we always have room for another whole word, as the ifield
7986 +        inserters can only write words. */
7987 +      frag_grow(4);
7988 +      buf = frag_more(opc->size);
7989 +      dwarf2_emit_insn(opc->size);
7990 +    }
7991 +
7992 +  assert(!(opc->value & ~opc->mask));
7993 +
7994 +  pr_debug("inserting opcode: 0x%lx\n", opc->value);
7995 +  bfd_putb32(opc->value, buf);
7996 +
7997 +  for (i = 0; i < opc->nr_fields; i++)
7998 +    {
7999 +      const struct avr32_ifield *f = opc->fields[i];
8000 +      const struct avr32_ifield_data *fd = &current_insn.field_value[i];
8001 +
8002 +      pr_debug("inserting field: 0x%lx & 0x%lx\n",
8003 +              fd->value >> fd->align_order, f->mask);
8004 +
8005 +      f->insert(f, buf, fd->value >> fd->align_order);
8006 +    }
8007 +
8008 +  assert(will_relax || !current_insn.immediate.X_add_symbol);
8009 +  return NULL;
8010 +}
8011 +
8012 +static const char *
8013 +finish_alias(const struct avr32_alias *alias)
8014 +{
8015 +  const struct avr32_opcode *opc;
8016 +  struct {
8017 +    unsigned long value;
8018 +    unsigned long align;
8019 +  } mapped_operand[AVR32_MAX_OPERANDS];
8020 +  unsigned int i;
8021 +
8022 +  opc = alias->opc;
8023 +
8024 +  /* Remap the operands from the alias to the real opcode */
8025 +  for (i = 0; i < opc->nr_fields; i++)
8026 +    {
8027 +      if (alias->operand_map[i].is_opindex)
8028 +       {
8029 +         struct avr32_ifield_data *fd;
8030 +         fd = &current_insn.field_value[alias->operand_map[i].value];
8031 +         mapped_operand[i].value = fd->value;
8032 +         mapped_operand[i].align = fd->align_order;
8033 +       }
8034 +      else
8035 +       {
8036 +         mapped_operand[i].value = alias->operand_map[i].value;
8037 +         mapped_operand[i].align = 0;
8038 +       }
8039 +    }
8040 +
8041 +  for (i = 0; i < opc->nr_fields; i++)
8042 +    {
8043 +      current_insn.field_value[i].value = mapped_operand[i].value;
8044 +      if (opc->id == AVR32_OPC_COP)
8045 +       current_insn.field_value[i].align_order = 0;
8046 +      else
8047 +       current_insn.field_value[i].align_order
8048 +         = mapped_operand[i].align;
8049 +    }
8050 +
8051 +  current_insn.next_slot = opc->nr_fields;
8052 +
8053 +  return finish_insn(opc);
8054 +}
8055 +
8056 +static const char *
8057 +finish_lda(const struct avr32_syntax *syntax ATTRIBUTE_UNUSED)
8058 +{
8059 +  expressionS *exp = &current_insn.immediate;
8060 +  relax_substateT initial_subtype;
8061 +  symbolS *sym;
8062 +  offsetT off;
8063 +  int initial_size, max_size;
8064 +  char *buf;
8065 +
8066 +  initial_size = LDA_INITIAL_SIZE;
8067 +
8068 +  if (avr32_pic)
8069 +    {
8070 +      initial_subtype = LDA_SUBTYPE_SUB;
8071 +      if (linkrelax)
8072 +       max_size = 8;
8073 +      else
8074 +       max_size = 4;
8075 +    }
8076 +  else
8077 +    {
8078 +      initial_subtype = LDA_SUBTYPE_MOV1;
8079 +      max_size = 4;
8080 +    }
8081 +
8082 +  frag_grow(max_size);
8083 +  buf = frag_more(initial_size);
8084 +  dwarf2_emit_insn(initial_size);
8085 +
8086 +  if (exp->X_op == O_symbol)
8087 +    {
8088 +      sym = exp->X_add_symbol;
8089 +      off = exp->X_add_number;
8090 +    }
8091 +  else
8092 +    {
8093 +      sym = make_expr_symbol(exp);
8094 +      off = 0;
8095 +    }
8096 +
8097 +  frag_now->tc_frag_data.reloc_info = current_insn.field_value[0].value;
8098 +  frag_now->tc_frag_data.relaxer = &avr32_lda_relaxer;
8099 +
8100 +  if (!avr32_pic)
8101 +    {
8102 +      /* The relaxer will bump the refcount if necessary */
8103 +      frag_now->tc_frag_data.pool
8104 +       = add_to_cpool(exp, &frag_now->tc_frag_data.pool_entry, 0);
8105 +    }
8106 +
8107 +  frag_var(rs_machine_dependent, max_size - initial_size,
8108 +          initial_size, initial_subtype, sym, off, buf);
8109 +
8110 +  return NULL;
8111 +}
8112 +
8113 +static const char *
8114 +finish_call(const struct avr32_syntax *syntax ATTRIBUTE_UNUSED)
8115 +{
8116 +  expressionS *exp = &current_insn.immediate;
8117 +  symbolS *sym;
8118 +  offsetT off;
8119 +  int initial_size, max_size;
8120 +  char *buf;
8121 +
8122 +  initial_size = CALL_INITIAL_SIZE;
8123 +
8124 +  if (avr32_pic)
8125 +    {
8126 +      if (linkrelax)
8127 +       max_size = 10;
8128 +      else
8129 +       max_size = 4;
8130 +    }
8131 +  else
8132 +    max_size = 4;
8133 +
8134 +  frag_grow(max_size);
8135 +  buf = frag_more(initial_size);
8136 +  dwarf2_emit_insn(initial_size);
8137 +
8138 +  frag_now->tc_frag_data.relaxer = &avr32_call_relaxer;
8139 +
8140 +  if (exp->X_op == O_symbol)
8141 +    {
8142 +      sym = exp->X_add_symbol;
8143 +      off = exp->X_add_number;
8144 +    }
8145 +  else
8146 +    {
8147 +      sym = make_expr_symbol(exp);
8148 +      off = 0;
8149 +    }
8150 +
8151 +  if (!avr32_pic)
8152 +    {
8153 +      /* The relaxer will bump the refcount if necessary */
8154 +      frag_now->tc_frag_data.pool
8155 +       = add_to_cpool(exp, &frag_now->tc_frag_data.pool_entry, 0);
8156 +    }
8157 +
8158 +  frag_var(rs_machine_dependent, max_size - initial_size,
8159 +          initial_size, CALL_SUBTYPE_RCALL1, sym, off, buf);
8160 +
8161 +  return NULL;
8162 +}
8163 +
8164 +void
8165 +md_begin (void)
8166 +{
8167 +  unsigned long flags = 0;
8168 +  int i;
8169 +
8170 +  avr32_mnemonic_htab = hash_new();
8171 +
8172 +  if (!avr32_mnemonic_htab)
8173 +    as_fatal(_("virtual memory exhausted"));
8174 +
8175 +  for (i = 0; i < AVR32_NR_MNEMONICS; i++)
8176 +    {
8177 +      hash_insert(avr32_mnemonic_htab, avr32_mnemonic_table[i].name,
8178 +                 (void *)&avr32_mnemonic_table[i]);
8179 +    }
8180 +
8181 +  if (linkrelax)
8182 +    flags |= EF_AVR32_LINKRELAX;
8183 +  if (avr32_pic)
8184 +    flags |= EF_AVR32_PIC;
8185 +
8186 +  bfd_set_private_flags(stdoutput, flags);
8187 +
8188 +#ifdef OPC_CONSISTENCY_CHECK
8189 +  if (sizeof(avr32_operand_table)/sizeof(avr32_operand_table[0])
8190 +      < AVR32_NR_OPERANDS)
8191 +    as_fatal(_("operand table is incomplete"));
8192 +
8193 +  for (i = 0; i < AVR32_NR_OPERANDS; i++)
8194 +    if (avr32_operand_table[i].id != i)
8195 +      as_fatal(_("operand table inconsistency found at index %d\n"), i);
8196 +  pr_debug("%d operands verified\n", AVR32_NR_OPERANDS);
8197 +
8198 +  for (i = 0; i < AVR32_NR_IFIELDS; i++)
8199 +    if (avr32_ifield_table[i].id != i)
8200 +      as_fatal(_("ifield table inconsistency found at index %d\n"), i);
8201 +  pr_debug("%d instruction fields verified\n", AVR32_NR_IFIELDS);
8202 +
8203 +  for (i = 0; i < AVR32_NR_OPCODES; i++)
8204 +    {
8205 +      if (avr32_opc_table[i].id != i)
8206 +       as_fatal(_("opcode table inconsistency found at index %d\n"), i);
8207 +      if ((avr32_opc_table[i].var_field == -1
8208 +          && avr32_relax_table[i].length != 0)
8209 +         || (avr32_opc_table[i].var_field != -1
8210 +             && avr32_relax_table[i].length == 0))
8211 +       as_fatal(_("relax table inconsistency found at index %d\n"), i);
8212 +    }
8213 +  pr_debug("%d opcodes verified\n", AVR32_NR_OPCODES);
8214 +
8215 +  for (i = 0; i < AVR32_NR_SYNTAX; i++)
8216 +    if (avr32_syntax_table[i].id != i)
8217 +      as_fatal(_("syntax table inconsistency found at index %d\n"), i);
8218 +  pr_debug("%d syntax variants verified\n", AVR32_NR_SYNTAX);
8219 +
8220 +  for (i = 0; i < AVR32_NR_ALIAS; i++)
8221 +    if (avr32_alias_table[i].id != i)
8222 +      as_fatal(_("alias table inconsistency found at index %d\n"), i);
8223 +  pr_debug("%d aliases verified\n", AVR32_NR_ALIAS);
8224 +
8225 +  for (i = 0; i < AVR32_NR_MNEMONICS; i++)
8226 +    if (avr32_mnemonic_table[i].id != i)
8227 +      as_fatal(_("mnemonic table inconsistency found at index %d\n"), i);
8228 +  pr_debug("%d mnemonics verified\n", AVR32_NR_MNEMONICS);
8229 +#endif
8230 +}
8231 +
8232 +void
8233 +md_assemble (char *str)
8234 +{
8235 +  struct avr32_mnemonic *mnemonic;
8236 +  char *p, c;
8237 +
8238 +  memset(&current_insn, 0, sizeof(current_insn));
8239 +  current_insn.immediate.X_op = O_constant;
8240 +
8241 +  skip_whitespace(str);
8242 +  for (p = str; *p; p++)
8243 +    if (*p == ' ')
8244 +      break;
8245 +  c = *p;
8246 +  *p = 0;
8247 +
8248 +  mnemonic = hash_find(avr32_mnemonic_htab, str);
8249 +  *p = c;
8250 +  if (c) p++;
8251 +
8252 +  if (mnemonic)
8253 +    {
8254 +      const struct avr32_syntax *syntax;
8255 +
8256 +      for (syntax = mnemonic->syntax; syntax; syntax = syntax->next)
8257 +       {
8258 +         const char *errmsg = NULL;
8259 +
8260 +         if (syntax_matches(syntax, p))
8261 +           {
8262 +             if (!(syntax->isa_flags & avr32_arch->isa_flags))
8263 +               {
8264 +                 as_bad(_("Selected architecture `%s'  does not support `%s'"),
8265 +                        avr32_arch->name, str);
8266 +                 return;
8267 +               }
8268 +
8269 +             current_insn.syntax = syntax;
8270 +             parse_operands(p);
8271 +
8272 +             switch (syntax->type)
8273 +               {
8274 +               case AVR32_PARSER_NORMAL:
8275 +                 errmsg = finish_insn(syntax->u.opc);
8276 +                 break;
8277 +               case AVR32_PARSER_ALIAS:
8278 +                 errmsg = finish_alias(syntax->u.alias);
8279 +                 break;
8280 +               case AVR32_PARSER_LDA:
8281 +                 errmsg = finish_lda(syntax);
8282 +                 break;
8283 +               case AVR32_PARSER_CALL:
8284 +                 errmsg = finish_call(syntax);
8285 +                 break;
8286 +               default:
8287 +                 BAD_CASE(syntax->type);
8288 +                 break;
8289 +               }
8290 +
8291 +             if (errmsg)
8292 +               as_bad("%s in `%s'", errmsg, str);
8293 +
8294 +             return;
8295 +           }
8296 +       }
8297 +
8298 +      as_bad(_("unrecognized form of instruction: `%s'"), str);
8299 +    }
8300 +  else
8301 +    as_bad(_("unrecognized instruction `%s'"), str);
8302 +}
8303 +
8304 +void avr32_cleanup(void)
8305 +{
8306 +  struct cpool *pool;
8307 +
8308 +  /* Emit any constant pools that haven't been explicitly flushed with
8309 +     a .cpool directive. */
8310 +  for (pool = cpool_list; pool; pool = pool->next)
8311 +    {
8312 +      subseg_set(pool->section, pool->sub_section);
8313 +      s_cpool(0);
8314 +    }
8315 +}
8316 +
8317 +/* Handle any PIC-related operands in data allocation pseudo-ops */
8318 +void
8319 +avr32_cons_fix_new (fragS *frag, int off, int size, expressionS *exp)
8320 +{
8321 +  bfd_reloc_code_real_type r_type = BFD_RELOC_UNUSED;
8322 +  int pcrel = 0;
8323 +
8324 +  pr_debug("%s:%u: cons_fix_new, add_sym: %s, op_sym: %s, op: %d, add_num: %d\n",
8325 +          frag->fr_file, frag->fr_line,
8326 +          exp->X_add_symbol?S_GET_NAME(exp->X_add_symbol):"(none)",
8327 +          exp->X_op_symbol?S_GET_NAME(exp->X_op_symbol):"(none)",
8328 +          exp->X_op, exp->X_add_number);
8329 +
8330 +  if (exp->X_op == O_subtract && exp->X_op_symbol)
8331 +    {
8332 +      if (exp->X_op_symbol == GOT_symbol)
8333 +       {
8334 +         if (size != 4)
8335 +           goto bad_size;
8336 +         r_type = BFD_RELOC_AVR32_GOTPC;
8337 +         exp->X_op = O_symbol;
8338 +         exp->X_op_symbol = NULL;
8339 +       }
8340 +    }
8341 +  else if (exp->X_op == O_got)
8342 +    {
8343 +      switch (size)
8344 +       {
8345 +       case 1:
8346 +         r_type = BFD_RELOC_AVR32_GOT8;
8347 +         break;
8348 +       case 2:
8349 +         r_type = BFD_RELOC_AVR32_GOT16;
8350 +         break;
8351 +       case 4:
8352 +         r_type = BFD_RELOC_AVR32_GOT32;
8353 +         break;
8354 +       default:
8355 +         goto bad_size;
8356 +       }
8357 +
8358 +      exp->X_op = O_symbol;
8359 +    }
8360 +
8361 +  if (r_type == BFD_RELOC_UNUSED)
8362 +    switch (size)
8363 +      {
8364 +      case 1:
8365 +       r_type = BFD_RELOC_8;
8366 +       break;
8367 +      case 2:
8368 +       r_type = BFD_RELOC_16;
8369 +       break;
8370 +      case 4:
8371 +       r_type = BFD_RELOC_32;
8372 +       break;
8373 +      default:
8374 +       goto bad_size;
8375 +      }
8376 +  else if (size != 4)
8377 +    {
8378 +    bad_size:
8379 +      as_bad(_("unsupported BFD relocation size %u"), size);
8380 +      r_type = BFD_RELOC_UNUSED;
8381 +    }
8382 +
8383 +  fix_new_exp (frag, off, size, exp, pcrel, r_type);
8384 +}
8385 +
8386 +static void
8387 +avr32_frob_section(bfd *abfd ATTRIBUTE_UNUSED, segT sec,
8388 +                  void *ignore ATTRIBUTE_UNUSED)
8389 +{
8390 +  segment_info_type *seginfo;
8391 +  fixS *fix;
8392 +
8393 +  seginfo = seg_info(sec);
8394 +  if (!seginfo)
8395 +    return;
8396 +
8397 +  for (fix = seginfo->fix_root; fix; fix = fix->fx_next)
8398 +    {
8399 +      if (fix->fx_done)
8400 +       continue;
8401 +
8402 +      if (fix->fx_r_type == BFD_RELOC_AVR32_SUB5
8403 +         && fix->fx_addsy && fix->fx_subsy)
8404 +       {
8405 +         if (S_GET_SEGMENT(fix->fx_addsy) != S_GET_SEGMENT(fix->fx_subsy)
8406 +             || linkrelax)
8407 +           {
8408 +             symbolS *tmp;
8409 +#ifdef DEBUG
8410 +             fprintf(stderr, "Swapping symbols in fixup:\n");
8411 +             print_fixup(fix);
8412 +#endif
8413 +             tmp = fix->fx_addsy;
8414 +             fix->fx_addsy = fix->fx_subsy;
8415 +             fix->fx_subsy = tmp;
8416 +             fix->fx_offset = -fix->fx_offset;
8417 +           }
8418 +       }
8419 +    }
8420 +}
8421 +
8422 +/* We need to look for SUB5 instructions with expressions that will be
8423 +   made PC-relative and switch fx_addsy with fx_subsy.  This has to be
8424 +   done before adjustment or the wrong symbol might be adjusted.
8425 +
8426 +   This applies to fixups that are a result of expressions like -(sym
8427 +   - .) and that will make it all the way to md_apply_fix3().  LDA
8428 +   does the right thing in convert_frag, so we must not convert
8429 +   those. */
8430 +void
8431 +avr32_frob_file(void)
8432 +{
8433 +  /* if (1 || !linkrelax)
8434 +     return; */
8435 +
8436 +  bfd_map_over_sections(stdoutput, avr32_frob_section, NULL);
8437 +}
8438 +
8439 +static bfd_boolean
8440 +convert_to_diff_reloc(fixS *fixP)
8441 +{
8442 +  switch (fixP->fx_r_type)
8443 +    {
8444 +    case BFD_RELOC_32:
8445 +      fixP->fx_r_type = BFD_RELOC_AVR32_DIFF32;
8446 +      break;
8447 +    case BFD_RELOC_16:
8448 +      fixP->fx_r_type = BFD_RELOC_AVR32_DIFF16;
8449 +      break;
8450 +    case BFD_RELOC_8:
8451 +      fixP->fx_r_type = BFD_RELOC_AVR32_DIFF8;
8452 +      break;
8453 +    default:
8454 +      return FALSE;
8455 +    }
8456 +
8457 +  return TRUE;
8458 +}
8459 +
8460 +/* Simplify a fixup.  If possible, the fixup is reduced to a single
8461 +   constant which is written to the output file.  Otherwise, a
8462 +   relocation is generated so that the linker can take care of the
8463 +   rest.
8464 +
8465 +   ELF relocations have certain constraints: They can only take a
8466 +   single symbol and a single addend.  This means that for difference
8467 +   expressions, we _must_ get rid of the fx_subsy symbol somehow.
8468 +
8469 +   The difference between two labels in the same section can be
8470 +   calculated directly unless 'linkrelax' is set, or a relocation is
8471 +   forced.  If so, we must emit a R_AVR32_DIFFxx relocation.  If there
8472 +   are addends involved at this point, we must be especially careful
8473 +   as the relocation must point exactly to the symbol being
8474 +   subtracted.
8475 +
8476 +   When subtracting a symbol defined in the same section as the fixup,
8477 +   we might be able to convert it to a PC-relative expression, unless
8478 +   linkrelax is set. If this is the case, there's no way we can make
8479 +   sure that the difference between the fixup and fx_subsy stays
8480 +   constant.  So for now, we're just going to disallow that.
8481 +   */
8482 +void
8483 +avr32_process_fixup(fixS *fixP, segT this_segment)
8484 +{
8485 +  segT add_symbol_segment = absolute_section;
8486 +  segT sub_symbol_segment = absolute_section;
8487 +  symbolS *fx_addsy, *fx_subsy;
8488 +  offsetT value = 0, fx_offset;
8489 +  bfd_boolean apply = FALSE;
8490 +
8491 +  assert(this_segment != absolute_section);
8492 +
8493 +  if (fixP->fx_r_type >= BFD_RELOC_UNUSED)
8494 +    {
8495 +      as_bad_where(fixP->fx_file, fixP->fx_line,
8496 +                  _("Bad relocation type %d\n"), fixP->fx_r_type);
8497 +      return;
8498 +    }
8499 +
8500 +  /* BFD_RELOC_AVR32_SUB5 fixups have been swapped by avr32_frob_section() */
8501 +  fx_addsy = fixP->fx_addsy;
8502 +  fx_subsy = fixP->fx_subsy;
8503 +  fx_offset = fixP->fx_offset;
8504 +
8505 +  if (fx_addsy)
8506 +    add_symbol_segment = S_GET_SEGMENT(fx_addsy);
8507 +
8508 +  if (fx_subsy)
8509 +    {
8510 +      resolve_symbol_value(fx_subsy);
8511 +      sub_symbol_segment = S_GET_SEGMENT(fx_subsy);
8512 +
8513 +      if (sub_symbol_segment == this_segment
8514 +         && (!linkrelax
8515 +             || S_GET_VALUE(fx_subsy) == (fixP->fx_frag->fr_address
8516 +                                          + fixP->fx_where)))
8517 +       {
8518 +         fixP->fx_pcrel = TRUE;
8519 +         fx_offset += (fixP->fx_frag->fr_address + fixP->fx_where
8520 +                       - S_GET_VALUE(fx_subsy));
8521 +         fx_subsy = NULL;
8522 +       }
8523 +      else if (sub_symbol_segment == absolute_section)
8524 +       {
8525 +         /* The symbol is really a constant.  */
8526 +         fx_offset -= S_GET_VALUE(fx_subsy);
8527 +         fx_subsy = NULL;
8528 +       }
8529 +      else if (SEG_NORMAL(add_symbol_segment)
8530 +              && sub_symbol_segment == add_symbol_segment
8531 +              && (!linkrelax || convert_to_diff_reloc(fixP)))
8532 +       {
8533 +         /* Difference between two labels in the same section.  */
8534 +         if (linkrelax)
8535 +           {
8536 +             /* convert_to_diff() has ensured that the reloc type is
8537 +                either DIFF32, DIFF16 or DIFF8.  */
8538 +             value = (S_GET_VALUE(fx_addsy) + fixP->fx_offset
8539 +                      - S_GET_VALUE(fx_subsy));
8540 +
8541 +             /* Try to convert it to a section symbol if possible  */
8542 +             if (!S_FORCE_RELOC(fx_addsy, 1)
8543 +                 && !(sub_symbol_segment->flags & SEC_THREAD_LOCAL))
8544 +               {
8545 +                 fx_offset = S_GET_VALUE(fx_subsy);
8546 +                 fx_addsy = section_symbol(sub_symbol_segment);
8547 +               }
8548 +             else
8549 +               {
8550 +                 fx_addsy = fx_subsy;
8551 +                 fx_offset = 0;
8552 +               }
8553 +
8554 +             fx_subsy = NULL;
8555 +             apply = TRUE;
8556 +           }
8557 +         else
8558 +           {
8559 +             fx_offset += S_GET_VALUE(fx_addsy);
8560 +             fx_offset -= S_GET_VALUE(fx_subsy);
8561 +             fx_addsy = NULL;
8562 +             fx_subsy = NULL;
8563 +           }
8564 +       }
8565 +      else
8566 +       {
8567 +         as_bad_where(fixP->fx_file, fixP->fx_line,
8568 +                      _("can't resolve `%s' {%s section} - `%s' {%s section}"),
8569 +                      fx_addsy ? S_GET_NAME (fx_addsy) : "0",
8570 +                      segment_name (add_symbol_segment),
8571 +                      S_GET_NAME (fx_subsy),
8572 +                      segment_name (sub_symbol_segment));
8573 +         return;
8574 +       }
8575 +    }
8576 +
8577 +  if (fx_addsy && !TC_FORCE_RELOCATION(fixP))
8578 +    {
8579 +      if (add_symbol_segment == this_segment
8580 +         && fixP->fx_pcrel)
8581 +       {
8582 +         value += S_GET_VALUE(fx_addsy);
8583 +         value -= md_pcrel_from_section(fixP, this_segment);
8584 +         fx_addsy = NULL;
8585 +         fixP->fx_pcrel = FALSE;
8586 +       }
8587 +      else if (add_symbol_segment == absolute_section)
8588 +       {
8589 +         fx_offset += S_GET_VALUE(fixP->fx_addsy);
8590 +         fx_addsy = NULL;
8591 +       }
8592 +    }
8593 +
8594 +  if (!fx_addsy)
8595 +    fixP->fx_done = TRUE;
8596 +
8597 +  if (fixP->fx_pcrel)
8598 +    {
8599 +      if (fx_addsy != NULL
8600 +         && S_IS_DEFINED(fx_addsy)
8601 +         && S_GET_SEGMENT(fx_addsy) != this_segment)
8602 +       value += md_pcrel_from_section(fixP, this_segment);
8603 +
8604 +      switch (fixP->fx_r_type)
8605 +       {
8606 +       case BFD_RELOC_32:
8607 +         fixP->fx_r_type = BFD_RELOC_32_PCREL;
8608 +         break;
8609 +       case BFD_RELOC_16:
8610 +         fixP->fx_r_type = BFD_RELOC_16_PCREL;
8611 +         break;
8612 +       case BFD_RELOC_8:
8613 +         fixP->fx_r_type = BFD_RELOC_8_PCREL;
8614 +         break;
8615 +       case BFD_RELOC_AVR32_SUB5:
8616 +         fixP->fx_r_type = BFD_RELOC_AVR32_16N_PCREL;
8617 +         break;
8618 +       case BFD_RELOC_AVR32_16S:
8619 +         fixP->fx_r_type = BFD_RELOC_AVR32_16B_PCREL;
8620 +         break;
8621 +       case BFD_RELOC_AVR32_14UW:
8622 +         fixP->fx_r_type = BFD_RELOC_AVR32_14UW_PCREL;
8623 +         break;
8624 +       case BFD_RELOC_AVR32_10UW:
8625 +         fixP->fx_r_type = BFD_RELOC_AVR32_10UW_PCREL;
8626 +         break;
8627 +       default:
8628 +         /* Should have been taken care of already */
8629 +         break;
8630 +       }
8631 +    }
8632 +
8633 +  if (fixP->fx_done || apply)
8634 +    {
8635 +      const struct avr32_ifield *ifield;
8636 +      char *buf = fixP->fx_where + fixP->fx_frag->fr_literal;
8637 +
8638 +      if (fixP->fx_done)
8639 +       value += fx_offset;
8640 +
8641 +      /* For hosts with longs bigger than 32-bits make sure that the top
8642 +         bits of a 32-bit negative value read in by the parser are set,
8643 +         so that the correct comparisons are made.  */
8644 +      if (value & 0x80000000)
8645 +        value |= (-1L << 31);
8646 +
8647 +      switch (fixP->fx_r_type)
8648 +       {
8649 +       case BFD_RELOC_32:
8650 +       case BFD_RELOC_16:
8651 +       case BFD_RELOC_8:
8652 +       case BFD_RELOC_AVR32_DIFF32:
8653 +       case BFD_RELOC_AVR32_DIFF16:
8654 +       case BFD_RELOC_AVR32_DIFF8:
8655 +         md_number_to_chars(buf, value, fixP->fx_size);
8656 +         break;
8657 +       case BFD_RELOC_HI16:
8658 +         value >>= 16;
8659 +       case BFD_RELOC_LO16:
8660 +         value &= 0xffff;
8661 +         md_number_to_chars(buf + 2, value, 2);
8662 +         break;
8663 +       case BFD_RELOC_AVR32_16N_PCREL:
8664 +         value = -value;
8665 +         /* fall through */
8666 +       case BFD_RELOC_AVR32_22H_PCREL:
8667 +       case BFD_RELOC_AVR32_18W_PCREL:
8668 +       case BFD_RELOC_AVR32_16B_PCREL:
8669 +       case BFD_RELOC_AVR32_11H_PCREL:
8670 +       case BFD_RELOC_AVR32_9H_PCREL:
8671 +       case BFD_RELOC_AVR32_9UW_PCREL:
8672 +       case BFD_RELOC_AVR32_3U:
8673 +       case BFD_RELOC_AVR32_4UH:
8674 +       case BFD_RELOC_AVR32_6UW:
8675 +       case BFD_RELOC_AVR32_6S:
8676 +       case BFD_RELOC_AVR32_7UW:
8677 +       case BFD_RELOC_AVR32_8S_EXT:
8678 +       case BFD_RELOC_AVR32_8S:
8679 +       case BFD_RELOC_AVR32_10UW:
8680 +       case BFD_RELOC_AVR32_10SW:
8681 +       case BFD_RELOC_AVR32_STHH_W:
8682 +       case BFD_RELOC_AVR32_14UW:
8683 +       case BFD_RELOC_AVR32_16S:
8684 +       case BFD_RELOC_AVR32_16U:
8685 +       case BFD_RELOC_AVR32_21S:
8686 +       case BFD_RELOC_AVR32_SUB5:
8687 +       case BFD_RELOC_AVR32_CPCALL:
8688 +       case BFD_RELOC_AVR32_16_CP:
8689 +       case BFD_RELOC_AVR32_9W_CP:
8690 +       case BFD_RELOC_AVR32_15S:
8691 +         ifield = fixP->tc_fix_data.ifield;
8692 +         pr_debug("insert field: %ld <= %ld <= %ld (align %u)\n",
8693 +                  fixP->tc_fix_data.min, value, fixP->tc_fix_data.max,
8694 +                  fixP->tc_fix_data.align);
8695 +         if (value < fixP->tc_fix_data.min || value > fixP->tc_fix_data.max)
8696 +           as_bad_where(fixP->fx_file, fixP->fx_line,
8697 +                        _("operand out of range (%ld not between %ld and %ld)"),
8698 +                        value, fixP->tc_fix_data.min, fixP->tc_fix_data.max);
8699 +         if (value & ((1 << fixP->tc_fix_data.align) - 1))
8700 +           as_bad_where(fixP->fx_file, fixP->fx_line,
8701 +                        _("misaligned operand (required alignment: %d)"),
8702 +                        1 << fixP->tc_fix_data.align);
8703 +         ifield->insert(ifield, buf, value >> fixP->tc_fix_data.align);
8704 +         break;
8705 +       case BFD_RELOC_AVR32_ALIGN:
8706 +         /* Nothing to do */
8707 +         fixP->fx_done = FALSE;
8708 +         break;
8709 +       default:
8710 +         as_fatal("reloc type %s not handled\n",
8711 +                  bfd_get_reloc_code_name(fixP->fx_r_type));
8712 +       }
8713 +    }
8714 +
8715 +  fixP->fx_addsy = fx_addsy;
8716 +  fixP->fx_subsy = fx_subsy;
8717 +  fixP->fx_offset = fx_offset;
8718 +
8719 +  if (!fixP->fx_done)
8720 +    {
8721 +      if (!fixP->fx_addsy)
8722 +       fixP->fx_addsy = abs_section_sym;
8723 +
8724 +      symbol_mark_used_in_reloc(fixP->fx_addsy);
8725 +      if (fixP->fx_subsy)
8726 +       abort();
8727 +    }
8728 +}
8729 +
8730 +#if 0
8731 +void
8732 +md_apply_fix3 (fixS *fixP, valueT *valP, segT seg)
8733 +{
8734 +  const struct avr32_ifield *ifield;
8735 +  offsetT      value = *valP;
8736 +  char         *buf = fixP->fx_where + fixP->fx_frag->fr_literal;
8737 +  bfd_boolean  apply;
8738 +
8739 +  pr_debug("%s:%u: apply_fix3: r_type=%d value=%lx offset=%lx\n",
8740 +          fixP->fx_file, fixP->fx_line, fixP->fx_r_type, *valP,
8741 +          fixP->fx_offset);
8742 +
8743 +  if (fixP->fx_r_type >= BFD_RELOC_UNUSED)
8744 +    {
8745 +      as_bad_where(fixP->fx_file, fixP->fx_line,
8746 +                  _("Bad relocation type %d\n"), fixP->fx_r_type);
8747 +      return;
8748 +    }
8749 +
8750 +  if (!fixP->fx_addsy && !fixP->fx_subsy)
8751 +    fixP->fx_done = 1;
8752 +
8753 +  if (fixP->fx_pcrel)
8754 +    {
8755 +      if (fixP->fx_addsy != NULL
8756 +         && S_IS_DEFINED(fixP->fx_addsy)
8757 +         && S_GET_SEGMENT(fixP->fx_addsy) != seg)
8758 +       value += md_pcrel_from_section(fixP, seg);
8759 +
8760 +      switch (fixP->fx_r_type)
8761 +       {
8762 +       case BFD_RELOC_32:
8763 +         fixP->fx_r_type = BFD_RELOC_32_PCREL;
8764 +         break;
8765 +       case BFD_RELOC_16:
8766 +       case BFD_RELOC_8:
8767 +         as_bad_where (fixP->fx_file, fixP->fx_line,
8768 +                       _("8- and 16-bit PC-relative relocations not supported"));
8769 +         break;
8770 +       case BFD_RELOC_AVR32_SUB5:
8771 +         fixP->fx_r_type = BFD_RELOC_AVR32_PCREL_SUB5;
8772 +         break;
8773 +       case BFD_RELOC_AVR32_16S:
8774 +         fixP->fx_r_type = BFD_RELOC_AVR32_16_PCREL;
8775 +         break;
8776 +       default:
8777 +         /* Should have been taken care of already */
8778 +         break;
8779 +       }
8780 +    }
8781 +
8782 +  if (fixP->fx_r_type == BFD_RELOC_32
8783 +      && fixP->fx_subsy)
8784 +    {
8785 +      fixP->fx_r_type = BFD_RELOC_AVR32_DIFF32;
8786 +
8787 +      /* Offsets are only allowed if it's a result of adjusting a
8788 +        local symbol into a section-relative offset.
8789 +        tc_fix_adjustable() should prevent any adjustment if there
8790 +        was an offset involved before.  */
8791 +      if (fixP->fx_offset && !symbol_section_p(fixP->fx_addsy))
8792 +       as_bad_where(fixP->fx_file, fixP->fx_line,
8793 +                    _("cannot represent symbol difference with an offset"));
8794 +
8795 +      value = (S_GET_VALUE(fixP->fx_addsy) + fixP->fx_offset
8796 +              - S_GET_VALUE(fixP->fx_subsy));
8797 +
8798 +      /* The difference before any relaxing takes place is written
8799 +        out, and the DIFF32 reloc identifies the address of the first
8800 +        symbol (i.e. the on that's subtracted.)  */
8801 +      *valP = value;
8802 +      fixP->fx_offset -= value;
8803 +      fixP->fx_subsy = NULL;
8804 +
8805 +      md_number_to_chars(buf, value, fixP->fx_size);
8806 +    }
8807 +
8808 +  if (fixP->fx_done)
8809 +    {
8810 +      switch (fixP->fx_r_type)
8811 +       {
8812 +       case BFD_RELOC_8:
8813 +       case BFD_RELOC_16:
8814 +       case BFD_RELOC_32:
8815 +         md_number_to_chars(buf, value, fixP->fx_size);
8816 +         break;
8817 +       case BFD_RELOC_HI16:
8818 +         value >>= 16;
8819 +       case BFD_RELOC_LO16:
8820 +         value &= 0xffff;
8821 +         *valP = value;
8822 +         md_number_to_chars(buf + 2, value, 2);
8823 +         break;
8824 +       case BFD_RELOC_AVR32_PCREL_SUB5:
8825 +         value = -value;
8826 +         /* fall through */
8827 +       case BFD_RELOC_AVR32_9_PCREL:
8828 +       case BFD_RELOC_AVR32_11_PCREL:
8829 +       case BFD_RELOC_AVR32_16_PCREL:
8830 +       case BFD_RELOC_AVR32_18_PCREL:
8831 +       case BFD_RELOC_AVR32_22_PCREL:
8832 +       case BFD_RELOC_AVR32_3U:
8833 +       case BFD_RELOC_AVR32_4UH:
8834 +       case BFD_RELOC_AVR32_6UW:
8835 +       case BFD_RELOC_AVR32_6S:
8836 +       case BFD_RELOC_AVR32_7UW:
8837 +       case BFD_RELOC_AVR32_8S:
8838 +       case BFD_RELOC_AVR32_10UW:
8839 +       case BFD_RELOC_AVR32_10SW:
8840 +       case BFD_RELOC_AVR32_14UW:
8841 +       case BFD_RELOC_AVR32_16S:
8842 +       case BFD_RELOC_AVR32_16U:
8843 +       case BFD_RELOC_AVR32_21S:
8844 +       case BFD_RELOC_AVR32_BRC1:
8845 +       case BFD_RELOC_AVR32_SUB5:
8846 +       case BFD_RELOC_AVR32_CPCALL:
8847 +       case BFD_RELOC_AVR32_16_CP:
8848 +       case BFD_RELOC_AVR32_9_CP:
8849 +       case BFD_RELOC_AVR32_15S:
8850 +         ifield = fixP->tc_fix_data.ifield;
8851 +         pr_debug("insert field: %ld <= %ld <= %ld (align %u)\n",
8852 +                  fixP->tc_fix_data.min, value, fixP->tc_fix_data.max,
8853 +                  fixP->tc_fix_data.align);
8854 +         if (value < fixP->tc_fix_data.min || value > fixP->tc_fix_data.max)
8855 +           as_bad_where(fixP->fx_file, fixP->fx_line,
8856 +                        _("operand out of range (%ld not between %ld and %ld)"),
8857 +                        value, fixP->tc_fix_data.min, fixP->tc_fix_data.max);
8858 +         if (value & ((1 << fixP->tc_fix_data.align) - 1))
8859 +           as_bad_where(fixP->fx_file, fixP->fx_line,
8860 +                        _("misaligned operand (required alignment: %d)"),
8861 +                        1 << fixP->tc_fix_data.align);
8862 +         ifield->insert(ifield, buf, value >> fixP->tc_fix_data.align);
8863 +         break;
8864 +       case BFD_RELOC_AVR32_ALIGN:
8865 +         /* Nothing to do */
8866 +         fixP->fx_done = FALSE;
8867 +         break;
8868 +       default:
8869 +         as_fatal("reloc type %s not handled\n",
8870 +                  bfd_get_reloc_code_name(fixP->fx_r_type));
8871 +       }
8872 +    }
8873 +}
8874 +#endif
8875 +
8876 +arelent *
8877 +tc_gen_reloc (asection *section ATTRIBUTE_UNUSED,
8878 +             fixS *fixp)
8879 +{
8880 +  arelent *reloc;
8881 +  bfd_reloc_code_real_type code;
8882 +
8883 +  reloc = xmalloc (sizeof (arelent));
8884 +
8885 +  reloc->sym_ptr_ptr = xmalloc (sizeof (asymbol *));
8886 +  *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
8887 +  reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
8888 +  reloc->addend = fixp->fx_offset;
8889 +  code = fixp->fx_r_type;
8890 +
8891 +  reloc->howto = bfd_reloc_type_lookup (stdoutput, code);
8892 +
8893 +  if (reloc->howto == NULL)
8894 +    {
8895 +      as_bad_where (fixp->fx_file, fixp->fx_line,
8896 +                   _("cannot represent relocation %s in this object file format"),
8897 +                   bfd_get_reloc_code_name (code));
8898 +      return NULL;
8899 +    }
8900 +
8901 +  return reloc;
8902 +}
8903 +
8904 +bfd_boolean
8905 +avr32_force_reloc(fixS *fixP)
8906 +{
8907 +  if (linkrelax && fixP->fx_addsy
8908 +      && !(S_GET_SEGMENT(fixP->fx_addsy)->flags & SEC_DEBUGGING)
8909 +      && S_GET_SEGMENT(fixP->fx_addsy) != absolute_section)
8910 +    {
8911 +      pr_debug(stderr, "force reloc: addsy=%p, r_type=%d, sec=%s\n",
8912 +              fixP->fx_addsy, fixP->fx_r_type, S_GET_SEGMENT(fixP->fx_addsy)->name);
8913 +      return 1;
8914 +    }
8915 +
8916 +  return generic_force_reloc(fixP);
8917 +}
8918 +
8919 +bfd_boolean
8920 +avr32_fix_adjustable(fixS *fixP)
8921 +{
8922 +  switch (fixP->fx_r_type)
8923 +    {
8924 +      /* GOT relocations can't have addends since BFD treats all
8925 +        references to a given symbol the same. This means that we
8926 +        must avoid section-relative references to local symbols when
8927 +        dealing with these kinds of relocs */
8928 +    case BFD_RELOC_AVR32_GOT32:
8929 +    case BFD_RELOC_AVR32_GOT16:
8930 +    case BFD_RELOC_AVR32_GOT8:
8931 +    case BFD_RELOC_AVR32_GOT21S:
8932 +    case BFD_RELOC_AVR32_GOT18SW:
8933 +    case BFD_RELOC_AVR32_GOT16S:
8934 +    case BFD_RELOC_AVR32_LDA_GOT:
8935 +    case BFD_RELOC_AVR32_GOTCALL:
8936 +      pr_debug("fix not adjustable\n");
8937 +      return 0;
8938 +
8939 +    default:
8940 +      break;
8941 +    }
8942 +
8943 +  return 1;
8944 +}
8945 +
8946 +/* When we want the linker to be able to relax the code, we need to
8947 +   output a reloc for every .align directive requesting an alignment
8948 +   to a four byte boundary or larger.  If we don't do this, the linker
8949 +   can't guarantee that the alignment is actually maintained in the
8950 +   linker output.
8951 +
8952 +   TODO: Might as well insert proper NOPs while we're at it... */
8953 +void
8954 +avr32_handle_align(fragS *frag)
8955 +{
8956 +  if (linkrelax
8957 +      && frag->fr_type == rs_align_code
8958 +      && frag->fr_address + frag->fr_fix > 0
8959 +      && frag->fr_offset > 0)
8960 +    {
8961 +      /* The alignment order (fr_offset) is stored in the addend. */
8962 +      fix_new(frag, frag->fr_fix, 2, &abs_symbol, frag->fr_offset,
8963 +             FALSE, BFD_RELOC_AVR32_ALIGN);
8964 +    }
8965 +}
8966 +
8967 +/* Relax_align. Advance location counter to next address that has 'alignment'
8968 +   lowest order bits all 0s, return size of adjustment made.  */
8969 +relax_addressT
8970 +avr32_relax_align(segT segment ATTRIBUTE_UNUSED,
8971 +                 fragS *fragP,
8972 +                 relax_addressT address)
8973 +{
8974 +  relax_addressT mask;
8975 +  relax_addressT new_address;
8976 +  int alignment;
8977 +
8978 +  alignment = fragP->fr_offset;
8979 +  mask = ~((~0) << alignment);
8980 +  new_address = (address + mask) & (~mask);
8981 +
8982 +  return new_address - address;
8983 +}
8984 +
8985 +/* Turn a string in input_line_pointer into a floating point constant
8986 +   of type type, and store the appropriate bytes in *litP.  The number
8987 +   of LITTLENUMS emitted is stored in *sizeP .  An error message is
8988 +   returned, or NULL on OK. */
8989 +
8990 +/* Equal to MAX_PRECISION in atof-ieee.c */
8991 +#define MAX_LITTLENUMS 6
8992 +
8993 +char *
8994 +md_atof (type, litP, sizeP)
8995 +char   type;
8996 +char * litP;
8997 +int *  sizeP;
8998 +{
8999 +  int              i;
9000 +  int              prec;
9001 +  LITTLENUM_TYPE   words [MAX_LITTLENUMS];
9002 +  char *           t;
9003 +
9004 +  switch (type)
9005 +  {
9006 +    case 'f':
9007 +    case 'F':
9008 +    case 's':
9009 +    case 'S':
9010 +      prec = 2;
9011 +      break;
9012 +
9013 +    case 'd':
9014 +    case 'D':
9015 +    case 'r':
9016 +    case 'R':
9017 +      prec = 4;
9018 +      break;
9019 +
9020 +      /* FIXME: Some targets allow other format chars for bigger sizes here.  */
9021 +
9022 +    default:
9023 +      * sizeP = 0;
9024 +      return _("Bad call to md_atof()");
9025 +  }
9026 +
9027 +  t = atof_ieee (input_line_pointer, type, words);
9028 +  if (t)
9029 +    input_line_pointer = t;
9030 +  * sizeP = prec * sizeof (LITTLENUM_TYPE);
9031 +
9032 +  for (i = 0; i < prec; i++)
9033 +  {
9034 +    md_number_to_chars (litP, (valueT) words[i],
9035 +                        sizeof (LITTLENUM_TYPE));
9036 +    litP += sizeof (LITTLENUM_TYPE);
9037 +  }
9038 +
9039 +  return 0;
9040 +}
9041 +
9042 +static char *avr32_end_of_match(char *cont, char *what)
9043 +{
9044 +  int len = strlen (what);
9045 +
9046 +  if (! is_part_of_name (cont[len])
9047 +      && strncasecmp (cont, what, len) == 0)
9048 +    return cont + len;
9049 +
9050 +  return NULL;
9051 +}
9052 +
9053 +int
9054 +avr32_parse_name (char const *name, expressionS *exp, char *nextchar)
9055 +{
9056 +  char *next = input_line_pointer;
9057 +  char *next_end;
9058 +
9059 +  pr_debug("parse_name: %s, nextchar=%c (%02x)\n", name, *nextchar, *nextchar);
9060 +
9061 +  if (*nextchar == '(')
9062 +    {
9063 +      if (strcasecmp(name, "hi") == 0)
9064 +       {
9065 +         *next = *nextchar;
9066 +
9067 +         expression(exp);
9068 +
9069 +         if (exp->X_op == O_constant)
9070 +           {
9071 +             pr_debug("  -> constant hi(0x%08lx) -> 0x%04lx\n",
9072 +                      exp->X_add_number, exp->X_add_number >> 16);
9073 +             exp->X_add_number = (exp->X_add_number >> 16) & 0xffff;
9074 +           }
9075 +         else
9076 +           {
9077 +             exp->X_md = exp->X_op;
9078 +             exp->X_op = O_hi;
9079 +           }
9080 +
9081 +         return 1;
9082 +       }
9083 +      else if (strcasecmp(name, "lo") == 0)
9084 +       {
9085 +         *next = *nextchar;
9086 +
9087 +         expression(exp);
9088 +
9089 +         if (exp->X_op == O_constant)
9090 +           exp->X_add_number &= 0xffff;
9091 +         else
9092 +           {
9093 +             exp->X_md = exp->X_op;
9094 +             exp->X_op = O_lo;
9095 +           }
9096 +
9097 +         return 1;
9098 +       }
9099 +    }
9100 +  else if (*nextchar == '@')
9101 +    {
9102 +      exp->X_md = exp->X_op;
9103 +
9104 +      if ((next_end = avr32_end_of_match (next + 1, "got")))
9105 +       exp->X_op = O_got;
9106 +      else if ((next_end = avr32_end_of_match (next + 1, "tlsgd")))
9107 +       exp->X_op = O_tlsgd;
9108 +      /* Add more as needed */
9109 +      else
9110 +       {
9111 +         char c;
9112 +         input_line_pointer++;
9113 +         c = get_symbol_end();
9114 +         as_bad (_("unknown relocation override `%s'"), next + 1);
9115 +         *input_line_pointer = c;
9116 +         input_line_pointer = next;
9117 +         return 0;
9118 +       }
9119 +
9120 +      exp->X_op_symbol = NULL;
9121 +      exp->X_add_symbol = symbol_find_or_make (name);
9122 +      exp->X_add_number = 0;
9123 +
9124 +      *input_line_pointer = *nextchar;
9125 +      input_line_pointer = next_end;
9126 +      *nextchar = *input_line_pointer;
9127 +      *input_line_pointer = '\0';
9128 +      return 1;
9129 +    }
9130 +  else if (strcmp (name, "_GLOBAL_OFFSET_TABLE_") == 0)
9131 +    {
9132 +      if (!GOT_symbol)
9133 +       GOT_symbol = symbol_find_or_make(name);
9134 +
9135 +      exp->X_add_symbol = GOT_symbol;
9136 +      exp->X_op = O_symbol;
9137 +      exp->X_add_number = 0;
9138 +      return 1;
9139 +    }
9140 +
9141 +  return 0;
9142 +}
9143 +
9144 +static void
9145 +s_rseg (int value ATTRIBUTE_UNUSED)
9146 +{
9147 +  /* Syntax: RSEG segment_name [:type] [NOROOT|ROOT] [(align)]
9148 +   * Defaults:
9149 +   *  - type: undocumented ("typically CODE or DATA")
9150 +   *  - ROOT
9151 +   *  - align: 1 for code, 0 for others
9152 +   *
9153 +   * TODO: NOROOT is ignored. If gas supports discardable segments, it should
9154 +   * be implemented.
9155 +   */
9156 +  char *name, *end;
9157 +  int length, type, attr;
9158 +  int align = 0;
9159 +
9160 +  SKIP_WHITESPACE();
9161 +
9162 +  end = input_line_pointer;
9163 +  while (0 == strchr ("\n\t;:( ", *end))
9164 +    end++;
9165 +  if (end == input_line_pointer)
9166 +    {
9167 +      as_warn (_("missing name"));
9168 +      ignore_rest_of_line();
9169 +      return;
9170 +    }
9171 +
9172 +  name = xmalloc (end - input_line_pointer + 1);
9173 +  memcpy (name, input_line_pointer, end - input_line_pointer);
9174 +  name[end - input_line_pointer] = '\0';
9175 +  input_line_pointer = end;
9176 +
9177 +  SKIP_WHITESPACE();
9178 +
9179 +  type = SHT_NULL;
9180 +  attr = 0;
9181 +
9182 +  if (*input_line_pointer == ':')
9183 +    {
9184 +      /* Skip the colon */
9185 +      ++input_line_pointer;
9186 +      SKIP_WHITESPACE();
9187 +
9188 +      /* Possible options at this point:
9189 +       *   - flag (ROOT or NOROOT)
9190 +       *   - a segment type
9191 +       */
9192 +      end = input_line_pointer;
9193 +      while (0 == strchr ("\n\t;:( ", *end))
9194 +       end++;
9195 +      length = end - input_line_pointer;
9196 +      if (((length == 4) && (0 == strncasecmp( input_line_pointer, "ROOT", 4))) ||
9197 +         ((length == 6) && (0 == strncasecmp( input_line_pointer, "NOROOT", 6))))
9198 +       {
9199 +         /* Ignore ROOT/NOROOT */
9200 +         input_line_pointer = end;
9201 +       }
9202 +      else
9203 +       {
9204 +         /* Must be a segment type */
9205 +         switch (*input_line_pointer)
9206 +           {
9207 +           case 'C':
9208 +           case 'c':
9209 +             if ((length == 4) &&
9210 +                 (0 == strncasecmp (input_line_pointer, "CODE", 4)))
9211 +               {
9212 +                 attr |= SHF_ALLOC | SHF_EXECINSTR;
9213 +                 type = SHT_PROGBITS;
9214 +                 align = 1;
9215 +                 break;
9216 +               }
9217 +             if ((length == 5) &&
9218 +                 (0 == strncasecmp (input_line_pointer, "CONST", 5)))
9219 +               {
9220 +                 attr |= SHF_ALLOC;
9221 +                 type = SHT_PROGBITS;
9222 +                 break;
9223 +               }
9224 +             goto de_fault;
9225 +
9226 +           case 'D':
9227 +           case 'd':
9228 +             if ((length == 4) &&
9229 +                 (0 == strncasecmp (input_line_pointer, "DATA", 4)))
9230 +               {
9231 +                 attr |= SHF_ALLOC | SHF_WRITE;
9232 +                 type = SHT_PROGBITS;
9233 +                 break;
9234 +               }
9235 +             goto de_fault;
9236 +
9237 +             /* TODO: Add FAR*, HUGE*, IDATA and NEAR* if necessary */
9238 +
9239 +           case 'U':
9240 +           case 'u':
9241 +             if ((length == 7) &&
9242 +                 (0 == strncasecmp (input_line_pointer, "UNTYPED", 7)))
9243 +               break;
9244 +             goto de_fault;
9245 +
9246 +             /* TODO: Add XDATA and ZPAGE if necessary */
9247 +
9248 +           de_fault:
9249 +           default:
9250 +             as_warn (_("unrecognized segment type"));
9251 +           }
9252 +
9253 +         input_line_pointer = end;
9254 +         SKIP_WHITESPACE();
9255 +
9256 +         if (*input_line_pointer == ':')
9257 +           {
9258 +             /*  ROOT/NOROOT */
9259 +             ++input_line_pointer;
9260 +             SKIP_WHITESPACE();
9261 +
9262 +             end = input_line_pointer;
9263 +             while (0 == strchr ("\n\t;:( ", *end))
9264 +               end++;
9265 +             length = end - input_line_pointer;
9266 +             if (! ((length == 4) &&
9267 +                    (0 == strncasecmp( input_line_pointer, "ROOT", 4))) &&
9268 +                 ! ((length == 6) &&
9269 +                    (0 == strncasecmp( input_line_pointer, "NOROOT", 6))))
9270 +               {
9271 +                 as_warn (_("unrecognized segment flag"));
9272 +               }
9273 +
9274 +             input_line_pointer = end;
9275 +             SKIP_WHITESPACE();
9276 +           }
9277 +       }
9278 +    }
9279 +
9280 +  if (*input_line_pointer == '(')
9281 +    {
9282 +      align = get_absolute_expression ();
9283 +    }
9284 +
9285 +  demand_empty_rest_of_line();
9286 +
9287 +  obj_elf_change_section (name, type, attr, 0, NULL, 0, 0);
9288 +#ifdef AVR32_DEBUG
9289 +  fprintf( stderr, "RSEG: Changed section to %s, type: 0x%x, attr: 0x%x\n",
9290 +      name, type, attr );
9291 +  fprintf( stderr, "RSEG: Aligning to 2**%d\n", align );
9292 +#endif
9293 +
9294 +  if (align > 15)
9295 +    {
9296 +      align = 15;
9297 +      as_warn (_("alignment too large: %u assumed"), align);
9298 +    }
9299 +
9300 +  /* Hope not, that is */
9301 +  assert (now_seg != absolute_section);
9302 +
9303 +  /* Only make a frag if we HAVE to... */
9304 +  if (align != 0 && !need_pass_2)
9305 +    {
9306 +      if (subseg_text_p (now_seg))
9307 +       frag_align_code (align, 0);
9308 +      else
9309 +       frag_align (align, 0, 0);
9310 +    }
9311 +
9312 +  record_alignment (now_seg, align - OCTETS_PER_BYTE_POWER);
9313 +}
9314 +
9315 +/* vim: syntax=c sw=2
9316 + */
9317 --- /dev/null
9318 +++ b/gas/config/tc-avr32.h
9319 @@ -0,0 +1,325 @@
9320 +/* Assembler definitions for AVR32.
9321 +   Copyright 2003,2004,2005,2006,2007,2008,2009 Atmel Corporation.
9322 +
9323 +   Written by Haavard Skinnemoen, Atmel Norway, <hskinnemoen@atmel.com>
9324 +
9325 +   This file is part of GAS, the GNU Assembler.
9326 +
9327 +   GAS is free software; you can redistribute it and/or modify it
9328 +   under the terms of the GNU General Public License as published by
9329 +   the Free Software Foundation; either version 2, or (at your option)
9330 +   any later version.
9331 +
9332 +   GAS is distributed in the hope that it will be useful, but WITHOUT
9333 +   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
9334 +   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
9335 +   License for more details.
9336 +
9337 +   You should have received a copy of the GNU General Public License
9338 +   along with GAS; see the file COPYING.  If not, write to the Free
9339 +   Software Foundation, 59 Temple Place - Suite 330, Boston, MA
9340 +   02111-1307, USA.  */
9341 +
9342 +#if 0
9343 +#define DEBUG
9344 +#define DEBUG1
9345 +#define DEBUG2
9346 +#define DEBUG3
9347 +#define DEBUG4
9348 +#define DEBUG5
9349 +#endif
9350 +
9351 +/* Are we trying to be compatible with the IAR assembler? (--iar) */
9352 +extern int avr32_iarcompat;
9353 +
9354 +/* By convention, you should define this macro in the `.h' file.  For
9355 +   example, `tc-m68k.h' defines `TC_M68K'.  You might have to use this
9356 +   if it is necessary to add CPU specific code to the object format
9357 +   file.  */
9358 +#define TC_AVR32
9359 +
9360 +/* This macro is the BFD target name to use when creating the output
9361 +   file.  This will normally depend upon the `OBJ_FMT' macro.  */
9362 +#define TARGET_FORMAT "elf32-avr32"
9363 +
9364 +/* This macro is the BFD architecture to pass to `bfd_set_arch_mach'.  */
9365 +#define TARGET_ARCH bfd_arch_avr32
9366 +
9367 +/* This macro is the BFD machine number to pass to
9368 +   `bfd_set_arch_mach'.  If it is not defined, GAS will use 0.  */
9369 +#define TARGET_MACH 0
9370 +
9371 +/* UNDOCUMENTED: Allow //-style comments */
9372 +#define DOUBLESLASH_LINE_COMMENTS
9373 +
9374 +/* You should define this macro to be non-zero if the target is big
9375 +   endian, and zero if the target is little endian.  */
9376 +#define TARGET_BYTES_BIG_ENDIAN 1
9377 +
9378 +/* FIXME: It seems that GAS only expects a one-byte opcode...
9379 +   #define NOP_OPCODE 0xd703 */
9380 +
9381 +/* If you define this macro, GAS will warn about the use of
9382 +   nonstandard escape sequences in a string.  */
9383 +#undef ONLY_STANDARD_ESCAPES
9384 +
9385 +#define DWARF2_FORMAT(SEC) dwarf2_format_32bit
9386 +
9387 +/* Instructions are either 2 or 4 bytes long */
9388 +/* #define DWARF2_LINE_MIN_INSN_LENGTH 2 */
9389 +
9390 +/* GAS will call this function for any expression that can not be
9391 +   recognized.  When the function is called, `input_line_pointer'
9392 +   will point to the start of the expression.  */
9393 +#define md_operand(x)
9394 +
9395 +#define md_parse_name(name, expr, mode, c) avr32_parse_name(name, expr, c)
9396 +extern int avr32_parse_name(const char *, struct expressionS *, char *);
9397 +
9398 +/* You may define this macro to generate a fixup for a data
9399 +   allocation pseudo-op.  */
9400 +#define TC_CONS_FIX_NEW(FRAG, OFF, LEN, EXP)   \
9401 +  avr32_cons_fix_new(FRAG, OFF, LEN, EXP)
9402 +void avr32_cons_fix_new (fragS *, int, int, expressionS *);
9403 +
9404 +/* `extsym - .' expressions can be emitted using PC-relative relocs */
9405 +#define DIFF_EXPR_OK
9406 +
9407 +/* This is used to construct expressions out of @gotoff, etc. The
9408 +   relocation type is stored in X_md */
9409 +#define O_got          O_md1
9410 +#define O_hi           O_md2
9411 +#define O_lo           O_md3
9412 +#define O_tlsgd                O_md4
9413 +
9414 +/* You may define this macro to parse an expression used in a data
9415 +   allocation pseudo-op such as `.word'.  You can use this to
9416 +   recognize relocation directives that may appear in such directives.  */
9417 +/* #define TC_PARSE_CONS_EXPRESSION(EXPR,N) avr_parse_cons_expression (EXPR,N)
9418 +   void avr_parse_cons_expression (expressionS *exp, int nbytes); */
9419 +
9420 +/* This should just call either `number_to_chars_bigendian' or
9421 +   `number_to_chars_littleendian', whichever is appropriate.  On
9422 +   targets like the MIPS which support options to change the
9423 +   endianness, which function to call is a runtime decision.  On
9424 +   other targets, `md_number_to_chars' can be a simple macro.  */
9425 +#define md_number_to_chars number_to_chars_bigendian
9426 +
9427 +/* `md_short_jump_size'
9428 +   `md_long_jump_size'
9429 +   `md_create_short_jump'
9430 +   `md_create_long_jump'
9431 +   If `WORKING_DOT_WORD' is defined, GAS will not do broken word
9432 +   processing (*note Broken words::.).  Otherwise, you should set
9433 +   `md_short_jump_size' to the size of a short jump (a jump that is
9434 +   just long enough to jump around a long jmp) and
9435 +   `md_long_jump_size' to the size of a long jump (a jump that can go
9436 +   anywhere in the function), You should define
9437 +   `md_create_short_jump' to create a short jump around a long jump,
9438 +   and define `md_create_long_jump' to create a long jump.  */
9439 +#define WORKING_DOT_WORD
9440 +
9441 +/* If you define this macro, it means that `tc_gen_reloc' may return
9442 +   multiple relocation entries for a single fixup.  In this case, the
9443 +   return value of `tc_gen_reloc' is a pointer to a null terminated
9444 +   array.  */
9445 +#undef RELOC_EXPANSION_POSSIBLE
9446 +
9447 +/* If you define this macro, GAS will not require pseudo-ops to start with a .
9448 +   character. */
9449 +#define NO_PSEUDO_DOT (avr32_iarcompat)
9450 +
9451 +/* The IAR assembler uses $ as the location counter. Unfortunately, we
9452 +   can't make this dependent on avr32_iarcompat... */
9453 +#define DOLLAR_DOT
9454 +
9455 +/* Values passed to md_apply_fix3 don't include the symbol value.  */
9456 +#define MD_APPLY_SYM_VALUE(FIX) 0
9457 +
9458 +/* The number of bytes to put into a word in a listing.  This affects
9459 +   the way the bytes are clumped together in the listing.  For
9460 +   example, a value of 2 might print `1234 5678' where a value of 1
9461 +   would print `12 34 56 78'.  The default value is 4.  */
9462 +#define LISTING_WORD_SIZE 4
9463 +
9464 +/* extern const struct relax_type md_relax_table[];
9465 +#define TC_GENERIC_RELAX_TABLE md_relax_table */
9466 +
9467 +/*
9468 +  An `.lcomm' directive with no explicit alignment parameter will use
9469 +  this macro to set P2VAR to the alignment that a request for SIZE
9470 +  bytes will have.  The alignment is expressed as a power of two.  If
9471 +  no alignment should take place, the macro definition should do
9472 +  nothing.  Some targets define a `.bss' directive that is also
9473 +  affected by this macro.  The default definition will set P2VAR to
9474 +  the truncated power of two of sizes up to eight bytes.
9475 +
9476 +  We want doublewords to be word-aligned, so we're going to modify the
9477 +  default definition a tiny bit.
9478 +*/
9479 +#define TC_IMPLICIT_LCOMM_ALIGNMENT(SIZE, P2VAR)       \
9480 +  do                                                   \
9481 +    {                                                  \
9482 +      if ((SIZE) >= 4)                                 \
9483 +       (P2VAR) = 2;                                    \
9484 +      else if ((SIZE) >= 2)                            \
9485 +       (P2VAR) = 1;                                    \
9486 +      else                                             \
9487 +       (P2VAR) = 0;                                    \
9488 +    }                                                  \
9489 +  while (0)
9490 +
9491 +/* When relaxing, we need to generate relocations for alignment
9492 +   directives.  */
9493 +#define HANDLE_ALIGN(frag) avr32_handle_align(frag)
9494 +extern void avr32_handle_align(fragS *);
9495 +
9496 +/* See internals doc for explanation. Oh wait...
9497 +   Now, can you guess where "alignment" comes from? ;-) */
9498 +#define MAX_MEM_FOR_RS_ALIGN_CODE ((1 << alignment) - 1)
9499 +
9500 +/* We need to stop gas from reducing certain expressions (e.g. GOT
9501 +   references) */
9502 +#define tc_fix_adjustable(fix) avr32_fix_adjustable(fix)
9503 +extern bfd_boolean avr32_fix_adjustable(struct fix *);
9504 +
9505 +/* The linker needs to be passed a little more information when relaxing. */
9506 +#define TC_FORCE_RELOCATION(fix) avr32_force_reloc(fix)
9507 +extern bfd_boolean avr32_force_reloc(struct fix *);
9508 +
9509 +/* I'm tired of working around all the madness in fixup_segment().
9510 +   This hook will do basically the same things as the generic code,
9511 +   and then it will "goto" right past it.  */
9512 +#define TC_VALIDATE_FIX(FIX, SEG, SKIP)                \
9513 +  do                                           \
9514 +    {                                          \
9515 +      avr32_process_fixup(FIX, SEG);           \
9516 +      if (!(FIX)->fx_done)                     \
9517 +       ++seg_reloc_count;                      \
9518 +      goto SKIP;                               \
9519 +    }                                          \
9520 +  while (0)
9521 +extern void avr32_process_fixup(struct fix *fixP, segT this_segment);
9522 +
9523 +/* Positive values of TC_FX_SIZE_SLACK allow a target to define
9524 +   fixups that far past the end of a frag.  Having such fixups
9525 +   is of course most most likely a bug in setting fx_size correctly.
9526 +   A negative value disables the fixup check entirely, which is
9527 +   appropriate for something like the Renesas / SuperH SH_COUNT
9528 +   reloc.  */
9529 +/* This target is buggy, and sets fix size too large.  */
9530 +#define TC_FX_SIZE_SLACK(FIX) -1
9531 +
9532 +/* We don't want the gas core to make any assumptions about our way of
9533 +   doing linkrelaxing.  */
9534 +#define TC_LINKRELAX_FIXUP(SEG)                        0
9535 +
9536 +/* ... but we do want it to insert lots of padding. */
9537 +#define LINKER_RELAXING_SHRINKS_ONLY
9538 +
9539 +/* Better do it ourselves, really... */
9540 +#define TC_RELAX_ALIGN(SEG, FRAG, ADDR)        avr32_relax_align(SEG, FRAG, ADDR)
9541 +extern relax_addressT
9542 +avr32_relax_align(segT segment, fragS *fragP, relax_addressT address);
9543 +
9544 +/* Use line number format that is amenable to linker relaxation.  */
9545 +#define DWARF2_USE_FIXED_ADVANCE_PC (linkrelax != 0)
9546 +
9547 +/* This is called by write_object_file() just before symbols are
9548 +   attempted converted into section symbols.  */
9549 +#define tc_frob_file_before_adjust()   avr32_frob_file()
9550 +extern void avr32_frob_file(void);
9551 +
9552 +/* If you define this macro, GAS will call it at the end of each input
9553 +   file.  */
9554 +#define md_cleanup() avr32_cleanup()
9555 +extern void avr32_cleanup(void);
9556 +
9557 +/* There's an AVR32-specific hack in operand() which creates O_md
9558 +   expressions when encountering HWRD or LWRD. We need to generate
9559 +   proper relocs for them */
9560 +/* #define md_cgen_record_fixup_exp avr32_cgen_record_fixup_exp */
9561 +
9562 +/* I needed to add an extra hook in gas_cgen_finish_insn() for
9563 +   conversion of O_md* operands because md_cgen_record_fixup_exp()
9564 +   isn't called for relaxable insns */
9565 +/* #define md_cgen_convert_expr(exp, opinfo) avr32_cgen_convert_expr(exp, opinfo)
9566 +   int avr32_cgen_convert_expr(expressionS *, int); */
9567 +
9568 +/* #define tc_gen_reloc gas_cgen_tc_gen_reloc */
9569 +
9570 +/* If you define this macro, it should return the position from which
9571 +   the PC relative adjustment for a PC relative fixup should be
9572 +   made. On many processors, the base of a PC relative instruction is
9573 +   the next instruction, so this macro would return the length of an
9574 +   instruction, plus the address of the PC relative fixup. The latter
9575 +   can be calculated as fixp->fx_where + fixp->fx_frag->fr_address. */
9576 +extern long md_pcrel_from_section (struct fix *, segT);
9577 +#define MD_PCREL_FROM_SECTION(FIX, SEC) md_pcrel_from_section (FIX, SEC)
9578 +
9579 +#define LOCAL_LABEL(name) (name[0] == '.' && (name[1] == 'L'))
9580 +#define LOCAL_LABELS_FB                1
9581 +
9582 +struct avr32_relaxer
9583 +{
9584 +  int (*estimate_size)(fragS *, segT);
9585 +  long (*relax_frag)(segT, fragS *, long);
9586 +  void (*convert_frag)(bfd *, segT, fragS *);
9587 +};
9588 +
9589 +/* AVR32 has quite complex instruction coding, which means we need
9590 + * lots of information in order to do the right thing during relaxing
9591 + * (basically, we need to be able to reconstruct a whole new opcode if
9592 + * necessary) */
9593 +#define TC_FRAG_TYPE struct avr32_frag_data
9594 +
9595 +struct cpool;
9596 +
9597 +struct avr32_frag_data
9598 +{
9599 +  /* TODO: Maybe add an expression object here so that we can use
9600 +     fix_new_exp() in md_convert_frag?  We may have to decide
9601 +     pcrel-ness in md_estimate_size_before_relax() as well...or we
9602 +     might do it when parsing.  Doing it while parsing may fail
9603 +     because the sub_symbol is undefined then... */
9604 +  int pcrel;
9605 +  int force_extended;
9606 +  int reloc_info;
9607 +  struct avr32_relaxer *relaxer;
9608 +  expressionS exp;
9609 +
9610 +  /* Points to associated constant pool, for use by LDA and CALL in
9611 +     non-pic mode, and when relaxing the .cpool directive */
9612 +  struct cpool *pool;
9613 +  unsigned int pool_entry;
9614 +};
9615 +
9616 +/* We will have to initialize the fields explicitly when needed */
9617 +#define TC_FRAG_INIT(fragP)
9618 +
9619 +#define md_estimate_size_before_relax(fragP, segT)                     \
9620 +  ((fragP)->tc_frag_data.relaxer->estimate_size(fragP, segT))
9621 +#define md_relax_frag(segment, fragP, stretch)                         \
9622 +  ((fragP)->tc_frag_data.relaxer->relax_frag(segment, fragP, stretch))
9623 +#define md_convert_frag(abfd, segment, fragP)                          \
9624 +  ((fragP)->tc_frag_data.relaxer->convert_frag(abfd, segment, fragP))
9625 +
9626 +#define TC_FIX_TYPE struct avr32_fix_data
9627 +
9628 +struct avr32_fix_data
9629 +{
9630 +  const struct avr32_ifield *ifield;
9631 +  unsigned int align;
9632 +  long min;
9633 +  long max;
9634 +};
9635 +
9636 +#define TC_INIT_FIX_DATA(fixP)                 \
9637 +  do                                           \
9638 +    {                                          \
9639 +      (fixP)->tc_fix_data.ifield = NULL;       \
9640 +      (fixP)->tc_fix_data.align = 0;           \
9641 +      (fixP)->tc_fix_data.min = 0;             \
9642 +      (fixP)->tc_fix_data.max = 0;             \
9643 +    }                                          \
9644 +  while (0)
9645 --- a/gas/configure.tgt
9646 +++ b/gas/configure.tgt
9647 @@ -33,6 +33,7 @@ case ${cpu} in
9648    am33_2.0)            cpu_type=mn10300 endian=little ;;
9649    arm*be|arm*b)                cpu_type=arm endian=big ;;
9650    arm*)                        cpu_type=arm endian=little ;;
9651 +  avr32*)              cpu_type=avr32 endian=big ;;
9652    bfin*)               cpu_type=bfin endian=little ;;
9653    c4x*)                        cpu_type=tic4x ;;
9654    cr16*)               cpu_type=cr16 endian=little ;;
9655 @@ -134,6 +135,9 @@ case ${generic_target} in
9656
9657    cr16-*-elf*)                         fmt=elf ;;
9658
9659 +  avr32-*-linux*)                      fmt=elf  em=linux bfd_gas=yes ;;
9660 +  avr32*)                              fmt=elf  bfd_gas=yes ;;
9661 +
9662    cris-*-linux-* | crisv32-*-linux-*)
9663                                         fmt=multi em=linux ;;
9664    cris-*-* | crisv32-*-*)              fmt=multi ;;
9665 --- a/gas/doc/all.texi
9666 +++ b/gas/doc/all.texi
9667 @@ -30,6 +30,7 @@
9668  @set ARC
9669  @set ARM
9670  @set AVR
9671 +@set AVR32
9672  @set BFIN
9673  @set CR16
9674  @set CRIS
9675 --- a/gas/doc/asconfig.texi
9676 +++ b/gas/doc/asconfig.texi
9677 @@ -30,6 +30,7 @@
9678  @set ARC
9679  @set ARM
9680  @set AVR
9681 +@set AVR32
9682  @set BFIN
9683  @set CR16
9684  @set CRIS
9685 --- a/gas/doc/as.texinfo
9686 +++ b/gas/doc/as.texinfo
9687 @@ -6603,6 +6603,9 @@ subject, see the hardware manufacturer's
9688  @ifset AVR
9689  * AVR-Dependent::               AVR Dependent Features
9690  @end ifset
9691 +@ifset AVR32
9692 +* AVR32-Dependent::             AVR32 Dependent Features
9693 +@end ifset
9694  @ifset BFIN
9695  * BFIN-Dependent::             BFIN Dependent Features
9696  @end ifset
9697 @@ -6726,6 +6729,10 @@ subject, see the hardware manufacturer's
9698  @include c-avr.texi
9699  @end ifset
9700
9701 +@ifset AVR32
9702 +@include c-avr32.texi
9703 +@end ifset
9704 +
9705  @ifset BFIN
9706  @include c-bfin.texi
9707  @end ifset
9708 --- /dev/null
9709 +++ b/gas/doc/c-avr32.texi
9710 @@ -0,0 +1,244 @@
9711 +@c Copyright 2005, 2006, 2007, 2008, 2009
9712 +@c Atmel Corporation
9713 +@c This is part of the GAS manual.
9714 +@c For copying conditions, see the file as.texinfo.
9715 +
9716 +@ifset GENERIC
9717 +@page
9718 +@node AVR32-Dependent
9719 +@chapter AVR32 Dependent Features
9720 +@end ifset
9721 +
9722 +@ifclear GENERIC
9723 +@node Machine Dependencies
9724 +@chapter AVR32 Dependent Features
9725 +@end ifclear
9726 +
9727 +@cindex AVR32 support
9728 +@menu
9729 +* AVR32 Options::               Options
9730 +* AVR32 Syntax::                Syntax
9731 +* AVR32 Directives::            Directives
9732 +* AVR32 Opcodes::               Opcodes
9733 +@end menu
9734 +
9735 +@node AVR32 Options
9736 +@section Options
9737 +@cindex AVR32 options
9738 +@cindex options for AVR32
9739 +
9740 +@table @code
9741 +
9742 +@cindex @code{--pic} command line option, AVR32
9743 +@cindex PIC code generation for AVR32
9744 +@item --pic
9745 +This option specifies that the output of the assembler should be marked
9746 +as position-independent code (PIC).  It will also ensure that
9747 +pseudo-instructions that deal with address calculation are output as
9748 +PIC, and that all absolute address references in the code are marked as
9749 +such.
9750 +
9751 +@cindex @code{--linkrelax} command line option, AVR32
9752 +@item --linkrelax
9753 +This option specifies that the output of the assembler should be marked
9754 +as linker-relaxable.  It will also ensure that all PC-relative operands
9755 +that may change during linker relaxation get appropriate relocations.
9756 +
9757 +@end table
9758 +
9759 +
9760 +@node AVR32 Syntax
9761 +@section Syntax
9762 +@menu
9763 +* AVR32-Chars::              Special Characters
9764 +* AVR32-Symrefs::            Symbol references
9765 +@end menu
9766 +
9767 +@node AVR32-Chars
9768 +@subsection Special Characters
9769 +
9770 +@cindex line comment character, AVR32
9771 +@cindex AVR32 line comment character
9772 +The presence of a @samp{//} on a line indicates the start of a comment
9773 +that extends to the end of the current line.  If a @samp{#} appears as
9774 +the first character of a line, the whole line is treated as a comment.
9775 +
9776 +@cindex line separator, AVR32
9777 +@cindex statement separator, AVR32
9778 +@cindex AVR32 line separator
9779 +The @samp{;} character can be used instead of a newline to separate
9780 +statements.
9781 +
9782 +@node AVR32-Symrefs
9783 +@subsection Symbol references
9784 +
9785 +The absolute value of a symbol can be obtained by simply naming the
9786 +symbol.  However, as AVR32 symbols have 32-bit values, most symbols have
9787 +values that are outside the range of any instructions.
9788 +
9789 +Instructions that take a PC-relative offset, e.g. @code{lddpc} or
9790 +@code{rcall}, can also reference a symbol by simply naming the symbol
9791 +(no explicit calculations necessary).  In this case, the assembler or
9792 +linker subtracts the address of the instruction from the symbol's value
9793 +and inserts the result into the instruction.  Note that even though an
9794 +overflow is less likely to happen for a relative reference than for an
9795 +absolute reference, the assembler or linker will generate an error if
9796 +the referenced symbol is too far away from the current location.
9797 +
9798 +Relative references can be used for data as well.  For example:
9799 +
9800 +@smallexample
9801 +        lddpc   r0, 2f
9802 +1:      add     r0, pc
9803 +        ...
9804 +        .align  2
9805 +2:      .int    @var{some_symbol} - 1b
9806 +@end smallexample
9807 +
9808 +Here, r0 will end up with the run-time address of @var{some_symbol} even
9809 +if the program was loaded at a different address than it was linked
9810 +(position-independent code).
9811 +
9812 +@subsubsection Symbol modifiers
9813 +
9814 +@table @code
9815 +
9816 +@item @code{hi(@var{symbol})}
9817 +Evaluates to the value of the symbol shifted right 16 bits.  This will
9818 +work even if @var{symbol} is defined in a different module.
9819 +
9820 +@item @code{lo(@var{symbol})}
9821 +Evaluates to the low 16 bits of the symbol's value.  This will work even
9822 +if @var{symbol} is defined in a different module.
9823 +
9824 +@item @code{@var{symbol}@@got}
9825 +Create a GOT entry for @var{symbol} and return the offset of that entry
9826 +relative to the GOT base.
9827 +
9828 +@end table
9829 +
9830 +
9831 +@node AVR32 Directives
9832 +@section Directives
9833 +@cindex machine directives, AVR32
9834 +@cindex AVR32 directives
9835 +
9836 +@table @code
9837 +
9838 +@cindex @code{.cpool} directive, AVR32
9839 +@item .cpool
9840 +This directive causes the current contents of the constant pool to be
9841 +dumped into the current section at the current location (aligned to a
9842 +word boundary).  @code{GAS} maintains a separate constant pool for each
9843 +section and each sub-section.  The @code{.cpool} directive will only
9844 +affect the constant pool of the current section and sub-section.  At the
9845 +end of assembly, all remaining, non-empty constant pools will
9846 +automatically be dumped.
9847 +
9848 +@end table
9849 +
9850 +
9851 +@node AVR32 Opcodes
9852 +@section Opcodes
9853 +@cindex AVR32 opcodes
9854 +@cindex opcodes for AVR32
9855 +
9856 +@code{@value{AS}} implements all the standard AVR32 opcodes.  It also
9857 +implements several pseudo-opcodes, which are recommended to use wherever
9858 +possible because they give the tool chain better freedom to generate
9859 +optimal code.
9860 +
9861 +@table @code
9862 +
9863 +@cindex @code{LDA.W reg, symbol} pseudo op, AVR32
9864 +@item LDA.W
9865 +@smallexample
9866 +        lda.w   @var{reg}, @var{symbol}
9867 +@end smallexample
9868 +
9869 +This instruction will load the address of @var{symbol} into
9870 +@var{reg}. The instruction will evaluate to one of the following,
9871 +depending on the relative distance to the symbol, the relative distance
9872 +to the constant pool and whether the @code{--pic} option has been
9873 +specified. If the @code{--pic} option has not been specified, the
9874 +alternatives are as follows:
9875 +@smallexample
9876 +        /* @var{symbol} evaluates to a small enough value */
9877 +        mov     @var{reg}, @var{symbol}
9878 +
9879 +        /* (. - @var{symbol}) evaluates to a small enough value */
9880 +        sub     @var{reg}, pc, . - @var{symbol}
9881 +
9882 +        /* Constant pool is close enough */
9883 +        lddpc   @var{reg}, @var{cpent}
9884 +        ...
9885 +@var{cpent}:
9886 +        .long   @var{symbol}
9887 +
9888 +        /* Otherwise (not implemented yet, probably not necessary) */
9889 +        mov     @var{reg}, lo(@var{symbol})
9890 +        orh     @var{reg}, hi(@var{symbol})
9891 +@end smallexample
9892 +
9893 +If the @code{--pic} option has been specified, the alternatives are as
9894 +follows:
9895 +@smallexample
9896 +        /* (. - @var{symbol}) evaluates to a small enough value */
9897 +        sub     @var{reg}, pc, . - @var{symbol}
9898 +
9899 +        /* If @code{--linkrelax} not specified */
9900 +        ld.w    @var{reg}, r6[@var{symbol}@@got]
9901 +
9902 +        /* Otherwise */
9903 +        mov     @var{reg}, @var{symbol}@@got / 4
9904 +        ld.w    @var{reg}, r6[@var{reg} << 2]
9905 +@end smallexample
9906 +
9907 +If @var{symbol} is not defined in the same file and section as the
9908 +@code{LDA.W} instruction, the most pessimistic alternative of the
9909 +above is selected. The linker may convert it back into the most
9910 +optimal alternative when the final value of all symbols is known.
9911 +
9912 +@cindex @code{CALL symbol} pseudo op, AVR32
9913 +@item CALL
9914 +@smallexample
9915 +        call    @var{symbol}
9916 +@end smallexample
9917 +
9918 +This instruction will insert code to call the subroutine identified by
9919 +@var{symbol}. It will evaluate to one of the following, depending on
9920 +the relative distance to the symbol as well as the @code{--linkrelax}
9921 +and @code{--pic} command-line options.
9922 +
9923 +If @var{symbol} is defined in the same section and input file, and the
9924 +distance is small enough, an @code{rcall} instruction is inserted:
9925 +@smallexample
9926 +        rcall   @var{symbol}
9927 +@end smallexample
9928 +
9929 +Otherwise, if the @code{--pic} option has not been specified:
9930 +@smallexample
9931 +        mcall   @var{cpent}
9932 +        ...
9933 +@var{cpent}:
9934 +        .long   @var{symbol}
9935 +@end smallexample
9936 +
9937 +Finally, if nothing else fits and the @code{--pic} option has been
9938 +specified, the assembler will indirect the call through the Global
9939 +Offset Table:
9940 +@smallexample
9941 +        /* If @code{--linkrelax} not specified */
9942 +        mcall   r6[@var{symbol}@@got]
9943 +
9944 +        /* If @code{--linkrelax} specified */
9945 +        mov     lr, @var{symbol}@@got / 4
9946 +        ld.w    lr, r6[lr << 2]
9947 +        icall   lr
9948 +@end smallexample
9949 +
9950 +The linker, after determining the final value of @var{symbol}, may
9951 +convert any of these into more optimal alternatives. This includes
9952 +deleting any superfluous constant pool- and GOT-entries.
9953 +
9954 +@end table
9955 --- a/gas/doc/Makefile.am
9956 +++ b/gas/doc/Makefile.am
9957 @@ -33,6 +33,7 @@ CPU_DOCS = \
9958         c-arc.texi \
9959         c-arm.texi \
9960         c-avr.texi \
9961 +       c-avr32.texi \
9962         c-bfin.texi \
9963         c-cr16.texi \
9964         c-d10v.texi \
9965 --- a/gas/doc/Makefile.in
9966 +++ b/gas/doc/Makefile.in
9967 @@ -240,6 +240,7 @@ CPU_DOCS = \
9968         c-arc.texi \
9969         c-arm.texi \
9970         c-avr.texi \
9971 +       c-avr32.texi \
9972         c-bfin.texi \
9973         c-cr16.texi \
9974         c-d10v.texi \
9975 --- a/gas/Makefile.am
9976 +++ b/gas/Makefile.am
9977 @@ -47,6 +47,7 @@ CPU_TYPES = \
9978         arc \
9979         arm \
9980         avr \
9981 +       avr32 \
9982         bfin \
9983         cr16 \
9984         cris \
9985 @@ -242,6 +243,7 @@ TARGET_CPU_CFILES = \
9986         config/tc-arc.c \
9987         config/tc-arm.c \
9988         config/tc-avr.c \
9989 +       config/tc-avr32.c \
9990         config/tc-bfin.c \
9991         config/tc-cr16.c \
9992         config/tc-cris.c \
9993 @@ -303,6 +305,7 @@ TARGET_CPU_HFILES = \
9994         config/tc-arc.h \
9995         config/tc-arm.h \
9996         config/tc-avr.h \
9997 +       config/tc-avr32.h \
9998         config/tc-bfin.h \
9999         config/tc-cr16.h \
10000         config/tc-cris.h \
10001 @@ -1075,6 +1078,11 @@ DEPTC_avr_elf = $(srcdir)/config/obj-elf
10002    $(INCDIR)/bfdlink.h $(srcdir)/config/tc-avr.h dwarf2dbg.h \
10003    $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
10004    $(INCDIR)/opcode/avr.h
10005 +DEPTC_avr32_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
10006 +  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
10007 +  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-avr32.h \
10008 +  $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
10009 +  $(srcdir)/../opcodes/avr32-opc.h $(srcdir)/../opcodes/avr32-asm.h
10010  DEPTC_bfin_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
10011    $(INCDIR)/elf/common.h $(INCDIR)/elf/external.h $(INCDIR)/elf/internal.h \
10012    $(INCDIR)/bfdlink.h $(srcdir)/config/tc-bfin.h dwarf2dbg.h \
10013 @@ -1511,6 +1519,11 @@ DEPOBJ_avr_elf = $(srcdir)/config/obj-el
10014    $(INCDIR)/bfdlink.h $(srcdir)/config/tc-avr.h dwarf2dbg.h \
10015    $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
10016    struc-symbol.h $(INCDIR)/aout/aout64.h
10017 +DEPOBJ_avr32_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
10018 +  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
10019 +  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-avr32.h \
10020 +  $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
10021 +  struc-symbol.h dwarf2dbg.h
10022  DEPOBJ_bfin_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
10023    $(INCDIR)/elf/common.h $(INCDIR)/elf/external.h $(INCDIR)/elf/internal.h \
10024    $(INCDIR)/bfdlink.h $(srcdir)/config/tc-bfin.h dwarf2dbg.h \
10025 @@ -1884,6 +1897,9 @@ DEP_cr16_elf = $(srcdir)/config/obj-elf.
10026    $(INCDIR)/bfdlink.h $(srcdir)/config/tc-cr16.h dwarf2dbg.h \
10027    $(srcdir)/config/obj-coff.h $(INCDIR)/coff/internal.h \
10028    $(BFDDIR)/libcoff.h
10029 +DEP_avr32_elf = $(srcdir)/config/obj-elf.h $(INCDIR)/symcat.h \
10030 +  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
10031 +  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-avr32.h
10032  DEP_cris_aout = $(srcdir)/config/obj-aout.h $(srcdir)/config/tc-cris.h \
10033    $(BFDDIR)/libaout.h $(INCDIR)/bfdlink.h
10034  DEP_cris_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
10035 --- a/gas/Makefile.in
10036 +++ b/gas/Makefile.in
10037 @@ -296,6 +296,7 @@ CPU_TYPES = \
10038         arc \
10039         arm \
10040         avr \
10041 +       avr32 \
10042         bfin \
10043         cr16 \
10044         cris \
10045 @@ -489,6 +490,7 @@ TARGET_CPU_CFILES = \
10046         config/tc-arc.c \
10047         config/tc-arm.c \
10048         config/tc-avr.c \
10049 +       config/tc-avr32.c \
10050         config/tc-bfin.c \
10051         config/tc-cr16.c \
10052         config/tc-cris.c \
10053 @@ -550,6 +552,7 @@ TARGET_CPU_HFILES = \
10054         config/tc-arc.h \
10055         config/tc-arm.h \
10056         config/tc-avr.h \
10057 +       config/tc-avr32.h \
10058         config/tc-bfin.h \
10059         config/tc-cr16.h \
10060         config/tc-cris.h \
10061 @@ -844,6 +847,12 @@ DEPTC_avr_elf = $(srcdir)/config/obj-elf
10062    $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
10063    $(INCDIR)/opcode/avr.h
10064
10065 +DEPTC_avr32_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
10066 +  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
10067 +  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-avr32.h \
10068 +  $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
10069 +  $(srcdir)/../opcodes/avr32-opc.h $(srcdir)/../opcodes/avr32-asm.h
10070 +
10071  DEPTC_bfin_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
10072    $(INCDIR)/elf/common.h $(INCDIR)/elf/external.h $(INCDIR)/elf/internal.h \
10073    $(INCDIR)/bfdlink.h $(srcdir)/config/tc-bfin.h dwarf2dbg.h \
10074 @@ -1359,6 +1368,12 @@ DEPOBJ_avr_elf = $(srcdir)/config/obj-el
10075    $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
10076    struc-symbol.h $(INCDIR)/aout/aout64.h
10077
10078 +DEPOBJ_avr32_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
10079 +  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
10080 +  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-avr32.h \
10081 +  $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
10082 +  struc-symbol.h dwarf2dbg.h
10083 +
10084  DEPOBJ_bfin_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
10085    $(INCDIR)/elf/common.h $(INCDIR)/elf/external.h $(INCDIR)/elf/internal.h \
10086    $(INCDIR)/bfdlink.h $(srcdir)/config/tc-bfin.h dwarf2dbg.h \
10087 @@ -1814,6 +1829,10 @@ DEP_cr16_elf = $(srcdir)/config/obj-elf.
10088    $(srcdir)/config/obj-coff.h $(INCDIR)/coff/internal.h \
10089    $(BFDDIR)/libcoff.h
10090
10091 +DEP_avr32_elf = $(srcdir)/config/obj-elf.h $(INCDIR)/symcat.h \
10092 +  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
10093 +  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-avr32.h
10094 +
10095  DEP_cris_aout = $(srcdir)/config/obj-aout.h $(srcdir)/config/tc-cris.h \
10096    $(BFDDIR)/libaout.h $(INCDIR)/bfdlink.h
10097
10098 --- /dev/null
10099 +++ b/gas/testsuite/gas/avr32/aliases.d
10100 @@ -0,0 +1,19 @@
10101 +#as:
10102 +#objdump: -dr
10103 +#name: aliases
10104 +
10105 +.*: +file format .*
10106 +
10107 +Disassembly of section \.text:
10108 +
10109 +00000000 <ld_nodisp>:
10110 +   0:  19 80      [ \t]+ld\.ub r0,r12\[0x0\]
10111 +   2:  f9 20 00 00[ \t]+ld\.sb r0,r12\[0\]
10112 +   6:  98 80      [ \t]+ld\.uh r0,r12\[0x0\]
10113 +   8:  98 00      [ \t]+ld\.sh r0,r12\[0x0\]
10114 +   a:  78 00      [ \t]+ld\.w r0,r12\[0x0\]
10115 +
10116 +0000000c <st_nodisp>:
10117 +   c:  b8 80      [ \t]+st\.b r12\[0x0\],r0
10118 +   e:  b8 00      [ \t]+st\.h r12\[0x0\],r0
10119 +  10:  99 00      [ \t]+st\.w r12\[0x0\],r0
10120 --- /dev/null
10121 +++ b/gas/testsuite/gas/avr32/aliases.s
10122 @@ -0,0 +1,14 @@
10123 +       .text
10124 +       .global ld_nodisp
10125 +ld_nodisp:
10126 +       ld.ub   r0, r12
10127 +       ld.sb   r0, r12
10128 +       ld.uh   r0, r12
10129 +       ld.sh   r0, r12
10130 +       ld.w    r0, r12
10131 +
10132 +       .global st_nodisp
10133 +st_nodisp:
10134 +       st.b    r12, r0
10135 +       st.h    r12, r0
10136 +       st.w    r12, r0
10137 --- /dev/null
10138 +++ b/gas/testsuite/gas/avr32/allinsn.d
10139 @@ -0,0 +1,2987 @@
10140 +#as:
10141 +#objdump: -dr
10142 +#name: allinsn
10143 +
10144 +.*: +file format .*
10145 +
10146 +Disassembly of section \.text:
10147 +
10148 +[0-9a-f]* <ld_d5>:
10149 + *[0-9a-f]*:   fe 0f 02 3e     ld\.d lr,pc\[pc<<0x3\]
10150 + *[0-9a-f]*:   e0 00 02 00     ld\.d r0,r0\[r0\]
10151 + *[0-9a-f]*:   ea 05 02 26     ld\.d r6,r5\[r5<<0x2\]
10152 + *[0-9a-f]*:   e8 04 02 14     ld\.d r4,r4\[r4<<0x1\]
10153 + *[0-9a-f]*:   fc 0e 02 1e     ld\.d lr,lr\[lr<<0x1\]
10154 + *[0-9a-f]*:   e6 0d 02 2a     ld\.d r10,r3\[sp<<0x2\]
10155 + *[0-9a-f]*:   f4 06 02 28     ld\.d r8,r10\[r6<<0x2\]
10156 + *[0-9a-f]*:   ee 09 02 02     ld\.d r2,r7\[r9\]
10157 +
10158 +[0-9a-f]* <ld_w5>:
10159 + *[0-9a-f]*:   fe 0f 03 0f     ld\.w pc,pc\[pc\]
10160 + *[0-9a-f]*:   f8 0c 03 3c     ld\.w r12,r12\[r12<<0x3\]
10161 + *[0-9a-f]*:   ea 05 03 25     ld\.w r5,r5\[r5<<0x2\]
10162 + *[0-9a-f]*:   e8 04 03 14     ld\.w r4,r4\[r4<<0x1\]
10163 + *[0-9a-f]*:   fc 0e 03 1e     ld\.w lr,lr\[lr<<0x1\]
10164 + *[0-9a-f]*:   f2 09 03 02     ld\.w r2,r9\[r9\]
10165 + *[0-9a-f]*:   e4 06 03 0b     ld\.w r11,r2\[r6\]
10166 + *[0-9a-f]*:   e4 0d 03 30     ld\.w r0,r2\[sp<<0x3\]
10167 +
10168 +[0-9a-f]* <ld_sh5>:
10169 + *[0-9a-f]*:   fe 0f 04 0f     ld\.sh pc,pc\[pc\]
10170 + *[0-9a-f]*:   f8 0c 04 3c     ld\.sh r12,r12\[r12<<0x3\]
10171 + *[0-9a-f]*:   ea 05 04 25     ld\.sh r5,r5\[r5<<0x2\]
10172 + *[0-9a-f]*:   e8 04 04 14     ld\.sh r4,r4\[r4<<0x1\]
10173 + *[0-9a-f]*:   fc 0e 04 1e     ld\.sh lr,lr\[lr<<0x1\]
10174 + *[0-9a-f]*:   e0 0f 04 2b     ld\.sh r11,r0\[pc<<0x2\]
10175 + *[0-9a-f]*:   fa 06 04 2a     ld\.sh r10,sp\[r6<<0x2\]
10176 + *[0-9a-f]*:   e4 02 04 0c     ld\.sh r12,r2\[r2\]
10177 +
10178 +[0-9a-f]* <ld_uh5>:
10179 + *[0-9a-f]*:   fe 0f 05 0f     ld\.uh pc,pc\[pc\]
10180 + *[0-9a-f]*:   f8 0c 05 3c     ld\.uh r12,r12\[r12<<0x3\]
10181 + *[0-9a-f]*:   ea 05 05 25     ld\.uh r5,r5\[r5<<0x2\]
10182 + *[0-9a-f]*:   e8 04 05 14     ld\.uh r4,r4\[r4<<0x1\]
10183 + *[0-9a-f]*:   fc 0e 05 1e     ld\.uh lr,lr\[lr<<0x1\]
10184 + *[0-9a-f]*:   fe 0e 05 38     ld\.uh r8,pc\[lr<<0x3\]
10185 + *[0-9a-f]*:   e2 0f 05 16     ld\.uh r6,r1\[pc<<0x1\]
10186 + *[0-9a-f]*:   fc 0d 05 16     ld\.uh r6,lr\[sp<<0x1\]
10187 +
10188 +[0-9a-f]* <ld_sb2>:
10189 + *[0-9a-f]*:   fe 0f 06 0f     ld\.sb pc,pc\[pc\]
10190 + *[0-9a-f]*:   f8 0c 06 3c     ld\.sb r12,r12\[r12<<0x3\]
10191 + *[0-9a-f]*:   ea 05 06 25     ld\.sb r5,r5\[r5<<0x2\]
10192 + *[0-9a-f]*:   e8 04 06 14     ld\.sb r4,r4\[r4<<0x1\]
10193 + *[0-9a-f]*:   fc 0e 06 1e     ld\.sb lr,lr\[lr<<0x1\]
10194 + *[0-9a-f]*:   e2 0f 06 39     ld\.sb r9,r1\[pc<<0x3\]
10195 + *[0-9a-f]*:   e6 0b 06 10     ld\.sb r0,r3\[r11<<0x1\]
10196 + *[0-9a-f]*:   ea 05 06 1a     ld\.sb r10,r5\[r5<<0x1\]
10197 +
10198 +[0-9a-f]* <ld_ub5>:
10199 + *[0-9a-f]*:   fe 0f 07 0f     ld\.ub pc,pc\[pc\]
10200 + *[0-9a-f]*:   f8 0c 07 3c     ld\.ub r12,r12\[r12<<0x3\]
10201 + *[0-9a-f]*:   ea 05 07 25     ld\.ub r5,r5\[r5<<0x2\]
10202 + *[0-9a-f]*:   e8 04 07 14     ld\.ub r4,r4\[r4<<0x1\]
10203 + *[0-9a-f]*:   fc 0e 07 1e     ld\.ub lr,lr\[lr<<0x1\]
10204 + *[0-9a-f]*:   f8 07 07 36     ld\.ub r6,r12\[r7<<0x3\]
10205 + *[0-9a-f]*:   ec 0c 07 02     ld\.ub r2,r6\[r12\]
10206 + *[0-9a-f]*:   ee 0b 07 10     ld\.ub r0,r7\[r11<<0x1\]
10207 +
10208 +[0-9a-f]* <st_d5>:
10209 + *[0-9a-f]*:   fe 0f 08 0e     st\.d pc\[pc\],lr
10210 + *[0-9a-f]*:   f8 0c 08 3c     st\.d r12\[r12<<0x3\],r12
10211 + *[0-9a-f]*:   ea 05 08 26     st\.d r5\[r5<<0x2\],r6
10212 + *[0-9a-f]*:   e8 04 08 14     st\.d r4\[r4<<0x1\],r4
10213 + *[0-9a-f]*:   fc 0e 08 1e     st\.d lr\[lr<<0x1\],lr
10214 + *[0-9a-f]*:   e2 09 08 14     st\.d r1\[r9<<0x1\],r4
10215 + *[0-9a-f]*:   f4 02 08 14     st\.d r10\[r2<<0x1\],r4
10216 + *[0-9a-f]*:   f8 06 08 0e     st\.d r12\[r6\],lr
10217 +
10218 +[0-9a-f]* <st_w5>:
10219 + *[0-9a-f]*:   fe 0f 09 0f     st\.w pc\[pc\],pc
10220 + *[0-9a-f]*:   f8 0c 09 3c     st\.w r12\[r12<<0x3\],r12
10221 + *[0-9a-f]*:   ea 05 09 25     st\.w r5\[r5<<0x2\],r5
10222 + *[0-9a-f]*:   e8 04 09 14     st\.w r4\[r4<<0x1\],r4
10223 + *[0-9a-f]*:   fc 0e 09 1e     st\.w lr\[lr<<0x1\],lr
10224 + *[0-9a-f]*:   e2 0a 09 03     st\.w r1\[r10\],r3
10225 + *[0-9a-f]*:   e0 0a 09 19     st\.w r0\[r10<<0x1\],r9
10226 + *[0-9a-f]*:   e8 05 09 3f     st\.w r4\[r5<<0x3\],pc
10227 +
10228 +[0-9a-f]* <st_h5>:
10229 + *[0-9a-f]*:   fe 0f 0a 0f     st\.h pc\[pc\],pc
10230 + *[0-9a-f]*:   f8 0c 0a 3c     st\.h r12\[r12<<0x3\],r12
10231 + *[0-9a-f]*:   ea 05 0a 25     st\.h r5\[r5<<0x2\],r5
10232 + *[0-9a-f]*:   e8 04 0a 14     st\.h r4\[r4<<0x1\],r4
10233 + *[0-9a-f]*:   fc 0e 0a 1e     st\.h lr\[lr<<0x1\],lr
10234 + *[0-9a-f]*:   e4 09 0a 0b     st\.h r2\[r9\],r11
10235 + *[0-9a-f]*:   ea 01 0a 2c     st\.h r5\[r1<<0x2\],r12
10236 + *[0-9a-f]*:   fe 08 0a 23     st\.h pc\[r8<<0x2\],r3
10237 +
10238 +[0-9a-f]* <st_b5>:
10239 + *[0-9a-f]*:   fe 0f 0b 0f     st\.b pc\[pc\],pc
10240 + *[0-9a-f]*:   f8 0c 0b 3c     st\.b r12\[r12<<0x3\],r12
10241 + *[0-9a-f]*:   ea 05 0b 25     st\.b r5\[r5<<0x2\],r5
10242 + *[0-9a-f]*:   e8 04 0b 14     st\.b r4\[r4<<0x1\],r4
10243 + *[0-9a-f]*:   fc 0e 0b 1e     st\.b lr\[lr<<0x1\],lr
10244 + *[0-9a-f]*:   e2 08 0b 16     st\.b r1\[r8<<0x1\],r6
10245 + *[0-9a-f]*:   fc 0e 0b 31     st\.b lr\[lr<<0x3\],r1
10246 + *[0-9a-f]*:   ea 00 0b 2f     st\.b r5\[r0<<0x2\],pc
10247 +
10248 +[0-9a-f]* <divs>:
10249 + *[0-9a-f]*:   fe 0f 0c 0f     divs pc,pc,pc
10250 + *[0-9a-f]*:   f8 0c 0c 0c     divs r12,r12,r12
10251 + *[0-9a-f]*:   ea 05 0c 05     divs r5,r5,r5
10252 + *[0-9a-f]*:   e8 04 0c 04     divs r4,r4,r4
10253 + *[0-9a-f]*:   fc 0e 0c 0e     divs lr,lr,lr
10254 + *[0-9a-f]*:   fe 0f 0c 03     divs r3,pc,pc
10255 + *[0-9a-f]*:   f8 02 0c 09     divs r9,r12,r2
10256 + *[0-9a-f]*:   e8 01 0c 07     divs r7,r4,r1
10257 +
10258 +[0-9a-f]* <add1>:
10259 + *[0-9a-f]*:   1e 0f           add pc,pc
10260 + *[0-9a-f]*:   18 0c           add r12,r12
10261 + *[0-9a-f]*:   0a 05           add r5,r5
10262 + *[0-9a-f]*:   08 04           add r4,r4
10263 + *[0-9a-f]*:   1c 0e           add lr,lr
10264 + *[0-9a-f]*:   12 0c           add r12,r9
10265 + *[0-9a-f]*:   06 06           add r6,r3
10266 + *[0-9a-f]*:   18 0a           add r10,r12
10267 +
10268 +[0-9a-f]* <sub1>:
10269 + *[0-9a-f]*:   1e 1f           sub pc,pc
10270 + *[0-9a-f]*:   18 1c           sub r12,r12
10271 + *[0-9a-f]*:   0a 15           sub r5,r5
10272 + *[0-9a-f]*:   08 14           sub r4,r4
10273 + *[0-9a-f]*:   1c 1e           sub lr,lr
10274 + *[0-9a-f]*:   0c 1e           sub lr,r6
10275 + *[0-9a-f]*:   1a 10           sub r0,sp
10276 + *[0-9a-f]*:   18 16           sub r6,r12
10277 +
10278 +[0-9a-f]* <rsub1>:
10279 + *[0-9a-f]*:   1e 2f           rsub pc,pc
10280 + *[0-9a-f]*:   18 2c           rsub r12,r12
10281 + *[0-9a-f]*:   0a 25           rsub r5,r5
10282 + *[0-9a-f]*:   08 24           rsub r4,r4
10283 + *[0-9a-f]*:   1c 2e           rsub lr,lr
10284 + *[0-9a-f]*:   1a 2b           rsub r11,sp
10285 + *[0-9a-f]*:   08 27           rsub r7,r4
10286 + *[0-9a-f]*:   02 29           rsub r9,r1
10287 +
10288 +[0-9a-f]* <cp1>:
10289 + *[0-9a-f]*:   1e 3f           cp\.w pc,pc
10290 + *[0-9a-f]*:   18 3c           cp\.w r12,r12
10291 + *[0-9a-f]*:   0a 35           cp\.w r5,r5
10292 + *[0-9a-f]*:   08 34           cp\.w r4,r4
10293 + *[0-9a-f]*:   1c 3e           cp\.w lr,lr
10294 + *[0-9a-f]*:   04 36           cp\.w r6,r2
10295 + *[0-9a-f]*:   12 30           cp\.w r0,r9
10296 + *[0-9a-f]*:   1a 33           cp\.w r3,sp
10297 +
10298 +[0-9a-f]* <or1>:
10299 + *[0-9a-f]*:   1e 4f           or pc,pc
10300 + *[0-9a-f]*:   18 4c           or r12,r12
10301 + *[0-9a-f]*:   0a 45           or r5,r5
10302 + *[0-9a-f]*:   08 44           or r4,r4
10303 + *[0-9a-f]*:   1c 4e           or lr,lr
10304 + *[0-9a-f]*:   12 44           or r4,r9
10305 + *[0-9a-f]*:   08 4b           or r11,r4
10306 + *[0-9a-f]*:   00 44           or r4,r0
10307 +
10308 +[0-9a-f]* <eor1>:
10309 + *[0-9a-f]*:   1e 5f           eor pc,pc
10310 + *[0-9a-f]*:   18 5c           eor r12,r12
10311 + *[0-9a-f]*:   0a 55           eor r5,r5
10312 + *[0-9a-f]*:   08 54           eor r4,r4
10313 + *[0-9a-f]*:   1c 5e           eor lr,lr
10314 + *[0-9a-f]*:   16 5c           eor r12,r11
10315 + *[0-9a-f]*:   02 50           eor r0,r1
10316 + *[0-9a-f]*:   1e 55           eor r5,pc
10317 +
10318 +[0-9a-f]* <and1>:
10319 + *[0-9a-f]*:   1e 6f           and pc,pc
10320 + *[0-9a-f]*:   18 6c           and r12,r12
10321 + *[0-9a-f]*:   0a 65           and r5,r5
10322 + *[0-9a-f]*:   08 64           and r4,r4
10323 + *[0-9a-f]*:   1c 6e           and lr,lr
10324 + *[0-9a-f]*:   02 68           and r8,r1
10325 + *[0-9a-f]*:   1a 60           and r0,sp
10326 + *[0-9a-f]*:   0a 6a           and r10,r5
10327 +
10328 +[0-9a-f]* <tst>:
10329 + *[0-9a-f]*:   1e 7f           tst pc,pc
10330 + *[0-9a-f]*:   18 7c           tst r12,r12
10331 + *[0-9a-f]*:   0a 75           tst r5,r5
10332 + *[0-9a-f]*:   08 74           tst r4,r4
10333 + *[0-9a-f]*:   1c 7e           tst lr,lr
10334 + *[0-9a-f]*:   18 70           tst r0,r12
10335 + *[0-9a-f]*:   0c 7a           tst r10,r6
10336 + *[0-9a-f]*:   08 7d           tst sp,r4
10337 +
10338 +[0-9a-f]* <andn>:
10339 + *[0-9a-f]*:   1e 8f           andn pc,pc
10340 + *[0-9a-f]*:   18 8c           andn r12,r12
10341 + *[0-9a-f]*:   0a 85           andn r5,r5
10342 + *[0-9a-f]*:   08 84           andn r4,r4
10343 + *[0-9a-f]*:   1c 8e           andn lr,lr
10344 + *[0-9a-f]*:   18 89           andn r9,r12
10345 + *[0-9a-f]*:   1a 8b           andn r11,sp
10346 + *[0-9a-f]*:   0a 8c           andn r12,r5
10347 +
10348 +[0-9a-f]* <mov3>:
10349 + *[0-9a-f]*:   1e 9f           mov pc,pc
10350 + *[0-9a-f]*:   18 9c           mov r12,r12
10351 + *[0-9a-f]*:   0a 95           mov r5,r5
10352 + *[0-9a-f]*:   08 94           mov r4,r4
10353 + *[0-9a-f]*:   1c 9e           mov lr,lr
10354 + *[0-9a-f]*:   12 95           mov r5,r9
10355 + *[0-9a-f]*:   16 9b           mov r11,r11
10356 + *[0-9a-f]*:   1c 92           mov r2,lr
10357 +
10358 +[0-9a-f]* <st_w1>:
10359 + *[0-9a-f]*:   1e af           st\.w pc\+\+,pc
10360 + *[0-9a-f]*:   18 ac           st\.w r12\+\+,r12
10361 + *[0-9a-f]*:   0a a5           st\.w r5\+\+,r5
10362 + *[0-9a-f]*:   08 a4           st\.w r4\+\+,r4
10363 + *[0-9a-f]*:   1c ae           st\.w lr\+\+,lr
10364 + *[0-9a-f]*:   02 ab           st\.w r1\+\+,r11
10365 + *[0-9a-f]*:   1a a0           st\.w sp\+\+,r0
10366 + *[0-9a-f]*:   1a a1           st\.w sp\+\+,r1
10367 +
10368 +[0-9a-f]* <st_h1>:
10369 + *[0-9a-f]*:   1e bf           st\.h pc\+\+,pc
10370 + *[0-9a-f]*:   18 bc           st\.h r12\+\+,r12
10371 + *[0-9a-f]*:   0a b5           st\.h r5\+\+,r5
10372 + *[0-9a-f]*:   08 b4           st\.h r4\+\+,r4
10373 + *[0-9a-f]*:   1c be           st\.h lr\+\+,lr
10374 + *[0-9a-f]*:   18 bd           st\.h r12\+\+,sp
10375 + *[0-9a-f]*:   0e be           st\.h r7\+\+,lr
10376 + *[0-9a-f]*:   0e b4           st\.h r7\+\+,r4
10377 +
10378 +[0-9a-f]* <st_b1>:
10379 + *[0-9a-f]*:   1e cf           st\.b pc\+\+,pc
10380 + *[0-9a-f]*:   18 cc           st\.b r12\+\+,r12
10381 + *[0-9a-f]*:   0a c5           st\.b r5\+\+,r5
10382 + *[0-9a-f]*:   08 c4           st\.b r4\+\+,r4
10383 + *[0-9a-f]*:   1c ce           st\.b lr\+\+,lr
10384 + *[0-9a-f]*:   12 cd           st\.b r9\+\+,sp
10385 + *[0-9a-f]*:   02 cd           st\.b r1\+\+,sp
10386 + *[0-9a-f]*:   00 c4           st\.b r0\+\+,r4
10387 +
10388 +[0-9a-f]* <st_w2>:
10389 + *[0-9a-f]*:   1e df           st\.w --pc,pc
10390 + *[0-9a-f]*:   18 dc           st\.w --r12,r12
10391 + *[0-9a-f]*:   0a d5           st\.w --r5,r5
10392 + *[0-9a-f]*:   08 d4           st\.w --r4,r4
10393 + *[0-9a-f]*:   1c de           st\.w --lr,lr
10394 + *[0-9a-f]*:   02 d7           st\.w --r1,r7
10395 + *[0-9a-f]*:   06 d9           st\.w --r3,r9
10396 + *[0-9a-f]*:   0a d5           st\.w --r5,r5
10397 +
10398 +[0-9a-f]* <st_h2>:
10399 + *[0-9a-f]*:   1e ef           st\.h --pc,pc
10400 + *[0-9a-f]*:   18 ec           st\.h --r12,r12
10401 + *[0-9a-f]*:   0a e5           st\.h --r5,r5
10402 + *[0-9a-f]*:   08 e4           st\.h --r4,r4
10403 + *[0-9a-f]*:   1c ee           st\.h --lr,lr
10404 + *[0-9a-f]*:   0a e7           st\.h --r5,r7
10405 + *[0-9a-f]*:   10 e8           st\.h --r8,r8
10406 + *[0-9a-f]*:   0e e2           st\.h --r7,r2
10407 +
10408 +[0-9a-f]* <st_b2>:
10409 + *[0-9a-f]*:   1e ff           st\.b --pc,pc
10410 + *[0-9a-f]*:   18 fc           st\.b --r12,r12
10411 + *[0-9a-f]*:   0a f5           st\.b --r5,r5
10412 + *[0-9a-f]*:   08 f4           st\.b --r4,r4
10413 + *[0-9a-f]*:   1c fe           st\.b --lr,lr
10414 + *[0-9a-f]*:   1a fd           st\.b --sp,sp
10415 + *[0-9a-f]*:   1a fb           st\.b --sp,r11
10416 + *[0-9a-f]*:   08 f5           st\.b --r4,r5
10417 +
10418 +[0-9a-f]* <ld_w1>:
10419 + *[0-9a-f]*:   1f 0f           ld\.w pc,pc\+\+
10420 + *[0-9a-f]*:   19 0c           ld\.w r12,r12\+\+
10421 + *[0-9a-f]*:   0b 05           ld\.w r5,r5\+\+
10422 + *[0-9a-f]*:   09 04           ld\.w r4,r4\+\+
10423 + *[0-9a-f]*:   1d 0e           ld\.w lr,lr\+\+
10424 + *[0-9a-f]*:   0f 03           ld\.w r3,r7\+\+
10425 + *[0-9a-f]*:   1d 03           ld\.w r3,lr\+\+
10426 + *[0-9a-f]*:   0b 0c           ld\.w r12,r5\+\+
10427 +
10428 +[0-9a-f]* <ld_sh1>:
10429 + *[0-9a-f]*:   1f 1f           ld\.sh pc,pc\+\+
10430 + *[0-9a-f]*:   19 1c           ld\.sh r12,r12\+\+
10431 + *[0-9a-f]*:   0b 15           ld\.sh r5,r5\+\+
10432 + *[0-9a-f]*:   09 14           ld\.sh r4,r4\+\+
10433 + *[0-9a-f]*:   1d 1e           ld\.sh lr,lr\+\+
10434 + *[0-9a-f]*:   05 1b           ld\.sh r11,r2\+\+
10435 + *[0-9a-f]*:   11 12           ld\.sh r2,r8\+\+
10436 + *[0-9a-f]*:   0d 17           ld\.sh r7,r6\+\+
10437 +
10438 +[0-9a-f]* <ld_uh1>:
10439 + *[0-9a-f]*:   1f 2f           ld\.uh pc,pc\+\+
10440 + *[0-9a-f]*:   19 2c           ld\.uh r12,r12\+\+
10441 + *[0-9a-f]*:   0b 25           ld\.uh r5,r5\+\+
10442 + *[0-9a-f]*:   09 24           ld\.uh r4,r4\+\+
10443 + *[0-9a-f]*:   1d 2e           ld\.uh lr,lr\+\+
10444 + *[0-9a-f]*:   0f 26           ld\.uh r6,r7\+\+
10445 + *[0-9a-f]*:   17 2a           ld\.uh r10,r11\+\+
10446 + *[0-9a-f]*:   09 2e           ld\.uh lr,r4\+\+
10447 +
10448 +[0-9a-f]* <ld_ub1>:
10449 + *[0-9a-f]*:   1f 3f           ld\.ub pc,pc\+\+
10450 + *[0-9a-f]*:   19 3c           ld\.ub r12,r12\+\+
10451 + *[0-9a-f]*:   0b 35           ld\.ub r5,r5\+\+
10452 + *[0-9a-f]*:   09 34           ld\.ub r4,r4\+\+
10453 + *[0-9a-f]*:   1d 3e           ld\.ub lr,lr\+\+
10454 + *[0-9a-f]*:   1d 38           ld\.ub r8,lr\+\+
10455 + *[0-9a-f]*:   19 3c           ld\.ub r12,r12\+\+
10456 + *[0-9a-f]*:   15 3b           ld\.ub r11,r10\+\+
10457 +
10458 +[0-9a-f]* <ld_w2>:
10459 + *[0-9a-f]*:   1f 4f           ld\.w pc,--pc
10460 + *[0-9a-f]*:   19 4c           ld\.w r12,--r12
10461 + *[0-9a-f]*:   0b 45           ld\.w r5,--r5
10462 + *[0-9a-f]*:   09 44           ld\.w r4,--r4
10463 + *[0-9a-f]*:   1d 4e           ld\.w lr,--lr
10464 + *[0-9a-f]*:   1d 4a           ld\.w r10,--lr
10465 + *[0-9a-f]*:   13 4c           ld\.w r12,--r9
10466 + *[0-9a-f]*:   0b 46           ld\.w r6,--r5
10467 +
10468 +[0-9a-f]* <ld_sh2>:
10469 + *[0-9a-f]*:   1f 5f           ld\.sh pc,--pc
10470 + *[0-9a-f]*:   19 5c           ld\.sh r12,--r12
10471 + *[0-9a-f]*:   0b 55           ld\.sh r5,--r5
10472 + *[0-9a-f]*:   09 54           ld\.sh r4,--r4
10473 + *[0-9a-f]*:   1d 5e           ld\.sh lr,--lr
10474 + *[0-9a-f]*:   15 5f           ld\.sh pc,--r10
10475 + *[0-9a-f]*:   07 56           ld\.sh r6,--r3
10476 + *[0-9a-f]*:   0d 54           ld\.sh r4,--r6
10477 +
10478 +[0-9a-f]* <ld_uh2>:
10479 + *[0-9a-f]*:   1f 6f           ld\.uh pc,--pc
10480 + *[0-9a-f]*:   19 6c           ld\.uh r12,--r12
10481 + *[0-9a-f]*:   0b 65           ld\.uh r5,--r5
10482 + *[0-9a-f]*:   09 64           ld\.uh r4,--r4
10483 + *[0-9a-f]*:   1d 6e           ld\.uh lr,--lr
10484 + *[0-9a-f]*:   05 63           ld\.uh r3,--r2
10485 + *[0-9a-f]*:   01 61           ld\.uh r1,--r0
10486 + *[0-9a-f]*:   13 62           ld\.uh r2,--r9
10487 +
10488 +[0-9a-f]* <ld_ub2>:
10489 + *[0-9a-f]*:   1f 7f           ld\.ub pc,--pc
10490 + *[0-9a-f]*:   19 7c           ld\.ub r12,--r12
10491 + *[0-9a-f]*:   0b 75           ld\.ub r5,--r5
10492 + *[0-9a-f]*:   09 74           ld\.ub r4,--r4
10493 + *[0-9a-f]*:   1d 7e           ld\.ub lr,--lr
10494 + *[0-9a-f]*:   03 71           ld\.ub r1,--r1
10495 + *[0-9a-f]*:   0d 70           ld\.ub r0,--r6
10496 + *[0-9a-f]*:   0f 72           ld\.ub r2,--r7
10497 +
10498 +[0-9a-f]* <ld_ub3>:
10499 + *[0-9a-f]*:   1f 8f           ld\.ub pc,pc\[0x0\]
10500 + *[0-9a-f]*:   19 fc           ld\.ub r12,r12\[0x7\]
10501 + *[0-9a-f]*:   0b c5           ld\.ub r5,r5\[0x4\]
10502 + *[0-9a-f]*:   09 b4           ld\.ub r4,r4\[0x3\]
10503 + *[0-9a-f]*:   1d 9e           ld\.ub lr,lr\[0x1\]
10504 + *[0-9a-f]*:   13 e6           ld\.ub r6,r9\[0x6\]
10505 + *[0-9a-f]*:   1d c2           ld\.ub r2,lr\[0x4\]
10506 + *[0-9a-f]*:   11 81           ld\.ub r1,r8\[0x0\]
10507 +
10508 +[0-9a-f]* <sub3_sp>:
10509 + *[0-9a-f]*:   20 0d           sub sp,0
10510 + *[0-9a-f]*:   2f fd           sub sp,-4
10511 + *[0-9a-f]*:   28 0d           sub sp,-512
10512 + *[0-9a-f]*:   27 fd           sub sp,508
10513 + *[0-9a-f]*:   20 1d           sub sp,4
10514 + *[0-9a-f]*:   20 bd           sub sp,44
10515 + *[0-9a-f]*:   20 2d           sub sp,8
10516 + *[0-9a-f]*:   25 7d           sub sp,348
10517 +
10518 +[0-9a-f]* <sub3>:
10519 + *[0-9a-f]*:   20 0f           sub pc,0
10520 + *[0-9a-f]*:   2f fc           sub r12,-1
10521 + *[0-9a-f]*:   28 05           sub r5,-128
10522 + *[0-9a-f]*:   27 f4           sub r4,127
10523 + *[0-9a-f]*:   20 1e           sub lr,1
10524 + *[0-9a-f]*:   2d 76           sub r6,-41
10525 + *[0-9a-f]*:   22 54           sub r4,37
10526 + *[0-9a-f]*:   23 8c           sub r12,56
10527 +
10528 +[0-9a-f]* <mov1>:
10529 + *[0-9a-f]*:   30 0f           mov pc,0
10530 + *[0-9a-f]*:   3f fc           mov r12,-1
10531 + *[0-9a-f]*:   38 05           mov r5,-128
10532 + *[0-9a-f]*:   37 f4           mov r4,127
10533 + *[0-9a-f]*:   30 1e           mov lr,1
10534 + *[0-9a-f]*:   30 ef           mov pc,14
10535 + *[0-9a-f]*:   39 c6           mov r6,-100
10536 + *[0-9a-f]*:   38 6e           mov lr,-122
10537 +
10538 +[0-9a-f]* <lddsp>:
10539 + *[0-9a-f]*:   40 0f           lddsp pc,sp\[0x0\]
10540 + *[0-9a-f]*:   47 fc           lddsp r12,sp\[0x1fc\]
10541 + *[0-9a-f]*:   44 05           lddsp r5,sp\[0x100\]
10542 + *[0-9a-f]*:   43 f4           lddsp r4,sp\[0xfc\]
10543 + *[0-9a-f]*:   40 1e           lddsp lr,sp\[0x4\]
10544 + *[0-9a-f]*:   44 0e           lddsp lr,sp\[0x100\]
10545 + *[0-9a-f]*:   40 5c           lddsp r12,sp\[0x14\]
10546 + *[0-9a-f]*:   47 69           lddsp r9,sp\[0x1d8\]
10547 +
10548 +[0-9a-f]* <lddpc>:
10549 + *[0-9a-f]*:   48 0f           lddpc pc,[0-9a-f]* <.*>
10550 + *[0-9a-f]*:   4f f0           lddpc r0,[0-9a-f]* <.*>
10551 + *[0-9a-f]*:   4c 08           lddpc r8,[0-9a-f]* <.*>
10552 + *[0-9a-f]*:   4b f7           lddpc r7,[0-9a-f]* <.*>
10553 + *[0-9a-f]*:   48 1e           lddpc lr,[0-9a-f]* <.*>
10554 + *[0-9a-f]*:   4f 6d           lddpc sp,[0-9a-f]* <.*>
10555 + *[0-9a-f]*:   49 e6           lddpc r6,[0-9a-f]* <.*>
10556 + *[0-9a-f]*:   48 7b           lddpc r11,[0-9a-f]* <.*>
10557 +
10558 +[0-9a-f]* <stdsp>:
10559 + *[0-9a-f]*:   50 0f           stdsp sp\[0x0\],pc
10560 + *[0-9a-f]*:   57 fc           stdsp sp\[0x1fc\],r12
10561 + *[0-9a-f]*:   54 05           stdsp sp\[0x100\],r5
10562 + *[0-9a-f]*:   53 f4           stdsp sp\[0xfc\],r4
10563 + *[0-9a-f]*:   50 1e           stdsp sp\[0x4\],lr
10564 + *[0-9a-f]*:   54 cf           stdsp sp\[0x130\],pc
10565 + *[0-9a-f]*:   54 00           stdsp sp\[0x100\],r0
10566 + *[0-9a-f]*:   55 45           stdsp sp\[0x150\],r5
10567 +
10568 +[0-9a-f]* <cp2>:
10569 + *[0-9a-f]*:   58 0f           cp.w pc,0
10570 + *[0-9a-f]*:   5b fc           cp.w r12,-1
10571 + *[0-9a-f]*:   5a 05           cp.w r5,-32
10572 + *[0-9a-f]*:   59 f4           cp.w r4,31
10573 + *[0-9a-f]*:   58 1e           cp.w lr,1
10574 + *[0-9a-f]*:   58 38           cp.w r8,3
10575 + *[0-9a-f]*:   59 0e           cp.w lr,16
10576 + *[0-9a-f]*:   5a 67           cp.w r7,-26
10577 +
10578 +[0-9a-f]* <acr>:
10579 + *[0-9a-f]*:   5c 0f           acr pc
10580 + *[0-9a-f]*:   5c 0c           acr r12
10581 + *[0-9a-f]*:   5c 05           acr r5
10582 + *[0-9a-f]*:   5c 04           acr r4
10583 + *[0-9a-f]*:   5c 0e           acr lr
10584 + *[0-9a-f]*:   5c 02           acr r2
10585 + *[0-9a-f]*:   5c 0c           acr r12
10586 + *[0-9a-f]*:   5c 0f           acr pc
10587 +
10588 +[0-9a-f]* <scr>:
10589 + *[0-9a-f]*:   5c 1f           scr pc
10590 + *[0-9a-f]*:   5c 1c           scr r12
10591 + *[0-9a-f]*:   5c 15           scr r5
10592 + *[0-9a-f]*:   5c 14           scr r4
10593 + *[0-9a-f]*:   5c 1e           scr lr
10594 + *[0-9a-f]*:   5c 1f           scr pc
10595 + *[0-9a-f]*:   5c 16           scr r6
10596 + *[0-9a-f]*:   5c 11           scr r1
10597 +
10598 +[0-9a-f]* <cpc0>:
10599 + *[0-9a-f]*:   5c 2f           cpc pc
10600 + *[0-9a-f]*:   5c 2c           cpc r12
10601 + *[0-9a-f]*:   5c 25           cpc r5
10602 + *[0-9a-f]*:   5c 24           cpc r4
10603 + *[0-9a-f]*:   5c 2e           cpc lr
10604 + *[0-9a-f]*:   5c 2f           cpc pc
10605 + *[0-9a-f]*:   5c 24           cpc r4
10606 + *[0-9a-f]*:   5c 29           cpc r9
10607 +
10608 +[0-9a-f]* <neg>:
10609 + *[0-9a-f]*:   5c 3f           neg pc
10610 + *[0-9a-f]*:   5c 3c           neg r12
10611 + *[0-9a-f]*:   5c 35           neg r5
10612 + *[0-9a-f]*:   5c 34           neg r4
10613 + *[0-9a-f]*:   5c 3e           neg lr
10614 + *[0-9a-f]*:   5c 37           neg r7
10615 + *[0-9a-f]*:   5c 31           neg r1
10616 + *[0-9a-f]*:   5c 39           neg r9
10617 +
10618 +[0-9a-f]* <abs>:
10619 + *[0-9a-f]*:   5c 4f           abs pc
10620 + *[0-9a-f]*:   5c 4c           abs r12
10621 + *[0-9a-f]*:   5c 45           abs r5
10622 + *[0-9a-f]*:   5c 44           abs r4
10623 + *[0-9a-f]*:   5c 4e           abs lr
10624 + *[0-9a-f]*:   5c 46           abs r6
10625 + *[0-9a-f]*:   5c 46           abs r6
10626 + *[0-9a-f]*:   5c 44           abs r4
10627 +
10628 +[0-9a-f]* <castu_b>:
10629 + *[0-9a-f]*:   5c 5f           castu\.b pc
10630 + *[0-9a-f]*:   5c 5c           castu\.b r12
10631 + *[0-9a-f]*:   5c 55           castu\.b r5
10632 + *[0-9a-f]*:   5c 54           castu\.b r4
10633 + *[0-9a-f]*:   5c 5e           castu\.b lr
10634 + *[0-9a-f]*:   5c 57           castu\.b r7
10635 + *[0-9a-f]*:   5c 5d           castu\.b sp
10636 + *[0-9a-f]*:   5c 59           castu\.b r9
10637 +
10638 +[0-9a-f]* <casts_b>:
10639 + *[0-9a-f]*:   5c 6f           casts\.b pc
10640 + *[0-9a-f]*:   5c 6c           casts\.b r12
10641 + *[0-9a-f]*:   5c 65           casts\.b r5
10642 + *[0-9a-f]*:   5c 64           casts\.b r4
10643 + *[0-9a-f]*:   5c 6e           casts\.b lr
10644 + *[0-9a-f]*:   5c 6b           casts\.b r11
10645 + *[0-9a-f]*:   5c 61           casts\.b r1
10646 + *[0-9a-f]*:   5c 6a           casts\.b r10
10647 +
10648 +[0-9a-f]* <castu_h>:
10649 + *[0-9a-f]*:   5c 7f           castu\.h pc
10650 + *[0-9a-f]*:   5c 7c           castu\.h r12
10651 + *[0-9a-f]*:   5c 75           castu\.h r5
10652 + *[0-9a-f]*:   5c 74           castu\.h r4
10653 + *[0-9a-f]*:   5c 7e           castu\.h lr
10654 + *[0-9a-f]*:   5c 7a           castu\.h r10
10655 + *[0-9a-f]*:   5c 7b           castu\.h r11
10656 + *[0-9a-f]*:   5c 71           castu\.h r1
10657 +
10658 +[0-9a-f]* <casts_h>:
10659 + *[0-9a-f]*:   5c 8f           casts\.h pc
10660 + *[0-9a-f]*:   5c 8c           casts\.h r12
10661 + *[0-9a-f]*:   5c 85           casts\.h r5
10662 + *[0-9a-f]*:   5c 84           casts\.h r4
10663 + *[0-9a-f]*:   5c 8e           casts\.h lr
10664 + *[0-9a-f]*:   5c 80           casts\.h r0
10665 + *[0-9a-f]*:   5c 85           casts\.h r5
10666 + *[0-9a-f]*:   5c 89           casts\.h r9
10667 +
10668 +[0-9a-f]* <brev>:
10669 + *[0-9a-f]*:   5c 9f           brev pc
10670 + *[0-9a-f]*:   5c 9c           brev r12
10671 + *[0-9a-f]*:   5c 95           brev r5
10672 + *[0-9a-f]*:   5c 94           brev r4
10673 + *[0-9a-f]*:   5c 9e           brev lr
10674 + *[0-9a-f]*:   5c 95           brev r5
10675 + *[0-9a-f]*:   5c 9a           brev r10
10676 + *[0-9a-f]*:   5c 98           brev r8
10677 +
10678 +[0-9a-f]* <swap_h>:
10679 + *[0-9a-f]*:   5c af           swap\.h pc
10680 + *[0-9a-f]*:   5c ac           swap\.h r12
10681 + *[0-9a-f]*:   5c a5           swap\.h r5
10682 + *[0-9a-f]*:   5c a4           swap\.h r4
10683 + *[0-9a-f]*:   5c ae           swap\.h lr
10684 + *[0-9a-f]*:   5c a7           swap\.h r7
10685 + *[0-9a-f]*:   5c a0           swap\.h r0
10686 + *[0-9a-f]*:   5c a8           swap\.h r8
10687 +
10688 +[0-9a-f]* <swap_b>:
10689 + *[0-9a-f]*:   5c bf           swap\.b pc
10690 + *[0-9a-f]*:   5c bc           swap\.b r12
10691 + *[0-9a-f]*:   5c b5           swap\.b r5
10692 + *[0-9a-f]*:   5c b4           swap\.b r4
10693 + *[0-9a-f]*:   5c be           swap\.b lr
10694 + *[0-9a-f]*:   5c ba           swap\.b r10
10695 + *[0-9a-f]*:   5c bc           swap\.b r12
10696 + *[0-9a-f]*:   5c b1           swap\.b r1
10697 +
10698 +[0-9a-f]* <swap_bh>:
10699 + *[0-9a-f]*:   5c cf           swap\.bh pc
10700 + *[0-9a-f]*:   5c cc           swap\.bh r12
10701 + *[0-9a-f]*:   5c c5           swap\.bh r5
10702 + *[0-9a-f]*:   5c c4           swap\.bh r4
10703 + *[0-9a-f]*:   5c ce           swap\.bh lr
10704 + *[0-9a-f]*:   5c c9           swap\.bh r9
10705 + *[0-9a-f]*:   5c c4           swap\.bh r4
10706 + *[0-9a-f]*:   5c c1           swap\.bh r1
10707 +
10708 +[0-9a-f]* <One_s_compliment>:
10709 + *[0-9a-f]*:   5c df           com pc
10710 + *[0-9a-f]*:   5c dc           com r12
10711 + *[0-9a-f]*:   5c d5           com r5
10712 + *[0-9a-f]*:   5c d4           com r4
10713 + *[0-9a-f]*:   5c de           com lr
10714 + *[0-9a-f]*:   5c d2           com r2
10715 + *[0-9a-f]*:   5c d2           com r2
10716 + *[0-9a-f]*:   5c d7           com r7
10717 +
10718 +[0-9a-f]* <tnbz>:
10719 + *[0-9a-f]*:   5c ef           tnbz pc
10720 + *[0-9a-f]*:   5c ec           tnbz r12
10721 + *[0-9a-f]*:   5c e5           tnbz r5
10722 + *[0-9a-f]*:   5c e4           tnbz r4
10723 + *[0-9a-f]*:   5c ee           tnbz lr
10724 + *[0-9a-f]*:   5c e8           tnbz r8
10725 + *[0-9a-f]*:   5c ec           tnbz r12
10726 + *[0-9a-f]*:   5c ef           tnbz pc
10727 +
10728 +[0-9a-f]* <rol>:
10729 + *[0-9a-f]*:   5c ff           rol pc
10730 + *[0-9a-f]*:   5c fc           rol r12
10731 + *[0-9a-f]*:   5c f5           rol r5
10732 + *[0-9a-f]*:   5c f4           rol r4
10733 + *[0-9a-f]*:   5c fe           rol lr
10734 + *[0-9a-f]*:   5c fa           rol r10
10735 + *[0-9a-f]*:   5c f9           rol r9
10736 + *[0-9a-f]*:   5c f5           rol r5
10737 +
10738 +[0-9a-f]* <ror>:
10739 + *[0-9a-f]*:   5d 0f           ror pc
10740 + *[0-9a-f]*:   5d 0c           ror r12
10741 + *[0-9a-f]*:   5d 05           ror r5
10742 + *[0-9a-f]*:   5d 04           ror r4
10743 + *[0-9a-f]*:   5d 0e           ror lr
10744 + *[0-9a-f]*:   5d 08           ror r8
10745 + *[0-9a-f]*:   5d 04           ror r4
10746 + *[0-9a-f]*:   5d 07           ror r7
10747 +
10748 +[0-9a-f]* <icall>:
10749 + *[0-9a-f]*:   5d 1f           icall pc
10750 + *[0-9a-f]*:   5d 1c           icall r12
10751 + *[0-9a-f]*:   5d 15           icall r5
10752 + *[0-9a-f]*:   5d 14           icall r4
10753 + *[0-9a-f]*:   5d 1e           icall lr
10754 + *[0-9a-f]*:   5d 13           icall r3
10755 + *[0-9a-f]*:   5d 11           icall r1
10756 + *[0-9a-f]*:   5d 13           icall r3
10757 +
10758 +[0-9a-f]* <mustr>:
10759 + *[0-9a-f]*:   5d 2f           mustr pc
10760 + *[0-9a-f]*:   5d 2c           mustr r12
10761 + *[0-9a-f]*:   5d 25           mustr r5
10762 + *[0-9a-f]*:   5d 24           mustr r4
10763 + *[0-9a-f]*:   5d 2e           mustr lr
10764 + *[0-9a-f]*:   5d 21           mustr r1
10765 + *[0-9a-f]*:   5d 24           mustr r4
10766 + *[0-9a-f]*:   5d 2c           mustr r12
10767 +
10768 +[0-9a-f]* <musfr>:
10769 + *[0-9a-f]*:   5d 3f           musfr pc
10770 + *[0-9a-f]*:   5d 3c           musfr r12
10771 + *[0-9a-f]*:   5d 35           musfr r5
10772 + *[0-9a-f]*:   5d 34           musfr r4
10773 + *[0-9a-f]*:   5d 3e           musfr lr
10774 + *[0-9a-f]*:   5d 3b           musfr r11
10775 + *[0-9a-f]*:   5d 3c           musfr r12
10776 + *[0-9a-f]*:   5d 32           musfr r2
10777 +
10778 +[0-9a-f]* <ret_cond>:
10779 + *[0-9a-f]*:   5e 0f           reteq 1
10780 + *[0-9a-f]*:   5e fc           retal r12
10781 + *[0-9a-f]*:   5e 85           retls r5
10782 + *[0-9a-f]*:   5e 74           retpl r4
10783 + *[0-9a-f]*:   5e 1e           retne -1
10784 + *[0-9a-f]*:   5e 90           retgt r0
10785 + *[0-9a-f]*:   5e 9c           retgt r12
10786 + *[0-9a-f]*:   5e 4a           retge r10
10787 +
10788 +[0-9a-f]* <sr_cond>:
10789 + *[0-9a-f]*:   5f 0f           sreq pc
10790 + *[0-9a-f]*:   5f fc           sral r12
10791 + *[0-9a-f]*:   5f 85           srls r5
10792 + *[0-9a-f]*:   5f 74           srpl r4
10793 + *[0-9a-f]*:   5f 1e           srne lr
10794 + *[0-9a-f]*:   5f 50           srlt r0
10795 + *[0-9a-f]*:   5f fd           sral sp
10796 + *[0-9a-f]*:   5f 49           srge r9
10797 +
10798 +[0-9a-f]* <ld_w3>:
10799 + *[0-9a-f]*:   7e 0f           ld\.w pc,pc\[0x0\]
10800 + *[0-9a-f]*:   79 fc           ld\.w r12,r12\[0x7c\]
10801 + *[0-9a-f]*:   6b 05           ld\.w r5,r5\[0x40\]
10802 + *[0-9a-f]*:   68 f4           ld\.w r4,r4\[0x3c\]
10803 + *[0-9a-f]*:   7c 1e           ld\.w lr,lr\[0x4\]
10804 + *[0-9a-f]*:   64 dd           ld\.w sp,r2\[0x34\]
10805 + *[0-9a-f]*:   62 29           ld\.w r9,r1\[0x8\]
10806 + *[0-9a-f]*:   7a f5           ld\.w r5,sp\[0x3c\]
10807 +
10808 +[0-9a-f]* <ld_sh3>:
10809 + *[0-9a-f]*:   9e 0f           ld\.sh pc,pc\[0x0\]
10810 + *[0-9a-f]*:   98 7c           ld\.sh r12,r12\[0xe\]
10811 + *[0-9a-f]*:   8a 45           ld\.sh r5,r5\[0x8\]
10812 + *[0-9a-f]*:   88 34           ld\.sh r4,r4\[0x6\]
10813 + *[0-9a-f]*:   9c 1e           ld\.sh lr,lr\[0x2\]
10814 + *[0-9a-f]*:   84 44           ld\.sh r4,r2\[0x8\]
10815 + *[0-9a-f]*:   9c 5d           ld\.sh sp,lr\[0xa\]
10816 + *[0-9a-f]*:   96 12           ld\.sh r2,r11\[0x2\]
10817 +
10818 +[0-9a-f]* <ld_uh3>:
10819 + *[0-9a-f]*:   9e 8f           ld\.uh pc,pc\[0x0\]
10820 + *[0-9a-f]*:   98 fc           ld\.uh r12,r12\[0xe\]
10821 + *[0-9a-f]*:   8a c5           ld\.uh r5,r5\[0x8\]
10822 + *[0-9a-f]*:   88 b4           ld\.uh r4,r4\[0x6\]
10823 + *[0-9a-f]*:   9c 9e           ld\.uh lr,lr\[0x2\]
10824 + *[0-9a-f]*:   80 da           ld\.uh r10,r0\[0xa\]
10825 + *[0-9a-f]*:   96 c8           ld\.uh r8,r11\[0x8\]
10826 + *[0-9a-f]*:   84 ea           ld\.uh r10,r2\[0xc\]
10827 +
10828 +[0-9a-f]* <st_w3>:
10829 + *[0-9a-f]*:   9f 0f           st\.w pc\[0x0\],pc
10830 + *[0-9a-f]*:   99 fc           st\.w r12\[0x3c\],r12
10831 + *[0-9a-f]*:   8b 85           st\.w r5\[0x20\],r5
10832 + *[0-9a-f]*:   89 74           st\.w r4\[0x1c\],r4
10833 + *[0-9a-f]*:   9d 1e           st\.w lr\[0x4\],lr
10834 + *[0-9a-f]*:   8f bb           st\.w r7\[0x2c\],r11
10835 + *[0-9a-f]*:   85 66           st\.w r2\[0x18\],r6
10836 + *[0-9a-f]*:   89 39           st\.w r4\[0xc\],r9
10837 +
10838 +[0-9a-f]* <st_h3>:
10839 + *[0-9a-f]*:   be 0f           st\.h pc\[0x0\],pc
10840 + *[0-9a-f]*:   b8 7c           st\.h r12\[0xe\],r12
10841 + *[0-9a-f]*:   aa 45           st\.h r5\[0x8\],r5
10842 + *[0-9a-f]*:   a8 34           st\.h r4\[0x6\],r4
10843 + *[0-9a-f]*:   bc 1e           st\.h lr\[0x2\],lr
10844 + *[0-9a-f]*:   bc 5c           st\.h lr\[0xa\],r12
10845 + *[0-9a-f]*:   ac 20           st\.h r6\[0x4\],r0
10846 + *[0-9a-f]*:   aa 6d           st\.h r5\[0xc\],sp
10847 +
10848 +[0-9a-f]* <st_b3>:
10849 + *[0-9a-f]*:   be 8f           st\.b pc\[0x0\],pc
10850 + *[0-9a-f]*:   b8 fc           st\.b r12\[0x7\],r12
10851 + *[0-9a-f]*:   aa c5           st\.b r5\[0x4\],r5
10852 + *[0-9a-f]*:   a8 b4           st\.b r4\[0x3\],r4
10853 + *[0-9a-f]*:   bc 9e           st\.b lr\[0x1\],lr
10854 + *[0-9a-f]*:   b8 e9           st\.b r12\[0x6\],r9
10855 + *[0-9a-f]*:   a4 be           st\.b r2\[0x3\],lr
10856 + *[0-9a-f]*:   a2 bb           st\.b r1\[0x3\],r11
10857 +
10858 +[0-9a-f]* <ldd>:
10859 + *[0-9a-f]*:   bf 00           ld\.d r0,pc
10860 + *[0-9a-f]*:   b9 0e           ld\.d lr,r12
10861 + *[0-9a-f]*:   ab 08           ld\.d r8,r5
10862 + *[0-9a-f]*:   a9 06           ld\.d r6,r4
10863 + *[0-9a-f]*:   bd 02           ld\.d r2,lr
10864 + *[0-9a-f]*:   af 0e           ld\.d lr,r7
10865 + *[0-9a-f]*:   a9 04           ld\.d r4,r4
10866 + *[0-9a-f]*:   bf 0e           ld\.d lr,pc
10867 +
10868 +[0-9a-f]* <ldd_postinc>:
10869 + *[0-9a-f]*:   bf 01           ld\.d r0,pc\+\+
10870 + *[0-9a-f]*:   b9 0f           ld\.d lr,r12\+\+
10871 + *[0-9a-f]*:   ab 09           ld\.d r8,r5\+\+
10872 + *[0-9a-f]*:   a9 07           ld\.d r6,r4\+\+
10873 + *[0-9a-f]*:   bd 03           ld\.d r2,lr\+\+
10874 + *[0-9a-f]*:   ab 0f           ld\.d lr,r5\+\+
10875 + *[0-9a-f]*:   b7 0d           ld\.d r12,r11\+\+
10876 + *[0-9a-f]*:   b9 03           ld\.d r2,r12\+\+
10877 +
10878 +[0-9a-f]* <ldd_predec>:
10879 + *[0-9a-f]*:   bf 10           ld\.d r0,--pc
10880 + *[0-9a-f]*:   b9 1e           ld\.d lr,--r12
10881 + *[0-9a-f]*:   ab 18           ld\.d r8,--r5
10882 + *[0-9a-f]*:   a9 16           ld\.d r6,--r4
10883 + *[0-9a-f]*:   bd 12           ld\.d r2,--lr
10884 + *[0-9a-f]*:   a1 18           ld\.d r8,--r0
10885 + *[0-9a-f]*:   bf 1a           ld\.d r10,--pc
10886 + *[0-9a-f]*:   a9 12           ld\.d r2,--r4
10887 +
10888 +[0-9a-f]* <std>:
10889 + *[0-9a-f]*:   bf 11           st\.d pc,r0
10890 + *[0-9a-f]*:   b9 1f           st\.d r12,lr
10891 + *[0-9a-f]*:   ab 19           st\.d r5,r8
10892 + *[0-9a-f]*:   a9 17           st\.d r4,r6
10893 + *[0-9a-f]*:   bd 13           st\.d lr,r2
10894 + *[0-9a-f]*:   a1 1d           st\.d r0,r12
10895 + *[0-9a-f]*:   bb 15           st\.d sp,r4
10896 + *[0-9a-f]*:   b9 1d           st\.d r12,r12
10897 +
10898 +[0-9a-f]* <std_postinc>:
10899 + *[0-9a-f]*:   bf 20           st\.d pc\+\+,r0
10900 + *[0-9a-f]*:   b9 2e           st\.d r12\+\+,lr
10901 + *[0-9a-f]*:   ab 28           st\.d r5\+\+,r8
10902 + *[0-9a-f]*:   a9 26           st\.d r4\+\+,r6
10903 + *[0-9a-f]*:   bd 22           st\.d lr\+\+,r2
10904 + *[0-9a-f]*:   bb 26           st\.d sp\+\+,r6
10905 + *[0-9a-f]*:   b5 26           st\.d r10\+\+,r6
10906 + *[0-9a-f]*:   af 22           st\.d r7\+\+,r2
10907 +
10908 +[0-9a-f]* <std_predec>:
10909 + *[0-9a-f]*:   bf 21           st\.d --pc,r0
10910 + *[0-9a-f]*:   b9 2f           st\.d --r12,lr
10911 + *[0-9a-f]*:   ab 29           st\.d --r5,r8
10912 + *[0-9a-f]*:   a9 27           st\.d --r4,r6
10913 + *[0-9a-f]*:   bd 23           st\.d --lr,r2
10914 + *[0-9a-f]*:   a7 27           st\.d --r3,r6
10915 + *[0-9a-f]*:   bd 23           st\.d --lr,r2
10916 + *[0-9a-f]*:   a1 25           st\.d --r0,r4
10917 +
10918 +[0-9a-f]* <mul>:
10919 + *[0-9a-f]*:   bf 3f           mul pc,pc
10920 + *[0-9a-f]*:   b9 3c           mul r12,r12
10921 + *[0-9a-f]*:   ab 35           mul r5,r5
10922 + *[0-9a-f]*:   a9 34           mul r4,r4
10923 + *[0-9a-f]*:   bd 3e           mul lr,lr
10924 + *[0-9a-f]*:   bd 3a           mul r10,lr
10925 + *[0-9a-f]*:   b1 30           mul r0,r8
10926 + *[0-9a-f]*:   ab 38           mul r8,r5
10927 +
10928 +[0-9a-f]* <asr_imm5>:
10929 + *[0-9a-f]*:   a1 4f           asr pc,0x0
10930 + *[0-9a-f]*:   bf 5c           asr r12,0x1f
10931 + *[0-9a-f]*:   b1 45           asr r5,0x10
10932 + *[0-9a-f]*:   af 54           asr r4,0xf
10933 + *[0-9a-f]*:   a1 5e           asr lr,0x1
10934 + *[0-9a-f]*:   b7 56           asr r6,0x17
10935 + *[0-9a-f]*:   b3 46           asr r6,0x12
10936 + *[0-9a-f]*:   a9 45           asr r5,0x8
10937 +
10938 +[0-9a-f]* <lsl_imm5>:
10939 + *[0-9a-f]*:   a1 6f           lsl pc,0x0
10940 + *[0-9a-f]*:   bf 7c           lsl r12,0x1f
10941 + *[0-9a-f]*:   b1 65           lsl r5,0x10
10942 + *[0-9a-f]*:   af 74           lsl r4,0xf
10943 + *[0-9a-f]*:   a1 7e           lsl lr,0x1
10944 + *[0-9a-f]*:   ad 7c           lsl r12,0xd
10945 + *[0-9a-f]*:   b1 66           lsl r6,0x10
10946 + *[0-9a-f]*:   b9 71           lsl r1,0x19
10947 +
10948 +[0-9a-f]* <lsr_imm5>:
10949 + *[0-9a-f]*:   a1 8f           lsr pc,0x0
10950 + *[0-9a-f]*:   bf 9c           lsr r12,0x1f
10951 + *[0-9a-f]*:   b1 85           lsr r5,0x10
10952 + *[0-9a-f]*:   af 94           lsr r4,0xf
10953 + *[0-9a-f]*:   a1 9e           lsr lr,0x1
10954 + *[0-9a-f]*:   a1 90           lsr r0,0x1
10955 + *[0-9a-f]*:   ab 88           lsr r8,0xa
10956 + *[0-9a-f]*:   bb 87           lsr r7,0x1a
10957 +
10958 +[0-9a-f]* <sbr>:
10959 + *[0-9a-f]*:   a1 af           sbr pc,0x0
10960 + *[0-9a-f]*:   bf bc           sbr r12,0x1f
10961 + *[0-9a-f]*:   b1 a5           sbr r5,0x10
10962 + *[0-9a-f]*:   af b4           sbr r4,0xf
10963 + *[0-9a-f]*:   a1 be           sbr lr,0x1
10964 + *[0-9a-f]*:   bf b8           sbr r8,0x1f
10965 + *[0-9a-f]*:   b7 a6           sbr r6,0x16
10966 + *[0-9a-f]*:   b7 b1           sbr r1,0x17
10967 +
10968 +[0-9a-f]* <cbr>:
10969 + *[0-9a-f]*:   a1 cf           cbr pc,0x0
10970 + *[0-9a-f]*:   bf dc           cbr r12,0x1f
10971 + *[0-9a-f]*:   b1 c5           cbr r5,0x10
10972 + *[0-9a-f]*:   af d4           cbr r4,0xf
10973 + *[0-9a-f]*:   a1 de           cbr lr,0x1
10974 + *[0-9a-f]*:   ab cc           cbr r12,0xa
10975 + *[0-9a-f]*:   b7 c7           cbr r7,0x16
10976 + *[0-9a-f]*:   a9 d8           cbr r8,0x9
10977 +
10978 +[0-9a-f]* <brc1>:
10979 + *[0-9a-f]*:   c0 00           breq [0-9a-f]* <.*>
10980 + *[0-9a-f]*:   cf f7           brpl [0-9a-f]* <.*>
10981 + *[0-9a-f]*:   c8 04           brge [0-9a-f]* <.*>
10982 + *[0-9a-f]*:   c7 f3           brcs [0-9a-f]* <.*>
10983 + *[0-9a-f]*:   c0 11           brne [0-9a-f]* <.*>
10984 + *[0-9a-f]*:   c7 33           brcs [0-9a-f]* <.*>
10985 + *[0-9a-f]*:   cf 70           breq [0-9a-f]* <.*>
10986 + *[0-9a-f]*:   c0 60           breq [0-9a-f]* <.*>
10987 +
10988 +[0-9a-f]* <rjmp>:
10989 + *[0-9a-f]*:   c0 08           rjmp [0-9a-f]* <.*>
10990 + *[0-9a-f]*:   cf fb           rjmp [0-9a-f]* <.*>
10991 + *[0-9a-f]*:   c0 0a           rjmp [0-9a-f]* <.*>
10992 + *[0-9a-f]*:   cf f9           rjmp [0-9a-f]* <.*>
10993 + *[0-9a-f]*:   c0 18           rjmp [0-9a-f]* <.*>
10994 + *[0-9a-f]*:   c1 fa           rjmp [0-9a-f]* <.*>
10995 + *[0-9a-f]*:   c0 78           rjmp [0-9a-f]* <.*>
10996 + *[0-9a-f]*:   cf ea           rjmp [0-9a-f]* <.*>
10997 +
10998 +[0-9a-f]* <rcall1>:
10999 + *[0-9a-f]*:   c0 0c           rcall [0-9a-f]* <.*>
11000 + *[0-9a-f]*:   cf ff           rcall [0-9a-f]* <.*>
11001 + *[0-9a-f]*:   c0 0e           rcall [0-9a-f]* <.*>
11002 + *[0-9a-f]*:   cf fd           rcall [0-9a-f]* <.*>
11003 + *[0-9a-f]*:   c0 1c           rcall [0-9a-f]* <.*>
11004 + *[0-9a-f]*:   c6 cc           rcall [0-9a-f]* <.*>
11005 + *[0-9a-f]*:   cf 7e           rcall [0-9a-f]* <.*>
11006 + *[0-9a-f]*:   c1 ae           rcall [0-9a-f]* <.*>
11007 +
11008 +[0-9a-f]* <acall>:
11009 + *[0-9a-f]*:   d0 00           acall 0x0
11010 + *[0-9a-f]*:   df f0           acall 0x3fc
11011 + *[0-9a-f]*:   d8 00           acall 0x200
11012 + *[0-9a-f]*:   d7 f0           acall 0x1fc
11013 + *[0-9a-f]*:   d0 10           acall 0x4
11014 + *[0-9a-f]*:   d5 90           acall 0x164
11015 + *[0-9a-f]*:   d4 c0           acall 0x130
11016 + *[0-9a-f]*:   d2 b0           acall 0xac
11017 +
11018 +[0-9a-f]* <scall>:
11019 + *[0-9a-f]*:   d7 33           scall
11020 + *[0-9a-f]*:   d7 33           scall
11021 + *[0-9a-f]*:   d7 33           scall
11022 + *[0-9a-f]*:   d7 33           scall
11023 + *[0-9a-f]*:   d7 33           scall
11024 + *[0-9a-f]*:   d7 33           scall
11025 + *[0-9a-f]*:   d7 33           scall
11026 + *[0-9a-f]*:   d7 33           scall
11027 +
11028 +[0-9a-f]* <popm>:
11029 + *[0-9a-f]*:   d8 02           popm pc
11030 + *[0-9a-f]*:   dd fa           popm r0-r11,pc,r12=-1
11031 + *[0-9a-f]*:   d4 02           popm lr
11032 + *[0-9a-f]*:   db fa           popm r0-r11,pc,r12=1
11033 + *[0-9a-f]*:   d0 12           popm r0-r3
11034 + *[0-9a-f]*:   d8 e2           popm r4-r10,pc
11035 + *[0-9a-f]*:   d9 1a           popm r0-r3,r11,pc,r12=0
11036 + *[0-9a-f]*:   d7 b2           popm r0-r7,r10-r12,lr
11037 +
11038 +[0-9a-f]* <pushm>:
11039 + *[0-9a-f]*:   d8 01           pushm pc
11040 + *[0-9a-f]*:   df f1           pushm r0-r12,lr-pc
11041 + *[0-9a-f]*:   d8 01           pushm pc
11042 + *[0-9a-f]*:   d7 f1           pushm r0-r12,lr
11043 + *[0-9a-f]*:   d0 11           pushm r0-r3
11044 + *[0-9a-f]*:   dc c1           pushm r8-r10,lr-pc
11045 + *[0-9a-f]*:   d0 91           pushm r0-r3,r10
11046 + *[0-9a-f]*:   d2 41           pushm r8-r9,r12
11047 +
11048 +[0-9a-f]* <popm_n>:
11049 +.*
11050 +.*
11051 +.*
11052 +.*
11053 +.*
11054 +.*
11055 +.*
11056 +.*
11057 +
11058 +[0-9a-f]* <pushm_n>:
11059 +.*
11060 +.*
11061 +.*
11062 +.*
11063 +.*
11064 +.*
11065 +.*
11066 +.*
11067 +
11068 +[0-9a-f]* <csrfcz>:
11069 + *[0-9a-f]*:   d0 03           csrfcz 0x0
11070 + *[0-9a-f]*:   d1 f3           csrfcz 0x1f
11071 + *[0-9a-f]*:   d1 03           csrfcz 0x10
11072 + *[0-9a-f]*:   d0 f3           csrfcz 0xf
11073 + *[0-9a-f]*:   d0 13           csrfcz 0x1
11074 + *[0-9a-f]*:   d0 53           csrfcz 0x5
11075 + *[0-9a-f]*:   d0 d3           csrfcz 0xd
11076 + *[0-9a-f]*:   d1 73           csrfcz 0x17
11077 +
11078 +[0-9a-f]* <ssrf>:
11079 + *[0-9a-f]*:   d2 03           ssrf 0x0
11080 + *[0-9a-f]*:   d3 f3           ssrf 0x1f
11081 + *[0-9a-f]*:   d3 03           ssrf 0x10
11082 + *[0-9a-f]*:   d2 f3           ssrf 0xf
11083 + *[0-9a-f]*:   d2 13           ssrf 0x1
11084 + *[0-9a-f]*:   d3 d3           ssrf 0x1d
11085 + *[0-9a-f]*:   d2 d3           ssrf 0xd
11086 + *[0-9a-f]*:   d2 d3           ssrf 0xd
11087 +
11088 +[0-9a-f]* <csrf>:
11089 + *[0-9a-f]*:   d4 03           csrf 0x0
11090 + *[0-9a-f]*:   d5 f3           csrf 0x1f
11091 + *[0-9a-f]*:   d5 03           csrf 0x10
11092 + *[0-9a-f]*:   d4 f3           csrf 0xf
11093 + *[0-9a-f]*:   d4 13           csrf 0x1
11094 + *[0-9a-f]*:   d4 a3           csrf 0xa
11095 + *[0-9a-f]*:   d4 f3           csrf 0xf
11096 + *[0-9a-f]*:   d4 b3           csrf 0xb
11097 +
11098 +[0-9a-f]* <rete>:
11099 + *[0-9a-f]*:   d6 03           rete
11100 +
11101 +[0-9a-f]* <rets>:
11102 + *[0-9a-f]*:   d6 13           rets
11103 +
11104 +[0-9a-f]* <retd>:
11105 + *[0-9a-f]*:   d6 23           retd
11106 +
11107 +[0-9a-f]* <retj>:
11108 + *[0-9a-f]*:   d6 33           retj
11109 +
11110 +[0-9a-f]* <tlbr>:
11111 + *[0-9a-f]*:   d6 43           tlbr
11112 +
11113 +[0-9a-f]* <tlbs>:
11114 + *[0-9a-f]*:   d6 53           tlbs
11115 +
11116 +[0-9a-f]* <tlbw>:
11117 + *[0-9a-f]*:   d6 63           tlbw
11118 +
11119 +[0-9a-f]* <breakpoint>:
11120 + *[0-9a-f]*:   d6 73           breakpoint
11121 +
11122 +[0-9a-f]* <incjosp>:
11123 + *[0-9a-f]*:   d6 83           incjosp 1
11124 + *[0-9a-f]*:   d6 93           incjosp 2
11125 + *[0-9a-f]*:   d6 a3           incjosp 3
11126 + *[0-9a-f]*:   d6 b3           incjosp 4
11127 + *[0-9a-f]*:   d6 c3           incjosp -4
11128 + *[0-9a-f]*:   d6 d3           incjosp -3
11129 + *[0-9a-f]*:   d6 e3           incjosp -2
11130 + *[0-9a-f]*:   d6 f3           incjosp -1
11131 +
11132 +[0-9a-f]* <nop>:
11133 + *[0-9a-f]*:   d7 03           nop
11134 +
11135 +[0-9a-f]* <popjc>:
11136 + *[0-9a-f]*:   d7 13           popjc
11137 +
11138 +[0-9a-f]* <pushjc>:
11139 + *[0-9a-f]*:   d7 23           pushjc
11140 +
11141 +[0-9a-f]* <add2>:
11142 + *[0-9a-f]*:   fe 0f 00 0f     add pc,pc,pc
11143 + *[0-9a-f]*:   f8 0c 00 3c     add r12,r12,r12<<0x3
11144 + *[0-9a-f]*:   ea 05 00 25     add r5,r5,r5<<0x2
11145 + *[0-9a-f]*:   e8 04 00 14     add r4,r4,r4<<0x1
11146 + *[0-9a-f]*:   fc 0e 00 1e     add lr,lr,lr<<0x1
11147 + *[0-9a-f]*:   f8 00 00 10     add r0,r12,r0<<0x1
11148 + *[0-9a-f]*:   f8 04 00 09     add r9,r12,r4
11149 + *[0-9a-f]*:   f8 07 00 2c     add r12,r12,r7<<0x2
11150 +
11151 +[0-9a-f]* <sub2>:
11152 + *[0-9a-f]*:   fe 0f 01 0f     sub pc,pc,pc
11153 + *[0-9a-f]*:   f8 0c 01 3c     sub r12,r12,r12<<0x3
11154 + *[0-9a-f]*:   ea 05 01 25     sub r5,r5,r5<<0x2
11155 + *[0-9a-f]*:   e8 04 01 14     sub r4,r4,r4<<0x1
11156 + *[0-9a-f]*:   fc 0e 01 1e     sub lr,lr,lr<<0x1
11157 + *[0-9a-f]*:   e6 04 01 0d     sub sp,r3,r4
11158 + *[0-9a-f]*:   ee 03 01 03     sub r3,r7,r3
11159 + *[0-9a-f]*:   f4 0d 01 1d     sub sp,r10,sp<<0x1
11160 +
11161 +[0-9a-f]* <divu>:
11162 + *[0-9a-f]*:   fe 0f 0d 0f     divu pc,pc,pc
11163 + *[0-9a-f]*:   f8 0c 0d 0c     divu r12,r12,r12
11164 + *[0-9a-f]*:   ea 05 0d 05     divu r5,r5,r5
11165 + *[0-9a-f]*:   e8 04 0d 04     divu r4,r4,r4
11166 + *[0-9a-f]*:   fc 0e 0d 0e     divu lr,lr,lr
11167 + *[0-9a-f]*:   e8 0f 0d 0d     divu sp,r4,pc
11168 + *[0-9a-f]*:   ea 0d 0d 05     divu r5,r5,sp
11169 + *[0-9a-f]*:   fa 00 0d 0a     divu r10,sp,r0
11170 +
11171 +[0-9a-f]* <addhh_w>:
11172 + *[0-9a-f]*:   fe 0f 0e 0f     addhh\.w pc,pc:b,pc:b
11173 + *[0-9a-f]*:   f8 0c 0e 3c     addhh\.w r12,r12:t,r12:t
11174 + *[0-9a-f]*:   ea 05 0e 35     addhh\.w r5,r5:t,r5:t
11175 + *[0-9a-f]*:   e8 04 0e 04     addhh\.w r4,r4:b,r4:b
11176 + *[0-9a-f]*:   fc 0e 0e 3e     addhh\.w lr,lr:t,lr:t
11177 + *[0-9a-f]*:   e0 03 0e 00     addhh\.w r0,r0:b,r3:b
11178 + *[0-9a-f]*:   f8 07 0e 2e     addhh\.w lr,r12:t,r7:b
11179 + *[0-9a-f]*:   f4 02 0e 23     addhh\.w r3,r10:t,r2:b
11180 +
11181 +[0-9a-f]* <subhh_w>:
11182 + *[0-9a-f]*:   fe 0f 0f 0f     subhh\.w pc,pc:b,pc:b
11183 + *[0-9a-f]*:   f8 0c 0f 3c     subhh\.w r12,r12:t,r12:t
11184 + *[0-9a-f]*:   ea 05 0f 35     subhh\.w r5,r5:t,r5:t
11185 + *[0-9a-f]*:   e8 04 0f 04     subhh\.w r4,r4:b,r4:b
11186 + *[0-9a-f]*:   fc 0e 0f 3e     subhh\.w lr,lr:t,lr:t
11187 + *[0-9a-f]*:   e2 07 0f 2a     subhh\.w r10,r1:t,r7:b
11188 + *[0-9a-f]*:   f4 0e 0f 3f     subhh\.w pc,r10:t,lr:t
11189 + *[0-9a-f]*:   e0 0c 0f 23     subhh\.w r3,r0:t,r12:b
11190 +
11191 +[0-9a-f]* <adc>:
11192 + *[0-9a-f]*:   fe 0f 00 4f     adc pc,pc,pc
11193 + *[0-9a-f]*:   f8 0c 00 4c     adc r12,r12,r12
11194 + *[0-9a-f]*:   ea 05 00 45     adc r5,r5,r5
11195 + *[0-9a-f]*:   e8 04 00 44     adc r4,r4,r4
11196 + *[0-9a-f]*:   fc 0e 00 4e     adc lr,lr,lr
11197 + *[0-9a-f]*:   e0 07 00 44     adc r4,r0,r7
11198 + *[0-9a-f]*:   e8 03 00 4d     adc sp,r4,r3
11199 + *[0-9a-f]*:   f8 00 00 42     adc r2,r12,r0
11200 +
11201 +[0-9a-f]* <sbc>:
11202 + *[0-9a-f]*:   fe 0f 01 4f     sbc pc,pc,pc
11203 + *[0-9a-f]*:   f8 0c 01 4c     sbc r12,r12,r12
11204 + *[0-9a-f]*:   ea 05 01 45     sbc r5,r5,r5
11205 + *[0-9a-f]*:   e8 04 01 44     sbc r4,r4,r4
11206 + *[0-9a-f]*:   fc 0e 01 4e     sbc lr,lr,lr
11207 + *[0-9a-f]*:   ee 09 01 46     sbc r6,r7,r9
11208 + *[0-9a-f]*:   f0 05 01 40     sbc r0,r8,r5
11209 + *[0-9a-f]*:   e0 04 01 41     sbc r1,r0,r4
11210 +
11211 +[0-9a-f]* <mul_2>:
11212 + *[0-9a-f]*:   fe 0f 02 4f     mul pc,pc,pc
11213 + *[0-9a-f]*:   f8 0c 02 4c     mul r12,r12,r12
11214 + *[0-9a-f]*:   ea 05 02 45     mul r5,r5,r5
11215 + *[0-9a-f]*:   e8 04 02 44     mul r4,r4,r4
11216 + *[0-9a-f]*:   fc 0e 02 4e     mul lr,lr,lr
11217 + *[0-9a-f]*:   e0 00 02 4f     mul pc,r0,r0
11218 + *[0-9a-f]*:   fe 0e 02 48     mul r8,pc,lr
11219 + *[0-9a-f]*:   f8 0f 02 44     mul r4,r12,pc
11220 +
11221 +[0-9a-f]* <mac>:
11222 + *[0-9a-f]*:   fe 0f 03 4f     mac pc,pc,pc
11223 + *[0-9a-f]*:   f8 0c 03 4c     mac r12,r12,r12
11224 + *[0-9a-f]*:   ea 05 03 45     mac r5,r5,r5
11225 + *[0-9a-f]*:   e8 04 03 44     mac r4,r4,r4
11226 + *[0-9a-f]*:   fc 0e 03 4e     mac lr,lr,lr
11227 + *[0-9a-f]*:   e8 00 03 4a     mac r10,r4,r0
11228 + *[0-9a-f]*:   fc 00 03 47     mac r7,lr,r0
11229 + *[0-9a-f]*:   f2 0c 03 42     mac r2,r9,r12
11230 +
11231 +[0-9a-f]* <mulsd>:
11232 + *[0-9a-f]*:   fe 0f 04 4f     muls\.d pc,pc,pc
11233 + *[0-9a-f]*:   f8 0c 04 4c     muls\.d r12,r12,r12
11234 + *[0-9a-f]*:   ea 05 04 45     muls\.d r5,r5,r5
11235 + *[0-9a-f]*:   e8 04 04 44     muls\.d r4,r4,r4
11236 + *[0-9a-f]*:   fc 0e 04 4e     muls\.d lr,lr,lr
11237 + *[0-9a-f]*:   f0 0e 04 42     muls\.d r2,r8,lr
11238 + *[0-9a-f]*:   e0 0b 04 44     muls\.d r4,r0,r11
11239 + *[0-9a-f]*:   fc 06 04 45     muls\.d r5,lr,r6
11240 +
11241 +[0-9a-f]* <macsd>:
11242 + *[0-9a-f]*:   fe 0f 05 40     macs\.d r0,pc,pc
11243 + *[0-9a-f]*:   f8 0c 05 4e     macs\.d lr,r12,r12
11244 + *[0-9a-f]*:   ea 05 05 48     macs\.d r8,r5,r5
11245 + *[0-9a-f]*:   e8 04 05 46     macs\.d r6,r4,r4
11246 + *[0-9a-f]*:   fc 0e 05 42     macs\.d r2,lr,lr
11247 + *[0-9a-f]*:   e2 09 05 48     macs\.d r8,r1,r9
11248 + *[0-9a-f]*:   f0 08 05 4e     macs\.d lr,r8,r8
11249 + *[0-9a-f]*:   e6 0c 05 44     macs\.d r4,r3,r12
11250 +
11251 +[0-9a-f]* <mulud>:
11252 + *[0-9a-f]*:   fe 0f 06 40     mulu\.d r0,pc,pc
11253 + *[0-9a-f]*:   f8 0c 06 4e     mulu\.d lr,r12,r12
11254 + *[0-9a-f]*:   ea 05 06 48     mulu\.d r8,r5,r5
11255 + *[0-9a-f]*:   e8 04 06 46     mulu\.d r6,r4,r4
11256 + *[0-9a-f]*:   fc 0e 06 42     mulu\.d r2,lr,lr
11257 + *[0-9a-f]*:   ea 00 06 46     mulu\.d r6,r5,r0
11258 + *[0-9a-f]*:   ec 01 06 44     mulu\.d r4,r6,r1
11259 + *[0-9a-f]*:   f0 02 06 48     mulu\.d r8,r8,r2
11260 +
11261 +[0-9a-f]* <macud>:
11262 + *[0-9a-f]*:   fe 0f 07 40     macu\.d r0,pc,pc
11263 + *[0-9a-f]*:   f8 0c 07 4e     macu\.d lr,r12,r12
11264 + *[0-9a-f]*:   ea 05 07 48     macu\.d r8,r5,r5
11265 + *[0-9a-f]*:   e8 04 07 46     macu\.d r6,r4,r4
11266 + *[0-9a-f]*:   fc 0e 07 42     macu\.d r2,lr,lr
11267 + *[0-9a-f]*:   fa 0b 07 46     macu\.d r6,sp,r11
11268 + *[0-9a-f]*:   e8 08 07 42     macu\.d r2,r4,r8
11269 + *[0-9a-f]*:   f4 09 07 46     macu\.d r6,r10,r9
11270 +
11271 +[0-9a-f]* <asr_1>:
11272 + *[0-9a-f]*:   fe 0f 08 4f     asr pc,pc,pc
11273 + *[0-9a-f]*:   f8 0c 08 4c     asr r12,r12,r12
11274 + *[0-9a-f]*:   ea 05 08 45     asr r5,r5,r5
11275 + *[0-9a-f]*:   e8 04 08 44     asr r4,r4,r4
11276 + *[0-9a-f]*:   fc 0e 08 4e     asr lr,lr,lr
11277 + *[0-9a-f]*:   ec 0f 08 4f     asr pc,r6,pc
11278 + *[0-9a-f]*:   ec 0c 08 40     asr r0,r6,r12
11279 + *[0-9a-f]*:   fa 00 08 44     asr r4,sp,r0
11280 +
11281 +[0-9a-f]* <lsl_1>:
11282 + *[0-9a-f]*:   fe 0f 09 4f     lsl pc,pc,pc
11283 + *[0-9a-f]*:   f8 0c 09 4c     lsl r12,r12,r12
11284 + *[0-9a-f]*:   ea 05 09 45     lsl r5,r5,r5
11285 + *[0-9a-f]*:   e8 04 09 44     lsl r4,r4,r4
11286 + *[0-9a-f]*:   fc 0e 09 4e     lsl lr,lr,lr
11287 + *[0-9a-f]*:   ea 0e 09 4e     lsl lr,r5,lr
11288 + *[0-9a-f]*:   fe 03 09 45     lsl r5,pc,r3
11289 + *[0-9a-f]*:   fe 09 09 41     lsl r1,pc,r9
11290 +
11291 +[0-9a-f]* <lsr_1>:
11292 + *[0-9a-f]*:   fe 0f 0a 4f     lsr pc,pc,pc
11293 + *[0-9a-f]*:   f8 0c 0a 4c     lsr r12,r12,r12
11294 + *[0-9a-f]*:   ea 05 0a 45     lsr r5,r5,r5
11295 + *[0-9a-f]*:   e8 04 0a 44     lsr r4,r4,r4
11296 + *[0-9a-f]*:   fc 0e 0a 4e     lsr lr,lr,lr
11297 + *[0-9a-f]*:   e8 01 0a 42     lsr r2,r4,r1
11298 + *[0-9a-f]*:   e2 06 0a 45     lsr r5,r1,r6
11299 + *[0-9a-f]*:   ec 07 0a 4d     lsr sp,r6,r7
11300 +
11301 +[0-9a-f]* <xchg>:
11302 + *[0-9a-f]*:   fe 0f 0b 4f     xchg pc,pc,pc
11303 + *[0-9a-f]*:   f8 0c 0b 4c     xchg r12,r12,r12
11304 + *[0-9a-f]*:   ea 05 0b 45     xchg r5,r5,r5
11305 + *[0-9a-f]*:   e8 04 0b 44     xchg r4,r4,r4
11306 + *[0-9a-f]*:   fc 0e 0b 4e     xchg lr,lr,lr
11307 + *[0-9a-f]*:   e8 0d 0b 4e     xchg lr,r4,sp
11308 + *[0-9a-f]*:   ea 0c 0b 41     xchg r1,r5,r12
11309 + *[0-9a-f]*:   f8 00 0b 4e     xchg lr,r12,r0
11310 +
11311 +[0-9a-f]* <max>:
11312 + *[0-9a-f]*:   fe 0f 0c 4f     max pc,pc,pc
11313 + *[0-9a-f]*:   f8 0c 0c 4c     max r12,r12,r12
11314 + *[0-9a-f]*:   ea 05 0c 45     max r5,r5,r5
11315 + *[0-9a-f]*:   e8 04 0c 44     max r4,r4,r4
11316 + *[0-9a-f]*:   fc 0e 0c 4e     max lr,lr,lr
11317 + *[0-9a-f]*:   e4 0d 0c 4e     max lr,r2,sp
11318 + *[0-9a-f]*:   f4 09 0c 44     max r4,r10,r9
11319 + *[0-9a-f]*:   f2 0e 0c 4e     max lr,r9,lr
11320 +
11321 +[0-9a-f]* <min>:
11322 + *[0-9a-f]*:   fe 0f 0d 4f     min pc,pc,pc
11323 + *[0-9a-f]*:   f8 0c 0d 4c     min r12,r12,r12
11324 + *[0-9a-f]*:   ea 05 0d 45     min r5,r5,r5
11325 + *[0-9a-f]*:   e8 04 0d 44     min r4,r4,r4
11326 + *[0-9a-f]*:   fc 0e 0d 4e     min lr,lr,lr
11327 + *[0-9a-f]*:   ee 08 0d 49     min r9,r7,r8
11328 + *[0-9a-f]*:   ea 05 0d 4d     min sp,r5,r5
11329 + *[0-9a-f]*:   e2 04 0d 44     min r4,r1,r4
11330 +
11331 +[0-9a-f]* <addabs>:
11332 + *[0-9a-f]*:   fe 0f 0e 4f     addabs pc,pc,pc
11333 + *[0-9a-f]*:   f8 0c 0e 4c     addabs r12,r12,r12
11334 + *[0-9a-f]*:   ea 05 0e 45     addabs r5,r5,r5
11335 + *[0-9a-f]*:   e8 04 0e 44     addabs r4,r4,r4
11336 + *[0-9a-f]*:   fc 0e 0e 4e     addabs lr,lr,lr
11337 + *[0-9a-f]*:   f4 00 0e 47     addabs r7,r10,r0
11338 + *[0-9a-f]*:   f2 07 0e 49     addabs r9,r9,r7
11339 + *[0-9a-f]*:   f0 0c 0e 42     addabs r2,r8,r12
11340 +
11341 +[0-9a-f]* <mulnhh_w>:
11342 + *[0-9a-f]*:   fe 0f 01 8f     mulnhh\.w pc,pc:b,pc:b
11343 + *[0-9a-f]*:   f8 0c 01 bc     mulnhh\.w r12,r12:t,r12:t
11344 + *[0-9a-f]*:   ea 05 01 b5     mulnhh\.w r5,r5:t,r5:t
11345 + *[0-9a-f]*:   e8 04 01 84     mulnhh\.w r4,r4:b,r4:b
11346 + *[0-9a-f]*:   fc 0e 01 be     mulnhh\.w lr,lr:t,lr:t
11347 + *[0-9a-f]*:   fa 09 01 ab     mulnhh\.w r11,sp:t,r9:b
11348 + *[0-9a-f]*:   e8 0e 01 9d     mulnhh\.w sp,r4:b,lr:t
11349 + *[0-9a-f]*:   e4 0b 01 ac     mulnhh\.w r12,r2:t,r11:b
11350 +
11351 +[0-9a-f]* <mulnwh_d>:
11352 + *[0-9a-f]*:   fe 0f 02 80     mulnwh\.d r0,pc,pc:b
11353 + *[0-9a-f]*:   f8 0c 02 9e     mulnwh\.d lr,r12,r12:t
11354 + *[0-9a-f]*:   ea 05 02 98     mulnwh\.d r8,r5,r5:t
11355 + *[0-9a-f]*:   e8 04 02 86     mulnwh\.d r6,r4,r4:b
11356 + *[0-9a-f]*:   fc 0e 02 92     mulnwh\.d r2,lr,lr:t
11357 + *[0-9a-f]*:   e6 02 02 9e     mulnwh\.d lr,r3,r2:t
11358 + *[0-9a-f]*:   ea 09 02 84     mulnwh\.d r4,r5,r9:b
11359 + *[0-9a-f]*:   e8 04 02 9c     mulnwh\.d r12,r4,r4:t
11360 +
11361 +[0-9a-f]* <machh_w>:
11362 + *[0-9a-f]*:   fe 0f 04 8f     machh\.w pc,pc:b,pc:b
11363 + *[0-9a-f]*:   f8 0c 04 bc     machh\.w r12,r12:t,r12:t
11364 + *[0-9a-f]*:   ea 05 04 b5     machh\.w r5,r5:t,r5:t
11365 + *[0-9a-f]*:   e8 04 04 84     machh\.w r4,r4:b,r4:b
11366 + *[0-9a-f]*:   fc 0e 04 be     machh\.w lr,lr:t,lr:t
11367 + *[0-9a-f]*:   ea 01 04 9e     machh\.w lr,r5:b,r1:t
11368 + *[0-9a-f]*:   ec 07 04 89     machh\.w r9,r6:b,r7:b
11369 + *[0-9a-f]*:   fc 0c 04 a5     machh\.w r5,lr:t,r12:b
11370 +
11371 +[0-9a-f]* <machh_d>:
11372 + *[0-9a-f]*:   fe 0f 05 80     machh\.d r0,pc:b,pc:b
11373 + *[0-9a-f]*:   f8 0c 05 be     machh\.d lr,r12:t,r12:t
11374 + *[0-9a-f]*:   ea 05 05 b8     machh\.d r8,r5:t,r5:t
11375 + *[0-9a-f]*:   e8 04 05 86     machh\.d r6,r4:b,r4:b
11376 + *[0-9a-f]*:   fc 0e 05 b2     machh\.d r2,lr:t,lr:t
11377 + *[0-9a-f]*:   e0 08 05 8a     machh\.d r10,r0:b,r8:b
11378 + *[0-9a-f]*:   e8 05 05 9e     machh\.d lr,r4:b,r5:t
11379 + *[0-9a-f]*:   e0 04 05 98     machh\.d r8,r0:b,r4:t
11380 +
11381 +[0-9a-f]* <macsathh_w>:
11382 + *[0-9a-f]*:   fe 0f 06 8f     macsathh\.w pc,pc:b,pc:b
11383 + *[0-9a-f]*:   f8 0c 06 bc     macsathh\.w r12,r12:t,r12:t
11384 + *[0-9a-f]*:   ea 05 06 b5     macsathh\.w r5,r5:t,r5:t
11385 + *[0-9a-f]*:   e8 04 06 84     macsathh\.w r4,r4:b,r4:b
11386 + *[0-9a-f]*:   fc 0e 06 be     macsathh\.w lr,lr:t,lr:t
11387 + *[0-9a-f]*:   ee 0f 06 b7     macsathh\.w r7,r7:t,pc:t
11388 + *[0-9a-f]*:   e4 04 06 a4     macsathh\.w r4,r2:t,r4:b
11389 + *[0-9a-f]*:   f0 03 06 b4     macsathh\.w r4,r8:t,r3:t
11390 +
11391 +[0-9a-f]* <mulhh_w>:
11392 + *[0-9a-f]*:   fe 0f 07 8f     mulhh\.w pc,pc:b,pc:b
11393 + *[0-9a-f]*:   f8 0c 07 bc     mulhh\.w r12,r12:t,r12:t
11394 + *[0-9a-f]*:   ea 05 07 b5     mulhh\.w r5,r5:t,r5:t
11395 + *[0-9a-f]*:   e8 04 07 84     mulhh\.w r4,r4:b,r4:b
11396 + *[0-9a-f]*:   fc 0e 07 be     mulhh\.w lr,lr:t,lr:t
11397 + *[0-9a-f]*:   e8 09 07 a7     mulhh\.w r7,r4:t,r9:b
11398 + *[0-9a-f]*:   e6 07 07 bf     mulhh\.w pc,r3:t,r7:t
11399 + *[0-9a-f]*:   e8 09 07 9f     mulhh\.w pc,r4:b,r9:t
11400 +
11401 +[0-9a-f]* <mulsathh_h>:
11402 + *[0-9a-f]*:   fe 0f 08 8f     mulsathh\.h pc,pc:b,pc:b
11403 + *[0-9a-f]*:   f8 0c 08 bc     mulsathh\.h r12,r12:t,r12:t
11404 + *[0-9a-f]*:   ea 05 08 b5     mulsathh\.h r5,r5:t,r5:t
11405 + *[0-9a-f]*:   e8 04 08 84     mulsathh\.h r4,r4:b,r4:b
11406 + *[0-9a-f]*:   fc 0e 08 be     mulsathh\.h lr,lr:t,lr:t
11407 + *[0-9a-f]*:   e2 0d 08 83     mulsathh\.h r3,r1:b,sp:b
11408 + *[0-9a-f]*:   fc 0b 08 ab     mulsathh\.h r11,lr:t,r11:b
11409 + *[0-9a-f]*:   f0 0b 08 98     mulsathh\.h r8,r8:b,r11:t
11410 +
11411 +[0-9a-f]* <mulsathh_w>:
11412 + *[0-9a-f]*:   fe 0f 09 8f     mulsathh\.w pc,pc:b,pc:b
11413 + *[0-9a-f]*:   f8 0c 09 bc     mulsathh\.w r12,r12:t,r12:t
11414 + *[0-9a-f]*:   ea 05 09 b5     mulsathh\.w r5,r5:t,r5:t
11415 + *[0-9a-f]*:   e8 04 09 84     mulsathh\.w r4,r4:b,r4:b
11416 + *[0-9a-f]*:   fc 0e 09 be     mulsathh\.w lr,lr:t,lr:t
11417 + *[0-9a-f]*:   f6 06 09 ae     mulsathh\.w lr,r11:t,r6:b
11418 + *[0-9a-f]*:   ec 07 09 96     mulsathh\.w r6,r6:b,r7:t
11419 + *[0-9a-f]*:   e4 03 09 8a     mulsathh\.w r10,r2:b,r3:b
11420 +
11421 +[0-9a-f]* <mulsatrndhh_h>:
11422 + *[0-9a-f]*:   fe 0f 0a 8f     mulsatrndhh\.h pc,pc:b,pc:b
11423 + *[0-9a-f]*:   f8 0c 0a bc     mulsatrndhh\.h r12,r12:t,r12:t
11424 + *[0-9a-f]*:   ea 05 0a b5     mulsatrndhh\.h r5,r5:t,r5:t
11425 + *[0-9a-f]*:   e8 04 0a 84     mulsatrndhh\.h r4,r4:b,r4:b
11426 + *[0-9a-f]*:   fc 0e 0a be     mulsatrndhh\.h lr,lr:t,lr:t
11427 + *[0-9a-f]*:   ec 09 0a 8b     mulsatrndhh\.h r11,r6:b,r9:b
11428 + *[0-9a-f]*:   e6 08 0a 9b     mulsatrndhh\.h r11,r3:b,r8:t
11429 + *[0-9a-f]*:   fa 07 0a b5     mulsatrndhh\.h r5,sp:t,r7:t
11430 +
11431 +[0-9a-f]* <mulsatrndwh_w>:
11432 + *[0-9a-f]*:   fe 0f 0b 8f     mulsatrndwh\.w pc,pc,pc:b
11433 + *[0-9a-f]*:   f8 0c 0b 9c     mulsatrndwh\.w r12,r12,r12:t
11434 + *[0-9a-f]*:   ea 05 0b 95     mulsatrndwh\.w r5,r5,r5:t
11435 + *[0-9a-f]*:   e8 04 0b 84     mulsatrndwh\.w r4,r4,r4:b
11436 + *[0-9a-f]*:   fc 0e 0b 9e     mulsatrndwh\.w lr,lr,lr:t
11437 + *[0-9a-f]*:   f8 00 0b 85     mulsatrndwh\.w r5,r12,r0:b
11438 + *[0-9a-f]*:   f4 0f 0b 87     mulsatrndwh\.w r7,r10,pc:b
11439 + *[0-9a-f]*:   f0 05 0b 9a     mulsatrndwh\.w r10,r8,r5:t
11440 +
11441 +[0-9a-f]* <macwh_d>:
11442 + *[0-9a-f]*:   fe 0f 0c 80     macwh\.d r0,pc,pc:b
11443 + *[0-9a-f]*:   f8 0c 0c 9e     macwh\.d lr,r12,r12:t
11444 + *[0-9a-f]*:   ea 05 0c 98     macwh\.d r8,r5,r5:t
11445 + *[0-9a-f]*:   e8 04 0c 86     macwh\.d r6,r4,r4:b
11446 + *[0-9a-f]*:   fc 0e 0c 92     macwh\.d r2,lr,lr:t
11447 + *[0-9a-f]*:   f4 0c 0c 94     macwh\.d r4,r10,r12:t
11448 + *[0-9a-f]*:   ee 0d 0c 84     macwh\.d r4,r7,sp:b
11449 + *[0-9a-f]*:   f2 0b 0c 8e     macwh\.d lr,r9,r11:b
11450 +
11451 +[0-9a-f]* <mulwh_d>:
11452 + *[0-9a-f]*:   fe 0f 0d 80     mulwh\.d r0,pc,pc:b
11453 + *[0-9a-f]*:   f8 0c 0d 9e     mulwh\.d lr,r12,r12:t
11454 + *[0-9a-f]*:   ea 05 0d 98     mulwh\.d r8,r5,r5:t
11455 + *[0-9a-f]*:   e8 04 0d 86     mulwh\.d r6,r4,r4:b
11456 + *[0-9a-f]*:   fc 0e 0d 92     mulwh\.d r2,lr,lr:t
11457 + *[0-9a-f]*:   ea 01 0d 8c     mulwh\.d r12,r5,r1:b
11458 + *[0-9a-f]*:   e2 03 0d 90     mulwh\.d r0,r1,r3:t
11459 + *[0-9a-f]*:   f2 02 0d 80     mulwh\.d r0,r9,r2:b
11460 +
11461 +[0-9a-f]* <mulsatwh_w>:
11462 + *[0-9a-f]*:   fe 0f 0e 8f     mulsatwh\.w pc,pc,pc:b
11463 + *[0-9a-f]*:   f8 0c 0e 9c     mulsatwh\.w r12,r12,r12:t
11464 + *[0-9a-f]*:   ea 05 0e 95     mulsatwh\.w r5,r5,r5:t
11465 + *[0-9a-f]*:   e8 04 0e 84     mulsatwh\.w r4,r4,r4:b
11466 + *[0-9a-f]*:   fc 0e 0e 9e     mulsatwh\.w lr,lr,lr:t
11467 + *[0-9a-f]*:   fe 0a 0e 9b     mulsatwh\.w r11,pc,r10:t
11468 + *[0-9a-f]*:   f8 09 0e 9d     mulsatwh\.w sp,r12,r9:t
11469 + *[0-9a-f]*:   e6 02 0e 90     mulsatwh\.w r0,r3,r2:t
11470 +
11471 +[0-9a-f]* <ldw7>:
11472 + *[0-9a-f]*:   fe 0f 0f 8f     ld\.w pc,pc\[pc:b<<2\]
11473 + *[0-9a-f]*:   f8 0c 0f bc     ld\.w r12,r12\[r12:t<<2\]
11474 + *[0-9a-f]*:   ea 05 0f a5     ld\.w r5,r5\[r5:u<<2\]
11475 + *[0-9a-f]*:   e8 04 0f 94     ld\.w r4,r4\[r4:l<<2\]
11476 + *[0-9a-f]*:   fc 0e 0f 9e     ld\.w lr,lr\[lr:l<<2\]
11477 + *[0-9a-f]*:   f4 06 0f 99     ld\.w r9,r10\[r6:l<<2\]
11478 + *[0-9a-f]*:   f4 0a 0f 82     ld\.w r2,r10\[r10:b<<2\]
11479 + *[0-9a-f]*:   ea 0f 0f 8b     ld\.w r11,r5\[pc:b<<2\]
11480 +
11481 +[0-9a-f]* <satadd_w>:
11482 + *[0-9a-f]*:   fe 0f 00 cf     satadd\.w pc,pc,pc
11483 + *[0-9a-f]*:   f8 0c 00 cc     satadd\.w r12,r12,r12
11484 + *[0-9a-f]*:   ea 05 00 c5     satadd\.w r5,r5,r5
11485 + *[0-9a-f]*:   e8 04 00 c4     satadd\.w r4,r4,r4
11486 + *[0-9a-f]*:   fc 0e 00 ce     satadd\.w lr,lr,lr
11487 + *[0-9a-f]*:   f0 0b 00 c4     satadd\.w r4,r8,r11
11488 + *[0-9a-f]*:   f8 06 00 c3     satadd\.w r3,r12,r6
11489 + *[0-9a-f]*:   fc 09 00 c3     satadd\.w r3,lr,r9
11490 +
11491 +[0-9a-f]* <satsub_w1>:
11492 + *[0-9a-f]*:   fe 0f 01 cf     satsub\.w pc,pc,pc
11493 + *[0-9a-f]*:   f8 0c 01 cc     satsub\.w r12,r12,r12
11494 + *[0-9a-f]*:   ea 05 01 c5     satsub\.w r5,r5,r5
11495 + *[0-9a-f]*:   e8 04 01 c4     satsub\.w r4,r4,r4
11496 + *[0-9a-f]*:   fc 0e 01 ce     satsub\.w lr,lr,lr
11497 + *[0-9a-f]*:   fa 00 01 c8     satsub\.w r8,sp,r0
11498 + *[0-9a-f]*:   f0 04 01 c9     satsub\.w r9,r8,r4
11499 + *[0-9a-f]*:   fc 02 01 cf     satsub\.w pc,lr,r2
11500 +
11501 +[0-9a-f]* <satadd_h>:
11502 + *[0-9a-f]*:   fe 0f 02 cf     satadd\.h pc,pc,pc
11503 + *[0-9a-f]*:   f8 0c 02 cc     satadd\.h r12,r12,r12
11504 + *[0-9a-f]*:   ea 05 02 c5     satadd\.h r5,r5,r5
11505 + *[0-9a-f]*:   e8 04 02 c4     satadd\.h r4,r4,r4
11506 + *[0-9a-f]*:   fc 0e 02 ce     satadd\.h lr,lr,lr
11507 + *[0-9a-f]*:   e6 09 02 c7     satadd\.h r7,r3,r9
11508 + *[0-9a-f]*:   e0 02 02 c1     satadd\.h r1,r0,r2
11509 + *[0-9a-f]*:   e8 0e 02 c1     satadd\.h r1,r4,lr
11510 +
11511 +[0-9a-f]* <satsub_h>:
11512 + *[0-9a-f]*:   fe 0f 03 cf     satsub\.h pc,pc,pc
11513 + *[0-9a-f]*:   f8 0c 03 cc     satsub\.h r12,r12,r12
11514 + *[0-9a-f]*:   ea 05 03 c5     satsub\.h r5,r5,r5
11515 + *[0-9a-f]*:   e8 04 03 c4     satsub\.h r4,r4,r4
11516 + *[0-9a-f]*:   fc 0e 03 ce     satsub\.h lr,lr,lr
11517 + *[0-9a-f]*:   fc 03 03 ce     satsub\.h lr,lr,r3
11518 + *[0-9a-f]*:   ec 05 03 cb     satsub\.h r11,r6,r5
11519 + *[0-9a-f]*:   fa 00 03 c3     satsub\.h r3,sp,r0
11520 +
11521 +[0-9a-f]* <mul3>:
11522 + *[0-9a-f]*:   fe 0f 10 00     mul pc,pc,0
11523 + *[0-9a-f]*:   f8 0c 10 ff     mul r12,r12,-1
11524 + *[0-9a-f]*:   ea 05 10 80     mul r5,r5,-128
11525 + *[0-9a-f]*:   e8 04 10 7f     mul r4,r4,127
11526 + *[0-9a-f]*:   fc 0e 10 01     mul lr,lr,1
11527 + *[0-9a-f]*:   e4 0c 10 f9     mul r12,r2,-7
11528 + *[0-9a-f]*:   fe 01 10 5f     mul r1,pc,95
11529 + *[0-9a-f]*:   ec 04 10 13     mul r4,r6,19
11530 +
11531 +[0-9a-f]* <rsub2>:
11532 + *[0-9a-f]*:   fe 0f 11 00     rsub pc,pc,0
11533 + *[0-9a-f]*:   f8 0c 11 ff     rsub r12,r12,-1
11534 + *[0-9a-f]*:   ea 05 11 80     rsub r5,r5,-128
11535 + *[0-9a-f]*:   e8 04 11 7f     rsub r4,r4,127
11536 + *[0-9a-f]*:   fc 0e 11 01     rsub lr,lr,1
11537 + *[0-9a-f]*:   fc 09 11 60     rsub r9,lr,96
11538 + *[0-9a-f]*:   e2 0b 11 38     rsub r11,r1,56
11539 + *[0-9a-f]*:   ee 00 11 a9     rsub r0,r7,-87
11540 +
11541 +[0-9a-f]* <clz>:
11542 + *[0-9a-f]*:   fe 0f 12 00     clz pc,pc
11543 + *[0-9a-f]*:   f8 0c 12 00     clz r12,r12
11544 + *[0-9a-f]*:   ea 05 12 00     clz r5,r5
11545 + *[0-9a-f]*:   e8 04 12 00     clz r4,r4
11546 + *[0-9a-f]*:   fc 0e 12 00     clz lr,lr
11547 + *[0-9a-f]*:   e6 02 12 00     clz r2,r3
11548 + *[0-9a-f]*:   f6 05 12 00     clz r5,r11
11549 + *[0-9a-f]*:   e6 0f 12 00     clz pc,r3
11550 +
11551 +[0-9a-f]* <cpc1>:
11552 + *[0-9a-f]*:   fe 0f 13 00     cpc pc,pc
11553 + *[0-9a-f]*:   f8 0c 13 00     cpc r12,r12
11554 + *[0-9a-f]*:   ea 05 13 00     cpc r5,r5
11555 + *[0-9a-f]*:   e8 04 13 00     cpc r4,r4
11556 + *[0-9a-f]*:   fc 0e 13 00     cpc lr,lr
11557 + *[0-9a-f]*:   e8 0f 13 00     cpc pc,r4
11558 + *[0-9a-f]*:   f2 05 13 00     cpc r5,r9
11559 + *[0-9a-f]*:   ee 06 13 00     cpc r6,r7
11560 +
11561 +[0-9a-f]* <asr3>:
11562 + *[0-9a-f]*:   fe 0f 14 00     asr pc,pc,0x0
11563 + *[0-9a-f]*:   f8 0c 14 1f     asr r12,r12,0x1f
11564 + *[0-9a-f]*:   ea 05 14 10     asr r5,r5,0x10
11565 + *[0-9a-f]*:   e8 04 14 0f     asr r4,r4,0xf
11566 + *[0-9a-f]*:   fc 0e 14 01     asr lr,lr,0x1
11567 + *[0-9a-f]*:   f6 04 14 13     asr r4,r11,0x13
11568 + *[0-9a-f]*:   fe 0d 14 1a     asr sp,pc,0x1a
11569 + *[0-9a-f]*:   fa 0b 14 08     asr r11,sp,0x8
11570 +
11571 +[0-9a-f]* <lsl3>:
11572 + *[0-9a-f]*:   fe 0f 15 00     lsl pc,pc,0x0
11573 + *[0-9a-f]*:   f8 0c 15 1f     lsl r12,r12,0x1f
11574 + *[0-9a-f]*:   ea 05 15 10     lsl r5,r5,0x10
11575 + *[0-9a-f]*:   e8 04 15 0f     lsl r4,r4,0xf
11576 + *[0-9a-f]*:   fc 0e 15 01     lsl lr,lr,0x1
11577 + *[0-9a-f]*:   f4 08 15 11     lsl r8,r10,0x11
11578 + *[0-9a-f]*:   fc 02 15 03     lsl r2,lr,0x3
11579 + *[0-9a-f]*:   f6 0e 15 0e     lsl lr,r11,0xe
11580 +
11581 +[0-9a-f]* <lsr3>:
11582 + *[0-9a-f]*:   fe 0f 16 00     lsr pc,pc,0x0
11583 + *[0-9a-f]*:   f8 0c 16 1f     lsr r12,r12,0x1f
11584 + *[0-9a-f]*:   ea 05 16 10     lsr r5,r5,0x10
11585 + *[0-9a-f]*:   e8 04 16 0f     lsr r4,r4,0xf
11586 + *[0-9a-f]*:   fc 0e 16 01     lsr lr,lr,0x1
11587 + *[0-9a-f]*:   e6 04 16 1f     lsr r4,r3,0x1f
11588 + *[0-9a-f]*:   f2 0f 16 0e     lsr pc,r9,0xe
11589 + *[0-9a-f]*:   e0 03 16 06     lsr r3,r0,0x6
11590 +
11591 +[0-9a-f]* <movc1>:
11592 + *[0-9a-f]*:   fe 0f 17 00     moveq pc,pc
11593 + *[0-9a-f]*:   f8 0c 17 f0     moval r12,r12
11594 + *[0-9a-f]*:   ea 05 17 80     movls r5,r5
11595 + *[0-9a-f]*:   e8 04 17 70     movpl r4,r4
11596 + *[0-9a-f]*:   fc 0e 17 10     movne lr,lr
11597 + *[0-9a-f]*:   f6 0f 17 10     movne pc,r11
11598 + *[0-9a-f]*:   e4 0a 17 60     movmi r10,r2
11599 + *[0-9a-f]*:   f8 08 17 80     movls r8,r12
11600 +
11601 +[0-9a-f]* <padd_h>:
11602 + *[0-9a-f]*:   fe 0f 20 0f     padd\.h pc,pc,pc
11603 + *[0-9a-f]*:   f8 0c 20 0c     padd\.h r12,r12,r12
11604 + *[0-9a-f]*:   ea 05 20 05     padd\.h r5,r5,r5
11605 + *[0-9a-f]*:   e8 04 20 04     padd\.h r4,r4,r4
11606 + *[0-9a-f]*:   fc 0e 20 0e     padd\.h lr,lr,lr
11607 + *[0-9a-f]*:   e4 07 20 08     padd\.h r8,r2,r7
11608 + *[0-9a-f]*:   e0 03 20 00     padd\.h r0,r0,r3
11609 + *[0-9a-f]*:   f6 06 20 0d     padd\.h sp,r11,r6
11610 +
11611 +[0-9a-f]* <psub_h>:
11612 + *[0-9a-f]*:   fe 0f 20 1f     psub\.h pc,pc,pc
11613 + *[0-9a-f]*:   f8 0c 20 1c     psub\.h r12,r12,r12
11614 + *[0-9a-f]*:   ea 05 20 15     psub\.h r5,r5,r5
11615 + *[0-9a-f]*:   e8 04 20 14     psub\.h r4,r4,r4
11616 + *[0-9a-f]*:   fc 0e 20 1e     psub\.h lr,lr,lr
11617 + *[0-9a-f]*:   ec 08 20 1e     psub\.h lr,r6,r8
11618 + *[0-9a-f]*:   e2 0d 20 10     psub\.h r0,r1,sp
11619 + *[0-9a-f]*:   fe 0d 20 1f     psub\.h pc,pc,sp
11620 +
11621 +[0-9a-f]* <paddx_h>:
11622 + *[0-9a-f]*:   fe 0f 20 2f     paddx\.h pc,pc,pc
11623 + *[0-9a-f]*:   f8 0c 20 2c     paddx\.h r12,r12,r12
11624 + *[0-9a-f]*:   ea 05 20 25     paddx\.h r5,r5,r5
11625 + *[0-9a-f]*:   e8 04 20 24     paddx\.h r4,r4,r4
11626 + *[0-9a-f]*:   fc 0e 20 2e     paddx\.h lr,lr,lr
11627 + *[0-9a-f]*:   fe 01 20 2f     paddx\.h pc,pc,r1
11628 + *[0-9a-f]*:   e8 05 20 2a     paddx\.h r10,r4,r5
11629 + *[0-9a-f]*:   fe 02 20 25     paddx\.h r5,pc,r2
11630 +
11631 +[0-9a-f]* <psubx_h>:
11632 + *[0-9a-f]*:   fe 0f 20 3f     psubx\.h pc,pc,pc
11633 + *[0-9a-f]*:   f8 0c 20 3c     psubx\.h r12,r12,r12
11634 + *[0-9a-f]*:   ea 05 20 35     psubx\.h r5,r5,r5
11635 + *[0-9a-f]*:   e8 04 20 34     psubx\.h r4,r4,r4
11636 + *[0-9a-f]*:   fc 0e 20 3e     psubx\.h lr,lr,lr
11637 + *[0-9a-f]*:   f8 05 20 35     psubx\.h r5,r12,r5
11638 + *[0-9a-f]*:   f0 03 20 33     psubx\.h r3,r8,r3
11639 + *[0-9a-f]*:   e4 03 20 35     psubx\.h r5,r2,r3
11640 +
11641 +[0-9a-f]* <padds_sh>:
11642 + *[0-9a-f]*:   fe 0f 20 4f     padds\.sh pc,pc,pc
11643 + *[0-9a-f]*:   f8 0c 20 4c     padds\.sh r12,r12,r12
11644 + *[0-9a-f]*:   ea 05 20 45     padds\.sh r5,r5,r5
11645 + *[0-9a-f]*:   e8 04 20 44     padds\.sh r4,r4,r4
11646 + *[0-9a-f]*:   fc 0e 20 4e     padds\.sh lr,lr,lr
11647 + *[0-9a-f]*:   fc 02 20 49     padds\.sh r9,lr,r2
11648 + *[0-9a-f]*:   f0 01 20 46     padds\.sh r6,r8,r1
11649 + *[0-9a-f]*:   e8 0a 20 46     padds\.sh r6,r4,r10
11650 +
11651 +[0-9a-f]* <psubs_sh>:
11652 + *[0-9a-f]*:   fe 0f 20 5f     psubs\.sh pc,pc,pc
11653 + *[0-9a-f]*:   f8 0c 20 5c     psubs\.sh r12,r12,r12
11654 + *[0-9a-f]*:   ea 05 20 55     psubs\.sh r5,r5,r5
11655 + *[0-9a-f]*:   e8 04 20 54     psubs\.sh r4,r4,r4
11656 + *[0-9a-f]*:   fc 0e 20 5e     psubs\.sh lr,lr,lr
11657 + *[0-9a-f]*:   fc 0b 20 56     psubs\.sh r6,lr,r11
11658 + *[0-9a-f]*:   f8 04 20 52     psubs\.sh r2,r12,r4
11659 + *[0-9a-f]*:   f2 00 20 50     psubs\.sh r0,r9,r0
11660 +
11661 +[0-9a-f]* <paddxs_sh>:
11662 + *[0-9a-f]*:   fe 0f 20 6f     paddxs\.sh pc,pc,pc
11663 + *[0-9a-f]*:   f8 0c 20 6c     paddxs\.sh r12,r12,r12
11664 + *[0-9a-f]*:   ea 05 20 65     paddxs\.sh r5,r5,r5
11665 + *[0-9a-f]*:   e8 04 20 64     paddxs\.sh r4,r4,r4
11666 + *[0-9a-f]*:   fc 0e 20 6e     paddxs\.sh lr,lr,lr
11667 + *[0-9a-f]*:   e6 09 20 60     paddxs\.sh r0,r3,r9
11668 + *[0-9a-f]*:   f4 0b 20 6f     paddxs\.sh pc,r10,r11
11669 + *[0-9a-f]*:   f4 0f 20 6f     paddxs\.sh pc,r10,pc
11670 +
11671 +[0-9a-f]* <psubxs_sh>:
11672 + *[0-9a-f]*:   fe 0f 20 7f     psubxs\.sh pc,pc,pc
11673 + *[0-9a-f]*:   f8 0c 20 7c     psubxs\.sh r12,r12,r12
11674 + *[0-9a-f]*:   ea 05 20 75     psubxs\.sh r5,r5,r5
11675 + *[0-9a-f]*:   e8 04 20 74     psubxs\.sh r4,r4,r4
11676 + *[0-9a-f]*:   fc 0e 20 7e     psubxs\.sh lr,lr,lr
11677 + *[0-9a-f]*:   e8 04 20 77     psubxs\.sh r7,r4,r4
11678 + *[0-9a-f]*:   f0 03 20 77     psubxs\.sh r7,r8,r3
11679 + *[0-9a-f]*:   ec 05 20 7f     psubxs\.sh pc,r6,r5
11680 +
11681 +[0-9a-f]* <padds_uh>:
11682 + *[0-9a-f]*:   fe 0f 20 8f     padds\.uh pc,pc,pc
11683 + *[0-9a-f]*:   f8 0c 20 8c     padds\.uh r12,r12,r12
11684 + *[0-9a-f]*:   ea 05 20 85     padds\.uh r5,r5,r5
11685 + *[0-9a-f]*:   e8 04 20 84     padds\.uh r4,r4,r4
11686 + *[0-9a-f]*:   fc 0e 20 8e     padds\.uh lr,lr,lr
11687 + *[0-9a-f]*:   f6 07 20 8c     padds\.uh r12,r11,r7
11688 + *[0-9a-f]*:   f0 0e 20 87     padds\.uh r7,r8,lr
11689 + *[0-9a-f]*:   f2 07 20 86     padds\.uh r6,r9,r7
11690 +
11691 +[0-9a-f]* <psubs_uh>:
11692 + *[0-9a-f]*:   fe 0f 20 9f     psubs\.uh pc,pc,pc
11693 + *[0-9a-f]*:   f8 0c 20 9c     psubs\.uh r12,r12,r12
11694 + *[0-9a-f]*:   ea 05 20 95     psubs\.uh r5,r5,r5
11695 + *[0-9a-f]*:   e8 04 20 94     psubs\.uh r4,r4,r4
11696 + *[0-9a-f]*:   fc 0e 20 9e     psubs\.uh lr,lr,lr
11697 + *[0-9a-f]*:   f4 06 20 9e     psubs\.uh lr,r10,r6
11698 + *[0-9a-f]*:   e4 0f 20 9d     psubs\.uh sp,r2,pc
11699 + *[0-9a-f]*:   f2 02 20 92     psubs\.uh r2,r9,r2
11700 +
11701 +[0-9a-f]* <paddxs_uh>:
11702 + *[0-9a-f]*:   fe 0f 20 af     paddxs\.uh pc,pc,pc
11703 + *[0-9a-f]*:   f8 0c 20 ac     paddxs\.uh r12,r12,r12
11704 + *[0-9a-f]*:   ea 05 20 a5     paddxs\.uh r5,r5,r5
11705 + *[0-9a-f]*:   e8 04 20 a4     paddxs\.uh r4,r4,r4
11706 + *[0-9a-f]*:   fc 0e 20 ae     paddxs\.uh lr,lr,lr
11707 + *[0-9a-f]*:   f2 05 20 a7     paddxs\.uh r7,r9,r5
11708 + *[0-9a-f]*:   e2 04 20 a9     paddxs\.uh r9,r1,r4
11709 + *[0-9a-f]*:   e4 03 20 a5     paddxs\.uh r5,r2,r3
11710 +
11711 +[0-9a-f]* <psubxs_uh>:
11712 + *[0-9a-f]*:   fe 0f 20 bf     psubxs\.uh pc,pc,pc
11713 + *[0-9a-f]*:   f8 0c 20 bc     psubxs\.uh r12,r12,r12
11714 + *[0-9a-f]*:   ea 05 20 b5     psubxs\.uh r5,r5,r5
11715 + *[0-9a-f]*:   e8 04 20 b4     psubxs\.uh r4,r4,r4
11716 + *[0-9a-f]*:   fc 0e 20 be     psubxs\.uh lr,lr,lr
11717 + *[0-9a-f]*:   ea 0d 20 bd     psubxs\.uh sp,r5,sp
11718 + *[0-9a-f]*:   ec 06 20 bd     psubxs\.uh sp,r6,r6
11719 + *[0-9a-f]*:   f6 08 20 b3     psubxs\.uh r3,r11,r8
11720 +
11721 +[0-9a-f]* <paddh_sh>:
11722 + *[0-9a-f]*:   fe 0f 20 cf     paddh\.sh pc,pc,pc
11723 + *[0-9a-f]*:   f8 0c 20 cc     paddh\.sh r12,r12,r12
11724 + *[0-9a-f]*:   ea 05 20 c5     paddh\.sh r5,r5,r5
11725 + *[0-9a-f]*:   e8 04 20 c4     paddh\.sh r4,r4,r4
11726 + *[0-9a-f]*:   fc 0e 20 ce     paddh\.sh lr,lr,lr
11727 + *[0-9a-f]*:   fa 03 20 cc     paddh\.sh r12,sp,r3
11728 + *[0-9a-f]*:   ea 03 20 cf     paddh\.sh pc,r5,r3
11729 + *[0-9a-f]*:   f0 0d 20 c8     paddh\.sh r8,r8,sp
11730 +
11731 +[0-9a-f]* <psubh_sh>:
11732 + *[0-9a-f]*:   fe 0f 20 df     psubh\.sh pc,pc,pc
11733 + *[0-9a-f]*:   f8 0c 20 dc     psubh\.sh r12,r12,r12
11734 + *[0-9a-f]*:   ea 05 20 d5     psubh\.sh r5,r5,r5
11735 + *[0-9a-f]*:   e8 04 20 d4     psubh\.sh r4,r4,r4
11736 + *[0-9a-f]*:   fc 0e 20 de     psubh\.sh lr,lr,lr
11737 + *[0-9a-f]*:   ea 08 20 d1     psubh\.sh r1,r5,r8
11738 + *[0-9a-f]*:   e6 06 20 d7     psubh\.sh r7,r3,r6
11739 + *[0-9a-f]*:   e6 03 20 d4     psubh\.sh r4,r3,r3
11740 +
11741 +[0-9a-f]* <paddxh_sh>:
11742 + *[0-9a-f]*:   fe 0f 20 ef     paddxh\.sh pc,pc,pc
11743 + *[0-9a-f]*:   f8 0c 20 ec     paddxh\.sh r12,r12,r12
11744 + *[0-9a-f]*:   ea 05 20 e5     paddxh\.sh r5,r5,r5
11745 + *[0-9a-f]*:   e8 04 20 e4     paddxh\.sh r4,r4,r4
11746 + *[0-9a-f]*:   fc 0e 20 ee     paddxh\.sh lr,lr,lr
11747 + *[0-9a-f]*:   e0 04 20 e6     paddxh\.sh r6,r0,r4
11748 + *[0-9a-f]*:   f0 09 20 e9     paddxh\.sh r9,r8,r9
11749 + *[0-9a-f]*:   e0 0d 20 e3     paddxh\.sh r3,r0,sp
11750 +
11751 +[0-9a-f]* <psubxh_sh>:
11752 + *[0-9a-f]*:   fe 0f 20 ff     psubxh\.sh pc,pc,pc
11753 + *[0-9a-f]*:   f8 0c 20 fc     psubxh\.sh r12,r12,r12
11754 + *[0-9a-f]*:   ea 05 20 f5     psubxh\.sh r5,r5,r5
11755 + *[0-9a-f]*:   e8 04 20 f4     psubxh\.sh r4,r4,r4
11756 + *[0-9a-f]*:   fc 0e 20 fe     psubxh\.sh lr,lr,lr
11757 + *[0-9a-f]*:   fe 0c 20 f4     psubxh\.sh r4,pc,r12
11758 + *[0-9a-f]*:   e8 06 20 f8     psubxh\.sh r8,r4,r6
11759 + *[0-9a-f]*:   f2 04 20 fc     psubxh\.sh r12,r9,r4
11760 +
11761 +[0-9a-f]* <paddsub_h>:
11762 + *[0-9a-f]*:   fe 0f 21 0f     paddsub\.h pc,pc:b,pc:b
11763 + *[0-9a-f]*:   f8 0c 21 3c     paddsub\.h r12,r12:t,r12:t
11764 + *[0-9a-f]*:   ea 05 21 35     paddsub\.h r5,r5:t,r5:t
11765 + *[0-9a-f]*:   e8 04 21 04     paddsub\.h r4,r4:b,r4:b
11766 + *[0-9a-f]*:   fc 0e 21 3e     paddsub\.h lr,lr:t,lr:t
11767 + *[0-9a-f]*:   e4 0e 21 25     paddsub\.h r5,r2:t,lr:b
11768 + *[0-9a-f]*:   e2 08 21 07     paddsub\.h r7,r1:b,r8:b
11769 + *[0-9a-f]*:   f4 05 21 36     paddsub\.h r6,r10:t,r5:t
11770 +
11771 +[0-9a-f]* <psubadd_h>:
11772 + *[0-9a-f]*:   fe 0f 21 4f     psubadd\.h pc,pc:b,pc:b
11773 + *[0-9a-f]*:   f8 0c 21 7c     psubadd\.h r12,r12:t,r12:t
11774 + *[0-9a-f]*:   ea 05 21 75     psubadd\.h r5,r5:t,r5:t
11775 + *[0-9a-f]*:   e8 04 21 44     psubadd\.h r4,r4:b,r4:b
11776 + *[0-9a-f]*:   fc 0e 21 7e     psubadd\.h lr,lr:t,lr:t
11777 + *[0-9a-f]*:   f6 08 21 79     psubadd\.h r9,r11:t,r8:t
11778 + *[0-9a-f]*:   ee 0e 21 7a     psubadd\.h r10,r7:t,lr:t
11779 + *[0-9a-f]*:   fe 0f 21 66     psubadd\.h r6,pc:t,pc:b
11780 +
11781 +[0-9a-f]* <paddsubs_sh>:
11782 + *[0-9a-f]*:   fe 0f 21 8f     paddsubs\.sh pc,pc:b,pc:b
11783 + *[0-9a-f]*:   f8 0c 21 bc     paddsubs\.sh r12,r12:t,r12:t
11784 + *[0-9a-f]*:   ea 05 21 b5     paddsubs\.sh r5,r5:t,r5:t
11785 + *[0-9a-f]*:   e8 04 21 84     paddsubs\.sh r4,r4:b,r4:b
11786 + *[0-9a-f]*:   fc 0e 21 be     paddsubs\.sh lr,lr:t,lr:t
11787 + *[0-9a-f]*:   fc 00 21 a0     paddsubs\.sh r0,lr:t,r0:b
11788 + *[0-9a-f]*:   e4 04 21 b9     paddsubs\.sh r9,r2:t,r4:t
11789 + *[0-9a-f]*:   f2 0d 21 bc     paddsubs\.sh r12,r9:t,sp:t
11790 +
11791 +[0-9a-f]* <psubadds_sh>:
11792 + *[0-9a-f]*:   fe 0f 21 cf     psubadds\.sh pc,pc:b,pc:b
11793 + *[0-9a-f]*:   f8 0c 21 fc     psubadds\.sh r12,r12:t,r12:t
11794 + *[0-9a-f]*:   ea 05 21 f5     psubadds\.sh r5,r5:t,r5:t
11795 + *[0-9a-f]*:   e8 04 21 c4     psubadds\.sh r4,r4:b,r4:b
11796 + *[0-9a-f]*:   fc 0e 21 fe     psubadds\.sh lr,lr:t,lr:t
11797 + *[0-9a-f]*:   fc 01 21 df     psubadds\.sh pc,lr:b,r1:t
11798 + *[0-9a-f]*:   e6 0c 21 cb     psubadds\.sh r11,r3:b,r12:b
11799 + *[0-9a-f]*:   e4 08 21 fa     psubadds\.sh r10,r2:t,r8:t
11800 +
11801 +[0-9a-f]* <paddsubs_uh>:
11802 + *[0-9a-f]*:   fe 0f 22 0f     paddsubs\.uh pc,pc:b,pc:b
11803 + *[0-9a-f]*:   f8 0c 22 3c     paddsubs\.uh r12,r12:t,r12:t
11804 + *[0-9a-f]*:   ea 05 22 35     paddsubs\.uh r5,r5:t,r5:t
11805 + *[0-9a-f]*:   e8 04 22 04     paddsubs\.uh r4,r4:b,r4:b
11806 + *[0-9a-f]*:   fc 0e 22 3e     paddsubs\.uh lr,lr:t,lr:t
11807 + *[0-9a-f]*:   e4 03 22 09     paddsubs\.uh r9,r2:b,r3:b
11808 + *[0-9a-f]*:   fa 07 22 1d     paddsubs\.uh sp,sp:b,r7:t
11809 + *[0-9a-f]*:   e0 0a 22 1e     paddsubs\.uh lr,r0:b,r10:t
11810 +
11811 +[0-9a-f]* <psubadds_uh>:
11812 + *[0-9a-f]*:   fe 0f 22 4f     psubadds\.uh pc,pc:b,pc:b
11813 + *[0-9a-f]*:   f8 0c 22 7c     psubadds\.uh r12,r12:t,r12:t
11814 + *[0-9a-f]*:   ea 05 22 75     psubadds\.uh r5,r5:t,r5:t
11815 + *[0-9a-f]*:   e8 04 22 44     psubadds\.uh r4,r4:b,r4:b
11816 + *[0-9a-f]*:   fc 0e 22 7e     psubadds\.uh lr,lr:t,lr:t
11817 + *[0-9a-f]*:   f2 0f 22 7c     psubadds\.uh r12,r9:t,pc:t
11818 + *[0-9a-f]*:   ec 08 22 48     psubadds\.uh r8,r6:b,r8:b
11819 + *[0-9a-f]*:   f0 04 22 48     psubadds\.uh r8,r8:b,r4:b
11820 +
11821 +[0-9a-f]* <paddsubh_sh>:
11822 + *[0-9a-f]*:   fe 0f 22 8f     paddsubh\.sh pc,pc:b,pc:b
11823 + *[0-9a-f]*:   f8 0c 22 bc     paddsubh\.sh r12,r12:t,r12:t
11824 + *[0-9a-f]*:   ea 05 22 b5     paddsubh\.sh r5,r5:t,r5:t
11825 + *[0-9a-f]*:   e8 04 22 84     paddsubh\.sh r4,r4:b,r4:b
11826 + *[0-9a-f]*:   fc 0e 22 be     paddsubh\.sh lr,lr:t,lr:t
11827 + *[0-9a-f]*:   f2 09 22 a8     paddsubh\.sh r8,r9:t,r9:b
11828 + *[0-9a-f]*:   fa 01 22 b0     paddsubh\.sh r0,sp:t,r1:t
11829 + *[0-9a-f]*:   e2 00 22 93     paddsubh\.sh r3,r1:b,r0:t
11830 +
11831 +[0-9a-f]* <psubaddh_sh>:
11832 + *[0-9a-f]*:   fe 0f 22 cf     psubaddh\.sh pc,pc:b,pc:b
11833 + *[0-9a-f]*:   f8 0c 22 fc     psubaddh\.sh r12,r12:t,r12:t
11834 + *[0-9a-f]*:   ea 05 22 f5     psubaddh\.sh r5,r5:t,r5:t
11835 + *[0-9a-f]*:   e8 04 22 c4     psubaddh\.sh r4,r4:b,r4:b
11836 + *[0-9a-f]*:   fc 0e 22 fe     psubaddh\.sh lr,lr:t,lr:t
11837 + *[0-9a-f]*:   e6 0a 22 e7     psubaddh\.sh r7,r3:t,r10:b
11838 + *[0-9a-f]*:   e4 01 22 f7     psubaddh\.sh r7,r2:t,r1:t
11839 + *[0-9a-f]*:   e6 06 22 cb     psubaddh\.sh r11,r3:b,r6:b
11840 +
11841 +[0-9a-f]* <padd_b>:
11842 + *[0-9a-f]*:   fe 0f 23 0f     padd\.b pc,pc,pc
11843 + *[0-9a-f]*:   f8 0c 23 0c     padd\.b r12,r12,r12
11844 + *[0-9a-f]*:   ea 05 23 05     padd\.b r5,r5,r5
11845 + *[0-9a-f]*:   e8 04 23 04     padd\.b r4,r4,r4
11846 + *[0-9a-f]*:   fc 0e 23 0e     padd\.b lr,lr,lr
11847 + *[0-9a-f]*:   ec 0f 23 02     padd\.b r2,r6,pc
11848 + *[0-9a-f]*:   f2 0c 23 08     padd\.b r8,r9,r12
11849 + *[0-9a-f]*:   f8 03 23 05     padd\.b r5,r12,r3
11850 +
11851 +[0-9a-f]* <psub_b>:
11852 + *[0-9a-f]*:   fe 0f 23 1f     psub\.b pc,pc,pc
11853 + *[0-9a-f]*:   f8 0c 23 1c     psub\.b r12,r12,r12
11854 + *[0-9a-f]*:   ea 05 23 15     psub\.b r5,r5,r5
11855 + *[0-9a-f]*:   e8 04 23 14     psub\.b r4,r4,r4
11856 + *[0-9a-f]*:   fc 0e 23 1e     psub\.b lr,lr,lr
11857 + *[0-9a-f]*:   f8 0f 23 10     psub\.b r0,r12,pc
11858 + *[0-9a-f]*:   fa 0a 23 17     psub\.b r7,sp,r10
11859 + *[0-9a-f]*:   fa 0c 23 15     psub\.b r5,sp,r12
11860 +
11861 +[0-9a-f]* <padds_sb>:
11862 + *[0-9a-f]*:   fe 0f 23 2f     padds\.sb pc,pc,pc
11863 + *[0-9a-f]*:   f8 0c 23 2c     padds\.sb r12,r12,r12
11864 + *[0-9a-f]*:   ea 05 23 25     padds\.sb r5,r5,r5
11865 + *[0-9a-f]*:   e8 04 23 24     padds\.sb r4,r4,r4
11866 + *[0-9a-f]*:   fc 0e 23 2e     padds\.sb lr,lr,lr
11867 + *[0-9a-f]*:   f6 04 23 2d     padds\.sb sp,r11,r4
11868 + *[0-9a-f]*:   f4 0b 23 2b     padds\.sb r11,r10,r11
11869 + *[0-9a-f]*:   f8 06 23 25     padds\.sb r5,r12,r6
11870 +
11871 +[0-9a-f]* <psubs_sb>:
11872 + *[0-9a-f]*:   fe 0f 23 3f     psubs\.sb pc,pc,pc
11873 + *[0-9a-f]*:   f8 0c 23 3c     psubs\.sb r12,r12,r12
11874 + *[0-9a-f]*:   ea 05 23 35     psubs\.sb r5,r5,r5
11875 + *[0-9a-f]*:   e8 04 23 34     psubs\.sb r4,r4,r4
11876 + *[0-9a-f]*:   fc 0e 23 3e     psubs\.sb lr,lr,lr
11877 + *[0-9a-f]*:   ec 08 23 37     psubs\.sb r7,r6,r8
11878 + *[0-9a-f]*:   f4 09 23 3c     psubs\.sb r12,r10,r9
11879 + *[0-9a-f]*:   f6 00 23 3f     psubs\.sb pc,r11,r0
11880 +
11881 +[0-9a-f]* <padds_ub>:
11882 + *[0-9a-f]*:   fe 0f 23 4f     padds\.ub pc,pc,pc
11883 + *[0-9a-f]*:   f8 0c 23 4c     padds\.ub r12,r12,r12
11884 + *[0-9a-f]*:   ea 05 23 45     padds\.ub r5,r5,r5
11885 + *[0-9a-f]*:   e8 04 23 44     padds\.ub r4,r4,r4
11886 + *[0-9a-f]*:   fc 0e 23 4e     padds\.ub lr,lr,lr
11887 + *[0-9a-f]*:   e4 0b 23 43     padds\.ub r3,r2,r11
11888 + *[0-9a-f]*:   f0 01 23 4a     padds\.ub r10,r8,r1
11889 + *[0-9a-f]*:   f0 0a 23 4b     padds\.ub r11,r8,r10
11890 +
11891 +[0-9a-f]* <psubs_ub>:
11892 + *[0-9a-f]*:   fe 0f 23 5f     psubs\.ub pc,pc,pc
11893 + *[0-9a-f]*:   f8 0c 23 5c     psubs\.ub r12,r12,r12
11894 + *[0-9a-f]*:   ea 05 23 55     psubs\.ub r5,r5,r5
11895 + *[0-9a-f]*:   e8 04 23 54     psubs\.ub r4,r4,r4
11896 + *[0-9a-f]*:   fc 0e 23 5e     psubs\.ub lr,lr,lr
11897 + *[0-9a-f]*:   e4 07 23 50     psubs\.ub r0,r2,r7
11898 + *[0-9a-f]*:   ea 03 23 5e     psubs\.ub lr,r5,r3
11899 + *[0-9a-f]*:   ee 09 23 56     psubs\.ub r6,r7,r9
11900 +
11901 +[0-9a-f]* <paddh_ub>:
11902 + *[0-9a-f]*:   fe 0f 23 6f     paddh\.ub pc,pc,pc
11903 + *[0-9a-f]*:   f8 0c 23 6c     paddh\.ub r12,r12,r12
11904 + *[0-9a-f]*:   ea 05 23 65     paddh\.ub r5,r5,r5
11905 + *[0-9a-f]*:   e8 04 23 64     paddh\.ub r4,r4,r4
11906 + *[0-9a-f]*:   fc 0e 23 6e     paddh\.ub lr,lr,lr
11907 + *[0-9a-f]*:   e2 00 23 6e     paddh\.ub lr,r1,r0
11908 + *[0-9a-f]*:   ee 07 23 62     paddh\.ub r2,r7,r7
11909 + *[0-9a-f]*:   e2 02 23 62     paddh\.ub r2,r1,r2
11910 +
11911 +[0-9a-f]* <psubh_ub>:
11912 + *[0-9a-f]*:   fe 0f 23 7f     psubh\.ub pc,pc,pc
11913 + *[0-9a-f]*:   f8 0c 23 7c     psubh\.ub r12,r12,r12
11914 + *[0-9a-f]*:   ea 05 23 75     psubh\.ub r5,r5,r5
11915 + *[0-9a-f]*:   e8 04 23 74     psubh\.ub r4,r4,r4
11916 + *[0-9a-f]*:   fc 0e 23 7e     psubh\.ub lr,lr,lr
11917 + *[0-9a-f]*:   e2 06 23 70     psubh\.ub r0,r1,r6
11918 + *[0-9a-f]*:   fc 0a 23 74     psubh\.ub r4,lr,r10
11919 + *[0-9a-f]*:   f0 01 23 79     psubh\.ub r9,r8,r1
11920 +
11921 +[0-9a-f]* <pmax_ub>:
11922 + *[0-9a-f]*:   fe 0f 23 8f     pmax\.ub pc,pc,pc
11923 + *[0-9a-f]*:   f8 0c 23 8c     pmax\.ub r12,r12,r12
11924 + *[0-9a-f]*:   ea 05 23 85     pmax\.ub r5,r5,r5
11925 + *[0-9a-f]*:   e8 04 23 84     pmax\.ub r4,r4,r4
11926 + *[0-9a-f]*:   fc 0e 23 8e     pmax\.ub lr,lr,lr
11927 + *[0-9a-f]*:   e4 0b 23 8f     pmax\.ub pc,r2,r11
11928 + *[0-9a-f]*:   e2 01 23 8c     pmax\.ub r12,r1,r1
11929 + *[0-9a-f]*:   e4 00 23 85     pmax\.ub r5,r2,r0
11930 +
11931 +[0-9a-f]* <pmax_sh>:
11932 + *[0-9a-f]*:   fe 0f 23 9f     pmax\.sh pc,pc,pc
11933 + *[0-9a-f]*:   f8 0c 23 9c     pmax\.sh r12,r12,r12
11934 + *[0-9a-f]*:   ea 05 23 95     pmax\.sh r5,r5,r5
11935 + *[0-9a-f]*:   e8 04 23 94     pmax\.sh r4,r4,r4
11936 + *[0-9a-f]*:   fc 0e 23 9e     pmax\.sh lr,lr,lr
11937 + *[0-9a-f]*:   ec 0c 23 9e     pmax\.sh lr,r6,r12
11938 + *[0-9a-f]*:   fe 05 23 92     pmax\.sh r2,pc,r5
11939 + *[0-9a-f]*:   e4 07 23 9f     pmax\.sh pc,r2,r7
11940 +
11941 +[0-9a-f]* <pmin_ub>:
11942 + *[0-9a-f]*:   fe 0f 23 af     pmin\.ub pc,pc,pc
11943 + *[0-9a-f]*:   f8 0c 23 ac     pmin\.ub r12,r12,r12
11944 + *[0-9a-f]*:   ea 05 23 a5     pmin\.ub r5,r5,r5
11945 + *[0-9a-f]*:   e8 04 23 a4     pmin\.ub r4,r4,r4
11946 + *[0-9a-f]*:   fc 0e 23 ae     pmin\.ub lr,lr,lr
11947 + *[0-9a-f]*:   e2 05 23 a8     pmin\.ub r8,r1,r5
11948 + *[0-9a-f]*:   f0 03 23 a1     pmin\.ub r1,r8,r3
11949 + *[0-9a-f]*:   e4 07 23 a0     pmin\.ub r0,r2,r7
11950 +
11951 +[0-9a-f]* <pmin_sh>:
11952 + *[0-9a-f]*:   fe 0f 23 bf     pmin\.sh pc,pc,pc
11953 + *[0-9a-f]*:   f8 0c 23 bc     pmin\.sh r12,r12,r12
11954 + *[0-9a-f]*:   ea 05 23 b5     pmin\.sh r5,r5,r5
11955 + *[0-9a-f]*:   e8 04 23 b4     pmin\.sh r4,r4,r4
11956 + *[0-9a-f]*:   fc 0e 23 be     pmin\.sh lr,lr,lr
11957 + *[0-9a-f]*:   e8 0a 23 b8     pmin\.sh r8,r4,r10
11958 + *[0-9a-f]*:   f4 0c 23 be     pmin\.sh lr,r10,r12
11959 + *[0-9a-f]*:   ec 02 23 b2     pmin\.sh r2,r6,r2
11960 +
11961 +[0-9a-f]* <pavg_ub>:
11962 + *[0-9a-f]*:   fe 0f 23 cf     pavg\.ub pc,pc,pc
11963 + *[0-9a-f]*:   f8 0c 23 cc     pavg\.ub r12,r12,r12
11964 + *[0-9a-f]*:   ea 05 23 c5     pavg\.ub r5,r5,r5
11965 + *[0-9a-f]*:   e8 04 23 c4     pavg\.ub r4,r4,r4
11966 + *[0-9a-f]*:   fc 0e 23 ce     pavg\.ub lr,lr,lr
11967 + *[0-9a-f]*:   e2 06 23 c0     pavg\.ub r0,r1,r6
11968 + *[0-9a-f]*:   e6 06 23 c8     pavg\.ub r8,r3,r6
11969 + *[0-9a-f]*:   f8 0a 23 cf     pavg\.ub pc,r12,r10
11970 +
11971 +[0-9a-f]* <pavg_sh>:
11972 + *[0-9a-f]*:   fe 0f 23 df     pavg\.sh pc,pc,pc
11973 + *[0-9a-f]*:   f8 0c 23 dc     pavg\.sh r12,r12,r12
11974 + *[0-9a-f]*:   ea 05 23 d5     pavg\.sh r5,r5,r5
11975 + *[0-9a-f]*:   e8 04 23 d4     pavg\.sh r4,r4,r4
11976 + *[0-9a-f]*:   fc 0e 23 de     pavg\.sh lr,lr,lr
11977 + *[0-9a-f]*:   fe 0d 23 d9     pavg\.sh r9,pc,sp
11978 + *[0-9a-f]*:   fa 03 23 df     pavg\.sh pc,sp,r3
11979 + *[0-9a-f]*:   e2 09 23 d6     pavg\.sh r6,r1,r9
11980 +
11981 +[0-9a-f]* <pabs_sb>:
11982 + *[0-9a-f]*:   e0 0f 23 ef     pabs\.sb pc,pc
11983 + *[0-9a-f]*:   e0 0c 23 ec     pabs\.sb r12,r12
11984 + *[0-9a-f]*:   e0 05 23 e5     pabs\.sb r5,r5
11985 + *[0-9a-f]*:   e0 04 23 e4     pabs\.sb r4,r4
11986 + *[0-9a-f]*:   e0 0e 23 ee     pabs\.sb lr,lr
11987 + *[0-9a-f]*:   e0 06 23 eb     pabs\.sb r11,r6
11988 + *[0-9a-f]*:   e0 09 23 ee     pabs\.sb lr,r9
11989 + *[0-9a-f]*:   e0 07 23 ed     pabs\.sb sp,r7
11990 +
11991 +[0-9a-f]* <pabs_sh>:
11992 + *[0-9a-f]*:   e0 0f 23 ff     pabs\.sh pc,pc
11993 + *[0-9a-f]*:   e0 0c 23 fc     pabs\.sh r12,r12
11994 + *[0-9a-f]*:   e0 05 23 f5     pabs\.sh r5,r5
11995 + *[0-9a-f]*:   e0 04 23 f4     pabs\.sh r4,r4
11996 + *[0-9a-f]*:   e0 0e 23 fe     pabs\.sh lr,lr
11997 + *[0-9a-f]*:   e0 03 23 ff     pabs\.sh pc,r3
11998 + *[0-9a-f]*:   e0 07 23 f5     pabs\.sh r5,r7
11999 + *[0-9a-f]*:   e0 00 23 f4     pabs\.sh r4,r0
12000 +
12001 +[0-9a-f]* <psad>:
12002 + *[0-9a-f]*:   fe 0f 24 0f     psad pc,pc,pc
12003 + *[0-9a-f]*:   f8 0c 24 0c     psad r12,r12,r12
12004 + *[0-9a-f]*:   ea 05 24 05     psad r5,r5,r5
12005 + *[0-9a-f]*:   e8 04 24 04     psad r4,r4,r4
12006 + *[0-9a-f]*:   fc 0e 24 0e     psad lr,lr,lr
12007 + *[0-9a-f]*:   f6 0b 24 09     psad r9,r11,r11
12008 + *[0-9a-f]*:   e8 0d 24 0e     psad lr,r4,sp
12009 + *[0-9a-f]*:   e8 05 24 0e     psad lr,r4,r5
12010 +
12011 +[0-9a-f]* <pasr_b>:
12012 + *[0-9a-f]*:   fe 00 24 1f     pasr\.b pc,pc,0x0
12013 + *[0-9a-f]*:   f8 07 24 1c     pasr\.b r12,r12,0x7
12014 + *[0-9a-f]*:   ea 04 24 15     pasr\.b r5,r5,0x4
12015 + *[0-9a-f]*:   e8 03 24 14     pasr\.b r4,r4,0x3
12016 + *[0-9a-f]*:   fc 01 24 1e     pasr\.b lr,lr,0x1
12017 + *[0-9a-f]*:   ee 01 24 1f     pasr\.b pc,r7,0x1
12018 + *[0-9a-f]*:   fc 06 24 1d     pasr\.b sp,lr,0x6
12019 + *[0-9a-f]*:   e6 02 24 1d     pasr\.b sp,r3,0x2
12020 +
12021 +[0-9a-f]* <plsl_b>:
12022 + *[0-9a-f]*:   fe 00 24 2f     plsl\.b pc,pc,0x0
12023 + *[0-9a-f]*:   f8 07 24 2c     plsl\.b r12,r12,0x7
12024 + *[0-9a-f]*:   ea 04 24 25     plsl\.b r5,r5,0x4
12025 + *[0-9a-f]*:   e8 03 24 24     plsl\.b r4,r4,0x3
12026 + *[0-9a-f]*:   fc 01 24 2e     plsl\.b lr,lr,0x1
12027 + *[0-9a-f]*:   f6 04 24 22     plsl\.b r2,r11,0x4
12028 + *[0-9a-f]*:   ea 07 24 28     plsl\.b r8,r5,0x7
12029 + *[0-9a-f]*:   e0 02 24 2f     plsl\.b pc,r0,0x2
12030 +
12031 +[0-9a-f]* <plsr_b>:
12032 + *[0-9a-f]*:   fe 00 24 3f     plsr\.b pc,pc,0x0
12033 + *[0-9a-f]*:   f8 07 24 3c     plsr\.b r12,r12,0x7
12034 + *[0-9a-f]*:   ea 04 24 35     plsr\.b r5,r5,0x4
12035 + *[0-9a-f]*:   e8 03 24 34     plsr\.b r4,r4,0x3
12036 + *[0-9a-f]*:   fc 01 24 3e     plsr\.b lr,lr,0x1
12037 + *[0-9a-f]*:   e2 02 24 3c     plsr\.b r12,r1,0x2
12038 + *[0-9a-f]*:   fe 07 24 36     plsr\.b r6,pc,0x7
12039 + *[0-9a-f]*:   f6 02 24 3c     plsr\.b r12,r11,0x2
12040 +
12041 +[0-9a-f]* <pasr_h>:
12042 + *[0-9a-f]*:   fe 00 24 4f     pasr\.h pc,pc,0x0
12043 + *[0-9a-f]*:   f8 0f 24 4c     pasr\.h r12,r12,0xf
12044 + *[0-9a-f]*:   ea 08 24 45     pasr\.h r5,r5,0x8
12045 + *[0-9a-f]*:   e8 07 24 44     pasr\.h r4,r4,0x7
12046 + *[0-9a-f]*:   fc 01 24 4e     pasr\.h lr,lr,0x1
12047 + *[0-9a-f]*:   f6 0a 24 40     pasr\.h r0,r11,0xa
12048 + *[0-9a-f]*:   ec 08 24 44     pasr\.h r4,r6,0x8
12049 + *[0-9a-f]*:   e4 04 24 46     pasr\.h r6,r2,0x4
12050 +
12051 +[0-9a-f]* <plsl_h>:
12052 + *[0-9a-f]*:   fe 00 24 5f     plsl\.h pc,pc,0x0
12053 + *[0-9a-f]*:   f8 0f 24 5c     plsl\.h r12,r12,0xf
12054 + *[0-9a-f]*:   ea 08 24 55     plsl\.h r5,r5,0x8
12055 + *[0-9a-f]*:   e8 07 24 54     plsl\.h r4,r4,0x7
12056 + *[0-9a-f]*:   fc 01 24 5e     plsl\.h lr,lr,0x1
12057 + *[0-9a-f]*:   f4 09 24 55     plsl\.h r5,r10,0x9
12058 + *[0-9a-f]*:   fc 08 24 5d     plsl\.h sp,lr,0x8
12059 + *[0-9a-f]*:   fc 07 24 50     plsl\.h r0,lr,0x7
12060 +
12061 +[0-9a-f]* <plsr_h>:
12062 + *[0-9a-f]*:   fe 00 24 6f     plsr\.h pc,pc,0x0
12063 + *[0-9a-f]*:   f8 0f 24 6c     plsr\.h r12,r12,0xf
12064 + *[0-9a-f]*:   ea 08 24 65     plsr\.h r5,r5,0x8
12065 + *[0-9a-f]*:   e8 07 24 64     plsr\.h r4,r4,0x7
12066 + *[0-9a-f]*:   fc 01 24 6e     plsr\.h lr,lr,0x1
12067 + *[0-9a-f]*:   e0 0f 24 6b     plsr\.h r11,r0,0xf
12068 + *[0-9a-f]*:   e6 03 24 6e     plsr\.h lr,r3,0x3
12069 + *[0-9a-f]*:   fc 0a 24 68     plsr\.h r8,lr,0xa
12070 +
12071 +[0-9a-f]* <packw_sh>:
12072 + *[0-9a-f]*:   fe 0f 24 7f     packw\.sh pc,pc,pc
12073 + *[0-9a-f]*:   f8 0c 24 7c     packw\.sh r12,r12,r12
12074 + *[0-9a-f]*:   ea 05 24 75     packw\.sh r5,r5,r5
12075 + *[0-9a-f]*:   e8 04 24 74     packw\.sh r4,r4,r4
12076 + *[0-9a-f]*:   fc 0e 24 7e     packw\.sh lr,lr,lr
12077 + *[0-9a-f]*:   f6 0a 24 7d     packw\.sh sp,r11,r10
12078 + *[0-9a-f]*:   e4 0c 24 78     packw\.sh r8,r2,r12
12079 + *[0-9a-f]*:   e2 05 24 78     packw\.sh r8,r1,r5
12080 +
12081 +[0-9a-f]* <punpckub_h>:
12082 + *[0-9a-f]*:   fe 00 24 8f     punpckub\.h pc,pc:b
12083 + *[0-9a-f]*:   f8 00 24 9c     punpckub\.h r12,r12:t
12084 + *[0-9a-f]*:   ea 00 24 95     punpckub\.h r5,r5:t
12085 + *[0-9a-f]*:   e8 00 24 84     punpckub\.h r4,r4:b
12086 + *[0-9a-f]*:   fc 00 24 9e     punpckub\.h lr,lr:t
12087 + *[0-9a-f]*:   e2 00 24 96     punpckub\.h r6,r1:t
12088 + *[0-9a-f]*:   ea 00 24 8e     punpckub\.h lr,r5:b
12089 + *[0-9a-f]*:   e4 00 24 9e     punpckub\.h lr,r2:t
12090 +
12091 +[0-9a-f]* <punpcksb_h>:
12092 + *[0-9a-f]*:   fe 00 24 af     punpcksb\.h pc,pc:b
12093 + *[0-9a-f]*:   f8 00 24 bc     punpcksb\.h r12,r12:t
12094 + *[0-9a-f]*:   ea 00 24 b5     punpcksb\.h r5,r5:t
12095 + *[0-9a-f]*:   e8 00 24 a4     punpcksb\.h r4,r4:b
12096 + *[0-9a-f]*:   fc 00 24 be     punpcksb\.h lr,lr:t
12097 + *[0-9a-f]*:   ee 00 24 b4     punpcksb\.h r4,r7:t
12098 + *[0-9a-f]*:   fc 00 24 a6     punpcksb\.h r6,lr:b
12099 + *[0-9a-f]*:   f8 00 24 bc     punpcksb\.h r12,r12:t
12100 +
12101 +[0-9a-f]* <packsh_ub>:
12102 + *[0-9a-f]*:   fe 0f 24 cf     packsh\.ub pc,pc,pc
12103 + *[0-9a-f]*:   f8 0c 24 cc     packsh\.ub r12,r12,r12
12104 + *[0-9a-f]*:   ea 05 24 c5     packsh\.ub r5,r5,r5
12105 + *[0-9a-f]*:   e8 04 24 c4     packsh\.ub r4,r4,r4
12106 + *[0-9a-f]*:   fc 0e 24 ce     packsh\.ub lr,lr,lr
12107 + *[0-9a-f]*:   ec 03 24 c3     packsh\.ub r3,r6,r3
12108 + *[0-9a-f]*:   e0 03 24 c8     packsh\.ub r8,r0,r3
12109 + *[0-9a-f]*:   e6 0e 24 c9     packsh\.ub r9,r3,lr
12110 +
12111 +[0-9a-f]* <packsh_sb>:
12112 + *[0-9a-f]*:   fe 0f 24 df     packsh\.sb pc,pc,pc
12113 + *[0-9a-f]*:   f8 0c 24 dc     packsh\.sb r12,r12,r12
12114 + *[0-9a-f]*:   ea 05 24 d5     packsh\.sb r5,r5,r5
12115 + *[0-9a-f]*:   e8 04 24 d4     packsh\.sb r4,r4,r4
12116 + *[0-9a-f]*:   fc 0e 24 de     packsh\.sb lr,lr,lr
12117 + *[0-9a-f]*:   f0 01 24 d6     packsh\.sb r6,r8,r1
12118 + *[0-9a-f]*:   f2 08 24 de     packsh\.sb lr,r9,r8
12119 + *[0-9a-f]*:   ec 06 24 dd     packsh\.sb sp,r6,r6
12120 +
12121 +[0-9a-f]* <andl>:
12122 + *[0-9a-f]*:   e0 1f 00 00     andl pc,0x0
12123 + *[0-9a-f]*:   e0 1c ff ff     andl r12,0xffff
12124 + *[0-9a-f]*:   e0 15 80 00     andl r5,0x8000
12125 + *[0-9a-f]*:   e0 14 7f ff     andl r4,0x7fff
12126 + *[0-9a-f]*:   e0 1e 00 01     andl lr,0x1
12127 + *[0-9a-f]*:   e0 1f 5a 58     andl pc,0x5a58
12128 + *[0-9a-f]*:   e0 18 b8 9e     andl r8,0xb89e
12129 + *[0-9a-f]*:   e0 17 35 97     andl r7,0x3597
12130 +
12131 +[0-9a-f]* <andl_coh>:
12132 + *[0-9a-f]*:   e2 1f 00 00     andl pc,0x0,COH
12133 + *[0-9a-f]*:   e2 1c ff ff     andl r12,0xffff,COH
12134 + *[0-9a-f]*:   e2 15 80 00     andl r5,0x8000,COH
12135 + *[0-9a-f]*:   e2 14 7f ff     andl r4,0x7fff,COH
12136 + *[0-9a-f]*:   e2 1e 00 01     andl lr,0x1,COH
12137 + *[0-9a-f]*:   e2 16 58 e1     andl r6,0x58e1,COH
12138 + *[0-9a-f]*:   e2 10 9e cd     andl r0,0x9ecd,COH
12139 + *[0-9a-f]*:   e2 14 bd c4     andl r4,0xbdc4,COH
12140 +
12141 +[0-9a-f]* <andh>:
12142 + *[0-9a-f]*:   e4 1f 00 00     andh pc,0x0
12143 + *[0-9a-f]*:   e4 1c ff ff     andh r12,0xffff
12144 + *[0-9a-f]*:   e4 15 80 00     andh r5,0x8000
12145 + *[0-9a-f]*:   e4 14 7f ff     andh r4,0x7fff
12146 + *[0-9a-f]*:   e4 1e 00 01     andh lr,0x1
12147 + *[0-9a-f]*:   e4 1c cc 58     andh r12,0xcc58
12148 + *[0-9a-f]*:   e4 13 21 e3     andh r3,0x21e3
12149 + *[0-9a-f]*:   e4 12 a7 eb     andh r2,0xa7eb
12150 +
12151 +[0-9a-f]* <andh_coh>:
12152 + *[0-9a-f]*:   e6 1f 00 00     andh pc,0x0,COH
12153 + *[0-9a-f]*:   e6 1c ff ff     andh r12,0xffff,COH
12154 + *[0-9a-f]*:   e6 15 80 00     andh r5,0x8000,COH
12155 + *[0-9a-f]*:   e6 14 7f ff     andh r4,0x7fff,COH
12156 + *[0-9a-f]*:   e6 1e 00 01     andh lr,0x1,COH
12157 + *[0-9a-f]*:   e6 1b 86 0d     andh r11,0x860d,COH
12158 + *[0-9a-f]*:   e6 18 ce f6     andh r8,0xcef6,COH
12159 + *[0-9a-f]*:   e6 1a 5c 83     andh r10,0x5c83,COH
12160 +
12161 +[0-9a-f]* <orl>:
12162 + *[0-9a-f]*:   e8 1f 00 00     orl pc,0x0
12163 + *[0-9a-f]*:   e8 1c ff ff     orl r12,0xffff
12164 + *[0-9a-f]*:   e8 15 80 00     orl r5,0x8000
12165 + *[0-9a-f]*:   e8 14 7f ff     orl r4,0x7fff
12166 + *[0-9a-f]*:   e8 1e 00 01     orl lr,0x1
12167 + *[0-9a-f]*:   e8 1d 41 7e     orl sp,0x417e
12168 + *[0-9a-f]*:   e8 10 52 bd     orl r0,0x52bd
12169 + *[0-9a-f]*:   e8 1f ac 47     orl pc,0xac47
12170 +
12171 +[0-9a-f]* <orh>:
12172 + *[0-9a-f]*:   ea 1f 00 00     orh pc,0x0
12173 + *[0-9a-f]*:   ea 1c ff ff     orh r12,0xffff
12174 + *[0-9a-f]*:   ea 15 80 00     orh r5,0x8000
12175 + *[0-9a-f]*:   ea 14 7f ff     orh r4,0x7fff
12176 + *[0-9a-f]*:   ea 1e 00 01     orh lr,0x1
12177 + *[0-9a-f]*:   ea 18 6e 7d     orh r8,0x6e7d
12178 + *[0-9a-f]*:   ea 1c 77 1c     orh r12,0x771c
12179 + *[0-9a-f]*:   ea 11 ea 1a     orh r1,0xea1a
12180 +
12181 +[0-9a-f]* <eorl>:
12182 + *[0-9a-f]*:   ec 1f 00 00     eorl pc,0x0
12183 + *[0-9a-f]*:   ec 1c ff ff     eorl r12,0xffff
12184 + *[0-9a-f]*:   ec 15 80 00     eorl r5,0x8000
12185 + *[0-9a-f]*:   ec 14 7f ff     eorl r4,0x7fff
12186 + *[0-9a-f]*:   ec 1e 00 01     eorl lr,0x1
12187 + *[0-9a-f]*:   ec 14 c7 b9     eorl r4,0xc7b9
12188 + *[0-9a-f]*:   ec 16 fb dd     eorl r6,0xfbdd
12189 + *[0-9a-f]*:   ec 11 51 b1     eorl r1,0x51b1
12190 +
12191 +[0-9a-f]* <eorh>:
12192 + *[0-9a-f]*:   ee 1f 00 00     eorh pc,0x0
12193 + *[0-9a-f]*:   ee 1c ff ff     eorh r12,0xffff
12194 + *[0-9a-f]*:   ee 15 80 00     eorh r5,0x8000
12195 + *[0-9a-f]*:   ee 14 7f ff     eorh r4,0x7fff
12196 + *[0-9a-f]*:   ee 1e 00 01     eorh lr,0x1
12197 + *[0-9a-f]*:   ee 10 2d d4     eorh r0,0x2dd4
12198 + *[0-9a-f]*:   ee 1a 94 b5     eorh r10,0x94b5
12199 + *[0-9a-f]*:   ee 19 df 2a     eorh r9,0xdf2a
12200 +
12201 +[0-9a-f]* <mcall>:
12202 + *[0-9a-f]*:   f0 1f 00 00     mcall [0-9a-f]* <.*>
12203 + *[0-9a-f]*:   f0 1c ff ff     mcall r12\[-4\]
12204 + *[0-9a-f]*:   f0 15 80 00     mcall r5\[-131072\]
12205 + *[0-9a-f]*:   f0 14 7f ff     mcall r4\[131068\]
12206 + *[0-9a-f]*:   f0 1e 00 01     mcall lr\[4\]
12207 + *[0-9a-f]*:   f0 1d 3b bf     mcall sp\[61180\]
12208 + *[0-9a-f]*:   f0 14 dd d2     mcall r4\[-35000\]
12209 + *[0-9a-f]*:   f0 10 09 b1     mcall r0\[9924\]
12210 +
12211 +[0-9a-f]* <pref>:
12212 + *[0-9a-f]*:   f2 1f 00 00     pref pc\[0\]
12213 + *[0-9a-f]*:   f2 1c ff ff     pref r12\[-1\]
12214 + *[0-9a-f]*:   f2 15 80 00     pref r5\[-32768\]
12215 + *[0-9a-f]*:   f2 14 7f ff     pref r4\[32767\]
12216 + *[0-9a-f]*:   f2 1e 00 01     pref lr\[1\]
12217 + *[0-9a-f]*:   f2 17 1e 44     pref r7\[7748\]
12218 + *[0-9a-f]*:   f2 17 e1 ed     pref r7\[-7699\]
12219 + *[0-9a-f]*:   f2 12 9a dc     pref r2\[-25892\]
12220 +
12221 +[0-9a-f]* <cache>:
12222 + *[0-9a-f]*:   f4 1f 00 00     cache pc\[0\],0x0
12223 + *[0-9a-f]*:   f4 1c ff ff     cache r12\[-1\],0x1f
12224 + *[0-9a-f]*:   f4 15 84 00     cache r5\[-1024\],0x10
12225 + *[0-9a-f]*:   f4 14 7b ff     cache r4\[1023\],0xf
12226 + *[0-9a-f]*:   f4 1e 08 01     cache lr\[1\],0x1
12227 + *[0-9a-f]*:   f4 13 8c 3c     cache r3\[-964\],0x11
12228 + *[0-9a-f]*:   f4 14 b6 89     cache r4\[-375\],0x16
12229 + *[0-9a-f]*:   f4 13 8c 88     cache r3\[-888\],0x11
12230 +
12231 +[0-9a-f]* <sub4>:
12232 + *[0-9a-f]*:   20 0f           sub pc,0
12233 + *[0-9a-f]*:   2f fc           sub r12,-1
12234 + *[0-9a-f]*:   f0 25 00 00     sub r5,-1048576
12235 + *[0-9a-f]*:   ee 34 ff ff     sub r4,1048575
12236 + *[0-9a-f]*:   20 1e           sub lr,1
12237 + *[0-9a-f]*:   f6 22 8d 6c     sub r2,-619156
12238 + *[0-9a-f]*:   e6 3e 0a cd     sub lr,461517
12239 + *[0-9a-f]*:   fc 38 2d 25     sub r8,-185051
12240 +
12241 +[0-9a-f]* <cp3>:
12242 + *[0-9a-f]*:   58 0f           cp.w pc,0
12243 + *[0-9a-f]*:   5b fc           cp.w r12,-1
12244 + *[0-9a-f]*:   f0 45 00 00     cp.w r5,-1048576
12245 + *[0-9a-f]*:   ee 54 ff ff     cp.w r4,1048575
12246 + *[0-9a-f]*:   58 1e           cp.w lr,1
12247 + *[0-9a-f]*:   e0 51 e4 ae     cp.w r1,124078
12248 + *[0-9a-f]*:   fa 40 37 e3     cp.w r0,-378909
12249 + *[0-9a-f]*:   fc 44 4a 14     cp.w r4,-243180
12250 +
12251 +[0-9a-f]* <mov2>:
12252 + *[0-9a-f]*:   30 0f           mov pc,0
12253 + *[0-9a-f]*:   3f fc           mov r12,-1
12254 + *[0-9a-f]*:   f0 65 00 00     mov r5,-1048576
12255 + *[0-9a-f]*:   ee 74 ff ff     mov r4,1048575
12256 + *[0-9a-f]*:   30 1e           mov lr,1
12257 + *[0-9a-f]*:   fa 75 29 a3     mov r5,-317021
12258 + *[0-9a-f]*:   f4 6d 91 94     mov sp,-749164
12259 + *[0-9a-f]*:   ee 65 58 93     mov r5,940179
12260 +
12261 +[0-9a-f]* <brc2>:
12262 + *[0-9a-f]*:   c0 00           breq [0-9a-f]* <.*>
12263 + *[0-9a-f]*:   fe 9f ff ff     bral [0-9a-f]* <.*>
12264 + *[0-9a-f]*:   f0 88 00 00     brls [0-9a-f]* <.*>
12265 + *[0-9a-f]*:   ee 97 ff ff     brpl [0-9a-f]* <.*>
12266 + *[0-9a-f]*:   c0 11           brne [0-9a-f]* <.*>
12267 + *[0-9a-f]*:   f2 8b 4a 4d     brhi [0-9a-f]* <.*>
12268 + *[0-9a-f]*:   ea 8e 14 cc     brqs [0-9a-f]* <.*>
12269 + *[0-9a-f]*:   fa 98 98 33     brls [0-9a-f]* <.*>
12270 +
12271 +[0-9a-f]* <rcall2>:
12272 + *[0-9a-f]*:   c0 0c           rcall [0-9a-f]* <.*>
12273 + *[0-9a-f]*:   cf ff           rcall [0-9a-f]* <.*>
12274 + *[0-9a-f]*:   f0 a0 00 00     rcall [0-9a-f]* <.*>
12275 + *[0-9a-f]*:   ee b0 ff ff     rcall [0-9a-f]* <.*>
12276 + *[0-9a-f]*:   c0 1c           rcall [0-9a-f]* <.*>
12277 + *[0-9a-f]*:   e2 b0 ca 5a     rcall [0-9a-f]* <.*>
12278 + *[0-9a-f]*:   e8 a0 47 52     rcall [0-9a-f]* <.*>
12279 + *[0-9a-f]*:   fe b0 fd ef     rcall [0-9a-f]* <.*>
12280 +
12281 +[0-9a-f]* <sub5>:
12282 + *[0-9a-f]*:   fe cf 00 00     sub pc,pc,0
12283 + *[0-9a-f]*:   f8 cc ff ff     sub r12,r12,-1
12284 + *[0-9a-f]*:   ea c5 80 00     sub r5,r5,-32768
12285 + *[0-9a-f]*:   e8 c4 7f ff     sub r4,r4,32767
12286 + *[0-9a-f]*:   fc ce 00 01     sub lr,lr,1
12287 + *[0-9a-f]*:   fe cf ce 38     sub pc,pc,-12744
12288 + *[0-9a-f]*:   ee c7 95 1b     sub r7,r7,-27365
12289 + *[0-9a-f]*:   f2 c2 bc 32     sub r2,r9,-17358
12290 +
12291 +[0-9a-f]* <satsub_w2>:
12292 + *[0-9a-f]*:   fe df 00 00     satsub\.w pc,pc,0
12293 + *[0-9a-f]*:   f8 dc ff ff     satsub\.w r12,r12,-1
12294 + *[0-9a-f]*:   ea d5 80 00     satsub\.w r5,r5,-32768
12295 + *[0-9a-f]*:   e8 d4 7f ff     satsub\.w r4,r4,32767
12296 + *[0-9a-f]*:   fc de 00 01     satsub\.w lr,lr,1
12297 + *[0-9a-f]*:   fc d2 f8 29     satsub\.w r2,lr,-2007
12298 + *[0-9a-f]*:   f8 d7 fc f0     satsub\.w r7,r12,-784
12299 + *[0-9a-f]*:   ee d4 5a 8c     satsub\.w r4,r7,23180
12300 +
12301 +[0-9a-f]* <ld_d4>:
12302 + *[0-9a-f]*:   fe e0 00 00     ld\.d r0,pc\[0\]
12303 + *[0-9a-f]*:   f8 ee ff ff     ld\.d lr,r12\[-1\]
12304 + *[0-9a-f]*:   ea e8 80 00     ld\.d r8,r5\[-32768\]
12305 + *[0-9a-f]*:   e8 e6 7f ff     ld\.d r6,r4\[32767\]
12306 + *[0-9a-f]*:   fc e2 00 01     ld\.d r2,lr\[1\]
12307 + *[0-9a-f]*:   f6 ee 39 c0     ld\.d lr,r11\[14784\]
12308 + *[0-9a-f]*:   f2 e6 b6 27     ld\.d r6,r9\[-18905\]
12309 + *[0-9a-f]*:   e6 e2 e7 2d     ld\.d r2,r3\[-6355\]
12310 +
12311 +[0-9a-f]* <ld_w4>:
12312 + *[0-9a-f]*:   7e 0f           ld\.w pc,pc\[0x0\]
12313 + *[0-9a-f]*:   f8 fc ff ff     ld\.w r12,r12\[-1\]
12314 + *[0-9a-f]*:   ea f5 80 00     ld\.w r5,r5\[-32768\]
12315 + *[0-9a-f]*:   e8 f4 7f ff     ld\.w r4,r4\[32767\]
12316 + *[0-9a-f]*:   fc fe 00 01     ld\.w lr,lr\[1\]
12317 + *[0-9a-f]*:   f8 f0 a9 8b     ld\.w r0,r12\[-22133\]
12318 + *[0-9a-f]*:   fe fd af d7     ld\.w sp,pc\[-20521\]
12319 + *[0-9a-f]*:   d7 03           nop
12320 +
12321 +[0-9a-f]* <ld_sh4>:
12322 + *[0-9a-f]*:   9e 0f           ld\.sh pc,pc\[0x0\]
12323 + *[0-9a-f]*:   f9 0c ff ff     ld\.sh r12,r12\[-1\]
12324 + *[0-9a-f]*:   eb 05 80 00     ld\.sh r5,r5\[-32768\]
12325 + *[0-9a-f]*:   e9 04 7f ff     ld\.sh r4,r4\[32767\]
12326 + *[0-9a-f]*:   fd 0e 00 01     ld\.sh lr,lr\[1\]
12327 + *[0-9a-f]*:   f5 06 78 d2     ld\.sh r6,r10\[30930\]
12328 + *[0-9a-f]*:   f5 06 55 d5     ld\.sh r6,r10\[21973\]
12329 + *[0-9a-f]*:   d7 03           nop
12330 +
12331 +[0-9a-f]* <ld_uh4>:
12332 + *[0-9a-f]*:   9e 8f           ld\.uh pc,pc\[0x0\]
12333 + *[0-9a-f]*:   f9 1c ff ff     ld\.uh r12,r12\[-1\]
12334 + *[0-9a-f]*:   eb 15 80 00     ld\.uh r5,r5\[-32768\]
12335 + *[0-9a-f]*:   e9 14 7f ff     ld\.uh r4,r4\[32767\]
12336 + *[0-9a-f]*:   fd 1e 00 01     ld\.uh lr,lr\[1\]
12337 + *[0-9a-f]*:   f3 11 cb d6     ld\.uh r1,r9\[-13354\]
12338 + *[0-9a-f]*:   f7 1e 53 59     ld\.uh lr,r11\[21337\]
12339 + *[0-9a-f]*:   d7 03           nop
12340 +
12341 +[0-9a-f]* <ld_sb1>:
12342 + *[0-9a-f]*:   ff 2f 00 00     ld\.sb pc,pc\[0\]
12343 + *[0-9a-f]*:   f9 2c ff ff     ld\.sb r12,r12\[-1\]
12344 + *[0-9a-f]*:   eb 25 80 00     ld\.sb r5,r5\[-32768\]
12345 + *[0-9a-f]*:   e9 24 7f ff     ld\.sb r4,r4\[32767\]
12346 + *[0-9a-f]*:   fd 2e 00 01     ld\.sb lr,lr\[1\]
12347 + *[0-9a-f]*:   fb 27 90 09     ld\.sb r7,sp\[-28663\]
12348 + *[0-9a-f]*:   e3 22 e9 09     ld\.sb r2,r1\[-5879\]
12349 + *[0-9a-f]*:   e7 2c 49 2e     ld\.sb r12,r3\[18734\]
12350 +
12351 +[0-9a-f]* <ld_ub4>:
12352 + *[0-9a-f]*:   1f 8f           ld\.ub pc,pc\[0x0\]
12353 + *[0-9a-f]*:   f9 3c ff ff     ld\.ub r12,r12\[-1\]
12354 + *[0-9a-f]*:   eb 35 80 00     ld\.ub r5,r5\[-32768\]
12355 + *[0-9a-f]*:   e9 34 7f ff     ld\.ub r4,r4\[32767\]
12356 + *[0-9a-f]*:   1d 9e           ld\.ub lr,lr\[0x1\]
12357 + *[0-9a-f]*:   e9 3f 20 55     ld\.ub pc,r4\[8277\]
12358 + *[0-9a-f]*:   f9 35 4a e4     ld\.ub r5,r12\[19172\]
12359 + *[0-9a-f]*:   fd 3a 66 eb     ld\.ub r10,lr\[26347\]
12360 +
12361 +[0-9a-f]* <st_d4>:
12362 + *[0-9a-f]*:   fe e1 00 00     st\.d pc\[0\],r0
12363 + *[0-9a-f]*:   f8 ef ff ff     st\.d r12\[-1\],lr
12364 + *[0-9a-f]*:   ea e9 80 00     st\.d r5\[-32768\],r8
12365 + *[0-9a-f]*:   e8 e7 7f ff     st\.d r4\[32767\],r6
12366 + *[0-9a-f]*:   fc e3 00 01     st\.d lr\[1\],r2
12367 + *[0-9a-f]*:   ea eb 33 90     st\.d r5\[13200\],r10
12368 + *[0-9a-f]*:   ea eb 24 88     st\.d r5\[9352\],r10
12369 + *[0-9a-f]*:   ea e5 7e 75     st\.d r5\[32373\],r4
12370 +
12371 +[0-9a-f]* <st_w4>:
12372 + *[0-9a-f]*:   9f 0f           st\.w pc\[0x0\],pc
12373 + *[0-9a-f]*:   f9 4c ff ff     st\.w r12\[-1\],r12
12374 + *[0-9a-f]*:   eb 45 80 00     st\.w r5\[-32768\],r5
12375 + *[0-9a-f]*:   e9 44 7f ff     st\.w r4\[32767\],r4
12376 + *[0-9a-f]*:   fd 4e 00 01     st\.w lr\[1\],lr
12377 + *[0-9a-f]*:   fb 47 17 f8     st\.w sp\[6136\],r7
12378 + *[0-9a-f]*:   ed 4c 69 cf     st\.w r6\[27087\],r12
12379 + *[0-9a-f]*:   d7 03           nop
12380 +
12381 +[0-9a-f]* <st_h4>:
12382 + *[0-9a-f]*:   be 0f           st\.h pc\[0x0\],pc
12383 + *[0-9a-f]*:   f9 5c ff ff     st\.h r12\[-1\],r12
12384 + *[0-9a-f]*:   eb 55 80 00     st\.h r5\[-32768\],r5
12385 + *[0-9a-f]*:   e9 54 7f ff     st\.h r4\[32767\],r4
12386 + *[0-9a-f]*:   fd 5e 00 01     st\.h lr\[1\],lr
12387 + *[0-9a-f]*:   e9 57 d9 16     st\.h r4\[-9962\],r7
12388 + *[0-9a-f]*:   f3 53 c0 86     st\.h r9\[-16250\],r3
12389 + *[0-9a-f]*:   d7 03           nop
12390 +
12391 +[0-9a-f]* <st_b4>:
12392 + *[0-9a-f]*:   be 8f           st\.b pc\[0x0\],pc
12393 + *[0-9a-f]*:   f9 6c ff ff     st\.b r12\[-1\],r12
12394 + *[0-9a-f]*:   eb 65 80 00     st\.b r5\[-32768\],r5
12395 + *[0-9a-f]*:   e9 64 7f ff     st\.b r4\[32767\],r4
12396 + *[0-9a-f]*:   bc 9e           st\.b lr\[0x1\],lr
12397 + *[0-9a-f]*:   f9 66 75 96     st\.b r12\[30102\],r6
12398 + *[0-9a-f]*:   eb 61 71 31     st\.b r5\[28977\],r1
12399 + *[0-9a-f]*:   e1 61 15 5e     st\.b r0\[5470\],r1
12400 +
12401 +[0-9a-f]* <mfsr>:
12402 + *[0-9a-f]*:   e1 bf 00 00     mfsr pc,0x0
12403 + *[0-9a-f]*:   e1 bc 00 ff     mfsr r12,0x3fc
12404 + *[0-9a-f]*:   e1 b5 00 80     mfsr r5,0x200
12405 + *[0-9a-f]*:   e1 b4 00 7f     mfsr r4,0x1fc
12406 + *[0-9a-f]*:   e1 be 00 01     mfsr lr,0x4
12407 + *[0-9a-f]*:   e1 b2 00 ae     mfsr r2,0x2b8
12408 + *[0-9a-f]*:   e1 b4 00 41     mfsr r4,0x104
12409 + *[0-9a-f]*:   e1 ba 00 fe     mfsr r10,0x3f8
12410 +
12411 +[0-9a-f]* <mtsr>:
12412 + *[0-9a-f]*:   e3 bf 00 00     mtsr 0x0,pc
12413 + *[0-9a-f]*:   e3 bc 00 ff     mtsr 0x3fc,r12
12414 + *[0-9a-f]*:   e3 b5 00 80     mtsr 0x200,r5
12415 + *[0-9a-f]*:   e3 b4 00 7f     mtsr 0x1fc,r4
12416 + *[0-9a-f]*:   e3 be 00 01     mtsr 0x4,lr
12417 + *[0-9a-f]*:   e3 ba 00 38     mtsr 0xe0,r10
12418 + *[0-9a-f]*:   e3 bc 00 d1     mtsr 0x344,r12
12419 + *[0-9a-f]*:   e3 b9 00 4c     mtsr 0x130,r9
12420 +
12421 +[0-9a-f]* <mfdr>:
12422 + *[0-9a-f]*:   e5 bf 00 00     mfdr pc,0x0
12423 + *[0-9a-f]*:   e5 bc 00 ff     mfdr r12,0x3fc
12424 + *[0-9a-f]*:   e5 b5 00 80     mfdr r5,0x200
12425 + *[0-9a-f]*:   e5 b4 00 7f     mfdr r4,0x1fc
12426 + *[0-9a-f]*:   e5 be 00 01     mfdr lr,0x4
12427 + *[0-9a-f]*:   e5 b6 00 e9     mfdr r6,0x3a4
12428 + *[0-9a-f]*:   e5 b5 00 09     mfdr r5,0x24
12429 + *[0-9a-f]*:   e5 b9 00 4b     mfdr r9,0x12c
12430 +
12431 +[0-9a-f]* <mtdr>:
12432 + *[0-9a-f]*:   e7 bf 00 00     mtdr 0x0,pc
12433 + *[0-9a-f]*:   e7 bc 00 ff     mtdr 0x3fc,r12
12434 + *[0-9a-f]*:   e7 b5 00 80     mtdr 0x200,r5
12435 + *[0-9a-f]*:   e7 b4 00 7f     mtdr 0x1fc,r4
12436 + *[0-9a-f]*:   e7 be 00 01     mtdr 0x4,lr
12437 + *[0-9a-f]*:   e7 b8 00 2d     mtdr 0xb4,r8
12438 + *[0-9a-f]*:   e7 ba 00 b4     mtdr 0x2d0,r10
12439 + *[0-9a-f]*:   e7 be 00 66     mtdr 0x198,lr
12440 +
12441 +[0-9a-f]* <sleep>:
12442 + *[0-9a-f]*:   e9 b0 00 00     sleep 0x0
12443 + *[0-9a-f]*:   e9 b0 00 ff     sleep 0xff
12444 + *[0-9a-f]*:   e9 b0 00 80     sleep 0x80
12445 + *[0-9a-f]*:   e9 b0 00 7f     sleep 0x7f
12446 + *[0-9a-f]*:   e9 b0 00 01     sleep 0x1
12447 + *[0-9a-f]*:   e9 b0 00 fe     sleep 0xfe
12448 + *[0-9a-f]*:   e9 b0 00 0f     sleep 0xf
12449 + *[0-9a-f]*:   e9 b0 00 2b     sleep 0x2b
12450 +
12451 +[0-9a-f]* <sync>:
12452 + *[0-9a-f]*:   eb b0 00 00     sync 0x0
12453 + *[0-9a-f]*:   eb b0 00 ff     sync 0xff
12454 + *[0-9a-f]*:   eb b0 00 80     sync 0x80
12455 + *[0-9a-f]*:   eb b0 00 7f     sync 0x7f
12456 + *[0-9a-f]*:   eb b0 00 01     sync 0x1
12457 + *[0-9a-f]*:   eb b0 00 a6     sync 0xa6
12458 + *[0-9a-f]*:   eb b0 00 e6     sync 0xe6
12459 + *[0-9a-f]*:   eb b0 00 b4     sync 0xb4
12460 +
12461 +[0-9a-f]* <bld>:
12462 + *[0-9a-f]*:   ed bf 00 00     bld pc,0x0
12463 + *[0-9a-f]*:   ed bc 00 1f     bld r12,0x1f
12464 + *[0-9a-f]*:   ed b5 00 10     bld r5,0x10
12465 + *[0-9a-f]*:   ed b4 00 0f     bld r4,0xf
12466 + *[0-9a-f]*:   ed be 00 01     bld lr,0x1
12467 + *[0-9a-f]*:   ed b9 00 0f     bld r9,0xf
12468 + *[0-9a-f]*:   ed b0 00 04     bld r0,0x4
12469 + *[0-9a-f]*:   ed be 00 1a     bld lr,0x1a
12470 +
12471 +[0-9a-f]* <bst>:
12472 + *[0-9a-f]*:   ef bf 00 00     bst pc,0x0
12473 + *[0-9a-f]*:   ef bc 00 1f     bst r12,0x1f
12474 + *[0-9a-f]*:   ef b5 00 10     bst r5,0x10
12475 + *[0-9a-f]*:   ef b4 00 0f     bst r4,0xf
12476 + *[0-9a-f]*:   ef be 00 01     bst lr,0x1
12477 + *[0-9a-f]*:   ef ba 00 1c     bst r10,0x1c
12478 + *[0-9a-f]*:   ef b0 00 03     bst r0,0x3
12479 + *[0-9a-f]*:   ef bd 00 02     bst sp,0x2
12480 +
12481 +[0-9a-f]* <sats>:
12482 + *[0-9a-f]*:   f1 bf 00 00     sats pc,0x0
12483 + *[0-9a-f]*:   f1 bc 03 ff     sats r12>>0x1f,0x1f
12484 + *[0-9a-f]*:   f1 b5 02 10     sats r5>>0x10,0x10
12485 + *[0-9a-f]*:   f1 b4 01 ef     sats r4>>0xf,0xf
12486 + *[0-9a-f]*:   f1 be 00 21     sats lr>>0x1,0x1
12487 + *[0-9a-f]*:   f1 ba 02 63     sats r10>>0x3,0x13
12488 + *[0-9a-f]*:   f1 ba 03 42     sats r10>>0x2,0x1a
12489 + *[0-9a-f]*:   f1 b1 00 34     sats r1>>0x14,0x1
12490 +
12491 +[0-9a-f]* <satu>:
12492 + *[0-9a-f]*:   f1 bf 04 00     satu pc,0x0
12493 + *[0-9a-f]*:   f1 bc 07 ff     satu r12>>0x1f,0x1f
12494 + *[0-9a-f]*:   f1 b5 06 10     satu r5>>0x10,0x10
12495 + *[0-9a-f]*:   f1 b4 05 ef     satu r4>>0xf,0xf
12496 + *[0-9a-f]*:   f1 be 04 21     satu lr>>0x1,0x1
12497 + *[0-9a-f]*:   f1 bf 04 e5     satu pc>>0x5,0x7
12498 + *[0-9a-f]*:   f1 b7 04 a5     satu r7>>0x5,0x5
12499 + *[0-9a-f]*:   f1 b2 06 7a     satu r2>>0x1a,0x13
12500 +
12501 +[0-9a-f]* <satrnds>:
12502 + *[0-9a-f]*:   f3 bf 00 00     satrnds pc,0x0
12503 + *[0-9a-f]*:   f3 bc 03 ff     satrnds r12>>0x1f,0x1f
12504 + *[0-9a-f]*:   f3 b5 02 10     satrnds r5>>0x10,0x10
12505 + *[0-9a-f]*:   f3 b4 01 ef     satrnds r4>>0xf,0xf
12506 + *[0-9a-f]*:   f3 be 00 21     satrnds lr>>0x1,0x1
12507 + *[0-9a-f]*:   f3 b0 02 75     satrnds r0>>0x15,0x13
12508 + *[0-9a-f]*:   f3 bd 00 40     satrnds sp,0x2
12509 + *[0-9a-f]*:   f3 b7 03 a6     satrnds r7>>0x6,0x1d
12510 +
12511 +[0-9a-f]* <satrndu>:
12512 + *[0-9a-f]*:   f3 bf 04 00     satrndu pc,0x0
12513 + *[0-9a-f]*:   f3 bc 07 ff     satrndu r12>>0x1f,0x1f
12514 + *[0-9a-f]*:   f3 b5 06 10     satrndu r5>>0x10,0x10
12515 + *[0-9a-f]*:   f3 b4 05 ef     satrndu r4>>0xf,0xf
12516 + *[0-9a-f]*:   f3 be 04 21     satrndu lr>>0x1,0x1
12517 + *[0-9a-f]*:   f3 bc 07 40     satrndu r12,0x1a
12518 + *[0-9a-f]*:   f3 b4 04 75     satrndu r4>>0x15,0x3
12519 + *[0-9a-f]*:   f3 ba 06 03     satrndu r10>>0x3,0x10
12520 +
12521 +[0-9a-f]* <subfc>:
12522 + *[0-9a-f]*:   f5 bf 00 00     subfeq pc,0
12523 + *[0-9a-f]*:   f5 bc 0f ff     subfal r12,-1
12524 + *[0-9a-f]*:   f5 b5 08 80     subfls r5,-128
12525 + *[0-9a-f]*:   f5 b4 07 7f     subfpl r4,127
12526 + *[0-9a-f]*:   f5 be 01 01     subfne lr,1
12527 + *[0-9a-f]*:   f5 ba 08 08     subfls r10,8
12528 + *[0-9a-f]*:   f5 bb 0d 63     subfvc r11,99
12529 + *[0-9a-f]*:   f5 b2 0c 49     subfvs r2,73
12530 +
12531 +[0-9a-f]* <subc>:
12532 + *[0-9a-f]*:   f7 bf 00 00     subeq pc,0
12533 + *[0-9a-f]*:   f7 bc 0f ff     subal r12,-1
12534 + *[0-9a-f]*:   f7 b5 08 80     subls r5,-128
12535 + *[0-9a-f]*:   f7 b4 07 7f     subpl r4,127
12536 + *[0-9a-f]*:   f7 be 01 01     subne lr,1
12537 + *[0-9a-f]*:   f7 bc 08 76     subls r12,118
12538 + *[0-9a-f]*:   f7 be 0d f4     subvc lr,-12
12539 + *[0-9a-f]*:   f7 b4 06 f3     submi r4,-13
12540 +
12541 +[0-9a-f]* <movc2>:
12542 + *[0-9a-f]*:   f9 bf 00 00     moveq pc,0
12543 + *[0-9a-f]*:   f9 bc 0f ff     moval r12,-1
12544 + *[0-9a-f]*:   f9 b5 08 80     movls r5,-128
12545 + *[0-9a-f]*:   f9 b4 07 7f     movpl r4,127
12546 + *[0-9a-f]*:   f9 be 01 01     movne lr,1
12547 + *[0-9a-f]*:   f9 b3 05 86     movlt r3,-122
12548 + *[0-9a-f]*:   f9 b8 0d 02     movvc r8,2
12549 + *[0-9a-f]*:   f9 b7 01 91     movne r7,-111
12550 +
12551 +[0-9a-f]* <cp_b>:
12552 + *[0-9a-f]*:   e0 0f 18 00     cp\.b pc,r0
12553 + *[0-9a-f]*:   fe 00 18 00     cp\.b r0,pc
12554 + *[0-9a-f]*:   f0 07 18 00     cp\.b r7,r8
12555 + *[0-9a-f]*:   ee 08 18 00     cp\.b r8,r7
12556 +
12557 +[0-9a-f]* <cp_h>:
12558 + *[0-9a-f]*:   e0 0f 19 00     cp\.h pc,r0
12559 + *[0-9a-f]*:   fe 00 19 00     cp\.h r0,pc
12560 + *[0-9a-f]*:   f0 07 19 00     cp\.h r7,r8
12561 + *[0-9a-f]*:   ee 08 19 00     cp\.h r8,r7
12562 +
12563 +[0-9a-f]* <ldm>:
12564 + *[0-9a-f]*:   e1 cf 00 7e     ldm pc,r1-r6
12565 + *[0-9a-f]*:   e1 cc ff ff     ldm r12,r0-pc
12566 + *[0-9a-f]*:   e1 c5 80 00     ldm r5,pc
12567 + *[0-9a-f]*:   e1 c4 7f ff     ldm r4,r0-lr
12568 + *[0-9a-f]*:   e1 ce 00 01     ldm lr,r0
12569 + *[0-9a-f]*:   e1 c9 40 22     ldm r9,r1,r5,lr
12570 + *[0-9a-f]*:   e1 cb 81 ec     ldm r11,r2-r3,r5-r8,pc
12571 + *[0-9a-f]*:   e1 c6 a2 09     ldm r6,r0,r3,r9,sp,pc
12572 +
12573 +[0-9a-f]* <ldm_pu>:
12574 + *[0-9a-f]*:   e3 cf 03 c0     ldm pc\+\+,r6-r9
12575 + *[0-9a-f]*:   e3 cc ff ff     ldm r12\+\+,r0-pc
12576 + *[0-9a-f]*:   e3 c5 80 00     ldm r5\+\+,pc
12577 + *[0-9a-f]*:   e3 c4 7f ff     ldm r4\+\+,r0-lr
12578 + *[0-9a-f]*:   e3 ce 00 01     ldm lr\+\+,r0
12579 + *[0-9a-f]*:   e3 cc d5 38     ldm r12\+\+,r3-r5,r8,r10,r12,lr-pc
12580 + *[0-9a-f]*:   e3 ca c0 74     ldm r10\+\+,r2,r4-r6,lr-pc
12581 + *[0-9a-f]*:   e3 c6 7e 1a     ldm r6\+\+,r1,r3-r4,r9-lr
12582 +
12583 +[0-9a-f]* <ldmts>:
12584 + *[0-9a-f]*:   e5 cf 01 80     ldmts pc,r7-r8
12585 + *[0-9a-f]*:   e5 cc ff ff     ldmts r12,r0-pc
12586 + *[0-9a-f]*:   e5 c5 80 00     ldmts r5,pc
12587 + *[0-9a-f]*:   e5 c4 7f ff     ldmts r4,r0-lr
12588 + *[0-9a-f]*:   e5 ce 00 01     ldmts lr,r0
12589 + *[0-9a-f]*:   e5 c0 18 06     ldmts r0,r1-r2,r11-r12
12590 + *[0-9a-f]*:   e5 ce 61 97     ldmts lr,r0-r2,r4,r7-r8,sp-lr
12591 + *[0-9a-f]*:   e5 cc c2 3b     ldmts r12,r0-r1,r3-r5,r9,lr-pc
12592 +
12593 +[0-9a-f]* <ldmts_pu>:
12594 + *[0-9a-f]*:   e7 cf 02 00     ldmts pc\+\+,r9
12595 + *[0-9a-f]*:   e7 cc ff ff     ldmts r12\+\+,r0-pc
12596 + *[0-9a-f]*:   e7 c5 80 00     ldmts r5\+\+,pc
12597 + *[0-9a-f]*:   e7 c4 7f ff     ldmts r4\+\+,r0-lr
12598 + *[0-9a-f]*:   e7 ce 00 01     ldmts lr\+\+,r0
12599 + *[0-9a-f]*:   e7 cd 0a bd     ldmts sp\+\+,r0,r2-r5,r7,r9,r11
12600 + *[0-9a-f]*:   e7 c5 0c 8e     ldmts r5\+\+,r1-r3,r7,r10-r11
12601 + *[0-9a-f]*:   e7 c8 a1 9c     ldmts r8\+\+,r2-r4,r7-r8,sp,pc
12602 +
12603 +[0-9a-f]* <stm>:
12604 + *[0-9a-f]*:   e9 cf 00 80     stm pc,r7
12605 + *[0-9a-f]*:   e9 cc ff ff     stm r12,r0-pc
12606 + *[0-9a-f]*:   e9 c5 80 00     stm r5,pc
12607 + *[0-9a-f]*:   e9 c4 7f ff     stm r4,r0-lr
12608 + *[0-9a-f]*:   e9 ce 00 01     stm lr,r0
12609 + *[0-9a-f]*:   e9 cd 49 2c     stm sp,r2-r3,r5,r8,r11,lr
12610 + *[0-9a-f]*:   e9 c4 4c 5f     stm r4,r0-r4,r6,r10-r11,lr
12611 + *[0-9a-f]*:   e9 c9 f2 22     stm r9,r1,r5,r9,r12-pc
12612 +
12613 +[0-9a-f]* <stm_pu>:
12614 + *[0-9a-f]*:   eb cf 00 70     stm --pc,r4-r6
12615 + *[0-9a-f]*:   eb cc ff ff     stm --r12,r0-pc
12616 + *[0-9a-f]*:   eb c5 80 00     stm --r5,pc
12617 + *[0-9a-f]*:   eb c4 7f ff     stm --r4,r0-lr
12618 + *[0-9a-f]*:   eb ce 00 01     stm --lr,r0
12619 + *[0-9a-f]*:   eb cb fb f1     stm --r11,r0,r4-r9,r11-pc
12620 + *[0-9a-f]*:   eb cb 56 09     stm --r11,r0,r3,r9-r10,r12,lr
12621 + *[0-9a-f]*:   eb c6 63 04     stm --r6,r2,r8-r9,sp-lr
12622 +
12623 +[0-9a-f]* <stmts>:
12624 + *[0-9a-f]*:   ed cf 01 00     stmts pc,r8
12625 + *[0-9a-f]*:   ed cc ff ff     stmts r12,r0-pc
12626 + *[0-9a-f]*:   ed c5 80 00     stmts r5,pc
12627 + *[0-9a-f]*:   ed c4 7f ff     stmts r4,r0-lr
12628 + *[0-9a-f]*:   ed ce 00 01     stmts lr,r0
12629 + *[0-9a-f]*:   ed c1 c6 5b     stmts r1,r0-r1,r3-r4,r6,r9-r10,lr-pc
12630 + *[0-9a-f]*:   ed c3 1d c1     stmts r3,r0,r6-r8,r10-r12
12631 + *[0-9a-f]*:   ed cb d6 d1     stmts r11,r0,r4,r6-r7,r9-r10,r12,lr-pc
12632 +
12633 +[0-9a-f]* <stmts_pu>:
12634 + *[0-9a-f]*:   ef cf 01 c0     stmts --pc,r6-r8
12635 + *[0-9a-f]*:   ef cc ff ff     stmts --r12,r0-pc
12636 + *[0-9a-f]*:   ef c5 80 00     stmts --r5,pc
12637 + *[0-9a-f]*:   ef c4 7f ff     stmts --r4,r0-lr
12638 + *[0-9a-f]*:   ef ce 00 01     stmts --lr,r0
12639 + *[0-9a-f]*:   ef c2 36 19     stmts --r2,r0,r3-r4,r9-r10,r12-sp
12640 + *[0-9a-f]*:   ef c3 c0 03     stmts --r3,r0-r1,lr-pc
12641 + *[0-9a-f]*:   ef c0 44 7d     stmts --r0,r0,r2-r6,r10,lr
12642 +
12643 +[0-9a-f]* <ldins_h>:
12644 + *[0-9a-f]*:   ff df 00 00     ldins\.h pc:b,pc\[0\]
12645 + *[0-9a-f]*:   f9 dc 1f ff     ldins\.h r12:t,r12\[-2\]
12646 + *[0-9a-f]*:   eb d5 18 00     ldins\.h r5:t,r5\[-4096\]
12647 + *[0-9a-f]*:   e9 d4 07 ff     ldins\.h r4:b,r4\[4094\]
12648 + *[0-9a-f]*:   fd de 10 01     ldins\.h lr:t,lr\[2\]
12649 + *[0-9a-f]*:   fd d0 13 c5     ldins\.h r0:t,lr\[1930\]
12650 + *[0-9a-f]*:   ef d3 0e f5     ldins\.h r3:b,r7\[-534\]
12651 + *[0-9a-f]*:   f9 d2 0b 9a     ldins\.h r2:b,r12\[-2252\]
12652 +
12653 +[0-9a-f]* <ldins_b>:
12654 + *[0-9a-f]*:   ff df 40 00     ldins\.b pc:b,pc\[0\]
12655 + *[0-9a-f]*:   f9 dc 7f ff     ldins\.b r12:t,r12\[-1\]
12656 + *[0-9a-f]*:   eb d5 68 00     ldins\.b r5:u,r5\[-2048\]
12657 + *[0-9a-f]*:   e9 d4 57 ff     ldins\.b r4:l,r4\[2047\]
12658 + *[0-9a-f]*:   fd de 50 01     ldins\.b lr:l,lr\[1\]
12659 + *[0-9a-f]*:   e9 d6 7d 6a     ldins\.b r6:t,r4\[-662\]
12660 + *[0-9a-f]*:   e3 d5 4f 69     ldins\.b r5:b,r1\[-151\]
12661 + *[0-9a-f]*:   f7 da 78 7d     ldins\.b r10:t,r11\[-1923\]
12662 +
12663 +[0-9a-f]* <ldswp_sh>:
12664 + *[0-9a-f]*:   ff df 20 00     ldswp\.sh pc,pc\[0\]
12665 + *[0-9a-f]*:   f9 dc 2f ff     ldswp\.sh r12,r12\[-2\]
12666 + *[0-9a-f]*:   eb d5 28 00     ldswp\.sh r5,r5\[-4096\]
12667 + *[0-9a-f]*:   e9 d4 27 ff     ldswp\.sh r4,r4\[4094\]
12668 + *[0-9a-f]*:   fd de 20 01     ldswp\.sh lr,lr\[2\]
12669 + *[0-9a-f]*:   f5 d9 27 84     ldswp\.sh r9,r10\[3848\]
12670 + *[0-9a-f]*:   f9 d4 2c 04     ldswp\.sh r4,r12\[-2040\]
12671 + *[0-9a-f]*:   e5 da 26 08     ldswp\.sh r10,r2\[3088\]
12672 +
12673 +[0-9a-f]* <ldswp_uh>:
12674 + *[0-9a-f]*:   ff df 30 00     ldswp\.uh pc,pc\[0\]
12675 + *[0-9a-f]*:   f9 dc 3f ff     ldswp\.uh r12,r12\[-2\]
12676 + *[0-9a-f]*:   eb d5 38 00     ldswp\.uh r5,r5\[-4096\]
12677 + *[0-9a-f]*:   e9 d4 37 ff     ldswp\.uh r4,r4\[4094\]
12678 + *[0-9a-f]*:   fd de 30 01     ldswp\.uh lr,lr\[2\]
12679 + *[0-9a-f]*:   f3 d4 37 46     ldswp\.uh r4,r9\[3724\]
12680 + *[0-9a-f]*:   fb de 3c bc     ldswp\.uh lr,sp\[-1672\]
12681 + *[0-9a-f]*:   f9 d8 38 7d     ldswp\.uh r8,r12\[-3846\]
12682 +
12683 +[0-9a-f]* <ldswp_w>:
12684 + *[0-9a-f]*:   ff df 80 00     ldswp\.w pc,pc\[0\]
12685 + *[0-9a-f]*:   f9 dc 8f ff     ldswp\.w r12,r12\[-4\]
12686 + *[0-9a-f]*:   eb d5 88 00     ldswp\.w r5,r5\[-8192\]
12687 + *[0-9a-f]*:   e9 d4 87 ff     ldswp\.w r4,r4\[8188\]
12688 + *[0-9a-f]*:   fd de 80 01     ldswp\.w lr,lr\[4\]
12689 + *[0-9a-f]*:   ef dd 81 d1     ldswp\.w sp,r7\[1860\]
12690 + *[0-9a-f]*:   eb df 8c c1     ldswp\.w pc,r5\[-3324\]
12691 + *[0-9a-f]*:   f5 dc 8c c8     ldswp\.w r12,r10\[-3296\]
12692 +
12693 +[0-9a-f]* <stswp_h>:
12694 + *[0-9a-f]*:   ff df 90 00     stswp\.h pc\[0\],pc
12695 + *[0-9a-f]*:   f9 dc 9f ff     stswp\.h r12\[-2\],r12
12696 + *[0-9a-f]*:   eb d5 98 00     stswp\.h r5\[-4096\],r5
12697 + *[0-9a-f]*:   e9 d4 97 ff     stswp\.h r4\[4094\],r4
12698 + *[0-9a-f]*:   fd de 90 01     stswp\.h lr\[2\],lr
12699 + *[0-9a-f]*:   ef da 90 20     stswp\.h r7\[64\],r10
12700 + *[0-9a-f]*:   f5 d2 95 e8     stswp\.h r10\[3024\],r2
12701 + *[0-9a-f]*:   e1 da 9b 74     stswp\.h r0\[-2328\],r10
12702 +
12703 +[0-9a-f]* <stswp_w>:
12704 + *[0-9a-f]*:   ff df a0 00     stswp\.w pc\[0\],pc
12705 + *[0-9a-f]*:   f9 dc af ff     stswp\.w r12\[-4\],r12
12706 + *[0-9a-f]*:   eb d5 a8 00     stswp\.w r5\[-8192\],r5
12707 + *[0-9a-f]*:   e9 d4 a7 ff     stswp\.w r4\[8188\],r4
12708 + *[0-9a-f]*:   fd de a0 01     stswp\.w lr\[4\],lr
12709 + *[0-9a-f]*:   ff d8 a1 21     stswp\.w pc\[1156\],r8
12710 + *[0-9a-f]*:   fb da a7 ce     stswp\.w sp\[7992\],r10
12711 + *[0-9a-f]*:   f1 d5 ae db     stswp\.w r8\[-1172\],r5
12712 +
12713 +[0-9a-f]* <and2>:
12714 + *[0-9a-f]*:   ff ef 00 0f     and pc,pc,pc
12715 + *[0-9a-f]*:   f9 ec 01 fc     and r12,r12,r12<<0x1f
12716 + *[0-9a-f]*:   eb e5 01 05     and r5,r5,r5<<0x10
12717 + *[0-9a-f]*:   e9 e4 00 f4     and r4,r4,r4<<0xf
12718 + *[0-9a-f]*:   fd ee 00 1e     and lr,lr,lr<<0x1
12719 + *[0-9a-f]*:   e5 e1 00 1a     and r10,r2,r1<<0x1
12720 + *[0-9a-f]*:   f1 eb 01 bc     and r12,r8,r11<<0x1b
12721 + *[0-9a-f]*:   ef e0 00 3a     and r10,r7,r0<<0x3
12722 +
12723 +[0-9a-f]* <and3>:
12724 + *[0-9a-f]*:   ff ef 02 0f     and pc,pc,pc
12725 + *[0-9a-f]*:   f9 ec 03 fc     and r12,r12,r12>>0x1f
12726 + *[0-9a-f]*:   eb e5 03 05     and r5,r5,r5>>0x10
12727 + *[0-9a-f]*:   e9 e4 02 f4     and r4,r4,r4>>0xf
12728 + *[0-9a-f]*:   fd ee 02 1e     and lr,lr,lr>>0x1
12729 + *[0-9a-f]*:   f1 e7 03 1c     and r12,r8,r7>>0x11
12730 + *[0-9a-f]*:   e9 e9 03 4f     and pc,r4,r9>>0x14
12731 + *[0-9a-f]*:   f3 ea 02 ca     and r10,r9,r10>>0xc
12732 +
12733 +[0-9a-f]* <or2>:
12734 + *[0-9a-f]*:   ff ef 10 0f     or pc,pc,pc
12735 + *[0-9a-f]*:   f9 ec 11 fc     or r12,r12,r12<<0x1f
12736 + *[0-9a-f]*:   eb e5 11 05     or r5,r5,r5<<0x10
12737 + *[0-9a-f]*:   e9 e4 10 f4     or r4,r4,r4<<0xf
12738 + *[0-9a-f]*:   fd ee 10 1e     or lr,lr,lr<<0x1
12739 + *[0-9a-f]*:   fb eb 11 d8     or r8,sp,r11<<0x1d
12740 + *[0-9a-f]*:   f3 e2 11 cf     or pc,r9,r2<<0x1c
12741 + *[0-9a-f]*:   e3 e2 10 35     or r5,r1,r2<<0x3
12742 +
12743 +[0-9a-f]* <or3>:
12744 + *[0-9a-f]*:   ff ef 12 0f     or pc,pc,pc
12745 + *[0-9a-f]*:   f9 ec 13 fc     or r12,r12,r12>>0x1f
12746 + *[0-9a-f]*:   eb e5 13 05     or r5,r5,r5>>0x10
12747 + *[0-9a-f]*:   e9 e4 12 f4     or r4,r4,r4>>0xf
12748 + *[0-9a-f]*:   fd ee 12 1e     or lr,lr,lr>>0x1
12749 + *[0-9a-f]*:   fb ed 12 21     or r1,sp,sp>>0x2
12750 + *[0-9a-f]*:   e3 e1 13 d0     or r0,r1,r1>>0x1d
12751 + *[0-9a-f]*:   f9 e8 12 84     or r4,r12,r8>>0x8
12752 +
12753 +[0-9a-f]* <eor2>:
12754 + *[0-9a-f]*:   ff ef 20 0f     eor pc,pc,pc
12755 + *[0-9a-f]*:   f9 ec 21 fc     eor r12,r12,r12<<0x1f
12756 + *[0-9a-f]*:   eb e5 21 05     eor r5,r5,r5<<0x10
12757 + *[0-9a-f]*:   e9 e4 20 f4     eor r4,r4,r4<<0xf
12758 + *[0-9a-f]*:   fd ee 20 1e     eor lr,lr,lr<<0x1
12759 + *[0-9a-f]*:   f3 e4 20 ba     eor r10,r9,r4<<0xb
12760 + *[0-9a-f]*:   e1 e1 21 f4     eor r4,r0,r1<<0x1f
12761 + *[0-9a-f]*:   e5 ec 20 d6     eor r6,r2,r12<<0xd
12762 +
12763 +[0-9a-f]* <eor3>:
12764 + *[0-9a-f]*:   ff ef 22 0f     eor pc,pc,pc
12765 + *[0-9a-f]*:   f9 ec 23 fc     eor r12,r12,r12>>0x1f
12766 + *[0-9a-f]*:   eb e5 23 05     eor r5,r5,r5>>0x10
12767 + *[0-9a-f]*:   e9 e4 22 f4     eor r4,r4,r4>>0xf
12768 + *[0-9a-f]*:   fd ee 22 1e     eor lr,lr,lr>>0x1
12769 + *[0-9a-f]*:   eb e5 23 65     eor r5,r5,r5>>0x16
12770 + *[0-9a-f]*:   e3 ee 22 3a     eor r10,r1,lr>>0x3
12771 + *[0-9a-f]*:   fd ed 23 a7     eor r7,lr,sp>>0x1a
12772 +
12773 +[0-9a-f]* <sthh_w2>:
12774 + *[0-9a-f]*:   ff ef 8f 0f     sthh\.w pc\[pc\],pc:b,pc:b
12775 + *[0-9a-f]*:   f9 ec bc 3c     sthh\.w r12\[r12<<0x3\],r12:t,r12:t
12776 + *[0-9a-f]*:   eb e5 b5 25     sthh\.w r5\[r5<<0x2\],r5:t,r5:t
12777 + *[0-9a-f]*:   e9 e4 84 14     sthh\.w r4\[r4<<0x1\],r4:b,r4:b
12778 + *[0-9a-f]*:   fd ee be 1e     sthh\.w lr\[lr<<0x1\],lr:t,lr:t
12779 + *[0-9a-f]*:   e3 ec b6 3d     sthh\.w sp\[r6<<0x3\],r1:t,r12:t
12780 + *[0-9a-f]*:   f3 e9 b6 06     sthh\.w r6\[r6\],r9:t,r9:t
12781 + *[0-9a-f]*:   e1 eb 93 0a     sthh\.w r10\[r3\],r0:b,r11:t
12782 +
12783 +[0-9a-f]* <sthh_w1>:
12784 + *[0-9a-f]*:   ff ef c0 0f     sthh\.w pc\[0x0\],pc:b,pc:b
12785 + *[0-9a-f]*:   f9 ec ff fc     sthh\.w r12\[0x3fc\],r12:t,r12:t
12786 + *[0-9a-f]*:   eb e5 f8 05     sthh\.w r5\[0x200\],r5:t,r5:t
12787 + *[0-9a-f]*:   e9 e4 c7 f4     sthh\.w r4\[0x1fc\],r4:b,r4:b
12788 + *[0-9a-f]*:   fd ee f0 1e     sthh\.w lr\[0x4\],lr:t,lr:t
12789 + *[0-9a-f]*:   f3 e0 e6 54     sthh\.w r4\[0x194\],r9:t,r0:b
12790 + *[0-9a-f]*:   e5 ea e5 78     sthh\.w r8\[0x15c\],r2:t,r10:b
12791 + *[0-9a-f]*:   f3 e2 c2 bd     sthh\.w sp\[0xac\],r9:b,r2:b
12792 +
12793 +[0-9a-f]* <cop>:
12794 + *[0-9a-f]*:   e1 a0 00 00     cop cp0,cr0,cr0,cr0,0x0
12795 + *[0-9a-f]*:   e7 af ff ff     cop cp7,cr15,cr15,cr15,0x7f
12796 + *[0-9a-f]*:   e3 a8 75 55     cop cp3,cr5,cr5,cr5,0x31
12797 + *[0-9a-f]*:   e3 a8 44 44     cop cp2,cr4,cr4,cr4,0x30
12798 + *[0-9a-f]*:   e5 ad a8 37     cop cp5,cr8,cr3,cr7,0x5a
12799 +
12800 +[0-9a-f]* <ldc_w1>:
12801 + *[0-9a-f]*:   e9 a0 00 00     ldc\.w cp0,cr0,r0\[0x0\]
12802 + *[0-9a-f]*:   e9 af ef ff     ldc\.w cp7,cr15,pc\[0x3fc\]
12803 + *[0-9a-f]*:   e9 a5 65 80     ldc\.w cp3,cr5,r5\[0x200\]
12804 + *[0-9a-f]*:   e9 a4 44 7f     ldc\.w cp2,cr4,r4\[0x1fc\]
12805 + *[0-9a-f]*:   e9 ad 89 24     ldc\.w cp4,cr9,sp\[0x90\]
12806 +
12807 +[0-9a-f]* <ldc_w2>:
12808 + *[0-9a-f]*:   ef a0 00 40     ldc\.w cp0,cr0,--r0
12809 + *[0-9a-f]*:   ef af ef 40     ldc\.w cp7,cr15,--pc
12810 + *[0-9a-f]*:   ef a5 65 40     ldc\.w cp3,cr5,--r5
12811 + *[0-9a-f]*:   ef a4 44 40     ldc\.w cp2,cr4,--r4
12812 + *[0-9a-f]*:   ef ad 89 40     ldc\.w cp4,cr9,--sp
12813 +
12814 +[0-9a-f]* <ldc_w3>:
12815 + *[0-9a-f]*:   ef a0 10 00     ldc\.w cp0,cr0,r0\[r0\]
12816 + *[0-9a-f]*:   ef af ff 3f     ldc\.w cp7,cr15,pc\[pc<<0x3\]
12817 + *[0-9a-f]*:   ef a5 75 24     ldc\.w cp3,cr5,r5\[r4<<0x2\]
12818 + *[0-9a-f]*:   ef a4 54 13     ldc\.w cp2,cr4,r4\[r3<<0x1\]
12819 + *[0-9a-f]*:   ef ad 99 0c     ldc\.w cp4,cr9,sp\[r12\]
12820 +
12821 +[0-9a-f]* <ldc_d1>:
12822 + *[0-9a-f]*:   e9 a0 10 00     ldc\.d cp0,cr0,r0\[0x0\]
12823 + *[0-9a-f]*:   e9 af fe ff     ldc\.d cp7,cr14,pc\[0x3fc\]
12824 + *[0-9a-f]*:   e9 a5 76 80     ldc\.d cp3,cr6,r5\[0x200\]
12825 + *[0-9a-f]*:   e9 a4 54 7f     ldc\.d cp2,cr4,r4\[0x1fc\]
12826 + *[0-9a-f]*:   e9 ad 98 24     ldc\.d cp4,cr8,sp\[0x90\]
12827 +
12828 +[0-9a-f]* <ldc_d2>:
12829 + *[0-9a-f]*:   ef a0 00 50     ldc\.d cp0,cr0,--r0
12830 + *[0-9a-f]*:   ef af ee 50     ldc\.d cp7,cr14,--pc
12831 + *[0-9a-f]*:   ef a5 66 50     ldc\.d cp3,cr6,--r5
12832 + *[0-9a-f]*:   ef a4 44 50     ldc\.d cp2,cr4,--r4
12833 + *[0-9a-f]*:   ef ad 88 50     ldc\.d cp4,cr8,--sp
12834 +
12835 +[0-9a-f]* <ldc_d3>:
12836 + *[0-9a-f]*:   ef a0 10 40     ldc\.d cp0,cr0,r0\[r0\]
12837 + *[0-9a-f]*:   ef af fe 7f     ldc\.d cp7,cr14,pc\[pc<<0x3\]
12838 + *[0-9a-f]*:   ef a5 76 64     ldc\.d cp3,cr6,r5\[r4<<0x2\]
12839 + *[0-9a-f]*:   ef a4 54 53     ldc\.d cp2,cr4,r4\[r3<<0x1\]
12840 + *[0-9a-f]*:   ef ad 98 4c     ldc\.d cp4,cr8,sp\[r12\]
12841 +
12842 +[0-9a-f]* <stc_w1>:
12843 + *[0-9a-f]*:   eb a0 00 00     stc\.w cp0,r0\[0x0\],cr0
12844 + *[0-9a-f]*:   eb af ef ff     stc\.w cp7,pc\[0x3fc\],cr15
12845 + *[0-9a-f]*:   eb a5 65 80     stc\.w cp3,r5\[0x200\],cr5
12846 + *[0-9a-f]*:   eb a4 44 7f     stc\.w cp2,r4\[0x1fc\],cr4
12847 + *[0-9a-f]*:   eb ad 89 24     stc\.w cp4,sp\[0x90\],cr9
12848 +
12849 +[0-9a-f]* <stc_w2>:
12850 + *[0-9a-f]*:   ef a0 00 60     stc\.w cp0,r0\+\+,cr0
12851 + *[0-9a-f]*:   ef af ef 60     stc\.w cp7,pc\+\+,cr15
12852 + *[0-9a-f]*:   ef a5 65 60     stc\.w cp3,r5\+\+,cr5
12853 + *[0-9a-f]*:   ef a4 44 60     stc\.w cp2,r4\+\+,cr4
12854 + *[0-9a-f]*:   ef ad 89 60     stc\.w cp4,sp\+\+,cr9
12855 +
12856 +[0-9a-f]* <stc_w3>:
12857 + *[0-9a-f]*:   ef a0 10 80     stc\.w cp0,r0\[r0\],cr0
12858 + *[0-9a-f]*:   ef af ff bf     stc\.w cp7,pc\[pc<<0x3\],cr15
12859 + *[0-9a-f]*:   ef a5 75 a4     stc\.w cp3,r5\[r4<<0x2\],cr5
12860 + *[0-9a-f]*:   ef a4 54 93     stc\.w cp2,r4\[r3<<0x1\],cr4
12861 + *[0-9a-f]*:   ef ad 99 8c     stc\.w cp4,sp\[r12\],cr9
12862 +
12863 +[0-9a-f]* <stc_d1>:
12864 + *[0-9a-f]*:   eb a0 10 00     stc\.d cp0,r0\[0x0\],cr0
12865 + *[0-9a-f]*:   eb af fe ff     stc\.d cp7,pc\[0x3fc\],cr14
12866 + *[0-9a-f]*:   eb a5 76 80     stc\.d cp3,r5\[0x200\],cr6
12867 + *[0-9a-f]*:   eb a4 54 7f     stc\.d cp2,r4\[0x1fc\],cr4
12868 + *[0-9a-f]*:   eb ad 98 24     stc\.d cp4,sp\[0x90\],cr8
12869 +
12870 +[0-9a-f]* <stc_d2>:
12871 + *[0-9a-f]*:   ef a0 00 70     stc\.d cp0,r0\+\+,cr0
12872 + *[0-9a-f]*:   ef af ee 70     stc\.d cp7,pc\+\+,cr14
12873 + *[0-9a-f]*:   ef a5 66 70     stc\.d cp3,r5\+\+,cr6
12874 + *[0-9a-f]*:   ef a4 44 70     stc\.d cp2,r4\+\+,cr4
12875 + *[0-9a-f]*:   ef ad 88 70     stc\.d cp4,sp\+\+,cr8
12876 +
12877 +[0-9a-f]* <stc_d3>:
12878 + *[0-9a-f]*:   ef a0 10 c0     stc\.d cp0,r0\[r0\],cr0
12879 + *[0-9a-f]*:   ef af fe ff     stc\.d cp7,pc\[pc<<0x3\],cr14
12880 + *[0-9a-f]*:   ef a5 76 e4     stc\.d cp3,r5\[r4<<0x2\],cr6
12881 + *[0-9a-f]*:   ef a4 54 d3     stc\.d cp2,r4\[r3<<0x1\],cr4
12882 + *[0-9a-f]*:   ef ad 98 cc     stc\.d cp4,sp\[r12\],cr8
12883 +
12884 +[0-9a-f]* <ldc0_w>:
12885 + *[0-9a-f]*:   f1 a0 00 00     ldc0\.w cr0,r0\[0x0\]
12886 + *[0-9a-f]*:   f1 af ff ff     ldc0\.w cr15,pc\[0x3ffc\]
12887 + *[0-9a-f]*:   f1 a5 85 00     ldc0\.w cr5,r5\[0x2000\]
12888 + *[0-9a-f]*:   f1 a4 74 ff     ldc0\.w cr4,r4\[0x1ffc\]
12889 + *[0-9a-f]*:   f1 ad 09 93     ldc0\.w cr9,sp\[0x24c\]
12890 +
12891 +[0-9a-f]* <ldc0_d>:
12892 + *[0-9a-f]*:   f3 a0 00 00     ldc0\.d cr0,r0\[0x0\]
12893 + *[0-9a-f]*:   f3 af fe ff     ldc0\.d cr14,pc\[0x3ffc\]
12894 + *[0-9a-f]*:   f3 a5 86 00     ldc0\.d cr6,r5\[0x2000\]
12895 + *[0-9a-f]*:   f3 a4 74 ff     ldc0\.d cr4,r4\[0x1ffc\]
12896 + *[0-9a-f]*:   f3 ad 08 93     ldc0\.d cr8,sp\[0x24c\]
12897 +
12898 +[0-9a-f]* <stc0_w>:
12899 + *[0-9a-f]*:   f5 a0 00 00     stc0\.w r0\[0x0\],cr0
12900 + *[0-9a-f]*:   f5 af ff ff     stc0\.w pc\[0x3ffc\],cr15
12901 + *[0-9a-f]*:   f5 a5 85 00     stc0\.w r5\[0x2000\],cr5
12902 + *[0-9a-f]*:   f5 a4 74 ff     stc0\.w r4\[0x1ffc\],cr4
12903 + *[0-9a-f]*:   f5 ad 09 93     stc0\.w sp\[0x24c\],cr9
12904 +
12905 +[0-9a-f]* <stc0_d>:
12906 + *[0-9a-f]*:   f7 a0 00 00     stc0\.d r0\[0x0\],cr0
12907 + *[0-9a-f]*:   f7 af fe ff     stc0\.d pc\[0x3ffc\],cr14
12908 + *[0-9a-f]*:   f7 a5 86 00     stc0\.d r5\[0x2000\],cr6
12909 + *[0-9a-f]*:   f7 a4 74 ff     stc0\.d r4\[0x1ffc\],cr4
12910 + *[0-9a-f]*:   f7 ad 08 93     stc0\.d sp\[0x24c\],cr8
12911 +
12912 +[0-9a-f]* <memc>:
12913 + *[0-9a-f]*:   f6 10 00 00     memc 0,0x0
12914 + *[0-9a-f]*:   f6 1f ff ff     memc -4,0x1f
12915 + *[0-9a-f]*:   f6 18 40 00     memc -65536,0x10
12916 + *[0-9a-f]*:   f6 17 bf ff     memc 65532,0xf
12917 +
12918 +[0-9a-f]* <mems>:
12919 + *[0-9a-f]*:   f8 10 00 00     mems 0,0x0
12920 + *[0-9a-f]*:   f8 1f ff ff     mems -4,0x1f
12921 + *[0-9a-f]*:   f8 18 40 00     mems -65536,0x10
12922 + *[0-9a-f]*:   f8 17 bf ff     mems 65532,0xf
12923 +
12924 +[0-9a-f]* <memt>:
12925 + *[0-9a-f]*:   fa 10 00 00     memt 0,0x0
12926 + *[0-9a-f]*:   fa 1f ff ff     memt -4,0x1f
12927 + *[0-9a-f]*:   fa 18 40 00     memt -65536,0x10
12928 + *[0-9a-f]*:   fa 17 bf ff     memt 65532,0xf
12929 +
12930 +[0-9a-f]* <stcond>:
12931 + *[0-9a-f]*:   e1 70 00 00     stcond r0\[0\],r0
12932 + *[0-9a-f]*:   ff 7f ff ff     stcond pc\[-1\],pc
12933 + *[0-9a-f]*:   f1 77 80 00     stcond r8\[-32768\],r7
12934 + *[0-9a-f]*:   ef 78 7f ff     stcond r7\[32767\],r8
12935 + *[0-9a-f]*:   eb 7a 12 34     stcond r5\[4660\],r10
12936 +
12937 +[0-9a-f]* <ldcm_w>:
12938 + *[0-9a-f]*:   ed af 00 ff     ldcm\.w cp0,pc,cr0-cr7
12939 + *[0-9a-f]*:   ed a0 e0 01     ldcm\.w cp7,r0,cr0
12940 + *[0-9a-f]*:   ed a4 90 7f     ldcm\.w cp4,r4\+\+,cr0-cr6
12941 + *[0-9a-f]*:   ed a7 60 80     ldcm\.w cp3,r7,cr7
12942 + *[0-9a-f]*:   ed ac 30 72     ldcm\.w cp1,r12\+\+,cr1,cr4-cr6
12943 + *[0-9a-f]*:   ed af 01 ff     ldcm\.w cp0,pc,cr8-cr15
12944 + *[0-9a-f]*:   ed a0 e1 01     ldcm\.w cp7,r0,cr8
12945 + *[0-9a-f]*:   ed a4 91 7f     ldcm\.w cp4,r4\+\+,cr8-cr14
12946 + *[0-9a-f]*:   ed a7 61 80     ldcm\.w cp3,r7,cr15
12947 + *[0-9a-f]*:   ed ac 31 72     ldcm\.w cp1,r12\+\+,cr9,cr12-cr14
12948 +
12949 +[0-9a-f]* <ldcm_d>:
12950 + *[0-9a-f]*:   ed af 04 ff     ldcm\.d cp0,pc,cr0-cr15
12951 + *[0-9a-f]*:   ed a0 e4 01     ldcm\.d cp7,r0,cr0-cr1
12952 + *[0-9a-f]*:   ed a4 94 7f     ldcm\.d cp4,r4\+\+,cr0-cr13
12953 + *[0-9a-f]*:   ed a7 64 80     ldcm\.d cp3,r7,cr14-cr15
12954 + *[0-9a-f]*:   ed ac 54 93     ldcm\.d cp2,r12\+\+,cr0-cr3,cr8-cr9,cr14-cr15
12955 +
12956 +[0-9a-f]* <stcm_w>:
12957 + *[0-9a-f]*:   ed af 02 ff     stcm\.w cp0,pc,cr0-cr7
12958 + *[0-9a-f]*:   ed a0 e2 01     stcm\.w cp7,r0,cr0
12959 + *[0-9a-f]*:   ed a4 92 7f     stcm\.w cp4,--r4,cr0-cr6
12960 + *[0-9a-f]*:   ed a7 62 80     stcm\.w cp3,r7,cr7
12961 + *[0-9a-f]*:   ed ac 32 72     stcm\.w cp1,--r12,cr1,cr4-cr6
12962 + *[0-9a-f]*:   ed af 03 ff     stcm\.w cp0,pc,cr8-cr15
12963 + *[0-9a-f]*:   ed a0 e3 01     stcm\.w cp7,r0,cr8
12964 + *[0-9a-f]*:   ed a4 93 7f     stcm\.w cp4,--r4,cr8-cr14
12965 + *[0-9a-f]*:   ed a7 63 80     stcm\.w cp3,r7,cr15
12966 + *[0-9a-f]*:   ed ac 33 72     stcm\.w cp1,--r12,cr9,cr12-cr14
12967 +
12968 +[0-9a-f]* <stcm_d>:
12969 + *[0-9a-f]*:   ed af 05 ff     stcm\.d cp0,pc,cr0-cr15
12970 + *[0-9a-f]*:   ed a0 e5 01     stcm\.d cp7,r0,cr0-cr1
12971 + *[0-9a-f]*:   ed a4 95 7f     stcm\.d cp4,--r4,cr0-cr13
12972 + *[0-9a-f]*:   ed a7 65 80     stcm\.d cp3,r7,cr14-cr15
12973 + *[0-9a-f]*:   ed ac 55 93     stcm\.d cp2,--r12,cr0-cr3,cr8-cr9,cr14-cr15
12974 +
12975 +[0-9a-f]* <mvcr_w>:
12976 + *[0-9a-f]*:   ef af ef 00     mvcr\.w cp7,pc,cr15
12977 + *[0-9a-f]*:   ef a0 00 00     mvcr\.w cp0,r0,cr0
12978 + *[0-9a-f]*:   ef af 0f 00     mvcr\.w cp0,pc,cr15
12979 + *[0-9a-f]*:   ef a0 ef 00     mvcr\.w cp7,r0,cr15
12980 + *[0-9a-f]*:   ef af e0 00     mvcr\.w cp7,pc,cr0
12981 + *[0-9a-f]*:   ef a7 88 00     mvcr\.w cp4,r7,cr8
12982 + *[0-9a-f]*:   ef a8 67 00     mvcr\.w cp3,r8,cr7
12983 +
12984 +[0-9a-f]* <mvcr_d>:
12985 + *[0-9a-f]*:   ef ae ee 10     mvcr\.d cp7,lr,cr14
12986 + *[0-9a-f]*:   ef a0 00 10     mvcr\.d cp0,r0,cr0
12987 + *[0-9a-f]*:   ef ae 0e 10     mvcr\.d cp0,lr,cr14
12988 + *[0-9a-f]*:   ef a0 ee 10     mvcr\.d cp7,r0,cr14
12989 + *[0-9a-f]*:   ef ae e0 10     mvcr\.d cp7,lr,cr0
12990 + *[0-9a-f]*:   ef a6 88 10     mvcr\.d cp4,r6,cr8
12991 + *[0-9a-f]*:   ef a8 66 10     mvcr\.d cp3,r8,cr6
12992 +
12993 +[0-9a-f]* <mvrc_w>:
12994 + *[0-9a-f]*:   ef af ef 20     mvrc\.w cp7,cr15,pc
12995 + *[0-9a-f]*:   ef a0 00 20     mvrc\.w cp0,cr0,r0
12996 + *[0-9a-f]*:   ef af 0f 20     mvrc\.w cp0,cr15,pc
12997 + *[0-9a-f]*:   ef a0 ef 20     mvrc\.w cp7,cr15,r0
12998 + *[0-9a-f]*:   ef af e0 20     mvrc\.w cp7,cr0,pc
12999 + *[0-9a-f]*:   ef a7 88 20     mvrc\.w cp4,cr8,r7
13000 + *[0-9a-f]*:   ef a8 67 20     mvrc\.w cp3,cr7,r8
13001 +
13002 +[0-9a-f]* <mvrc_d>:
13003 + *[0-9a-f]*:   ef ae ee 30     mvrc\.d cp7,cr14,lr
13004 + *[0-9a-f]*:   ef a0 00 30     mvrc\.d cp0,cr0,r0
13005 + *[0-9a-f]*:   ef ae 0e 30     mvrc\.d cp0,cr14,lr
13006 + *[0-9a-f]*:   ef a0 ee 30     mvrc\.d cp7,cr14,r0
13007 + *[0-9a-f]*:   ef ae e0 30     mvrc\.d cp7,cr0,lr
13008 + *[0-9a-f]*:   ef a6 88 30     mvrc\.d cp4,cr8,r6
13009 + *[0-9a-f]*:   ef a8 66 30     mvrc\.d cp3,cr6,r8
13010 +
13011 +[0-9a-f]* <bfexts>:
13012 + *[0-9a-f]*:   ff df b3 ff     bfexts pc,pc,0x1f,0x1f
13013 + *[0-9a-f]*:   e1 d0 b0 00     bfexts r0,r0,0x0,0x0
13014 + *[0-9a-f]*:   e1 df b3 ff     bfexts r0,pc,0x1f,0x1f
13015 + *[0-9a-f]*:   ff d0 b3 ff     bfexts pc,r0,0x1f,0x1f
13016 + *[0-9a-f]*:   ff df b0 1f     bfexts pc,pc,0x0,0x1f
13017 + *[0-9a-f]*:   ff df b3 e0     bfexts pc,pc,0x1f,0x0
13018 + *[0-9a-f]*:   ef d8 b1 f0     bfexts r7,r8,0xf,0x10
13019 + *[0-9a-f]*:   f1 d7 b2 0f     bfexts r8,r7,0x10,0xf
13020 +
13021 +[0-9a-f]* <bfextu>:
13022 + *[0-9a-f]*:   ff df c3 ff     bfextu pc,pc,0x1f,0x1f
13023 + *[0-9a-f]*:   e1 d0 c0 00     bfextu r0,r0,0x0,0x0
13024 + *[0-9a-f]*:   e1 df c3 ff     bfextu r0,pc,0x1f,0x1f
13025 + *[0-9a-f]*:   ff d0 c3 ff     bfextu pc,r0,0x1f,0x1f
13026 + *[0-9a-f]*:   ff df c0 1f     bfextu pc,pc,0x0,0x1f
13027 + *[0-9a-f]*:   ff df c3 e0     bfextu pc,pc,0x1f,0x0
13028 + *[0-9a-f]*:   ef d8 c1 f0     bfextu r7,r8,0xf,0x10
13029 + *[0-9a-f]*:   f1 d7 c2 0f     bfextu r8,r7,0x10,0xf
13030 +
13031 +[0-9a-f]* <bfins>:
13032 + *[0-9a-f]*:   ff df d3 ff     bfins pc,pc,0x1f,0x1f
13033 + *[0-9a-f]*:   e1 d0 d0 00     bfins r0,r0,0x0,0x0
13034 + *[0-9a-f]*:   e1 df d3 ff     bfins r0,pc,0x1f,0x1f
13035 + *[0-9a-f]*:   ff d0 d3 ff     bfins pc,r0,0x1f,0x1f
13036 + *[0-9a-f]*:   ff df d0 1f     bfins pc,pc,0x0,0x1f
13037 + *[0-9a-f]*:   ff df d3 e0     bfins pc,pc,0x1f,0x0
13038 + *[0-9a-f]*:   ef d8 d1 f0     bfins r7,r8,0xf,0x10
13039 + *[0-9a-f]*:   f1 d7 d2 0f     bfins r8,r7,0x10,0xf
13040 +
13041 +[0-9a-f]* <rsubc>:
13042 + *[0-9a-f]*:   fb bf 00 00     rsubeq pc,0
13043 + *[0-9a-f]*:   fb bc 0f ff     rsubal r12,-1
13044 + *[0-9a-f]*:   fb b5 08 80     rsubls r5,-128
13045 + *[0-9a-f]*:   fb b4 07 7f     rsubpl r4,127
13046 + *[0-9a-f]*:   fb be 01 01     rsubne lr,1
13047 + *[0-9a-f]*:   fb bc 08 76     rsubls r12,118
13048 + *[0-9a-f]*:   fb be 0d f4     rsubvc lr,-12
13049 + *[0-9a-f]*:   fb b4 06 f3     rsubmi r4,-13
13050 +
13051 +[0-9a-f]* <addc>:
13052 + *[0-9a-f]*:   ff df e0 0f     addeq pc,pc,pc
13053 + *[0-9a-f]*:   f9 dc ef 0c     addal r12,r12,r12
13054 + *[0-9a-f]*:   eb d5 e8 05     addls r5,r5,r5
13055 + *[0-9a-f]*:   e9 d4 e7 04     addpl r4,r4,r4
13056 + *[0-9a-f]*:   fd de e1 0e     addne lr,lr,lr
13057 + *[0-9a-f]*:   e5 d1 e8 0a     addls r10,r2,r1
13058 + *[0-9a-f]*:   f1 db ed 0c     addvc r12,r8,r11
13059 + *[0-9a-f]*:   ef d0 e6 0a     addmi r10,r7,r0
13060 +
13061 +[0-9a-f]* <subc2>:
13062 + *[0-9a-f]*:   ff df e0 1f     subeq pc,pc,pc
13063 + *[0-9a-f]*:   f9 dc ef 1c     subal r12,r12,r12
13064 + *[0-9a-f]*:   eb d5 e8 15     subls r5,r5,r5
13065 + *[0-9a-f]*:   e9 d4 e7 14     subpl r4,r4,r4
13066 + *[0-9a-f]*:   fd de e1 1e     subne lr,lr,lr
13067 + *[0-9a-f]*:   e5 d1 e8 1a     subls r10,r2,r1
13068 + *[0-9a-f]*:   f1 db ed 1c     subvc r12,r8,r11
13069 + *[0-9a-f]*:   ef d0 e6 1a     submi r10,r7,r0
13070 +
13071 +[0-9a-f]* <andc>:
13072 + *[0-9a-f]*:   ff df e0 2f     andeq pc,pc,pc
13073 + *[0-9a-f]*:   f9 dc ef 2c     andal r12,r12,r12
13074 + *[0-9a-f]*:   eb d5 e8 25     andls r5,r5,r5
13075 + *[0-9a-f]*:   e9 d4 e7 24     andpl r4,r4,r4
13076 + *[0-9a-f]*:   fd de e1 2e     andne lr,lr,lr
13077 + *[0-9a-f]*:   e5 d1 e8 2a     andls r10,r2,r1
13078 + *[0-9a-f]*:   f1 db ed 2c     andvc r12,r8,r11
13079 + *[0-9a-f]*:   ef d0 e6 2a     andmi r10,r7,r0
13080 +
13081 +[0-9a-f]* <orc>:
13082 + *[0-9a-f]*:   ff df e0 3f     oreq pc,pc,pc
13083 + *[0-9a-f]*:   f9 dc ef 3c     oral r12,r12,r12
13084 + *[0-9a-f]*:   eb d5 e8 35     orls r5,r5,r5
13085 + *[0-9a-f]*:   e9 d4 e7 34     orpl r4,r4,r4
13086 + *[0-9a-f]*:   fd de e1 3e     orne lr,lr,lr
13087 + *[0-9a-f]*:   e5 d1 e8 3a     orls r10,r2,r1
13088 + *[0-9a-f]*:   f1 db ed 3c     orvc r12,r8,r11
13089 + *[0-9a-f]*:   ef d0 e6 3a     ormi r10,r7,r0
13090 +
13091 +[0-9a-f]* <eorc>:
13092 + *[0-9a-f]*:   ff df e0 4f     eoreq pc,pc,pc
13093 + *[0-9a-f]*:   f9 dc ef 4c     eoral r12,r12,r12
13094 + *[0-9a-f]*:   eb d5 e8 45     eorls r5,r5,r5
13095 + *[0-9a-f]*:   e9 d4 e7 44     eorpl r4,r4,r4
13096 + *[0-9a-f]*:   fd de e1 4e     eorne lr,lr,lr
13097 + *[0-9a-f]*:   e5 d1 e8 4a     eorls r10,r2,r1
13098 + *[0-9a-f]*:   f1 db ed 4c     eorvc r12,r8,r11
13099 + *[0-9a-f]*:   ef d0 e6 4a     eormi r10,r7,r0
13100 +
13101 +[0-9a-f]* <ldcond>:
13102 + *[0-9a-f]*:   ff ff 01 ff     ld.weq  pc,pc[0x7fc]
13103 + *[0-9a-f]*:   f9 fc f3 ff     ld.shal r12,r12[0x3fe]
13104 + *[0-9a-f]*:   eb f5 84 00     ld.shls r5,r5[0x0]
13105 + *[0-9a-f]*:   e9 f4 79 ff     ld.ubpl r4,r4[0x1ff]
13106 + *[0-9a-f]*:   fd fe 16 00     ld.sbne lr,lr[0x0]
13107 + *[0-9a-f]*:   e5 fa 80 00     ld.wls  r10,r2[0x0]
13108 + *[0-9a-f]*:   f1 fc d3 ff     ld.shvc r12,r8[0x3fe]
13109 + *[0-9a-f]*:   ef fa 68 01     ld.ubmi r10,r7[0x1]
13110 +
13111 +[0-9a-f]* <stcond2>:
13112 + *[0-9a-f]*:   ff ff 0b ff     st.weq pc[0x7fc],pc
13113 + *[0-9a-f]*:   f9 fc fd ff     st.hal r12[0x3fe],r12
13114 + *[0-9a-f]*:   eb f5 8c 00     st.hls r5[0x0],r5
13115 + *[0-9a-f]*:   e9 f4 7f ff     st.bpl r4[0x1ff],r4
13116 + *[0-9a-f]*:   fd fe 1e 00     st.bne lr[0x0],lr
13117 + *[0-9a-f]*:   e5 fa 8a 00     st.wls r2[0x0],r10
13118 + *[0-9a-f]*:   f1 fc dd ff     st.hvc r8[0x3fe],r12
13119 + *[0-9a-f]*:   ef fa 6e 01     st.bmi r7[0x1],r10
13120 +
13121 +[0-9a-f]* <movh>:
13122 + *[0-9a-f]*:   fc 1f ff ff     movh pc,0xffff
13123 + *[0-9a-f]*:   fc 10 00 00     movh r0,0x0
13124 + *[0-9a-f]*:   fc 15 00 01     movh r5,0x1
13125 + *[0-9a-f]*:   fc 1c 7f ff     movh r12,0x7fff
13126 +
13127 --- /dev/null
13128 +++ b/gas/testsuite/gas/avr32/allinsn.exp
13129 @@ -0,0 +1,5 @@
13130 +# AVR32 assembler testsuite. -*- Tcl -*-
13131 +
13132 +if [istarget avr32-*-*] {
13133 +    run_dump_test "allinsn"
13134 +}
13135 --- /dev/null
13136 +++ b/gas/testsuite/gas/avr32/allinsn.s
13137 @@ -0,0 +1,3330 @@
13138 + .data
13139 +foodata: .word 42
13140 + .text
13141 +footext:
13142 +       .text
13143 +       .global ld_d5
13144 +ld_d5:
13145 +       ld.d lr,pc[pc<<3]
13146 +       ld.d r0,r0[r0<<0]
13147 +       ld.d r6,r5[r5<<2]
13148 +       ld.d r4,r4[r4<<1]
13149 +       ld.d lr,lr[lr<<1]
13150 +       ld.d r10,r3[sp<<2]
13151 +       ld.d r8,r10[r6<<2]
13152 +       ld.d r2,r7[r9<<0]
13153 +       .text
13154 +       .global ld_w5
13155 +ld_w5:
13156 +       ld.w pc,pc[pc<<0]
13157 +       ld.w r12,r12[r12<<3]
13158 +       ld.w r5,r5[r5<<2]
13159 +       ld.w r4,r4[r4<<1]
13160 +       ld.w lr,lr[lr<<1]
13161 +       ld.w r2,r9[r9<<0]
13162 +       ld.w r11,r2[r6<<0]
13163 +       ld.w r0,r2[sp<<3]
13164 +       .text
13165 +       .global ld_sh5
13166 +ld_sh5:
13167 +       ld.sh pc,pc[pc<<0]
13168 +       ld.sh r12,r12[r12<<3]
13169 +       ld.sh r5,r5[r5<<2]
13170 +       ld.sh r4,r4[r4<<1]
13171 +       ld.sh lr,lr[lr<<1]
13172 +       ld.sh r11,r0[pc<<2]
13173 +       ld.sh r10,sp[r6<<2]
13174 +       ld.sh r12,r2[r2<<0]
13175 +       .text
13176 +       .global ld_uh5
13177 +ld_uh5:
13178 +       ld.uh pc,pc[pc<<0]
13179 +       ld.uh r12,r12[r12<<3]
13180 +       ld.uh r5,r5[r5<<2]
13181 +       ld.uh r4,r4[r4<<1]
13182 +       ld.uh lr,lr[lr<<1]
13183 +       ld.uh r8,pc[lr<<3]
13184 +       ld.uh r6,r1[pc<<1]
13185 +       ld.uh r6,lr[sp<<1]
13186 +       .text
13187 +       .global ld_sb2
13188 +ld_sb2:
13189 +       ld.sb pc,pc[pc<<0]
13190 +       ld.sb r12,r12[r12<<3]
13191 +       ld.sb r5,r5[r5<<2]
13192 +       ld.sb r4,r4[r4<<1]
13193 +       ld.sb lr,lr[lr<<1]
13194 +       ld.sb r9,r1[pc<<3]
13195 +       ld.sb r0,r3[r11<<1]
13196 +       ld.sb r10,r5[r5<<1]
13197 +       .text
13198 +       .global ld_ub5
13199 +ld_ub5:
13200 +       ld.ub pc,pc[pc<<0]
13201 +       ld.ub r12,r12[r12<<3]
13202 +       ld.ub r5,r5[r5<<2]
13203 +       ld.ub r4,r4[r4<<1]
13204 +       ld.ub lr,lr[lr<<1]
13205 +       ld.ub r6,r12[r7<<3]
13206 +       ld.ub r2,r6[r12<<0]
13207 +       ld.ub r0,r7[r11<<1]
13208 +       .text
13209 +       .global st_d5
13210 +st_d5:
13211 +       st.d pc[pc<<0],r14
13212 +       st.d r12[r12<<3],r12
13213 +       st.d r5[r5<<2],r6
13214 +       st.d r4[r4<<1],r4
13215 +       st.d lr[lr<<1],lr
13216 +       st.d r1[r9<<1],r4
13217 +       st.d r10[r2<<1],r4
13218 +       st.d r12[r6<<0],lr
13219 +       .text
13220 +       .global st_w5
13221 +st_w5:
13222 +       st.w pc[pc<<0],pc
13223 +       st.w r12[r12<<3],r12
13224 +       st.w r5[r5<<2],r5
13225 +       st.w r4[r4<<1],r4
13226 +       st.w lr[lr<<1],lr
13227 +       st.w r1[r10<<0],r3
13228 +       st.w r0[r10<<1],r9
13229 +       st.w r4[r5<<3],pc
13230 +       .text
13231 +       .global st_h5
13232 +st_h5:
13233 +       st.h pc[pc<<0],pc
13234 +       st.h r12[r12<<3],r12
13235 +       st.h r5[r5<<2],r5
13236 +       st.h r4[r4<<1],r4
13237 +       st.h lr[lr<<1],lr
13238 +       st.h r2[r9<<0],r11
13239 +       st.h r5[r1<<2],r12
13240 +       st.h pc[r8<<2],r3
13241 +       .text
13242 +       .global st_b5
13243 +st_b5:
13244 +       st.b pc[pc<<0],pc
13245 +       st.b r12[r12<<3],r12
13246 +       st.b r5[r5<<2],r5
13247 +       st.b r4[r4<<1],r4
13248 +       st.b lr[lr<<1],lr
13249 +       st.b r1[r8<<1],r6
13250 +       st.b lr[lr<<3],r1
13251 +       st.b r5[r0<<2],pc
13252 +       .text
13253 +       .global divs
13254 +divs:
13255 +       divs pc,pc,pc
13256 +       divs r12,r12,r12
13257 +       divs r5,r5,r5
13258 +       divs r4,r4,r4
13259 +       divs lr,lr,lr
13260 +       divs r3,pc,pc
13261 +       divs r9,r12,r2
13262 +       divs r7,r4,r1
13263 +       .text
13264 +       .global add1
13265 +add1:
13266 +       add pc,pc
13267 +       add r12,r12
13268 +       add r5,r5
13269 +       add r4,r4
13270 +       add lr,lr
13271 +       add r12,r9
13272 +       add r6,r3
13273 +       add r10,r12
13274 +       .text
13275 +       .global sub1
13276 +sub1:
13277 +       sub pc,pc
13278 +       sub r12,r12
13279 +       sub r5,r5
13280 +       sub r4,r4
13281 +       sub lr,lr
13282 +       sub lr,r6
13283 +       sub r0,sp
13284 +       sub r6,r12
13285 +       .text
13286 +       .global rsub1
13287 +rsub1:
13288 +       rsub pc,pc
13289 +       rsub r12,r12
13290 +       rsub r5,r5
13291 +       rsub r4,r4
13292 +       rsub lr,lr
13293 +       rsub r11,sp
13294 +       rsub r7,r4
13295 +       rsub r9,r1
13296 +       .text
13297 +       .global cp1
13298 +cp1:
13299 +       cp pc,pc
13300 +       cp r12,r12
13301 +       cp r5,r5
13302 +       cp r4,r4
13303 +       cp lr,lr
13304 +       cp r6,r2
13305 +       cp r0,r9
13306 +       cp r3,sp
13307 +       .text
13308 +       .global or1
13309 +or1:
13310 +       or pc,pc
13311 +       or r12,r12
13312 +       or r5,r5
13313 +       or r4,r4
13314 +       or lr,lr
13315 +       or r4,r9
13316 +       or r11,r4
13317 +       or r4,r0
13318 +       .text
13319 +       .global eor1
13320 +eor1:
13321 +       eor pc,pc
13322 +       eor r12,r12
13323 +       eor r5,r5
13324 +       eor r4,r4
13325 +       eor lr,lr
13326 +       eor r12,r11
13327 +       eor r0,r1
13328 +       eor r5,pc
13329 +       .text
13330 +       .global and1
13331 +and1:
13332 +       and pc,pc
13333 +       and r12,r12
13334 +       and r5,r5
13335 +       and r4,r4
13336 +       and lr,lr
13337 +       and r8,r1
13338 +       and r0,sp
13339 +       and r10,r5
13340 +       .text
13341 +       .global tst
13342 +tst:
13343 +       tst pc,pc
13344 +       tst r12,r12
13345 +       tst r5,r5
13346 +       tst r4,r4
13347 +       tst lr,lr
13348 +       tst r0,r12
13349 +       tst r10,r6
13350 +       tst sp,r4
13351 +       .text
13352 +       .global andn
13353 +andn:
13354 +       andn pc,pc
13355 +       andn r12,r12
13356 +       andn r5,r5
13357 +       andn r4,r4
13358 +       andn lr,lr
13359 +       andn r9,r12
13360 +       andn r11,sp
13361 +       andn r12,r5
13362 +       .text
13363 +       .global mov3
13364 +mov3:
13365 +       mov pc,pc
13366 +       mov r12,r12
13367 +       mov r5,r5
13368 +       mov r4,r4
13369 +       mov lr,lr
13370 +       mov r5,r9
13371 +       mov r11,r11
13372 +       mov r2,lr
13373 +       .text
13374 +       .global st_w1
13375 +st_w1:
13376 +       st.w pc++,pc
13377 +       st.w r12++,r12
13378 +       st.w r5++,r5
13379 +       st.w r4++,r4
13380 +       st.w lr++,lr
13381 +       st.w r1++,r11
13382 +       st.w sp++,r0
13383 +       st.w sp++,r1
13384 +       .text
13385 +       .global st_h1
13386 +st_h1:
13387 +       st.h pc++,pc
13388 +       st.h r12++,r12
13389 +       st.h r5++,r5
13390 +       st.h r4++,r4
13391 +       st.h lr++,lr
13392 +       st.h r12++,sp
13393 +       st.h r7++,lr
13394 +       st.h r7++,r4
13395 +       .text
13396 +       .global st_b1
13397 +st_b1:
13398 +       st.b pc++,pc
13399 +       st.b r12++,r12
13400 +       st.b r5++,r5
13401 +       st.b r4++,r4
13402 +       st.b lr++,lr
13403 +       st.b r9++,sp
13404 +       st.b r1++,sp
13405 +       st.b r0++,r4
13406 +       .text
13407 +       .global st_w2
13408 +st_w2:
13409 +       st.w --pc,pc
13410 +       st.w --r12,r12
13411 +       st.w --r5,r5
13412 +       st.w --r4,r4
13413 +       st.w --lr,lr
13414 +       st.w --r1,r7
13415 +       st.w --r3,r9
13416 +       st.w --r5,r5
13417 +       .text
13418 +       .global st_h2
13419 +st_h2:
13420 +       st.h --pc,pc
13421 +       st.h --r12,r12
13422 +       st.h --r5,r5
13423 +       st.h --r4,r4
13424 +       st.h --lr,lr
13425 +       st.h --r5,r7
13426 +       st.h --r8,r8
13427 +       st.h --r7,r2
13428 +       .text
13429 +       .global st_b2
13430 +st_b2:
13431 +       st.b --pc,pc
13432 +       st.b --r12,r12
13433 +       st.b --r5,r5
13434 +       st.b --r4,r4
13435 +       st.b --lr,lr
13436 +       st.b --sp,sp
13437 +       st.b --sp,r11
13438 +       st.b --r4,r5
13439 +       .text
13440 +       .global ld_w1
13441 +ld_w1:
13442 +       ld.w pc,pc++
13443 +       ld.w r12,r12++
13444 +       ld.w r5,r5++
13445 +       ld.w r4,r4++
13446 +       ld.w lr,lr++
13447 +       ld.w r3,r7++
13448 +       ld.w r3,lr++
13449 +       ld.w r12,r5++
13450 +       .text
13451 +       .global ld_sh1
13452 +ld_sh1:
13453 +       ld.sh pc,pc++
13454 +       ld.sh r12,r12++
13455 +       ld.sh r5,r5++
13456 +       ld.sh r4,r4++
13457 +       ld.sh lr,lr++
13458 +       ld.sh r11,r2++
13459 +       ld.sh r2,r8++
13460 +       ld.sh r7,r6++
13461 +       .text
13462 +       .global ld_uh1
13463 +ld_uh1:
13464 +       ld.uh pc,pc++
13465 +       ld.uh r12,r12++
13466 +       ld.uh r5,r5++
13467 +       ld.uh r4,r4++
13468 +       ld.uh lr,lr++
13469 +       ld.uh r6,r7++
13470 +       ld.uh r10,r11++
13471 +       ld.uh lr,r4++
13472 +       .text
13473 +       .global ld_ub1
13474 +ld_ub1:
13475 +       ld.ub pc,pc++
13476 +       ld.ub r12,r12++
13477 +       ld.ub r5,r5++
13478 +       ld.ub r4,r4++
13479 +       ld.ub lr,lr++
13480 +       ld.ub r8,lr++
13481 +       ld.ub r12,r12++
13482 +       ld.ub r11,r10++
13483 +       .text
13484 +       .global ld_w2
13485 +ld_w2:
13486 +       ld.w pc,--pc
13487 +       ld.w r12,--r12
13488 +       ld.w r5,--r5
13489 +       ld.w r4,--r4
13490 +       ld.w lr,--lr
13491 +       ld.w r10,--lr
13492 +       ld.w r12,--r9
13493 +       ld.w r6,--r5
13494 +       .text
13495 +       .global ld_sh2
13496 +ld_sh2:
13497 +       ld.sh pc,--pc
13498 +       ld.sh r12,--r12
13499 +       ld.sh r5,--r5
13500 +       ld.sh r4,--r4
13501 +       ld.sh lr,--lr
13502 +       ld.sh pc,--r10
13503 +       ld.sh r6,--r3
13504 +       ld.sh r4,--r6
13505 +       .text
13506 +       .global ld_uh2
13507 +ld_uh2:
13508 +       ld.uh pc,--pc
13509 +       ld.uh r12,--r12
13510 +       ld.uh r5,--r5
13511 +       ld.uh r4,--r4
13512 +       ld.uh lr,--lr
13513 +       ld.uh r3,--r2
13514 +       ld.uh r1,--r0
13515 +       ld.uh r2,--r9
13516 +       .text
13517 +       .global ld_ub2
13518 +ld_ub2:
13519 +       ld.ub pc,--pc
13520 +       ld.ub r12,--r12
13521 +       ld.ub r5,--r5
13522 +       ld.ub r4,--r4
13523 +       ld.ub lr,--lr
13524 +       ld.ub r1,--r1
13525 +       ld.ub r0,--r6
13526 +       ld.ub r2,--r7
13527 +       .text
13528 +       .global ld_ub3
13529 +ld_ub3:
13530 +       ld.ub pc,pc[0]
13531 +       ld.ub r12,r12[7]
13532 +       ld.ub r5,r5[4]
13533 +       ld.ub r4,r4[3]
13534 +       ld.ub lr,lr[1]
13535 +       ld.ub r6,r9[6]
13536 +       ld.ub r2,lr[4]
13537 +       ld.ub r1,r8[0]
13538 +       .text
13539 +       .global sub3_sp
13540 +sub3_sp:
13541 +       sub sp,0
13542 +       sub sp,-4
13543 +       sub sp,-512
13544 +       sub sp,508
13545 +       sub sp,4
13546 +       sub sp,44
13547 +       sub sp,8
13548 +       sub sp,348
13549 +       .text
13550 +       .global sub3
13551 +sub3:
13552 +       sub pc,0
13553 +       sub r12,-1
13554 +       sub r5,-128
13555 +       sub r4,127
13556 +       sub lr,1
13557 +       sub r6,-41
13558 +       sub r4,37
13559 +       sub r12,56
13560 +       .text
13561 +       .global mov1
13562 +mov1:
13563 +       mov pc,0
13564 +       mov r12,-1
13565 +       mov r5,-128
13566 +       mov r4,127
13567 +       mov lr,1
13568 +       mov pc,14
13569 +       mov r6,-100
13570 +       mov lr,-122
13571 +       .text
13572 +       .global lddsp
13573 +lddsp:
13574 +       lddsp pc,sp[0]
13575 +       lddsp r12,sp[508]
13576 +       lddsp r5,sp[256]
13577 +       lddsp r4,sp[252]
13578 +       lddsp lr,sp[4]
13579 +       lddsp lr,sp[256]
13580 +       lddsp r12,sp[20]
13581 +       lddsp r9,sp[472]
13582 +       .text
13583 +       .global lddpc
13584 +lddpc:
13585 +       lddpc pc,pc[0]
13586 +       lddpc r0,pc[508]
13587 +       lddpc r8,pc[256]
13588 +       lddpc r7,pc[252]
13589 +       lddpc lr,pc[4]
13590 +       lddpc sp,pc[472]
13591 +       lddpc r6,pc[120]
13592 +       lddpc r11,pc[28]
13593 +       .text
13594 +       .global stdsp
13595 +stdsp:
13596 +       stdsp sp[0],pc
13597 +       stdsp sp[508],r12
13598 +       stdsp sp[256],r5
13599 +       stdsp sp[252],r4
13600 +       stdsp sp[4],lr
13601 +       stdsp sp[304],pc
13602 +       stdsp sp[256],r0
13603 +       stdsp sp[336],r5
13604 +       .text
13605 +       .global cp2
13606 +cp2:
13607 +       cp pc,0
13608 +       cp r12,-1
13609 +       cp r5,-32
13610 +       cp r4,31
13611 +       cp lr,1
13612 +       cp r8,3
13613 +       cp lr,16
13614 +       cp r7,-26
13615 +       .text
13616 +       .global acr
13617 +acr:
13618 +       acr pc
13619 +       acr r12
13620 +       acr r5
13621 +       acr r4
13622 +       acr lr
13623 +       acr r2
13624 +       acr r12
13625 +       acr pc
13626 +       .text
13627 +       .global scr
13628 +scr:
13629 +       scr pc
13630 +       scr r12
13631 +       scr r5
13632 +       scr r4
13633 +       scr lr
13634 +       scr pc
13635 +       scr r6
13636 +       scr r1
13637 +       .text
13638 +       .global cpc0
13639 +cpc0:
13640 +       cpc pc
13641 +       cpc r12
13642 +       cpc r5
13643 +       cpc r4
13644 +       cpc lr
13645 +       cpc pc
13646 +       cpc r4
13647 +       cpc r9
13648 +       .text
13649 +       .global neg
13650 +neg:
13651 +       neg pc
13652 +       neg r12
13653 +       neg r5
13654 +       neg r4
13655 +       neg lr
13656 +       neg r7
13657 +       neg r1
13658 +       neg r9
13659 +       .text
13660 +       .global abs
13661 +abs:
13662 +       abs pc
13663 +       abs r12
13664 +       abs r5
13665 +       abs r4
13666 +       abs lr
13667 +       abs r6
13668 +       abs r6
13669 +       abs r4
13670 +       .text
13671 +       .global castu_b
13672 +castu_b:
13673 +       castu.b pc
13674 +       castu.b r12
13675 +       castu.b r5
13676 +       castu.b r4
13677 +       castu.b lr
13678 +       castu.b r7
13679 +       castu.b sp
13680 +       castu.b r9
13681 +       .text
13682 +       .global casts_b
13683 +casts_b:
13684 +       casts.b pc
13685 +       casts.b r12
13686 +       casts.b r5
13687 +       casts.b r4
13688 +       casts.b lr
13689 +       casts.b r11
13690 +       casts.b r1
13691 +       casts.b r10
13692 +       .text
13693 +       .global castu_h
13694 +castu_h:
13695 +       castu.h pc
13696 +       castu.h r12
13697 +       castu.h r5
13698 +       castu.h r4
13699 +       castu.h lr
13700 +       castu.h r10
13701 +       castu.h r11
13702 +       castu.h r1
13703 +       .text
13704 +       .global casts_h
13705 +casts_h:
13706 +       casts.h pc
13707 +       casts.h r12
13708 +       casts.h r5
13709 +       casts.h r4
13710 +       casts.h lr
13711 +       casts.h r0
13712 +       casts.h r5
13713 +       casts.h r9
13714 +       .text
13715 +       .global brev
13716 +brev:
13717 +       brev pc
13718 +       brev r12
13719 +       brev r5
13720 +       brev r4
13721 +       brev lr
13722 +       brev r5
13723 +       brev r10
13724 +       brev r8
13725 +       .text
13726 +       .global swap_h
13727 +swap_h:
13728 +       swap.h pc
13729 +       swap.h r12
13730 +       swap.h r5
13731 +       swap.h r4
13732 +       swap.h lr
13733 +       swap.h r7
13734 +       swap.h r0
13735 +       swap.h r8
13736 +       .text
13737 +       .global swap_b
13738 +swap_b:
13739 +       swap.b pc
13740 +       swap.b r12
13741 +       swap.b r5
13742 +       swap.b r4
13743 +       swap.b lr
13744 +       swap.b r10
13745 +       swap.b r12
13746 +       swap.b r1
13747 +       .text
13748 +       .global swap_bh
13749 +swap_bh:
13750 +       swap.bh pc
13751 +       swap.bh r12
13752 +       swap.bh r5
13753 +       swap.bh r4
13754 +       swap.bh lr
13755 +       swap.bh r9
13756 +       swap.bh r4
13757 +       swap.bh r1
13758 +       .text
13759 +       .global One_s_compliment
13760 +One_s_compliment:
13761 +       com pc
13762 +       com r12
13763 +       com r5
13764 +       com r4
13765 +       com lr
13766 +       com r2
13767 +       com r2
13768 +       com r7
13769 +       .text
13770 +       .global tnbz
13771 +tnbz:
13772 +       tnbz pc
13773 +       tnbz r12
13774 +       tnbz r5
13775 +       tnbz r4
13776 +       tnbz lr
13777 +       tnbz r8
13778 +       tnbz r12
13779 +       tnbz pc
13780 +       .text
13781 +       .global rol
13782 +rol:
13783 +       rol pc
13784 +       rol r12
13785 +       rol r5
13786 +       rol r4
13787 +       rol lr
13788 +       rol r10
13789 +       rol r9
13790 +       rol r5
13791 +       .text
13792 +       .global ror
13793 +ror:
13794 +       ror pc
13795 +       ror r12
13796 +       ror r5
13797 +       ror r4
13798 +       ror lr
13799 +       ror r8
13800 +       ror r4
13801 +       ror r7
13802 +       .text
13803 +       .global icall
13804 +icall:
13805 +       icall pc
13806 +       icall r12
13807 +       icall r5
13808 +       icall r4
13809 +       icall lr
13810 +       icall r3
13811 +       icall r1
13812 +       icall r3
13813 +       .text
13814 +       .global mustr
13815 +mustr:
13816 +       mustr pc
13817 +       mustr r12
13818 +       mustr r5
13819 +       mustr r4
13820 +       mustr lr
13821 +       mustr r1
13822 +       mustr r4
13823 +       mustr r12
13824 +       .text
13825 +       .global musfr
13826 +musfr:
13827 +       musfr pc
13828 +       musfr r12
13829 +       musfr r5
13830 +       musfr r4
13831 +       musfr lr
13832 +       musfr r11
13833 +       musfr r12
13834 +       musfr r2
13835 +       .text
13836 +       .global ret_cond
13837 +ret_cond:
13838 +       reteq pc
13839 +       retal r12
13840 +       retls r5
13841 +       retpl r4
13842 +       retne lr
13843 +       retgt r0
13844 +       retgt r12
13845 +       retge r10
13846 +       .text
13847 +       .global sr_cond
13848 +sr_cond:
13849 +       sreq pc
13850 +       sral r12
13851 +       srls r5
13852 +       srpl r4
13853 +       srne lr
13854 +       srlt r0
13855 +       sral sp
13856 +       srge r9
13857 +       .text
13858 +       .global ld_w3
13859 +ld_w3:
13860 +       ld.w pc,pc[0]
13861 +       ld.w r12,r12[124]
13862 +       ld.w r5,r5[64]
13863 +       ld.w r4,r4[60]
13864 +       ld.w lr,lr[4]
13865 +       ld.w sp,r2[52]
13866 +       ld.w r9,r1[8]
13867 +       ld.w r5,sp[60]
13868 +       .text
13869 +       .global ld_sh3
13870 +ld_sh3:
13871 +       ld.sh pc,pc[0]
13872 +       ld.sh r12,r12[14]
13873 +       ld.sh r5,r5[8]
13874 +       ld.sh r4,r4[6]
13875 +       ld.sh lr,lr[2]
13876 +       ld.sh r4,r2[8]
13877 +       ld.sh sp,lr[10]
13878 +       ld.sh r2,r11[2]
13879 +       .text
13880 +       .global ld_uh3
13881 +ld_uh3:
13882 +       ld.uh pc,pc[0]
13883 +       ld.uh r12,r12[14]
13884 +       ld.uh r5,r5[8]
13885 +       ld.uh r4,r4[6]
13886 +       ld.uh lr,lr[2]
13887 +       ld.uh r10,r0[10]
13888 +       ld.uh r8,r11[8]
13889 +       ld.uh r10,r2[12]
13890 +       .text
13891 +       .global st_w3
13892 +st_w3:
13893 +       st.w pc[0],pc
13894 +       st.w r12[60],r12
13895 +       st.w r5[32],r5
13896 +       st.w r4[28],r4
13897 +       st.w lr[4],lr
13898 +       st.w r7[44],r11
13899 +       st.w r2[24],r6
13900 +       st.w r4[12],r9
13901 +       .text
13902 +       .global st_h3
13903 +st_h3:
13904 +       st.h pc[0],pc
13905 +       st.h r12[14],r12
13906 +       st.h r5[8],r5
13907 +       st.h r4[6],r4
13908 +       st.h lr[2],lr
13909 +       st.h lr[10],r12
13910 +       st.h r6[4],r0
13911 +       st.h r5[12],sp
13912 +       .text
13913 +       .global st_b3
13914 +st_b3:
13915 +       st.b pc[0],pc
13916 +       st.b r12[7],r12
13917 +       st.b r5[4],r5
13918 +       st.b r4[3],r4
13919 +       st.b lr[1],lr
13920 +       st.b r12[6],r9
13921 +       st.b r2[3],lr
13922 +       st.b r1[3],r11
13923 +       .text
13924 +       .global ldd
13925 +ldd:
13926 +       ld.d r0,pc
13927 +       ld.d r14,r12
13928 +       ld.d r8,r5
13929 +       ld.d r6,r4
13930 +       ld.d r2,lr
13931 +       ld.d r14,r7
13932 +       ld.d r4,r4
13933 +       ld.d r14,pc
13934 +       .text
13935 +       .global ldd_postinc
13936 +ldd_postinc:
13937 +       ld.d r0,pc++
13938 +       ld.d r14,r12++
13939 +       ld.d r8,r5++
13940 +       ld.d r6,r4++
13941 +       ld.d r2,lr++
13942 +       ld.d r14,r5++
13943 +       ld.d r12,r11++
13944 +       ld.d r2,r12++
13945 +       .text
13946 +       .global ldd_predec
13947 +ldd_predec:
13948 +       ld.d r0,--pc
13949 +       ld.d r14,--r12
13950 +       ld.d r8,--r5
13951 +       ld.d r6,--r4
13952 +       ld.d r2,--lr
13953 +       ld.d r8,--r0
13954 +       ld.d r10,--pc
13955 +       ld.d r2,--r4
13956 +       .text
13957 +       .global std
13958 +std:
13959 +       st.d pc,r0
13960 +       st.d r12,r14
13961 +       st.d r5,r8
13962 +       st.d r4,r6
13963 +       st.d lr,r2
13964 +       st.d r0,r12
13965 +       st.d sp,r4
13966 +       st.d r12,r12
13967 +       .text
13968 +       .global std_postinc
13969 +std_postinc:
13970 +       st.d pc++,r0
13971 +       st.d r12++,r14
13972 +       st.d r5++,r8
13973 +       st.d r4++,r6
13974 +       st.d lr++,r2
13975 +       st.d sp++,r6
13976 +       st.d r10++,r6
13977 +       st.d r7++,r2
13978 +       .text
13979 +       .global std_predec
13980 +std_predec:
13981 +       st.d --pc,r0
13982 +       st.d --r12,r14
13983 +       st.d --r5,r8
13984 +       st.d --r4,r6
13985 +       st.d --lr,r2
13986 +       st.d --r3,r6
13987 +       st.d --lr,r2
13988 +       st.d --r0,r4
13989 +       .text
13990 +       .global mul
13991 +mul:
13992 +       mul pc,pc
13993 +       mul r12,r12
13994 +       mul r5,r5
13995 +       mul r4,r4
13996 +       mul lr,lr
13997 +       mul r10,lr
13998 +       mul r0,r8
13999 +       mul r8,r5
14000 +       .text
14001 +       .global asr_imm5
14002 +asr_imm5:
14003 +       asr pc,0
14004 +       asr r12,31
14005 +       asr r5,16
14006 +       asr r4,15
14007 +       asr lr,1
14008 +       asr r6,23
14009 +       asr r6,18
14010 +       asr r5,8
14011 +       .text
14012 +       .global lsl_imm5
14013 +lsl_imm5:
14014 +       lsl pc,0
14015 +       lsl r12,31
14016 +       lsl r5,16
14017 +       lsl r4,15
14018 +       lsl lr,1
14019 +       lsl r12,13
14020 +       lsl r6,16
14021 +       lsl r1,25
14022 +       .text
14023 +       .global lsr_imm5
14024 +lsr_imm5:
14025 +       lsr pc,0
14026 +       lsr r12,31
14027 +       lsr r5,16
14028 +       lsr r4,15
14029 +       lsr lr,1
14030 +       lsr r0,1
14031 +       lsr r8,10
14032 +       lsr r7,26
14033 +       .text
14034 +       .global sbr
14035 +sbr:
14036 +       sbr pc,0
14037 +       sbr r12,31
14038 +       sbr r5,16
14039 +       sbr r4,15
14040 +       sbr lr,1
14041 +       sbr r8,31
14042 +       sbr r6,22
14043 +       sbr r1,23
14044 +       .text
14045 +       .global cbr
14046 +cbr:
14047 +       cbr pc,0
14048 +       cbr r12,31
14049 +       cbr r5,16
14050 +       cbr r4,15
14051 +       cbr lr,1
14052 +       cbr r12,10
14053 +       cbr r7,22
14054 +       cbr r8,9
14055 +       .text
14056 +       .global brc1
14057 +brc1:
14058 +       breq 0
14059 +       brpl -2
14060 +       brge -256
14061 +       brcs 254
14062 +       brne 2
14063 +       brcs 230
14064 +       breq -18
14065 +       breq 12
14066 +       .text
14067 +       .global rjmp
14068 +rjmp:
14069 +       rjmp 0
14070 +       rjmp -2
14071 +       rjmp -1024
14072 +       rjmp 1022
14073 +       rjmp 2
14074 +       rjmp -962
14075 +       rjmp 14
14076 +       rjmp -516
14077 +       .text
14078 +       .global rcall1
14079 +rcall1:
14080 +       rcall 0
14081 +       rcall -2
14082 +       rcall -1024
14083 +       rcall 1022
14084 +       rcall 2
14085 +       rcall 216
14086 +       rcall -530
14087 +       rcall -972
14088 +       .text
14089 +       .global acall
14090 +acall:
14091 +       acall 0
14092 +       acall 1020
14093 +       acall 512
14094 +       acall 508
14095 +       acall 4
14096 +       acall 356
14097 +       acall 304
14098 +       acall 172
14099 +       .text
14100 +       .global scall
14101 +scall:
14102 +       scall
14103 +       scall
14104 +       scall
14105 +       scall
14106 +       scall
14107 +       scall
14108 +       scall
14109 +       scall
14110 +       .text
14111 +       .global popm
14112 +popm:
14113 +       /* popm with no argument fails currently */
14114 +       popm pc
14115 +       popm r0-r11,pc,r12=-1
14116 +       popm lr
14117 +       popm r0-r11,pc,r12=1
14118 +       popm r0-r3
14119 +       popm r4-r10,pc
14120 +       popm r0-r3,r11,pc,r12=0
14121 +       popm r0-r7,r10-r12,lr
14122 +       .text
14123 +       .global pushm
14124 +pushm:
14125 +       pushm pc
14126 +       pushm r0-r12,lr,pc
14127 +       pushm pc
14128 +       pushm r0-r12,lr
14129 +       pushm r0-r3
14130 +       pushm r8-r10,lr,pc
14131 +       pushm r0-r3,r10
14132 +       pushm r8-r9,r12
14133 +       .text
14134 +       .global popm_n
14135 +popm_n:
14136 +       popm pc
14137 +       popm r0-r11,pc,r12=-1
14138 +       popm lr
14139 +       popm r0-r11,pc,r12=1
14140 +       popm r0-r3
14141 +       popm r4-r10,pc
14142 +       popm r0-r3,r11,pc,r12=0
14143 +       popm r0-r7,r10-r12,lr
14144 +       .text
14145 +       .global pushm_n
14146 +pushm_n:
14147 +       pushm pc
14148 +       pushm r0-r12,lr,pc
14149 +       pushm pc
14150 +       pushm r0-r12,lr
14151 +       pushm r0-r3
14152 +       pushm r8-r10,lr,pc
14153 +       pushm r0-r3,r10
14154 +       pushm r8-r9,r12
14155 +       .text
14156 +       .global csrfcz
14157 +csrfcz:
14158 +       csrfcz 0
14159 +       csrfcz 31
14160 +       csrfcz 16
14161 +       csrfcz 15
14162 +       csrfcz 1
14163 +       csrfcz 5
14164 +       csrfcz 13
14165 +       csrfcz 23
14166 +       .text
14167 +       .global ssrf
14168 +ssrf:
14169 +       ssrf 0
14170 +       ssrf 31
14171 +       ssrf 16
14172 +       ssrf 15
14173 +       ssrf 1
14174 +       ssrf 29
14175 +       ssrf 13
14176 +       ssrf 13
14177 +       .text
14178 +       .global csrf
14179 +csrf:
14180 +       csrf 0
14181 +       csrf 31
14182 +       csrf 16
14183 +       csrf 15
14184 +       csrf 1
14185 +       csrf 10
14186 +       csrf 15
14187 +       csrf 11
14188 +       .text
14189 +       .global rete
14190 +rete:
14191 +       rete
14192 +       .text
14193 +       .global rets
14194 +rets:
14195 +       rets
14196 +       .text
14197 +       .global retd
14198 +retd:
14199 +       retd
14200 +       .text
14201 +       .global retj
14202 +retj:
14203 +       retj
14204 +       .text
14205 +       .global tlbr
14206 +tlbr:
14207 +       tlbr
14208 +       .text
14209 +       .global tlbs
14210 +tlbs:
14211 +       tlbs
14212 +       .text
14213 +       .global tlbw
14214 +tlbw:
14215 +       tlbw
14216 +       .text
14217 +       .global breakpoint
14218 +breakpoint:
14219 +       breakpoint
14220 +       .text
14221 +       .global incjosp
14222 +incjosp:
14223 +       incjosp 1
14224 +       incjosp 2
14225 +       incjosp 3
14226 +       incjosp 4
14227 +       incjosp -4
14228 +       incjosp -3
14229 +       incjosp -2
14230 +       incjosp -1
14231 +       .text
14232 +       .global nop
14233 +nop:
14234 +       nop
14235 +       .text
14236 +       .global popjc
14237 +popjc:
14238 +       popjc
14239 +       .text
14240 +       .global pushjc
14241 +pushjc:
14242 +       pushjc
14243 +       .text
14244 +       .global add2
14245 +add2:
14246 +       add pc,pc,pc<<0
14247 +       add r12,r12,r12<<3
14248 +       add r5,r5,r5<<2
14249 +       add r4,r4,r4<<1
14250 +       add lr,lr,lr<<1
14251 +       add r0,r12,r0<<1
14252 +       add r9,r12,r4<<0
14253 +       add r12,r12,r7<<2
14254 +       .text
14255 +       .global sub2
14256 +sub2:
14257 +       sub pc,pc,pc<<0
14258 +       sub r12,r12,r12<<3
14259 +       sub r5,r5,r5<<2
14260 +       sub r4,r4,r4<<1
14261 +       sub lr,lr,lr<<1
14262 +       sub sp,r3,r4<<0
14263 +       sub r3,r7,r3<<0
14264 +       sub sp,r10,sp<<1
14265 +       .text
14266 +       .global divu
14267 +divu:
14268 +       divu pc,pc,pc
14269 +       divu r12,r12,r12
14270 +       divu r5,r5,r5
14271 +       divu r4,r4,r4
14272 +       divu lr,lr,lr
14273 +       divu sp,r4,pc
14274 +       divu r5,r5,sp
14275 +       divu r10,sp,r0
14276 +       .text
14277 +       .global addhh_w
14278 +addhh_w:
14279 +       addhh.w pc,pc:b,pc:b
14280 +       addhh.w r12,r12:t,r12:t
14281 +       addhh.w r5,r5:t,r5:t
14282 +       addhh.w r4,r4:b,r4:b
14283 +       addhh.w lr,lr:t,lr:t
14284 +       addhh.w r0,r0:b,r3:b
14285 +       addhh.w lr,r12:t,r7:b
14286 +       addhh.w r3,r10:t,r2:b
14287 +       .text
14288 +       .global subhh_w
14289 +subhh_w:
14290 +       subhh.w pc,pc:b,pc:b
14291 +       subhh.w r12,r12:t,r12:t
14292 +       subhh.w r5,r5:t,r5:t
14293 +       subhh.w r4,r4:b,r4:b
14294 +       subhh.w lr,lr:t,lr:t
14295 +       subhh.w r10,r1:t,r7:b
14296 +       subhh.w pc,r10:t,lr:t
14297 +       subhh.w r3,r0:t,r12:b
14298 +       .text
14299 +       .global adc
14300 +adc:
14301 +       adc pc,pc,pc
14302 +       adc r12,r12,r12
14303 +       adc r5,r5,r5
14304 +       adc r4,r4,r4
14305 +       adc lr,lr,lr
14306 +       adc r4,r0,r7
14307 +       adc sp,r4,r3
14308 +       adc r2,r12,r0
14309 +       .text
14310 +       .global sbc
14311 +sbc:
14312 +       sbc pc,pc,pc
14313 +       sbc r12,r12,r12
14314 +       sbc r5,r5,r5
14315 +       sbc r4,r4,r4
14316 +       sbc lr,lr,lr
14317 +       sbc r6,r7,r9
14318 +       sbc r0,r8,r5
14319 +       sbc r1,r0,r4
14320 +       .text
14321 +       .global mul_2
14322 +mul_2:
14323 +       mul pc,pc,pc
14324 +       mul r12,r12,r12
14325 +       mul r5,r5,r5
14326 +       mul r4,r4,r4
14327 +       mul lr,lr,lr
14328 +       mul pc,r0,r0
14329 +       mul r8,pc,lr
14330 +       mul r4,r12,pc
14331 +       .text
14332 +       .global mac
14333 +mac:
14334 +       mac pc,pc,pc
14335 +       mac r12,r12,r12
14336 +       mac r5,r5,r5
14337 +       mac r4,r4,r4
14338 +       mac lr,lr,lr
14339 +       mac r10,r4,r0
14340 +       mac r7,lr,r0
14341 +       mac r2,r9,r12
14342 +       .text
14343 +       .global mulsd
14344 +mulsd:
14345 +       muls.d pc,pc,pc
14346 +       muls.d r12,r12,r12
14347 +       muls.d r5,r5,r5
14348 +       muls.d r4,r4,r4
14349 +       muls.d lr,lr,lr
14350 +       muls.d r2,r8,lr
14351 +       muls.d r4,r0,r11
14352 +       muls.d r5,lr,r6
14353 +       .text
14354 +       .global macsd
14355 +macsd:
14356 +       macs.d r0,pc,pc
14357 +       macs.d r14,r12,r12
14358 +       macs.d r8,r5,r5
14359 +       macs.d r6,r4,r4
14360 +       macs.d r2,lr,lr
14361 +       macs.d r8,r1,r9
14362 +       macs.d r14,r8,r8
14363 +       macs.d r4,r3,r12
14364 +       .text
14365 +       .global mulud
14366 +mulud:
14367 +       mulu.d r0,pc,pc
14368 +       mulu.d r14,r12,r12
14369 +       mulu.d r8,r5,r5
14370 +       mulu.d r6,r4,r4
14371 +       mulu.d r2,lr,lr
14372 +       mulu.d r6,r5,r0
14373 +       mulu.d r4,r6,r1
14374 +       mulu.d r8,r8,r2
14375 +       .text
14376 +       .global macud
14377 +macud:
14378 +       macu.d r0,pc,pc
14379 +       macu.d r14,r12,r12
14380 +       macu.d r8,r5,r5
14381 +       macu.d r6,r4,r4
14382 +       macu.d r2,lr,lr
14383 +       macu.d r6,sp,r11
14384 +       macu.d r2,r4,r8
14385 +       macu.d r6,r10,r9
14386 +       .text
14387 +       .global asr_1
14388 +asr_1:
14389 +       asr pc,pc,pc
14390 +       asr r12,r12,r12
14391 +       asr r5,r5,r5
14392 +       asr r4,r4,r4
14393 +       asr lr,lr,lr
14394 +       asr pc,r6,pc
14395 +       asr r0,r6,r12
14396 +       asr r4,sp,r0
14397 +       .text
14398 +       .global lsl_1
14399 +lsl_1:
14400 +       lsl pc,pc,pc
14401 +       lsl r12,r12,r12
14402 +       lsl r5,r5,r5
14403 +       lsl r4,r4,r4
14404 +       lsl lr,lr,lr
14405 +       lsl lr,r5,lr
14406 +       lsl r5,pc,r3
14407 +       lsl r1,pc,r9
14408 +       .text
14409 +       .global lsr_1
14410 +lsr_1:
14411 +       lsr pc,pc,pc
14412 +       lsr r12,r12,r12
14413 +       lsr r5,r5,r5
14414 +       lsr r4,r4,r4
14415 +       lsr lr,lr,lr
14416 +       lsr r2,r4,r1
14417 +       lsr r5,r1,r6
14418 +       lsr sp,r6,r7
14419 +       .text
14420 +       .global xchg
14421 +xchg:
14422 +       xchg pc,pc,pc
14423 +       xchg r12,r12,r12
14424 +       xchg r5,r5,r5
14425 +       xchg r4,r4,r4
14426 +       xchg lr,lr,lr
14427 +       xchg lr,r4,sp
14428 +       xchg r1,r5,r12
14429 +       xchg lr,r12,r0
14430 +       .text
14431 +       .global max
14432 +max:
14433 +       max pc,pc,pc
14434 +       max r12,r12,r12
14435 +       max r5,r5,r5
14436 +       max r4,r4,r4
14437 +       max lr,lr,lr
14438 +       max lr,r2,sp
14439 +       max r4,r10,r9
14440 +       max lr,r9,lr
14441 +       .text
14442 +       .global min
14443 +min:
14444 +       min pc,pc,pc
14445 +       min r12,r12,r12
14446 +       min r5,r5,r5
14447 +       min r4,r4,r4
14448 +       min lr,lr,lr
14449 +       min r9,r7,r8
14450 +       min sp,r5,r5
14451 +       min r4,r1,r4
14452 +       .text
14453 +       .global addabs
14454 +addabs:
14455 +       addabs pc,pc,pc
14456 +       addabs r12,r12,r12
14457 +       addabs r5,r5,r5
14458 +       addabs r4,r4,r4
14459 +       addabs lr,lr,lr
14460 +       addabs r7,r10,r0
14461 +       addabs r9,r9,r7
14462 +       addabs r2,r8,r12
14463 +       .text
14464 +       .global mulnhh_w
14465 +mulnhh_w:
14466 +       mulnhh.w pc,pc:b,pc:b
14467 +       mulnhh.w r12,r12:t,r12:t
14468 +       mulnhh.w r5,r5:t,r5:t
14469 +       mulnhh.w r4,r4:b,r4:b
14470 +       mulnhh.w lr,lr:t,lr:t
14471 +       mulnhh.w r11,sp:t,r9:b
14472 +       mulnhh.w sp,r4:b,lr:t
14473 +       mulnhh.w r12,r2:t,r11:b
14474 +       .text
14475 +       .global mulnwh_d
14476 +mulnwh_d:
14477 +       mulnwh.d r0,pc,pc:b
14478 +       mulnwh.d r14,r12,r12:t
14479 +       mulnwh.d r8,r5,r5:t
14480 +       mulnwh.d r6,r4,r4:b
14481 +       mulnwh.d r2,lr,lr:t
14482 +       mulnwh.d r14,r3,r2:t
14483 +       mulnwh.d r4,r5,r9:b
14484 +       mulnwh.d r12,r4,r4:t
14485 +       .text
14486 +       .global machh_w
14487 +machh_w:
14488 +       machh.w pc,pc:b,pc:b
14489 +       machh.w r12,r12:t,r12:t
14490 +       machh.w r5,r5:t,r5:t
14491 +       machh.w r4,r4:b,r4:b
14492 +       machh.w lr,lr:t,lr:t
14493 +       machh.w lr,r5:b,r1:t
14494 +       machh.w r9,r6:b,r7:b
14495 +       machh.w r5,lr:t,r12:b
14496 +       .text
14497 +       .global machh_d
14498 +machh_d:
14499 +       machh.d r0,pc:b,pc:b
14500 +       machh.d r14,r12:t,r12:t
14501 +       machh.d r8,r5:t,r5:t
14502 +       machh.d r6,r4:b,r4:b
14503 +       machh.d r2,lr:t,lr:t
14504 +       machh.d r10,r0:b,r8:b
14505 +       machh.d r14,r4:b,r5:t
14506 +       machh.d r8,r0:b,r4:t
14507 +       .text
14508 +       .global macsathh_w
14509 +macsathh_w:
14510 +       macsathh.w pc,pc:b,pc:b
14511 +       macsathh.w r12,r12:t,r12:t
14512 +       macsathh.w r5,r5:t,r5:t
14513 +       macsathh.w r4,r4:b,r4:b
14514 +       macsathh.w lr,lr:t,lr:t
14515 +       macsathh.w r7,r7:t,pc:t
14516 +       macsathh.w r4,r2:t,r4:b
14517 +       macsathh.w r4,r8:t,r3:t
14518 +       .text
14519 +       .global mulhh_w
14520 +mulhh_w:
14521 +       mulhh.w pc,pc:b,pc:b
14522 +       mulhh.w r12,r12:t,r12:t
14523 +       mulhh.w r5,r5:t,r5:t
14524 +       mulhh.w r4,r4:b,r4:b
14525 +       mulhh.w lr,lr:t,lr:t
14526 +       mulhh.w r7,r4:t,r9:b
14527 +       mulhh.w pc,r3:t,r7:t
14528 +       mulhh.w pc,r4:b,r9:t
14529 +       .text
14530 +       .global mulsathh_h
14531 +mulsathh_h:
14532 +       mulsathh.h pc,pc:b,pc:b
14533 +       mulsathh.h r12,r12:t,r12:t
14534 +       mulsathh.h r5,r5:t,r5:t
14535 +       mulsathh.h r4,r4:b,r4:b
14536 +       mulsathh.h lr,lr:t,lr:t
14537 +       mulsathh.h r3,r1:b,sp:b
14538 +       mulsathh.h r11,lr:t,r11:b
14539 +       mulsathh.h r8,r8:b,r11:t
14540 +       .text
14541 +       .global mulsathh_w
14542 +mulsathh_w:
14543 +       mulsathh.w pc,pc:b,pc:b
14544 +       mulsathh.w r12,r12:t,r12:t
14545 +       mulsathh.w r5,r5:t,r5:t
14546 +       mulsathh.w r4,r4:b,r4:b
14547 +       mulsathh.w lr,lr:t,lr:t
14548 +       mulsathh.w lr,r11:t,r6:b
14549 +       mulsathh.w r6,r6:b,r7:t
14550 +       mulsathh.w r10,r2:b,r3:b
14551 +       .text
14552 +       .global mulsatrndhh_h
14553 +mulsatrndhh_h:
14554 +       mulsatrndhh.h pc,pc:b,pc:b
14555 +       mulsatrndhh.h r12,r12:t,r12:t
14556 +       mulsatrndhh.h r5,r5:t,r5:t
14557 +       mulsatrndhh.h r4,r4:b,r4:b
14558 +       mulsatrndhh.h lr,lr:t,lr:t
14559 +       mulsatrndhh.h r11,r6:b,r9:b
14560 +       mulsatrndhh.h r11,r3:b,r8:t
14561 +       mulsatrndhh.h r5,sp:t,r7:t
14562 +       .text
14563 +       .global mulsatrndwh_w
14564 +mulsatrndwh_w:
14565 +       mulsatrndwh.w pc,pc,pc:b
14566 +       mulsatrndwh.w r12,r12,r12:t
14567 +       mulsatrndwh.w r5,r5,r5:t
14568 +       mulsatrndwh.w r4,r4,r4:b
14569 +       mulsatrndwh.w lr,lr,lr:t
14570 +       mulsatrndwh.w r5,r12,r0:b
14571 +       mulsatrndwh.w r7,r10,pc:b
14572 +       mulsatrndwh.w r10,r8,r5:t
14573 +       .text
14574 +       .global macwh_d
14575 +macwh_d:
14576 +       macwh.d r0,pc,pc:b
14577 +       macwh.d r14,r12,r12:t
14578 +       macwh.d r8,r5,r5:t
14579 +       macwh.d r6,r4,r4:b
14580 +       macwh.d r2,lr,lr:t
14581 +       macwh.d r4,r10,r12:t
14582 +       macwh.d r4,r7,sp:b
14583 +       macwh.d r14,r9,r11:b
14584 +       .text
14585 +       .global mulwh_d
14586 +mulwh_d:
14587 +       mulwh.d r0,pc,pc:b
14588 +       mulwh.d r14,r12,r12:t
14589 +       mulwh.d r8,r5,r5:t
14590 +       mulwh.d r6,r4,r4:b
14591 +       mulwh.d r2,lr,lr:t
14592 +       mulwh.d r12,r5,r1:b
14593 +       mulwh.d r0,r1,r3:t
14594 +       mulwh.d r0,r9,r2:b
14595 +       .text
14596 +       .global mulsatwh_w
14597 +mulsatwh_w:
14598 +       mulsatwh.w pc,pc,pc:b
14599 +       mulsatwh.w r12,r12,r12:t
14600 +       mulsatwh.w r5,r5,r5:t
14601 +       mulsatwh.w r4,r4,r4:b
14602 +       mulsatwh.w lr,lr,lr:t
14603 +       mulsatwh.w r11,pc,r10:t
14604 +       mulsatwh.w sp,r12,r9:t
14605 +       mulsatwh.w r0,r3,r2:t
14606 +       .text
14607 +       .global ldw7
14608 +ldw7:
14609 +       ld.w pc,pc[pc:b<<2]
14610 +       ld.w r12,r12[r12:t<<2]
14611 +       ld.w r5,r5[r5:u<<2]
14612 +       ld.w r4,r4[r4:l<<2]
14613 +       ld.w lr,lr[lr:l<<2]
14614 +       ld.w r9,r10[r6:l<<2]
14615 +       ld.w r2,r10[r10:b<<2]
14616 +       ld.w r11,r5[pc:b<<2]
14617 +       .text
14618 +       .global satadd_w
14619 +satadd_w:
14620 +       satadd.w pc,pc,pc
14621 +       satadd.w r12,r12,r12
14622 +       satadd.w r5,r5,r5
14623 +       satadd.w r4,r4,r4
14624 +       satadd.w lr,lr,lr
14625 +       satadd.w r4,r8,r11
14626 +       satadd.w r3,r12,r6
14627 +       satadd.w r3,lr,r9
14628 +       .text
14629 +       .global satsub_w1
14630 +satsub_w1:
14631 +       satsub.w pc,pc,pc
14632 +       satsub.w r12,r12,r12
14633 +       satsub.w r5,r5,r5
14634 +       satsub.w r4,r4,r4
14635 +       satsub.w lr,lr,lr
14636 +       satsub.w r8,sp,r0
14637 +       satsub.w r9,r8,r4
14638 +       satsub.w pc,lr,r2
14639 +       .text
14640 +       .global satadd_h
14641 +satadd_h:
14642 +       satadd.h pc,pc,pc
14643 +       satadd.h r12,r12,r12
14644 +       satadd.h r5,r5,r5
14645 +       satadd.h r4,r4,r4
14646 +       satadd.h lr,lr,lr
14647 +       satadd.h r7,r3,r9
14648 +       satadd.h r1,r0,r2
14649 +       satadd.h r1,r4,lr
14650 +       .text
14651 +       .global satsub_h
14652 +satsub_h:
14653 +       satsub.h pc,pc,pc
14654 +       satsub.h r12,r12,r12
14655 +       satsub.h r5,r5,r5
14656 +       satsub.h r4,r4,r4
14657 +       satsub.h lr,lr,lr
14658 +       satsub.h lr,lr,r3
14659 +       satsub.h r11,r6,r5
14660 +       satsub.h r3,sp,r0
14661 +       .text
14662 +       .global mul3
14663 +mul3:
14664 +       mul pc,pc,0
14665 +       mul r12,r12,-1
14666 +       mul r5,r5,-128
14667 +       mul r4,r4,127
14668 +       mul lr,lr,1
14669 +       mul r12,r2,-7
14670 +       mul r1,pc,95
14671 +       mul r4,r6,19
14672 +       .text
14673 +       .global rsub2
14674 +rsub2:
14675 +       rsub pc,pc,0
14676 +       rsub r12,r12,-1
14677 +       rsub r5,r5,-128
14678 +       rsub r4,r4,127
14679 +       rsub lr,lr,1
14680 +       rsub r9,lr,96
14681 +       rsub r11,r1,56
14682 +       rsub r0,r7,-87
14683 +       .text
14684 +       .global clz
14685 +clz:
14686 +       clz pc,pc
14687 +       clz r12,r12
14688 +       clz r5,r5
14689 +       clz r4,r4
14690 +       clz lr,lr
14691 +       clz r2,r3
14692 +       clz r5,r11
14693 +       clz pc,r3
14694 +       .text
14695 +       .global cpc1
14696 +cpc1:
14697 +       cpc pc,pc
14698 +       cpc r12,r12
14699 +       cpc r5,r5
14700 +       cpc r4,r4
14701 +       cpc lr,lr
14702 +       cpc pc,r4
14703 +       cpc r5,r9
14704 +       cpc r6,r7
14705 +       .text
14706 +       .global asr3
14707 +asr3:
14708 +       asr pc,pc,0
14709 +       asr r12,r12,31
14710 +       asr r5,r5,16
14711 +       asr r4,r4,15
14712 +       asr lr,lr,1
14713 +       asr r4,r11,19
14714 +       asr sp,pc,26
14715 +       asr r11,sp,8
14716 +       .text
14717 +       .global lsl3
14718 +lsl3:
14719 +       lsl pc,pc,0
14720 +       lsl r12,r12,31
14721 +       lsl r5,r5,16
14722 +       lsl r4,r4,15
14723 +       lsl lr,lr,1
14724 +       lsl r8,r10,17
14725 +       lsl r2,lr,3
14726 +       lsl lr,r11,14
14727 +       .text
14728 +       .global lsr3
14729 +lsr3:
14730 +       lsr pc,pc,0
14731 +       lsr r12,r12,31
14732 +       lsr r5,r5,16
14733 +       lsr r4,r4,15
14734 +       lsr lr,lr,1
14735 +       lsr r4,r3,31
14736 +       lsr pc,r9,14
14737 +       lsr r3,r0,6
14738 +/*     .text
14739 +       .global extract_b
14740 +extract_b:
14741 +       extract.b pc,pc:b
14742 +       extract.b r12,r12:t
14743 +       extract.b r5,r5:u
14744 +       extract.b r4,r4:l
14745 +       extract.b lr,lr:l
14746 +       extract.b r2,r5:l
14747 +       extract.b r12,r3:l
14748 +       extract.b sp,r3:l
14749 +       .text
14750 +       .global insert_b
14751 +insert_b:
14752 +       insert.b pc:b,pc
14753 +       insert.b r12:t,r12
14754 +       insert.b r5:u,r5
14755 +       insert.b r4:l,r4
14756 +       insert.b lr:l,lr
14757 +       insert.b r12:u,r3
14758 +       insert.b r10:l,lr
14759 +       insert.b r11:l,r12
14760 +       .text
14761 +       .global extract_h
14762 +extract_h:
14763 +       extract.h pc,pc:b
14764 +       extract.h r12,r12:t
14765 +       extract.h r5,r5:t
14766 +       extract.h r4,r4:b
14767 +       extract.h lr,lr:t
14768 +       extract.h r11,lr:b
14769 +       extract.h r10,r0:b
14770 +       extract.h r11,r12:b
14771 +       .text
14772 +       .global insert_h
14773 +insert_h:
14774 +       insert.h pc:b,pc
14775 +       insert.h r12:t,r12
14776 +       insert.h r5:t,r5
14777 +       insert.h r4:b,r4
14778 +       insert.h lr:t,lr
14779 +       insert.h r12:t,r11
14780 +       insert.h r7:b,r6
14781 +       insert.h r1:t,r11 */
14782 +       .text
14783 +       .global movc1
14784 +movc1:
14785 +       moveq pc,pc
14786 +       moval r12,r12
14787 +       movls r5,r5
14788 +       movpl r4,r4
14789 +       movne lr,lr
14790 +       movne pc,r11
14791 +       movmi r10,r2
14792 +       movls r8,r12
14793 +       .text
14794 +       .global padd_h
14795 +padd_h:
14796 +       padd.h pc,pc,pc
14797 +       padd.h r12,r12,r12
14798 +       padd.h r5,r5,r5
14799 +       padd.h r4,r4,r4
14800 +       padd.h lr,lr,lr
14801 +       padd.h r8,r2,r7
14802 +       padd.h r0,r0,r3
14803 +       padd.h sp,r11,r6
14804 +       .text
14805 +       .global psub_h
14806 +psub_h:
14807 +       psub.h pc,pc,pc
14808 +       psub.h r12,r12,r12
14809 +       psub.h r5,r5,r5
14810 +       psub.h r4,r4,r4
14811 +       psub.h lr,lr,lr
14812 +       psub.h lr,r6,r8
14813 +       psub.h r0,r1,sp
14814 +       psub.h pc,pc,sp
14815 +       .text
14816 +       .global paddx_h
14817 +paddx_h:
14818 +       paddx.h pc,pc,pc
14819 +       paddx.h r12,r12,r12
14820 +       paddx.h r5,r5,r5
14821 +       paddx.h r4,r4,r4
14822 +       paddx.h lr,lr,lr
14823 +       paddx.h pc,pc,r1
14824 +       paddx.h r10,r4,r5
14825 +       paddx.h r5,pc,r2
14826 +       .text
14827 +       .global psubx_h
14828 +psubx_h:
14829 +       psubx.h pc,pc,pc
14830 +       psubx.h r12,r12,r12
14831 +       psubx.h r5,r5,r5
14832 +       psubx.h r4,r4,r4
14833 +       psubx.h lr,lr,lr
14834 +       psubx.h r5,r12,r5
14835 +       psubx.h r3,r8,r3
14836 +       psubx.h r5,r2,r3
14837 +       .text
14838 +       .global padds_sh
14839 +padds_sh:
14840 +       padds.sh pc,pc,pc
14841 +       padds.sh r12,r12,r12
14842 +       padds.sh r5,r5,r5
14843 +       padds.sh r4,r4,r4
14844 +       padds.sh lr,lr,lr
14845 +       padds.sh r9,lr,r2
14846 +       padds.sh r6,r8,r1
14847 +       padds.sh r6,r4,r10
14848 +       .text
14849 +       .global psubs_sh
14850 +psubs_sh:
14851 +       psubs.sh pc,pc,pc
14852 +       psubs.sh r12,r12,r12
14853 +       psubs.sh r5,r5,r5
14854 +       psubs.sh r4,r4,r4
14855 +       psubs.sh lr,lr,lr
14856 +       psubs.sh r6,lr,r11
14857 +       psubs.sh r2,r12,r4
14858 +       psubs.sh r0,r9,r0
14859 +       .text
14860 +       .global paddxs_sh
14861 +paddxs_sh:
14862 +       paddxs.sh pc,pc,pc
14863 +       paddxs.sh r12,r12,r12
14864 +       paddxs.sh r5,r5,r5
14865 +       paddxs.sh r4,r4,r4
14866 +       paddxs.sh lr,lr,lr
14867 +       paddxs.sh r0,r3,r9
14868 +       paddxs.sh pc,r10,r11
14869 +       paddxs.sh pc,r10,pc
14870 +       .text
14871 +       .global psubxs_sh
14872 +psubxs_sh:
14873 +       psubxs.sh pc,pc,pc
14874 +       psubxs.sh r12,r12,r12
14875 +       psubxs.sh r5,r5,r5
14876 +       psubxs.sh r4,r4,r4
14877 +       psubxs.sh lr,lr,lr
14878 +       psubxs.sh r7,r4,r4
14879 +       psubxs.sh r7,r8,r3
14880 +       psubxs.sh pc,r6,r5
14881 +       .text
14882 +       .global padds_uh
14883 +padds_uh:
14884 +       padds.uh pc,pc,pc
14885 +       padds.uh r12,r12,r12
14886 +       padds.uh r5,r5,r5
14887 +       padds.uh r4,r4,r4
14888 +       padds.uh lr,lr,lr
14889 +       padds.uh r12,r11,r7
14890 +       padds.uh r7,r8,lr
14891 +       padds.uh r6,r9,r7
14892 +       .text
14893 +       .global psubs_uh
14894 +psubs_uh:
14895 +       psubs.uh pc,pc,pc
14896 +       psubs.uh r12,r12,r12
14897 +       psubs.uh r5,r5,r5
14898 +       psubs.uh r4,r4,r4
14899 +       psubs.uh lr,lr,lr
14900 +       psubs.uh lr,r10,r6
14901 +       psubs.uh sp,r2,pc
14902 +       psubs.uh r2,r9,r2
14903 +       .text
14904 +       .global paddxs_uh
14905 +paddxs_uh:
14906 +       paddxs.uh pc,pc,pc
14907 +       paddxs.uh r12,r12,r12
14908 +       paddxs.uh r5,r5,r5
14909 +       paddxs.uh r4,r4,r4
14910 +       paddxs.uh lr,lr,lr
14911 +       paddxs.uh r7,r9,r5
14912 +       paddxs.uh r9,r1,r4
14913 +       paddxs.uh r5,r2,r3
14914 +       .text
14915 +       .global psubxs_uh
14916 +psubxs_uh:
14917 +       psubxs.uh pc,pc,pc
14918 +       psubxs.uh r12,r12,r12
14919 +       psubxs.uh r5,r5,r5
14920 +       psubxs.uh r4,r4,r4
14921 +       psubxs.uh lr,lr,lr
14922 +       psubxs.uh sp,r5,sp
14923 +       psubxs.uh sp,r6,r6
14924 +       psubxs.uh r3,r11,r8
14925 +       .text
14926 +       .global paddh_sh
14927 +paddh_sh:
14928 +       paddh.sh pc,pc,pc
14929 +       paddh.sh r12,r12,r12
14930 +       paddh.sh r5,r5,r5
14931 +       paddh.sh r4,r4,r4
14932 +       paddh.sh lr,lr,lr
14933 +       paddh.sh r12,sp,r3
14934 +       paddh.sh pc,r5,r3
14935 +       paddh.sh r8,r8,sp
14936 +       .text
14937 +       .global psubh_sh
14938 +psubh_sh:
14939 +       psubh.sh pc,pc,pc
14940 +       psubh.sh r12,r12,r12
14941 +       psubh.sh r5,r5,r5
14942 +       psubh.sh r4,r4,r4
14943 +       psubh.sh lr,lr,lr
14944 +       psubh.sh r1,r5,r8
14945 +       psubh.sh r7,r3,r6
14946 +       psubh.sh r4,r3,r3
14947 +       .text
14948 +       .global paddxh_sh
14949 +paddxh_sh:
14950 +       paddxh.sh pc,pc,pc
14951 +       paddxh.sh r12,r12,r12
14952 +       paddxh.sh r5,r5,r5
14953 +       paddxh.sh r4,r4,r4
14954 +       paddxh.sh lr,lr,lr
14955 +       paddxh.sh r6,r0,r4
14956 +       paddxh.sh r9,r8,r9
14957 +       paddxh.sh r3,r0,sp
14958 +       .text
14959 +       .global psubxh_sh
14960 +psubxh_sh:
14961 +       psubxh.sh pc,pc,pc
14962 +       psubxh.sh r12,r12,r12
14963 +       psubxh.sh r5,r5,r5
14964 +       psubxh.sh r4,r4,r4
14965 +       psubxh.sh lr,lr,lr
14966 +       psubxh.sh r4,pc,r12
14967 +       psubxh.sh r8,r4,r6
14968 +       psubxh.sh r12,r9,r4
14969 +       .text
14970 +       .global paddsub_h
14971 +paddsub_h:
14972 +       paddsub.h pc,pc:b,pc:b
14973 +       paddsub.h r12,r12:t,r12:t
14974 +       paddsub.h r5,r5:t,r5:t
14975 +       paddsub.h r4,r4:b,r4:b
14976 +       paddsub.h lr,lr:t,lr:t
14977 +       paddsub.h r5,r2:t,lr:b
14978 +       paddsub.h r7,r1:b,r8:b
14979 +       paddsub.h r6,r10:t,r5:t
14980 +       .text
14981 +       .global psubadd_h
14982 +psubadd_h:
14983 +       psubadd.h pc,pc:b,pc:b
14984 +       psubadd.h r12,r12:t,r12:t
14985 +       psubadd.h r5,r5:t,r5:t
14986 +       psubadd.h r4,r4:b,r4:b
14987 +       psubadd.h lr,lr:t,lr:t
14988 +       psubadd.h r9,r11:t,r8:t
14989 +       psubadd.h r10,r7:t,lr:t
14990 +       psubadd.h r6,pc:t,pc:b
14991 +       .text
14992 +       .global paddsubs_sh
14993 +paddsubs_sh:
14994 +       paddsubs.sh pc,pc:b,pc:b
14995 +       paddsubs.sh r12,r12:t,r12:t
14996 +       paddsubs.sh r5,r5:t,r5:t
14997 +       paddsubs.sh r4,r4:b,r4:b
14998 +       paddsubs.sh lr,lr:t,lr:t
14999 +       paddsubs.sh r0,lr:t,r0:b
15000 +       paddsubs.sh r9,r2:t,r4:t
15001 +       paddsubs.sh r12,r9:t,sp:t
15002 +       .text
15003 +       .global psubadds_sh
15004 +psubadds_sh:
15005 +       psubadds.sh pc,pc:b,pc:b
15006 +       psubadds.sh r12,r12:t,r12:t
15007 +       psubadds.sh r5,r5:t,r5:t
15008 +       psubadds.sh r4,r4:b,r4:b
15009 +       psubadds.sh lr,lr:t,lr:t
15010 +       psubadds.sh pc,lr:b,r1:t
15011 +       psubadds.sh r11,r3:b,r12:b
15012 +       psubadds.sh r10,r2:t,r8:t
15013 +       .text
15014 +       .global paddsubs_uh
15015 +paddsubs_uh:
15016 +       paddsubs.uh pc,pc:b,pc:b
15017 +       paddsubs.uh r12,r12:t,r12:t
15018 +       paddsubs.uh r5,r5:t,r5:t
15019 +       paddsubs.uh r4,r4:b,r4:b
15020 +       paddsubs.uh lr,lr:t,lr:t
15021 +       paddsubs.uh r9,r2:b,r3:b
15022 +       paddsubs.uh sp,sp:b,r7:t
15023 +       paddsubs.uh lr,r0:b,r10:t
15024 +       .text
15025 +       .global psubadds_uh
15026 +psubadds_uh:
15027 +       psubadds.uh pc,pc:b,pc:b
15028 +       psubadds.uh r12,r12:t,r12:t
15029 +       psubadds.uh r5,r5:t,r5:t
15030 +       psubadds.uh r4,r4:b,r4:b
15031 +       psubadds.uh lr,lr:t,lr:t
15032 +       psubadds.uh r12,r9:t,pc:t
15033 +       psubadds.uh r8,r6:b,r8:b
15034 +       psubadds.uh r8,r8:b,r4:b
15035 +       .text
15036 +       .global paddsubh_sh
15037 +paddsubh_sh:
15038 +       paddsubh.sh pc,pc:b,pc:b
15039 +       paddsubh.sh r12,r12:t,r12:t
15040 +       paddsubh.sh r5,r5:t,r5:t
15041 +       paddsubh.sh r4,r4:b,r4:b
15042 +       paddsubh.sh lr,lr:t,lr:t
15043 +       paddsubh.sh r8,r9:t,r9:b
15044 +       paddsubh.sh r0,sp:t,r1:t
15045 +       paddsubh.sh r3,r1:b,r0:t
15046 +       .text
15047 +       .global psubaddh_sh
15048 +psubaddh_sh:
15049 +       psubaddh.sh pc,pc:b,pc:b
15050 +       psubaddh.sh r12,r12:t,r12:t
15051 +       psubaddh.sh r5,r5:t,r5:t
15052 +       psubaddh.sh r4,r4:b,r4:b
15053 +       psubaddh.sh lr,lr:t,lr:t
15054 +       psubaddh.sh r7,r3:t,r10:b
15055 +       psubaddh.sh r7,r2:t,r1:t
15056 +       psubaddh.sh r11,r3:b,r6:b
15057 +       .text
15058 +       .global padd_b
15059 +padd_b:
15060 +       padd.b pc,pc,pc
15061 +       padd.b r12,r12,r12
15062 +       padd.b r5,r5,r5
15063 +       padd.b r4,r4,r4
15064 +       padd.b lr,lr,lr
15065 +       padd.b r2,r6,pc
15066 +       padd.b r8,r9,r12
15067 +       padd.b r5,r12,r3
15068 +       .text
15069 +       .global psub_b
15070 +psub_b:
15071 +       psub.b pc,pc,pc
15072 +       psub.b r12,r12,r12
15073 +       psub.b r5,r5,r5
15074 +       psub.b r4,r4,r4
15075 +       psub.b lr,lr,lr
15076 +       psub.b r0,r12,pc
15077 +       psub.b r7,sp,r10
15078 +       psub.b r5,sp,r12
15079 +       .text
15080 +       .global padds_sb
15081 +padds_sb:
15082 +       padds.sb pc,pc,pc
15083 +       padds.sb r12,r12,r12
15084 +       padds.sb r5,r5,r5
15085 +       padds.sb r4,r4,r4
15086 +       padds.sb lr,lr,lr
15087 +       padds.sb sp,r11,r4
15088 +       padds.sb r11,r10,r11
15089 +       padds.sb r5,r12,r6
15090 +       .text
15091 +       .global psubs_sb
15092 +psubs_sb:
15093 +       psubs.sb pc,pc,pc
15094 +       psubs.sb r12,r12,r12
15095 +       psubs.sb r5,r5,r5
15096 +       psubs.sb r4,r4,r4
15097 +       psubs.sb lr,lr,lr
15098 +       psubs.sb r7,r6,r8
15099 +       psubs.sb r12,r10,r9
15100 +       psubs.sb pc,r11,r0
15101 +       .text
15102 +       .global padds_ub
15103 +padds_ub:
15104 +       padds.ub pc,pc,pc
15105 +       padds.ub r12,r12,r12
15106 +       padds.ub r5,r5,r5
15107 +       padds.ub r4,r4,r4
15108 +       padds.ub lr,lr,lr
15109 +       padds.ub r3,r2,r11
15110 +       padds.ub r10,r8,r1
15111 +       padds.ub r11,r8,r10
15112 +       .text
15113 +       .global psubs_ub
15114 +psubs_ub:
15115 +       psubs.ub pc,pc,pc
15116 +       psubs.ub r12,r12,r12
15117 +       psubs.ub r5,r5,r5
15118 +       psubs.ub r4,r4,r4
15119 +       psubs.ub lr,lr,lr
15120 +       psubs.ub r0,r2,r7
15121 +       psubs.ub lr,r5,r3
15122 +       psubs.ub r6,r7,r9
15123 +       .text
15124 +       .global paddh_ub
15125 +paddh_ub:
15126 +       paddh.ub pc,pc,pc
15127 +       paddh.ub r12,r12,r12
15128 +       paddh.ub r5,r5,r5
15129 +       paddh.ub r4,r4,r4
15130 +       paddh.ub lr,lr,lr
15131 +       paddh.ub lr,r1,r0
15132 +       paddh.ub r2,r7,r7
15133 +       paddh.ub r2,r1,r2
15134 +       .text
15135 +       .global psubh_ub
15136 +psubh_ub:
15137 +       psubh.ub pc,pc,pc
15138 +       psubh.ub r12,r12,r12
15139 +       psubh.ub r5,r5,r5
15140 +       psubh.ub r4,r4,r4
15141 +       psubh.ub lr,lr,lr
15142 +       psubh.ub r0,r1,r6
15143 +       psubh.ub r4,lr,r10
15144 +       psubh.ub r9,r8,r1
15145 +       .text
15146 +       .global pmax_ub
15147 +pmax_ub:
15148 +       pmax.ub pc,pc,pc
15149 +       pmax.ub r12,r12,r12
15150 +       pmax.ub r5,r5,r5
15151 +       pmax.ub r4,r4,r4
15152 +       pmax.ub lr,lr,lr
15153 +       pmax.ub pc,r2,r11
15154 +       pmax.ub r12,r1,r1
15155 +       pmax.ub r5,r2,r0
15156 +       .text
15157 +       .global pmax_sh
15158 +pmax_sh:
15159 +       pmax.sh pc,pc,pc
15160 +       pmax.sh r12,r12,r12
15161 +       pmax.sh r5,r5,r5
15162 +       pmax.sh r4,r4,r4
15163 +       pmax.sh lr,lr,lr
15164 +       pmax.sh lr,r6,r12
15165 +       pmax.sh r2,pc,r5
15166 +       pmax.sh pc,r2,r7
15167 +       .text
15168 +       .global pmin_ub
15169 +pmin_ub:
15170 +       pmin.ub pc,pc,pc
15171 +       pmin.ub r12,r12,r12
15172 +       pmin.ub r5,r5,r5
15173 +       pmin.ub r4,r4,r4
15174 +       pmin.ub lr,lr,lr
15175 +       pmin.ub r8,r1,r5
15176 +       pmin.ub r1,r8,r3
15177 +       pmin.ub r0,r2,r7
15178 +       .text
15179 +       .global pmin_sh
15180 +pmin_sh:
15181 +       pmin.sh pc,pc,pc
15182 +       pmin.sh r12,r12,r12
15183 +       pmin.sh r5,r5,r5
15184 +       pmin.sh r4,r4,r4
15185 +       pmin.sh lr,lr,lr
15186 +       pmin.sh r8,r4,r10
15187 +       pmin.sh lr,r10,r12
15188 +       pmin.sh r2,r6,r2
15189 +       .text
15190 +       .global pavg_ub
15191 +pavg_ub:
15192 +       pavg.ub pc,pc,pc
15193 +       pavg.ub r12,r12,r12
15194 +       pavg.ub r5,r5,r5
15195 +       pavg.ub r4,r4,r4
15196 +       pavg.ub lr,lr,lr
15197 +       pavg.ub r0,r1,r6
15198 +       pavg.ub r8,r3,r6
15199 +       pavg.ub pc,r12,r10
15200 +       .text
15201 +       .global pavg_sh
15202 +pavg_sh:
15203 +       pavg.sh pc,pc,pc
15204 +       pavg.sh r12,r12,r12
15205 +       pavg.sh r5,r5,r5
15206 +       pavg.sh r4,r4,r4
15207 +       pavg.sh lr,lr,lr
15208 +       pavg.sh r9,pc,sp
15209 +       pavg.sh pc,sp,r3
15210 +       pavg.sh r6,r1,r9
15211 +       .text
15212 +       .global pabs_sb
15213 +pabs_sb:
15214 +       pabs.sb pc,pc
15215 +       pabs.sb r12,r12
15216 +       pabs.sb r5,r5
15217 +       pabs.sb r4,r4
15218 +       pabs.sb lr,lr
15219 +       pabs.sb r11,r6
15220 +       pabs.sb lr,r9
15221 +       pabs.sb sp,r7
15222 +       .text
15223 +       .global pabs_sh
15224 +pabs_sh:
15225 +       pabs.sh pc,pc
15226 +       pabs.sh r12,r12
15227 +       pabs.sh r5,r5
15228 +       pabs.sh r4,r4
15229 +       pabs.sh lr,lr
15230 +       pabs.sh pc,r3
15231 +       pabs.sh r5,r7
15232 +       pabs.sh r4,r0
15233 +       .text
15234 +       .global psad
15235 +psad:
15236 +       psad pc,pc,pc
15237 +       psad r12,r12,r12
15238 +       psad r5,r5,r5
15239 +       psad r4,r4,r4
15240 +       psad lr,lr,lr
15241 +       psad r9,r11,r11
15242 +       psad lr,r4,sp
15243 +       psad lr,r4,r5
15244 +       .text
15245 +       .global pasr_b
15246 +pasr_b:
15247 +       pasr.b pc,pc,0
15248 +       pasr.b r12,r12,7
15249 +       pasr.b r5,r5,4
15250 +       pasr.b r4,r4,3
15251 +       pasr.b lr,lr,1
15252 +       pasr.b pc,r7,1
15253 +       pasr.b sp,lr,6
15254 +       pasr.b sp,r3,2
15255 +       .text
15256 +       .global plsl_b
15257 +plsl_b:
15258 +       plsl.b pc,pc,0
15259 +       plsl.b r12,r12,7
15260 +       plsl.b r5,r5,4
15261 +       plsl.b r4,r4,3
15262 +       plsl.b lr,lr,1
15263 +       plsl.b r2,r11,4
15264 +       plsl.b r8,r5,7
15265 +       plsl.b pc,r0,2
15266 +       .text
15267 +       .global plsr_b
15268 +plsr_b:
15269 +       plsr.b pc,pc,0
15270 +       plsr.b r12,r12,7
15271 +       plsr.b r5,r5,4
15272 +       plsr.b r4,r4,3
15273 +       plsr.b lr,lr,1
15274 +       plsr.b r12,r1,2
15275 +       plsr.b r6,pc,7
15276 +       plsr.b r12,r11,2
15277 +       .text
15278 +       .global pasr_h
15279 +pasr_h:
15280 +       pasr.h pc,pc,0
15281 +       pasr.h r12,r12,15
15282 +       pasr.h r5,r5,8
15283 +       pasr.h r4,r4,7
15284 +       pasr.h lr,lr,1
15285 +       pasr.h r0,r11,10
15286 +       pasr.h r4,r6,8
15287 +       pasr.h r6,r2,4
15288 +       .text
15289 +       .global plsl_h
15290 +plsl_h:
15291 +       plsl.h pc,pc,0
15292 +       plsl.h r12,r12,15
15293 +       plsl.h r5,r5,8
15294 +       plsl.h r4,r4,7
15295 +       plsl.h lr,lr,1
15296 +       plsl.h r5,r10,9
15297 +       plsl.h sp,lr,8
15298 +       plsl.h r0,lr,7
15299 +       .text
15300 +       .global plsr_h
15301 +plsr_h:
15302 +       plsr.h pc,pc,0
15303 +       plsr.h r12,r12,15
15304 +       plsr.h r5,r5,8
15305 +       plsr.h r4,r4,7
15306 +       plsr.h lr,lr,1
15307 +       plsr.h r11,r0,15
15308 +       plsr.h lr,r3,3
15309 +       plsr.h r8,lr,10
15310 +       .text
15311 +       .global packw_sh
15312 +packw_sh:
15313 +       packw.sh pc,pc,pc
15314 +       packw.sh r12,r12,r12
15315 +       packw.sh r5,r5,r5
15316 +       packw.sh r4,r4,r4
15317 +       packw.sh lr,lr,lr
15318 +       packw.sh sp,r11,r10
15319 +       packw.sh r8,r2,r12
15320 +       packw.sh r8,r1,r5
15321 +       .text
15322 +       .global punpckub_h
15323 +punpckub_h:
15324 +       punpckub.h pc,pc:b
15325 +       punpckub.h r12,r12:t
15326 +       punpckub.h r5,r5:t
15327 +       punpckub.h r4,r4:b
15328 +       punpckub.h lr,lr:t
15329 +       punpckub.h r6,r1:t
15330 +       punpckub.h lr,r5:b
15331 +       punpckub.h lr,r2:t
15332 +       .text
15333 +       .global punpcksb_h
15334 +punpcksb_h:
15335 +       punpcksb.h pc,pc:b
15336 +       punpcksb.h r12,r12:t
15337 +       punpcksb.h r5,r5:t
15338 +       punpcksb.h r4,r4:b
15339 +       punpcksb.h lr,lr:t
15340 +       punpcksb.h r4,r7:t
15341 +       punpcksb.h r6,lr:b
15342 +       punpcksb.h r12,r12:t
15343 +       .text
15344 +       .global packsh_ub
15345 +packsh_ub:
15346 +       packsh.ub pc,pc,pc
15347 +       packsh.ub r12,r12,r12
15348 +       packsh.ub r5,r5,r5
15349 +       packsh.ub r4,r4,r4
15350 +       packsh.ub lr,lr,lr
15351 +       packsh.ub r3,r6,r3
15352 +       packsh.ub r8,r0,r3
15353 +       packsh.ub r9,r3,lr
15354 +       .text
15355 +       .global packsh_sb
15356 +packsh_sb:
15357 +       packsh.sb pc,pc,pc
15358 +       packsh.sb r12,r12,r12
15359 +       packsh.sb r5,r5,r5
15360 +       packsh.sb r4,r4,r4
15361 +       packsh.sb lr,lr,lr
15362 +       packsh.sb r6,r8,r1
15363 +       packsh.sb lr,r9,r8
15364 +       packsh.sb sp,r6,r6
15365 +       .text
15366 +       .global andl
15367 +andl:
15368 +       andl pc,0
15369 +       andl r12,65535
15370 +       andl r5,32768
15371 +       andl r4,32767
15372 +       andl lr,1
15373 +       andl pc,23128
15374 +       andl r8,47262
15375 +       andl r7,13719
15376 +       .text
15377 +       .global andl_coh
15378 +andl_coh:
15379 +       andl pc,0,COH
15380 +       andl r12,65535,COH
15381 +       andl r5,32768,COH
15382 +       andl r4,32767,COH
15383 +       andl lr,1,COH
15384 +       andl r6,22753,COH
15385 +       andl r0,40653,COH
15386 +       andl r4,48580,COH
15387 +       .text
15388 +       .global andh
15389 +andh:
15390 +       andh pc,0
15391 +       andh r12,65535
15392 +       andh r5,32768
15393 +       andh r4,32767
15394 +       andh lr,1
15395 +       andh r12,52312
15396 +       andh r3,8675
15397 +       andh r2,42987
15398 +       .text
15399 +       .global andh_coh
15400 +andh_coh:
15401 +       andh pc,0,COH
15402 +       andh r12,65535,COH
15403 +       andh r5,32768,COH
15404 +       andh r4,32767,COH
15405 +       andh lr,1,COH
15406 +       andh r11,34317,COH
15407 +       andh r8,52982,COH
15408 +       andh r10,23683,COH
15409 +       .text
15410 +       .global orl
15411 +orl:
15412 +       orl pc,0
15413 +       orl r12,65535
15414 +       orl r5,32768
15415 +       orl r4,32767
15416 +       orl lr,1
15417 +       orl sp,16766
15418 +       orl r0,21181
15419 +       orl pc,44103
15420 +       .text
15421 +       .global orh
15422 +orh:
15423 +       orh pc,0
15424 +       orh r12,65535
15425 +       orh r5,32768
15426 +       orh r4,32767
15427 +       orh lr,1
15428 +       orh r8,28285
15429 +       orh r12,30492
15430 +       orh r1,59930
15431 +       .text
15432 +       .global eorl
15433 +eorl:
15434 +       eorl pc,0
15435 +       eorl r12,65535
15436 +       eorl r5,32768
15437 +       eorl r4,32767
15438 +       eorl lr,1
15439 +       eorl r4,51129
15440 +       eorl r6,64477
15441 +       eorl r1,20913
15442 +       .text
15443 +       .global eorh
15444 +eorh:
15445 +       eorh pc,0
15446 +       eorh r12,65535
15447 +       eorh r5,32768
15448 +       eorh r4,32767
15449 +       eorh lr,1
15450 +       eorh r0,11732
15451 +       eorh r10,38069
15452 +       eorh r9,57130
15453 +       .text
15454 +       .global mcall
15455 +mcall:
15456 +       mcall pc[0]
15457 +       mcall r12[-4]
15458 +       mcall r5[-131072]
15459 +       mcall r4[131068]
15460 +       mcall lr[4]
15461 +       mcall sp[61180]
15462 +       mcall r4[-35000]
15463 +       mcall r0[9924]
15464 +       .text
15465 +       .global pref
15466 +pref:
15467 +       pref pc[0]
15468 +       pref r12[-1]
15469 +       pref r5[-32768]
15470 +       pref r4[32767]
15471 +       pref lr[1]
15472 +       pref r7[7748]
15473 +       pref r7[-7699]
15474 +       pref r2[-25892]
15475 +       .text
15476 +       .global cache
15477 +cache:
15478 +       cache pc[0],0
15479 +       cache r12[-1],31
15480 +       cache r5[-1024],16
15481 +       cache r4[1023],15
15482 +       cache lr[1],1
15483 +       cache r3[-964],17
15484 +       cache r4[-375],22
15485 +       cache r3[-888],17
15486 +       .text
15487 +       .global sub4
15488 +sub4:
15489 +       sub pc,0
15490 +       sub r12,-1
15491 +       sub r5,-1048576
15492 +       sub r4,1048575
15493 +       sub lr,1
15494 +       sub r2,-619156
15495 +       sub lr,461517
15496 +       sub r8,-185051
15497 +       .text
15498 +       .global cp3
15499 +cp3:
15500 +       cp pc,0
15501 +       cp r12,-1
15502 +       cp r5,-1048576
15503 +       cp r4,1048575
15504 +       cp lr,1
15505 +       cp r1,124078
15506 +       cp r0,-378909
15507 +       cp r4,-243180
15508 +       .text
15509 +       .global mov2
15510 +mov2:
15511 +       mov pc,0
15512 +       mov r12,-1
15513 +       mov r5,-1048576
15514 +       mov r4,1048575
15515 +       mov lr,1
15516 +       mov r5,-317021
15517 +       mov sp,-749164
15518 +       mov r5,940179
15519 +       .text
15520 +       .global brc2
15521 +brc2:
15522 +       breq 0
15523 +       bral -2
15524 +       brls -2097152
15525 +       brpl 2097150
15526 +       brne 2
15527 +       brhi -1796966
15528 +       brqs 1321368
15529 +       brls -577434
15530 +       .text
15531 +       .global rcall2
15532 +rcall2:
15533 +       rcall 0
15534 +       rcall -2
15535 +       rcall -2097152
15536 +       rcall 2097150
15537 +       rcall 2
15538 +       rcall 496820
15539 +       rcall 1085092
15540 +       rcall -1058
15541 +       .text
15542 +       .global sub5
15543 +sub5:
15544 +       sub pc,pc,0
15545 +       sub r12,r12,-1
15546 +       sub r5,r5,-32768
15547 +       sub r4,r4,32767
15548 +       sub lr,lr,1
15549 +       sub pc,pc,-12744
15550 +       sub r7,r7,-27365
15551 +       sub r2,r9,-17358
15552 +       .text
15553 +       .global satsub_w2
15554 +satsub_w2:
15555 +       satsub.w pc,pc,0
15556 +       satsub.w r12,r12,-1
15557 +       satsub.w r5,r5,-32768
15558 +       satsub.w r4,r4,32767
15559 +       satsub.w lr,lr,1
15560 +       satsub.w r2,lr,-2007
15561 +       satsub.w r7,r12,-784
15562 +       satsub.w r4,r7,23180
15563 +       .text
15564 +       .global ld_d4
15565 +ld_d4:
15566 +       ld.d r0,pc[0]
15567 +       ld.d r14,r12[-1]
15568 +       ld.d r8,r5[-32768]
15569 +       ld.d r6,r4[32767]
15570 +       ld.d r2,lr[1]
15571 +       ld.d r14,r11[14784]
15572 +       ld.d r6,r9[-18905]
15573 +       ld.d r2,r3[-6355]
15574 +       .text
15575 +       .global ld_w4
15576 +ld_w4:
15577 +       ld.w pc,pc[0]
15578 +       ld.w r12,r12[-1]
15579 +       ld.w r5,r5[-32768]
15580 +       ld.w r4,r4[32767]
15581 +       ld.w lr,lr[1]
15582 +       ld.w r0,r12[-22133]
15583 +       ld.w sp,pc[-20521]
15584 +       /* ld.w r3,r5[29035] */
15585 +       nop
15586 +       .text
15587 +       .global ld_sh4
15588 +ld_sh4:
15589 +       ld.sh pc,pc[0]
15590 +       ld.sh r12,r12[-1]
15591 +       ld.sh r5,r5[-32768]
15592 +       ld.sh r4,r4[32767]
15593 +       ld.sh lr,lr[1]
15594 +       ld.sh r6,r10[30930]
15595 +       ld.sh r6,r10[21973]
15596 +       /* ld.sh r11,r10[-2058] */
15597 +       nop
15598 +       .text
15599 +       .global ld_uh4
15600 +ld_uh4:
15601 +       ld.uh pc,pc[0]
15602 +       ld.uh r12,r12[-1]
15603 +       ld.uh r5,r5[-32768]
15604 +       ld.uh r4,r4[32767]
15605 +       ld.uh lr,lr[1]
15606 +       ld.uh r1,r9[-13354]
15607 +       ld.uh lr,r11[21337]
15608 +       /* ld.uh r2,lr[-25370] */
15609 +       nop
15610 +       .text
15611 +       .global ld_sb1
15612 +ld_sb1:
15613 +       ld.sb pc,pc[0]
15614 +       ld.sb r12,r12[-1]
15615 +       ld.sb r5,r5[-32768]
15616 +       ld.sb r4,r4[32767]
15617 +       ld.sb lr,lr[1]
15618 +       ld.sb r7,sp[-28663]
15619 +       ld.sb r2,r1[-5879]
15620 +       ld.sb r12,r3[18734]
15621 +       .text
15622 +       .global ld_ub4
15623 +ld_ub4:
15624 +       ld.ub pc,pc[0]
15625 +       ld.ub r12,r12[-1]
15626 +       ld.ub r5,r5[-32768]
15627 +       ld.ub r4,r4[32767]
15628 +       ld.ub lr,lr[1]
15629 +       ld.ub pc,r4[8277]
15630 +       ld.ub r5,r12[19172]
15631 +       ld.ub r10,lr[26347]
15632 +       .text
15633 +       .global st_d4
15634 +st_d4:
15635 +       st.d pc[0],r0
15636 +       st.d r12[-1],r14
15637 +       st.d r5[-32768],r8
15638 +       st.d r4[32767],r6
15639 +       st.d lr[1],r2
15640 +       st.d r5[13200],r10
15641 +       st.d r5[9352],r10
15642 +       st.d r5[32373],r4
15643 +       .text
15644 +       .global st_w4
15645 +st_w4:
15646 +       st.w pc[0],pc
15647 +       st.w r12[-1],r12
15648 +       st.w r5[-32768],r5
15649 +       st.w r4[32767],r4
15650 +       st.w lr[1],lr
15651 +       st.w sp[6136],r7
15652 +       st.w r6[27087],r12
15653 +       /* st.w r3[20143],r7 */
15654 +       nop
15655 +       .text
15656 +       .global st_h4
15657 +st_h4:
15658 +       st.h pc[0],pc
15659 +       st.h r12[-1],r12
15660 +       st.h r5[-32768],r5
15661 +       st.h r4[32767],r4
15662 +       st.h lr[1],lr
15663 +       st.h r4[-9962],r7
15664 +       st.h r9[-16250],r3
15665 +       /* st.h r8[-28810],r7 */
15666 +       nop
15667 +       .text
15668 +       .global st_b4
15669 +st_b4:
15670 +       st.b pc[0],pc
15671 +       st.b r12[-1],r12
15672 +       st.b r5[-32768],r5
15673 +       st.b r4[32767],r4
15674 +       st.b lr[1],lr
15675 +       st.b r12[30102],r6
15676 +       st.b r5[28977],r1
15677 +       st.b r0[5470],r1
15678 +       .text
15679 +       .global mfsr
15680 +mfsr:
15681 +       mfsr pc,0
15682 +       mfsr r12,1020
15683 +       mfsr r5,512
15684 +       mfsr r4,508
15685 +       mfsr lr,4
15686 +       mfsr r2,696
15687 +       mfsr r4,260
15688 +       mfsr r10,1016
15689 +       .text
15690 +       .global mtsr
15691 +mtsr:
15692 +       mtsr 0,pc
15693 +       mtsr 1020,r12
15694 +       mtsr 512,r5
15695 +       mtsr 508,r4
15696 +       mtsr 4,lr
15697 +       mtsr 224,r10
15698 +       mtsr 836,r12
15699 +       mtsr 304,r9
15700 +       .text
15701 +       .global mfdr
15702 +mfdr:
15703 +       mfdr pc,0
15704 +       mfdr r12,1020
15705 +       mfdr r5,512
15706 +       mfdr r4,508
15707 +       mfdr lr,4
15708 +       mfdr r6,932
15709 +       mfdr r5,36
15710 +       mfdr r9,300
15711 +       .text
15712 +       .global mtdr
15713 +mtdr:
15714 +       mtdr 0,pc
15715 +       mtdr 1020,r12
15716 +       mtdr 512,r5
15717 +       mtdr 508,r4
15718 +       mtdr 4,lr
15719 +       mtdr 180,r8
15720 +       mtdr 720,r10
15721 +       mtdr 408,lr
15722 +       .text
15723 +       .global sleep
15724 +sleep:
15725 +       sleep 0
15726 +       sleep 255
15727 +       sleep 128
15728 +       sleep 127
15729 +       sleep 1
15730 +       sleep 254
15731 +       sleep 15
15732 +       sleep 43
15733 +       .text
15734 +       .global sync
15735 +sync:
15736 +       sync 0
15737 +       sync 255
15738 +       sync 128
15739 +       sync 127
15740 +       sync 1
15741 +       sync 166
15742 +       sync 230
15743 +       sync 180
15744 +       .text
15745 +       .global bld
15746 +bld:
15747 +       bld pc,0
15748 +       bld r12,31
15749 +       bld r5,16
15750 +       bld r4,15
15751 +       bld lr,1
15752 +       bld r9,15
15753 +       bld r0,4
15754 +       bld lr,26
15755 +       .text
15756 +       .global bst
15757 +bst:
15758 +       bst pc,0
15759 +       bst r12,31
15760 +       bst r5,16
15761 +       bst r4,15
15762 +       bst lr,1
15763 +       bst r10,28
15764 +       bst r0,3
15765 +       bst sp,2
15766 +       .text
15767 +       .global sats
15768 +sats:
15769 +       sats pc>>0,0
15770 +       sats r12>>31,31
15771 +       sats r5>>16,16
15772 +       sats r4>>15,15
15773 +       sats lr>>1,1
15774 +       sats r10>>3,19
15775 +       sats r10>>2,26
15776 +       sats r1>>20,1
15777 +       .text
15778 +       .global satu
15779 +satu:
15780 +       satu pc>>0,0
15781 +       satu r12>>31,31
15782 +       satu r5>>16,16
15783 +       satu r4>>15,15
15784 +       satu lr>>1,1
15785 +       satu pc>>5,7
15786 +       satu r7>>5,5
15787 +       satu r2>>26,19
15788 +       .text
15789 +       .global satrnds
15790 +satrnds:
15791 +       satrnds pc>>0,0
15792 +       satrnds r12>>31,31
15793 +       satrnds r5>>16,16
15794 +       satrnds r4>>15,15
15795 +       satrnds lr>>1,1
15796 +       satrnds r0>>21,19
15797 +       satrnds sp>>0,2
15798 +       satrnds r7>>6,29
15799 +       .text
15800 +       .global satrndu
15801 +satrndu:
15802 +       satrndu pc>>0,0
15803 +       satrndu r12>>31,31
15804 +       satrndu r5>>16,16
15805 +       satrndu r4>>15,15
15806 +       satrndu lr>>1,1
15807 +       satrndu r12>>0,26
15808 +       satrndu r4>>21,3
15809 +       satrndu r10>>3,16
15810 +       .text
15811 +       .global subfc
15812 +subfc:
15813 +       subfeq pc,0
15814 +       subfal r12,-1
15815 +       subfls r5,-128
15816 +       subfpl r4,127
15817 +       subfne lr,1
15818 +       subfls r10,8
15819 +       subfvc r11,99
15820 +       subfvs r2,73
15821 +       .text
15822 +       .global subc
15823 +subc:
15824 +       subeq pc,0
15825 +       subal r12,-1
15826 +       subls r5,-128
15827 +       subpl r4,127
15828 +       subne lr,1
15829 +       subls r12,118
15830 +       subvc lr,-12
15831 +       submi r4,-13
15832 +       .text
15833 +       .global movc2
15834 +movc2:
15835 +       moveq pc,0
15836 +       moval r12,-1
15837 +       movls r5,-128
15838 +       movpl r4,127
15839 +       movne lr,1
15840 +       movlt r3,-122
15841 +       movvc r8,2
15842 +       movne r7,-111
15843 +       .text
15844 +       .global cp_b
15845 +cp_b:
15846 +       cp.b pc,r0
15847 +       cp.b r0,pc
15848 +       cp.b r7,r8
15849 +       cp.b r8,r7
15850 +       .text
15851 +       .global cp_h
15852 +cp_h:
15853 +       cp.h pc,r0
15854 +       cp.h r0,pc
15855 +       cp.h r7,r8
15856 +       cp.h r8,r7
15857 +       .text
15858 +       .global ldm
15859 +ldm:
15860 +       ldm pc,r1-r6
15861 +       ldm r12,r0-r15
15862 +       ldm r5,r15
15863 +       ldm r4,r0-r14
15864 +       ldm lr,r0
15865 +       ldm r9,r1,r5,r14
15866 +       ldm r11,r2-r3,r5-r8,r15
15867 +       ldm r6,r0,r3,r9,r13,r15
15868 +       .text
15869 +       .global ldm_pu
15870 +ldm_pu:
15871 +       ldm pc++,r6-r9
15872 +       ldm r12++,r0-r15
15873 +       ldm r5++,r15
15874 +       ldm r4++,r0-r14
15875 +       ldm lr++,r0
15876 +       ldm r12++,r3-r5,r8,r10,r12,r14-r15
15877 +       ldm r10++,r2,r4-r6,r14-r15
15878 +       ldm r6++,r1,r3-r4,r9-r14
15879 +       .text
15880 +       .global ldmts
15881 +ldmts:
15882 +       ldmts pc,r7-r8
15883 +       ldmts r12,r0-r15
15884 +       ldmts r5,r15
15885 +       ldmts r4,r0-r14
15886 +       ldmts lr,r0
15887 +       ldmts r0,r1-r2,r11-r12
15888 +       ldmts lr,r0-r2,r4,r7-r8,r13-r14
15889 +       ldmts r12,r0-r1,r3-r5,r9,r14-r15
15890 +       .text
15891 +       .global ldmts_pu
15892 +ldmts_pu:
15893 +       ldmts pc++,r9
15894 +       ldmts r12++,r0-r15
15895 +       ldmts r5++,r15
15896 +       ldmts r4++,r0-r14
15897 +       ldmts lr++,r0
15898 +       ldmts sp++,r0,r2-r5,r7,r9,r11
15899 +       ldmts r5++,r1-r3,r7,r10-r11
15900 +       ldmts r8++,r2-r4,r7-r8,r13,r15
15901 +       .text
15902 +       .global stm
15903 +stm:
15904 +       stm pc,r7
15905 +       stm r12,r0-r15
15906 +       stm r5,r15
15907 +       stm r4,r0-r14
15908 +       stm lr,r0
15909 +       stm sp,r2-r3,r5,r8,r11,r14
15910 +       stm r4,r0-r4,r6,r10-r11,r14
15911 +       stm r9,r1,r5,r9,r12-r15
15912 +       .text
15913 +       .global stm_pu
15914 +stm_pu:
15915 +       stm --pc,r4-r6
15916 +       stm --r12,r0-r15
15917 +       stm --r5,r15
15918 +       stm --r4,r0-r14
15919 +       stm --lr,r0
15920 +       stm --r11,r0,r4-r9,r11-r15
15921 +       stm --r11,r0,r3,r9-r10,r12,r14
15922 +       stm --r6,r2,r8-r9,r13-r14
15923 +       .text
15924 +       .global stmts
15925 +stmts:
15926 +       stmts pc,r8
15927 +       stmts r12,r0-r15
15928 +       stmts r5,r15
15929 +       stmts r4,r0-r14
15930 +       stmts lr,r0
15931 +       stmts r1,r0-r1,r3-r4,r6,r9-r10,r14-r15
15932 +       stmts r3,r0,r6-r8,r10-r12
15933 +       stmts r11,r0,r4,r6-r7,r9-r10,r12,r14-r15
15934 +       .text
15935 +       .global stmts_pu
15936 +stmts_pu:
15937 +       stmts --pc,r6-r8
15938 +       stmts --r12,r0-r15
15939 +       stmts --r5,r15
15940 +       stmts --r4,r0-r14
15941 +       stmts --lr,r0
15942 +       stmts --r2,r0,r3-r4,r9-r10,r12-r13
15943 +       stmts --r3,r0-r1,r14-r15
15944 +       stmts --r0,r0,r2-r6,r10,r14
15945 +       .text
15946 +       .global ldins_h
15947 +ldins_h:
15948 +       ldins.h pc:b,pc[0]
15949 +       ldins.h r12:t,r12[-2]
15950 +       ldins.h r5:t,r5[-4096]
15951 +       ldins.h r4:b,r4[4094]
15952 +       ldins.h lr:t,lr[2]
15953 +       ldins.h r0:t,lr[1930]
15954 +       ldins.h r3:b,r7[-534]
15955 +       ldins.h r2:b,r12[-2252]
15956 +       .text
15957 +       .global ldins_b
15958 +ldins_b:
15959 +       ldins.b pc:b,pc[0]
15960 +       ldins.b r12:t,r12[-1]
15961 +       ldins.b r5:u,r5[-2048]
15962 +       ldins.b r4:l,r4[2047]
15963 +       ldins.b lr:l,lr[1]
15964 +       ldins.b r6:t,r4[-662]
15965 +       ldins.b r5:b,r1[-151]
15966 +       ldins.b r10:t,r11[-1923]
15967 +       .text
15968 +       .global ldswp_sh
15969 +ldswp_sh:
15970 +       ldswp.sh pc,pc[0]
15971 +       ldswp.sh r12,r12[-2]
15972 +       ldswp.sh r5,r5[-4096]
15973 +       ldswp.sh r4,r4[4094]
15974 +       ldswp.sh lr,lr[2]
15975 +       ldswp.sh r9,r10[3848]
15976 +       ldswp.sh r4,r12[-2040]
15977 +       ldswp.sh r10,r2[3088]
15978 +       .text
15979 +       .global ldswp_uh
15980 +ldswp_uh:
15981 +       ldswp.uh pc,pc[0]
15982 +       ldswp.uh r12,r12[-2]
15983 +       ldswp.uh r5,r5[-4096]
15984 +       ldswp.uh r4,r4[4094]
15985 +       ldswp.uh lr,lr[2]
15986 +       ldswp.uh r4,r9[3724]
15987 +       ldswp.uh lr,sp[-1672]
15988 +       ldswp.uh r8,r12[-3846]
15989 +       .text
15990 +       .global ldswp_w
15991 +ldswp_w:
15992 +       ldswp.w pc,pc[0]
15993 +       ldswp.w r12,r12[-4]
15994 +       ldswp.w r5,r5[-8192]
15995 +       ldswp.w r4,r4[8188]
15996 +       ldswp.w lr,lr[4]
15997 +       ldswp.w sp,r7[1860]
15998 +       ldswp.w pc,r5[-3324]
15999 +       ldswp.w r12,r10[-3296]
16000 +       .text
16001 +       .global stswp_h
16002 +stswp_h:
16003 +       stswp.h pc[0],pc
16004 +       stswp.h r12[-2],r12
16005 +       stswp.h r5[-4096],r5
16006 +       stswp.h r4[4094],r4
16007 +       stswp.h lr[2],lr
16008 +       stswp.h r7[64],r10
16009 +       stswp.h r10[3024],r2
16010 +       stswp.h r0[-2328],r10
16011 +       .text
16012 +       .global stswp_w
16013 +stswp_w:
16014 +       stswp.w pc[0],pc
16015 +       stswp.w r12[-4],r12
16016 +       stswp.w r5[-8192],r5
16017 +       stswp.w r4[8188],r4
16018 +       stswp.w lr[4],lr
16019 +       stswp.w pc[1156],r8
16020 +       stswp.w sp[7992],r10
16021 +       stswp.w r8[-1172],r5
16022 +       .text
16023 +       .global and2
16024 +and2:
16025 +       and pc,pc,pc<<0
16026 +       and r12,r12,r12<<31
16027 +       and r5,r5,r5<<16
16028 +       and r4,r4,r4<<15
16029 +       and lr,lr,lr<<1
16030 +       and r10,r2,r1<<1
16031 +       and r12,r8,r11<<27
16032 +       and r10,r7,r0<<3
16033 +       .text
16034 +       .global and3
16035 +and3:
16036 +       and pc,pc,pc>>0
16037 +       and r12,r12,r12>>31
16038 +       and r5,r5,r5>>16
16039 +       and r4,r4,r4>>15
16040 +       and lr,lr,lr>>1
16041 +       and r12,r8,r7>>17
16042 +       and pc,r4,r9>>20
16043 +       and r10,r9,r10>>12
16044 +       .text
16045 +       .global or2
16046 +or2:
16047 +       or pc,pc,pc<<0
16048 +       or r12,r12,r12<<31
16049 +       or r5,r5,r5<<16
16050 +       or r4,r4,r4<<15
16051 +       or lr,lr,lr<<1
16052 +       or r8,sp,r11<<29
16053 +       or pc,r9,r2<<28
16054 +       or r5,r1,r2<<3
16055 +       .text
16056 +       .global or3
16057 +or3:
16058 +       or pc,pc,pc>>0
16059 +       or r12,r12,r12>>31
16060 +       or r5,r5,r5>>16
16061 +       or r4,r4,r4>>15
16062 +       or lr,lr,lr>>1
16063 +       or r1,sp,sp>>2
16064 +       or r0,r1,r1>>29
16065 +       or r4,r12,r8>>8
16066 +       .text
16067 +       .global eor2
16068 +eor2:
16069 +       eor pc,pc,pc<<0
16070 +       eor r12,r12,r12<<31
16071 +       eor r5,r5,r5<<16
16072 +       eor r4,r4,r4<<15
16073 +       eor lr,lr,lr<<1
16074 +       eor r10,r9,r4<<11
16075 +       eor r4,r0,r1<<31
16076 +       eor r6,r2,r12<<13
16077 +       .text
16078 +       .global eor3
16079 +eor3:
16080 +       eor pc,pc,pc>>0
16081 +       eor r12,r12,r12>>31
16082 +       eor r5,r5,r5>>16
16083 +       eor r4,r4,r4>>15
16084 +       eor lr,lr,lr>>1
16085 +       eor r5,r5,r5>>22
16086 +       eor r10,r1,lr>>3
16087 +       eor r7,lr,sp>>26
16088 +       .text
16089 +       .global sthh_w2
16090 +sthh_w2:
16091 +       sthh.w pc[pc<<0],pc:b,pc:b
16092 +       sthh.w r12[r12<<3],r12:t,r12:t
16093 +       sthh.w r5[r5<<2],r5:t,r5:t
16094 +       sthh.w r4[r4<<1],r4:b,r4:b
16095 +       sthh.w lr[lr<<1],lr:t,lr:t
16096 +       sthh.w sp[r6<<3],r1:t,r12:t
16097 +       sthh.w r6[r6<<0],r9:t,r9:t
16098 +       sthh.w r10[r3<<0],r0:b,r11:t
16099 +       .text
16100 +       .global sthh_w1
16101 +sthh_w1:
16102 +       sthh.w pc[0],pc:b,pc:b
16103 +       sthh.w r12[1020],r12:t,r12:t
16104 +       sthh.w r5[512],r5:t,r5:t
16105 +       sthh.w r4[508],r4:b,r4:b
16106 +       sthh.w lr[4],lr:t,lr:t
16107 +       sthh.w r4[404],r9:t,r0:b
16108 +       sthh.w r8[348],r2:t,r10:b
16109 +       sthh.w sp[172],r9:b,r2:b
16110 +       .text
16111 +       .global cop
16112 +cop:
16113 +       cop cp0,cr0,cr0,cr0,0
16114 +       cop cp7,cr15,cr15,cr15,0x7f
16115 +       cop cp3,cr5,cr5,cr5,0x31
16116 +       cop cp2,cr4,cr4,cr4,0x30
16117 +       cop cp5,cr8,cr3,cr7,0x5a
16118 +       .text
16119 +       .global ldc_w1
16120 +ldc_w1:
16121 +       ldc.w cp0,cr0,r0[0]
16122 +       ldc.w cp7,cr15,pc[255<<2]
16123 +       ldc.w cp3,cr5,r5[128<<2]
16124 +       ldc.w cp2,cr4,r4[127<<2]
16125 +       ldc.w cp4,cr9,r13[36<<2]
16126 +       .text
16127 +       .global ldc_w2
16128 +ldc_w2:
16129 +       ldc.w cp0,cr0,--r0
16130 +       ldc.w cp7,cr15,--pc
16131 +       ldc.w cp3,cr5,--r5
16132 +       ldc.w cp2,cr4,--r4
16133 +       ldc.w cp4,cr9,--r13
16134 +       .text
16135 +       .global ldc_w3
16136 +ldc_w3:
16137 +       ldc.w cp0,cr0,r0[r0]
16138 +       ldc.w cp7,cr15,pc[pc<<3]
16139 +       ldc.w cp3,cr5,r5[r4<<2]
16140 +       ldc.w cp2,cr4,r4[r3<<1]
16141 +       ldc.w cp4,cr9,r13[r12<<0]
16142 +       .text
16143 +       .global ldc_d1
16144 +ldc_d1:
16145 +       ldc.d cp0,cr0,r0[0]
16146 +       ldc.d cp7,cr14,pc[255<<2]
16147 +       ldc.d cp3,cr6,r5[128<<2]
16148 +       ldc.d cp2,cr4,r4[127<<2]
16149 +       ldc.d cp4,cr8,r13[36<<2]
16150 +       .text
16151 +       .global ldc_d2
16152 +ldc_d2:
16153 +       ldc.d cp0,cr0,--r0
16154 +       ldc.d cp7,cr14,--pc
16155 +       ldc.d cp3,cr6,--r5
16156 +       ldc.d cp2,cr4,--r4
16157 +       ldc.d cp4,cr8,--r13
16158 +       .text
16159 +       .global ldc_d3
16160 +ldc_d3:
16161 +       ldc.d cp0,cr0,r0[r0]
16162 +       ldc.d cp7,cr14,pc[pc<<3]
16163 +       ldc.d cp3,cr6,r5[r4<<2]
16164 +       ldc.d cp2,cr4,r4[r3<<1]
16165 +       ldc.d cp4,cr8,r13[r12<<0]
16166 +       .text
16167 +       .global stc_w1
16168 +stc_w1:
16169 +       stc.w cp0,r0[0],cr0
16170 +       stc.w cp7,pc[255<<2],cr15
16171 +       stc.w cp3,r5[128<<2],cr5
16172 +       stc.w cp2,r4[127<<2],cr4
16173 +       stc.w cp4,r13[36<<2],cr9
16174 +       .text
16175 +       .global stc_w2
16176 +stc_w2:
16177 +       stc.w cp0,r0++,cr0
16178 +       stc.w cp7,pc++,cr15
16179 +       stc.w cp3,r5++,cr5
16180 +       stc.w cp2,r4++,cr4
16181 +       stc.w cp4,r13++,cr9
16182 +       .text
16183 +       .global stc_w3
16184 +stc_w3:
16185 +       stc.w cp0,r0[r0],cr0
16186 +       stc.w cp7,pc[pc<<3],cr15
16187 +       stc.w cp3,r5[r4<<2],cr5
16188 +       stc.w cp2,r4[r3<<1],cr4
16189 +       stc.w cp4,r13[r12<<0],cr9
16190 +       .text
16191 +       .global stc_d1
16192 +stc_d1:
16193 +       stc.d cp0,r0[0],cr0
16194 +       stc.d cp7,pc[255<<2],cr14
16195 +       stc.d cp3,r5[128<<2],cr6
16196 +       stc.d cp2,r4[127<<2],cr4
16197 +       stc.d cp4,r13[36<<2],cr8
16198 +       .text
16199 +       .global stc_d2
16200 +stc_d2:
16201 +       stc.d cp0,r0++,cr0
16202 +       stc.d cp7,pc++,cr14
16203 +       stc.d cp3,r5++,cr6
16204 +       stc.d cp2,r4++,cr4
16205 +       stc.d cp4,r13++,cr8
16206 +       .text
16207 +       .global stc_d3
16208 +stc_d3:
16209 +       stc.d cp0,r0[r0],cr0
16210 +       stc.d cp7,pc[pc<<3],cr14
16211 +       stc.d cp3,r5[r4<<2],cr6
16212 +       stc.d cp2,r4[r3<<1],cr4
16213 +       stc.d cp4,r13[r12<<0],cr8
16214 +       .text
16215 +       .global ldc0_w
16216 +ldc0_w:
16217 +       ldc0.w cr0,r0[0]
16218 +       ldc0.w cr15,pc[4095<<2]
16219 +       ldc0.w cr5,r5[2048<<2]
16220 +       ldc0.w cr4,r4[2047<<2]
16221 +       ldc0.w cr9,r13[147<<2]
16222 +       .text
16223 +       .global ldc0_d
16224 +ldc0_d:
16225 +       ldc0.d cr0,r0[0]
16226 +       ldc0.d cr14,pc[4095<<2]
16227 +       ldc0.d cr6,r5[2048<<2]
16228 +       ldc0.d cr4,r4[2047<<2]
16229 +       ldc0.d cr8,r13[147<<2]
16230 +       .text
16231 +       .global stc0_w
16232 +stc0_w:
16233 +       stc0.w r0[0],cr0
16234 +       stc0.w pc[4095<<2],cr15
16235 +       stc0.w r5[2048<<2],cr5
16236 +       stc0.w r4[2047<<2],cr4
16237 +       stc0.w r13[147<<2],cr9
16238 +       .text
16239 +       .global stc0_d
16240 +stc0_d:
16241 +       stc0.d r0[0],cr0
16242 +       stc0.d pc[4095<<2],cr14
16243 +       stc0.d r5[2048<<2],cr6
16244 +       stc0.d r4[2047<<2],cr4
16245 +       stc0.d r13[147<<2],cr8
16246 +       .text
16247 +       .global memc
16248 +memc:
16249 +       memc 0, 0
16250 +       memc -4, 31
16251 +       memc -65536, 16
16252 +       memc 65532, 15
16253 +       .text
16254 +       .global mems
16255 +mems:
16256 +       mems 0, 0
16257 +       mems -4, 31
16258 +       mems -65536, 16
16259 +       mems 65532, 15
16260 +       .text
16261 +       .global memt
16262 +memt:
16263 +       memt 0, 0
16264 +       memt -4, 31
16265 +       memt -65536, 16
16266 +       memt 65532, 15
16267 +
16268 +       .text
16269 +       .global stcond
16270 +stcond:
16271 +       stcond r0[0], r0
16272 +       stcond pc[-1], pc
16273 +       stcond r8[-32768], r7
16274 +       stcond r7[32767], r8
16275 +       stcond r5[0x1234], r10
16276 +
16277 +ldcm_w:
16278 +       ldcm.w cp0,pc,cr0-cr7
16279 +       ldcm.w cp7,r0,cr0
16280 +       ldcm.w cp4,r4++,cr0-cr6
16281 +       ldcm.w cp3,r7,cr7
16282 +       ldcm.w cp1,r12++,cr1,cr4-cr6
16283 +       ldcm.w cp0,pc,cr8-cr15
16284 +       ldcm.w cp7,r0,cr8
16285 +       ldcm.w cp4,r4++,cr8-cr14
16286 +       ldcm.w cp3,r7,cr15
16287 +       ldcm.w cp1,r12++,cr9,cr12-cr14
16288 +
16289 +ldcm_d:
16290 +       ldcm.d cp0,pc,cr0-cr15
16291 +       ldcm.d cp7,r0,cr0,cr1
16292 +       ldcm.d cp4,r4++,cr0-cr13
16293 +       ldcm.d cp3,r7,cr14-cr15
16294 +       ldcm.d cp2,r12++,cr0-cr3,cr8-cr9,cr14-cr15
16295 +
16296 +stcm_w:
16297 +       stcm.w cp0,pc,cr0-cr7
16298 +       stcm.w cp7,r0,cr0
16299 +       stcm.w cp4,--r4,cr0-cr6
16300 +       stcm.w cp3,r7,cr7
16301 +       stcm.w cp1,--r12,cr1,cr4-cr6
16302 +       stcm.w cp0,pc,cr8-cr15
16303 +       stcm.w cp7,r0,cr8
16304 +       stcm.w cp4,--r4,cr8-cr14
16305 +       stcm.w cp3,r7,cr15
16306 +       stcm.w cp1,--r12,cr9,cr12-cr14
16307 +
16308 +stcm_d:
16309 +       stcm.d cp0,pc,cr0-cr15
16310 +       stcm.d cp7,r0,cr0,cr1
16311 +       stcm.d cp4,--r4,cr0-cr13
16312 +       stcm.d cp3,r7,cr14-cr15
16313 +       stcm.d cp2,--r12,cr0-cr3,cr8-cr9,cr14-cr15
16314 +
16315 +mvcr_w:
16316 +       mvcr.w cp7,pc,cr15
16317 +       mvcr.w cp0,r0,cr0
16318 +       mvcr.w cp0,pc,cr15
16319 +       mvcr.w cp7,r0,cr15
16320 +       mvcr.w cp7,pc,cr0
16321 +       mvcr.w cp4,r7,cr8
16322 +       mvcr.w cp3,r8,cr7
16323 +
16324 +mvcr_d:
16325 +       mvcr.d cp7,lr,cr14
16326 +       mvcr.d cp0,r0,cr0
16327 +       mvcr.d cp0,lr,cr14
16328 +       mvcr.d cp7,r0,cr14
16329 +       mvcr.d cp7,lr,cr0
16330 +       mvcr.d cp4,r6,cr8
16331 +       mvcr.d cp3,r8,cr6
16332 +
16333 +mvrc_w:
16334 +       mvrc.w cp7,cr15,pc
16335 +       mvrc.w cp0,cr0,r0
16336 +       mvrc.w cp0,cr15,pc
16337 +       mvrc.w cp7,cr15,r0
16338 +       mvrc.w cp7,cr0,pc
16339 +       mvrc.w cp4,cr8,r7
16340 +       mvrc.w cp3,cr7,r8
16341 +
16342 +mvrc_d:
16343 +       mvrc.d cp7,cr14,lr
16344 +       mvrc.d cp0,cr0,r0
16345 +       mvrc.d cp0,cr14,lr
16346 +       mvrc.d cp7,cr14,r0
16347 +       mvrc.d cp7,cr0,lr
16348 +       mvrc.d cp4,cr8,r6
16349 +       mvrc.d cp3,cr6,r8
16350 +
16351 +bfexts:
16352 +       bfexts pc,pc,31,31
16353 +       bfexts r0,r0,0,0
16354 +       bfexts r0,pc,31,31
16355 +       bfexts pc,r0,31,31
16356 +       bfexts pc,pc,0,31
16357 +       bfexts pc,pc,31,0
16358 +       bfexts r7,r8,15,16
16359 +       bfexts r8,r7,16,15
16360 +
16361 +bfextu:
16362 +       bfextu pc,pc,31,31
16363 +       bfextu r0,r0,0,0
16364 +       bfextu r0,pc,31,31
16365 +       bfextu pc,r0,31,31
16366 +       bfextu pc,pc,0,31
16367 +       bfextu pc,pc,31,0
16368 +       bfextu r7,r8,15,16
16369 +       bfextu r8,r7,16,15
16370 +
16371 +bfins:
16372 +       bfins pc,pc,31,31
16373 +       bfins r0,r0,0,0
16374 +       bfins r0,pc,31,31
16375 +       bfins pc,r0,31,31
16376 +       bfins pc,pc,0,31
16377 +       bfins pc,pc,31,0
16378 +       bfins r7,r8,15,16
16379 +       bfins r8,r7,16,15
16380 +
16381 +rsubc:
16382 +       rsubeq pc,0
16383 +       rsubal r12,-1
16384 +       rsubls r5,-128
16385 +       rsubpl r4,127
16386 +       rsubne lr,1
16387 +       rsubls r12,118
16388 +       rsubvc lr,-12
16389 +       rsubmi r4,-13
16390 +
16391 +addc:
16392 +       addeq pc,pc,pc
16393 +       addal r12,r12,r12
16394 +       addls r5,r5,r5
16395 +       addpl r4,r4,r4
16396 +       addne lr,lr,lr
16397 +       addls r10,r2,r1
16398 +       addvc r12,r8,r11
16399 +       addmi r10,r7,r0
16400 +
16401 +subc2:
16402 +       subeq pc,pc,pc
16403 +       subal r12,r12,r12
16404 +       subls r5,r5,r5
16405 +       subpl r4,r4,r4
16406 +       subne lr,lr,lr
16407 +       subls r10,r2,r1
16408 +       subvc r12,r8,r11
16409 +       submi r10,r7,r0
16410 +
16411 +andc:
16412 +       andeq pc,pc,pc
16413 +       andal r12,r12,r12
16414 +       andls r5,r5,r5
16415 +       andpl r4,r4,r4
16416 +       andne lr,lr,lr
16417 +       andls r10,r2,r1
16418 +       andvc r12,r8,r11
16419 +       andmi r10,r7,r0
16420 +
16421 +orc:
16422 +       oreq pc,pc,pc
16423 +       oral r12,r12,r12
16424 +       orls r5,r5,r5
16425 +       orpl r4,r4,r4
16426 +       orne lr,lr,lr
16427 +       orls r10,r2,r1
16428 +       orvc r12,r8,r11
16429 +       ormi r10,r7,r0
16430 +
16431 +eorc:
16432 +       eoreq pc,pc,pc
16433 +       eoral r12,r12,r12
16434 +       eorls r5,r5,r5
16435 +       eorpl r4,r4,r4
16436 +       eorne lr,lr,lr
16437 +       eorls r10,r2,r1
16438 +       eorvc r12,r8,r11
16439 +       eormi r10,r7,r0
16440 +
16441 +ldcond:
16442 +       ld.weq  pc,pc[2044]
16443 +       ld.shal r12,r12[1022]
16444 +       ld.uhls r5,r5[0]
16445 +       ld.ubpl r4,r4[511]
16446 +       ld.sbne lr,lr[0]
16447 +       ld.wls  r10,r2[0]
16448 +       ld.shvc r12,r8[0x3fe]
16449 +       ld.ubmi r10,r7[1]
16450 +
16451 +stcond2:
16452 +       st.weq pc[2044],pc
16453 +       st.hal r12[1022],r12
16454 +       st.hls r5[0],r5
16455 +       st.bpl r4[511],r4
16456 +       st.bne lr[0],lr
16457 +       st.wls r2[0],r10
16458 +       st.hvc r8[0x3fe],r12
16459 +       st.bmi r7[1],r10
16460 +
16461 +movh:
16462 +       movh    pc, 65535
16463 +       movh    r0, 0
16464 +       movh    r5, 1
16465 +       movh    r12, 32767
16466 +
16467 +
16468 --- /dev/null
16469 +++ b/gas/testsuite/gas/avr32/avr32.exp
16470 @@ -0,0 +1,23 @@
16471 +# AVR32 assembler testsuite. -*- Tcl -*-
16472 +
16473 +if [istarget avr32-*-*] {
16474 +    run_dump_test "hwrd-lwrd"
16475 +    run_dump_test "pcrel"
16476 +    run_dump_test "aliases"
16477 +    run_dump_test "dwarf2"
16478 +    run_dump_test "pic_reloc"
16479 +    run_dump_test "fpinsn"
16480 +    run_dump_test "pico"
16481 +    run_dump_test "lda_pic"
16482 +    run_dump_test "lda_pic_linkrelax"
16483 +    run_dump_test "lda_nopic"
16484 +    run_dump_test "lda_nopic_linkrelax"
16485 +    run_dump_test "call_pic"
16486 +    run_dump_test "call_pic_linkrelax"
16487 +    run_dump_test "call_nopic"
16488 +    run_dump_test "call_nopic_linkrelax"
16489 +    run_dump_test "jmptable"
16490 +    run_dump_test "jmptable_linkrelax"
16491 +    run_dump_test "symdiff"
16492 +    run_dump_test "symdiff_linkrelax"
16493 +}
16494 --- /dev/null
16495 +++ b/gas/testsuite/gas/avr32/call_nopic.d
16496 @@ -0,0 +1,36 @@
16497 +#source: call.s
16498 +#as:
16499 +#objdump: -dr
16500 +#name: call_nopic
16501 +
16502 +.*: +file format .*
16503 +
16504 +Disassembly of section \.text:
16505 +
16506 +00000000 <call_test>:
16507 +       0:      d7 03           nop
16508 +
16509 +00000002 <toofar_negative>:
16510 +       \.\.\.
16511 +  1ffffe:      00 00           add r0,r0
16512 +  200000:      f0 a0 00 00     rcall 0 <call_test>
16513 +  200004:      f0 1f 00 0c     mcall 200034 <toofar_negative\+0x200032>
16514 +  200008:      f0 1f 00 0c     mcall 200038 <toofar_negative\+0x200036>
16515 +  20000c:      f0 1f 00 0c     mcall 20003c <toofar_negative\+0x20003a>
16516 +  200010:      f0 1f 00 0c     mcall 200040 <toofar_negative\+0x20003e>
16517 +       \.\.\.
16518 +  200030:      ee b0 ff ff     rcall 40002e <far_positive>
16519 +       \.\.\.
16520 +                       200034: R_AVR32_32_CPENT        \.text\+0x2
16521 +                       200038: R_AVR32_32_CPENT        \.text\.init
16522 +                       20003c: R_AVR32_32_CPENT        undefined
16523 +                       200040: R_AVR32_32_CPENT        \.text\+0x40002c
16524 +
16525 +0040002c <toofar_positive>:
16526 +  40002c:      d7 03           nop
16527 +0040002e <far_positive>:
16528 +  40002e:      d7 03           nop
16529 +Disassembly of section \.text\.init:
16530 +
16531 +00000000 <different_section>:
16532 +   0:  e2 c0 00 00     sub r0,r1,0
16533 --- /dev/null
16534 +++ b/gas/testsuite/gas/avr32/call_nopic_linkrelax.d
16535 @@ -0,0 +1,43 @@
16536 +#source: call.s
16537 +#as: --linkrelax
16538 +#objdump: -dr
16539 +#name: call_nopic_linkrelax
16540 +
16541 +.*: +file format .*
16542 +
16543 +Disassembly of section \.text:
16544 +
16545 +00000000 <call_test>:
16546 +       0:      d7 03           nop
16547 +
16548 +00000002 <toofar_negative>:
16549 +       \.\.\.
16550 +  1ffffe:      00 00           add r0,r0
16551 +  200000:      e0 a0 00 00     rcall 200000 <toofar_negative\+0x1ffffe>
16552 +                       200000: R_AVR32_22H_PCREL       \.text
16553 +  200004:      f0 1f 00 00     mcall 200004 <toofar_negative\+0x200002>
16554 +                       200004: R_AVR32_CPCALL  \.text\+0x200034
16555 +  200008:      f0 1f 00 00     mcall 200008 <toofar_negative\+0x200006>
16556 +                       200008: R_AVR32_CPCALL  \.text\+0x200038
16557 +  20000c:      f0 1f 00 00     mcall 20000c <toofar_negative\+0x20000a>
16558 +                       20000c: R_AVR32_CPCALL  \.text\+0x20003c
16559 +  200010:      f0 1f 00 00     mcall 200010 <toofar_negative\+0x20000e>
16560 +                       200010: R_AVR32_CPCALL  \.text\+0x200040
16561 +       \.\.\.
16562 +  200030:      e0 a0 00 00     rcall 200030 <toofar_negative\+0x20002e>
16563 +                       200030: R_AVR32_22H_PCREL       \.text\+0x40002e
16564 +       \.\.\.
16565 +                       200034: R_AVR32_ALIGN   \*ABS\*\+0x2
16566 +                       200034: R_AVR32_32_CPENT        \.text\+0x2
16567 +                       200038: R_AVR32_32_CPENT        \.text\.init
16568 +                       20003c: R_AVR32_32_CPENT        undefined
16569 +                       200040: R_AVR32_32_CPENT        \.text\+0x40002c
16570 +
16571 +0040002c <toofar_positive>:
16572 +  40002c:      d7 03           nop
16573 +0040002e <far_positive>:
16574 +  40002e:      d7 03           nop
16575 +Disassembly of section \.text\.init:
16576 +
16577 +00000000 <different_section>:
16578 +   0:  e2 c0 00 00     sub r0,r1,0
16579 --- /dev/null
16580 +++ b/gas/testsuite/gas/avr32/call_pic.d
16581 @@ -0,0 +1,36 @@
16582 +#source: call.s
16583 +#as: --pic
16584 +#objdump: -dr
16585 +#name: call_pic
16586 +
16587 +.*: +file format .*
16588 +
16589 +Disassembly of section \.text:
16590 +
16591 +00000000 <call_test>:
16592 +       0:      d7 03           nop
16593 +
16594 +00000002 <toofar_negative>:
16595 +       \.\.\.
16596 +  1ffffe:      00 00           add r0,r0
16597 +  200000:      f0 a0 00 00     rcall 0 <call_test>
16598 +  200004:      f0 16 00 00     mcall r6\[0\]
16599 +                       200004: R_AVR32_GOT18SW toofar_negative
16600 +  200008:      f0 16 00 00     mcall r6\[0\]
16601 +                       200008: R_AVR32_GOT18SW different_section
16602 +  20000c:      f0 16 00 00     mcall r6\[0\]
16603 +                       20000c: R_AVR32_GOT18SW undefined
16604 +  200010:      f0 16 00 00     mcall r6\[0\]
16605 +                       200010: R_AVR32_GOT18SW toofar_positive
16606 +       \.\.\.
16607 +  200030:      ee b0 ff ff     rcall 40002e <far_positive>
16608 +       \.\.\.
16609 +
16610 +0040002c <toofar_positive>:
16611 +  40002c:      d7 03           nop
16612 +0040002e <far_positive>:
16613 +  40002e:      d7 03           nop
16614 +Disassembly of section \.text\.init:
16615 +
16616 +00000000 <different_section>:
16617 +   0:  e2 c0 00 00     sub r0,r1,0
16618 --- /dev/null
16619 +++ b/gas/testsuite/gas/avr32/call_pic_linkrelax.d
16620 @@ -0,0 +1,47 @@
16621 +#source: call.s
16622 +#as: --pic --linkrelax
16623 +#objdump: -dr
16624 +#name: call_pic_linkrelax
16625 +
16626 +.*: +file format .*
16627 +
16628 +Disassembly of section \.text:
16629 +
16630 +00000000 <call_test>:
16631 +       0:      d7 03           nop
16632 +
16633 +00000002 <toofar_negative>:
16634 +       \.\.\.
16635 +  1ffffe:      00 00           add r0,r0
16636 +  200000:      e0 a0 00 00     rcall 200000 <toofar_negative\+0x1ffffe>
16637 +                       200000: R_AVR32_22H_PCREL       \.text
16638 +  200004:      e0 6e 00 00     mov lr,0
16639 +                       200004: R_AVR32_GOTCALL toofar_negative
16640 +  200008:      ec 0e 03 2e     ld\.w lr,r6\[lr<<0x2\]
16641 +  20000c:      5d 1e           icall lr
16642 +  20000e:      e0 6e 00 00     mov lr,0
16643 +                       20000e: R_AVR32_GOTCALL different_section
16644 +  200012:      ec 0e 03 2e     ld\.w lr,r6\[lr<<0x2\]
16645 +  200016:      5d 1e           icall lr
16646 +  200018:      e0 6e 00 00     mov lr,0
16647 +                       200018: R_AVR32_GOTCALL undefined
16648 +  20001c:      ec 0e 03 2e     ld\.w lr,r6\[lr<<0x2\]
16649 +  200020:      5d 1e           icall lr
16650 +  200022:      e0 6e 00 00     mov lr,0
16651 +                       200022: R_AVR32_GOTCALL toofar_positive
16652 +  200026:      ec 0e 03 2e     ld\.w lr,r6\[lr<<0x2\]
16653 +  20002a:      5d 1e           icall lr
16654 +  20002c:      00 00           add r0,r0
16655 +  20002e:      00 00           add r0,r0
16656 +  200030:      e0 a0 00 00     rcall 200030 <toofar_negative\+0x20002e>
16657 +                       200030: R_AVR32_22H_PCREL       \.text\+0x40002e
16658 +       \.\.\.
16659 +
16660 +0040002c <toofar_positive>:
16661 +  40002c:      d7 03           nop
16662 +0040002e <far_positive>:
16663 +  40002e:      d7 03           nop
16664 +Disassembly of section \.text\.init:
16665 +
16666 +00000000 <different_section>:
16667 +   0:  e2 c0 00 00     sub r0,r1,0
16668 --- /dev/null
16669 +++ b/gas/testsuite/gas/avr32/call.s
16670 @@ -0,0 +1,30 @@
16671 +
16672 +       .text
16673 +       .global call_test
16674 +call_test:
16675 +far_negative:
16676 +       nop
16677 +toofar_negative:
16678 +
16679 +       .org    0x200000
16680 +
16681 +       call    far_negative
16682 +       call    toofar_negative
16683 +       call    different_section
16684 +       call    undefined
16685 +       call    toofar_positive
16686 +       .org    0x200030
16687 +       call    far_positive
16688 +
16689 +       .cpool
16690 +
16691 +       .org    0x40002c
16692 +
16693 +toofar_positive:
16694 +       nop
16695 +far_positive:
16696 +       nop
16697 +
16698 +       .section .text.init,"ax",@progbits
16699 +different_section:
16700 +       sub     r0, r1, 0
16701 --- /dev/null
16702 +++ b/gas/testsuite/gas/avr32/dwarf2.d
16703 @@ -0,0 +1,42 @@
16704 +#readelf: -wl
16705 +#name: dwarf2
16706 +#source: dwarf2.s
16707 +
16708 +Dump of debug contents of section \.debug_line:
16709 +
16710 +  Length:                      53
16711 +  DWARF Version:               2
16712 +  Prologue Length:             26
16713 +  Minimum Instruction Length:  1
16714 +  Initial value of 'is_stmt':  1
16715 +  Line Base:                   -5
16716 +  Line Range:                  14
16717 +  Opcode Base:                 10
16718 +  \(Pointer size:               4\)
16719 +
16720 + Opcodes:
16721 +  Opcode 1 has 0 args
16722 +  Opcode 2 has 1 args
16723 +  Opcode 3 has 1 args
16724 +  Opcode 4 has 1 args
16725 +  Opcode 5 has 1 args
16726 +  Opcode 6 has 0 args
16727 +  Opcode 7 has 0 args
16728 +  Opcode 8 has 0 args
16729 +  Opcode 9 has 1 args
16730 +
16731 + The Directory Table is empty\.
16732 +
16733 + The File Name Table:
16734 +  Entry        Dir     Time    Size    Name
16735 +  1    0       0       0       main\.c
16736 +
16737 + Line Number Statements:
16738 +  Extended opcode 2: set Address to 0x0
16739 +  Advance Line by 87 to 88
16740 +  Copy
16741 +  Advance Line by 23 to 111
16742 +  Special opcode .*: advance Address by 4 to 0x4 and Line by 0 to 111
16743 +  Special opcode .*: advance Address by 10 to 0xe and Line by 1 to 112
16744 +  Advance PC by 530 to 220
16745 +  Extended opcode 1: End of Sequence
16746 --- /dev/null
16747 +++ b/gas/testsuite/gas/avr32/dwarf2.s
16748 @@ -0,0 +1,67 @@
16749 +# Source file used to test DWARF2 information for AVR32.
16750 +
16751 +       .file   "main.c"
16752 +
16753 +       .section .debug_abbrev,"",@progbits
16754 +.Ldebug_abbrev0:
16755 +       .section .debug_info,"",@progbits
16756 +.Ldebug_info0:
16757 +       .section .debug_line,"",@progbits
16758 +.Ldebug_line0:
16759 +
16760 +       .text
16761 +       .align  1
16762 +       .globl  main
16763 +       .type   main, @function
16764 +.Ltext0:
16765 +main:
16766 +       .file 1 "main.c"
16767 +       .loc 1 88 0
16768 +       pushm   r0-r7,lr
16769 +       sub     sp, 4
16770 +       .loc 1 111 0
16771 +       lddpc   r12, .LC1
16772 +       lddpc   r7, .LC1
16773 +       icall   r7
16774 +       .loc 1 112 0
16775 +       lddpc   r6, .LC4
16776 +
16777 +       .align  2
16778 +.LC4:  .int    0
16779 +
16780 +       .fill   256, 2, 0
16781 +
16782 +       .align  2
16783 +.LC1:
16784 +       .int    0
16785 +.LC2:
16786 +       .int    0
16787 +.LC3:
16788 +       .int    0
16789 +       .size   main, . - main
16790 +
16791 +.Letext0:
16792 +
16793 +       .section .debug_info
16794 +       .int    .Ledebug_info0 - .Ldebug_info0  // size
16795 +       .short  2                               // version
16796 +       .int    .Ldebug_abbrev0                 // abbrev offset
16797 +       .byte   4                               // bytes per addr
16798 +
16799 +       .uleb128 1                              // abbrev 1
16800 +       .int    .Ldebug_line0                   // DW_AT_stmt_list
16801 +       .int    .Letext0                        // DW_AT_high_pc
16802 +       .int    .Ltext0                         // DW_AT_low_pc
16803 +
16804 +.Ledebug_info0:
16805 +
16806 +       .section .debug_abbrev
16807 +       .uleb128 0x01
16808 +       .uleb128 0x11           // DW_TAG_compile_unit
16809 +       .byte   0               // DW_CHILDREN_no
16810 +       .uleb128 0x10, 0x6      // DW_AT_stmt_list
16811 +       .uleb128 0x12, 0x1      // DW_AT_high_pc
16812 +       .uleb128 0x11, 0x1      // DW_AT_low_pc
16813 +       .uleb128 0, 0
16814 +
16815 +       .byte   0
16816 --- /dev/null
16817 +++ b/gas/testsuite/gas/avr32/fpinsn.d
16818 @@ -0,0 +1,271 @@
16819 +#as:
16820 +#objdump: -dr
16821 +#name: fpinsn
16822 +
16823 +.*: +file format .*
16824 +
16825 +Disassembly of section \.text:
16826 +
16827 +[0-9a-f]* <fadd_s>:
16828 + *[0-9a-f]*:   e1 a2 0f ff     cop cp0,cr15,cr15,cr15,0x4
16829 + *[0-9a-f]*:   e1 a2 00 00     cop cp0,cr0,cr0,cr0,0x4
16830 + *[0-9a-f]*:   e1 a2 00 ff     cop cp0,cr0,cr15,cr15,0x4
16831 + *[0-9a-f]*:   e1 a2 0f 0f     cop cp0,cr15,cr0,cr15,0x4
16832 + *[0-9a-f]*:   e1 a2 0f f0     cop cp0,cr15,cr15,cr0,0x4
16833 + *[0-9a-f]*:   e1 a2 07 88     cop cp0,cr7,cr8,cr8,0x4
16834 + *[0-9a-f]*:   e1 a2 08 78     cop cp0,cr8,cr7,cr8,0x4
16835 + *[0-9a-f]*:   e1 a2 08 87     cop cp0,cr8,cr8,cr7,0x4
16836 +
16837 +[0-9a-f]* <fsub_s>:
16838 + *[0-9a-f]*:   e1 a2 1f ff     cop cp0,cr15,cr15,cr15,0x5
16839 + *[0-9a-f]*:   e1 a2 10 00     cop cp0,cr0,cr0,cr0,0x5
16840 + *[0-9a-f]*:   e1 a2 10 ff     cop cp0,cr0,cr15,cr15,0x5
16841 + *[0-9a-f]*:   e1 a2 1f 0f     cop cp0,cr15,cr0,cr15,0x5
16842 + *[0-9a-f]*:   e1 a2 1f f0     cop cp0,cr15,cr15,cr0,0x5
16843 + *[0-9a-f]*:   e1 a2 17 88     cop cp0,cr7,cr8,cr8,0x5
16844 + *[0-9a-f]*:   e1 a2 18 78     cop cp0,cr8,cr7,cr8,0x5
16845 + *[0-9a-f]*:   e1 a2 18 87     cop cp0,cr8,cr8,cr7,0x5
16846 +
16847 +[0-9a-f]* <fmac_s>:
16848 + *[0-9a-f]*:   e1 a0 0f ff     cop cp0,cr15,cr15,cr15,0x0
16849 + *[0-9a-f]*:   e1 a0 00 00     cop cp0,cr0,cr0,cr0,0x0
16850 + *[0-9a-f]*:   e1 a0 00 ff     cop cp0,cr0,cr15,cr15,0x0
16851 + *[0-9a-f]*:   e1 a0 0f 0f     cop cp0,cr15,cr0,cr15,0x0
16852 + *[0-9a-f]*:   e1 a0 0f f0     cop cp0,cr15,cr15,cr0,0x0
16853 + *[0-9a-f]*:   e1 a0 07 88     cop cp0,cr7,cr8,cr8,0x0
16854 + *[0-9a-f]*:   e1 a0 08 78     cop cp0,cr8,cr7,cr8,0x0
16855 + *[0-9a-f]*:   e1 a0 08 87     cop cp0,cr8,cr8,cr7,0x0
16856 +
16857 +[0-9a-f]* <fnmac_s>:
16858 + *[0-9a-f]*:   e1 a0 1f ff     cop cp0,cr15,cr15,cr15,0x1
16859 + *[0-9a-f]*:   e1 a0 10 00     cop cp0,cr0,cr0,cr0,0x1
16860 + *[0-9a-f]*:   e1 a0 10 ff     cop cp0,cr0,cr15,cr15,0x1
16861 + *[0-9a-f]*:   e1 a0 1f 0f     cop cp0,cr15,cr0,cr15,0x1
16862 + *[0-9a-f]*:   e1 a0 1f f0     cop cp0,cr15,cr15,cr0,0x1
16863 + *[0-9a-f]*:   e1 a0 17 88     cop cp0,cr7,cr8,cr8,0x1
16864 + *[0-9a-f]*:   e1 a0 18 78     cop cp0,cr8,cr7,cr8,0x1
16865 + *[0-9a-f]*:   e1 a0 18 87     cop cp0,cr8,cr8,cr7,0x1
16866 +
16867 +[0-9a-f]* <fmsc_s>:
16868 + *[0-9a-f]*:   e1 a1 0f ff     cop cp0,cr15,cr15,cr15,0x2
16869 + *[0-9a-f]*:   e1 a1 00 00     cop cp0,cr0,cr0,cr0,0x2
16870 + *[0-9a-f]*:   e1 a1 00 ff     cop cp0,cr0,cr15,cr15,0x2
16871 + *[0-9a-f]*:   e1 a1 0f 0f     cop cp0,cr15,cr0,cr15,0x2
16872 + *[0-9a-f]*:   e1 a1 0f f0     cop cp0,cr15,cr15,cr0,0x2
16873 + *[0-9a-f]*:   e1 a1 07 88     cop cp0,cr7,cr8,cr8,0x2
16874 + *[0-9a-f]*:   e1 a1 08 78     cop cp0,cr8,cr7,cr8,0x2
16875 + *[0-9a-f]*:   e1 a1 08 87     cop cp0,cr8,cr8,cr7,0x2
16876 +
16877 +[0-9a-f]* <fnmsc_s>:
16878 + *[0-9a-f]*:   e1 a1 1f ff     cop cp0,cr15,cr15,cr15,0x3
16879 + *[0-9a-f]*:   e1 a1 10 00     cop cp0,cr0,cr0,cr0,0x3
16880 + *[0-9a-f]*:   e1 a1 10 ff     cop cp0,cr0,cr15,cr15,0x3
16881 + *[0-9a-f]*:   e1 a1 1f 0f     cop cp0,cr15,cr0,cr15,0x3
16882 + *[0-9a-f]*:   e1 a1 1f f0     cop cp0,cr15,cr15,cr0,0x3
16883 + *[0-9a-f]*:   e1 a1 17 88     cop cp0,cr7,cr8,cr8,0x3
16884 + *[0-9a-f]*:   e1 a1 18 78     cop cp0,cr8,cr7,cr8,0x3
16885 + *[0-9a-f]*:   e1 a1 18 87     cop cp0,cr8,cr8,cr7,0x3
16886 +
16887 +[0-9a-f]* <fmul_s>:
16888 + *[0-9a-f]*:   e1 a3 0f ff     cop cp0,cr15,cr15,cr15,0x6
16889 + *[0-9a-f]*:   e1 a3 00 00     cop cp0,cr0,cr0,cr0,0x6
16890 + *[0-9a-f]*:   e1 a3 00 ff     cop cp0,cr0,cr15,cr15,0x6
16891 + *[0-9a-f]*:   e1 a3 0f 0f     cop cp0,cr15,cr0,cr15,0x6
16892 + *[0-9a-f]*:   e1 a3 0f f0     cop cp0,cr15,cr15,cr0,0x6
16893 + *[0-9a-f]*:   e1 a3 07 88     cop cp0,cr7,cr8,cr8,0x6
16894 + *[0-9a-f]*:   e1 a3 08 78     cop cp0,cr8,cr7,cr8,0x6
16895 + *[0-9a-f]*:   e1 a3 08 87     cop cp0,cr8,cr8,cr7,0x6
16896 +
16897 +[0-9a-f]* <fnmul_s>:
16898 + *[0-9a-f]*:   e1 a3 1f ff     cop cp0,cr15,cr15,cr15,0x7
16899 + *[0-9a-f]*:   e1 a3 10 00     cop cp0,cr0,cr0,cr0,0x7
16900 + *[0-9a-f]*:   e1 a3 10 ff     cop cp0,cr0,cr15,cr15,0x7
16901 + *[0-9a-f]*:   e1 a3 1f 0f     cop cp0,cr15,cr0,cr15,0x7
16902 + *[0-9a-f]*:   e1 a3 1f f0     cop cp0,cr15,cr15,cr0,0x7
16903 + *[0-9a-f]*:   e1 a3 17 88     cop cp0,cr7,cr8,cr8,0x7
16904 + *[0-9a-f]*:   e1 a3 18 78     cop cp0,cr8,cr7,cr8,0x7
16905 + *[0-9a-f]*:   e1 a3 18 87     cop cp0,cr8,cr8,cr7,0x7
16906 +
16907 +[0-9a-f]* <fneg_s>:
16908 + *[0-9a-f]*:   e1 a4 0f f0     cop cp0,cr15,cr15,cr0,0x8
16909 + *[0-9a-f]*:   e1 a4 00 00     cop cp0,cr0,cr0,cr0,0x8
16910 + *[0-9a-f]*:   e1 a4 00 f0     cop cp0,cr0,cr15,cr0,0x8
16911 + *[0-9a-f]*:   e1 a4 0f 00     cop cp0,cr15,cr0,cr0,0x8
16912 + *[0-9a-f]*:   e1 a4 07 80     cop cp0,cr7,cr8,cr0,0x8
16913 + *[0-9a-f]*:   e1 a4 08 70     cop cp0,cr8,cr7,cr0,0x8
16914 +
16915 +[0-9a-f]* <fabs_s>:
16916 + *[0-9a-f]*:   e1 a4 1f f0     cop cp0,cr15,cr15,cr0,0x9
16917 + *[0-9a-f]*:   e1 a4 10 00     cop cp0,cr0,cr0,cr0,0x9
16918 + *[0-9a-f]*:   e1 a4 10 f0     cop cp0,cr0,cr15,cr0,0x9
16919 + *[0-9a-f]*:   e1 a4 1f 00     cop cp0,cr15,cr0,cr0,0x9
16920 + *[0-9a-f]*:   e1 a4 17 80     cop cp0,cr7,cr8,cr0,0x9
16921 + *[0-9a-f]*:   e1 a4 18 70     cop cp0,cr8,cr7,cr0,0x9
16922 +
16923 +[0-9a-f]* <fcmp_s>:
16924 + *[0-9a-f]*:   e1 a6 10 ff     cop cp0,cr0,cr15,cr15,0xd
16925 + *[0-9a-f]*:   e1 a6 10 00     cop cp0,cr0,cr0,cr0,0xd
16926 + *[0-9a-f]*:   e1 a6 10 0f     cop cp0,cr0,cr0,cr15,0xd
16927 + *[0-9a-f]*:   e1 a6 10 f0     cop cp0,cr0,cr15,cr0,0xd
16928 + *[0-9a-f]*:   e1 a6 10 78     cop cp0,cr0,cr7,cr8,0xd
16929 + *[0-9a-f]*:   e1 a6 10 87     cop cp0,cr0,cr8,cr7,0xd
16930 +
16931 +[0-9a-f]* <fadd_d>:
16932 + *[0-9a-f]*:   e5 a2 0e ee     cop cp0,cr14,cr14,cr14,0x44
16933 + *[0-9a-f]*:   e5 a2 00 00     cop cp0,cr0,cr0,cr0,0x44
16934 + *[0-9a-f]*:   e5 a2 00 ee     cop cp0,cr0,cr14,cr14,0x44
16935 + *[0-9a-f]*:   e5 a2 0e 0e     cop cp0,cr14,cr0,cr14,0x44
16936 + *[0-9a-f]*:   e5 a2 0e e0     cop cp0,cr14,cr14,cr0,0x44
16937 + *[0-9a-f]*:   e5 a2 06 88     cop cp0,cr6,cr8,cr8,0x44
16938 + *[0-9a-f]*:   e5 a2 08 68     cop cp0,cr8,cr6,cr8,0x44
16939 + *[0-9a-f]*:   e5 a2 08 86     cop cp0,cr8,cr8,cr6,0x44
16940 +
16941 +[0-9a-f]* <fsub_d>:
16942 + *[0-9a-f]*:   e5 a2 1e ee     cop cp0,cr14,cr14,cr14,0x45
16943 + *[0-9a-f]*:   e5 a2 10 00     cop cp0,cr0,cr0,cr0,0x45
16944 + *[0-9a-f]*:   e5 a2 10 ee     cop cp0,cr0,cr14,cr14,0x45
16945 + *[0-9a-f]*:   e5 a2 1e 0e     cop cp0,cr14,cr0,cr14,0x45
16946 + *[0-9a-f]*:   e5 a2 1e e0     cop cp0,cr14,cr14,cr0,0x45
16947 + *[0-9a-f]*:   e5 a2 16 88     cop cp0,cr6,cr8,cr8,0x45
16948 + *[0-9a-f]*:   e5 a2 18 68     cop cp0,cr8,cr6,cr8,0x45
16949 + *[0-9a-f]*:   e5 a2 18 86     cop cp0,cr8,cr8,cr6,0x45
16950 +
16951 +[0-9a-f]* <fmac_d>:
16952 + *[0-9a-f]*:   e5 a0 0e ee     cop cp0,cr14,cr14,cr14,0x40
16953 + *[0-9a-f]*:   e5 a0 00 00     cop cp0,cr0,cr0,cr0,0x40
16954 + *[0-9a-f]*:   e5 a0 00 ee     cop cp0,cr0,cr14,cr14,0x40
16955 + *[0-9a-f]*:   e5 a0 0e 0e     cop cp0,cr14,cr0,cr14,0x40
16956 + *[0-9a-f]*:   e5 a0 0e e0     cop cp0,cr14,cr14,cr0,0x40
16957 + *[0-9a-f]*:   e5 a0 06 88     cop cp0,cr6,cr8,cr8,0x40
16958 + *[0-9a-f]*:   e5 a0 08 68     cop cp0,cr8,cr6,cr8,0x40
16959 + *[0-9a-f]*:   e5 a0 08 86     cop cp0,cr8,cr8,cr6,0x40
16960 +
16961 +[0-9a-f]* <fnmac_d>:
16962 + *[0-9a-f]*:   e5 a0 1e ee     cop cp0,cr14,cr14,cr14,0x41
16963 + *[0-9a-f]*:   e5 a0 10 00     cop cp0,cr0,cr0,cr0,0x41
16964 + *[0-9a-f]*:   e5 a0 10 ee     cop cp0,cr0,cr14,cr14,0x41
16965 + *[0-9a-f]*:   e5 a0 1e 0e     cop cp0,cr14,cr0,cr14,0x41
16966 + *[0-9a-f]*:   e5 a0 1e e0     cop cp0,cr14,cr14,cr0,0x41
16967 + *[0-9a-f]*:   e5 a0 16 88     cop cp0,cr6,cr8,cr8,0x41
16968 + *[0-9a-f]*:   e5 a0 18 68     cop cp0,cr8,cr6,cr8,0x41
16969 + *[0-9a-f]*:   e5 a0 18 86     cop cp0,cr8,cr8,cr6,0x41
16970 +
16971 +[0-9a-f]* <fmsc_d>:
16972 + *[0-9a-f]*:   e5 a1 0e ee     cop cp0,cr14,cr14,cr14,0x42
16973 + *[0-9a-f]*:   e5 a1 00 00     cop cp0,cr0,cr0,cr0,0x42
16974 + *[0-9a-f]*:   e5 a1 00 ee     cop cp0,cr0,cr14,cr14,0x42
16975 + *[0-9a-f]*:   e5 a1 0e 0e     cop cp0,cr14,cr0,cr14,0x42
16976 + *[0-9a-f]*:   e5 a1 0e e0     cop cp0,cr14,cr14,cr0,0x42
16977 + *[0-9a-f]*:   e5 a1 06 88     cop cp0,cr6,cr8,cr8,0x42
16978 + *[0-9a-f]*:   e5 a1 08 68     cop cp0,cr8,cr6,cr8,0x42
16979 + *[0-9a-f]*:   e5 a1 08 86     cop cp0,cr8,cr8,cr6,0x42
16980 +
16981 +[0-9a-f]* <fnmsc_d>:
16982 + *[0-9a-f]*:   e5 a1 1e ee     cop cp0,cr14,cr14,cr14,0x43
16983 + *[0-9a-f]*:   e5 a1 10 00     cop cp0,cr0,cr0,cr0,0x43
16984 + *[0-9a-f]*:   e5 a1 10 ee     cop cp0,cr0,cr14,cr14,0x43
16985 + *[0-9a-f]*:   e5 a1 1e 0e     cop cp0,cr14,cr0,cr14,0x43
16986 + *[0-9a-f]*:   e5 a1 1e e0     cop cp0,cr14,cr14,cr0,0x43
16987 + *[0-9a-f]*:   e5 a1 16 88     cop cp0,cr6,cr8,cr8,0x43
16988 + *[0-9a-f]*:   e5 a1 18 68     cop cp0,cr8,cr6,cr8,0x43
16989 + *[0-9a-f]*:   e5 a1 18 86     cop cp0,cr8,cr8,cr6,0x43
16990 +
16991 +[0-9a-f]* <fmul_d>:
16992 + *[0-9a-f]*:   e5 a3 0e ee     cop cp0,cr14,cr14,cr14,0x46
16993 + *[0-9a-f]*:   e5 a3 00 00     cop cp0,cr0,cr0,cr0,0x46
16994 + *[0-9a-f]*:   e5 a3 00 ee     cop cp0,cr0,cr14,cr14,0x46
16995 + *[0-9a-f]*:   e5 a3 0e 0e     cop cp0,cr14,cr0,cr14,0x46
16996 + *[0-9a-f]*:   e5 a3 0e e0     cop cp0,cr14,cr14,cr0,0x46
16997 + *[0-9a-f]*:   e5 a3 06 88     cop cp0,cr6,cr8,cr8,0x46
16998 + *[0-9a-f]*:   e5 a3 08 68     cop cp0,cr8,cr6,cr8,0x46
16999 + *[0-9a-f]*:   e5 a3 08 86     cop cp0,cr8,cr8,cr6,0x46
17000 +
17001 +[0-9a-f]* <fnmul_d>:
17002 + *[0-9a-f]*:   e5 a3 1e ee     cop cp0,cr14,cr14,cr14,0x47
17003 + *[0-9a-f]*:   e5 a3 10 00     cop cp0,cr0,cr0,cr0,0x47
17004 + *[0-9a-f]*:   e5 a3 10 ee     cop cp0,cr0,cr14,cr14,0x47
17005 + *[0-9a-f]*:   e5 a3 1e 0e     cop cp0,cr14,cr0,cr14,0x47
17006 + *[0-9a-f]*:   e5 a3 1e e0     cop cp0,cr14,cr14,cr0,0x47
17007 + *[0-9a-f]*:   e5 a3 16 88     cop cp0,cr6,cr8,cr8,0x47
17008 + *[0-9a-f]*:   e5 a3 18 68     cop cp0,cr8,cr6,cr8,0x47
17009 + *[0-9a-f]*:   e5 a3 18 86     cop cp0,cr8,cr8,cr6,0x47
17010 +
17011 +[0-9a-f]* <fneg_d>:
17012 + *[0-9a-f]*:   e5 a4 0e e0     cop cp0,cr14,cr14,cr0,0x48
17013 + *[0-9a-f]*:   e5 a4 00 00     cop cp0,cr0,cr0,cr0,0x48
17014 + *[0-9a-f]*:   e5 a4 00 e0     cop cp0,cr0,cr14,cr0,0x48
17015 + *[0-9a-f]*:   e5 a4 0e 00     cop cp0,cr14,cr0,cr0,0x48
17016 + *[0-9a-f]*:   e5 a4 06 80     cop cp0,cr6,cr8,cr0,0x48
17017 + *[0-9a-f]*:   e5 a4 08 60     cop cp0,cr8,cr6,cr0,0x48
17018 +
17019 +[0-9a-f]* <fabs_d>:
17020 + *[0-9a-f]*:   e5 a4 1e e0     cop cp0,cr14,cr14,cr0,0x49
17021 + *[0-9a-f]*:   e5 a4 10 00     cop cp0,cr0,cr0,cr0,0x49
17022 + *[0-9a-f]*:   e5 a4 10 e0     cop cp0,cr0,cr14,cr0,0x49
17023 + *[0-9a-f]*:   e5 a4 1e 00     cop cp0,cr14,cr0,cr0,0x49
17024 + *[0-9a-f]*:   e5 a4 16 80     cop cp0,cr6,cr8,cr0,0x49
17025 + *[0-9a-f]*:   e5 a4 18 60     cop cp0,cr8,cr6,cr0,0x49
17026 +
17027 +[0-9a-f]* <fcmp_d>:
17028 + *[0-9a-f]*:   e5 a6 10 ee     cop cp0,cr0,cr14,cr14,0x4d
17029 + *[0-9a-f]*:   e5 a6 10 00     cop cp0,cr0,cr0,cr0,0x4d
17030 + *[0-9a-f]*:   e5 a6 10 0e     cop cp0,cr0,cr0,cr14,0x4d
17031 + *[0-9a-f]*:   e5 a6 10 e0     cop cp0,cr0,cr14,cr0,0x4d
17032 + *[0-9a-f]*:   e5 a6 10 68     cop cp0,cr0,cr6,cr8,0x4d
17033 + *[0-9a-f]*:   e5 a6 10 86     cop cp0,cr0,cr8,cr6,0x4d
17034 +
17035 +[0-9a-f]* <fmov_s>:
17036 + *[0-9a-f]*:   e1 a5 0f f0     cop cp0,cr15,cr15,cr0,0xa
17037 + *[0-9a-f]*:   e1 a5 00 00     cop cp0,cr0,cr0,cr0,0xa
17038 + *[0-9a-f]*:   e1 a5 0f 00     cop cp0,cr15,cr0,cr0,0xa
17039 + *[0-9a-f]*:   e1 a5 00 f0     cop cp0,cr0,cr15,cr0,0xa
17040 + *[0-9a-f]*:   e1 a5 08 70     cop cp0,cr8,cr7,cr0,0xa
17041 + *[0-9a-f]*:   e1 a5 07 80     cop cp0,cr7,cr8,cr0,0xa
17042 + *[0-9a-f]*:   ef af 0f 00     mvcr.w cp0,pc,cr15
17043 + *[0-9a-f]*:   ef a0 00 00     mvcr.w cp0,r0,cr0
17044 + *[0-9a-f]*:   ef af 00 00     mvcr.w cp0,pc,cr0
17045 + *[0-9a-f]*:   ef a0 0f 00     mvcr.w cp0,r0,cr15
17046 + *[0-9a-f]*:   ef a8 07 00     mvcr.w cp0,r8,cr7
17047 + *[0-9a-f]*:   ef a7 08 00     mvcr.w cp0,r7,cr8
17048 + *[0-9a-f]*:   ef af 0f 20     mvrc.w cp0,cr15,pc
17049 + *[0-9a-f]*:   ef a0 00 20     mvrc.w cp0,cr0,r0
17050 + *[0-9a-f]*:   ef a0 0f 20     mvrc.w cp0,cr15,r0
17051 + *[0-9a-f]*:   ef af 00 20     mvrc.w cp0,cr0,pc
17052 + *[0-9a-f]*:   ef a7 08 20     mvrc.w cp0,cr8,r7
17053 + *[0-9a-f]*:   ef a8 07 20     mvrc.w cp0,cr7,r8
17054 +
17055 +[0-9a-f]* <fmov_d>:
17056 + *[0-9a-f]*:   e5 a5 0e e0     cop cp0,cr14,cr14,cr0,0x4a
17057 + *[0-9a-f]*:   e5 a5 00 00     cop cp0,cr0,cr0,cr0,0x4a
17058 + *[0-9a-f]*:   e5 a5 0e 00     cop cp0,cr14,cr0,cr0,0x4a
17059 + *[0-9a-f]*:   e5 a5 00 e0     cop cp0,cr0,cr14,cr0,0x4a
17060 + *[0-9a-f]*:   e5 a5 08 60     cop cp0,cr8,cr6,cr0,0x4a
17061 + *[0-9a-f]*:   e5 a5 06 80     cop cp0,cr6,cr8,cr0,0x4a
17062 + *[0-9a-f]*:   ef ae 0e 10     mvcr.d cp0,lr,cr14
17063 + *[0-9a-f]*:   ef a0 00 10     mvcr.d cp0,r0,cr0
17064 + *[0-9a-f]*:   ef ae 00 10     mvcr.d cp0,lr,cr0
17065 + *[0-9a-f]*:   ef a0 0e 10     mvcr.d cp0,r0,cr14
17066 + *[0-9a-f]*:   ef a8 06 10     mvcr.d cp0,r8,cr6
17067 + *[0-9a-f]*:   ef a6 08 10     mvcr.d cp0,r6,cr8
17068 + *[0-9a-f]*:   ef ae 0e 30     mvrc.d cp0,cr14,lr
17069 + *[0-9a-f]*:   ef a0 00 30     mvrc.d cp0,cr0,r0
17070 + *[0-9a-f]*:   ef a0 0e 30     mvrc.d cp0,cr14,r0
17071 + *[0-9a-f]*:   ef ae 00 30     mvrc.d cp0,cr0,lr
17072 + *[0-9a-f]*:   ef a6 08 30     mvrc.d cp0,cr8,r6
17073 + *[0-9a-f]*:   ef a8 06 30     mvrc.d cp0,cr6,r8
17074 +
17075 +[0-9a-f]* <fcasts_d>:
17076 + *[0-9a-f]*:   e1 a7 1f e0     cop cp0,cr15,cr14,cr0,0xf
17077 + *[0-9a-f]*:   e1 a7 10 00     cop cp0,cr0,cr0,cr0,0xf
17078 + *[0-9a-f]*:   e1 a7 1f 00     cop cp0,cr15,cr0,cr0,0xf
17079 + *[0-9a-f]*:   e1 a7 10 e0     cop cp0,cr0,cr14,cr0,0xf
17080 + *[0-9a-f]*:   e1 a7 18 60     cop cp0,cr8,cr6,cr0,0xf
17081 + *[0-9a-f]*:   e1 a7 17 80     cop cp0,cr7,cr8,cr0,0xf
17082 +
17083 +[0-9a-f]* <fcastd_s>:
17084 + *[0-9a-f]*:   e1 a8 0e f0     cop cp0,cr14,cr15,cr0,0x10
17085 + *[0-9a-f]*:   e1 a8 00 00     cop cp0,cr0,cr0,cr0,0x10
17086 + *[0-9a-f]*:   e1 a8 0e 00     cop cp0,cr14,cr0,cr0,0x10
17087 + *[0-9a-f]*:   e1 a8 00 f0     cop cp0,cr0,cr15,cr0,0x10
17088 + *[0-9a-f]*:   e1 a8 08 70     cop cp0,cr8,cr7,cr0,0x10
17089 + *[0-9a-f]*:   e1 a8 06 80     cop cp0,cr6,cr8,cr0,0x10
17090 --- /dev/null
17091 +++ b/gas/testsuite/gas/avr32/fpinsn.s
17092 @@ -0,0 +1,266 @@
17093 +
17094 +       .text
17095 +       .global fadd_s
17096 +fadd_s:
17097 +       fadd.s fr15, fr15, fr15
17098 +       fadd.s fr0, fr0, fr0
17099 +       fadd.s fr0, fr15, fr15
17100 +       fadd.s fr15, fr0, fr15
17101 +       fadd.s fr15, fr15, fr0
17102 +       fadd.s fr7, fr8, fr8
17103 +       fadd.s fr8, fr7, fr8
17104 +       fadd.s fr8, fr8, fr7
17105 +       .global fsub_s
17106 +fsub_s:
17107 +       fsub.s fr15, fr15, fr15
17108 +       fsub.s fr0, fr0, fr0
17109 +       fsub.s fr0, fr15, fr15
17110 +       fsub.s fr15, fr0, fr15
17111 +       fsub.s fr15, fr15, fr0
17112 +       fsub.s fr7, fr8, fr8
17113 +       fsub.s fr8, fr7, fr8
17114 +       fsub.s fr8, fr8, fr7
17115 +       .global fmac_s
17116 +fmac_s:
17117 +       fmac.s fr15, fr15, fr15
17118 +       fmac.s fr0, fr0, fr0
17119 +       fmac.s fr0, fr15, fr15
17120 +       fmac.s fr15, fr0, fr15
17121 +       fmac.s fr15, fr15, fr0
17122 +       fmac.s fr7, fr8, fr8
17123 +       fmac.s fr8, fr7, fr8
17124 +       fmac.s fr8, fr8, fr7
17125 +       .global fnmac_s
17126 +fnmac_s:
17127 +       fnmac.s fr15, fr15, fr15
17128 +       fnmac.s fr0, fr0, fr0
17129 +       fnmac.s fr0, fr15, fr15
17130 +       fnmac.s fr15, fr0, fr15
17131 +       fnmac.s fr15, fr15, fr0
17132 +       fnmac.s fr7, fr8, fr8
17133 +       fnmac.s fr8, fr7, fr8
17134 +       fnmac.s fr8, fr8, fr7
17135 +       .global fmsc_s
17136 +fmsc_s:
17137 +       fmsc.s fr15, fr15, fr15
17138 +       fmsc.s fr0, fr0, fr0
17139 +       fmsc.s fr0, fr15, fr15
17140 +       fmsc.s fr15, fr0, fr15
17141 +       fmsc.s fr15, fr15, fr0
17142 +       fmsc.s fr7, fr8, fr8
17143 +       fmsc.s fr8, fr7, fr8
17144 +       fmsc.s fr8, fr8, fr7
17145 +       .global fnmsc_s
17146 +fnmsc_s:
17147 +       fnmsc.s fr15, fr15, fr15
17148 +       fnmsc.s fr0, fr0, fr0
17149 +       fnmsc.s fr0, fr15, fr15
17150 +       fnmsc.s fr15, fr0, fr15
17151 +       fnmsc.s fr15, fr15, fr0
17152 +       fnmsc.s fr7, fr8, fr8
17153 +       fnmsc.s fr8, fr7, fr8
17154 +       fnmsc.s fr8, fr8, fr7
17155 +       .global fmul_s
17156 +fmul_s:
17157 +       fmul.s fr15, fr15, fr15
17158 +       fmul.s fr0, fr0, fr0
17159 +       fmul.s fr0, fr15, fr15
17160 +       fmul.s fr15, fr0, fr15
17161 +       fmul.s fr15, fr15, fr0
17162 +       fmul.s fr7, fr8, fr8
17163 +       fmul.s fr8, fr7, fr8
17164 +       fmul.s fr8, fr8, fr7
17165 +       .global fnmul_s
17166 +fnmul_s:
17167 +       fnmul.s fr15, fr15, fr15
17168 +       fnmul.s fr0, fr0, fr0
17169 +       fnmul.s fr0, fr15, fr15
17170 +       fnmul.s fr15, fr0, fr15
17171 +       fnmul.s fr15, fr15, fr0
17172 +       fnmul.s fr7, fr8, fr8
17173 +       fnmul.s fr8, fr7, fr8
17174 +       fnmul.s fr8, fr8, fr7
17175 +       .global fneg_s
17176 +fneg_s:
17177 +       fneg.s fr15, fr15
17178 +       fneg.s fr0, fr0
17179 +       fneg.s fr0, fr15
17180 +       fneg.s fr15, fr0
17181 +       fneg.s fr7, fr8
17182 +       fneg.s fr8, fr7
17183 +       .global fabs_s
17184 +fabs_s:
17185 +       fabs.s fr15, fr15
17186 +       fabs.s fr0, fr0
17187 +       fabs.s fr0, fr15
17188 +       fabs.s fr15, fr0
17189 +       fabs.s fr7, fr8
17190 +       fabs.s fr8, fr7
17191 +       .global fcmp_s
17192 +fcmp_s:
17193 +       fcmp.s fr15, fr15
17194 +       fcmp.s fr0, fr0
17195 +       fcmp.s fr0, fr15
17196 +       fcmp.s fr15, fr0
17197 +       fcmp.s fr7, fr8
17198 +       fcmp.s fr8, fr7
17199 +       .global fadd_d
17200 +fadd_d:
17201 +       fadd.d fr14, fr14, fr14
17202 +       fadd.d fr0, fr0, fr0
17203 +       fadd.d fr0, fr14, fr14
17204 +       fadd.d fr14, fr0, fr14
17205 +       fadd.d fr14, fr14, fr0
17206 +       fadd.d fr6, fr8, fr8
17207 +       fadd.d fr8, fr6, fr8
17208 +       fadd.d fr8, fr8, fr6
17209 +       .global fsub_d
17210 +fsub_d:
17211 +       fsub.d fr14, fr14, fr14
17212 +       fsub.d fr0, fr0, fr0
17213 +       fsub.d fr0, fr14, fr14
17214 +       fsub.d fr14, fr0, fr14
17215 +       fsub.d fr14, fr14, fr0
17216 +       fsub.d fr6, fr8, fr8
17217 +       fsub.d fr8, fr6, fr8
17218 +       fsub.d fr8, fr8, fr6
17219 +       .global fmac_d
17220 +fmac_d:
17221 +       fmac.d fr14, fr14, fr14
17222 +       fmac.d fr0, fr0, fr0
17223 +       fmac.d fr0, fr14, fr14
17224 +       fmac.d fr14, fr0, fr14
17225 +       fmac.d fr14, fr14, fr0
17226 +       fmac.d fr6, fr8, fr8
17227 +       fmac.d fr8, fr6, fr8
17228 +       fmac.d fr8, fr8, fr6
17229 +       .global fnmac_d
17230 +fnmac_d:
17231 +       fnmac.d fr14, fr14, fr14
17232 +       fnmac.d fr0, fr0, fr0
17233 +       fnmac.d fr0, fr14, fr14
17234 +       fnmac.d fr14, fr0, fr14
17235 +       fnmac.d fr14, fr14, fr0
17236 +       fnmac.d fr6, fr8, fr8
17237 +       fnmac.d fr8, fr6, fr8
17238 +       fnmac.d fr8, fr8, fr6
17239 +       .global fmsc_d
17240 +fmsc_d:
17241 +       fmsc.d fr14, fr14, fr14
17242 +       fmsc.d fr0, fr0, fr0
17243 +       fmsc.d fr0, fr14, fr14
17244 +       fmsc.d fr14, fr0, fr14
17245 +       fmsc.d fr14, fr14, fr0
17246 +       fmsc.d fr6, fr8, fr8
17247 +       fmsc.d fr8, fr6, fr8
17248 +       fmsc.d fr8, fr8, fr6
17249 +       .global fnmsc_d
17250 +fnmsc_d:
17251 +       fnmsc.d fr14, fr14, fr14
17252 +       fnmsc.d fr0, fr0, fr0
17253 +       fnmsc.d fr0, fr14, fr14
17254 +       fnmsc.d fr14, fr0, fr14
17255 +       fnmsc.d fr14, fr14, fr0
17256 +       fnmsc.d fr6, fr8, fr8
17257 +       fnmsc.d fr8, fr6, fr8
17258 +       fnmsc.d fr8, fr8, fr6
17259 +       .global fmul_d
17260 +fmul_d:
17261 +       fmul.d fr14, fr14, fr14
17262 +       fmul.d fr0, fr0, fr0
17263 +       fmul.d fr0, fr14, fr14
17264 +       fmul.d fr14, fr0, fr14
17265 +       fmul.d fr14, fr14, fr0
17266 +       fmul.d fr6, fr8, fr8
17267 +       fmul.d fr8, fr6, fr8
17268 +       fmul.d fr8, fr8, fr6
17269 +       .global fnmul_d
17270 +fnmul_d:
17271 +       fnmul.d fr14, fr14, fr14
17272 +       fnmul.d fr0, fr0, fr0
17273 +       fnmul.d fr0, fr14, fr14
17274 +       fnmul.d fr14, fr0, fr14
17275 +       fnmul.d fr14, fr14, fr0
17276 +       fnmul.d fr6, fr8, fr8
17277 +       fnmul.d fr8, fr6, fr8
17278 +       fnmul.d fr8, fr8, fr6
17279 +       .global fneg_d
17280 +fneg_d:
17281 +       fneg.d fr14, fr14
17282 +       fneg.d fr0, fr0
17283 +       fneg.d fr0, fr14
17284 +       fneg.d fr14, fr0
17285 +       fneg.d fr6, fr8
17286 +       fneg.d fr8, fr6
17287 +       .global fabs_d
17288 +fabs_d:
17289 +       fabs.d fr14, fr14
17290 +       fabs.d fr0, fr0
17291 +       fabs.d fr0, fr14
17292 +       fabs.d fr14, fr0
17293 +       fabs.d fr6, fr8
17294 +       fabs.d fr8, fr6
17295 +       .global fcmp_d
17296 +fcmp_d:
17297 +       fcmp.d fr14, fr14
17298 +       fcmp.d fr0, fr0
17299 +       fcmp.d fr0, fr14
17300 +       fcmp.d fr14, fr0
17301 +       fcmp.d fr6, fr8
17302 +       fcmp.d fr8, fr6
17303 +       .global fmov_s
17304 +fmov_s:
17305 +       fmov.s fr15, fr15
17306 +       fmov.s fr0, fr0
17307 +       fmov.s fr15, fr0
17308 +       fmov.s fr0, fr15
17309 +       fmov.s fr8, fr7
17310 +       fmov.s fr7, fr8
17311 +       fmov.s pc, fr15
17312 +       fmov.s r0, fr0
17313 +       fmov.s pc, fr0
17314 +       fmov.s r0, fr15
17315 +       fmov.s r8, fr7
17316 +       fmov.s r7, fr8
17317 +       fmov.s fr15, pc
17318 +       fmov.s fr0, r0
17319 +       fmov.s fr15, r0
17320 +       fmov.s fr0, pc
17321 +       fmov.s fr8, r7
17322 +       fmov.s fr7, r8
17323 +       .global fmov_d
17324 +fmov_d:
17325 +       fmov.d fr14, fr14
17326 +       fmov.d fr0, fr0
17327 +       fmov.d fr14, fr0
17328 +       fmov.d fr0, fr14
17329 +       fmov.d fr8, fr6
17330 +       fmov.d fr6, fr8
17331 +       fmov.d lr, fr14
17332 +       fmov.d r0, fr0
17333 +       fmov.d lr, fr0
17334 +       fmov.d r0, fr14
17335 +       fmov.d r8, fr6
17336 +       fmov.d r6, fr8
17337 +       fmov.d fr14, lr
17338 +       fmov.d fr0, r0
17339 +       fmov.d fr14, r0
17340 +       fmov.d fr0, lr
17341 +       fmov.d fr8, r6
17342 +       fmov.d fr6, r8
17343 +       .global fcasts_d
17344 +fcasts_d:
17345 +       fcasts.d fr15, fr14
17346 +       fcasts.d fr0, fr0
17347 +       fcasts.d fr15, fr0
17348 +       fcasts.d fr0, fr14
17349 +       fcasts.d fr8, fr6
17350 +       fcasts.d fr7, fr8
17351 +       .global fcastd_s
17352 +fcastd_s:
17353 +       fcastd.s fr14, fr15
17354 +       fcastd.s fr0, fr0
17355 +       fcastd.s fr14, fr0
17356 +       fcastd.s fr0, fr15
17357 +       fcastd.s fr8, fr7
17358 +       fcastd.s fr6, fr8
17359 --- /dev/null
17360 +++ b/gas/testsuite/gas/avr32/hwrd-lwrd.d
17361 @@ -0,0 +1,47 @@
17362 +#as:
17363 +#objdump: -dr
17364 +#name: hwrd-lwrd
17365 +
17366 +.*: +file format .*
17367 +
17368 +Disassembly of section \.text:
17369 +
17370 +00000000 <test_hwrd>:
17371 +   0:  e0 60 87 65     mov r0,34661
17372 +   4:  e0 60 12 34     mov r0,4660
17373 +   8:  e0 60 00 00     mov r0,0
17374 +                       8: R_AVR32_HI16 \.text\+0x60
17375 +   c:  e0 60 00 00     mov r0,0
17376 +                       c: R_AVR32_HI16 extsym1
17377 +  10:  ea 10 87 65     orh r0,0x8765
17378 +  14:  ea 10 12 34     orh r0,0x1234
17379 +  18:  ea 10 00 00     orh r0,0x0
17380 +                       18: R_AVR32_HI16        \.text\+0x60
17381 +  1c:  ea 10 00 00     orh r0,0x0
17382 +                       1c: R_AVR32_HI16        extsym1
17383 +  20:  e4 10 87 65     andh r0,0x8765
17384 +  24:  e4 10 12 34     andh r0,0x1234
17385 +  28:  e4 10 00 00     andh r0,0x0
17386 +                       28: R_AVR32_HI16        \.text\+0x60
17387 +  2c:  e4 10 00 00     andh r0,0x0
17388 +                       2c: R_AVR32_HI16        extsym1
17389 +
17390 +00000030 <test_lwrd>:
17391 +  30:  e0 60 43 21     mov r0,17185
17392 +  34:  e0 60 56 78     mov r0,22136
17393 +  38:  e0 60 00 00     mov r0,0
17394 +                       38: R_AVR32_LO16        \.text\+0x60
17395 +  3c:  e0 60 00 00     mov r0,0
17396 +                       3c: R_AVR32_LO16        extsym1
17397 +  40:  e8 10 43 21     orl r0,0x4321
17398 +  44:  e8 10 56 78     orl r0,0x5678
17399 +  48:  e8 10 00 00     orl r0,0x0
17400 +                       48: R_AVR32_LO16        \.text\+0x60
17401 +  4c:  e8 10 00 00     orl r0,0x0
17402 +                       4c: R_AVR32_LO16        extsym1
17403 +  50:  e0 10 43 21     andl r0,0x4321
17404 +  54:  e0 10 56 78     andl r0,0x5678
17405 +  58:  e0 10 00 00     andl r0,0x0
17406 +                       58: R_AVR32_LO16        \.text\+0x60
17407 +  5c:  e0 10 00 00     andl r0,0x0
17408 +                       5c: R_AVR32_LO16        extsym1
17409 --- /dev/null
17410 +++ b/gas/testsuite/gas/avr32/hwrd-lwrd.s
17411 @@ -0,0 +1,39 @@
17412 +
17413 +        .equ    sym1, 0x12345678
17414 +
17415 +        .text
17416 +        .global test_hwrd
17417 +test_hwrd:
17418 +        mov     r0, hi(0x87654321)
17419 +        mov     r0, hi(sym1)
17420 +        mov     r0, hi(sym2)
17421 +        mov     r0, hi(extsym1)
17422 +
17423 +        orh    r0, hi(0x87654321)
17424 +        orh    r0, hi(sym1)
17425 +        orh    r0, hi(sym2)
17426 +        orh    r0, hi(extsym1)
17427 +
17428 +        andh   r0, hi(0x87654321)
17429 +        andh   r0, hi(sym1)
17430 +        andh   r0, hi(sym2)
17431 +        andh   r0, hi(extsym1)
17432 +
17433 +        .global test_lwrd
17434 +test_lwrd:
17435 +        mov     r0, lo(0x87654321)
17436 +        mov     r0, lo(sym1)
17437 +        mov     r0, lo(sym2)
17438 +        mov     r0, lo(extsym1)
17439 +
17440 +        orl    r0, lo(0x87654321)
17441 +        orl    r0, lo(sym1)
17442 +        orl    r0, lo(sym2)
17443 +        orl    r0, lo(extsym1)
17444 +
17445 +        andl   r0, lo(0x87654321)
17446 +        andl   r0, lo(sym1)
17447 +        andl   r0, lo(sym2)
17448 +        andl   r0, lo(extsym1)
17449 +
17450 +sym2:
17451 --- /dev/null
17452 +++ b/gas/testsuite/gas/avr32/jmptable.d
17453 @@ -0,0 +1,20 @@
17454 +#source: jmptable.s
17455 +#as:
17456 +#objdump: -dr
17457 +#name: jmptable
17458 +
17459 +.*: +file format .*
17460 +
17461 +Disassembly of section \.text:
17462 +
17463 +00000000 <jmptable_test>:
17464 +   0:  fe c8 ff f4     sub r8,pc,-12
17465 +   4:  f0 00 00 2f     add pc,r8,r0<<0x2
17466 +   8:  d7 03           nop
17467 +   a:  00 00           add r0,r0
17468 +   c:  c0 38           rjmp 12 <jmptable_test\+0x12>
17469 +   e:  c0 38           rjmp 14 <jmptable_test\+0x14>
17470 +  10:  c0 38           rjmp 16 <jmptable_test\+0x16>
17471 +  12:  d7 03           nop
17472 +  14:  d7 03           nop
17473 +  16:  d7 03           nop
17474 --- /dev/null
17475 +++ b/gas/testsuite/gas/avr32/jmptable_linkrelax.d
17476 @@ -0,0 +1,25 @@
17477 +#source: jmptable.s
17478 +#as: --linkrelax
17479 +#objdump: -dr
17480 +#name: jmptable_linkrelax
17481 +
17482 +.*: +file format .*
17483 +
17484 +Disassembly of section \.text:
17485 +
17486 +00000000 <jmptable_test>:
17487 +   0:  fe c8 00 00     sub r8,pc,0
17488 +                       0: R_AVR32_16N_PCREL    \.text\+0xc
17489 +   4:  f0 00 00 2f     add pc,r8,r0<<0x2
17490 +   8:  d7 03           nop
17491 +   a:  00 00           add r0,r0
17492 +                       a: R_AVR32_ALIGN        \*ABS\*\+0x2
17493 +   c:  c0 08           rjmp c <jmptable_test\+0xc>
17494 +                       c: R_AVR32_11H_PCREL    \.text\+0x12
17495 +   e:  c0 08           rjmp e <jmptable_test\+0xe>
17496 +                       e: R_AVR32_11H_PCREL    \.text\+0x14
17497 +  10:  c0 08           rjmp 10 <jmptable_test\+0x10>
17498 +                       10: R_AVR32_11H_PCREL   \.text\+0x16
17499 +  12:  d7 03           nop
17500 +  14:  d7 03           nop
17501 +  16:  d7 03           nop
17502 --- /dev/null
17503 +++ b/gas/testsuite/gas/avr32/jmptable.s
17504 @@ -0,0 +1,14 @@
17505 +
17506 +       .text
17507 +       .global jmptable_test
17508 +jmptable_test:
17509 +       sub     r8, pc, -(.L1 - .)
17510 +       add     pc, r8, r0 << 2
17511 +       nop
17512 +       .align  2
17513 +.L1:   rjmp    1f
17514 +       rjmp    2f
17515 +       rjmp    3f
17516 +1:     nop
17517 +2:     nop
17518 +3:     nop
17519 --- /dev/null
17520 +++ b/gas/testsuite/gas/avr32/lda_nopic.d
17521 @@ -0,0 +1,32 @@
17522 +#source: lda.s
17523 +#as:
17524 +#objdump: -dr
17525 +#name: lda_nopic
17526 +
17527 +.*: +file format .*
17528 +
17529 +Disassembly of section \.text:
17530 +
17531 +00000000 <lda_test>:
17532 +       0:      f2 c8 00 00     sub r8,r9,0
17533 +
17534 +00000004 <far_negative>:
17535 +       4:      f6 ca 00 00     sub r10,r11,0
17536 +       ...
17537 +    8000:      fe c0 7f fc     sub r0,pc,32764
17538 +    8004:      48 31           lddpc r1,8010 <far_negative\+0x800c>
17539 +    8006:      48 42           lddpc r2,8014 <far_negative\+0x8010>
17540 +    8008:      48 43           lddpc r3,8018 <far_negative\+0x8014>
17541 +    800a:      48 54           lddpc r4,801c <far_negative\+0x8018>
17542 +    800c:      fe c5 80 04     sub r5,pc,-32764
17543 +       ...
17544 +                       8010: R_AVR32_32_CPENT  \.text
17545 +                       8014: R_AVR32_32_CPENT  \.data
17546 +                       8018: R_AVR32_32_CPENT  undefined
17547 +                       801c: R_AVR32_32_CPENT  \.text\+0x1001c
17548 +
17549 +00010008 <far_positive>:
17550 +   10008:      fa cc 00 00     sub r12,sp,0
17551 +       ...
17552 +0001001c <toofar_positive>:
17553 +   1001c:      fe ce 00 00     sub lr,pc,0
17554 --- /dev/null
17555 +++ b/gas/testsuite/gas/avr32/lda_nopic_linkrelax.d
17556 @@ -0,0 +1,41 @@
17557 +#source: lda.s
17558 +#as: --linkrelax
17559 +#objdump: -dr
17560 +#name: lda_nopic_linkrelax
17561 +
17562 +.*: +file format .*
17563 +
17564 +Disassembly of section \.text:
17565 +
17566 +00000000 <lda_test>:
17567 +       0:      f2 c8 00 00     sub r8,r9,0
17568 +
17569 +00000004 <far_negative>:
17570 +       4:      f6 ca 00 00     sub r10,r11,0
17571 +       \.\.\.
17572 +    8000:      48 00           lddpc r0,8000 <far_negative\+0x7ffc>
17573 +                       8000: R_AVR32_9W_CP     \.text\+0x800c
17574 +    8002:      48 01           lddpc r1,8000 <far_negative\+0x7ffc>
17575 +                       8002: R_AVR32_9W_CP     \.text\+0x8010
17576 +    8004:      48 02           lddpc r2,8004 <far_negative\+0x8000>
17577 +                       8004: R_AVR32_9W_CP     \.text\+0x8014
17578 +    8006:      48 03           lddpc r3,8004 <far_negative\+0x8000>
17579 +                       8006: R_AVR32_9W_CP     \.text\+0x8018
17580 +    8008:      48 04           lddpc r4,8008 <far_negative\+0x8004>
17581 +                       8008: R_AVR32_9W_CP     \.text\+0x801c
17582 +    800a:      48 05           lddpc r5,8008 <far_negative\+0x8004>
17583 +                       800a: R_AVR32_9W_CP     \.text\+0x8020
17584 +       \.\.\.
17585 +                       800c: R_AVR32_ALIGN     \*ABS\*\+0x2
17586 +                       800c: R_AVR32_32_CPENT  \.text\+0x4
17587 +                       8010: R_AVR32_32_CPENT  \.text
17588 +                       8014: R_AVR32_32_CPENT  \.data
17589 +                       8018: R_AVR32_32_CPENT  undefined
17590 +                       801c: R_AVR32_32_CPENT  \.text\+0x10020
17591 +                       8020: R_AVR32_32_CPENT  \.text\+0x1000c
17592 +
17593 +0001000c <far_positive>:
17594 +   1000c:      fa cc 00 00     sub r12,sp,0
17595 +       \.\.\.
17596 +00010020 <toofar_positive>:
17597 +   10020:      fe ce 00 00     sub lr,pc,0
17598 --- /dev/null
17599 +++ b/gas/testsuite/gas/avr32/lda_pic.d
17600 @@ -0,0 +1,32 @@
17601 +#source: lda.s
17602 +#as: --pic
17603 +#objdump: -dr
17604 +#name: lda_pic
17605 +
17606 +.*: +file format .*
17607 +
17608 +Disassembly of section \.text:
17609 +
17610 +00000000 <lda_test>:
17611 +       0:      f2 c8 00 00     sub r8,r9,0
17612 +
17613 +00000004 <far_negative>:
17614 +       4:      f6 ca 00 00     sub r10,r11,0
17615 +       ...
17616 +    8000:      fe c0 7f fc     sub r0,pc,32764
17617 +    8004:      ec f1 00 00     ld.w r1,r6\[0\]
17618 +                       8004: R_AVR32_GOT16S    toofar_negative
17619 +    8008:      ec f2 00 00     ld.w r2,r6\[0\]
17620 +                       8008: R_AVR32_GOT16S    different_section
17621 +    800c:      ec f3 00 00     ld.w r3,r6\[0\]
17622 +                       800c: R_AVR32_GOT16S    undefined
17623 +    8010:      ec f4 00 00     ld.w r4,r6\[0\]
17624 +                       8010: R_AVR32_GOT16S    toofar_positive
17625 +    8014:      fe c5 80 14     sub r5,pc,-32748
17626 +       ...
17627 +
17628 +00010000 <far_positive>:
17629 +   10000:      fa cc 00 00     sub r12,sp,0
17630 +       ...
17631 +00010014 <toofar_positive>:
17632 +   10014:      fe ce 00 00     sub lr,pc,0
17633 --- /dev/null
17634 +++ b/gas/testsuite/gas/avr32/lda_pic_linkrelax.d
17635 @@ -0,0 +1,40 @@
17636 +#source: lda.s
17637 +#as: --pic --linkrelax
17638 +#objdump: -dr
17639 +#name: lda_pic_linkrelax
17640 +
17641 +.*: +file format .*
17642 +
17643 +Disassembly of section \.text:
17644 +
17645 +00000000 <lda_test>:
17646 +       0:      f2 c8 00 00     sub r8,r9,0
17647 +
17648 +00000004 <far_negative>:
17649 +       4:      f6 ca 00 00     sub r10,r11,0
17650 +       ...
17651 +    8000:      e0 60 00 00     mov r0,0
17652 +                       8000: R_AVR32_LDA_GOT   far_negative
17653 +    8004:      ec 00 03 20     ld\.w r0,r6\[r0<<0x2\]
17654 +    8008:      e0 61 00 00     mov r1,0
17655 +                       8008: R_AVR32_LDA_GOT   toofar_negative
17656 +    800c:      ec 01 03 21     ld\.w r1,r6\[r1<<0x2\]
17657 +    8010:      e0 62 00 00     mov r2,0
17658 +                       8010: R_AVR32_LDA_GOT   different_section
17659 +    8014:      ec 02 03 22     ld\.w r2,r6\[r2<<0x2\]
17660 +    8018:      e0 63 00 00     mov r3,0
17661 +                       8018: R_AVR32_LDA_GOT   undefined
17662 +    801c:      ec 03 03 23     ld\.w r3,r6\[r3<<0x2\]
17663 +    8020:      e0 64 00 00     mov r4,0
17664 +                       8020: R_AVR32_LDA_GOT   toofar_positive
17665 +    8024:      ec 04 03 24     ld\.w r4,r6\[r4<<0x2\]
17666 +    8028:      e0 65 00 00     mov r5,0
17667 +                       8028: R_AVR32_LDA_GOT   far_positive
17668 +    802c:      ec 05 03 25     ld\.w r5,r6\[r5<<0x2\]
17669 +       ...
17670 +
17671 +00010018 <far_positive>:
17672 +   10018:      fa cc 00 00     sub r12,sp,0
17673 +       ...
17674 +0001002c <toofar_positive>:
17675 +   1002c:      fe ce 00 00     sub lr,pc,0
17676 --- /dev/null
17677 +++ b/gas/testsuite/gas/avr32/lda.s
17678 @@ -0,0 +1,30 @@
17679 +
17680 +       .text
17681 +       .global lda_test
17682 +lda_test:
17683 +toofar_negative:
17684 +       sub     r8, r9, 0
17685 +far_negative:
17686 +       sub     r10, r11, 0
17687 +
17688 +       .fill   32760, 1, 0x00
17689 +
17690 +       lda.w   r0, far_negative
17691 +       lda.w   r1, toofar_negative
17692 +       lda.w   r2, different_section
17693 +       lda.w   r3, undefined
17694 +       lda.w   r4, toofar_positive
17695 +       lda.w   r5, far_positive
17696 +
17697 +       .cpool
17698 +
17699 +       .fill   32744, 1, 0x00
17700 +far_positive:
17701 +       sub     r12, sp, 0
17702 +       .fill   16, 1, 0x00
17703 +toofar_positive:
17704 +       sub     lr, pc, 0
17705 +
17706 +       .data
17707 +different_section:
17708 +       .long   0x12345678
17709 --- /dev/null
17710 +++ b/gas/testsuite/gas/avr32/pcrel.d
17711 @@ -0,0 +1,64 @@
17712 +#as:
17713 +#objdump: -dr
17714 +#name: pcrel
17715 +
17716 +.*: +file format .*
17717 +
17718 +Disassembly of section \.text:
17719 +
17720 +00000000 <test_rjmp>:
17721 +   0:  d7 03           nop
17722 +   2:  c0 28           rjmp 6 <test_rjmp\+0x6>
17723 +   4:  d7 03           nop
17724 +   6:  e0 8f 00 00     bral 6 <test_rjmp\+0x6>
17725 +                       6: R_AVR32_22H_PCREL    extsym10
17726 +
17727 +0000000a <test_rcall>:
17728 +   a:  d7 03           nop
17729 +0000000c <test_rcall2>:
17730 +   c:  c0 2c           rcall 10 <test_rcall2\+0x4>
17731 +   e:  d7 03           nop
17732 +  10:  e0 a0 00 00     rcall 10 <test_rcall2\+0x4>
17733 +                       10: R_AVR32_22H_PCREL   extsym21
17734 +
17735 +00000014 <test_branch>:
17736 +  14:  c0 31           brne 1a <test_branch\+0x6>
17737 +  16:  e0 8f 00 00     bral 16 <test_branch\+0x2>
17738 +                       16: R_AVR32_22H_PCREL   test_branch
17739 +  1a:  e0 80 00 00     breq 1a <test_branch\+0x6>
17740 +                       1a: R_AVR32_22H_PCREL   extsym21
17741 +
17742 +0000001e <test_lddpc>:
17743 +  1e:  48 30           lddpc r0,28 <sym1>
17744 +  20:  48 20           lddpc r0,28 <sym1>
17745 +  22:  fe f0 00 00     ld.w r0,pc\[0\]
17746 +                       22: R_AVR32_16B_PCREL   extsym16
17747 +       \.\.\.
17748 +
17749 +00000028 <sym1>:
17750 +  28:  d7 03           nop
17751 +  2a:  d7 03           nop
17752 +
17753 +0000002c <test_local>:
17754 +  2c:  48 20           lddpc r0,34 <test_local\+0x8>
17755 +  2e:  48 30           lddpc r0,38 <test_local\+0xc>
17756 +  30:  48 20           lddpc r0,38 <test_local\+0xc>
17757 +  32:  00 00           add r0,r0
17758 +  34:  d7 03           nop
17759 +  36:  d7 03           nop
17760 +  38:  d7 03           nop
17761 +  3a:  d7 03           nop
17762 +
17763 +Disassembly of section \.text\.init:
17764 +
17765 +00000000 <test_inter_section>:
17766 +   0:  e0 a0 .. ..     rcall [0-9a-f]+ <.*>
17767 +                       0: R_AVR32_22H_PCREL    test_rcall
17768 +   4:  d7 03           nop
17769 +   6:  e0 a0 .. ..     rcall [0-9a-f]+ <.*>
17770 +                       6: R_AVR32_22H_PCREL    test_rcall
17771 +   a:  e0 a0 .. ..     rcall [0-9a-z]+ <.*>
17772 +                       a: R_AVR32_22H_PCREL    \.text\+0xc
17773 +   e:  d7 03           nop
17774 +  10:  e0 a0 .. ..     rcall [0-9a-f]+ <.*>
17775 +                       10: R_AVR32_22H_PCREL   \.text\+0xc
17776 --- /dev/null
17777 +++ b/gas/testsuite/gas/avr32/pcrel.s
17778 @@ -0,0 +1,57 @@
17779 +
17780 +        .text
17781 +        .global test_rjmp
17782 +test_rjmp:
17783 +        nop
17784 +        rjmp    0f
17785 +        nop
17786 +0:      rjmp    extsym10
17787 +
17788 +        .global test_rcall
17789 +test_rcall:
17790 +        nop
17791 +test_rcall2:
17792 +        rcall   0f
17793 +        nop
17794 +0:      rcall   extsym21
17795 +
17796 +        .global test_branch
17797 +test_branch:
17798 +        brne    0f
17799 +       /* This will generate a reloc since test_branch is global */
17800 +        bral    test_branch
17801 +0:     breq    extsym21
17802 +
17803 +        .global test_lddpc
17804 +test_lddpc:
17805 +        lddpc   r0,sym1
17806 +        lddpc   r0,sym1
17807 +        lddpc   r0,extsym16
17808 +
17809 +        .align 2
17810 +sym1:   nop
17811 +        nop
17812 +
17813 +       .global test_local
17814 +test_local:
17815 +       lddpc   r0, .LC1
17816 +       lddpc   r0, .LC2
17817 +       lddpc   r0, .LC1 + 0x4
17818 +
17819 +       .align  2
17820 +.LC1:
17821 +       nop
17822 +       nop
17823 +.LC2:
17824 +       nop
17825 +       nop
17826 +
17827 +       .section .text.init,"ax"
17828 +       .global test_inter_section
17829 +test_inter_section:
17830 +       rcall   test_rcall
17831 +       nop
17832 +       rcall   test_rcall
17833 +       rcall   test_rcall2
17834 +       nop
17835 +       rcall   test_rcall2
17836 --- /dev/null
17837 +++ b/gas/testsuite/gas/avr32/pico.d
17838 @@ -0,0 +1,149 @@
17839 +#as:
17840 +#objdump: -dr
17841 +#name: pico
17842 +
17843 +.*: +file format .*
17844 +
17845 +Disassembly of section \.text:
17846 +
17847 +[0-9a-f]* <picosvmac>:
17848 + *[0-9a-f]*:   e1 a6 20 00     cop cp1,cr0,cr0,cr0,0xc
17849 + *[0-9a-f]*:   e1 a7 2b bb     cop cp1,cr11,cr11,cr11,0xe
17850 + *[0-9a-f]*:   e1 a6 3a 05     cop cp1,cr10,cr0,cr5,0xd
17851 + *[0-9a-f]*:   e1 a7 36 90     cop cp1,cr6,cr9,cr0,0xf
17852 +
17853 +[0-9a-f]* <picosvmul>:
17854 + *[0-9a-f]*:   e1 a4 20 00     cop cp1,cr0,cr0,cr0,0x8
17855 + *[0-9a-f]*:   e1 a5 2b bb     cop cp1,cr11,cr11,cr11,0xa
17856 + *[0-9a-f]*:   e1 a4 3a 05     cop cp1,cr10,cr0,cr5,0x9
17857 + *[0-9a-f]*:   e1 a5 36 90     cop cp1,cr6,cr9,cr0,0xb
17858 +
17859 +[0-9a-f]* <picovmac>:
17860 + *[0-9a-f]*:   e1 a2 20 00     cop cp1,cr0,cr0,cr0,0x4
17861 + *[0-9a-f]*:   e1 a3 2b bb     cop cp1,cr11,cr11,cr11,0x6
17862 + *[0-9a-f]*:   e1 a2 3a 05     cop cp1,cr10,cr0,cr5,0x5
17863 + *[0-9a-f]*:   e1 a3 36 90     cop cp1,cr6,cr9,cr0,0x7
17864 +
17865 +[0-9a-f]* <picovmul>:
17866 + *[0-9a-f]*:   e1 a0 20 00     cop cp1,cr0,cr0,cr0,0x0
17867 + *[0-9a-f]*:   e1 a1 2b bb     cop cp1,cr11,cr11,cr11,0x2
17868 + *[0-9a-f]*:   e1 a0 3a 05     cop cp1,cr10,cr0,cr5,0x1
17869 + *[0-9a-f]*:   e1 a1 36 90     cop cp1,cr6,cr9,cr0,0x3
17870 +
17871 +[0-9a-f]* <picold_d>:
17872 + *[0-9a-f]*:   e9 af 3e ff     ldc\.d cp1,cr14,pc\[0x3fc\]
17873 + *[0-9a-f]*:   e9 a0 30 ff     ldc\.d cp1,cr0,r0\[0x3fc\]
17874 + *[0-9a-f]*:   e9 a0 30 00     ldc\.d cp1,cr0,r0\[0x0\]
17875 + *[0-9a-f]*:   ef a8 26 50     ldc\.d cp1,cr6,--r8
17876 + *[0-9a-f]*:   ef a7 28 50     ldc\.d cp1,cr8,--r7
17877 + *[0-9a-f]*:   ef aa 32 65     ldc\.d cp1,cr2,r10\[r5<<0x2\]
17878 + *[0-9a-f]*:   ef a3 3c 46     ldc\.d cp1,cr12,r3\[r6\]
17879 +
17880 +[0-9a-f]* <picold_w>:
17881 + *[0-9a-f]*:   e9 af 2f ff     ldc\.w cp1,cr15,pc\[0x3fc\]
17882 + *[0-9a-f]*:   e9 a0 20 ff     ldc\.w cp1,cr0,r0\[0x3fc\]
17883 + *[0-9a-f]*:   e9 a0 20 00     ldc\.w cp1,cr0,r0\[0x0\]
17884 + *[0-9a-f]*:   ef a8 27 40     ldc\.w cp1,cr7,--r8
17885 + *[0-9a-f]*:   ef a7 28 40     ldc\.w cp1,cr8,--r7
17886 + *[0-9a-f]*:   ef aa 31 25     ldc\.w cp1,cr1,r10\[r5<<0x2\]
17887 + *[0-9a-f]*:   ef a3 3d 06     ldc\.w cp1,cr13,r3\[r6\]
17888 +
17889 +[0-9a-f]* <picoldm_d>:
17890 + *[0-9a-f]*:   ed af 24 ff     ldcm\.d cp1,pc,cr0-cr15
17891 + *[0-9a-f]*:   ed a0 24 01     ldcm\.d cp1,r0,cr0-cr1
17892 + *[0-9a-f]*:   ed a7 24 80     ldcm\.d cp1,r7,cr14-cr15
17893 + *[0-9a-f]*:   ed a8 24 7f     ldcm\.d cp1,r8,cr0-cr13
17894 +
17895 +[0-9a-f]* <picoldm_d_pu>:
17896 + *[0-9a-f]*:   ed af 34 ff     ldcm\.d cp1,pc\+\+,cr0-cr15
17897 + *[0-9a-f]*:   ed a0 34 01     ldcm\.d cp1,r0\+\+,cr0-cr1
17898 + *[0-9a-f]*:   ed a7 34 80     ldcm\.d cp1,r7\+\+,cr14-cr15
17899 + *[0-9a-f]*:   ed a8 34 7f     ldcm\.d cp1,r8\+\+,cr0-cr13
17900 +
17901 +[0-9a-f]* <picoldm_w>:
17902 + *[0-9a-f]*:   ed af 20 ff     ldcm\.w cp1,pc,cr0-cr7
17903 + *[0-9a-f]*:   ed a0 20 01     ldcm\.w cp1,r0,cr0
17904 + *[0-9a-f]*:   ed a7 20 80     ldcm\.w cp1,r7,cr7
17905 + *[0-9a-f]*:   ed a8 20 7f     ldcm\.w cp1,r8,cr0-cr6
17906 + *[0-9a-f]*:   ed af 21 ff     ldcm\.w cp1,pc,cr8-cr15
17907 + *[0-9a-f]*:   ed a0 21 01     ldcm\.w cp1,r0,cr8
17908 + *[0-9a-f]*:   ed a7 21 80     ldcm\.w cp1,r7,cr15
17909 + *[0-9a-f]*:   ed a8 21 7f     ldcm\.w cp1,r8,cr8-cr14
17910 +
17911 +[0-9a-f]* <picoldm_w_pu>:
17912 + *[0-9a-f]*:   ed af 30 ff     ldcm\.w cp1,pc\+\+,cr0-cr7
17913 + *[0-9a-f]*:   ed a0 30 01     ldcm\.w cp1,r0\+\+,cr0
17914 + *[0-9a-f]*:   ed a7 30 80     ldcm\.w cp1,r7\+\+,cr7
17915 + *[0-9a-f]*:   ed a8 30 7f     ldcm\.w cp1,r8\+\+,cr0-cr6
17916 + *[0-9a-f]*:   ed af 31 ff     ldcm\.w cp1,pc\+\+,cr8-cr15
17917 + *[0-9a-f]*:   ed a0 31 01     ldcm\.w cp1,r0\+\+,cr8
17918 + *[0-9a-f]*:   ed a7 31 80     ldcm\.w cp1,r7\+\+,cr15
17919 + *[0-9a-f]*:   ed a8 31 7f     ldcm\.w cp1,r8\+\+,cr8-cr14
17920 +
17921 +[0-9a-f]* <picomv_d>:
17922 + *[0-9a-f]*:   ef ae 2e 30     mvrc\.d cp1,cr14,lr
17923 + *[0-9a-f]*:   ef a0 20 30     mvrc\.d cp1,cr0,r0
17924 + *[0-9a-f]*:   ef a8 26 30     mvrc\.d cp1,cr6,r8
17925 + *[0-9a-f]*:   ef a6 28 30     mvrc\.d cp1,cr8,r6
17926 + *[0-9a-f]*:   ef ae 2e 10     mvcr\.d cp1,lr,cr14
17927 + *[0-9a-f]*:   ef a0 20 10     mvcr\.d cp1,r0,cr0
17928 + *[0-9a-f]*:   ef a8 26 10     mvcr\.d cp1,r8,cr6
17929 + *[0-9a-f]*:   ef a6 28 10     mvcr\.d cp1,r6,cr8
17930 +
17931 +[0-9a-f]* <picomv_w>:
17932 + *[0-9a-f]*:   ef af 2f 20     mvrc\.w cp1,cr15,pc
17933 + *[0-9a-f]*:   ef a0 20 20     mvrc\.w cp1,cr0,r0
17934 + *[0-9a-f]*:   ef a8 27 20     mvrc\.w cp1,cr7,r8
17935 + *[0-9a-f]*:   ef a7 28 20     mvrc\.w cp1,cr8,r7
17936 + *[0-9a-f]*:   ef af 2f 00     mvcr\.w cp1,pc,cr15
17937 + *[0-9a-f]*:   ef a0 20 00     mvcr\.w cp1,r0,cr0
17938 + *[0-9a-f]*:   ef a8 27 00     mvcr\.w cp1,r8,cr7
17939 + *[0-9a-f]*:   ef a7 28 00     mvcr\.w cp1,r7,cr8
17940 +
17941 +[0-9a-f]* <picost_d>:
17942 + *[0-9a-f]*:   eb af 3e ff     stc\.d cp1,pc\[0x3fc\],cr14
17943 + *[0-9a-f]*:   eb a0 30 00     stc\.d cp1,r0\[0x0\],cr0
17944 + *[0-9a-f]*:   ef a8 26 70     stc\.d cp1,r8\+\+,cr6
17945 + *[0-9a-f]*:   ef a7 28 70     stc\.d cp1,r7\+\+,cr8
17946 + *[0-9a-f]*:   ef aa 32 e5     stc\.d cp1,r10\[r5<<0x2\],cr2
17947 + *[0-9a-f]*:   ef a3 3c c6     stc\.d cp1,r3\[r6\],cr12
17948 +
17949 +[0-9a-f]* <picost_w>:
17950 + *[0-9a-f]*:   eb af 2f ff     stc\.w cp1,pc\[0x3fc\],cr15
17951 + *[0-9a-f]*:   eb a0 20 00     stc\.w cp1,r0\[0x0\],cr0
17952 + *[0-9a-f]*:   ef a8 27 60     stc\.w cp1,r8\+\+,cr7
17953 + *[0-9a-f]*:   ef a7 28 60     stc\.w cp1,r7\+\+,cr8
17954 + *[0-9a-f]*:   ef aa 31 a5     stc\.w cp1,r10\[r5<<0x2\],cr1
17955 + *[0-9a-f]*:   ef a3 3d 86     stc\.w cp1,r3\[r6\],cr13
17956 +
17957 +[0-9a-f]* <picostm_d>:
17958 + *[0-9a-f]*:   ed af 25 ff     stcm\.d cp1,pc,cr0-cr15
17959 + *[0-9a-f]*:   ed a0 25 01     stcm\.d cp1,r0,cr0-cr1
17960 + *[0-9a-f]*:   ed a7 25 80     stcm\.d cp1,r7,cr14-cr15
17961 + *[0-9a-f]*:   ed a8 25 7f     stcm\.d cp1,r8,cr0-cr13
17962 +
17963 +[0-9a-f]* <picostm_d_pu>:
17964 + *[0-9a-f]*:   ed af 35 ff     stcm\.d cp1,--pc,cr0-cr15
17965 + *[0-9a-f]*:   ed a0 35 01     stcm\.d cp1,--r0,cr0-cr1
17966 + *[0-9a-f]*:   ed a7 35 80     stcm\.d cp1,--r7,cr14-cr15
17967 + *[0-9a-f]*:   ed a8 35 7f     stcm\.d cp1,--r8,cr0-cr13
17968 +
17969 +[0-9a-f]* <picostm_w>:
17970 + *[0-9a-f]*:   ed af 22 ff     stcm\.w cp1,pc,cr0-cr7
17971 + *[0-9a-f]*:   ed a0 22 01     stcm\.w cp1,r0,cr0
17972 + *[0-9a-f]*:   ed a7 22 80     stcm\.w cp1,r7,cr7
17973 + *[0-9a-f]*:   ed a8 22 7f     stcm\.w cp1,r8,cr0-cr6
17974 + *[0-9a-f]*:   ed af 23 ff     stcm\.w cp1,pc,cr8-cr15
17975 + *[0-9a-f]*:   ed a0 23 01     stcm\.w cp1,r0,cr8
17976 + *[0-9a-f]*:   ed a7 23 80     stcm\.w cp1,r7,cr15
17977 + *[0-9a-f]*:   ed a8 23 7f     stcm\.w cp1,r8,cr8-cr14
17978 +
17979 +[0-9a-f]* <picostm_w_pu>:
17980 + *[0-9a-f]*:   ed af 32 ff     stcm\.w cp1,--pc,cr0-cr7
17981 + *[0-9a-f]*:   ed a0 32 01     stcm\.w cp1,--r0,cr0
17982 + *[0-9a-f]*:   ed a7 32 80     stcm\.w cp1,--r7,cr7
17983 + *[0-9a-f]*:   ed a8 32 7f     stcm\.w cp1,--r8,cr0-cr6
17984 + *[0-9a-f]*:   ed af 33 ff     stcm\.w cp1,--pc,cr8-cr15
17985 + *[0-9a-f]*:   ed a0 33 01     stcm\.w cp1,--r0,cr8
17986 + *[0-9a-f]*:   ed a7 33 80     stcm\.w cp1,--r7,cr15
17987 + *[0-9a-f]*:   ed a8 33 7f     stcm\.w cp1,--r8,cr8-cr14
17988 --- /dev/null
17989 +++ b/gas/testsuite/gas/avr32/pico.s
17990 @@ -0,0 +1,144 @@
17991 +
17992 +       .text
17993 +       .global picosvmac
17994 +picosvmac:
17995 +       picosvmac       out0, in0, in0, in0
17996 +       picosvmac       out2, in11, in11, in11
17997 +       picosvmac       out1, in10, in0, in5
17998 +       picosvmac       out3, in6, in9, in0
17999 +       .global picosvmul
18000 +picosvmul:
18001 +       picosvmul       out0, in0, in0, in0
18002 +       picosvmul       out2, in11, in11, in11
18003 +       picosvmul       out1, in10, in0, in5
18004 +       picosvmul       out3, in6, in9, in0
18005 +       .global picovmac
18006 +picovmac:
18007 +       picovmac        out0, in0, in0, in0
18008 +       picovmac        out2, in11, in11, in11
18009 +       picovmac        out1, in10, in0, in5
18010 +       picovmac        out3, in6, in9, in0
18011 +       .global picovmul
18012 +picovmul:
18013 +       picovmul        out0, in0, in0, in0
18014 +       picovmul        out2, in11, in11, in11
18015 +       picovmul        out1, in10, in0, in5
18016 +       picovmul        out3, in6, in9, in0
18017 +       .global picold_d
18018 +picold_d:
18019 +       picold.d        vmu2_out, pc[1020]
18020 +       picold.d        inpix2, r0[1020]
18021 +       picold.d        inpix2, r0[0]
18022 +       picold.d        coeff0_a, --r8
18023 +       picold.d        coeff1_a, --r7
18024 +       picold.d        inpix0, r10[r5 << 2]
18025 +       picold.d        vmu0_out, r3[r6 << 0]
18026 +       .global picold_w
18027 +picold_w:
18028 +       picold.w        config, pc[1020]
18029 +       picold.w        inpix2, r0[1020]
18030 +       picold.w        inpix2, r0[0]
18031 +       picold.w        coeff0_b, --r8
18032 +       picold.w        coeff1_a, --r7
18033 +       picold.w        inpix1, r10[r5 << 2]
18034 +       picold.w        vmu1_out, r3[r6 << 0]
18035 +       .global picoldm_d
18036 +picoldm_d:
18037 +       picoldm.d       pc, inpix2-config
18038 +       picoldm.d       r0, inpix2, inpix1
18039 +       picoldm.d       r7, vmu2_out, config
18040 +       picoldm.d       r8, inpix2-vmu1_out
18041 +       .global picoldm_d_pu
18042 +picoldm_d_pu:
18043 +       picoldm.d       pc++, inpix2, inpix1, inpix0, outpix2, outpix1, outpix0, coeff0_a, coeff0_b, coeff1_a, coeff1_b, coeff2_a, coeff2_b, vmu0_out, vmu1_out, vmu2_out, config
18044 +       picoldm.d       r0++, inpix2, inpix1
18045 +       picoldm.d       r7++, vmu2_out, config
18046 +       picoldm.d       r8++, inpix2, inpix1, inpix0, outpix2, outpix1, outpix0, coeff0_a, coeff0_b, coeff1_a, coeff1_b, coeff2_a, coeff2_b, vmu0_out, vmu1_out
18047 +       .global picoldm_w
18048 +picoldm_w:
18049 +       picoldm.w       pc, inpix2-coeff0_b
18050 +       picoldm.w       r0, inpix2
18051 +       picoldm.w       r7, coeff0_b
18052 +       picoldm.w       r8, inpix2-coeff0_a
18053 +       picoldm.w       pc, coeff1_a-config
18054 +       picoldm.w       r0, coeff1_a
18055 +       picoldm.w       r7, config
18056 +       picoldm.w       r8, coeff1_a-vmu2_out
18057 +       .global picoldm_w_pu
18058 +picoldm_w_pu:
18059 +       picoldm.w       pc++, inpix2-coeff0_b
18060 +       picoldm.w       r0++, inpix2
18061 +       picoldm.w       r7++, coeff0_b
18062 +       picoldm.w       r8++, inpix2-coeff0_a
18063 +       picoldm.w       pc++, coeff1_a-config
18064 +       picoldm.w       r0++, coeff1_a
18065 +       picoldm.w       r7++, config
18066 +       picoldm.w       r8++, coeff1_a-vmu2_out
18067 +       .global picomv_d
18068 +picomv_d:
18069 +       picomv.d        vmu2_out, lr
18070 +       picomv.d        inpix2, r0
18071 +       picomv.d        coeff0_a, r8
18072 +       picomv.d        coeff1_a, r6
18073 +       picomv.d        pc, vmu2_out
18074 +       picomv.d        r0, inpix2
18075 +       picomv.d        r8, coeff0_a
18076 +       picomv.d        r6, coeff1_a
18077 +       .global picomv_w
18078 +picomv_w:
18079 +       picomv.w        config, pc
18080 +       picomv.w        inpix2, r0
18081 +       picomv.w        coeff0_b, r8
18082 +       picomv.w        coeff1_a, r7
18083 +       picomv.w        pc, config
18084 +       picomv.w        r0, inpix2
18085 +       picomv.w        r8, coeff0_b
18086 +       picomv.w        r7, coeff1_a
18087 +       .global picost_d
18088 +picost_d:
18089 +       picost.d        pc[1020], vmu2_out
18090 +       picost.d        r0[0], inpix2
18091 +       picost.d        r8++, coeff0_a
18092 +       picost.d        r7++, coeff1_a
18093 +       picost.d        r10[r5 << 2], inpix0
18094 +       picost.d        r3[r6 << 0], vmu0_out
18095 +       .global picost_w
18096 +picost_w:
18097 +       picost.w        pc[1020], config
18098 +       picost.w        r0[0], inpix2
18099 +       picost.w        r8++, coeff0_b
18100 +       picost.w        r7++, coeff1_a
18101 +       picost.w        r10[r5 << 2], inpix1
18102 +       picost.w        r3[r6 << 0], vmu1_out
18103 +       .global picostm_d
18104 +picostm_d:
18105 +       picostm.d       pc, inpix2-config
18106 +       picostm.d       r0, inpix2, inpix1
18107 +       picostm.d       r7, vmu2_out, config
18108 +       picostm.d       r8, inpix2-vmu1_out
18109 +       .global picostm_d_pu
18110 +picostm_d_pu:
18111 +       picostm.d       --pc, inpix2, inpix1, inpix0, outpix2, outpix1, outpix0, coeff0_a, coeff0_b, coeff1_a, coeff1_b, coeff2_a, coeff2_b, vmu0_out, vmu1_out, vmu2_out, config
18112 +       picostm.d       --r0, inpix2, inpix1
18113 +       picostm.d       --r7, vmu2_out, config
18114 +       picostm.d       --r8, inpix2, inpix1, inpix0, outpix2, outpix1, outpix0, coeff0_a, coeff0_b, coeff1_a, coeff1_b, coeff2_a, coeff2_b, vmu0_out, vmu1_out
18115 +       .global picostm_w
18116 +picostm_w:
18117 +       picostm.w       pc, inpix2-coeff0_b
18118 +       picostm.w       r0, inpix2
18119 +       picostm.w       r7, coeff0_b
18120 +       picostm.w       r8, inpix2-coeff0_a
18121 +       picostm.w       pc, coeff1_a-config
18122 +       picostm.w       r0, coeff1_a
18123 +       picostm.w       r7, config
18124 +       picostm.w       r8, coeff1_a-vmu2_out
18125 +       .global picostm_w_pu
18126 +picostm_w_pu:
18127 +       picostm.w       --pc, inpix2-coeff0_b
18128 +       picostm.w       --r0, inpix2
18129 +       picostm.w       --r7, coeff0_b
18130 +       picostm.w       --r8, inpix2-coeff0_a
18131 +       picostm.w       --pc, coeff1_a-config
18132 +       picostm.w       --r0, coeff1_a
18133 +       picostm.w       --r7, config
18134 +       picostm.w       --r8, coeff1_a-vmu2_out
18135 --- /dev/null
18136 +++ b/gas/testsuite/gas/avr32/pic_reloc.d
18137 @@ -0,0 +1,27 @@
18138 +#as:
18139 +#objdump: -dr
18140 +#name: pic_reloc
18141 +
18142 +.*: +file format .*
18143 +
18144 +Disassembly of section \.text:
18145 +
18146 +00000000 <mcall_got>:
18147 +   0:  f0 16 00 00     mcall r6\[0\]
18148 +                       0: R_AVR32_GOT18SW      extfunc
18149 +   4:  f0 16 00 00     mcall r6\[0\]
18150 +                       4: R_AVR32_GOT18SW      \.L1
18151 +   8:  f0 16 00 00     mcall r6\[0\]
18152 +                       8: R_AVR32_GOT18SW      \.L2
18153 +   c:  f0 16 00 00     mcall r6\[0\]
18154 +                       c: R_AVR32_GOT18SW      mcall_got
18155 +
18156 +00000010 <ldw_got>:
18157 +  10:  ec f0 00 00     ld.w r0,r6\[0\]
18158 +                       10: R_AVR32_GOT16S      extvar
18159 +  14:  ec f0 00 00     ld.w r0,r6\[0\]
18160 +                       14: R_AVR32_GOT16S      \.L3
18161 +  18:  ec f0 00 00     ld.w r0,r6\[0\]
18162 +                       18: R_AVR32_GOT16S      \.L4
18163 +  1c:  ec f0 00 00     ld.w r0,r6\[0\]
18164 +                       1c: R_AVR32_GOT16S      ldw_got
18165 --- /dev/null
18166 +++ b/gas/testsuite/gas/avr32/pic_reloc.s
18167 @@ -0,0 +1,18 @@
18168 +
18169 +       .text
18170 +       .global mcall_got
18171 +mcall_got:
18172 +.L1:
18173 +       mcall   r6[extfunc@got]
18174 +       mcall   r6[.L1@got]
18175 +       mcall   r6[.L2@got]
18176 +       mcall   r6[mcall_got@got]
18177 +.L2:
18178 +
18179 +       .global ldw_got
18180 +ldw_got:
18181 +.L3:   ld.w    r0,r6[extvar@got]
18182 +       ld.w    r0,r6[.L3@got]
18183 +       ld.w    r0,r6[.L4@got]
18184 +       ld.w    r0,r6[ldw_got@got]
18185 +.L4:
18186 --- /dev/null
18187 +++ b/gas/testsuite/gas/avr32/symdiff.d
18188 @@ -0,0 +1,24 @@
18189 +#source: symdiff.s
18190 +#as:
18191 +#objdump: -dr
18192 +#name: symdiff
18193 +
18194 +.*: +file format .*
18195 +
18196 +Disassembly of section \.text:
18197 +
18198 +00000000 <diff32>:
18199 +   0:  00 00           add r0,r0
18200 +   2:  00 04           add r4,r0
18201 +
18202 +00000004 <diff16>:
18203 +   4:  00 04           add r4,r0
18204 +
18205 +00000006 <diff8>:
18206 +   6:  04 00           add r0,r2
18207 +
18208 +00000008 <symdiff_test>:
18209 +   8:  d7 03           nop
18210 +   a:  d7 03           nop
18211 +   c:  d7 03           nop
18212 +   e:  d7 03           nop
18213 --- /dev/null
18214 +++ b/gas/testsuite/gas/avr32/symdiff_linkrelax.d
18215 @@ -0,0 +1,28 @@
18216 +#source: symdiff.s
18217 +#as: --linkrelax
18218 +#objdump: -dr
18219 +#name: symdiff_linkrelax
18220 +
18221 +.*: +file format .*
18222 +
18223 +Disassembly of section \.text:
18224 +
18225 +00000000 <diff32>:
18226 +   0:  00 00           add r0,r0
18227 +                       0: R_AVR32_DIFF32       \.text\+0xa
18228 +   2:  00 04           add r4,r0
18229 +
18230 +00000004 <diff16>:
18231 +   4:  00 04           add r4,r0
18232 +                       4: R_AVR32_DIFF16       \.text\+0xa
18233 +
18234 +00000006 <diff8>:
18235 +   6:  04 00           add r0,r2
18236 +                       6: R_AVR32_DIFF8        \.text\+0xa
18237 +                       7: R_AVR32_ALIGN        \*ABS\*\+0x1
18238 +
18239 +00000008 <symdiff_test>:
18240 +   8:  d7 03           nop
18241 +   a:  d7 03           nop
18242 +   c:  d7 03           nop
18243 +   e:  d7 03           nop
18244 --- /dev/null
18245 +++ b/gas/testsuite/gas/avr32/symdiff.s
18246 @@ -0,0 +1,19 @@
18247 +
18248 +       .text
18249 +       .global diff32
18250 +diff32:
18251 +       .long   .L2 - .L1
18252 +       .global diff16
18253 +diff16:
18254 +       .short  .L2 - .L1
18255 +       .global diff8
18256 +diff8:
18257 +       .byte   .L2 - .L1
18258 +
18259 +       .global symdiff_test
18260 +       .align  1
18261 +symdiff_test:
18262 +       nop
18263 +.L1:   nop
18264 +       nop
18265 +.L2:   nop
18266 --- a/gas/write.c
18267 +++ b/gas/write.c
18268 @@ -1993,6 +1993,10 @@ relax_frag (segT segment, fragS *fragP,
18269
18270  #endif /* defined (TC_GENERIC_RELAX_TABLE)  */
18271
18272 +#ifdef TC_RELAX_ALIGN
18273 +#define RELAX_ALIGN(SEG, FRAG, ADDR) TC_RELAX_ALIGN(SEG, FRAG, ADDR)
18274 +#else
18275 +#define RELAX_ALIGN(SEG, FRAG, ADDR) relax_align(ADDR, (FRAG)->fr_offset)
18276  /* Relax_align. Advance location counter to next address that has 'alignment'
18277     lowest order bits all 0s, return size of adjustment made.  */
18278  static relax_addressT
18279 @@ -2012,6 +2016,7 @@ relax_align (register relax_addressT add
18280  #endif
18281    return (new_address - address);
18282  }
18283 +#endif
18284
18285  /* Now we have a segment, not a crowd of sub-segments, we can make
18286     fr_address values.
18287 @@ -2055,7 +2060,7 @@ relax_segment (struct frag *segment_frag
18288         case rs_align_code:
18289         case rs_align_test:
18290           {
18291 -           addressT offset = relax_align (address, (int) fragP->fr_offset);
18292 +           addressT offset = RELAX_ALIGN(segment, fragP, address);
18293
18294             if (fragP->fr_subtype != 0 && offset > fragP->fr_subtype)
18295               offset = 0;
18296 @@ -2256,10 +2261,10 @@ relax_segment (struct frag *segment_frag
18297                 {
18298                   addressT oldoff, newoff;
18299
18300 -                 oldoff = relax_align (was_address + fragP->fr_fix,
18301 -                                       (int) offset);
18302 -                 newoff = relax_align (address + fragP->fr_fix,
18303 -                                       (int) offset);
18304 +                 oldoff = RELAX_ALIGN (segment, fragP,
18305 +                                       was_address + fragP->fr_fix);
18306 +                 newoff = RELAX_ALIGN (segment, fragP,
18307 +                                       address + fragP->fr_fix);
18308
18309                   if (fragP->fr_subtype != 0)
18310                     {
18311 --- a/include/dis-asm.h
18312 +++ b/include/dis-asm.h
18313 @@ -213,6 +213,7 @@ typedef int (*disassembler_ftype) (bfd_v
18314
18315  extern int print_insn_alpha            (bfd_vma, disassemble_info *);
18316  extern int print_insn_avr              (bfd_vma, disassemble_info *);
18317 +extern int print_insn_avr32            (bfd_vma, disassemble_info *);
18318  extern int print_insn_bfin             (bfd_vma, disassemble_info *);
18319  extern int print_insn_big_arm          (bfd_vma, disassemble_info *);
18320  extern int print_insn_big_mips         (bfd_vma, disassemble_info *);
18321 @@ -293,7 +294,9 @@ extern void print_i386_disassembler_opti
18322  extern void print_mips_disassembler_options (FILE *);
18323  extern void print_ppc_disassembler_options (FILE *);
18324  extern void print_arm_disassembler_options (FILE *);
18325 +extern void print_avr32_disassembler_options (FILE *);
18326  extern void parse_arm_disassembler_option (char *);
18327 +extern void parse_avr32_disassembler_option (char *);
18328  extern void print_s390_disassembler_options (FILE *);
18329  extern int  get_arm_regname_num_options (void);
18330  extern int  set_arm_regname_option (int);
18331 --- /dev/null
18332 +++ b/include/elf/avr32.h
18333 @@ -0,0 +1,98 @@
18334 +/* AVR32 ELF support for BFD.
18335 +   Copyright 2003,2004,2005,2006,2007,2008,2009 Atmel Corporation.
18336 +
18337 +   Written by Haavard Skinnemoen, Atmel Norway, <hskinnemoen@atmel.com>
18338 +
18339 +   This file is part of BFD, the Binary File Descriptor library.
18340 +
18341 +   This program is free software; you can redistribute it and/or
18342 +   modify it under the terms of the GNU General Public License as
18343 +   published by the Free Software Foundation; either version 2 of the
18344 +   License, or (at your option) any later version.
18345 +
18346 +   This program is distributed in the hope that it will be useful, but
18347 +   WITHOUT ANY WARRANTY; without even the implied warranty of
18348 +   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
18349 +   General Public License for more details.
18350 +
18351 +   You should have received a copy of the GNU General Public License
18352 +   along with this program; if not, write to the Free Software
18353 +   Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA
18354 +   02111-1307, USA.  */
18355 +
18356 +#include "elf/reloc-macros.h"
18357 +
18358 +/* CPU-specific flags for the ELF header e_flags field */
18359 +#define EF_AVR32_LINKRELAX             0x01
18360 +#define EF_AVR32_PIC                   0x02
18361 +
18362 +START_RELOC_NUMBERS (elf_avr32_reloc_type)
18363 +    RELOC_NUMBER (R_AVR32_NONE,                        0)
18364 +
18365 +    /* Data Relocations */
18366 +    RELOC_NUMBER (R_AVR32_32,                  1)
18367 +    RELOC_NUMBER (R_AVR32_16,                  2)
18368 +    RELOC_NUMBER (R_AVR32_8,                   3)
18369 +    RELOC_NUMBER (R_AVR32_32_PCREL,            4)
18370 +    RELOC_NUMBER (R_AVR32_16_PCREL,            5)
18371 +    RELOC_NUMBER (R_AVR32_8_PCREL,             6)
18372 +    RELOC_NUMBER (R_AVR32_DIFF32,              7)
18373 +    RELOC_NUMBER (R_AVR32_DIFF16,              8)
18374 +    RELOC_NUMBER (R_AVR32_DIFF8,               9)
18375 +    RELOC_NUMBER (R_AVR32_GOT32,               10)
18376 +    RELOC_NUMBER (R_AVR32_GOT16,               11)
18377 +    RELOC_NUMBER (R_AVR32_GOT8,                        12)
18378 +
18379 +    /* Normal Code Relocations */
18380 +    RELOC_NUMBER (R_AVR32_21S,                 13)
18381 +    RELOC_NUMBER (R_AVR32_16U,                 14)
18382 +    RELOC_NUMBER (R_AVR32_16S,                 15)
18383 +    RELOC_NUMBER (R_AVR32_8S,                  16)
18384 +    RELOC_NUMBER (R_AVR32_8S_EXT,              17)
18385 +
18386 +    /* PC-Relative Code Relocations */
18387 +    RELOC_NUMBER (R_AVR32_22H_PCREL,           18)
18388 +    RELOC_NUMBER (R_AVR32_18W_PCREL,           19)
18389 +    RELOC_NUMBER (R_AVR32_16B_PCREL,           20)
18390 +    RELOC_NUMBER (R_AVR32_16N_PCREL,           21)
18391 +    RELOC_NUMBER (R_AVR32_14UW_PCREL,          22)
18392 +    RELOC_NUMBER (R_AVR32_11H_PCREL,           23)
18393 +    RELOC_NUMBER (R_AVR32_10UW_PCREL,          24)
18394 +    RELOC_NUMBER (R_AVR32_9H_PCREL,            25)
18395 +    RELOC_NUMBER (R_AVR32_9UW_PCREL,           26)
18396 +
18397 +    /* Special Code Relocations */
18398 +    RELOC_NUMBER (R_AVR32_HI16,                        27)
18399 +    RELOC_NUMBER (R_AVR32_LO16,                        28)
18400 +
18401 +    /* PIC Relocations */
18402 +    RELOC_NUMBER (R_AVR32_GOTPC,               29)
18403 +    RELOC_NUMBER (R_AVR32_GOTCALL,             30)
18404 +    RELOC_NUMBER (R_AVR32_LDA_GOT,             31)
18405 +    RELOC_NUMBER (R_AVR32_GOT21S,              32)
18406 +    RELOC_NUMBER (R_AVR32_GOT18SW,             33)
18407 +    RELOC_NUMBER (R_AVR32_GOT16S,              34)
18408 +    RELOC_NUMBER (R_AVR32_GOT7UW,              35)
18409 +
18410 +    /* Constant Pool Relocations */
18411 +    RELOC_NUMBER (R_AVR32_32_CPENT,            36)
18412 +    RELOC_NUMBER (R_AVR32_CPCALL,              37)
18413 +    RELOC_NUMBER (R_AVR32_16_CP,               38)
18414 +    RELOC_NUMBER (R_AVR32_9W_CP,               39)
18415 +
18416 +    /* Dynamic Relocations */
18417 +    RELOC_NUMBER (R_AVR32_RELATIVE,            40)
18418 +    RELOC_NUMBER (R_AVR32_GLOB_DAT,            41)
18419 +    RELOC_NUMBER (R_AVR32_JMP_SLOT,            42)
18420 +
18421 +    /* Linkrelax Information */
18422 +    RELOC_NUMBER (R_AVR32_ALIGN,               43)
18423 +
18424 +    RELOC_NUMBER (R_AVR32_15S,                 44)
18425 +
18426 +END_RELOC_NUMBERS (R_AVR32_max)
18427 +
18428 +/* Processor specific dynamic array tags.  */
18429 +
18430 +/* The total size in bytes of the Global Offset Table */
18431 +#define DT_AVR32_GOTSZ                 0x70000001
18432 --- a/include/elf/common.h
18433 +++ b/include/elf/common.h
18434 @@ -310,6 +310,9 @@
18435  /* V850 backend magic number.  Written in the absense of an ABI.  */
18436  #define EM_CYGNUS_V850         0x9080
18437
18438 +/* AVR32 magic number, picked by IAR Systems. */
18439 +#define EM_AVR32               0x18ad
18440 +
18441  /* old S/390 backend magic number. Written in the absence of an ABI.  */
18442  #define EM_S390_OLD            0xa390
18443
18444 --- a/ld/configdoc.texi
18445 +++ b/ld/configdoc.texi
18446 @@ -7,6 +7,7 @@
18447  @set H8300
18448  @set HPPA
18449  @set I960
18450 +@set AVR32
18451  @set M68HC11
18452  @set M68K
18453  @set MMIX
18454 --- a/ld/configure.tgt
18455 +++ b/ld/configure.tgt
18456 @@ -109,6 +109,9 @@ xscale-*-elf)               targ_emul=armelf
18457  avr-*-*)               targ_emul=avr2
18458                         targ_extra_emuls="avr1 avr25 avr3 avr31 avr35 avr4 avr5 avr51 avr6"
18459                         ;;
18460 +avr32-*-none)           targ_emul=avr32elf_ap7000
18461 +                        targ_extra_emuls="avr32elf_ap7001 avr32elf_ap7002 avr32elf_ap7200 avr32elf_uc3a0128 avr32elf_uc3a0256 avr32elf_uc3a0512 avr32elf_uc3a0512es avr32elf_uc3a1128 avr32elf_uc3a1256 avr32elf_uc3a1512es avr32elf_uc3a1512 avr32elf_uc3a364 avr32elf_uc3a364s avr32elf_uc3a3128 avr32elf_uc3a3128s avr32elf_uc3a3256 avr32elf_uc3a3256s avr32elf_uc3b064 avr32elf_uc3b0128 avr32elf_uc3b0256es avr32elf_uc3b0256 avr32elf_uc3b0512 avr32elf_uc3b0512revc avr32elf_uc3b164 avr32elf_uc3b1128 avr32elf_uc3b1256es avr32elf_uc3b1256 avr32elf_uc3b1512 avr32elf_uc3b1512revc avr32elf_uc3c064c avr32elf_uc3c0128c avr32elf_uc3c0256c avr32elf_uc3c0512crevc avr32elf_uc3c164c avr32elf_uc3c1128c avr32elf_uc3c1256c avr32elf_uc3c1512crevc avr32elf_uc3c264c avr32elf_uc3c2128c avr32elf_uc3c2256c avr32elf_uc3c2512crevc avr32elf_uc3l064 avr32elf_uc3l032 avr32elf_uc3l016 avr32elf_uc3l064revb" ;;
18462 +avr32-*-linux*)         targ_emul=avr32linux ;;
18463  bfin-*-elf)            targ_emul=elf32bfin;
18464                         targ_extra_emuls="elf32bfinfd"
18465                         targ_extra_libpath=$targ_extra_emuls
18466 --- /dev/null
18467 +++ b/ld/emulparams/avr32elf.sh
18468 @@ -0,0 +1,274 @@
18469 +# This script is called from ld/genscript.sh
18470 +# There is a difference on how 'bash' and POSIX handles
18471 +# the  '.' (source) command in a script.
18472 +# genscript.sh calls this script with argument ${EMULATION_NAME}
18473 +# but that will fail on POSIX compilant shells like 'sh' or 'dash'
18474 +# therefor I use the variable directly instead of $1
18475 +EMULATION=${EMULATION_NAME}
18476 +SCRIPT_NAME=avr32
18477 +TEMPLATE_NAME=elf32
18478 +EXTRA_EM_FILE=avr32elf
18479 +OUTPUT_FORMAT="elf32-avr32"
18480 +ARCH=avr32
18481 +MAXPAGESIZE=4096
18482 +ENTRY=_start
18483 +EMBEDDED=yes
18484 +NO_SMALL_DATA=yes
18485 +NOP=0xd703d703
18486 +
18487 +DATA_SEGMENT_ALIGN=8
18488 +BSS_ALIGNMENT=8
18489 +
18490 +RO_LMA_REGION="FLASH"
18491 +RO_VMA_REGION="FLASH"
18492 +RW_LMA_REGION="FLASH"
18493 +RW_VMA_REGION="CPUSRAM"
18494 +
18495 +STACK_SIZE=_stack_size
18496 +STACK_ADDR="ORIGIN(CPUSRAM) + LENGTH(CPUSRAM) - ${STACK_SIZE}"
18497 +
18498 +DATA_SEGMENT_END="
18499 +  __heap_start__ = ALIGN(8);
18500 +  . = ${STACK_ADDR};
18501 +  __heap_end__ = .;
18502 +"
18503 +
18504 +case "$EMULATION" in
18505 +avr32elf_ap*)
18506 +    MACHINE=ap
18507 +    INITIAL_READONLY_SECTIONS="
18508 +    .reset : {  *(.reset) } >FLASH AT>FLASH
18509 +    . = . & 0x9fffffff;
18510 +"
18511 +    TEXT_START_ADDR=0xa0000000
18512 +    case "$EMULATION" in
18513 +           avr32elf_ap700[0-2])
18514 +              MEMORY="
18515 +MEMORY
18516 +{
18517 +    FLASH (rxai) : ORIGIN = 0x00000000, LENGTH = 64M
18518 +    CPUSRAM (rwxa) : ORIGIN = 0x24000000, LENGTH = 32K
18519 +}
18520 +"
18521 +        ;;
18522 +    avr32elf_ap7200)
18523 +        MEMORY="
18524 +MEMORY
18525 +{
18526 +    FLASH (rxai) : ORIGIN = 0x00000000, LENGTH = 64M
18527 +    CPUSRAM (rwxa) : ORIGIN = 0x08000000, LENGTH = 64K
18528 +}
18529 +"
18530 +        ;;
18531 +    esac
18532 +    ;;
18533 +
18534 +avr32elf_uc3*)
18535 +    MACHINE=uc
18536 +    INITIAL_READONLY_SECTIONS=".reset : {  *(.reset) } >FLASH AT>FLASH"
18537 +    TEXT_START_ADDR=0x80000000
18538 +    OTHER_SECTIONS="
18539 +  .userpage :  { *(.userpage .userpage.*)  } >USERPAGE AT>USERPAGE
18540 +  .factorypage :  { *(.factorypage .factorypage.*)  } >FACTORYPAGE AT>FACTORYPAGE
18541 +"
18542 +
18543 +    case "$EMULATION" in
18544 +    avr32elf_uc3[ac][012]512*)
18545 +       MEMORY="
18546 +MEMORY
18547 +{
18548 +    FLASH (rxai!w) : ORIGIN = 0x80000000, LENGTH = 512K
18549 +    CPUSRAM (wxa!ri) : ORIGIN = 0x00000004, LENGTH = 0xFFFC
18550 +    USERPAGE : ORIGIN = 0x80800000, LENGTH = 512
18551 +    FACTORYPAGE : ORIGIN = 0x80800200, LENGTH = 512
18552 +}
18553 +"
18554 +        ;;
18555 +
18556 +    avr32elf_uc3[ac][012]256*)
18557 +        MEMORY="
18558 +MEMORY
18559 +{
18560 +    FLASH (rxai!w) : ORIGIN = 0x80000000, LENGTH = 256K
18561 +    CPUSRAM (wxa!ri) : ORIGIN = 0x00000004, LENGTH = 0xFFFC
18562 +    USERPAGE : ORIGIN = 0x80800000, LENGTH = 512
18563 +    FACTORYPAGE : ORIGIN = 0x80800200, LENGTH = 512
18564 +}
18565 +"
18566 +        ;;
18567 +
18568 +    avr32elf_uc3b[01]512revc)
18569 +        MEMORY="
18570 +MEMORY
18571 +{
18572 +    FLASH (rxai!w) : ORIGIN = 0x80000000, LENGTH = 512K
18573 +    CPUSRAM (wxa!ri) : ORIGIN = 0x00000004, LENGTH = 0x17FFC
18574 +    USERPAGE : ORIGIN = 0x80800000, LENGTH = 512
18575 +    FACTORYPAGE : ORIGIN = 0x80800200, LENGTH = 512
18576 +}
18577 +"
18578 +         PADDING="
18579 +  .padding : {
18580 +  QUAD(0)
18581 +  QUAD(0)
18582 +  QUAD(0)
18583 +  QUAD(0)
18584 +  } >FLASH AT>FLASH
18585 +"
18586 +        ;;
18587 +
18588 +    avr32elf_uc3b[01]512)
18589 +        MEMORY="
18590 +MEMORY
18591 +{
18592 +    FLASH (rxai!w) : ORIGIN = 0x80000000, LENGTH = 512K
18593 +    CPUSRAM (wxa!ri) : ORIGIN = 0x00000004, LENGTH = 0x17FFC
18594 +    USERPAGE : ORIGIN = 0x80800000, LENGTH = 512
18595 +    FACTORYPAGE : ORIGIN = 0x80800200, LENGTH = 512
18596 +}
18597 +"
18598 +        ;;
18599 +
18600 +    avr32elf_uc3b[01]256*)
18601 +        MEMORY="
18602 +MEMORY
18603 +{
18604 +    FLASH (rxai!w) : ORIGIN = 0x80000000, LENGTH = 256K
18605 +    CPUSRAM (wxa!ri) : ORIGIN = 0x00000004, LENGTH = 0x7FFC
18606 +    USERPAGE : ORIGIN = 0x80800000, LENGTH = 512
18607 +    FACTORYPAGE : ORIGIN = 0x80800200, LENGTH = 512
18608 +}
18609 +"
18610 +        ;;
18611 +
18612 +    avr32elf_uc3[abc][012]128*)
18613 +        MEMORY="
18614 +MEMORY
18615 +{
18616 +    FLASH (rxai!w) : ORIGIN = 0x80000000, LENGTH = 128K
18617 +    CPUSRAM (wxa!ri) : ORIGIN = 0x00000004, LENGTH = 0x7FFC
18618 +    USERPAGE : ORIGIN = 0x80800000, LENGTH = 512
18619 +    FACTORYPAGE : ORIGIN = 0x80800200, LENGTH = 512
18620 +}
18621 +"
18622 +        ;;
18623 +
18624 +    avr32elf_uc3[bc][0123]64*)
18625 +        MEMORY="
18626 +MEMORY
18627 +{
18628 +    FLASH (rxai!w) : ORIGIN = 0x80000000, LENGTH = 64K
18629 +    CPUSRAM (wxa!ri) : ORIGIN = 0x00000004, LENGTH = 0x3FFC
18630 +    USERPAGE : ORIGIN = 0x80800000, LENGTH = 512
18631 +    FACTORYPAGE : ORIGIN = 0x80800200, LENGTH = 512
18632 +}
18633 +"
18634 +        ;;
18635 +
18636 +    avr32elf_uc3a3256*)
18637 +        MEMORY="
18638 +MEMORY
18639 +{
18640 +    FLASH (rxai!w) : ORIGIN = 0x80000000, LENGTH = 256K
18641 +    CPUSRAM (wxa!ri) : ORIGIN = 0x00000004, LENGTH = 0xFFFC
18642 +    HSBSRAM (wxa!ri) : ORIGIN = 0xFF000000, LENGTH = 64K
18643 +    USERPAGE : ORIGIN = 0x80800000, LENGTH = 512
18644 +    FACTORYPAGE : ORIGIN = 0x80800200, LENGTH = 512
18645 +}
18646 +"
18647 +        OTHER_SECTIONS="${OTHER_SECTIONS}
18648 +  .hsbsram       : { *(.hsbsram .hsbsram.*) } >HSBSRAM AT>FLASH :FLASH
18649 +"
18650 +
18651 +        ;;
18652 +
18653 +    avr32elf_uc3a3128*)
18654 +        MEMORY="
18655 +MEMORY
18656 +{
18657 +    FLASH (rxai!w) : ORIGIN = 0x80000000, LENGTH = 128K
18658 +    CPUSRAM (wxa!ri) : ORIGIN = 0x00000004, LENGTH = 0xFFFC
18659 +    HSBSRAM (wxa!ri) : ORIGIN = 0xFF000000, LENGTH = 64K
18660 +    USERPAGE : ORIGIN = 0x80800000, LENGTH = 512
18661 +    FACTORYPAGE : ORIGIN = 0x80800200, LENGTH = 512
18662 +}
18663 +"
18664 +        OTHER_SECTIONS="${OTHER_SECTIONS}
18665 +  .hsbsram       : { *(.hsbsram .hsbsram.*) } >HSBSRAM AT>FLASH :FLASH
18666 +"
18667 +        ;;
18668 +
18669 +    avr32elf_uc3a364*)
18670 +        MEMORY="
18671 +MEMORY
18672 +{
18673 +    FLASH (rxai!w) : ORIGIN = 0x80000000, LENGTH = 64K
18674 +    CPUSRAM (wxa!ri) : ORIGIN = 0x00000004, LENGTH = 0xFFFC
18675 +    HSBSRAM (wxa!ri) : ORIGIN = 0xFF000000, LENGTH = 64K
18676 +    USERPAGE : ORIGIN = 0x80800000, LENGTH = 512
18677 +    FACTORYPAGE : ORIGIN = 0x80800200, LENGTH = 512
18678 +}
18679 +"
18680 +        OTHER_SECTIONS="${OTHER_SECTIONS}
18681 +  .hsbsram       : { *(.hsbsram .hsbsram.*) } >HSBSRAM AT>FLASH :FLASH
18682 +"
18683 +        ;;
18684 +
18685 +
18686 +    avr32elf_uc3l[0123]64*)
18687 +        MEMORY="
18688 +MEMORY
18689 +{
18690 +    FLASH (rxai!w) : ORIGIN = 0x80000000, LENGTH = 64K
18691 +    CPUSRAM (wxa!ri) : ORIGIN = 0x00000004, LENGTH = 0x3FFC
18692 +    USERPAGE : ORIGIN = 0x80800000, LENGTH = 512
18693 +    FACTORYPAGE : ORIGIN = 0x80800200, LENGTH = 512
18694 +    FLASHVAULT_FLASH_SIZE (r) : ORIGIN = 0x80800400, LENGTH = 8
18695 +    FLASHVAULT_RAM_SIZE (r) : ORIGIN = 0x80800408, LENGTH = 8
18696 +}
18697 +"
18698 +        OTHER_SECTIONS="${OTHER_SECTIONS}
18699 +  .flashvault_flash_size : { KEEP(*(.flashvault_flash_size .flashvault_flash_size.*)) } > FLASHVAULT_FLASH_SIZE
18700 +  .flashvault_ram_size   : { KEEP(*(.flashvault_ram_size .flashvault_ram_size.*)) } > FLASHVAULT_RAM_SIZE
18701 +"
18702 +        ;;
18703 +
18704 +    avr32elf_uc3l[0123]32*)
18705 +        MEMORY="
18706 +MEMORY
18707 +{
18708 +    FLASH (rxai!w) : ORIGIN = 0x80000000, LENGTH = 32K
18709 +    CPUSRAM (wxa!ri) : ORIGIN = 0x00000004, LENGTH = 0x3FFC
18710 +    USERPAGE : ORIGIN = 0x80800000, LENGTH = 512
18711 +    FACTORYPAGE : ORIGIN = 0x80800200, LENGTH = 512
18712 +    FLASHVAULT_FLASH_SIZE (r) : ORIGIN = 0x80800400, LENGTH = 8
18713 +    FLASHVAULT_RAM_SIZE (r) : ORIGIN = 0x80800408, LENGTH = 8
18714 +}
18715 +"
18716 +        OTHER_SECTIONS="${OTHER_SECTIONS}
18717 +  .flashvault_flash_size : { KEEP(*(.flashvault_flash_size .flashvault_flash_size.*)) } > FLASHVAULT_FLASH_SIZE
18718 +  .flashvault_ram_size   : { KEEP(*(.flashvault_ram_size .flashvault_ram_size.*)) } > FLASHVAULT_RAM_SIZE
18719 +"
18720 +        ;;
18721 +
18722 +    avr32elf_uc3l[0123]16*)
18723 +        MEMORY="
18724 +MEMORY
18725 +{
18726 +    FLASH (rxai!w) : ORIGIN = 0x80000000, LENGTH = 16K
18727 +    CPUSRAM (wxa!ri) : ORIGIN = 0x00000004, LENGTH = 0x1FFC
18728 +    USERPAGE : ORIGIN = 0x80800000, LENGTH = 512
18729 +    FACTORYPAGE : ORIGIN = 0x80800200, LENGTH = 512
18730 +    FLASHVAULT_FLASH_SIZE (r) : ORIGIN = 0x80800400, LENGTH = 8
18731 +    FLASHVAULT_RAM_SIZE (r) : ORIGIN = 0x80800408, LENGTH = 8
18732 +}
18733 +"
18734 +        OTHER_SECTIONS="${OTHER_SECTIONS}
18735 +  .flashvault_flash_size : { KEEP(*(.flashvault_flash_size .flashvault_flash_size.*)) } > FLASHVAULT_FLASH_SIZE
18736 +  .flashvault_ram_size   : { KEEP(*(.flashvault_ram_size .flashvault_ram_size.*)) } > FLASHVAULT_RAM_SIZE
18737 +"
18738 +        ;;
18739 +    esac
18740 +    ;;
18741 +
18742 +esac
18743 --- /dev/null
18744 +++ b/ld/emulparams/avr32linux.sh
18745 @@ -0,0 +1,14 @@
18746 +ARCH=avr32
18747 +SCRIPT_NAME=elf
18748 +TEMPLATE_NAME=elf32
18749 +EXTRA_EM_FILE=avr32elf
18750 +OUTPUT_FORMAT="elf32-avr32"
18751 +GENERATE_SHLIB_SCRIPT=yes
18752 +MAXPAGESIZE=0x1000
18753 +TEXT_START_ADDR=0x00001000
18754 +NOP=0xd703d703
18755 +
18756 +# This appears to place the GOT before the data section, which is
18757 +# essential for uClinux.  We don't use those .s* sections on AVR32
18758 +# anyway, so it shouldn't hurt for regular Linux either...
18759 +NO_SMALL_DATA=yes
18760 --- /dev/null
18761 +++ b/ld/emultempl/avr32elf.em
18762 @@ -0,0 +1,162 @@
18763 +# This shell script emits a C file. -*- C -*-
18764 +#   Copyright (C) 2007,2008,2009 Atmel Corporation
18765 +#
18766 +# This file is part of GLD, the Gnu Linker.
18767 +#
18768 +# This program is free software; you can redistribute it and/or modify
18769 +# it under the terms of the GNU General Public License as published by
18770 +# the Free Software Foundation; either version 2 of the License, or
18771 +# (at your option) any later version.
18772 +#
18773 +# This program is distributed in the hope that it will be useful,
18774 +# but WITHOUT ANY WARRANTY; without even the implied warranty of
18775 +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
18776 +# GNU General Public License for more details.
18777 +#
18778 +# You should have received a copy of the GNU General Public License
18779 +# along with this program; if not, write to the Free Software
18780 +# Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
18781 +#
18782 +
18783 +# This file is sourced from elf32.em, and defines extra avr32-elf
18784 +# specific routines.
18785 +#
18786 +
18787 +# Generate linker script for writable rodata
18788 +LD_FLAG=rodata-writable
18789 +DATA_ALIGNMENT=${DATA_ALIGNMENT_}
18790 +RELOCATING=" "
18791 +WRITABLE_RODATA=" "
18792 +( echo "/* Linker script for writable rodata */"
18793 +  . ${CUSTOMIZER_SCRIPT} ${EMULATION_NAME}
18794 +  . ${srcdir}/scripttempl/${SCRIPT_NAME}.sc
18795 +) | sed -e '/^ *$/d;s/[        ]*$//' > ldscripts/${EMULATION_NAME}.xwr
18796 +
18797 +
18798 +cat >> e${EMULATION_NAME}.c <<EOF
18799 +
18800 +#include "libbfd.h"
18801 +#include "elf32-avr32.h"
18802 +
18803 +/* Whether to allow direct references (sub or mov) to SEC_DATA and
18804 +   !SEC_CONTENTS sections when optimizing.  Not enabled by default
18805 +   since it might cause link errors.  */
18806 +static int direct_data_refs = 0;
18807 +
18808 +static void avr32_elf_after_open (void)
18809 +{
18810 +  bfd_elf32_avr32_set_options (&link_info, direct_data_refs);
18811 +  gld${EMULATION_NAME}_after_open ();
18812 +}
18813 +
18814 +static int rodata_writable = 0;
18815 +
18816 +static int stack_size = 0x1000;
18817 +
18818 +static void avr32_elf_set_symbols (void)
18819 +{
18820 +  /* Glue the assignments into the abs section.  */
18821 +  lang_statement_list_type *save = stat_ptr;
18822 +
18823 +
18824 +  stat_ptr = &(abs_output_section->children);
18825 +
18826 +  lang_add_assignment (exp_assop ('=', "_stack_size",
18827 +                                  exp_intop (stack_size)));
18828 +
18829 +  stat_ptr = save;
18830 +}
18831 +
18832 +static char * gld${EMULATION_NAME}_get_script (int *isfile);
18833 +
18834 +static char * avr32_elf_get_script (int *isfile)
18835 +{
18836 +  if ( rodata_writable )
18837 +    {
18838 +EOF
18839 +if test -n "$COMPILE_IN"
18840 +then
18841 +# Scripts compiled in.
18842 +
18843 +# sed commands to quote an ld script as a C string.
18844 +sc="-f stringify.sed"
18845 +
18846 +cat >>e${EMULATION_NAME}.c <<EOF
18847 +      *isfile = 0;
18848 +      return
18849 +EOF
18850 +sed $sc ldscripts/${EMULATION_NAME}.xwr                        >> e${EMULATION_NAME}.c
18851 +echo  ';'                                              >> e${EMULATION_NAME}.c
18852 +else
18853 +# Scripts read from the filesystem.
18854 +
18855 +cat >>e${EMULATION_NAME}.c <<EOF
18856 +      *isfile = 1;
18857 +      return "ldscripts/${EMULATION_NAME}.xwr";
18858 +EOF
18859 +fi
18860 +
18861 +cat >>e${EMULATION_NAME}.c <<EOF
18862 +    }
18863 +  return gld${EMULATION_NAME}_get_script (isfile);
18864 +}
18865 +
18866 +
18867 +EOF
18868 +
18869 +# Define some shell vars to insert bits of code into the standard elf
18870 +# parse_args and list_options functions.
18871 +#
18872 +PARSE_AND_LIST_PROLOGUE='
18873 +#define OPTION_DIRECT_DATA             300
18874 +#define OPTION_NO_DIRECT_DATA          301
18875 +#define OPTION_RODATA_WRITABLE         302
18876 +#define OPTION_NO_RODATA_WRITABLE      303
18877 +#define OPTION_STACK                   304
18878 +'
18879 +
18880 +PARSE_AND_LIST_LONGOPTS='
18881 +  { "direct-data", no_argument, NULL, OPTION_DIRECT_DATA },
18882 +  { "no-direct-data", no_argument, NULL, OPTION_NO_DIRECT_DATA },
18883 +  { "rodata-writable", no_argument, NULL, OPTION_RODATA_WRITABLE },
18884 +  { "no-rodata-writable", no_argument, NULL, OPTION_NO_RODATA_WRITABLE },
18885 +  { "stack", required_argument, NULL, OPTION_STACK },
18886 +'
18887 +
18888 +PARSE_AND_LIST_OPTIONS='
18889 +  fprintf (file, _("  --direct-data\t\tAllow direct data references when optimizing\n"));
18890 +  fprintf (file, _("  --no-direct-data\tDo not allow direct data references when optimizing\n"));
18891 +  fprintf (file, _("  --rodata-writable\tPut read-only data in writable data section\n"));
18892 +  fprintf (file, _("  --no-rodata-writable\tDo not put read-only data in writable data section\n"));
18893 +  fprintf (file, _("  --stack <size>\tSet the initial size of the stack\n"));
18894 +'
18895 +
18896 +PARSE_AND_LIST_ARGS_CASES='
18897 +    case OPTION_DIRECT_DATA:
18898 +      direct_data_refs = 1;
18899 +      break;
18900 +    case OPTION_NO_DIRECT_DATA:
18901 +      direct_data_refs = 0;
18902 +      break;
18903 +    case OPTION_RODATA_WRITABLE:
18904 +      rodata_writable = 1;
18905 +      break;
18906 +    case OPTION_NO_RODATA_WRITABLE:
18907 +      rodata_writable = 0;
18908 +      break;
18909 +    case OPTION_STACK:
18910 +     {
18911 +      char *end;
18912 +      stack_size = strtoul (optarg, &end, 0);
18913 +      if (end == optarg)
18914 +        einfo (_("%P%F: invalid hex number for parameter '%s'\n"), optarg);
18915 +      optarg = end;
18916 +      break;
18917 +     }
18918 +'
18919 +
18920 +# Replace some of the standard ELF functions with our own versions.
18921 +#
18922 +LDEMUL_AFTER_OPEN=avr32_elf_after_open
18923 +LDEMUL_GET_SCRIPT=avr32_elf_get_script
18924 +LDEMUL_SET_SYMBOLS=avr32_elf_set_symbols
18925 --- a/ld/Makefile.am
18926 +++ b/ld/Makefile.am
18927 @@ -142,6 +142,53 @@ ALL_EMULATIONS = \
18928         eavr5.o \
18929         eavr51.o \
18930         eavr6.o \
18931 +       eavr32elf_ap7000.o \
18932 +       eavr32elf_ap7001.o \
18933 +       eavr32elf_ap7002.o \
18934 +       eavr32elf_ap7200.o \
18935 +       eavr32elf_uc3a0128.o \
18936 +       eavr32elf_uc3a0256.o \
18937 +       eavr32elf_uc3a0512.o \
18938 +       eavr32elf_uc3a0512es.o \
18939 +       eavr32elf_uc3a1128.o \
18940 +       eavr32elf_uc3a1256.o \
18941 +       eavr32elf_uc3a1512es.o \
18942 +       eavr32elf_uc3a1512.o \
18943 +       eavr32elf_uc3a364.o \
18944 +       eavr32elf_uc3a364s.o \
18945 +       eavr32elf_uc3a3128.o \
18946 +       eavr32elf_uc3a3128s.o \
18947 +       eavr32elf_uc3a3256.o \
18948 +       eavr32elf_uc3a3256s.o \
18949 +       eavr32elf_uc3b064.o \
18950 +       eavr32elf_uc3b0128.o \
18951 +       eavr32elf_uc3b0256es.o \
18952 +       eavr32elf_uc3b0256.o \
18953 +       eavr32elf_uc3b0512.o \
18954 +       eavr32elf_uc3b0512revc.o \
18955 +       eavr32elf_uc3b164.o \
18956 +       eavr32elf_uc3b1128.o \
18957 +       eavr32elf_uc3b1256es.o \
18958 +       eavr32elf_uc3b1256.o \
18959 +       eavr32elf_uc3b1512.o \
18960 +       eavr32elf_uc3b1512revc.o \
18961 +       eavr32elf_uc3c064c.o \
18962 +       eavr32elf_uc3c0128c.o \
18963 +       eavr32elf_uc3c0256c.o \
18964 +       eavr32elf_uc3c0512crevc.o \
18965 +       eavr32elf_uc3c164c.o \
18966 +       eavr32elf_uc3c1128c.o \
18967 +       eavr32elf_uc3c1256c.o \
18968 +       eavr32elf_uc3c1512crevc.o \
18969 +       eavr32elf_uc3c264c.o \
18970 +       eavr32elf_uc3c2128c.o \
18971 +       eavr32elf_uc3c2256c.o \
18972 +       eavr32elf_uc3c2512crevc.o \
18973 +       eavr32elf_uc3l064.o \
18974 +       eavr32elf_uc3l032.o \
18975 +       eavr32elf_uc3l016.o \
18976 +       eavr32elf_uc3l064revb.o \
18977 +       eavr32linux.o \
18978         ecoff_i860.o \
18979         ecoff_sparc.o \
18980         eelf32_spu.o \
18981 @@ -648,6 +695,194 @@ eavr6.c: $(srcdir)/emulparams/avr6.sh $(
18982    $(ELF_DEPS) $(srcdir)/scripttempl/avr.sc \
18983    ${GEN_DEPENDS}
18984         ${GENSCRIPTS} avr6 "$(tdir_avr2)"
18985 +eavr32elf_ap7000.c: $(srcdir)/emulparams/avr32elf.sh \
18986 +  $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
18987 +  $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
18988 +       ${GENSCRIPTS} avr32elf_ap7000 "$(tdir_avr32)" avr32elf
18989 +eavr32elf_ap7001.c: $(srcdir)/emulparams/avr32elf.sh \
18990 +  $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
18991 +  $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
18992 +       ${GENSCRIPTS} avr32elf_ap7001 "$(tdir_avr32)" avr32elf
18993 +eavr32elf_ap7002.c: $(srcdir)/emulparams/avr32elf.sh \
18994 +  $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
18995 +  $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
18996 +       ${GENSCRIPTS} avr32elf_ap7002 "$(tdir_avr32)" avr32elf
18997 +eavr32elf_ap7200.c: $(srcdir)/emulparams/avr32elf.sh \
18998 +  $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
18999 +  $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
19000 +       ${GENSCRIPTS} avr32elf_ap7200 "$(tdir_avr32)" avr32elf
19001 +eavr32elf_uc3a0128.c: $(srcdir)/emulparams/avr32elf.sh \
19002 +  $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
19003 +  $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
19004 +       ${GENSCRIPTS} avr32elf_uc3a0128 "$(tdir_avr32)" avr32elf
19005 +eavr32elf_uc3a0256.c: $(srcdir)/emulparams/avr32elf.sh \
19006 +  $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
19007 +  $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
19008 +       ${GENSCRIPTS} avr32elf_uc3a0256 "$(tdir_avr32)" avr32elf
19009 +eavr32elf_uc3a0512.c: $(srcdir)/emulparams/avr32elf.sh \
19010 +  $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
19011 +  $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
19012 +       ${GENSCRIPTS} avr32elf_uc3a0512 "$(tdir_avr32)" avr32elf
19013 +eavr32elf_uc3a0512es.c: $(srcdir)/emulparams/avr32elf.sh \
19014 +  $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
19015 +  $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
19016 +       ${GENSCRIPTS} avr32elf_uc3a0512es "$(tdir_avr32)" avr32elf
19017 +eavr32elf_uc3a1128.c: $(srcdir)/emulparams/avr32elf.sh \
19018 +  $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
19019 +  $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
19020 +       ${GENSCRIPTS} avr32elf_uc3a1128 "$(tdir_avr32)" avr32elf
19021 +eavr32elf_uc3a1256.c: $(srcdir)/emulparams/avr32elf.sh \
19022 +  $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
19023 +  $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
19024 +       ${GENSCRIPTS} avr32elf_uc3a1256 "$(tdir_avr32)" avr32elf
19025 +eavr32elf_uc3a1512.c: $(srcdir)/emulparams/avr32elf.sh \
19026 +  $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
19027 +  $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
19028 +       ${GENSCRIPTS} avr32elf_uc3a1512 "$(tdir_avr32)" avr32elf
19029 +eavr32elf_uc3a1512es.c: $(srcdir)/emulparams/avr32elf.sh \
19030 +  $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
19031 +  $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
19032 +       ${GENSCRIPTS} avr32elf_uc3a1512es "$(tdir_avr32)" avr32elf
19033 +eavr32elf_uc3a364.c: $(srcdir)/emulparams/avr32elf.sh \
19034 +  $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
19035 +  $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
19036 +       ${GENSCRIPTS} avr32elf_uc3a364 "$(tdir_avr32)" avr32elf
19037 +eavr32elf_uc3a364s.c: $(srcdir)/emulparams/avr32elf.sh \
19038 +  $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
19039 +  $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
19040 +       ${GENSCRIPTS} avr32elf_uc3a364s "$(tdir_avr32)" avr32elf
19041 +eavr32elf_uc3a3128.c: $(srcdir)/emulparams/avr32elf.sh \
19042 +  $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
19043 +  $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
19044 +       ${GENSCRIPTS} avr32elf_uc3a3128 "$(tdir_avr32)" avr32elf
19045 +eavr32elf_uc3a3128s.c: $(srcdir)/emulparams/avr32elf.sh \
19046 +  $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
19047 +  $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
19048 +       ${GENSCRIPTS} avr32elf_uc3a3128s "$(tdir_avr32)" avr32elf
19049 +eavr32elf_uc3a3256.c: $(srcdir)/emulparams/avr32elf.sh \
19050 +  $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
19051 +  $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
19052 +       ${GENSCRIPTS} avr32elf_uc3a3256 "$(tdir_avr32)" avr32elf
19053 +eavr32elf_uc3a3256s.c: $(srcdir)/emulparams/avr32elf.sh \
19054 +  $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
19055 +  $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
19056 +       ${GENSCRIPTS} avr32elf_uc3a3256s "$(tdir_avr32)" avr32elf
19057 +eavr32elf_uc3b064.c: $(srcdir)/emulparams/avr32elf.sh \
19058 +  $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
19059 +  $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
19060 +       ${GENSCRIPTS} avr32elf_uc3b064 "$(tdir_avr32)" avr32elf
19061 +eavr32elf_uc3b0128.c: $(srcdir)/emulparams/avr32elf.sh \
19062 +  $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
19063 +  $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
19064 +       ${GENSCRIPTS} avr32elf_uc3b0128 "$(tdir_avr32)" avr32elf
19065 +eavr32elf_uc3b0256.c: $(srcdir)/emulparams/avr32elf.sh \
19066 +  $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
19067 +  $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
19068 +       ${GENSCRIPTS} avr32elf_uc3b0256 "$(tdir_avr32)" avr32elf
19069 +eavr32elf_uc3b0256es.c: $(srcdir)/emulparams/avr32elf.sh \
19070 +  $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
19071 +  $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
19072 +       ${GENSCRIPTS} avr32elf_uc3b0256es "$(tdir_avr32)" avr32elf
19073 +eavr32elf_uc3b0512.c: $(srcdir)/emulparams/avr32elf.sh \
19074 +  $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
19075 +  $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
19076 +       ${GENSCRIPTS} avr32elf_uc3b0512 "$(tdir_avr32)" avr32elf
19077 +eavr32elf_uc3b0512revc.c: $(srcdir)/emulparams/avr32elf.sh \
19078 +  $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
19079 +  $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
19080 +       ${GENSCRIPTS} avr32elf_uc3b0512revc "$(tdir_avr32)" avr32elf
19081 +eavr32elf_uc3b164.c: $(srcdir)/emulparams/avr32elf.sh \
19082 +  $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
19083 +  $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
19084 +       ${GENSCRIPTS} avr32elf_uc3b164 "$(tdir_avr32)" avr32elf
19085 +eavr32elf_uc3b1128.c: $(srcdir)/emulparams/avr32elf.sh \
19086 +  $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
19087 +  $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
19088 +       ${GENSCRIPTS} avr32elf_uc3b1128 "$(tdir_avr32)" avr32elf
19089 +eavr32elf_uc3b1256.c: $(srcdir)/emulparams/avr32elf.sh \
19090 +  $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
19091 +  $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
19092 +       ${GENSCRIPTS} avr32elf_uc3b1256 "$(tdir_avr32)" avr32elf
19093 +eavr32elf_uc3b1256es.c: $(srcdir)/emulparams/avr32elf.sh \
19094 +  $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
19095 +  $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
19096 +       ${GENSCRIPTS} avr32elf_uc3b1256es "$(tdir_avr32)" avr32elf
19097 +eavr32elf_uc3b1512.c: $(srcdir)/emulparams/avr32elf.sh \
19098 +  $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
19099 +  $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
19100 +       ${GENSCRIPTS} avr32elf_uc3b1512 "$(tdir_avr32)" avr32elf
19101 +eavr32elf_uc3b1512revc.c: $(srcdir)/emulparams/avr32elf.sh \
19102 +  $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
19103 +  $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
19104 +       ${GENSCRIPTS} avr32elf_uc3b1512revc "$(tdir_avr32)" avr32elf
19105 +eavr32elf_uc3c064c.c: $(srcdir)/emulparams/avr32elf.sh \
19106 +  $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
19107 +  $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
19108 +       ${GENSCRIPTS} avr32elf_uc3c064c "$(tdir_avr32)" avr32elf
19109 +eavr32elf_uc3c0128c.c: $(srcdir)/emulparams/avr32elf.sh \
19110 +  $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
19111 +  $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
19112 +       ${GENSCRIPTS} avr32elf_uc3c0128c "$(tdir_avr32)" avr32elf
19113 +eavr32elf_uc3c0256c.c: $(srcdir)/emulparams/avr32elf.sh \
19114 +  $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
19115 +  $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
19116 +       ${GENSCRIPTS} avr32elf_uc3c0256c "$(tdir_avr32)" avr32elf
19117 +eavr32elf_uc3c0512crevc.c: $(srcdir)/emulparams/avr32elf.sh \
19118 +  $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
19119 +  $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
19120 +       ${GENSCRIPTS} avr32elf_uc3c0512crevc "$(tdir_avr32)" avr32elf
19121 +eavr32elf_uc3c164c.c: $(srcdir)/emulparams/avr32elf.sh \
19122 +  $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
19123 +  $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
19124 +       ${GENSCRIPTS} avr32elf_uc3c164c "$(tdir_avr32)" avr32elf
19125 +eavr32elf_uc3c1128c.c: $(srcdir)/emulparams/avr32elf.sh \
19126 +  $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
19127 +  $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
19128 +       ${GENSCRIPTS} avr32elf_uc3c1128c "$(tdir_avr32)" avr32elf
19129 +eavr32elf_uc3c1256c.c: $(srcdir)/emulparams/avr32elf.sh \
19130 +  $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
19131 +  $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
19132 +       ${GENSCRIPTS} avr32elf_uc3c1256c "$(tdir_avr32)" avr32elf
19133 +eavr32elf_uc3c1512crevc.c: $(srcdir)/emulparams/avr32elf.sh \
19134 +  $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
19135 +  $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
19136 +       ${GENSCRIPTS} avr32elf_uc3c1512crevc "$(tdir_avr32)" avr32elf
19137 +eavr32elf_uc3c264c.c: $(srcdir)/emulparams/avr32elf.sh \
19138 +  $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
19139 +  $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
19140 +       ${GENSCRIPTS} avr32elf_uc3c264c "$(tdir_avr32)" avr32elf
19141 +eavr32elf_uc3c2128c.c: $(srcdir)/emulparams/avr32elf.sh \
19142 +  $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
19143 +  $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
19144 +       ${GENSCRIPTS} avr32elf_uc3c2128c "$(tdir_avr32)" avr32elf
19145 +eavr32elf_uc3c2256c.c: $(srcdir)/emulparams/avr32elf.sh \
19146 +  $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
19147 +  $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
19148 +       ${GENSCRIPTS} avr32elf_uc3c2256c "$(tdir_avr32)" avr32elf
19149 +eavr32elf_uc3c2512crevc.c: $(srcdir)/emulparams/avr32elf.sh \
19150 +  $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
19151 +  $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
19152 +       ${GENSCRIPTS} avr32elf_uc3c2512crevc "$(tdir_avr32)" avr32elf
19153 +eavr32elf_uc3l064.c: $(srcdir)/emulparams/avr32elf.sh \
19154 +  $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
19155 +  $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
19156 +       ${GENSCRIPTS} avr32elf_uc3l064 "$(tdir_avr32)" avr32elf
19157 +eavr32elf_uc3l032.c: $(srcdir)/emulparams/avr32elf.sh \
19158 +  $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
19159 +  $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
19160 +       ${GENSCRIPTS} avr32elf_uc3l032 "$(tdir_avr32)" avr32elf
19161 +eavr32elf_uc3l016.c: $(srcdir)/emulparams/avr32elf.sh \
19162 +  $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
19163 +  $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
19164 +       ${GENSCRIPTS} avr32elf_uc3l016 "$(tdir_avr32)" avr32elf
19165 +eavr32elf_uc3l064revb.c: $(srcdir)/emulparams/avr32elf.sh \
19166 +  $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
19167 +  $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
19168 +       ${GENSCRIPTS} avr32elf_uc3l064revb "$(tdir_avr32)" avr32elf
19169 +eavr32linux.c: $(srcdir)/emulparams/avr32linux.sh \
19170 +  $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
19171 +  $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS}
19172 +       ${GENSCRIPTS} avr32linux "$(tdir_avr32)"
19173  ecoff_i860.c: $(srcdir)/emulparams/coff_i860.sh \
19174    $(srcdir)/emultempl/generic.em $(srcdir)/scripttempl/i860coff.sc ${GEN_DEPENDS}
19175         ${GENSCRIPTS} coff_i860 "$(tdir_coff_i860)"
19176 --- a/ld/Makefile.in
19177 +++ b/ld/Makefile.in
19178 @@ -393,6 +393,53 @@ ALL_EMULATIONS = \
19179         eavr5.o \
19180         eavr51.o \
19181         eavr6.o \
19182 +       eavr32elf_ap7000.o \
19183 +       eavr32elf_ap7001.o \
19184 +       eavr32elf_ap7002.o \
19185 +       eavr32elf_ap7200.o \
19186 +       eavr32elf_uc3a0128.o \
19187 +       eavr32elf_uc3a0256.o \
19188 +       eavr32elf_uc3a0512.o \
19189 +       eavr32elf_uc3a0512es.o \
19190 +       eavr32elf_uc3a1128.o \
19191 +       eavr32elf_uc3a1256.o \
19192 +       eavr32elf_uc3a1512es.o \
19193 +       eavr32elf_uc3a1512.o \
19194 +       eavr32elf_uc3a364.o \
19195 +       eavr32elf_uc3a364s.o \
19196 +       eavr32elf_uc3a3128.o \
19197 +       eavr32elf_uc3a3128s.o \
19198 +       eavr32elf_uc3a3256.o \
19199 +       eavr32elf_uc3a3256s.o \
19200 +       eavr32elf_uc3b064.o \
19201 +       eavr32elf_uc3b0128.o \
19202 +       eavr32elf_uc3b0256es.o \
19203 +       eavr32elf_uc3b0256.o \
19204 +       eavr32elf_uc3b0512.o \
19205 +       eavr32elf_uc3b0512revc.o \
19206 +       eavr32elf_uc3b164.o \
19207 +       eavr32elf_uc3b1128.o \
19208 +       eavr32elf_uc3b1256es.o \
19209 +       eavr32elf_uc3b1256.o \
19210 +       eavr32elf_uc3b1512.o \
19211 +       eavr32elf_uc3b1512revc.o \
19212 +       eavr32elf_uc3c064c.o \
19213 +       eavr32elf_uc3c0128c.o \
19214 +       eavr32elf_uc3c0256c.o \
19215 +       eavr32elf_uc3c0512crevc.o \
19216 +       eavr32elf_uc3c164c.o \
19217 +       eavr32elf_uc3c1128c.o \
19218 +       eavr32elf_uc3c1256c.o \
19219 +       eavr32elf_uc3c1512crevc.o \
19220 +       eavr32elf_uc3c264c.o \
19221 +       eavr32elf_uc3c2128c.o \
19222 +       eavr32elf_uc3c2256c.o \
19223 +       eavr32elf_uc3c2512crevc.o \
19224 +       eavr32elf_uc3l064.o \
19225 +       eavr32elf_uc3l032.o \
19226 +       eavr32elf_uc3l016.o \
19227 +       eavr32elf_uc3l064revb.o \
19228 +       eavr32linux.o \
19229         ecoff_i860.o \
19230         ecoff_sparc.o \
19231         eelf32_spu.o \
19232 @@ -1480,6 +1527,194 @@ eavr6.c: $(srcdir)/emulparams/avr6.sh $(
19233    $(ELF_DEPS) $(srcdir)/scripttempl/avr.sc \
19234    ${GEN_DEPENDS}
19235         ${GENSCRIPTS} avr6 "$(tdir_avr2)"
19236 +eavr32elf_ap7000.c: $(srcdir)/emulparams/avr32elf.sh \
19237 +  $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
19238 +  $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
19239 +       ${GENSCRIPTS} avr32elf_ap7000 "$(tdir_avr32)" avr32elf
19240 +eavr32elf_ap7001.c: $(srcdir)/emulparams/avr32elf.sh \
19241 +  $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
19242 +  $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
19243 +       ${GENSCRIPTS} avr32elf_ap7001 "$(tdir_avr32)" avr32elf
19244 +eavr32elf_ap7002.c: $(srcdir)/emulparams/avr32elf.sh \
19245 +  $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
19246 +  $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
19247 +       ${GENSCRIPTS} avr32elf_ap7002 "$(tdir_avr32)" avr32elf
19248 +eavr32elf_ap7200.c: $(srcdir)/emulparams/avr32elf.sh \
19249 +  $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
19250 +  $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
19251 +       ${GENSCRIPTS} avr32elf_ap7200 "$(tdir_avr32)" avr32elf
19252 +eavr32elf_uc3a0128.c: $(srcdir)/emulparams/avr32elf.sh \
19253 +  $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
19254 +  $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
19255 +       ${GENSCRIPTS} avr32elf_uc3a0128 "$(tdir_avr32)" avr32elf
19256 +eavr32elf_uc3a0256.c: $(srcdir)/emulparams/avr32elf.sh \
19257 +  $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
19258 +  $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
19259 +       ${GENSCRIPTS} avr32elf_uc3a0256 "$(tdir_avr32)" avr32elf
19260 +eavr32elf_uc3a0512.c: $(srcdir)/emulparams/avr32elf.sh \
19261 +  $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
19262 +  $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
19263 +       ${GENSCRIPTS} avr32elf_uc3a0512 "$(tdir_avr32)" avr32elf
19264 +eavr32elf_uc3a0512es.c: $(srcdir)/emulparams/avr32elf.sh \
19265 +  $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
19266 +  $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
19267 +       ${GENSCRIPTS} avr32elf_uc3a0512es "$(tdir_avr32)" avr32elf
19268 +eavr32elf_uc3a1128.c: $(srcdir)/emulparams/avr32elf.sh \
19269 +  $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
19270 +  $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
19271 +       ${GENSCRIPTS} avr32elf_uc3a1128 "$(tdir_avr32)" avr32elf
19272 +eavr32elf_uc3a1256.c: $(srcdir)/emulparams/avr32elf.sh \
19273 +  $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
19274 +  $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
19275 +       ${GENSCRIPTS} avr32elf_uc3a1256 "$(tdir_avr32)" avr32elf
19276 +eavr32elf_uc3a1512.c: $(srcdir)/emulparams/avr32elf.sh \
19277 +  $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
19278 +  $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
19279 +       ${GENSCRIPTS} avr32elf_uc3a1512 "$(tdir_avr32)" avr32elf
19280 +eavr32elf_uc3a1512es.c: $(srcdir)/emulparams/avr32elf.sh \
19281 +  $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
19282 +  $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
19283 +       ${GENSCRIPTS} avr32elf_uc3a1512es "$(tdir_avr32)" avr32elf
19284 +eavr32elf_uc3a364.c: $(srcdir)/emulparams/avr32elf.sh \
19285 +  $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
19286 +  $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
19287 +       ${GENSCRIPTS} avr32elf_uc3a364 "$(tdir_avr32)" avr32elf
19288 +eavr32elf_uc3a364s.c: $(srcdir)/emulparams/avr32elf.sh \
19289 +  $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
19290 +  $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
19291 +       ${GENSCRIPTS} avr32elf_uc3a364s "$(tdir_avr32)" avr32elf
19292 +eavr32elf_uc3a3128.c: $(srcdir)/emulparams/avr32elf.sh \
19293 +  $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
19294 +  $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
19295 +       ${GENSCRIPTS} avr32elf_uc3a3128 "$(tdir_avr32)" avr32elf
19296 +eavr32elf_uc3a3128s.c: $(srcdir)/emulparams/avr32elf.sh \
19297 +  $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
19298 +  $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
19299 +       ${GENSCRIPTS} avr32elf_uc3a3128s "$(tdir_avr32)" avr32elf
19300 +eavr32elf_uc3a3256.c: $(srcdir)/emulparams/avr32elf.sh \
19301 +  $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
19302 +  $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
19303 +       ${GENSCRIPTS} avr32elf_uc3a3256 "$(tdir_avr32)" avr32elf
19304 +eavr32elf_uc3a3256s.c: $(srcdir)/emulparams/avr32elf.sh \
19305 +  $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
19306 +  $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
19307 +       ${GENSCRIPTS} avr32elf_uc3a3256s "$(tdir_avr32)" avr32elf
19308 +eavr32elf_uc3b064.c: $(srcdir)/emulparams/avr32elf.sh \
19309 +  $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
19310 +  $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
19311 +       ${GENSCRIPTS} avr32elf_uc3b064 "$(tdir_avr32)" avr32elf
19312 +eavr32elf_uc3b0128.c: $(srcdir)/emulparams/avr32elf.sh \
19313 +  $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
19314 +  $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
19315 +       ${GENSCRIPTS} avr32elf_uc3b0128 "$(tdir_avr32)" avr32elf
19316 +eavr32elf_uc3b0256.c: $(srcdir)/emulparams/avr32elf.sh \
19317 +  $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
19318 +  $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
19319 +       ${GENSCRIPTS} avr32elf_uc3b0256 "$(tdir_avr32)" avr32elf
19320 +eavr32elf_uc3b0256es.c: $(srcdir)/emulparams/avr32elf.sh \
19321 +  $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
19322 +  $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
19323 +       ${GENSCRIPTS} avr32elf_uc3b0256es "$(tdir_avr32)" avr32elf
19324 +eavr32elf_uc3b0512.c: $(srcdir)/emulparams/avr32elf.sh \
19325 +  $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
19326 +  $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
19327 +       ${GENSCRIPTS} avr32elf_uc3b0512 "$(tdir_avr32)" avr32elf
19328 +eavr32elf_uc3b0512revc.c: $(srcdir)/emulparams/avr32elf.sh \
19329 +  $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
19330 +  $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
19331 +       ${GENSCRIPTS} avr32elf_uc3b0512revc "$(tdir_avr32)" avr32elf
19332 +eavr32elf_uc3b164.c: $(srcdir)/emulparams/avr32elf.sh \
19333 +  $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
19334 +  $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
19335 +       ${GENSCRIPTS} avr32elf_uc3b164 "$(tdir_avr32)" avr32elf
19336 +eavr32elf_uc3b1128.c: $(srcdir)/emulparams/avr32elf.sh \
19337 +  $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
19338 +  $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
19339 +       ${GENSCRIPTS} avr32elf_uc3b1128 "$(tdir_avr32)" avr32elf
19340 +eavr32elf_uc3b1256.c: $(srcdir)/emulparams/avr32elf.sh \
19341 +  $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
19342 +  $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
19343 +       ${GENSCRIPTS} avr32elf_uc3b1256 "$(tdir_avr32)" avr32elf
19344 +eavr32elf_uc3b1256es.c: $(srcdir)/emulparams/avr32elf.sh \
19345 +  $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
19346 +  $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
19347 +       ${GENSCRIPTS} avr32elf_uc3b1256es "$(tdir_avr32)" avr32elf
19348 +eavr32elf_uc3b1512.c: $(srcdir)/emulparams/avr32elf.sh \
19349 +  $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
19350 +  $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
19351 +       ${GENSCRIPTS} avr32elf_uc3b1512 "$(tdir_avr32)" avr32elf
19352 +eavr32elf_uc3b1512revc.c: $(srcdir)/emulparams/avr32elf.sh \
19353 +  $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
19354 +  $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
19355 +       ${GENSCRIPTS} avr32elf_uc3b1512revc "$(tdir_avr32)" avr32elf
19356 +eavr32elf_uc3c064c.c: $(srcdir)/emulparams/avr32elf.sh \
19357 +  $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
19358 +  $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
19359 +       ${GENSCRIPTS} avr32elf_uc3c064c "$(tdir_avr32)" avr32elf
19360 +eavr32elf_uc3c0128c.c: $(srcdir)/emulparams/avr32elf.sh \
19361 +  $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
19362 +  $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
19363 +       ${GENSCRIPTS} avr32elf_uc3c0128c "$(tdir_avr32)" avr32elf
19364 +eavr32elf_uc3c0256c.c: $(srcdir)/emulparams/avr32elf.sh \
19365 +  $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
19366 +  $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
19367 +       ${GENSCRIPTS} avr32elf_uc3c0256c "$(tdir_avr32)" avr32elf
19368 +eavr32elf_uc3c0512crevc.c: $(srcdir)/emulparams/avr32elf.sh \
19369 +  $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
19370 +  $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
19371 +       ${GENSCRIPTS} avr32elf_uc3c0512crevc "$(tdir_avr32)" avr32elf
19372 +eavr32elf_uc3c164c.c: $(srcdir)/emulparams/avr32elf.sh \
19373 +  $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
19374 +  $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
19375 +       ${GENSCRIPTS} avr32elf_uc3c164c "$(tdir_avr32)" avr32elf
19376 +eavr32elf_uc3c1128c.c: $(srcdir)/emulparams/avr32elf.sh \
19377 +  $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
19378 +  $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
19379 +       ${GENSCRIPTS} avr32elf_uc3c1128c "$(tdir_avr32)" avr32elf
19380 +eavr32elf_uc3c1256c.c: $(srcdir)/emulparams/avr32elf.sh \
19381 +  $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
19382 +  $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
19383 +       ${GENSCRIPTS} avr32elf_uc3c1256c "$(tdir_avr32)" avr32elf
19384 +eavr32elf_uc3c1512crevc.c: $(srcdir)/emulparams/avr32elf.sh \
19385 +  $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
19386 +  $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
19387 +       ${GENSCRIPTS} avr32elf_uc3c1512crevc "$(tdir_avr32)" avr32elf
19388 +eavr32elf_uc3c264c.c: $(srcdir)/emulparams/avr32elf.sh \
19389 +  $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
19390 +  $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
19391 +       ${GENSCRIPTS} avr32elf_uc3c264c "$(tdir_avr32)" avr32elf
19392 +eavr32elf_uc3c2128c.c: $(srcdir)/emulparams/avr32elf.sh \
19393 +  $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
19394 +  $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
19395 +       ${GENSCRIPTS} avr32elf_uc3c2128c "$(tdir_avr32)" avr32elf
19396 +eavr32elf_uc3c2256c.c: $(srcdir)/emulparams/avr32elf.sh \
19397 +  $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
19398 +  $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
19399 +       ${GENSCRIPTS} avr32elf_uc3c2256c "$(tdir_avr32)" avr32elf
19400 +eavr32elf_uc3c2512crevc.c: $(srcdir)/emulparams/avr32elf.sh \
19401 +  $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
19402 +  $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
19403 +       ${GENSCRIPTS} avr32elf_uc3c2512crevc "$(tdir_avr32)" avr32elf
19404 +eavr32elf_uc3l064.c: $(srcdir)/emulparams/avr32elf.sh \
19405 +  $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
19406 +  $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
19407 +       ${GENSCRIPTS} avr32elf_uc3l064 "$(tdir_avr32)" avr32elf
19408 +eavr32elf_uc3l032.c: $(srcdir)/emulparams/avr32elf.sh \
19409 +  $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
19410 +  $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
19411 +       ${GENSCRIPTS} avr32elf_uc3l032 "$(tdir_avr32)" avr32elf
19412 +eavr32elf_uc3l016.c: $(srcdir)/emulparams/avr32elf.sh \
19413 +  $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
19414 +  $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
19415 +       ${GENSCRIPTS} avr32elf_uc3l016 "$(tdir_avr32)" avr32elf
19416 +eavr32elf_uc3l064revb.c: $(srcdir)/emulparams/avr32elf.sh \
19417 +  $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
19418 +  $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
19419 +       ${GENSCRIPTS} avr32elf_uc3l064revb "$(tdir_avr32)" avr32elf
19420 +eavr32linux.c: $(srcdir)/emulparams/avr32linux.sh \
19421 +  $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
19422 +  $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS}
19423 +       ${GENSCRIPTS} avr32linux "$(tdir_avr32)"
19424  ecoff_i860.c: $(srcdir)/emulparams/coff_i860.sh \
19425    $(srcdir)/emultempl/generic.em $(srcdir)/scripttempl/i860coff.sc ${GEN_DEPENDS}
19426         ${GENSCRIPTS} coff_i860 "$(tdir_coff_i860)"
19427 --- /dev/null
19428 +++ b/ld/scripttempl/avr32.sc
19429 @@ -0,0 +1,459 @@
19430 +#
19431 +# Unusual variables checked by this code:
19432 +#      NOP - four byte opcode for no-op (defaults to 0)
19433 +#      NO_SMALL_DATA - no .sbss/.sbss2/.sdata/.sdata2 sections if not
19434 +#              empty.
19435 +#      SMALL_DATA_CTOR - .ctors contains small data.
19436 +#      SMALL_DATA_DTOR - .dtors contains small data.
19437 +#      DATA_ADDR - if end-of-text-plus-one-page isn't right for data start
19438 +#      INITIAL_READONLY_SECTIONS - at start of text segment
19439 +#      OTHER_READONLY_SECTIONS - other than .text .init .rodata ...
19440 +#              (e.g., .PARISC.milli)
19441 +#      OTHER_TEXT_SECTIONS - these get put in .text when relocating
19442 +#      OTHER_READWRITE_SECTIONS - other than .data .bss .ctors .sdata ...
19443 +#              (e.g., .PARISC.global)
19444 +#      OTHER_RELRO_SECTIONS - other than .data.rel.ro ...
19445 +#              (e.g. PPC32 .fixup, .got[12])
19446 +#      OTHER_BSS_SECTIONS - other than .bss .sbss ...
19447 +#      OTHER_SECTIONS - at the end
19448 +#      EXECUTABLE_SYMBOLS - symbols that must be defined for an
19449 +#              executable (e.g., _DYNAMIC_LINK)
19450 +#       TEXT_START_ADDR - the first byte of the text segment, after any
19451 +#               headers.
19452 +#       TEXT_BASE_ADDRESS - the first byte of the text segment.
19453 +#      TEXT_START_SYMBOLS - symbols that appear at the start of the
19454 +#              .text section.
19455 +#      DATA_START_SYMBOLS - symbols that appear at the start of the
19456 +#              .data section.
19457 +#      OTHER_GOT_SYMBOLS - symbols defined just before .got.
19458 +#      OTHER_GOT_SECTIONS - sections just after .got.
19459 +#      OTHER_SDATA_SECTIONS - sections just after .sdata.
19460 +#      OTHER_BSS_SYMBOLS - symbols that appear at the start of the
19461 +#              .bss section besides __bss_start.
19462 +#      DATA_PLT - .plt should be in data segment, not text segment.
19463 +#      PLT_BEFORE_GOT - .plt just before .got when .plt is in data segement.
19464 +#      BSS_PLT - .plt should be in bss segment
19465 +#      TEXT_DYNAMIC - .dynamic in text segment, not data segment.
19466 +#      EMBEDDED - whether this is for an embedded system.
19467 +#      SHLIB_TEXT_START_ADDR - if set, add to SIZEOF_HEADERS to set
19468 +#              start address of shared library.
19469 +#      INPUT_FILES - INPUT command of files to always include
19470 +#      WRITABLE_RODATA - if set, the .rodata section should be writable
19471 +#      INIT_START, INIT_END -  statements just before and just after
19472 +#      combination of .init sections.
19473 +#      FINI_START, FINI_END - statements just before and just after
19474 +#      combination of .fini sections.
19475 +#      STACK_ADDR - start of a .stack section.
19476 +#      OTHER_END_SYMBOLS - symbols to place right at the end of the script.
19477 +#      SEPARATE_GOTPLT - if set, .got.plt should be separate output section,
19478 +#              so that .got can be in the RELRO area.  It should be set to
19479 +#              the number of bytes in the beginning of .got.plt which can be
19480 +#              in the RELRO area as well.
19481 +#
19482 +# When adding sections, do note that the names of some sections are used
19483 +# when specifying the start address of the next.
19484 +#
19485 +
19486 +#  Many sections come in three flavours.  There is the 'real' section,
19487 +#  like ".data".  Then there are the per-procedure or per-variable
19488 +#  sections, generated by -ffunction-sections and -fdata-sections in GCC,
19489 +#  and useful for --gc-sections, which for a variable "foo" might be
19490 +#  ".data.foo".  Then there are the linkonce sections, for which the linker
19491 +#  eliminates duplicates, which are named like ".gnu.linkonce.d.foo".
19492 +#  The exact correspondences are:
19493 +#
19494 +#  Section     Linkonce section
19495 +#  .text       .gnu.linkonce.t.foo
19496 +#  .rodata     .gnu.linkonce.r.foo
19497 +#  .data       .gnu.linkonce.d.foo
19498 +#  .bss                .gnu.linkonce.b.foo
19499 +#  .sdata      .gnu.linkonce.s.foo
19500 +#  .sbss       .gnu.linkonce.sb.foo
19501 +#  .sdata2     .gnu.linkonce.s2.foo
19502 +#  .sbss2      .gnu.linkonce.sb2.foo
19503 +#  .debug_info .gnu.linkonce.wi.foo
19504 +#  .tdata      .gnu.linkonce.td.foo
19505 +#  .tbss       .gnu.linkonce.tb.foo
19506 +#
19507 +#  Each of these can also have corresponding .rel.* and .rela.* sections.
19508 +
19509 +test -z "$ENTRY" && ENTRY=_start
19510 +test -z "${BIG_OUTPUT_FORMAT}" && BIG_OUTPUT_FORMAT=${OUTPUT_FORMAT}
19511 +test -z "${LITTLE_OUTPUT_FORMAT}" && LITTLE_OUTPUT_FORMAT=${OUTPUT_FORMAT}
19512 +if [ -z "$MACHINE" ]; then OUTPUT_ARCH=${ARCH}; else OUTPUT_ARCH=${ARCH}:${MACHINE}; fi
19513 +test -z "${ELFSIZE}" && ELFSIZE=32
19514 +test -z "${ALIGNMENT}" && ALIGNMENT="${ELFSIZE} / 8"
19515 +test "$LD_FLAG" = "N" && DATA_ADDR=.
19516 +test -n "$CREATE_SHLIB$CREATE_PIE" && test -n "$SHLIB_DATA_ADDR" && COMMONPAGESIZE=""
19517 +test -z "$CREATE_SHLIB$CREATE_PIE" && test -n "$DATA_ADDR" && COMMONPAGESIZE=""
19518 +test -n "$RELRO_NOW" && unset SEPARATE_GOTPLT
19519 +if test -n "$RELOCATING"; then
19520 +  RO_REGION="${RO_VMA_REGION+ >}${RO_VMA_REGION}${RO_LMA_REGION+ AT>}${RO_LMA_REGION}"
19521 +  RW_REGION="${RW_VMA_REGION+ >}${RW_VMA_REGION}${RW_LMA_REGION+ AT>}${RW_LMA_REGION}"
19522 +  RW_BSS_REGION="${RW_VMA_REGION+ >}${RW_VMA_REGION}"
19523 +else
19524 +  RO_REGION=""
19525 +  RW_REGION=""
19526 +  RW_BSS_REGION=""
19527 +fi
19528 +INTERP=".interp       ${RELOCATING-0} : { *(.interp) }${RO_REGION}"
19529 +PLT=".plt          ${RELOCATING-0} : { *(.plt) }"
19530 +if test -z "$GOT"; then
19531 +  if test -z "$SEPARATE_GOTPLT"; then
19532 +    GOT=".got          ${RELOCATING-0} : { *(.got.plt) *(.got) }"
19533 +  else
19534 +    GOT=".got          ${RELOCATING-0} : { *(.got) }"
19535 +    GOTPLT="${RELOCATING+${DATA_SEGMENT_RELRO_GOTPLT_END}}
19536 +  .got.plt      ${RELOCATING-0} : { *(.got.plt) }"
19537 +  fi
19538 +fi
19539 +DALIGN=".dalign        : { . = ALIGN(${DATA_SEGMENT_ALIGN}); PROVIDE(_data_lma = .); }${RO_REGION}"
19540 +BALIGN=".balign        : { . = ALIGN(${BSS_ALIGNMENT}); _edata = .; }${RW_REGION}"
19541 +DYNAMIC=".dynamic      ${RELOCATING-0} : { *(.dynamic) }"
19542 +RODATA=".rodata       ${RELOCATING-0} : { *(.rodata${RELOCATING+ .rodata.* .gnu.linkonce.r.*}) }"
19543 +DATARELRO=".data.rel.ro : { *(.data.rel.ro.local) *(.data.rel.ro*) }${RW_REGION}"
19544 +STACKNOTE="/DISCARD/ : { *(.note.GNU-stack) }"
19545 +if test -z "${NO_SMALL_DATA}"; then
19546 +  SBSS=".sbss         ${RELOCATING-0} :
19547 +  {
19548 +    ${RELOCATING+PROVIDE (__sbss_start = .);}
19549 +    ${RELOCATING+PROVIDE (___sbss_start = .);}
19550 +    ${CREATE_SHLIB+*(.sbss2 .sbss2.* .gnu.linkonce.sb2.*)}
19551 +    *(.dynsbss)
19552 +    *(.sbss${RELOCATING+ .sbss.* .gnu.linkonce.sb.*})
19553 +    *(.scommon)
19554 +    ${RELOCATING+PROVIDE (__sbss_end = .);}
19555 +    ${RELOCATING+PROVIDE (___sbss_end = .);}
19556 +  }${RW_BSS_REGION}"
19557 +  SBSS2=".sbss2        ${RELOCATING-0} : { *(.sbss2${RELOCATING+ .sbss2.* .gnu.linkonce.sb2.*}) }${RW_REGION}"
19558 +  SDATA="/* We want the small data sections together, so single-instruction offsets
19559 +     can access them all, and initialized data all before uninitialized, so
19560 +     we can shorten the on-disk segment size.  */
19561 +  .sdata        ${RELOCATING-0} :
19562 +  {
19563 +    ${RELOCATING+${SDATA_START_SYMBOLS}}
19564 +    ${CREATE_SHLIB+*(.sdata2 .sdata2.* .gnu.linkonce.s2.*)}
19565 +    *(.sdata${RELOCATING+ .sdata.* .gnu.linkonce.s.*})
19566 +  }${RW_REGION}"
19567 +  SDATA2=".sdata2       ${RELOCATING-0} : { *(.sdata2${RELOCATING+ .sdata2.* .gnu.linkonce.s2.*}) }${RW_REGION}"
19568 +  REL_SDATA=".rel.sdata    ${RELOCATING-0} : { *(.rel.sdata${RELOCATING+ .rel.sdata.* .rel.gnu.linkonce.s.*}) }${RO_REGION}
19569 +  .rela.sdata   ${RELOCATING-0} : { *(.rela.sdata${RELOCATING+ .rela.sdata.* .rela.gnu.linkonce.s.*}) }"
19570 +  REL_SBSS=".rel.sbss     ${RELOCATING-0} : { *(.rel.sbss${RELOCATING+ .rel.sbss.* .rel.gnu.linkonce.sb.*}) }${RO_REGION}
19571 +  .rela.sbss    ${RELOCATING-0} : { *(.rela.sbss${RELOCATING+ .rela.sbss.* .rela.gnu.linkonce.sb.*}) }${RO_REGION}"
19572 +  REL_SDATA2=".rel.sdata2   ${RELOCATING-0} : { *(.rel.sdata2${RELOCATING+ .rel.sdata2.* .rel.gnu.linkonce.s2.*}) }${RO_REGION}
19573 +  .rela.sdata2  ${RELOCATING-0} : { *(.rela.sdata2${RELOCATING+ .rela.sdata2.* .rela.gnu.linkonce.s2.*}) }${RO_REGION}"
19574 +  REL_SBSS2=".rel.sbss2    ${RELOCATING-0} : { *(.rel.sbss2${RELOCATING+ .rel.sbss2.* .rel.gnu.linkonce.sb2.*}) }${RO_REGION}
19575 +  .rela.sbss2   ${RELOCATING-0} : { *(.rela.sbss2${RELOCATING+ .rela.sbss2.* .rela.gnu.linkonce.sb2.*}) }${RO_REGION}"
19576 +else
19577 +  NO_SMALL_DATA=" "
19578 +fi
19579 +test -n "$SEPARATE_GOTPLT" && SEPARATE_GOTPLT=" "
19580 +CTOR=".ctors        ${CONSTRUCTING-0} :
19581 +  {
19582 +    ${CONSTRUCTING+${CTOR_START}}
19583 +    /* gcc uses crtbegin.o to find the start of
19584 +       the constructors, so we make sure it is
19585 +       first.  Because this is a wildcard, it
19586 +       doesn't matter if the user does not
19587 +       actually link against crtbegin.o; the
19588 +       linker won't look for a file to match a
19589 +       wildcard.  The wildcard also means that it
19590 +       doesn't matter which directory crtbegin.o
19591 +       is in.  */
19592 +
19593 +    KEEP (*crtbegin*.o(.ctors))
19594 +
19595 +    /* We don't want to include the .ctor section from
19596 +       from the crtend.o file until after the sorted ctors.
19597 +       The .ctor section from the crtend file contains the
19598 +       end of ctors marker and it must be last */
19599 +
19600 +    KEEP (*(EXCLUDE_FILE (*crtend*.o $OTHER_EXCLUDE_FILES) .ctors))
19601 +    KEEP (*(SORT(.ctors.*)))
19602 +    KEEP (*(.ctors))
19603 +    ${CONSTRUCTING+${CTOR_END}}
19604 +  }"
19605 +DTOR=".dtors        ${CONSTRUCTING-0} :
19606 +  {
19607 +    ${CONSTRUCTING+${DTOR_START}}
19608 +    KEEP (*crtbegin*.o(.dtors))
19609 +    KEEP (*(EXCLUDE_FILE (*crtend*.o $OTHER_EXCLUDE_FILES) .dtors))
19610 +    KEEP (*(SORT(.dtors.*)))
19611 +    KEEP (*(.dtors))
19612 +    ${CONSTRUCTING+${DTOR_END}}
19613 +  }"
19614 +STACK=".stack        ${RELOCATING-0}${RELOCATING+${STACK_ADDR}} :
19615 +  {
19616 +    ${RELOCATING+_stack = .;}
19617 +    *(.stack)
19618 +    ${RELOCATING+${STACK_SIZE+. = ${STACK_SIZE};}}
19619 +    ${RELOCATING+_estack = .;}
19620 +  }${RW_BSS_REGION}"
19621 +
19622 +# if this is for an embedded system, don't add SIZEOF_HEADERS.
19623 +if [ -z "$EMBEDDED" ]; then
19624 +   test -z "${TEXT_BASE_ADDRESS}" && TEXT_BASE_ADDRESS="${TEXT_START_ADDR} + SIZEOF_HEADERS"
19625 +else
19626 +   test -z "${TEXT_BASE_ADDRESS}" && TEXT_BASE_ADDRESS="${TEXT_START_ADDR}"
19627 +fi
19628 +
19629 +cat <<EOF
19630 +OUTPUT_FORMAT("${OUTPUT_FORMAT}", "${BIG_OUTPUT_FORMAT}",
19631 +             "${LITTLE_OUTPUT_FORMAT}")
19632 +OUTPUT_ARCH(${OUTPUT_ARCH})
19633 +ENTRY(${ENTRY})
19634 +
19635 +${RELOCATING+${LIB_SEARCH_DIRS}}
19636 +${RELOCATING+/* Do we need any of these for elf?
19637 +   __DYNAMIC = 0; ${STACKZERO+${STACKZERO}} ${SHLIB_PATH+${SHLIB_PATH}}  */}
19638 +${RELOCATING+${EXECUTABLE_SYMBOLS}}
19639 +${RELOCATING+${INPUT_FILES}}
19640 +${RELOCATING- /* For some reason, the Solaris linker makes bad executables
19641 +  if gld -r is used and the intermediate file has sections starting
19642 +  at non-zero addresses.  Could be a Solaris ld bug, could be a GNU ld
19643 +  bug.  But for now assigning the zero vmas works.  */}
19644 +
19645 +${RELOCATING+${MEMORY}}
19646 +
19647 +SECTIONS
19648 +{
19649 +  /* Read-only sections, merged into text segment: */
19650 +  ${CREATE_SHLIB-${CREATE_PIE-${RELOCATING+PROVIDE (__executable_start = ${TEXT_START_ADDR}); . = ${TEXT_BASE_ADDRESS};}}}
19651 +  ${PADDING}
19652 +  ${CREATE_SHLIB+${RELOCATING+. = ${SHLIB_TEXT_START_ADDR:-0} + SIZEOF_HEADERS;}}
19653 +  ${CREATE_PIE+${RELOCATING+. = ${SHLIB_TEXT_START_ADDR:-0} + SIZEOF_HEADERS;}}
19654 +  ${CREATE_SHLIB-${INTERP}}
19655 +  ${INITIAL_READONLY_SECTIONS}
19656 +  ${TEXT_DYNAMIC+${DYNAMIC}${RO_REGION}}
19657 +  .hash         ${RELOCATING-0} : { *(.hash) }${RO_REGION}
19658 +  .dynsym       ${RELOCATING-0} : { *(.dynsym) }${RO_REGION}
19659 +  .dynstr       ${RELOCATING-0} : { *(.dynstr) }${RO_REGION}
19660 +  .gnu.version  ${RELOCATING-0} : { *(.gnu.version) }${RO_REGION}
19661 +  .gnu.version_d ${RELOCATING-0}: { *(.gnu.version_d) }${RO_REGION}
19662 +  .gnu.version_r ${RELOCATING-0}: { *(.gnu.version_r) }${RO_REGION}
19663 +
19664 +EOF
19665 +if [ "x$COMBRELOC" = x ]; then
19666 +  COMBRELOCCAT=cat
19667 +else
19668 +  COMBRELOCCAT="cat > $COMBRELOC"
19669 +fi
19670 +eval $COMBRELOCCAT <<EOF
19671 +  .rel.init     ${RELOCATING-0} : { *(.rel.init) }${RO_REGION}
19672 +  .rela.init    ${RELOCATING-0} : { *(.rela.init) }${RO_REGION}
19673 +  .rel.text     ${RELOCATING-0} : { *(.rel.text${RELOCATING+ .rel.text.* .rel.gnu.linkonce.t.*}) }${RO_REGION}
19674 +  .rela.text    ${RELOCATING-0} : { *(.rela.text${RELOCATING+ .rela.text.* .rela.gnu.linkonce.t.*}) }${RO_REGION}
19675 +  .rel.fini     ${RELOCATING-0} : { *(.rel.fini) }${RO_REGION}
19676 +  .rela.fini    ${RELOCATING-0} : { *(.rela.fini) }${RO_REGION}
19677 +  .rel.rodata   ${RELOCATING-0} : { *(.rel.rodata${RELOCATING+ .rel.rodata.* .rel.gnu.linkonce.r.*}) }${RO_REGION}
19678 +  .rela.rodata  ${RELOCATING-0} : { *(.rela.rodata${RELOCATING+ .rela.rodata.* .rela.gnu.linkonce.r.*}) }${RO_REGION}
19679 +  ${OTHER_READONLY_RELOC_SECTIONS}
19680 +  .rel.data.rel.ro ${RELOCATING-0} : { *(.rel.data.rel.ro${RELOCATING+*}) }${RO_REGION}
19681 +  .rela.data.rel.ro ${RELOCATING-0} : { *(.rel.data.rel.ro${RELOCATING+*}) }${RO_REGION}
19682 +  .rel.data     ${RELOCATING-0} : { *(.rel.data${RELOCATING+ .rel.data.* .rel.gnu.linkonce.d.*}) }${RO_REGION}
19683 +  .rela.data    ${RELOCATING-0} : { *(.rela.data${RELOCATING+ .rela.data.* .rela.gnu.linkonce.d.*}) }${RO_REGION}
19684 +  .rel.tdata   ${RELOCATING-0} : { *(.rel.tdata${RELOCATING+ .rel.tdata.* .rel.gnu.linkonce.td.*}) }${RO_REGION}
19685 +  .rela.tdata  ${RELOCATING-0} : { *(.rela.tdata${RELOCATING+ .rela.tdata.* .rela.gnu.linkonce.td.*}) }${RO_REGION}
19686 +  .rel.tbss    ${RELOCATING-0} : { *(.rel.tbss${RELOCATING+ .rel.tbss.* .rel.gnu.linkonce.tb.*}) }${RO_REGION}
19687 +  .rela.tbss   ${RELOCATING-0} : { *(.rela.tbss${RELOCATING+ .rela.tbss.* .rela.gnu.linkonce.tb.*}) }${RO_REGION}
19688 +  .rel.ctors    ${RELOCATING-0} : { *(.rel.ctors) }${RO_REGION}
19689 +  .rela.ctors   ${RELOCATING-0} : { *(.rela.ctors) }${RO_REGION}
19690 +  .rel.dtors    ${RELOCATING-0} : { *(.rel.dtors) }${RO_REGION}
19691 +  .rela.dtors   ${RELOCATING-0} : { *(.rela.dtors) }${RO_REGION}
19692 +  .rel.got      ${RELOCATING-0} : { *(.rel.got) }${RO_REGION}
19693 +  .rela.got     ${RELOCATING-0} : { *(.rela.got) }${RO_REGION}
19694 +  ${OTHER_GOT_RELOC_SECTIONS}
19695 +  ${REL_SDATA}
19696 +  ${REL_SBSS}
19697 +  ${REL_SDATA2}
19698 +  ${REL_SBSS2}
19699 +  .rel.bss      ${RELOCATING-0} : { *(.rel.bss${RELOCATING+ .rel.bss.* .rel.gnu.linkonce.b.*}) }${RO_REGION}
19700 +  .rela.bss     ${RELOCATING-0} : { *(.rela.bss${RELOCATING+ .rela.bss.* .rela.gnu.linkonce.b.*}) }${RO_REGION}
19701 +EOF
19702 +if [ -n "$COMBRELOC" ]; then
19703 +cat <<EOF
19704 +  .rel.dyn      ${RELOCATING-0} :
19705 +    {
19706 +EOF
19707 +sed -e '/^[    ]*[{}][         ]*$/d;/:[       ]*$/d;/\.rela\./d;s/^.*: { *\(.*\)}$/      \1/' $COMBRELOC
19708 +cat <<EOF
19709 +    }${RO_REGION}
19710 +  .rela.dyn     ${RELOCATING-0} :
19711 +    {
19712 +EOF
19713 +sed -e '/^[    ]*[{}][         ]*$/d;/:[       ]*$/d;/\.rel\./d;s/^.*: { *\(.*\)}/      \1/' $COMBRELOC
19714 +cat <<EOF
19715 +    }${RO_REGION}
19716 +EOF
19717 +fi
19718 +cat <<EOF
19719 +  .rel.plt      ${RELOCATING-0} : { *(.rel.plt) }${RO_REGION}
19720 +  .rela.plt     ${RELOCATING-0} : { *(.rela.plt) }${RO_REGION}
19721 +  ${OTHER_PLT_RELOC_SECTIONS}
19722 +
19723 +  .init         ${RELOCATING-0} :
19724 +  {
19725 +    ${RELOCATING+${INIT_START}}
19726 +    KEEP (*(.init))
19727 +    ${RELOCATING+${INIT_END}}
19728 +  }${RO_REGION} =${NOP-0}
19729 +
19730 +  ${DATA_PLT-${BSS_PLT-${PLT}${RO_REGION}}}
19731 +  .text         ${RELOCATING-0} :
19732 +  {
19733 +    ${RELOCATING+${TEXT_START_SYMBOLS}}
19734 +    *(.text .stub${RELOCATING+ .text.* .gnu.linkonce.t.*})
19735 +    KEEP (*(.text.*personality*))
19736 +    /* .gnu.warning sections are handled specially by elf32.em.  */
19737 +    *(.gnu.warning)
19738 +    ${RELOCATING+${OTHER_TEXT_SECTIONS}}
19739 +  }${RO_REGION} =${NOP-0}
19740 +  .fini         ${RELOCATING-0} :
19741 +  {
19742 +    ${RELOCATING+${FINI_START}}
19743 +    KEEP (*(.fini))
19744 +    ${RELOCATING+${FINI_END}}
19745 +  }${RO_REGION} =${NOP-0}
19746 +  ${RELOCATING+PROVIDE (__etext = .);}
19747 +  ${RELOCATING+PROVIDE (_etext = .);}
19748 +  ${RELOCATING+PROVIDE (etext = .);}
19749 +  ${WRITABLE_RODATA-${RODATA}${RO_REGION}}
19750 +  .rodata1      ${RELOCATING-0} : { *(.rodata1) }${RO_REGION}
19751 +  ${CREATE_SHLIB-${SDATA2}}
19752 +  ${CREATE_SHLIB-${SBSS2}}
19753 +  ${OTHER_READONLY_SECTIONS}
19754 +  .eh_frame_hdr : { *(.eh_frame_hdr) }${RO_REGION}
19755 +  .eh_frame     ${RELOCATING-0} : ONLY_IF_RO { KEEP (*(.eh_frame)) }${RO_REGION}
19756 +  .gcc_except_table ${RELOCATING-0} : ONLY_IF_RO { KEEP (*(.gcc_except_table)) *(.gcc_except_table.*) }${RO_REGION}
19757 +
19758 +  ${RELOCATING+${DALIGN}}
19759 +  ${RELOCATING+PROVIDE (_data = ORIGIN(${RW_VMA_REGION}));}
19760 +  . = ORIGIN(${RW_VMA_REGION});
19761 +  /* Exception handling  */
19762 +  .eh_frame     ${RELOCATING-0} : ONLY_IF_RW { KEEP (*(.eh_frame)) }${RW_REGION}
19763 +  .gcc_except_table ${RELOCATING-0} : ONLY_IF_RW { KEEP (*(.gcc_except_table)) *(.gcc_except_table.*) }${RW_REGION}
19764 +
19765 +  /* Thread Local Storage sections  */
19766 +  .tdata       ${RELOCATING-0} : { *(.tdata${RELOCATING+ .tdata.* .gnu.linkonce.td.*}) }${RW_REGION}
19767 +  .tbss                ${RELOCATING-0} : { *(.tbss${RELOCATING+ .tbss.* .gnu.linkonce.tb.*})${RELOCATING+ *(.tcommon)} }${RW_BSS_REGION}
19768 +
19769 +  /* Ensure the __preinit_array_start label is properly aligned.  We
19770 +     could instead move the label definition inside the section, but
19771 +     the linker would then create the section even if it turns out to
19772 +     be empty, which isn't pretty.  */
19773 +  ${RELOCATING+${CREATE_SHLIB-PROVIDE (__preinit_array_start = ALIGN(${ALIGNMENT}));}}
19774 +  .preinit_array   ${RELOCATING-0} : { KEEP (*(.preinit_array)) }${RW_REGION}
19775 +  ${RELOCATING+${CREATE_SHLIB-PROVIDE (__preinit_array_end = .);}}
19776 +
19777 +  ${RELOCATING+${CREATE_SHLIB-PROVIDE (__init_array_start = .);}}
19778 +  .init_array   ${RELOCATING-0} : { KEEP (*(.init_array)) }${RW_REGION}
19779 +  ${RELOCATING+${CREATE_SHLIB-PROVIDE (__init_array_end = .);}}
19780 +
19781 +  ${RELOCATING+${CREATE_SHLIB-PROVIDE (__fini_array_start = .);}}
19782 +  .fini_array   ${RELOCATING-0} : { KEEP (*(.fini_array)) }${RW_REGION}
19783 +  ${RELOCATING+${CREATE_SHLIB-PROVIDE (__fini_array_end = .);}}
19784 +
19785 +  ${SMALL_DATA_CTOR-${RELOCATING+${CTOR}${RW_REGION}}}
19786 +  ${SMALL_DATA_DTOR-${RELOCATING+${DTOR}${RW_REGION}}}
19787 +  .jcr          ${RELOCATING-0} : { KEEP (*(.jcr)) }${RW_REGION}
19788 +
19789 +  ${RELOCATING+${DATARELRO}}
19790 +  ${OTHER_RELRO_SECTIONS}
19791 +  ${TEXT_DYNAMIC-${DYNAMIC}${RW_REGION}}
19792 +  ${NO_SMALL_DATA+${RELRO_NOW+${GOT}${RW_REGION}}}
19793 +  ${NO_SMALL_DATA+${RELRO_NOW-${SEPARATE_GOTPLT+${GOT}${RW_REGION}}}}
19794 +  ${NO_SMALL_DATA+${RELRO_NOW-${SEPARATE_GOTPLT+${GOTPLT}${RW_REGION}}}}
19795 +  ${RELOCATING+${DATA_SEGMENT_RELRO_END}}
19796 +  ${NO_SMALL_DATA+${RELRO_NOW-${SEPARATE_GOTPLT-${GOT}${RW_REGION}}}}
19797 +
19798 +  ${DATA_PLT+${PLT_BEFORE_GOT-${PLT}${RW_REGION}}}
19799 +
19800 +  .data         ${RELOCATING-0} :
19801 +  {
19802 +    ${RELOCATING+${DATA_START_SYMBOLS}}
19803 +    *(.data${RELOCATING+ .data.* .gnu.linkonce.d.*})
19804 +    KEEP (*(.gnu.linkonce.d.*personality*))
19805 +    ${CONSTRUCTING+SORT(CONSTRUCTORS)}
19806 +  }${RW_REGION}
19807 +  .data1        ${RELOCATING-0} : { *(.data1) }${RW_REGION}
19808 +  ${WRITABLE_RODATA+${RODATA}${RW_REGION}}
19809 +  ${OTHER_READWRITE_SECTIONS}
19810 +  ${SMALL_DATA_CTOR+${RELOCATING+${CTOR}${RW_REGION}}}
19811 +  ${SMALL_DATA_DTOR+${RELOCATING+${DTOR}${RW_REGION}}}
19812 +  ${DATA_PLT+${PLT_BEFORE_GOT+${PLT}${RW_REGION}}}
19813 +  ${RELOCATING+${OTHER_GOT_SYMBOLS}}
19814 +  ${NO_SMALL_DATA-${GOT}${RW_REGION}}
19815 +  ${OTHER_GOT_SECTIONS}
19816 +  ${SDATA}
19817 +  ${OTHER_SDATA_SECTIONS}
19818 +  ${RELOCATING+${BALIGN}}
19819 +  ${RELOCATING+_edata = .;}
19820 +  ${RELOCATING+PROVIDE (edata = .);}
19821 +  ${RELOCATING+__bss_start = .;}
19822 +  ${RELOCATING+${OTHER_BSS_SYMBOLS}}
19823 +  ${SBSS}
19824 +  ${BSS_PLT+${PLT}${RW_REGION}}
19825 +  .bss          ${RELOCATING-0} :
19826 +  {
19827 +   *(.dynbss)
19828 +   *(.bss${RELOCATING+ .bss.* .gnu.linkonce.b.*})
19829 +   *(COMMON)
19830 +   /* Align here to ensure that the .bss section occupies space up to
19831 +      _end.  Align after .bss to ensure correct alignment even if the
19832 +      .bss section disappears because there are no input sections.  */
19833 +   ${RELOCATING+. = ALIGN(${BSS_ALIGNMENT});}
19834 +  }${RW_BSS_REGION}
19835 +  ${OTHER_BSS_SECTIONS}
19836 +  ${RELOCATING+. = ALIGN(${BSS_ALIGNMENT});}
19837 +  ${RELOCATING+_end = .;}
19838 +  ${RELOCATING+${OTHER_BSS_END_SYMBOLS}}
19839 +  ${RELOCATING+PROVIDE (end = .);}
19840 +  ${RELOCATING+${DATA_SEGMENT_END}}
19841 +
19842 +  /* Stabs debugging sections.  */
19843 +  .stab          0 : { *(.stab) }
19844 +  .stabstr       0 : { *(.stabstr) }
19845 +  .stab.excl     0 : { *(.stab.excl) }
19846 +  .stab.exclstr  0 : { *(.stab.exclstr) }
19847 +  .stab.index    0 : { *(.stab.index) }
19848 +  .stab.indexstr 0 : { *(.stab.indexstr) }
19849 +
19850 +  .comment       0 : { *(.comment) }
19851 +
19852 +  /* DWARF debug sections.
19853 +     Symbols in the DWARF debugging sections are relative to the beginning
19854 +     of the section so we begin them at 0.  */
19855 +
19856 +  /* DWARF 1 */
19857 +  .debug          0 : { *(.debug) }
19858 +  .line           0 : { *(.line) }
19859 +
19860 +  /* GNU DWARF 1 extensions */
19861 +  .debug_srcinfo  0 : { *(.debug_srcinfo) }
19862 +  .debug_sfnames  0 : { *(.debug_sfnames) }
19863 +
19864 +  /* DWARF 1.1 and DWARF 2 */
19865 +  .debug_aranges  0 : { *(.debug_aranges) }
19866 +  .debug_pubnames 0 : { *(.debug_pubnames) }
19867 +
19868 +  /* DWARF 2 */
19869 +  .debug_info     0 : { *(.debug_info .gnu.linkonce.wi.*) }
19870 +  .debug_abbrev   0 : { *(.debug_abbrev) }
19871 +  .debug_line     0 : { *(.debug_line) }
19872 +  .debug_frame    0 : { *(.debug_frame) }
19873 +  .debug_str      0 : { *(.debug_str) }
19874 +  .debug_loc      0 : { *(.debug_loc) }
19875 +  .debug_macinfo  0 : { *(.debug_macinfo) }
19876 +
19877 +  /* SGI/MIPS DWARF 2 extensions */
19878 +  .debug_weaknames 0 : { *(.debug_weaknames) }
19879 +  .debug_funcnames 0 : { *(.debug_funcnames) }
19880 +  .debug_typenames 0 : { *(.debug_typenames) }
19881 +  .debug_varnames  0 : { *(.debug_varnames) }
19882 +
19883 +  ${STACK_ADDR+${STACK}}
19884 +  ${OTHER_SECTIONS}
19885 +  ${RELOCATING+${OTHER_END_SYMBOLS}}
19886 +  ${RELOCATING+${STACKNOTE}}
19887 +}
19888 +EOF
19889 --- /dev/null
19890 +++ b/ld/testsuite/ld-avr32/avr32.exp
19891 @@ -0,0 +1,25 @@
19892 +# Expect script for AVR32 ELF linker tests.
19893 +#   Copyright 2004-2006 Atmel Corporation.
19894 +#
19895 +# This file is free software; you can redistribute it and/or modify
19896 +# it under the terms of the GNU General Public License as published by
19897 +# the Free Software Foundation; either version 2 of the License, or
19898 +# (at your option) any later version.
19899 +#
19900 +# This program is distributed in the hope that it will be useful,
19901 +# but WITHOUT ANY WARRANTY; without even the implied warranty of
19902 +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
19903 +# GNU General Public License for more details.
19904 +#
19905 +# You should have received a copy of the GNU General Public License
19906 +# along with this program; if not, write to the Free Software
19907 +# Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
19908 +#
19909 +# Written by Haavard Skinnemoen (hskinnemoen@atmel.com)
19910 +#
19911 +
19912 +if ![istarget avr32-*-*] {
19913 +    return
19914 +}
19915 +
19916 +run_dump_test "pcrel"
19917 --- /dev/null
19918 +++ b/ld/testsuite/ld-avr32/pcrel.d
19919 @@ -0,0 +1,74 @@
19920 +#name: AVR32 ELF PC-relative external relocs
19921 +#source: symbols.s
19922 +#source: ../../../gas/testsuite/gas/avr32/pcrel.s
19923 +#ld: -T $srcdir/$subdir/pcrel.ld
19924 +#objdump: -d
19925 +
19926 +.*:     file format elf.*avr32.*
19927 +
19928 +Disassembly of section .text:
19929 +
19930 +a0000000 <_start>:
19931 +a0000000:      d7 03           nop
19932 +a0000002:      d7 03           nop
19933 +
19934 +a0000004 <test_rjmp>:
19935 +a0000004:      d7 03           nop
19936 +a0000006:      c0 28           rjmp a000000a <test_rjmp\+0x6>
19937 +a0000008:      d7 03           nop
19938 +a000000a:      e0 8f 01 fb     bral a0000400 <extsym10>
19939 +
19940 +a000000e <test_rcall>:
19941 +a000000e:      d7 03           nop
19942 +a0000010 <test_rcall2>:
19943 +a0000010:      c0 2c           rcall a0000014 <test_rcall2\+0x4>
19944 +a0000012:      d7 03           nop
19945 +a0000014:      ee b0 ff f6     rcall a0200000 <extsym21>
19946 +
19947 +a0000018 <test_branch>:
19948 +a0000018:      c0 31           brne a000001e <test_branch\+0x6>
19949 +a000001a:      fe 9f ff ff     bral a0000018 <test_branch>
19950 +a000001e:      ee 90 ff f1     breq a0200000 <extsym21>
19951 +
19952 +a0000022 <test_lddpc>:
19953 +a0000022:      48 30           lddpc r0,a000002c <sym1>
19954 +a0000024:      48 20           lddpc r0,a000002c <sym1>
19955 +a0000026:      fe f0 7f da     ld.w r0,pc\[32730\]
19956 +       ...
19957 +
19958 +a000002c <sym1>:
19959 +a000002c:      d7 03           nop
19960 +a000002e:      d7 03           nop
19961 +
19962 +a0000030 <test_local>:
19963 +a0000030:      48 20           lddpc r0,a0000038 <test_local\+0x8>
19964 +a0000032:      48 30           lddpc r0,a000003c <test_local\+0xc>
19965 +a0000034:      48 20           lddpc r0,a000003c <test_local\+0xc>
19966 +a0000036:      00 00           add r0,r0
19967 +a0000038:      d7 03           nop
19968 +a000003a:      d7 03           nop
19969 +a000003c:      d7 03           nop
19970 +a000003e:      d7 03           nop
19971 +
19972 +Disassembly of section \.text\.init:
19973 +a0000040 <test_inter_section>:
19974 +a0000040:      fe b0 ff e7     rcall a000000e <test_rcall>
19975 +a0000044:      d7 03           nop
19976 +a0000046:      fe b0 ff e4     rcall a000000e <test_rcall>
19977 +a000004a:      fe b0 ff e3     rcall a0000010 <test_rcall2>
19978 +a000004e:      d7 03           nop
19979 +a0000050:      fe b0 ff e0     rcall a0000010 <test_rcall2>
19980 +
19981 +Disassembly of section \.text\.pcrel10:
19982 +
19983 +a0000400 <extsym10>:
19984 +a0000400:      d7 03           nop
19985 +
19986 +Disassembly of section \.text\.pcrel16:
19987 +
19988 +a0008000 <extsym16>:
19989 +a0008000:      d7 03           nop
19990 +
19991 +Disassembly of section \.text\.pcrel21:
19992 +a0200000 <extsym21>:
19993 +a0200000:      d7 03           nop
19994 --- /dev/null
19995 +++ b/ld/testsuite/ld-avr32/pcrel.ld
19996 @@ -0,0 +1,23 @@
19997 +ENTRY(_start)
19998 +SECTIONS
19999 +{
20000 +       .text 0xa0000000:
20001 +       {
20002 +               *(.text)
20003 +       }
20004 +
20005 +       .text.pcrel10 0xa0000400:
20006 +       {
20007 +               *(.text.pcrel10)
20008 +       }
20009 +
20010 +       .text.pcrel16 0xa0008000:
20011 +       {
20012 +               *(.text.pcrel16)
20013 +       }
20014 +
20015 +       .text.pcrel21 0xa0200000:
20016 +       {
20017 +               *(.text.pcrel21)
20018 +       }
20019 +}
20020 --- /dev/null
20021 +++ b/ld/testsuite/ld-avr32/symbols.s
20022 @@ -0,0 +1,20 @@
20023 +       .text
20024 +       .global _start
20025 +_start:
20026 +       nop
20027 +       nop
20028 +
20029 +       .section .text.pcrel10,"ax"
20030 +       .global extsym10
20031 +extsym10:
20032 +       nop
20033 +
20034 +       .section .text.pcrel16,"ax"
20035 +       .global extsym16
20036 +extsym16:
20037 +       nop
20038 +
20039 +       .section .text.pcrel21,"ax"
20040 +       .global extsym21
20041 +extsym21:
20042 +       nop
20043 --- /dev/null
20044 +++ b/opcodes/avr32-asm.c
20045 @@ -0,0 +1,264 @@
20046 +/* Assembler interface for AVR32.
20047 +   Copyright 2005,2006,2007,2008,2009 Atmel Corporation.
20048 +
20049 +   Written by Haavard Skinnemoen, Atmel Norway, <hskinnemoen@atmel.com>
20050 +
20051 +   This file is part of libopcodes.
20052 +
20053 +   This program is free software; you can redistribute it and/or
20054 +   modify it under the terms of the GNU General Public License as
20055 +   published by the Free Software Foundation; either version 2 of the
20056 +   License, or (at your option) any later version.
20057 +
20058 +   This program is distributed in the hope that it will be useful, but
20059 +   WITHOUT ANY WARRANTY; without even the implied warranty of
20060 +   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
20061 +   General Public License for more details.
20062 +
20063 +   You should have received a copy of the GNU General Public License
20064 +   along with this program; if not, write to the Free Software
20065 +   Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA
20066 +   02111-1307, USA.  */
20067 +
20068 +#include <string.h>
20069 +
20070 +#include "avr32-opc.h"
20071 +#include "avr32-asm.h"
20072 +
20073 +/* Structure for a register hash table entry.  */
20074 +struct reg_entry
20075 +{
20076 +  const char   *name;
20077 +  int          number;
20078 +};
20079 +
20080 +/* Integer Registers.  */
20081 +static const struct reg_entry reg_table[] =
20082 +  {
20083 +    /* Primary names (used by the disassembler) */
20084 +    { "r0",   0 }, { "r1",   1 }, { "r2",   2 }, { "r3",   3 },
20085 +    { "r4",   4 }, { "r5",   5 }, { "r6",   6 }, { "r7",   7 },
20086 +    { "r8",   8 }, { "r9",   9 }, { "r10", 10 }, { "r11", 11 },
20087 +    { "r12", 12 }, { "sp",  13 }, { "lr",  14 }, { "pc",  15 },
20088 +    /* Alternatives to sp, lr and pc.  */
20089 +    { "r13", 13 }, { "r14", 14 }, { "r15", 15 },
20090 +  };
20091 +#define AVR32_NR_INTREGS (sizeof(reg_table)/sizeof(reg_table[0]))
20092 +
20093 +/* Coprocessor Registers.  */
20094 +static const struct reg_entry cr_table[] =
20095 +  {
20096 +    { "cr0",   0 }, { "cr1",   1 }, { "cr2",   2 }, { "cr3",   3 },
20097 +    { "cr4",   4 }, { "cr5",   5 }, { "cr6",   6 }, { "cr7",   7 },
20098 +    { "cr8",   8 }, { "cr9",   9 }, { "cr10", 10 }, { "cr11", 11 },
20099 +    { "cr12", 12 }, { "cr13", 13 }, { "cr14", 14 }, { "cr15", 15 },
20100 +  };
20101 +#define AVR32_NR_CPREGS (sizeof(cr_table)/sizeof(cr_table[0]))
20102 +
20103 +/* Floating-point Registers.  */
20104 +static const struct reg_entry fr_table[] =
20105 +  {
20106 +    { "fr0",   0 }, { "fr1",   1 }, { "fr2",   2 }, { "fr3",   3 },
20107 +    { "fr4",   4 }, { "fr5",   5 }, { "fr6",   6 }, { "fr7",   7 },
20108 +    { "fr8",   8 }, { "fr9",   9 }, { "fr10", 10 }, { "fr11", 11 },
20109 +    { "fr12", 12 }, { "fr13", 13 }, { "fr14", 14 }, { "fr15", 15 },
20110 +  };
20111 +#define AVR32_NR_FPREGS (sizeof(fr_table)/sizeof(fr_table[0]))
20112 +
20113 +/* PiCo Registers.  */
20114 +static const struct reg_entry pico_table[] =
20115 +  {
20116 +    { "inpix2",    0 }, { "inpix1",    1 }, { "inpix0",    2 },
20117 +    { "outpix2",   3 }, { "outpix1",   4 }, { "outpix0",   5 },
20118 +    { "coeff0_a",  6 }, { "coeff0_b",  7 }, { "coeff1_a",  8 },
20119 +    { "coeff1_b",  9 }, { "coeff2_a", 10 }, { "coeff2_b", 11 },
20120 +    { "vmu0_out", 12 }, { "vmu1_out", 13 }, { "vmu2_out", 14 },
20121 +    { "config",   15 },
20122 +  };
20123 +#define AVR32_NR_PICOREGS (sizeof(pico_table)/sizeof(pico_table[0]))
20124 +
20125 +int
20126 +avr32_parse_intreg(const char *str)
20127 +{
20128 +  unsigned int i;
20129 +
20130 +  for (i = 0; i < AVR32_NR_INTREGS; i++)
20131 +    {
20132 +      if (strcasecmp(reg_table[i].name, str) == 0)
20133 +       return reg_table[i].number;
20134 +    }
20135 +
20136 +  return -1;
20137 +}
20138 +
20139 +int
20140 +avr32_parse_cpreg(const char *str)
20141 +{
20142 +  unsigned int i;
20143 +
20144 +  for (i = 0; i < AVR32_NR_CPREGS; i++)
20145 +    {
20146 +      if (strcasecmp(cr_table[i].name, str) == 0)
20147 +       return cr_table[i].number;
20148 +    }
20149 +
20150 +  return -1;
20151 +}
20152 +
20153 +int avr32_parse_fpreg(const char *str)
20154 +{
20155 +  unsigned int i;
20156 +
20157 +  for (i = 0; i < AVR32_NR_FPREGS; i++)
20158 +    {
20159 +      if (strcasecmp(fr_table[i].name, str) == 0)
20160 +       return fr_table[i].number;
20161 +    }
20162 +
20163 +  return -1;
20164 +}
20165 +
20166 +int avr32_parse_picoreg(const char *str)
20167 +{
20168 +  unsigned int i;
20169 +
20170 +  for (i = 0; i < AVR32_NR_PICOREGS; i++)
20171 +    {
20172 +      if (strcasecmp(pico_table[i].name, str) == 0)
20173 +       return pico_table[i].number;
20174 +    }
20175 +
20176 +  return -1;
20177 +}
20178 +
20179 +static unsigned long
20180 +parse_reglist(char *str, char **endptr, int (*parse_reg)(const char *))
20181 +{
20182 +  int reg_from, reg_to;
20183 +  unsigned long result = 0;
20184 +  char *p1, *p2, c;
20185 +
20186 +  while (*str)
20187 +    {
20188 +      for (p1 = str; *p1; p1++)
20189 +       if (*p1 == ',' || *p1 == '-')
20190 +         break;
20191 +
20192 +      c = *p1, *p1 = 0;
20193 +      reg_from = parse_reg(str);
20194 +      *p1 = c;
20195 +
20196 +      if (reg_from < 0)
20197 +       break;
20198 +
20199 +      if (*p1 == '-')
20200 +       {
20201 +         for (p2 = ++p1; *p2; p2++)
20202 +           if (*p2 == ',')
20203 +             break;
20204 +
20205 +         c = *p2, *p2 = 0;
20206 +         /* printf("going to parse reg_to from `%s'\n", p1); */
20207 +         reg_to = parse_reg(p1);
20208 +         *p2 = c;
20209 +
20210 +         if (reg_to < 0)
20211 +           break;
20212 +
20213 +         while (reg_from <= reg_to)
20214 +           result |= (1 << reg_from++);
20215 +         p1 = p2;
20216 +       }
20217 +      else
20218 +       result |= (1 << reg_from);
20219 +
20220 +      str = p1;
20221 +      if (*str) ++str;
20222 +    }
20223 +
20224 +  if (endptr)
20225 +    *endptr = str;
20226 +
20227 +  return result;
20228 +}
20229 +
20230 +unsigned long
20231 +avr32_parse_reglist(char *str, char **endptr)
20232 +{
20233 +  return parse_reglist(str, endptr, avr32_parse_intreg);
20234 +}
20235 +
20236 +unsigned long
20237 +avr32_parse_cpreglist(char *str, char **endptr)
20238 +{
20239 +  return parse_reglist(str, endptr, avr32_parse_cpreg);
20240 +}
20241 +
20242 +unsigned long
20243 +avr32_parse_pico_reglist(char *str, char **endptr)
20244 +{
20245 +  return parse_reglist(str, endptr, avr32_parse_picoreg);
20246 +}
20247 +
20248 +int
20249 +avr32_make_regmask8(unsigned long regmask16, unsigned long *regmask8)
20250 +{
20251 +  unsigned long result = 0;
20252 +
20253 +  /* printf("convert regmask16 0x%04lx\n", regmask16); */
20254 +
20255 +  if (regmask16 & 0xf)
20256 +    {
20257 +      if ((regmask16 & 0xf) == 0xf)
20258 +       result |= 1 << 0;
20259 +      else
20260 +       return -1;
20261 +    }
20262 +  if (regmask16 & 0xf0)
20263 +    {
20264 +      if ((regmask16 & 0xf0) == 0xf0)
20265 +       result |= 1 << 1;
20266 +      else
20267 +       return -1;
20268 +    }
20269 +  if (regmask16 & 0x300)
20270 +    {
20271 +      if ((regmask16 & 0x300) == 0x300)
20272 +       result |= 1 << 2;
20273 +      else
20274 +       return -1;
20275 +    }
20276 +  if (regmask16 & (1 << 13))
20277 +    return -1;
20278 +
20279 +  if (regmask16 & (1 << 10))
20280 +    result |= 1 << 3;
20281 +  if (regmask16 & (1 << 11))
20282 +    result |= 1 << 4;
20283 +  if (regmask16 & (1 << 12))
20284 +    result |= 1 << 5;
20285 +  if (regmask16 & (1 << 14))
20286 +    result |= 1 << 6;
20287 +  if (regmask16 & (1 << 15))
20288 +    result |= 1 << 7;
20289 +
20290 +  *regmask8 = result;
20291 +
20292 +  return 0;
20293 +}
20294 +
20295 +#if 0
20296 +struct reg_map
20297 +{
20298 +  const struct reg_entry       *names;
20299 +  int                          nr_regs;
20300 +  struct hash_control          *htab;
20301 +  const char                   *errmsg;
20302 +};
20303 +
20304 +struct reg_map all_reg_maps[] =
20305 +  {
20306 +    { reg_table, AVR32_NR_INTREGS, NULL, N_("integral register expected") },
20307 +    { cr_table,  AVR32_NR_CPREGS,  NULL, N_("coprocessor register expected") },
20308 +  };
20309 +#endif
20310 --- /dev/null
20311 +++ b/opcodes/avr32-asm.h
20312 @@ -0,0 +1,42 @@
20313 +/* Assembler interface for AVR32.
20314 +   Copyright 2005,2006,2007,2008,2009 Atmel Corporation.
20315 +
20316 +   Written by Haavard Skinnemoen, Atmel Norway, <hskinnemoen@atmel.com>
20317 +
20318 +   This file is part of libopcodes.
20319 +
20320 +   This program is free software; you can redistribute it and/or
20321 +   modify it under the terms of the GNU General Public License as
20322 +   published by the Free Software Foundation; either version 2 of the
20323 +   License, or (at your option) any later version.
20324 +
20325 +   This program is distributed in the hope that it will be useful, but
20326 +   WITHOUT ANY WARRANTY; without even the implied warranty of
20327 +   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
20328 +   General Public License for more details.
20329 +
20330 +   You should have received a copy of the GNU General Public License
20331 +   along with this program; if not, write to the Free Software
20332 +   Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA
20333 +   02111-1307, USA.  */
20334 +#ifndef __OPCODES_AVR32_ASM_H
20335 +#define __OPCODES_AVR32_ASM_H
20336 +
20337 +extern int
20338 +avr32_parse_intreg(const char *str);
20339 +extern int
20340 +avr32_parse_cpreg(const char *str);
20341 +extern int
20342 +avr32_parse_fpreg(const char *str);
20343 +extern int
20344 +avr32_parse_picoreg(const char *str);
20345 +extern unsigned long
20346 +avr32_parse_reglist(char *str, char **endptr);
20347 +extern unsigned long
20348 +avr32_parse_cpreglist(char *str, char **endptr);
20349 +extern unsigned long
20350 +avr32_parse_pico_reglist(char *str, char **endptr);
20351 +extern int
20352 +avr32_make_regmask8(unsigned long regmask16, unsigned long *regmask8);
20353 +
20354 +#endif /* __OPCODES_AVR32_ASM_H */
20355 --- /dev/null
20356 +++ b/opcodes/avr32-dis.c
20357 @@ -0,0 +1,891 @@
20358 +/* Print AVR32 instructions for GDB and objdump.
20359 +   Copyright 2005,2006,2007,2008,2009 Atmel Corporation.
20360 +
20361 +   Written by Haavard Skinnemoen, Atmel Norway, <hskinnemoen@atmel.com>
20362 +
20363 +   This file is part of libopcodes.
20364 +
20365 +   This program is free software; you can redistribute it and/or
20366 +   modify it under the terms of the GNU General Public License as
20367 +   published by the Free Software Foundation; either version 2 of the
20368 +   License, or (at your option) any later version.
20369 +
20370 +   This program is distributed in the hope that it will be useful, but
20371 +   WITHOUT ANY WARRANTY; without even the implied warranty of
20372 +   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
20373 +   General Public License for more details.
20374 +
20375 +   You should have received a copy of the GNU General Public License
20376 +   along with this program; if not, write to the Free Software
20377 +   Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA
20378 +   02111-1307, USA.  */
20379 +
20380 +#include "sysdep.h"
20381 +#include "dis-asm.h"
20382 +#include "avr32-opc.h"
20383 +#include "opintl.h"
20384 +#include "safe-ctype.h"
20385 +
20386 +/* TODO: Share this with -asm */
20387 +
20388 +/* Structure for a register hash table entry.  */
20389 +struct reg_entry
20390 +{
20391 +  const char   *name;
20392 +  int          number;
20393 +};
20394 +
20395 +#ifndef strneq
20396 +#define strneq(a,b,n)  (strncmp ((a), (b), (n)) == 0)
20397 +#endif
20398 +
20399 +
20400 +static const struct reg_entry reg_table[] =
20401 +  {
20402 +    /* Primary names (used by the disassembler) */
20403 +    { "r0",   0 }, { "r1",   1 }, { "r2",   2 }, { "r3",   3 },
20404 +    { "r4",   4 }, { "r5",   5 }, { "r6",   6 }, { "r7",   7 },
20405 +    { "r8",   8 }, { "r9",   9 }, { "r10", 10 }, { "r11", 11 },
20406 +    { "r12", 12 }, { "sp",  13 }, { "lr",  14 }, { "pc",  15 },
20407 +    /* Alternatives to sp, lr and pc.  */
20408 +    { "r13", 13 }, { "r14", 14 }, { "r15", 15 },
20409 +  };
20410 +#define AVR32_NR_INTREGS (sizeof(reg_table)/sizeof(reg_table[0]))
20411 +
20412 +/* Coprocessor Registers.  */
20413 +static const struct reg_entry cr_table[] =
20414 +  {
20415 +    { "cr0",   0 }, { "cr1",   1 }, { "cr2",   2 }, { "cr3",   3 },
20416 +    { "cr4",   4 }, { "cr5",   5 }, { "cr6",   6 }, { "cr7",   7 },
20417 +    { "cr8",   8 }, { "cr9",   9 }, { "cr10", 10 }, { "cr11", 11 },
20418 +    { "cr12", 12 }, { "cr13", 13 }, { "cr14", 14 }, { "cr15", 15 },
20419 +  };
20420 +#define AVR32_NR_CPREGS (sizeof(cr_table)/sizeof(cr_table[0]))
20421 +
20422 +static const char bparts[4] = { 'b', 'l', 'u', 't' };
20423 +static bfd_vma current_pc;
20424 +
20425 +struct avr32_field_value
20426 +{
20427 +  const struct avr32_ifield *ifield;
20428 +  unsigned long value;
20429 +};
20430 +
20431 +struct avr32_operand
20432 +{
20433 +  int id;
20434 +  int is_pcrel;
20435 +  int align_order;
20436 +  int (*print)(struct avr32_operand *op, struct disassemble_info *info,
20437 +              struct avr32_field_value *ifields);
20438 +};
20439 +
20440 +static signed long
20441 +get_signed_value(const struct avr32_field_value *fv)
20442 +{
20443 +  signed long value = fv->value;
20444 +
20445 +  if (fv->value & (1 << (fv->ifield->bitsize - 1)))
20446 +    value |= (~0UL << fv->ifield->bitsize);
20447 +
20448 +  return value;
20449 +}
20450 +
20451 +static void
20452 +print_reglist_range(unsigned int first, unsigned int last,
20453 +                   const struct reg_entry *reg_names,
20454 +                   int need_comma,
20455 +                   struct disassemble_info *info)
20456 +{
20457 +  if (need_comma)
20458 +    info->fprintf_func(info->stream, ",");
20459 +
20460 +  if (first == last)
20461 +    info->fprintf_func(info->stream, "%s",
20462 +                      reg_names[first].name);
20463 +  else
20464 +    info->fprintf_func(info->stream, "%s-%s",
20465 +                      reg_names[first].name, reg_names[last].name);
20466 +}
20467 +
20468 +static int
20469 +print_intreg(struct avr32_operand *op,
20470 +            struct disassemble_info *info,
20471 +            struct avr32_field_value *ifields)
20472 +{
20473 +  unsigned long regid = ifields[0].value << op->align_order;
20474 +
20475 +  info->fprintf_func(info->stream, "%s",
20476 +                    reg_table[regid].name);
20477 +  return 1;
20478 +}
20479 +
20480 +static int
20481 +print_intreg_predec(struct avr32_operand *op ATTRIBUTE_UNUSED,
20482 +                   struct disassemble_info *info,
20483 +                   struct avr32_field_value *ifields)
20484 +{
20485 +  info->fprintf_func(info->stream, "--%s",
20486 +                    reg_table[ifields[0].value].name);
20487 +  return 1;
20488 +}
20489 +
20490 +static int
20491 +print_intreg_postinc(struct avr32_operand *op ATTRIBUTE_UNUSED,
20492 +                    struct disassemble_info *info,
20493 +                    struct avr32_field_value *ifields)
20494 +{
20495 +  info->fprintf_func(info->stream, "%s++",
20496 +                    reg_table[ifields[0].value].name);
20497 +  return 1;
20498 +}
20499 +
20500 +static int
20501 +print_intreg_lsl(struct avr32_operand *op ATTRIBUTE_UNUSED,
20502 +                struct disassemble_info *info,
20503 +                struct avr32_field_value *ifields)
20504 +{
20505 +  const char *rp = reg_table[ifields[0].value].name;
20506 +  unsigned long sa = ifields[1].value;
20507 +
20508 +  if (sa)
20509 +    info->fprintf_func(info->stream, "%s<<0x%lx", rp, sa);
20510 +  else
20511 +    info->fprintf_func(info->stream, "%s", rp);
20512 +
20513 +  return 2;
20514 +}
20515 +
20516 +static int
20517 +print_intreg_lsr(struct avr32_operand *op ATTRIBUTE_UNUSED,
20518 +                struct disassemble_info *info,
20519 +                struct avr32_field_value *ifields)
20520 +{
20521 +  const char *rp = reg_table[ifields[0].value].name;
20522 +  unsigned long sa = ifields[1].value;
20523 +
20524 +  if (sa)
20525 +    info->fprintf_func(info->stream, "%s>>0x%lx", rp, sa);
20526 +  else
20527 +    info->fprintf_func(info->stream, "%s", rp);
20528 +
20529 +  return 2;
20530 +}
20531 +
20532 +static int
20533 +print_intreg_bpart(struct avr32_operand *op ATTRIBUTE_UNUSED,
20534 +                  struct disassemble_info *info,
20535 +                  struct avr32_field_value *ifields)
20536 +{
20537 +  info->fprintf_func(info->stream, "%s:%c",
20538 +                    reg_table[ifields[0].value].name,
20539 +                    bparts[ifields[1].value]);
20540 +  return 2;
20541 +}
20542 +
20543 +static int
20544 +print_intreg_hpart(struct avr32_operand *op ATTRIBUTE_UNUSED,
20545 +                  struct disassemble_info *info,
20546 +                  struct avr32_field_value *ifields)
20547 +{
20548 +  info->fprintf_func(info->stream, "%s:%c",
20549 +                    reg_table[ifields[0].value].name,
20550 +                    ifields[1].value ? 't' : 'b');
20551 +  return 2;
20552 +}
20553 +
20554 +static int
20555 +print_intreg_sdisp(struct avr32_operand *op,
20556 +                 struct disassemble_info *info,
20557 +                 struct avr32_field_value *ifields)
20558 +{
20559 +  signed long disp;
20560 +
20561 +  disp = get_signed_value(&ifields[1]) << op->align_order;
20562 +
20563 +  info->fprintf_func(info->stream, "%s[%ld]",
20564 +                    reg_table[ifields[0].value].name, disp);
20565 +  return 2;
20566 +}
20567 +
20568 +static int
20569 +print_intreg_udisp(struct avr32_operand *op,
20570 +                  struct disassemble_info *info,
20571 +                  struct avr32_field_value *ifields)
20572 +{
20573 +  info->fprintf_func(info->stream, "%s[0x%lx]",
20574 +                    reg_table[ifields[0].value].name,
20575 +                    ifields[1].value << op->align_order);
20576 +  return 2;
20577 +}
20578 +
20579 +static int
20580 +print_intreg_index(struct avr32_operand *op ATTRIBUTE_UNUSED,
20581 +                  struct disassemble_info *info,
20582 +                  struct avr32_field_value *ifields)
20583 +{
20584 +  const char *rb, *ri;
20585 +  unsigned long sa = ifields[2].value;
20586 +
20587 +  rb = reg_table[ifields[0].value].name;
20588 +  ri = reg_table[ifields[1].value].name;
20589 +
20590 +  if (sa)
20591 +    info->fprintf_func(info->stream, "%s[%s<<0x%lx]", rb, ri, sa);
20592 +  else
20593 +    info->fprintf_func(info->stream, "%s[%s]", rb, ri);
20594 +
20595 +  return 3;
20596 +}
20597 +
20598 +static int
20599 +print_intreg_xindex(struct avr32_operand *op ATTRIBUTE_UNUSED,
20600 +                   struct disassemble_info *info,
20601 +                   struct avr32_field_value *ifields)
20602 +{
20603 +  info->fprintf_func(info->stream, "%s[%s:%c<<2]",
20604 +                    reg_table[ifields[0].value].name,
20605 +                    reg_table[ifields[1].value].name,
20606 +                    bparts[ifields[2].value]);
20607 +  return 3;
20608 +}
20609 +
20610 +static int
20611 +print_jmplabel(struct avr32_operand *op,
20612 +              struct disassemble_info *info,
20613 +              struct avr32_field_value *ifields)
20614 +{
20615 +  bfd_vma address, offset;
20616 +
20617 +  offset = get_signed_value(ifields) << op->align_order;
20618 +  address = (current_pc & (~0UL << op->align_order)) + offset;
20619 +
20620 +  info->print_address_func(address, info);
20621 +
20622 +  return 1;
20623 +}
20624 +
20625 +static int
20626 +print_pc_disp(struct avr32_operand *op,
20627 +             struct disassemble_info *info,
20628 +             struct avr32_field_value *ifields)
20629 +{
20630 +  bfd_vma address, offset;
20631 +
20632 +  offset = ifields[0].value << op->align_order;
20633 +  address = (current_pc & (~0UL << op->align_order)) + offset;
20634 +
20635 +  info->print_address_func(address, info);
20636 +
20637 +  return 1;
20638 +}
20639 +
20640 +static int
20641 +print_sp(struct avr32_operand *op ATTRIBUTE_UNUSED,
20642 +        struct disassemble_info *info,
20643 +        struct avr32_field_value *ifields ATTRIBUTE_UNUSED)
20644 +{
20645 +  info->fprintf_func(info->stream, "sp");
20646 +  return 1;
20647 +}
20648 +
20649 +static int
20650 +print_sp_disp(struct avr32_operand *op,
20651 +             struct disassemble_info *info,
20652 +             struct avr32_field_value *ifields)
20653 +{
20654 +  info->fprintf_func(info->stream, "sp[0x%lx]",
20655 +                    ifields[0].value << op->align_order);
20656 +  return 1;
20657 +}
20658 +
20659 +static int
20660 +print_cpno(struct avr32_operand *op ATTRIBUTE_UNUSED,
20661 +          struct disassemble_info *info,
20662 +          struct avr32_field_value *ifields)
20663 +{
20664 +  info->fprintf_func(info->stream, "cp%lu", ifields[0].value);
20665 +  return 1;
20666 +}
20667 +
20668 +static int
20669 +print_cpreg(struct avr32_operand *op,
20670 +           struct disassemble_info *info,
20671 +           struct avr32_field_value *ifields)
20672 +{
20673 +  info->fprintf_func(info->stream, "cr%lu",
20674 +                    ifields[0].value << op->align_order);
20675 +  return 1;
20676 +}
20677 +
20678 +static int
20679 +print_uconst(struct avr32_operand *op,
20680 +            struct disassemble_info *info,
20681 +            struct avr32_field_value *ifields)
20682 +{
20683 +  info->fprintf_func(info->stream, "0x%lx",
20684 +                    ifields[0].value << op->align_order);
20685 +  return 1;
20686 +}
20687 +
20688 +static int
20689 +print_sconst(struct avr32_operand *op,
20690 +            struct disassemble_info *info,
20691 +            struct avr32_field_value *ifields)
20692 +{
20693 +  info->fprintf_func(info->stream, "%ld",
20694 +                    get_signed_value(ifields) << op->align_order);
20695 +  return 1;
20696 +}
20697 +
20698 +static int
20699 +print_reglist8_head(unsigned long regmask, int *commap,
20700 +                   struct disassemble_info *info)
20701 +{
20702 +  int first = -1, last, i = 0;
20703 +  int need_comma = 0;
20704 +
20705 +  while (i < 12)
20706 +    {
20707 +      if (first == -1 && (regmask & 1))
20708 +       {
20709 +         first = i;
20710 +       }
20711 +      else if (first != -1 && !(regmask & 1))
20712 +       {
20713 +         last = i - 1;
20714 +
20715 +         print_reglist_range(first, last, reg_table, need_comma, info);
20716 +         need_comma = 1;
20717 +         first = -1;
20718 +       }
20719 +
20720 +      if (i < 8)
20721 +       i += 4;
20722 +      else if (i < 10)
20723 +       i += 2;
20724 +      else
20725 +       i++;
20726 +      regmask >>= 1;
20727 +    }
20728 +
20729 +  *commap = need_comma;
20730 +  return first;
20731 +}
20732 +
20733 +static void
20734 +print_reglist8_tail(unsigned long regmask, int first, int need_comma,
20735 +                   struct disassemble_info *info)
20736 +{
20737 +  int last = 11;
20738 +
20739 +  if (regmask & 0x20)
20740 +    {
20741 +      if (first == -1)
20742 +       first = 12;
20743 +      last = 12;
20744 +    }
20745 +
20746 +  if (first != -1)
20747 +    {
20748 +      print_reglist_range(first, last, reg_table, need_comma, info);
20749 +      need_comma = 1;
20750 +      first = -1;
20751 +    }
20752 +
20753 +  if (regmask & 0x40)
20754 +    {
20755 +      if (first == -1)
20756 +       first = 14;
20757 +      last = 14;
20758 +    }
20759 +
20760 +  if (regmask & 0x80)
20761 +    {
20762 +      if (first == -1)
20763 +       first = 15;
20764 +      last = 15;
20765 +    }
20766 +
20767 +  if (first != -1)
20768 +    print_reglist_range(first, last, reg_table, need_comma, info);
20769 +}
20770 +
20771 +static int
20772 +print_reglist8(struct avr32_operand *op ATTRIBUTE_UNUSED,
20773 +              struct disassemble_info *info,
20774 +              struct avr32_field_value *ifields)
20775 +{
20776 +  unsigned long regmask = ifields[0].value;
20777 +  int first, need_comma;
20778 +
20779 +  first = print_reglist8_head(regmask, &need_comma, info);
20780 +  print_reglist8_tail(regmask, first, need_comma, info);
20781 +
20782 +  return 1;
20783 +}
20784 +
20785 +static int
20786 +print_reglist9(struct avr32_operand *op ATTRIBUTE_UNUSED,
20787 +              struct disassemble_info *info,
20788 +              struct avr32_field_value *ifields)
20789 +{
20790 +  unsigned long regmask = ifields[0].value >> 1;
20791 +  int first, last, need_comma;
20792 +
20793 +  first = print_reglist8_head(regmask, &need_comma, info);
20794 +
20795 +  if ((ifields[0].value & 0x101) == 0x101)
20796 +    {
20797 +      if (first != -1)
20798 +       {
20799 +         last = 11;
20800 +
20801 +         print_reglist_range(first, last, reg_table, need_comma, info);
20802 +         need_comma = 1;
20803 +         first = -1;
20804 +       }
20805 +
20806 +      print_reglist_range(15, 15, reg_table, need_comma, info);
20807 +
20808 +      regmask >>= 5;
20809 +
20810 +      if ((regmask & 3) == 0)
20811 +       info->fprintf_func(info->stream, ",r12=0");
20812 +      else if ((regmask & 3) == 1)
20813 +       info->fprintf_func(info->stream, ",r12=1");
20814 +      else
20815 +       info->fprintf_func(info->stream, ",r12=-1");
20816 +    }
20817 +  else
20818 +      print_reglist8_tail(regmask, first, need_comma, info);
20819 +
20820 +  return 1;
20821 +}
20822 +
20823 +static int
20824 +print_reglist16(struct avr32_operand *op ATTRIBUTE_UNUSED,
20825 +               struct disassemble_info *info,
20826 +               struct avr32_field_value *ifields)
20827 +{
20828 +  unsigned long regmask = ifields[0].value;
20829 +  unsigned int i = 0, first, last;
20830 +  int need_comma = 0;
20831 +
20832 +  while (i < 16)
20833 +    {
20834 +      if (regmask & 1)
20835 +       {
20836 +         first = i;
20837 +         while (i < 16)
20838 +           {
20839 +             i++;
20840 +             regmask >>= 1;
20841 +             if (!(regmask & 1))
20842 +               break;
20843 +           }
20844 +         last = i - 1;
20845 +         print_reglist_range(first, last, reg_table, need_comma, info);
20846 +         need_comma = 1;
20847 +       }
20848 +      else
20849 +       {
20850 +         i++;
20851 +         regmask >>= 1;
20852 +       }
20853 +    }
20854 +
20855 +  return 1;
20856 +}
20857 +
20858 +static int
20859 +print_reglist_ldm(struct avr32_operand *op,
20860 +                 struct disassemble_info *info,
20861 +                 struct avr32_field_value *ifields)
20862 +{
20863 +  int rp, w_bit;
20864 +  int i, first, last;
20865 +  unsigned long regmask;
20866 +
20867 +  rp = ifields[0].value;
20868 +  w_bit = ifields[1].value;
20869 +  regmask = ifields[2].value;
20870 +
20871 +  if (regmask & (1 << AVR32_REG_PC) && rp == AVR32_REG_PC)
20872 +    {
20873 +      if (w_bit)
20874 +       info->fprintf_func(info->stream, "sp++");
20875 +      else
20876 +       info->fprintf_func(info->stream, "sp");
20877 +
20878 +      for (i = 0; i < 12; )
20879 +       {
20880 +         if (regmask & (1 << i))
20881 +           {
20882 +             first = i;
20883 +             while (i < 12)
20884 +               {
20885 +                 i++;
20886 +                 if (!(regmask & (1 << i)))
20887 +                   break;
20888 +               }
20889 +             last = i - 1;
20890 +             print_reglist_range(first, last, reg_table, 1, info);
20891 +           }
20892 +         else
20893 +           i++;
20894 +       }
20895 +
20896 +      info->fprintf_func(info->stream, ",pc");
20897 +      if (regmask & (1 << AVR32_REG_LR))
20898 +       info->fprintf_func(info->stream, ",r12=-1");
20899 +      else if (regmask & (1 << AVR32_REG_R12))
20900 +       info->fprintf_func(info->stream, ",r12=1");
20901 +      else
20902 +       info->fprintf_func(info->stream, ",r12=0");
20903 +    }
20904 +  else
20905 +    {
20906 +      if (w_bit)
20907 +       info->fprintf_func(info->stream, "%s++,", reg_table[rp].name);
20908 +      else
20909 +       info->fprintf_func(info->stream, "%s,", reg_table[rp].name);
20910 +
20911 +      print_reglist16(op, info, ifields + 2);
20912 +    }
20913 +
20914 +  return 3;
20915 +}
20916 +
20917 +static int
20918 +print_reglist_cp8(struct avr32_operand *op ATTRIBUTE_UNUSED,
20919 +                 struct disassemble_info *info,
20920 +                 struct avr32_field_value *ifields)
20921 +{
20922 +  unsigned long regmask = ifields[0].value;
20923 +  unsigned int i = 0, first, last, offset = 0;
20924 +  int need_comma = 0;
20925 +
20926 +  if (ifields[1].value)
20927 +    offset = 8;
20928 +
20929 +  while (i < 8)
20930 +    {
20931 +      if (regmask & 1)
20932 +       {
20933 +         first = i;
20934 +         while (i < 8)
20935 +           {
20936 +             i++;
20937 +             regmask >>= 1;
20938 +             if (!(regmask & 1))
20939 +               break;
20940 +           }
20941 +         last = i - 1;
20942 +         print_reglist_range(offset + first, offset + last,
20943 +                             cr_table, need_comma, info);
20944 +         need_comma = 1;
20945 +       }
20946 +      else
20947 +       {
20948 +         i++;
20949 +         regmask >>= 1;
20950 +       }
20951 +    }
20952 +
20953 +  return 2;
20954 +}
20955 +
20956 +static int
20957 +print_reglist_cpd8(struct avr32_operand *op ATTRIBUTE_UNUSED,
20958 +                  struct disassemble_info *info,
20959 +                  struct avr32_field_value *ifields)
20960 +{
20961 +  unsigned long regmask = ifields[0].value;
20962 +  unsigned int i = 0, first, last;
20963 +  int need_comma = 0;
20964 +
20965 +  while (i < 8)
20966 +    {
20967 +      if (regmask & 1)
20968 +       {
20969 +         first = 2 * i;
20970 +         while (i < 8)
20971 +           {
20972 +             i++;
20973 +             regmask >>= 1;
20974 +             if (!(regmask & 1))
20975 +               break;
20976 +           }
20977 +         last = 2 * (i - 1) + 1;
20978 +         print_reglist_range(first, last, cr_table, need_comma, info);
20979 +         need_comma = 1;
20980 +       }
20981 +      else
20982 +       {
20983 +         i++;
20984 +         regmask >>= 1;
20985 +       }
20986 +    }
20987 +
20988 +  return 1;
20989 +}
20990 +
20991 +static int
20992 +print_retval(struct avr32_operand *op ATTRIBUTE_UNUSED,
20993 +            struct disassemble_info *info,
20994 +            struct avr32_field_value *ifields)
20995 +{
20996 +  unsigned long regid = ifields[0].value;
20997 +  const char *retval;
20998 +
20999 +  if (regid < AVR32_REG_SP)
21000 +    retval = reg_table[regid].name;
21001 +  else if (regid == AVR32_REG_SP)
21002 +    retval = "0";
21003 +  else if (regid == AVR32_REG_LR)
21004 +    retval = "-1";
21005 +  else
21006 +    retval = "1";
21007 +
21008 +  info->fprintf_func(info->stream, "%s", retval);
21009 +
21010 +  return 1;
21011 +}
21012 +
21013 +static int
21014 +print_mcall(struct avr32_operand *op,
21015 +           struct disassemble_info *info,
21016 +           struct avr32_field_value *ifields)
21017 +{
21018 +  unsigned long regid = ifields[0].value;
21019 +
21020 +  if (regid == AVR32_REG_PC)
21021 +    print_jmplabel(op, info, ifields + 1);
21022 +  else
21023 +    print_intreg_sdisp(op, info, ifields);
21024 +
21025 +  return 2;
21026 +}
21027 +
21028 +static int
21029 +print_jospinc(struct avr32_operand *op ATTRIBUTE_UNUSED,
21030 +             struct disassemble_info *info,
21031 +             struct avr32_field_value *ifields)
21032 +{
21033 +  signed long value = ifields[0].value;
21034 +
21035 +  if (value >= 4)
21036 +    value -= 8;
21037 +  else
21038 +    value += 1;
21039 +
21040 +  info->fprintf_func(info->stream, "%ld", value);
21041 +
21042 +  return 1;
21043 +}
21044 +
21045 +static int
21046 +print_coh(struct avr32_operand *op ATTRIBUTE_UNUSED,
21047 +         struct disassemble_info *info,
21048 +         struct avr32_field_value *ifields ATTRIBUTE_UNUSED)
21049 +{
21050 +  info->fprintf_func(info->stream, "COH");
21051 +  return 0;
21052 +}
21053 +
21054 +#define OP(name, sgn, pcrel, align, func) \
21055 +  { AVR32_OPERAND_##name, pcrel, align, print_##func }
21056 +
21057 +struct avr32_operand operand[AVR32_NR_OPERANDS] =
21058 +  {
21059 +    OP(INTREG, 0, 0, 0, intreg),
21060 +    OP(INTREG_PREDEC, 0, 0, 0, intreg_predec),
21061 +    OP(INTREG_POSTINC, 0, 0, 0, intreg_postinc),
21062 +    OP(INTREG_LSL, 0, 0, 0, intreg_lsl),
21063 +    OP(INTREG_LSR, 0, 0, 0, intreg_lsr),
21064 +    OP(INTREG_BSEL, 0, 0, 0, intreg_bpart),
21065 +    OP(INTREG_HSEL, 0, 0, 1, intreg_hpart),
21066 +    OP(INTREG_SDISP, 1, 0, 0, intreg_sdisp),
21067 +    OP(INTREG_SDISP_H, 1, 0, 1, intreg_sdisp),
21068 +    OP(INTREG_SDISP_W, 1, 0, 2, intreg_sdisp),
21069 +    OP(INTREG_UDISP, 0, 0, 0, intreg_udisp),
21070 +    OP(INTREG_UDISP_H, 0, 0, 1, intreg_udisp),
21071 +    OP(INTREG_UDISP_W, 0, 0, 2, intreg_udisp),
21072 +    OP(INTREG_INDEX, 0, 0, 0, intreg_index),
21073 +    OP(INTREG_XINDEX, 0, 0, 0, intreg_xindex),
21074 +    OP(DWREG, 0, 0, 1, intreg),
21075 +    OP(PC_UDISP_W, 0, 1, 2, pc_disp),
21076 +    OP(SP, 0, 0, 0, sp),
21077 +    OP(SP_UDISP_W, 0, 0, 2, sp_disp),
21078 +    OP(CPNO, 0, 0, 0, cpno),
21079 +    OP(CPREG, 0, 0, 0, cpreg),
21080 +    OP(CPREG_D, 0, 0, 1, cpreg),
21081 +    OP(UNSIGNED_CONST, 0, 0, 0, uconst),
21082 +    OP(UNSIGNED_CONST_W, 0, 0, 2, uconst),
21083 +    OP(SIGNED_CONST, 1, 0, 0, sconst),
21084 +    OP(SIGNED_CONST_W, 1, 0, 2, sconst),
21085 +    OP(JMPLABEL, 1, 1, 1, jmplabel),
21086 +    OP(UNSIGNED_NUMBER, 0, 0, 0, uconst),
21087 +    OP(UNSIGNED_NUMBER_W, 0, 0, 2, uconst),
21088 +    OP(REGLIST8, 0, 0, 0, reglist8),
21089 +    OP(REGLIST9, 0, 0, 0, reglist9),
21090 +    OP(REGLIST16, 0, 0, 0, reglist16),
21091 +    OP(REGLIST_LDM, 0, 0, 0, reglist_ldm),
21092 +    OP(REGLIST_CP8, 0, 0, 0, reglist_cp8),
21093 +    OP(REGLIST_CPD8, 0, 0, 0, reglist_cpd8),
21094 +    OP(RETVAL, 0, 0, 0, retval),
21095 +    OP(MCALL, 1, 0, 2, mcall),
21096 +    OP(JOSPINC, 0, 0, 0, jospinc),
21097 +    OP(COH, 0, 0, 0, coh),
21098 +  };
21099 +
21100 +static void
21101 +print_opcode(bfd_vma insn_word, const struct avr32_opcode *opc,
21102 +            bfd_vma pc, struct disassemble_info *info)
21103 +{
21104 +  const struct avr32_syntax *syntax = opc->syntax;
21105 +  struct avr32_field_value fields[AVR32_MAX_FIELDS];
21106 +  unsigned int i, next_field = 0, nr_operands;
21107 +
21108 +  for (i = 0; i < opc->nr_fields; i++)
21109 +    {
21110 +      opc->fields[i]->extract(opc->fields[i], &insn_word, &fields[i].value);
21111 +      fields[i].ifield = opc->fields[i];
21112 +    }
21113 +
21114 +  current_pc = pc;
21115 +  info->fprintf_func(info->stream, "%s", syntax->mnemonic->name);
21116 +
21117 +  if (syntax->nr_operands < 0)
21118 +    nr_operands = (unsigned int) -syntax->nr_operands;
21119 +  else
21120 +    nr_operands = (unsigned int) syntax->nr_operands;
21121 +
21122 +  for (i = 0; i < nr_operands; i++)
21123 +    {
21124 +      struct avr32_operand *op = &operand[syntax->operand[i]];
21125 +
21126 +      if (i)
21127 +       info->fprintf_func(info->stream, ",");
21128 +      else
21129 +       info->fprintf_func(info->stream, "\t");
21130 +      next_field += op->print(op, info, &fields[next_field]);
21131 +    }
21132 +}
21133 +
21134 +static const struct avr32_opcode *
21135 +find_opcode(bfd_vma insn_word)
21136 +{
21137 +  int i;
21138 +
21139 +  for (i = 0; i < AVR32_NR_OPCODES; i++)
21140 +    {
21141 +      const struct avr32_opcode *opc = &avr32_opc_table[i];
21142 +
21143 +      if ((insn_word & opc->mask) == opc->value)
21144 +       return opc;
21145 +    }
21146 +
21147 +  return NULL;
21148 +}
21149 +
21150 +static int
21151 +read_insn_word(bfd_vma pc, bfd_vma *valuep,
21152 +              struct disassemble_info *info)
21153 +{
21154 +  bfd_byte b[4];
21155 +  int status;
21156 +
21157 +  status = info->read_memory_func(pc, b, 4, info);
21158 +  if (status)
21159 +    {
21160 +      status = info->read_memory_func(pc, b, 2, info);
21161 +      if (status)
21162 +       {
21163 +         info->memory_error_func(status, pc, info);
21164 +         return -1;
21165 +       }
21166 +      b[3] = b[2] = 0;
21167 +    }
21168 +
21169 +  *valuep =  (b[0] << 24) | (b[1] << 16) | (b[2] << 8) | b[3];
21170 +  return 0;
21171 +}
21172 +
21173 +/* Parse an individual disassembler option.  */
21174 +
21175 +void
21176 +parse_avr32_disassembler_option (option)
21177 +     char * option;
21178 +{
21179 +  if (option == NULL)
21180 +    return;
21181 +
21182 +  /* XXX - should break 'option' at following delimiter.  */
21183 +  fprintf (stderr, _("Unrecognised disassembler option: %s\n"), option);
21184 +
21185 +  return;
21186 +}
21187 +
21188 +/* Parse the string of disassembler options, spliting it at whitespaces
21189 +   or commas.  (Whitespace separators supported for backwards compatibility).  */
21190 +
21191 +static void
21192 +parse_disassembler_options (char *options)
21193 +{
21194 +  if (options == NULL)
21195 +    return;
21196 +
21197 +  while (*options)
21198 +    {
21199 +      parse_avr32_disassembler_option (options);
21200 +
21201 +      /* Skip forward to next seperator.  */
21202 +      while ((*options) && (! ISSPACE (*options)) && (*options != ','))
21203 +       ++ options;
21204 +      /* Skip forward past seperators.  */
21205 +      while (ISSPACE (*options) || (*options == ','))
21206 +       ++ options;
21207 +    }
21208 +}
21209 +
21210 +int
21211 +print_insn_avr32(bfd_vma pc, struct disassemble_info *info)
21212 +{
21213 +  bfd_vma insn_word;
21214 +  const struct avr32_opcode *opc;
21215 +
21216 +  if (info->disassembler_options)
21217 +    {
21218 +      parse_disassembler_options (info->disassembler_options);
21219 +
21220 +      /* To avoid repeated parsing of these options, we remove them here.  */
21221 +      info->disassembler_options = NULL;
21222 +    }
21223 +
21224 +  info->bytes_per_chunk = 1;
21225 +  info->display_endian = BFD_ENDIAN_BIG;
21226 +
21227 +  if (read_insn_word(pc, &insn_word, info))
21228 +    return -1;
21229 +
21230 +  opc = find_opcode(insn_word);
21231 +  if (opc)
21232 +    {
21233 +      print_opcode(insn_word, opc, pc, info);
21234 +      return opc->size;
21235 +    }
21236 +  else
21237 +    {
21238 +      info->fprintf_func(info->stream, _("*unknown*"));
21239 +      return 2;
21240 +    }
21241 +
21242 +}
21243 +
21244 +void
21245 +print_avr32_disassembler_options (FILE *stream ATTRIBUTE_UNUSED)
21246 +{
21247 +
21248 +}
21249 --- /dev/null
21250 +++ b/opcodes/avr32-opc.c
21251 @@ -0,0 +1,6946 @@
21252 +/* Opcode tables for AVR32.
21253 +   Copyright 2005,2006,2007,2008,2009 Atmel Corporation.
21254 +
21255 +   Written by Haavard Skinnemoen, Atmel Norway, <hskinnemoen@atmel.com>
21256 +
21257 +   This file is part of libopcodes.
21258 +
21259 +   This program is free software; you can redistribute it and/or
21260 +   modify it under the terms of the GNU General Public License as
21261 +   published by the Free Software Foundation; either version 2 of the
21262 +   License, or (at your option) any later version.
21263 +
21264 +   This program is distributed in the hope that it will be useful, but
21265 +   WITHOUT ANY WARRANTY; without even the implied warranty of
21266 +   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
21267 +   General Public License for more details.
21268 +
21269 +   You should have received a copy of the GNU General Public License
21270 +   along with this program; if not, write to the Free Software
21271 +   Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA
21272 +   02111-1307, USA.  */
21273 +
21274 +#include <stdlib.h>
21275 +#include <assert.h>
21276 +
21277 +#include "avr32-opc.h"
21278 +
21279 +#define PICO_CPNO      1
21280 +
21281 +void
21282 +avr32_insert_simple(const struct avr32_ifield *field,
21283 +                   void *buf, unsigned long value)
21284 +{
21285 +  bfd_vma word;
21286 +
21287 +  word = bfd_getb32(buf);
21288 +  word &= ~field->mask;
21289 +  word |= (value << field->shift) & field->mask;
21290 +  bfd_putb32(word, buf);
21291 +}
21292 +
21293 +void
21294 +avr32_insert_bit5c(const struct avr32_ifield *field ATTRIBUTE_UNUSED,
21295 +                  void *buf, unsigned long value)
21296 +{
21297 +  char *opcode = buf;
21298 +
21299 +  opcode[0] = (opcode[0] & 0xe1) | (value & 0x1e);
21300 +  opcode[1] = (opcode[1] & 0xef) | ((value & 1) << 4);
21301 +}
21302 +
21303 +void
21304 +avr32_insert_k10(const struct avr32_ifield *field ATTRIBUTE_UNUSED,
21305 +                void *buf, unsigned long value)
21306 +{
21307 +  char *opcode = buf;
21308 +
21309 +  opcode[0] = (opcode[0] & 0xf0) | ((value & 0xf0) >> 4);
21310 +  opcode[1] = ((opcode[1] & 0x0c) | ((value & 0x0f) << 4)
21311 +              | ((value & 0x300) >> 8));
21312 +}
21313 +
21314 +
21315 +void
21316 +avr32_insert_k21(const struct avr32_ifield *field,
21317 +                void *buf, unsigned long value)
21318 +{
21319 +  bfd_vma word;
21320 +  bfd_vma k21;
21321 +
21322 +  word = bfd_getb32(buf);
21323 +  word &= ~field->mask;
21324 +  k21 = ((value & 0xffff) | ((value & 0x10000) << 4)
21325 +        | ((value & 0x1e0000) << 8));
21326 +  assert(!(k21 & ~field->mask));
21327 +  word |= k21;
21328 +  bfd_putb32(word, buf);
21329 +}
21330 +
21331 +void
21332 +avr32_insert_cpop(const struct avr32_ifield *field,
21333 +                 void *buf, unsigned long value)
21334 +{
21335 +  bfd_vma word;
21336 +
21337 +  word = bfd_getb32(buf);
21338 +  word &= ~field->mask;
21339 +  word |= (((value & 0x1e) << 15) | ((value & 0x60) << 20)
21340 +          | ((value & 0x01) << 12));
21341 +  bfd_putb32(word, buf);
21342 +}
21343 +
21344 +void
21345 +avr32_insert_k12cp(const struct avr32_ifield *field,
21346 +                  void *buf, unsigned long value)
21347 +{
21348 +  bfd_vma word;
21349 +
21350 +  word = bfd_getb32(buf);
21351 +  word &= ~field->mask;
21352 +  word |= ((value & 0xf00) << 4) | (value & 0xff);
21353 +  bfd_putb32(word, buf);
21354 +}
21355 +
21356 +void avr32_extract_simple(const struct avr32_ifield *field,
21357 +                         void *buf, unsigned long *value)
21358 +{
21359 +  /* XXX: The disassembler has done any necessary byteswapping already */
21360 +  bfd_vma word = *(bfd_vma *)buf;
21361 +
21362 +  *value = (word & field->mask) >> field->shift;
21363 +}
21364 +
21365 +void avr32_extract_bit5c(const struct avr32_ifield *field ATTRIBUTE_UNUSED,
21366 +                        void *buf, unsigned long *value)
21367 +{
21368 +  bfd_vma word = *(bfd_vma *)buf;
21369 +
21370 +  *value = ((word >> 20) & 1) | ((word >> 24) & 0x1e);
21371 +}
21372 +
21373 +void avr32_extract_k10(const struct avr32_ifield *field ATTRIBUTE_UNUSED,
21374 +                      void *buf, unsigned long *value)
21375 +{
21376 +  bfd_vma word = *(bfd_vma *)buf;
21377 +
21378 +  *value = ((word >> 8) & 0x300) | ((word >> 20) & 0xff);
21379 +}
21380 +
21381 +void avr32_extract_k21(const struct avr32_ifield *field ATTRIBUTE_UNUSED,
21382 +                      void *buf, unsigned long *value)
21383 +{
21384 +  bfd_vma word = *(bfd_vma *)buf;
21385 +
21386 +  *value = ((word & 0xffff) | ((word >> 4) & 0x10000)
21387 +           | ((word >> 8) & 0x1e0000));
21388 +}
21389 +
21390 +void avr32_extract_cpop(const struct avr32_ifield *field ATTRIBUTE_UNUSED,
21391 +                       void *buf, unsigned long *value)
21392 +{
21393 +  bfd_vma word = *(bfd_vma *)buf;
21394 +
21395 +  *value = (((word >> 12) & 1) | ((word >> 15) & 0x1e)
21396 +           | ((word >> 20) & 0x60));
21397 +}
21398 +
21399 +void avr32_extract_k12cp(const struct avr32_ifield *field ATTRIBUTE_UNUSED,
21400 +                        void *buf, unsigned long *value)
21401 +{
21402 +  bfd_vma word = *(bfd_vma *)buf;
21403 +
21404 +  *value = ((word >> 4) & 0xf00) | (word & 0xff);
21405 +}
21406 +
21407 +
21408 +#define IFLD(id, bitsz, shift, mask, func) \
21409 +  { AVR32_IFIELD_##id, bitsz, shift, mask, \
21410 +    avr32_insert_##func, avr32_extract_##func }
21411 +
21412 +const struct avr32_ifield avr32_ifield_table[] =
21413 +  {
21414 +    IFLD(RX, 4, 25, 0x1e000000, simple),
21415 +    IFLD(RY, 4, 16, 0x000f0000, simple),
21416 +    IFLD(COND4C, 4, 20, 0x00f00000, simple),
21417 +    IFLD(K8C, 8, 20, 0x0ff00000, simple),
21418 +    IFLD(K7C, 7, 20, 0x07f00000, simple),
21419 +    IFLD(K5C, 5, 20, 0x01f00000, simple),
21420 +    IFLD(K3, 3, 20, 0x00700000, simple),
21421 +    IFLD(RY_DW, 3, 17, 0x000e0000, simple),
21422 +    IFLD(COND4E, 4, 8, 0x00000f00, simple),
21423 +    IFLD(K8E, 8, 0, 0x000000ff, simple),
21424 +    IFLD(BIT5C, 5, 20, 0x1e100000, bit5c),
21425 +    IFLD(COND3, 3, 16, 0x00070000, simple),
21426 +    IFLD(K10, 10, 16, 0x0ff30000, k10),
21427 +    IFLD(POPM, 9, 19, 0x0ff80000, simple),
21428 +    IFLD(K2, 2, 4, 0x00000030, simple),
21429 +    IFLD(RD_E, 4, 0, 0x0000000f, simple),
21430 +    IFLD(RD_DW, 3, 1, 0x0000000e, simple),
21431 +    IFLD(X, 1, 5, 0x00000020, simple),
21432 +    IFLD(Y, 1, 4, 0x00000010, simple),
21433 +    IFLD(X2, 1, 13, 0x00002000, simple),
21434 +    IFLD(Y2, 1, 12, 0x00001000, simple),
21435 +    IFLD(K5E, 5, 0, 0x0000001f, simple),
21436 +    IFLD(PART2, 2, 0, 0x00000003, simple),
21437 +    IFLD(PART1, 1, 0, 0x00000001, simple),
21438 +    IFLD(K16, 16, 0, 0x0000ffff, simple),
21439 +    IFLD(CACHEOP, 5, 11, 0x0000f800, simple),
21440 +    IFLD(K11, 11, 0, 0x000007ff, simple),
21441 +    IFLD(K21, 21, 0, 0x1e10ffff, k21),
21442 +    IFLD(CPOP, 7, 12, 0x060f1000, cpop),
21443 +    IFLD(CPNO, 3, 13, 0x0000e000, simple),
21444 +    IFLD(CRD_RI, 4, 8, 0x00000f00, simple),
21445 +    IFLD(CRX, 4, 4, 0x000000f0, simple),
21446 +    IFLD(CRY, 4, 0, 0x0000000f, simple),
21447 +    IFLD(K7E, 7, 0, 0x0000007f, simple),
21448 +    IFLD(CRD_DW, 3, 9, 0x00000e00, simple),
21449 +    IFLD(PART1_K12, 1, 12, 0x00001000, simple),
21450 +    IFLD(PART2_K12, 2, 12, 0x00003000, simple),
21451 +    IFLD(K12, 12, 0, 0x00000fff, simple),
21452 +    IFLD(S5, 5, 5, 0x000003e0, simple),
21453 +    IFLD(K5E2, 5, 4, 0x000001f0, simple),
21454 +    IFLD(K4, 4, 20, 0x00f00000, simple),
21455 +    IFLD(COND4E2, 4, 4, 0x000000f0, simple),
21456 +    IFLD(K8E2, 8, 4, 0x00000ff0, simple),
21457 +    IFLD(K6, 6, 20, 0x03f00000, simple),
21458 +    IFLD(MEM15, 15, 0, 0x00007fff, simple),
21459 +    IFLD(MEMB5, 5, 15, 0x000f8000, simple),
21460 +    IFLD(W, 1, 25, 0x02000000, simple),
21461 +    /* Coprocessor Multiple High/Low */
21462 +    IFLD(CM_HL, 1, 8, 0x00000100, simple),
21463 +    IFLD(K12CP, 12 ,0, 0x0000f0ff, k12cp),
21464 +    IFLD(K9E, 9 ,0, 0x000001ff, simple),
21465 +  };
21466 +#undef IFLD
21467 +
21468 +
21469 +struct avr32_opcode avr32_opc_table[] =
21470 +  {
21471 +    {
21472 +      AVR32_OPC_ABS, 2, 0x5c400000, 0xfff00000,
21473 +      &avr32_syntax_table[AVR32_SYNTAX_ABS],
21474 +      BFD_RELOC_UNUSED, 1, -1,
21475 +      {
21476 +       &avr32_ifield_table[AVR32_IFIELD_RY],
21477 +      }
21478 +    },
21479 +    {
21480 +      AVR32_OPC_ACALL, 2, 0xd0000000, 0xf00f0000,
21481 +      &avr32_syntax_table[AVR32_SYNTAX_ACALL],
21482 +      BFD_RELOC_UNUSED, 1, -1,
21483 +      {
21484 +       &avr32_ifield_table[AVR32_IFIELD_K8C],
21485 +      },
21486 +    },
21487 +    {
21488 +      AVR32_OPC_ACR, 2, 0x5c000000, 0xfff00000,
21489 +      &avr32_syntax_table[AVR32_SYNTAX_ACR],
21490 +      BFD_RELOC_UNUSED, 1, -1,
21491 +      {
21492 +       &avr32_ifield_table[AVR32_IFIELD_RY],
21493 +      },
21494 +    },
21495 +    {
21496 +      AVR32_OPC_ADC, 4, 0xe0000040, 0xe1f0fff0,
21497 +      &avr32_syntax_table[AVR32_SYNTAX_ADC],
21498 +      BFD_RELOC_UNUSED, 3, -1,
21499 +      {
21500 +       &avr32_ifield_table[AVR32_IFIELD_RD_E],
21501 +       &avr32_ifield_table[AVR32_IFIELD_RX],
21502 +       &avr32_ifield_table[AVR32_IFIELD_RY],
21503 +      },
21504 +    },
21505 +    {
21506 +      AVR32_OPC_ADD1, 2, 0x00000000, 0xe1f00000,
21507 +      &avr32_syntax_table[AVR32_SYNTAX_ADD1],
21508 +      BFD_RELOC_UNUSED, 2, -1,
21509 +      {
21510 +       &avr32_ifield_table[AVR32_IFIELD_RY],
21511 +       &avr32_ifield_table[AVR32_IFIELD_RX],
21512 +      },
21513 +    },
21514 +    {
21515 +      AVR32_OPC_ADD2, 4, 0xe0000000, 0xe1f0ffc0,
21516 +      &avr32_syntax_table[AVR32_SYNTAX_ADD2],
21517 +      BFD_RELOC_UNUSED, 4, -1,
21518 +      {
21519 +       &avr32_ifield_table[AVR32_IFIELD_RD_E],
21520 +       &avr32_ifield_table[AVR32_IFIELD_RX],
21521 +       &avr32_ifield_table[AVR32_IFIELD_RY],
21522 +       &avr32_ifield_table[AVR32_IFIELD_K2],
21523 +      },
21524 +    },
21525 +    {
21526 +      AVR32_OPC_ADDABS, 4, 0xe0000e40, 0xe1f0fff0,
21527 +      &avr32_syntax_table[AVR32_SYNTAX_ADDABS],
21528 +      BFD_RELOC_UNUSED, 3, -1,
21529 +      {
21530 +       &avr32_ifield_table[AVR32_IFIELD_RD_E],
21531 +       &avr32_ifield_table[AVR32_IFIELD_RX],
21532 +       &avr32_ifield_table[AVR32_IFIELD_RY],
21533 +      },
21534 +    },
21535 +    {
21536 +      AVR32_OPC_ADDHH_W, 4, 0xe0000e00, 0xe1f0ffc0,
21537 +      &avr32_syntax_table[AVR32_SYNTAX_ADDHH_W],
21538 +      BFD_RELOC_UNUSED, 5, -1,
21539 +      {
21540 +       &avr32_ifield_table[AVR32_IFIELD_RD_E],
21541 +       &avr32_ifield_table[AVR32_IFIELD_RX],
21542 +       &avr32_ifield_table[AVR32_IFIELD_X],
21543 +       &avr32_ifield_table[AVR32_IFIELD_RY],
21544 +       &avr32_ifield_table[AVR32_IFIELD_Y],
21545 +      },
21546 +    },
21547 +    {
21548 +      AVR32_OPC_AND1, 2, 0x00600000, 0xe1f00000,
21549 +      &avr32_syntax_table[AVR32_SYNTAX_AND1],
21550 +      BFD_RELOC_UNUSED, 2, -1,
21551 +      {
21552 +       &avr32_ifield_table[AVR32_IFIELD_RY],
21553 +       &avr32_ifield_table[AVR32_IFIELD_RX],
21554 +      },
21555 +    },
21556 +    {
21557 +      AVR32_OPC_AND2, 4, 0xe1e00000, 0xe1f0fe00,
21558 +      &avr32_syntax_table[AVR32_SYNTAX_AND2],
21559 +      BFD_RELOC_UNUSED, 4, -1,
21560 +      {
21561 +       &avr32_ifield_table[AVR32_IFIELD_RD_E],
21562 +       &avr32_ifield_table[AVR32_IFIELD_RX],
21563 +       &avr32_ifield_table[AVR32_IFIELD_RY],
21564 +       &avr32_ifield_table[AVR32_IFIELD_K5E2],
21565 +      },
21566 +    },
21567 +    {
21568 +      AVR32_OPC_AND3, 4, 0xe1e00200, 0xe1f0fe00,
21569 +      &avr32_syntax_table[AVR32_SYNTAX_AND3],
21570 +      BFD_RELOC_UNUSED, 4, -1,
21571 +      {
21572 +       &avr32_ifield_table[AVR32_IFIELD_RD_E],
21573 +       &avr32_ifield_table[AVR32_IFIELD_RX],
21574 +       &avr32_ifield_table[AVR32_IFIELD_RY],
21575 +       &avr32_ifield_table[AVR32_IFIELD_K5E2],
21576 +      },
21577 +    },
21578 +    {
21579 +      AVR32_OPC_ANDH, 4, 0xe4100000, 0xfff00000,
21580 +      &avr32_syntax_table[AVR32_SYNTAX_ANDH],
21581 +      BFD_RELOC_AVR32_16U, 2, 1,
21582 +      {
21583 +       &avr32_ifield_table[AVR32_IFIELD_RY],
21584 +       &avr32_ifield_table[AVR32_IFIELD_K16],
21585 +      },
21586 +    },
21587 +    {
21588 +      AVR32_OPC_ANDH_COH, 4, 0xe6100000, 0xfff00000,
21589 +      &avr32_syntax_table[AVR32_SYNTAX_ANDH_COH],
21590 +      BFD_RELOC_AVR32_16U, 2, 1,
21591 +      {
21592 +       &avr32_ifield_table[AVR32_IFIELD_RY],
21593 +       &avr32_ifield_table[AVR32_IFIELD_K16],
21594 +      },
21595 +    },
21596 +    {
21597 +      AVR32_OPC_ANDL, 4, 0xe0100000, 0xfff00000,
21598 +      &avr32_syntax_table[AVR32_SYNTAX_ANDL],
21599 +      BFD_RELOC_AVR32_16U, 2, 1,
21600 +      {
21601 +       &avr32_ifield_table[AVR32_IFIELD_RY],
21602 +       &avr32_ifield_table[AVR32_IFIELD_K16],
21603 +      },
21604 +    },
21605 +    {
21606 +      AVR32_OPC_ANDL_COH, 4, 0xe2100000, 0xfff00000,
21607 +      &avr32_syntax_table[AVR32_SYNTAX_ANDL_COH],
21608 +      BFD_RELOC_AVR32_16U, 2, 1,
21609 +      {
21610 +       &avr32_ifield_table[AVR32_IFIELD_RY],
21611 +       &avr32_ifield_table[AVR32_IFIELD_K16],
21612 +      },
21613 +    },
21614 +    {
21615 +      AVR32_OPC_ANDN, 2, 0x00800000, 0xe1f00000,
21616 +      &avr32_syntax_table[AVR32_SYNTAX_ANDN],
21617 +      BFD_RELOC_UNUSED, 2, -1,
21618 +      {
21619 +       &avr32_ifield_table[AVR32_IFIELD_RY],
21620 +       &avr32_ifield_table[AVR32_IFIELD_RX],
21621 +      },
21622 +    },
21623 +    {
21624 +      AVR32_OPC_ASR1, 4, 0xe0000840, 0xe1f0fff0,
21625 +      &avr32_syntax_table[AVR32_SYNTAX_ASR1],
21626 +      BFD_RELOC_UNUSED, 3, -1,
21627 +      {
21628 +       &avr32_ifield_table[AVR32_IFIELD_RD_E],
21629 +       &avr32_ifield_table[AVR32_IFIELD_RX],
21630 +       &avr32_ifield_table[AVR32_IFIELD_RY],
21631 +      },
21632 +    },
21633 +    {
21634 +      AVR32_OPC_ASR3, 4, 0xe0001400, 0xe1f0ffe0,
21635 +      &avr32_syntax_table[AVR32_SYNTAX_ASR3],
21636 +      BFD_RELOC_UNUSED, 3, -1,
21637 +      {
21638 +       &avr32_ifield_table[AVR32_IFIELD_RY],
21639 +       &avr32_ifield_table[AVR32_IFIELD_RX],
21640 +       &avr32_ifield_table[AVR32_IFIELD_K5E],
21641 +      },
21642 +    },
21643 +    {
21644 +      AVR32_OPC_ASR2, 2, 0xa1400000, 0xe1e00000,
21645 +      &avr32_syntax_table[AVR32_SYNTAX_ASR2],
21646 +      BFD_RELOC_UNUSED, 2, -1,
21647 +      {
21648 +       &avr32_ifield_table[AVR32_IFIELD_RY],
21649 +       &avr32_ifield_table[AVR32_IFIELD_BIT5C],
21650 +      },
21651 +    },
21652 +    {
21653 +      AVR32_OPC_BLD, 4, 0xedb00000, 0xfff0ffe0,
21654 +      &avr32_syntax_table[AVR32_SYNTAX_BLD],
21655 +      BFD_RELOC_UNUSED, 2, -1,
21656 +      {
21657 +       &avr32_ifield_table[AVR32_IFIELD_RY],
21658 +       &avr32_ifield_table[AVR32_IFIELD_K5E],
21659 +      },
21660 +    },
21661 +    {
21662 +      AVR32_OPC_BREQ1, 2, 0xc0000000, 0xf00f0000,
21663 +      &avr32_syntax_table[AVR32_SYNTAX_BREQ1],
21664 +      BFD_RELOC_AVR32_9H_PCREL, 1, 0,
21665 +      {
21666 +       &avr32_ifield_table[AVR32_IFIELD_K8C],
21667 +      },
21668 +    },
21669 +    {
21670 +      AVR32_OPC_BRNE1, 2, 0xc0010000, 0xf00f0000,
21671 +      &avr32_syntax_table[AVR32_SYNTAX_BRNE1],
21672 +      BFD_RELOC_AVR32_9H_PCREL, 1, 0,
21673 +      {
21674 +       &avr32_ifield_table[AVR32_IFIELD_K8C],
21675 +      },
21676 +    },
21677 +    {
21678 +      AVR32_OPC_BRCC1, 2, 0xc0020000, 0xf00f0000,
21679 +      &avr32_syntax_table[AVR32_SYNTAX_BRCC1],
21680 +      BFD_RELOC_AVR32_9H_PCREL, 1, 0,
21681 +      {
21682 +       &avr32_ifield_table[AVR32_IFIELD_K8C],
21683 +      },
21684 +    },
21685 +    {
21686 +      AVR32_OPC_BRCS1, 2, 0xc0030000, 0xf00f0000,
21687 +      &avr32_syntax_table[AVR32_SYNTAX_BRCS1],
21688 +      BFD_RELOC_AVR32_9H_PCREL, 1, 0,
21689 +      {
21690 +       &avr32_ifield_table[AVR32_IFIELD_K8C],
21691 +      },
21692 +    },
21693 +    {
21694 +      AVR32_OPC_BRGE1, 2, 0xc0040000, 0xf00f0000,
21695 +      &avr32_syntax_table[AVR32_SYNTAX_BRGE1],
21696 +      BFD_RELOC_AVR32_9H_PCREL, 1, 0,
21697 +      {
21698 +       &avr32_ifield_table[AVR32_IFIELD_K8C],
21699 +      },
21700 +    },
21701 +    {
21702 +      AVR32_OPC_BRLT1, 2, 0xc0050000, 0xf00f0000,
21703 +      &avr32_syntax_table[AVR32_SYNTAX_BRLT1],
21704 +      BFD_RELOC_AVR32_9H_PCREL, 1, 0,
21705 +      {
21706 +       &avr32_ifield_table[AVR32_IFIELD_K8C],
21707 +      },
21708 +    },
21709 +    {
21710 +      AVR32_OPC_BRMI1, 2, 0xc0060000, 0xf00f0000,
21711 +      &avr32_syntax_table[AVR32_SYNTAX_BRMI1],
21712 +      BFD_RELOC_AVR32_9H_PCREL, 1, 0,
21713 +      {
21714 +       &avr32_ifield_table[AVR32_IFIELD_K8C],
21715 +      },
21716 +    },
21717 +    {
21718 +      AVR32_OPC_BRPL1, 2, 0xc0070000, 0xf00f0000,
21719 +      &avr32_syntax_table[AVR32_SYNTAX_BRPL1],
21720 +      BFD_RELOC_AVR32_9H_PCREL, 1, 0,
21721 +      {
21722 +       &avr32_ifield_table[AVR32_IFIELD_K8C],
21723 +      },
21724 +    },
21725 +    {
21726 +      AVR32_OPC_BREQ2, 4, 0xe0800000, 0xe1ef0000,
21727 +      &avr32_syntax_table[AVR32_SYNTAX_BREQ2],
21728 +      BFD_RELOC_AVR32_22H_PCREL, 1, 0,
21729 +      {
21730 +       &avr32_ifield_table[AVR32_IFIELD_K21],
21731 +      },
21732 +    },
21733 +    {
21734 +      AVR32_OPC_BRNE2, 4, 0xe0810000, 0xe1ef0000,
21735 +      &avr32_syntax_table[AVR32_SYNTAX_BRNE2],
21736 +      BFD_RELOC_AVR32_22H_PCREL, 1, 0,
21737 +      {
21738 +       &avr32_ifield_table[AVR32_IFIELD_K21],
21739 +      },
21740 +    },
21741 +    {
21742 +      AVR32_OPC_BRCC2, 4, 0xe0820000, 0xe1ef0000,
21743 +      &avr32_syntax_table[AVR32_SYNTAX_BRHS2],
21744 +      BFD_RELOC_AVR32_22H_PCREL, 1, 0,
21745 +      {
21746 +       &avr32_ifield_table[AVR32_IFIELD_K21],
21747 +      },
21748 +    },
21749 +    {
21750 +      AVR32_OPC_BRCS2, 4, 0xe0830000, 0xe1ef0000,
21751 +      &avr32_syntax_table[AVR32_SYNTAX_BRLO2],
21752 +      BFD_RELOC_AVR32_22H_PCREL, 1, 0,
21753 +      {
21754 +       &avr32_ifield_table[AVR32_IFIELD_K21],
21755 +      },
21756 +    },
21757 +    {
21758 +      AVR32_OPC_BRGE2, 4, 0xe0840000, 0xe1ef0000,
21759 +      &avr32_syntax_table[AVR32_SYNTAX_BRGE2],
21760 +      BFD_RELOC_AVR32_22H_PCREL, 1, 0,
21761 +      {
21762 +       &avr32_ifield_table[AVR32_IFIELD_K21],
21763 +      },
21764 +    },
21765 +    {
21766 +      AVR32_OPC_BRLT2, 4, 0xe0850000, 0xe1ef0000,
21767 +      &avr32_syntax_table[AVR32_SYNTAX_BRLT2],
21768 +      BFD_RELOC_AVR32_22H_PCREL, 1, 0,
21769 +      {
21770 +       &avr32_ifield_table[AVR32_IFIELD_K21],
21771 +      },
21772 +    },
21773 +    {
21774 +      AVR32_OPC_BRMI2, 4, 0xe0860000, 0xe1ef0000,
21775 +      &avr32_syntax_table[AVR32_SYNTAX_BRMI2],
21776 +      BFD_RELOC_AVR32_22H_PCREL, 1, 0,
21777 +      {
21778 +       &avr32_ifield_table[AVR32_IFIELD_K21],
21779 +      },
21780 +    },
21781 +    {
21782 +      AVR32_OPC_BRPL2, 4, 0xe0870000, 0xe1ef0000,
21783 +      &avr32_syntax_table[AVR32_SYNTAX_BRPL2],
21784 +      BFD_RELOC_AVR32_22H_PCREL, 1, 0,
21785 +      {
21786 +       &avr32_ifield_table[AVR32_IFIELD_K21],
21787 +      },
21788 +    },
21789 +    {
21790 +      AVR32_OPC_BRLS, 4, 0xe0880000, 0xe1ef0000,
21791 +      &avr32_syntax_table[AVR32_SYNTAX_BRLS],
21792 +      BFD_RELOC_AVR32_22H_PCREL, 1, 0,
21793 +      {
21794 +       &avr32_ifield_table[AVR32_IFIELD_K21],
21795 +      },
21796 +    },
21797 +    {
21798 +      AVR32_OPC_BRGT, 4, 0xe0890000, 0xe1ef0000,
21799 +      &avr32_syntax_table[AVR32_SYNTAX_BRGT],
21800 +      BFD_RELOC_AVR32_22H_PCREL, 1, 0,
21801 +      {
21802 +       &avr32_ifield_table[AVR32_IFIELD_K21],
21803 +      },
21804 +    },
21805 +    {
21806 +      AVR32_OPC_BRLE, 4, 0xe08a0000, 0xe1ef0000,
21807 +      &avr32_syntax_table[AVR32_SYNTAX_BRLE],
21808 +      BFD_RELOC_AVR32_22H_PCREL, 1, 0,
21809 +      {
21810 +       &avr32_ifield_table[AVR32_IFIELD_K21],
21811 +      },
21812 +    },
21813 +    {
21814 +      AVR32_OPC_BRHI, 4, 0xe08b0000, 0xe1ef0000,
21815 +      &avr32_syntax_table[AVR32_SYNTAX_BRHI],
21816 +      BFD_RELOC_AVR32_22H_PCREL, 1, 0,
21817 +      {
21818 +       &avr32_ifield_table[AVR32_IFIELD_K21],
21819 +      },
21820 +    },
21821 +    {
21822 +      AVR32_OPC_BRVS, 4, 0xe08c0000, 0xe1ef0000,
21823 +      &avr32_syntax_table[AVR32_SYNTAX_BRVS],
21824 +      BFD_RELOC_AVR32_22H_PCREL, 1, 0,
21825 +      {
21826 +       &avr32_ifield_table[AVR32_IFIELD_K21],
21827 +      },
21828 +    },
21829 +    {
21830 +      AVR32_OPC_BRVC, 4, 0xe08d0000, 0xe1ef0000,
21831 +      &avr32_syntax_table[AVR32_SYNTAX_BRVC],
21832 +      BFD_RELOC_AVR32_22H_PCREL, 1, 0,
21833 +      {
21834 +       &avr32_ifield_table[AVR32_IFIELD_K21],
21835 +      },
21836 +    },
21837 +    {
21838 +      AVR32_OPC_BRQS, 4, 0xe08e0000, 0xe1ef0000,
21839 +      &avr32_syntax_table[AVR32_SYNTAX_BRQS],
21840 +      BFD_RELOC_AVR32_22H_PCREL, 1, 0,
21841 +      {
21842 +       &avr32_ifield_table[AVR32_IFIELD_K21],
21843 +      },
21844 +    },
21845 +    {
21846 +      AVR32_OPC_BRAL, 4, 0xe08f0000, 0xe1ef0000,
21847 +      &avr32_syntax_table[AVR32_SYNTAX_BRAL],
21848 +      BFD_RELOC_AVR32_22H_PCREL, 1, 0,
21849 +      {
21850 +       &avr32_ifield_table[AVR32_IFIELD_K21],
21851 +      },
21852 +    },
21853 +    {
21854 +      AVR32_OPC_BREAKPOINT, 2, 0xd6730000, 0xffff0000,
21855 +      &avr32_syntax_table[AVR32_SYNTAX_BREAKPOINT],
21856 +      BFD_RELOC_UNUSED, 0, -1, { NULL },
21857 +    },
21858 +    {
21859 +      AVR32_OPC_BREV, 2, 0x5c900000, 0xfff00000,
21860 +      &avr32_syntax_table[AVR32_SYNTAX_BREV],
21861 +      BFD_RELOC_UNUSED, 1, -1,
21862 +      {
21863 +       &avr32_ifield_table[AVR32_IFIELD_RY],
21864 +      },
21865 +    },
21866 +    {
21867 +      AVR32_OPC_BST, 4, 0xefb00000, 0xfff0ffe0,
21868 +      &avr32_syntax_table[AVR32_SYNTAX_BST],
21869 +      BFD_RELOC_UNUSED, 2, -1,
21870 +      {
21871 +       &avr32_ifield_table[AVR32_IFIELD_RY],
21872 +       &avr32_ifield_table[AVR32_IFIELD_K5E],
21873 +      },
21874 +    },
21875 +    {
21876 +      AVR32_OPC_CACHE, 4, 0xf4100000, 0xfff00000,
21877 +      &avr32_syntax_table[AVR32_SYNTAX_CACHE],
21878 +      BFD_RELOC_UNUSED, 3, -1,
21879 +      {
21880 +       &avr32_ifield_table[AVR32_IFIELD_RY],
21881 +       &avr32_ifield_table[AVR32_IFIELD_K11],
21882 +       &avr32_ifield_table[AVR32_IFIELD_CACHEOP],
21883 +      },
21884 +    },
21885 +    {
21886 +      AVR32_OPC_CASTS_B, 2, 0x5c600000, 0xfff00000,
21887 +      &avr32_syntax_table[AVR32_SYNTAX_CASTS_B],
21888 +      BFD_RELOC_UNUSED, 1, -1,
21889 +      {
21890 +       &avr32_ifield_table[AVR32_IFIELD_RY],
21891 +      },
21892 +    },
21893 +    {
21894 +      AVR32_OPC_CASTS_H, 2, 0x5c800000, 0xfff00000,
21895 +      &avr32_syntax_table[AVR32_SYNTAX_CASTS_H],
21896 +      BFD_RELOC_UNUSED, 1, -1,
21897 +      {
21898 +       &avr32_ifield_table[AVR32_IFIELD_RY],
21899 +      },
21900 +    },
21901 +    {
21902 +      AVR32_OPC_CASTU_B, 2, 0x5c500000, 0xfff00000,
21903 +      &avr32_syntax_table[AVR32_SYNTAX_CASTU_B],
21904 +      BFD_RELOC_UNUSED, 1, -1,
21905 +      {
21906 +       &avr32_ifield_table[AVR32_IFIELD_RY],
21907 +      },
21908 +    },
21909 +    {
21910 +      AVR32_OPC_CASTU_H, 2, 0x5c700000, 0xfff00000,
21911 +      &avr32_syntax_table[AVR32_SYNTAX_CASTU_H],
21912 +      BFD_RELOC_UNUSED, 1, -1,
21913 +      {
21914 +       &avr32_ifield_table[AVR32_IFIELD_RY],
21915 +      },
21916 +    },
21917 +    {
21918 +      AVR32_OPC_CBR, 2, 0xa1c00000, 0xe1e00000,
21919 +      &avr32_syntax_table[AVR32_SYNTAX_CBR],
21920 +      BFD_RELOC_UNUSED, 2, -1,
21921 +      {
21922 +       &avr32_ifield_table[AVR32_IFIELD_RY],
21923 +       &avr32_ifield_table[AVR32_IFIELD_BIT5C],
21924 +      },
21925 +    },
21926 +    {
21927 +      AVR32_OPC_CLZ, 4, 0xe0001200, 0xe1f0ffff,
21928 +      &avr32_syntax_table[AVR32_SYNTAX_CLZ],
21929 +      BFD_RELOC_UNUSED, 2, -1,
21930 +      {
21931 +       &avr32_ifield_table[AVR32_IFIELD_RY],
21932 +       &avr32_ifield_table[AVR32_IFIELD_RX],
21933 +      },
21934 +    },
21935 +    {
21936 +      AVR32_OPC_COM, 2, 0x5cd00000, 0xfff00000,
21937 +      &avr32_syntax_table[AVR32_SYNTAX_COM],
21938 +      BFD_RELOC_UNUSED, 1, -1,
21939 +      {
21940 +       &avr32_ifield_table[AVR32_IFIELD_RY],
21941 +      },
21942 +    },
21943 +    {
21944 +      AVR32_OPC_COP, 4, 0xe1a00000, 0xf9f00000,
21945 +      &avr32_syntax_table[AVR32_SYNTAX_COP],
21946 +      BFD_RELOC_UNUSED, 5, -1,
21947 +      {
21948 +       &avr32_ifield_table[AVR32_IFIELD_CPNO],
21949 +       &avr32_ifield_table[AVR32_IFIELD_CRD_RI],
21950 +       &avr32_ifield_table[AVR32_IFIELD_CRX],
21951 +       &avr32_ifield_table[AVR32_IFIELD_CRY],
21952 +       &avr32_ifield_table[AVR32_IFIELD_CPOP],
21953 +      },
21954 +    },
21955 +    {
21956 +      AVR32_OPC_CP_B, 4, 0xe0001800, 0xe1f0ffff,
21957 +      &avr32_syntax_table[AVR32_SYNTAX_CP_B],
21958 +      BFD_RELOC_UNUSED, 2, -1,
21959 +      {
21960 +       &avr32_ifield_table[AVR32_IFIELD_RY],
21961 +       &avr32_ifield_table[AVR32_IFIELD_RX],
21962 +      },
21963 +    },
21964 +    {
21965 +      AVR32_OPC_CP_H, 4, 0xe0001900, 0xe1f0ffff,
21966 +      &avr32_syntax_table[AVR32_SYNTAX_CP_H],
21967 +      BFD_RELOC_UNUSED, 2, -1,
21968 +      {
21969 +       &avr32_ifield_table[AVR32_IFIELD_RY],
21970 +       &avr32_ifield_table[AVR32_IFIELD_RX],
21971 +      },
21972 +    },
21973 +    {
21974 +      AVR32_OPC_CP_W1, 2, 0x00300000, 0xe1f00000,
21975 +      &avr32_syntax_table[AVR32_SYNTAX_CP_W1],
21976 +      BFD_RELOC_UNUSED, 2, -1,
21977 +      {
21978 +       &avr32_ifield_table[AVR32_IFIELD_RY],
21979 +       &avr32_ifield_table[AVR32_IFIELD_RX],
21980 +      },
21981 +    },
21982 +    {
21983 +      AVR32_OPC_CP_W2, 2, 0x58000000, 0xfc000000,
21984 +      &avr32_syntax_table[AVR32_SYNTAX_CP_W2],
21985 +      BFD_RELOC_AVR32_6S, 2, 1,
21986 +      {
21987 +       &avr32_ifield_table[AVR32_IFIELD_RY],
21988 +       &avr32_ifield_table[AVR32_IFIELD_K6],
21989 +      },
21990 +    },
21991 +    {
21992 +      AVR32_OPC_CP_W3, 4, 0xe0400000, 0xe1e00000,
21993 +      &avr32_syntax_table[AVR32_SYNTAX_CP_W3],
21994 +      BFD_RELOC_AVR32_21S, 2, 1,
21995 +      {
21996 +       &avr32_ifield_table[AVR32_IFIELD_RY],
21997 +       &avr32_ifield_table[AVR32_IFIELD_K21],
21998 +      },
21999 +    },
22000 +    {
22001 +      AVR32_OPC_CPC1, 4, 0xe0001300, 0xe1f0ffff,
22002 +      &avr32_syntax_table[AVR32_SYNTAX_CPC1],
22003 +      BFD_RELOC_UNUSED, 2, -1,
22004 +      {
22005 +       &avr32_ifield_table[AVR32_IFIELD_RY],
22006 +       &avr32_ifield_table[AVR32_IFIELD_RX],
22007 +      },
22008 +    },
22009 +    {
22010 +      AVR32_OPC_CPC2, 2, 0x5c200000, 0xfff00000,
22011 +      &avr32_syntax_table[AVR32_SYNTAX_CPC2],
22012 +      BFD_RELOC_UNUSED, 1, -1,
22013 +      {
22014 +       &avr32_ifield_table[AVR32_IFIELD_RY],
22015 +      },
22016 +    },
22017 +    {
22018 +      AVR32_OPC_CSRF, 2, 0xd4030000, 0xfe0f0000,
22019 +      &avr32_syntax_table[AVR32_SYNTAX_CSRF],
22020 +      BFD_RELOC_UNUSED, 1, -1,
22021 +      {
22022 +       &avr32_ifield_table[AVR32_IFIELD_K5C],
22023 +      },
22024 +    },
22025 +    {
22026 +      AVR32_OPC_CSRFCZ, 2, 0xd0030000, 0xfe0f0000,
22027 +      &avr32_syntax_table[AVR32_SYNTAX_CSRFCZ],
22028 +      BFD_RELOC_UNUSED, 1, -1,
22029 +      {
22030 +       &avr32_ifield_table[AVR32_IFIELD_K5C],
22031 +      },
22032 +    },
22033 +    {
22034 +      AVR32_OPC_DIVS, 4, 0xe0000c00, 0xe1f0ffc0,
22035 +      &avr32_syntax_table[AVR32_SYNTAX_DIVS],
22036 +      BFD_RELOC_UNUSED, 3, -1,
22037 +      {
22038 +       &avr32_ifield_table[AVR32_IFIELD_RD_E],
22039 +       &avr32_ifield_table[AVR32_IFIELD_RX],
22040 +       &avr32_ifield_table[AVR32_IFIELD_RY],
22041 +      },
22042 +    },
22043 +    {
22044 +      AVR32_OPC_DIVU, 4, 0xe0000d00, 0xe1f0ffc0,
22045 +      &avr32_syntax_table[AVR32_SYNTAX_DIVU],
22046 +      BFD_RELOC_UNUSED, 3, -1,
22047 +      {
22048 +       &avr32_ifield_table[AVR32_IFIELD_RD_E],
22049 +       &avr32_ifield_table[AVR32_IFIELD_RX],
22050 +       &avr32_ifield_table[AVR32_IFIELD_RY],
22051 +      },
22052 +    },
22053 +    {
22054 +      AVR32_OPC_EOR1, 2, 0x00500000, 0xe1f00000,
22055 +      &avr32_syntax_table[AVR32_SYNTAX_EOR1],
22056 +      BFD_RELOC_UNUSED, 2, -1,
22057 +      {
22058 +       &avr32_ifield_table[AVR32_IFIELD_RY],
22059 +       &avr32_ifield_table[AVR32_IFIELD_RX],
22060 +      },
22061 +    },
22062 +    {
22063 +      AVR32_OPC_EOR2, 4, 0xe1e02000, 0xe1f0fe00,
22064 +      &avr32_syntax_table[AVR32_SYNTAX_EOR2],
22065 +      BFD_RELOC_UNUSED, 4, -1,
22066 +      {
22067 +       &avr32_ifield_table[AVR32_IFIELD_RD_E],
22068 +       &avr32_ifield_table[AVR32_IFIELD_RX],
22069 +       &avr32_ifield_table[AVR32_IFIELD_RY],
22070 +       &avr32_ifield_table[AVR32_IFIELD_K5E2],
22071 +      }
22072 +    },
22073 +    {
22074 +      AVR32_OPC_EOR3, 4, 0xe1e02200, 0xe1f0fe00,
22075 +      &avr32_syntax_table[AVR32_SYNTAX_EOR3],
22076 +      BFD_RELOC_UNUSED, 4, -1,
22077 +      {
22078 +       &avr32_ifield_table[AVR32_IFIELD_RD_E],
22079 +       &avr32_ifield_table[AVR32_IFIELD_RX],
22080 +       &avr32_ifield_table[AVR32_IFIELD_RY],
22081 +       &avr32_ifield_table[AVR32_IFIELD_K5E2],
22082 +      }
22083 +    },
22084 +    {
22085 +      AVR32_OPC_EORL, 4, 0xec100000, 0xfff00000,
22086 +      &avr32_syntax_table[AVR32_SYNTAX_EORL],
22087 +      BFD_RELOC_AVR32_16U, 2, 1,
22088 +      {
22089 +       &avr32_ifield_table[AVR32_IFIELD_RY],
22090 +       &avr32_ifield_table[AVR32_IFIELD_K16],
22091 +      },
22092 +    },
22093 +    {
22094 +      AVR32_OPC_EORH, 4, 0xee100000, 0xfff00000,
22095 +      &avr32_syntax_table[AVR32_SYNTAX_EORH],
22096 +      BFD_RELOC_AVR32_16U, 2, 1,
22097 +      {
22098 +       &avr32_ifield_table[AVR32_IFIELD_RY],
22099 +       &avr32_ifield_table[AVR32_IFIELD_K16],
22100 +      },
22101 +    },
22102 +    {
22103 +      AVR32_OPC_FRS, 2, 0xd7430000, 0xffff0000,
22104 +      &avr32_syntax_table[AVR32_SYNTAX_FRS],
22105 +      BFD_RELOC_UNUSED, 0, -1, { NULL },
22106 +    },
22107 +    {
22108 +      AVR32_OPC_ICALL, 2, 0x5d100000, 0xfff00000,
22109 +      &avr32_syntax_table[AVR32_SYNTAX_ICALL],
22110 +      BFD_RELOC_UNUSED, 1, -1,
22111 +      {
22112 +       &avr32_ifield_table[AVR32_IFIELD_RY],
22113 +      },
22114 +    },
22115 +    {
22116 +      AVR32_OPC_INCJOSP, 2, 0xd6830000, 0xff8f0000,
22117 +      &avr32_syntax_table[AVR32_SYNTAX_INCJOSP],
22118 +      BFD_RELOC_UNUSED, 1, -1,
22119 +      {
22120 +       &avr32_ifield_table[AVR32_IFIELD_K3],
22121 +      },
22122 +    },
22123 +    {
22124 +      AVR32_OPC_LD_D1, 2, 0xa1010000, 0xe1f10000,
22125 +      &avr32_syntax_table[AVR32_SYNTAX_LD_D1],
22126 +      BFD_RELOC_UNUSED, 2, -1,
22127 +      {
22128 +       &avr32_ifield_table[AVR32_IFIELD_RY_DW],
22129 +       &avr32_ifield_table[AVR32_IFIELD_RX],
22130 +      },
22131 +    },
22132 +    {
22133 +      AVR32_OPC_LD_D2, 2, 0xa1100000, 0xe1f10000,
22134 +      &avr32_syntax_table[AVR32_SYNTAX_LD_D2],
22135 +      BFD_RELOC_UNUSED, 2, -1,
22136 +      {
22137 +       &avr32_ifield_table[AVR32_IFIELD_RY_DW],
22138 +       &avr32_ifield_table[AVR32_IFIELD_RX],
22139 +      },
22140 +    },
22141 +    {
22142 +      AVR32_OPC_LD_D3, 2, 0xa1000000, 0xe1f10000,
22143 +      &avr32_syntax_table[AVR32_SYNTAX_LD_D3],
22144 +      BFD_RELOC_UNUSED, 2, -1,
22145 +      {
22146 +       &avr32_ifield_table[AVR32_IFIELD_RY_DW],
22147 +       &avr32_ifield_table[AVR32_IFIELD_RX],
22148 +      },
22149 +    },
22150 +    {
22151 +      AVR32_OPC_LD_D5, 4, 0xe0000200, 0xe1f0ffc1,
22152 +      &avr32_syntax_table[AVR32_SYNTAX_LD_D5],
22153 +      BFD_RELOC_UNUSED, 4, -1,
22154 +      {
22155 +       &avr32_ifield_table[AVR32_IFIELD_RD_DW],
22156 +       &avr32_ifield_table[AVR32_IFIELD_RX],
22157 +       &avr32_ifield_table[AVR32_IFIELD_RY],
22158 +       &avr32_ifield_table[AVR32_IFIELD_K2],
22159 +      },
22160 +    },
22161 +    {
22162 +      AVR32_OPC_LD_D4, 4, 0xe0e00000, 0xe1f10000,
22163 +      &avr32_syntax_table[AVR32_SYNTAX_LD_D4],
22164 +      BFD_RELOC_AVR32_16S, 3, 2,
22165 +      {
22166 +       &avr32_ifield_table[AVR32_IFIELD_RY_DW],
22167 +       &avr32_ifield_table[AVR32_IFIELD_RX],
22168 +       &avr32_ifield_table[AVR32_IFIELD_K16],
22169 +      },
22170 +    },
22171 +    {
22172 +      AVR32_OPC_LD_SB2, 4, 0xe0000600, 0xe1f0ffc0,
22173 +      &avr32_syntax_table[AVR32_SYNTAX_LD_SB2],
22174 +      BFD_RELOC_UNUSED, 4, -1,
22175 +      {
22176 +       &avr32_ifield_table[AVR32_IFIELD_RD_E],
22177 +       &avr32_ifield_table[AVR32_IFIELD_RX],
22178 +       &avr32_ifield_table[AVR32_IFIELD_RY],
22179 +       &avr32_ifield_table[AVR32_IFIELD_K2],
22180 +      },
22181 +    },
22182 +    {
22183 +      AVR32_OPC_LD_SB1, 4, 0xe1200000, 0xe1f00000,
22184 +      &avr32_syntax_table[AVR32_SYNTAX_LD_SB1],
22185 +      BFD_RELOC_AVR32_16S, 3, -1,
22186 +      {
22187 +       &avr32_ifield_table[AVR32_IFIELD_RY],
22188 +       &avr32_ifield_table[AVR32_IFIELD_RX],
22189 +       &avr32_ifield_table[AVR32_IFIELD_K16],
22190 +      },
22191 +    },
22192 +    {
22193 +      AVR32_OPC_LD_UB1, 2, 0x01300000, 0xe1f00000,
22194 +      &avr32_syntax_table[AVR32_SYNTAX_LD_UB1],
22195 +      BFD_RELOC_UNUSED, 2, -1,
22196 +      {
22197 +       &avr32_ifield_table[AVR32_IFIELD_RY],
22198 +       &avr32_ifield_table[AVR32_IFIELD_RX],
22199 +      },
22200 +    },
22201 +    {
22202 +      AVR32_OPC_LD_UB2, 2, 0x01700000, 0xe1f00000,
22203 +      &avr32_syntax_table[AVR32_SYNTAX_LD_UB2],
22204 +      BFD_RELOC_UNUSED, 2, -1,
22205 +      {
22206 +       &avr32_ifield_table[AVR32_IFIELD_RY],
22207 +       &avr32_ifield_table[AVR32_IFIELD_RX],
22208 +      },
22209 +    },
22210 +    {
22211 +      AVR32_OPC_LD_UB5, 4, 0xe0000700, 0xe1f0ffc0,
22212 +      &avr32_syntax_table[AVR32_SYNTAX_LD_UB5],
22213 +      BFD_RELOC_UNUSED, 4, -1,
22214 +      {
22215 +       &avr32_ifield_table[AVR32_IFIELD_RD_E],
22216 +       &avr32_ifield_table[AVR32_IFIELD_RX],
22217 +       &avr32_ifield_table[AVR32_IFIELD_RY],
22218 +       &avr32_ifield_table[AVR32_IFIELD_K2],
22219 +      },
22220 +    },
22221 +    {
22222 +      AVR32_OPC_LD_UB3, 2, 0x01800000, 0xe1800000,
22223 +      &avr32_syntax_table[AVR32_SYNTAX_LD_UB3],
22224 +      BFD_RELOC_AVR32_3U, 3, 2,
22225 +      {
22226 +       &avr32_ifield_table[AVR32_IFIELD_RY],
22227 +       &avr32_ifield_table[AVR32_IFIELD_RX],
22228 +       &avr32_ifield_table[AVR32_IFIELD_K3],
22229 +      },
22230 +    },
22231 +    {
22232 +      AVR32_OPC_LD_UB4, 4, 0xe1300000, 0xe1f00000,
22233 +      &avr32_syntax_table[AVR32_SYNTAX_LD_UB4],
22234 +      BFD_RELOC_AVR32_16S, 3, 2,
22235 +      {
22236 +       &avr32_ifield_table[AVR32_IFIELD_RY],
22237 +       &avr32_ifield_table[AVR32_IFIELD_RX],
22238 +       &avr32_ifield_table[AVR32_IFIELD_K16],
22239 +      },
22240 +    },
22241 +    {
22242 +      AVR32_OPC_LD_SH1, 2, 0x01100000, 0xe1f00000,
22243 +      &avr32_syntax_table[AVR32_SYNTAX_LD_SH1],
22244 +      BFD_RELOC_UNUSED, 2, -1,
22245 +      {
22246 +       &avr32_ifield_table[AVR32_IFIELD_RY],
22247 +       &avr32_ifield_table[AVR32_IFIELD_RX],
22248 +      },
22249 +    },
22250 +    {
22251 +      AVR32_OPC_LD_SH2, 2, 0x01500000, 0xe1f00000,
22252 +      &avr32_syntax_table[AVR32_SYNTAX_LD_SH2],
22253 +      BFD_RELOC_UNUSED, 2, -1,
22254 +      {
22255 +       &avr32_ifield_table[AVR32_IFIELD_RY],
22256 +       &avr32_ifield_table[AVR32_IFIELD_RX],
22257 +      },
22258 +    },
22259 +    {
22260 +      AVR32_OPC_LD_SH5, 4, 0xe0000400, 0xe1f0ffc0,
22261 +      &avr32_syntax_table[AVR32_SYNTAX_LD_SH5],
22262 +      BFD_RELOC_UNUSED, 4, -1,
22263 +      {
22264 +       &avr32_ifield_table[AVR32_IFIELD_RD_E],
22265 +       &avr32_ifield_table[AVR32_IFIELD_RX],
22266 +       &avr32_ifield_table[AVR32_IFIELD_RY],
22267 +       &avr32_ifield_table[AVR32_IFIELD_K2],
22268 +      },
22269 +    },
22270 +    {
22271 +      AVR32_OPC_LD_SH3, 2, 0x80000000, 0xe1800000,
22272 +      &avr32_syntax_table[AVR32_SYNTAX_LD_SH3],
22273 +      BFD_RELOC_AVR32_4UH, 3, 2,
22274 +      {
22275 +       &avr32_ifield_table[AVR32_IFIELD_RY],
22276 +       &avr32_ifield_table[AVR32_IFIELD_RX],
22277 +       &avr32_ifield_table[AVR32_IFIELD_K3],
22278 +      },
22279 +    },
22280 +    {
22281 +      AVR32_OPC_LD_SH4, 4, 0xe1000000, 0xe1f00000,
22282 +      &avr32_syntax_table[AVR32_SYNTAX_LD_SH4],
22283 +      BFD_RELOC_AVR32_16S, 3, 2,
22284 +      {
22285 +       &avr32_ifield_table[AVR32_IFIELD_RY],
22286 +       &avr32_ifield_table[AVR32_IFIELD_RX],
22287 +       &avr32_ifield_table[AVR32_IFIELD_K16],
22288 +      },
22289 +    },
22290 +    {
22291 +      AVR32_OPC_LD_UH1, 2, 0x01200000, 0xe1f00000,
22292 +      &avr32_syntax_table[AVR32_SYNTAX_LD_UH1],
22293 +      BFD_RELOC_UNUSED, 2, -1,
22294 +      {
22295 +       &avr32_ifield_table[AVR32_IFIELD_RY],
22296 +       &avr32_ifield_table[AVR32_IFIELD_RX],
22297 +      },
22298 +    },
22299 +    {
22300 +      AVR32_OPC_LD_UH2, 2, 0x01600000, 0xe1f00000,
22301 +      &avr32_syntax_table[AVR32_SYNTAX_LD_UH2],
22302 +      BFD_RELOC_UNUSED, 2, -1,
22303 +      {
22304 +       &avr32_ifield_table[AVR32_IFIELD_RY],
22305 +       &avr32_ifield_table[AVR32_IFIELD_RX],
22306 +      },
22307 +    },
22308 +    {
22309 +      AVR32_OPC_LD_UH5, 4, 0xe0000500, 0xe1f0ffc0,
22310 +      &avr32_syntax_table[AVR32_SYNTAX_LD_UH5],
22311 +      BFD_RELOC_UNUSED, 4, -1,
22312 +      {
22313 +       &avr32_ifield_table[AVR32_IFIELD_RD_E],
22314 +       &avr32_ifield_table[AVR32_IFIELD_RX],
22315 +       &avr32_ifield_table[AVR32_IFIELD_RY],
22316 +       &avr32_ifield_table[AVR32_IFIELD_K2],
22317 +      },
22318 +    },
22319 +    {
22320 +      AVR32_OPC_LD_UH3, 2, 0x80800000, 0xe1800000,
22321 +      &avr32_syntax_table[AVR32_SYNTAX_LD_UH3],
22322 +      BFD_RELOC_AVR32_4UH, 3, 2,
22323 +      {
22324 +       &avr32_ifield_table[AVR32_IFIELD_RY],
22325 +       &avr32_ifield_table[AVR32_IFIELD_RX],
22326 +       &avr32_ifield_table[AVR32_IFIELD_K3],
22327 +      },
22328 +    },
22329 +    {
22330 +      AVR32_OPC_LD_UH4, 4, 0xe1100000, 0xe1f00000,
22331 +      &avr32_syntax_table[AVR32_SYNTAX_LD_UH4],
22332 +      BFD_RELOC_AVR32_16S, 3, 2,
22333 +      {
22334 +       &avr32_ifield_table[AVR32_IFIELD_RY],
22335 +       &avr32_ifield_table[AVR32_IFIELD_RX],
22336 +       &avr32_ifield_table[AVR32_IFIELD_K16],
22337 +      },
22338 +    },
22339 +    {
22340 +      AVR32_OPC_LD_W1, 2, 0x01000000, 0xe1f00000,
22341 +      &avr32_syntax_table[AVR32_SYNTAX_LD_W1],
22342 +      BFD_RELOC_UNUSED, 2, -1,
22343 +      {
22344 +       &avr32_ifield_table[AVR32_IFIELD_RY],
22345 +       &avr32_ifield_table[AVR32_IFIELD_RX],
22346 +      },
22347 +    },
22348 +    {
22349 +      AVR32_OPC_LD_W2, 2, 0x01400000, 0xe1f00000,
22350 +      &avr32_syntax_table[AVR32_SYNTAX_LD_W2],
22351 +      BFD_RELOC_UNUSED, 2, -1,
22352 +      {
22353 +       &avr32_ifield_table[AVR32_IFIELD_RY],
22354 +       &avr32_ifield_table[AVR32_IFIELD_RX],
22355 +      },
22356 +    },
22357 +    {
22358 +      AVR32_OPC_LD_W5, 4, 0xe0000300, 0xe1f0ffc0,
22359 +      &avr32_syntax_table[AVR32_SYNTAX_LD_W5],
22360 +      BFD_RELOC_UNUSED, 4, -1,
22361 +      {
22362 +       &avr32_ifield_table[AVR32_IFIELD_RD_E],
22363 +       &avr32_ifield_table[AVR32_IFIELD_RX],
22364 +       &avr32_ifield_table[AVR32_IFIELD_RY],
22365 +       &avr32_ifield_table[AVR32_IFIELD_K2],
22366 +      },
22367 +    },
22368 +    {
22369 +      AVR32_OPC_LD_W6, 4, 0xe0000f80, 0xe1f0ffc0,
22370 +      &avr32_syntax_table[AVR32_SYNTAX_LD_W6],
22371 +      BFD_RELOC_UNUSED, 4, -1,
22372 +      {
22373 +       &avr32_ifield_table[AVR32_IFIELD_RD_E],
22374 +       &avr32_ifield_table[AVR32_IFIELD_RX],
22375 +       &avr32_ifield_table[AVR32_IFIELD_RY],
22376 +       &avr32_ifield_table[AVR32_IFIELD_K2],
22377 +      },
22378 +    },
22379 +    {
22380 +      AVR32_OPC_LD_W3, 2, 0x60000000, 0xe0000000,
22381 +      &avr32_syntax_table[AVR32_SYNTAX_LD_W3],
22382 +      BFD_RELOC_AVR32_7UW, 3, 2,
22383 +      {
22384 +       &avr32_ifield_table[AVR32_IFIELD_RY],
22385 +       &avr32_ifield_table[AVR32_IFIELD_RX],
22386 +       &avr32_ifield_table[AVR32_IFIELD_K5C],
22387 +      },
22388 +    },
22389 +    {
22390 +      AVR32_OPC_LD_W4, 4, 0xe0f00000, 0xe1f00000,
22391 +      &avr32_syntax_table[AVR32_SYNTAX_LD_W4],
22392 +      BFD_RELOC_AVR32_16S, 3, 2,
22393 +      {
22394 +       &avr32_ifield_table[AVR32_IFIELD_RY],
22395 +       &avr32_ifield_table[AVR32_IFIELD_RX],
22396 +       &avr32_ifield_table[AVR32_IFIELD_K16],
22397 +      },
22398 +    },
22399 +    {
22400 +      AVR32_OPC_LDC_D1, 4, 0xe9a01000, 0xfff01100,
22401 +      &avr32_syntax_table[AVR32_SYNTAX_LDC_D1],
22402 +      BFD_RELOC_AVR32_10UW, 4, 3,
22403 +      {
22404 +       &avr32_ifield_table[AVR32_IFIELD_CPNO],
22405 +       &avr32_ifield_table[AVR32_IFIELD_CRD_DW],
22406 +       &avr32_ifield_table[AVR32_IFIELD_RY],
22407 +       &avr32_ifield_table[AVR32_IFIELD_K8E],
22408 +      },
22409 +    },
22410 +    {
22411 +      AVR32_OPC_LDC_D2, 4, 0xefa00050, 0xfff011ff,
22412 +      &avr32_syntax_table[AVR32_SYNTAX_LDC_D2],
22413 +      BFD_RELOC_UNUSED, 3, -1,
22414 +      {
22415 +       &avr32_ifield_table[AVR32_IFIELD_CPNO],
22416 +       &avr32_ifield_table[AVR32_IFIELD_CRD_DW],
22417 +       &avr32_ifield_table[AVR32_IFIELD_RY],
22418 +      },
22419 +    },
22420 +    {
22421 +      AVR32_OPC_LDC_D3, 4, 0xefa01040, 0xfff011c0,
22422 +      &avr32_syntax_table[AVR32_SYNTAX_LDC_D3],
22423 +      BFD_RELOC_UNUSED, 5, -1,
22424 +      {
22425 +       &avr32_ifield_table[AVR32_IFIELD_CPNO],
22426 +       &avr32_ifield_table[AVR32_IFIELD_CRD_DW],
22427 +       &avr32_ifield_table[AVR32_IFIELD_RY],
22428 +       &avr32_ifield_table[AVR32_IFIELD_RD_E],
22429 +       &avr32_ifield_table[AVR32_IFIELD_K2],
22430 +      },
22431 +    },
22432 +    {
22433 +      AVR32_OPC_LDC_W1, 4, 0xe9a00000, 0xfff01000,
22434 +      &avr32_syntax_table[AVR32_SYNTAX_LDC_W1],
22435 +      BFD_RELOC_AVR32_10UW, 4, 3,
22436 +      {
22437 +       &avr32_ifield_table[AVR32_IFIELD_CPNO],
22438 +       &avr32_ifield_table[AVR32_IFIELD_CRD_RI],
22439 +       &avr32_ifield_table[AVR32_IFIELD_RY],
22440 +       &avr32_ifield_table[AVR32_IFIELD_K8E],
22441 +      },
22442 +    },
22443 +    {
22444 +      AVR32_OPC_LDC_W2, 4, 0xefa00040, 0xfff010ff,
22445 +      &avr32_syntax_table[AVR32_SYNTAX_LDC_W2],
22446 +      BFD_RELOC_UNUSED, 3, -1,
22447 +      {
22448 +       &avr32_ifield_table[AVR32_IFIELD_CPNO],
22449 +       &avr32_ifield_table[AVR32_IFIELD_CRD_RI],
22450 +       &avr32_ifield_table[AVR32_IFIELD_RY],
22451 +      },
22452 +    },
22453 +    {
22454 +      AVR32_OPC_LDC_W3, 4, 0xefa01000, 0xfff010c0,
22455 +      &avr32_syntax_table[AVR32_SYNTAX_LDC_W3],
22456 +      BFD_RELOC_UNUSED, 5, -1,
22457 +      {
22458 +       &avr32_ifield_table[AVR32_IFIELD_CPNO],
22459 +       &avr32_ifield_table[AVR32_IFIELD_CRD_RI],
22460 +       &avr32_ifield_table[AVR32_IFIELD_RY],
22461 +       &avr32_ifield_table[AVR32_IFIELD_RD_E],
22462 +       &avr32_ifield_table[AVR32_IFIELD_K2],
22463 +      },
22464 +    },
22465 +    {
22466 +      AVR32_OPC_LDC0_D, 4, 0xf3a00000, 0xfff00100,
22467 +      &avr32_syntax_table[AVR32_SYNTAX_LDC0_D],
22468 +      BFD_RELOC_AVR32_14UW, 3, 2,
22469 +      {
22470 +       &avr32_ifield_table[AVR32_IFIELD_CRD_DW],
22471 +       &avr32_ifield_table[AVR32_IFIELD_RY],
22472 +       &avr32_ifield_table[AVR32_IFIELD_K12CP],
22473 +      },
22474 +    },
22475 +    {
22476 +      AVR32_OPC_LDC0_W, 4, 0xf1a00000, 0xfff00000,
22477 +      &avr32_syntax_table[AVR32_SYNTAX_LDC0_W],
22478 +      BFD_RELOC_AVR32_14UW, 3, 2,
22479 +      {
22480 +       &avr32_ifield_table[AVR32_IFIELD_CRD_RI],
22481 +       &avr32_ifield_table[AVR32_IFIELD_RY],
22482 +       &avr32_ifield_table[AVR32_IFIELD_K12CP],
22483 +      },
22484 +    },
22485 +    {
22486 +      AVR32_OPC_LDCM_D, 4, 0xeda00400, 0xfff01f00,
22487 +      &avr32_syntax_table[AVR32_SYNTAX_LDCM_D],
22488 +      BFD_RELOC_UNUSED, 3, -1,
22489 +      {
22490 +       &avr32_ifield_table[AVR32_IFIELD_CPNO],
22491 +       &avr32_ifield_table[AVR32_IFIELD_RY],
22492 +       &avr32_ifield_table[AVR32_IFIELD_K8E],
22493 +      },
22494 +    },
22495 +    {
22496 +      AVR32_OPC_LDCM_D_PU, 4, 0xeda01400, 0xfff01f00,
22497 +      &avr32_syntax_table[AVR32_SYNTAX_LDCM_D_PU],
22498 +      BFD_RELOC_UNUSED, 3, -1,
22499 +      {
22500 +       &avr32_ifield_table[AVR32_IFIELD_CPNO],
22501 +       &avr32_ifield_table[AVR32_IFIELD_RY],
22502 +       &avr32_ifield_table[AVR32_IFIELD_K8E],
22503 +      },
22504 +    },
22505 +    {
22506 +      AVR32_OPC_LDCM_W, 4, 0xeda00000, 0xfff01e00,
22507 +      &avr32_syntax_table[AVR32_SYNTAX_LDCM_W],
22508 +      BFD_RELOC_UNUSED, 4, -1,
22509 +      {
22510 +       &avr32_ifield_table[AVR32_IFIELD_CPNO],
22511 +       &avr32_ifield_table[AVR32_IFIELD_RY],
22512 +       &avr32_ifield_table[AVR32_IFIELD_K8E],
22513 +       &avr32_ifield_table[AVR32_IFIELD_CM_HL],
22514 +      },
22515 +    },
22516 +    {
22517 +      AVR32_OPC_LDCM_W_PU, 4, 0xeda01000, 0xfff01e00,
22518 +      &avr32_syntax_table[AVR32_SYNTAX_LDCM_W_PU],
22519 +      BFD_RELOC_UNUSED, 4, -1,
22520 +      {
22521 +       &avr32_ifield_table[AVR32_IFIELD_CPNO],
22522 +       &avr32_ifield_table[AVR32_IFIELD_RY],
22523 +       &avr32_ifield_table[AVR32_IFIELD_K8E],
22524 +       &avr32_ifield_table[AVR32_IFIELD_CM_HL],
22525 +      },
22526 +    },
22527 +    {
22528 +      AVR32_OPC_LDDPC, 2, 0x48000000, 0xf8000000,
22529 +      &avr32_syntax_table[AVR32_SYNTAX_LDDPC],
22530 +      BFD_RELOC_AVR32_9UW_PCREL, 2, 1,
22531 +      {
22532 +       &avr32_ifield_table[AVR32_IFIELD_RY],
22533 +       &avr32_ifield_table[AVR32_IFIELD_K7C],
22534 +      },
22535 +    },
22536 +    {
22537 +      AVR32_OPC_LDDPC_EXT, 4, 0xfef00000, 0xfff00000,
22538 +      &avr32_syntax_table[AVR32_SYNTAX_LDDPC_EXT],
22539 +      BFD_RELOC_AVR32_16B_PCREL, 2, 1,
22540 +      {
22541 +       &avr32_ifield_table[AVR32_IFIELD_RY],
22542 +       &avr32_ifield_table[AVR32_IFIELD_K16],
22543 +      },
22544 +    },
22545 +    {
22546 +      AVR32_OPC_LDDSP, 2, 0x40000000, 0xf8000000,
22547 +      &avr32_syntax_table[AVR32_SYNTAX_LDDSP],
22548 +      BFD_RELOC_UNUSED, 2, -1,
22549 +      {
22550 +       &avr32_ifield_table[AVR32_IFIELD_RY],
22551 +       &avr32_ifield_table[AVR32_IFIELD_K7C],
22552 +      },
22553 +    },
22554 +    {
22555 +      AVR32_OPC_LDINS_B, 4, 0xe1d04000, 0xe1f0c000,
22556 +      &avr32_syntax_table[AVR32_SYNTAX_LDINS_B],
22557 +      BFD_RELOC_UNUSED, 4, -1,
22558 +      {
22559 +       &avr32_ifield_table[AVR32_IFIELD_RY],
22560 +       &avr32_ifield_table[AVR32_IFIELD_PART2_K12],
22561 +       &avr32_ifield_table[AVR32_IFIELD_RX],
22562 +       &avr32_ifield_table[AVR32_IFIELD_K12],
22563 +      },
22564 +    },
22565 +    {
22566 +      AVR32_OPC_LDINS_H, 4, 0xe1d00000, 0xe1f0e000,
22567 +      &avr32_syntax_table[AVR32_SYNTAX_LDINS_H],
22568 +      BFD_RELOC_UNUSED, 4, -1,
22569 +      {
22570 +       &avr32_ifield_table[AVR32_IFIELD_RY],
22571 +       &avr32_ifield_table[AVR32_IFIELD_PART1_K12],
22572 +       &avr32_ifield_table[AVR32_IFIELD_RX],
22573 +       &avr32_ifield_table[AVR32_IFIELD_K12],
22574 +      },
22575 +    },
22576 +    {
22577 +      AVR32_OPC_LDM, 4, 0xe1c00000, 0xfdf00000,
22578 +      &avr32_syntax_table[AVR32_SYNTAX_LDM],
22579 +      BFD_RELOC_UNUSED, 3, -1,
22580 +      {
22581 +       &avr32_ifield_table[AVR32_IFIELD_RY],
22582 +       &avr32_ifield_table[AVR32_IFIELD_W],
22583 +       &avr32_ifield_table[AVR32_IFIELD_K16],
22584 +      },
22585 +    },
22586 +    {
22587 +      AVR32_OPC_LDMTS, 4, 0xe5c00000, 0xfff00000,
22588 +      &avr32_syntax_table[AVR32_SYNTAX_LDMTS],
22589 +      BFD_RELOC_UNUSED, 2, -1,
22590 +      {
22591 +       &avr32_ifield_table[AVR32_IFIELD_RY],
22592 +       &avr32_ifield_table[AVR32_IFIELD_K16],
22593 +      },
22594 +    },
22595 +    {
22596 +      AVR32_OPC_LDMTS_PU, 4, 0xe7c00000, 0xfff00000,
22597 +      &avr32_syntax_table[AVR32_SYNTAX_LDMTS_PU],
22598 +      BFD_RELOC_UNUSED, 2, -1,
22599 +      {
22600 +       &avr32_ifield_table[AVR32_IFIELD_RY],
22601 +       &avr32_ifield_table[AVR32_IFIELD_K16],
22602 +      },
22603 +    },
22604 +    {
22605 +      AVR32_OPC_LDSWP_SH, 4, 0xe1d02000, 0xe1f0f000,
22606 +      &avr32_syntax_table[AVR32_SYNTAX_LDSWP_SH],
22607 +      BFD_RELOC_UNUSED, 3, -1,
22608 +      {
22609 +       &avr32_ifield_table[AVR32_IFIELD_RY],
22610 +       &avr32_ifield_table[AVR32_IFIELD_RX],
22611 +       &avr32_ifield_table[AVR32_IFIELD_K12],
22612 +      },
22613 +    },
22614 +    {
22615 +      AVR32_OPC_LDSWP_UH, 4, 0xe1d03000, 0xe1f0f000,
22616 +      &avr32_syntax_table[AVR32_SYNTAX_LDSWP_UH],
22617 +      BFD_RELOC_UNUSED, 3, -1,
22618 +      {
22619 +       &avr32_ifield_table[AVR32_IFIELD_RY],
22620 +       &avr32_ifield_table[AVR32_IFIELD_RX],
22621 +       &avr32_ifield_table[AVR32_IFIELD_K12],
22622 +      },
22623 +    },
22624 +    {
22625 +      AVR32_OPC_LDSWP_W, 4, 0xe1d08000, 0xe1f0f000,
22626 +      &avr32_syntax_table[AVR32_SYNTAX_LDSWP_W],
22627 +      BFD_RELOC_UNUSED, 3, -1,
22628 +      {
22629 +       &avr32_ifield_table[AVR32_IFIELD_RY],
22630 +       &avr32_ifield_table[AVR32_IFIELD_RX],
22631 +       &avr32_ifield_table[AVR32_IFIELD_K12],
22632 +      },
22633 +    },
22634 +    {
22635 +      AVR32_OPC_LSL1, 4, 0xe0000940, 0xe1f0fff0,
22636 +      &avr32_syntax_table[AVR32_SYNTAX_LSL1],
22637 +      BFD_RELOC_UNUSED, 3, -1,
22638 +      {
22639 +       &avr32_ifield_table[AVR32_IFIELD_RD_E],
22640 +       &avr32_ifield_table[AVR32_IFIELD_RX],
22641 +       &avr32_ifield_table[AVR32_IFIELD_RY],
22642 +      },
22643 +    },
22644 +    {
22645 +      AVR32_OPC_LSL3, 4, 0xe0001500, 0xe1f0ffe0,
22646 +      &avr32_syntax_table[AVR32_SYNTAX_LSL3],
22647 +      BFD_RELOC_UNUSED, 3, -1,
22648 +      {
22649 +       &avr32_ifield_table[AVR32_IFIELD_RY],
22650 +       &avr32_ifield_table[AVR32_IFIELD_RX],
22651 +       &avr32_ifield_table[AVR32_IFIELD_K5E],
22652 +      },
22653 +    },
22654 +    {
22655 +      AVR32_OPC_LSL2, 2, 0xa1600000, 0xe1e00000,
22656 +      &avr32_syntax_table[AVR32_SYNTAX_LSL2],
22657 +      BFD_RELOC_UNUSED, 2, -1,
22658 +      {
22659 +       &avr32_ifield_table[AVR32_IFIELD_RY],
22660 +       &avr32_ifield_table[AVR32_IFIELD_BIT5C],
22661 +      },
22662 +    },
22663 +    {
22664 +      AVR32_OPC_LSR1, 4, 0xe0000a40, 0xe1f0fff0,
22665 +      &avr32_syntax_table[AVR32_SYNTAX_LSR1],
22666 +      BFD_RELOC_UNUSED, 3, -1,
22667 +      {
22668 +       &avr32_ifield_table[AVR32_IFIELD_RD_E],
22669 +       &avr32_ifield_table[AVR32_IFIELD_RX],
22670 +       &avr32_ifield_table[AVR32_IFIELD_RY],
22671 +      },
22672 +    },
22673 +    {
22674 +      AVR32_OPC_LSR3, 4, 0xe0001600, 0xe1f0ffe0,
22675 +      &avr32_syntax_table[AVR32_SYNTAX_LSR3],
22676 +      BFD_RELOC_UNUSED, 3, -1,
22677 +      {
22678 +       &avr32_ifield_table[AVR32_IFIELD_RY],
22679 +       &avr32_ifield_table[AVR32_IFIELD_RX],
22680 +       &avr32_ifield_table[AVR32_IFIELD_K5E],
22681 +      },
22682 +    },
22683 +    {
22684 +      AVR32_OPC_LSR2, 2, 0xa1800000, 0xe1e00000,
22685 +      &avr32_syntax_table[AVR32_SYNTAX_LSR2],
22686 +      BFD_RELOC_UNUSED, 2, -1,
22687 +      {
22688 +       &avr32_ifield_table[AVR32_IFIELD_RY],
22689 +       &avr32_ifield_table[AVR32_IFIELD_BIT5C],
22690 +      },
22691 +    },
22692 +    {
22693 +      AVR32_OPC_MAC, 4, 0xe0000340, 0xe1f0fff0,
22694 +      &avr32_syntax_table[AVR32_SYNTAX_MAC],
22695 +      BFD_RELOC_UNUSED, 3, -1,
22696 +      {
22697 +       &avr32_ifield_table[AVR32_IFIELD_RD_E],
22698 +       &avr32_ifield_table[AVR32_IFIELD_RX],
22699 +       &avr32_ifield_table[AVR32_IFIELD_RY],
22700 +      },
22701 +    },
22702 +    {
22703 +      AVR32_OPC_MACHH_D, 4, 0xe0000580, 0xe1f0ffc1,
22704 +      &avr32_syntax_table[AVR32_SYNTAX_MACHH_D],
22705 +      BFD_RELOC_UNUSED, 5, -1,
22706 +      {
22707 +       &avr32_ifield_table[AVR32_IFIELD_RD_E],
22708 +       &avr32_ifield_table[AVR32_IFIELD_RX],
22709 +       &avr32_ifield_table[AVR32_IFIELD_X],
22710 +       &avr32_ifield_table[AVR32_IFIELD_RY],
22711 +       &avr32_ifield_table[AVR32_IFIELD_Y],
22712 +      },
22713 +    },
22714 +    {
22715 +      AVR32_OPC_MACHH_W, 4, 0xe0000480, 0xe1f0ffc0,
22716 +      &avr32_syntax_table[AVR32_SYNTAX_MACHH_W],
22717 +      BFD_RELOC_UNUSED, 5, -1,
22718 +      {
22719 +       &avr32_ifield_table[AVR32_IFIELD_RD_E],
22720 +       &avr32_ifield_table[AVR32_IFIELD_RX],
22721 +       &avr32_ifield_table[AVR32_IFIELD_X],
22722 +       &avr32_ifield_table[AVR32_IFIELD_RY],
22723 +       &avr32_ifield_table[AVR32_IFIELD_Y],
22724 +      },
22725 +    },
22726 +    {
22727 +      AVR32_OPC_MACS_D, 4, 0xe0000540, 0xe1f0fff1,
22728 +      &avr32_syntax_table[AVR32_SYNTAX_MACS_D],
22729 +      BFD_RELOC_UNUSED, 3, -1,
22730 +      {
22731 +       &avr32_ifield_table[AVR32_IFIELD_RD_E],
22732 +       &avr32_ifield_table[AVR32_IFIELD_RX],
22733 +       &avr32_ifield_table[AVR32_IFIELD_RY],
22734 +      },
22735 +    },
22736 +    {
22737 +      AVR32_OPC_MACSATHH_W, 4, 0xe0000680, 0xe1f0ffc0,
22738 +      &avr32_syntax_table[AVR32_SYNTAX_MACSATHH_W],
22739 +      BFD_RELOC_UNUSED, 5, -1,
22740 +      {
22741 +       &avr32_ifield_table[AVR32_IFIELD_RD_E],
22742 +       &avr32_ifield_table[AVR32_IFIELD_RX],
22743 +       &avr32_ifield_table[AVR32_IFIELD_X],
22744 +       &avr32_ifield_table[AVR32_IFIELD_RY],
22745 +       &avr32_ifield_table[AVR32_IFIELD_Y],
22746 +      },
22747 +    },
22748 +    {
22749 +      AVR32_OPC_MACUD, 4, 0xe0000740, 0xe1f0fff1,
22750 +      &avr32_syntax_table[AVR32_SYNTAX_MACUD],
22751 +      BFD_RELOC_UNUSED, 3, -1,
22752 +      {
22753 +       &avr32_ifield_table[AVR32_IFIELD_RD_E],
22754 +       &avr32_ifield_table[AVR32_IFIELD_RX],
22755 +       &avr32_ifield_table[AVR32_IFIELD_RY],
22756 +      },
22757 +    },
22758 +    {
22759 +      AVR32_OPC_MACWH_D, 4, 0xe0000c80, 0xe1f0ffe1,
22760 +      &avr32_syntax_table[AVR32_SYNTAX_MACWH_D],
22761 +      BFD_RELOC_UNUSED, 4, -1,
22762 +      {
22763 +       &avr32_ifield_table[AVR32_IFIELD_RD_E],
22764 +       &avr32_ifield_table[AVR32_IFIELD_RX],
22765 +       &avr32_ifield_table[AVR32_IFIELD_RY],
22766 +       &avr32_ifield_table[AVR32_IFIELD_Y],
22767 +      },
22768 +    },
22769 +    {
22770 +      AVR32_OPC_MAX, 4, 0xe0000c40, 0xe1f0fff0,
22771 +      &avr32_syntax_table[AVR32_SYNTAX_MAX],
22772 +      BFD_RELOC_UNUSED, 3, -1,
22773 +      {
22774 +       &avr32_ifield_table[AVR32_IFIELD_RD_E],
22775 +       &avr32_ifield_table[AVR32_IFIELD_RX],
22776 +       &avr32_ifield_table[AVR32_IFIELD_RY],
22777 +      },
22778 +    },
22779 +    {
22780 +      AVR32_OPC_MCALL, 4, 0xf0100000, 0xfff00000,
22781 +      &avr32_syntax_table[AVR32_SYNTAX_MCALL],
22782 +      BFD_RELOC_AVR32_18W_PCREL, 2, 1,
22783 +      {
22784 +       &avr32_ifield_table[AVR32_IFIELD_RY],
22785 +       &avr32_ifield_table[AVR32_IFIELD_K16],
22786 +      },
22787 +    },
22788 +    {
22789 +      AVR32_OPC_MFDR, 4, 0xe5b00000, 0xfff0ff00,
22790 +      &avr32_syntax_table[AVR32_SYNTAX_MFDR],
22791 +      BFD_RELOC_AVR32_8S_EXT, 2, 1,
22792 +      {
22793 +       &avr32_ifield_table[AVR32_IFIELD_RY],
22794 +       &avr32_ifield_table[AVR32_IFIELD_K8E],
22795 +      },
22796 +    },
22797 +    {
22798 +      AVR32_OPC_MFSR, 4, 0xe1b00000, 0xfff0ff00,
22799 +      &avr32_syntax_table[AVR32_SYNTAX_MFSR],
22800 +      BFD_RELOC_AVR32_8S_EXT, 2, 1,
22801 +      {
22802 +       &avr32_ifield_table[AVR32_IFIELD_RY],
22803 +       &avr32_ifield_table[AVR32_IFIELD_K8E],
22804 +      },
22805 +    },
22806 +    {
22807 +      AVR32_OPC_MIN, 4, 0xe0000d40, 0xe1f0fff0,
22808 +      &avr32_syntax_table[AVR32_SYNTAX_MIN],
22809 +      BFD_RELOC_UNUSED, 3, -1,
22810 +      {
22811 +       &avr32_ifield_table[AVR32_IFIELD_RD_E],
22812 +       &avr32_ifield_table[AVR32_IFIELD_RX],
22813 +       &avr32_ifield_table[AVR32_IFIELD_RY],
22814 +      },
22815 +    },
22816 +    {
22817 +      AVR32_OPC_MOV3, 2, 0x00900000, 0xe1f00000,
22818 +      &avr32_syntax_table[AVR32_SYNTAX_MOV3],
22819 +      BFD_RELOC_NONE, 2, -1,
22820 +      {
22821 +       &avr32_ifield_table[AVR32_IFIELD_RY],
22822 +       &avr32_ifield_table[AVR32_IFIELD_RX],
22823 +      },
22824 +    },
22825 +    {
22826 +      AVR32_OPC_MOV1, 2, 0x30000000, 0xf0000000,
22827 +      &avr32_syntax_table[AVR32_SYNTAX_MOV1],
22828 +      BFD_RELOC_AVR32_8S, 2, 1,
22829 +      {
22830 +       &avr32_ifield_table[AVR32_IFIELD_RY],
22831 +       &avr32_ifield_table[AVR32_IFIELD_K8C],
22832 +      },
22833 +    },
22834 +    {
22835 +      AVR32_OPC_MOV2, 4, 0xe0600000, 0xe1e00000,
22836 +      &avr32_syntax_table[AVR32_SYNTAX_MOV2],
22837 +      BFD_RELOC_AVR32_21S, 2, 1,
22838 +      {
22839 +       &avr32_ifield_table[AVR32_IFIELD_RY],
22840 +       &avr32_ifield_table[AVR32_IFIELD_K21],
22841 +      },
22842 +    },
22843 +    {
22844 +      AVR32_OPC_MOVEQ1, 4, 0xe0001700, 0xe1f0ffff,
22845 +      &avr32_syntax_table[AVR32_SYNTAX_MOVEQ1],
22846 +      BFD_RELOC_UNUSED, 2, -1,
22847 +      {
22848 +       &avr32_ifield_table[AVR32_IFIELD_RY],
22849 +       &avr32_ifield_table[AVR32_IFIELD_RX],
22850 +      },
22851 +    },
22852 +    {
22853 +      AVR32_OPC_MOVNE1, 4, 0xe0001710, 0xe1f0ffff,
22854 +      &avr32_syntax_table[AVR32_SYNTAX_MOVNE1],
22855 +      BFD_RELOC_UNUSED, 2, -1,
22856 +      {
22857 +       &avr32_ifield_table[AVR32_IFIELD_RY],
22858 +       &avr32_ifield_table[AVR32_IFIELD_RX],
22859 +      },
22860 +    },
22861 +    {
22862 +      AVR32_OPC_MOVCC1, 4, 0xe0001720, 0xe1f0ffff,
22863 +      &avr32_syntax_table[AVR32_SYNTAX_MOVHS1],
22864 +      BFD_RELOC_UNUSED, 2, -1,
22865 +      {
22866 +       &avr32_ifield_table[AVR32_IFIELD_RY],
22867 +       &avr32_ifield_table[AVR32_IFIELD_RX],
22868 +      },
22869 +    },
22870 +    {
22871 +      AVR32_OPC_MOVCS1, 4, 0xe0001730, 0xe1f0ffff,
22872 +      &avr32_syntax_table[AVR32_SYNTAX_MOVLO1],
22873 +      BFD_RELOC_UNUSED, 2, -1,
22874 +      {
22875 +       &avr32_ifield_table[AVR32_IFIELD_RY],
22876 +       &avr32_ifield_table[AVR32_IFIELD_RX],
22877 +      },
22878 +    },
22879 +    {
22880 +      AVR32_OPC_MOVGE1, 4, 0xe0001740, 0xe1f0ffff,
22881 +      &avr32_syntax_table[AVR32_SYNTAX_MOVGE1],
22882 +      BFD_RELOC_UNUSED, 2, -1,
22883 +      {
22884 +       &avr32_ifield_table[AVR32_IFIELD_RY],
22885 +       &avr32_ifield_table[AVR32_IFIELD_RX],
22886 +      },
22887 +    },
22888 +    {
22889 +      AVR32_OPC_MOVLT1, 4, 0xe0001750, 0xe1f0ffff,
22890 +      &avr32_syntax_table[AVR32_SYNTAX_MOVLT1],
22891 +      BFD_RELOC_UNUSED, 2, -1,
22892 +      {
22893 +       &avr32_ifield_table[AVR32_IFIELD_RY],
22894 +       &avr32_ifield_table[AVR32_IFIELD_RX],
22895 +      },
22896 +    },
22897 +    {
22898 +      AVR32_OPC_MOVMI1, 4, 0xe0001760, 0xe1f0ffff,
22899 +      &avr32_syntax_table[AVR32_SYNTAX_MOVMI1],
22900 +      BFD_RELOC_UNUSED, 2, -1,
22901 +      {
22902 +       &avr32_ifield_table[AVR32_IFIELD_RY],
22903 +       &avr32_ifield_table[AVR32_IFIELD_RX],
22904 +      },
22905 +    },
22906 +    {
22907 +      AVR32_OPC_MOVPL1, 4, 0xe0001770, 0xe1f0ffff,
22908 +      &avr32_syntax_table[AVR32_SYNTAX_MOVPL1],
22909 +      BFD_RELOC_UNUSED, 2, -1,
22910 +      {
22911 +       &avr32_ifield_table[AVR32_IFIELD_RY],
22912 +       &avr32_ifield_table[AVR32_IFIELD_RX],
22913 +      },
22914 +    },
22915 +    {
22916 +      AVR32_OPC_MOVLS1, 4, 0xe0001780, 0xe1f0ffff,
22917 +      &avr32_syntax_table[AVR32_SYNTAX_MOVLS1],
22918 +      BFD_RELOC_UNUSED, 2, -1,
22919 +      {
22920 +       &avr32_ifield_table[AVR32_IFIELD_RY],
22921 +       &avr32_ifield_table[AVR32_IFIELD_RX],
22922 +      },
22923 +    },
22924 +    {
22925 +      AVR32_OPC_MOVGT1, 4, 0xe0001790, 0xe1f0ffff,
22926 +      &avr32_syntax_table[AVR32_SYNTAX_MOVGT1],
22927 +      BFD_RELOC_UNUSED, 2, -1,
22928 +      {
22929 +       &avr32_ifield_table[AVR32_IFIELD_RY],
22930 +       &avr32_ifield_table[AVR32_IFIELD_RX],
22931 +      },
22932 +    },
22933 +    {
22934 +      AVR32_OPC_MOVLE1, 4, 0xe00017a0, 0xe1f0ffff,
22935 +      &avr32_syntax_table[AVR32_SYNTAX_MOVLE1],
22936 +      BFD_RELOC_UNUSED, 2, -1,
22937 +      {
22938 +       &avr32_ifield_table[AVR32_IFIELD_RY],
22939 +       &avr32_ifield_table[AVR32_IFIELD_RX],
22940 +      },
22941 +    },
22942 +    {
22943 +      AVR32_OPC_MOVHI1, 4, 0xe00017b0, 0xe1f0ffff,
22944 +      &avr32_syntax_table[AVR32_SYNTAX_MOVHI1],
22945 +      BFD_RELOC_UNUSED, 2, -1,
22946 +      {
22947 +       &avr32_ifield_table[AVR32_IFIELD_RY],
22948 +       &avr32_ifield_table[AVR32_IFIELD_RX],
22949 +      },
22950 +    },
22951 +    {
22952 +      AVR32_OPC_MOVVS1, 4, 0xe00017c0, 0xe1f0ffff,
22953 +      &avr32_syntax_table[AVR32_SYNTAX_MOVVS1],
22954 +      BFD_RELOC_UNUSED, 2, -1,
22955 +      {
22956 +       &avr32_ifield_table[AVR32_IFIELD_RY],
22957 +       &avr32_ifield_table[AVR32_IFIELD_RX],
22958 +      },
22959 +    },
22960 +    {
22961 +      AVR32_OPC_MOVVC1, 4, 0xe00017d0, 0xe1f0ffff,
22962 +      &avr32_syntax_table[AVR32_SYNTAX_MOVVC1],
22963 +      BFD_RELOC_UNUSED, 2, -1,
22964 +      {
22965 +       &avr32_ifield_table[AVR32_IFIELD_RY],
22966 +       &avr32_ifield_table[AVR32_IFIELD_RX],
22967 +      },
22968 +    },
22969 +    {
22970 +      AVR32_OPC_MOVQS1, 4, 0xe00017e0, 0xe1f0ffff,
22971 +      &avr32_syntax_table[AVR32_SYNTAX_MOVQS1],
22972 +      BFD_RELOC_UNUSED, 2, -1,
22973 +      {
22974 +       &avr32_ifield_table[AVR32_IFIELD_RY],
22975 +       &avr32_ifield_table[AVR32_IFIELD_RX],
22976 +      },
22977 +    },
22978 +    {
22979 +      AVR32_OPC_MOVAL1, 4, 0xe00017f0, 0xe1f0ffff,
22980 +      &avr32_syntax_table[AVR32_SYNTAX_MOVAL1],
22981 +      BFD_RELOC_UNUSED, 2, -1,
22982 +      {
22983 +       &avr32_ifield_table[AVR32_IFIELD_RY],
22984 +       &avr32_ifield_table[AVR32_IFIELD_RX],
22985 +      },
22986 +    },
22987 +    {
22988 +      AVR32_OPC_MOVEQ2, 4, 0xf9b00000, 0xfff0ff00,
22989 +      &avr32_syntax_table[AVR32_SYNTAX_MOVEQ2],
22990 +      BFD_RELOC_AVR32_8S_EXT, 2, 1,
22991 +      {
22992 +       &avr32_ifield_table[AVR32_IFIELD_RY],
22993 +       &avr32_ifield_table[AVR32_IFIELD_K8E],
22994 +      },
22995 +    },
22996 +    {
22997 +      AVR32_OPC_MOVNE2, 4, 0xf9b00100, 0xfff0ff00,
22998 +      &avr32_syntax_table[AVR32_SYNTAX_MOVNE2],
22999 +      BFD_RELOC_AVR32_8S_EXT, 2, 1,
23000 +      {
23001 +       &avr32_ifield_table[AVR32_IFIELD_RY],
23002 +       &avr32_ifield_table[AVR32_IFIELD_K8E],
23003 +      },
23004 +    },
23005 +    {
23006 +      AVR32_OPC_MOVCC2, 4, 0xf9b00200, 0xfff0ff00,
23007 +      &avr32_syntax_table[AVR32_SYNTAX_MOVHS2],
23008 +      BFD_RELOC_AVR32_8S_EXT, 2, 1,
23009 +      {
23010 +       &avr32_ifield_table[AVR32_IFIELD_RY],
23011 +       &avr32_ifield_table[AVR32_IFIELD_K8E],
23012 +      },
23013 +    },
23014 +    {
23015 +      AVR32_OPC_MOVCS2, 4, 0xf9b00300, 0xfff0ff00,
23016 +      &avr32_syntax_table[AVR32_SYNTAX_MOVLO2],
23017 +      BFD_RELOC_AVR32_8S_EXT, 2, 1,
23018 +      {
23019 +       &avr32_ifield_table[AVR32_IFIELD_RY],
23020 +       &avr32_ifield_table[AVR32_IFIELD_K8E],
23021 +      },
23022 +    },
23023 +    {
23024 +      AVR32_OPC_MOVGE2, 4, 0xf9b00400, 0xfff0ff00,
23025 +      &avr32_syntax_table[AVR32_SYNTAX_MOVGE2],
23026 +      BFD_RELOC_AVR32_8S_EXT, 2, 1,
23027 +      {
23028 +       &avr32_ifield_table[AVR32_IFIELD_RY],
23029 +       &avr32_ifield_table[AVR32_IFIELD_K8E],
23030 +      },
23031 +    },
23032 +    {
23033 +      AVR32_OPC_MOVLT2, 4, 0xf9b00500, 0xfff0ff00,
23034 +      &avr32_syntax_table[AVR32_SYNTAX_MOVLT2],
23035 +      BFD_RELOC_AVR32_8S_EXT, 2, 1,
23036 +      {
23037 +       &avr32_ifield_table[AVR32_IFIELD_RY],
23038 +       &avr32_ifield_table[AVR32_IFIELD_K8E],
23039 +      },
23040 +    },
23041 +    {
23042 +      AVR32_OPC_MOVMI2, 4, 0xf9b00600, 0xfff0ff00,
23043 +      &avr32_syntax_table[AVR32_SYNTAX_MOVMI2],
23044 +      BFD_RELOC_AVR32_8S_EXT, 2, 1,
23045 +      {
23046 +       &avr32_ifield_table[AVR32_IFIELD_RY],
23047 +       &avr32_ifield_table[AVR32_IFIELD_K8E],
23048 +      },
23049 +    },
23050 +    {
23051 +      AVR32_OPC_MOVPL2, 4, 0xf9b00700, 0xfff0ff00,
23052 +      &avr32_syntax_table[AVR32_SYNTAX_MOVPL2],
23053 +      BFD_RELOC_AVR32_8S_EXT, 2, 1,
23054 +      {
23055 +       &avr32_ifield_table[AVR32_IFIELD_RY],
23056 +       &avr32_ifield_table[AVR32_IFIELD_K8E],
23057 +      },
23058 +    },
23059 +    {
23060 +      AVR32_OPC_MOVLS2, 4, 0xf9b00800, 0xfff0ff00,
23061 +      &avr32_syntax_table[AVR32_SYNTAX_MOVLS2],
23062 +      BFD_RELOC_AVR32_8S_EXT, 2, 1,
23063 +      {
23064 +       &avr32_ifield_table[AVR32_IFIELD_RY],
23065 +       &avr32_ifield_table[AVR32_IFIELD_K8E],
23066 +      },
23067 +    },
23068 +    {
23069 +      AVR32_OPC_MOVGT2, 4, 0xf9b00900, 0xfff0ff00,
23070 +      &avr32_syntax_table[AVR32_SYNTAX_MOVGT2],
23071 +      BFD_RELOC_AVR32_8S_EXT, 2, 1,
23072 +      {
23073 +       &avr32_ifield_table[AVR32_IFIELD_RY],
23074 +       &avr32_ifield_table[AVR32_IFIELD_K8E],
23075 +      },
23076 +    },
23077 +    {
23078 +      AVR32_OPC_MOVLE2, 4, 0xf9b00a00, 0xfff0ff00,
23079 +      &avr32_syntax_table[AVR32_SYNTAX_MOVLE2],
23080 +      BFD_RELOC_AVR32_8S_EXT, 2, 1,
23081 +      {
23082 +       &avr32_ifield_table[AVR32_IFIELD_RY],
23083 +       &avr32_ifield_table[AVR32_IFIELD_K8E],
23084 +      },
23085 +    },
23086 +    {
23087 +      AVR32_OPC_MOVHI2, 4, 0xf9b00b00, 0xfff0ff00,
23088 +      &avr32_syntax_table[AVR32_SYNTAX_MOVHI2],
23089 +      BFD_RELOC_AVR32_8S_EXT, 2, 1,
23090 +      {
23091 +       &avr32_ifield_table[AVR32_IFIELD_RY],
23092 +       &avr32_ifield_table[AVR32_IFIELD_K8E],
23093 +      },
23094 +    },
23095 +    {
23096 +      AVR32_OPC_MOVVS2, 4, 0xf9b00c00, 0xfff0ff00,
23097 +      &avr32_syntax_table[AVR32_SYNTAX_MOVVS2],
23098 +      BFD_RELOC_AVR32_8S_EXT, 2, 1,
23099 +      {
23100 +       &avr32_ifield_table[AVR32_IFIELD_RY],
23101 +       &avr32_ifield_table[AVR32_IFIELD_K8E],
23102 +      },
23103 +    },
23104 +    {
23105 +      AVR32_OPC_MOVVC2, 4, 0xf9b00d00, 0xfff0ff00,
23106 +      &avr32_syntax_table[AVR32_SYNTAX_MOVVC2],
23107 +      BFD_RELOC_AVR32_8S_EXT, 2, 1,
23108 +      {
23109 +       &avr32_ifield_table[AVR32_IFIELD_RY],
23110 +       &avr32_ifield_table[AVR32_IFIELD_K8E],
23111 +      },
23112 +    },
23113 +    {
23114 +      AVR32_OPC_MOVQS2, 4, 0xf9b00e00, 0xfff0ff00,
23115 +      &avr32_syntax_table[AVR32_SYNTAX_MOVQS2],
23116 +      BFD_RELOC_AVR32_8S_EXT, 2, 1,
23117 +      {
23118 +       &avr32_ifield_table[AVR32_IFIELD_RY],
23119 +       &avr32_ifield_table[AVR32_IFIELD_K8E],
23120 +      },
23121 +    },
23122 +    {
23123 +      AVR32_OPC_MOVAL2, 4, 0xf9b00f00, 0xfff0ff00,
23124 +      &avr32_syntax_table[AVR32_SYNTAX_MOVAL2],
23125 +      BFD_RELOC_AVR32_8S_EXT, 2, 1,
23126 +      {
23127 +       &avr32_ifield_table[AVR32_IFIELD_RY],
23128 +       &avr32_ifield_table[AVR32_IFIELD_K8E],
23129 +      },
23130 +    },
23131 +    {
23132 +      AVR32_OPC_MTDR, 4, 0xe7b00000, 0xfff0ff00,
23133 +      &avr32_syntax_table[AVR32_SYNTAX_MTDR],
23134 +      BFD_RELOC_AVR32_8S_EXT, 2, 0,
23135 +      {
23136 +       &avr32_ifield_table[AVR32_IFIELD_K8E],
23137 +       &avr32_ifield_table[AVR32_IFIELD_RY],
23138 +      },
23139 +    },
23140 +    {
23141 +      AVR32_OPC_MTSR, 4, 0xe3b00000, 0xfff0ff00,
23142 +      &avr32_syntax_table[AVR32_SYNTAX_MTSR],
23143 +      BFD_RELOC_AVR32_8S_EXT, 2, 0,
23144 +      {
23145 +       &avr32_ifield_table[AVR32_IFIELD_K8E],
23146 +       &avr32_ifield_table[AVR32_IFIELD_RY],
23147 +      },
23148 +    },
23149 +    {
23150 +      AVR32_OPC_MUL1, 2, 0xa1300000, 0xe1f00000,
23151 +      &avr32_syntax_table[AVR32_SYNTAX_MUL1],
23152 +      BFD_RELOC_UNUSED, 2, -1,
23153 +      {
23154 +       &avr32_ifield_table[AVR32_IFIELD_RY],
23155 +       &avr32_ifield_table[AVR32_IFIELD_RX],
23156 +      },
23157 +    },
23158 +    {
23159 +      AVR32_OPC_MUL2, 4, 0xe0000240, 0xe1f0fff0,
23160 +      &avr32_syntax_table[AVR32_SYNTAX_MUL2],
23161 +      BFD_RELOC_UNUSED, 3, -1,
23162 +      {
23163 +       &avr32_ifield_table[AVR32_IFIELD_RD_E],
23164 +       &avr32_ifield_table[AVR32_IFIELD_RX],
23165 +       &avr32_ifield_table[AVR32_IFIELD_RY],
23166 +      },
23167 +    },
23168 +    {
23169 +      AVR32_OPC_MUL3, 4, 0xe0001000, 0xe1f0ff00,
23170 +      &avr32_syntax_table[AVR32_SYNTAX_MUL3],
23171 +      BFD_RELOC_AVR32_8S_EXT, 3, 2,
23172 +      {
23173 +       &avr32_ifield_table[AVR32_IFIELD_RY],
23174 +       &avr32_ifield_table[AVR32_IFIELD_RX],
23175 +       &avr32_ifield_table[AVR32_IFIELD_K8E],
23176 +      },
23177 +    },
23178 +    {
23179 +      AVR32_OPC_MULHH_W, 4, 0xe0000780, 0xe1f0ffc0,
23180 +      &avr32_syntax_table[AVR32_SYNTAX_MULHH_W],
23181 +      BFD_RELOC_UNUSED, 5, -1,
23182 +      {
23183 +       &avr32_ifield_table[AVR32_IFIELD_RD_E],
23184 +       &avr32_ifield_table[AVR32_IFIELD_RX],
23185 +       &avr32_ifield_table[AVR32_IFIELD_X],
23186 +       &avr32_ifield_table[AVR32_IFIELD_RY],
23187 +       &avr32_ifield_table[AVR32_IFIELD_Y],
23188 +      },
23189 +    },
23190 +    {
23191 +      AVR32_OPC_MULNHH_W, 4, 0xe0000180, 0xe1f0ffc0,
23192 +      &avr32_syntax_table[AVR32_SYNTAX_MULNHH_W],
23193 +      BFD_RELOC_UNUSED, 5, -1,
23194 +      {
23195 +       &avr32_ifield_table[AVR32_IFIELD_RD_E],
23196 +       &avr32_ifield_table[AVR32_IFIELD_RX],
23197 +       &avr32_ifield_table[AVR32_IFIELD_X],
23198 +       &avr32_ifield_table[AVR32_IFIELD_RY],
23199 +       &avr32_ifield_table[AVR32_IFIELD_Y],
23200 +      },
23201 +    },
23202 +    {
23203 +      AVR32_OPC_MULNWH_D, 4, 0xe0000280, 0xe1f0ffe1,
23204 +      &avr32_syntax_table[AVR32_SYNTAX_MULNWH_D],
23205 +      BFD_RELOC_UNUSED, 4, -1,
23206 +      {
23207 +       &avr32_ifield_table[AVR32_IFIELD_RD_E],
23208 +       &avr32_ifield_table[AVR32_IFIELD_RX],
23209 +       &avr32_ifield_table[AVR32_IFIELD_RY],
23210 +       &avr32_ifield_table[AVR32_IFIELD_Y],
23211 +      },
23212 +    },
23213 +    {
23214 +      AVR32_OPC_MULSD, 4, 0xe0000440, 0xe1f0fff0,
23215 +      &avr32_syntax_table[AVR32_SYNTAX_MULSD],
23216 +      BFD_RELOC_UNUSED, 3, -1,
23217 +      {
23218 +       &avr32_ifield_table[AVR32_IFIELD_RD_E],
23219 +       &avr32_ifield_table[AVR32_IFIELD_RX],
23220 +       &avr32_ifield_table[AVR32_IFIELD_RY],
23221 +      },
23222 +    },
23223 +    {
23224 +      AVR32_OPC_MULSATHH_H, 4, 0xe0000880, 0xe1f0ffc0,
23225 +      &avr32_syntax_table[AVR32_SYNTAX_MULSATHH_H],
23226 +      BFD_RELOC_UNUSED, 5, -1,
23227 +      {
23228 +       &avr32_ifield_table[AVR32_IFIELD_RD_E],
23229 +       &avr32_ifield_table[AVR32_IFIELD_RX],
23230 +       &avr32_ifield_table[AVR32_IFIELD_X],
23231 +       &avr32_ifield_table[AVR32_IFIELD_RY],
23232 +       &avr32_ifield_table[AVR32_IFIELD_Y],
23233 +      },
23234 +    },
23235 +    {
23236 +      AVR32_OPC_MULSATHH_W, 4, 0xe0000980, 0xe1f0ffc0,
23237 +      &avr32_syntax_table[AVR32_SYNTAX_MULSATHH_W],
23238 +      BFD_RELOC_UNUSED, 5, -1,
23239 +      {
23240 +       &avr32_ifield_table[AVR32_IFIELD_RD_E],
23241 +       &avr32_ifield_table[AVR32_IFIELD_RX],
23242 +       &avr32_ifield_table[AVR32_IFIELD_X],
23243 +       &avr32_ifield_table[AVR32_IFIELD_RY],
23244 +       &avr32_ifield_table[AVR32_IFIELD_Y],
23245 +      },
23246 +    },
23247 +    {
23248 +      AVR32_OPC_MULSATRNDHH_H, 4, 0xe0000a80, 0xe1f0ffc0,
23249 +      &avr32_syntax_table[AVR32_SYNTAX_MULSATRNDHH_H],
23250 +      BFD_RELOC_UNUSED, 5, -1,
23251 +      {
23252 +       &avr32_ifield_table[AVR32_IFIELD_RD_E],
23253 +       &avr32_ifield_table[AVR32_IFIELD_RX],
23254 +       &avr32_ifield_table[AVR32_IFIELD_X],
23255 +       &avr32_ifield_table[AVR32_IFIELD_RY],
23256 +       &avr32_ifield_table[AVR32_IFIELD_Y],
23257 +      },
23258 +    },
23259 +    {
23260 +      AVR32_OPC_MULSATRNDWH_W, 4, 0xe0000b80, 0xe1f0ffe0,
23261 +      &avr32_syntax_table[AVR32_SYNTAX_MULSATRNDWH_W],
23262 +      BFD_RELOC_UNUSED, 4, -1,
23263 +      {
23264 +       &avr32_ifield_table[AVR32_IFIELD_RD_E],
23265 +       &avr32_ifield_table[AVR32_IFIELD_RX],
23266 +       &avr32_ifield_table[AVR32_IFIELD_RY],
23267 +       &avr32_ifield_table[AVR32_IFIELD_Y],
23268 +      },
23269 +    },
23270 +    {
23271 +      AVR32_OPC_MULSATWH_W, 4, 0xe0000e80, 0xe1f0ffe0,
23272 +      &avr32_syntax_table[AVR32_SYNTAX_MULSATWH_W],
23273 +      BFD_RELOC_UNUSED, 4, -1,
23274 +      {
23275 +       &avr32_ifield_table[AVR32_IFIELD_RD_E],
23276 +       &avr32_ifield_table[AVR32_IFIELD_RX],
23277 +       &avr32_ifield_table[AVR32_IFIELD_RY],
23278 +       &avr32_ifield_table[AVR32_IFIELD_Y],
23279 +      },
23280 +    },
23281 +    {
23282 +      AVR32_OPC_MULU_D, 4, 0xe0000640, 0xe1f0fff1,
23283 +      &avr32_syntax_table[AVR32_SYNTAX_MULU_D],
23284 +      BFD_RELOC_UNUSED, 3, -1,
23285 +      {
23286 +       &avr32_ifield_table[AVR32_IFIELD_RD_E],
23287 +       &avr32_ifield_table[AVR32_IFIELD_RX],
23288 +       &avr32_ifield_table[AVR32_IFIELD_RY],
23289 +      },
23290 +    },
23291 +    {
23292 +      AVR32_OPC_MULWH_D, 4, 0xe0000d80, 0xe1f0ffe1,
23293 +      &avr32_syntax_table[AVR32_SYNTAX_MULWH_D],
23294 +      BFD_RELOC_UNUSED, 4, -1,
23295 +      {
23296 +       &avr32_ifield_table[AVR32_IFIELD_RD_E],
23297 +       &avr32_ifield_table[AVR32_IFIELD_RX],
23298 +       &avr32_ifield_table[AVR32_IFIELD_RY],
23299 +       &avr32_ifield_table[AVR32_IFIELD_Y],
23300 +      },
23301 +    },
23302 +    {
23303 +      AVR32_OPC_MUSFR, 2, 0x5d300000, 0xfff00000,
23304 +      &avr32_syntax_table[AVR32_SYNTAX_MUSFR],
23305 +      BFD_RELOC_UNUSED, 1, -1,
23306 +      {
23307 +       &avr32_ifield_table[AVR32_IFIELD_RY],
23308 +      }
23309 +    },
23310 +    {
23311 +      AVR32_OPC_MUSTR, 2, 0x5d200000, 0xfff00000,
23312 +      &avr32_syntax_table[AVR32_SYNTAX_MUSTR],
23313 +      BFD_RELOC_UNUSED, 1, -1,
23314 +      {
23315 +       &avr32_ifield_table[AVR32_IFIELD_RY],
23316 +      }
23317 +    },
23318 +    {
23319 +      AVR32_OPC_MVCR_D, 4, 0xefa00010, 0xfff111ff,
23320 +      &avr32_syntax_table[AVR32_SYNTAX_MVCR_D],
23321 +      BFD_RELOC_UNUSED, 3, -1,
23322 +      {
23323 +       &avr32_ifield_table[AVR32_IFIELD_CPNO],
23324 +       &avr32_ifield_table[AVR32_IFIELD_RY_DW],
23325 +       &avr32_ifield_table[AVR32_IFIELD_CRD_DW],
23326 +      },
23327 +    },
23328 +    {
23329 +      AVR32_OPC_MVCR_W, 4, 0xefa00000, 0xfff010ff,
23330 +      &avr32_syntax_table[AVR32_SYNTAX_MVCR_W],
23331 +      BFD_RELOC_UNUSED, 3, -1,
23332 +      {
23333 +       &avr32_ifield_table[AVR32_IFIELD_CPNO],
23334 +       &avr32_ifield_table[AVR32_IFIELD_RY],
23335 +       &avr32_ifield_table[AVR32_IFIELD_CRD_RI],
23336 +      },
23337 +    },
23338 +    {
23339 +      AVR32_OPC_MVRC_D, 4, 0xefa00030, 0xfff111ff,
23340 +      &avr32_syntax_table[AVR32_SYNTAX_MVRC_D],
23341 +      BFD_RELOC_UNUSED, 3, -1,
23342 +      {
23343 +       &avr32_ifield_table[AVR32_IFIELD_CPNO],
23344 +       &avr32_ifield_table[AVR32_IFIELD_CRD_DW],
23345 +       &avr32_ifield_table[AVR32_IFIELD_RY_DW],
23346 +      },
23347 +    },
23348 +    {
23349 +      AVR32_OPC_MVRC_W, 4, 0xefa00020, 0xfff010ff,
23350 +      &avr32_syntax_table[AVR32_SYNTAX_MVRC_W],
23351 +      BFD_RELOC_UNUSED, 3, -1,
23352 +      {
23353 +       &avr32_ifield_table[AVR32_IFIELD_CPNO],
23354 +       &avr32_ifield_table[AVR32_IFIELD_CRD_RI],
23355 +       &avr32_ifield_table[AVR32_IFIELD_RY],
23356 +      },
23357 +    },
23358 +    {
23359 +      AVR32_OPC_NEG, 2, 0x5c300000, 0xfff00000,
23360 +      &avr32_syntax_table[AVR32_SYNTAX_NEG],
23361 +      BFD_RELOC_UNUSED, 1, -1,
23362 +      {
23363 +       &avr32_ifield_table[AVR32_IFIELD_RY],
23364 +      }
23365 +    },
23366 +    {
23367 +      AVR32_OPC_NOP, 2, 0xd7030000, 0xffff0000,
23368 +      &avr32_syntax_table[AVR32_SYNTAX_NOP],
23369 +      BFD_RELOC_UNUSED, 0, -1, { NULL },
23370 +    },
23371 +    {
23372 +      AVR32_OPC_OR1, 2, 0x00400000, 0xe1f00000,
23373 +      &avr32_syntax_table[AVR32_SYNTAX_OR1],
23374 +      BFD_RELOC_UNUSED, 2, -1,
23375 +      {
23376 +       &avr32_ifield_table[AVR32_IFIELD_RY],
23377 +       &avr32_ifield_table[AVR32_IFIELD_RX],
23378 +      },
23379 +    },
23380 +    {
23381 +      AVR32_OPC_OR2, 4, 0xe1e01000, 0xe1f0fe00,
23382 +      &avr32_syntax_table[AVR32_SYNTAX_OR2],
23383 +      BFD_RELOC_UNUSED, 4, -1,
23384 +      {
23385 +       &avr32_ifield_table[AVR32_IFIELD_RD_E],
23386 +       &avr32_ifield_table[AVR32_IFIELD_RX],
23387 +       &avr32_ifield_table[AVR32_IFIELD_RY],
23388 +       &avr32_ifield_table[AVR32_IFIELD_K5E2],
23389 +      },
23390 +    },
23391 +    {
23392 +      AVR32_OPC_OR3, 4, 0xe1e01200, 0xe1f0fe00,
23393 +      &avr32_syntax_table[AVR32_SYNTAX_OR3],
23394 +      BFD_RELOC_UNUSED, 4, -1,
23395 +      {
23396 +       &avr32_ifield_table[AVR32_IFIELD_RD_E],
23397 +       &avr32_ifield_table[AVR32_IFIELD_RX],
23398 +       &avr32_ifield_table[AVR32_IFIELD_RY],
23399 +       &avr32_ifield_table[AVR32_IFIELD_K5E2],
23400 +      },
23401 +    },
23402 +    {
23403 +      AVR32_OPC_ORH, 4, 0xea100000, 0xfff00000,
23404 +      &avr32_syntax_table[AVR32_SYNTAX_ORH],
23405 +      BFD_RELOC_AVR32_16U, 2, 1,
23406 +      {
23407 +       &avr32_ifield_table[AVR32_IFIELD_RY],
23408 +       &avr32_ifield_table[AVR32_IFIELD_K16],
23409 +      },
23410 +    },
23411 +    {
23412 +      AVR32_OPC_ORL, 4, 0xe8100000, 0xfff00000,
23413 +      &avr32_syntax_table[AVR32_SYNTAX_ORL],
23414 +      BFD_RELOC_AVR32_16U, 2, 1,
23415 +      {
23416 +       &avr32_ifield_table[AVR32_IFIELD_RY],
23417 +       &avr32_ifield_table[AVR32_IFIELD_K16],
23418 +      },
23419 +    },
23420 +    {
23421 +      AVR32_OPC_PABS_SB, 4, 0xe00023e0, 0xfff0fff0,
23422 +      &avr32_syntax_table[AVR32_SYNTAX_PABS_SB],
23423 +      BFD_RELOC_UNUSED, 2, -1,
23424 +      {
23425 +       &avr32_ifield_table[AVR32_IFIELD_RD_E],
23426 +       &avr32_ifield_table[AVR32_IFIELD_RY],
23427 +      },
23428 +    },
23429 +    {
23430 +      AVR32_OPC_PABS_SH, 4, 0xe00023f0, 0xfff0fff0,
23431 +      &avr32_syntax_table[AVR32_SYNTAX_PABS_SH],
23432 +      BFD_RELOC_UNUSED, 2, -1,
23433 +      {
23434 +       &avr32_ifield_table[AVR32_IFIELD_RD_E],
23435 +       &avr32_ifield_table[AVR32_IFIELD_RY],
23436 +      },
23437 +    },
23438 +    {
23439 +      AVR32_OPC_PACKSH_SB, 4, 0xe00024d0, 0xe1f0fff0,
23440 +      &avr32_syntax_table[AVR32_SYNTAX_PACKSH_SB],
23441 +      BFD_RELOC_UNUSED, 3, -1,
23442 +      {
23443 +       &avr32_ifield_table[AVR32_IFIELD_RD_E],
23444 +       &avr32_ifield_table[AVR32_IFIELD_RX],
23445 +       &avr32_ifield_table[AVR32_IFIELD_RY],
23446 +      },
23447 +    },
23448 +    {
23449 +      AVR32_OPC_PACKSH_UB, 4, 0xe00024c0, 0xe1f0fff0,
23450 +      &avr32_syntax_table[AVR32_SYNTAX_PACKSH_UB],
23451 +      BFD_RELOC_UNUSED, 3, -1,
23452 +      {
23453 +       &avr32_ifield_table[AVR32_IFIELD_RD_E],
23454 +       &avr32_ifield_table[AVR32_IFIELD_RX],
23455 +       &avr32_ifield_table[AVR32_IFIELD_RY],
23456 +      },
23457 +    },
23458 +    {
23459 +      AVR32_OPC_PACKW_SH, 4, 0xe0002470, 0xe1f0fff0,
23460 +      &avr32_syntax_table[AVR32_SYNTAX_PACKW_SH],
23461 +      BFD_RELOC_UNUSED, 3, -1,
23462 +      {
23463 +       &avr32_ifield_table[AVR32_IFIELD_RD_E],
23464 +       &avr32_ifield_table[AVR32_IFIELD_RX],
23465 +       &avr32_ifield_table[AVR32_IFIELD_RY],
23466 +      },
23467 +    },
23468 +    {
23469 +      AVR32_OPC_PADD_B, 4, 0xe0002300, 0xe1f0fff0,
23470 +      &avr32_syntax_table[AVR32_SYNTAX_PADD_B],
23471 +      BFD_RELOC_UNUSED, 3, -1,
23472 +      {
23473 +       &avr32_ifield_table[AVR32_IFIELD_RD_E],
23474 +       &avr32_ifield_table[AVR32_IFIELD_RX],
23475 +       &avr32_ifield_table[AVR32_IFIELD_RY],
23476 +      },
23477 +    },
23478 +    {
23479 +      AVR32_OPC_PADD_H, 4, 0xe0002000, 0xe1f0fff0,
23480 +      &avr32_syntax_table[AVR32_SYNTAX_PADD_H],
23481 +      BFD_RELOC_UNUSED, 3, -1,
23482 +      {
23483 +       &avr32_ifield_table[AVR32_IFIELD_RD_E],
23484 +       &avr32_ifield_table[AVR32_IFIELD_RX],
23485 +       &avr32_ifield_table[AVR32_IFIELD_RY],
23486 +      },
23487 +    },
23488 +    {
23489 +      AVR32_OPC_PADDH_SH, 4, 0xe00020c0, 0xe1f0fff0,
23490 +      &avr32_syntax_table[AVR32_SYNTAX_PADDH_SH],
23491 +      BFD_RELOC_UNUSED, 3, -1,
23492 +      {
23493 +       &avr32_ifield_table[AVR32_IFIELD_RD_E],
23494 +       &avr32_ifield_table[AVR32_IFIELD_RX],
23495 +       &avr32_ifield_table[AVR32_IFIELD_RY],
23496 +      },
23497 +    },
23498 +    {
23499 +      AVR32_OPC_PADDH_UB, 4, 0xe0002360, 0xe1f0fff0,
23500 +      &avr32_syntax_table[AVR32_SYNTAX_PADDH_UB],
23501 +      BFD_RELOC_UNUSED, 3, -1,
23502 +      {
23503 +       &avr32_ifield_table[AVR32_IFIELD_RD_E],
23504 +       &avr32_ifield_table[AVR32_IFIELD_RX],
23505 +       &avr32_ifield_table[AVR32_IFIELD_RY],
23506 +      },
23507 +    },
23508 +    {
23509 +      AVR32_OPC_PADDS_SB, 4, 0xe0002320, 0xe1f0fff0,
23510 +      &avr32_syntax_table[AVR32_SYNTAX_PADDS_SB],
23511 +      BFD_RELOC_UNUSED, 3, -1,
23512 +      {
23513 +       &avr32_ifield_table[AVR32_IFIELD_RD_E],
23514 +       &avr32_ifield_table[AVR32_IFIELD_RX],
23515 +       &avr32_ifield_table[AVR32_IFIELD_RY],
23516 +      },
23517 +    },
23518 +    {
23519 +      AVR32_OPC_PADDS_SH, 4, 0xe0002040, 0xe1f0fff0,
23520 +      &avr32_syntax_table[AVR32_SYNTAX_PADDS_SH],
23521 +      BFD_RELOC_UNUSED, 3, -1,
23522 +      {
23523 +       &avr32_ifield_table[AVR32_IFIELD_RD_E],
23524 +       &avr32_ifield_table[AVR32_IFIELD_RX],
23525 +       &avr32_ifield_table[AVR32_IFIELD_RY],
23526 +      },
23527 +    },
23528 +    {
23529 +      AVR32_OPC_PADDS_UB, 4, 0xe0002340, 0xe1f0fff0,
23530 +      &avr32_syntax_table[AVR32_SYNTAX_PADDS_UB],
23531 +      BFD_RELOC_UNUSED, 3, -1,
23532 +      {
23533 +       &avr32_ifield_table[AVR32_IFIELD_RD_E],
23534 +       &avr32_ifield_table[AVR32_IFIELD_RX],
23535 +       &avr32_ifield_table[AVR32_IFIELD_RY],
23536 +      },
23537 +    },
23538 +    {
23539 +      AVR32_OPC_PADDS_UH, 4, 0xe0002080, 0xe1f0fff0,
23540 +      &avr32_syntax_table[AVR32_SYNTAX_PADDS_UH],
23541 +      BFD_RELOC_UNUSED, 3, -1,
23542 +      {
23543 +       &avr32_ifield_table[AVR32_IFIELD_RD_E],
23544 +       &avr32_ifield_table[AVR32_IFIELD_RX],
23545 +       &avr32_ifield_table[AVR32_IFIELD_RY],
23546 +      },
23547 +    },
23548 +    {
23549 +      AVR32_OPC_PADDSUB_H, 4, 0xe0002100, 0xe1f0ffc0,
23550 +      &avr32_syntax_table[AVR32_SYNTAX_PADDSUB_H],
23551 +      BFD_RELOC_UNUSED, 5, -1,
23552 +      {
23553 +       &avr32_ifield_table[AVR32_IFIELD_RD_E],
23554 +       &avr32_ifield_table[AVR32_IFIELD_RX],
23555 +       &avr32_ifield_table[AVR32_IFIELD_X],
23556 +       &avr32_ifield_table[AVR32_IFIELD_RY],
23557 +       &avr32_ifield_table[AVR32_IFIELD_Y],
23558 +      },
23559 +    },
23560 +    {
23561 +      AVR32_OPC_PADDSUBH_SH, 4, 0xe0002280, 0xe1f0ffc0,
23562 +      &avr32_syntax_table[AVR32_SYNTAX_PADDSUBH_SH],
23563 +      BFD_RELOC_UNUSED, 5, -1,
23564 +      {
23565 +       &avr32_ifield_table[AVR32_IFIELD_RD_E],
23566 +       &avr32_ifield_table[AVR32_IFIELD_RX],
23567 +       &avr32_ifield_table[AVR32_IFIELD_X],
23568 +       &avr32_ifield_table[AVR32_IFIELD_RY],
23569 +       &avr32_ifield_table[AVR32_IFIELD_Y],
23570 +      },
23571 +    },
23572 +    {
23573 +      AVR32_OPC_PADDSUBS_SH, 4, 0xe0002180, 0xe1f0ffc0,
23574 +      &avr32_syntax_table[AVR32_SYNTAX_PADDSUBS_SH],
23575 +      BFD_RELOC_UNUSED, 5, -1,
23576 +      {
23577 +       &avr32_ifield_table[AVR32_IFIELD_RD_E],
23578 +       &avr32_ifield_table[AVR32_IFIELD_RX],
23579 +       &avr32_ifield_table[AVR32_IFIELD_X],
23580 +       &avr32_ifield_table[AVR32_IFIELD_RY],
23581 +       &avr32_ifield_table[AVR32_IFIELD_Y],
23582 +      },
23583 +    },
23584 +    {
23585 +      AVR32_OPC_PADDSUBS_UH, 4, 0xe0002200, 0xe1f0ffc0,
23586 +      &avr32_syntax_table[AVR32_SYNTAX_PADDSUBS_UH],
23587 +      BFD_RELOC_UNUSED, 5, -1,
23588 +      {
23589 +       &avr32_ifield_table[AVR32_IFIELD_RD_E],
23590 +       &avr32_ifield_table[AVR32_IFIELD_RX],
23591 +       &avr32_ifield_table[AVR32_IFIELD_X],
23592 +       &avr32_ifield_table[AVR32_IFIELD_RY],
23593 +       &avr32_ifield_table[AVR32_IFIELD_Y],
23594 +      },
23595 +    },
23596 +    {
23597 +      AVR32_OPC_PADDX_H, 4, 0xe0002020, 0xe1f0fff0,
23598 +      &avr32_syntax_table[AVR32_SYNTAX_PADDX_H],
23599 +      BFD_RELOC_UNUSED, 3, -1,
23600 +      {
23601 +       &avr32_ifield_table[AVR32_IFIELD_RD_E],
23602 +       &avr32_ifield_table[AVR32_IFIELD_RX],
23603 +       &avr32_ifield_table[AVR32_IFIELD_RY],
23604 +      },
23605 +    },
23606 +    {
23607 +      AVR32_OPC_PADDXH_SH, 4, 0xe00020e0, 0xe1f0fff0,
23608 +      &avr32_syntax_table[AVR32_SYNTAX_PADDXH_SH],
23609 +      BFD_RELOC_UNUSED, 3, -1,
23610 +      {
23611 +       &avr32_ifield_table[AVR32_IFIELD_RD_E],
23612 +       &avr32_ifield_table[AVR32_IFIELD_RX],
23613 +       &avr32_ifield_table[AVR32_IFIELD_RY],
23614 +      },
23615 +    },
23616 +    {
23617 +      AVR32_OPC_PADDXS_SH, 4, 0xe0002060, 0xe1f0fff0,
23618 +      &avr32_syntax_table[AVR32_SYNTAX_PADDXS_SH],
23619 +      BFD_RELOC_UNUSED, 3, -1,
23620 +      {
23621 +       &avr32_ifield_table[AVR32_IFIELD_RD_E],
23622 +       &avr32_ifield_table[AVR32_IFIELD_RX],
23623 +       &avr32_ifield_table[AVR32_IFIELD_RY],
23624 +      },
23625 +    },
23626 +    {
23627 +      AVR32_OPC_PADDXS_UH, 4, 0xe00020a0, 0xe1f0fff0,
23628 +      &avr32_syntax_table[AVR32_SYNTAX_PADDXS_UH],
23629 +      BFD_RELOC_UNUSED, 3, -1,
23630 +      {
23631 +       &avr32_ifield_table[AVR32_IFIELD_RD_E],
23632 +       &avr32_ifield_table[AVR32_IFIELD_RX],
23633 +       &avr32_ifield_table[AVR32_IFIELD_RY],
23634 +      },
23635 +    },
23636 +    {
23637 +      AVR32_OPC_PASR_B, 4, 0xe0002410, 0xe1f8fff0,
23638 +      &avr32_syntax_table[AVR32_SYNTAX_PASR_B],
23639 +      BFD_RELOC_UNUSED, 3, -1,
23640 +      {
23641 +       &avr32_ifield_table[AVR32_IFIELD_RD_E],
23642 +       &avr32_ifield_table[AVR32_IFIELD_RX],
23643 +       &avr32_ifield_table[AVR32_IFIELD_COND3],
23644 +      },
23645 +    },
23646 +    {
23647 +      AVR32_OPC_PASR_H, 4, 0xe0002440, 0xe1f0fff0,
23648 +      &avr32_syntax_table[AVR32_SYNTAX_PASR_H],
23649 +      BFD_RELOC_UNUSED, 3, -1,
23650 +      {
23651 +       &avr32_ifield_table[AVR32_IFIELD_RD_E],
23652 +       &avr32_ifield_table[AVR32_IFIELD_RX],
23653 +       &avr32_ifield_table[AVR32_IFIELD_RY],
23654 +      },
23655 +    },
23656 +    {
23657 +      AVR32_OPC_PAVG_SH, 4, 0xe00023d0, 0xe1f0fff0,
23658 +      &avr32_syntax_table[AVR32_SYNTAX_PAVG_SH],
23659 +      BFD_RELOC_UNUSED, 3, -1,
23660 +      {
23661 +       &avr32_ifield_table[AVR32_IFIELD_RD_E],
23662 +       &avr32_ifield_table[AVR32_IFIELD_RX],
23663 +       &avr32_ifield_table[AVR32_IFIELD_RY],
23664 +      },
23665 +    },
23666 +    {
23667 +      AVR32_OPC_PAVG_UB, 4, 0xe00023c0, 0xe1f0fff0,
23668 +      &avr32_syntax_table[AVR32_SYNTAX_PAVG_UB],
23669 +      BFD_RELOC_UNUSED, 3, -1,
23670 +      {
23671 +       &avr32_ifield_table[AVR32_IFIELD_RD_E],
23672 +       &avr32_ifield_table[AVR32_IFIELD_RX],
23673 +       &avr32_ifield_table[AVR32_IFIELD_RY],
23674 +      },
23675 +    },
23676 +    {
23677 +      AVR32_OPC_PLSL_B, 4, 0xe0002420, 0xe1f8fff0,
23678 +      &avr32_syntax_table[AVR32_SYNTAX_PLSL_B],
23679 +      BFD_RELOC_UNUSED, 3, -1,
23680 +      {
23681 +       &avr32_ifield_table[AVR32_IFIELD_RD_E],
23682 +       &avr32_ifield_table[AVR32_IFIELD_RX],
23683 +       &avr32_ifield_table[AVR32_IFIELD_COND3],
23684 +      },
23685 +    },
23686 +    {
23687 +      AVR32_OPC_PLSL_H, 4, 0xe0002450, 0xe1f0fff0,
23688 +      &avr32_syntax_table[AVR32_SYNTAX_PLSL_H],
23689 +      BFD_RELOC_UNUSED, 3, -1,
23690 +      {
23691 +       &avr32_ifield_table[AVR32_IFIELD_RD_E],
23692 +       &avr32_ifield_table[AVR32_IFIELD_RX],
23693 +       &avr32_ifield_table[AVR32_IFIELD_RY],
23694 +      },
23695 +    },
23696 +    {
23697 +      AVR32_OPC_PLSR_B, 4, 0xe0002430, 0xe1f8fff0,
23698 +      &avr32_syntax_table[AVR32_SYNTAX_PLSR_B],
23699 +      BFD_RELOC_UNUSED, 3, -1,
23700 +      {
23701 +       &avr32_ifield_table[AVR32_IFIELD_RD_E],
23702 +       &avr32_ifield_table[AVR32_IFIELD_RX],
23703 +       &avr32_ifield_table[AVR32_IFIELD_COND3],
23704 +      },
23705 +    },
23706 +    {
23707 +      AVR32_OPC_PLSR_H, 4, 0xe0002460, 0xe1f0fff0,
23708 +      &avr32_syntax_table[AVR32_SYNTAX_PLSR_H],
23709 +      BFD_RELOC_UNUSED, 3, -1,
23710 +      {
23711 +       &avr32_ifield_table[AVR32_IFIELD_RD_E],
23712 +       &avr32_ifield_table[AVR32_IFIELD_RX],
23713 +       &avr32_ifield_table[AVR32_IFIELD_RY],
23714 +      },
23715 +    },
23716 +    {
23717 +      AVR32_OPC_PMAX_SH, 4, 0xe0002390, 0xe1f0fff0,
23718 +      &avr32_syntax_table[AVR32_SYNTAX_PMAX_SH],
23719 +      BFD_RELOC_UNUSED, 3, -1,
23720 +      {
23721 +       &avr32_ifield_table[AVR32_IFIELD_RD_E],
23722 +       &avr32_ifield_table[AVR32_IFIELD_RX],
23723 +       &avr32_ifield_table[AVR32_IFIELD_RY],
23724 +      },
23725 +    },
23726 +    {
23727 +      AVR32_OPC_PMAX_UB, 4, 0xe0002380, 0xe1f0fff0,
23728 +      &avr32_syntax_table[AVR32_SYNTAX_PMAX_UB],
23729 +      BFD_RELOC_UNUSED, 3, -1,
23730 +      {
23731 +       &avr32_ifield_table[AVR32_IFIELD_RD_E],
23732 +       &avr32_ifield_table[AVR32_IFIELD_RX],
23733 +       &avr32_ifield_table[AVR32_IFIELD_RY],
23734 +      },
23735 +    },
23736 +    {
23737 +      AVR32_OPC_PMIN_SH, 4, 0xe00023b0, 0xe1f0fff0,
23738 +      &avr32_syntax_table[AVR32_SYNTAX_PMIN_SH],
23739 +      BFD_RELOC_UNUSED, 3, -1,
23740 +      {
23741 +       &avr32_ifield_table[AVR32_IFIELD_RD_E],
23742 +       &avr32_ifield_table[AVR32_IFIELD_RX],
23743 +       &avr32_ifield_table[AVR32_IFIELD_RY],
23744 +      },
23745 +    },
23746 +    {
23747 +      AVR32_OPC_PMIN_UB, 4, 0xe00023a0, 0xe1f0fff0,
23748 +      &avr32_syntax_table[AVR32_SYNTAX_PMIN_UB],
23749 +      BFD_RELOC_UNUSED, 3, -1,
23750 +      {
23751 +       &avr32_ifield_table[AVR32_IFIELD_RD_E],
23752 +       &avr32_ifield_table[AVR32_IFIELD_RX],
23753 +       &avr32_ifield_table[AVR32_IFIELD_RY],
23754 +      },
23755 +    },
23756 +    {
23757 +      AVR32_OPC_POPJC, 2, 0xd7130000, 0xffff0000,
23758 +      &avr32_syntax_table[AVR32_SYNTAX_POPJC],
23759 +      BFD_RELOC_UNUSED, 0, -1, { NULL },
23760 +    },
23761 +    {
23762 +      AVR32_OPC_POPM, 2, 0xd0020000, 0xf0070000,
23763 +      &avr32_syntax_table[AVR32_SYNTAX_POPM],
23764 +      BFD_RELOC_UNUSED, 1, -1,
23765 +      {
23766 +       &avr32_ifield_table[AVR32_IFIELD_POPM],
23767 +      },
23768 +    },
23769 +    {
23770 +      AVR32_OPC_POPM_E, 4, 0xe3cd0000, 0xffff0000,
23771 +      &avr32_syntax_table[AVR32_SYNTAX_POPM_E],
23772 +      BFD_RELOC_UNUSED, 1, -1,
23773 +      {
23774 +       &avr32_ifield_table[AVR32_IFIELD_K16],
23775 +      },
23776 +    },
23777 +    {
23778 +      AVR32_OPC_PREF, 4, 0xf2100000, 0xfff00000,
23779 +      &avr32_syntax_table[AVR32_SYNTAX_PREF],
23780 +      BFD_RELOC_AVR32_16S, 2, -1,
23781 +      {
23782 +       &avr32_ifield_table[AVR32_IFIELD_RY],
23783 +       &avr32_ifield_table[AVR32_IFIELD_K16],
23784 +      },
23785 +    },
23786 +    {
23787 +      AVR32_OPC_PSAD, 4, 0xe0002400, 0xe1f0fff0,
23788 +      &avr32_syntax_table[AVR32_SYNTAX_PSAD],
23789 +      BFD_RELOC_UNUSED, 3, -1,
23790 +      {
23791 +       &avr32_ifield_table[AVR32_IFIELD_RD_E],
23792 +       &avr32_ifield_table[AVR32_IFIELD_RX],
23793 +       &avr32_ifield_table[AVR32_IFIELD_RY],
23794 +      },
23795 +    },
23796 +    {
23797 +      AVR32_OPC_PSUB_B, 4, 0xe0002310, 0xe1f0fff0,
23798 +      &avr32_syntax_table[AVR32_SYNTAX_PSUB_B],
23799 +      BFD_RELOC_UNUSED, 3, -1,
23800 +      {
23801 +       &avr32_ifield_table[AVR32_IFIELD_RD_E],
23802 +       &avr32_ifield_table[AVR32_IFIELD_RX],
23803 +       &avr32_ifield_table[AVR32_IFIELD_RY],
23804 +      },
23805 +    },
23806 +    {
23807 +      AVR32_OPC_PSUB_H, 4, 0xe0002010, 0xe1f0fff0,
23808 +      &avr32_syntax_table[AVR32_SYNTAX_PSUB_H],
23809 +      BFD_RELOC_UNUSED, 3, -1,
23810 +      {
23811 +       &avr32_ifield_table[AVR32_IFIELD_RD_E],
23812 +       &avr32_ifield_table[AVR32_IFIELD_RX],
23813 +       &avr32_ifield_table[AVR32_IFIELD_RY],
23814 +      },
23815 +    },
23816 +    {
23817 +      AVR32_OPC_PSUBADD_H, 4, 0xe0002140, 0xe1f0ffc0,
23818 +      &avr32_syntax_table[AVR32_SYNTAX_PSUBADD_H],
23819 +      BFD_RELOC_UNUSED, 5, -1,
23820 +      {
23821 +       &avr32_ifield_table[AVR32_IFIELD_RD_E],
23822 +       &avr32_ifield_table[AVR32_IFIELD_RX],
23823 +       &avr32_ifield_table[AVR32_IFIELD_X],
23824 +       &avr32_ifield_table[AVR32_IFIELD_RY],
23825 +       &avr32_ifield_table[AVR32_IFIELD_Y],
23826 +      },
23827 +    },
23828 +    {
23829 +      AVR32_OPC_PSUBADDH_SH, 4, 0xe00022c0, 0xe1f0ffc0,
23830 +      &avr32_syntax_table[AVR32_SYNTAX_PSUBADDH_SH],
23831 +      BFD_RELOC_UNUSED, 5, -1,
23832 +      {
23833 +       &avr32_ifield_table[AVR32_IFIELD_RD_E],
23834 +       &avr32_ifield_table[AVR32_IFIELD_RX],
23835 +       &avr32_ifield_table[AVR32_IFIELD_X],
23836 +       &avr32_ifield_table[AVR32_IFIELD_RY],
23837 +       &avr32_ifield_table[AVR32_IFIELD_Y],
23838 +      },
23839 +    },
23840 +    {
23841 +      AVR32_OPC_PSUBADDS_SH, 4, 0xe00021c0, 0xe1f0ffc0,
23842 +      &avr32_syntax_table[AVR32_SYNTAX_PSUBADDS_SH],
23843 +      BFD_RELOC_UNUSED, 5, -1,
23844 +      {
23845 +       &avr32_ifield_table[AVR32_IFIELD_RD_E],
23846 +       &avr32_ifield_table[AVR32_IFIELD_RX],
23847 +       &avr32_ifield_table[AVR32_IFIELD_X],
23848 +       &avr32_ifield_table[AVR32_IFIELD_RY],
23849 +       &avr32_ifield_table[AVR32_IFIELD_Y],
23850 +      },
23851 +    },
23852 +    {
23853 +      AVR32_OPC_PSUBADDS_UH, 4, 0xe0002240, 0xe1f0ffc0,
23854 +      &avr32_syntax_table[AVR32_SYNTAX_PSUBADDS_UH],
23855 +      BFD_RELOC_UNUSED, 5, -1,
23856 +      {
23857 +       &avr32_ifield_table[AVR32_IFIELD_RD_E],
23858 +       &avr32_ifield_table[AVR32_IFIELD_RX],
23859 +       &avr32_ifield_table[AVR32_IFIELD_X],
23860 +       &avr32_ifield_table[AVR32_IFIELD_RY],
23861 +       &avr32_ifield_table[AVR32_IFIELD_Y],
23862 +      },
23863 +    },
23864 +    {
23865 +      AVR32_OPC_PSUBH_SH, 4, 0xe00020d0, 0xe1f0fff0,
23866 +      &avr32_syntax_table[AVR32_SYNTAX_PSUBH_SH],
23867 +      BFD_RELOC_UNUSED, 3, -1,
23868 +      {
23869 +       &avr32_ifield_table[AVR32_IFIELD_RD_E],
23870 +       &avr32_ifield_table[AVR32_IFIELD_RX],
23871 +       &avr32_ifield_table[AVR32_IFIELD_RY],
23872 +      },
23873 +    },
23874 +    {
23875 +      AVR32_OPC_PSUBH_UB, 4, 0xe0002370, 0xe1f0fff0,
23876 +      &avr32_syntax_table[AVR32_SYNTAX_PSUBH_UB],
23877 +      BFD_RELOC_UNUSED, 3, -1,
23878 +      {
23879 +       &avr32_ifield_table[AVR32_IFIELD_RD_E],
23880 +       &avr32_ifield_table[AVR32_IFIELD_RX],
23881 +       &avr32_ifield_table[AVR32_IFIELD_RY],
23882 +      },
23883 +    },
23884 +    {
23885 +      AVR32_OPC_PSUBS_SB, 4, 0xe0002330, 0xe1f0fff0,
23886 +      &avr32_syntax_table[AVR32_SYNTAX_PSUBS_SB],
23887 +      BFD_RELOC_UNUSED, 3, -1,
23888 +      {
23889 +       &avr32_ifield_table[AVR32_IFIELD_RD_E],
23890 +       &avr32_ifield_table[AVR32_IFIELD_RX],
23891 +       &avr32_ifield_table[AVR32_IFIELD_RY],
23892 +      },
23893 +    },
23894 +    {
23895 +      AVR32_OPC_PSUBS_SH, 4, 0xe0002050, 0xe1f0fff0,
23896 +      &avr32_syntax_table[AVR32_SYNTAX_PSUBS_SH],
23897 +      BFD_RELOC_UNUSED, 3, -1,
23898 +      {
23899 +       &avr32_ifield_table[AVR32_IFIELD_RD_E],
23900 +       &avr32_ifield_table[AVR32_IFIELD_RX],
23901 +       &avr32_ifield_table[AVR32_IFIELD_RY],
23902 +      },
23903 +    },
23904 +    {
23905 +      AVR32_OPC_PSUBS_UB, 4, 0xe0002350, 0xe1f0fff0,
23906 +      &avr32_syntax_table[AVR32_SYNTAX_PSUBS_UB],
23907 +      BFD_RELOC_UNUSED, 3, -1,
23908 +      {
23909 +       &avr32_ifield_table[AVR32_IFIELD_RD_E],
23910 +       &avr32_ifield_table[AVR32_IFIELD_RX],
23911 +       &avr32_ifield_table[AVR32_IFIELD_RY],
23912 +      },
23913 +    },
23914 +    {
23915 +      AVR32_OPC_PSUBS_UH, 4, 0xe0002090, 0xe1f0fff0,
23916 +      &avr32_syntax_table[AVR32_SYNTAX_PSUBS_UH],
23917 +      BFD_RELOC_UNUSED, 3, -1,
23918 +      {
23919 +       &avr32_ifield_table[AVR32_IFIELD_RD_E],
23920 +       &avr32_ifield_table[AVR32_IFIELD_RX],
23921 +       &avr32_ifield_table[AVR32_IFIELD_RY],
23922 +      },
23923 +    },
23924 +    {
23925 +      AVR32_OPC_PSUBX_H, 4, 0xe0002030, 0xe1f0fff0,
23926 +      &avr32_syntax_table[AVR32_SYNTAX_PSUBX_H],
23927 +      BFD_RELOC_UNUSED, 3, -1,
23928 +      {
23929 +       &avr32_ifield_table[AVR32_IFIELD_RD_E],
23930 +       &avr32_ifield_table[AVR32_IFIELD_RX],
23931 +       &avr32_ifield_table[AVR32_IFIELD_RY],
23932 +      },
23933 +    },
23934 +    {
23935 +      AVR32_OPC_PSUBXH_SH, 4, 0xe00020f0, 0xe1f0fff0,
23936 +      &avr32_syntax_table[AVR32_SYNTAX_PSUBXH_SH],
23937 +      BFD_RELOC_UNUSED, 3, -1,
23938 +      {
23939 +       &avr32_ifield_table[AVR32_IFIELD_RD_E],
23940 +       &avr32_ifield_table[AVR32_IFIELD_RX],
23941 +       &avr32_ifield_table[AVR32_IFIELD_RY],
23942 +      },
23943 +    },
23944 +    {
23945 +      AVR32_OPC_PSUBXS_SH, 4, 0xe0002070, 0xe1f0fff0,
23946 +      &avr32_syntax_table[AVR32_SYNTAX_PSUBXS_SH],
23947 +      BFD_RELOC_UNUSED, 3, -1,
23948 +      {
23949 +       &avr32_ifield_table[AVR32_IFIELD_RD_E],
23950 +       &avr32_ifield_table[AVR32_IFIELD_RX],
23951 +       &avr32_ifield_table[AVR32_IFIELD_RY],
23952 +      },
23953 +    },
23954 +    {
23955 +      AVR32_OPC_PSUBXS_UH, 4, 0xe00020b0, 0xe1f0fff0,
23956 +      &avr32_syntax_table[AVR32_SYNTAX_PSUBXS_UH],
23957 +      BFD_RELOC_UNUSED, 3, -1,
23958 +      {
23959 +       &avr32_ifield_table[AVR32_IFIELD_RD_E],
23960 +       &avr32_ifield_table[AVR32_IFIELD_RX],
23961 +       &avr32_ifield_table[AVR32_IFIELD_RY],
23962 +      },
23963 +    },
23964 +    {
23965 +      AVR32_OPC_PUNPCKSB_H, 4, 0xe00024a0, 0xe1ffffe0,
23966 +      &avr32_syntax_table[AVR32_SYNTAX_PUNPCKSB_H],
23967 +      BFD_RELOC_UNUSED, 3, -1,
23968 +      {
23969 +       &avr32_ifield_table[AVR32_IFIELD_RD_E],
23970 +       &avr32_ifield_table[AVR32_IFIELD_RX],
23971 +       &avr32_ifield_table[AVR32_IFIELD_Y],
23972 +      },
23973 +    },
23974 +    {
23975 +      AVR32_OPC_PUNPCKUB_H, 4, 0xe0002480, 0xe1ffffe0,
23976 +      &avr32_syntax_table[AVR32_SYNTAX_PUNPCKUB_H],
23977 +      BFD_RELOC_UNUSED, 3, -1,
23978 +      {
23979 +       &avr32_ifield_table[AVR32_IFIELD_RD_E],
23980 +       &avr32_ifield_table[AVR32_IFIELD_RX],
23981 +       &avr32_ifield_table[AVR32_IFIELD_Y],
23982 +      },
23983 +    },
23984 +    {
23985 +      AVR32_OPC_PUSHJC, 2, 0xd7230000, 0xffff0000,
23986 +      &avr32_syntax_table[AVR32_SYNTAX_PUSHJC],
23987 +      BFD_RELOC_UNUSED, 0, -1, { NULL },
23988 +    },
23989 +    {
23990 +      AVR32_OPC_PUSHM, 2, 0xd0010000, 0xf00f0000,
23991 +      &avr32_syntax_table[AVR32_SYNTAX_PUSHM],
23992 +      BFD_RELOC_UNUSED, 1, -1,
23993 +      {
23994 +       &avr32_ifield_table[AVR32_IFIELD_K8C],
23995 +      },
23996 +    },
23997 +    {
23998 +      AVR32_OPC_PUSHM_E, 4, 0xebcd0000, 0xffff0000,
23999 +      &avr32_syntax_table[AVR32_SYNTAX_PUSHM_E],
24000 +      BFD_RELOC_UNUSED, 1, -1,
24001 +      {
24002 +       &avr32_ifield_table[AVR32_IFIELD_K16],
24003 +      },
24004 +    },
24005 +    {
24006 +      AVR32_OPC_RCALL1, 2, 0xc00c0000, 0xf00c0000,
24007 +      &avr32_syntax_table[AVR32_SYNTAX_RCALL1],
24008 +      BFD_RELOC_AVR32_11H_PCREL, 1, 0,
24009 +      {
24010 +       &avr32_ifield_table[AVR32_IFIELD_K10],
24011 +      },
24012 +    },
24013 +    {
24014 +      AVR32_OPC_RCALL2, 4, 0xe0a00000, 0xe1ef0000,
24015 +      &avr32_syntax_table[AVR32_SYNTAX_RCALL2],
24016 +      BFD_RELOC_AVR32_22H_PCREL, 1, 0,
24017 +      {
24018 +       &avr32_ifield_table[AVR32_IFIELD_K21],
24019 +      },
24020 +    },
24021 +    {
24022 +      AVR32_OPC_RETEQ, 2, 0x5e000000, 0xfff00000,
24023 +      &avr32_syntax_table[AVR32_SYNTAX_RETEQ],
24024 +      BFD_RELOC_NONE, 1, -1,
24025 +      {
24026 +       &avr32_ifield_table[AVR32_IFIELD_RY],
24027 +      },
24028 +    },
24029 +    {
24030 +      AVR32_OPC_RETNE, 2, 0x5e100000, 0xfff00000,
24031 +      &avr32_syntax_table[AVR32_SYNTAX_RETNE],
24032 +      BFD_RELOC_NONE, 1, -1,
24033 +      {
24034 +       &avr32_ifield_table[AVR32_IFIELD_RY],
24035 +      },
24036 +    },
24037 +    {
24038 +      AVR32_OPC_RETCC, 2, 0x5e200000, 0xfff00000,
24039 +      &avr32_syntax_table[AVR32_SYNTAX_RETHS],
24040 +      BFD_RELOC_NONE, 1, -1,
24041 +      {
24042 +       &avr32_ifield_table[AVR32_IFIELD_RY],
24043 +      },
24044 +    },
24045 +    {
24046 +      AVR32_OPC_RETCS, 2, 0x5e300000, 0xfff00000,
24047 +      &avr32_syntax_table[AVR32_SYNTAX_RETLO],
24048 +      BFD_RELOC_NONE, 1, -1,
24049 +      {
24050 +       &avr32_ifield_table[AVR32_IFIELD_RY],
24051 +      },
24052 +    },
24053 +    {
24054 +      AVR32_OPC_RETGE, 2, 0x5e400000, 0xfff00000,
24055 +      &avr32_syntax_table[AVR32_SYNTAX_RETGE],
24056 +      BFD_RELOC_NONE, 1, -1,
24057 +      {
24058 +       &avr32_ifield_table[AVR32_IFIELD_RY],
24059 +      },
24060 +    },
24061 +    {
24062 +      AVR32_OPC_RETLT, 2, 0x5e500000, 0xfff00000,
24063 +      &avr32_syntax_table[AVR32_SYNTAX_RETLT],
24064 +      BFD_RELOC_NONE, 1, -1,
24065 +      {
24066 +       &avr32_ifield_table[AVR32_IFIELD_RY],
24067 +      },
24068 +    },
24069 +    {
24070 +      AVR32_OPC_RETMI, 2, 0x5e600000, 0xfff00000,
24071 +      &avr32_syntax_table[AVR32_SYNTAX_RETMI],
24072 +      BFD_RELOC_NONE, 1, -1,
24073 +      {
24074 +       &avr32_ifield_table[AVR32_IFIELD_RY],
24075 +      },
24076 +    },
24077 +    {
24078 +      AVR32_OPC_RETPL, 2, 0x5e700000, 0xfff00000,
24079 +      &avr32_syntax_table[AVR32_SYNTAX_RETPL],
24080 +      BFD_RELOC_NONE, 1, -1,
24081 +      {
24082 +       &avr32_ifield_table[AVR32_IFIELD_RY],
24083 +      },
24084 +    },
24085 +    {
24086 +      AVR32_OPC_RETLS, 2, 0x5e800000, 0xfff00000,
24087 +      &avr32_syntax_table[AVR32_SYNTAX_RETLS],
24088 +      BFD_RELOC_NONE, 1, -1,
24089 +      {
24090 +       &avr32_ifield_table[AVR32_IFIELD_RY],
24091 +      },
24092 +    },
24093 +    {
24094 +      AVR32_OPC_RETGT, 2, 0x5e900000, 0xfff00000,
24095 +      &avr32_syntax_table[AVR32_SYNTAX_RETGT],
24096 +      BFD_RELOC_NONE, 1, -1,
24097 +      {
24098 +       &avr32_ifield_table[AVR32_IFIELD_RY],
24099 +      },
24100 +    },
24101 +    {
24102 +      AVR32_OPC_RETLE, 2, 0x5ea00000, 0xfff00000,
24103 +      &avr32_syntax_table[AVR32_SYNTAX_RETLE],
24104 +      BFD_RELOC_NONE, 1, -1,
24105 +      {
24106 +       &avr32_ifield_table[AVR32_IFIELD_RY],
24107 +      },
24108 +    },
24109 +    {
24110 +      AVR32_OPC_RETHI, 2, 0x5eb00000, 0xfff00000,
24111 +      &avr32_syntax_table[AVR32_SYNTAX_RETHI],
24112 +      BFD_RELOC_NONE, 1, -1,
24113 +      {
24114 +       &avr32_ifield_table[AVR32_IFIELD_RY],
24115 +      },
24116 +    },
24117 +    {
24118 +      AVR32_OPC_RETVS, 2, 0x5ec00000, 0xfff00000,
24119 +      &avr32_syntax_table[AVR32_SYNTAX_RETVS],
24120 +      BFD_RELOC_NONE, 1, -1,
24121 +      {
24122 +       &avr32_ifield_table[AVR32_IFIELD_RY],
24123 +      },
24124 +    },
24125 +    {
24126 +      AVR32_OPC_RETVC, 2, 0x5ed00000, 0xfff00000,
24127 +      &avr32_syntax_table[AVR32_SYNTAX_RETVC],
24128 +      BFD_RELOC_NONE, 1, -1,
24129 +      {
24130 +       &avr32_ifield_table[AVR32_IFIELD_RY],
24131 +      },
24132 +    },
24133 +    {
24134 +      AVR32_OPC_RETQS, 2, 0x5ee00000, 0xfff00000,
24135 +      &avr32_syntax_table[AVR32_SYNTAX_RETQS],
24136 +      BFD_RELOC_NONE, 1, -1,
24137 +      {
24138 +       &avr32_ifield_table[AVR32_IFIELD_RY],
24139 +      },
24140 +    },
24141 +    {
24142 +      AVR32_OPC_RETAL, 2, 0x5ef00000, 0xfff00000,
24143 +      &avr32_syntax_table[AVR32_SYNTAX_RETAL],
24144 +      BFD_RELOC_NONE, 1, -1,
24145 +      {
24146 +       &avr32_ifield_table[AVR32_IFIELD_RY],
24147 +      },
24148 +    },
24149 +    {
24150 +      AVR32_OPC_RETD, 2, 0xd6230000, 0xffff0000,
24151 +      &avr32_syntax_table[AVR32_SYNTAX_RETD],
24152 +      BFD_RELOC_NONE, 0, -1, { NULL },
24153 +    },
24154 +    {
24155 +      AVR32_OPC_RETE, 2, 0xd6030000, 0xffff0000,
24156 +      &avr32_syntax_table[AVR32_SYNTAX_RETE],
24157 +      BFD_RELOC_NONE, 0, -1, { NULL },
24158 +    },
24159 +    {
24160 +      AVR32_OPC_RETJ, 2, 0xd6330000, 0xffff0000,
24161 +      &avr32_syntax_table[AVR32_SYNTAX_RETJ],
24162 +      BFD_RELOC_NONE, 0, -1, { NULL },
24163 +    },
24164 +    {
24165 +      AVR32_OPC_RETS, 2, 0xd6130000, 0xffff0000,
24166 +      &avr32_syntax_table[AVR32_SYNTAX_RETS],
24167 +      BFD_RELOC_NONE, 0, -1, { NULL },
24168 +    },
24169 +    {
24170 +      AVR32_OPC_RJMP, 2, 0xc0080000, 0xf00c0000,
24171 +      &avr32_syntax_table[AVR32_SYNTAX_RJMP],
24172 +      BFD_RELOC_AVR32_11H_PCREL, 1, 0,
24173 +      {
24174 +       &avr32_ifield_table[AVR32_IFIELD_K10],
24175 +      },
24176 +    },
24177 +    {
24178 +      AVR32_OPC_ROL, 2, 0x5cf00000, 0xfff00000,
24179 +      &avr32_syntax_table[AVR32_SYNTAX_ROL],
24180 +      BFD_RELOC_UNUSED, 1, -1,
24181 +      {
24182 +       &avr32_ifield_table[AVR32_IFIELD_RY],
24183 +      }
24184 +    },
24185 +    {
24186 +      AVR32_OPC_ROR, 2, 0x5d000000, 0xfff00000,
24187 +      &avr32_syntax_table[AVR32_SYNTAX_ROR],
24188 +      BFD_RELOC_UNUSED, 1, -1,
24189 +      {
24190 +       &avr32_ifield_table[AVR32_IFIELD_RY],
24191 +      }
24192 +    },
24193 +    {
24194 +      AVR32_OPC_RSUB1, 2, 0x00200000, 0xe1f00000,
24195 +      &avr32_syntax_table[AVR32_SYNTAX_RSUB1],
24196 +      BFD_RELOC_UNUSED, 2, -1,
24197 +      {
24198 +       &avr32_ifield_table[AVR32_IFIELD_RY],
24199 +       &avr32_ifield_table[AVR32_IFIELD_RX],
24200 +      },
24201 +    },
24202 +    {
24203 +      AVR32_OPC_RSUB2, 4, 0xe0001100, 0xe1f0ff00,
24204 +      &avr32_syntax_table[AVR32_SYNTAX_RSUB2],
24205 +      BFD_RELOC_AVR32_8S_EXT, 3, 2,
24206 +      {
24207 +       &avr32_ifield_table[AVR32_IFIELD_RY],
24208 +       &avr32_ifield_table[AVR32_IFIELD_RX],
24209 +       &avr32_ifield_table[AVR32_IFIELD_K8E],
24210 +      },
24211 +    },
24212 +    {
24213 +      AVR32_OPC_SATADD_H, 4, 0xe00002c0, 0xe1f0fff0,
24214 +      &avr32_syntax_table[AVR32_SYNTAX_SATADD_H],
24215 +      BFD_RELOC_UNUSED, 3, -1,
24216 +      {
24217 +       &avr32_ifield_table[AVR32_IFIELD_RD_E],
24218 +       &avr32_ifield_table[AVR32_IFIELD_RX],
24219 +       &avr32_ifield_table[AVR32_IFIELD_RY],
24220 +      },
24221 +    },
24222 +    {
24223 +      AVR32_OPC_SATADD_W, 4, 0xe00000c0, 0xe1f0fff0,
24224 +      &avr32_syntax_table[AVR32_SYNTAX_SATADD_W],
24225 +      BFD_RELOC_UNUSED, 3, -1,
24226 +      {
24227 +       &avr32_ifield_table[AVR32_IFIELD_RD_E],
24228 +       &avr32_ifield_table[AVR32_IFIELD_RX],
24229 +       &avr32_ifield_table[AVR32_IFIELD_RY],
24230 +      },
24231 +    },
24232 +    {
24233 +      AVR32_OPC_SATRNDS, 4, 0xf3b00000, 0xfff0fc00,
24234 +      &avr32_syntax_table[AVR32_SYNTAX_SATRNDS],
24235 +      BFD_RELOC_UNUSED, 3, -1,
24236 +      {
24237 +       &avr32_ifield_table[AVR32_IFIELD_RY],
24238 +       &avr32_ifield_table[AVR32_IFIELD_K5E],
24239 +       &avr32_ifield_table[AVR32_IFIELD_S5],
24240 +      },
24241 +    },
24242 +    {
24243 +      AVR32_OPC_SATRNDU, 4, 0xf3b00400, 0xfff0fc00,
24244 +      &avr32_syntax_table[AVR32_SYNTAX_SATRNDU],
24245 +      BFD_RELOC_UNUSED, 3, -1,
24246 +      {
24247 +       &avr32_ifield_table[AVR32_IFIELD_RY],
24248 +       &avr32_ifield_table[AVR32_IFIELD_K5E],
24249 +       &avr32_ifield_table[AVR32_IFIELD_S5],
24250 +      },
24251 +    },
24252 +    {
24253 +      AVR32_OPC_SATS, 4, 0xf1b00000, 0xfff0fc00,
24254 +      &avr32_syntax_table[AVR32_SYNTAX_SATS],
24255 +      BFD_RELOC_UNUSED, 3, -1,
24256 +      {
24257 +       &avr32_ifield_table[AVR32_IFIELD_RY],
24258 +       &avr32_ifield_table[AVR32_IFIELD_K5E],
24259 +       &avr32_ifield_table[AVR32_IFIELD_S5],
24260 +      },
24261 +    },
24262 +    {
24263 +      AVR32_OPC_SATSUB_H, 4, 0xe00003c0, 0xe1f0fff0,
24264 +      &avr32_syntax_table[AVR32_SYNTAX_SATSUB_H],
24265 +      BFD_RELOC_UNUSED, 3, -1,
24266 +      {
24267 +       &avr32_ifield_table[AVR32_IFIELD_RD_E],
24268 +       &avr32_ifield_table[AVR32_IFIELD_RX],
24269 +       &avr32_ifield_table[AVR32_IFIELD_RY],
24270 +      },
24271 +    },
24272 +    {
24273 +      AVR32_OPC_SATSUB_W1, 4, 0xe00001c0, 0xe1f0fff0,
24274 +      &avr32_syntax_table[AVR32_SYNTAX_SATSUB_W1],
24275 +      BFD_RELOC_UNUSED, 3, -1,
24276 +      {
24277 +       &avr32_ifield_table[AVR32_IFIELD_RD_E],
24278 +       &avr32_ifield_table[AVR32_IFIELD_RX],
24279 +       &avr32_ifield_table[AVR32_IFIELD_RY],
24280 +      },
24281 +    },
24282 +    {
24283 +      AVR32_OPC_SATSUB_W2, 4, 0xe0d00000, 0xe1f00000,
24284 +      &avr32_syntax_table[AVR32_SYNTAX_SATSUB_W2],
24285 +      BFD_RELOC_UNUSED, 3, -1,
24286 +      {
24287 +       &avr32_ifield_table[AVR32_IFIELD_RY],
24288 +       &avr32_ifield_table[AVR32_IFIELD_RX],
24289 +       &avr32_ifield_table[AVR32_IFIELD_K16],
24290 +      },
24291 +    },
24292 +    {
24293 +      AVR32_OPC_SATU, 4, 0xf1b00400, 0xfff0fc00,
24294 +      &avr32_syntax_table[AVR32_SYNTAX_SATU],
24295 +      BFD_RELOC_UNUSED, 3, -1,
24296 +      {
24297 +       &avr32_ifield_table[AVR32_IFIELD_RY],
24298 +       &avr32_ifield_table[AVR32_IFIELD_K5E],
24299 +       &avr32_ifield_table[AVR32_IFIELD_S5],
24300 +      },
24301 +    },
24302 +    {
24303 +      AVR32_OPC_SBC, 4, 0xe0000140, 0xe1f0fff0,
24304 +      &avr32_syntax_table[AVR32_SYNTAX_SBC],
24305 +      BFD_RELOC_UNUSED, 3, -1,
24306 +      {
24307 +       &avr32_ifield_table[AVR32_IFIELD_RD_E],
24308 +       &avr32_ifield_table[AVR32_IFIELD_RX],
24309 +       &avr32_ifield_table[AVR32_IFIELD_RY],
24310 +      },
24311 +    },
24312 +    {
24313 +      AVR32_OPC_SBR, 2, 0xa1a00000, 0xe1e00000,
24314 +      &avr32_syntax_table[AVR32_SYNTAX_SBR],
24315 +      BFD_RELOC_UNUSED, 2, -1,
24316 +      {
24317 +       &avr32_ifield_table[AVR32_IFIELD_RY],
24318 +       &avr32_ifield_table[AVR32_IFIELD_BIT5C],
24319 +      },
24320 +    },
24321 +    {
24322 +      AVR32_OPC_SCALL, 2, 0xd7330000, 0xffff0000,
24323 +      &avr32_syntax_table[AVR32_SYNTAX_SCALL],
24324 +      BFD_RELOC_UNUSED, 0, -1, { NULL },
24325 +    },
24326 +    {
24327 +      AVR32_OPC_SCR, 2, 0x5c100000, 0xfff00000,
24328 +      &avr32_syntax_table[AVR32_SYNTAX_SCR],
24329 +      BFD_RELOC_UNUSED, 1, -1,
24330 +      {
24331 +       &avr32_ifield_table[AVR32_IFIELD_RY],
24332 +      },
24333 +    },
24334 +    {
24335 +      AVR32_OPC_SLEEP, 4, 0xe9b00000, 0xffffff00,
24336 +      &avr32_syntax_table[AVR32_SYNTAX_SLEEP],
24337 +      BFD_RELOC_AVR32_8S_EXT, 1, 0,
24338 +      {
24339 +       &avr32_ifield_table[AVR32_IFIELD_K8E],
24340 +      },
24341 +    },
24342 +    {
24343 +      AVR32_OPC_SREQ, 2, 0x5f000000, 0xfff00000,
24344 +      &avr32_syntax_table[AVR32_SYNTAX_SREQ],
24345 +      BFD_RELOC_UNUSED, 1, -1,
24346 +      {
24347 +       &avr32_ifield_table[AVR32_IFIELD_RY],
24348 +      },
24349 +    },
24350 +    {
24351 +      AVR32_OPC_SRNE, 2, 0x5f100000, 0xfff00000,
24352 +      &avr32_syntax_table[AVR32_SYNTAX_SRNE],
24353 +      BFD_RELOC_UNUSED, 1, -1,
24354 +      {
24355 +       &avr32_ifield_table[AVR32_IFIELD_RY],
24356 +      },
24357 +    },
24358 +    {
24359 +      AVR32_OPC_SRCC, 2, 0x5f200000, 0xfff00000,
24360 +      &avr32_syntax_table[AVR32_SYNTAX_SRHS],
24361 +      BFD_RELOC_UNUSED, 1, -1,
24362 +      {
24363 +       &avr32_ifield_table[AVR32_IFIELD_RY],
24364 +      },
24365 +    },
24366 +    {
24367 +      AVR32_OPC_SRCS, 2, 0x5f300000, 0xfff00000,
24368 +      &avr32_syntax_table[AVR32_SYNTAX_SRLO],
24369 +      BFD_RELOC_UNUSED, 1, -1,
24370 +      {
24371 +       &avr32_ifield_table[AVR32_IFIELD_RY],
24372 +      },
24373 +    },
24374 +    {
24375 +      AVR32_OPC_SRGE, 2, 0x5f400000, 0xfff00000,
24376 +      &avr32_syntax_table[AVR32_SYNTAX_SRGE],
24377 +      BFD_RELOC_UNUSED, 1, -1,
24378 +      {
24379 +       &avr32_ifield_table[AVR32_IFIELD_RY],
24380 +      },
24381 +    },
24382 +    {
24383 +      AVR32_OPC_SRLT, 2, 0x5f500000, 0xfff00000,
24384 +      &avr32_syntax_table[AVR32_SYNTAX_SRLT],
24385 +      BFD_RELOC_UNUSED, 1, -1,
24386 +      {
24387 +       &avr32_ifield_table[AVR32_IFIELD_RY],
24388 +      },
24389 +    },
24390 +    {
24391 +      AVR32_OPC_SRMI, 2, 0x5f600000, 0xfff00000,
24392 +      &avr32_syntax_table[AVR32_SYNTAX_SRMI],
24393 +      BFD_RELOC_UNUSED, 1, -1,
24394 +      {
24395 +       &avr32_ifield_table[AVR32_IFIELD_RY],
24396 +      },
24397 +    },
24398 +    {
24399 +      AVR32_OPC_SRPL, 2, 0x5f700000, 0xfff00000,
24400 +      &avr32_syntax_table[AVR32_SYNTAX_SRPL],
24401 +      BFD_RELOC_UNUSED, 1, -1,
24402 +      {
24403 +       &avr32_ifield_table[AVR32_IFIELD_RY],
24404 +      },
24405 +    },
24406 +    {
24407 +      AVR32_OPC_SRLS, 2, 0x5f800000, 0xfff00000,
24408 +      &avr32_syntax_table[AVR32_SYNTAX_SRLS],
24409 +      BFD_RELOC_UNUSED, 1, -1,
24410 +      {
24411 +       &avr32_ifield_table[AVR32_IFIELD_RY],
24412 +      },
24413 +    },
24414 +    {
24415 +      AVR32_OPC_SRGT, 2, 0x5f900000, 0xfff00000,
24416 +      &avr32_syntax_table[AVR32_SYNTAX_SRGT],
24417 +      BFD_RELOC_UNUSED, 1, -1,
24418 +      {
24419 +       &avr32_ifield_table[AVR32_IFIELD_RY],
24420 +      },
24421 +    },
24422 +    {
24423 +      AVR32_OPC_SRLE, 2, 0x5fa00000, 0xfff00000,
24424 +      &avr32_syntax_table[AVR32_SYNTAX_SRLE],
24425 +      BFD_RELOC_UNUSED, 1, -1,
24426 +      {
24427 +       &avr32_ifield_table[AVR32_IFIELD_RY],
24428 +      },
24429 +    },
24430 +    {
24431 +      AVR32_OPC_SRHI, 2, 0x5fb00000, 0xfff00000,
24432 +      &avr32_syntax_table[AVR32_SYNTAX_SRHI],
24433 +      BFD_RELOC_UNUSED, 1, -1,
24434 +      {
24435 +       &avr32_ifield_table[AVR32_IFIELD_RY],
24436 +      },
24437 +    },
24438 +    {
24439 +      AVR32_OPC_SRVS, 2, 0x5fc00000, 0xfff00000,
24440 +      &avr32_syntax_table[AVR32_SYNTAX_SRVS],
24441 +      BFD_RELOC_UNUSED, 1, -1,
24442 +      {
24443 +       &avr32_ifield_table[AVR32_IFIELD_RY],
24444 +      },
24445 +    },
24446 +    {
24447 +      AVR32_OPC_SRVC, 2, 0x5fd00000, 0xfff00000,
24448 +      &avr32_syntax_table[AVR32_SYNTAX_SRVC],
24449 +      BFD_RELOC_UNUSED, 1, -1,
24450 +      {
24451 +       &avr32_ifield_table[AVR32_IFIELD_RY],
24452 +      },
24453 +    },
24454 +    {
24455 +      AVR32_OPC_SRQS, 2, 0x5fe00000, 0xfff00000,
24456 +      &avr32_syntax_table[AVR32_SYNTAX_SRQS],
24457 +      BFD_RELOC_UNUSED, 1, -1,
24458 +      {
24459 +       &avr32_ifield_table[AVR32_IFIELD_RY],
24460 +      },
24461 +    },
24462 +    {
24463 +      AVR32_OPC_SRAL, 2, 0x5ff00000, 0xfff00000,
24464 +      &avr32_syntax_table[AVR32_SYNTAX_SRAL],
24465 +      BFD_RELOC_UNUSED, 1, -1,
24466 +      {
24467 +       &avr32_ifield_table[AVR32_IFIELD_RY],
24468 +      },
24469 +    },
24470 +    {
24471 +      AVR32_OPC_SSRF, 2, 0xd2030000, 0xfe0f0000,
24472 +      &avr32_syntax_table[AVR32_SYNTAX_SSRF],
24473 +      BFD_RELOC_UNUSED, 1, -1,
24474 +      {
24475 +       &avr32_ifield_table[AVR32_IFIELD_K5C],
24476 +      },
24477 +    },
24478 +    {
24479 +      AVR32_OPC_ST_B1, 2, 0x00c00000, 0xe1f00000,
24480 +      &avr32_syntax_table[AVR32_SYNTAX_ST_B1],
24481 +      BFD_RELOC_UNUSED, 2, -1,
24482 +      {
24483 +       &avr32_ifield_table[AVR32_IFIELD_RX],
24484 +       &avr32_ifield_table[AVR32_IFIELD_RY],
24485 +      },
24486 +    },
24487 +    {
24488 +      AVR32_OPC_ST_B2, 2, 0x00f00000, 0xe1f00000,
24489 +      &avr32_syntax_table[AVR32_SYNTAX_ST_B2],
24490 +      BFD_RELOC_UNUSED, 2, -1,
24491 +      {
24492 +       &avr32_ifield_table[AVR32_IFIELD_RX],
24493 +       &avr32_ifield_table[AVR32_IFIELD_RY],
24494 +      },
24495 +    },
24496 +    {
24497 +      AVR32_OPC_ST_B5, 4, 0xe0000b00, 0xe1f0ffc0,
24498 +      &avr32_syntax_table[AVR32_SYNTAX_ST_B5],
24499 +      BFD_RELOC_UNUSED, 4, -1,
24500 +      {
24501 +       &avr32_ifield_table[AVR32_IFIELD_RX],
24502 +       &avr32_ifield_table[AVR32_IFIELD_RY],
24503 +       &avr32_ifield_table[AVR32_IFIELD_K2],
24504 +       &avr32_ifield_table[AVR32_IFIELD_RD_E],
24505 +      },
24506 +    },
24507 +    {
24508 +      AVR32_OPC_ST_B3, 2, 0xa0800000, 0xe1800000,
24509 +      &avr32_syntax_table[AVR32_SYNTAX_ST_B3],
24510 +      BFD_RELOC_AVR32_3U, 3, 1,
24511 +      {
24512 +       &avr32_ifield_table[AVR32_IFIELD_RX],
24513 +       &avr32_ifield_table[AVR32_IFIELD_K3],
24514 +       &avr32_ifield_table[AVR32_IFIELD_RY],
24515 +      },
24516 +    },
24517 +    {
24518 +      AVR32_OPC_ST_B4, 4, 0xe1600000, 0xe1f00000,
24519 +      &avr32_syntax_table[AVR32_SYNTAX_ST_B4],
24520 +      BFD_RELOC_AVR32_16S, 3, 1,
24521 +      {
24522 +       &avr32_ifield_table[AVR32_IFIELD_RX],
24523 +       &avr32_ifield_table[AVR32_IFIELD_K16],
24524 +       &avr32_ifield_table[AVR32_IFIELD_RY],
24525 +      },
24526 +    },
24527 +    {
24528 +      AVR32_OPC_ST_D1, 2, 0xa1200000, 0xe1f10000,
24529 +      &avr32_syntax_table[AVR32_SYNTAX_ST_D1],
24530 +      BFD_RELOC_UNUSED, 2, -1,
24531 +      {
24532 +       &avr32_ifield_table[AVR32_IFIELD_RX],
24533 +       &avr32_ifield_table[AVR32_IFIELD_RY_DW],
24534 +      },
24535 +    },
24536 +    {
24537 +      AVR32_OPC_ST_D2, 2, 0xa1210000, 0xe1f10000,
24538 +      &avr32_syntax_table[AVR32_SYNTAX_ST_D2],
24539 +      BFD_RELOC_UNUSED, 2, -1,
24540 +      {
24541 +       &avr32_ifield_table[AVR32_IFIELD_RX],
24542 +       &avr32_ifield_table[AVR32_IFIELD_RY_DW],
24543 +      },
24544 +    },
24545 +    {
24546 +      AVR32_OPC_ST_D3, 2, 0xa1110000, 0xe1f10000,
24547 +      &avr32_syntax_table[AVR32_SYNTAX_ST_D3],
24548 +      BFD_RELOC_UNUSED, 2, -1,
24549 +      {
24550 +       &avr32_ifield_table[AVR32_IFIELD_RX],
24551 +       &avr32_ifield_table[AVR32_IFIELD_RY_DW],
24552 +      },
24553 +    },
24554 +    {
24555 +      AVR32_OPC_ST_D5, 4, 0xe0000800, 0xe1f0ffc1,
24556 +      &avr32_syntax_table[AVR32_SYNTAX_ST_D5],
24557 +      BFD_RELOC_UNUSED, 4, -1,
24558 +      {
24559 +       &avr32_ifield_table[AVR32_IFIELD_RX],
24560 +       &avr32_ifield_table[AVR32_IFIELD_RY],
24561 +       &avr32_ifield_table[AVR32_IFIELD_K2],
24562 +       &avr32_ifield_table[AVR32_IFIELD_RD_DW],
24563 +      },
24564 +    },
24565 +    {
24566 +      AVR32_OPC_ST_D4, 4, 0xe0e10000, 0xe1f10000,
24567 +      &avr32_syntax_table[AVR32_SYNTAX_ST_D4],
24568 +      BFD_RELOC_AVR32_16S, 3, 1,
24569 +      {
24570 +       &avr32_ifield_table[AVR32_IFIELD_RX],
24571 +       &avr32_ifield_table[AVR32_IFIELD_K16],
24572 +       &avr32_ifield_table[AVR32_IFIELD_RY_DW],
24573 +      },
24574 +    },
24575 +    {
24576 +      AVR32_OPC_ST_H1, 2, 0x00b00000, 0xe1f00000,
24577 +      &avr32_syntax_table[AVR32_SYNTAX_ST_H1],
24578 +      BFD_RELOC_UNUSED, 2, -1,
24579 +      {
24580 +       &avr32_ifield_table[AVR32_IFIELD_RX],
24581 +       &avr32_ifield_table[AVR32_IFIELD_RY],
24582 +      },
24583 +    },
24584 +    {
24585 +      AVR32_OPC_ST_H2, 2, 0x00e00000, 0xe1f00000,
24586 +      &avr32_syntax_table[AVR32_SYNTAX_ST_H2],
24587 +      BFD_RELOC_UNUSED, 2, -1,
24588 +      {
24589 +       &avr32_ifield_table[AVR32_IFIELD_RX],
24590 +       &avr32_ifield_table[AVR32_IFIELD_RY],
24591 +      },
24592 +    },
24593 +    {
24594 +      AVR32_OPC_ST_H5, 4, 0xe0000a00, 0xe1f0ffc0,
24595 +      &avr32_syntax_table[AVR32_SYNTAX_ST_H5],
24596 +      BFD_RELOC_UNUSED, 4, -1,
24597 +      {
24598 +       &avr32_ifield_table[AVR32_IFIELD_RX],
24599 +       &avr32_ifield_table[AVR32_IFIELD_RY],
24600 +       &avr32_ifield_table[AVR32_IFIELD_K2],
24601 +       &avr32_ifield_table[AVR32_IFIELD_RD_E],
24602 +      },
24603 +    },
24604 +    {
24605 +      AVR32_OPC_ST_H3, 2, 0xa0000000, 0xe1800000,
24606 +      &avr32_syntax_table[AVR32_SYNTAX_ST_H3],
24607 +      BFD_RELOC_AVR32_4UH, 3, 1,
24608 +      {
24609 +       &avr32_ifield_table[AVR32_IFIELD_RX],
24610 +       &avr32_ifield_table[AVR32_IFIELD_K3],
24611 +       &avr32_ifield_table[AVR32_IFIELD_RY],
24612 +      },
24613 +    },
24614 +    {
24615 +      AVR32_OPC_ST_H4, 4, 0xe1500000, 0xe1f00000,
24616 +      &avr32_syntax_table[AVR32_SYNTAX_ST_H4],
24617 +      BFD_RELOC_AVR32_16S, 3, 1,
24618 +      {
24619 +       &avr32_ifield_table[AVR32_IFIELD_RX],
24620 +       &avr32_ifield_table[AVR32_IFIELD_K16],
24621 +       &avr32_ifield_table[AVR32_IFIELD_RY],
24622 +      },
24623 +    },
24624 +    {
24625 +      AVR32_OPC_ST_W1, 2, 0x00a00000, 0xe1f00000,
24626 +      &avr32_syntax_table[AVR32_SYNTAX_ST_W1],
24627 +      BFD_RELOC_UNUSED, 2, -1,
24628 +      {
24629 +       &avr32_ifield_table[AVR32_IFIELD_RX],
24630 +       &avr32_ifield_table[AVR32_IFIELD_RY],
24631 +      },
24632 +    },
24633 +    {
24634 +      AVR32_OPC_ST_W2, 2, 0x00d00000, 0xe1f00000,
24635 +      &avr32_syntax_table[AVR32_SYNTAX_ST_W2],
24636 +      BFD_RELOC_UNUSED, 2, -1,
24637 +      {
24638 +       &avr32_ifield_table[AVR32_IFIELD_RX],
24639 +       &avr32_ifield_table[AVR32_IFIELD_RY],
24640 +      },
24641 +    },
24642 +    {
24643 +      AVR32_OPC_ST_W5, 4, 0xe0000900, 0xe1f0ffc0,
24644 +      &avr32_syntax_table[AVR32_SYNTAX_ST_W5],
24645 +      BFD_RELOC_UNUSED, 4, -1,
24646 +      {
24647 +       &avr32_ifield_table[AVR32_IFIELD_RX],
24648 +       &avr32_ifield_table[AVR32_IFIELD_RY],
24649 +       &avr32_ifield_table[AVR32_IFIELD_K2],
24650 +       &avr32_ifield_table[AVR32_IFIELD_RD_E],
24651 +      },
24652 +    },
24653 +    {
24654 +      AVR32_OPC_ST_W3, 2, 0x81000000, 0xe1000000,
24655 +      &avr32_syntax_table[AVR32_SYNTAX_ST_W3],
24656 +      BFD_RELOC_AVR32_6UW, 3, 1,
24657 +      {
24658 +       &avr32_ifield_table[AVR32_IFIELD_RX],
24659 +       &avr32_ifield_table[AVR32_IFIELD_K4],
24660 +       &avr32_ifield_table[AVR32_IFIELD_RY],
24661 +      },
24662 +    },
24663 +    {
24664 +      AVR32_OPC_ST_W4, 4, 0xe1400000, 0xe1f00000,
24665 +      &avr32_syntax_table[AVR32_SYNTAX_ST_W4],
24666 +      BFD_RELOC_AVR32_16S, 3, 1,
24667 +      {
24668 +       &avr32_ifield_table[AVR32_IFIELD_RX],
24669 +       &avr32_ifield_table[AVR32_IFIELD_K16],
24670 +       &avr32_ifield_table[AVR32_IFIELD_RY],
24671 +      },
24672 +    },
24673 +    {
24674 +      AVR32_OPC_STC_D1, 4, 0xeba01000, 0xfff01100,
24675 +      &avr32_syntax_table[AVR32_SYNTAX_STC_D1],
24676 +      BFD_RELOC_AVR32_10UW, 4, 2,
24677 +      {
24678 +       &avr32_ifield_table[AVR32_IFIELD_CPNO],
24679 +       &avr32_ifield_table[AVR32_IFIELD_RY],
24680 +       &avr32_ifield_table[AVR32_IFIELD_K8E],
24681 +       &avr32_ifield_table[AVR32_IFIELD_CRD_DW],
24682 +      },
24683 +    },
24684 +    {
24685 +      AVR32_OPC_STC_D2, 4, 0xefa00070, 0xfff011f0,
24686 +      &avr32_syntax_table[AVR32_SYNTAX_STC_D2],
24687 +      BFD_RELOC_UNUSED, 3, -1,
24688 +      {
24689 +       &avr32_ifield_table[AVR32_IFIELD_CPNO],
24690 +       &avr32_ifield_table[AVR32_IFIELD_RY],
24691 +       &avr32_ifield_table[AVR32_IFIELD_CRD_DW],
24692 +      },
24693 +    },
24694 +    {
24695 +      AVR32_OPC_STC_D3, 4, 0xefa010c0, 0xfff011c0,
24696 +      &avr32_syntax_table[AVR32_SYNTAX_STC_D3],
24697 +      BFD_RELOC_UNUSED, 5, -1,
24698 +      {
24699 +       &avr32_ifield_table[AVR32_IFIELD_CPNO],
24700 +       &avr32_ifield_table[AVR32_IFIELD_RY],
24701 +       &avr32_ifield_table[AVR32_IFIELD_RD_E],
24702 +       &avr32_ifield_table[AVR32_IFIELD_K2],
24703 +       &avr32_ifield_table[AVR32_IFIELD_CRD_DW],
24704 +      },
24705 +    },
24706 +    {
24707 +      AVR32_OPC_STC_W1, 4, 0xeba00000, 0xfff01000,
24708 +      &avr32_syntax_table[AVR32_SYNTAX_STC_W1],
24709 +      BFD_RELOC_AVR32_10UW, 4, 2,
24710 +      {
24711 +       &avr32_ifield_table[AVR32_IFIELD_CPNO],
24712 +       &avr32_ifield_table[AVR32_IFIELD_RY],
24713 +       &avr32_ifield_table[AVR32_IFIELD_K8E],
24714 +       &avr32_ifield_table[AVR32_IFIELD_CRD_RI],
24715 +      },
24716 +    },
24717 +    {
24718 +      AVR32_OPC_STC_W2, 4, 0xefa00060, 0xfff010ff,
24719 +      &avr32_syntax_table[AVR32_SYNTAX_STC_W2],
24720 +      BFD_RELOC_UNUSED, 3, -1,
24721 +      {
24722 +       &avr32_ifield_table[AVR32_IFIELD_CPNO],
24723 +       &avr32_ifield_table[AVR32_IFIELD_RY],
24724 +       &avr32_ifield_table[AVR32_IFIELD_CRD_RI],
24725 +      },
24726 +    },
24727 +    {
24728 +      AVR32_OPC_STC_W3, 4, 0xefa01080, 0xfff010c0,
24729 +      &avr32_syntax_table[AVR32_SYNTAX_STC_W3],
24730 +      BFD_RELOC_UNUSED, 5, -1,
24731 +      {
24732 +       &avr32_ifield_table[AVR32_IFIELD_CPNO],
24733 +       &avr32_ifield_table[AVR32_IFIELD_RY],
24734 +       &avr32_ifield_table[AVR32_IFIELD_RD_E],
24735 +       &avr32_ifield_table[AVR32_IFIELD_K2],
24736 +       &avr32_ifield_table[AVR32_IFIELD_CRD_RI],
24737 +      },
24738 +    },
24739 +    {
24740 +      AVR32_OPC_STC0_D, 4, 0xf7a00000, 0xfff00100,
24741 +      &avr32_syntax_table[AVR32_SYNTAX_STC0_D],
24742 +      BFD_RELOC_AVR32_14UW, 3, 1,
24743 +      {
24744 +       &avr32_ifield_table[AVR32_IFIELD_RY],
24745 +       &avr32_ifield_table[AVR32_IFIELD_K12CP],
24746 +       &avr32_ifield_table[AVR32_IFIELD_CRD_DW],
24747 +      },
24748 +    },
24749 +    {
24750 +      AVR32_OPC_STC0_W, 4, 0xf5a00000, 0xfff00000,
24751 +      &avr32_syntax_table[AVR32_SYNTAX_STC0_W],
24752 +      BFD_RELOC_AVR32_14UW, 3, 1,
24753 +      {
24754 +       &avr32_ifield_table[AVR32_IFIELD_RY],
24755 +       &avr32_ifield_table[AVR32_IFIELD_K12CP],
24756 +       &avr32_ifield_table[AVR32_IFIELD_CRD_RI],
24757 +      },
24758 +    },
24759 +    {
24760 +      AVR32_OPC_STCM_D, 4, 0xeda00500, 0xfff01f00,
24761 +      &avr32_syntax_table[AVR32_SYNTAX_STCM_D],
24762 +      BFD_RELOC_UNUSED, 3, -1,
24763 +      {
24764 +       &avr32_ifield_table[AVR32_IFIELD_CPNO],
24765 +       &avr32_ifield_table[AVR32_IFIELD_RY],
24766 +       &avr32_ifield_table[AVR32_IFIELD_K8E],
24767 +      },
24768 +    },
24769 +    {
24770 +      AVR32_OPC_STCM_D_PU, 4, 0xeda01500, 0xfff01f00,
24771 +      &avr32_syntax_table[AVR32_SYNTAX_STCM_D_PU],
24772 +      BFD_RELOC_UNUSED, 3, -1,
24773 +      {
24774 +       &avr32_ifield_table[AVR32_IFIELD_CPNO],
24775 +       &avr32_ifield_table[AVR32_IFIELD_RY],
24776 +       &avr32_ifield_table[AVR32_IFIELD_K8E],
24777 +      },
24778 +    },
24779 +    {
24780 +      AVR32_OPC_STCM_W, 4, 0xeda00200, 0xfff01e00,
24781 +      &avr32_syntax_table[AVR32_SYNTAX_STCM_W],
24782 +      BFD_RELOC_UNUSED, 4, -1,
24783 +      {
24784 +       &avr32_ifield_table[AVR32_IFIELD_CPNO],
24785 +       &avr32_ifield_table[AVR32_IFIELD_RY],
24786 +       &avr32_ifield_table[AVR32_IFIELD_K8E],
24787 +       &avr32_ifield_table[AVR32_IFIELD_CM_HL],
24788 +      },
24789 +    },
24790 +    {
24791 +      AVR32_OPC_STCM_W_PU, 4, 0xeda01200, 0xfff01e00,
24792 +      &avr32_syntax_table[AVR32_SYNTAX_STCM_W_PU],
24793 +      BFD_RELOC_UNUSED, 4, -1,
24794 +      {
24795 +       &avr32_ifield_table[AVR32_IFIELD_CPNO],
24796 +       &avr32_ifield_table[AVR32_IFIELD_RY],
24797 +       &avr32_ifield_table[AVR32_IFIELD_K8E],
24798 +       &avr32_ifield_table[AVR32_IFIELD_CM_HL],
24799 +      },
24800 +    },
24801 +    {
24802 +      AVR32_OPC_STCOND, 4, 0xe1700000, 0xe1f00000,
24803 +      &avr32_syntax_table[AVR32_SYNTAX_STCOND],
24804 +      BFD_RELOC_UNUSED, 3, -1,
24805 +      {
24806 +       &avr32_ifield_table[AVR32_IFIELD_RX],
24807 +       &avr32_ifield_table[AVR32_IFIELD_K16],
24808 +       &avr32_ifield_table[AVR32_IFIELD_RY],
24809 +      },
24810 +    },
24811 +    {
24812 +      AVR32_OPC_STDSP, 2, 0x50000000, 0xf8000000,
24813 +      &avr32_syntax_table[AVR32_SYNTAX_STDSP],
24814 +      BFD_RELOC_UNUSED, 2, -1,
24815 +      {
24816 +       &avr32_ifield_table[AVR32_IFIELD_K7C],
24817 +       &avr32_ifield_table[AVR32_IFIELD_RY],
24818 +      },
24819 +    },
24820 +    {
24821 +      AVR32_OPC_STHH_W2, 4, 0xe1e08000, 0xe1f0c0c0,
24822 +      &avr32_syntax_table[AVR32_SYNTAX_STHH_W2],
24823 +      BFD_RELOC_UNUSED, 7, -1,
24824 +      {
24825 +       &avr32_ifield_table[AVR32_IFIELD_RD_E],
24826 +       &avr32_ifield_table[AVR32_IFIELD_CRD_RI],
24827 +       &avr32_ifield_table[AVR32_IFIELD_K2],
24828 +       &avr32_ifield_table[AVR32_IFIELD_RX],
24829 +       &avr32_ifield_table[AVR32_IFIELD_X2],
24830 +       &avr32_ifield_table[AVR32_IFIELD_RY],
24831 +       &avr32_ifield_table[AVR32_IFIELD_Y2],
24832 +      },
24833 +    },
24834 +    {
24835 +      AVR32_OPC_STHH_W1, 4, 0xe1e0c000, 0xe1f0c000,
24836 +      &avr32_syntax_table[AVR32_SYNTAX_STHH_W1],
24837 +      BFD_RELOC_AVR32_STHH_W, 6, 1,
24838 +      {
24839 +       &avr32_ifield_table[AVR32_IFIELD_RD_E],
24840 +       &avr32_ifield_table[AVR32_IFIELD_K8E2],
24841 +       &avr32_ifield_table[AVR32_IFIELD_RX],
24842 +       &avr32_ifield_table[AVR32_IFIELD_X2],
24843 +       &avr32_ifield_table[AVR32_IFIELD_RY],
24844 +       &avr32_ifield_table[AVR32_IFIELD_Y2],
24845 +      },
24846 +    },
24847 +    {
24848 +      AVR32_OPC_STM, 4, 0xe9c00000, 0xfff00000,
24849 +      &avr32_syntax_table[AVR32_SYNTAX_STM],
24850 +      BFD_RELOC_UNUSED, 2, -1,
24851 +      {
24852 +       &avr32_ifield_table[AVR32_IFIELD_RY],
24853 +       &avr32_ifield_table[AVR32_IFIELD_K16],
24854 +      },
24855 +    },
24856 +    {
24857 +      AVR32_OPC_STM_PU, 4, 0xebc00000, 0xfff00000,
24858 +      &avr32_syntax_table[AVR32_SYNTAX_STM_PU],
24859 +      BFD_RELOC_UNUSED, 2, -1,
24860 +      {
24861 +       &avr32_ifield_table[AVR32_IFIELD_RY],
24862 +       &avr32_ifield_table[AVR32_IFIELD_K16],
24863 +      },
24864 +    },
24865 +    {
24866 +      AVR32_OPC_STMTS, 4, 0xedc00000, 0xfff00000,
24867 +      &avr32_syntax_table[AVR32_SYNTAX_STMTS],
24868 +      BFD_RELOC_UNUSED, 2, -1,
24869 +      {
24870 +       &avr32_ifield_table[AVR32_IFIELD_RY],
24871 +       &avr32_ifield_table[AVR32_IFIELD_K16],
24872 +      },
24873 +    },
24874 +    {
24875 +      AVR32_OPC_STMTS_PU, 4, 0xefc00000, 0xfff00000,
24876 +      &avr32_syntax_table[AVR32_SYNTAX_STMTS_PU],
24877 +      BFD_RELOC_UNUSED, 2, -1,
24878 +      {
24879 +       &avr32_ifield_table[AVR32_IFIELD_RY],
24880 +       &avr32_ifield_table[AVR32_IFIELD_K16],
24881 +      },
24882 +    },
24883 +    {
24884 +      AVR32_OPC_STSWP_H, 4, 0xe1d09000, 0xe1f0f000,
24885 +      &avr32_syntax_table[AVR32_SYNTAX_STSWP_H],
24886 +      BFD_RELOC_UNUSED, 3, -1,
24887 +      {
24888 +       &avr32_ifield_table[AVR32_IFIELD_RX],
24889 +       &avr32_ifield_table[AVR32_IFIELD_K12],
24890 +       &avr32_ifield_table[AVR32_IFIELD_RY],
24891 +      },
24892 +    },
24893 +    {
24894 +      AVR32_OPC_STSWP_W, 4, 0xe1d0a000, 0xe1f0f000,
24895 +      &avr32_syntax_table[AVR32_SYNTAX_STSWP_W],
24896 +      BFD_RELOC_UNUSED, 3, -1,
24897 +      {
24898 +       &avr32_ifield_table[AVR32_IFIELD_RX],
24899 +       &avr32_ifield_table[AVR32_IFIELD_K12],
24900 +       &avr32_ifield_table[AVR32_IFIELD_RY],
24901 +      },
24902 +    },
24903 +    {
24904 +      AVR32_OPC_SUB1, 2, 0x00100000, 0xe1f00000,
24905 +      &avr32_syntax_table[AVR32_SYNTAX_SUB1],
24906 +      BFD_RELOC_UNUSED, 2, -1,
24907 +      {
24908 +       &avr32_ifield_table[AVR32_IFIELD_RY],
24909 +       &avr32_ifield_table[AVR32_IFIELD_RX],
24910 +      },
24911 +    },
24912 +    {
24913 +      AVR32_OPC_SUB2, 4, 0xe0000100, 0xe1f0ffc0,
24914 +      &avr32_syntax_table[AVR32_SYNTAX_SUB2],
24915 +      BFD_RELOC_UNUSED, 4, -1,
24916 +      {
24917 +       &avr32_ifield_table[AVR32_IFIELD_RD_E],
24918 +       &avr32_ifield_table[AVR32_IFIELD_RX],
24919 +       &avr32_ifield_table[AVR32_IFIELD_RY],
24920 +       &avr32_ifield_table[AVR32_IFIELD_K2],
24921 +      },
24922 +    },
24923 +    {
24924 +      AVR32_OPC_SUB5, 4, 0xe0c00000, 0xe1f00000,
24925 +      &avr32_syntax_table[AVR32_SYNTAX_SUB5],
24926 +      BFD_RELOC_AVR32_SUB5, 3, 2,
24927 +      {
24928 +       &avr32_ifield_table[AVR32_IFIELD_RY],
24929 +       &avr32_ifield_table[AVR32_IFIELD_RX],
24930 +       &avr32_ifield_table[AVR32_IFIELD_K16],
24931 +      },
24932 +    },
24933 +    {
24934 +      AVR32_OPC_SUB3_SP, 2, 0x200d0000, 0xf00f0000,
24935 +      &avr32_syntax_table[AVR32_SYNTAX_SUB3_SP],
24936 +      BFD_RELOC_AVR32_10SW, 2, 1,
24937 +      {
24938 +       &avr32_ifield_table[AVR32_IFIELD_RY],
24939 +       &avr32_ifield_table[AVR32_IFIELD_K8C],
24940 +      },
24941 +    },
24942 +    {
24943 +      AVR32_OPC_SUB3, 2, 0x20000000, 0xf0000000,
24944 +      &avr32_syntax_table[AVR32_SYNTAX_SUB3],
24945 +      BFD_RELOC_AVR32_8S, 2, 1,
24946 +      {
24947 +       &avr32_ifield_table[AVR32_IFIELD_RY],
24948 +       &avr32_ifield_table[AVR32_IFIELD_K8C],
24949 +      },
24950 +    },
24951 +    {
24952 +      AVR32_OPC_SUB4, 4, 0xe0200000, 0xe1e00000,
24953 +      &avr32_syntax_table[AVR32_SYNTAX_SUB4],
24954 +      BFD_RELOC_AVR32_21S, 2, 1,
24955 +      {
24956 +       &avr32_ifield_table[AVR32_IFIELD_RY],
24957 +       &avr32_ifield_table[AVR32_IFIELD_K21],
24958 +      },
24959 +    },
24960 +    {
24961 +      AVR32_OPC_SUBEQ, 4, 0xf7b00000, 0xfff0ff00,
24962 +      &avr32_syntax_table[AVR32_SYNTAX_SUBEQ],
24963 +      BFD_RELOC_AVR32_8S_EXT, 2, 1,
24964 +      {
24965 +       &avr32_ifield_table[AVR32_IFIELD_RY],
24966 +       &avr32_ifield_table[AVR32_IFIELD_K8E],
24967 +      },
24968 +    },
24969 +    {
24970 +      AVR32_OPC_SUBNE, 4, 0xf7b00100, 0xfff0ff00,
24971 +      &avr32_syntax_table[AVR32_SYNTAX_SUBNE],
24972 +      BFD_RELOC_AVR32_8S_EXT, 2, 1,
24973 +      {
24974 +       &avr32_ifield_table[AVR32_IFIELD_RY],
24975 +       &avr32_ifield_table[AVR32_IFIELD_K8E],
24976 +      },
24977 +    },
24978 +    {
24979 +      AVR32_OPC_SUBCC, 4, 0xf7b00200, 0xfff0ff00,
24980 +      &avr32_syntax_table[AVR32_SYNTAX_SUBHS],
24981 +      BFD_RELOC_AVR32_8S_EXT, 2, 1,
24982 +      {
24983 +       &avr32_ifield_table[AVR32_IFIELD_RY],
24984 +       &avr32_ifield_table[AVR32_IFIELD_K8E],
24985 +      },
24986 +    },
24987 +    {
24988 +      AVR32_OPC_SUBCS, 4, 0xf7b00300, 0xfff0ff00,
24989 +      &avr32_syntax_table[AVR32_SYNTAX_SUBLO],
24990 +      BFD_RELOC_AVR32_8S_EXT, 2, 1,
24991 +      {
24992 +       &avr32_ifield_table[AVR32_IFIELD_RY],
24993 +       &avr32_ifield_table[AVR32_IFIELD_K8E],
24994 +      },
24995 +    },
24996 +    {
24997 +      AVR32_OPC_SUBGE, 4, 0xf7b00400, 0xfff0ff00,
24998 +      &avr32_syntax_table[AVR32_SYNTAX_SUBGE],
24999 +      BFD_RELOC_AVR32_8S_EXT, 2, 1,
25000 +      {
25001 +       &avr32_ifield_table[AVR32_IFIELD_RY],
25002 +       &avr32_ifield_table[AVR32_IFIELD_K8E],
25003 +      },
25004 +    },
25005 +    {
25006 +      AVR32_OPC_SUBLT, 4, 0xf7b00500, 0xfff0ff00,
25007 +      &avr32_syntax_table[AVR32_SYNTAX_SUBLT],
25008 +      BFD_RELOC_AVR32_8S_EXT, 2, 1,
25009 +      {
25010 +       &avr32_ifield_table[AVR32_IFIELD_RY],
25011 +       &avr32_ifield_table[AVR32_IFIELD_K8E],
25012 +      },
25013 +    },
25014 +    {
25015 +      AVR32_OPC_SUBMI, 4, 0xf7b00600, 0xfff0ff00,
25016 +      &avr32_syntax_table[AVR32_SYNTAX_SUBMI],
25017 +      BFD_RELOC_AVR32_8S_EXT, 2, 1,
25018 +      {
25019 +       &avr32_ifield_table[AVR32_IFIELD_RY],
25020 +       &avr32_ifield_table[AVR32_IFIELD_K8E],
25021 +      },
25022 +    },
25023 +    {
25024 +      AVR32_OPC_SUBPL, 4, 0xf7b00700, 0xfff0ff00,
25025 +      &avr32_syntax_table[AVR32_SYNTAX_SUBPL],
25026 +      BFD_RELOC_AVR32_8S_EXT, 2, 1,
25027 +      {
25028 +       &avr32_ifield_table[AVR32_IFIELD_RY],
25029 +       &avr32_ifield_table[AVR32_IFIELD_K8E],
25030 +      },
25031 +    },
25032 +    {
25033 +      AVR32_OPC_SUBLS, 4, 0xf7b00800, 0xfff0ff00,
25034 +      &avr32_syntax_table[AVR32_SYNTAX_SUBLS],
25035 +      BFD_RELOC_AVR32_8S_EXT, 2, 1,
25036 +      {
25037 +       &avr32_ifield_table[AVR32_IFIELD_RY],
25038 +       &avr32_ifield_table[AVR32_IFIELD_K8E],
25039 +      },
25040 +    },
25041 +    {
25042 +      AVR32_OPC_SUBGT, 4, 0xf7b00900, 0xfff0ff00,
25043 +      &avr32_syntax_table[AVR32_SYNTAX_SUBGT],
25044 +      BFD_RELOC_AVR32_8S_EXT, 2, 1,
25045 +      {
25046 +       &avr32_ifield_table[AVR32_IFIELD_RY],
25047 +       &avr32_ifield_table[AVR32_IFIELD_K8E],
25048 +      },
25049 +    },
25050 +    {
25051 +      AVR32_OPC_SUBLE, 4, 0xf7b00a00, 0xfff0ff00,
25052 +      &avr32_syntax_table[AVR32_SYNTAX_SUBLE],
25053 +      BFD_RELOC_AVR32_8S_EXT, 2, 1,
25054 +      {
25055 +       &avr32_ifield_table[AVR32_IFIELD_RY],
25056 +       &avr32_ifield_table[AVR32_IFIELD_K8E],
25057 +      },
25058 +    },
25059 +    {
25060 +      AVR32_OPC_SUBHI, 4, 0xf7b00b00, 0xfff0ff00,
25061 +      &avr32_syntax_table[AVR32_SYNTAX_SUBHI],
25062 +      BFD_RELOC_AVR32_8S_EXT, 2, 1,
25063 +      {
25064 +       &avr32_ifield_table[AVR32_IFIELD_RY],
25065 +       &avr32_ifield_table[AVR32_IFIELD_K8E],
25066 +      },
25067 +    },
25068 +    {
25069 +      AVR32_OPC_SUBVS, 4, 0xf7b00c00, 0xfff0ff00,
25070 +      &avr32_syntax_table[AVR32_SYNTAX_SUBVS],
25071 +      BFD_RELOC_AVR32_8S_EXT, 2, 1,
25072 +      {
25073 +       &avr32_ifield_table[AVR32_IFIELD_RY],
25074 +       &avr32_ifield_table[AVR32_IFIELD_K8E],
25075 +      },
25076 +    },
25077 +    {
25078 +      AVR32_OPC_SUBVC, 4, 0xf7b00d00, 0xfff0ff00,
25079 +      &avr32_syntax_table[AVR32_SYNTAX_SUBVC],
25080 +      BFD_RELOC_AVR32_8S_EXT, 2, 1,
25081 +      {
25082 +       &avr32_ifield_table[AVR32_IFIELD_RY],
25083 +       &avr32_ifield_table[AVR32_IFIELD_K8E],
25084 +      },
25085 +    },
25086 +    {
25087 +      AVR32_OPC_SUBQS, 4, 0xf7b00e00, 0xfff0ff00,
25088 +      &avr32_syntax_table[AVR32_SYNTAX_SUBQS],
25089 +      BFD_RELOC_AVR32_8S_EXT, 2, 1,
25090 +      {
25091 +       &avr32_ifield_table[AVR32_IFIELD_RY],
25092 +       &avr32_ifield_table[AVR32_IFIELD_K8E],
25093 +      },
25094 +    },
25095 +    {
25096 +      AVR32_OPC_SUBAL, 4, 0xf7b00f00, 0xfff0ff00,
25097 +      &avr32_syntax_table[AVR32_SYNTAX_SUBAL],
25098 +      BFD_RELOC_AVR32_8S_EXT, 2, 1,
25099 +      {
25100 +       &avr32_ifield_table[AVR32_IFIELD_RY],
25101 +       &avr32_ifield_table[AVR32_IFIELD_K8E],
25102 +      },
25103 +    },
25104 +    {
25105 +      AVR32_OPC_SUBFEQ, 4, 0xf5b00000, 0xfff0ff00,
25106 +      &avr32_syntax_table[AVR32_SYNTAX_SUBFEQ],
25107 +      BFD_RELOC_AVR32_8S_EXT, 2, 1,
25108 +      {
25109 +       &avr32_ifield_table[AVR32_IFIELD_RY],
25110 +       &avr32_ifield_table[AVR32_IFIELD_K8E],
25111 +      },
25112 +    },
25113 +    {
25114 +      AVR32_OPC_SUBFNE, 4, 0xf5b00100, 0xfff0ff00,
25115 +      &avr32_syntax_table[AVR32_SYNTAX_SUBFNE],
25116 +      BFD_RELOC_AVR32_8S_EXT, 2, 1,
25117 +      {
25118 +       &avr32_ifield_table[AVR32_IFIELD_RY],
25119 +       &avr32_ifield_table[AVR32_IFIELD_K8E],
25120 +      },
25121 +    },
25122 +    {
25123 +      AVR32_OPC_SUBFCC, 4, 0xf5b00200, 0xfff0ff00,
25124 +      &avr32_syntax_table[AVR32_SYNTAX_SUBFHS],
25125 +      BFD_RELOC_AVR32_8S_EXT, 2, 1,
25126 +      {
25127 +       &avr32_ifield_table[AVR32_IFIELD_RY],
25128 +       &avr32_ifield_table[AVR32_IFIELD_K8E],
25129 +      },
25130 +    },
25131 +    {
25132 +      AVR32_OPC_SUBFCS, 4, 0xf5b00300, 0xfff0ff00,
25133 +      &avr32_syntax_table[AVR32_SYNTAX_SUBFLO],
25134 +      BFD_RELOC_AVR32_8S_EXT, 2, 1,
25135 +      {
25136 +       &avr32_ifield_table[AVR32_IFIELD_RY],
25137 +       &avr32_ifield_table[AVR32_IFIELD_K8E],
25138 +      },
25139 +    },
25140 +    {
25141 +      AVR32_OPC_SUBFGE, 4, 0xf5b00400, 0xfff0ff00,
25142 +      &avr32_syntax_table[AVR32_SYNTAX_SUBFGE],
25143 +      BFD_RELOC_AVR32_8S_EXT, 2, 1,
25144 +      {
25145 +       &avr32_ifield_table[AVR32_IFIELD_RY],
25146 +       &avr32_ifield_table[AVR32_IFIELD_K8E],
25147 +      },
25148 +    },
25149 +    {
25150 +      AVR32_OPC_SUBFLT, 4, 0xf5b00500, 0xfff0ff00,
25151 +      &avr32_syntax_table[AVR32_SYNTAX_SUBFLT],
25152 +      BFD_RELOC_AVR32_8S_EXT, 2, 1,
25153 +      {
25154 +       &avr32_ifield_table[AVR32_IFIELD_RY],
25155 +       &avr32_ifield_table[AVR32_IFIELD_K8E],
25156 +      },
25157 +    },
25158 +    {
25159 +      AVR32_OPC_SUBFMI, 4, 0xf5b00600, 0xfff0ff00,
25160 +      &avr32_syntax_table[AVR32_SYNTAX_SUBFMI],
25161 +      BFD_RELOC_AVR32_8S_EXT, 2, 1,
25162 +      {
25163 +       &avr32_ifield_table[AVR32_IFIELD_RY],
25164 +       &avr32_ifield_table[AVR32_IFIELD_K8E],
25165 +      },
25166 +    },
25167 +    {
25168 +      AVR32_OPC_SUBFPL, 4, 0xf5b00700, 0xfff0ff00,
25169 +      &avr32_syntax_table[AVR32_SYNTAX_SUBFPL],
25170 +      BFD_RELOC_AVR32_8S_EXT, 2, 1,
25171 +      {
25172 +       &avr32_ifield_table[AVR32_IFIELD_RY],
25173 +       &avr32_ifield_table[AVR32_IFIELD_K8E],
25174 +      },
25175 +    },
25176 +    {
25177 +      AVR32_OPC_SUBFLS, 4, 0xf5b00800, 0xfff0ff00,
25178 +      &avr32_syntax_table[AVR32_SYNTAX_SUBFLS],
25179 +      BFD_RELOC_AVR32_8S_EXT, 2, 1,
25180 +      {
25181 +       &avr32_ifield_table[AVR32_IFIELD_RY],
25182 +       &avr32_ifield_table[AVR32_IFIELD_K8E],
25183 +      },
25184 +    },
25185 +    {
25186 +      AVR32_OPC_SUBFGT, 4, 0xf5b00900, 0xfff0ff00,
25187 +      &avr32_syntax_table[AVR32_SYNTAX_SUBFGT],
25188 +      BFD_RELOC_AVR32_8S_EXT, 2, 1,
25189 +      {
25190 +       &avr32_ifield_table[AVR32_IFIELD_RY],
25191 +       &avr32_ifield_table[AVR32_IFIELD_K8E],
25192 +      },
25193 +    },
25194 +    {
25195 +      AVR32_OPC_SUBFLE, 4, 0xf5b00a00, 0xfff0ff00,
25196 +      &avr32_syntax_table[AVR32_SYNTAX_SUBFLE],
25197 +      BFD_RELOC_AVR32_8S_EXT, 2, 1,
25198 +      {
25199 +       &avr32_ifield_table[AVR32_IFIELD_RY],
25200 +       &avr32_ifield_table[AVR32_IFIELD_K8E],
25201 +      },
25202 +    },
25203 +    {
25204 +      AVR32_OPC_SUBFHI, 4, 0xf5b00b00, 0xfff0ff00,
25205 +      &avr32_syntax_table[AVR32_SYNTAX_SUBFHI],
25206 +      BFD_RELOC_AVR32_8S_EXT, 2, 1,
25207 +      {
25208 +       &avr32_ifield_table[AVR32_IFIELD_RY],
25209 +       &avr32_ifield_table[AVR32_IFIELD_K8E],
25210 +      },
25211 +    },
25212 +    {
25213 +      AVR32_OPC_SUBFVS, 4, 0xf5b00c00, 0xfff0ff00,
25214 +      &avr32_syntax_table[AVR32_SYNTAX_SUBFVS],
25215 +      BFD_RELOC_AVR32_8S_EXT, 2, 1,
25216 +      {
25217 +       &avr32_ifield_table[AVR32_IFIELD_RY],
25218 +       &avr32_ifield_table[AVR32_IFIELD_K8E],
25219 +      },
25220 +    },
25221 +    {
25222 +      AVR32_OPC_SUBFVC, 4, 0xf5b00d00, 0xfff0ff00,
25223 +      &avr32_syntax_table[AVR32_SYNTAX_SUBFVC],
25224 +      BFD_RELOC_AVR32_8S_EXT, 2, 1,
25225 +      {
25226 +       &avr32_ifield_table[AVR32_IFIELD_RY],
25227 +       &avr32_ifield_table[AVR32_IFIELD_K8E],
25228 +      },
25229 +    },
25230 +    {
25231 +      AVR32_OPC_SUBFQS, 4, 0xf5b00e00, 0xfff0ff00,
25232 +      &avr32_syntax_table[AVR32_SYNTAX_SUBFQS],
25233 +      BFD_RELOC_AVR32_8S_EXT, 2, 1,
25234 +      {
25235 +       &avr32_ifield_table[AVR32_IFIELD_RY],
25236 +       &avr32_ifield_table[AVR32_IFIELD_K8E],
25237 +      },
25238 +    },
25239 +    {
25240 +      AVR32_OPC_SUBFAL, 4, 0xf5b00f00, 0xfff0ff00,
25241 +      &avr32_syntax_table[AVR32_SYNTAX_SUBFAL],
25242 +      BFD_RELOC_AVR32_8S_EXT, 2, 1,
25243 +      {
25244 +       &avr32_ifield_table[AVR32_IFIELD_RY],
25245 +       &avr32_ifield_table[AVR32_IFIELD_K8E],
25246 +      },
25247 +    },
25248 +    {
25249 +      AVR32_OPC_SUBHH_W, 4, 0xe0000f00, 0xe1f0ffc0,
25250 +      &avr32_syntax_table[AVR32_SYNTAX_SUBHH_W],
25251 +      BFD_RELOC_UNUSED, 5, -1,
25252 +      {
25253 +       &avr32_ifield_table[AVR32_IFIELD_RD_E],
25254 +       &avr32_ifield_table[AVR32_IFIELD_RX],
25255 +       &avr32_ifield_table[AVR32_IFIELD_X],
25256 +       &avr32_ifield_table[AVR32_IFIELD_RY],
25257 +       &avr32_ifield_table[AVR32_IFIELD_Y],
25258 +      },
25259 +    },
25260 +    {
25261 +      AVR32_OPC_SWAP_B, 2, 0x5cb00000, 0xfff00000,
25262 +      &avr32_syntax_table[AVR32_SYNTAX_SWAP_B],
25263 +      BFD_RELOC_UNUSED, 1, -1,
25264 +      {
25265 +       &avr32_ifield_table[AVR32_IFIELD_RY],
25266 +      }
25267 +    },
25268 +    {
25269 +      AVR32_OPC_SWAP_BH, 2, 0x5cc00000, 0xfff00000,
25270 +      &avr32_syntax_table[AVR32_SYNTAX_SWAP_BH],
25271 +      BFD_RELOC_UNUSED, 1, -1,
25272 +      {
25273 +       &avr32_ifield_table[AVR32_IFIELD_RY],
25274 +      }
25275 +    },
25276 +    {
25277 +      AVR32_OPC_SWAP_H, 2, 0x5ca00000, 0xfff00000,
25278 +      &avr32_syntax_table[AVR32_SYNTAX_SWAP_H],
25279 +      BFD_RELOC_UNUSED, 1, -1,
25280 +      {
25281 +       &avr32_ifield_table[AVR32_IFIELD_RY],
25282 +      }
25283 +    },
25284 +    {
25285 +      AVR32_OPC_SYNC, 4, 0xebb00000, 0xffffff00,
25286 +      &avr32_syntax_table[AVR32_SYNTAX_SYNC],
25287 +      BFD_RELOC_AVR32_8S_EXT, 1, 0,
25288 +      {
25289 +       &avr32_ifield_table[AVR32_IFIELD_K8E],
25290 +      }
25291 +    },
25292 +    {
25293 +      AVR32_OPC_TLBR, 2, 0xd6430000, 0xffff0000,
25294 +      &avr32_syntax_table[AVR32_SYNTAX_TLBR],
25295 +      BFD_RELOC_UNUSED, 0, -1, { NULL },
25296 +    },
25297 +    {
25298 +      AVR32_OPC_TLBS, 2, 0xd6530000, 0xffff0000,
25299 +      &avr32_syntax_table[AVR32_SYNTAX_TLBS],
25300 +      BFD_RELOC_UNUSED, 0, -1, { NULL },
25301 +    },
25302 +    {
25303 +      AVR32_OPC_TLBW, 2, 0xd6630000, 0xffff0000,
25304 +      &avr32_syntax_table[AVR32_SYNTAX_TLBW],
25305 +      BFD_RELOC_UNUSED, 0, -1, { NULL },
25306 +    },
25307 +    {
25308 +      AVR32_OPC_TNBZ, 2, 0x5ce00000, 0xfff00000,
25309 +      &avr32_syntax_table[AVR32_SYNTAX_TNBZ],
25310 +      BFD_RELOC_UNUSED, 1, -1,
25311 +      {
25312 +       &avr32_ifield_table[AVR32_IFIELD_RY],
25313 +      }
25314 +    },
25315 +    {
25316 +      AVR32_OPC_TST, 2, 0x00700000, 0xe1f00000,
25317 +      &avr32_syntax_table[AVR32_SYNTAX_TST],
25318 +      BFD_RELOC_UNUSED, 2, -1,
25319 +      {
25320 +       &avr32_ifield_table[AVR32_IFIELD_RY],
25321 +       &avr32_ifield_table[AVR32_IFIELD_RX],
25322 +      },
25323 +    },
25324 +    {
25325 +      AVR32_OPC_XCHG, 4, 0xe0000b40, 0xe1f0fff0,
25326 +      &avr32_syntax_table[AVR32_SYNTAX_XCHG],
25327 +      BFD_RELOC_UNUSED, 3, -1,
25328 +      {
25329 +       &avr32_ifield_table[AVR32_IFIELD_RD_E],
25330 +       &avr32_ifield_table[AVR32_IFIELD_RX],
25331 +       &avr32_ifield_table[AVR32_IFIELD_RY],
25332 +      },
25333 +    },
25334 +    {
25335 +      AVR32_OPC_MEMC, 4, 0xf6100000, 0xfff00000,
25336 +      &avr32_syntax_table[AVR32_SYNTAX_MEMC],
25337 +      BFD_RELOC_AVR32_15S, 2, 0,
25338 +      {
25339 +       &avr32_ifield_table[AVR32_IFIELD_MEM15],
25340 +       &avr32_ifield_table[AVR32_IFIELD_MEMB5],
25341 +      },
25342 +    },
25343 +    {
25344 +      AVR32_OPC_MEMS, 4, 0xf8100000, 0xfff00000,
25345 +      &avr32_syntax_table[AVR32_SYNTAX_MEMS],
25346 +      BFD_RELOC_AVR32_15S, 2, 0,
25347 +      {
25348 +       &avr32_ifield_table[AVR32_IFIELD_MEM15],
25349 +       &avr32_ifield_table[AVR32_IFIELD_MEMB5],
25350 +      },
25351 +    },
25352 +    {
25353 +      AVR32_OPC_MEMT, 4, 0xfa100000, 0xfff00000,
25354 +      &avr32_syntax_table[AVR32_SYNTAX_MEMT],
25355 +      BFD_RELOC_AVR32_15S, 2, 0,
25356 +      {
25357 +       &avr32_ifield_table[AVR32_IFIELD_MEM15],
25358 +       &avr32_ifield_table[AVR32_IFIELD_MEMB5],
25359 +      },
25360 +    },
25361 +    {
25362 +      AVR32_OPC_BFEXTS, 4, 0xe1d0b000, 0xe1f0fc00,
25363 +      &avr32_syntax_table[AVR32_SYNTAX_BFEXTS],
25364 +      BFD_RELOC_UNUSED, 4, -1,
25365 +      {
25366 +       &avr32_ifield_table[AVR32_IFIELD_RX],
25367 +       &avr32_ifield_table[AVR32_IFIELD_RY],
25368 +       &avr32_ifield_table[AVR32_IFIELD_S5],
25369 +       &avr32_ifield_table[AVR32_IFIELD_K5E],
25370 +      },
25371 +    },
25372 +    {
25373 +      AVR32_OPC_BFEXTU, 4, 0xe1d0c000, 0xe1f0fc00,
25374 +      &avr32_syntax_table[AVR32_SYNTAX_BFEXTU],
25375 +      BFD_RELOC_UNUSED, 4, -1,
25376 +      {
25377 +       &avr32_ifield_table[AVR32_IFIELD_RX],
25378 +       &avr32_ifield_table[AVR32_IFIELD_RY],
25379 +       &avr32_ifield_table[AVR32_IFIELD_S5],
25380 +       &avr32_ifield_table[AVR32_IFIELD_K5E],
25381 +      },
25382 +    },
25383 +    {
25384 +      AVR32_OPC_BFINS, 4, 0xe1d0d000, 0xe1f0fc00,
25385 +      &avr32_syntax_table[AVR32_SYNTAX_BFINS],
25386 +      BFD_RELOC_UNUSED, 4, -1,
25387 +      {
25388 +       &avr32_ifield_table[AVR32_IFIELD_RX],
25389 +       &avr32_ifield_table[AVR32_IFIELD_RY],
25390 +       &avr32_ifield_table[AVR32_IFIELD_S5],
25391 +       &avr32_ifield_table[AVR32_IFIELD_K5E],
25392 +      },
25393 +    },
25394 +#define AVR32_OPCODE_RSUBCOND(cond_name, cond_field)                    \
25395 +    {                                                                   \
25396 +      AVR32_OPC_RSUB ## cond_name , 4,                                  \
25397 +      0xfbb00000 | (cond_field << 8), 0xfff0ff00,                       \
25398 +      &avr32_syntax_table[AVR32_SYNTAX_RSUB ## cond_name ],             \
25399 +      BFD_RELOC_AVR32_8S_EXT, 2, 1,                                     \
25400 +      {                                                                 \
25401 +       &avr32_ifield_table[AVR32_IFIELD_RY],                           \
25402 +       &avr32_ifield_table[AVR32_IFIELD_K8E],                          \
25403 +      },                                                                \
25404 +    },
25405 +
25406 +    AVR32_OPCODE_RSUBCOND (EQ, 0)
25407 +    AVR32_OPCODE_RSUBCOND (NE, 1)
25408 +    AVR32_OPCODE_RSUBCOND (CC, 2)
25409 +    AVR32_OPCODE_RSUBCOND (CS, 3)
25410 +    AVR32_OPCODE_RSUBCOND (GE, 4)
25411 +    AVR32_OPCODE_RSUBCOND (LT, 5)
25412 +    AVR32_OPCODE_RSUBCOND (MI, 6)
25413 +    AVR32_OPCODE_RSUBCOND (PL, 7)
25414 +    AVR32_OPCODE_RSUBCOND (LS, 8)
25415 +    AVR32_OPCODE_RSUBCOND (GT, 9)
25416 +    AVR32_OPCODE_RSUBCOND (LE, 10)
25417 +    AVR32_OPCODE_RSUBCOND (HI, 11)
25418 +    AVR32_OPCODE_RSUBCOND (VS, 12)
25419 +    AVR32_OPCODE_RSUBCOND (VC, 13)
25420 +    AVR32_OPCODE_RSUBCOND (QS, 14)
25421 +    AVR32_OPCODE_RSUBCOND (AL, 15)
25422 +
25423 +#define AVR32_OPCODE_OP3_COND(op_name, op_field, cond_name, cond_field) \
25424 +    {                                                                   \
25425 +      AVR32_OPC_ ## op_name ## cond_name , 4,                           \
25426 +      0xe1d0e000 | (cond_field << 8) | (op_field << 4), 0xe1f0fff0,     \
25427 +      &avr32_syntax_table[AVR32_SYNTAX_ ## op_name ## cond_name ],      \
25428 +      BFD_RELOC_UNUSED, 3, -1,                                          \
25429 +      {                                                                 \
25430 +       &avr32_ifield_table[AVR32_IFIELD_RD_E],                         \
25431 +       &avr32_ifield_table[AVR32_IFIELD_RX],                           \
25432 +       &avr32_ifield_table[AVR32_IFIELD_RY],                           \
25433 +      },                                                                \
25434 +    },
25435 +
25436 +    AVR32_OPCODE_OP3_COND (ADD, 0, EQ, 0)
25437 +    AVR32_OPCODE_OP3_COND (ADD, 0, NE, 1)
25438 +    AVR32_OPCODE_OP3_COND (ADD, 0, CC, 2)
25439 +    AVR32_OPCODE_OP3_COND (ADD, 0, CS, 3)
25440 +    AVR32_OPCODE_OP3_COND (ADD, 0, GE, 4)
25441 +    AVR32_OPCODE_OP3_COND (ADD, 0, LT, 5)
25442 +    AVR32_OPCODE_OP3_COND (ADD, 0, MI, 6)
25443 +    AVR32_OPCODE_OP3_COND (ADD, 0, PL, 7)
25444 +    AVR32_OPCODE_OP3_COND (ADD, 0, LS, 8)
25445 +    AVR32_OPCODE_OP3_COND (ADD, 0, GT, 9)
25446 +    AVR32_OPCODE_OP3_COND (ADD, 0, LE, 10)
25447 +    AVR32_OPCODE_OP3_COND (ADD, 0, HI, 11)
25448 +    AVR32_OPCODE_OP3_COND (ADD, 0, VS, 12)
25449 +    AVR32_OPCODE_OP3_COND (ADD, 0, VC, 13)
25450 +    AVR32_OPCODE_OP3_COND (ADD, 0, QS, 14)
25451 +    AVR32_OPCODE_OP3_COND (ADD, 0, AL, 15)
25452 +
25453 +    AVR32_OPCODE_OP3_COND (SUB2, 1, EQ, 0)
25454 +    AVR32_OPCODE_OP3_COND (SUB2, 1, NE, 1)
25455 +    AVR32_OPCODE_OP3_COND (SUB2, 1, CC, 2)
25456 +    AVR32_OPCODE_OP3_COND (SUB2, 1, CS, 3)
25457 +    AVR32_OPCODE_OP3_COND (SUB2, 1, GE, 4)
25458 +    AVR32_OPCODE_OP3_COND (SUB2, 1, LT, 5)
25459 +    AVR32_OPCODE_OP3_COND (SUB2, 1, MI, 6)
25460 +    AVR32_OPCODE_OP3_COND (SUB2, 1, PL, 7)
25461 +    AVR32_OPCODE_OP3_COND (SUB2, 1, LS, 8)
25462 +    AVR32_OPCODE_OP3_COND (SUB2, 1, GT, 9)
25463 +    AVR32_OPCODE_OP3_COND (SUB2, 1, LE, 10)
25464 +    AVR32_OPCODE_OP3_COND (SUB2, 1, HI, 11)
25465 +    AVR32_OPCODE_OP3_COND (SUB2, 1, VS, 12)
25466 +    AVR32_OPCODE_OP3_COND (SUB2, 1, VC, 13)
25467 +    AVR32_OPCODE_OP3_COND (SUB2, 1, QS, 14)
25468 +    AVR32_OPCODE_OP3_COND (SUB2, 1, AL, 15)
25469 +
25470 +    AVR32_OPCODE_OP3_COND (AND, 2, EQ, 0)
25471 +    AVR32_OPCODE_OP3_COND (AND, 2, NE, 1)
25472 +    AVR32_OPCODE_OP3_COND (AND, 2, CC, 2)
25473 +    AVR32_OPCODE_OP3_COND (AND, 2, CS, 3)
25474 +    AVR32_OPCODE_OP3_COND (AND, 2, GE, 4)
25475 +    AVR32_OPCODE_OP3_COND (AND, 2, LT, 5)
25476 +    AVR32_OPCODE_OP3_COND (AND, 2, MI, 6)
25477 +    AVR32_OPCODE_OP3_COND (AND, 2, PL, 7)
25478 +    AVR32_OPCODE_OP3_COND (AND, 2, LS, 8)
25479 +    AVR32_OPCODE_OP3_COND (AND, 2, GT, 9)
25480 +    AVR32_OPCODE_OP3_COND (AND, 2, LE, 10)
25481 +    AVR32_OPCODE_OP3_COND (AND, 2, HI, 11)
25482 +    AVR32_OPCODE_OP3_COND (AND, 2, VS, 12)
25483 +    AVR32_OPCODE_OP3_COND (AND, 2, VC, 13)
25484 +    AVR32_OPCODE_OP3_COND (AND, 2, QS, 14)
25485 +    AVR32_OPCODE_OP3_COND (AND, 2, AL, 15)
25486 +
25487 +    AVR32_OPCODE_OP3_COND (OR, 3, EQ, 0)
25488 +    AVR32_OPCODE_OP3_COND (OR, 3, NE, 1)
25489 +    AVR32_OPCODE_OP3_COND (OR, 3, CC, 2)
25490 +    AVR32_OPCODE_OP3_COND (OR, 3, CS, 3)
25491 +    AVR32_OPCODE_OP3_COND (OR, 3, GE, 4)
25492 +    AVR32_OPCODE_OP3_COND (OR, 3, LT, 5)
25493 +    AVR32_OPCODE_OP3_COND (OR, 3, MI, 6)
25494 +    AVR32_OPCODE_OP3_COND (OR, 3, PL, 7)
25495 +    AVR32_OPCODE_OP3_COND (OR, 3, LS, 8)
25496 +    AVR32_OPCODE_OP3_COND (OR, 3, GT, 9)
25497 +    AVR32_OPCODE_OP3_COND (OR, 3, LE, 10)
25498 +    AVR32_OPCODE_OP3_COND (OR, 3, HI, 11)
25499 +    AVR32_OPCODE_OP3_COND (OR, 3, VS, 12)
25500 +    AVR32_OPCODE_OP3_COND (OR, 3, VC, 13)
25501 +    AVR32_OPCODE_OP3_COND (OR, 3, QS, 14)
25502 +    AVR32_OPCODE_OP3_COND (OR, 3, AL, 15)
25503 +
25504 +    AVR32_OPCODE_OP3_COND (EOR, 4, EQ, 0)
25505 +    AVR32_OPCODE_OP3_COND (EOR, 4, NE, 1)
25506 +    AVR32_OPCODE_OP3_COND (EOR, 4, CC, 2)
25507 +    AVR32_OPCODE_OP3_COND (EOR, 4, CS, 3)
25508 +    AVR32_OPCODE_OP3_COND (EOR, 4, GE, 4)
25509 +    AVR32_OPCODE_OP3_COND (EOR, 4, LT, 5)
25510 +    AVR32_OPCODE_OP3_COND (EOR, 4, MI, 6)
25511 +    AVR32_OPCODE_OP3_COND (EOR, 4, PL, 7)
25512 +    AVR32_OPCODE_OP3_COND (EOR, 4, LS, 8)
25513 +    AVR32_OPCODE_OP3_COND (EOR, 4, GT, 9)
25514 +    AVR32_OPCODE_OP3_COND (EOR, 4, LE, 10)
25515 +    AVR32_OPCODE_OP3_COND (EOR, 4, HI, 11)
25516 +    AVR32_OPCODE_OP3_COND (EOR, 4, VS, 12)
25517 +    AVR32_OPCODE_OP3_COND (EOR, 4, VC, 13)
25518 +    AVR32_OPCODE_OP3_COND (EOR, 4, QS, 14)
25519 +    AVR32_OPCODE_OP3_COND (EOR, 4, AL, 15)
25520 +
25521 +#define AVR32_OPCODE_LD_COND(op_name, op_field, cond_name, cond_field)  \
25522 +    {                                                                   \
25523 +      AVR32_OPC_ ## op_name ## cond_name , 4,                           \
25524 +      0xe1f00000 | (cond_field << 12) | (op_field  << 9), 0xe1f0fe00,   \
25525 +      &avr32_syntax_table[AVR32_SYNTAX_ ## op_name ## cond_name ],      \
25526 +      BFD_RELOC_UNUSED, 3, -1,                                          \
25527 +      {                                                                 \
25528 +       &avr32_ifield_table[AVR32_IFIELD_RY],                           \
25529 +       &avr32_ifield_table[AVR32_IFIELD_RX],                           \
25530 +       &avr32_ifield_table[AVR32_IFIELD_K9E],                          \
25531 +      },                                                                \
25532 +    },
25533 +
25534 +#define AVR32_OPCODE_ST_COND(op_name, op_field, cond_name, cond_field)  \
25535 +    {                                                                   \
25536 +      AVR32_OPC_ ## op_name ## cond_name , 4,                           \
25537 +      0xe1f00000 | (cond_field << 12) | (op_field  << 9), 0xe1f0fe00,   \
25538 +      &avr32_syntax_table[AVR32_SYNTAX_ ## op_name ## cond_name ],      \
25539 +      BFD_RELOC_UNUSED, 3, -1,                                          \
25540 +      {                                                                 \
25541 +       &avr32_ifield_table[AVR32_IFIELD_RX],                           \
25542 +       &avr32_ifield_table[AVR32_IFIELD_K9E],                          \
25543 +       &avr32_ifield_table[AVR32_IFIELD_RY],                           \
25544 +      },                                                                \
25545 +    },
25546 +
25547 +    AVR32_OPCODE_LD_COND (LD_W, 0, EQ, 0)
25548 +    AVR32_OPCODE_LD_COND (LD_W, 0, NE, 1)
25549 +    AVR32_OPCODE_LD_COND (LD_W, 0, CC, 2)
25550 +    AVR32_OPCODE_LD_COND (LD_W, 0, CS, 3)
25551 +    AVR32_OPCODE_LD_COND (LD_W, 0, GE, 4)
25552 +    AVR32_OPCODE_LD_COND (LD_W, 0, LT, 5)
25553 +    AVR32_OPCODE_LD_COND (LD_W, 0, MI, 6)
25554 +    AVR32_OPCODE_LD_COND (LD_W, 0, PL, 7)
25555 +    AVR32_OPCODE_LD_COND (LD_W, 0, LS, 8)
25556 +    AVR32_OPCODE_LD_COND (LD_W, 0, GT, 9)
25557 +    AVR32_OPCODE_LD_COND (LD_W, 0, LE, 10)
25558 +    AVR32_OPCODE_LD_COND (LD_W, 0, HI, 11)
25559 +    AVR32_OPCODE_LD_COND (LD_W, 0, VS, 12)
25560 +    AVR32_OPCODE_LD_COND (LD_W, 0, VC, 13)
25561 +    AVR32_OPCODE_LD_COND (LD_W, 0, QS, 14)
25562 +    AVR32_OPCODE_LD_COND (LD_W, 0, AL, 15)
25563 +
25564 +    AVR32_OPCODE_LD_COND (LD_SH, 1, EQ, 0)
25565 +    AVR32_OPCODE_LD_COND (LD_SH, 1, NE, 1)
25566 +    AVR32_OPCODE_LD_COND (LD_SH, 1, CC, 2)
25567 +    AVR32_OPCODE_LD_COND (LD_SH, 1, CS, 3)
25568 +    AVR32_OPCODE_LD_COND (LD_SH, 1, GE, 4)
25569 +    AVR32_OPCODE_LD_COND (LD_SH, 1, LT, 5)
25570 +    AVR32_OPCODE_LD_COND (LD_SH, 1, MI, 6)
25571 +    AVR32_OPCODE_LD_COND (LD_SH, 1, PL, 7)
25572 +    AVR32_OPCODE_LD_COND (LD_SH, 1, LS, 8)
25573 +    AVR32_OPCODE_LD_COND (LD_SH, 1, GT, 9)
25574 +    AVR32_OPCODE_LD_COND (LD_SH, 1, LE, 10)
25575 +    AVR32_OPCODE_LD_COND (LD_SH, 1, HI, 11)
25576 +    AVR32_OPCODE_LD_COND (LD_SH, 1, VS, 12)
25577 +    AVR32_OPCODE_LD_COND (LD_SH, 1, VC, 13)
25578 +    AVR32_OPCODE_LD_COND (LD_SH, 1, QS, 14)
25579 +    AVR32_OPCODE_LD_COND (LD_SH, 1, AL, 15)
25580 +
25581 +    AVR32_OPCODE_LD_COND (LD_UH, 2, EQ, 0)
25582 +    AVR32_OPCODE_LD_COND (LD_UH, 2, NE, 1)
25583 +    AVR32_OPCODE_LD_COND (LD_UH, 2, CC, 2)
25584 +    AVR32_OPCODE_LD_COND (LD_UH, 2, CS, 3)
25585 +    AVR32_OPCODE_LD_COND (LD_UH, 2, GE, 4)
25586 +    AVR32_OPCODE_LD_COND (LD_UH, 2, LT, 5)
25587 +    AVR32_OPCODE_LD_COND (LD_UH, 2, MI, 6)
25588 +    AVR32_OPCODE_LD_COND (LD_UH, 2, PL, 7)
25589 +    AVR32_OPCODE_LD_COND (LD_SH, 2, LS, 8)
25590 +    AVR32_OPCODE_LD_COND (LD_SH, 2, GT, 9)
25591 +    AVR32_OPCODE_LD_COND (LD_SH, 2, LE, 10)
25592 +    AVR32_OPCODE_LD_COND (LD_SH, 2, HI, 11)
25593 +    AVR32_OPCODE_LD_COND (LD_SH, 2, VS, 12)
25594 +    AVR32_OPCODE_LD_COND (LD_SH, 2, VC, 13)
25595 +    AVR32_OPCODE_LD_COND (LD_SH, 2, QS, 14)
25596 +    AVR32_OPCODE_LD_COND (LD_SH, 2, AL, 15)
25597 +
25598 +    AVR32_OPCODE_LD_COND (LD_SB, 3, EQ, 0)
25599 +    AVR32_OPCODE_LD_COND (LD_SB, 3, NE, 1)
25600 +    AVR32_OPCODE_LD_COND (LD_SB, 3, CC, 2)
25601 +    AVR32_OPCODE_LD_COND (LD_SB, 3, CS, 3)
25602 +    AVR32_OPCODE_LD_COND (LD_SB, 3, GE, 4)
25603 +    AVR32_OPCODE_LD_COND (LD_SB, 3, LT, 5)
25604 +    AVR32_OPCODE_LD_COND (LD_SB, 3, MI, 6)
25605 +    AVR32_OPCODE_LD_COND (LD_SB, 3, PL, 7)
25606 +    AVR32_OPCODE_LD_COND (LD_SB, 3, LS, 8)
25607 +    AVR32_OPCODE_LD_COND (LD_SB, 3, GT, 9)
25608 +    AVR32_OPCODE_LD_COND (LD_SB, 3, LE, 10)
25609 +    AVR32_OPCODE_LD_COND (LD_SB, 3, HI, 11)
25610 +    AVR32_OPCODE_LD_COND (LD_SB, 3, VS, 12)
25611 +    AVR32_OPCODE_LD_COND (LD_SB, 3, VC, 13)
25612 +    AVR32_OPCODE_LD_COND (LD_SB, 3, QS, 14)
25613 +    AVR32_OPCODE_LD_COND (LD_SB, 3, AL, 15)
25614 +
25615 +    AVR32_OPCODE_LD_COND (LD_UB, 4, EQ, 0)
25616 +    AVR32_OPCODE_LD_COND (LD_UB, 4, NE, 1)
25617 +    AVR32_OPCODE_LD_COND (LD_UB, 4, CC, 2)
25618 +    AVR32_OPCODE_LD_COND (LD_UB, 4, CS, 3)
25619 +    AVR32_OPCODE_LD_COND (LD_UB, 4, GE, 4)
25620 +    AVR32_OPCODE_LD_COND (LD_UB, 4, LT, 5)
25621 +    AVR32_OPCODE_LD_COND (LD_UB, 4, MI, 6)
25622 +    AVR32_OPCODE_LD_COND (LD_UB, 4, PL, 7)
25623 +    AVR32_OPCODE_LD_COND (LD_UB, 4, LS, 8)
25624 +    AVR32_OPCODE_LD_COND (LD_UB, 4, GT, 9)
25625 +    AVR32_OPCODE_LD_COND (LD_UB, 4, LE, 10)
25626 +    AVR32_OPCODE_LD_COND (LD_UB, 4, HI, 11)
25627 +    AVR32_OPCODE_LD_COND (LD_UB, 4, VS, 12)
25628 +    AVR32_OPCODE_LD_COND (LD_UB, 4, VC, 13)
25629 +    AVR32_OPCODE_LD_COND (LD_UB, 4, QS, 14)
25630 +    AVR32_OPCODE_LD_COND (LD_UB, 4, AL, 15)
25631 +
25632 +    AVR32_OPCODE_ST_COND (ST_W, 5, EQ, 0)
25633 +    AVR32_OPCODE_ST_COND (ST_W, 5, NE, 1)
25634 +    AVR32_OPCODE_ST_COND (ST_W, 5, CC, 2)
25635 +    AVR32_OPCODE_ST_COND (ST_W, 5, CS, 3)
25636 +    AVR32_OPCODE_ST_COND (ST_W, 5, GE, 4)
25637 +    AVR32_OPCODE_ST_COND (ST_W, 5, LT, 5)
25638 +    AVR32_OPCODE_ST_COND (ST_W, 5, MI, 6)
25639 +    AVR32_OPCODE_ST_COND (ST_W, 5, PL, 7)
25640 +    AVR32_OPCODE_ST_COND (ST_W, 5, LS, 8)
25641 +    AVR32_OPCODE_ST_COND (ST_W, 5, GT, 9)
25642 +    AVR32_OPCODE_ST_COND (ST_W, 5, LE, 10)
25643 +    AVR32_OPCODE_ST_COND (ST_W, 5, HI, 11)
25644 +    AVR32_OPCODE_ST_COND (ST_W, 5, VS, 12)
25645 +    AVR32_OPCODE_ST_COND (ST_W, 5, VC, 13)
25646 +    AVR32_OPCODE_ST_COND (ST_W, 5, QS, 14)
25647 +    AVR32_OPCODE_ST_COND (ST_W, 5, AL, 15)
25648 +
25649 +    AVR32_OPCODE_ST_COND (ST_H, 6, EQ, 0)
25650 +    AVR32_OPCODE_ST_COND (ST_H, 6, NE, 1)
25651 +    AVR32_OPCODE_ST_COND (ST_H, 6, CC, 2)
25652 +    AVR32_OPCODE_ST_COND (ST_H, 6, CS, 3)
25653 +    AVR32_OPCODE_ST_COND (ST_H, 6, GE, 4)
25654 +    AVR32_OPCODE_ST_COND (ST_H, 6, LT, 5)
25655 +    AVR32_OPCODE_ST_COND (ST_H, 6, MI, 6)
25656 +    AVR32_OPCODE_ST_COND (ST_H, 6, PL, 7)
25657 +    AVR32_OPCODE_ST_COND (ST_H, 6, LS, 8)
25658 +    AVR32_OPCODE_ST_COND (ST_H, 6, GT, 9)
25659 +    AVR32_OPCODE_ST_COND (ST_H, 6, LE, 10)
25660 +    AVR32_OPCODE_ST_COND (ST_H, 6, HI, 11)
25661 +    AVR32_OPCODE_ST_COND (ST_H, 6, VS, 12)
25662 +    AVR32_OPCODE_ST_COND (ST_H, 6, VC, 13)
25663 +    AVR32_OPCODE_ST_COND (ST_H, 6, QS, 14)
25664 +    AVR32_OPCODE_ST_COND (ST_H, 6, AL, 15)
25665 +
25666 +    AVR32_OPCODE_ST_COND (ST_B, 7, EQ, 0)
25667 +    AVR32_OPCODE_ST_COND (ST_B, 7, NE, 1)
25668 +    AVR32_OPCODE_ST_COND (ST_B, 7, CC, 2)
25669 +    AVR32_OPCODE_ST_COND (ST_B, 7, CS, 3)
25670 +    AVR32_OPCODE_ST_COND (ST_B, 7, GE, 4)
25671 +    AVR32_OPCODE_ST_COND (ST_B, 7, LT, 5)
25672 +    AVR32_OPCODE_ST_COND (ST_B, 7, MI, 6)
25673 +    AVR32_OPCODE_ST_COND (ST_B, 7, PL, 7)
25674 +    AVR32_OPCODE_ST_COND (ST_B, 7, LS, 8)
25675 +    AVR32_OPCODE_ST_COND (ST_B, 7, GT, 9)
25676 +    AVR32_OPCODE_ST_COND (ST_B, 7, LE, 10)
25677 +    AVR32_OPCODE_ST_COND (ST_B, 7, HI, 11)
25678 +    AVR32_OPCODE_ST_COND (ST_B, 7, VS, 12)
25679 +    AVR32_OPCODE_ST_COND (ST_B, 7, VC, 13)
25680 +    AVR32_OPCODE_ST_COND (ST_B, 7, QS, 14)
25681 +    AVR32_OPCODE_ST_COND (ST_B, 7, AL, 15)
25682 +
25683 +    {
25684 +      AVR32_OPC_MOVH, 4, 0xfc100000, 0xfff00000,
25685 +      &avr32_syntax_table[AVR32_SYNTAX_MOVH],
25686 +      BFD_RELOC_AVR32_16U,  2, 1,
25687 +      {
25688 +       &avr32_ifield_table[AVR32_IFIELD_RY],
25689 +       &avr32_ifield_table[AVR32_IFIELD_K16],
25690 +      },
25691 +    },
25692 +    {
25693 +      AVR32_OPC_SSCALL, 2, 0xd7530000, 0xffff0000,
25694 +      &avr32_syntax_table[AVR32_SYNTAX_SSCALL],
25695 +      BFD_RELOC_UNUSED, 0, -1, { NULL },
25696 +    },
25697 +    {
25698 +      AVR32_OPC_RETSS, 2, 0xd7630000, 0xffff0000,
25699 +      &avr32_syntax_table[AVR32_SYNTAX_RETSS],
25700 +      BFD_RELOC_UNUSED, 0, -1, { NULL },
25701 +    },
25702 +
25703 + };
25704 +
25705 +#define FPALIAS_DXY(name, opcode)                      \
25706 +  {                                                    \
25707 +    AVR32_ALIAS_##name##_S,                            \
25708 +    &avr32_opc_table[AVR32_OPC_COP],                   \
25709 +    {                                                  \
25710 +      { 0, 0 },                                                \
25711 +      { 1, 0 }, { 1, 1 }, { 1, 2 },                    \
25712 +      { 0, opcode },                                   \
25713 +    },                                                 \
25714 +  }, {                                                 \
25715 +    AVR32_ALIAS_##name##_D,                            \
25716 +    &avr32_opc_table[AVR32_OPC_COP],                   \
25717 +    {                                                  \
25718 +      { 0, 0 },                                                \
25719 +      { 1, 0 }, { 1, 1 }, { 1, 2 },                    \
25720 +      { 0, (opcode) | 0x40 },                          \
25721 +    },                                                 \
25722 +  }
25723 +#define FPALIAS_DX(name, opcode)                       \
25724 +  {                                                    \
25725 +    AVR32_ALIAS_##name##_S,                            \
25726 +    &avr32_opc_table[AVR32_OPC_COP],                   \
25727 +    {                                                  \
25728 +      { 0, 0 },                                                \
25729 +      { 1, 0 }, { 1, 1 }, { 0, 0 },                    \
25730 +      { 0, opcode },                                   \
25731 +    },                                                 \
25732 +  }, {                                                 \
25733 +    AVR32_ALIAS_##name##_D,                            \
25734 +    &avr32_opc_table[AVR32_OPC_COP],                   \
25735 +    {                                                  \
25736 +      { 0, 0 },                                                \
25737 +      { 1, 0 }, { 1, 1 }, { 0, 0 },                    \
25738 +      { 0, (opcode) | 0x40 },                          \
25739 +    },                                                 \
25740 +  }
25741 +#define FPALIAS_XY(name, opcode)                       \
25742 +  {                                                    \
25743 +    AVR32_ALIAS_##name##_S,                            \
25744 +    &avr32_opc_table[AVR32_OPC_COP],                   \
25745 +    {                                                  \
25746 +      { 0, 0 },                                                \
25747 +      { 0, 0 }, { 1, 0 }, { 1, 1 },                    \
25748 +      { 0, opcode },                                   \
25749 +    },                                                 \
25750 +  }, {                                                 \
25751 +    AVR32_ALIAS_##name##_D,                            \
25752 +    &avr32_opc_table[AVR32_OPC_COP],                   \
25753 +    {                                                  \
25754 +      { 0, 0 },                                                \
25755 +      { 0, 0 }, { 1, 0 }, { 1, 1 },                    \
25756 +      { 0, (opcode) | 0x40 },                          \
25757 +    },                                                 \
25758 +  }
25759 +
25760 +const struct avr32_alias avr32_alias_table[] =
25761 +  {
25762 +    FPALIAS_DXY(FMAC, 0x00),
25763 +    FPALIAS_DXY(FNMAC, 0x01),
25764 +    FPALIAS_DXY(FMSC, 0x02),
25765 +    FPALIAS_DXY(FNMSC, 0x03),
25766 +    FPALIAS_DXY(FADD, 0x04),
25767 +    FPALIAS_DXY(FSUB, 0x05),
25768 +    FPALIAS_DXY(FMUL, 0x06),
25769 +    FPALIAS_DXY(FNMUL, 0x07),
25770 +    FPALIAS_DX(FNEG, 0x08),
25771 +    FPALIAS_DX(FABS, 0x09),
25772 +    FPALIAS_XY(FCMP, 0x0d),
25773 +    FPALIAS_DX(FMOV1, 0x0a),
25774 +    {
25775 +      AVR32_ALIAS_FMOV2_S,
25776 +      &avr32_opc_table[AVR32_OPC_MVCR_W],
25777 +      { { 0, 0 }, { 1, 0 }, { 1, 1 }, },
25778 +    },
25779 +    {
25780 +      AVR32_ALIAS_FMOV2_D,
25781 +      &avr32_opc_table[AVR32_OPC_MVCR_D],
25782 +      { { 0, 0 }, { 1, 0 }, { 1, 1 }, },
25783 +    },
25784 +    {
25785 +      AVR32_ALIAS_FMOV3_S,
25786 +      &avr32_opc_table[AVR32_OPC_MVRC_W],
25787 +      { { 0, 0 }, { 1, 0 }, { 1, 1 }, },
25788 +    },
25789 +    {
25790 +      AVR32_ALIAS_FMOV3_D,
25791 +      &avr32_opc_table[AVR32_OPC_MVRC_D],
25792 +      { { 0, 0 }, { 1, 0 }, { 1, 1 }, },
25793 +    },
25794 +    {
25795 +      AVR32_ALIAS_FCASTS_D,
25796 +      &avr32_opc_table[AVR32_OPC_COP],
25797 +      {
25798 +       { 0, 0 },
25799 +       { 1, 0 }, { 1, 1 }, { 0, 0 },
25800 +       { 0, 0x0f },
25801 +      },
25802 +    },
25803 +    {
25804 +      AVR32_ALIAS_FCASTD_S,
25805 +      &avr32_opc_table[AVR32_OPC_COP],
25806 +      {
25807 +       { 0, 0 },
25808 +       { 1, 0 }, { 1, 1 }, { 0, 0 },
25809 +       { 0, 0x10 },
25810 +      },
25811 +    },
25812 +    {
25813 +      AVR32_ALIAS_PICOSVMAC0,
25814 +      &avr32_opc_table[AVR32_OPC_COP],
25815 +      {
25816 +       { 0, PICO_CPNO },
25817 +       { 1, 0 }, { 1, 1 }, { 1, 2 },
25818 +       { 0, 0x0c },
25819 +      },
25820 +    },
25821 +    {
25822 +      AVR32_ALIAS_PICOSVMAC1,
25823 +      &avr32_opc_table[AVR32_OPC_COP],
25824 +      {
25825 +       { 0, PICO_CPNO },
25826 +       { 1, 0 }, { 1, 1 }, { 1, 2 },
25827 +       { 0, 0x0d },
25828 +      },
25829 +    },
25830 +    {
25831 +      AVR32_ALIAS_PICOSVMAC2,
25832 +      &avr32_opc_table[AVR32_OPC_COP],
25833 +      {
25834 +       { 0, PICO_CPNO },
25835 +       { 1, 0 }, { 1, 1 }, { 1, 2 },
25836 +       { 0, 0x0e },
25837 +      },
25838 +    },
25839 +    {
25840 +      AVR32_ALIAS_PICOSVMAC3,
25841 +      &avr32_opc_table[AVR32_OPC_COP],
25842 +      {
25843 +       { 0, PICO_CPNO },
25844 +       { 1, 0 }, { 1, 1 }, { 1, 2 },
25845 +       { 0, 0x0f },
25846 +      },
25847 +    },
25848 +    {
25849 +      AVR32_ALIAS_PICOSVMUL0,
25850 +      &avr32_opc_table[AVR32_OPC_COP],
25851 +      {
25852 +       { 0, PICO_CPNO },
25853 +       { 1, 0 }, { 1, 1 }, { 1, 2 },
25854 +       { 0, 0x08 },
25855 +      },
25856 +    },
25857 +    {
25858 +      AVR32_ALIAS_PICOSVMUL1,
25859 +      &avr32_opc_table[AVR32_OPC_COP],
25860 +      {
25861 +       { 0, PICO_CPNO },
25862 +       { 1, 0 }, { 1, 1 }, { 1, 2 },
25863 +       { 0, 0x09 },
25864 +      },
25865 +    },
25866 +    {
25867 +      AVR32_ALIAS_PICOSVMUL2,
25868 +      &avr32_opc_table[AVR32_OPC_COP],
25869 +      {
25870 +       { 0, PICO_CPNO },
25871 +       { 1, 0 }, { 1, 1 }, { 1, 2 },
25872 +       { 0, 0x0a },
25873 +      },
25874 +    },
25875 +    {
25876 +      AVR32_ALIAS_PICOSVMUL3,
25877 +      &avr32_opc_table[AVR32_OPC_COP],
25878 +      {
25879 +       { 0, PICO_CPNO },
25880 +       { 1, 0 }, { 1, 1 }, { 1, 2 },
25881 +       { 0, 0x0b },
25882 +      },
25883 +    },
25884 +    {
25885 +      AVR32_ALIAS_PICOVMAC0,
25886 +      &avr32_opc_table[AVR32_OPC_COP],
25887 +      {
25888 +       { 0, PICO_CPNO },
25889 +       { 1, 0 }, { 1, 1 }, { 1, 2 },
25890 +       { 0, 0x04 },
25891 +      },
25892 +    },
25893 +    {
25894 +      AVR32_ALIAS_PICOVMAC1,
25895 +      &avr32_opc_table[AVR32_OPC_COP],
25896 +      {
25897 +       { 0, PICO_CPNO },
25898 +       { 1, 0 }, { 1, 1 }, { 1, 2 },
25899 +       { 0, 0x05 },
25900 +      },
25901 +    },
25902 +    {
25903 +      AVR32_ALIAS_PICOVMAC2,
25904 +      &avr32_opc_table[AVR32_OPC_COP],
25905 +      {
25906 +       { 0, PICO_CPNO },
25907 +       { 1, 0 }, { 1, 1 }, { 1, 2 },
25908 +       { 0, 0x06 },
25909 +      },
25910 +    },
25911 +    {
25912 +      AVR32_ALIAS_PICOVMAC3,
25913 +      &avr32_opc_table[AVR32_OPC_COP],
25914 +      {
25915 +       { 0, PICO_CPNO },
25916 +       { 1, 0 }, { 1, 1 }, { 1, 2 },
25917 +       { 0, 0x07 },
25918 +      },
25919 +    },
25920 +    {
25921 +      AVR32_ALIAS_PICOVMUL0,
25922 +      &avr32_opc_table[AVR32_OPC_COP],
25923 +      {
25924 +       { 0, PICO_CPNO },
25925 +       { 1, 0 }, { 1, 1 }, { 1, 2 },
25926 +       { 0, 0x00 },
25927 +      },
25928 +    },
25929 +    {
25930 +      AVR32_ALIAS_PICOVMUL1,
25931 +      &avr32_opc_table[AVR32_OPC_COP],
25932 +      {
25933 +       { 0, PICO_CPNO },
25934 +       { 1, 0 }, { 1, 1 }, { 1, 2 },
25935 +       { 0, 0x01 },
25936 +      },
25937 +    },
25938 +    {
25939 +      AVR32_ALIAS_PICOVMUL2,
25940 +      &avr32_opc_table[AVR32_OPC_COP],
25941 +      {
25942 +       { 0, PICO_CPNO },
25943 +       { 1, 0 }, { 1, 1 }, { 1, 2 },
25944 +       { 0, 0x02 },
25945 +      },
25946 +    },
25947 +    {
25948 +      AVR32_ALIAS_PICOVMUL3,
25949 +      &avr32_opc_table[AVR32_OPC_COP],
25950 +      {
25951 +       { 0, PICO_CPNO },
25952 +       { 1, 0 }, { 1, 1 }, { 1, 2 },
25953 +       { 0, 0x03 },
25954 +      },
25955 +    },
25956 +    {
25957 +      AVR32_ALIAS_PICOLD_D1,
25958 +      &avr32_opc_table[AVR32_OPC_LDC_D1],
25959 +      {
25960 +       { 0, PICO_CPNO },
25961 +       { 1, 0 }, { 1, 1 },
25962 +      },
25963 +    },
25964 +    {
25965 +      AVR32_ALIAS_PICOLD_D2,
25966 +      &avr32_opc_table[AVR32_OPC_LDC_D2],
25967 +      {
25968 +       { 0, PICO_CPNO },
25969 +       { 1, 0 }, { 1, 1 },
25970 +      },
25971 +    },
25972 +    {
25973 +      AVR32_ALIAS_PICOLD_D3,
25974 +      &avr32_opc_table[AVR32_OPC_LDC_D3],
25975 +      {
25976 +       { 0, PICO_CPNO },
25977 +       { 1, 0 }, { 1, 1 }, { 1, 2 }, { 1, 3 },
25978 +      },
25979 +    },
25980 +    {
25981 +      AVR32_ALIAS_PICOLD_W1,
25982 +      &avr32_opc_table[AVR32_OPC_LDC_W1],
25983 +      {
25984 +       { 0, PICO_CPNO },
25985 +       { 1, 0 }, { 1, 1 },
25986 +      },
25987 +    },
25988 +    {
25989 +      AVR32_ALIAS_PICOLD_W2,
25990 +      &avr32_opc_table[AVR32_OPC_LDC_W2],
25991 +      {
25992 +       { 0, PICO_CPNO },
25993 +       { 1, 0 }, { 1, 1 },
25994 +      },
25995 +    },
25996 +    {
25997 +      AVR32_ALIAS_PICOLD_W3,
25998 +      &avr32_opc_table[AVR32_OPC_LDC_W3],
25999 +      {
26000 +       { 0, PICO_CPNO },
26001 +       { 1, 0 }, { 1, 1 }, { 1, 2 }, { 1, 3 },
26002 +      },
26003 +    },
26004 +    {
26005 +      AVR32_ALIAS_PICOLDM_D,
26006 +      &avr32_opc_table[AVR32_OPC_LDCM_D],
26007 +      {
26008 +       { 0, PICO_CPNO },
26009 +       { 1, 0 }, { 1, 1 },
26010 +      },
26011 +    },
26012 +    {
26013 +      AVR32_ALIAS_PICOLDM_D_PU,
26014 +      &avr32_opc_table[AVR32_OPC_LDCM_D_PU],
26015 +      {
26016 +       { 0, PICO_CPNO },
26017 +       { 1, 0 }, { 1, 1 },
26018 +      },
26019 +    },
26020 +    {
26021 +      AVR32_ALIAS_PICOLDM_W,
26022 +      &avr32_opc_table[AVR32_OPC_LDCM_W],
26023 +      {
26024 +       { 0, PICO_CPNO },
26025 +       { 1, 0 }, { 1, 1 }, { 1, 2 },
26026 +      },
26027 +    },
26028 +    {
26029 +      AVR32_ALIAS_PICOLDM_W_PU,
26030 +      &avr32_opc_table[AVR32_OPC_LDCM_W_PU],
26031 +      {
26032 +       { 0, PICO_CPNO },
26033 +       { 1, 0 }, { 1, 1 }, { 1, 2 },
26034 +      },
26035 +    },
26036 +    {
26037 +      AVR32_ALIAS_PICOMV_D1,
26038 +      &avr32_opc_table[AVR32_OPC_MVCR_D],
26039 +      {
26040 +       { 0, PICO_CPNO },
26041 +       { 1, 0 }, { 1, 1 },
26042 +      },
26043 +    },
26044 +    {
26045 +      AVR32_ALIAS_PICOMV_D2,
26046 +      &avr32_opc_table[AVR32_OPC_MVRC_D],
26047 +      {
26048 +       { 0, PICO_CPNO },
26049 +       { 1, 0 }, { 1, 1 },
26050 +      },
26051 +    },
26052 +    {
26053 +      AVR32_ALIAS_PICOMV_W1,
26054 +      &avr32_opc_table[AVR32_OPC_MVCR_W],
26055 +      {
26056 +       { 0, PICO_CPNO },
26057 +       { 1, 0 }, { 1, 1 },
26058 +      },
26059 +    },
26060 +    {
26061 +      AVR32_ALIAS_PICOMV_W2,
26062 +      &avr32_opc_table[AVR32_OPC_MVRC_W],
26063 +      {
26064 +       { 0, PICO_CPNO },
26065 +       { 1, 0 }, { 1, 1 },
26066 +      },
26067 +    },
26068 +    {
26069 +      AVR32_ALIAS_PICOST_D1,
26070 +      &avr32_opc_table[AVR32_OPC_STC_D1],
26071 +      {
26072 +       { 0, PICO_CPNO },
26073 +       { 1, 0 }, { 1, 1 }, { 1, 2 },
26074 +      },
26075 +    },
26076 +    {
26077 +      AVR32_ALIAS_PICOST_D2,
26078 +      &avr32_opc_table[AVR32_OPC_STC_D2],
26079 +      {
26080 +       { 0, PICO_CPNO },
26081 +       { 1, 0 }, { 1, 1 },
26082 +      },
26083 +    },
26084 +    {
26085 +      AVR32_ALIAS_PICOST_D3,
26086 +      &avr32_opc_table[AVR32_OPC_STC_D3],
26087 +      {
26088 +       { 0, PICO_CPNO },
26089 +       { 1, 0 }, { 1, 1 }, { 1, 2 }, { 1, 3 },
26090 +      },
26091 +    },
26092 +    {
26093 +      AVR32_ALIAS_PICOST_W1,
26094 +      &avr32_opc_table[AVR32_OPC_STC_W1],
26095 +      {
26096 +       { 0, PICO_CPNO },
26097 +       { 1, 0 }, { 1, 1 }, { 1, 2 },
26098 +      },
26099 +    },
26100 +    {
26101 +      AVR32_ALIAS_PICOST_W2,
26102 +      &avr32_opc_table[AVR32_OPC_STC_W2],
26103 +      {
26104 +       { 0, PICO_CPNO },
26105 +       { 1, 0 }, { 1, 1 },
26106 +      },
26107 +    },
26108 +    {
26109 +      AVR32_ALIAS_PICOST_W3,
26110 +      &avr32_opc_table[AVR32_OPC_STC_W3],
26111 +      {
26112 +       { 0, PICO_CPNO },
26113 +       { 1, 0 }, { 1, 1 }, { 1, 2 }, { 1, 3 },
26114 +      },
26115 +    },
26116 +    {
26117 +      AVR32_ALIAS_PICOSTM_D,
26118 +      &avr32_opc_table[AVR32_OPC_STCM_D],
26119 +      {
26120 +       { 0, PICO_CPNO },
26121 +       { 1, 0 }, { 1, 1 },
26122 +      },
26123 +    },
26124 +    {
26125 +      AVR32_ALIAS_PICOSTM_D_PU,
26126 +      &avr32_opc_table[AVR32_OPC_STCM_D_PU],
26127 +      {
26128 +       { 0, PICO_CPNO },
26129 +       { 1, 0 }, { 1, 1 },
26130 +      },
26131 +    },
26132 +    {
26133 +      AVR32_ALIAS_PICOSTM_W,
26134 +      &avr32_opc_table[AVR32_OPC_STCM_W],
26135 +      {
26136 +       { 0, PICO_CPNO },
26137 +       { 1, 0 }, { 1, 1 }, { 1, 2 },
26138 +      },
26139 +    },
26140 +    {
26141 +      AVR32_ALIAS_PICOSTM_W_PU,
26142 +      &avr32_opc_table[AVR32_OPC_STCM_W_PU],
26143 +      {
26144 +       { 0, PICO_CPNO },
26145 +       { 1, 0 }, { 1, 1 }, { 1, 2 },
26146 +      },
26147 +    },
26148 +  };
26149 +
26150 +
26151 +#define SYNTAX_NORMAL0(id, mne, opc, arch)                     \
26152 +  {                                                    \
26153 +    AVR32_SYNTAX_##id, arch,                   \
26154 +    &avr32_mnemonic_table[AVR32_MNEMONIC_##mne],       \
26155 +    AVR32_PARSER_NORMAL,                                       \
26156 +    { &avr32_opc_table[AVR32_OPC_##opc], },            \
26157 +    NULL, 0, { }                                       \
26158 +  }
26159 +#define SYNTAX_NORMAL1(id, mne, opc, op0, arch)                \
26160 +  {                                                    \
26161 +    AVR32_SYNTAX_##id, arch,                   \
26162 +    &avr32_mnemonic_table[AVR32_MNEMONIC_##mne],       \
26163 +    AVR32_PARSER_NORMAL,                                       \
26164 +    { &avr32_opc_table[AVR32_OPC_##opc], },            \
26165 +    NULL, 1,                                           \
26166 +    {                                                  \
26167 +      AVR32_OPERAND_##op0,                             \
26168 +    }                                                  \
26169 +  }
26170 +#define SYNTAX_NORMALM1(id, mne, opc, op0, arch)               \
26171 +  {                                                    \
26172 +    AVR32_SYNTAX_##id, arch,                   \
26173 +    &avr32_mnemonic_table[AVR32_MNEMONIC_##mne],       \
26174 +    AVR32_PARSER_NORMAL,                                       \
26175 +    { &avr32_opc_table[AVR32_OPC_##opc], },                    \
26176 +    NULL, -1,                                          \
26177 +    {                                                  \
26178 +      AVR32_OPERAND_##op0,                             \
26179 +    }                                                  \
26180 +  }
26181 +#define SYNTAX_NORMAL2(id, mne, opc, op0, op1, arch)           \
26182 +  {                                                    \
26183 +    AVR32_SYNTAX_##id, arch,                   \
26184 +    &avr32_mnemonic_table[AVR32_MNEMONIC_##mne],       \
26185 +    AVR32_PARSER_NORMAL,                                       \
26186 +    { &avr32_opc_table[AVR32_OPC_##opc], },                    \
26187 +    NULL, 2,                                           \
26188 +    {                                                  \
26189 +      AVR32_OPERAND_##op0, AVR32_OPERAND_##op1,                \
26190 +    }                                                  \
26191 +  }
26192 +#define SYNTAX_NORMALM2(id, mne, opc, op0, op1, arch)          \
26193 +  {                                                    \
26194 +    AVR32_SYNTAX_##id, arch,                   \
26195 +    &avr32_mnemonic_table[AVR32_MNEMONIC_##mne],       \
26196 +    AVR32_PARSER_NORMAL,                                       \
26197 +    { &avr32_opc_table[AVR32_OPC_##opc], },                    \
26198 +    NULL, -2,                                          \
26199 +    {                                                  \
26200 +      AVR32_OPERAND_##op0, AVR32_OPERAND_##op1,                \
26201 +    }                                                  \
26202 +  }
26203 +#define SYNTAX_NORMAL3(id, mne, opc, op0, op1, op2, arch)      \
26204 +  {                                                    \
26205 +    AVR32_SYNTAX_##id, arch,                   \
26206 +    &avr32_mnemonic_table[AVR32_MNEMONIC_##mne],       \
26207 +    AVR32_PARSER_NORMAL,                                       \
26208 +    { &avr32_opc_table[AVR32_OPC_##opc], },                    \
26209 +    NULL, 3,                                           \
26210 +    {                                                  \
26211 +      AVR32_OPERAND_##op0, AVR32_OPERAND_##op1,                \
26212 +      AVR32_OPERAND_##op2,                             \
26213 +    }                                                  \
26214 +  }
26215 +#define SYNTAX_NORMALM3(id, mne, opc, op0, op1, op2, arch)     \
26216 +  {                                                    \
26217 +    AVR32_SYNTAX_##id, arch,                   \
26218 +    &avr32_mnemonic_table[AVR32_MNEMONIC_##mne],       \
26219 +    AVR32_PARSER_NORMAL,                                       \
26220 +    { &avr32_opc_table[AVR32_OPC_##opc], },                    \
26221 +    NULL, -3,                                          \
26222 +    {                                                  \
26223 +      AVR32_OPERAND_##op0, AVR32_OPERAND_##op1,                \
26224 +      AVR32_OPERAND_##op2,                             \
26225 +    }                                                  \
26226 +  }
26227 +#define SYNTAX_NORMAL4(id, mne, opc, op0, op1, op2, op3, arch)\
26228 +  {                                                    \
26229 +    AVR32_SYNTAX_##id, arch,                   \
26230 +    &avr32_mnemonic_table[AVR32_MNEMONIC_##mne],       \
26231 +    AVR32_PARSER_NORMAL,                                       \
26232 +    { &avr32_opc_table[AVR32_OPC_##opc], },                    \
26233 +    NULL, 4,                                           \
26234 +    {                                                  \
26235 +      AVR32_OPERAND_##op0, AVR32_OPERAND_##op1,                \
26236 +      AVR32_OPERAND_##op2, AVR32_OPERAND_##op3,                \
26237 +    }                                                  \
26238 +  }
26239 +#define SYNTAX_NORMAL5(id, mne, opc, op0, op1, op2, op3, op4, arch)    \
26240 +  {                                                            \
26241 +    AVR32_SYNTAX_##id, arch,                           \
26242 +    &avr32_mnemonic_table[AVR32_MNEMONIC_##mne],               \
26243 +    AVR32_PARSER_NORMAL,                                               \
26244 +    { &avr32_opc_table[AVR32_OPC_##opc], },                            \
26245 +    NULL, 5,                                                   \
26246 +    {                                                          \
26247 +      AVR32_OPERAND_##op0, AVR32_OPERAND_##op1,                        \
26248 +      AVR32_OPERAND_##op2, AVR32_OPERAND_##op3,                        \
26249 +      AVR32_OPERAND_##op4,                                     \
26250 +    }                                                          \
26251 +  }
26252 +
26253 +#define SYNTAX_NORMAL_C1(id, mne, opc, nxt, op0, arch) \
26254 +  {                                                    \
26255 +    AVR32_SYNTAX_##id, arch,                   \
26256 +    &avr32_mnemonic_table[AVR32_MNEMONIC_##mne],       \
26257 +    AVR32_PARSER_NORMAL,                                       \
26258 +    { &avr32_opc_table[AVR32_OPC_##opc], },                    \
26259 +    &avr32_syntax_table[AVR32_SYNTAX_##nxt], 1,                \
26260 +    {                                                  \
26261 +      AVR32_OPERAND_##op0,                             \
26262 +    }                                                  \
26263 +  }
26264 +#define SYNTAX_NORMAL_CM1(id, mne, opc, nxt, op0, arch)        \
26265 +  {                                                    \
26266 +    AVR32_SYNTAX_##id, arch,                   \
26267 +    &avr32_mnemonic_table[AVR32_MNEMONIC_##mne],       \
26268 +    AVR32_PARSER_NORMAL,                                       \
26269 +    { &avr32_opc_table[AVR32_OPC_##opc], },                    \
26270 +    &avr32_syntax_table[AVR32_SYNTAX_##nxt], -1,       \
26271 +    {                                                  \
26272 +      AVR32_OPERAND_##op0,                             \
26273 +    }                                                  \
26274 +  }
26275 +#define SYNTAX_NORMAL_C2(id, mne, opc, nxt, op0, op1, arch)    \
26276 +  {                                                    \
26277 +    AVR32_SYNTAX_##id, arch,                   \
26278 +    &avr32_mnemonic_table[AVR32_MNEMONIC_##mne],       \
26279 +    AVR32_PARSER_NORMAL,                                       \
26280 +    { &avr32_opc_table[AVR32_OPC_##opc], },                    \
26281 +    &avr32_syntax_table[AVR32_SYNTAX_##nxt], 2,                \
26282 +    {                                                  \
26283 +      AVR32_OPERAND_##op0, AVR32_OPERAND_##op1,                \
26284 +    }                                                  \
26285 +  }
26286 +#define SYNTAX_NORMAL_CM2(id, mne, opc, nxt, op0, op1, arch)   \
26287 +  {                                                    \
26288 +    AVR32_SYNTAX_##id, arch,                   \
26289 +    &avr32_mnemonic_table[AVR32_MNEMONIC_##mne],       \
26290 +    AVR32_PARSER_NORMAL,                                       \
26291 +    { &avr32_opc_table[AVR32_OPC_##opc], },                    \
26292 +    &avr32_syntax_table[AVR32_SYNTAX_##nxt], -2,       \
26293 +    {                                                  \
26294 +      AVR32_OPERAND_##op0, AVR32_OPERAND_##op1,                \
26295 +    }                                                  \
26296 +  }
26297 +#define SYNTAX_NORMAL_C3(id, mne, opc, nxt, op0, op1, op2, arch)       \
26298 +  {                                                            \
26299 +    AVR32_SYNTAX_##id, arch,                           \
26300 +    &avr32_mnemonic_table[AVR32_MNEMONIC_##mne],               \
26301 +    AVR32_PARSER_NORMAL,                                               \
26302 +    { &avr32_opc_table[AVR32_OPC_##opc], },                            \
26303 +    &avr32_syntax_table[AVR32_SYNTAX_##nxt], 3,                        \
26304 +    {                                                          \
26305 +      AVR32_OPERAND_##op0, AVR32_OPERAND_##op1,                        \
26306 +      AVR32_OPERAND_##op2,                                     \
26307 +    }                                                          \
26308 +  }
26309 +#define SYNTAX_NORMAL_CM3(id, mne, opc, nxt, op0, op1, op2, arch)      \
26310 +  {                                                            \
26311 +    AVR32_SYNTAX_##id, arch,                           \
26312 +    &avr32_mnemonic_table[AVR32_MNEMONIC_##mne],               \
26313 +    AVR32_PARSER_NORMAL,                                               \
26314 +    { &avr32_opc_table[AVR32_OPC_##opc], },                            \
26315 +    &avr32_syntax_table[AVR32_SYNTAX_##nxt], -3,               \
26316 +    {                                                          \
26317 +      AVR32_OPERAND_##op0, AVR32_OPERAND_##op1,                        \
26318 +      AVR32_OPERAND_##op2,                                     \
26319 +    }                                                          \
26320 +  }
26321 +
26322 +#define SYNTAX_FP(name, nr_ops)                                        \
26323 +    {                                                          \
26324 +      AVR32_SYNTAX_##name##_S,                                 \
26325 +      AVR32_FP, NULL, AVR32_PARSER_ALIAS,                      \
26326 +      { .alias = &avr32_alias_table[AVR32_ALIAS_##name##_S] }, \
26327 +      NULL, nr_ops,                                            \
26328 +      {                                                                \
26329 +       AVR32_OPERAND_FPREG_S,                                  \
26330 +       AVR32_OPERAND_FPREG_S,                                  \
26331 +       AVR32_OPERAND_FPREG_S,                                  \
26332 +      },                                                       \
26333 +    },                                                         \
26334 +    {                                                          \
26335 +      AVR32_SYNTAX_##name##_D,                                 \
26336 +      AVR32_FP, NULL, AVR32_PARSER_ALIAS,                      \
26337 +      { .alias = &avr32_alias_table[AVR32_ALIAS_##name##_D] }, \
26338 +      NULL, nr_ops,                                            \
26339 +      {                                                                \
26340 +       AVR32_OPERAND_FPREG_D,                                  \
26341 +       AVR32_OPERAND_FPREG_D,                                  \
26342 +       AVR32_OPERAND_FPREG_D,                                  \
26343 +      },                                                       \
26344 +    }
26345 +
26346 +const struct avr32_syntax avr32_syntax_table[] =
26347 +  {
26348 +    SYNTAX_NORMAL1(ABS, ABS, ABS, INTREG, AVR32_V1),
26349 +    SYNTAX_NORMAL1(ACALL, ACALL, ACALL, UNSIGNED_CONST_W, AVR32_V1),
26350 +    SYNTAX_NORMAL1(ACR, ACR, ACR, INTREG,AVR32_V1),
26351 +    SYNTAX_NORMAL3(ADC, ADC, ADC, INTREG, INTREG, INTREG, AVR32_V1),
26352 +    SYNTAX_NORMAL_C2(ADD1, ADD, ADD1, ADD2, INTREG, INTREG, AVR32_V1),
26353 +    SYNTAX_NORMAL3(ADD2, ADD, ADD2, INTREG, INTREG, INTREG_LSL, AVR32_V1),
26354 +    SYNTAX_NORMAL3(ADDABS, ADDABS, ADDABS, INTREG, INTREG, INTREG, AVR32_V1),
26355 +    SYNTAX_NORMAL3(ADDHH_W, ADDHH_W, ADDHH_W, INTREG, INTREG_HSEL, INTREG_HSEL, AVR32_DSP),
26356 +    SYNTAX_NORMAL_C2(AND1, AND, AND1, AND2, INTREG, INTREG, AVR32_V1),
26357 +    SYNTAX_NORMAL_C3(AND2, AND, AND2, AND3, INTREG, INTREG, INTREG_LSL, AVR32_V1),
26358 +    SYNTAX_NORMAL3(AND3, AND, AND3, INTREG, INTREG, INTREG_LSR, AVR32_V1),
26359 +    SYNTAX_NORMAL_C2(ANDH, ANDH, ANDH, ANDH_COH, INTREG, UNSIGNED_CONST, AVR32_V1),
26360 +    SYNTAX_NORMAL3(ANDH_COH, ANDH, ANDH_COH, INTREG, UNSIGNED_CONST, COH, AVR32_V1),
26361 +    SYNTAX_NORMAL_C2(ANDL, ANDL, ANDL, ANDL_COH, INTREG, UNSIGNED_CONST, AVR32_V1),
26362 +    SYNTAX_NORMAL3(ANDL_COH, ANDL, ANDL_COH, INTREG, UNSIGNED_CONST, COH, AVR32_V1),
26363 +    SYNTAX_NORMAL2(ANDN, ANDN, ANDN, INTREG, INTREG, AVR32_V1),
26364 +    SYNTAX_NORMAL_C3(ASR1, ASR, ASR1, ASR3, INTREG, INTREG, INTREG, AVR32_V1),
26365 +    SYNTAX_NORMAL_C3(ASR3, ASR, ASR3, ASR2, INTREG, INTREG, UNSIGNED_NUMBER, AVR32_V1),
26366 +    SYNTAX_NORMAL2(ASR2, ASR, ASR2, INTREG, UNSIGNED_NUMBER, AVR32_V1),
26367 +    SYNTAX_NORMAL4(BFEXTS, BFEXTS, BFEXTS, INTREG, INTREG, UNSIGNED_NUMBER, UNSIGNED_NUMBER, AVR32_V1),
26368 +    SYNTAX_NORMAL4(BFEXTU, BFEXTU, BFEXTU, INTREG, INTREG, UNSIGNED_NUMBER, UNSIGNED_NUMBER, AVR32_V1),
26369 +    SYNTAX_NORMAL4(BFINS, BFINS, BFINS, INTREG, INTREG, UNSIGNED_NUMBER, UNSIGNED_NUMBER, AVR32_V1),
26370 +    SYNTAX_NORMAL2(BLD, BLD, BLD, INTREG, UNSIGNED_NUMBER, AVR32_V1),
26371 +    SYNTAX_NORMAL_C1(BREQ1, BREQ, BREQ1, BREQ2, JMPLABEL, AVR32_V1),
26372 +    SYNTAX_NORMAL_C1(BRNE1, BRNE, BRNE1, BRNE2, JMPLABEL, AVR32_V1),
26373 +    SYNTAX_NORMAL_C1(BRCC1, BRCC, BRCC1, BRCC2, JMPLABEL, AVR32_V1),
26374 +    SYNTAX_NORMAL_C1(BRCS1, BRCS, BRCS1, BRCS2, JMPLABEL, AVR32_V1),
26375 +    SYNTAX_NORMAL_C1(BRGE1, BRGE, BRGE1, BRGE2, JMPLABEL, AVR32_V1),
26376 +    SYNTAX_NORMAL_C1(BRLT1, BRLT, BRLT1, BRLT2, JMPLABEL, AVR32_V1),
26377 +    SYNTAX_NORMAL_C1(BRMI1, BRMI, BRMI1, BRMI2, JMPLABEL, AVR32_V1),
26378 +    SYNTAX_NORMAL_C1(BRPL1, BRPL, BRPL1, BRPL2, JMPLABEL, AVR32_V1),
26379 +    SYNTAX_NORMAL_C1(BRHS1, BRHS, BRCC1, BRHS2, JMPLABEL, AVR32_V1),
26380 +    SYNTAX_NORMAL_C1(BRLO1, BRLO, BRCS1, BRLO2, JMPLABEL, AVR32_V1),
26381 +    SYNTAX_NORMAL1(BREQ2, BREQ, BREQ2, JMPLABEL, AVR32_V1),
26382 +    SYNTAX_NORMAL1(BRNE2, BRNE, BRNE2, JMPLABEL, AVR32_V1),
26383 +    SYNTAX_NORMAL1(BRCC2, BRCC, BRCC2, JMPLABEL, AVR32_V1),
26384 +    SYNTAX_NORMAL1(BRCS2, BRCS, BRCS2, JMPLABEL, AVR32_V1),
26385 +    SYNTAX_NORMAL1(BRGE2, BRGE, BRGE2, JMPLABEL, AVR32_V1),
26386 +    SYNTAX_NORMAL1(BRLT2, BRLT, BRLT2, JMPLABEL, AVR32_V1),
26387 +    SYNTAX_NORMAL1(BRMI2, BRMI, BRMI2, JMPLABEL, AVR32_V1),
26388 +    SYNTAX_NORMAL1(BRPL2, BRPL, BRPL2, JMPLABEL, AVR32_V1),
26389 +    SYNTAX_NORMAL1(BRLS, BRLS, BRLS, JMPLABEL, AVR32_V1),
26390 +    SYNTAX_NORMAL1(BRGT, BRGT, BRGT, JMPLABEL, AVR32_V1),
26391 +    SYNTAX_NORMAL1(BRLE, BRLE, BRLE, JMPLABEL, AVR32_V1),
26392 +    SYNTAX_NORMAL1(BRHI, BRHI, BRHI, JMPLABEL, AVR32_V1),
26393 +    SYNTAX_NORMAL1(BRVS, BRVS, BRVS, JMPLABEL, AVR32_V1),
26394 +    SYNTAX_NORMAL1(BRVC, BRVC, BRVC, JMPLABEL, AVR32_V1),
26395 +    SYNTAX_NORMAL1(BRQS, BRQS, BRQS, JMPLABEL, AVR32_V1),
26396 +    SYNTAX_NORMAL1(BRAL, BRAL, BRAL, JMPLABEL, AVR32_V1),
26397 +    SYNTAX_NORMAL1(BRHS2, BRHS, BRCC2, JMPLABEL, AVR32_V1),
26398 +    SYNTAX_NORMAL1(BRLO2, BRLO, BRCS2, JMPLABEL, AVR32_V1),
26399 +    SYNTAX_NORMAL0(BREAKPOINT, BREAKPOINT, BREAKPOINT, AVR32_V1),
26400 +    SYNTAX_NORMAL1(BREV, BREV, BREV, INTREG, AVR32_V1),
26401 +    SYNTAX_NORMAL2(BST, BST, BST, INTREG, UNSIGNED_NUMBER, AVR32_V1),
26402 +    SYNTAX_NORMAL2(CACHE, CACHE, CACHE, INTREG_SDISP, UNSIGNED_NUMBER, AVR32_V1),
26403 +    SYNTAX_NORMAL1(CASTS_B, CASTS_B, CASTS_B, INTREG, AVR32_V1),
26404 +    SYNTAX_NORMAL1(CASTS_H, CASTS_H, CASTS_H, INTREG, AVR32_V1),
26405 +    SYNTAX_NORMAL1(CASTU_B, CASTU_B, CASTU_B, INTREG, AVR32_V1),
26406 +    SYNTAX_NORMAL1(CASTU_H, CASTU_H, CASTU_H, INTREG, AVR32_V1),
26407 +    SYNTAX_NORMAL2(CBR, CBR, CBR, INTREG, UNSIGNED_NUMBER, AVR32_V1),
26408 +    SYNTAX_NORMAL2(CLZ, CLZ, CLZ, INTREG, INTREG, AVR32_V1),
26409 +    SYNTAX_NORMAL1(COM, COM, COM, INTREG, AVR32_V1),
26410 +    SYNTAX_NORMAL5(COP, COP, COP, CPNO, CPREG, CPREG, CPREG, UNSIGNED_NUMBER, AVR32_V1),
26411 +    SYNTAX_NORMAL2(CP_B, CP_B, CP_B, INTREG, INTREG, AVR32_V1),
26412 +    SYNTAX_NORMAL2(CP_H, CP_H, CP_H, INTREG, INTREG, AVR32_V1),
26413 +    SYNTAX_NORMAL_C2(CP_W1, CP_W, CP_W1, CP_W2, INTREG, INTREG, AVR32_V1),
26414 +    SYNTAX_NORMAL_C2(CP_W2, CP_W, CP_W2, CP_W3, INTREG, SIGNED_CONST, AVR32_V1),
26415 +    SYNTAX_NORMAL2(CP_W3, CP_W, CP_W3, INTREG, SIGNED_CONST, AVR32_V1),
26416 +    SYNTAX_NORMAL_C2(CPC1, CPC, CPC1, CPC2, INTREG, INTREG, AVR32_V1),
26417 +    SYNTAX_NORMAL1(CPC2, CPC, CPC2, INTREG, AVR32_V1),
26418 +    SYNTAX_NORMAL1(CSRF, CSRF, CSRF, UNSIGNED_NUMBER, AVR32_V1),
26419 +    SYNTAX_NORMAL1(CSRFCZ, CSRFCZ, CSRFCZ, UNSIGNED_NUMBER, AVR32_V1),
26420 +    SYNTAX_NORMAL3(DIVS, DIVS, DIVS, INTREG, INTREG, INTREG, AVR32_V1),
26421 +    SYNTAX_NORMAL3(DIVU, DIVU, DIVU, INTREG, INTREG, INTREG, AVR32_V1),
26422 +    SYNTAX_NORMAL_C2(EOR1, EOR, EOR1, EOR2, INTREG, INTREG, AVR32_V1),
26423 +    SYNTAX_NORMAL_C3(EOR2, EOR, EOR2, EOR3, INTREG, INTREG, INTREG_LSL, AVR32_V1),
26424 +    SYNTAX_NORMAL3(EOR3, EOR, EOR3, INTREG, INTREG, INTREG_LSR, AVR32_V1),
26425 +    SYNTAX_NORMAL2(EORL, EORL, EORL, INTREG, UNSIGNED_CONST, AVR32_V1),
26426 +    SYNTAX_NORMAL2(EORH, EORH, EORH, INTREG, UNSIGNED_CONST, AVR32_V1),
26427 +    SYNTAX_NORMAL0(FRS, FRS, FRS, AVR32_V1),
26428 +    SYNTAX_NORMAL0(SSCALL, SSCALL, SSCALL, AVR32_V3),
26429 +    SYNTAX_NORMAL0(RETSS, RETSS, RETSS, AVR32_V3),
26430 +    SYNTAX_NORMAL1(ICALL, ICALL, ICALL, INTREG, AVR32_V1),
26431 +    SYNTAX_NORMAL1(INCJOSP, INCJOSP, INCJOSP, JOSPINC, AVR32_V1),
26432 +    SYNTAX_NORMAL_C2(LD_D1, LD_D, LD_D1, LD_D2, DWREG, INTREG_POSTINC, AVR32_V1),
26433 +    SYNTAX_NORMAL_C2(LD_D2, LD_D, LD_D2, LD_D3, DWREG, INTREG_PREDEC, AVR32_V1),
26434 +    SYNTAX_NORMAL_C2(LD_D3, LD_D, LD_D3, LD_D5, DWREG, INTREG, AVR32_V1),
26435 +    SYNTAX_NORMAL_C2(LD_D5, LD_D, LD_D5, LD_D4, DWREG, INTREG_INDEX, AVR32_V1),
26436 +    SYNTAX_NORMAL2(LD_D4, LD_D, LD_D4, DWREG, INTREG_SDISP, AVR32_V1),
26437 +    SYNTAX_NORMAL_C2(LD_SB2, LD_SB, LD_SB2, LD_SB1, INTREG, INTREG_INDEX, AVR32_V1),
26438 +    SYNTAX_NORMAL2(LD_SB1, LD_SB, LD_SB1, INTREG, INTREG_SDISP, AVR32_V1),
26439 +    SYNTAX_NORMAL_C2(LD_UB1, LD_UB, LD_UB1, LD_UB2, INTREG, INTREG_POSTINC, AVR32_V1),
26440 +    SYNTAX_NORMAL_C2(LD_UB2, LD_UB, LD_UB2, LD_UB5, INTREG, INTREG_PREDEC, AVR32_V1),
26441 +    SYNTAX_NORMAL_C2(LD_UB5, LD_UB, LD_UB5, LD_UB3, INTREG, INTREG_INDEX, AVR32_V1),
26442 +    SYNTAX_NORMAL_C2(LD_UB3, LD_UB, LD_UB3, LD_UB4, INTREG, INTREG_UDISP, AVR32_V1),
26443 +    SYNTAX_NORMAL2(LD_UB4, LD_UB, LD_UB4, INTREG, INTREG_SDISP, AVR32_V1),
26444 +    SYNTAX_NORMAL_C2(LD_SH1, LD_SH, LD_SH1, LD_SH2, INTREG, INTREG_POSTINC, AVR32_V1),
26445 +    SYNTAX_NORMAL_C2(LD_SH2, LD_SH, LD_SH2, LD_SH5, INTREG, INTREG_PREDEC, AVR32_V1),
26446 +    SYNTAX_NORMAL_C2(LD_SH5, LD_SH, LD_SH5, LD_SH3, INTREG, INTREG_INDEX, AVR32_V1),
26447 +    SYNTAX_NORMAL_C2(LD_SH3, LD_SH, LD_SH3, LD_SH4, INTREG, INTREG_UDISP_H, AVR32_V1),
26448 +    SYNTAX_NORMAL2(LD_SH4, LD_SH, LD_SH4, INTREG, INTREG_SDISP, AVR32_V1),
26449 +    SYNTAX_NORMAL_C2(LD_UH1, LD_UH, LD_UH1, LD_UH2, INTREG, INTREG_POSTINC, AVR32_V1),
26450 +    SYNTAX_NORMAL_C2(LD_UH2, LD_UH, LD_UH2, LD_UH5, INTREG, INTREG_PREDEC, AVR32_V1),
26451 +    SYNTAX_NORMAL_C2(LD_UH5, LD_UH, LD_UH5, LD_UH3, INTREG, INTREG_INDEX, AVR32_V1),
26452 +    SYNTAX_NORMAL_C2(LD_UH3, LD_UH, LD_UH3, LD_UH4, INTREG, INTREG_UDISP_H, AVR32_V1),
26453 +    SYNTAX_NORMAL2(LD_UH4, LD_UH, LD_UH4, INTREG, INTREG_SDISP, AVR32_V1),
26454 +    SYNTAX_NORMAL_C2(LD_W1, LD_W, LD_W1, LD_W2, INTREG, INTREG_POSTINC, AVR32_V1),
26455 +    SYNTAX_NORMAL_C2(LD_W2, LD_W, LD_W2, LD_W5, INTREG, INTREG_PREDEC, AVR32_V1),
26456 +    SYNTAX_NORMAL_C2(LD_W5, LD_W, LD_W5, LD_W6, INTREG, INTREG_INDEX, AVR32_V1),
26457 +    SYNTAX_NORMAL_C2(LD_W6, LD_W, LD_W6, LD_W3, INTREG, INTREG_XINDEX, AVR32_V1),
26458 +    SYNTAX_NORMAL_C2(LD_W3, LD_W, LD_W3, LD_W4, INTREG, INTREG_UDISP_W, AVR32_V1),
26459 +    SYNTAX_NORMAL2(LD_W4, LD_W, LD_W4, INTREG, INTREG_SDISP, AVR32_V1),
26460 +    SYNTAX_NORMAL3(LDC_D1, LDC_D, LDC_D1, CPNO, CPREG_D, INTREG_UDISP_W, AVR32_V1),
26461 +    SYNTAX_NORMAL_C3(LDC_D2, LDC_D, LDC_D2, LDC_D1, CPNO, CPREG_D, INTREG_PREDEC, AVR32_V1),
26462 +    SYNTAX_NORMAL_C3(LDC_D3, LDC_D, LDC_D3, LDC_D2, CPNO, CPREG_D, INTREG_INDEX, AVR32_V1),
26463 +    SYNTAX_NORMAL3(LDC_W1, LDC_W, LDC_W1, CPNO, CPREG, INTREG_UDISP_W, AVR32_V1),
26464 +    SYNTAX_NORMAL_C3(LDC_W2, LDC_W, LDC_W2, LDC_W1, CPNO, CPREG, INTREG_PREDEC, AVR32_V1),
26465 +    SYNTAX_NORMAL_C3(LDC_W3, LDC_W, LDC_W3, LDC_W2, CPNO, CPREG, INTREG_INDEX, AVR32_V1),
26466 +    SYNTAX_NORMAL2(LDC0_D, LDC0_D, LDC0_D, CPREG_D, INTREG_UDISP_W, AVR32_V1),
26467 +    SYNTAX_NORMAL2(LDC0_W, LDC0_W, LDC0_W, CPREG, INTREG_UDISP_W, AVR32_V1),
26468 +    SYNTAX_NORMAL_CM3(LDCM_D, LDCM_D, LDCM_D, LDCM_D_PU, CPNO, INTREG, REGLIST_CPD8, AVR32_V1),
26469 +    SYNTAX_NORMALM3(LDCM_D_PU, LDCM_D, LDCM_D_PU, CPNO, INTREG_POSTINC, REGLIST_CPD8, AVR32_V1),
26470 +    SYNTAX_NORMAL_CM3(LDCM_W, LDCM_W, LDCM_W, LDCM_W_PU, CPNO, INTREG, REGLIST_CP8, AVR32_V1),
26471 +    SYNTAX_NORMALM3(LDCM_W_PU, LDCM_W, LDCM_W_PU, CPNO, INTREG_POSTINC, REGLIST_CP8, AVR32_V1),
26472 +    SYNTAX_NORMAL2(LDDPC, LDDPC, LDDPC, INTREG, PC_UDISP_W, AVR32_V1),
26473 +    SYNTAX_NORMAL2(LDDPC_EXT, LDDPC, LDDPC_EXT, INTREG, SIGNED_CONST, AVR32_V1),
26474 +    SYNTAX_NORMAL2(LDDSP, LDDSP, LDDSP, INTREG, SP_UDISP_W, AVR32_V1),
26475 +    SYNTAX_NORMAL2(LDINS_B, LDINS_B, LDINS_B, INTREG_BSEL, INTREG_SDISP, AVR32_V1),
26476 +    SYNTAX_NORMAL2(LDINS_H, LDINS_H, LDINS_H, INTREG_HSEL, INTREG_SDISP_H, AVR32_V1),
26477 +    SYNTAX_NORMALM1(LDM, LDM, LDM, REGLIST_LDM, AVR32_V1),
26478 +    SYNTAX_NORMAL_CM2(LDMTS, LDMTS, LDMTS, LDMTS_PU, INTREG, REGLIST16, AVR32_V1),
26479 +    SYNTAX_NORMALM2(LDMTS_PU, LDMTS, LDMTS_PU, INTREG_POSTINC, REGLIST16, AVR32_V1),
26480 +    SYNTAX_NORMAL2(LDSWP_SH, LDSWP_SH, LDSWP_SH, INTREG, INTREG_SDISP_H, AVR32_V1),
26481 +    SYNTAX_NORMAL2(LDSWP_UH, LDSWP_UH, LDSWP_UH, INTREG, INTREG_SDISP_H, AVR32_V1),
26482 +    SYNTAX_NORMAL2(LDSWP_W, LDSWP_W, LDSWP_W, INTREG, INTREG_SDISP_W, AVR32_V1),
26483 +    SYNTAX_NORMAL_C3(LSL1, LSL, LSL1, LSL3, INTREG, INTREG, INTREG, AVR32_V1),
26484 +    SYNTAX_NORMAL_C3(LSL3, LSL, LSL3, LSL2, INTREG, INTREG, UNSIGNED_NUMBER, AVR32_V1),
26485 +    SYNTAX_NORMAL2(LSL2, LSL, LSL2, INTREG, UNSIGNED_NUMBER, AVR32_V1),
26486 +    SYNTAX_NORMAL_C3(LSR1, LSR, LSR1, LSR3, INTREG, INTREG, INTREG, AVR32_V1),
26487 +    SYNTAX_NORMAL_C3(LSR3, LSR, LSR3, LSR2, INTREG, INTREG, UNSIGNED_NUMBER, AVR32_V1),
26488 +    SYNTAX_NORMAL2(LSR2, LSR, LSR2, INTREG, UNSIGNED_NUMBER, AVR32_V1),
26489 +    SYNTAX_NORMAL3(MAC, MAC, MAC, INTREG, INTREG, INTREG, AVR32_V1),
26490 +    SYNTAX_NORMAL3(MACHH_D, MACHH_D, MACHH_D, INTREG, INTREG_HSEL, INTREG_HSEL, AVR32_DSP),
26491 +    SYNTAX_NORMAL3(MACHH_W, MACHH_W, MACHH_W, INTREG, INTREG_HSEL, INTREG_HSEL, AVR32_DSP),
26492 +    SYNTAX_NORMAL3(MACS_D, MACS_D, MACS_D, INTREG, INTREG, INTREG, AVR32_V1),
26493 +    SYNTAX_NORMAL3(MACSATHH_W, MACSATHH_W, MACSATHH_W, INTREG, INTREG_HSEL, INTREG_HSEL, AVR32_DSP),
26494 +    SYNTAX_NORMAL3(MACUD, MACU_D, MACUD, INTREG, INTREG, INTREG, AVR32_V1),
26495 +    SYNTAX_NORMAL3(MACWH_D, MACWH_D, MACWH_D, INTREG, INTREG, INTREG_HSEL, AVR32_DSP),
26496 +    SYNTAX_NORMAL3(MAX, MAX, MAX, INTREG, INTREG, INTREG, AVR32_V1),
26497 +    SYNTAX_NORMAL1(MCALL, MCALL, MCALL, MCALL, AVR32_V1),
26498 +    SYNTAX_NORMAL2(MFDR, MFDR, MFDR, INTREG, UNSIGNED_CONST_W, AVR32_V1),
26499 +    SYNTAX_NORMAL2(MFSR, MFSR, MFSR, INTREG, UNSIGNED_CONST_W, AVR32_V1),
26500 +    SYNTAX_NORMAL3(MIN, MIN, MIN, INTREG, INTREG, INTREG, AVR32_V1),
26501 +    SYNTAX_NORMAL_C2(MOV3, MOV, MOV3, MOV1, INTREG, INTREG, AVR32_V1),
26502 +    SYNTAX_NORMAL_C2(MOV1, MOV, MOV1, MOV2, INTREG, SIGNED_CONST, AVR32_V1),
26503 +    SYNTAX_NORMAL2(MOV2, MOV, MOV2,INTREG, SIGNED_CONST, AVR32_V1),
26504 +    SYNTAX_NORMAL_C2(MOVEQ1, MOVEQ, MOVEQ1, MOVEQ2, INTREG, INTREG, AVR32_V1),
26505 +    SYNTAX_NORMAL_C2(MOVNE1, MOVNE, MOVNE1, MOVNE2, INTREG, INTREG, AVR32_V1),
26506 +    SYNTAX_NORMAL_C2(MOVCC1, MOVCC, MOVCC1, MOVCC2, INTREG, INTREG, AVR32_V1),
26507 +    SYNTAX_NORMAL_C2(MOVCS1, MOVCS, MOVCS1, MOVCS2, INTREG, INTREG, AVR32_V1),
26508 +    SYNTAX_NORMAL_C2(MOVGE1, MOVGE, MOVGE1, MOVGE2, INTREG, INTREG, AVR32_V1),
26509 +    SYNTAX_NORMAL_C2(MOVLT1, MOVLT, MOVLT1, MOVLT2, INTREG, INTREG, AVR32_V1),
26510 +    SYNTAX_NORMAL_C2(MOVMI1, MOVMI, MOVMI1, MOVMI2, INTREG, INTREG, AVR32_V1),
26511 +    SYNTAX_NORMAL_C2(MOVPL1, MOVPL, MOVPL1, MOVPL2, INTREG, INTREG, AVR32_V1),
26512 +    SYNTAX_NORMAL_C2(MOVLS1, MOVLS, MOVLS1, MOVLS2, INTREG, INTREG, AVR32_V1),
26513 +    SYNTAX_NORMAL_C2(MOVGT1, MOVGT, MOVGT1, MOVGT2, INTREG, INTREG, AVR32_V1),
26514 +    SYNTAX_NORMAL_C2(MOVLE1, MOVLE, MOVLE1, MOVLE2, INTREG, INTREG, AVR32_V1),
26515 +    SYNTAX_NORMAL_C2(MOVHI1, MOVHI, MOVHI1, MOVHI2, INTREG, INTREG, AVR32_V1),
26516 +    SYNTAX_NORMAL_C2(MOVVS1, MOVVS, MOVVS1, MOVVS2, INTREG, INTREG, AVR32_V1),
26517 +    SYNTAX_NORMAL_C2(MOVVC1, MOVVC, MOVVC1, MOVVC2, INTREG, INTREG, AVR32_V1),
26518 +    SYNTAX_NORMAL_C2(MOVQS1, MOVQS, MOVQS1, MOVQS2, INTREG, INTREG, AVR32_V1),
26519 +    SYNTAX_NORMAL_C2(MOVAL1, MOVAL, MOVAL1, MOVAL2, INTREG, INTREG, AVR32_V1),
26520 +    SYNTAX_NORMAL_C2(MOVHS1, MOVHS, MOVCC1, MOVHS2, INTREG, INTREG, AVR32_V1),
26521 +    SYNTAX_NORMAL_C2(MOVLO1, MOVLO, MOVCS1, MOVLO2, INTREG, INTREG, AVR32_V1),
26522 +    SYNTAX_NORMAL2(MOVEQ2, MOVEQ, MOVEQ2, INTREG, SIGNED_CONST, AVR32_V1),
26523 +    SYNTAX_NORMAL2(MOVNE2, MOVNE, MOVNE2, INTREG, SIGNED_CONST, AVR32_V1),
26524 +    SYNTAX_NORMAL2(MOVCC2, MOVCC, MOVCC2, INTREG, SIGNED_CONST, AVR32_V1),
26525 +    SYNTAX_NORMAL2(MOVCS2, MOVCS, MOVCS2, INTREG, SIGNED_CONST, AVR32_V1),
26526 +    SYNTAX_NORMAL2(MOVGE2, MOVGE, MOVGE2, INTREG, SIGNED_CONST, AVR32_V1),
26527 +    SYNTAX_NORMAL2(MOVLT2, MOVLT, MOVLT2, INTREG, SIGNED_CONST, AVR32_V1),
26528 +    SYNTAX_NORMAL2(MOVMI2, MOVMI, MOVMI2, INTREG, SIGNED_CONST, AVR32_V1),
26529 +    SYNTAX_NORMAL2(MOVPL2, MOVPL, MOVPL2, INTREG, SIGNED_CONST, AVR32_V1),
26530 +    SYNTAX_NORMAL2(MOVLS2, MOVLS, MOVLS2, INTREG, SIGNED_CONST, AVR32_V1),
26531 +    SYNTAX_NORMAL2(MOVGT2, MOVGT, MOVGT2, INTREG, SIGNED_CONST, AVR32_V1),
26532 +    SYNTAX_NORMAL2(MOVLE2, MOVLE, MOVLE2, INTREG, SIGNED_CONST, AVR32_V1),
26533 +    SYNTAX_NORMAL2(MOVHI2, MOVHI, MOVHI2, INTREG, SIGNED_CONST, AVR32_V1),
26534 +    SYNTAX_NORMAL2(MOVVS2, MOVVS, MOVVS2, INTREG, SIGNED_CONST, AVR32_V1),
26535 +    SYNTAX_NORMAL2(MOVVC2, MOVVC, MOVVC2, INTREG, SIGNED_CONST, AVR32_V1),
26536 +    SYNTAX_NORMAL2(MOVQS2, MOVQS, MOVQS2, INTREG, SIGNED_CONST, AVR32_V1),
26537 +    SYNTAX_NORMAL2(MOVAL2, MOVAL, MOVAL2, INTREG, SIGNED_CONST, AVR32_V1),
26538 +    SYNTAX_NORMAL2(MOVHS2, MOVHS, MOVCC2, INTREG, SIGNED_CONST, AVR32_V1),
26539 +    SYNTAX_NORMAL2(MOVLO2, MOVLO, MOVCS2, INTREG, SIGNED_CONST, AVR32_V1),
26540 +    SYNTAX_NORMAL2(MTDR, MTDR, MTDR, UNSIGNED_CONST_W, INTREG, AVR32_V1),
26541 +    SYNTAX_NORMAL2(MTSR, MTSR, MTSR, UNSIGNED_CONST_W, INTREG, AVR32_V1),
26542 +    SYNTAX_NORMAL_C2(MUL1, MUL, MUL1, MUL2, INTREG, INTREG, AVR32_V1),
26543 +    SYNTAX_NORMAL_C3(MUL2, MUL, MUL2, MUL3, INTREG, INTREG, INTREG, AVR32_V1),
26544 +    SYNTAX_NORMAL3(MUL3, MUL, MUL3, INTREG, INTREG, SIGNED_CONST, AVR32_V1),
26545 +    SYNTAX_NORMAL3(MULHH_W, MULHH_W, MULHH_W, INTREG, INTREG_HSEL, INTREG_HSEL, AVR32_DSP),
26546 +    SYNTAX_NORMAL3(MULNHH_W, MULNHH_W, MULNHH_W, INTREG, INTREG_HSEL, INTREG_HSEL, AVR32_DSP),
26547 +    SYNTAX_NORMAL3(MULNWH_D, MULNWH_D, MULNWH_D, INTREG, INTREG, INTREG_HSEL, AVR32_DSP),
26548 +    SYNTAX_NORMAL3(MULSD, MULS_D, MULSD, INTREG, INTREG, INTREG, AVR32_V1),
26549 +    SYNTAX_NORMAL3(MULSATHH_H, MULSATHH_H, MULSATHH_H, INTREG, INTREG_HSEL, INTREG_HSEL, AVR32_DSP),
26550 +    SYNTAX_NORMAL3(MULSATHH_W, MULSATHH_W, MULSATHH_W, INTREG, INTREG_HSEL, INTREG_HSEL, AVR32_DSP),
26551 +    SYNTAX_NORMAL3(MULSATRNDHH_H, MULSATRNDHH_H, MULSATRNDHH_H, INTREG, INTREG_HSEL, INTREG_HSEL, AVR32_DSP),
26552 +    SYNTAX_NORMAL3(MULSATRNDWH_W, MULSATRNDWH_W, MULSATRNDWH_W, INTREG, INTREG, INTREG_HSEL, AVR32_DSP),
26553 +    SYNTAX_NORMAL3(MULSATWH_W, MULSATWH_W, MULSATWH_W, INTREG, INTREG, INTREG_HSEL, AVR32_DSP),
26554 +    SYNTAX_NORMAL3(MULU_D, MULU_D, MULU_D, INTREG, INTREG, INTREG, AVR32_V1),
26555 +    SYNTAX_NORMAL3(MULWH_D, MULWH_D, MULWH_D, INTREG, INTREG, INTREG_HSEL, AVR32_DSP),
26556 +    SYNTAX_NORMAL1(MUSFR, MUSFR, MUSFR, INTREG, AVR32_V1),
26557 +    SYNTAX_NORMAL1(MUSTR, MUSTR, MUSTR, INTREG, AVR32_V1),
26558 +    SYNTAX_NORMAL3(MVCR_D, MVCR_D, MVCR_D, CPNO, DWREG, CPREG_D, AVR32_V1),
26559 +    SYNTAX_NORMAL3(MVCR_W, MVCR_W, MVCR_W, CPNO, INTREG, CPREG, AVR32_V1),
26560 +    SYNTAX_NORMAL3(MVRC_D, MVRC_D, MVRC_D, CPNO, CPREG_D, DWREG, AVR32_V1),
26561 +    SYNTAX_NORMAL3(MVRC_W, MVRC_W, MVRC_W, CPNO, CPREG, INTREG, AVR32_V1),
26562 +    SYNTAX_NORMAL1(NEG, NEG, NEG, INTREG, AVR32_V1),
26563 +    SYNTAX_NORMAL0(NOP, NOP, NOP, AVR32_V1),
26564 +    SYNTAX_NORMAL_C2(OR1, OR, OR1, OR2, INTREG, INTREG, AVR32_V1),
26565 +    SYNTAX_NORMAL_C3(OR2, OR, OR2, OR3, INTREG, INTREG, INTREG_LSL, AVR32_V1),
26566 +    SYNTAX_NORMAL3(OR3, OR, OR3, INTREG, INTREG, INTREG_LSR, AVR32_V1),
26567 +    SYNTAX_NORMAL2(ORH, ORH, ORH, INTREG, UNSIGNED_CONST, AVR32_V1),
26568 +    SYNTAX_NORMAL2(ORL, ORL, ORL, INTREG, UNSIGNED_CONST, AVR32_V1),
26569 +    SYNTAX_NORMAL2(PABS_SB, PABS_SB, PABS_SB, INTREG, INTREG, AVR32_SIMD),
26570 +    SYNTAX_NORMAL2(PABS_SH, PABS_SH, PABS_SH, INTREG, INTREG, AVR32_SIMD),
26571 +    SYNTAX_NORMAL3(PACKSH_SB, PACKSH_SB, PACKSH_SB, INTREG, INTREG, INTREG, AVR32_SIMD),
26572 +    SYNTAX_NORMAL3(PACKSH_UB, PACKSH_UB, PACKSH_UB, INTREG, INTREG, INTREG, AVR32_SIMD),
26573 +    SYNTAX_NORMAL3(PACKW_SH, PACKW_SH, PACKW_SH, INTREG, INTREG, INTREG, AVR32_SIMD),
26574 +    SYNTAX_NORMAL3(PADD_B, PADD_B, PADD_B, INTREG, INTREG, INTREG, AVR32_SIMD),
26575 +    SYNTAX_NORMAL3(PADD_H, PADD_H, PADD_H, INTREG, INTREG, INTREG, AVR32_SIMD),
26576 +    SYNTAX_NORMAL3(PADDH_SH, PADDH_SH, PADDH_SH, INTREG, INTREG, INTREG, AVR32_SIMD),
26577 +    SYNTAX_NORMAL3(PADDH_UB, PADDH_UB, PADDH_UB, INTREG, INTREG, INTREG, AVR32_SIMD),
26578 +    SYNTAX_NORMAL3(PADDS_SB, PADDS_SB, PADDS_SB, INTREG, INTREG, INTREG, AVR32_SIMD),
26579 +    SYNTAX_NORMAL3(PADDS_SH, PADDS_SH, PADDS_SH, INTREG, INTREG, INTREG, AVR32_SIMD),
26580 +    SYNTAX_NORMAL3(PADDS_UB, PADDS_UB, PADDS_UB, INTREG, INTREG, INTREG, AVR32_SIMD),
26581 +    SYNTAX_NORMAL3(PADDS_UH, PADDS_UH, PADDS_UH, INTREG, INTREG, INTREG, AVR32_SIMD),
26582 +    SYNTAX_NORMAL3(PADDSUB_H, PADDSUB_H, PADDSUB_H, INTREG, INTREG_HSEL, INTREG_HSEL, AVR32_SIMD),
26583 +    SYNTAX_NORMAL3(PADDSUBH_SH, PADDSUBH_SH, PADDSUBH_SH, INTREG, INTREG_HSEL, INTREG_HSEL, AVR32_SIMD),
26584 +    SYNTAX_NORMAL3(PADDSUBS_SH, PADDSUBS_SH, PADDSUBS_SH, INTREG, INTREG_HSEL, INTREG_HSEL, AVR32_SIMD),
26585 +    SYNTAX_NORMAL3(PADDSUBS_UH, PADDSUBS_UH, PADDSUBS_UH, INTREG, INTREG_HSEL, INTREG_HSEL, AVR32_SIMD),
26586 +    SYNTAX_NORMAL3(PADDX_H, PADDX_H, PADDX_H, INTREG, INTREG, INTREG, AVR32_SIMD),
26587 +    SYNTAX_NORMAL3(PADDXH_SH, PADDXH_SH, PADDXH_SH, INTREG, INTREG, INTREG, AVR32_SIMD),
26588 +    SYNTAX_NORMAL3(PADDXS_SH, PADDXS_SH, PADDXS_SH, INTREG, INTREG, INTREG, AVR32_SIMD),
26589 +    SYNTAX_NORMAL3(PADDXS_UH, PADDXS_UH, PADDXS_UH, INTREG, INTREG, INTREG, AVR32_SIMD),
26590 +    SYNTAX_NORMAL3(PASR_B, PASR_B, PASR_B, INTREG, INTREG, UNSIGNED_NUMBER, AVR32_SIMD),
26591 +    SYNTAX_NORMAL3(PASR_H, PASR_H, PASR_H, INTREG, INTREG, UNSIGNED_NUMBER, AVR32_SIMD),
26592 +    SYNTAX_NORMAL3(PAVG_SH, PAVG_SH, PAVG_SH, INTREG, INTREG, INTREG, AVR32_SIMD),
26593 +    SYNTAX_NORMAL3(PAVG_UB, PAVG_UB, PAVG_UB, INTREG, INTREG, INTREG, AVR32_SIMD),
26594 +    SYNTAX_NORMAL3(PLSL_B, PLSL_B, PLSL_B, INTREG, INTREG, UNSIGNED_NUMBER, AVR32_SIMD),
26595 +    SYNTAX_NORMAL3(PLSL_H, PLSL_H, PLSL_H, INTREG, INTREG, UNSIGNED_NUMBER, AVR32_SIMD),
26596 +    SYNTAX_NORMAL3(PLSR_B, PLSR_B, PLSR_B, INTREG, INTREG, UNSIGNED_NUMBER, AVR32_SIMD),
26597 +    SYNTAX_NORMAL3(PLSR_H, PLSR_H, PLSR_H, INTREG, INTREG, UNSIGNED_NUMBER, AVR32_SIMD),
26598 +    SYNTAX_NORMAL3(PMAX_SH, PMAX_SH, PMAX_SH, INTREG, INTREG, INTREG, AVR32_SIMD),
26599 +    SYNTAX_NORMAL3(PMAX_UB, PMAX_UB, PMAX_UB, INTREG, INTREG, INTREG, AVR32_SIMD),
26600 +    SYNTAX_NORMAL3(PMIN_SH, PMIN_SH, PMIN_SH, INTREG, INTREG, INTREG, AVR32_SIMD),
26601 +    SYNTAX_NORMAL3(PMIN_UB, PMIN_UB, PMIN_UB, INTREG, INTREG, INTREG, AVR32_SIMD),
26602 +    SYNTAX_NORMAL0(POPJC, POPJC, POPJC, AVR32_V1),
26603 +    SYNTAX_NORMAL_CM1(POPM, POPM, POPM, POPM_E, REGLIST9, AVR32_V1),
26604 +    SYNTAX_NORMALM1(POPM_E, POPM, POPM_E, REGLIST16, AVR32_V1),
26605 +    SYNTAX_NORMAL1(PREF, PREF, PREF, INTREG_SDISP, AVR32_V1),
26606 +    SYNTAX_NORMAL3(PSAD, PSAD, PSAD, INTREG, INTREG, INTREG, AVR32_SIMD),
26607 +    SYNTAX_NORMAL3(PSUB_B, PSUB_B, PSUB_B, INTREG, INTREG, INTREG, AVR32_SIMD),
26608 +    SYNTAX_NORMAL3(PSUB_H, PSUB_H, PSUB_H, INTREG, INTREG, INTREG, AVR32_SIMD),
26609 +    SYNTAX_NORMAL3(PSUBADD_H, PSUBADD_H, PSUBADD_H, INTREG, INTREG_HSEL, INTREG_HSEL, AVR32_SIMD),
26610 +    SYNTAX_NORMAL3(PSUBADDH_SH, PSUBADDH_SH, PSUBADDH_SH, INTREG, INTREG_HSEL, INTREG_HSEL, AVR32_SIMD),
26611 +    SYNTAX_NORMAL3(PSUBADDS_SH, PSUBADDS_SH, PSUBADDS_SH, INTREG, INTREG_HSEL, INTREG_HSEL, AVR32_SIMD),
26612 +    SYNTAX_NORMAL3(PSUBADDS_UH, PSUBADDS_UH, PSUBADDS_UH, INTREG, INTREG_HSEL, INTREG_HSEL, AVR32_SIMD),
26613 +    SYNTAX_NORMAL3(PSUBH_SH, PSUBH_SH, PSUBH_SH, INTREG, INTREG, INTREG, AVR32_SIMD),
26614 +    SYNTAX_NORMAL3(PSUBH_UB, PSUBH_UB, PSUBH_UB, INTREG, INTREG, INTREG, AVR32_SIMD),
26615 +    SYNTAX_NORMAL3(PSUBS_SB, PSUBS_SB, PSUBS_SB, INTREG, INTREG, INTREG, AVR32_SIMD),
26616 +    SYNTAX_NORMAL3(PSUBS_SH, PSUBS_SH, PSUBS_SH, INTREG, INTREG, INTREG, AVR32_SIMD),
26617 +    SYNTAX_NORMAL3(PSUBS_UB, PSUBS_UB, PSUBS_UB, INTREG, INTREG, INTREG, AVR32_SIMD),
26618 +    SYNTAX_NORMAL3(PSUBS_UH, PSUBS_UH, PSUBS_UH, INTREG, INTREG, INTREG, AVR32_SIMD),
26619 +    SYNTAX_NORMAL3(PSUBX_H, PSUBX_H, PSUBX_H, INTREG, INTREG, INTREG, AVR32_SIMD),
26620 +    SYNTAX_NORMAL3(PSUBXH_SH, PSUBXH_SH, PSUBXH_SH, INTREG, INTREG, INTREG, AVR32_SIMD),
26621 +    SYNTAX_NORMAL3(PSUBXS_SH, PSUBXS_SH, PSUBXS_SH, INTREG, INTREG, INTREG, AVR32_SIMD),
26622 +    SYNTAX_NORMAL3(PSUBXS_UH, PSUBXS_UH, PSUBXS_UH, INTREG, INTREG, INTREG, AVR32_SIMD),
26623 +    SYNTAX_NORMAL2(PUNPCKSB_H, PUNPCKSB_H, PUNPCKSB_H, INTREG, INTREG_HSEL, AVR32_SIMD),
26624 +    SYNTAX_NORMAL2(PUNPCKUB_H, PUNPCKUB_H, PUNPCKUB_H, INTREG, INTREG_HSEL, AVR32_SIMD),
26625 +    SYNTAX_NORMAL0(PUSHJC, PUSHJC, PUSHJC, AVR32_V1),
26626 +    SYNTAX_NORMAL_CM1(PUSHM, PUSHM, PUSHM, PUSHM_E, REGLIST8, AVR32_V1),
26627 +    SYNTAX_NORMALM1(PUSHM_E, PUSHM, PUSHM_E, REGLIST16, AVR32_V1),
26628 +    SYNTAX_NORMAL_C1(RCALL1, RCALL, RCALL1, RCALL2, JMPLABEL, AVR32_V1),
26629 +    SYNTAX_NORMAL1(RCALL2, RCALL, RCALL2, JMPLABEL, AVR32_V1),
26630 +    SYNTAX_NORMAL1(RETEQ, RETEQ, RETEQ, RETVAL, AVR32_V1),
26631 +    SYNTAX_NORMAL1(RETNE, RETNE, RETNE, RETVAL, AVR32_V1),
26632 +    SYNTAX_NORMAL1(RETCC, RETCC, RETCC, RETVAL, AVR32_V1),
26633 +    SYNTAX_NORMAL1(RETCS, RETCS, RETCS, RETVAL, AVR32_V1),
26634 +    SYNTAX_NORMAL1(RETGE, RETGE, RETGE, RETVAL, AVR32_V1),
26635 +    SYNTAX_NORMAL1(RETLT, RETLT, RETLT, RETVAL, AVR32_V1),
26636 +    SYNTAX_NORMAL1(RETMI, RETMI, RETMI, RETVAL, AVR32_V1),
26637 +    SYNTAX_NORMAL1(RETPL, RETPL, RETPL, RETVAL, AVR32_V1),
26638 +    SYNTAX_NORMAL1(RETLS, RETLS, RETLS, RETVAL, AVR32_V1),
26639 +    SYNTAX_NORMAL1(RETGT, RETGT, RETGT, RETVAL, AVR32_V1),
26640 +    SYNTAX_NORMAL1(RETLE, RETLE, RETLE, RETVAL, AVR32_V1),
26641 +    SYNTAX_NORMAL1(RETHI, RETHI, RETHI, RETVAL, AVR32_V1),
26642 +    SYNTAX_NORMAL1(RETVS, RETVS, RETVS, RETVAL, AVR32_V1),
26643 +    SYNTAX_NORMAL1(RETVC, RETVC, RETVC, RETVAL, AVR32_V1),
26644 +    SYNTAX_NORMAL1(RETQS, RETQS, RETQS, RETVAL, AVR32_V1),
26645 +    SYNTAX_NORMAL1(RETAL, RETAL, RETAL, RETVAL, AVR32_V1),
26646 +    SYNTAX_NORMAL1(RETHS, RETHS, RETCC, RETVAL, AVR32_V1),
26647 +    SYNTAX_NORMAL1(RETLO, RETLO, RETCS, RETVAL, AVR32_V1),
26648 +    SYNTAX_NORMAL0(RETD, RETD, RETD, AVR32_V1),
26649 +    SYNTAX_NORMAL0(RETE, RETE, RETE, AVR32_V1),
26650 +    SYNTAX_NORMAL0(RETJ, RETJ, RETJ, AVR32_V1),
26651 +    SYNTAX_NORMAL0(RETS, RETS, RETS, AVR32_V1),
26652 +    SYNTAX_NORMAL1(RJMP, RJMP, RJMP, JMPLABEL, AVR32_V1),
26653 +    SYNTAX_NORMAL1(ROL, ROL, ROL, INTREG, AVR32_V1),
26654 +    SYNTAX_NORMAL1(ROR, ROR, ROR, INTREG, AVR32_V1),
26655 +    SYNTAX_NORMAL_C2(RSUB1, RSUB, RSUB1, RSUB2, INTREG, INTREG, AVR32_V1),
26656 +    SYNTAX_NORMAL3(RSUB2, RSUB, RSUB2, INTREG, INTREG, SIGNED_CONST, AVR32_V1),
26657 +    SYNTAX_NORMAL3(SATADD_H, SATADD_H, SATADD_H, INTREG, INTREG, INTREG,  AVR32_DSP),
26658 +    SYNTAX_NORMAL3(SATADD_W, SATADD_W, SATADD_W, INTREG, INTREG, INTREG, AVR32_DSP),
26659 +    SYNTAX_NORMAL2(SATRNDS, SATRNDS, SATRNDS, INTREG_LSR, UNSIGNED_NUMBER, AVR32_DSP),
26660 +    SYNTAX_NORMAL2(SATRNDU, SATRNDU, SATRNDU, INTREG_LSR, UNSIGNED_NUMBER, AVR32_DSP),
26661 +    SYNTAX_NORMAL2(SATS, SATS, SATS, INTREG_LSR, UNSIGNED_NUMBER, AVR32_DSP),
26662 +    SYNTAX_NORMAL3(SATSUB_H, SATSUB_H, SATSUB_H, INTREG, INTREG, INTREG, AVR32_DSP),
26663 +    SYNTAX_NORMAL_C3(SATSUB_W1, SATSUB_W, SATSUB_W1, SATSUB_W2, INTREG, INTREG, INTREG, AVR32_DSP),
26664 +    SYNTAX_NORMAL3(SATSUB_W2, SATSUB_W, SATSUB_W2, INTREG, INTREG, SIGNED_CONST, AVR32_DSP),
26665 +    SYNTAX_NORMAL2(SATU, SATU, SATU, INTREG_LSR, UNSIGNED_NUMBER, AVR32_V1),
26666 +    SYNTAX_NORMAL3(SBC, SBC, SBC, INTREG, INTREG, INTREG, AVR32_V1),
26667 +    SYNTAX_NORMAL2(SBR, SBR, SBR, INTREG, UNSIGNED_NUMBER, AVR32_V1),
26668 +    SYNTAX_NORMAL0(SCALL, SCALL, SCALL, AVR32_V1),
26669 +    SYNTAX_NORMAL1(SCR, SCR, SCR, INTREG, AVR32_V1),
26670 +    SYNTAX_NORMAL1(SLEEP, SLEEP, SLEEP, UNSIGNED_CONST, AVR32_V1),
26671 +    SYNTAX_NORMAL1(SREQ, SREQ, SREQ, INTREG, AVR32_V1),
26672 +    SYNTAX_NORMAL1(SRNE, SRNE, SRNE, INTREG, AVR32_V1),
26673 +    SYNTAX_NORMAL1(SRCC, SRCC, SRCC, INTREG, AVR32_V1),
26674 +    SYNTAX_NORMAL1(SRCS, SRCS, SRCS, INTREG, AVR32_V1),
26675 +    SYNTAX_NORMAL1(SRGE, SRGE, SRGE, INTREG, AVR32_V1),
26676 +    SYNTAX_NORMAL1(SRLT, SRLT, SRLT, INTREG, AVR32_V1),
26677 +    SYNTAX_NORMAL1(SRMI, SRMI, SRMI, INTREG, AVR32_V1),
26678 +    SYNTAX_NORMAL1(SRPL, SRPL, SRPL, INTREG, AVR32_V1),
26679 +    SYNTAX_NORMAL1(SRLS, SRLS, SRLS, INTREG, AVR32_V1),
26680 +    SYNTAX_NORMAL1(SRGT, SRGT, SRGT, INTREG, AVR32_V1),
26681 +    SYNTAX_NORMAL1(SRLE, SRLE, SRLE, INTREG, AVR32_V1),
26682 +    SYNTAX_NORMAL1(SRHI, SRHI, SRHI, INTREG, AVR32_V1),
26683 +    SYNTAX_NORMAL1(SRVS, SRVS, SRVS, INTREG, AVR32_V1),
26684 +    SYNTAX_NORMAL1(SRVC, SRVC, SRVC, INTREG, AVR32_V1),
26685 +    SYNTAX_NORMAL1(SRQS, SRQS, SRQS, INTREG, AVR32_V1),
26686 +    SYNTAX_NORMAL1(SRAL, SRAL, SRAL, INTREG, AVR32_V1),
26687 +    SYNTAX_NORMAL1(SRHS, SRHS, SRCC, INTREG, AVR32_V1),
26688 +    SYNTAX_NORMAL1(SRLO, SRLO, SRCS, INTREG, AVR32_V1),
26689 +    SYNTAX_NORMAL1(SSRF, SSRF, SSRF, UNSIGNED_NUMBER, AVR32_V1),
26690 +    SYNTAX_NORMAL_C2(ST_B1, ST_B, ST_B1, ST_B2, INTREG_POSTINC, INTREG, AVR32_V1),
26691 +    SYNTAX_NORMAL_C2(ST_B2, ST_B, ST_B2, ST_B5, INTREG_PREDEC, INTREG, AVR32_V1),
26692 +    SYNTAX_NORMAL_C2(ST_B5, ST_B, ST_B5, ST_B3, INTREG_INDEX, INTREG, AVR32_V1),
26693 +    SYNTAX_NORMAL_C2(ST_B3, ST_B, ST_B3, ST_B4, INTREG_UDISP, INTREG, AVR32_V1),
26694 +    SYNTAX_NORMAL2(ST_B4, ST_B, ST_B4, INTREG_SDISP, INTREG, AVR32_V1),
26695 +    SYNTAX_NORMAL_C2(ST_D1, ST_D, ST_D1, ST_D2, INTREG_POSTINC, DWREG, AVR32_V1),
26696 +    SYNTAX_NORMAL_C2(ST_D2, ST_D, ST_D2, ST_D3, INTREG_PREDEC, DWREG, AVR32_V1),
26697 +    SYNTAX_NORMAL_C2(ST_D3, ST_D, ST_D3, ST_D5, INTREG, DWREG, AVR32_V1),
26698 +    SYNTAX_NORMAL_C2(ST_D5, ST_D, ST_D5, ST_D4, INTREG_INDEX, DWREG, AVR32_V1),
26699 +    SYNTAX_NORMAL2(ST_D4, ST_D, ST_D4, INTREG_SDISP, DWREG, AVR32_V1),
26700 +    SYNTAX_NORMAL_C2(ST_H1, ST_H, ST_H1, ST_H2, INTREG_POSTINC, INTREG, AVR32_V1),
26701 +    SYNTAX_NORMAL_C2(ST_H2, ST_H, ST_H2, ST_H5, INTREG_PREDEC, INTREG, AVR32_V1),
26702 +    SYNTAX_NORMAL_C2(ST_H5, ST_H, ST_H5, ST_H3, INTREG_INDEX, INTREG, AVR32_V1),
26703 +    SYNTAX_NORMAL_C2(ST_H3, ST_H, ST_H3, ST_H4, INTREG_UDISP_H, INTREG, AVR32_V1),
26704 +    SYNTAX_NORMAL2(ST_H4, ST_H, ST_H4, INTREG_SDISP, INTREG, AVR32_V1),
26705 +    SYNTAX_NORMAL_C2(ST_W1, ST_W, ST_W1, ST_W2, INTREG_POSTINC, INTREG, AVR32_V1),
26706 +    SYNTAX_NORMAL_C2(ST_W2, ST_W, ST_W2, ST_W5, INTREG_PREDEC, INTREG, AVR32_V1),
26707 +    SYNTAX_NORMAL_C2(ST_W5, ST_W, ST_W5, ST_W3, INTREG_INDEX, INTREG, AVR32_V1),
26708 +    SYNTAX_NORMAL_C2(ST_W3, ST_W, ST_W3, ST_W4, INTREG_UDISP_W, INTREG, AVR32_V1),
26709 +    SYNTAX_NORMAL2(ST_W4, ST_W, ST_W4, INTREG_SDISP, INTREG, AVR32_V1),
26710 +    SYNTAX_NORMAL3(STC_D1, STC_D, STC_D1, CPNO, INTREG_UDISP_W, CPREG_D, AVR32_V1),
26711 +    SYNTAX_NORMAL_C3(STC_D2, STC_D, STC_D2, STC_D1, CPNO, INTREG_POSTINC, CPREG_D, AVR32_V1),
26712 +    SYNTAX_NORMAL_C3(STC_D3, STC_D, STC_D3, STC_D2, CPNO, INTREG_INDEX, CPREG_D, AVR32_V1),
26713 +    SYNTAX_NORMAL3(STC_W1, STC_W, STC_W1, CPNO, INTREG_UDISP_W, CPREG, AVR32_V1),
26714 +    SYNTAX_NORMAL_C3(STC_W2, STC_W, STC_W2, STC_W1, CPNO, INTREG_POSTINC, CPREG, AVR32_V1),
26715 +    SYNTAX_NORMAL_C3(STC_W3, STC_W, STC_W3, STC_W2, CPNO, INTREG_INDEX, CPREG, AVR32_V1),
26716 +    SYNTAX_NORMAL2(STC0_D, STC0_D, STC0_D, INTREG_UDISP_W, CPREG_D, AVR32_V1),
26717 +    SYNTAX_NORMAL2(STC0_W, STC0_W, STC0_W, INTREG_UDISP_W, CPREG, AVR32_V1),
26718 +    SYNTAX_NORMAL_CM3(STCM_D, STCM_D, STCM_D, STCM_D_PU, CPNO, INTREG, REGLIST_CPD8, AVR32_V1),
26719 +    SYNTAX_NORMALM3(STCM_D_PU, STCM_D, STCM_D_PU, CPNO, INTREG_PREDEC, REGLIST_CPD8, AVR32_V1),
26720 +    SYNTAX_NORMAL_CM3(STCM_W, STCM_W, STCM_W, STCM_W_PU, CPNO, INTREG, REGLIST_CP8, AVR32_V1),
26721 +    SYNTAX_NORMALM3(STCM_W_PU, STCM_W, STCM_W_PU, CPNO, INTREG_PREDEC, REGLIST_CP8, AVR32_V1),
26722 +    SYNTAX_NORMAL2(STCOND, STCOND, STCOND, INTREG_SDISP, INTREG, AVR32_V1),
26723 +    SYNTAX_NORMAL2(STDSP, STDSP, STDSP, SP_UDISP_W, INTREG, AVR32_V1),
26724 +    SYNTAX_NORMAL_C3(STHH_W2, STHH_W, STHH_W2, STHH_W1, INTREG_INDEX, INTREG_HSEL, INTREG_HSEL, AVR32_V1),
26725 +    SYNTAX_NORMAL3(STHH_W1, STHH_W, STHH_W1, INTREG_UDISP_W, INTREG_HSEL, INTREG_HSEL, AVR32_V1),
26726 +    SYNTAX_NORMAL_CM2(STM, STM, STM, STM_PU, INTREG, REGLIST16, AVR32_V1),
26727 +    SYNTAX_NORMALM2(STM_PU, STM, STM_PU, INTREG_PREDEC, REGLIST16, AVR32_V1),
26728 +    SYNTAX_NORMAL_CM2(STMTS, STMTS, STMTS, STMTS_PU, INTREG, REGLIST16, AVR32_V1),
26729 +    SYNTAX_NORMALM2(STMTS_PU, STMTS, STMTS_PU, INTREG_PREDEC, REGLIST16, AVR32_V1),
26730 +    SYNTAX_NORMAL2(STSWP_H, STSWP_H, STSWP_H, INTREG_SDISP_H, INTREG, AVR32_V1),
26731 +    SYNTAX_NORMAL2(STSWP_W, STSWP_W, STSWP_W, INTREG_SDISP_W, INTREG, AVR32_V1),
26732 +    SYNTAX_NORMAL_C2(SUB1, SUB, SUB1, SUB2, INTREG, INTREG, AVR32_V1),
26733 +    SYNTAX_NORMAL_C3(SUB2, SUB, SUB2, SUB5, INTREG, INTREG, INTREG_LSL, AVR32_V1),
26734 +    SYNTAX_NORMAL_C3(SUB5, SUB, SUB5, SUB3_SP, INTREG, INTREG, SIGNED_CONST, AVR32_V1),
26735 +    SYNTAX_NORMAL_C2(SUB3_SP, SUB, SUB3_SP, SUB3, SP, SIGNED_CONST_W, AVR32_V1),
26736 +    SYNTAX_NORMAL_C2(SUB3, SUB, SUB3, SUB4, INTREG, SIGNED_CONST, AVR32_V1),
26737 +    SYNTAX_NORMAL2(SUB4, SUB, SUB4, INTREG, SIGNED_CONST, AVR32_V1),
26738 +    SYNTAX_NORMAL_C2(SUBEQ, SUBEQ, SUBEQ, SUB2EQ, INTREG, SIGNED_CONST, AVR32_V1),
26739 +    SYNTAX_NORMAL_C2(SUBNE, SUBNE, SUBNE, SUB2NE, INTREG, SIGNED_CONST, AVR32_V1),
26740 +    SYNTAX_NORMAL_C2(SUBCC, SUBCC, SUBCC, SUB2CC, INTREG, SIGNED_CONST, AVR32_V1),
26741 +    SYNTAX_NORMAL_C2(SUBCS, SUBCS, SUBCS, SUB2CS, INTREG, SIGNED_CONST, AVR32_V1),
26742 +    SYNTAX_NORMAL_C2(SUBGE, SUBGE, SUBGE, SUB2GE, INTREG, SIGNED_CONST, AVR32_V1),
26743 +    SYNTAX_NORMAL_C2(SUBLT, SUBLT, SUBLT, SUB2LT, INTREG, SIGNED_CONST, AVR32_V1),
26744 +    SYNTAX_NORMAL_C2(SUBMI, SUBMI, SUBMI, SUB2MI, INTREG, SIGNED_CONST, AVR32_V1),
26745 +    SYNTAX_NORMAL_C2(SUBPL, SUBPL, SUBPL, SUB2PL, INTREG, SIGNED_CONST, AVR32_V1),
26746 +    SYNTAX_NORMAL_C2(SUBLS, SUBLS, SUBLS, SUB2LS, INTREG, SIGNED_CONST, AVR32_V1),
26747 +    SYNTAX_NORMAL_C2(SUBGT, SUBGT, SUBGT, SUB2GT, INTREG, SIGNED_CONST, AVR32_V1),
26748 +    SYNTAX_NORMAL_C2(SUBLE, SUBLE, SUBLE, SUB2LE, INTREG, SIGNED_CONST, AVR32_V1),
26749 +    SYNTAX_NORMAL_C2(SUBHI, SUBHI, SUBHI, SUB2HI, INTREG, SIGNED_CONST, AVR32_V1),
26750 +    SYNTAX_NORMAL_C2(SUBVS, SUBVS, SUBVS, SUB2VS, INTREG, SIGNED_CONST, AVR32_V1),
26751 +    SYNTAX_NORMAL_C2(SUBVC, SUBVC, SUBVC, SUB2VC, INTREG, SIGNED_CONST, AVR32_V1),
26752 +    SYNTAX_NORMAL_C2(SUBQS, SUBQS, SUBQS, SUB2QS, INTREG, SIGNED_CONST, AVR32_V1),
26753 +    SYNTAX_NORMAL_C2(SUBAL, SUBAL, SUBAL, SUB2AL, INTREG, SIGNED_CONST, AVR32_V1),
26754 +    SYNTAX_NORMAL_C2(SUBHS, SUBHS, SUBCC, SUB2CC, INTREG, SIGNED_CONST, AVR32_V1),
26755 +    SYNTAX_NORMAL_C2(SUBLO, SUBLO, SUBCS, SUB2CS, INTREG, SIGNED_CONST, AVR32_V1),
26756 +    SYNTAX_NORMAL2(SUBFEQ, SUBFEQ, SUBFEQ, INTREG, SIGNED_CONST, AVR32_V1),
26757 +    SYNTAX_NORMAL2(SUBFNE, SUBFNE, SUBFNE, INTREG, SIGNED_CONST, AVR32_V1),
26758 +    SYNTAX_NORMAL2(SUBFCC, SUBFCC, SUBFCC, INTREG, SIGNED_CONST, AVR32_V1),
26759 +    SYNTAX_NORMAL2(SUBFCS, SUBFCS, SUBFCS, INTREG, SIGNED_CONST, AVR32_V1),
26760 +    SYNTAX_NORMAL2(SUBFGE, SUBFGE, SUBFGE, INTREG, SIGNED_CONST, AVR32_V1),
26761 +    SYNTAX_NORMAL2(SUBFLT, SUBFLT, SUBFLT, INTREG, SIGNED_CONST, AVR32_V1),
26762 +    SYNTAX_NORMAL2(SUBFMI, SUBFMI, SUBFMI, INTREG, SIGNED_CONST, AVR32_V1),
26763 +    SYNTAX_NORMAL2(SUBFPL, SUBFPL, SUBFPL, INTREG, SIGNED_CONST, AVR32_V1),
26764 +    SYNTAX_NORMAL2(SUBFLS, SUBFLS, SUBFLS, INTREG, SIGNED_CONST, AVR32_V1),
26765 +    SYNTAX_NORMAL2(SUBFGT, SUBFGT, SUBFGT, INTREG, SIGNED_CONST, AVR32_V1),
26766 +    SYNTAX_NORMAL2(SUBFLE, SUBFLE, SUBFLE, INTREG, SIGNED_CONST, AVR32_V1),
26767 +    SYNTAX_NORMAL2(SUBFHI, SUBFHI, SUBFHI, INTREG, SIGNED_CONST, AVR32_V1),
26768 +    SYNTAX_NORMAL2(SUBFVS, SUBFVS, SUBFVS, INTREG, SIGNED_CONST, AVR32_V1),
26769 +    SYNTAX_NORMAL2(SUBFVC, SUBFVC, SUBFVC, INTREG, SIGNED_CONST, AVR32_V1),
26770 +    SYNTAX_NORMAL2(SUBFQS, SUBFQS, SUBFQS, INTREG, SIGNED_CONST, AVR32_V1),
26771 +    SYNTAX_NORMAL2(SUBFAL, SUBFAL, SUBFAL, INTREG, SIGNED_CONST, AVR32_V1),
26772 +    SYNTAX_NORMAL2(SUBFHS, SUBFHS, SUBFCC, INTREG, SIGNED_CONST, AVR32_V1),
26773 +    SYNTAX_NORMAL2(SUBFLO, SUBFLO, SUBFCS, INTREG, SIGNED_CONST, AVR32_V1),
26774 +    SYNTAX_NORMAL3(SUBHH_W, SUBHH_W, SUBHH_W, INTREG, INTREG_HSEL, INTREG_HSEL, AVR32_DSP),
26775 +    SYNTAX_NORMAL1(SWAP_B, SWAP_B, SWAP_B, INTREG, AVR32_V1),
26776 +    SYNTAX_NORMAL1(SWAP_BH, SWAP_BH, SWAP_BH, INTREG, AVR32_V1),
26777 +    SYNTAX_NORMAL1(SWAP_H, SWAP_H, SWAP_H, INTREG, AVR32_V1),
26778 +    SYNTAX_NORMAL1(SYNC, SYNC, SYNC, UNSIGNED_CONST, AVR32_V1),
26779 +    SYNTAX_NORMAL0(TLBR, TLBR, TLBR, AVR32_V1),
26780 +    SYNTAX_NORMAL0(TLBS, TLBS, TLBS, AVR32_V1),
26781 +    SYNTAX_NORMAL0(TLBW, TLBW, TLBW, AVR32_V1),
26782 +    SYNTAX_NORMAL1(TNBZ, TNBZ, TNBZ, INTREG, AVR32_V1),
26783 +    SYNTAX_NORMAL2(TST, TST, TST, INTREG, INTREG, AVR32_V1),
26784 +    SYNTAX_NORMAL3(XCHG, XCHG, XCHG, INTREG, INTREG, INTREG, AVR32_V1),
26785 +    SYNTAX_NORMAL2(MEMC, MEMC, MEMC, SIGNED_CONST_W, UNSIGNED_NUMBER, AVR32_RMW),
26786 +    SYNTAX_NORMAL2(MEMS, MEMS, MEMS, SIGNED_CONST_W, UNSIGNED_NUMBER, AVR32_RMW),
26787 +    SYNTAX_NORMAL2(MEMT, MEMT, MEMT, SIGNED_CONST_W, UNSIGNED_NUMBER, AVR32_RMW),
26788 +    SYNTAX_FP(FADD, 3),
26789 +    SYNTAX_FP(FSUB, 3),
26790 +    SYNTAX_FP(FMAC, 3),
26791 +    SYNTAX_FP(FNMAC, 3),
26792 +    SYNTAX_FP(FMSC, 3),
26793 +    SYNTAX_FP(FNMSC, 3),
26794 +    SYNTAX_FP(FMUL, 3),
26795 +    SYNTAX_FP(FNMUL, 3),
26796 +    SYNTAX_FP(FNEG, 2),
26797 +    SYNTAX_FP(FABS, 2),
26798 +    SYNTAX_FP(FCMP, 2),
26799 +    {
26800 +      AVR32_SYNTAX_FMOV1_S,
26801 +      AVR32_FP, NULL, AVR32_PARSER_ALIAS,
26802 +      { .alias = &avr32_alias_table[AVR32_ALIAS_FMOV1_S] },
26803 +      &avr32_syntax_table[AVR32_SYNTAX_FMOV2_S],
26804 +      2,
26805 +      {
26806 +       AVR32_OPERAND_FPREG_S,
26807 +       AVR32_OPERAND_FPREG_S,
26808 +      },
26809 +    },
26810 +    {
26811 +      AVR32_SYNTAX_FMOV1_D,
26812 +      AVR32_FP, NULL, AVR32_PARSER_ALIAS,
26813 +      { .alias = &avr32_alias_table[AVR32_ALIAS_FMOV1_D] },
26814 +      &avr32_syntax_table[AVR32_SYNTAX_FMOV2_D],
26815 +      2,
26816 +      {
26817 +       AVR32_OPERAND_FPREG_D,
26818 +       AVR32_OPERAND_FPREG_D,
26819 +      },
26820 +    },
26821 +    {
26822 +      AVR32_SYNTAX_FMOV2_S,
26823 +      AVR32_FP, NULL, AVR32_PARSER_ALIAS,
26824 +      { .alias = &avr32_alias_table[AVR32_ALIAS_FMOV2_S] },
26825 +      &avr32_syntax_table[AVR32_SYNTAX_FMOV3_S],
26826 +      2,
26827 +      {
26828 +       AVR32_OPERAND_INTREG,
26829 +       AVR32_OPERAND_FPREG_S,
26830 +      },
26831 +    },
26832 +    {
26833 +      AVR32_SYNTAX_FMOV2_D,
26834 +      AVR32_FP, NULL, AVR32_PARSER_ALIAS,
26835 +      { .alias = &avr32_alias_table[AVR32_ALIAS_FMOV2_D] },
26836 +      &avr32_syntax_table[AVR32_SYNTAX_FMOV3_D],
26837 +      2,
26838 +      {
26839 +       AVR32_OPERAND_DWREG,
26840 +       AVR32_OPERAND_FPREG_D,
26841 +      },
26842 +    },
26843 +    {
26844 +      AVR32_SYNTAX_FMOV3_S,
26845 +      AVR32_FP, NULL, AVR32_PARSER_ALIAS,
26846 +      { .alias = &avr32_alias_table[AVR32_ALIAS_FMOV3_S] }, NULL,
26847 +      2,
26848 +      {
26849 +       AVR32_OPERAND_FPREG_S,
26850 +       AVR32_OPERAND_INTREG,
26851 +      },
26852 +    },
26853 +    {
26854 +      AVR32_SYNTAX_FMOV3_D,
26855 +      AVR32_FP, NULL, AVR32_PARSER_ALIAS,
26856 +      { .alias = &avr32_alias_table[AVR32_ALIAS_FMOV3_D] }, NULL,
26857 +      2,
26858 +      {
26859 +       AVR32_OPERAND_FPREG_D,
26860 +       AVR32_OPERAND_DWREG,
26861 +      },
26862 +    },
26863 +    {
26864 +      AVR32_SYNTAX_FCASTS_D,
26865 +      AVR32_FP, NULL, AVR32_PARSER_ALIAS,
26866 +      { .alias = &avr32_alias_table[AVR32_ALIAS_FCASTS_D] }, NULL,
26867 +      2,
26868 +      {
26869 +       AVR32_OPERAND_FPREG_S,
26870 +       AVR32_OPERAND_FPREG_D,
26871 +      },
26872 +    },
26873 +    {
26874 +      AVR32_SYNTAX_FCASTD_S,
26875 +      AVR32_FP, NULL, AVR32_PARSER_ALIAS,
26876 +      { .alias = &avr32_alias_table[AVR32_ALIAS_FCASTD_S] }, NULL,
26877 +      2,
26878 +      {
26879 +       AVR32_OPERAND_FPREG_D,
26880 +       AVR32_OPERAND_FPREG_S,
26881 +      },
26882 +    },
26883 +    {
26884 +      AVR32_SYNTAX_LDA_W,
26885 +      AVR32_V1, NULL, AVR32_PARSER_LDA,
26886 +      { NULL }, NULL,
26887 +      2,
26888 +      {
26889 +       AVR32_OPERAND_INTREG,
26890 +       AVR32_OPERAND_SIGNED_CONST,
26891 +      },
26892 +    },
26893 +    {
26894 +      AVR32_SYNTAX_CALL,
26895 +      AVR32_V1, NULL, AVR32_PARSER_CALL,
26896 +      { NULL }, NULL,
26897 +      1,
26898 +      {
26899 +       AVR32_OPERAND_JMPLABEL,
26900 +      },
26901 +    },
26902 +    {
26903 +      AVR32_SYNTAX_PICOSVMAC0,
26904 +      AVR32_PICO, &avr32_mnemonic_table[AVR32_MNEMONIC_PICOSVMAC], AVR32_PARSER_ALIAS,
26905 +      { .alias = &avr32_alias_table[AVR32_ALIAS_PICOSVMAC0] },
26906 +      &avr32_syntax_table[AVR32_SYNTAX_PICOSVMAC1], 4,
26907 +      {
26908 +       AVR32_OPERAND_PICO_OUT0,
26909 +       AVR32_OPERAND_PICO_IN,
26910 +       AVR32_OPERAND_PICO_IN,
26911 +       AVR32_OPERAND_PICO_IN,
26912 +      },
26913 +    },
26914 +    {
26915 +      AVR32_SYNTAX_PICOSVMAC1,
26916 +      AVR32_PICO, &avr32_mnemonic_table[AVR32_MNEMONIC_PICOSVMAC], AVR32_PARSER_ALIAS,
26917 +      { .alias = &avr32_alias_table[AVR32_ALIAS_PICOSVMAC1] },
26918 +      &avr32_syntax_table[AVR32_SYNTAX_PICOSVMAC2], 4,
26919 +      {
26920 +       AVR32_OPERAND_PICO_OUT1,
26921 +       AVR32_OPERAND_PICO_IN,
26922 +       AVR32_OPERAND_PICO_IN,
26923 +       AVR32_OPERAND_PICO_IN,
26924 +      },
26925 +    },
26926 +    {
26927 +      AVR32_SYNTAX_PICOSVMAC2,
26928 +      AVR32_PICO, &avr32_mnemonic_table[AVR32_MNEMONIC_PICOSVMAC], AVR32_PARSER_ALIAS,
26929 +      { .alias = &avr32_alias_table[AVR32_ALIAS_PICOSVMAC2] },
26930 +      &avr32_syntax_table[AVR32_SYNTAX_PICOSVMAC3], 4,
26931 +      {
26932 +       AVR32_OPERAND_PICO_OUT2,
26933 +       AVR32_OPERAND_PICO_IN,
26934 +       AVR32_OPERAND_PICO_IN,
26935 +       AVR32_OPERAND_PICO_IN,
26936 +      },
26937 +    },
26938 +    {
26939 +      AVR32_SYNTAX_PICOSVMAC3,
26940 +      AVR32_PICO, &avr32_mnemonic_table[AVR32_MNEMONIC_PICOSVMAC], AVR32_PARSER_ALIAS,
26941 +      { .alias = &avr32_alias_table[AVR32_ALIAS_PICOSVMAC3] },
26942 +      NULL, 4,
26943 +      {
26944 +       AVR32_OPERAND_PICO_OUT3,
26945 +       AVR32_OPERAND_PICO_IN,
26946 +       AVR32_OPERAND_PICO_IN,
26947 +       AVR32_OPERAND_PICO_IN,
26948 +      },
26949 +    },
26950 +    {
26951 +      AVR32_SYNTAX_PICOSVMUL0,
26952 +      AVR32_PICO, &avr32_mnemonic_table[AVR32_MNEMONIC_PICOSVMUL], AVR32_PARSER_ALIAS,
26953 +      { .alias = &avr32_alias_table[AVR32_ALIAS_PICOSVMUL0] },
26954 +      &avr32_syntax_table[AVR32_SYNTAX_PICOSVMUL1], 4,
26955 +      {
26956 +       AVR32_OPERAND_PICO_OUT0,
26957 +       AVR32_OPERAND_PICO_IN,
26958 +       AVR32_OPERAND_PICO_IN,
26959 +       AVR32_OPERAND_PICO_IN,
26960 +      },
26961 +    },
26962 +    {
26963 +      AVR32_SYNTAX_PICOSVMUL1,
26964 +      AVR32_PICO, &avr32_mnemonic_table[AVR32_MNEMONIC_PICOSVMUL], AVR32_PARSER_ALIAS,
26965 +      { .alias = &avr32_alias_table[AVR32_ALIAS_PICOSVMUL1] },
26966 +      &avr32_syntax_table[AVR32_SYNTAX_PICOSVMUL2], 4,
26967 +      {
26968 +       AVR32_OPERAND_PICO_OUT1,
26969 +       AVR32_OPERAND_PICO_IN,
26970 +       AVR32_OPERAND_PICO_IN,
26971 +       AVR32_OPERAND_PICO_IN,
26972 +      },
26973 +    },
26974 +    {
26975 +      AVR32_SYNTAX_PICOSVMUL2,
26976 +      AVR32_PICO, &avr32_mnemonic_table[AVR32_MNEMONIC_PICOSVMUL], AVR32_PARSER_ALIAS,
26977 +      { .alias = &avr32_alias_table[AVR32_ALIAS_PICOSVMUL2] },
26978 +      &avr32_syntax_table[AVR32_SYNTAX_PICOSVMUL3], 4,
26979 +      {
26980 +       AVR32_OPERAND_PICO_OUT2,
26981 +       AVR32_OPERAND_PICO_IN,
26982 +       AVR32_OPERAND_PICO_IN,
26983 +       AVR32_OPERAND_PICO_IN,
26984 +      },
26985 +    },
26986 +    {
26987 +      AVR32_SYNTAX_PICOSVMUL3,
26988 +      AVR32_PICO, &avr32_mnemonic_table[AVR32_MNEMONIC_PICOSVMUL], AVR32_PARSER_ALIAS,
26989 +      { .alias = &avr32_alias_table[AVR32_ALIAS_PICOSVMUL3] },
26990 +      NULL, 4,
26991 +      {
26992 +       AVR32_OPERAND_PICO_OUT3,
26993 +       AVR32_OPERAND_PICO_IN,
26994 +       AVR32_OPERAND_PICO_IN,
26995 +       AVR32_OPERAND_PICO_IN,
26996 +      },
26997 +    },
26998 +    {
26999 +      AVR32_SYNTAX_PICOVMAC0,
27000 +      AVR32_PICO, &avr32_mnemonic_table[AVR32_MNEMONIC_PICOVMAC], AVR32_PARSER_ALIAS,
27001 +      { .alias = &avr32_alias_table[AVR32_ALIAS_PICOVMAC0] },
27002 +      &avr32_syntax_table[AVR32_SYNTAX_PICOVMAC1], 4,
27003 +      {
27004 +       AVR32_OPERAND_PICO_OUT0,
27005 +       AVR32_OPERAND_PICO_IN,
27006 +       AVR32_OPERAND_PICO_IN,
27007 +       AVR32_OPERAND_PICO_IN,
27008 +      },
27009 +    },
27010 +    {
27011 +      AVR32_SYNTAX_PICOVMAC1,
27012 +      AVR32_PICO, &avr32_mnemonic_table[AVR32_MNEMONIC_PICOVMAC], AVR32_PARSER_ALIAS,
27013 +      { .alias = &avr32_alias_table[AVR32_ALIAS_PICOVMAC1] },
27014 +      &avr32_syntax_table[AVR32_SYNTAX_PICOVMAC2], 4,
27015 +      {
27016 +       AVR32_OPERAND_PICO_OUT1,
27017 +       AVR32_OPERAND_PICO_IN,
27018 +       AVR32_OPERAND_PICO_IN,
27019 +       AVR32_OPERAND_PICO_IN,
27020 +      },
27021 +    },
27022 +    {
27023 +      AVR32_SYNTAX_PICOVMAC2,
27024 +      AVR32_PICO, &avr32_mnemonic_table[AVR32_MNEMONIC_PICOVMAC], AVR32_PARSER_ALIAS,
27025 +      { .alias = &avr32_alias_table[AVR32_ALIAS_PICOVMAC2] },
27026 +      &avr32_syntax_table[AVR32_SYNTAX_PICOVMAC3], 4,
27027 +      {
27028 +       AVR32_OPERAND_PICO_OUT2,
27029 +       AVR32_OPERAND_PICO_IN,
27030 +       AVR32_OPERAND_PICO_IN,
27031 +       AVR32_OPERAND_PICO_IN,
27032 +      },
27033 +    },
27034 +    {
27035 +      AVR32_SYNTAX_PICOVMAC3,
27036 +      AVR32_PICO, &avr32_mnemonic_table[AVR32_MNEMONIC_PICOVMAC], AVR32_PARSER_ALIAS,
27037 +      { .alias = &avr32_alias_table[AVR32_ALIAS_PICOVMAC3] },
27038 +      NULL, 4,
27039 +      {
27040 +       AVR32_OPERAND_PICO_OUT3,
27041 +       AVR32_OPERAND_PICO_IN,
27042 +       AVR32_OPERAND_PICO_IN,
27043 +       AVR32_OPERAND_PICO_IN,
27044 +      },
27045 +    },
27046 +    {
27047 +      AVR32_SYNTAX_PICOVMUL0,
27048 +      AVR32_PICO, &avr32_mnemonic_table[AVR32_MNEMONIC_PICOVMUL], AVR32_PARSER_ALIAS,
27049 +      { .alias = &avr32_alias_table[AVR32_ALIAS_PICOVMUL0] },
27050 +      &avr32_syntax_table[AVR32_SYNTAX_PICOVMUL1], 4,
27051 +      {
27052 +       AVR32_OPERAND_PICO_OUT0,
27053 +       AVR32_OPERAND_PICO_IN,
27054 +       AVR32_OPERAND_PICO_IN,
27055 +       AVR32_OPERAND_PICO_IN,
27056 +      },
27057 +    },
27058 +    {
27059 +      AVR32_SYNTAX_PICOVMUL1,
27060 +      AVR32_PICO, &avr32_mnemonic_table[AVR32_MNEMONIC_PICOVMUL], AVR32_PARSER_ALIAS,
27061 +      { .alias = &avr32_alias_table[AVR32_ALIAS_PICOVMUL1] },
27062 +      &avr32_syntax_table[AVR32_SYNTAX_PICOVMUL2], 4,
27063 +      {
27064 +       AVR32_OPERAND_PICO_OUT1,
27065 +       AVR32_OPERAND_PICO_IN,
27066 +       AVR32_OPERAND_PICO_IN,
27067 +       AVR32_OPERAND_PICO_IN,
27068 +      },
27069 +    },
27070 +    {
27071 +      AVR32_SYNTAX_PICOVMUL2,
27072 +      AVR32_PICO, &avr32_mnemonic_table[AVR32_MNEMONIC_PICOVMUL], AVR32_PARSER_ALIAS,
27073 +      { .alias = &avr32_alias_table[AVR32_ALIAS_PICOVMUL2] },
27074 +      &avr32_syntax_table[AVR32_SYNTAX_PICOVMUL3], 4,
27075 +      {
27076 +       AVR32_OPERAND_PICO_OUT2,
27077 +       AVR32_OPERAND_PICO_IN,
27078 +       AVR32_OPERAND_PICO_IN,
27079 +       AVR32_OPERAND_PICO_IN,
27080 +      },
27081 +    },
27082 +    {
27083 +      AVR32_SYNTAX_PICOVMUL3,
27084 +      AVR32_PICO, &avr32_mnemonic_table[AVR32_MNEMONIC_PICOVMUL], AVR32_PARSER_ALIAS,
27085 +      { .alias = &avr32_alias_table[AVR32_ALIAS_PICOVMUL3] },
27086 +      NULL, 4,
27087 +      {
27088 +       AVR32_OPERAND_PICO_OUT3,
27089 +       AVR32_OPERAND_PICO_IN,
27090 +       AVR32_OPERAND_PICO_IN,
27091 +       AVR32_OPERAND_PICO_IN,
27092 +      },
27093 +    },
27094 +    {
27095 +      AVR32_SYNTAX_PICOLD_D2,
27096 +      AVR32_PICO, &avr32_mnemonic_table[AVR32_MNEMONIC_PICOLD_D], AVR32_PARSER_ALIAS,
27097 +      { .alias = &avr32_alias_table[AVR32_ALIAS_PICOLD_D2] },
27098 +      &avr32_syntax_table[AVR32_SYNTAX_PICOLD_D3], 2,
27099 +      {
27100 +       AVR32_OPERAND_PICO_REG_D,
27101 +       AVR32_OPERAND_INTREG_PREDEC,
27102 +      },
27103 +    },
27104 +    {
27105 +      AVR32_SYNTAX_PICOLD_D3,
27106 +      AVR32_PICO, &avr32_mnemonic_table[AVR32_MNEMONIC_PICOLD_D], AVR32_PARSER_ALIAS,
27107 +      { .alias = &avr32_alias_table[AVR32_ALIAS_PICOLD_D3] },
27108 +      &avr32_syntax_table[AVR32_SYNTAX_PICOLD_D1], 2,
27109 +      {
27110 +       AVR32_OPERAND_PICO_REG_D,
27111 +       AVR32_OPERAND_INTREG_INDEX,
27112 +      },
27113 +    },
27114 +    {
27115 +      AVR32_SYNTAX_PICOLD_D1,
27116 +      AVR32_PICO, &avr32_mnemonic_table[AVR32_MNEMONIC_PICOLD_D], AVR32_PARSER_ALIAS,
27117 +      { .alias = &avr32_alias_table[AVR32_ALIAS_PICOLD_D1] },
27118 +      NULL, 2,
27119 +      {
27120 +       AVR32_OPERAND_PICO_REG_D,
27121 +       AVR32_OPERAND_INTREG_UDISP_W,
27122 +      },
27123 +    },
27124 +    {
27125 +      AVR32_SYNTAX_PICOLD_W2,
27126 +      AVR32_PICO, &avr32_mnemonic_table[AVR32_MNEMONIC_PICOLD_W], AVR32_PARSER_ALIAS,
27127 +      { .alias = &avr32_alias_table[AVR32_ALIAS_PICOLD_W2] },
27128 +      &avr32_syntax_table[AVR32_SYNTAX_PICOLD_W3], 2,
27129 +      {
27130 +       AVR32_OPERAND_PICO_REG_W,
27131 +       AVR32_OPERAND_INTREG_PREDEC,
27132 +      },
27133 +    },
27134 +    {
27135 +      AVR32_SYNTAX_PICOLD_W3,
27136 +      AVR32_PICO, &avr32_mnemonic_table[AVR32_MNEMONIC_PICOLD_W], AVR32_PARSER_ALIAS,
27137 +      { .alias = &avr32_alias_table[AVR32_ALIAS_PICOLD_W3] },
27138 +      &avr32_syntax_table[AVR32_SYNTAX_PICOLD_W1], 2,
27139 +      {
27140 +       AVR32_OPERAND_PICO_REG_W,
27141 +       AVR32_OPERAND_INTREG_INDEX,
27142 +      },
27143 +    },
27144 +    {
27145 +      AVR32_SYNTAX_PICOLD_W1,
27146 +      AVR32_PICO, &avr32_mnemonic_table[AVR32_MNEMONIC_PICOLD_W], AVR32_PARSER_ALIAS,
27147 +      { .alias = &avr32_alias_table[AVR32_ALIAS_PICOLD_W1] },
27148 +      NULL, 2,
27149 +      {
27150 +       AVR32_OPERAND_PICO_REG_W,
27151 +       AVR32_OPERAND_INTREG_UDISP_W,
27152 +      },
27153 +    },
27154 +    {
27155 +      AVR32_SYNTAX_PICOLDM_D,
27156 +      AVR32_PICO, &avr32_mnemonic_table[AVR32_MNEMONIC_PICOLDM_D], AVR32_PARSER_ALIAS,
27157 +      { .alias = &avr32_alias_table[AVR32_ALIAS_PICOLDM_D] },
27158 +      &avr32_syntax_table[AVR32_SYNTAX_PICOLDM_D_PU], -2,
27159 +      {
27160 +       AVR32_OPERAND_INTREG,
27161 +       AVR32_OPERAND_PICO_REGLIST_D,
27162 +      },
27163 +    },
27164 +    {
27165 +      AVR32_SYNTAX_PICOLDM_D_PU,
27166 +      AVR32_PICO, &avr32_mnemonic_table[AVR32_MNEMONIC_PICOLDM_D], AVR32_PARSER_ALIAS,
27167 +      { .alias = &avr32_alias_table[AVR32_ALIAS_PICOLDM_D_PU] },
27168 +      NULL, -2,
27169 +      {
27170 +       AVR32_OPERAND_INTREG_POSTINC,
27171 +       AVR32_OPERAND_PICO_REGLIST_D,
27172 +      },
27173 +    },
27174 +    {
27175 +      AVR32_SYNTAX_PICOLDM_W,
27176 +      AVR32_PICO, &avr32_mnemonic_table[AVR32_MNEMONIC_PICOLDM_W], AVR32_PARSER_ALIAS,
27177 +      { .alias = &avr32_alias_table[AVR32_ALIAS_PICOLDM_W] },
27178 +      &avr32_syntax_table[AVR32_SYNTAX_PICOLDM_W_PU], -2,
27179 +      {
27180 +       AVR32_OPERAND_INTREG,
27181 +       AVR32_OPERAND_PICO_REGLIST_W,
27182 +      },
27183 +    },
27184 +    {
27185 +      AVR32_SYNTAX_PICOLDM_W_PU,
27186 +      AVR32_PICO, &avr32_mnemonic_table[AVR32_MNEMONIC_PICOLDM_W], AVR32_PARSER_ALIAS,
27187 +      { .alias = &avr32_alias_table[AVR32_ALIAS_PICOLDM_W_PU] },
27188 +      NULL, -2,
27189 +      {
27190 +       AVR32_OPERAND_INTREG_POSTINC,
27191 +       AVR32_OPERAND_PICO_REGLIST_W,
27192 +      },
27193 +    },
27194 +    {
27195 +      AVR32_SYNTAX_PICOMV_D1,
27196 +      AVR32_PICO, &avr32_mnemonic_table[AVR32_MNEMONIC_PICOMV_D], AVR32_PARSER_ALIAS,
27197 +      { .alias = &avr32_alias_table[AVR32_ALIAS_PICOMV_D1] },
27198 +      &avr32_syntax_table[AVR32_SYNTAX_PICOMV_D2], 2,
27199 +      {
27200 +       AVR32_OPERAND_DWREG,
27201 +       AVR32_OPERAND_PICO_REG_D,
27202 +      },
27203 +    },
27204 +    {
27205 +      AVR32_SYNTAX_PICOMV_D2,
27206 +      AVR32_PICO, &avr32_mnemonic_table[AVR32_MNEMONIC_PICOMV_D], AVR32_PARSER_ALIAS,
27207 +      { .alias = &avr32_alias_table[AVR32_ALIAS_PICOMV_D2] },
27208 +      NULL, 2,
27209 +      {
27210 +       AVR32_OPERAND_PICO_REG_D,
27211 +       AVR32_OPERAND_DWREG,
27212 +      },
27213 +    },
27214 +    {
27215 +      AVR32_SYNTAX_PICOMV_W1,
27216 +      AVR32_PICO, &avr32_mnemonic_table[AVR32_MNEMONIC_PICOMV_W], AVR32_PARSER_ALIAS,
27217 +      { .alias = &avr32_alias_table[AVR32_ALIAS_PICOMV_W1] },
27218 +      &avr32_syntax_table[AVR32_SYNTAX_PICOMV_W2], 2,
27219 +      {
27220 +       AVR32_OPERAND_INTREG,
27221 +       AVR32_OPERAND_PICO_REG_W,
27222 +      },
27223 +    },
27224 +    {
27225 +      AVR32_SYNTAX_PICOMV_W2,
27226 +      AVR32_PICO, &avr32_mnemonic_table[AVR32_MNEMONIC_PICOMV_W], AVR32_PARSER_ALIAS,
27227 +      { .alias = &avr32_alias_table[AVR32_ALIAS_PICOMV_W2] },
27228 +      NULL, 2,
27229 +      {
27230 +       AVR32_OPERAND_PICO_REG_W,
27231 +       AVR32_OPERAND_INTREG,
27232 +      },
27233 +    },
27234 +    {
27235 +      AVR32_SYNTAX_PICOST_D2,
27236 +      AVR32_PICO, &avr32_mnemonic_table[AVR32_MNEMONIC_PICOST_D], AVR32_PARSER_ALIAS,
27237 +      { .alias = &avr32_alias_table[AVR32_ALIAS_PICOST_D2] },
27238 +      &avr32_syntax_table[AVR32_SYNTAX_PICOST_D3], 2,
27239 +      {
27240 +       AVR32_OPERAND_INTREG_POSTINC,
27241 +       AVR32_OPERAND_PICO_REG_D,
27242 +      },
27243 +    },
27244 +    {
27245 +      AVR32_SYNTAX_PICOST_D3,
27246 +      AVR32_PICO, &avr32_mnemonic_table[AVR32_MNEMONIC_PICOST_D], AVR32_PARSER_ALIAS,
27247 +      { .alias = &avr32_alias_table[AVR32_ALIAS_PICOST_D3] },
27248 +      &avr32_syntax_table[AVR32_SYNTAX_PICOST_D1], 2,
27249 +      {
27250 +       AVR32_OPERAND_INTREG_INDEX,
27251 +       AVR32_OPERAND_PICO_REG_D,
27252 +      },
27253 +    },
27254 +    {
27255 +      AVR32_SYNTAX_PICOST_D1,
27256 +      AVR32_PICO, &avr32_mnemonic_table[AVR32_MNEMONIC_PICOST_D], AVR32_PARSER_ALIAS,
27257 +      { .alias = &avr32_alias_table[AVR32_ALIAS_PICOST_D1] },
27258 +      NULL, 2,
27259 +      {
27260 +       AVR32_OPERAND_INTREG_UDISP_W,
27261 +       AVR32_OPERAND_PICO_REG_D,
27262 +      },
27263 +    },
27264 +    {
27265 +      AVR32_SYNTAX_PICOST_W2,
27266 +      AVR32_PICO, &avr32_mnemonic_table[AVR32_MNEMONIC_PICOST_W], AVR32_PARSER_ALIAS,
27267 +      { .alias = &avr32_alias_table[AVR32_ALIAS_PICOST_W2] },
27268 +      &avr32_syntax_table[AVR32_SYNTAX_PICOST_W3], 2,
27269 +      {
27270 +       AVR32_OPERAND_INTREG_POSTINC,
27271 +       AVR32_OPERAND_PICO_REG_W,
27272 +      },
27273 +    },
27274 +    {
27275 +      AVR32_SYNTAX_PICOST_W3,
27276 +      AVR32_PICO, &avr32_mnemonic_table[AVR32_MNEMONIC_PICOST_W], AVR32_PARSER_ALIAS,
27277 +      { .alias = &avr32_alias_table[AVR32_ALIAS_PICOST_W3] },
27278 +      &avr32_syntax_table[AVR32_SYNTAX_PICOST_W1], 2,
27279 +      {
27280 +       AVR32_OPERAND_INTREG_INDEX,
27281 +       AVR32_OPERAND_PICO_REG_W,
27282 +      },
27283 +    },
27284 +    {
27285 +      AVR32_SYNTAX_PICOST_W1,
27286 +      AVR32_PICO, &avr32_mnemonic_table[AVR32_MNEMONIC_PICOST_W], AVR32_PARSER_ALIAS,
27287 +      { .alias = &avr32_alias_table[AVR32_ALIAS_PICOST_W1] },
27288 +      NULL, 2,
27289 +      {
27290 +       AVR32_OPERAND_INTREG_UDISP_W,
27291 +       AVR32_OPERAND_PICO_REG_W,
27292 +      },
27293 +    },
27294 +    {
27295 +      AVR32_SYNTAX_PICOSTM_D,
27296 +      AVR32_PICO, &avr32_mnemonic_table[AVR32_MNEMONIC_PICOSTM_D], AVR32_PARSER_ALIAS,
27297 +      { .alias = &avr32_alias_table[AVR32_ALIAS_PICOSTM_D] },
27298 +      &avr32_syntax_table[AVR32_SYNTAX_PICOSTM_D_PU], -2,
27299 +      {
27300 +       AVR32_OPERAND_INTREG,
27301 +       AVR32_OPERAND_PICO_REGLIST_D,
27302 +      },
27303 +    },
27304 +    {
27305 +      AVR32_SYNTAX_PICOSTM_D_PU,
27306 +      AVR32_PICO, &avr32_mnemonic_table[AVR32_MNEMONIC_PICOSTM_D], AVR32_PARSER_ALIAS,
27307 +      { .alias = &avr32_alias_table[AVR32_ALIAS_PICOSTM_D_PU] },
27308 +      NULL, -2,
27309 +      {
27310 +       AVR32_OPERAND_INTREG_PREDEC,
27311 +       AVR32_OPERAND_PICO_REGLIST_D,
27312 +      },
27313 +    },
27314 +    {
27315 +      AVR32_SYNTAX_PICOSTM_W,
27316 +      AVR32_PICO, &avr32_mnemonic_table[AVR32_MNEMONIC_PICOSTM_W], AVR32_PARSER_ALIAS,
27317 +      { .alias = &avr32_alias_table[AVR32_ALIAS_PICOSTM_W] },
27318 +      &avr32_syntax_table[AVR32_SYNTAX_PICOSTM_W_PU], -2,
27319 +      {
27320 +       AVR32_OPERAND_INTREG,
27321 +       AVR32_OPERAND_PICO_REGLIST_W,
27322 +      },
27323 +    },
27324 +    {
27325 +      AVR32_SYNTAX_PICOSTM_W_PU,
27326 +      AVR32_PICO, &avr32_mnemonic_table[AVR32_MNEMONIC_PICOSTM_W], AVR32_PARSER_ALIAS,
27327 +      { .alias = &avr32_alias_table[AVR32_ALIAS_PICOSTM_W_PU] },
27328 +      NULL, -2,
27329 +      {
27330 +       AVR32_OPERAND_INTREG_PREDEC,
27331 +       AVR32_OPERAND_PICO_REGLIST_W,
27332 +      },
27333 +    },
27334 +    SYNTAX_NORMAL2(RSUBEQ, RSUBEQ, RSUBEQ, INTREG, SIGNED_CONST, AVR32_V1),
27335 +    SYNTAX_NORMAL2(RSUBNE, RSUBNE, RSUBNE, INTREG, SIGNED_CONST, AVR32_V2),
27336 +    SYNTAX_NORMAL2(RSUBCC, RSUBCC, RSUBCC, INTREG, SIGNED_CONST, AVR32_V2),
27337 +    SYNTAX_NORMAL2(RSUBCS, RSUBCS, RSUBCS, INTREG, SIGNED_CONST, AVR32_V2),
27338 +    SYNTAX_NORMAL2(RSUBGE, RSUBGE, RSUBGE, INTREG, SIGNED_CONST, AVR32_V2),
27339 +    SYNTAX_NORMAL2(RSUBLT, RSUBLT, RSUBLT, INTREG, SIGNED_CONST, AVR32_V2),
27340 +    SYNTAX_NORMAL2(RSUBMI, RSUBMI, RSUBMI, INTREG, SIGNED_CONST, AVR32_V2),
27341 +    SYNTAX_NORMAL2(RSUBPL, RSUBPL, RSUBPL, INTREG, SIGNED_CONST, AVR32_V2),
27342 +    SYNTAX_NORMAL2(RSUBLS, RSUBLS, RSUBLS, INTREG, SIGNED_CONST, AVR32_V2),
27343 +    SYNTAX_NORMAL2(RSUBGT, RSUBGT, RSUBGT, INTREG, SIGNED_CONST, AVR32_V2),
27344 +    SYNTAX_NORMAL2(RSUBLE, RSUBLE, RSUBLE, INTREG, SIGNED_CONST, AVR32_V2),
27345 +    SYNTAX_NORMAL2(RSUBHI, RSUBHI, RSUBHI, INTREG, SIGNED_CONST, AVR32_V2),
27346 +    SYNTAX_NORMAL2(RSUBVS, RSUBVS, RSUBVS, INTREG, SIGNED_CONST, AVR32_V2),
27347 +    SYNTAX_NORMAL2(RSUBVC, RSUBVC, RSUBVC, INTREG, SIGNED_CONST, AVR32_V2),
27348 +    SYNTAX_NORMAL2(RSUBQS, RSUBQS, RSUBQS, INTREG, SIGNED_CONST, AVR32_V2),
27349 +    SYNTAX_NORMAL2(RSUBAL, RSUBAL, RSUBAL, INTREG, SIGNED_CONST, AVR32_V2),
27350 +    SYNTAX_NORMAL2(RSUBHS, RSUBHS, RSUBCC, INTREG, SIGNED_CONST, AVR32_V2),
27351 +    SYNTAX_NORMAL2(RSUBLO, RSUBLO, RSUBCS, INTREG, SIGNED_CONST, AVR32_V2),
27352 +    SYNTAX_NORMAL3(ADDEQ, ADDEQ, ADDEQ, INTREG, INTREG, INTREG, AVR32_V2),
27353 +    SYNTAX_NORMAL3(ADDNE, ADDNE, ADDNE, INTREG, INTREG, INTREG, AVR32_V2),
27354 +    SYNTAX_NORMAL3(ADDCC, ADDCC, ADDCC, INTREG, INTREG, INTREG, AVR32_V2),
27355 +    SYNTAX_NORMAL3(ADDCS, ADDCS, ADDCS, INTREG, INTREG, INTREG, AVR32_V2),
27356 +    SYNTAX_NORMAL3(ADDGE, ADDGE, ADDGE, INTREG, INTREG, INTREG, AVR32_V2),
27357 +    SYNTAX_NORMAL3(ADDLT, ADDLT, ADDLT, INTREG, INTREG, INTREG, AVR32_V2),
27358 +    SYNTAX_NORMAL3(ADDMI, ADDMI, ADDMI, INTREG, INTREG, INTREG, AVR32_V2),
27359 +    SYNTAX_NORMAL3(ADDPL, ADDPL, ADDPL, INTREG, INTREG, INTREG, AVR32_V2),
27360 +    SYNTAX_NORMAL3(ADDLS, ADDLS, ADDLS, INTREG, INTREG, INTREG, AVR32_V2),
27361 +    SYNTAX_NORMAL3(ADDGT, ADDGT, ADDGT, INTREG, INTREG, INTREG, AVR32_V2),
27362 +    SYNTAX_NORMAL3(ADDLE, ADDLE, ADDLE, INTREG, INTREG, INTREG, AVR32_V2),
27363 +    SYNTAX_NORMAL3(ADDHI, ADDHI, ADDHI, INTREG, INTREG, INTREG, AVR32_V2),
27364 +    SYNTAX_NORMAL3(ADDVS, ADDVS, ADDVS, INTREG, INTREG, INTREG, AVR32_V2),
27365 +    SYNTAX_NORMAL3(ADDVC, ADDVC, ADDVC, INTREG, INTREG, INTREG, AVR32_V2),
27366 +    SYNTAX_NORMAL3(ADDQS, ADDQS, ADDQS, INTREG, INTREG, INTREG, AVR32_V2),
27367 +    SYNTAX_NORMAL3(ADDAL, ADDAL, ADDAL, INTREG, INTREG, INTREG, AVR32_V2),
27368 +    SYNTAX_NORMAL3(ADDHS, ADDHS, ADDCC, INTREG, INTREG, INTREG, AVR32_V2),
27369 +    SYNTAX_NORMAL3(ADDLO, ADDLO, ADDCS, INTREG, INTREG, INTREG, AVR32_V2),
27370 +    SYNTAX_NORMAL3(SUB2EQ, SUBEQ, SUB2EQ, INTREG, INTREG, INTREG, AVR32_V2),
27371 +    SYNTAX_NORMAL3(SUB2NE, SUBNE, SUB2NE, INTREG, INTREG, INTREG, AVR32_V2),
27372 +    SYNTAX_NORMAL3(SUB2CC, SUBCC, SUB2CC, INTREG, INTREG, INTREG, AVR32_V2),
27373 +    SYNTAX_NORMAL3(SUB2CS, SUBCS, SUB2CS, INTREG, INTREG, INTREG, AVR32_V2),
27374 +    SYNTAX_NORMAL3(SUB2GE, SUBGE, SUB2GE, INTREG, INTREG, INTREG, AVR32_V2),
27375 +    SYNTAX_NORMAL3(SUB2LT, SUBLT, SUB2LT, INTREG, INTREG, INTREG, AVR32_V2),
27376 +    SYNTAX_NORMAL3(SUB2MI, SUBMI, SUB2MI, INTREG, INTREG, INTREG, AVR32_V2),
27377 +    SYNTAX_NORMAL3(SUB2PL, SUBPL, SUB2PL, INTREG, INTREG, INTREG, AVR32_V2),
27378 +    SYNTAX_NORMAL3(SUB2LS, SUBLS, SUB2LS, INTREG, INTREG, INTREG, AVR32_V2),
27379 +    SYNTAX_NORMAL3(SUB2GT, SUBGT, SUB2GT, INTREG, INTREG, INTREG, AVR32_V2),
27380 +    SYNTAX_NORMAL3(SUB2LE, SUBLE, SUB2LE, INTREG, INTREG, INTREG, AVR32_V2),
27381 +    SYNTAX_NORMAL3(SUB2HI, SUBHI, SUB2HI, INTREG, INTREG, INTREG, AVR32_V2),
27382 +    SYNTAX_NORMAL3(SUB2VS, SUBVS, SUB2VS, INTREG, INTREG, INTREG, AVR32_V2),
27383 +    SYNTAX_NORMAL3(SUB2VC, SUBVC, SUB2VC, INTREG, INTREG, INTREG, AVR32_V2),
27384 +    SYNTAX_NORMAL3(SUB2QS, SUBQS, SUB2QS, INTREG, INTREG, INTREG, AVR32_V2),
27385 +    SYNTAX_NORMAL3(SUB2AL, SUBAL, SUB2AL, INTREG, INTREG, INTREG, AVR32_V2),
27386 +    SYNTAX_NORMAL3(SUB2HS, SUBHS, SUB2CC, INTREG, INTREG, INTREG, AVR32_V2),
27387 +    SYNTAX_NORMAL3(SUB2LO, SUBLO, SUB2CS, INTREG, INTREG, INTREG, AVR32_V2),
27388 +    SYNTAX_NORMAL3(ANDEQ, ANDEQ, ANDEQ, INTREG, INTREG, INTREG, AVR32_V2),
27389 +    SYNTAX_NORMAL3(ANDNE, ANDNE, ANDNE, INTREG, INTREG, INTREG, AVR32_V2),
27390 +    SYNTAX_NORMAL3(ANDCC, ANDCC, ANDCC, INTREG, INTREG, INTREG, AVR32_V2),
27391 +    SYNTAX_NORMAL3(ANDCS, ANDCS, ANDCS, INTREG, INTREG, INTREG, AVR32_V2),
27392 +    SYNTAX_NORMAL3(ANDGE, ANDGE, ANDGE, INTREG, INTREG, INTREG, AVR32_V2),
27393 +    SYNTAX_NORMAL3(ANDLT, ANDLT, ANDLT, INTREG, INTREG, INTREG, AVR32_V2),
27394 +    SYNTAX_NORMAL3(ANDMI, ANDMI, ANDMI, INTREG, INTREG, INTREG, AVR32_V2),
27395 +    SYNTAX_NORMAL3(ANDPL, ANDPL, ANDPL, INTREG, INTREG, INTREG, AVR32_V2),
27396 +    SYNTAX_NORMAL3(ANDLS, ANDLS, ANDLS, INTREG, INTREG, INTREG, AVR32_V2),
27397 +    SYNTAX_NORMAL3(ANDGT, ANDGT, ANDGT, INTREG, INTREG, INTREG, AVR32_V2),
27398 +    SYNTAX_NORMAL3(ANDLE, ANDLE, ANDLE, INTREG, INTREG, INTREG, AVR32_V2),
27399 +    SYNTAX_NORMAL3(ANDHI, ANDHI, ANDHI, INTREG, INTREG, INTREG, AVR32_V2),
27400 +    SYNTAX_NORMAL3(ANDVS, ANDVS, ANDVS, INTREG, INTREG, INTREG, AVR32_V2),
27401 +    SYNTAX_NORMAL3(ANDVC, ANDVC, ANDVC, INTREG, INTREG, INTREG, AVR32_V2),
27402 +    SYNTAX_NORMAL3(ANDQS, ANDQS, ANDQS, INTREG, INTREG, INTREG, AVR32_V2),
27403 +    SYNTAX_NORMAL3(ANDAL, ANDAL, ANDAL, INTREG, INTREG, INTREG, AVR32_V2),
27404 +    SYNTAX_NORMAL3(ANDHS, ANDHS, ANDCC, INTREG, INTREG, INTREG, AVR32_V2),
27405 +    SYNTAX_NORMAL3(ANDLO, ANDLO, ANDCS, INTREG, INTREG, INTREG, AVR32_V2),
27406 +    SYNTAX_NORMAL3(OREQ, OREQ, OREQ, INTREG, INTREG, INTREG, AVR32_V2),
27407 +    SYNTAX_NORMAL3(ORNE, ORNE, ORNE, INTREG, INTREG, INTREG, AVR32_V2),
27408 +    SYNTAX_NORMAL3(ORCC, ORCC, ORCC, INTREG, INTREG, INTREG, AVR32_V2),
27409 +    SYNTAX_NORMAL3(ORCS, ORCS, ORCS, INTREG, INTREG, INTREG, AVR32_V2),
27410 +    SYNTAX_NORMAL3(ORGE, ORGE, ORGE, INTREG, INTREG, INTREG, AVR32_V2),
27411 +    SYNTAX_NORMAL3(ORLT, ORLT, ORLT, INTREG, INTREG, INTREG, AVR32_V2),
27412 +    SYNTAX_NORMAL3(ORMI, ORMI, ORMI, INTREG, INTREG, INTREG, AVR32_V2),
27413 +    SYNTAX_NORMAL3(ORPL, ORPL, ORPL, INTREG, INTREG, INTREG, AVR32_V2),
27414 +    SYNTAX_NORMAL3(ORLS, ORLS, ORLS, INTREG, INTREG, INTREG, AVR32_V2),
27415 +    SYNTAX_NORMAL3(ORGT, ORGT, ORGT, INTREG, INTREG, INTREG, AVR32_V2),
27416 +    SYNTAX_NORMAL3(ORLE, ORLE, ORLE, INTREG, INTREG, INTREG, AVR32_V2),
27417 +    SYNTAX_NORMAL3(ORHI, ORHI, ORHI, INTREG, INTREG, INTREG, AVR32_V2),
27418 +    SYNTAX_NORMAL3(ORVS, ORVS, ORVS, INTREG, INTREG, INTREG, AVR32_V2),
27419 +    SYNTAX_NORMAL3(ORVC, ORVC, ORVC, INTREG, INTREG, INTREG, AVR32_V2),
27420 +    SYNTAX_NORMAL3(ORQS, ORQS, ORQS, INTREG, INTREG, INTREG, AVR32_V2),
27421 +    SYNTAX_NORMAL3(ORAL, ORAL, ORAL, INTREG, INTREG, INTREG, AVR32_V2),
27422 +    SYNTAX_NORMAL3(ORHS, ORHS, ORCC, INTREG, INTREG, INTREG, AVR32_V2),
27423 +    SYNTAX_NORMAL3(ORLO, ORLO, ORCS, INTREG, INTREG, INTREG, AVR32_V2),
27424 +    SYNTAX_NORMAL3(EOREQ, EOREQ, EOREQ, INTREG, INTREG, INTREG, AVR32_V2),
27425 +    SYNTAX_NORMAL3(EORNE, EORNE, EORNE, INTREG, INTREG, INTREG, AVR32_V2),
27426 +    SYNTAX_NORMAL3(EORCC, EORCC, EORCC, INTREG, INTREG, INTREG, AVR32_V2),
27427 +    SYNTAX_NORMAL3(EORCS, EORCS, EORCS, INTREG, INTREG, INTREG, AVR32_V2),
27428 +    SYNTAX_NORMAL3(EORGE, EORGE, EORGE, INTREG, INTREG, INTREG, AVR32_V2),
27429 +    SYNTAX_NORMAL3(EORLT, EORLT, EORLT, INTREG, INTREG, INTREG, AVR32_V2),
27430 +    SYNTAX_NORMAL3(EORMI, EORMI, EORMI, INTREG, INTREG, INTREG, AVR32_V2),
27431 +    SYNTAX_NORMAL3(EORPL, EORPL, EORPL, INTREG, INTREG, INTREG, AVR32_V2),
27432 +    SYNTAX_NORMAL3(EORLS, EORLS, EORLS, INTREG, INTREG, INTREG, AVR32_V2),
27433 +    SYNTAX_NORMAL3(EORGT, EORGT, EORGT, INTREG, INTREG, INTREG, AVR32_V2),
27434 +    SYNTAX_NORMAL3(EORLE, EORLE, EORLE, INTREG, INTREG, INTREG, AVR32_V2),
27435 +    SYNTAX_NORMAL3(EORHI, EORHI, EORHI, INTREG, INTREG, INTREG, AVR32_V2),
27436 +    SYNTAX_NORMAL3(EORVS, EORVS, EORVS, INTREG, INTREG, INTREG, AVR32_V2),
27437 +    SYNTAX_NORMAL3(EORVC, EORVC, EORVC, INTREG, INTREG, INTREG, AVR32_V2),
27438 +    SYNTAX_NORMAL3(EORQS, EORQS, EORQS, INTREG, INTREG, INTREG, AVR32_V2),
27439 +    SYNTAX_NORMAL3(EORAL, EORAL, EORAL, INTREG, INTREG, INTREG, AVR32_V2),
27440 +    SYNTAX_NORMAL3(EORHS, EORHS, EORCC, INTREG, INTREG, INTREG, AVR32_V2),
27441 +    SYNTAX_NORMAL3(EORLO, EORLO, EORCS, INTREG, INTREG, INTREG, AVR32_V2),
27442 +    SYNTAX_NORMAL2(LD_WEQ, LD_WEQ, LD_WEQ, INTREG, INTREG_UDISP_W, AVR32_V2),
27443 +    SYNTAX_NORMAL2(LD_WNE, LD_WNE, LD_WNE, INTREG, INTREG_UDISP_W, AVR32_V2),
27444 +    SYNTAX_NORMAL2(LD_WCC, LD_WCC, LD_WCC, INTREG, INTREG_UDISP_W, AVR32_V2),
27445 +    SYNTAX_NORMAL2(LD_WCS, LD_WCS, LD_WCS, INTREG, INTREG_UDISP_W, AVR32_V2),
27446 +    SYNTAX_NORMAL2(LD_WGE, LD_WGE, LD_WGE, INTREG, INTREG_UDISP_W, AVR32_V2),
27447 +    SYNTAX_NORMAL2(LD_WLT, LD_WLT, LD_WLT, INTREG, INTREG_UDISP_W, AVR32_V2),
27448 +    SYNTAX_NORMAL2(LD_WMI, LD_WMI, LD_WMI, INTREG, INTREG_UDISP_W, AVR32_V2),
27449 +    SYNTAX_NORMAL2(LD_WPL, LD_WPL, LD_WPL, INTREG, INTREG_UDISP_W, AVR32_V2),
27450 +    SYNTAX_NORMAL2(LD_WLS, LD_WLS, LD_WLS, INTREG, INTREG_UDISP_W, AVR32_V2),
27451 +    SYNTAX_NORMAL2(LD_WGT, LD_WGT, LD_WGT, INTREG, INTREG_UDISP_W, AVR32_V2),
27452 +    SYNTAX_NORMAL2(LD_WLE, LD_WLE, LD_WLE, INTREG, INTREG_UDISP_W, AVR32_V2),
27453 +    SYNTAX_NORMAL2(LD_WHI, LD_WHI, LD_WHI, INTREG, INTREG_UDISP_W, AVR32_V2),
27454 +    SYNTAX_NORMAL2(LD_WVS, LD_WVS, LD_WVS, INTREG, INTREG_UDISP_W, AVR32_V2),
27455 +    SYNTAX_NORMAL2(LD_WVC, LD_WVC, LD_WVC, INTREG, INTREG_UDISP_W, AVR32_V2),
27456 +    SYNTAX_NORMAL2(LD_WQS, LD_WQS, LD_WQS, INTREG, INTREG_UDISP_W, AVR32_V2),
27457 +    SYNTAX_NORMAL2(LD_WAL, LD_WAL, LD_WAL, INTREG, INTREG_UDISP_W, AVR32_V2),
27458 +    SYNTAX_NORMAL2(LD_WHS, LD_WHS, LD_WCC, INTREG, INTREG_UDISP_W, AVR32_V2),
27459 +    SYNTAX_NORMAL2(LD_WLO, LD_WLO, LD_WCS, INTREG, INTREG_UDISP_W, AVR32_V2),
27460 +    SYNTAX_NORMAL2(LD_SHEQ, LD_SHEQ, LD_SHEQ, INTREG, INTREG_UDISP_H, AVR32_V2),
27461 +    SYNTAX_NORMAL2(LD_SHNE, LD_SHNE, LD_SHNE, INTREG, INTREG_UDISP_H, AVR32_V2),
27462 +    SYNTAX_NORMAL2(LD_SHCC, LD_SHCC, LD_SHCC, INTREG, INTREG_UDISP_H, AVR32_V2),
27463 +    SYNTAX_NORMAL2(LD_SHCS, LD_SHCS, LD_SHCS, INTREG, INTREG_UDISP_H, AVR32_V2),
27464 +    SYNTAX_NORMAL2(LD_SHGE, LD_SHGE, LD_SHGE, INTREG, INTREG_UDISP_H, AVR32_V2),
27465 +    SYNTAX_NORMAL2(LD_SHLT, LD_SHLT, LD_SHLT, INTREG, INTREG_UDISP_H, AVR32_V2),
27466 +    SYNTAX_NORMAL2(LD_SHMI, LD_SHMI, LD_SHMI, INTREG, INTREG_UDISP_H, AVR32_V2),
27467 +    SYNTAX_NORMAL2(LD_SHPL, LD_SHPL, LD_SHPL, INTREG, INTREG_UDISP_H, AVR32_V2),
27468 +    SYNTAX_NORMAL2(LD_SHLS, LD_SHLS, LD_SHLS, INTREG, INTREG_UDISP_H, AVR32_V2),
27469 +    SYNTAX_NORMAL2(LD_SHGT, LD_SHGT, LD_SHGT, INTREG, INTREG_UDISP_H, AVR32_V2),
27470 +    SYNTAX_NORMAL2(LD_SHLE, LD_SHLE, LD_SHLE, INTREG, INTREG_UDISP_H, AVR32_V2),
27471 +    SYNTAX_NORMAL2(LD_SHHI, LD_SHHI, LD_SHHI, INTREG, INTREG_UDISP_H, AVR32_V2),
27472 +    SYNTAX_NORMAL2(LD_SHVS, LD_SHVS, LD_SHVS, INTREG, INTREG_UDISP_H, AVR32_V2),
27473 +    SYNTAX_NORMAL2(LD_SHVC, LD_SHVC, LD_SHVC, INTREG, INTREG_UDISP_H, AVR32_V2),
27474 +    SYNTAX_NORMAL2(LD_SHQS, LD_SHQS, LD_SHQS, INTREG, INTREG_UDISP_H, AVR32_V2),
27475 +    SYNTAX_NORMAL2(LD_SHAL, LD_SHAL, LD_SHAL, INTREG, INTREG_UDISP_H, AVR32_V2),
27476 +    SYNTAX_NORMAL2(LD_SHHS, LD_SHHS, LD_SHCC, INTREG, INTREG_UDISP_H, AVR32_V2),
27477 +    SYNTAX_NORMAL2(LD_SHLO, LD_SHLO, LD_SHCS, INTREG, INTREG_UDISP_H, AVR32_V2),
27478 +    SYNTAX_NORMAL2(LD_UHEQ, LD_UHEQ, LD_UHEQ, INTREG, INTREG_UDISP_H, AVR32_V2),
27479 +    SYNTAX_NORMAL2(LD_UHNE, LD_UHNE, LD_UHNE, INTREG, INTREG_UDISP_H, AVR32_V2),
27480 +    SYNTAX_NORMAL2(LD_UHCC, LD_UHCC, LD_UHCC, INTREG, INTREG_UDISP_H, AVR32_V2),
27481 +    SYNTAX_NORMAL2(LD_UHCS, LD_UHCS, LD_UHCS, INTREG, INTREG_UDISP_H, AVR32_V2),
27482 +    SYNTAX_NORMAL2(LD_UHGE, LD_UHGE, LD_UHGE, INTREG, INTREG_UDISP_H, AVR32_V2),
27483 +    SYNTAX_NORMAL2(LD_UHLT, LD_UHLT, LD_UHLT, INTREG, INTREG_UDISP_H, AVR32_V2),
27484 +    SYNTAX_NORMAL2(LD_UHMI, LD_UHMI, LD_UHMI, INTREG, INTREG_UDISP_H, AVR32_V2),
27485 +    SYNTAX_NORMAL2(LD_UHPL, LD_UHPL, LD_UHPL, INTREG, INTREG_UDISP_H, AVR32_V2),
27486 +    SYNTAX_NORMAL2(LD_UHLS, LD_UHLS, LD_UHLS, INTREG, INTREG_UDISP_H, AVR32_V2),
27487 +    SYNTAX_NORMAL2(LD_UHGT, LD_UHGT, LD_UHGT, INTREG, INTREG_UDISP_H, AVR32_V2),
27488 +    SYNTAX_NORMAL2(LD_UHLE, LD_UHLE, LD_UHLE, INTREG, INTREG_UDISP_H, AVR32_V2),
27489 +    SYNTAX_NORMAL2(LD_UHHI, LD_UHHI, LD_UHHI, INTREG, INTREG_UDISP_H, AVR32_V2),
27490 +    SYNTAX_NORMAL2(LD_UHVS, LD_UHVS, LD_UHVS, INTREG, INTREG_UDISP_H, AVR32_V2),
27491 +    SYNTAX_NORMAL2(LD_UHVC, LD_UHVC, LD_UHVC, INTREG, INTREG_UDISP_H, AVR32_V2),
27492 +    SYNTAX_NORMAL2(LD_UHQS, LD_UHQS, LD_UHQS, INTREG, INTREG_UDISP_H, AVR32_V2),
27493 +    SYNTAX_NORMAL2(LD_UHAL, LD_UHAL, LD_UHAL, INTREG, INTREG_UDISP_H, AVR32_V2),
27494 +    SYNTAX_NORMAL2(LD_UHHS, LD_UHHS, LD_UHCC, INTREG, INTREG_UDISP_H, AVR32_V2),
27495 +    SYNTAX_NORMAL2(LD_UHLO, LD_UHLO, LD_UHCS, INTREG, INTREG_UDISP_H, AVR32_V2),
27496 +    SYNTAX_NORMAL2(LD_SBEQ, LD_SBEQ, LD_SBEQ, INTREG, INTREG_UDISP, AVR32_V2),
27497 +    SYNTAX_NORMAL2(LD_SBNE, LD_SBNE, LD_SBNE, INTREG, INTREG_UDISP, AVR32_V2),
27498 +    SYNTAX_NORMAL2(LD_SBCC, LD_SBCC, LD_SBCC, INTREG, INTREG_UDISP, AVR32_V2),
27499 +    SYNTAX_NORMAL2(LD_SBCS, LD_SBCS, LD_SBCS, INTREG, INTREG_UDISP, AVR32_V2),
27500 +    SYNTAX_NORMAL2(LD_SBGE, LD_SBGE, LD_SBGE, INTREG, INTREG_UDISP, AVR32_V2),
27501 +    SYNTAX_NORMAL2(LD_SBLT, LD_SBLT, LD_SBLT, INTREG, INTREG_UDISP, AVR32_V2),
27502 +    SYNTAX_NORMAL2(LD_SBMI, LD_SBMI, LD_SBMI, INTREG, INTREG_UDISP, AVR32_V2),
27503 +    SYNTAX_NORMAL2(LD_SBPL, LD_SBPL, LD_SBPL, INTREG, INTREG_UDISP, AVR32_V2),
27504 +    SYNTAX_NORMAL2(LD_SBLS, LD_SBLS, LD_SBLS, INTREG, INTREG_UDISP, AVR32_V2),
27505 +    SYNTAX_NORMAL2(LD_SBGT, LD_SBGT, LD_SBGT, INTREG, INTREG_UDISP, AVR32_V2),
27506 +    SYNTAX_NORMAL2(LD_SBLE, LD_SBLE, LD_SBLE, INTREG, INTREG_UDISP, AVR32_V2),
27507 +    SYNTAX_NORMAL2(LD_SBHI, LD_SBHI, LD_SBHI, INTREG, INTREG_UDISP, AVR32_V2),
27508 +    SYNTAX_NORMAL2(LD_SBVS, LD_SBVS, LD_SBVS, INTREG, INTREG_UDISP, AVR32_V2),
27509 +    SYNTAX_NORMAL2(LD_SBVC, LD_SBVC, LD_SBVC, INTREG, INTREG_UDISP, AVR32_V2),
27510 +    SYNTAX_NORMAL2(LD_SBQS, LD_SBQS, LD_SBQS, INTREG, INTREG_UDISP, AVR32_V2),
27511 +    SYNTAX_NORMAL2(LD_SBAL, LD_SBAL, LD_SBAL, INTREG, INTREG_UDISP, AVR32_V2),
27512 +    SYNTAX_NORMAL2(LD_SBHS, LD_SBHS, LD_SBCC, INTREG, INTREG_UDISP, AVR32_V2),
27513 +    SYNTAX_NORMAL2(LD_SBLO, LD_SBLO, LD_SBCS, INTREG, INTREG_UDISP, AVR32_V2),
27514 +    SYNTAX_NORMAL2(LD_UBEQ, LD_UBEQ, LD_UBEQ, INTREG, INTREG_UDISP, AVR32_V2),
27515 +    SYNTAX_NORMAL2(LD_UBNE, LD_UBNE, LD_UBNE, INTREG, INTREG_UDISP, AVR32_V2),
27516 +    SYNTAX_NORMAL2(LD_UBCC, LD_UBCC, LD_UBCC, INTREG, INTREG_UDISP, AVR32_V2),
27517 +    SYNTAX_NORMAL2(LD_UBCS, LD_UBCS, LD_UBCS, INTREG, INTREG_UDISP, AVR32_V2),
27518 +    SYNTAX_NORMAL2(LD_UBGE, LD_UBGE, LD_UBGE, INTREG, INTREG_UDISP, AVR32_V2),
27519 +    SYNTAX_NORMAL2(LD_UBLT, LD_UBLT, LD_UBLT, INTREG, INTREG_UDISP, AVR32_V2),
27520 +    SYNTAX_NORMAL2(LD_UBMI, LD_UBMI, LD_UBMI, INTREG, INTREG_UDISP, AVR32_V2),
27521 +    SYNTAX_NORMAL2(LD_UBPL, LD_UBPL, LD_UBPL, INTREG, INTREG_UDISP, AVR32_V2),
27522 +    SYNTAX_NORMAL2(LD_UBLS, LD_UBLS, LD_UBLS, INTREG, INTREG_UDISP, AVR32_V2),
27523 +    SYNTAX_NORMAL2(LD_UBGT, LD_UBGT, LD_UBGT, INTREG, INTREG_UDISP, AVR32_V2),
27524 +    SYNTAX_NORMAL2(LD_UBLE, LD_UBLE, LD_UBLE, INTREG, INTREG_UDISP, AVR32_V2),
27525 +    SYNTAX_NORMAL2(LD_UBHI, LD_UBHI, LD_UBHI, INTREG, INTREG_UDISP, AVR32_V2),
27526 +    SYNTAX_NORMAL2(LD_UBVS, LD_UBVS, LD_UBVS, INTREG, INTREG_UDISP, AVR32_V2),
27527 +    SYNTAX_NORMAL2(LD_UBVC, LD_UBVC, LD_UBVC, INTREG, INTREG_UDISP, AVR32_V2),
27528 +    SYNTAX_NORMAL2(LD_UBQS, LD_UBQS, LD_UBQS, INTREG, INTREG_UDISP, AVR32_V2),
27529 +    SYNTAX_NORMAL2(LD_UBAL, LD_UBAL, LD_UBAL, INTREG, INTREG_UDISP, AVR32_V2),
27530 +    SYNTAX_NORMAL2(LD_UBHS, LD_UBHS, LD_UBCC, INTREG, INTREG_UDISP, AVR32_V2),
27531 +    SYNTAX_NORMAL2(LD_UBLO, LD_UBLO, LD_UBCS, INTREG, INTREG_UDISP, AVR32_V2),
27532 +    SYNTAX_NORMAL2(ST_WEQ, ST_WEQ, ST_WEQ, INTREG_UDISP_W, INTREG, AVR32_V2),
27533 +    SYNTAX_NORMAL2(ST_WNE, ST_WNE, ST_WNE, INTREG_UDISP_W, INTREG, AVR32_V2),
27534 +    SYNTAX_NORMAL2(ST_WCC, ST_WCC, ST_WCC, INTREG_UDISP_W, INTREG, AVR32_V2),
27535 +    SYNTAX_NORMAL2(ST_WCS, ST_WCS, ST_WCS, INTREG_UDISP_W, INTREG, AVR32_V2),
27536 +    SYNTAX_NORMAL2(ST_WGE, ST_WGE, ST_WGE, INTREG_UDISP_W, INTREG, AVR32_V2),
27537 +    SYNTAX_NORMAL2(ST_WLT, ST_WLT, ST_WLT, INTREG_UDISP_W, INTREG, AVR32_V2),
27538 +    SYNTAX_NORMAL2(ST_WMI, ST_WMI, ST_WMI, INTREG_UDISP_W, INTREG, AVR32_V2),
27539 +    SYNTAX_NORMAL2(ST_WPL, ST_WPL, ST_WPL, INTREG_UDISP_W, INTREG, AVR32_V2),
27540 +    SYNTAX_NORMAL2(ST_WLS, ST_WLS, ST_WLS, INTREG_UDISP_W, INTREG, AVR32_V2),
27541 +    SYNTAX_NORMAL2(ST_WGT, ST_WGT, ST_WGT, INTREG_UDISP_W, INTREG, AVR32_V2),
27542 +    SYNTAX_NORMAL2(ST_WLE, ST_WLE, ST_WLE, INTREG_UDISP_W, INTREG, AVR32_V2),
27543 +    SYNTAX_NORMAL2(ST_WHI, ST_WHI, ST_WHI, INTREG_UDISP_W, INTREG, AVR32_V2),
27544 +    SYNTAX_NORMAL2(ST_WVS, ST_WVS, ST_WVS, INTREG_UDISP_W, INTREG, AVR32_V2),
27545 +    SYNTAX_NORMAL2(ST_WVC, ST_WVC, ST_WVC, INTREG_UDISP_W, INTREG, AVR32_V2),
27546 +    SYNTAX_NORMAL2(ST_WQS, ST_WQS, ST_WQS, INTREG_UDISP_W, INTREG, AVR32_V2),
27547 +    SYNTAX_NORMAL2(ST_WAL, ST_WAL, ST_WAL, INTREG_UDISP_W, INTREG, AVR32_V2),
27548 +    SYNTAX_NORMAL2(ST_WHS, ST_WHS, ST_WCC, INTREG_UDISP_W, INTREG, AVR32_V2),
27549 +    SYNTAX_NORMAL2(ST_WLO, ST_WLO, ST_WCS, INTREG_UDISP_W, INTREG, AVR32_V2),
27550 +    SYNTAX_NORMAL2(ST_HEQ, ST_HEQ, ST_HEQ, INTREG_UDISP_H, INTREG, AVR32_V2),
27551 +    SYNTAX_NORMAL2(ST_HNE, ST_HNE, ST_HNE, INTREG_UDISP_H, INTREG, AVR32_V2),
27552 +    SYNTAX_NORMAL2(ST_HCC, ST_HCC, ST_HCC, INTREG_UDISP_H, INTREG, AVR32_V2),
27553 +    SYNTAX_NORMAL2(ST_HCS, ST_HCS, ST_HCS, INTREG_UDISP_H, INTREG, AVR32_V2),
27554 +    SYNTAX_NORMAL2(ST_HGE, ST_HGE, ST_HGE, INTREG_UDISP_H, INTREG, AVR32_V2),
27555 +    SYNTAX_NORMAL2(ST_HLT, ST_HLT, ST_HLT, INTREG_UDISP_H, INTREG, AVR32_V2),
27556 +    SYNTAX_NORMAL2(ST_HMI, ST_HMI, ST_HMI, INTREG_UDISP_H, INTREG, AVR32_V2),
27557 +    SYNTAX_NORMAL2(ST_HPL, ST_HPL, ST_HPL, INTREG_UDISP_H, INTREG, AVR32_V2),
27558 +    SYNTAX_NORMAL2(ST_HLS, ST_HLS, ST_HLS, INTREG_UDISP_H, INTREG, AVR32_V2),
27559 +    SYNTAX_NORMAL2(ST_HGT, ST_HGT, ST_HGT, INTREG_UDISP_H, INTREG, AVR32_V2),
27560 +    SYNTAX_NORMAL2(ST_HLE, ST_HLE, ST_HLE, INTREG_UDISP_H, INTREG, AVR32_V2),
27561 +    SYNTAX_NORMAL2(ST_HHI, ST_HHI, ST_HHI, INTREG_UDISP_H, INTREG, AVR32_V2),
27562 +    SYNTAX_NORMAL2(ST_HVS, ST_HVS, ST_HVS, INTREG_UDISP_H, INTREG, AVR32_V2),
27563 +    SYNTAX_NORMAL2(ST_HVC, ST_HVC, ST_HVC, INTREG_UDISP_H, INTREG, AVR32_V2),
27564 +    SYNTAX_NORMAL2(ST_HQS, ST_HQS, ST_HQS, INTREG_UDISP_H, INTREG, AVR32_V2),
27565 +    SYNTAX_NORMAL2(ST_HAL, ST_HAL, ST_HAL, INTREG_UDISP_H, INTREG, AVR32_V2),
27566 +    SYNTAX_NORMAL2(ST_HHS, ST_HHS, ST_HCC, INTREG_UDISP_H, INTREG, AVR32_V2),
27567 +    SYNTAX_NORMAL2(ST_HLO, ST_HLO, ST_HCS, INTREG_UDISP_H, INTREG, AVR32_V2),
27568 +    SYNTAX_NORMAL2(ST_BEQ, ST_BEQ, ST_BEQ, INTREG_UDISP, INTREG, AVR32_V2),
27569 +    SYNTAX_NORMAL2(ST_BNE, ST_BNE, ST_BNE, INTREG_UDISP, INTREG, AVR32_V2),
27570 +    SYNTAX_NORMAL2(ST_BCC, ST_BCC, ST_BCC, INTREG_UDISP, INTREG, AVR32_V2),
27571 +    SYNTAX_NORMAL2(ST_BCS, ST_BCS, ST_BCS, INTREG_UDISP, INTREG, AVR32_V2),
27572 +    SYNTAX_NORMAL2(ST_BGE, ST_BGE, ST_BGE, INTREG_UDISP, INTREG, AVR32_V2),
27573 +    SYNTAX_NORMAL2(ST_BLT, ST_BLT, ST_BLT, INTREG_UDISP, INTREG, AVR32_V2),
27574 +    SYNTAX_NORMAL2(ST_BMI, ST_BMI, ST_BMI, INTREG_UDISP, INTREG, AVR32_V2),
27575 +    SYNTAX_NORMAL2(ST_BPL, ST_BPL, ST_BPL, INTREG_UDISP, INTREG, AVR32_V2),
27576 +    SYNTAX_NORMAL2(ST_BLS, ST_BLS, ST_BLS, INTREG_UDISP, INTREG, AVR32_V2),
27577 +    SYNTAX_NORMAL2(ST_BGT, ST_BGT, ST_BGT, INTREG_UDISP, INTREG, AVR32_V2),
27578 +    SYNTAX_NORMAL2(ST_BLE, ST_BLE, ST_BLE, INTREG_UDISP, INTREG, AVR32_V2),
27579 +    SYNTAX_NORMAL2(ST_BHI, ST_BHI, ST_BHI, INTREG_UDISP, INTREG, AVR32_V2),
27580 +    SYNTAX_NORMAL2(ST_BVS, ST_BVS, ST_BVS, INTREG_UDISP, INTREG, AVR32_V2),
27581 +    SYNTAX_NORMAL2(ST_BVC, ST_BVC, ST_BVC, INTREG_UDISP, INTREG, AVR32_V2),
27582 +    SYNTAX_NORMAL2(ST_BQS, ST_BQS, ST_BQS, INTREG_UDISP, INTREG, AVR32_V2),
27583 +    SYNTAX_NORMAL2(ST_BAL, ST_BAL, ST_BAL, INTREG_UDISP, INTREG, AVR32_V2),
27584 +    SYNTAX_NORMAL2(ST_BHS, ST_BHS, ST_BCC, INTREG_UDISP, INTREG, AVR32_V2),
27585 +    SYNTAX_NORMAL2(ST_BLO, ST_BLO, ST_BCS, INTREG_UDISP, INTREG, AVR32_V2),
27586 +    SYNTAX_NORMAL2(MOVH, MOVH, MOVH, INTREG, UNSIGNED_CONST, AVR32_V2),
27587 +
27588 +  };
27589 +
27590 +#define NORMAL_MNEMONIC(name, syntax, str)             \
27591 +  {                                                    \
27592 +    AVR32_MNEMONIC_##name, str,                                \
27593 +    &avr32_syntax_table[AVR32_SYNTAX_##syntax],                \
27594 +  }
27595 +#define FP_MNEMONIC(name, syntax, str)                 \
27596 +  NORMAL_MNEMONIC(name##_S, syntax##_S, str ".s"),     \
27597 +  NORMAL_MNEMONIC(name##_D, syntax##_D, str ".d")
27598 +
27599 +const struct avr32_mnemonic avr32_mnemonic_table[] =
27600 +  {
27601 +    NORMAL_MNEMONIC(ABS, ABS, "abs"),
27602 +    NORMAL_MNEMONIC(ACALL, ACALL, "acall"),
27603 +    NORMAL_MNEMONIC(ACR, ACR, "acr"),
27604 +    NORMAL_MNEMONIC(ADC, ADC, "adc"),
27605 +    NORMAL_MNEMONIC(ADD, ADD1, "add"),
27606 +    NORMAL_MNEMONIC(ADDABS, ADDABS, "addabs"),
27607 +    NORMAL_MNEMONIC(ADDHH_W, ADDHH_W, "addhh.w"),
27608 +    NORMAL_MNEMONIC(AND, AND1, "and"),
27609 +    NORMAL_MNEMONIC(ANDH, ANDH, "andh"),
27610 +    NORMAL_MNEMONIC(ANDL, ANDL, "andl"),
27611 +    NORMAL_MNEMONIC(ANDN, ANDN, "andn"),
27612 +    NORMAL_MNEMONIC(ASR, ASR1, "asr"),
27613 +    NORMAL_MNEMONIC(BFEXTS, BFEXTS, "bfexts"),
27614 +    NORMAL_MNEMONIC(BFEXTU, BFEXTU, "bfextu"),
27615 +    NORMAL_MNEMONIC(BFINS, BFINS, "bfins"),
27616 +    NORMAL_MNEMONIC(BLD, BLD, "bld"),
27617 +    NORMAL_MNEMONIC(BREQ, BREQ1, "breq"),
27618 +    NORMAL_MNEMONIC(BRNE, BRNE1, "brne"),
27619 +    NORMAL_MNEMONIC(BRCC, BRCC1, "brcc"),
27620 +    NORMAL_MNEMONIC(BRCS, BRCS1, "brcs"),
27621 +    NORMAL_MNEMONIC(BRGE, BRGE1, "brge"),
27622 +    NORMAL_MNEMONIC(BRLT, BRLT1, "brlt"),
27623 +    NORMAL_MNEMONIC(BRMI, BRMI1, "brmi"),
27624 +    NORMAL_MNEMONIC(BRPL, BRPL1, "brpl"),
27625 +    NORMAL_MNEMONIC(BRHS, BRHS1, "brhs"),
27626 +    NORMAL_MNEMONIC(BRLO, BRLO1, "brlo"),
27627 +    NORMAL_MNEMONIC(BRLS, BRLS, "brls"),
27628 +    NORMAL_MNEMONIC(BRGT, BRGT, "brgt"),
27629 +    NORMAL_MNEMONIC(BRLE, BRLE, "brle"),
27630 +    NORMAL_MNEMONIC(BRHI, BRHI, "brhi"),
27631 +    NORMAL_MNEMONIC(BRVS, BRVS, "brvs"),
27632 +    NORMAL_MNEMONIC(BRVC, BRVC, "brvc"),
27633 +    NORMAL_MNEMONIC(BRQS, BRQS, "brqs"),
27634 +    NORMAL_MNEMONIC(BRAL, BRAL, "bral"),
27635 +    NORMAL_MNEMONIC(BREAKPOINT, BREAKPOINT, "breakpoint"),
27636 +    NORMAL_MNEMONIC(BREV, BREV, "brev"),
27637 +    NORMAL_MNEMONIC(BST, BST, "bst"),
27638 +    NORMAL_MNEMONIC(CACHE, CACHE, "cache"),
27639 +    NORMAL_MNEMONIC(CASTS_B, CASTS_B, "casts.b"),
27640 +    NORMAL_MNEMONIC(CASTS_H, CASTS_H, "casts.h"),
27641 +    NORMAL_MNEMONIC(CASTU_B, CASTU_B, "castu.b"),
27642 +    NORMAL_MNEMONIC(CASTU_H, CASTU_H, "castu.h"),
27643 +    NORMAL_MNEMONIC(CBR, CBR, "cbr"),
27644 +    NORMAL_MNEMONIC(CLZ, CLZ, "clz"),
27645 +    NORMAL_MNEMONIC(COM, COM, "com"),
27646 +    NORMAL_MNEMONIC(COP, COP, "cop"),
27647 +    NORMAL_MNEMONIC(CP_B, CP_B, "cp.b"),
27648 +    NORMAL_MNEMONIC(CP_H, CP_H, "cp.h"),
27649 +    NORMAL_MNEMONIC(CP_W, CP_W1, "cp.w"),
27650 +    NORMAL_MNEMONIC(CP, CP_W1, "cp"),
27651 +    NORMAL_MNEMONIC(CPC, CPC1, "cpc"),
27652 +    NORMAL_MNEMONIC(CSRF, CSRF, "csrf"),
27653 +    NORMAL_MNEMONIC(CSRFCZ, CSRFCZ, "csrfcz"),
27654 +    NORMAL_MNEMONIC(DIVS, DIVS, "divs"),
27655 +    NORMAL_MNEMONIC(DIVU, DIVU, "divu"),
27656 +    NORMAL_MNEMONIC(EOR, EOR1, "eor"),
27657 +    NORMAL_MNEMONIC(EORL, EORL, "eorl"),
27658 +    NORMAL_MNEMONIC(EORH, EORH, "eorh"),
27659 +    NORMAL_MNEMONIC(FRS, FRS, "frs"),
27660 +    NORMAL_MNEMONIC(SSCALL, SSCALL, "sscall"),
27661 +    NORMAL_MNEMONIC(RETSS, RETSS, "retss"),
27662 +    NORMAL_MNEMONIC(ICALL, ICALL, "icall"),
27663 +    NORMAL_MNEMONIC(INCJOSP, INCJOSP, "incjosp"),
27664 +    NORMAL_MNEMONIC(LD_D, LD_D1, "ld.d"),
27665 +    NORMAL_MNEMONIC(LD_SB, LD_SB2, "ld.sb"),
27666 +    NORMAL_MNEMONIC(LD_UB, LD_UB1, "ld.ub"),
27667 +    NORMAL_MNEMONIC(LD_SH, LD_SH1, "ld.sh"),
27668 +    NORMAL_MNEMONIC(LD_UH, LD_UH1, "ld.uh"),
27669 +    NORMAL_MNEMONIC(LD_W, LD_W1, "ld.w"),
27670 +    NORMAL_MNEMONIC(LDC_D, LDC_D3, "ldc.d"),
27671 +    NORMAL_MNEMONIC(LDC_W, LDC_W3, "ldc.w"),
27672 +    NORMAL_MNEMONIC(LDC0_D, LDC0_D, "ldc0.d"),
27673 +    NORMAL_MNEMONIC(LDC0_W, LDC0_W, "ldc0.w"),
27674 +    NORMAL_MNEMONIC(LDCM_D, LDCM_D, "ldcm.d"),
27675 +    NORMAL_MNEMONIC(LDCM_W, LDCM_W, "ldcm.w"),
27676 +    NORMAL_MNEMONIC(LDDPC, LDDPC, "lddpc"),
27677 +    NORMAL_MNEMONIC(LDDSP, LDDSP, "lddsp"),
27678 +    NORMAL_MNEMONIC(LDINS_B, LDINS_B, "ldins.b"),
27679 +    NORMAL_MNEMONIC(LDINS_H, LDINS_H, "ldins.h"),
27680 +    NORMAL_MNEMONIC(LDM, LDM, "ldm"),
27681 +    NORMAL_MNEMONIC(LDMTS, LDMTS, "ldmts"),
27682 +    NORMAL_MNEMONIC(LDSWP_SH, LDSWP_SH, "ldswp.sh"),
27683 +    NORMAL_MNEMONIC(LDSWP_UH, LDSWP_UH, "ldswp.uh"),
27684 +    NORMAL_MNEMONIC(LDSWP_W, LDSWP_W, "ldswp.w"),
27685 +    NORMAL_MNEMONIC(LSL, LSL1, "lsl"),
27686 +    NORMAL_MNEMONIC(LSR, LSR1, "lsr"),
27687 +    NORMAL_MNEMONIC(MAC, MAC, "mac"),
27688 +    NORMAL_MNEMONIC(MACHH_D, MACHH_D, "machh.d"),
27689 +    NORMAL_MNEMONIC(MACHH_W, MACHH_W, "machh.w"),
27690 +    NORMAL_MNEMONIC(MACS_D, MACS_D, "macs.d"),
27691 +    NORMAL_MNEMONIC(MACSATHH_W, MACSATHH_W, "macsathh.w"),
27692 +    NORMAL_MNEMONIC(MACU_D, MACUD, "macu.d"),
27693 +    NORMAL_MNEMONIC(MACWH_D, MACWH_D, "macwh.d"),
27694 +    NORMAL_MNEMONIC(MAX, MAX, "max"),
27695 +    NORMAL_MNEMONIC(MCALL, MCALL, "mcall"),
27696 +    NORMAL_MNEMONIC(MFDR, MFDR, "mfdr"),
27697 +    NORMAL_MNEMONIC(MFSR, MFSR, "mfsr"),
27698 +    NORMAL_MNEMONIC(MIN, MIN, "min"),
27699 +    NORMAL_MNEMONIC(MOV, MOV3, "mov"),
27700 +    NORMAL_MNEMONIC(MOVEQ, MOVEQ1, "moveq"),
27701 +    NORMAL_MNEMONIC(MOVNE, MOVNE1, "movne"),
27702 +    NORMAL_MNEMONIC(MOVCC, MOVCC1, "movcc"),
27703 +    NORMAL_MNEMONIC(MOVCS, MOVCS1, "movcs"),
27704 +    NORMAL_MNEMONIC(MOVGE, MOVGE1, "movge"),
27705 +    NORMAL_MNEMONIC(MOVLT, MOVLT1, "movlt"),
27706 +    NORMAL_MNEMONIC(MOVMI, MOVMI1, "movmi"),
27707 +    NORMAL_MNEMONIC(MOVPL, MOVPL1, "movpl"),
27708 +    NORMAL_MNEMONIC(MOVLS, MOVLS1, "movls"),
27709 +    NORMAL_MNEMONIC(MOVGT, MOVGT1, "movgt"),
27710 +    NORMAL_MNEMONIC(MOVLE, MOVLE1, "movle"),
27711 +    NORMAL_MNEMONIC(MOVHI, MOVHI1, "movhi"),
27712 +    NORMAL_MNEMONIC(MOVVS, MOVVS1, "movvs"),
27713 +    NORMAL_MNEMONIC(MOVVC, MOVVC1, "movvc"),
27714 +    NORMAL_MNEMONIC(MOVQS, MOVQS1, "movqs"),
27715 +    NORMAL_MNEMONIC(MOVAL, MOVAL1, "moval"),
27716 +    NORMAL_MNEMONIC(MOVHS, MOVHS1, "movhs"),
27717 +    NORMAL_MNEMONIC(MOVLO, MOVLO1, "movlo"),
27718 +    NORMAL_MNEMONIC(MTDR, MTDR, "mtdr"),
27719 +    NORMAL_MNEMONIC(MTSR, MTSR, "mtsr"),
27720 +    NORMAL_MNEMONIC(MUL, MUL1, "mul"),
27721 +    NORMAL_MNEMONIC(MULHH_W, MULHH_W, "mulhh.w"),
27722 +    NORMAL_MNEMONIC(MULNHH_W, MULNHH_W, "mulnhh.w"),
27723 +    NORMAL_MNEMONIC(MULNWH_D, MULNWH_D, "mulnwh.d"),
27724 +    NORMAL_MNEMONIC(MULS_D, MULSD, "muls.d"),
27725 +    NORMAL_MNEMONIC(MULSATHH_H, MULSATHH_H, "mulsathh.h"),
27726 +    NORMAL_MNEMONIC(MULSATHH_W, MULSATHH_W, "mulsathh.w"),
27727 +    NORMAL_MNEMONIC(MULSATRNDHH_H, MULSATRNDHH_H, "mulsatrndhh.h"),
27728 +    NORMAL_MNEMONIC(MULSATRNDWH_W, MULSATRNDWH_W, "mulsatrndwh.w"),
27729 +    NORMAL_MNEMONIC(MULSATWH_W, MULSATWH_W, "mulsatwh.w"),
27730 +    NORMAL_MNEMONIC(MULU_D, MULU_D, "mulu.d"),
27731 +    NORMAL_MNEMONIC(MULWH_D, MULWH_D, "mulwh.d"),
27732 +    NORMAL_MNEMONIC(MUSFR, MUSFR, "musfr"),
27733 +    NORMAL_MNEMONIC(MUSTR, MUSTR, "mustr"),
27734 +    NORMAL_MNEMONIC(MVCR_D, MVCR_D, "mvcr.d"),
27735 +    NORMAL_MNEMONIC(MVCR_W, MVCR_W, "mvcr.w"),
27736 +    NORMAL_MNEMONIC(MVRC_D, MVRC_D, "mvrc.d"),
27737 +    NORMAL_MNEMONIC(MVRC_W, MVRC_W, "mvrc.w"),
27738 +    NORMAL_MNEMONIC(NEG, NEG, "neg"),
27739 +    NORMAL_MNEMONIC(NOP, NOP, "nop"),
27740 +    NORMAL_MNEMONIC(OR, OR1, "or"),
27741 +    NORMAL_MNEMONIC(ORH, ORH, "orh"),
27742 +    NORMAL_MNEMONIC(ORL, ORL, "orl"),
27743 +    NORMAL_MNEMONIC(PABS_SB, PABS_SB, "pabs.sb"),
27744 +    NORMAL_MNEMONIC(PABS_SH, PABS_SH, "pabs.sh"),
27745 +    NORMAL_MNEMONIC(PACKSH_SB, PACKSH_SB, "packsh.sb"),
27746 +    NORMAL_MNEMONIC(PACKSH_UB, PACKSH_UB, "packsh.ub"),
27747 +    NORMAL_MNEMONIC(PACKW_SH, PACKW_SH, "packw.sh"),
27748 +    NORMAL_MNEMONIC(PADD_B, PADD_B, "padd.b"),
27749 +    NORMAL_MNEMONIC(PADD_H, PADD_H, "padd.h"),
27750 +    NORMAL_MNEMONIC(PADDH_SH, PADDH_SH, "paddh.sh"),
27751 +    NORMAL_MNEMONIC(PADDH_UB, PADDH_UB, "paddh.ub"),
27752 +    NORMAL_MNEMONIC(PADDS_SB, PADDS_SB, "padds.sb"),
27753 +    NORMAL_MNEMONIC(PADDS_SH, PADDS_SH, "padds.sh"),
27754 +    NORMAL_MNEMONIC(PADDS_UB, PADDS_UB, "padds.ub"),
27755 +    NORMAL_MNEMONIC(PADDS_UH, PADDS_UH, "padds.uh"),
27756 +    NORMAL_MNEMONIC(PADDSUB_H, PADDSUB_H, "paddsub.h"),
27757 +    NORMAL_MNEMONIC(PADDSUBH_SH, PADDSUBH_SH, "paddsubh.sh"),
27758 +    NORMAL_MNEMONIC(PADDSUBS_SH, PADDSUBS_SH, "paddsubs.sh"),
27759 +    NORMAL_MNEMONIC(PADDSUBS_UH, PADDSUBS_UH, "paddsubs.uh"),
27760 +    NORMAL_MNEMONIC(PADDX_H, PADDX_H, "paddx.h"),
27761 +    NORMAL_MNEMONIC(PADDXH_SH, PADDXH_SH, "paddxh.sh"),
27762 +    NORMAL_MNEMONIC(PADDXS_SH, PADDXS_SH, "paddxs.sh"),
27763 +    NORMAL_MNEMONIC(PADDXS_UH, PADDXS_UH, "paddxs.uh"),
27764 +    NORMAL_MNEMONIC(PASR_B, PASR_B, "pasr.b"),
27765 +    NORMAL_MNEMONIC(PASR_H, PASR_H, "pasr.h"),
27766 +    NORMAL_MNEMONIC(PAVG_SH, PAVG_SH, "pavg.sh"),
27767 +    NORMAL_MNEMONIC(PAVG_UB, PAVG_UB, "pavg.ub"),
27768 +    NORMAL_MNEMONIC(PLSL_B, PLSL_B, "plsl.b"),
27769 +    NORMAL_MNEMONIC(PLSL_H, PLSL_H, "plsl.h"),
27770 +    NORMAL_MNEMONIC(PLSR_B, PLSR_B, "plsr.b"),
27771 +    NORMAL_MNEMONIC(PLSR_H, PLSR_H, "plsr.h"),
27772 +    NORMAL_MNEMONIC(PMAX_SH, PMAX_SH, "pmax.sh"),
27773 +    NORMAL_MNEMONIC(PMAX_UB, PMAX_UB, "pmax.ub"),
27774 +    NORMAL_MNEMONIC(PMIN_SH, PMIN_SH, "pmin.sh"),
27775 +    NORMAL_MNEMONIC(PMIN_UB, PMIN_UB, "pmin.ub"),
27776 +    NORMAL_MNEMONIC(POPJC, POPJC, "popjc"),
27777 +    NORMAL_MNEMONIC(POPM, POPM, "popm"),
27778 +    NORMAL_MNEMONIC(PREF, PREF, "pref"),
27779 +    NORMAL_MNEMONIC(PSAD, PSAD, "psad"),
27780 +    NORMAL_MNEMONIC(PSUB_B, PSUB_B, "psub.b"),
27781 +    NORMAL_MNEMONIC(PSUB_H, PSUB_H, "psub.h"),
27782 +    NORMAL_MNEMONIC(PSUBADD_H, PSUBADD_H, "psubadd.h"),
27783 +    NORMAL_MNEMONIC(PSUBADDH_SH, PSUBADDH_SH, "psubaddh.sh"),
27784 +    NORMAL_MNEMONIC(PSUBADDS_SH, PSUBADDS_SH, "psubadds.sh"),
27785 +    NORMAL_MNEMONIC(PSUBADDS_UH, PSUBADDS_UH, "psubadds.uh"),
27786 +    NORMAL_MNEMONIC(PSUBH_SH, PSUBH_SH, "psubh.sh"),
27787 +    NORMAL_MNEMONIC(PSUBH_UB, PSUBH_UB, "psubh.ub"),
27788 +    NORMAL_MNEMONIC(PSUBS_SB, PSUBS_SB, "psubs.sb"),
27789 +    NORMAL_MNEMONIC(PSUBS_SH, PSUBS_SH, "psubs.sh"),
27790 +    NORMAL_MNEMONIC(PSUBS_UB, PSUBS_UB, "psubs.ub"),
27791 +    NORMAL_MNEMONIC(PSUBS_UH, PSUBS_UH, "psubs.uh"),
27792 +    NORMAL_MNEMONIC(PSUBX_H, PSUBX_H, "psubx.h"),
27793 +    NORMAL_MNEMONIC(PSUBXH_SH, PSUBXH_SH, "psubxh.sh"),
27794 +    NORMAL_MNEMONIC(PSUBXS_SH, PSUBXS_SH, "psubxs.sh"),
27795 +    NORMAL_MNEMONIC(PSUBXS_UH, PSUBXS_UH, "psubxs.uh"),
27796 +    NORMAL_MNEMONIC(PUNPCKSB_H, PUNPCKSB_H, "punpcksb.h"),
27797 +    NORMAL_MNEMONIC(PUNPCKUB_H, PUNPCKUB_H, "punpckub.h"),
27798 +    NORMAL_MNEMONIC(PUSHJC, PUSHJC, "pushjc"),
27799 +    NORMAL_MNEMONIC(PUSHM, PUSHM, "pushm"),
27800 +    NORMAL_MNEMONIC(RCALL, RCALL1, "rcall"),
27801 +    NORMAL_MNEMONIC(RETEQ, RETEQ, "reteq"),
27802 +    NORMAL_MNEMONIC(RETNE, RETNE, "retne"),
27803 +    NORMAL_MNEMONIC(RETCC, RETCC, "retcc"),
27804 +    NORMAL_MNEMONIC(RETCS, RETCS, "retcs"),
27805 +    NORMAL_MNEMONIC(RETGE, RETGE, "retge"),
27806 +    NORMAL_MNEMONIC(RETLT, RETLT, "retlt"),
27807 +    NORMAL_MNEMONIC(RETMI, RETMI, "retmi"),
27808 +    NORMAL_MNEMONIC(RETPL, RETPL, "retpl"),
27809 +    NORMAL_MNEMONIC(RETLS, RETLS, "retls"),
27810 +    NORMAL_MNEMONIC(RETGT, RETGT, "retgt"),
27811 +    NORMAL_MNEMONIC(RETLE, RETLE, "retle"),
27812 +    NORMAL_MNEMONIC(RETHI, RETHI, "rethi"),
27813 +    NORMAL_MNEMONIC(RETVS, RETVS, "retvs"),
27814 +    NORMAL_MNEMONIC(RETVC, RETVC, "retvc"),
27815 +    NORMAL_MNEMONIC(RETQS, RETQS, "retqs"),
27816 +    NORMAL_MNEMONIC(RETAL, RETAL, "retal"),
27817 +    NORMAL_MNEMONIC(RETHS, RETHS, "reths"),
27818 +    NORMAL_MNEMONIC(RETLO, RETLO, "retlo"),
27819 +    NORMAL_MNEMONIC(RET, RETAL, "ret"),
27820 +    NORMAL_MNEMONIC(RETD, RETD, "retd"),
27821 +    NORMAL_MNEMONIC(RETE, RETE, "rete"),
27822 +    NORMAL_MNEMONIC(RETJ, RETJ, "retj"),
27823 +    NORMAL_MNEMONIC(RETS, RETS, "rets"),
27824 +    NORMAL_MNEMONIC(RJMP, RJMP, "rjmp"),
27825 +    NORMAL_MNEMONIC(ROL, ROL, "rol"),
27826 +    NORMAL_MNEMONIC(ROR, ROR, "ror"),
27827 +    NORMAL_MNEMONIC(RSUB, RSUB1, "rsub"),
27828 +    NORMAL_MNEMONIC(SATADD_H, SATADD_H, "satadd.h"),
27829 +    NORMAL_MNEMONIC(SATADD_W, SATADD_W, "satadd.w"),
27830 +    NORMAL_MNEMONIC(SATRNDS, SATRNDS, "satrnds"),
27831 +    NORMAL_MNEMONIC(SATRNDU, SATRNDU, "satrndu"),
27832 +    NORMAL_MNEMONIC(SATS, SATS, "sats"),
27833 +    NORMAL_MNEMONIC(SATSUB_H, SATSUB_H, "satsub.h"),
27834 +    NORMAL_MNEMONIC(SATSUB_W, SATSUB_W1, "satsub.w"),
27835 +    NORMAL_MNEMONIC(SATU, SATU, "satu"),
27836 +    NORMAL_MNEMONIC(SBC, SBC, "sbc"),
27837 +    NORMAL_MNEMONIC(SBR, SBR, "sbr"),
27838 +    NORMAL_MNEMONIC(SCALL, SCALL, "scall"),
27839 +    NORMAL_MNEMONIC(SCR, SCR, "scr"),
27840 +    NORMAL_MNEMONIC(SLEEP, SLEEP, "sleep"),
27841 +    NORMAL_MNEMONIC(SREQ, SREQ, "sreq"),
27842 +    NORMAL_MNEMONIC(SRNE, SRNE, "srne"),
27843 +    NORMAL_MNEMONIC(SRCC, SRCC, "srcc"),
27844 +    NORMAL_MNEMONIC(SRCS, SRCS, "srcs"),
27845 +    NORMAL_MNEMONIC(SRGE, SRGE, "srge"),
27846 +    NORMAL_MNEMONIC(SRLT, SRLT, "srlt"),
27847 +    NORMAL_MNEMONIC(SRMI, SRMI, "srmi"),
27848 +    NORMAL_MNEMONIC(SRPL, SRPL, "srpl"),
27849 +    NORMAL_MNEMONIC(SRLS, SRLS, "srls"),
27850 +    NORMAL_MNEMONIC(SRGT, SRGT, "srgt"),
27851 +    NORMAL_MNEMONIC(SRLE, SRLE, "srle"),
27852 +    NORMAL_MNEMONIC(SRHI, SRHI, "srhi"),
27853 +    NORMAL_MNEMONIC(SRVS, SRVS, "srvs"),
27854 +    NORMAL_MNEMONIC(SRVC, SRVC, "srvc"),
27855 +    NORMAL_MNEMONIC(SRQS, SRQS, "srqs"),
27856 +    NORMAL_MNEMONIC(SRAL, SRAL, "sral"),
27857 +    NORMAL_MNEMONIC(SRHS, SRHS, "srhs"),
27858 +    NORMAL_MNEMONIC(SRLO, SRLO, "srlo"),
27859 +    NORMAL_MNEMONIC(SSRF, SSRF, "ssrf"),
27860 +    NORMAL_MNEMONIC(ST_B, ST_B1, "st.b"),
27861 +    NORMAL_MNEMONIC(ST_D, ST_D1, "st.d"),
27862 +    NORMAL_MNEMONIC(ST_H, ST_H1, "st.h"),
27863 +    NORMAL_MNEMONIC(ST_W, ST_W1, "st.w"),
27864 +    NORMAL_MNEMONIC(STC_D, STC_D3, "stc.d"),
27865 +    NORMAL_MNEMONIC(STC_W, STC_W3, "stc.w"),
27866 +    NORMAL_MNEMONIC(STC0_D, STC0_D, "stc0.d"),
27867 +    NORMAL_MNEMONIC(STC0_W, STC0_W, "stc0.w"),
27868 +    NORMAL_MNEMONIC(STCM_D, STCM_D, "stcm.d"),
27869 +    NORMAL_MNEMONIC(STCM_W, STCM_W, "stcm.w"),
27870 +    NORMAL_MNEMONIC(STCOND, STCOND, "stcond"),
27871 +    NORMAL_MNEMONIC(STDSP, STDSP, "stdsp"),
27872 +    NORMAL_MNEMONIC(STHH_W, STHH_W2, "sthh.w"),
27873 +    NORMAL_MNEMONIC(STM, STM, "stm"),
27874 +    NORMAL_MNEMONIC(STMTS, STMTS, "stmts"),
27875 +    NORMAL_MNEMONIC(STSWP_H, STSWP_H, "stswp.h"),
27876 +    NORMAL_MNEMONIC(STSWP_W, STSWP_W, "stswp.w"),
27877 +    NORMAL_MNEMONIC(SUB, SUB1, "sub"),
27878 +    NORMAL_MNEMONIC(SUBEQ, SUBEQ, "subeq"),
27879 +    NORMAL_MNEMONIC(SUBNE, SUBNE, "subne"),
27880 +    NORMAL_MNEMONIC(SUBCC, SUBCC, "subcc"),
27881 +    NORMAL_MNEMONIC(SUBCS, SUBCS, "subcs"),
27882 +    NORMAL_MNEMONIC(SUBGE, SUBGE, "subge"),
27883 +    NORMAL_MNEMONIC(SUBLT, SUBLT, "sublt"),
27884 +    NORMAL_MNEMONIC(SUBMI, SUBMI, "submi"),
27885 +    NORMAL_MNEMONIC(SUBPL, SUBPL, "subpl"),
27886 +    NORMAL_MNEMONIC(SUBLS, SUBLS, "subls"),
27887 +    NORMAL_MNEMONIC(SUBGT, SUBGT, "subgt"),
27888 +    NORMAL_MNEMONIC(SUBLE, SUBLE, "suble"),
27889 +    NORMAL_MNEMONIC(SUBHI, SUBHI, "subhi"),
27890 +    NORMAL_MNEMONIC(SUBVS, SUBVS, "subvs"),
27891 +    NORMAL_MNEMONIC(SUBVC, SUBVC, "subvc"),
27892 +    NORMAL_MNEMONIC(SUBQS, SUBQS, "subqs"),
27893 +    NORMAL_MNEMONIC(SUBAL, SUBAL, "subal"),
27894 +    NORMAL_MNEMONIC(SUBHS, SUBHS, "subhs"),
27895 +    NORMAL_MNEMONIC(SUBLO, SUBLO, "sublo"),
27896 +    NORMAL_MNEMONIC(SUBFEQ, SUBFEQ, "subfeq"),
27897 +    NORMAL_MNEMONIC(SUBFNE, SUBFNE, "subfne"),
27898 +    NORMAL_MNEMONIC(SUBFCC, SUBFCC, "subfcc"),
27899 +    NORMAL_MNEMONIC(SUBFCS, SUBFCS, "subfcs"),
27900 +    NORMAL_MNEMONIC(SUBFGE, SUBFGE, "subfge"),
27901 +    NORMAL_MNEMONIC(SUBFLT, SUBFLT, "subflt"),
27902 +    NORMAL_MNEMONIC(SUBFMI, SUBFMI, "subfmi"),
27903 +    NORMAL_MNEMONIC(SUBFPL, SUBFPL, "subfpl"),
27904 +    NORMAL_MNEMONIC(SUBFLS, SUBFLS, "subfls"),
27905 +    NORMAL_MNEMONIC(SUBFGT, SUBFGT, "subfgt"),
27906 +    NORMAL_MNEMONIC(SUBFLE, SUBFLE, "subfle"),
27907 +    NORMAL_MNEMONIC(SUBFHI, SUBFHI, "subfhi"),
27908 +    NORMAL_MNEMONIC(SUBFVS, SUBFVS, "subfvs"),
27909 +    NORMAL_MNEMONIC(SUBFVC, SUBFVC, "subfvc"),
27910 +    NORMAL_MNEMONIC(SUBFQS, SUBFQS, "subfqs"),
27911 +    NORMAL_MNEMONIC(SUBFAL, SUBFAL, "subfal"),
27912 +    NORMAL_MNEMONIC(SUBFHS, SUBFHS, "subfhs"),
27913 +    NORMAL_MNEMONIC(SUBFLO, SUBFLO, "subflo"),
27914 +    NORMAL_MNEMONIC(SUBHH_W, SUBHH_W, "subhh.w"),
27915 +    NORMAL_MNEMONIC(SWAP_B, SWAP_B, "swap.b"),
27916 +    NORMAL_MNEMONIC(SWAP_BH, SWAP_BH, "swap.bh"),
27917 +    NORMAL_MNEMONIC(SWAP_H, SWAP_H, "swap.h"),
27918 +    NORMAL_MNEMONIC(SYNC, SYNC, "sync"),
27919 +    NORMAL_MNEMONIC(TLBR, TLBR, "tlbr"),
27920 +    NORMAL_MNEMONIC(TLBS, TLBS, "tlbs"),
27921 +    NORMAL_MNEMONIC(TLBW, TLBW, "tlbw"),
27922 +    NORMAL_MNEMONIC(TNBZ, TNBZ, "tnbz"),
27923 +    NORMAL_MNEMONIC(TST, TST, "tst"),
27924 +    NORMAL_MNEMONIC(XCHG, XCHG, "xchg"),
27925 +    NORMAL_MNEMONIC(MEMC, MEMC, "memc"),
27926 +    NORMAL_MNEMONIC(MEMS, MEMS, "mems"),
27927 +    NORMAL_MNEMONIC(MEMT, MEMT, "memt"),
27928 +    FP_MNEMONIC(FADD, FADD, "fadd"),
27929 +    FP_MNEMONIC(FSUB, FSUB, "fsub"),
27930 +    FP_MNEMONIC(FMAC, FMAC, "fmac"),
27931 +    FP_MNEMONIC(FNMAC, FNMAC, "fnmac"),
27932 +    FP_MNEMONIC(FMSC, FMSC, "fmsc"),
27933 +    FP_MNEMONIC(FNMSC, FNMSC, "fnmsc"),
27934 +    FP_MNEMONIC(FMUL, FMUL, "fmul"),
27935 +    FP_MNEMONIC(FNMUL, FNMUL, "fnmul"),
27936 +    FP_MNEMONIC(FNEG, FNEG, "fneg"),
27937 +    FP_MNEMONIC(FABS, FABS, "fabs"),
27938 +    FP_MNEMONIC(FCMP, FCMP, "fcmp"),
27939 +    FP_MNEMONIC(FMOV, FMOV1, "fmov"),
27940 +    NORMAL_MNEMONIC(FCASTS_D, FCASTS_D, "fcasts.d"),
27941 +    NORMAL_MNEMONIC(FCASTD_S, FCASTD_S, "fcastd.s"),
27942 +    NORMAL_MNEMONIC(LDA_W, LDA_W, "lda.w"),
27943 +    NORMAL_MNEMONIC(CALL, CALL, "call"),
27944 +    NORMAL_MNEMONIC(PICOSVMAC, PICOSVMAC0, "picosvmac"),
27945 +    NORMAL_MNEMONIC(PICOSVMUL, PICOSVMUL0, "picosvmul"),
27946 +    NORMAL_MNEMONIC(PICOVMAC, PICOVMAC0, "picovmac"),
27947 +    NORMAL_MNEMONIC(PICOVMUL, PICOVMUL0, "picovmul"),
27948 +    NORMAL_MNEMONIC(PICOLD_D, PICOLD_D2, "picold.d"),
27949 +    NORMAL_MNEMONIC(PICOLD_W, PICOLD_W2, "picold.w"),
27950 +    NORMAL_MNEMONIC(PICOLDM_D, PICOLDM_D, "picoldm.d"),
27951 +    NORMAL_MNEMONIC(PICOLDM_W, PICOLDM_W, "picoldm.w"),
27952 +    NORMAL_MNEMONIC(PICOMV_D, PICOMV_D1, "picomv.d"),
27953 +    NORMAL_MNEMONIC(PICOMV_W, PICOMV_W1, "picomv.w"),
27954 +    NORMAL_MNEMONIC(PICOST_D, PICOST_D2, "picost.d"),
27955 +    NORMAL_MNEMONIC(PICOST_W, PICOST_W2, "picost.w"),
27956 +    NORMAL_MNEMONIC(PICOSTM_D, PICOSTM_D, "picostm.d"),
27957 +    NORMAL_MNEMONIC(PICOSTM_W, PICOSTM_W, "picostm.w"),
27958 +    NORMAL_MNEMONIC(RSUBEQ, RSUBEQ, "rsubeq"),
27959 +    NORMAL_MNEMONIC(RSUBNE, RSUBNE, "rsubne"),
27960 +    NORMAL_MNEMONIC(RSUBCC, RSUBCC, "rsubcc"),
27961 +    NORMAL_MNEMONIC(RSUBCS, RSUBCS, "rsubcs"),
27962 +    NORMAL_MNEMONIC(RSUBGE, RSUBGE, "rsubge"),
27963 +    NORMAL_MNEMONIC(RSUBLT, RSUBLT, "rsublt"),
27964 +    NORMAL_MNEMONIC(RSUBMI, RSUBMI, "rsubmi"),
27965 +    NORMAL_MNEMONIC(RSUBPL, RSUBPL, "rsubpl"),
27966 +    NORMAL_MNEMONIC(RSUBLS, RSUBLS, "rsubls"),
27967 +    NORMAL_MNEMONIC(RSUBGT, RSUBGT, "rsubgt"),
27968 +    NORMAL_MNEMONIC(RSUBLE, RSUBLE, "rsuble"),
27969 +    NORMAL_MNEMONIC(RSUBHI, RSUBHI, "rsubhi"),
27970 +    NORMAL_MNEMONIC(RSUBVS, RSUBVS, "rsubvs"),
27971 +    NORMAL_MNEMONIC(RSUBVC, RSUBVC, "rsubvc"),
27972 +    NORMAL_MNEMONIC(RSUBQS, RSUBQS, "rsubqs"),
27973 +    NORMAL_MNEMONIC(RSUBAL, RSUBAL, "rsubal"),
27974 +    NORMAL_MNEMONIC(RSUBHS, RSUBHS, "rsubhs"),
27975 +    NORMAL_MNEMONIC(RSUBLO, RSUBLO, "rsublo"),
27976 +    NORMAL_MNEMONIC(ADDEQ, ADDEQ, "addeq"),
27977 +    NORMAL_MNEMONIC(ADDNE, ADDNE, "addne"),
27978 +    NORMAL_MNEMONIC(ADDCC, ADDCC, "addcc"),
27979 +    NORMAL_MNEMONIC(ADDCS, ADDCS, "addcs"),
27980 +    NORMAL_MNEMONIC(ADDGE, ADDGE, "addge"),
27981 +    NORMAL_MNEMONIC(ADDLT, ADDLT, "addlt"),
27982 +    NORMAL_MNEMONIC(ADDMI, ADDMI, "addmi"),
27983 +    NORMAL_MNEMONIC(ADDPL, ADDPL, "addpl"),
27984 +    NORMAL_MNEMONIC(ADDLS, ADDLS, "addls"),
27985 +    NORMAL_MNEMONIC(ADDGT, ADDGT, "addgt"),
27986 +    NORMAL_MNEMONIC(ADDLE, ADDLE, "addle"),
27987 +    NORMAL_MNEMONIC(ADDHI, ADDHI, "addhi"),
27988 +    NORMAL_MNEMONIC(ADDVS, ADDVS, "addvs"),
27989 +    NORMAL_MNEMONIC(ADDVC, ADDVC, "addvc"),
27990 +    NORMAL_MNEMONIC(ADDQS, ADDQS, "addqs"),
27991 +    NORMAL_MNEMONIC(ADDAL, ADDAL, "addal"),
27992 +    NORMAL_MNEMONIC(ADDHS, ADDHS, "addhs"),
27993 +    NORMAL_MNEMONIC(ADDLO, ADDLO, "addlo"),
27994 +    NORMAL_MNEMONIC(ANDEQ, ANDEQ, "andeq"),
27995 +    NORMAL_MNEMONIC(ANDNE, ANDNE, "andne"),
27996 +    NORMAL_MNEMONIC(ANDCC, ANDCC, "andcc"),
27997 +    NORMAL_MNEMONIC(ANDCS, ANDCS, "andcs"),
27998 +    NORMAL_MNEMONIC(ANDGE, ANDGE, "andge"),
27999 +    NORMAL_MNEMONIC(ANDLT, ANDLT, "andlt"),
28000 +    NORMAL_MNEMONIC(ANDMI, ANDMI, "andmi"),
28001 +    NORMAL_MNEMONIC(ANDPL, ANDPL, "andpl"),
28002 +    NORMAL_MNEMONIC(ANDLS, ANDLS, "andls"),
28003 +    NORMAL_MNEMONIC(ANDGT, ANDGT, "andgt"),
28004 +    NORMAL_MNEMONIC(ANDLE, ANDLE, "andle"),
28005 +    NORMAL_MNEMONIC(ANDHI, ANDHI, "andhi"),
28006 +    NORMAL_MNEMONIC(ANDVS, ANDVS, "andvs"),
28007 +    NORMAL_MNEMONIC(ANDVC, ANDVC, "andvc"),
28008 +    NORMAL_MNEMONIC(ANDQS, ANDQS, "andqs"),
28009 +    NORMAL_MNEMONIC(ANDAL, ANDAL, "andal"),
28010 +    NORMAL_MNEMONIC(ANDHS, ANDHS, "andhs"),
28011 +    NORMAL_MNEMONIC(ANDLO, ANDLO, "andlo"),
28012 +    NORMAL_MNEMONIC(OREQ, OREQ, "oreq"),
28013 +    NORMAL_MNEMONIC(ORNE, ORNE, "orne"),
28014 +    NORMAL_MNEMONIC(ORCC, ORCC, "orcc"),
28015 +    NORMAL_MNEMONIC(ORCS, ORCS, "orcs"),
28016 +    NORMAL_MNEMONIC(ORGE, ORGE, "orge"),
28017 +    NORMAL_MNEMONIC(ORLT, ORLT, "orlt"),
28018 +    NORMAL_MNEMONIC(ORMI, ORMI, "ormi"),
28019 +    NORMAL_MNEMONIC(ORPL, ORPL, "orpl"),
28020 +    NORMAL_MNEMONIC(ORLS, ORLS, "orls"),
28021 +    NORMAL_MNEMONIC(ORGT, ORGT, "orgt"),
28022 +    NORMAL_MNEMONIC(ORLE, ORLE, "orle"),
28023 +    NORMAL_MNEMONIC(ORHI, ORHI, "orhi"),
28024 +    NORMAL_MNEMONIC(ORVS, ORVS, "orvs"),
28025 +    NORMAL_MNEMONIC(ORVC, ORVC, "orvc"),
28026 +    NORMAL_MNEMONIC(ORQS, ORQS, "orqs"),
28027 +    NORMAL_MNEMONIC(ORAL, ORAL, "oral"),
28028 +    NORMAL_MNEMONIC(ORHS, ORHS, "orhs"),
28029 +    NORMAL_MNEMONIC(ORLO, ORLO, "orlo"),
28030 +    NORMAL_MNEMONIC(EOREQ, EOREQ, "eoreq"),
28031 +    NORMAL_MNEMONIC(EORNE, EORNE, "eorne"),
28032 +    NORMAL_MNEMONIC(EORCC, EORCC, "eorcc"),
28033 +    NORMAL_MNEMONIC(EORCS, EORCS, "eorcs"),
28034 +    NORMAL_MNEMONIC(EORGE, EORGE, "eorge"),
28035 +    NORMAL_MNEMONIC(EORLT, EORLT, "eorlt"),
28036 +    NORMAL_MNEMONIC(EORMI, EORMI, "eormi"),
28037 +    NORMAL_MNEMONIC(EORPL, EORPL, "eorpl"),
28038 +    NORMAL_MNEMONIC(EORLS, EORLS, "eorls"),
28039 +    NORMAL_MNEMONIC(EORGT, EORGT, "eorgt"),
28040 +    NORMAL_MNEMONIC(EORLE, EORLE, "eorle"),
28041 +    NORMAL_MNEMONIC(EORHI, EORHI, "eorhi"),
28042 +    NORMAL_MNEMONIC(EORVS, EORVS, "eorvs"),
28043 +    NORMAL_MNEMONIC(EORVC, EORVC, "eorvc"),
28044 +    NORMAL_MNEMONIC(EORQS, EORQS, "eorqs"),
28045 +    NORMAL_MNEMONIC(EORAL, EORAL, "eoral"),
28046 +    NORMAL_MNEMONIC(EORHS, EORHS, "eorhs"),
28047 +    NORMAL_MNEMONIC(EORLO, EORLO, "eorlo"),
28048 +    NORMAL_MNEMONIC(LD_WEQ, LD_WEQ, "ld.weq"),
28049 +    NORMAL_MNEMONIC(LD_WNE, LD_WNE, "ld.wne"),
28050 +    NORMAL_MNEMONIC(LD_WCC, LD_WCC, "ld.wcc"),
28051 +    NORMAL_MNEMONIC(LD_WCS, LD_WCS, "ld.wcs"),
28052 +    NORMAL_MNEMONIC(LD_WGE, LD_WGE, "ld.wge"),
28053 +    NORMAL_MNEMONIC(LD_WLT, LD_WLT, "ld.wlt"),
28054 +    NORMAL_MNEMONIC(LD_WMI, LD_WMI, "ld.wmi"),
28055 +    NORMAL_MNEMONIC(LD_WPL, LD_WPL, "ld.wpl"),
28056 +    NORMAL_MNEMONIC(LD_WLS, LD_WLS, "ld.wls"),
28057 +    NORMAL_MNEMONIC(LD_WGT, LD_WGT, "ld.wgt"),
28058 +    NORMAL_MNEMONIC(LD_WLE, LD_WLE, "ld.wle"),
28059 +    NORMAL_MNEMONIC(LD_WHI, LD_WHI, "ld.whi"),
28060 +    NORMAL_MNEMONIC(LD_WVS, LD_WVS, "ld.wvs"),
28061 +    NORMAL_MNEMONIC(LD_WVC, LD_WVC, "ld.wvc"),
28062 +    NORMAL_MNEMONIC(LD_WQS, LD_WQS, "ld.wqs"),
28063 +    NORMAL_MNEMONIC(LD_WAL, LD_WAL, "ld.wal"),
28064 +    NORMAL_MNEMONIC(LD_WHS, LD_WHS, "ld.whs"),
28065 +    NORMAL_MNEMONIC(LD_WLO, LD_WLO, "ld.wlo"),
28066 +    NORMAL_MNEMONIC(LD_SHEQ, LD_SHEQ, "ld.sheq"),
28067 +    NORMAL_MNEMONIC(LD_SHNE, LD_SHNE, "ld.shne"),
28068 +    NORMAL_MNEMONIC(LD_SHCC, LD_SHCC, "ld.shcc"),
28069 +    NORMAL_MNEMONIC(LD_SHCS, LD_SHCS, "ld.shcs"),
28070 +    NORMAL_MNEMONIC(LD_SHGE, LD_SHGE, "ld.shge"),
28071 +    NORMAL_MNEMONIC(LD_SHLT, LD_SHLT, "ld.shlt"),
28072 +    NORMAL_MNEMONIC(LD_SHMI, LD_SHMI, "ld.shmi"),
28073 +    NORMAL_MNEMONIC(LD_SHPL, LD_SHPL, "ld.shpl"),
28074 +    NORMAL_MNEMONIC(LD_SHLS, LD_SHLS, "ld.shls"),
28075 +    NORMAL_MNEMONIC(LD_SHGT, LD_SHGT, "ld.shgt"),
28076 +    NORMAL_MNEMONIC(LD_SHLE, LD_SHLE, "ld.shle"),
28077 +    NORMAL_MNEMONIC(LD_SHHI, LD_SHHI, "ld.shhi"),
28078 +    NORMAL_MNEMONIC(LD_SHVS, LD_SHVS, "ld.shvs"),
28079 +    NORMAL_MNEMONIC(LD_SHVC, LD_SHVC, "ld.shvc"),
28080 +    NORMAL_MNEMONIC(LD_SHQS, LD_SHQS, "ld.shqs"),
28081 +    NORMAL_MNEMONIC(LD_SHAL, LD_SHAL, "ld.shal"),
28082 +    NORMAL_MNEMONIC(LD_SHHS, LD_SHHS, "ld.shhs"),
28083 +    NORMAL_MNEMONIC(LD_SHLO, LD_SHLO, "ld.shlo"),
28084 +    NORMAL_MNEMONIC(LD_UHEQ, LD_UHEQ, "ld.uheq"),
28085 +    NORMAL_MNEMONIC(LD_UHNE, LD_UHNE, "ld.uhne"),
28086 +    NORMAL_MNEMONIC(LD_UHCC, LD_UHCC, "ld.uhcc"),
28087 +    NORMAL_MNEMONIC(LD_UHCS, LD_UHCS, "ld.uhcs"),
28088 +    NORMAL_MNEMONIC(LD_UHGE, LD_UHGE, "ld.uhge"),
28089 +    NORMAL_MNEMONIC(LD_UHLT, LD_UHLT, "ld.uhlt"),
28090 +    NORMAL_MNEMONIC(LD_UHMI, LD_UHMI, "ld.uhmi"),
28091 +    NORMAL_MNEMONIC(LD_UHPL, LD_UHPL, "ld.uhpl"),
28092 +    NORMAL_MNEMONIC(LD_UHLS, LD_UHLS, "ld.uhls"),
28093 +    NORMAL_MNEMONIC(LD_UHGT, LD_UHGT, "ld.uhgt"),
28094 +    NORMAL_MNEMONIC(LD_UHLE, LD_UHLE, "ld.uhle"),
28095 +    NORMAL_MNEMONIC(LD_UHHI, LD_UHHI, "ld.uhhi"),
28096 +    NORMAL_MNEMONIC(LD_UHVS, LD_UHVS, "ld.uhvs"),
28097 +    NORMAL_MNEMONIC(LD_UHVC, LD_UHVC, "ld.uhvc"),
28098 +    NORMAL_MNEMONIC(LD_UHQS, LD_UHQS, "ld.uhqs"),
28099 +    NORMAL_MNEMONIC(LD_UHAL, LD_UHAL, "ld.uhal"),
28100 +    NORMAL_MNEMONIC(LD_UHHS, LD_UHHS, "ld.uhhs"),
28101 +    NORMAL_MNEMONIC(LD_UHLO, LD_UHLO, "ld.uhlo"),
28102 +    NORMAL_MNEMONIC(LD_SBEQ, LD_SBEQ, "ld.sbeq"),
28103 +    NORMAL_MNEMONIC(LD_SBNE, LD_SBNE, "ld.sbne"),
28104 +    NORMAL_MNEMONIC(LD_SBCC, LD_SBCC, "ld.sbcc"),
28105 +    NORMAL_MNEMONIC(LD_SBCS, LD_SBCS, "ld.sbcs"),
28106 +    NORMAL_MNEMONIC(LD_SBGE, LD_SBGE, "ld.sbge"),
28107 +    NORMAL_MNEMONIC(LD_SBLT, LD_SBLT, "ld.sblt"),
28108 +    NORMAL_MNEMONIC(LD_SBMI, LD_SBMI, "ld.sbmi"),
28109 +    NORMAL_MNEMONIC(LD_SBPL, LD_SBPL, "ld.sbpl"),
28110 +    NORMAL_MNEMONIC(LD_SBLS, LD_SBLS, "ld.sbls"),
28111 +    NORMAL_MNEMONIC(LD_SBGT, LD_SBGT, "ld.sbgt"),
28112 +    NORMAL_MNEMONIC(LD_SBLE, LD_SBLE, "ld.sble"),
28113 +    NORMAL_MNEMONIC(LD_SBHI, LD_SBHI, "ld.sbhi"),
28114 +    NORMAL_MNEMONIC(LD_SBVS, LD_SBVS, "ld.sbvs"),
28115 +    NORMAL_MNEMONIC(LD_SBVC, LD_SBVC, "ld.sbvc"),
28116 +    NORMAL_MNEMONIC(LD_SBQS, LD_SBQS, "ld.sbqs"),
28117 +    NORMAL_MNEMONIC(LD_SBAL, LD_SBAL, "ld.sbal"),
28118 +    NORMAL_MNEMONIC(LD_SBHS, LD_SBHS, "ld.sbhs"),
28119 +    NORMAL_MNEMONIC(LD_SBLO, LD_SBLO, "ld.sblo"),
28120 +    NORMAL_MNEMONIC(LD_UBEQ, LD_UBEQ, "ld.ubeq"),
28121 +    NORMAL_MNEMONIC(LD_UBNE, LD_UBNE, "ld.ubne"),
28122 +    NORMAL_MNEMONIC(LD_UBCC, LD_UBCC, "ld.ubcc"),
28123 +    NORMAL_MNEMONIC(LD_UBCS, LD_UBCS, "ld.ubcs"),
28124 +    NORMAL_MNEMONIC(LD_UBGE, LD_UBGE, "ld.ubge"),
28125 +    NORMAL_MNEMONIC(LD_UBLT, LD_UBLT, "ld.ublt"),
28126 +    NORMAL_MNEMONIC(LD_UBMI, LD_UBMI, "ld.ubmi"),
28127 +    NORMAL_MNEMONIC(LD_UBPL, LD_UBPL, "ld.ubpl"),
28128 +    NORMAL_MNEMONIC(LD_UBLS, LD_UBLS, "ld.ubls"),
28129 +    NORMAL_MNEMONIC(LD_UBGT, LD_UBGT, "ld.ubgt"),
28130 +    NORMAL_MNEMONIC(LD_UBLE, LD_UBLE, "ld.uble"),
28131 +    NORMAL_MNEMONIC(LD_UBHI, LD_UBHI, "ld.ubhi"),
28132 +    NORMAL_MNEMONIC(LD_UBVS, LD_UBVS, "ld.ubvs"),
28133 +    NORMAL_MNEMONIC(LD_UBVC, LD_UBVC, "ld.ubvc"),
28134 +    NORMAL_MNEMONIC(LD_UBQS, LD_UBQS, "ld.ubqs"),
28135 +    NORMAL_MNEMONIC(LD_UBAL, LD_UBAL, "ld.ubal"),
28136 +    NORMAL_MNEMONIC(LD_UBHS, LD_UBHS, "ld.ubhs"),
28137 +    NORMAL_MNEMONIC(LD_UBLO, LD_UBLO, "ld.ublo"),
28138 +    NORMAL_MNEMONIC(ST_WEQ, ST_WEQ, "st.weq"),
28139 +    NORMAL_MNEMONIC(ST_WNE, ST_WNE, "st.wne"),
28140 +    NORMAL_MNEMONIC(ST_WCC, ST_WCC, "st.wcc"),
28141 +    NORMAL_MNEMONIC(ST_WCS, ST_WCS, "st.wcs"),
28142 +    NORMAL_MNEMONIC(ST_WGE, ST_WGE, "st.wge"),
28143 +    NORMAL_MNEMONIC(ST_WLT, ST_WLT, "st.wlt"),
28144 +    NORMAL_MNEMONIC(ST_WMI, ST_WMI, "st.wmi"),
28145 +    NORMAL_MNEMONIC(ST_WPL, ST_WPL, "st.wpl"),
28146 +    NORMAL_MNEMONIC(ST_WLS, ST_WLS, "st.wls"),
28147 +    NORMAL_MNEMONIC(ST_WGT, ST_WGT, "st.wgt"),
28148 +    NORMAL_MNEMONIC(ST_WLE, ST_WLE, "st.wle"),
28149 +    NORMAL_MNEMONIC(ST_WHI, ST_WHI, "st.whi"),
28150 +    NORMAL_MNEMONIC(ST_WVS, ST_WVS, "st.wvs"),
28151 +    NORMAL_MNEMONIC(ST_WVC, ST_WVC, "st.wvc"),
28152 +    NORMAL_MNEMONIC(ST_WQS, ST_WQS, "st.wqs"),
28153 +    NORMAL_MNEMONIC(ST_WAL, ST_WAL, "st.wal"),
28154 +    NORMAL_MNEMONIC(ST_WHS, ST_WHS, "st.whs"),
28155 +    NORMAL_MNEMONIC(ST_WLO, ST_WLO, "st.wlo"),
28156 +    NORMAL_MNEMONIC(ST_HEQ, ST_HEQ, "st.heq"),
28157 +    NORMAL_MNEMONIC(ST_HNE, ST_HNE, "st.hne"),
28158 +    NORMAL_MNEMONIC(ST_HCC, ST_HCC, "st.hcc"),
28159 +    NORMAL_MNEMONIC(ST_HCS, ST_HCS, "st.hcs"),
28160 +    NORMAL_MNEMONIC(ST_HGE, ST_HGE, "st.hge"),
28161 +    NORMAL_MNEMONIC(ST_HLT, ST_HLT, "st.hlt"),
28162 +    NORMAL_MNEMONIC(ST_HMI, ST_HMI, "st.hmi"),
28163 +    NORMAL_MNEMONIC(ST_HPL, ST_HPL, "st.hpl"),
28164 +    NORMAL_MNEMONIC(ST_HLS, ST_HLS, "st.hls"),
28165 +    NORMAL_MNEMONIC(ST_HGT, ST_HGT, "st.hgt"),
28166 +    NORMAL_MNEMONIC(ST_HLE, ST_HLE, "st.hle"),
28167 +    NORMAL_MNEMONIC(ST_HHI, ST_HHI, "st.hhi"),
28168 +    NORMAL_MNEMONIC(ST_HVS, ST_HVS, "st.hvs"),
28169 +    NORMAL_MNEMONIC(ST_HVC, ST_HVC, "st.hvc"),
28170 +    NORMAL_MNEMONIC(ST_HQS, ST_HQS, "st.hqs"),
28171 +    NORMAL_MNEMONIC(ST_HAL, ST_HAL, "st.hal"),
28172 +    NORMAL_MNEMONIC(ST_HHS, ST_HHS, "st.hhs"),
28173 +    NORMAL_MNEMONIC(ST_HLO, ST_HLO, "st.hlo"),
28174 +    NORMAL_MNEMONIC(ST_BEQ, ST_BEQ, "st.beq"),
28175 +    NORMAL_MNEMONIC(ST_BNE, ST_BNE, "st.bne"),
28176 +    NORMAL_MNEMONIC(ST_BCC, ST_BCC, "st.bcc"),
28177 +    NORMAL_MNEMONIC(ST_BCS, ST_BCS, "st.bcs"),
28178 +    NORMAL_MNEMONIC(ST_BGE, ST_BGE, "st.bge"),
28179 +    NORMAL_MNEMONIC(ST_BLT, ST_BLT, "st.blt"),
28180 +    NORMAL_MNEMONIC(ST_BMI, ST_BMI, "st.bmi"),
28181 +    NORMAL_MNEMONIC(ST_BPL, ST_BPL, "st.bpl"),
28182 +    NORMAL_MNEMONIC(ST_BLS, ST_BLS, "st.bls"),
28183 +    NORMAL_MNEMONIC(ST_BGT, ST_BGT, "st.bgt"),
28184 +    NORMAL_MNEMONIC(ST_BLE, ST_BLE, "st.ble"),
28185 +    NORMAL_MNEMONIC(ST_BHI, ST_BHI, "st.bhi"),
28186 +    NORMAL_MNEMONIC(ST_BVS, ST_BVS, "st.bvs"),
28187 +    NORMAL_MNEMONIC(ST_BVC, ST_BVC, "st.bvc"),
28188 +    NORMAL_MNEMONIC(ST_BQS, ST_BQS, "st.bqs"),
28189 +    NORMAL_MNEMONIC(ST_BAL, ST_BAL, "st.bal"),
28190 +    NORMAL_MNEMONIC(ST_BHS, ST_BHS, "st.bhs"),
28191 +    NORMAL_MNEMONIC(ST_BLO, ST_BLO, "st.blo"),
28192 +    NORMAL_MNEMONIC(MOVH, MOVH, "movh"),
28193 +
28194 +  };
28195 +#undef NORMAL_MNEMONIC
28196 +#undef ALIAS_MNEMONIC
28197 +#undef FP_MNEMONIC
28198 --- /dev/null
28199 +++ b/opcodes/avr32-opc.h
28200 @@ -0,0 +1,2377 @@
28201 +/* Opcode tables for AVR32.
28202 +   Copyright 2005,2006,2007,2008,2009 Atmel Corporation.
28203 +
28204 +   Written by Haavard Skinnemoen, Atmel Norway, <hskinnemoen@atmel.com>
28205 +
28206 +   This file is part of libopcodes.
28207 +
28208 +   This program is free software; you can redistribute it and/or
28209 +   modify it under the terms of the GNU General Public License as
28210 +   published by the Free Software Foundation; either version 2 of the
28211 +   License, or (at your option) any later version.
28212 +
28213 +   This program is distributed in the hope that it will be useful, but
28214 +   WITHOUT ANY WARRANTY; without even the implied warranty of
28215 +   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
28216 +   General Public License for more details.
28217 +
28218 +   You should have received a copy of the GNU General Public License
28219 +   along with this program; if not, write to the Free Software
28220 +   Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA
28221 +   02111-1307, USA.  */
28222 +
28223 +#include "bfd.h"
28224 +
28225 +#define AVR32_MAX_OPERANDS     8
28226 +#define AVR32_MAX_FIELDS       8
28227 +
28228 +#define AVR32_V1               (1 << 1)
28229 +#define AVR32_SIMD             (1 << 2)
28230 +#define AVR32_DSP              (1 << 3)
28231 +#define AVR32_RMW              (1 << 4)
28232 +#define AVR32_V2               (1 << 5)
28233 +#define AVR32_V3               (1 << 6)
28234 +#define AVR32_FP               (1 << 16)
28235 +#define AVR32_PICO             (1 << 17)
28236 +
28237 +/* Registers we commonly refer to */
28238 +#define AVR32_REG_R12          12
28239 +#define AVR32_REG_SP           13
28240 +#define AVR32_REG_LR           14
28241 +#define AVR32_REG_PC           15
28242 +
28243 +struct avr32_ifield
28244 +{
28245 +  int id;
28246 +  unsigned short bitsize;
28247 +  unsigned short shift;
28248 +  unsigned long mask;
28249 +
28250 +  /* If the value doesn't fit, it will be truncated with no warning */
28251 +  void (*insert)(const struct avr32_ifield *, void *, unsigned long);
28252 +  void (*extract)(const struct avr32_ifield *, void *, unsigned long *);
28253 +};
28254 +
28255 +struct avr32_opcode
28256 +{
28257 +  int id;
28258 +  int size;
28259 +  unsigned long value;
28260 +  unsigned long mask;
28261 +  const struct avr32_syntax *syntax;
28262 +  bfd_reloc_code_real_type reloc_type;
28263 +  unsigned int nr_fields;
28264 +  /* if relaxable, which field is variable, otherwise -1 */
28265 +  int var_field;
28266 +  const struct avr32_ifield *fields[AVR32_MAX_FIELDS];
28267 +};
28268 +
28269 +struct avr32_alias
28270 +{
28271 +  int id;
28272 +  const struct avr32_opcode *opc;
28273 +  struct {
28274 +    int is_opindex;
28275 +    unsigned long value;
28276 +  } operand_map[AVR32_MAX_OPERANDS];
28277 +};
28278 +
28279 +struct avr32_syntax
28280 +{
28281 +  int id;
28282 +  unsigned long isa_flags;
28283 +  const struct avr32_mnemonic *mnemonic;
28284 +  int type;
28285 +  union {
28286 +    const struct avr32_opcode *opc;
28287 +    const struct avr32_alias *alias;
28288 +  } u;
28289 +  const struct avr32_syntax *next;
28290 +  /* negative means "vararg" */
28291 +  int nr_operands;
28292 +  int operand[AVR32_MAX_OPERANDS];
28293 +};
28294 +
28295 +#if 0
28296 +#define AVR32_ALIAS_MAKE_CONST(val) ((val) | 0x80000000UL)
28297 +#define AVR32_ALIAS_IS_CONST(mapval) (((mapval) & 0x80000000UL) != 0)
28298 +#define AVR32_ALIAS_GET_CONST(mapval) ((mapval) & ~0x80000000UL)
28299 +#endif
28300 +
28301 +struct avr32_mnemonic
28302 +{
28303 +  int id;
28304 +  const char *name;
28305 +  const struct avr32_syntax *syntax;
28306 +};
28307 +
28308 +extern const struct avr32_ifield avr32_ifield_table[];
28309 +extern struct avr32_opcode avr32_opc_table[];
28310 +extern const struct avr32_syntax avr32_syntax_table[];
28311 +extern const struct avr32_alias avr32_alias_table[];
28312 +extern const struct avr32_mnemonic avr32_mnemonic_table[];
28313 +
28314 +extern void avr32_insert_simple(const struct avr32_ifield *field,
28315 +                               void *buf, unsigned long value);
28316 +extern void avr32_insert_bit5c(const struct avr32_ifield *field,
28317 +                              void *buf, unsigned long value);
28318 +extern void avr32_insert_k10(const struct avr32_ifield *field,
28319 +                            void *buf, unsigned long value);
28320 +extern void avr32_insert_k21(const struct avr32_ifield *field,
28321 +                            void *buf, unsigned long value);
28322 +extern void avr32_insert_cpop(const struct avr32_ifield *field,
28323 +                             void *buf, unsigned long value);
28324 +extern void avr32_insert_k12cp(const struct avr32_ifield *field,
28325 +                              void *buf, unsigned long value);
28326 +
28327 +extern void avr32_extract_simple(const struct avr32_ifield *field,
28328 +                                void *buf, unsigned long *value);
28329 +extern void avr32_extract_bit5c(const struct avr32_ifield *field,
28330 +                               void *buf, unsigned long *value);
28331 +extern void avr32_extract_k10(const struct avr32_ifield *field,
28332 +                             void *buf, unsigned long *value);
28333 +extern void avr32_extract_k21(const struct avr32_ifield *field,
28334 +                             void *buf, unsigned long *value);
28335 +extern void avr32_extract_cpop(const struct avr32_ifield *field,
28336 +                              void *buf, unsigned long *value);
28337 +extern void avr32_extract_k12cp(const struct avr32_ifield *field,
28338 +                               void *buf, unsigned long *value);
28339 +
28340 +enum avr32_operand_type
28341 +{
28342 +  AVR32_OPERAND_INTREG,                /* just a register */
28343 +  AVR32_OPERAND_INTREG_PREDEC, /* register with pre-decrement */
28344 +  AVR32_OPERAND_INTREG_POSTINC,        /* register with post-increment */
28345 +  AVR32_OPERAND_INTREG_LSL,    /* register with left shift */
28346 +  AVR32_OPERAND_INTREG_LSR,    /* register with right shift */
28347 +  AVR32_OPERAND_INTREG_BSEL,   /* register with byte selector */
28348 +  AVR32_OPERAND_INTREG_HSEL,   /* register with halfword selector */
28349 +  AVR32_OPERAND_INTREG_SDISP,  /* Rp[signed disp] */
28350 +  AVR32_OPERAND_INTREG_SDISP_H,        /* Rp[signed hword-aligned disp] */
28351 +  AVR32_OPERAND_INTREG_SDISP_W,        /* Rp[signed word-aligned disp] */
28352 +  AVR32_OPERAND_INTREG_UDISP,  /* Rp[unsigned disp] */
28353 +  AVR32_OPERAND_INTREG_UDISP_H,        /* Rp[unsigned hword-aligned disp] */
28354 +  AVR32_OPERAND_INTREG_UDISP_W, /* Rp[unsigned word-aligned disp] */
28355 +  AVR32_OPERAND_INTREG_INDEX,  /* Rp[Ri << sa] */
28356 +  AVR32_OPERAND_INTREG_XINDEX, /* Rp[Ri:bytesel << 2] */
28357 +  AVR32_OPERAND_DWREG,         /* Even-numbered register */
28358 +  AVR32_OPERAND_PC_UDISP_W,    /* PC[unsigned word-aligned disp] or label */
28359 +  AVR32_OPERAND_SP,            /* Just SP */
28360 +  AVR32_OPERAND_SP_UDISP_W,    /* SP[unsigned word-aligned disp] */
28361 +  AVR32_OPERAND_CPNO,
28362 +  AVR32_OPERAND_CPREG,
28363 +  AVR32_OPERAND_CPREG_D,
28364 +  AVR32_OPERAND_UNSIGNED_CONST,
28365 +  AVR32_OPERAND_UNSIGNED_CONST_W,
28366 +  AVR32_OPERAND_SIGNED_CONST,
28367 +  AVR32_OPERAND_SIGNED_CONST_W,
28368 +  AVR32_OPERAND_JMPLABEL,
28369 +  AVR32_OPERAND_UNSIGNED_NUMBER,
28370 +  AVR32_OPERAND_UNSIGNED_NUMBER_W,
28371 +  AVR32_OPERAND_REGLIST8,
28372 +  AVR32_OPERAND_REGLIST9,
28373 +  AVR32_OPERAND_REGLIST16,
28374 +  AVR32_OPERAND_REGLIST_LDM,
28375 +  AVR32_OPERAND_REGLIST_CP8,
28376 +  AVR32_OPERAND_REGLIST_CPD8,
28377 +  AVR32_OPERAND_RETVAL,
28378 +  AVR32_OPERAND_MCALL,
28379 +  AVR32_OPERAND_JOSPINC,
28380 +  AVR32_OPERAND_COH,
28381 +  AVR32_OPERAND_FPREG_S,
28382 +  AVR32_OPERAND_FPREG_D,
28383 +  AVR32_OPERAND_PICO_REG_W,
28384 +  AVR32_OPERAND_PICO_REG_D,
28385 +  AVR32_OPERAND_PICO_REGLIST_W,
28386 +  AVR32_OPERAND_PICO_REGLIST_D,
28387 +  AVR32_OPERAND_PICO_IN,
28388 +  AVR32_OPERAND_PICO_OUT0,
28389 +  AVR32_OPERAND_PICO_OUT1,
28390 +  AVR32_OPERAND_PICO_OUT2,
28391 +  AVR32_OPERAND_PICO_OUT3,
28392 +  AVR32_OPERAND__END_
28393 +};
28394 +#define AVR32_OPERAND_UNKNOWN AVR32_OPERAND__END_
28395 +#define AVR32_NR_OPERANDS AVR32_OPERAND__END_
28396 +
28397 +enum avr32_ifield_type
28398 +{
28399 +  AVR32_IFIELD_RX,
28400 +  AVR32_IFIELD_RY,
28401 +  AVR32_IFIELD_COND4C,
28402 +  AVR32_IFIELD_K8C,
28403 +  AVR32_IFIELD_K7C,
28404 +  AVR32_IFIELD_K5C,
28405 +  AVR32_IFIELD_K3,
28406 +  AVR32_IFIELD_RY_DW,
28407 +  AVR32_IFIELD_COND4E,
28408 +  AVR32_IFIELD_K8E,
28409 +  AVR32_IFIELD_BIT5C,
28410 +  AVR32_IFIELD_COND3,
28411 +  AVR32_IFIELD_K10,
28412 +  AVR32_IFIELD_POPM,
28413 +  AVR32_IFIELD_K2,
28414 +  AVR32_IFIELD_RD_E,
28415 +  AVR32_IFIELD_RD_DW,
28416 +  AVR32_IFIELD_X,
28417 +  AVR32_IFIELD_Y,
28418 +  AVR32_IFIELD_X2,
28419 +  AVR32_IFIELD_Y2,
28420 +  AVR32_IFIELD_K5E,
28421 +  AVR32_IFIELD_PART2,
28422 +  AVR32_IFIELD_PART1,
28423 +  AVR32_IFIELD_K16,
28424 +  AVR32_IFIELD_CACHEOP,
28425 +  AVR32_IFIELD_K11,
28426 +  AVR32_IFIELD_K21,
28427 +  AVR32_IFIELD_CPOP,
28428 +  AVR32_IFIELD_CPNO,
28429 +  AVR32_IFIELD_CRD_RI,
28430 +  AVR32_IFIELD_CRX,
28431 +  AVR32_IFIELD_CRY,
28432 +  AVR32_IFIELD_K7E,
28433 +  AVR32_IFIELD_CRD_DW,
28434 +  AVR32_IFIELD_PART1_K12,
28435 +  AVR32_IFIELD_PART2_K12,
28436 +  AVR32_IFIELD_K12,
28437 +  AVR32_IFIELD_S5,
28438 +  AVR32_IFIELD_K5E2,
28439 +  AVR32_IFIELD_K4,
28440 +  AVR32_IFIELD_COND4E2,
28441 +  AVR32_IFIELD_K8E2,
28442 +  AVR32_IFIELD_K6,
28443 +  AVR32_IFIELD_MEM15,
28444 +  AVR32_IFIELD_MEMB5,
28445 +  AVR32_IFIELD_W,
28446 +  AVR32_IFIELD_CM_HL,
28447 +  AVR32_IFIELD_K12CP,
28448 +  AVR32_IFIELD_K9E,
28449 +  AVR32_IFIELD__END_,
28450 +};
28451 +#define AVR32_NR_IFIELDS AVR32_IFIELD__END_
28452 +
28453 +enum avr32_opc_type
28454 +{
28455 +  AVR32_OPC_ABS,
28456 +  AVR32_OPC_ACALL,
28457 +  AVR32_OPC_ACR,
28458 +  AVR32_OPC_ADC,
28459 +  AVR32_OPC_ADD1,
28460 +  AVR32_OPC_ADD2,
28461 +  AVR32_OPC_ADDABS,
28462 +  AVR32_OPC_ADDHH_W,
28463 +  AVR32_OPC_AND1,
28464 +  AVR32_OPC_AND2,
28465 +  AVR32_OPC_AND3,
28466 +  AVR32_OPC_ANDH,
28467 +  AVR32_OPC_ANDH_COH,
28468 +  AVR32_OPC_ANDL,
28469 +  AVR32_OPC_ANDL_COH,
28470 +  AVR32_OPC_ANDN,
28471 +  AVR32_OPC_ASR1,
28472 +  AVR32_OPC_ASR3,
28473 +  AVR32_OPC_ASR2,
28474 +  AVR32_OPC_BLD,
28475 +  AVR32_OPC_BREQ1,
28476 +  AVR32_OPC_BRNE1,
28477 +  AVR32_OPC_BRCC1,
28478 +  AVR32_OPC_BRCS1,
28479 +  AVR32_OPC_BRGE1,
28480 +  AVR32_OPC_BRLT1,
28481 +  AVR32_OPC_BRMI1,
28482 +  AVR32_OPC_BRPL1,
28483 +  AVR32_OPC_BREQ2,
28484 +  AVR32_OPC_BRNE2,
28485 +  AVR32_OPC_BRCC2,
28486 +  AVR32_OPC_BRCS2,
28487 +  AVR32_OPC_BRGE2,
28488 +  AVR32_OPC_BRLT2,
28489 +  AVR32_OPC_BRMI2,
28490 +  AVR32_OPC_BRPL2,
28491 +  AVR32_OPC_BRLS,
28492 +  AVR32_OPC_BRGT,
28493 +  AVR32_OPC_BRLE,
28494 +  AVR32_OPC_BRHI,
28495 +  AVR32_OPC_BRVS,
28496 +  AVR32_OPC_BRVC,
28497 +  AVR32_OPC_BRQS,
28498 +  AVR32_OPC_BRAL,
28499 +  AVR32_OPC_BREAKPOINT,
28500 +  AVR32_OPC_BREV,
28501 +  AVR32_OPC_BST,
28502 +  AVR32_OPC_CACHE,
28503 +  AVR32_OPC_CASTS_B,
28504 +  AVR32_OPC_CASTS_H,
28505 +  AVR32_OPC_CASTU_B,
28506 +  AVR32_OPC_CASTU_H,
28507 +  AVR32_OPC_CBR,
28508 +  AVR32_OPC_CLZ,
28509 +  AVR32_OPC_COM,
28510 +  AVR32_OPC_COP,
28511 +  AVR32_OPC_CP_B,
28512 +  AVR32_OPC_CP_H,
28513 +  AVR32_OPC_CP_W1,
28514 +  AVR32_OPC_CP_W2,
28515 +  AVR32_OPC_CP_W3,
28516 +  AVR32_OPC_CPC1,
28517 +  AVR32_OPC_CPC2,
28518 +  AVR32_OPC_CSRF,
28519 +  AVR32_OPC_CSRFCZ,
28520 +  AVR32_OPC_DIVS,
28521 +  AVR32_OPC_DIVU,
28522 +  AVR32_OPC_EOR1,
28523 +  AVR32_OPC_EOR2,
28524 +  AVR32_OPC_EOR3,
28525 +  AVR32_OPC_EORL,
28526 +  AVR32_OPC_EORH,
28527 +  AVR32_OPC_FRS,
28528 +  AVR32_OPC_ICALL,
28529 +  AVR32_OPC_INCJOSP,
28530 +  AVR32_OPC_LD_D1,
28531 +  AVR32_OPC_LD_D2,
28532 +  AVR32_OPC_LD_D3,
28533 +  AVR32_OPC_LD_D5,
28534 +  AVR32_OPC_LD_D4,
28535 +  AVR32_OPC_LD_SB2,
28536 +  AVR32_OPC_LD_SB1,
28537 +  AVR32_OPC_LD_UB1,
28538 +  AVR32_OPC_LD_UB2,
28539 +  AVR32_OPC_LD_UB5,
28540 +  AVR32_OPC_LD_UB3,
28541 +  AVR32_OPC_LD_UB4,
28542 +  AVR32_OPC_LD_SH1,
28543 +  AVR32_OPC_LD_SH2,
28544 +  AVR32_OPC_LD_SH5,
28545 +  AVR32_OPC_LD_SH3,
28546 +  AVR32_OPC_LD_SH4,
28547 +  AVR32_OPC_LD_UH1,
28548 +  AVR32_OPC_LD_UH2,
28549 +  AVR32_OPC_LD_UH5,
28550 +  AVR32_OPC_LD_UH3,
28551 +  AVR32_OPC_LD_UH4,
28552 +  AVR32_OPC_LD_W1,
28553 +  AVR32_OPC_LD_W2,
28554 +  AVR32_OPC_LD_W5,
28555 +  AVR32_OPC_LD_W6,
28556 +  AVR32_OPC_LD_W3,
28557 +  AVR32_OPC_LD_W4,
28558 +  AVR32_OPC_LDC_D1,
28559 +  AVR32_OPC_LDC_D2,
28560 +  AVR32_OPC_LDC_D3,
28561 +  AVR32_OPC_LDC_W1,
28562 +  AVR32_OPC_LDC_W2,
28563 +  AVR32_OPC_LDC_W3,
28564 +  AVR32_OPC_LDC0_D,
28565 +  AVR32_OPC_LDC0_W,
28566 +  AVR32_OPC_LDCM_D,
28567 +  AVR32_OPC_LDCM_D_PU,
28568 +  AVR32_OPC_LDCM_W,
28569 +  AVR32_OPC_LDCM_W_PU,
28570 +  AVR32_OPC_LDDPC,
28571 +  AVR32_OPC_LDDPC_EXT,
28572 +  AVR32_OPC_LDDSP,
28573 +  AVR32_OPC_LDINS_B,
28574 +  AVR32_OPC_LDINS_H,
28575 +  AVR32_OPC_LDM,
28576 +  AVR32_OPC_LDMTS,
28577 +  AVR32_OPC_LDMTS_PU,
28578 +  AVR32_OPC_LDSWP_SH,
28579 +  AVR32_OPC_LDSWP_UH,
28580 +  AVR32_OPC_LDSWP_W,
28581 +  AVR32_OPC_LSL1,
28582 +  AVR32_OPC_LSL3,
28583 +  AVR32_OPC_LSL2,
28584 +  AVR32_OPC_LSR1,
28585 +  AVR32_OPC_LSR3,
28586 +  AVR32_OPC_LSR2,
28587 +  AVR32_OPC_MAC,
28588 +  AVR32_OPC_MACHH_D,
28589 +  AVR32_OPC_MACHH_W,
28590 +  AVR32_OPC_MACS_D,
28591 +  AVR32_OPC_MACSATHH_W,
28592 +  AVR32_OPC_MACUD,
28593 +  AVR32_OPC_MACWH_D,
28594 +  AVR32_OPC_MAX,
28595 +  AVR32_OPC_MCALL,
28596 +  AVR32_OPC_MFDR,
28597 +  AVR32_OPC_MFSR,
28598 +  AVR32_OPC_MIN,
28599 +  AVR32_OPC_MOV3,
28600 +  AVR32_OPC_MOV1,
28601 +  AVR32_OPC_MOV2,
28602 +  AVR32_OPC_MOVEQ1,
28603 +  AVR32_OPC_MOVNE1,
28604 +  AVR32_OPC_MOVCC1,
28605 +  AVR32_OPC_MOVCS1,
28606 +  AVR32_OPC_MOVGE1,
28607 +  AVR32_OPC_MOVLT1,
28608 +  AVR32_OPC_MOVMI1,
28609 +  AVR32_OPC_MOVPL1,
28610 +  AVR32_OPC_MOVLS1,
28611 +  AVR32_OPC_MOVGT1,
28612 +  AVR32_OPC_MOVLE1,
28613 +  AVR32_OPC_MOVHI1,
28614 +  AVR32_OPC_MOVVS1,
28615 +  AVR32_OPC_MOVVC1,
28616 +  AVR32_OPC_MOVQS1,
28617 +  AVR32_OPC_MOVAL1,
28618 +  AVR32_OPC_MOVEQ2,
28619 +  AVR32_OPC_MOVNE2,
28620 +  AVR32_OPC_MOVCC2,
28621 +  AVR32_OPC_MOVCS2,
28622 +  AVR32_OPC_MOVGE2,
28623 +  AVR32_OPC_MOVLT2,
28624 +  AVR32_OPC_MOVMI2,
28625 +  AVR32_OPC_MOVPL2,
28626 +  AVR32_OPC_MOVLS2,
28627 +  AVR32_OPC_MOVGT2,
28628 +  AVR32_OPC_MOVLE2,
28629 +  AVR32_OPC_MOVHI2,
28630 +  AVR32_OPC_MOVVS2,
28631 +  AVR32_OPC_MOVVC2,
28632 +  AVR32_OPC_MOVQS2,
28633 +  AVR32_OPC_MOVAL2,
28634 +  AVR32_OPC_MTDR,
28635 +  AVR32_OPC_MTSR,
28636 +  AVR32_OPC_MUL1,
28637 +  AVR32_OPC_MUL2,
28638 +  AVR32_OPC_MUL3,
28639 +  AVR32_OPC_MULHH_W,
28640 +  AVR32_OPC_MULNHH_W,
28641 +  AVR32_OPC_MULNWH_D,
28642 +  AVR32_OPC_MULSD,
28643 +  AVR32_OPC_MULSATHH_H,
28644 +  AVR32_OPC_MULSATHH_W,
28645 +  AVR32_OPC_MULSATRNDHH_H,
28646 +  AVR32_OPC_MULSATRNDWH_W,
28647 +  AVR32_OPC_MULSATWH_W,
28648 +  AVR32_OPC_MULU_D,
28649 +  AVR32_OPC_MULWH_D,
28650 +  AVR32_OPC_MUSFR,
28651 +  AVR32_OPC_MUSTR,
28652 +  AVR32_OPC_MVCR_D,
28653 +  AVR32_OPC_MVCR_W,
28654 +  AVR32_OPC_MVRC_D,
28655 +  AVR32_OPC_MVRC_W,
28656 +  AVR32_OPC_NEG,
28657 +  AVR32_OPC_NOP,
28658 +  AVR32_OPC_OR1,
28659 +  AVR32_OPC_OR2,
28660 +  AVR32_OPC_OR3,
28661 +  AVR32_OPC_ORH,
28662 +  AVR32_OPC_ORL,
28663 +  AVR32_OPC_PABS_SB,
28664 +  AVR32_OPC_PABS_SH,
28665 +  AVR32_OPC_PACKSH_SB,
28666 +  AVR32_OPC_PACKSH_UB,
28667 +  AVR32_OPC_PACKW_SH,
28668 +  AVR32_OPC_PADD_B,
28669 +  AVR32_OPC_PADD_H,
28670 +  AVR32_OPC_PADDH_SH,
28671 +  AVR32_OPC_PADDH_UB,
28672 +  AVR32_OPC_PADDS_SB,
28673 +  AVR32_OPC_PADDS_SH,
28674 +  AVR32_OPC_PADDS_UB,
28675 +  AVR32_OPC_PADDS_UH,
28676 +  AVR32_OPC_PADDSUB_H,
28677 +  AVR32_OPC_PADDSUBH_SH,
28678 +  AVR32_OPC_PADDSUBS_SH,
28679 +  AVR32_OPC_PADDSUBS_UH,
28680 +  AVR32_OPC_PADDX_H,
28681 +  AVR32_OPC_PADDXH_SH,
28682 +  AVR32_OPC_PADDXS_SH,
28683 +  AVR32_OPC_PADDXS_UH,
28684 +  AVR32_OPC_PASR_B,
28685 +  AVR32_OPC_PASR_H,
28686 +  AVR32_OPC_PAVG_SH,
28687 +  AVR32_OPC_PAVG_UB,
28688 +  AVR32_OPC_PLSL_B,
28689 +  AVR32_OPC_PLSL_H,
28690 +  AVR32_OPC_PLSR_B,
28691 +  AVR32_OPC_PLSR_H,
28692 +  AVR32_OPC_PMAX_SH,
28693 +  AVR32_OPC_PMAX_UB,
28694 +  AVR32_OPC_PMIN_SH,
28695 +  AVR32_OPC_PMIN_UB,
28696 +  AVR32_OPC_POPJC,
28697 +  AVR32_OPC_POPM,
28698 +  AVR32_OPC_POPM_E,
28699 +  AVR32_OPC_PREF,
28700 +  AVR32_OPC_PSAD,
28701 +  AVR32_OPC_PSUB_B,
28702 +  AVR32_OPC_PSUB_H,
28703 +  AVR32_OPC_PSUBADD_H,
28704 +  AVR32_OPC_PSUBADDH_SH,
28705 +  AVR32_OPC_PSUBADDS_SH,
28706 +  AVR32_OPC_PSUBADDS_UH,
28707 +  AVR32_OPC_PSUBH_SH,
28708 +  AVR32_OPC_PSUBH_UB,
28709 +  AVR32_OPC_PSUBS_SB,
28710 +  AVR32_OPC_PSUBS_SH,
28711 +  AVR32_OPC_PSUBS_UB,
28712 +  AVR32_OPC_PSUBS_UH,
28713 +  AVR32_OPC_PSUBX_H,
28714 +  AVR32_OPC_PSUBXH_SH,
28715 +  AVR32_OPC_PSUBXS_SH,
28716 +  AVR32_OPC_PSUBXS_UH,
28717 +  AVR32_OPC_PUNPCKSB_H,
28718 +  AVR32_OPC_PUNPCKUB_H,
28719 +  AVR32_OPC_PUSHJC,
28720 +  AVR32_OPC_PUSHM,
28721 +  AVR32_OPC_PUSHM_E,
28722 +  AVR32_OPC_RCALL1,
28723 +  AVR32_OPC_RCALL2,
28724 +  AVR32_OPC_RETEQ,
28725 +  AVR32_OPC_RETNE,
28726 +  AVR32_OPC_RETCC,
28727 +  AVR32_OPC_RETCS,
28728 +  AVR32_OPC_RETGE,
28729 +  AVR32_OPC_RETLT,
28730 +  AVR32_OPC_RETMI,
28731 +  AVR32_OPC_RETPL,
28732 +  AVR32_OPC_RETLS,
28733 +  AVR32_OPC_RETGT,
28734 +  AVR32_OPC_RETLE,
28735 +  AVR32_OPC_RETHI,
28736 +  AVR32_OPC_RETVS,
28737 +  AVR32_OPC_RETVC,
28738 +  AVR32_OPC_RETQS,
28739 +  AVR32_OPC_RETAL,
28740 +  AVR32_OPC_RETD,
28741 +  AVR32_OPC_RETE,
28742 +  AVR32_OPC_RETJ,
28743 +  AVR32_OPC_RETS,
28744 +  AVR32_OPC_RJMP,
28745 +  AVR32_OPC_ROL,
28746 +  AVR32_OPC_ROR,
28747 +  AVR32_OPC_RSUB1,
28748 +  AVR32_OPC_RSUB2,
28749 +  AVR32_OPC_SATADD_H,
28750 +  AVR32_OPC_SATADD_W,
28751 +  AVR32_OPC_SATRNDS,
28752 +  AVR32_OPC_SATRNDU,
28753 +  AVR32_OPC_SATS,
28754 +  AVR32_OPC_SATSUB_H,
28755 +  AVR32_OPC_SATSUB_W1,
28756 +  AVR32_OPC_SATSUB_W2,
28757 +  AVR32_OPC_SATU,
28758 +  AVR32_OPC_SBC,
28759 +  AVR32_OPC_SBR,
28760 +  AVR32_OPC_SCALL,
28761 +  AVR32_OPC_SCR,
28762 +  AVR32_OPC_SLEEP,
28763 +  AVR32_OPC_SREQ,
28764 +  AVR32_OPC_SRNE,
28765 +  AVR32_OPC_SRCC,
28766 +  AVR32_OPC_SRCS,
28767 +  AVR32_OPC_SRGE,
28768 +  AVR32_OPC_SRLT,
28769 +  AVR32_OPC_SRMI,
28770 +  AVR32_OPC_SRPL,
28771 +  AVR32_OPC_SRLS,
28772 +  AVR32_OPC_SRGT,
28773 +  AVR32_OPC_SRLE,
28774 +  AVR32_OPC_SRHI,
28775 +  AVR32_OPC_SRVS,
28776 +  AVR32_OPC_SRVC,
28777 +  AVR32_OPC_SRQS,
28778 +  AVR32_OPC_SRAL,
28779 +  AVR32_OPC_SSRF,
28780 +  AVR32_OPC_ST_B1,
28781 +  AVR32_OPC_ST_B2,
28782 +  AVR32_OPC_ST_B5,
28783 +  AVR32_OPC_ST_B3,
28784 +  AVR32_OPC_ST_B4,
28785 +  AVR32_OPC_ST_D1,
28786 +  AVR32_OPC_ST_D2,
28787 +  AVR32_OPC_ST_D3,
28788 +  AVR32_OPC_ST_D5,
28789 +  AVR32_OPC_ST_D4,
28790 +  AVR32_OPC_ST_H1,
28791 +  AVR32_OPC_ST_H2,
28792 +  AVR32_OPC_ST_H5,
28793 +  AVR32_OPC_ST_H3,
28794 +  AVR32_OPC_ST_H4,
28795 +  AVR32_OPC_ST_W1,
28796 +  AVR32_OPC_ST_W2,
28797 +  AVR32_OPC_ST_W5,
28798 +  AVR32_OPC_ST_W3,
28799 +  AVR32_OPC_ST_W4,
28800 +  AVR32_OPC_STC_D1,
28801 +  AVR32_OPC_STC_D2,
28802 +  AVR32_OPC_STC_D3,
28803 +  AVR32_OPC_STC_W1,
28804 +  AVR32_OPC_STC_W2,
28805 +  AVR32_OPC_STC_W3,
28806 +  AVR32_OPC_STC0_D,
28807 +  AVR32_OPC_STC0_W,
28808 +  AVR32_OPC_STCM_D,
28809 +  AVR32_OPC_STCM_D_PU,
28810 +  AVR32_OPC_STCM_W,
28811 +  AVR32_OPC_STCM_W_PU,
28812 +  AVR32_OPC_STCOND,
28813 +  AVR32_OPC_STDSP,
28814 +  AVR32_OPC_STHH_W2,
28815 +  AVR32_OPC_STHH_W1,
28816 +  AVR32_OPC_STM,
28817 +  AVR32_OPC_STM_PU,
28818 +  AVR32_OPC_STMTS,
28819 +  AVR32_OPC_STMTS_PU,
28820 +  AVR32_OPC_STSWP_H,
28821 +  AVR32_OPC_STSWP_W,
28822 +  AVR32_OPC_SUB1,
28823 +  AVR32_OPC_SUB2,
28824 +  AVR32_OPC_SUB5,
28825 +  AVR32_OPC_SUB3_SP,
28826 +  AVR32_OPC_SUB3,
28827 +  AVR32_OPC_SUB4,
28828 +  AVR32_OPC_SUBEQ,
28829 +  AVR32_OPC_SUBNE,
28830 +  AVR32_OPC_SUBCC,
28831 +  AVR32_OPC_SUBCS,
28832 +  AVR32_OPC_SUBGE,
28833 +  AVR32_OPC_SUBLT,
28834 +  AVR32_OPC_SUBMI,
28835 +  AVR32_OPC_SUBPL,
28836 +  AVR32_OPC_SUBLS,
28837 +  AVR32_OPC_SUBGT,
28838 +  AVR32_OPC_SUBLE,
28839 +  AVR32_OPC_SUBHI,
28840 +  AVR32_OPC_SUBVS,
28841 +  AVR32_OPC_SUBVC,
28842 +  AVR32_OPC_SUBQS,
28843 +  AVR32_OPC_SUBAL,
28844 +  AVR32_OPC_SUBFEQ,
28845 +  AVR32_OPC_SUBFNE,
28846 +  AVR32_OPC_SUBFCC,
28847 +  AVR32_OPC_SUBFCS,
28848 +  AVR32_OPC_SUBFGE,
28849 +  AVR32_OPC_SUBFLT,
28850 +  AVR32_OPC_SUBFMI,
28851 +  AVR32_OPC_SUBFPL,
28852 +  AVR32_OPC_SUBFLS,
28853 +  AVR32_OPC_SUBFGT,
28854 +  AVR32_OPC_SUBFLE,
28855 +  AVR32_OPC_SUBFHI,
28856 +  AVR32_OPC_SUBFVS,
28857 +  AVR32_OPC_SUBFVC,
28858 +  AVR32_OPC_SUBFQS,
28859 +  AVR32_OPC_SUBFAL,
28860 +  AVR32_OPC_SUBHH_W,
28861 +  AVR32_OPC_SWAP_B,
28862 +  AVR32_OPC_SWAP_BH,
28863 +  AVR32_OPC_SWAP_H,
28864 +  AVR32_OPC_SYNC,
28865 +  AVR32_OPC_TLBR,
28866 +  AVR32_OPC_TLBS,
28867 +  AVR32_OPC_TLBW,
28868 +  AVR32_OPC_TNBZ,
28869 +  AVR32_OPC_TST,
28870 +  AVR32_OPC_XCHG,
28871 +  AVR32_OPC_MEMC,
28872 +  AVR32_OPC_MEMS,
28873 +  AVR32_OPC_MEMT,
28874 +  AVR32_OPC_BFEXTS,
28875 +  AVR32_OPC_BFEXTU,
28876 +  AVR32_OPC_BFINS,
28877 +  AVR32_OPC_RSUBEQ,
28878 +  AVR32_OPC_RSUBNE,
28879 +  AVR32_OPC_RSUBCC,
28880 +  AVR32_OPC_RSUBCS,
28881 +  AVR32_OPC_RSUBGE,
28882 +  AVR32_OPC_RSUBLT,
28883 +  AVR32_OPC_RSUBMI,
28884 +  AVR32_OPC_RSUBPL,
28885 +  AVR32_OPC_RSUBLS,
28886 +  AVR32_OPC_RSUBGT,
28887 +  AVR32_OPC_RSUBLE,
28888 +  AVR32_OPC_RSUBHI,
28889 +  AVR32_OPC_RSUBVS,
28890 +  AVR32_OPC_RSUBVC,
28891 +  AVR32_OPC_RSUBQS,
28892 +  AVR32_OPC_RSUBAL,
28893 +  AVR32_OPC_ADDEQ,
28894 +  AVR32_OPC_ADDNE,
28895 +  AVR32_OPC_ADDCC,
28896 +  AVR32_OPC_ADDCS,
28897 +  AVR32_OPC_ADDGE,
28898 +  AVR32_OPC_ADDLT,
28899 +  AVR32_OPC_ADDMI,
28900 +  AVR32_OPC_ADDPL,
28901 +  AVR32_OPC_ADDLS,
28902 +  AVR32_OPC_ADDGT,
28903 +  AVR32_OPC_ADDLE,
28904 +  AVR32_OPC_ADDHI,
28905 +  AVR32_OPC_ADDVS,
28906 +  AVR32_OPC_ADDVC,
28907 +  AVR32_OPC_ADDQS,
28908 +  AVR32_OPC_ADDAL,
28909 +  AVR32_OPC_SUB2EQ,
28910 +  AVR32_OPC_SUB2NE,
28911 +  AVR32_OPC_SUB2CC,
28912 +  AVR32_OPC_SUB2CS,
28913 +  AVR32_OPC_SUB2GE,
28914 +  AVR32_OPC_SUB2LT,
28915 +  AVR32_OPC_SUB2MI,
28916 +  AVR32_OPC_SUB2PL,
28917 +  AVR32_OPC_SUB2LS,
28918 +  AVR32_OPC_SUB2GT,
28919 +  AVR32_OPC_SUB2LE,
28920 +  AVR32_OPC_SUB2HI,
28921 +  AVR32_OPC_SUB2VS,
28922 +  AVR32_OPC_SUB2VC,
28923 +  AVR32_OPC_SUB2QS,
28924 +  AVR32_OPC_SUB2AL,
28925 +  AVR32_OPC_ANDEQ,
28926 +  AVR32_OPC_ANDNE,
28927 +  AVR32_OPC_ANDCC,
28928 +  AVR32_OPC_ANDCS,
28929 +  AVR32_OPC_ANDGE,
28930 +  AVR32_OPC_ANDLT,
28931 +  AVR32_OPC_ANDMI,
28932 +  AVR32_OPC_ANDPL,
28933 +  AVR32_OPC_ANDLS,
28934 +  AVR32_OPC_ANDGT,
28935 +  AVR32_OPC_ANDLE,
28936 +  AVR32_OPC_ANDHI,
28937 +  AVR32_OPC_ANDVS,
28938 +  AVR32_OPC_ANDVC,
28939 +  AVR32_OPC_ANDQS,
28940 +  AVR32_OPC_ANDAL,
28941 +  AVR32_OPC_OREQ,
28942 +  AVR32_OPC_ORNE,
28943 +  AVR32_OPC_ORCC,
28944 +  AVR32_OPC_ORCS,
28945 +  AVR32_OPC_ORGE,
28946 +  AVR32_OPC_ORLT,
28947 +  AVR32_OPC_ORMI,
28948 +  AVR32_OPC_ORPL,
28949 +  AVR32_OPC_ORLS,
28950 +  AVR32_OPC_ORGT,
28951 +  AVR32_OPC_ORLE,
28952 +  AVR32_OPC_ORHI,
28953 +  AVR32_OPC_ORVS,
28954 +  AVR32_OPC_ORVC,
28955 +  AVR32_OPC_ORQS,
28956 +  AVR32_OPC_ORAL,
28957 +  AVR32_OPC_EOREQ,
28958 +  AVR32_OPC_EORNE,
28959 +  AVR32_OPC_EORCC,
28960 +  AVR32_OPC_EORCS,
28961 +  AVR32_OPC_EORGE,
28962 +  AVR32_OPC_EORLT,
28963 +  AVR32_OPC_EORMI,
28964 +  AVR32_OPC_EORPL,
28965 +  AVR32_OPC_EORLS,
28966 +  AVR32_OPC_EORGT,
28967 +  AVR32_OPC_EORLE,
28968 +  AVR32_OPC_EORHI,
28969 +  AVR32_OPC_EORVS,
28970 +  AVR32_OPC_EORVC,
28971 +  AVR32_OPC_EORQS,
28972 +  AVR32_OPC_EORAL,
28973 +  AVR32_OPC_LD_WEQ,
28974 +  AVR32_OPC_LD_WNE,
28975 +  AVR32_OPC_LD_WCC,
28976 +  AVR32_OPC_LD_WCS,
28977 +  AVR32_OPC_LD_WGE,
28978 +  AVR32_OPC_LD_WLT,
28979 +  AVR32_OPC_LD_WMI,
28980 +  AVR32_OPC_LD_WPL,
28981 +  AVR32_OPC_LD_WLS,
28982 +  AVR32_OPC_LD_WGT,
28983 +  AVR32_OPC_LD_WLE,
28984 +  AVR32_OPC_LD_WHI,
28985 +  AVR32_OPC_LD_WVS,
28986 +  AVR32_OPC_LD_WVC,
28987 +  AVR32_OPC_LD_WQS,
28988 +  AVR32_OPC_LD_WAL,
28989 +  AVR32_OPC_LD_SHEQ,
28990 +  AVR32_OPC_LD_SHNE,
28991 +  AVR32_OPC_LD_SHCC,
28992 +  AVR32_OPC_LD_SHCS,
28993 +  AVR32_OPC_LD_SHGE,
28994 +  AVR32_OPC_LD_SHLT,
28995 +  AVR32_OPC_LD_SHMI,
28996 +  AVR32_OPC_LD_SHPL,
28997 +  AVR32_OPC_LD_SHLS,
28998 +  AVR32_OPC_LD_SHGT,
28999 +  AVR32_OPC_LD_SHLE,
29000 +  AVR32_OPC_LD_SHHI,
29001 +  AVR32_OPC_LD_SHVS,
29002 +  AVR32_OPC_LD_SHVC,
29003 +  AVR32_OPC_LD_SHQS,
29004 +  AVR32_OPC_LD_SHAL,
29005 +  AVR32_OPC_LD_UHEQ,
29006 +  AVR32_OPC_LD_UHNE,
29007 +  AVR32_OPC_LD_UHCC,
29008 +  AVR32_OPC_LD_UHCS,
29009 +  AVR32_OPC_LD_UHGE,
29010 +  AVR32_OPC_LD_UHLT,
29011 +  AVR32_OPC_LD_UHMI,
29012 +  AVR32_OPC_LD_UHPL,
29013 +  AVR32_OPC_LD_UHLS,
29014 +  AVR32_OPC_LD_UHGT,
29015 +  AVR32_OPC_LD_UHLE,
29016 +  AVR32_OPC_LD_UHHI,
29017 +  AVR32_OPC_LD_UHVS,
29018 +  AVR32_OPC_LD_UHVC,
29019 +  AVR32_OPC_LD_UHQS,
29020 +  AVR32_OPC_LD_UHAL,
29021 +  AVR32_OPC_LD_SBEQ,
29022 +  AVR32_OPC_LD_SBNE,
29023 +  AVR32_OPC_LD_SBCC,
29024 +  AVR32_OPC_LD_SBCS,
29025 +  AVR32_OPC_LD_SBGE,
29026 +  AVR32_OPC_LD_SBLT,
29027 +  AVR32_OPC_LD_SBMI,
29028 +  AVR32_OPC_LD_SBPL,
29029 +  AVR32_OPC_LD_SBLS,
29030 +  AVR32_OPC_LD_SBGT,
29031 +  AVR32_OPC_LD_SBLE,
29032 +  AVR32_OPC_LD_SBHI,
29033 +  AVR32_OPC_LD_SBVS,
29034 +  AVR32_OPC_LD_SBVC,
29035 +  AVR32_OPC_LD_SBQS,
29036 +  AVR32_OPC_LD_SBAL,
29037 +  AVR32_OPC_LD_UBEQ,
29038 +  AVR32_OPC_LD_UBNE,
29039 +  AVR32_OPC_LD_UBCC,
29040 +  AVR32_OPC_LD_UBCS,
29041 +  AVR32_OPC_LD_UBGE,
29042 +  AVR32_OPC_LD_UBLT,
29043 +  AVR32_OPC_LD_UBMI,
29044 +  AVR32_OPC_LD_UBPL,
29045 +  AVR32_OPC_LD_UBLS,
29046 +  AVR32_OPC_LD_UBGT,
29047 +  AVR32_OPC_LD_UBLE,
29048 +  AVR32_OPC_LD_UBHI,
29049 +  AVR32_OPC_LD_UBVS,
29050 +  AVR32_OPC_LD_UBVC,
29051 +  AVR32_OPC_LD_UBQS,
29052 +  AVR32_OPC_LD_UBAL,
29053 +  AVR32_OPC_ST_WEQ,
29054 +  AVR32_OPC_ST_WNE,
29055 +  AVR32_OPC_ST_WCC,
29056 +  AVR32_OPC_ST_WCS,
29057 +  AVR32_OPC_ST_WGE,
29058 +  AVR32_OPC_ST_WLT,
29059 +  AVR32_OPC_ST_WMI,
29060 +  AVR32_OPC_ST_WPL,
29061 +  AVR32_OPC_ST_WLS,
29062 +  AVR32_OPC_ST_WGT,
29063 +  AVR32_OPC_ST_WLE,
29064 +  AVR32_OPC_ST_WHI,
29065 +  AVR32_OPC_ST_WVS,
29066 +  AVR32_OPC_ST_WVC,
29067 +  AVR32_OPC_ST_WQS,
29068 +  AVR32_OPC_ST_WAL,
29069 +  AVR32_OPC_ST_HEQ,
29070 +  AVR32_OPC_ST_HNE,
29071 +  AVR32_OPC_ST_HCC,
29072 +  AVR32_OPC_ST_HCS,
29073 +  AVR32_OPC_ST_HGE,
29074 +  AVR32_OPC_ST_HLT,
29075 +  AVR32_OPC_ST_HMI,
29076 +  AVR32_OPC_ST_HPL,
29077 +  AVR32_OPC_ST_HLS,
29078 +  AVR32_OPC_ST_HGT,
29079 +  AVR32_OPC_ST_HLE,
29080 +  AVR32_OPC_ST_HHI,
29081 +  AVR32_OPC_ST_HVS,
29082 +  AVR32_OPC_ST_HVC,
29083 +  AVR32_OPC_ST_HQS,
29084 +  AVR32_OPC_ST_HAL,
29085 +  AVR32_OPC_ST_BEQ,
29086 +  AVR32_OPC_ST_BNE,
29087 +  AVR32_OPC_ST_BCC,
29088 +  AVR32_OPC_ST_BCS,
29089 +  AVR32_OPC_ST_BGE,
29090 +  AVR32_OPC_ST_BLT,
29091 +  AVR32_OPC_ST_BMI,
29092 +  AVR32_OPC_ST_BPL,
29093 +  AVR32_OPC_ST_BLS,
29094 +  AVR32_OPC_ST_BGT,
29095 +  AVR32_OPC_ST_BLE,
29096 +  AVR32_OPC_ST_BHI,
29097 +  AVR32_OPC_ST_BVS,
29098 +  AVR32_OPC_ST_BVC,
29099 +  AVR32_OPC_ST_BQS,
29100 +  AVR32_OPC_ST_BAL,
29101 +  AVR32_OPC_MOVH,
29102 +  AVR32_OPC_SSCALL,
29103 +  AVR32_OPC_RETSS,
29104 +  AVR32_OPC__END_
29105 +};
29106 +#define AVR32_NR_OPCODES AVR32_OPC__END_
29107 +
29108 +enum avr32_syntax_type
29109 +{
29110 +  AVR32_SYNTAX_ABS,
29111 +  AVR32_SYNTAX_ACALL,
29112 +  AVR32_SYNTAX_ACR,
29113 +  AVR32_SYNTAX_ADC,
29114 +  AVR32_SYNTAX_ADD1,
29115 +  AVR32_SYNTAX_ADD2,
29116 +  AVR32_SYNTAX_ADDABS,
29117 +  AVR32_SYNTAX_ADDHH_W,
29118 +  AVR32_SYNTAX_AND1,
29119 +  AVR32_SYNTAX_AND2,
29120 +  AVR32_SYNTAX_AND3,
29121 +  AVR32_SYNTAX_ANDH,
29122 +  AVR32_SYNTAX_ANDH_COH,
29123 +  AVR32_SYNTAX_ANDL,
29124 +  AVR32_SYNTAX_ANDL_COH,
29125 +  AVR32_SYNTAX_ANDN,
29126 +  AVR32_SYNTAX_ASR1,
29127 +  AVR32_SYNTAX_ASR3,
29128 +  AVR32_SYNTAX_ASR2,
29129 +  AVR32_SYNTAX_BFEXTS,
29130 +  AVR32_SYNTAX_BFEXTU,
29131 +  AVR32_SYNTAX_BFINS,
29132 +  AVR32_SYNTAX_BLD,
29133 +  AVR32_SYNTAX_BREQ1,
29134 +  AVR32_SYNTAX_BRNE1,
29135 +  AVR32_SYNTAX_BRCC1,
29136 +  AVR32_SYNTAX_BRCS1,
29137 +  AVR32_SYNTAX_BRGE1,
29138 +  AVR32_SYNTAX_BRLT1,
29139 +  AVR32_SYNTAX_BRMI1,
29140 +  AVR32_SYNTAX_BRPL1,
29141 +  AVR32_SYNTAX_BRHS1,
29142 +  AVR32_SYNTAX_BRLO1,
29143 +  AVR32_SYNTAX_BREQ2,
29144 +  AVR32_SYNTAX_BRNE2,
29145 +  AVR32_SYNTAX_BRCC2,
29146 +  AVR32_SYNTAX_BRCS2,
29147 +  AVR32_SYNTAX_BRGE2,
29148 +  AVR32_SYNTAX_BRLT2,
29149 +  AVR32_SYNTAX_BRMI2,
29150 +  AVR32_SYNTAX_BRPL2,
29151 +  AVR32_SYNTAX_BRLS,
29152 +  AVR32_SYNTAX_BRGT,
29153 +  AVR32_SYNTAX_BRLE,
29154 +  AVR32_SYNTAX_BRHI,
29155 +  AVR32_SYNTAX_BRVS,
29156 +  AVR32_SYNTAX_BRVC,
29157 +  AVR32_SYNTAX_BRQS,
29158 +  AVR32_SYNTAX_BRAL,
29159 +  AVR32_SYNTAX_BRHS2,
29160 +  AVR32_SYNTAX_BRLO2,
29161 +  AVR32_SYNTAX_BREAKPOINT,
29162 +  AVR32_SYNTAX_BREV,
29163 +  AVR32_SYNTAX_BST,
29164 +  AVR32_SYNTAX_CACHE,
29165 +  AVR32_SYNTAX_CASTS_B,
29166 +  AVR32_SYNTAX_CASTS_H,
29167 +  AVR32_SYNTAX_CASTU_B,
29168 +  AVR32_SYNTAX_CASTU_H,
29169 +  AVR32_SYNTAX_CBR,
29170 +  AVR32_SYNTAX_CLZ,
29171 +  AVR32_SYNTAX_COM,
29172 +  AVR32_SYNTAX_COP,
29173 +  AVR32_SYNTAX_CP_B,
29174 +  AVR32_SYNTAX_CP_H,
29175 +  AVR32_SYNTAX_CP_W1,
29176 +  AVR32_SYNTAX_CP_W2,
29177 +  AVR32_SYNTAX_CP_W3,
29178 +  AVR32_SYNTAX_CPC1,
29179 +  AVR32_SYNTAX_CPC2,
29180 +  AVR32_SYNTAX_CSRF,
29181 +  AVR32_SYNTAX_CSRFCZ,
29182 +  AVR32_SYNTAX_DIVS,
29183 +  AVR32_SYNTAX_DIVU,
29184 +  AVR32_SYNTAX_EOR1,
29185 +  AVR32_SYNTAX_EOR2,
29186 +  AVR32_SYNTAX_EOR3,
29187 +  AVR32_SYNTAX_EORL,
29188 +  AVR32_SYNTAX_EORH,
29189 +  AVR32_SYNTAX_FRS,
29190 +  AVR32_SYNTAX_SSCALL,
29191 +  AVR32_SYNTAX_RETSS,
29192 +  AVR32_SYNTAX_ICALL,
29193 +  AVR32_SYNTAX_INCJOSP,
29194 +  AVR32_SYNTAX_LD_D1,
29195 +  AVR32_SYNTAX_LD_D2,
29196 +  AVR32_SYNTAX_LD_D3,
29197 +  AVR32_SYNTAX_LD_D5,
29198 +  AVR32_SYNTAX_LD_D4,
29199 +  AVR32_SYNTAX_LD_SB2,
29200 +  AVR32_SYNTAX_LD_SB1,
29201 +  AVR32_SYNTAX_LD_UB1,
29202 +  AVR32_SYNTAX_LD_UB2,
29203 +  AVR32_SYNTAX_LD_UB5,
29204 +  AVR32_SYNTAX_LD_UB3,
29205 +  AVR32_SYNTAX_LD_UB4,
29206 +  AVR32_SYNTAX_LD_SH1,
29207 +  AVR32_SYNTAX_LD_SH2,
29208 +  AVR32_SYNTAX_LD_SH5,
29209 +  AVR32_SYNTAX_LD_SH3,
29210 +  AVR32_SYNTAX_LD_SH4,
29211 +  AVR32_SYNTAX_LD_UH1,
29212 +  AVR32_SYNTAX_LD_UH2,
29213 +  AVR32_SYNTAX_LD_UH5,
29214 +  AVR32_SYNTAX_LD_UH3,
29215 +  AVR32_SYNTAX_LD_UH4,
29216 +  AVR32_SYNTAX_LD_W1,
29217 +  AVR32_SYNTAX_LD_W2,
29218 +  AVR32_SYNTAX_LD_W5,
29219 +  AVR32_SYNTAX_LD_W6,
29220 +  AVR32_SYNTAX_LD_W3,
29221 +  AVR32_SYNTAX_LD_W4,
29222 +  AVR32_SYNTAX_LDC_D1,
29223 +  AVR32_SYNTAX_LDC_D2,
29224 +  AVR32_SYNTAX_LDC_D3,
29225 +  AVR32_SYNTAX_LDC_W1,
29226 +  AVR32_SYNTAX_LDC_W2,
29227 +  AVR32_SYNTAX_LDC_W3,
29228 +  AVR32_SYNTAX_LDC0_D,
29229 +  AVR32_SYNTAX_LDC0_W,
29230 +  AVR32_SYNTAX_LDCM_D,
29231 +  AVR32_SYNTAX_LDCM_D_PU,
29232 +  AVR32_SYNTAX_LDCM_W,
29233 +  AVR32_SYNTAX_LDCM_W_PU,
29234 +  AVR32_SYNTAX_LDDPC,
29235 +  AVR32_SYNTAX_LDDPC_EXT,
29236 +  AVR32_SYNTAX_LDDSP,
29237 +  AVR32_SYNTAX_LDINS_B,
29238 +  AVR32_SYNTAX_LDINS_H,
29239 +  AVR32_SYNTAX_LDM,
29240 +  AVR32_SYNTAX_LDMTS,
29241 +  AVR32_SYNTAX_LDMTS_PU,
29242 +  AVR32_SYNTAX_LDSWP_SH,
29243 +  AVR32_SYNTAX_LDSWP_UH,
29244 +  AVR32_SYNTAX_LDSWP_W,
29245 +  AVR32_SYNTAX_LSL1,
29246 +  AVR32_SYNTAX_LSL3,
29247 +  AVR32_SYNTAX_LSL2,
29248 +  AVR32_SYNTAX_LSR1,
29249 +  AVR32_SYNTAX_LSR3,
29250 +  AVR32_SYNTAX_LSR2,
29251 +  AVR32_SYNTAX_MAC,
29252 +  AVR32_SYNTAX_MACHH_D,
29253 +  AVR32_SYNTAX_MACHH_W,
29254 +  AVR32_SYNTAX_MACS_D,
29255 +  AVR32_SYNTAX_MACSATHH_W,
29256 +  AVR32_SYNTAX_MACUD,
29257 +  AVR32_SYNTAX_MACWH_D,
29258 +  AVR32_SYNTAX_MAX,
29259 +  AVR32_SYNTAX_MCALL,
29260 +  AVR32_SYNTAX_MFDR,
29261 +  AVR32_SYNTAX_MFSR,
29262 +  AVR32_SYNTAX_MIN,
29263 +  AVR32_SYNTAX_MOV3,
29264 +  AVR32_SYNTAX_MOV1,
29265 +  AVR32_SYNTAX_MOV2,
29266 +  AVR32_SYNTAX_MOVEQ1,
29267 +  AVR32_SYNTAX_MOVNE1,
29268 +  AVR32_SYNTAX_MOVCC1,
29269 +  AVR32_SYNTAX_MOVCS1,
29270 +  AVR32_SYNTAX_MOVGE1,
29271 +  AVR32_SYNTAX_MOVLT1,
29272 +  AVR32_SYNTAX_MOVMI1,
29273 +  AVR32_SYNTAX_MOVPL1,
29274 +  AVR32_SYNTAX_MOVLS1,
29275 +  AVR32_SYNTAX_MOVGT1,
29276 +  AVR32_SYNTAX_MOVLE1,
29277 +  AVR32_SYNTAX_MOVHI1,
29278 +  AVR32_SYNTAX_MOVVS1,
29279 +  AVR32_SYNTAX_MOVVC1,
29280 +  AVR32_SYNTAX_MOVQS1,
29281 +  AVR32_SYNTAX_MOVAL1,
29282 +  AVR32_SYNTAX_MOVHS1,
29283 +  AVR32_SYNTAX_MOVLO1,
29284 +  AVR32_SYNTAX_MOVEQ2,
29285 +  AVR32_SYNTAX_MOVNE2,
29286 +  AVR32_SYNTAX_MOVCC2,
29287 +  AVR32_SYNTAX_MOVCS2,
29288 +  AVR32_SYNTAX_MOVGE2,
29289 +  AVR32_SYNTAX_MOVLT2,
29290 +  AVR32_SYNTAX_MOVMI2,
29291 +  AVR32_SYNTAX_MOVPL2,
29292 +  AVR32_SYNTAX_MOVLS2,
29293 +  AVR32_SYNTAX_MOVGT2,
29294 +  AVR32_SYNTAX_MOVLE2,
29295 +  AVR32_SYNTAX_MOVHI2,
29296 +  AVR32_SYNTAX_MOVVS2,
29297 +  AVR32_SYNTAX_MOVVC2,
29298 +  AVR32_SYNTAX_MOVQS2,
29299 +  AVR32_SYNTAX_MOVAL2,
29300 +  AVR32_SYNTAX_MOVHS2,
29301 +  AVR32_SYNTAX_MOVLO2,
29302 +  AVR32_SYNTAX_MTDR,
29303 +  AVR32_SYNTAX_MTSR,
29304 +  AVR32_SYNTAX_MUL1,
29305 +  AVR32_SYNTAX_MUL2,
29306 +  AVR32_SYNTAX_MUL3,
29307 +  AVR32_SYNTAX_MULHH_W,
29308 +  AVR32_SYNTAX_MULNHH_W,
29309 +  AVR32_SYNTAX_MULNWH_D,
29310 +  AVR32_SYNTAX_MULSD,
29311 +  AVR32_SYNTAX_MULSATHH_H,
29312 +  AVR32_SYNTAX_MULSATHH_W,
29313 +  AVR32_SYNTAX_MULSATRNDHH_H,
29314 +  AVR32_SYNTAX_MULSATRNDWH_W,
29315 +  AVR32_SYNTAX_MULSATWH_W,
29316 +  AVR32_SYNTAX_MULU_D,
29317 +  AVR32_SYNTAX_MULWH_D,
29318 +  AVR32_SYNTAX_MUSFR,
29319 +  AVR32_SYNTAX_MUSTR,
29320 +  AVR32_SYNTAX_MVCR_D,
29321 +  AVR32_SYNTAX_MVCR_W,
29322 +  AVR32_SYNTAX_MVRC_D,
29323 +  AVR32_SYNTAX_MVRC_W,
29324 +  AVR32_SYNTAX_NEG,
29325 +  AVR32_SYNTAX_NOP,
29326 +  AVR32_SYNTAX_OR1,
29327 +  AVR32_SYNTAX_OR2,
29328 +  AVR32_SYNTAX_OR3,
29329 +  AVR32_SYNTAX_ORH,
29330 +  AVR32_SYNTAX_ORL,
29331 +  AVR32_SYNTAX_PABS_SB,
29332 +  AVR32_SYNTAX_PABS_SH,
29333 +  AVR32_SYNTAX_PACKSH_SB,
29334 +  AVR32_SYNTAX_PACKSH_UB,
29335 +  AVR32_SYNTAX_PACKW_SH,
29336 +  AVR32_SYNTAX_PADD_B,
29337 +  AVR32_SYNTAX_PADD_H,
29338 +  AVR32_SYNTAX_PADDH_SH,
29339 +  AVR32_SYNTAX_PADDH_UB,
29340 +  AVR32_SYNTAX_PADDS_SB,
29341 +  AVR32_SYNTAX_PADDS_SH,
29342 +  AVR32_SYNTAX_PADDS_UB,
29343 +  AVR32_SYNTAX_PADDS_UH,
29344 +  AVR32_SYNTAX_PADDSUB_H,
29345 +  AVR32_SYNTAX_PADDSUBH_SH,
29346 +  AVR32_SYNTAX_PADDSUBS_SH,
29347 +  AVR32_SYNTAX_PADDSUBS_UH,
29348 +  AVR32_SYNTAX_PADDX_H,
29349 +  AVR32_SYNTAX_PADDXH_SH,
29350 +  AVR32_SYNTAX_PADDXS_SH,
29351 +  AVR32_SYNTAX_PADDXS_UH,
29352 +  AVR32_SYNTAX_PASR_B,
29353 +  AVR32_SYNTAX_PASR_H,
29354 +  AVR32_SYNTAX_PAVG_SH,
29355 +  AVR32_SYNTAX_PAVG_UB,
29356 +  AVR32_SYNTAX_PLSL_B,
29357 +  AVR32_SYNTAX_PLSL_H,
29358 +  AVR32_SYNTAX_PLSR_B,
29359 +  AVR32_SYNTAX_PLSR_H,
29360 +  AVR32_SYNTAX_PMAX_SH,
29361 +  AVR32_SYNTAX_PMAX_UB,
29362 +  AVR32_SYNTAX_PMIN_SH,
29363 +  AVR32_SYNTAX_PMIN_UB,
29364 +  AVR32_SYNTAX_POPJC,
29365 +  AVR32_SYNTAX_POPM,
29366 +  AVR32_SYNTAX_POPM_E,
29367 +  AVR32_SYNTAX_PREF,
29368 +  AVR32_SYNTAX_PSAD,
29369 +  AVR32_SYNTAX_PSUB_B,
29370 +  AVR32_SYNTAX_PSUB_H,
29371 +  AVR32_SYNTAX_PSUBADD_H,
29372 +  AVR32_SYNTAX_PSUBADDH_SH,
29373 +  AVR32_SYNTAX_PSUBADDS_SH,
29374 +  AVR32_SYNTAX_PSUBADDS_UH,
29375 +  AVR32_SYNTAX_PSUBH_SH,
29376 +  AVR32_SYNTAX_PSUBH_UB,
29377 +  AVR32_SYNTAX_PSUBS_SB,
29378 +  AVR32_SYNTAX_PSUBS_SH,
29379 +  AVR32_SYNTAX_PSUBS_UB,
29380 +  AVR32_SYNTAX_PSUBS_UH,
29381 +  AVR32_SYNTAX_PSUBX_H,
29382 +  AVR32_SYNTAX_PSUBXH_SH,
29383 +  AVR32_SYNTAX_PSUBXS_SH,
29384 +  AVR32_SYNTAX_PSUBXS_UH,
29385 +  AVR32_SYNTAX_PUNPCKSB_H,
29386 +  AVR32_SYNTAX_PUNPCKUB_H,
29387 +  AVR32_SYNTAX_PUSHJC,
29388 +  AVR32_SYNTAX_PUSHM,
29389 +  AVR32_SYNTAX_PUSHM_E,
29390 +  AVR32_SYNTAX_RCALL1,
29391 +  AVR32_SYNTAX_RCALL2,
29392 +  AVR32_SYNTAX_RETEQ,
29393 +  AVR32_SYNTAX_RETNE,
29394 +  AVR32_SYNTAX_RETCC,
29395 +  AVR32_SYNTAX_RETCS,
29396 +  AVR32_SYNTAX_RETGE,
29397 +  AVR32_SYNTAX_RETLT,
29398 +  AVR32_SYNTAX_RETMI,
29399 +  AVR32_SYNTAX_RETPL,
29400 +  AVR32_SYNTAX_RETLS,
29401 +  AVR32_SYNTAX_RETGT,
29402 +  AVR32_SYNTAX_RETLE,
29403 +  AVR32_SYNTAX_RETHI,
29404 +  AVR32_SYNTAX_RETVS,
29405 +  AVR32_SYNTAX_RETVC,
29406 +  AVR32_SYNTAX_RETQS,
29407 +  AVR32_SYNTAX_RETAL,
29408 +  AVR32_SYNTAX_RETHS,
29409 +  AVR32_SYNTAX_RETLO,
29410 +  AVR32_SYNTAX_RETD,
29411 +  AVR32_SYNTAX_RETE,
29412 +  AVR32_SYNTAX_RETJ,
29413 +  AVR32_SYNTAX_RETS,
29414 +  AVR32_SYNTAX_RJMP,
29415 +  AVR32_SYNTAX_ROL,
29416 +  AVR32_SYNTAX_ROR,
29417 +  AVR32_SYNTAX_RSUB1,
29418 +  AVR32_SYNTAX_RSUB2,
29419 +  AVR32_SYNTAX_SATADD_H,
29420 +  AVR32_SYNTAX_SATADD_W,
29421 +  AVR32_SYNTAX_SATRNDS,
29422 +  AVR32_SYNTAX_SATRNDU,
29423 +  AVR32_SYNTAX_SATS,
29424 +  AVR32_SYNTAX_SATSUB_H,
29425 +  AVR32_SYNTAX_SATSUB_W1,
29426 +  AVR32_SYNTAX_SATSUB_W2,
29427 +  AVR32_SYNTAX_SATU,
29428 +  AVR32_SYNTAX_SBC,
29429 +  AVR32_SYNTAX_SBR,
29430 +  AVR32_SYNTAX_SCALL,
29431 +  AVR32_SYNTAX_SCR,
29432 +  AVR32_SYNTAX_SLEEP,
29433 +  AVR32_SYNTAX_SREQ,
29434 +  AVR32_SYNTAX_SRNE,
29435 +  AVR32_SYNTAX_SRCC,
29436 +  AVR32_SYNTAX_SRCS,
29437 +  AVR32_SYNTAX_SRGE,
29438 +  AVR32_SYNTAX_SRLT,
29439 +  AVR32_SYNTAX_SRMI,
29440 +  AVR32_SYNTAX_SRPL,
29441 +  AVR32_SYNTAX_SRLS,
29442 +  AVR32_SYNTAX_SRGT,
29443 +  AVR32_SYNTAX_SRLE,
29444 +  AVR32_SYNTAX_SRHI,
29445 +  AVR32_SYNTAX_SRVS,
29446 +  AVR32_SYNTAX_SRVC,
29447 +  AVR32_SYNTAX_SRQS,
29448 +  AVR32_SYNTAX_SRAL,
29449 +  AVR32_SYNTAX_SRHS,
29450 +  AVR32_SYNTAX_SRLO,
29451 +  AVR32_SYNTAX_SSRF,
29452 +  AVR32_SYNTAX_ST_B1,
29453 +  AVR32_SYNTAX_ST_B2,
29454 +  AVR32_SYNTAX_ST_B5,
29455 +  AVR32_SYNTAX_ST_B3,
29456 +  AVR32_SYNTAX_ST_B4,
29457 +  AVR32_SYNTAX_ST_D1,
29458 +  AVR32_SYNTAX_ST_D2,
29459 +  AVR32_SYNTAX_ST_D3,
29460 +  AVR32_SYNTAX_ST_D5,
29461 +  AVR32_SYNTAX_ST_D4,
29462 +  AVR32_SYNTAX_ST_H1,
29463 +  AVR32_SYNTAX_ST_H2,
29464 +  AVR32_SYNTAX_ST_H5,
29465 +  AVR32_SYNTAX_ST_H3,
29466 +  AVR32_SYNTAX_ST_H4,
29467 +  AVR32_SYNTAX_ST_W1,
29468 +  AVR32_SYNTAX_ST_W2,
29469 +  AVR32_SYNTAX_ST_W5,
29470 +  AVR32_SYNTAX_ST_W3,
29471 +  AVR32_SYNTAX_ST_W4,
29472 +  AVR32_SYNTAX_STC_D1,
29473 +  AVR32_SYNTAX_STC_D2,
29474 +  AVR32_SYNTAX_STC_D3,
29475 +  AVR32_SYNTAX_STC_W1,
29476 +  AVR32_SYNTAX_STC_W2,
29477 +  AVR32_SYNTAX_STC_W3,
29478 +  AVR32_SYNTAX_STC0_D,
29479 +  AVR32_SYNTAX_STC0_W,
29480 +  AVR32_SYNTAX_STCM_D,
29481 +  AVR32_SYNTAX_STCM_D_PU,
29482 +  AVR32_SYNTAX_STCM_W,
29483 +  AVR32_SYNTAX_STCM_W_PU,
29484 +  AVR32_SYNTAX_STCOND,
29485 +  AVR32_SYNTAX_STDSP,
29486 +  AVR32_SYNTAX_STHH_W2,
29487 +  AVR32_SYNTAX_STHH_W1,
29488 +  AVR32_SYNTAX_STM,
29489 +  AVR32_SYNTAX_STM_PU,
29490 +  AVR32_SYNTAX_STMTS,
29491 +  AVR32_SYNTAX_STMTS_PU,
29492 +  AVR32_SYNTAX_STSWP_H,
29493 +  AVR32_SYNTAX_STSWP_W,
29494 +  AVR32_SYNTAX_SUB1,
29495 +  AVR32_SYNTAX_SUB2,
29496 +  AVR32_SYNTAX_SUB5,
29497 +  AVR32_SYNTAX_SUB3_SP,
29498 +  AVR32_SYNTAX_SUB3,
29499 +  AVR32_SYNTAX_SUB4,
29500 +  AVR32_SYNTAX_SUBEQ,
29501 +  AVR32_SYNTAX_SUBNE,
29502 +  AVR32_SYNTAX_SUBCC,
29503 +  AVR32_SYNTAX_SUBCS,
29504 +  AVR32_SYNTAX_SUBGE,
29505 +  AVR32_SYNTAX_SUBLT,
29506 +  AVR32_SYNTAX_SUBMI,
29507 +  AVR32_SYNTAX_SUBPL,
29508 +  AVR32_SYNTAX_SUBLS,
29509 +  AVR32_SYNTAX_SUBGT,
29510 +  AVR32_SYNTAX_SUBLE,
29511 +  AVR32_SYNTAX_SUBHI,
29512 +  AVR32_SYNTAX_SUBVS,
29513 +  AVR32_SYNTAX_SUBVC,
29514 +  AVR32_SYNTAX_SUBQS,
29515 +  AVR32_SYNTAX_SUBAL,
29516 +  AVR32_SYNTAX_SUBHS,
29517 +  AVR32_SYNTAX_SUBLO,
29518 +  AVR32_SYNTAX_SUBFEQ,
29519 +  AVR32_SYNTAX_SUBFNE,
29520 +  AVR32_SYNTAX_SUBFCC,
29521 +  AVR32_SYNTAX_SUBFCS,
29522 +  AVR32_SYNTAX_SUBFGE,
29523 +  AVR32_SYNTAX_SUBFLT,
29524 +  AVR32_SYNTAX_SUBFMI,
29525 +  AVR32_SYNTAX_SUBFPL,
29526 +  AVR32_SYNTAX_SUBFLS,
29527 +  AVR32_SYNTAX_SUBFGT,
29528 +  AVR32_SYNTAX_SUBFLE,
29529 +  AVR32_SYNTAX_SUBFHI,
29530 +  AVR32_SYNTAX_SUBFVS,
29531 +  AVR32_SYNTAX_SUBFVC,
29532 +  AVR32_SYNTAX_SUBFQS,
29533 +  AVR32_SYNTAX_SUBFAL,
29534 +  AVR32_SYNTAX_SUBFHS,
29535 +  AVR32_SYNTAX_SUBFLO,
29536 +  AVR32_SYNTAX_SUBHH_W,
29537 +  AVR32_SYNTAX_SWAP_B,
29538 +  AVR32_SYNTAX_SWAP_BH,
29539 +  AVR32_SYNTAX_SWAP_H,
29540 +  AVR32_SYNTAX_SYNC,
29541 +  AVR32_SYNTAX_TLBR,
29542 +  AVR32_SYNTAX_TLBS,
29543 +  AVR32_SYNTAX_TLBW,
29544 +  AVR32_SYNTAX_TNBZ,
29545 +  AVR32_SYNTAX_TST,
29546 +  AVR32_SYNTAX_XCHG,
29547 +  AVR32_SYNTAX_MEMC,
29548 +  AVR32_SYNTAX_MEMS,
29549 +  AVR32_SYNTAX_MEMT,
29550 +  AVR32_SYNTAX_FADD_S,
29551 +  AVR32_SYNTAX_FADD_D,
29552 +  AVR32_SYNTAX_FSUB_S,
29553 +  AVR32_SYNTAX_FSUB_D,
29554 +  AVR32_SYNTAX_FMAC_S,
29555 +  AVR32_SYNTAX_FMAC_D,
29556 +  AVR32_SYNTAX_FNMAC_S,
29557 +  AVR32_SYNTAX_FNMAC_D,
29558 +  AVR32_SYNTAX_FMSC_S,
29559 +  AVR32_SYNTAX_FMSC_D,
29560 +  AVR32_SYNTAX_FNMSC_S,
29561 +  AVR32_SYNTAX_FNMSC_D,
29562 +  AVR32_SYNTAX_FMUL_S,
29563 +  AVR32_SYNTAX_FMUL_D,
29564 +  AVR32_SYNTAX_FNMUL_S,
29565 +  AVR32_SYNTAX_FNMUL_D,
29566 +  AVR32_SYNTAX_FNEG_S,
29567 +  AVR32_SYNTAX_FNEG_D,
29568 +  AVR32_SYNTAX_FABS_S,
29569 +  AVR32_SYNTAX_FABS_D,
29570 +  AVR32_SYNTAX_FCMP_S,
29571 +  AVR32_SYNTAX_FCMP_D,
29572 +  AVR32_SYNTAX_FMOV1_S,
29573 +  AVR32_SYNTAX_FMOV1_D,
29574 +  AVR32_SYNTAX_FMOV2_S,
29575 +  AVR32_SYNTAX_FMOV2_D,
29576 +  AVR32_SYNTAX_FMOV3_S,
29577 +  AVR32_SYNTAX_FMOV3_D,
29578 +  AVR32_SYNTAX_FCASTS_D,
29579 +  AVR32_SYNTAX_FCASTD_S,
29580 +  AVR32_SYNTAX_LDA_W,
29581 +  AVR32_SYNTAX_CALL,
29582 +  AVR32_SYNTAX_PICOSVMAC0,
29583 +  AVR32_SYNTAX_PICOSVMAC1,
29584 +  AVR32_SYNTAX_PICOSVMAC2,
29585 +  AVR32_SYNTAX_PICOSVMAC3,
29586 +  AVR32_SYNTAX_PICOSVMUL0,
29587 +  AVR32_SYNTAX_PICOSVMUL1,
29588 +  AVR32_SYNTAX_PICOSVMUL2,
29589 +  AVR32_SYNTAX_PICOSVMUL3,
29590 +  AVR32_SYNTAX_PICOVMAC0,
29591 +  AVR32_SYNTAX_PICOVMAC1,
29592 +  AVR32_SYNTAX_PICOVMAC2,
29593 +  AVR32_SYNTAX_PICOVMAC3,
29594 +  AVR32_SYNTAX_PICOVMUL0,
29595 +  AVR32_SYNTAX_PICOVMUL1,
29596 +  AVR32_SYNTAX_PICOVMUL2,
29597 +  AVR32_SYNTAX_PICOVMUL3,
29598 +  AVR32_SYNTAX_PICOLD_D2,
29599 +  AVR32_SYNTAX_PICOLD_D3,
29600 +  AVR32_SYNTAX_PICOLD_D1,
29601 +  AVR32_SYNTAX_PICOLD_W2,
29602 +  AVR32_SYNTAX_PICOLD_W3,
29603 +  AVR32_SYNTAX_PICOLD_W1,
29604 +  AVR32_SYNTAX_PICOLDM_D,
29605 +  AVR32_SYNTAX_PICOLDM_D_PU,
29606 +  AVR32_SYNTAX_PICOLDM_W,
29607 +  AVR32_SYNTAX_PICOLDM_W_PU,
29608 +  AVR32_SYNTAX_PICOMV_D1,
29609 +  AVR32_SYNTAX_PICOMV_D2,
29610 +  AVR32_SYNTAX_PICOMV_W1,
29611 +  AVR32_SYNTAX_PICOMV_W2,
29612 +  AVR32_SYNTAX_PICOST_D2,
29613 +  AVR32_SYNTAX_PICOST_D3,
29614 +  AVR32_SYNTAX_PICOST_D1,
29615 +  AVR32_SYNTAX_PICOST_W2,
29616 +  AVR32_SYNTAX_PICOST_W3,
29617 +  AVR32_SYNTAX_PICOST_W1,
29618 +  AVR32_SYNTAX_PICOSTM_D,
29619 +  AVR32_SYNTAX_PICOSTM_D_PU,
29620 +  AVR32_SYNTAX_PICOSTM_W,
29621 +  AVR32_SYNTAX_PICOSTM_W_PU,
29622 +  AVR32_SYNTAX_RSUBEQ,
29623 +  AVR32_SYNTAX_RSUBNE,
29624 +  AVR32_SYNTAX_RSUBCC,
29625 +  AVR32_SYNTAX_RSUBCS,
29626 +  AVR32_SYNTAX_RSUBGE,
29627 +  AVR32_SYNTAX_RSUBLT,
29628 +  AVR32_SYNTAX_RSUBMI,
29629 +  AVR32_SYNTAX_RSUBPL,
29630 +  AVR32_SYNTAX_RSUBLS,
29631 +  AVR32_SYNTAX_RSUBGT,
29632 +  AVR32_SYNTAX_RSUBLE,
29633 +  AVR32_SYNTAX_RSUBHI,
29634 +  AVR32_SYNTAX_RSUBVS,
29635 +  AVR32_SYNTAX_RSUBVC,
29636 +  AVR32_SYNTAX_RSUBQS,
29637 +  AVR32_SYNTAX_RSUBAL,
29638 +  AVR32_SYNTAX_RSUBHS,
29639 +  AVR32_SYNTAX_RSUBLO,
29640 +  AVR32_SYNTAX_ADDEQ,
29641 +  AVR32_SYNTAX_ADDNE,
29642 +  AVR32_SYNTAX_ADDCC,
29643 +  AVR32_SYNTAX_ADDCS,
29644 +  AVR32_SYNTAX_ADDGE,
29645 +  AVR32_SYNTAX_ADDLT,
29646 +  AVR32_SYNTAX_ADDMI,
29647 +  AVR32_SYNTAX_ADDPL,
29648 +  AVR32_SYNTAX_ADDLS,
29649 +  AVR32_SYNTAX_ADDGT,
29650 +  AVR32_SYNTAX_ADDLE,
29651 +  AVR32_SYNTAX_ADDHI,
29652 +  AVR32_SYNTAX_ADDVS,
29653 +  AVR32_SYNTAX_ADDVC,
29654 +  AVR32_SYNTAX_ADDQS,
29655 +  AVR32_SYNTAX_ADDAL,
29656 +  AVR32_SYNTAX_ADDHS,
29657 +  AVR32_SYNTAX_ADDLO,
29658 +  AVR32_SYNTAX_SUB2EQ,
29659 +  AVR32_SYNTAX_SUB2NE,
29660 +  AVR32_SYNTAX_SUB2CC,
29661 +  AVR32_SYNTAX_SUB2CS,
29662 +  AVR32_SYNTAX_SUB2GE,
29663 +  AVR32_SYNTAX_SUB2LT,
29664 +  AVR32_SYNTAX_SUB2MI,
29665 +  AVR32_SYNTAX_SUB2PL,
29666 +  AVR32_SYNTAX_SUB2LS,
29667 +  AVR32_SYNTAX_SUB2GT,
29668 +  AVR32_SYNTAX_SUB2LE,
29669 +  AVR32_SYNTAX_SUB2HI,
29670 +  AVR32_SYNTAX_SUB2VS,
29671 +  AVR32_SYNTAX_SUB2VC,
29672 +  AVR32_SYNTAX_SUB2QS,
29673 +  AVR32_SYNTAX_SUB2AL,
29674 +  AVR32_SYNTAX_SUB2HS,
29675 +  AVR32_SYNTAX_SUB2LO,
29676 +  AVR32_SYNTAX_ANDEQ,
29677 +  AVR32_SYNTAX_ANDNE,
29678 +  AVR32_SYNTAX_ANDCC,
29679 +  AVR32_SYNTAX_ANDCS,
29680 +  AVR32_SYNTAX_ANDGE,
29681 +  AVR32_SYNTAX_ANDLT,
29682 +  AVR32_SYNTAX_ANDMI,
29683 +  AVR32_SYNTAX_ANDPL,
29684 +  AVR32_SYNTAX_ANDLS,
29685 +  AVR32_SYNTAX_ANDGT,
29686 +  AVR32_SYNTAX_ANDLE,
29687 +  AVR32_SYNTAX_ANDHI,
29688 +  AVR32_SYNTAX_ANDVS,
29689 +  AVR32_SYNTAX_ANDVC,
29690 +  AVR32_SYNTAX_ANDQS,
29691 +  AVR32_SYNTAX_ANDAL,
29692 +  AVR32_SYNTAX_ANDHS,
29693 +  AVR32_SYNTAX_ANDLO,
29694 +  AVR32_SYNTAX_OREQ,
29695 +  AVR32_SYNTAX_ORNE,
29696 +  AVR32_SYNTAX_ORCC,
29697 +  AVR32_SYNTAX_ORCS,
29698 +  AVR32_SYNTAX_ORGE,
29699 +  AVR32_SYNTAX_ORLT,
29700 +  AVR32_SYNTAX_ORMI,
29701 +  AVR32_SYNTAX_ORPL,
29702 +  AVR32_SYNTAX_ORLS,
29703 +  AVR32_SYNTAX_ORGT,
29704 +  AVR32_SYNTAX_ORLE,
29705 +  AVR32_SYNTAX_ORHI,
29706 +  AVR32_SYNTAX_ORVS,
29707 +  AVR32_SYNTAX_ORVC,
29708 +  AVR32_SYNTAX_ORQS,
29709 +  AVR32_SYNTAX_ORAL,
29710 +  AVR32_SYNTAX_ORHS,
29711 +  AVR32_SYNTAX_ORLO,
29712 +  AVR32_SYNTAX_EOREQ,
29713 +  AVR32_SYNTAX_EORNE,
29714 +  AVR32_SYNTAX_EORCC,
29715 +  AVR32_SYNTAX_EORCS,
29716 +  AVR32_SYNTAX_EORGE,
29717 +  AVR32_SYNTAX_EORLT,
29718 +  AVR32_SYNTAX_EORMI,
29719 +  AVR32_SYNTAX_EORPL,
29720 +  AVR32_SYNTAX_EORLS,
29721 +  AVR32_SYNTAX_EORGT,
29722 +  AVR32_SYNTAX_EORLE,
29723 +  AVR32_SYNTAX_EORHI,
29724 +  AVR32_SYNTAX_EORVS,
29725 +  AVR32_SYNTAX_EORVC,
29726 +  AVR32_SYNTAX_EORQS,
29727 +  AVR32_SYNTAX_EORAL,
29728 +  AVR32_SYNTAX_EORHS,
29729 +  AVR32_SYNTAX_EORLO,
29730 +  AVR32_SYNTAX_LD_WEQ,
29731 +  AVR32_SYNTAX_LD_WNE,
29732 +  AVR32_SYNTAX_LD_WCC,
29733 +  AVR32_SYNTAX_LD_WCS,
29734 +  AVR32_SYNTAX_LD_WGE,
29735 +  AVR32_SYNTAX_LD_WLT,
29736 +  AVR32_SYNTAX_LD_WMI,
29737 +  AVR32_SYNTAX_LD_WPL,
29738 +  AVR32_SYNTAX_LD_WLS,
29739 +  AVR32_SYNTAX_LD_WGT,
29740 +  AVR32_SYNTAX_LD_WLE,
29741 +  AVR32_SYNTAX_LD_WHI,
29742 +  AVR32_SYNTAX_LD_WVS,
29743 +  AVR32_SYNTAX_LD_WVC,
29744 +  AVR32_SYNTAX_LD_WQS,
29745 +  AVR32_SYNTAX_LD_WAL,
29746 +  AVR32_SYNTAX_LD_WHS,
29747 +  AVR32_SYNTAX_LD_WLO,
29748 +  AVR32_SYNTAX_LD_SHEQ,
29749 +  AVR32_SYNTAX_LD_SHNE,
29750 +  AVR32_SYNTAX_LD_SHCC,
29751 +  AVR32_SYNTAX_LD_SHCS,
29752 +  AVR32_SYNTAX_LD_SHGE,
29753 +  AVR32_SYNTAX_LD_SHLT,
29754 +  AVR32_SYNTAX_LD_SHMI,
29755 +  AVR32_SYNTAX_LD_SHPL,
29756 +  AVR32_SYNTAX_LD_SHLS,
29757 +  AVR32_SYNTAX_LD_SHGT,
29758 +  AVR32_SYNTAX_LD_SHLE,
29759 +  AVR32_SYNTAX_LD_SHHI,
29760 +  AVR32_SYNTAX_LD_SHVS,
29761 +  AVR32_SYNTAX_LD_SHVC,
29762 +  AVR32_SYNTAX_LD_SHQS,
29763 +  AVR32_SYNTAX_LD_SHAL,
29764 +  AVR32_SYNTAX_LD_SHHS,
29765 +  AVR32_SYNTAX_LD_SHLO,
29766 +  AVR32_SYNTAX_LD_UHEQ,
29767 +  AVR32_SYNTAX_LD_UHNE,
29768 +  AVR32_SYNTAX_LD_UHCC,
29769 +  AVR32_SYNTAX_LD_UHCS,
29770 +  AVR32_SYNTAX_LD_UHGE,
29771 +  AVR32_SYNTAX_LD_UHLT,
29772 +  AVR32_SYNTAX_LD_UHMI,
29773 +  AVR32_SYNTAX_LD_UHPL,
29774 +  AVR32_SYNTAX_LD_UHLS,
29775 +  AVR32_SYNTAX_LD_UHGT,
29776 +  AVR32_SYNTAX_LD_UHLE,
29777 +  AVR32_SYNTAX_LD_UHHI,
29778 +  AVR32_SYNTAX_LD_UHVS,
29779 +  AVR32_SYNTAX_LD_UHVC,
29780 +  AVR32_SYNTAX_LD_UHQS,
29781 +  AVR32_SYNTAX_LD_UHAL,
29782 +  AVR32_SYNTAX_LD_UHHS,
29783 +  AVR32_SYNTAX_LD_UHLO,
29784 +  AVR32_SYNTAX_LD_SBEQ,
29785 +  AVR32_SYNTAX_LD_SBNE,
29786 +  AVR32_SYNTAX_LD_SBCC,
29787 +  AVR32_SYNTAX_LD_SBCS,
29788 +  AVR32_SYNTAX_LD_SBGE,
29789 +  AVR32_SYNTAX_LD_SBLT,
29790 +  AVR32_SYNTAX_LD_SBMI,
29791 +  AVR32_SYNTAX_LD_SBPL,
29792 +  AVR32_SYNTAX_LD_SBLS,
29793 +  AVR32_SYNTAX_LD_SBGT,
29794 +  AVR32_SYNTAX_LD_SBLE,
29795 +  AVR32_SYNTAX_LD_SBHI,
29796 +  AVR32_SYNTAX_LD_SBVS,
29797 +  AVR32_SYNTAX_LD_SBVC,
29798 +  AVR32_SYNTAX_LD_SBQS,
29799 +  AVR32_SYNTAX_LD_SBAL,
29800 +  AVR32_SYNTAX_LD_SBHS,
29801 +  AVR32_SYNTAX_LD_SBLO,
29802 +  AVR32_SYNTAX_LD_UBEQ,
29803 +  AVR32_SYNTAX_LD_UBNE,
29804 +  AVR32_SYNTAX_LD_UBCC,
29805 +  AVR32_SYNTAX_LD_UBCS,
29806 +  AVR32_SYNTAX_LD_UBGE,
29807 +  AVR32_SYNTAX_LD_UBLT,
29808 +  AVR32_SYNTAX_LD_UBMI,
29809 +  AVR32_SYNTAX_LD_UBPL,
29810 +  AVR32_SYNTAX_LD_UBLS,
29811 +  AVR32_SYNTAX_LD_UBGT,
29812 +  AVR32_SYNTAX_LD_UBLE,
29813 +  AVR32_SYNTAX_LD_UBHI,
29814 +  AVR32_SYNTAX_LD_UBVS,
29815 +  AVR32_SYNTAX_LD_UBVC,
29816 +  AVR32_SYNTAX_LD_UBQS,
29817 +  AVR32_SYNTAX_LD_UBAL,
29818 +  AVR32_SYNTAX_LD_UBHS,
29819 +  AVR32_SYNTAX_LD_UBLO,
29820 +  AVR32_SYNTAX_ST_WEQ,
29821 +  AVR32_SYNTAX_ST_WNE,
29822 +  AVR32_SYNTAX_ST_WCC,
29823 +  AVR32_SYNTAX_ST_WCS,
29824 +  AVR32_SYNTAX_ST_WGE,
29825 +  AVR32_SYNTAX_ST_WLT,
29826 +  AVR32_SYNTAX_ST_WMI,
29827 +  AVR32_SYNTAX_ST_WPL,
29828 +  AVR32_SYNTAX_ST_WLS,
29829 +  AVR32_SYNTAX_ST_WGT,
29830 +  AVR32_SYNTAX_ST_WLE,
29831 +  AVR32_SYNTAX_ST_WHI,
29832 +  AVR32_SYNTAX_ST_WVS,
29833 +  AVR32_SYNTAX_ST_WVC,
29834 +  AVR32_SYNTAX_ST_WQS,
29835 +  AVR32_SYNTAX_ST_WAL,
29836 +  AVR32_SYNTAX_ST_WHS,
29837 +  AVR32_SYNTAX_ST_WLO,
29838 +  AVR32_SYNTAX_ST_HEQ,
29839 +  AVR32_SYNTAX_ST_HNE,
29840 +  AVR32_SYNTAX_ST_HCC,
29841 +  AVR32_SYNTAX_ST_HCS,
29842 +  AVR32_SYNTAX_ST_HGE,
29843 +  AVR32_SYNTAX_ST_HLT,
29844 +  AVR32_SYNTAX_ST_HMI,
29845 +  AVR32_SYNTAX_ST_HPL,
29846 +  AVR32_SYNTAX_ST_HLS,
29847 +  AVR32_SYNTAX_ST_HGT,
29848 +  AVR32_SYNTAX_ST_HLE,
29849 +  AVR32_SYNTAX_ST_HHI,
29850 +  AVR32_SYNTAX_ST_HVS,
29851 +  AVR32_SYNTAX_ST_HVC,
29852 +  AVR32_SYNTAX_ST_HQS,
29853 +  AVR32_SYNTAX_ST_HAL,
29854 +  AVR32_SYNTAX_ST_HHS,
29855 +  AVR32_SYNTAX_ST_HLO,
29856 +  AVR32_SYNTAX_ST_BEQ,
29857 +  AVR32_SYNTAX_ST_BNE,
29858 +  AVR32_SYNTAX_ST_BCC,
29859 +  AVR32_SYNTAX_ST_BCS,
29860 +  AVR32_SYNTAX_ST_BGE,
29861 +  AVR32_SYNTAX_ST_BLT,
29862 +  AVR32_SYNTAX_ST_BMI,
29863 +  AVR32_SYNTAX_ST_BPL,
29864 +  AVR32_SYNTAX_ST_BLS,
29865 +  AVR32_SYNTAX_ST_BGT,
29866 +  AVR32_SYNTAX_ST_BLE,
29867 +  AVR32_SYNTAX_ST_BHI,
29868 +  AVR32_SYNTAX_ST_BVS,
29869 +  AVR32_SYNTAX_ST_BVC,
29870 +  AVR32_SYNTAX_ST_BQS,
29871 +  AVR32_SYNTAX_ST_BAL,
29872 +  AVR32_SYNTAX_ST_BHS,
29873 +  AVR32_SYNTAX_ST_BLO,
29874 +  AVR32_SYNTAX_MOVH,
29875 +  AVR32_SYNTAX__END_
29876 +};
29877 +#define AVR32_NR_SYNTAX AVR32_SYNTAX__END_
29878 +
29879 +enum avr32_alias_type
29880 +  {
29881 +    AVR32_ALIAS_FMAC_S,
29882 +    AVR32_ALIAS_FMAC_D,
29883 +    AVR32_ALIAS_FNMAC_S,
29884 +    AVR32_ALIAS_FNMAC_D,
29885 +    AVR32_ALIAS_FMSC_S,
29886 +    AVR32_ALIAS_FMSC_D,
29887 +    AVR32_ALIAS_FNMSC_S,
29888 +    AVR32_ALIAS_FNMSC_D,
29889 +    AVR32_ALIAS_FADD_S,
29890 +    AVR32_ALIAS_FADD_D,
29891 +    AVR32_ALIAS_FSUB_S,
29892 +    AVR32_ALIAS_FSUB_D,
29893 +    AVR32_ALIAS_FMUL_S,
29894 +    AVR32_ALIAS_FMUL_D,
29895 +    AVR32_ALIAS_FNMUL_S,
29896 +    AVR32_ALIAS_FNMUL_D,
29897 +    AVR32_ALIAS_FNEG_S,
29898 +    AVR32_ALIAS_FNEG_D,
29899 +    AVR32_ALIAS_FABS_S,
29900 +    AVR32_ALIAS_FABS_D,
29901 +    AVR32_ALIAS_FCMP_S,
29902 +    AVR32_ALIAS_FCMP_D,
29903 +    AVR32_ALIAS_FMOV1_S,
29904 +    AVR32_ALIAS_FMOV1_D,
29905 +    AVR32_ALIAS_FMOV2_S,
29906 +    AVR32_ALIAS_FMOV2_D,
29907 +    AVR32_ALIAS_FMOV3_S,
29908 +    AVR32_ALIAS_FMOV3_D,
29909 +    AVR32_ALIAS_FCASTS_D,
29910 +    AVR32_ALIAS_FCASTD_S,
29911 +    AVR32_ALIAS_PICOSVMAC0,
29912 +    AVR32_ALIAS_PICOSVMAC1,
29913 +    AVR32_ALIAS_PICOSVMAC2,
29914 +    AVR32_ALIAS_PICOSVMAC3,
29915 +    AVR32_ALIAS_PICOSVMUL0,
29916 +    AVR32_ALIAS_PICOSVMUL1,
29917 +    AVR32_ALIAS_PICOSVMUL2,
29918 +    AVR32_ALIAS_PICOSVMUL3,
29919 +    AVR32_ALIAS_PICOVMAC0,
29920 +    AVR32_ALIAS_PICOVMAC1,
29921 +    AVR32_ALIAS_PICOVMAC2,
29922 +    AVR32_ALIAS_PICOVMAC3,
29923 +    AVR32_ALIAS_PICOVMUL0,
29924 +    AVR32_ALIAS_PICOVMUL1,
29925 +    AVR32_ALIAS_PICOVMUL2,
29926 +    AVR32_ALIAS_PICOVMUL3,
29927 +    AVR32_ALIAS_PICOLD_D1,
29928 +    AVR32_ALIAS_PICOLD_D2,
29929 +    AVR32_ALIAS_PICOLD_D3,
29930 +    AVR32_ALIAS_PICOLD_W1,
29931 +    AVR32_ALIAS_PICOLD_W2,
29932 +    AVR32_ALIAS_PICOLD_W3,
29933 +    AVR32_ALIAS_PICOLDM_D,
29934 +    AVR32_ALIAS_PICOLDM_D_PU,
29935 +    AVR32_ALIAS_PICOLDM_W,
29936 +    AVR32_ALIAS_PICOLDM_W_PU,
29937 +    AVR32_ALIAS_PICOMV_D1,
29938 +    AVR32_ALIAS_PICOMV_D2,
29939 +    AVR32_ALIAS_PICOMV_W1,
29940 +    AVR32_ALIAS_PICOMV_W2,
29941 +    AVR32_ALIAS_PICOST_D1,
29942 +    AVR32_ALIAS_PICOST_D2,
29943 +    AVR32_ALIAS_PICOST_D3,
29944 +    AVR32_ALIAS_PICOST_W1,
29945 +    AVR32_ALIAS_PICOST_W2,
29946 +    AVR32_ALIAS_PICOST_W3,
29947 +    AVR32_ALIAS_PICOSTM_D,
29948 +    AVR32_ALIAS_PICOSTM_D_PU,
29949 +    AVR32_ALIAS_PICOSTM_W,
29950 +    AVR32_ALIAS_PICOSTM_W_PU,
29951 +    AVR32_ALIAS__END_
29952 +  };
29953 +#define AVR32_NR_ALIAS AVR32_ALIAS__END_
29954 +
29955 +enum avr32_mnemonic_type
29956 +{
29957 +  AVR32_MNEMONIC_ABS,
29958 +  AVR32_MNEMONIC_ACALL,
29959 +  AVR32_MNEMONIC_ACR,
29960 +  AVR32_MNEMONIC_ADC,
29961 +  AVR32_MNEMONIC_ADD,
29962 +  AVR32_MNEMONIC_ADDABS,
29963 +  AVR32_MNEMONIC_ADDHH_W,
29964 +  AVR32_MNEMONIC_AND,
29965 +  AVR32_MNEMONIC_ANDH,
29966 +  AVR32_MNEMONIC_ANDL,
29967 +  AVR32_MNEMONIC_ANDN,
29968 +  AVR32_MNEMONIC_ASR,
29969 +  AVR32_MNEMONIC_BFEXTS,
29970 +  AVR32_MNEMONIC_BFEXTU,
29971 +  AVR32_MNEMONIC_BFINS,
29972 +  AVR32_MNEMONIC_BLD,
29973 +  AVR32_MNEMONIC_BREQ,
29974 +  AVR32_MNEMONIC_BRNE,
29975 +  AVR32_MNEMONIC_BRCC,
29976 +  AVR32_MNEMONIC_BRCS,
29977 +  AVR32_MNEMONIC_BRGE,
29978 +  AVR32_MNEMONIC_BRLT,
29979 +  AVR32_MNEMONIC_BRMI,
29980 +  AVR32_MNEMONIC_BRPL,
29981 +  AVR32_MNEMONIC_BRHS,
29982 +  AVR32_MNEMONIC_BRLO,
29983 +  AVR32_MNEMONIC_BRLS,
29984 +  AVR32_MNEMONIC_BRGT,
29985 +  AVR32_MNEMONIC_BRLE,
29986 +  AVR32_MNEMONIC_BRHI,
29987 +  AVR32_MNEMONIC_BRVS,
29988 +  AVR32_MNEMONIC_BRVC,
29989 +  AVR32_MNEMONIC_BRQS,
29990 +  AVR32_MNEMONIC_BRAL,
29991 +  AVR32_MNEMONIC_BREAKPOINT,
29992 +  AVR32_MNEMONIC_BREV,
29993 +  AVR32_MNEMONIC_BST,
29994 +  AVR32_MNEMONIC_CACHE,
29995 +  AVR32_MNEMONIC_CASTS_B,
29996 +  AVR32_MNEMONIC_CASTS_H,
29997 +  AVR32_MNEMONIC_CASTU_B,
29998 +  AVR32_MNEMONIC_CASTU_H,
29999 +  AVR32_MNEMONIC_CBR,
30000 +  AVR32_MNEMONIC_CLZ,
30001 +  AVR32_MNEMONIC_COM,
30002 +  AVR32_MNEMONIC_COP,
30003 +  AVR32_MNEMONIC_CP_B,
30004 +  AVR32_MNEMONIC_CP_H,
30005 +  AVR32_MNEMONIC_CP_W,
30006 +  AVR32_MNEMONIC_CP,
30007 +  AVR32_MNEMONIC_CPC,
30008 +  AVR32_MNEMONIC_CSRF,
30009 +  AVR32_MNEMONIC_CSRFCZ,
30010 +  AVR32_MNEMONIC_DIVS,
30011 +  AVR32_MNEMONIC_DIVU,
30012 +  AVR32_MNEMONIC_EOR,
30013 +  AVR32_MNEMONIC_EORL,
30014 +  AVR32_MNEMONIC_EORH,
30015 +  AVR32_MNEMONIC_FRS,
30016 +  AVR32_MNEMONIC_SSCALL,
30017 +  AVR32_MNEMONIC_RETSS,
30018 +  AVR32_MNEMONIC_ICALL,
30019 +  AVR32_MNEMONIC_INCJOSP,
30020 +  AVR32_MNEMONIC_LD_D,
30021 +  AVR32_MNEMONIC_LD_SB,
30022 +  AVR32_MNEMONIC_LD_UB,
30023 +  AVR32_MNEMONIC_LD_SH,
30024 +  AVR32_MNEMONIC_LD_UH,
30025 +  AVR32_MNEMONIC_LD_W,
30026 +  AVR32_MNEMONIC_LDC_D,
30027 +  AVR32_MNEMONIC_LDC_W,
30028 +  AVR32_MNEMONIC_LDC0_D,
30029 +  AVR32_MNEMONIC_LDC0_W,
30030 +  AVR32_MNEMONIC_LDCM_D,
30031 +  AVR32_MNEMONIC_LDCM_W,
30032 +  AVR32_MNEMONIC_LDDPC,
30033 +  AVR32_MNEMONIC_LDDSP,
30034 +  AVR32_MNEMONIC_LDINS_B,
30035 +  AVR32_MNEMONIC_LDINS_H,
30036 +  AVR32_MNEMONIC_LDM,
30037 +  AVR32_MNEMONIC_LDMTS,
30038 +  AVR32_MNEMONIC_LDSWP_SH,
30039 +  AVR32_MNEMONIC_LDSWP_UH,
30040 +  AVR32_MNEMONIC_LDSWP_W,
30041 +  AVR32_MNEMONIC_LSL,
30042 +  AVR32_MNEMONIC_LSR,
30043 +  AVR32_MNEMONIC_MAC,
30044 +  AVR32_MNEMONIC_MACHH_D,
30045 +  AVR32_MNEMONIC_MACHH_W,
30046 +  AVR32_MNEMONIC_MACS_D,
30047 +  AVR32_MNEMONIC_MACSATHH_W,
30048 +  AVR32_MNEMONIC_MACU_D,
30049 +  AVR32_MNEMONIC_MACWH_D,
30050 +  AVR32_MNEMONIC_MAX,
30051 +  AVR32_MNEMONIC_MCALL,
30052 +  AVR32_MNEMONIC_MFDR,
30053 +  AVR32_MNEMONIC_MFSR,
30054 +  AVR32_MNEMONIC_MIN,
30055 +  AVR32_MNEMONIC_MOV,
30056 +  AVR32_MNEMONIC_MOVEQ,
30057 +  AVR32_MNEMONIC_MOVNE,
30058 +  AVR32_MNEMONIC_MOVCC,
30059 +  AVR32_MNEMONIC_MOVCS,
30060 +  AVR32_MNEMONIC_MOVGE,
30061 +  AVR32_MNEMONIC_MOVLT,
30062 +  AVR32_MNEMONIC_MOVMI,
30063 +  AVR32_MNEMONIC_MOVPL,
30064 +  AVR32_MNEMONIC_MOVLS,
30065 +  AVR32_MNEMONIC_MOVGT,
30066 +  AVR32_MNEMONIC_MOVLE,
30067 +  AVR32_MNEMONIC_MOVHI,
30068 +  AVR32_MNEMONIC_MOVVS,
30069 +  AVR32_MNEMONIC_MOVVC,
30070 +  AVR32_MNEMONIC_MOVQS,
30071 +  AVR32_MNEMONIC_MOVAL,
30072 +  AVR32_MNEMONIC_MOVHS,
30073 +  AVR32_MNEMONIC_MOVLO,
30074 +  AVR32_MNEMONIC_MTDR,
30075 +  AVR32_MNEMONIC_MTSR,
30076 +  AVR32_MNEMONIC_MUL,
30077 +  AVR32_MNEMONIC_MULHH_W,
30078 +  AVR32_MNEMONIC_MULNHH_W,
30079 +  AVR32_MNEMONIC_MULNWH_D,
30080 +  AVR32_MNEMONIC_MULS_D,
30081 +  AVR32_MNEMONIC_MULSATHH_H,
30082 +  AVR32_MNEMONIC_MULSATHH_W,
30083 +  AVR32_MNEMONIC_MULSATRNDHH_H,
30084 +  AVR32_MNEMONIC_MULSATRNDWH_W,
30085 +  AVR32_MNEMONIC_MULSATWH_W,
30086 +  AVR32_MNEMONIC_MULU_D,
30087 +  AVR32_MNEMONIC_MULWH_D,
30088 +  AVR32_MNEMONIC_MUSFR,
30089 +  AVR32_MNEMONIC_MUSTR,
30090 +  AVR32_MNEMONIC_MVCR_D,
30091 +  AVR32_MNEMONIC_MVCR_W,
30092 +  AVR32_MNEMONIC_MVRC_D,
30093 +  AVR32_MNEMONIC_MVRC_W,
30094 +  AVR32_MNEMONIC_NEG,
30095 +  AVR32_MNEMONIC_NOP,
30096 +  AVR32_MNEMONIC_OR,
30097 +  AVR32_MNEMONIC_ORH,
30098 +  AVR32_MNEMONIC_ORL,
30099 +  AVR32_MNEMONIC_PABS_SB,
30100 +  AVR32_MNEMONIC_PABS_SH,
30101 +  AVR32_MNEMONIC_PACKSH_SB,
30102 +  AVR32_MNEMONIC_PACKSH_UB,
30103 +  AVR32_MNEMONIC_PACKW_SH,
30104 +  AVR32_MNEMONIC_PADD_B,
30105 +  AVR32_MNEMONIC_PADD_H,
30106 +  AVR32_MNEMONIC_PADDH_SH,
30107 +  AVR32_MNEMONIC_PADDH_UB,
30108 +  AVR32_MNEMONIC_PADDS_SB,
30109 +  AVR32_MNEMONIC_PADDS_SH,
30110 +  AVR32_MNEMONIC_PADDS_UB,
30111 +  AVR32_MNEMONIC_PADDS_UH,
30112 +  AVR32_MNEMONIC_PADDSUB_H,
30113 +  AVR32_MNEMONIC_PADDSUBH_SH,
30114 +  AVR32_MNEMONIC_PADDSUBS_SH,
30115 +  AVR32_MNEMONIC_PADDSUBS_UH,
30116 +  AVR32_MNEMONIC_PADDX_H,
30117 +  AVR32_MNEMONIC_PADDXH_SH,
30118 +  AVR32_MNEMONIC_PADDXS_SH,
30119 +  AVR32_MNEMONIC_PADDXS_UH,
30120 +  AVR32_MNEMONIC_PASR_B,
30121 +  AVR32_MNEMONIC_PASR_H,
30122 +  AVR32_MNEMONIC_PAVG_SH,
30123 +  AVR32_MNEMONIC_PAVG_UB,
30124 +  AVR32_MNEMONIC_PLSL_B,
30125 +  AVR32_MNEMONIC_PLSL_H,
30126 +  AVR32_MNEMONIC_PLSR_B,
30127 +  AVR32_MNEMONIC_PLSR_H,
30128 +  AVR32_MNEMONIC_PMAX_SH,
30129 +  AVR32_MNEMONIC_PMAX_UB,
30130 +  AVR32_MNEMONIC_PMIN_SH,
30131 +  AVR32_MNEMONIC_PMIN_UB,
30132 +  AVR32_MNEMONIC_POPJC,
30133 +  AVR32_MNEMONIC_POPM,
30134 +  AVR32_MNEMONIC_PREF,
30135 +  AVR32_MNEMONIC_PSAD,
30136 +  AVR32_MNEMONIC_PSUB_B,
30137 +  AVR32_MNEMONIC_PSUB_H,
30138 +  AVR32_MNEMONIC_PSUBADD_H,
30139 +  AVR32_MNEMONIC_PSUBADDH_SH,
30140 +  AVR32_MNEMONIC_PSUBADDS_SH,
30141 +  AVR32_MNEMONIC_PSUBADDS_UH,
30142 +  AVR32_MNEMONIC_PSUBH_SH,
30143 +  AVR32_MNEMONIC_PSUBH_UB,
30144 +  AVR32_MNEMONIC_PSUBS_SB,
30145 +  AVR32_MNEMONIC_PSUBS_SH,
30146 +  AVR32_MNEMONIC_PSUBS_UB,
30147 +  AVR32_MNEMONIC_PSUBS_UH,
30148 +  AVR32_MNEMONIC_PSUBX_H,
30149 +  AVR32_MNEMONIC_PSUBXH_SH,
30150 +  AVR32_MNEMONIC_PSUBXS_SH,
30151 +  AVR32_MNEMONIC_PSUBXS_UH,
30152 +  AVR32_MNEMONIC_PUNPCKSB_H,
30153 +  AVR32_MNEMONIC_PUNPCKUB_H,
30154 +  AVR32_MNEMONIC_PUSHJC,
30155 +  AVR32_MNEMONIC_PUSHM,
30156 +  AVR32_MNEMONIC_RCALL,
30157 +  AVR32_MNEMONIC_RETEQ,
30158 +  AVR32_MNEMONIC_RETNE,
30159 +  AVR32_MNEMONIC_RETCC,
30160 +  AVR32_MNEMONIC_RETCS,
30161 +  AVR32_MNEMONIC_RETGE,
30162 +  AVR32_MNEMONIC_RETLT,
30163 +  AVR32_MNEMONIC_RETMI,
30164 +  AVR32_MNEMONIC_RETPL,
30165 +  AVR32_MNEMONIC_RETLS,
30166 +  AVR32_MNEMONIC_RETGT,
30167 +  AVR32_MNEMONIC_RETLE,
30168 +  AVR32_MNEMONIC_RETHI,
30169 +  AVR32_MNEMONIC_RETVS,
30170 +  AVR32_MNEMONIC_RETVC,
30171 +  AVR32_MNEMONIC_RETQS,
30172 +  AVR32_MNEMONIC_RETAL,
30173 +  AVR32_MNEMONIC_RETHS,
30174 +  AVR32_MNEMONIC_RETLO,
30175 +  AVR32_MNEMONIC_RET,
30176 +  AVR32_MNEMONIC_RETD,
30177 +  AVR32_MNEMONIC_RETE,
30178 +  AVR32_MNEMONIC_RETJ,
30179 +  AVR32_MNEMONIC_RETS,
30180 +  AVR32_MNEMONIC_RJMP,
30181 +  AVR32_MNEMONIC_ROL,
30182 +  AVR32_MNEMONIC_ROR,
30183 +  AVR32_MNEMONIC_RSUB,
30184 +  AVR32_MNEMONIC_SATADD_H,
30185 +  AVR32_MNEMONIC_SATADD_W,
30186 +  AVR32_MNEMONIC_SATRNDS,
30187 +  AVR32_MNEMONIC_SATRNDU,
30188 +  AVR32_MNEMONIC_SATS,
30189 +  AVR32_MNEMONIC_SATSUB_H,
30190 +  AVR32_MNEMONIC_SATSUB_W,
30191 +  AVR32_MNEMONIC_SATU,
30192 +  AVR32_MNEMONIC_SBC,
30193 +  AVR32_MNEMONIC_SBR,
30194 +  AVR32_MNEMONIC_SCALL,
30195 +  AVR32_MNEMONIC_SCR,
30196 +  AVR32_MNEMONIC_SLEEP,
30197 +  AVR32_MNEMONIC_SREQ,
30198 +  AVR32_MNEMONIC_SRNE,
30199 +  AVR32_MNEMONIC_SRCC,
30200 +  AVR32_MNEMONIC_SRCS,
30201 +  AVR32_MNEMONIC_SRGE,
30202 +  AVR32_MNEMONIC_SRLT,
30203 +  AVR32_MNEMONIC_SRMI,
30204 +  AVR32_MNEMONIC_SRPL,
30205 +  AVR32_MNEMONIC_SRLS,
30206 +  AVR32_MNEMONIC_SRGT,
30207 +  AVR32_MNEMONIC_SRLE,
30208 +  AVR32_MNEMONIC_SRHI,
30209 +  AVR32_MNEMONIC_SRVS,
30210 +  AVR32_MNEMONIC_SRVC,
30211 +  AVR32_MNEMONIC_SRQS,
30212 +  AVR32_MNEMONIC_SRAL,
30213 +  AVR32_MNEMONIC_SRHS,
30214 +  AVR32_MNEMONIC_SRLO,
30215 +  AVR32_MNEMONIC_SSRF,
30216 +  AVR32_MNEMONIC_ST_B,
30217 +  AVR32_MNEMONIC_ST_D,
30218 +  AVR32_MNEMONIC_ST_H,
30219 +  AVR32_MNEMONIC_ST_W,
30220 +  AVR32_MNEMONIC_STC_D,
30221 +  AVR32_MNEMONIC_STC_W,
30222 +  AVR32_MNEMONIC_STC0_D,
30223 +  AVR32_MNEMONIC_STC0_W,
30224 +  AVR32_MNEMONIC_STCM_D,
30225 +  AVR32_MNEMONIC_STCM_W,
30226 +  AVR32_MNEMONIC_STCOND,
30227 +  AVR32_MNEMONIC_STDSP,
30228 +  AVR32_MNEMONIC_STHH_W,
30229 +  AVR32_MNEMONIC_STM,
30230 +  AVR32_MNEMONIC_STMTS,
30231 +  AVR32_MNEMONIC_STSWP_H,
30232 +  AVR32_MNEMONIC_STSWP_W,
30233 +  AVR32_MNEMONIC_SUB,
30234 +  AVR32_MNEMONIC_SUBEQ,
30235 +  AVR32_MNEMONIC_SUBNE,
30236 +  AVR32_MNEMONIC_SUBCC,
30237 +  AVR32_MNEMONIC_SUBCS,
30238 +  AVR32_MNEMONIC_SUBGE,
30239 +  AVR32_MNEMONIC_SUBLT,
30240 +  AVR32_MNEMONIC_SUBMI,
30241 +  AVR32_MNEMONIC_SUBPL,
30242 +  AVR32_MNEMONIC_SUBLS,
30243 +  AVR32_MNEMONIC_SUBGT,
30244 +  AVR32_MNEMONIC_SUBLE,
30245 +  AVR32_MNEMONIC_SUBHI,
30246 +  AVR32_MNEMONIC_SUBVS,
30247 +  AVR32_MNEMONIC_SUBVC,
30248 +  AVR32_MNEMONIC_SUBQS,
30249 +  AVR32_MNEMONIC_SUBAL,
30250 +  AVR32_MNEMONIC_SUBHS,
30251 +  AVR32_MNEMONIC_SUBLO,
30252 +  AVR32_MNEMONIC_SUBFEQ,
30253 +  AVR32_MNEMONIC_SUBFNE,
30254 +  AVR32_MNEMONIC_SUBFCC,
30255 +  AVR32_MNEMONIC_SUBFCS,
30256 +  AVR32_MNEMONIC_SUBFGE,
30257 +  AVR32_MNEMONIC_SUBFLT,
30258 +  AVR32_MNEMONIC_SUBFMI,
30259 +  AVR32_MNEMONIC_SUBFPL,
30260 +  AVR32_MNEMONIC_SUBFLS,
30261 +  AVR32_MNEMONIC_SUBFGT,
30262 +  AVR32_MNEMONIC_SUBFLE,
30263 +  AVR32_MNEMONIC_SUBFHI,
30264 +  AVR32_MNEMONIC_SUBFVS,
30265 +  AVR32_MNEMONIC_SUBFVC,
30266 +  AVR32_MNEMONIC_SUBFQS,
30267 +  AVR32_MNEMONIC_SUBFAL,
30268 +  AVR32_MNEMONIC_SUBFHS,
30269 +  AVR32_MNEMONIC_SUBFLO,
30270 +  AVR32_MNEMONIC_SUBHH_W,
30271 +  AVR32_MNEMONIC_SWAP_B,
30272 +  AVR32_MNEMONIC_SWAP_BH,
30273 +  AVR32_MNEMONIC_SWAP_H,
30274 +  AVR32_MNEMONIC_SYNC,
30275 +  AVR32_MNEMONIC_TLBR,
30276 +  AVR32_MNEMONIC_TLBS,
30277 +  AVR32_MNEMONIC_TLBW,
30278 +  AVR32_MNEMONIC_TNBZ,
30279 +  AVR32_MNEMONIC_TST,
30280 +  AVR32_MNEMONIC_XCHG,
30281 +  AVR32_MNEMONIC_MEMC,
30282 +  AVR32_MNEMONIC_MEMS,
30283 +  AVR32_MNEMONIC_MEMT,
30284 +  AVR32_MNEMONIC_FADD_S,
30285 +  AVR32_MNEMONIC_FADD_D,
30286 +  AVR32_MNEMONIC_FSUB_S,
30287 +  AVR32_MNEMONIC_FSUB_D,
30288 +  AVR32_MNEMONIC_FMAC_S,
30289 +  AVR32_MNEMONIC_FMAC_D,
30290 +  AVR32_MNEMONIC_FNMAC_S,
30291 +  AVR32_MNEMONIC_FNMAC_D,
30292 +  AVR32_MNEMONIC_FMSC_S,
30293 +  AVR32_MNEMONIC_FMSC_D,
30294 +  AVR32_MNEMONIC_FNMSC_S,
30295 +  AVR32_MNEMONIC_FNMSC_D,
30296 +  AVR32_MNEMONIC_FMUL_S,
30297 +  AVR32_MNEMONIC_FMUL_D,
30298 +  AVR32_MNEMONIC_FNMUL_S,
30299 +  AVR32_MNEMONIC_FNMUL_D,
30300 +  AVR32_MNEMONIC_FNEG_S,
30301 +  AVR32_MNEMONIC_FNEG_D,
30302 +  AVR32_MNEMONIC_FABS_S,
30303 +  AVR32_MNEMONIC_FABS_D,
30304 +  AVR32_MNEMONIC_FCMP_S,
30305 +  AVR32_MNEMONIC_FCMP_D,
30306 +  AVR32_MNEMONIC_FMOV_S,
30307 +  AVR32_MNEMONIC_FMOV_D,
30308 +  AVR32_MNEMONIC_FCASTS_D,
30309 +  AVR32_MNEMONIC_FCASTD_S,
30310 +  /* AVR32_MNEMONIC_FLD_S,
30311 +     AVR32_MNEMONIC_FLD_D,
30312 +     AVR32_MNEMONIC_FST_S,
30313 +     AVR32_MNEMONIC_FST_D, */
30314 +  AVR32_MNEMONIC_LDA_W,
30315 +  AVR32_MNEMONIC_CALL,
30316 +  AVR32_MNEMONIC_PICOSVMAC,
30317 +  AVR32_MNEMONIC_PICOSVMUL,
30318 +  AVR32_MNEMONIC_PICOVMAC,
30319 +  AVR32_MNEMONIC_PICOVMUL,
30320 +  AVR32_MNEMONIC_PICOLD_D,
30321 +  AVR32_MNEMONIC_PICOLD_W,
30322 +  AVR32_MNEMONIC_PICOLDM_D,
30323 +  AVR32_MNEMONIC_PICOLDM_W,
30324 +  AVR32_MNEMONIC_PICOMV_D,
30325 +  AVR32_MNEMONIC_PICOMV_W,
30326 +  AVR32_MNEMONIC_PICOST_D,
30327 +  AVR32_MNEMONIC_PICOST_W,
30328 +  AVR32_MNEMONIC_PICOSTM_D,
30329 +  AVR32_MNEMONIC_PICOSTM_W,
30330 +  AVR32_MNEMONIC_RSUBEQ,
30331 +  AVR32_MNEMONIC_RSUBNE,
30332 +  AVR32_MNEMONIC_RSUBCC,
30333 +  AVR32_MNEMONIC_RSUBCS,
30334 +  AVR32_MNEMONIC_RSUBGE,
30335 +  AVR32_MNEMONIC_RSUBLT,
30336 +  AVR32_MNEMONIC_RSUBMI,
30337 +  AVR32_MNEMONIC_RSUBPL,
30338 +  AVR32_MNEMONIC_RSUBLS,
30339 +  AVR32_MNEMONIC_RSUBGT,
30340 +  AVR32_MNEMONIC_RSUBLE,
30341 +  AVR32_MNEMONIC_RSUBHI,
30342 +  AVR32_MNEMONIC_RSUBVS,
30343 +  AVR32_MNEMONIC_RSUBVC,
30344 +  AVR32_MNEMONIC_RSUBQS,
30345 +  AVR32_MNEMONIC_RSUBAL,
30346 +  AVR32_MNEMONIC_RSUBHS,
30347 +  AVR32_MNEMONIC_RSUBLO,
30348 +  AVR32_MNEMONIC_ADDEQ,
30349 +  AVR32_MNEMONIC_ADDNE,
30350 +  AVR32_MNEMONIC_ADDCC,
30351 +  AVR32_MNEMONIC_ADDCS,
30352 +  AVR32_MNEMONIC_ADDGE,
30353 +  AVR32_MNEMONIC_ADDLT,
30354 +  AVR32_MNEMONIC_ADDMI,
30355 +  AVR32_MNEMONIC_ADDPL,
30356 +  AVR32_MNEMONIC_ADDLS,
30357 +  AVR32_MNEMONIC_ADDGT,
30358 +  AVR32_MNEMONIC_ADDLE,
30359 +  AVR32_MNEMONIC_ADDHI,
30360 +  AVR32_MNEMONIC_ADDVS,
30361 +  AVR32_MNEMONIC_ADDVC,
30362 +  AVR32_MNEMONIC_ADDQS,
30363 +  AVR32_MNEMONIC_ADDAL,
30364 +  AVR32_MNEMONIC_ADDHS,
30365 +  AVR32_MNEMONIC_ADDLO,
30366 +  AVR32_MNEMONIC_ANDEQ,
30367 +  AVR32_MNEMONIC_ANDNE,
30368 +  AVR32_MNEMONIC_ANDCC,
30369 +  AVR32_MNEMONIC_ANDCS,
30370 +  AVR32_MNEMONIC_ANDGE,
30371 +  AVR32_MNEMONIC_ANDLT,
30372 +  AVR32_MNEMONIC_ANDMI,
30373 +  AVR32_MNEMONIC_ANDPL,
30374 +  AVR32_MNEMONIC_ANDLS,
30375 +  AVR32_MNEMONIC_ANDGT,
30376 +  AVR32_MNEMONIC_ANDLE,
30377 +  AVR32_MNEMONIC_ANDHI,
30378 +  AVR32_MNEMONIC_ANDVS,
30379 +  AVR32_MNEMONIC_ANDVC,
30380 +  AVR32_MNEMONIC_ANDQS,
30381 +  AVR32_MNEMONIC_ANDAL,
30382 +  AVR32_MNEMONIC_ANDHS,
30383 +  AVR32_MNEMONIC_ANDLO,
30384 +  AVR32_MNEMONIC_OREQ,
30385 +  AVR32_MNEMONIC_ORNE,
30386 +  AVR32_MNEMONIC_ORCC,
30387 +  AVR32_MNEMONIC_ORCS,
30388 +  AVR32_MNEMONIC_ORGE,
30389 +  AVR32_MNEMONIC_ORLT,
30390 +  AVR32_MNEMONIC_ORMI,
30391 +  AVR32_MNEMONIC_ORPL,
30392 +  AVR32_MNEMONIC_ORLS,
30393 +  AVR32_MNEMONIC_ORGT,
30394 +  AVR32_MNEMONIC_ORLE,
30395 +  AVR32_MNEMONIC_ORHI,
30396 +  AVR32_MNEMONIC_ORVS,
30397 +  AVR32_MNEMONIC_ORVC,
30398 +  AVR32_MNEMONIC_ORQS,
30399 +  AVR32_MNEMONIC_ORAL,
30400 +  AVR32_MNEMONIC_ORHS,
30401 +  AVR32_MNEMONIC_ORLO,
30402 +  AVR32_MNEMONIC_EOREQ,
30403 +  AVR32_MNEMONIC_EORNE,
30404 +  AVR32_MNEMONIC_EORCC,
30405 +  AVR32_MNEMONIC_EORCS,
30406 +  AVR32_MNEMONIC_EORGE,
30407 +  AVR32_MNEMONIC_EORLT,
30408 +  AVR32_MNEMONIC_EORMI,
30409 +  AVR32_MNEMONIC_EORPL,
30410 +  AVR32_MNEMONIC_EORLS,
30411 +  AVR32_MNEMONIC_EORGT,
30412 +  AVR32_MNEMONIC_EORLE,
30413 +  AVR32_MNEMONIC_EORHI,
30414 +  AVR32_MNEMONIC_EORVS,
30415 +  AVR32_MNEMONIC_EORVC,
30416 +  AVR32_MNEMONIC_EORQS,
30417 +  AVR32_MNEMONIC_EORAL,
30418 +  AVR32_MNEMONIC_EORHS,
30419 +  AVR32_MNEMONIC_EORLO,
30420 +  AVR32_MNEMONIC_LD_WEQ,
30421 +  AVR32_MNEMONIC_LD_WNE,
30422 +  AVR32_MNEMONIC_LD_WCC,
30423 +  AVR32_MNEMONIC_LD_WCS,
30424 +  AVR32_MNEMONIC_LD_WGE,
30425 +  AVR32_MNEMONIC_LD_WLT,
30426 +  AVR32_MNEMONIC_LD_WMI,
30427 +  AVR32_MNEMONIC_LD_WPL,
30428 +  AVR32_MNEMONIC_LD_WLS,
30429 +  AVR32_MNEMONIC_LD_WGT,
30430 +  AVR32_MNEMONIC_LD_WLE,
30431 +  AVR32_MNEMONIC_LD_WHI,
30432 +  AVR32_MNEMONIC_LD_WVS,
30433 +  AVR32_MNEMONIC_LD_WVC,
30434 +  AVR32_MNEMONIC_LD_WQS,
30435 +  AVR32_MNEMONIC_LD_WAL,
30436 +  AVR32_MNEMONIC_LD_WHS,
30437 +  AVR32_MNEMONIC_LD_WLO,
30438 +  AVR32_MNEMONIC_LD_SHEQ,
30439 +  AVR32_MNEMONIC_LD_SHNE,
30440 +  AVR32_MNEMONIC_LD_SHCC,
30441 +  AVR32_MNEMONIC_LD_SHCS,
30442 +  AVR32_MNEMONIC_LD_SHGE,
30443 +  AVR32_MNEMONIC_LD_SHLT,
30444 +  AVR32_MNEMONIC_LD_SHMI,
30445 +  AVR32_MNEMONIC_LD_SHPL,
30446 +  AVR32_MNEMONIC_LD_SHLS,
30447 +  AVR32_MNEMONIC_LD_SHGT,
30448 +  AVR32_MNEMONIC_LD_SHLE,
30449 +  AVR32_MNEMONIC_LD_SHHI,
30450 +  AVR32_MNEMONIC_LD_SHVS,
30451 +  AVR32_MNEMONIC_LD_SHVC,
30452 +  AVR32_MNEMONIC_LD_SHQS,
30453 +  AVR32_MNEMONIC_LD_SHAL,
30454 +  AVR32_MNEMONIC_LD_SHHS,
30455 +  AVR32_MNEMONIC_LD_SHLO,
30456 +  AVR32_MNEMONIC_LD_UHEQ,
30457 +  AVR32_MNEMONIC_LD_UHNE,
30458 +  AVR32_MNEMONIC_LD_UHCC,
30459 +  AVR32_MNEMONIC_LD_UHCS,
30460 +  AVR32_MNEMONIC_LD_UHGE,
30461 +  AVR32_MNEMONIC_LD_UHLT,
30462 +  AVR32_MNEMONIC_LD_UHMI,
30463 +  AVR32_MNEMONIC_LD_UHPL,
30464 +  AVR32_MNEMONIC_LD_UHLS,
30465 +  AVR32_MNEMONIC_LD_UHGT,
30466 +  AVR32_MNEMONIC_LD_UHLE,
30467 +  AVR32_MNEMONIC_LD_UHHI,
30468 +  AVR32_MNEMONIC_LD_UHVS,
30469 +  AVR32_MNEMONIC_LD_UHVC,
30470 +  AVR32_MNEMONIC_LD_UHQS,
30471 +  AVR32_MNEMONIC_LD_UHAL,
30472 +  AVR32_MNEMONIC_LD_UHHS,
30473 +  AVR32_MNEMONIC_LD_UHLO,
30474 +  AVR32_MNEMONIC_LD_SBEQ,
30475 +  AVR32_MNEMONIC_LD_SBNE,
30476 +  AVR32_MNEMONIC_LD_SBCC,
30477 +  AVR32_MNEMONIC_LD_SBCS,
30478 +  AVR32_MNEMONIC_LD_SBGE,
30479 +  AVR32_MNEMONIC_LD_SBLT,
30480 +  AVR32_MNEMONIC_LD_SBMI,
30481 +  AVR32_MNEMONIC_LD_SBPL,
30482 +  AVR32_MNEMONIC_LD_SBLS,
30483 +  AVR32_MNEMONIC_LD_SBGT,
30484 +  AVR32_MNEMONIC_LD_SBLE,
30485 +  AVR32_MNEMONIC_LD_SBHI,
30486 +  AVR32_MNEMONIC_LD_SBVS,
30487 +  AVR32_MNEMONIC_LD_SBVC,
30488 +  AVR32_MNEMONIC_LD_SBQS,
30489 +  AVR32_MNEMONIC_LD_SBAL,
30490 +  AVR32_MNEMONIC_LD_SBHS,
30491 +  AVR32_MNEMONIC_LD_SBLO,
30492 +  AVR32_MNEMONIC_LD_UBEQ,
30493 +  AVR32_MNEMONIC_LD_UBNE,
30494 +  AVR32_MNEMONIC_LD_UBCC,
30495 +  AVR32_MNEMONIC_LD_UBCS,
30496 +  AVR32_MNEMONIC_LD_UBGE,
30497 +  AVR32_MNEMONIC_LD_UBLT,
30498 +  AVR32_MNEMONIC_LD_UBMI,
30499 +  AVR32_MNEMONIC_LD_UBPL,
30500 +  AVR32_MNEMONIC_LD_UBLS,
30501 +  AVR32_MNEMONIC_LD_UBGT,
30502 +  AVR32_MNEMONIC_LD_UBLE,
30503 +  AVR32_MNEMONIC_LD_UBHI,
30504 +  AVR32_MNEMONIC_LD_UBVS,
30505 +  AVR32_MNEMONIC_LD_UBVC,
30506 +  AVR32_MNEMONIC_LD_UBQS,
30507 +  AVR32_MNEMONIC_LD_UBAL,
30508 +  AVR32_MNEMONIC_LD_UBHS,
30509 +  AVR32_MNEMONIC_LD_UBLO,
30510 +  AVR32_MNEMONIC_ST_WEQ,
30511 +  AVR32_MNEMONIC_ST_WNE,
30512 +  AVR32_MNEMONIC_ST_WCC,
30513 +  AVR32_MNEMONIC_ST_WCS,
30514 +  AVR32_MNEMONIC_ST_WGE,
30515 +  AVR32_MNEMONIC_ST_WLT,
30516 +  AVR32_MNEMONIC_ST_WMI,
30517 +  AVR32_MNEMONIC_ST_WPL,
30518 +  AVR32_MNEMONIC_ST_WLS,
30519 +  AVR32_MNEMONIC_ST_WGT,
30520 +  AVR32_MNEMONIC_ST_WLE,
30521 +  AVR32_MNEMONIC_ST_WHI,
30522 +  AVR32_MNEMONIC_ST_WVS,
30523 +  AVR32_MNEMONIC_ST_WVC,
30524 +  AVR32_MNEMONIC_ST_WQS,
30525 +  AVR32_MNEMONIC_ST_WAL,
30526 +  AVR32_MNEMONIC_ST_WHS,
30527 +  AVR32_MNEMONIC_ST_WLO,
30528 +  AVR32_MNEMONIC_ST_HEQ,
30529 +  AVR32_MNEMONIC_ST_HNE,
30530 +  AVR32_MNEMONIC_ST_HCC,
30531 +  AVR32_MNEMONIC_ST_HCS,
30532 +  AVR32_MNEMONIC_ST_HGE,
30533 +  AVR32_MNEMONIC_ST_HLT,
30534 +  AVR32_MNEMONIC_ST_HMI,
30535 +  AVR32_MNEMONIC_ST_HPL,
30536 +  AVR32_MNEMONIC_ST_HLS,
30537 +  AVR32_MNEMONIC_ST_HGT,
30538 +  AVR32_MNEMONIC_ST_HLE,
30539 +  AVR32_MNEMONIC_ST_HHI,
30540 +  AVR32_MNEMONIC_ST_HVS,
30541 +  AVR32_MNEMONIC_ST_HVC,
30542 +  AVR32_MNEMONIC_ST_HQS,
30543 +  AVR32_MNEMONIC_ST_HAL,
30544 +  AVR32_MNEMONIC_ST_HHS,
30545 +  AVR32_MNEMONIC_ST_HLO,
30546 +  AVR32_MNEMONIC_ST_BEQ,
30547 +  AVR32_MNEMONIC_ST_BNE,
30548 +  AVR32_MNEMONIC_ST_BCC,
30549 +  AVR32_MNEMONIC_ST_BCS,
30550 +  AVR32_MNEMONIC_ST_BGE,
30551 +  AVR32_MNEMONIC_ST_BLT,
30552 +  AVR32_MNEMONIC_ST_BMI,
30553 +  AVR32_MNEMONIC_ST_BPL,
30554 +  AVR32_MNEMONIC_ST_BLS,
30555 +  AVR32_MNEMONIC_ST_BGT,
30556 +  AVR32_MNEMONIC_ST_BLE,
30557 +  AVR32_MNEMONIC_ST_BHI,
30558 +  AVR32_MNEMONIC_ST_BVS,
30559 +  AVR32_MNEMONIC_ST_BVC,
30560 +  AVR32_MNEMONIC_ST_BQS,
30561 +  AVR32_MNEMONIC_ST_BAL,
30562 +  AVR32_MNEMONIC_ST_BHS,
30563 +  AVR32_MNEMONIC_ST_BLO,
30564 +  AVR32_MNEMONIC_MOVH,
30565 +  AVR32_MNEMONIC__END_
30566 +};
30567 +#define AVR32_NR_MNEMONICS AVR32_MNEMONIC__END_
30568 +
30569 +enum avr32_syntax_parser
30570 +  {
30571 +    AVR32_PARSER_NORMAL,
30572 +    AVR32_PARSER_ALIAS,
30573 +    AVR32_PARSER_LDA,
30574 +    AVR32_PARSER_CALL,
30575 +    AVR32_PARSER__END_
30576 +  };
30577 +#define AVR32_NR_PARSERS AVR32_PARSER__END_
30578 --- a/opcodes/configure
30579 +++ b/opcodes/configure
30580 @@ -11817,6 +11817,7 @@ if test x${all_targets} = xfalse ; then
30581         bfd_arc_arch)           ta="$ta arc-dis.lo arc-opc.lo arc-ext.lo" ;;
30582         bfd_arm_arch)           ta="$ta arm-dis.lo" ;;
30583         bfd_avr_arch)           ta="$ta avr-dis.lo" ;;
30584 +       bfd_avr32_arch)         ta="$ta avr32-asm.lo avr32-dis.lo avr32-opc.lo" ;;
30585         bfd_bfin_arch)          ta="$ta bfin-dis.lo" ;;
30586         bfd_cr16_arch)          ta="$ta cr16-dis.lo cr16-opc.lo" ;;
30587         bfd_cris_arch)          ta="$ta cris-dis.lo cris-opc.lo cgen-bitset.lo" ;;
30588 --- a/opcodes/configure.in
30589 +++ b/opcodes/configure.in
30590 @@ -177,6 +177,7 @@ if test x${all_targets} = xfalse ; then
30591         bfd_arc_arch)           ta="$ta arc-dis.lo arc-opc.lo arc-ext.lo" ;;
30592         bfd_arm_arch)           ta="$ta arm-dis.lo" ;;
30593         bfd_avr_arch)           ta="$ta avr-dis.lo" ;;
30594 +       bfd_avr32_arch)         ta="$ta avr32-asm.lo avr32-dis.lo avr32-opc.lo" ;;
30595         bfd_bfin_arch)          ta="$ta bfin-dis.lo" ;;
30596         bfd_cr16_arch)          ta="$ta cr16-dis.lo cr16-opc.lo" ;;
30597         bfd_cris_arch)          ta="$ta cris-dis.lo cris-opc.lo cgen-bitset.lo" ;;
30598 --- a/opcodes/disassemble.c
30599 +++ b/opcodes/disassemble.c
30600 @@ -27,6 +27,7 @@
30601  #define ARCH_arc
30602  #define ARCH_arm
30603  #define ARCH_avr
30604 +#define ARCH_avr32
30605  #define ARCH_bfin
30606  #define ARCH_cr16
30607  #define ARCH_cris
30608 @@ -129,6 +130,11 @@ disassembler (abfd)
30609        disassemble = print_insn_avr;
30610        break;
30611  #endif
30612 +#ifdef ARCH_avr32
30613 +    case bfd_arch_avr32:
30614 +      disassemble = print_insn_avr32;
30615 +      break;
30616 +#endif
30617  #ifdef ARCH_bfin
30618      case bfd_arch_bfin:
30619        disassemble = print_insn_bfin;
30620 @@ -472,6 +478,9 @@ disassembler_usage (stream)
30621  #ifdef ARCH_i386
30622    print_i386_disassembler_options (stream);
30623  #endif
30624 +#ifdef ARCH_avr32
30625 +  print_avr32_disassembler_options (stream);
30626 +#endif
30627  #ifdef ARCH_s390
30628    print_s390_disassembler_options (stream);
30629  #endif