target/linux/xburst/files-2.6.32/drivers/mmc/host/jz_mmc.c

   1 /*
   2  *  Copyright (C) 2009, Lars-Peter Clausen <lars@metafoo.de>
   3  *      JZ7420/JZ4740 GPIO SD/MMC controller driver
   4  *
   5  *  This program is free software; you can redistribute  it and/or modify it
   6  *  under  the terms of  the GNU General  Public License as published by the
   7  *  Free Software Foundation;  either version 2 of the  License, or (at your
   8  *  option) any later version.
   9  *
  10  *  You should have received a copy of the  GNU General Public License along
  11  *  with this program; if not, write  to the Free Software Foundation, Inc.,
  12  *  675 Mass Ave, Cambridge, MA 02139, USA.
  13  *
  14  */
  15
  16 #include <linux/mmc/host.h>
  17 #include <linux/io.h>
  18 #include <linux/irq.h>
  19 #include <linux/interrupt.h>
  20 #include <linux/module.h>
  21 #include <linux/platform_device.h>
  22 #include <linux/delay.h>
  23 #include <linux/scatterlist.h>
  24 #include <linux/clk.h>
  25 #include <linux/mmc/jz4740_mmc.h>
  26
  27 #include <linux/gpio.h>
  28 #include <asm/mach-jz4740/gpio.h>
  29 #include <asm/cacheflush.h>
  30 #include <linux/dma-mapping.h>
  31
  32 #define JZ_REG_MMC_STRPCL       0x00
  33 #define JZ_REG_MMC_STATUS       0x04
  34 #define JZ_REG_MMC_CLKRT        0x08
  35 #define JZ_REG_MMC_CMDAT        0x0C
  36 #define JZ_REG_MMC_RESTO        0x10
  37 #define JZ_REG_MMC_RDTO         0x14
  38 #define JZ_REG_MMC_BLKLEN       0x18
  39 #define JZ_REG_MMC_NOB          0x1C
  40 #define JZ_REG_MMC_SNOB         0x20
  41 #define JZ_REG_MMC_IMASK        0x24
  42 #define JZ_REG_MMC_IREG         0x28
  43 #define JZ_REG_MMC_CMD          0x2C
  44 #define JZ_REG_MMC_ARG          0x30
  45 #define JZ_REG_MMC_RESP_FIFO    0x34
  46 #define JZ_REG_MMC_RXFIFO       0x38
  47 #define JZ_REG_MMC_TXFIFO       0x3C
  48
  49 #define JZ_MMC_STRPCL_EXIT_MULTIPLE BIT(7)
  50 #define JZ_MMC_STRPCL_EXIT_TRANSFER BIT(6)
  51 #define JZ_MMC_STRPCL_START_READWAIT BIT(5)
  52 #define JZ_MMC_STRPCL_STOP_READWAIT BIT(4)
  53 #define JZ_MMC_STRPCL_RESET BIT(3)
  54 #define JZ_MMC_STRPCL_START_OP BIT(2)
  55 #define JZ_MMC_STRPCL_CLOCK_CONTROL BIT(1) | BIT(0)
  56 #define JZ_MMC_STRPCL_CLOCK_STOP BIT(0)
  57 #define JZ_MMC_STRPCL_CLOCK_START BIT(1)
  58
  59
  60 #define JZ_MMC_STATUS_IS_RESETTING BIT(15)
  61 #define JZ_MMC_STATUS_SDIO_INT_ACTIVE BIT(14)
  62 #define JZ_MMC_STATUS_PRG_DONE BIT(13)
  63 #define JZ_MMC_STATUS_DATA_TRAN_DONE BIT(12)
  64 #define JZ_MMC_STATUS_END_CMD_RES BIT(11)
  65 #define JZ_MMC_STATUS_DATA_FIFO_AFULL BIT(10)
  66 #define JZ_MMC_STATUS_IS_READWAIT BIT(9)
  67 #define JZ_MMC_STATUS_CLK_EN BIT(8)
  68 #define JZ_MMC_STATUS_DATA_FIFO_FULL BIT(7)
  69 #define JZ_MMC_STATUS_DATA_FIFO_EMPTY BIT(6)
  70 #define JZ_MMC_STATUS_CRC_RES_ERR BIT(5)
  71 #define JZ_MMC_STATUS_CRC_READ_ERROR BIT(4)
  72 #define JZ_MMC_STATUS_TIMEOUT_WRITE BIT(3)
  73 #define JZ_MMC_STATUS_CRC_WRITE_ERROR BIT(2)
  74 #define JZ_MMC_STATUS_TIMEOUT_RES BIT(1)
  75 #define JZ_MMC_STATUS_TIMEOUT_READ BIT(0)
  76
  77 #define JZ_MMC_STATUS_READ_ERROR_MASK (BIT(4) | BIT(0))
  78 #define JZ_MMC_STATUS_WRITE_ERROR_MASK (BIT(3) | BIT(2))
  79
  80
  81 #define JZ_MMC_CMDAT_IO_ABORT BIT(11)
  82 #define JZ_MMC_CMDAT_BUS_WIDTH_4BIT BIT(10)
  83 #define JZ_MMC_CMDAT_DMA_EN BIT(8)
  84 #define JZ_MMC_CMDAT_INIT BIT(7)
  85 #define JZ_MMC_CMDAT_BUSY BIT(6)
  86 #define JZ_MMC_CMDAT_STREAM BIT(5)
  87 #define JZ_MMC_CMDAT_WRITE BIT(4)
  88 #define JZ_MMC_CMDAT_DATA_EN BIT(3)
  89 #define JZ_MMC_CMDAT_RESPONSE_FORMAT BIT(2) | BIT(1) | BIT(0)
  90 #define JZ_MMC_CMDAT_RSP_R1 1
  91 #define JZ_MMC_CMDAT_RSP_R2 2
  92 #define JZ_MMC_CMDAT_RSP_R3 3
  93
  94 #define JZ_MMC_IRQ_SDIO BIT(7)
  95 #define JZ_MMC_IRQ_TXFIFO_WR_REQ BIT(6)
  96 #define JZ_MMC_IRQ_RXFIFO_RD_REQ BIT(5)
  97 #define JZ_MMC_IRQ_END_CMD_RES BIT(2)
  98 #define JZ_MMC_IRQ_PRG_DONE BIT(1)
  99 #define JZ_MMC_IRQ_DATA_TRAN_DONE BIT(0)
 100
 101
 102 #define JZ_MMC_CLK_RATE 24000000
 103
 104 struct jz4740_mmc_host {
 105         struct mmc_host *mmc;
 106         struct platform_device *pdev;
 107         struct jz4740_mmc_platform_data *pdata;
 108         struct clk *clk;
 109
 110         int irq;
 111         int card_detect_irq;
 112
 113         struct resource *mem;
 114         void __iomem *base;
 115         struct mmc_request *req;
 116         struct mmc_command *cmd;
 117
 118         int max_clock;
 119         uint32_t cmdat;
 120
 121         uint16_t irq_mask;
 122
 123         spinlock_t lock;
 124         struct timer_list clock_timer;
 125         struct timer_list timeout_timer;
 126         unsigned waiting:1;
 127 };
 128
 129 static void jz4740_mmc_cmd_done(struct jz4740_mmc_host *host);
 130
 131 static void jz4740_mmc_enable_irq(struct jz4740_mmc_host *host, unsigned int irq)
 132 {
 133         unsigned long flags;
 134         spin_lock_irqsave(&host->lock, flags);
 135
 136         host->irq_mask &= ~irq;
 137         writew(host->irq_mask, host->base + JZ_REG_MMC_IMASK);
 138
 139         spin_unlock_irqrestore(&host->lock, flags);
 140 }
 141
 142 static void jz4740_mmc_disable_irq(struct jz4740_mmc_host *host, unsigned int irq)
 143 {
 144         unsigned long flags;
 145         spin_lock_irqsave(&host->lock, flags);
 146
 147         host->irq_mask |= irq;
 148         writew(host->irq_mask, host->base + JZ_REG_MMC_IMASK);
 149
 150         spin_unlock_irqrestore(&host->lock, flags);
 151 }
 152
 153 static void jz4740_mmc_clock_enable(struct jz4740_mmc_host *host, bool start_transfer)
 154 {
 155         uint16_t val = JZ_MMC_STRPCL_CLOCK_START;
 156
 157         if (start_transfer)
 158                 val |= JZ_MMC_STRPCL_START_OP;
 159
 160         writew(val, host->base + JZ_REG_MMC_STRPCL);
 161 }
 162
 163 static void jz4740_mmc_clock_disable(struct jz4740_mmc_host *host)
 164 {
 165         uint16_t status;
 166         writew(JZ_MMC_STRPCL_CLOCK_STOP, host->base + JZ_REG_MMC_STRPCL);
 167         do {
 168                 status = readl(host->base + JZ_REG_MMC_STATUS);
 169         } while (status & JZ_MMC_STATUS_CLK_EN);
 170
 171 }
 172
 173 static void jz4740_mmc_reset(struct jz4740_mmc_host *host)
 174 {
 175         writew(JZ_MMC_STRPCL_RESET, host->base + JZ_REG_MMC_STRPCL);
 176         udelay(10);
 177         while(readw(host->base + JZ_REG_MMC_STATUS) & JZ_MMC_STATUS_IS_RESETTING);
 178 }
 179
 180 static void jz4740_mmc_request_done(struct jz4740_mmc_host *host)
 181 {
 182         struct mmc_request *req;
 183         unsigned long flags;
 184
 185         spin_lock_irqsave(&host->lock, flags);
 186         req = host->req;
 187         host->req = NULL;
 188         host->waiting = 0;
 189         spin_unlock_irqrestore(&host->lock, flags);
 190
 191         if (!unlikely(req))
 192                 return;
 193
 194 /*      if (req->cmd->error != 0) {
 195                 printk("error\n");
 196                 jz4740_mmc_reset(host);
 197         }*/
 198
 199         mmc_request_done(host->mmc, req);
 200 }
 201
 202 static void jz4740_mmc_write_data(struct jz4740_mmc_host *host, struct mmc_data *data) {
 203         struct scatterlist *sg;
 204         uint32_t *sg_pointer;
 205         int status;
 206         unsigned int timeout;
 207         size_t i, j;
 208
 209         for (sg = data->sg; sg; sg = sg_next(sg)) {
 210                 sg_pointer = sg_virt(sg);
 211                 i = sg->length / 4;
 212                 j = i >> 3;
 213                 i = i & 0x7;
 214                 while (j) {
 215                         timeout = 100000;
 216                         do {
 217                                 status = readw(host->base + JZ_REG_MMC_IREG);
 218                         } while (!(status & JZ_MMC_IRQ_TXFIFO_WR_REQ) && --timeout);
 219                         if (timeout == 0)
 220                                 goto err_timeout;
 221
 222                         writew(JZ_MMC_IRQ_TXFIFO_WR_REQ, host->base + JZ_REG_MMC_IREG);
 223
 224                         writel(sg_pointer[0], host->base + JZ_REG_MMC_TXFIFO);
 225                         writel(sg_pointer[1], host->base + JZ_REG_MMC_TXFIFO);
 226                         writel(sg_pointer[2], host->base + JZ_REG_MMC_TXFIFO);
 227                         writel(sg_pointer[3], host->base + JZ_REG_MMC_TXFIFO);
 228                         writel(sg_pointer[4], host->base + JZ_REG_MMC_TXFIFO);
 229                         writel(sg_pointer[5], host->base + JZ_REG_MMC_TXFIFO);
 230                         writel(sg_pointer[6], host->base + JZ_REG_MMC_TXFIFO);
 231                         writel(sg_pointer[7], host->base + JZ_REG_MMC_TXFIFO);
 232                         sg_pointer += 8;
 233                         --j;
 234                 }
 235                 if (i) {
 236                         timeout = 100000;
 237                         do {
 238                                 status = readw(host->base + JZ_REG_MMC_IREG);
 239                         } while (!(status & JZ_MMC_IRQ_TXFIFO_WR_REQ) && --timeout);
 240                         if (timeout == 0)
 241                                 goto err_timeout;
 242
 243                         writew(JZ_MMC_IRQ_TXFIFO_WR_REQ, host->base + JZ_REG_MMC_IREG);
 244
 245                         while (i) {
 246                                 writel(*sg_pointer, host->base + JZ_REG_MMC_TXFIFO);
 247                                 ++sg_pointer;
 248                                 --i;
 249                         }
 250                 }
 251                 data->bytes_xfered += sg->length;
 252         }
 253
 254         status = readl(host->base + JZ_REG_MMC_STATUS);
 255         if (status & JZ_MMC_STATUS_WRITE_ERROR_MASK)
 256                 goto err;
 257
 258         writew(JZ_MMC_IRQ_TXFIFO_WR_REQ, host->base + JZ_REG_MMC_IREG);
 259         timeout = 100000;
 260         do {
 261                 status = readl(host->base + JZ_REG_MMC_STATUS);
 262         } while ((status & JZ_MMC_STATUS_DATA_TRAN_DONE) == 0 && --timeout);
 263         if (timeout == 0)
 264                 goto err_timeout;
 265         writew(JZ_MMC_IRQ_DATA_TRAN_DONE, host->base + JZ_REG_MMC_IREG);
 266
 267         return;
 268 err_timeout:
 269         host->req->cmd->error = -ETIMEDOUT;
 270         data->error = -ETIMEDOUT;
 271         return;
 272 err:
 273         if(status & (JZ_MMC_STATUS_TIMEOUT_WRITE)) {
 274                 host->req->cmd->error = -ETIMEDOUT;
 275                 data->error = -ETIMEDOUT;
 276         } else {
 277                 host->req->cmd->error = -EILSEQ;
 278                 data->error = -EILSEQ;
 279         }
 280 }
 281
 282 static void jz4740_mmc_timeout(unsigned long data)
 283 {
 284         struct jz4740_mmc_host *host = (struct jz4740_mmc_host*)data;
 285         unsigned long flags;
 286
 287         spin_lock_irqsave(&host->lock, flags);
 288         if (!host->waiting) {
 289                 spin_unlock_irqrestore(&host->lock, flags);
 290                 return;
 291         }
 292
 293         host->waiting = 0;
 294
 295         spin_unlock_irqrestore(&host->lock, flags);
 296
 297         host->req->cmd->error = -ETIMEDOUT;
 298         jz4740_mmc_request_done(host);
 299 }
 300
 301 static void jz4740_mmc_read_data(struct jz4740_mmc_host *host, struct mmc_data *data) {
 302         struct scatterlist *sg;
 303         uint32_t *sg_pointer;
 304         uint32_t d;
 305         uint16_t status = 0;
 306         size_t i, j;
 307         unsigned int timeout;
 308
 309         for (sg = data->sg; sg; sg = sg_next(sg)) {
 310                 sg_pointer = sg_virt(sg);
 311                 i = sg->length;
 312                 j = i >> 5;
 313                 i = i & 0x1f;
 314                 while (j) {
 315                         timeout = 100000;
 316                         do {
 317                                 status = readw(host->base + JZ_REG_MMC_IREG);
 318                         } while (!(status & JZ_MMC_IRQ_RXFIFO_RD_REQ) && --timeout);
 319
 320                         if (unlikely(timeout == 0))
 321                                 goto err_timeout;
 322
 323                         writew(JZ_MMC_IRQ_RXFIFO_RD_REQ, host->base + JZ_REG_MMC_IREG);
 324
 325                         sg_pointer[0] = readl(host->base + JZ_REG_MMC_RXFIFO);
 326                         sg_pointer[1] = readl(host->base + JZ_REG_MMC_RXFIFO);
 327                         sg_pointer[2] = readl(host->base + JZ_REG_MMC_RXFIFO);
 328                         sg_pointer[3] = readl(host->base + JZ_REG_MMC_RXFIFO);
 329                         sg_pointer[4] = readl(host->base + JZ_REG_MMC_RXFIFO);
 330                         sg_pointer[5] = readl(host->base + JZ_REG_MMC_RXFIFO);
 331                         sg_pointer[6] = readl(host->base + JZ_REG_MMC_RXFIFO);
 332                         sg_pointer[7] = readl(host->base + JZ_REG_MMC_RXFIFO);
 333
 334                         sg_pointer += 8;
 335                         --j;
 336                 }
 337
 338                 while (i >= 4) {
 339                         timeout = 100000;
 340                         do {
 341                                 status = readl(host->base + JZ_REG_MMC_STATUS);
 342                         } while ((status & JZ_MMC_STATUS_DATA_FIFO_EMPTY) && --timeout);
 343
 344                         if (unlikely(timeout == 0))
 345                                 goto err_timeout;
 346
 347                         *sg_pointer = readl(host->base + JZ_REG_MMC_RXFIFO);
 348                         ++sg_pointer;
 349                         i -= 4;
 350                 }
 351                 if (i > 0) {
 352                         d = readl(host->base + JZ_REG_MMC_RXFIFO);
 353                         memcpy(sg_pointer, &d, i);
 354                 }
 355                 data->bytes_xfered += sg->length;
 356
 357                 flush_dcache_page(sg_page(sg));
 358         }
 359
 360         status = readl(host->base + JZ_REG_MMC_STATUS);
 361         if (status & JZ_MMC_STATUS_READ_ERROR_MASK)
 362                 goto err;
 363
 364         /* For whatever reason there is sometime one word more in the fifo then
 365          * requested */
 366         while ((status & JZ_MMC_STATUS_DATA_FIFO_EMPTY) == 0 && --timeout) {
 367                 d = readl(host->base + JZ_REG_MMC_RXFIFO);
 368                 status = readl(host->base + JZ_REG_MMC_STATUS);
 369         }
 370         return;
 371 err_timeout:
 372         host->req->cmd->error = -ETIMEDOUT;
 373         data->error = -ETIMEDOUT;
 374         return;
 375 err:
 376         if(status & JZ_MMC_STATUS_TIMEOUT_READ) {
 377                 host->req->cmd->error = -ETIMEDOUT;
 378                 data->error = -ETIMEDOUT;
 379         } else {
 380                 host->req->cmd->error = -EILSEQ;
 381                 data->error = -EILSEQ;
 382         }
 383 }
 384
 385 static irqreturn_t jz_mmc_irq_worker(int irq, void *devid)
 386 {
 387         struct jz4740_mmc_host *host = (struct jz4740_mmc_host*)devid;
 388
 389         if (host->cmd->error)
 390                 jz4740_mmc_request_done(host);
 391         else
 392                 jz4740_mmc_cmd_done(host);
 393
 394         return IRQ_HANDLED;
 395 }
 396
 397 static irqreturn_t jz_mmc_irq(int irq, void *devid)
 398 {
 399         struct jz4740_mmc_host *host = devid;
 400         uint16_t irq_reg, status, tmp;
 401         unsigned long flags;
 402         irqreturn_t ret = IRQ_HANDLED;
 403
 404         irq_reg = readw(host->base + JZ_REG_MMC_IREG);
 405
 406         tmp = irq_reg;
 407         spin_lock_irqsave(&host->lock, flags);
 408         irq_reg &= ~host->irq_mask;
 409         spin_unlock_irqrestore(&host->lock, flags);
 410
 411         tmp &= ~(JZ_MMC_IRQ_TXFIFO_WR_REQ | JZ_MMC_IRQ_RXFIFO_RD_REQ |
 412                         JZ_MMC_IRQ_PRG_DONE | JZ_MMC_IRQ_DATA_TRAN_DONE);
 413
 414         if (tmp != irq_reg) {
 415                 dev_warn(&host->pdev->dev, "Sparse irq: %x\n", tmp & ~irq_reg);
 416                 writew(tmp & ~irq_reg, host->base + JZ_REG_MMC_IREG);
 417         }
 418
 419         if (irq_reg & JZ_MMC_IRQ_SDIO) {
 420                 writew(JZ_MMC_IRQ_SDIO, host->base + JZ_REG_MMC_IREG);
 421                 mmc_signal_sdio_irq(host->mmc);
 422         }
 423
 424         if (!host->req || !host->cmd) {
 425                 goto handled;
 426         }
 427
 428
 429         spin_lock_irqsave(&host->lock, flags);
 430         if (!host->waiting) {
 431                 spin_unlock_irqrestore(&host->lock, flags);
 432                 goto handled;
 433         }
 434
 435         host->waiting = 0;
 436         spin_unlock_irqrestore(&host->lock, flags);
 437
 438         del_timer(&host->timeout_timer);
 439
 440         status = readl(host->base + JZ_REG_MMC_STATUS);
 441
 442         if (status & JZ_MMC_STATUS_TIMEOUT_RES) {
 443                 host->cmd->error = -ETIMEDOUT;
 444         } else if (status & JZ_MMC_STATUS_CRC_RES_ERR) {
 445                 host->cmd->error = -EIO;
 446         } else if(status & (JZ_MMC_STATUS_CRC_READ_ERROR |
 447                                                 JZ_MMC_STATUS_CRC_WRITE_ERROR)) {
 448                 host->cmd->data->error = -EIO;
 449         } else if(status & (JZ_MMC_STATUS_CRC_READ_ERROR |
 450                                                 JZ_MMC_STATUS_CRC_WRITE_ERROR)) {
 451                 host->cmd->data->error = -EIO;
 452         }
 453
 454         if (irq_reg & JZ_MMC_IRQ_END_CMD_RES) {
 455                 jz4740_mmc_disable_irq(host, JZ_MMC_IRQ_END_CMD_RES);
 456                 writew(JZ_MMC_IRQ_END_CMD_RES, host->base + JZ_REG_MMC_IREG);
 457                 ret = IRQ_WAKE_THREAD;
 458         }
 459
 460         return ret;
 461 handled:
 462
 463         writew(0xff, host->base + JZ_REG_MMC_IREG);
 464         return IRQ_HANDLED;
 465 }
 466
 467 static int jz4740_mmc_set_clock_rate(struct jz4740_mmc_host *host, int rate) {
 468         int div = 0;
 469         int real_rate = host->max_clock;
 470         jz4740_mmc_clock_disable(host);
 471
 472         while ((real_rate >> 1) >= rate && div < 7) {
 473                 ++div;
 474                 real_rate >>= 1;
 475         }
 476         clk_set_rate(host->clk, JZ_MMC_CLK_RATE);
 477
 478         writew(div, host->base + JZ_REG_MMC_CLKRT);
 479         return real_rate;
 480 }
 481
 482
 483 static void jz4740_mmc_read_response(struct jz4740_mmc_host *host, struct mmc_command *cmd)
 484 {
 485         int i;
 486         uint16_t tmp;
 487         if (cmd->flags & MMC_RSP_136) {
 488                 tmp = readw(host->base + JZ_REG_MMC_RESP_FIFO);
 489                 for (i = 0; i < 4; ++i) {
 490                         cmd->resp[i] = tmp << 24;
 491                         cmd->resp[i] |= readw(host->base + JZ_REG_MMC_RESP_FIFO) << 8;
 492                         tmp = readw(host->base + JZ_REG_MMC_RESP_FIFO);
 493                         cmd->resp[i] |= tmp >> 8;
 494                 }
 495         } else {
 496                 cmd->resp[0] = readw(host->base + JZ_REG_MMC_RESP_FIFO) << 24;
 497                 cmd->resp[0] |= readw(host->base + JZ_REG_MMC_RESP_FIFO) << 8;
 498                 cmd->resp[0] |= readw(host->base + JZ_REG_MMC_RESP_FIFO) & 0xff;
 499         }
 500 }
 501
 502 static void jz4740_mmc_send_command(struct jz4740_mmc_host *host, struct mmc_command *cmd)
 503 {
 504         uint32_t cmdat = host->cmdat;
 505
 506         host->cmdat &= ~JZ_MMC_CMDAT_INIT;
 507         jz4740_mmc_clock_disable(host);
 508
 509         host->cmd = cmd;
 510
 511         if (cmd->flags & MMC_RSP_BUSY)
 512                 cmdat |= JZ_MMC_CMDAT_BUSY;
 513
 514         switch (mmc_resp_type(cmd)) {
 515         case MMC_RSP_R1B:
 516         case MMC_RSP_R1:
 517                 cmdat |= JZ_MMC_CMDAT_RSP_R1;
 518                 break;
 519         case MMC_RSP_R2:
 520                 cmdat |= JZ_MMC_CMDAT_RSP_R2;
 521                 break;
 522         case MMC_RSP_R3:
 523                 cmdat |= JZ_MMC_CMDAT_RSP_R3;
 524                 break;
 525         default:
 526                 break;
 527         }
 528
 529         if (cmd->data) {
 530                 cmdat |= JZ_MMC_CMDAT_DATA_EN;
 531                 if (cmd->data->flags & MMC_DATA_WRITE)
 532                         cmdat |= JZ_MMC_CMDAT_WRITE;
 533                 if (cmd->data->flags & MMC_DATA_STREAM)
 534                         cmdat |= JZ_MMC_CMDAT_STREAM;
 535
 536                 writew(cmd->data->blksz, host->base + JZ_REG_MMC_BLKLEN);
 537                 writew(cmd->data->blocks, host->base + JZ_REG_MMC_NOB);
 538         }
 539
 540         writeb(cmd->opcode, host->base + JZ_REG_MMC_CMD);
 541         writel(cmd->arg, host->base + JZ_REG_MMC_ARG);
 542         writel(cmdat, host->base + JZ_REG_MMC_CMDAT);
 543
 544         host->waiting = 1;
 545         jz4740_mmc_clock_enable(host, 1);
 546         mod_timer(&host->timeout_timer, 4*HZ);
 547 }
 548
 549 static void jz4740_mmc_cmd_done(struct jz4740_mmc_host *host)
 550 {
 551         uint32_t status;
 552         struct mmc_command *cmd = host->req->cmd;
 553         struct mmc_request *req = host->req;
 554         unsigned int timeout = 100000;
 555         status = readl(host->base + JZ_REG_MMC_STATUS);
 556
 557         if (cmd->flags & MMC_RSP_PRESENT)
 558                 jz4740_mmc_read_response(host, cmd);
 559
 560         if (cmd->data) {
 561                 if (cmd->data->flags & MMC_DATA_READ)
 562                         jz4740_mmc_read_data(host, cmd->data);
 563                 else
 564                         jz4740_mmc_write_data(host, cmd->data);
 565         }
 566
 567         if (req->stop) {
 568                 jz4740_mmc_send_command(host, req->stop);
 569                 do {
 570                         status = readl(host->base + JZ_REG_MMC_STATUS);
 571                 } while ((status & JZ_MMC_STATUS_PRG_DONE) == 0 && --timeout);
 572                 writew(JZ_MMC_IRQ_PRG_DONE, host->base + JZ_REG_MMC_IREG);
 573         }
 574
 575         if (timeout == 0)
 576                 req->stop->error = -ETIMEDOUT;
 577
 578         jz4740_mmc_request_done(host);
 579 }
 580
 581 static void jz4740_mmc_request(struct mmc_host *mmc, struct mmc_request *req)
 582 {
 583         struct jz4740_mmc_host *host = mmc_priv(mmc);
 584
 585         host->req = req;
 586
 587         writew(0xffff, host->base + JZ_REG_MMC_IREG);
 588
 589         writew(JZ_MMC_IRQ_END_CMD_RES, host->base + JZ_REG_MMC_IREG);
 590         jz4740_mmc_enable_irq(host, JZ_MMC_IRQ_END_CMD_RES);
 591         jz4740_mmc_send_command(host, req->cmd);
 592 }
 593
 594
 595 static void jz4740_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
 596 {
 597         struct jz4740_mmc_host *host = mmc_priv(mmc);
 598         if (ios->clock)
 599                 jz4740_mmc_set_clock_rate(host, ios->clock);
 600
 601         switch(ios->power_mode) {
 602         case MMC_POWER_UP:
 603                 jz4740_mmc_reset(host);
 604                 if (gpio_is_valid(host->pdata->gpio_power))
 605                         gpio_set_value(host->pdata->gpio_power,
 606                                         !host->pdata->power_active_low);
 607                 host->cmdat |= JZ_MMC_CMDAT_INIT;
 608                 clk_enable(host->clk);
 609                 break;
 610         case MMC_POWER_ON:
 611                 break;
 612         default:
 613                 if (gpio_is_valid(host->pdata->gpio_power))
 614                         gpio_set_value(host->pdata->gpio_power,
 615                                         host->pdata->power_active_low);
 616                 clk_disable(host->clk);
 617                 break;
 618         }
 619
 620         switch(ios->bus_width) {
 621         case MMC_BUS_WIDTH_1:
 622                 host->cmdat &= ~JZ_MMC_CMDAT_BUS_WIDTH_4BIT;
 623                 break;
 624         case MMC_BUS_WIDTH_4:
 625                 host->cmdat |= JZ_MMC_CMDAT_BUS_WIDTH_4BIT;
 626                 break;
 627         default:
 628                 dev_err(&host->pdev->dev, "Invalid bus width: %d\n", ios->bus_width);
 629         }
 630 }
 631
 632 static int jz4740_mmc_get_ro(struct mmc_host *mmc)
 633 {
 634         struct jz4740_mmc_host *host = mmc_priv(mmc);
 635         if (!gpio_is_valid(host->pdata->gpio_read_only))
 636                 return -ENOSYS;
 637
 638         return gpio_get_value(host->pdata->gpio_read_only) ^
 639                 host->pdata->read_only_active_low;
 640 }
 641
 642 static int jz4740_mmc_get_cd(struct mmc_host *mmc)
 643 {
 644         struct jz4740_mmc_host *host = mmc_priv(mmc);
 645         if (!gpio_is_valid(host->pdata->gpio_card_detect))
 646                 return -ENOSYS;
 647
 648         return gpio_get_value(host->pdata->gpio_card_detect) ^
 649                         host->pdata->card_detect_active_low;
 650 }
 651
 652 static irqreturn_t jz4740_mmc_card_detect_irq(int irq, void *devid)
 653 {
 654         struct jz4740_mmc_host *host = devid;
 655
 656         mmc_detect_change(host->mmc, HZ / 3);
 657
 658         return IRQ_HANDLED;
 659 }
 660
 661 static void jz4740_mmc_enable_sdio_irq(struct mmc_host *mmc, int enable)
 662 {
 663         struct jz4740_mmc_host *host = mmc_priv(mmc);
 664         if (enable)
 665                 jz4740_mmc_enable_irq(host, JZ_MMC_IRQ_SDIO);
 666         else
 667                 jz4740_mmc_disable_irq(host, JZ_MMC_IRQ_SDIO);
 668 }
 669
 670 static const struct mmc_host_ops jz4740_mmc_ops = {
 671         .request        = jz4740_mmc_request,
 672         .set_ios        = jz4740_mmc_set_ios,
 673         .get_ro         = jz4740_mmc_get_ro,
 674         .get_cd         = jz4740_mmc_get_cd,
 675         .enable_sdio_irq = jz4740_mmc_enable_sdio_irq,
 676 };
 677
 678 static const struct jz_gpio_bulk_request jz4740_mmc_pins[] = {
 679         JZ_GPIO_BULK_PIN(MSC_CMD),
 680         JZ_GPIO_BULK_PIN(MSC_CLK),
 681         JZ_GPIO_BULK_PIN(MSC_DATA0),
 682         JZ_GPIO_BULK_PIN(MSC_DATA1),
 683         JZ_GPIO_BULK_PIN(MSC_DATA2),
 684         JZ_GPIO_BULK_PIN(MSC_DATA3),
 685 };
 686
 687 static int __devinit jz4740_mmc_request_gpios(struct platform_device *pdev)
 688 {
 689         int ret;
 690         struct jz4740_mmc_platform_data *pdata = pdev->dev.platform_data;
 691
 692         if (!pdata)
 693                 return 0;
 694
 695         if (gpio_is_valid(pdata->gpio_card_detect)) {
 696                 ret = gpio_request(pdata->gpio_card_detect, "MMC detect change");
 697                 if (ret) {
 698                         dev_err(&pdev->dev, "Failed to request detect change gpio\n");
 699                         goto err;
 700                 }
 701                 gpio_direction_input(pdata->gpio_card_detect);
 702         }
 703
 704         if (gpio_is_valid(pdata->gpio_read_only)) {
 705                 ret = gpio_request(pdata->gpio_read_only, "MMC read only");
 706                 if (ret) {
 707                         dev_err(&pdev->dev, "Failed to request read only gpio: %d\n", ret);
 708                         goto err_free_gpio_card_detect;
 709                 }
 710                 gpio_direction_input(pdata->gpio_read_only);
 711         }
 712
 713         if (gpio_is_valid(pdata->gpio_power)) {
 714                 ret = gpio_request(pdata->gpio_power, "MMC power");
 715                 if (ret) {
 716                         dev_err(&pdev->dev, "Failed to request power gpio: %d\n", ret);
 717                         goto err_free_gpio_read_only;
 718                 }
 719                 gpio_direction_output(pdata->gpio_power, pdata->power_active_low);
 720         }
 721
 722         return 0;
 723
 724 err_free_gpio_read_only:
 725         if (gpio_is_valid(pdata->gpio_read_only))
 726                 gpio_free(pdata->gpio_read_only);
 727 err_free_gpio_card_detect:
 728         if (gpio_is_valid(pdata->gpio_card_detect))
 729                 gpio_free(pdata->gpio_card_detect);
 730 err:
 731         return ret;
 732 }
 733
 734 static void jz4740_mmc_free_gpios(struct platform_device *pdev)
 735 {
 736         struct jz4740_mmc_platform_data *pdata = pdev->dev.platform_data;
 737
 738         if (!pdata)
 739                 return;
 740
 741         if (gpio_is_valid(pdata->gpio_power))
 742                 gpio_free(pdata->gpio_power);
 743         if (gpio_is_valid(pdata->gpio_read_only))
 744                 gpio_free(pdata->gpio_read_only);
 745         if (gpio_is_valid(pdata->gpio_card_detect))
 746                 gpio_free(pdata->gpio_card_detect);
 747 }
 748
 749 static int __devinit jz4740_mmc_probe(struct platform_device* pdev)
 750 {
 751         int ret;
 752         struct mmc_host *mmc;
 753         struct jz4740_mmc_host *host;
 754         struct jz4740_mmc_platform_data *pdata;
 755
 756         pdata = pdev->dev.platform_data;
 757
 758         mmc = mmc_alloc_host(sizeof(struct jz4740_mmc_host), &pdev->dev);
 759
 760         if (!mmc) {
 761                 dev_err(&pdev->dev, "Failed to alloc mmc host structure\n");
 762                 return -ENOMEM;
 763         }
 764
 765         host = mmc_priv(mmc);
 766
 767         host->irq = platform_get_irq(pdev, 0);
 768
 769         if (host->irq < 0) {
 770                 ret = host->irq;
 771                 dev_err(&pdev->dev, "Failed to get platform irq: %d\n", ret);
 772                 goto err_free_host;
 773         }
 774
 775         host->clk = clk_get(&pdev->dev, "mmc");
 776         if (!host->clk) {
 777                 ret = -ENOENT;
 778                 dev_err(&pdev->dev, "Failed to get mmc clock\n");
 779                 goto err_free_host;
 780         }
 781
 782         host->mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 783
 784         if (!host->mem) {
 785                 ret = -ENOENT;
 786                 dev_err(&pdev->dev, "Failed to get base platform memory\n");
 787                 goto err_clk_put;
 788         }
 789
 790         host->mem = request_mem_region(host->mem->start, resource_size(host->mem),
 791                                         pdev->name);
 792
 793         if (!host->mem) {
 794                 ret = -EBUSY;
 795                 dev_err(&pdev->dev, "Failed to request base memory region\n");
 796                 goto err_clk_put;
 797         }
 798
 799         host->base = ioremap_nocache(host->mem->start, resource_size(host->mem));
 800
 801         if (!host->base) {
 802                 ret = -EBUSY;
 803                 dev_err(&pdev->dev, "Failed to ioremap base memory\n");
 804                 goto err_release_mem_region;
 805         }
 806
 807         if (pdata && pdata->data_1bit)
 808                 ret = jz_gpio_bulk_request(jz4740_mmc_pins, ARRAY_SIZE(jz4740_mmc_pins) - 3);
 809         else
 810                 ret = jz_gpio_bulk_request(jz4740_mmc_pins, ARRAY_SIZE(jz4740_mmc_pins));
 811
 812         if (ret) {
 813                 dev_err(&pdev->dev, "Failed to request function pins: %d\n", ret);
 814                 goto err_iounmap;
 815         }
 816
 817         ret = jz4740_mmc_request_gpios(pdev);
 818         if (ret)
 819                 goto err_gpio_bulk_free;
 820
 821         mmc->ops = &jz4740_mmc_ops;
 822         mmc->f_min = JZ_MMC_CLK_RATE / 128;
 823         mmc->f_max = JZ_MMC_CLK_RATE;
 824         mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34;
 825         mmc->caps = (pdata && pdata->data_1bit) ? 0 : MMC_CAP_4_BIT_DATA;
 826         mmc->caps |= MMC_CAP_SDIO_IRQ;
 827         mmc->max_seg_size = 4096;
 828         mmc->max_phys_segs = 128;
 829
 830         mmc->max_blk_size = (1 << 10) - 1;
 831         mmc->max_blk_count = (1 << 15) - 1;
 832         mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
 833
 834         host->mmc = mmc;
 835         host->pdev = pdev;
 836         host->pdata = pdata;
 837         host->max_clock = JZ_MMC_CLK_RATE;
 838         spin_lock_init(&host->lock);
 839         host->irq_mask = 0xffff;
 840
 841         host->card_detect_irq = gpio_to_irq(pdata->gpio_card_detect);
 842
 843         if (host->card_detect_irq < 0) {
 844                 dev_warn(&pdev->dev, "Failed to get irq for card detect gpio\n");
 845         } else {
 846                 ret = request_irq(host->card_detect_irq,
 847                                 jz4740_mmc_card_detect_irq, IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING, "MMC/SD detect changed", host);
 848
 849                 if (ret) {
 850                         dev_err(&pdev->dev, "Failed to request card detect irq");
 851                         goto err_free_gpios;
 852                 }
 853         }
 854
 855         ret = request_threaded_irq(host->irq, jz_mmc_irq, jz_mmc_irq_worker, IRQF_DISABLED, "MMC/SD", host);
 856         if (ret) {
 857                 dev_err(&pdev->dev, "Failed to request irq: %d\n", ret);
 858                 goto err_free_card_detect_irq;
 859         }
 860
 861         jz4740_mmc_reset(host);
 862         jz4740_mmc_clock_disable(host);
 863         setup_timer(&host->timeout_timer, jz4740_mmc_timeout, (unsigned long)host);
 864
 865         platform_set_drvdata(pdev, host);
 866         ret = mmc_add_host(mmc);
 867
 868         if (ret) {
 869                 dev_err(&pdev->dev, "Failed to add mmc host: %d\n", ret);
 870                 goto err_free_irq;
 871         }
 872         printk("JZ SD/MMC card driver registered\n");
 873
 874         return 0;
 875
 876 err_free_irq:
 877         free_irq(host->irq, host);
 878 err_free_card_detect_irq:
 879         if (host->card_detect_irq >= 0)
 880                 free_irq(host->card_detect_irq, host);
 881 err_free_gpios:
 882         jz4740_mmc_free_gpios(pdev);
 883 err_gpio_bulk_free:
 884         if (pdata && pdata->data_1bit)
 885                 jz_gpio_bulk_free(jz4740_mmc_pins, ARRAY_SIZE(jz4740_mmc_pins) - 3);
 886         else
 887                 jz_gpio_bulk_free(jz4740_mmc_pins, ARRAY_SIZE(jz4740_mmc_pins));
 888 err_iounmap:
 889         iounmap(host->base);
 890 err_release_mem_region:
 891         release_mem_region(host->mem->start, resource_size(host->mem));
 892 err_clk_put:
 893         clk_put(host->clk);
 894 err_free_host:
 895         platform_set_drvdata(pdev, NULL);
 896         mmc_free_host(mmc);
 897
 898         return ret;
 899 }
 900
 901 static int jz4740_mmc_remove(struct platform_device *pdev)
 902 {
 903         struct jz4740_mmc_host *host = platform_get_drvdata(pdev);
 904         struct jz4740_mmc_platform_data *pdata = host->pdata;
 905
 906         del_timer_sync(&host->timeout_timer);
 907         jz4740_mmc_disable_irq(host, 0xff);
 908         jz4740_mmc_reset(host);
 909
 910         mmc_remove_host(host->mmc);
 911
 912         free_irq(host->irq, host);
 913         if (host->card_detect_irq >= 0)
 914                 free_irq(host->card_detect_irq, host);
 915
 916         jz4740_mmc_free_gpios(pdev);
 917         if (pdata && pdata->data_1bit)
 918                 jz_gpio_bulk_free(jz4740_mmc_pins, ARRAY_SIZE(jz4740_mmc_pins) - 3);
 919         else
 920                 jz_gpio_bulk_free(jz4740_mmc_pins, ARRAY_SIZE(jz4740_mmc_pins));
 921
 922         iounmap(host->base);
 923         release_mem_region(host->mem->start, resource_size(host->mem));
 924
 925         clk_put(host->clk);
 926
 927         platform_set_drvdata(pdev, NULL);
 928         mmc_free_host(host->mmc);
 929
 930         return 0;
 931 }
 932
 933 #ifdef CONFIG_PM
 934 static int jz4740_mmc_suspend(struct device *dev)
 935 {
 936         struct jz4740_mmc_host *host = dev_get_drvdata(dev);
 937         struct jz4740_mmc_platform_data *pdata = host->pdata;
 938
 939         mmc_suspend_host(host->mmc, PMSG_SUSPEND);
 940
 941         if (pdata && pdata->data_1bit)
 942                 jz_gpio_bulk_suspend(jz4740_mmc_pins, ARRAY_SIZE(jz4740_mmc_pins) - 3);
 943         else
 944                 jz_gpio_bulk_suspend(jz4740_mmc_pins, ARRAY_SIZE(jz4740_mmc_pins));
 945
 946         return 0;
 947 }
 948
 949 static int jz4740_mmc_resume(struct device *dev)
 950 {
 951         struct jz4740_mmc_host *host = dev_get_drvdata(dev);
 952         struct jz4740_mmc_platform_data *pdata = host->pdata;
 953
 954         if (pdata && pdata->data_1bit)
 955                 jz_gpio_bulk_resume(jz4740_mmc_pins, ARRAY_SIZE(jz4740_mmc_pins) - 3);
 956         else
 957                 jz_gpio_bulk_resume(jz4740_mmc_pins, ARRAY_SIZE(jz4740_mmc_pins));
 958
 959         mmc_resume_host(host->mmc);
 960
 961         return 0;
 962 }
 963
 964 struct dev_pm_ops jz4740_mmc_pm_ops = {
 965         .suspend        = jz4740_mmc_suspend,
 966         .resume         = jz4740_mmc_resume,
 967         .poweroff       = jz4740_mmc_suspend,
 968         .restore        = jz4740_mmc_resume,
 969 };
 970
 971 #define jz4740_mmc_PM_OPS (&jz4740_mmc_pm_ops)
 972 #else
 973 #define jz4740_mmc_PM_OPS NULL
 974 #endif
 975
 976 static struct platform_driver jz4740_mmc_driver = {
 977         .probe = jz4740_mmc_probe,
 978         .remove = jz4740_mmc_remove,
 979         .driver = {
 980                 .name = "jz4740-mmc",
 981                 .owner = THIS_MODULE,
 982                 .pm = jz4740_mmc_PM_OPS,
 983         },
 984 };
 985
 986 static int __init jz4740_mmc_init(void) {
 987         return platform_driver_register(&jz4740_mmc_driver);
 988 }
 989 module_init(jz4740_mmc_init);
 990
 991 static void __exit jz4740_mmc_exit(void) {
 992         platform_driver_unregister(&jz4740_mmc_driver);
 993 }
 994 module_exit(jz4740_mmc_exit);
 995
 996 MODULE_DESCRIPTION("JZ4720/JZ4740 SD/MMC controller driver");
 997 MODULE_LICENSE("GPL");
 998 MODULE_AUTHOR("Lars-Peter Clausen <lars@metafoo.de>");