target/linux/sunxi/patches-4.1/165-asoc-add-sunxi-codec.patch

   1 From 97dcb50623db12f13c9c9a8b68dca61901b7f030 Mon Sep 17 00:00:00 2001
   2 From: =?UTF-8?q?Emilio=20L=C3=B3pez?= <emilio@elopez.com.ar>
   3 Date: Mon, 14 Jul 2014 20:25:23 -0300
   4 Subject: [PATCH] ASoC: sunxi: add support for the on-chip codec on early
   5  Allwinner SoCs
   6
   7 The sun4i, sun5i and sun7i SoC families have a built-in codec, capable
   8 of both audio capture and playback. This memory-mapped device can be fed
   9 with audio data via the Allwinner DMA controller.
  10
  11 Signed-off-by: Hans de Goede <hdegoede@redhat.com>
  12 ---
  13  sound/soc/Kconfig             |   1 +
  14  sound/soc/Makefile            |   1 +
  15  sound/soc/sunxi/Kconfig       |  10 +
  16  sound/soc/sunxi/Makefile      |   2 +
  17  sound/soc/sunxi/sunxi-codec.c | 802 ++++++++++++++++++++++++++++++++++++++++++
  18  5 files changed, 816 insertions(+)
  19  create mode 100644 sound/soc/sunxi/Kconfig
  20  create mode 100644 sound/soc/sunxi/Makefile
  21  create mode 100644 sound/soc/sunxi/sunxi-codec.c
  22
  23 diff --git a/sound/soc/Kconfig b/sound/soc/Kconfig
  24 index 3ba52da..87dbf48 100644
  25 --- a/sound/soc/Kconfig
  26 +++ b/sound/soc/Kconfig
  27 @@ -53,6 +53,7 @@ source "sound/soc/samsung/Kconfig"
  28  source "sound/soc/sh/Kconfig"
  29  source "sound/soc/sirf/Kconfig"
  30  source "sound/soc/spear/Kconfig"
  31 +source "sound/soc/sunxi/Kconfig"
  32  source "sound/soc/tegra/Kconfig"
  33  source "sound/soc/txx9/Kconfig"
  34  source "sound/soc/ux500/Kconfig"
  35 diff --git a/sound/soc/Makefile b/sound/soc/Makefile
  36 index 974ba70..39011b8 100644
  37 --- a/sound/soc/Makefile
  38 +++ b/sound/soc/Makefile
  39 @@ -34,6 +34,7 @@ obj-$(CONFIG_SND_SOC) += samsung/
  40  obj-$(CONFIG_SND_SOC)  += sh/
  41  obj-$(CONFIG_SND_SOC)  += sirf/
  42  obj-$(CONFIG_SND_SOC)  += spear/
  43 +obj-$(CONFIG_SND_SOC)  += sunxi/
  44  obj-$(CONFIG_SND_SOC)  += tegra/
  45  obj-$(CONFIG_SND_SOC)  += txx9/
  46  obj-$(CONFIG_SND_SOC)  += ux500/
  47 diff --git a/sound/soc/sunxi/Kconfig b/sound/soc/sunxi/Kconfig
  48 new file mode 100644
  49 index 0000000..79511ae
  50 --- /dev/null
  51 +++ b/sound/soc/sunxi/Kconfig
  52 @@ -0,0 +1,10 @@
  53 +menu "SoC Audio support for Allwinner SoCs"
  54 +        depends on ARCH_SUNXI
  55 +
  56 +config SND_SUNXI_SOC_CODEC
  57 +       tristate "APB on-chip sun4i/sun5i/sun7i CODEC"
  58 +       select SND_SOC_GENERIC_DMAENGINE_PCM
  59 +       select REGMAP_MMIO
  60 +       default y
  61 +
  62 +endmenu
  63 diff --git a/sound/soc/sunxi/Makefile b/sound/soc/sunxi/Makefile
  64 new file mode 100644
  65 index 0000000..b8950d3
  66 --- /dev/null
  67 +++ b/sound/soc/sunxi/Makefile
  68 @@ -0,0 +1,2 @@
  69 +obj-$(CONFIG_SND_SUNXI_SOC_CODEC) += sunxi-codec.o
  70 +
  71 diff --git a/sound/soc/sunxi/sunxi-codec.c b/sound/soc/sunxi/sunxi-codec.c
  72 new file mode 100644
  73 index 0000000..67f978e
  74 --- /dev/null
  75 +++ b/sound/soc/sunxi/sunxi-codec.c
  76 @@ -0,0 +1,802 @@
  77 +/*
  78 + * Copyright 2014 Emilio López <emilio@elopez.com.ar>
  79 + * Copyright 2014 Jon Smirl <jonsmirl@gmail.com>
  80 + *
  81 + * Based on the Allwinner SDK driver, released under the GPL.
  82 + *
  83 + * This program is free software; you can redistribute it and/or modify
  84 + * it under the terms of the GNU General Public License as published by
  85 + * the Free Software Foundation; either version 2 of the License, or
  86 + * (at your option) any later version.
  87 + *
  88 + * This program is distributed in the hope that it will be useful,
  89 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
  90 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  91 + * GNU General Public License for more details.
  92 + */
  93 +
  94 +#include <linux/init.h>
  95 +#include <linux/kernel.h>
  96 +#include <linux/module.h>
  97 +#include <linux/platform_device.h>
  98 +#include <linux/delay.h>
  99 +#include <linux/slab.h>
 100 +#include <linux/of.h>
 101 +#include <linux/of_platform.h>
 102 +#include <linux/of_address.h>
 103 +#include <linux/clk.h>
 104 +#include <linux/regmap.h>
 105 +
 106 +#include <sound/core.h>
 107 +#include <sound/pcm.h>
 108 +#include <sound/pcm_params.h>
 109 +#include <sound/soc.h>
 110 +#include <sound/tlv.h>
 111 +#include <sound/initval.h>
 112 +#include <sound/dmaengine_pcm.h>
 113 +
 114 +/* Codec DAC register offsets and bit fields */
 115 +#define SUNXI_DAC_DPC                  (0x00)
 116 +#define SUNXI_DAC_DPC_EN_DA                    (31)
 117 +#define SUNXI_DAC_DPC_DVOL                     (12)
 118 +#define SUNXI_DAC_FIFOC                        (0x04)
 119 +#define SUNXI_DAC_FIFOC_DAC_FS                 (29)
 120 +#define SUNXI_DAC_FIFOC_FIR_VERSION            (28)
 121 +#define SUNXI_DAC_FIFOC_SEND_LASAT             (26)
 122 +#define SUNXI_DAC_FIFOC_TX_FIFO_MODE           (24)
 123 +#define SUNXI_DAC_FIFOC_DRQ_CLR_CNT            (21)
 124 +#define SUNXI_DAC_FIFOC_TX_TRIG_LEVEL          (8)
 125 +#define SUNXI_DAC_FIFOC_MONO_EN                        (6)
 126 +#define SUNXI_DAC_FIFOC_TX_SAMPLE_BITS         (5)
 127 +#define SUNXI_DAC_FIFOC_DAC_DRQ_EN             (4)
 128 +#define SUNXI_DAC_FIFOC_FIFO_FLUSH             (0)
 129 +#define SUNXI_DAC_FIFOS                        (0x08)
 130 +#define SUNXI_DAC_TXDATA               (0x0c)
 131 +#define SUNXI_DAC_ACTL                 (0x10)
 132 +#define SUNXI_DAC_ACTL_DACAENR                 (31)
 133 +#define SUNXI_DAC_ACTL_DACAENL                 (30)
 134 +#define SUNXI_DAC_ACTL_MIXEN                   (29)
 135 +#define SUNXI_DAC_ACTL_LDACLMIXS               (15)
 136 +#define SUNXI_DAC_ACTL_RDACRMIXS               (14)
 137 +#define SUNXI_DAC_ACTL_LDACRMIXS               (13)
 138 +#define SUNXI_DAC_ACTL_DACPAS                  (8)
 139 +#define SUNXI_DAC_ACTL_MIXPAS                  (7)
 140 +#define SUNXI_DAC_ACTL_PA_MUTE                 (6)
 141 +#define SUNXI_DAC_ACTL_PA_VOL                  (0)
 142 +#define SUNXI_DAC_TUNE                 (0x14)
 143 +#define SUNXI_DAC_DEBUG                        (0x18)
 144 +
 145 +/* Codec ADC register offsets and bit fields */
 146 +#define SUNXI_ADC_FIFOC                        (0x1c)
 147 +#define SUNXI_ADC_FIFOC_EN_AD                  (28)
 148 +#define SUNXI_ADC_FIFOC_RX_FIFO_MODE           (24)
 149 +#define SUNXI_ADC_FIFOC_RX_TRIG_LEVEL          (8)
 150 +#define SUNXI_ADC_FIFOC_MONO_EN                        (7)
 151 +#define SUNXI_ADC_FIFOC_RX_SAMPLE_BITS         (6)
 152 +#define SUNXI_ADC_FIFOC_ADC_DRQ_EN             (4)
 153 +#define SUNXI_ADC_FIFOC_FIFO_FLUSH             (0)
 154 +#define SUNXI_ADC_FIFOS                        (0x20)
 155 +#define SUNXI_ADC_RXDATA               (0x24)
 156 +#define SUNXI_ADC_ACTL                 (0x28)
 157 +#define SUNXI_ADC_ACTL_ADCREN                  (31)
 158 +#define SUNXI_ADC_ACTL_ADCLEN                  (30)
 159 +#define SUNXI_ADC_ACTL_PREG1EN                 (29)
 160 +#define SUNXI_ADC_ACTL_PREG2EN                 (28)
 161 +#define SUNXI_ADC_ACTL_VMICEN                  (27)
 162 +#define SUNXI_ADC_ACTL_VADCG                   (20)
 163 +#define SUNXI_ADC_ACTL_ADCIS                   (17)
 164 +#define SUNXI_ADC_ACTL_PA_EN                   (4)
 165 +#define SUNXI_ADC_ACTL_DDE                     (3)
 166 +#define SUNXI_ADC_DEBUG                        (0x2c)
 167 +
 168 +/* Other various ADC registers */
 169 +#define SUNXI_DAC_TXCNT                        (0x30)
 170 +#define SUNXI_ADC_RXCNT                        (0x34)
 171 +#define SUNXI_AC_SYS_VERI              (0x38)
 172 +#define SUNXI_AC_MIC_PHONE_CAL         (0x3c)
 173 +
 174 +/* Supported SoC families - used for quirks */
 175 +enum sunxi_soc_family {
 176 +       SUN4IA, /* A10 SoC - revision A */
 177 +       SUN4I,  /* A10 SoC - later revisions */
 178 +       SUN5I,  /* A10S/A13 SoCs */
 179 +       SUN7I,  /* A20 SoC */
 180 +};
 181 +
 182 +struct sunxi_priv {
 183 +       struct regmap *regmap;
 184 +       struct clk *clk_apb, *clk_module;
 185 +
 186 +       enum sunxi_soc_family revision;
 187 +
 188 +       struct snd_dmaengine_dai_dma_data playback_dma_data;
 189 +       struct snd_dmaengine_dai_dma_data capture_dma_data;
 190 +};
 191 +
 192 +static void sunxi_codec_play_start(struct sunxi_priv *priv)
 193 +{
 194 +       /* TODO: see if we need to drive PA GPIO high */
 195 +
 196 +       /* flush TX FIFO */
 197 +       regmap_update_bits(priv->regmap, SUNXI_DAC_FIFOC, 0x1 << SUNXI_DAC_FIFOC_FIFO_FLUSH, 0x1 << SUNXI_DAC_FIFOC_FIFO_FLUSH);
 198 +
 199 +       /* enable DAC DRQ */
 200 +       regmap_update_bits(priv->regmap, SUNXI_DAC_FIFOC, 0x1 << SUNXI_DAC_FIFOC_DAC_DRQ_EN, 0x1 << SUNXI_DAC_FIFOC_DAC_DRQ_EN);
 201 +}
 202 +
 203 +static void sunxi_codec_play_stop(struct sunxi_priv *priv)
 204 +{
 205 +       /* TODO: see if we need to drive PA GPIO low */
 206 +
 207 +       /* disable DAC DRQ */
 208 +       regmap_update_bits(priv->regmap, SUNXI_DAC_FIFOC, 0x1 << SUNXI_DAC_FIFOC_DAC_DRQ_EN, 0x0 << SUNXI_DAC_FIFOC_DAC_DRQ_EN);
 209 +}
 210 +
 211 +static void sunxi_codec_capture_start(struct sunxi_priv *priv)
 212 +{
 213 +       /* TODO: see if we need to drive PA GPIO high */
 214 +
 215 +       /* enable ADC DRQ */
 216 +       regmap_update_bits(priv->regmap, SUNXI_ADC_FIFOC, 0x1 << SUNXI_ADC_FIFOC_ADC_DRQ_EN, 0x1 << SUNXI_ADC_FIFOC_ADC_DRQ_EN);
 217 +}
 218 +
 219 +static void sunxi_codec_capture_stop(struct sunxi_priv *priv)
 220 +{
 221 +       /* disable ADC DRQ */
 222 +       regmap_update_bits(priv->regmap, SUNXI_ADC_FIFOC, 0x1 << SUNXI_ADC_FIFOC_ADC_DRQ_EN, 0x0 << SUNXI_ADC_FIFOC_ADC_DRQ_EN);
 223 +
 224 +       /* enable mic1 PA */
 225 +       regmap_update_bits(priv->regmap, SUNXI_ADC_ACTL, 0x1 << SUNXI_ADC_ACTL_PREG1EN, 0x0 << SUNXI_ADC_ACTL_PREG1EN);
 226 +
 227 +       /* enable VMIC */
 228 +       regmap_update_bits(priv->regmap, SUNXI_ADC_ACTL, 0x1 << SUNXI_ADC_ACTL_VMICEN, 0x0 << SUNXI_ADC_ACTL_VMICEN);
 229 +       if (priv->revision == SUN7I) {
 230 +               /* TODO: undocumented */
 231 +               regmap_update_bits(priv->regmap, SUNXI_DAC_TUNE, 0x3 << 8, 0x0 << 8);
 232 +       }
 233 +
 234 +       /* enable ADC digital */
 235 +       regmap_update_bits(priv->regmap, SUNXI_ADC_FIFOC, 0x1 << SUNXI_ADC_FIFOC_EN_AD, 0x0 << SUNXI_ADC_FIFOC_EN_AD);
 236 +
 237 +       /* set RX FIFO mode */
 238 +       regmap_update_bits(priv->regmap, SUNXI_ADC_FIFOC, 0x1 << SUNXI_ADC_FIFOC_RX_FIFO_MODE, 0x0 << SUNXI_ADC_FIFOC_RX_FIFO_MODE);
 239 +
 240 +       /* flush RX FIFO */
 241 +       regmap_update_bits(priv->regmap, SUNXI_ADC_FIFOC, 0x1 << SUNXI_ADC_FIFOC_FIFO_FLUSH, 0x0 << SUNXI_ADC_FIFOC_FIFO_FLUSH);
 242 +
 243 +       /* enable adc1 analog */
 244 +       regmap_update_bits(priv->regmap, SUNXI_ADC_ACTL, 0x3 << SUNXI_ADC_ACTL_ADCLEN, 0x0 << SUNXI_ADC_ACTL_ADCLEN);
 245 +}
 246 +
 247 +static int sunxi_codec_trigger(struct snd_pcm_substream *substream, int cmd,
 248 +                              struct snd_soc_dai *dai)
 249 +{
 250 +       struct snd_soc_pcm_runtime *rtd = substream->private_data;
 251 +       struct sunxi_priv *priv = snd_soc_card_get_drvdata(rtd->card);
 252 +
 253 +       switch (cmd) {
 254 +       case SNDRV_PCM_TRIGGER_START:
 255 +       case SNDRV_PCM_TRIGGER_RESUME:
 256 +       case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
 257 +               if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
 258 +                       sunxi_codec_capture_start(priv);
 259 +               else
 260 +                       sunxi_codec_play_start(priv);
 261 +               break;
 262 +       case SNDRV_PCM_TRIGGER_STOP:
 263 +       case SNDRV_PCM_TRIGGER_SUSPEND:
 264 +       case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
 265 +               if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
 266 +                       sunxi_codec_capture_stop(priv);
 267 +               else
 268 +                       sunxi_codec_play_stop(priv);
 269 +               break;
 270 +       default:
 271 +               return -EINVAL;
 272 +       }
 273 +
 274 +       return 0;
 275 +}
 276 +
 277 +static int sunxi_codec_prepare(struct snd_pcm_substream *substream,
 278 +                              struct snd_soc_dai *dai)
 279 +{
 280 +       struct snd_soc_pcm_runtime *rtd = substream->private_data;
 281 +       struct sunxi_priv *priv = snd_soc_card_get_drvdata(rtd->card);
 282 +
 283 +       if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
 284 +               regmap_update_bits(priv->regmap, SUNXI_DAC_FIFOC, 0x1 << SUNXI_DAC_FIFOC_FIFO_FLUSH, 0x1 << SUNXI_DAC_FIFOC_FIFO_FLUSH);
 285 +
 286 +               /* set TX FIFO send DRQ level */
 287 +               regmap_update_bits(priv->regmap, SUNXI_DAC_FIFOC, 0x3f << SUNXI_DAC_FIFOC_TX_TRIG_LEVEL, 0xf << SUNXI_DAC_FIFOC_TX_TRIG_LEVEL);
 288 +               if (substream->runtime->rate > 32000) {
 289 +                       regmap_update_bits(priv->regmap, SUNXI_DAC_FIFOC, 0x1 << SUNXI_DAC_FIFOC_FIR_VERSION, 0x0 << SUNXI_DAC_FIFOC_FIR_VERSION);
 290 +               } else {
 291 +                       regmap_update_bits(priv->regmap, SUNXI_DAC_FIFOC, 0x1 << SUNXI_DAC_FIFOC_FIR_VERSION, 0x1 << SUNXI_DAC_FIFOC_FIR_VERSION);
 292 +               }
 293 +
 294 +               /* set TX FIFO MODE - 0 works for both 16 and 24 bits */
 295 +               regmap_update_bits(priv->regmap, SUNXI_DAC_FIFOC, 0x1 << SUNXI_DAC_FIFOC_TX_FIFO_MODE, 0x0 << SUNXI_DAC_FIFOC_TX_FIFO_MODE);
 296 +
 297 +               /* send last sample when DAC FIFO under run */
 298 +               regmap_update_bits(priv->regmap, SUNXI_DAC_FIFOC, 0x1 << SUNXI_DAC_FIFOC_SEND_LASAT, 0x0 << SUNXI_DAC_FIFOC_SEND_LASAT);
 299 +       } else {
 300 +               /* enable mic1 PA */
 301 +               regmap_update_bits(priv->regmap, SUNXI_ADC_ACTL, 0x1 << SUNXI_ADC_ACTL_PREG1EN, 0x1 << SUNXI_ADC_ACTL_PREG1EN);
 302 +
 303 +               /* mic1 gain 32dB */  /* FIXME - makes no sense */
 304 +               regmap_update_bits(priv->regmap, SUNXI_ADC_ACTL, 0x3 << 25, 0x1 << 25);
 305 +
 306 +               /* enable VMIC */
 307 +               regmap_update_bits(priv->regmap, SUNXI_ADC_ACTL, 0x1 << SUNXI_ADC_ACTL_VMICEN, 0x1 << SUNXI_ADC_ACTL_VMICEN);
 308 +
 309 +               if (priv->revision == SUN7I) {
 310 +                       /* boost up record effect */
 311 +                       regmap_update_bits(priv->regmap, SUNXI_DAC_TUNE, 0x3 << 8, 0x1 << 8);
 312 +               }
 313 +
 314 +               /* enable ADC digital */
 315 +               regmap_update_bits(priv->regmap, SUNXI_ADC_FIFOC, 0x1 << SUNXI_ADC_FIFOC_EN_AD, 0x1 << SUNXI_ADC_FIFOC_EN_AD);
 316 +
 317 +               /* set RX FIFO mode */
 318 +               regmap_update_bits(priv->regmap, SUNXI_ADC_FIFOC, 0x1 << SUNXI_ADC_FIFOC_RX_FIFO_MODE, 0x1 << SUNXI_ADC_FIFOC_RX_FIFO_MODE);
 319 +
 320 +               /* flush RX FIFO */
 321 +               regmap_update_bits(priv->regmap, SUNXI_ADC_FIFOC, 0x1 << SUNXI_ADC_FIFOC_FIFO_FLUSH, 0x1 << SUNXI_ADC_FIFOC_FIFO_FLUSH);
 322 +
 323 +               /* set RX FIFO rec drq level */
 324 +               regmap_update_bits(priv->regmap, SUNXI_ADC_FIFOC, 0xf << SUNXI_ADC_FIFOC_RX_TRIG_LEVEL, 0x7 << SUNXI_ADC_FIFOC_RX_TRIG_LEVEL);
 325 +
 326 +               /* enable adc1 analog */
 327 +               regmap_update_bits(priv->regmap, SUNXI_ADC_ACTL, 0x3 << SUNXI_ADC_ACTL_ADCLEN, 0x3 << SUNXI_ADC_ACTL_ADCLEN);
 328 +       }
 329 +
 330 +       return 0;
 331 +}
 332 +
 333 +static int sunxi_codec_hw_params(struct snd_pcm_substream *substream,
 334 +                                struct snd_pcm_hw_params *params,
 335 +                                struct snd_soc_dai *dai)
 336 +{
 337 +       struct snd_soc_pcm_runtime *rtd = substream->private_data;
 338 +       struct sunxi_priv *priv = snd_soc_card_get_drvdata(rtd->card);
 339 +       int is_mono = !!(params_channels(params) == 1);
 340 +       int is_24bit = !!(hw_param_interval(params, SNDRV_PCM_HW_PARAM_SAMPLE_BITS)->min == 32);
 341 +       unsigned int rate = params_rate(params);
 342 +       unsigned int hwrate;
 343 +
 344 +       switch (rate) {
 345 +       case 176400:
 346 +       case 88200:
 347 +       case 44100:
 348 +       case 33075:
 349 +       case 22050:
 350 +       case 14700:
 351 +       case 11025:
 352 +       case 7350:
 353 +       default:
 354 +               clk_set_rate(priv->clk_module, 22579200);
 355 +               break;
 356 +       case 192000:
 357 +       case 96000:
 358 +       case 48000:
 359 +       case 32000:
 360 +       case 24000:
 361 +       case 16000:
 362 +       case 12000:
 363 +       case 8000:
 364 +               clk_set_rate(priv->clk_module, 24576000);
 365 +               break;
 366 +       }
 367 +
 368 +       switch (rate) {
 369 +       case 192000:
 370 +       case 176400:
 371 +               hwrate = 6;
 372 +               break;
 373 +       case 96000:
 374 +       case 88200:
 375 +               hwrate = 7;
 376 +               break;
 377 +       default:
 378 +       case 48000:
 379 +       case 44100:
 380 +               hwrate = 0;
 381 +               break;
 382 +       case 32000:
 383 +       case 33075:
 384 +               hwrate = 1;
 385 +               break;
 386 +       case 24000:
 387 +       case 22050:
 388 +               hwrate = 2;
 389 +               break;
 390 +       case 16000:
 391 +       case 14700:
 392 +               hwrate = 3;
 393 +               break;
 394 +       case 12000:
 395 +       case 11025:
 396 +               hwrate = 4;
 397 +               break;
 398 +       case 8000:
 399 +       case 7350:
 400 +               hwrate = 5;
 401 +               break;
 402 +       }
 403 +
 404 +       if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
 405 +               regmap_update_bits(priv->regmap, SUNXI_DAC_FIFOC, 7 << SUNXI_DAC_FIFOC_DAC_FS, hwrate << SUNXI_DAC_FIFOC_DAC_FS);
 406 +               regmap_update_bits(priv->regmap, SUNXI_DAC_FIFOC, 1 << SUNXI_DAC_FIFOC_MONO_EN, is_mono << SUNXI_DAC_FIFOC_MONO_EN);
 407 +               regmap_update_bits(priv->regmap, SUNXI_DAC_FIFOC, 1 << SUNXI_DAC_FIFOC_TX_SAMPLE_BITS, is_24bit << SUNXI_DAC_FIFOC_TX_SAMPLE_BITS);
 408 +               if (is_24bit)
 409 +                       priv->playback_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
 410 +               else
 411 +                       priv->playback_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
 412 +       } else  {
 413 +               regmap_update_bits(priv->regmap, SUNXI_ADC_FIFOC, 7 << SUNXI_DAC_FIFOC_DAC_FS, hwrate << SUNXI_DAC_FIFOC_DAC_FS);
 414 +               regmap_update_bits(priv->regmap, SUNXI_ADC_FIFOC, 1 << SUNXI_ADC_FIFOC_MONO_EN, is_mono << SUNXI_ADC_FIFOC_MONO_EN);
 415 +       }
 416 +
 417 +       return 0;
 418 +}
 419 +
 420 +static const struct snd_kcontrol_new sun7i_dac_ctls[] = {
 421 +       /*SUNXI_DAC_ACTL = 0x10,PAVOL*/
 422 +       SOC_SINGLE("Master Playback Volume", SUNXI_DAC_ACTL, 0, 0x3f, 0),
 423 +       SOC_SINGLE("Playback Switch", SUNXI_DAC_ACTL, 6, 1, 0), /* Global output switch */
 424 +       SOC_SINGLE("FmL Switch", SUNXI_DAC_ACTL, 17, 1, 0), /* FM left switch */
 425 +       SOC_SINGLE("FmR Switch", SUNXI_DAC_ACTL, 16, 1, 0), /* FM right switch */
 426 +       SOC_SINGLE("LineL Switch", SUNXI_DAC_ACTL, 19, 1, 0), /* Line left switch */
 427 +       SOC_SINGLE("LineR Switch", SUNXI_DAC_ACTL, 18, 1, 0), /* Line right switch */
 428 +       SOC_SINGLE("Ldac Left Mixer", SUNXI_DAC_ACTL, 15, 1, 0),
 429 +       SOC_SINGLE("Rdac Right Mixer", SUNXI_DAC_ACTL, 14, 1, 0),
 430 +       SOC_SINGLE("Ldac Right Mixer", SUNXI_DAC_ACTL, 13, 1, 0),
 431 +       SOC_SINGLE("Mic Input Mux", SUNXI_DAC_ACTL, 9, 15, 0), /* from bit 9 to bit 12. Microphone input mute */
 432 +       SOC_SINGLE("MIC output volume", SUNXI_DAC_ACTL, 20, 7, 0),
 433 +       /*      FM Input to output mixer Gain Control
 434 +       *       From -4.5db to 6db,1.5db/step,default is 0db
 435 +       *       -4.5db:0x0,-3.0db:0x1,-1.5db:0x2,0db:0x3
 436 +       *       1.5db:0x4,3.0db:0x5,4.5db:0x6,6db:0x7
 437 +       */
 438 +       SOC_SINGLE("Fm output Volume", SUNXI_DAC_ACTL, 23, 7, 0),
 439 +       /*      Line-in gain stage to output mixer Gain Control
 440 +       *       0:-1.5db,1:0db
 441 +       */
 442 +       SOC_SINGLE("Line output Volume", SUNXI_DAC_ACTL, 26, 1, 0),
 443 +
 444 +       SOC_SINGLE("Master Capture Mute", SUNXI_ADC_ACTL, 4, 1, 0),
 445 +       SOC_SINGLE("Right Capture Mute", SUNXI_ADC_ACTL, 31, 1, 0),
 446 +       SOC_SINGLE("Left Capture Mute", SUNXI_ADC_ACTL, 30, 1, 0),
 447 +       SOC_SINGLE("Linein Pre-AMP", SUNXI_ADC_ACTL, 13, 7, 0),
 448 +       SOC_SINGLE("LINEIN APM Volume", SUNXI_AC_MIC_PHONE_CAL, 13, 0x7, 0),
 449 +       /* ADC Input Gain Control, capture volume
 450 +       * 000:-4.5db,001:-3db,010:-1.5db,011:0db,100:1.5db,101:3db,110:4.5db,111:6db
 451 +       */
 452 +       SOC_SINGLE("Capture Volume", SUNXI_ADC_ACTL, 20, 7, 0),
 453 +       /*
 454 +       *       MIC2 pre-amplifier Gain Control
 455 +       *       00:0db,01:35db,10:38db,11:41db
 456 +       */
 457 +       SOC_SINGLE("MicL Volume", SUNXI_ADC_ACTL, 25, 3, 0), /* Microphone left volume */
 458 +       SOC_SINGLE("MicR Volume", SUNXI_ADC_ACTL, 23, 3, 0), /* Microphone right volume */
 459 +       SOC_SINGLE("Mic2 Boost", SUNXI_ADC_ACTL, 29, 1, 0),
 460 +       SOC_SINGLE("Mic1 Boost", SUNXI_ADC_ACTL, 28, 1, 0),
 461 +       SOC_SINGLE("Mic Power", SUNXI_ADC_ACTL, 27, 1, 0),
 462 +       SOC_SINGLE("ADC Input Mux", SUNXI_ADC_ACTL, 17, 7, 0), /* ADC input mute */
 463 +       SOC_SINGLE("Mic2 gain Volume", SUNXI_AC_MIC_PHONE_CAL, 26, 7, 0),
 464 +       /*
 465 +       *       MIC1 pre-amplifier Gain Control
 466 +       *       00:0db,01:35db,10:38db,11:41db
 467 +       */
 468 +       SOC_SINGLE("Mic1 gain Volume", SUNXI_AC_MIC_PHONE_CAL, 29, 3, 0),
 469 +};
 470 +
 471 +static int sunxi_codec_dai_probe(struct snd_soc_dai *dai)
 472 +{
 473 +       struct snd_soc_card *card = snd_soc_dai_get_drvdata(dai);
 474 +       struct sunxi_priv *priv = snd_soc_card_get_drvdata(card);
 475 +
 476 +       snd_soc_dai_init_dma_data(dai, &priv->playback_dma_data, &priv->capture_dma_data);
 477 +
 478 +       return 0;
 479 +}
 480 +
 481 +static void sunxi_codec_init(struct sunxi_priv *priv)
 482 +{
 483 +       regmap_update_bits(priv->regmap, SUNXI_DAC_FIFOC, 1 << SUNXI_DAC_FIFOC_FIR_VERSION, 1 << SUNXI_DAC_FIFOC_FIR_VERSION);
 484 +
 485 +       /* set digital volume to maximum */
 486 +       if (priv->revision == SUN4IA)
 487 +               regmap_update_bits(priv->regmap, SUNXI_DAC_DPC, 0x3F << SUNXI_DAC_DPC_DVOL, 0 << SUNXI_DAC_DPC_DVOL);
 488 +
 489 +       regmap_update_bits(priv->regmap, SUNXI_DAC_FIFOC, 3 << SUNXI_DAC_FIFOC_DRQ_CLR_CNT, 3 << SUNXI_DAC_FIFOC_DRQ_CLR_CNT);
 490 +
 491 +       /* set volume */ /* TODO: is A10A inverted? */
 492 +       if (priv->revision == SUN4IA)
 493 +               regmap_update_bits(priv->regmap, SUNXI_DAC_ACTL, 0x3f << SUNXI_DAC_ACTL_PA_VOL, 1 << SUNXI_DAC_ACTL_PA_VOL);
 494 +       else
 495 +               regmap_update_bits(priv->regmap, SUNXI_DAC_ACTL, 0x3f << SUNXI_DAC_ACTL_PA_VOL, 0x3b << SUNXI_DAC_ACTL_PA_VOL);
 496 +}
 497 +
 498 +static int sunxi_codec_startup(struct snd_pcm_substream *substream,
 499 +                              struct snd_soc_dai *dai)
 500 +{
 501 +       struct snd_soc_pcm_runtime *rtd = substream->private_data;
 502 +       struct sunxi_priv *priv = snd_soc_card_get_drvdata(rtd->card);
 503 +
 504 +       sunxi_codec_init(priv);
 505 +
 506 +       return clk_prepare_enable(priv->clk_module);
 507 +}
 508 +
 509 +static void sunxi_codec_shutdown(struct snd_pcm_substream *substream,
 510 +                                struct snd_soc_dai *dai)
 511 +{
 512 +       struct snd_soc_pcm_runtime *rtd = substream->private_data;
 513 +       struct sunxi_priv *priv = snd_soc_card_get_drvdata(rtd->card);
 514 +
 515 +       clk_disable_unprepare(priv->clk_module);
 516 +}
 517 +
 518 +/*** Codec DAI ***/
 519 +
 520 +static const struct snd_soc_dai_ops sunxi_codec_dai_ops = {
 521 +       .startup = sunxi_codec_startup,
 522 +       .shutdown = sunxi_codec_shutdown,
 523 +       .trigger = sunxi_codec_trigger,
 524 +       .hw_params = sunxi_codec_hw_params,
 525 +       .prepare = sunxi_codec_prepare,
 526 +};
 527 +
 528 +static struct snd_soc_dai_driver sunxi_codec_dai = {
 529 +       .name = "Codec",
 530 +       .playback = {
 531 +               .stream_name = "Codec Playback",
 532 +               .channels_min = 1,
 533 +               .channels_max = 2,
 534 +               .rate_min = 8000,
 535 +               .rate_max = 192000,
 536 +               .rates = (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_11025 |\
 537 +                        SNDRV_PCM_RATE_22050| SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 |\
 538 +                        SNDRV_PCM_RATE_48000 |SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_192000 |\
 539 +                        SNDRV_PCM_RATE_KNOT),
 540 +               .formats = (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE),
 541 +               .sig_bits = 24,
 542 +       },
 543 +       .capture = {
 544 +               .stream_name = "Codec Capture",
 545 +               .channels_min = 1,
 546 +               .channels_max = 2,
 547 +               .rate_min = 8000,
 548 +               .rate_max = 192000,
 549 +               .rates = (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_11025 |\
 550 +                        SNDRV_PCM_RATE_22050| SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 |\
 551 +                        SNDRV_PCM_RATE_48000 |SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_192000 |\
 552 +                        SNDRV_PCM_RATE_KNOT),
 553 +               .formats = (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE),
 554 +               .sig_bits = 24,
 555 +       },
 556 +       .ops = &sunxi_codec_dai_ops,
 557 +};
 558 +
 559 +/*** Codec ***/
 560 +
 561 +static const struct snd_kcontrol_new sunxi_pa =
 562 +       SOC_DAPM_SINGLE("PA Switch", SUNXI_ADC_ACTL, SUNXI_ADC_ACTL_PA_EN, 1, 0);
 563 +
 564 +static const struct snd_kcontrol_new sunxi_pa_mute =
 565 +       SOC_DAPM_SINGLE("PA Mute Switch", SUNXI_DAC_ACTL, SUNXI_DAC_ACTL_PA_MUTE, 1, 0);
 566 +
 567 +static DECLARE_TLV_DB_SCALE(sunxi_pa_volume_scale, -6300, 100, 1);
 568 +
 569 +static const struct snd_kcontrol_new sunxi_codec_widgets[] = {
 570 +       SOC_SINGLE_TLV("PA Volume", SUNXI_DAC_ACTL, SUNXI_DAC_ACTL_PA_VOL,
 571 +                      0x3F, 0, sunxi_pa_volume_scale),
 572 +};
 573 +
 574 +static const char *right_output_mixer_text[] = { "Disabled", "Left", "Right" };
 575 +static const unsigned int right_output_mixer_values[] = { 0x0, 0x1, 0x2 };
 576 +static SOC_VALUE_ENUM_SINGLE_DECL(right_output_mixer, SUNXI_DAC_ACTL,
 577 +                                 SUNXI_DAC_ACTL_LDACRMIXS, 0x3,
 578 +                                 right_output_mixer_text,
 579 +                                 right_output_mixer_values);
 580 +
 581 +static const char *left_output_mixer_text[] = { "Disabled", "Left" };
 582 +static const unsigned int left_output_mixer_values[] = { 0x0, 0x1 };
 583 +static SOC_VALUE_ENUM_SINGLE_DECL(left_output_mixer, SUNXI_DAC_ACTL,
 584 +                                 SUNXI_DAC_ACTL_LDACLMIXS, 0x1,
 585 +                                 left_output_mixer_text,
 586 +                                 left_output_mixer_values);
 587 +
 588 +static const struct snd_kcontrol_new right_mixer =
 589 +       SOC_DAPM_ENUM("Right Mixer", right_output_mixer);
 590 +
 591 +static const struct snd_kcontrol_new left_mixer =
 592 +       SOC_DAPM_ENUM("Left Mixer", left_output_mixer);
 593 +
 594 +static const struct snd_kcontrol_new sunxi_mixer =
 595 +       SOC_DAPM_SINGLE("Mixer Switch", SUNXI_DAC_ACTL, SUNXI_DAC_ACTL_MIXEN, 1, 0);
 596 +
 597 +static const char *sunxi_dac_output_text[] = { "Muted", "Mixed", "Direct" };
 598 +static const unsigned int sunxi_dac_output_values[] = { 0x0, 0x1, 0x2 };
 599 +static SOC_VALUE_ENUM_SINGLE_DECL(dac_output_mux, SUNXI_DAC_ACTL,
 600 +                                 SUNXI_DAC_ACTL_MIXPAS, 0x3,
 601 +                                 sunxi_dac_output_text,
 602 +                                 sunxi_dac_output_values);
 603 +
 604 +static const struct snd_kcontrol_new sunxi_dac_output =
 605 +       SOC_DAPM_ENUM("DAC Output", dac_output_mux);
 606 +
 607 +static const struct snd_soc_dapm_widget codec_dapm_widgets[] = {
 608 +       /* Digital parts of the DACs */
 609 +       SND_SOC_DAPM_SUPPLY("DAC", SUNXI_DAC_DPC, SUNXI_DAC_DPC_EN_DA, 0, NULL, 0),
 610 +
 611 +       /* Analog parts of the DACs */
 612 +       SND_SOC_DAPM_DAC("Left DAC", NULL, SUNXI_DAC_ACTL, SUNXI_DAC_ACTL_DACAENL, 0),
 613 +       SND_SOC_DAPM_DAC("Right DAC", NULL, SUNXI_DAC_ACTL, SUNXI_DAC_ACTL_DACAENR, 0),
 614 +
 615 +       SND_SOC_DAPM_SWITCH("PA", SUNXI_ADC_ACTL, SUNXI_ADC_ACTL_PA_EN, 0, &sunxi_pa),
 616 +       SND_SOC_DAPM_SWITCH("PA Mute", SUNXI_DAC_ACTL, SUNXI_DAC_ACTL_PA_MUTE, 0, &sunxi_pa_mute),
 617 +
 618 +       SND_SOC_DAPM_MUX("Right Mixer", SUNXI_DAC_ACTL, SUNXI_DAC_ACTL_LDACRMIXS, 0, &right_mixer),
 619 +       SND_SOC_DAPM_MUX("Left Mixer", SUNXI_DAC_ACTL, SUNXI_DAC_ACTL_LDACLMIXS, 0, &left_mixer),
 620 +       SND_SOC_DAPM_SWITCH("Mixer", SUNXI_DAC_ACTL, SUNXI_DAC_ACTL_MIXEN, 0, &sunxi_mixer),
 621 +
 622 +       SND_SOC_DAPM_MUX("DAC Output", SUNXI_DAC_ACTL, SUNXI_DAC_ACTL_MIXPAS, 0, &sunxi_dac_output),
 623 +
 624 +       SND_SOC_DAPM_OUTPUT("Mic Bias"),
 625 +       SND_SOC_DAPM_OUTPUT("HP Right"),
 626 +       SND_SOC_DAPM_OUTPUT("HP Left"),
 627 +       SND_SOC_DAPM_INPUT("MIC_IN"),
 628 +       SND_SOC_DAPM_INPUT("LINE_IN"),
 629 +};
 630 +
 631 +static const struct snd_soc_dapm_route codec_dapm_routes[] = {
 632 +       /* DAC block */
 633 +       { "Left DAC", NULL, "Codec Playback" },
 634 +       { "Right DAC", NULL, "Codec Playback" },
 635 +       { "Left DAC", NULL, "DAC" },
 636 +       { "Right DAC", NULL, "DAC" },
 637 +
 638 +       /* DAC -> PA path */
 639 +       { "DAC Output", "Direct", "Left DAC" },
 640 +       { "DAC Output", "Direct", "Right DAC" },
 641 +       { "PA", NULL, "DAC Output"},
 642 +
 643 +       /* DAC -> MIX -> PA path */
 644 +       { "Left Mixer", "Left", "Left DAC" },
 645 +       { "Right Mixer", "Right", "Right DAC" },
 646 +       { "Mixer", NULL, "Left Mixer" },
 647 +       { "Mixer", NULL, "Right Mixer" },
 648 +       { "DAC Output", "Mixed", "Mixer" },
 649 +       { "PA", NULL, "DAC Output" },
 650 +
 651 +       /* PA -> HP path */
 652 +       { "PA Mute", NULL, "PA" },
 653 +       { "HP Right", NULL, "PA Mute" },
 654 +       { "HP Left", NULL, "PA Mute" },
 655 +};
 656 +
 657 +static struct snd_soc_codec_driver sunxi_codec = {
 658 +       .controls = sunxi_codec_widgets,
 659 +       .num_controls = ARRAY_SIZE(sunxi_codec_widgets),
 660 +       .dapm_widgets = codec_dapm_widgets,
 661 +       .num_dapm_widgets = ARRAY_SIZE(codec_dapm_widgets),
 662 +       .dapm_routes = codec_dapm_routes,
 663 +       .num_dapm_routes = ARRAY_SIZE(codec_dapm_routes),
 664 +};
 665 +
 666 +/*** Board routing ***/
 667 +/* TODO: do this with DT */
 668 +
 669 +static const struct snd_soc_dapm_widget sunxi_board_dapm_widgets[] = {
 670 +       SND_SOC_DAPM_HP("Headphone Jack", NULL),
 671 +};
 672 +
 673 +static const struct snd_soc_dapm_route sunxi_board_routing[] = {
 674 +       { "Headphone Jack",     NULL,   "HP Right" },
 675 +       { "Headphone Jack",     NULL,   "HP Left" },
 676 +};
 677 +
 678 +/*** Card and DAI Link ***/
 679 +
 680 +static struct snd_soc_dai_link cdc_dai = {
 681 +       .name = "cdc",
 682 +
 683 +       .stream_name = "CDC PCM",
 684 +       .codec_dai_name = "Codec",
 685 +       .cpu_dai_name = "1c22c00.codec",
 686 +       .codec_name = "1c22c00.codec",
 687 +       .platform_name = "1c22c00.codec",
 688 +       .dai_fmt = SND_SOC_DAIFMT_I2S,
 689 +};
 690 +
 691 +static struct snd_soc_card snd_soc_sunxi_codec = {
 692 +       .name = "sunxi-codec",
 693 +       .owner = THIS_MODULE,
 694 +       .dai_link = &cdc_dai,
 695 +       .num_links = 1,
 696 +       .dapm_widgets = sunxi_board_dapm_widgets,
 697 +       .num_dapm_widgets = ARRAY_SIZE(sunxi_board_dapm_widgets),
 698 +       .dapm_routes = sunxi_board_routing,
 699 +       .num_dapm_routes = ARRAY_SIZE(sunxi_board_routing),
 700 +};
 701 +
 702 +/*** CPU DAI ***/
 703 +
 704 +static const struct snd_soc_component_driver sunxi_codec_component = {
 705 +       .name = "sunxi-codec",
 706 +};
 707 +
 708 +#define SUNXI_RATES    SNDRV_PCM_RATE_8000_192000
 709 +#define SUNXI_FORMATS  (SNDRV_PCM_FMTBIT_S16_LE | \
 710 +                       SNDRV_PCM_FMTBIT_S32_LE)
 711 +
 712 +static struct snd_soc_dai_driver dummy_cpu_dai = {
 713 +       .name = "sunxi-cpu-dai",
 714 +       .probe = sunxi_codec_dai_probe,
 715 +       .playback = {
 716 +               .stream_name    = "Playback",
 717 +               .channels_min   = 1,
 718 +               .channels_max   = 2,
 719 +               .rates          = SUNXI_RATES,
 720 +               .formats        = SUNXI_FORMATS,
 721 +               .sig_bits       = 24,
 722 +       },
 723 +       .capture = {
 724 +               .stream_name    = "Capture",
 725 +               .channels_min   = 1,
 726 +               .channels_max   = 2,
 727 +               .rates          = SUNXI_RATES,
 728 +               .formats        = SUNXI_FORMATS,
 729 +               .sig_bits       = 24,
 730 +        },
 731 +};
 732 +
 733 +static const struct regmap_config sunxi_codec_regmap_config = {
 734 +       .reg_bits = 32,
 735 +       .reg_stride = 4,
 736 +       .val_bits = 32,
 737 +       .max_register = SUNXI_AC_MIC_PHONE_CAL,
 738 +};
 739 +
 740 +static const struct of_device_id sunxi_codec_of_match[] = {
 741 +       { .compatible = "allwinner,sun4i-a10a-codec", .data = (void *)SUN4IA},
 742 +       { .compatible = "allwinner,sun4i-a10-codec", .data = (void *)SUN4I},
 743 +       { .compatible = "allwinner,sun5i-a13-codec", .data = (void *)SUN5I},
 744 +       { .compatible = "allwinner,sun7i-a20-codec", .data = (void *)SUN7I},
 745 +       {}
 746 +};
 747 +MODULE_DEVICE_TABLE(of, sunxi_codec_of_match);
 748 +
 749 +static int sunxi_codec_probe(struct platform_device *pdev)
 750 +{
 751 +       struct device_node *np = pdev->dev.of_node;
 752 +       struct snd_soc_card *card = &snd_soc_sunxi_codec;
 753 +       const struct of_device_id *of_id;
 754 +       struct device *dev = &pdev->dev;
 755 +       struct sunxi_priv *priv;
 756 +       struct resource *res;
 757 +       void __iomem *base;
 758 +       int ret;
 759 +
 760 +       if (!of_device_is_available(np))
 761 +               return -ENODEV;
 762 +
 763 +       of_id = of_match_device(sunxi_codec_of_match, dev);
 764 +       if (!of_id)
 765 +               return -EINVAL;
 766 +
 767 +       priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
 768 +       if (!priv)
 769 +               return -ENOMEM;
 770 +
 771 +       card->dev = &pdev->dev;
 772 +       platform_set_drvdata(pdev, card);
 773 +       snd_soc_card_set_drvdata(card, priv);
 774 +
 775 +       priv->revision = (enum sunxi_soc_family)of_id->data;
 776 +
 777 +       res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 778 +       base = devm_ioremap_resource(&pdev->dev, res);
 779 +       if (IS_ERR(base))
 780 +               return PTR_ERR(base);
 781 +
 782 +       priv->regmap = devm_regmap_init_mmio(&pdev->dev, base,
 783 +                                            &sunxi_codec_regmap_config);
 784 +       if (IS_ERR(priv->regmap))
 785 +               return PTR_ERR(priv->regmap);
 786 +
 787 +       /* Get the clocks from the DT */
 788 +       priv->clk_apb = devm_clk_get(dev, "apb");
 789 +       if (IS_ERR(priv->clk_apb)) {
 790 +               dev_err(dev, "failed to get apb clock\n");
 791 +               return PTR_ERR(priv->clk_apb);
 792 +       }
 793 +       priv->clk_module = devm_clk_get(dev, "codec");
 794 +       if (IS_ERR(priv->clk_module)) {
 795 +               dev_err(dev, "failed to get codec clock\n");
 796 +               return PTR_ERR(priv->clk_module);
 797 +       }
 798 +
 799 +       /* Enable the clock on a basic rate */
 800 +       ret = clk_set_rate(priv->clk_module, 24576000);
 801 +       if (ret) {
 802 +               dev_err(dev, "failed to set codec base clock rate\n");
 803 +               return ret;
 804 +       }
 805 +
 806 +       /* Enable the bus clock */
 807 +       if (clk_prepare_enable(priv->clk_apb)) {
 808 +               dev_err(dev, "failed to enable apb clock\n");
 809 +               clk_disable_unprepare(priv->clk_module);
 810 +               return -EINVAL;
 811 +       }
 812 +
 813 +       /* DMA configuration for TX FIFO */
 814 +       priv->playback_dma_data.addr = res->start + SUNXI_DAC_TXDATA;
 815 +       priv->playback_dma_data.maxburst = 4;
 816 +       priv->playback_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
 817 +
 818 +       /* DMA configuration for RX FIFO */
 819 +       priv->capture_dma_data.addr = res->start + SUNXI_ADC_RXDATA;
 820 +       priv->capture_dma_data.maxburst = 4;
 821 +       priv->capture_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
 822 +
 823 +       ret = snd_soc_register_codec(&pdev->dev, &sunxi_codec, &sunxi_codec_dai, 1);
 824 +
 825 +       ret = devm_snd_soc_register_component(&pdev->dev, &sunxi_codec_component, &dummy_cpu_dai, 1);
 826 +       if (ret)
 827 +               goto err_clk_disable;
 828 +
 829 +       ret = devm_snd_dmaengine_pcm_register(&pdev->dev, NULL, 0);
 830 +       if (ret)
 831 +               goto err_clk_disable;
 832 +
 833 +       sunxi_codec_init(priv);
 834 +
 835 +       ret = snd_soc_register_card(card);
 836 +       if (ret) {
 837 +               dev_err(&pdev->dev, "snd_soc_register_card failed (%d)\n", ret);
 838 +               goto err_fini_utils;
 839 +       }
 840 +
 841 +       ret = snd_soc_of_parse_audio_routing(card, "routing");
 842 +       if (ret)
 843 +               goto err;
 844 +
 845 +       return 0;
 846 +
 847 +err_fini_utils:
 848 +err:
 849 +err_clk_disable:
 850 +       clk_disable_unprepare(priv->clk_apb);
 851 +       return ret;
 852 +}
 853 +
 854 +static int sunxi_codec_remove(struct platform_device *pdev)
 855 +{
 856 +       struct sunxi_priv *priv = platform_get_drvdata(pdev);
 857 +
 858 +       clk_disable_unprepare(priv->clk_apb);
 859 +       clk_disable_unprepare(priv->clk_module);
 860 +
 861 +       return 0;
 862 +}
 863 +
 864 +static struct platform_driver sunxi_codec_driver = {
 865 +       .driver = {
 866 +               .name = "sunxi-codec",
 867 +               .owner = THIS_MODULE,
 868 +               .of_match_table = sunxi_codec_of_match,
 869 +       },
 870 +       .probe = sunxi_codec_probe,
 871 +       .remove = sunxi_codec_remove,
 872 +};
 873 +module_platform_driver(sunxi_codec_driver);
 874 +
 875 +MODULE_DESCRIPTION("sunxi codec ASoC driver");
 876 +MODULE_AUTHOR("Emilio López <emilio@elopez.com.ar>");
 877 +MODULE_AUTHOR("Jon Smirl <jonsmirl@gmail.com>");
 878 +MODULE_LICENSE("GPL");