target/linux/sunxi/patches-3.13/122-2-dt-sun5i-add-mod0.patch

   1 From 9a8d3f21c94099a2bcd79ac1684cc8020fd98df2 Mon Sep 17 00:00:00 2001
   2 From: =?UTF-8?q?Emilio=20L=C3=B3pez?= <emilio@elopez.com.ar>
   3 Date: Mon, 23 Dec 2013 00:32:42 -0300
   4 Subject: [PATCH] ARM: sun5i: dt: mod0 clocks
   5 MIME-Version: 1.0
   6 Content-Type: text/plain; charset=UTF-8
   7 Content-Transfer-Encoding: 8bit
   8
   9 This commit adds all the mod0 clocks available on A10 and A13. The list
  10 has been constructed by looking at the Allwinner code release for A10S
  11 and A13.
  12
  13 Signed-off-by: Emilio López <emilio@elopez.com.ar>
  14 Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
  15 ---
  16  arch/arm/boot/dts/sun5i-a10s.dtsi | 88 +++++++++++++++++++++++++++++++++++++++
  17  arch/arm/boot/dts/sun5i-a13.dtsi  | 88 +++++++++++++++++++++++++++++++++++++++
  18  2 files changed, 176 insertions(+)
  19
  20 --- a/arch/arm/boot/dts/sun5i-a10s.dtsi
  21 +++ b/arch/arm/boot/dts/sun5i-a10s.dtsi
  22 @@ -169,6 +169,94 @@
  23                                 "apb1_i2c2", "apb1_uart0", "apb1_uart1",
  24                                 "apb1_uart2", "apb1_uart3";
  25                 };
  26 +
  27 +               nand_clk: clk@01c20080 {
  28 +                       #clock-cells = <0>;
  29 +                       compatible = "allwinner,sun4i-mod0-clk";
  30 +                       reg = <0x01c20080 0x4>;
  31 +                       clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
  32 +                       clock-output-names = "nand";
  33 +               };
  34 +
  35 +               ms_clk: clk@01c20084 {
  36 +                       #clock-cells = <0>;
  37 +                       compatible = "allwinner,sun4i-mod0-clk";
  38 +                       reg = <0x01c20084 0x4>;
  39 +                       clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
  40 +                       clock-output-names = "ms";
  41 +               };
  42 +
  43 +               mmc0_clk: clk@01c20088 {
  44 +                       #clock-cells = <0>;
  45 +                       compatible = "allwinner,sun4i-mod0-clk";
  46 +                       reg = <0x01c20088 0x4>;
  47 +                       clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
  48 +                       clock-output-names = "mmc0";
  49 +               };
  50 +
  51 +               mmc1_clk: clk@01c2008c {
  52 +                       #clock-cells = <0>;
  53 +                       compatible = "allwinner,sun4i-mod0-clk";
  54 +                       reg = <0x01c2008c 0x4>;
  55 +                       clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
  56 +                       clock-output-names = "mmc1";
  57 +               };
  58 +
  59 +               mmc2_clk: clk@01c20090 {
  60 +                       #clock-cells = <0>;
  61 +                       compatible = "allwinner,sun4i-mod0-clk";
  62 +                       reg = <0x01c20090 0x4>;
  63 +                       clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
  64 +                       clock-output-names = "mmc2";
  65 +               };
  66 +
  67 +               ts_clk: clk@01c20098 {
  68 +                       #clock-cells = <0>;
  69 +                       compatible = "allwinner,sun4i-mod0-clk";
  70 +                       reg = <0x01c20098 0x4>;
  71 +                       clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
  72 +                       clock-output-names = "ts";
  73 +               };
  74 +
  75 +               ss_clk: clk@01c2009c {
  76 +                       #clock-cells = <0>;
  77 +                       compatible = "allwinner,sun4i-mod0-clk";
  78 +                       reg = <0x01c2009c 0x4>;
  79 +                       clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
  80 +                       clock-output-names = "ss";
  81 +               };
  82 +
  83 +               spi0_clk: clk@01c200a0 {
  84 +                       #clock-cells = <0>;
  85 +                       compatible = "allwinner,sun4i-mod0-clk";
  86 +                       reg = <0x01c200a0 0x4>;
  87 +                       clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
  88 +                       clock-output-names = "spi0";
  89 +               };
  90 +
  91 +               spi1_clk: clk@01c200a4 {
  92 +                       #clock-cells = <0>;
  93 +                       compatible = "allwinner,sun4i-mod0-clk";
  94 +                       reg = <0x01c200a4 0x4>;
  95 +                       clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
  96 +                       clock-output-names = "spi1";
  97 +               };
  98 +
  99 +               spi2_clk: clk@01c200a8 {
 100 +                       #clock-cells = <0>;
 101 +                       compatible = "allwinner,sun4i-mod0-clk";
 102 +                       reg = <0x01c200a8 0x4>;
 103 +                       clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 104 +                       clock-output-names = "spi2";
 105 +               };
 106 +
 107 +               ir0_clk: clk@01c200b0 {
 108 +                       #clock-cells = <0>;
 109 +                       compatible = "allwinner,sun4i-mod0-clk";
 110 +                       reg = <0x01c200b0 0x4>;
 111 +                       clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 112 +                       clock-output-names = "ir0";
 113 +               };
 114         };
 115
 116         soc@01c00000 {
 117 --- a/arch/arm/boot/dts/sun5i-a13.dtsi
 118 +++ b/arch/arm/boot/dts/sun5i-a13.dtsi
 119 @@ -170,6 +170,94 @@
 120                         clock-output-names = "apb1_i2c0", "apb1_i2c1",
 121                                 "apb1_i2c2", "apb1_uart1", "apb1_uart3";
 122                 };
 123 +
 124 +               nand_clk: clk@01c20080 {
 125 +                       #clock-cells = <0>;
 126 +                       compatible = "allwinner,sun4i-mod0-clk";
 127 +                       reg = <0x01c20080 0x4>;
 128 +                       clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 129 +                       clock-output-names = "nand";
 130 +               };
 131 +
 132 +               ms_clk: clk@01c20084 {
 133 +                       #clock-cells = <0>;
 134 +                       compatible = "allwinner,sun4i-mod0-clk";
 135 +                       reg = <0x01c20084 0x4>;
 136 +                       clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 137 +                       clock-output-names = "ms";
 138 +               };
 139 +
 140 +               mmc0_clk: clk@01c20088 {
 141 +                       #clock-cells = <0>;
 142 +                       compatible = "allwinner,sun4i-mod0-clk";
 143 +                       reg = <0x01c20088 0x4>;
 144 +                       clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 145 +                       clock-output-names = "mmc0";
 146 +               };
 147 +
 148 +               mmc1_clk: clk@01c2008c {
 149 +                       #clock-cells = <0>;
 150 +                       compatible = "allwinner,sun4i-mod0-clk";
 151 +                       reg = <0x01c2008c 0x4>;
 152 +                       clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 153 +                       clock-output-names = "mmc1";
 154 +               };
 155 +
 156 +               mmc2_clk: clk@01c20090 {
 157 +                       #clock-cells = <0>;
 158 +                       compatible = "allwinner,sun4i-mod0-clk";
 159 +                       reg = <0x01c20090 0x4>;
 160 +                       clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 161 +                       clock-output-names = "mmc2";
 162 +               };
 163 +
 164 +               ts_clk: clk@01c20098 {
 165 +                       #clock-cells = <0>;
 166 +                       compatible = "allwinner,sun4i-mod0-clk";
 167 +                       reg = <0x01c20098 0x4>;
 168 +                       clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 169 +                       clock-output-names = "ts";
 170 +               };
 171 +
 172 +               ss_clk: clk@01c2009c {
 173 +                       #clock-cells = <0>;
 174 +                       compatible = "allwinner,sun4i-mod0-clk";
 175 +                       reg = <0x01c2009c 0x4>;
 176 +                       clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 177 +                       clock-output-names = "ss";
 178 +               };
 179 +
 180 +               spi0_clk: clk@01c200a0 {
 181 +                       #clock-cells = <0>;
 182 +                       compatible = "allwinner,sun4i-mod0-clk";
 183 +                       reg = <0x01c200a0 0x4>;
 184 +                       clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 185 +                       clock-output-names = "spi0";
 186 +               };
 187 +
 188 +               spi1_clk: clk@01c200a4 {
 189 +                       #clock-cells = <0>;
 190 +                       compatible = "allwinner,sun4i-mod0-clk";
 191 +                       reg = <0x01c200a4 0x4>;
 192 +                       clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 193 +                       clock-output-names = "spi1";
 194 +               };
 195 +
 196 +               spi2_clk: clk@01c200a8 {
 197 +                       #clock-cells = <0>;
 198 +                       compatible = "allwinner,sun4i-mod0-clk";
 199 +                       reg = <0x01c200a8 0x4>;
 200 +                       clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 201 +                       clock-output-names = "spi2";
 202 +               };
 203 +
 204 +               ir0_clk: clk@01c200b0 {
 205 +                       #clock-cells = <0>;
 206 +                       compatible = "allwinner,sun4i-mod0-clk";
 207 +                       reg = <0x01c200b0 0x4>;
 208 +                       clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 209 +                       clock-output-names = "ir0";
 210 +               };
 211         };
 212
 213         soc@01c00000 {