target/linux/sunxi/patches-3.12/137-1-dt-sun7i-add-hstimer.patch

   1 From 6c23e1fa6bd220b8f5665c150c83d4c016d95482 Mon Sep 17 00:00:00 2001
   2 From: Maxime Ripard <maxime.ripard@free-electrons.com>
   3 Date: Thu, 7 Nov 2013 12:01:48 +0100
   4 Subject: [PATCH] ARM: sun7i: a20: Add support for the High Speed Timers
   5 MIME-Version: 1.0
   6 Content-Type: text/plain; charset=UTF-8
   7 Content-Transfer-Encoding: 8bit
   8
   9 The Allwinner A20 has support for four high speed timers. Apart for the
  10 number of timers (4 vs 2), it's basically the same logic than the high
  11 speed timers found in the sun5i chips.
  12
  13 Now that we have a driver to support it, we can enable them in the
  14 device tree.
  15
  16 [dlezcano] : Fixed conflict with 428abbb8 "Enable the I2C controllers"
  17
  18 Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
  19 Tested-by: Emilio López <emilio@elopez.com.ar>
  20 Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
  21 ---
  22  arch/arm/boot/dts/sun7i-a20.dtsi | 10 ++++++++++
  23  1 file changed, 10 insertions(+)
  24
  25 diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/sun7i-a20.dtsi
  26 index 93f7f96..c74147a 100644
  27 --- a/arch/arm/boot/dts/sun7i-a20.dtsi
  28 +++ b/arch/arm/boot/dts/sun7i-a20.dtsi
  29 @@ -405,6 +405,16 @@
  30                         status = "disabled";
  31                 };
  32
  33 +               hstimer@01c60000 {
  34 +                       compatible = "allwinner,sun7i-a20-hstimer";
  35 +                       reg = <0x01c60000 0x1000>;
  36 +                       interrupts = <0 81 1>,
  37 +                                    <0 82 1>,
  38 +                                    <0 83 1>,
  39 +                                    <0 84 1>;
  40 +                       clocks = <&ahb_gates 28>;
  41 +               };
  42 +
  43                 gic: interrupt-controller@01c81000 {
  44                         compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
  45                         reg = <0x01c81000 0x1000>,
  46 --
  47 1.8.5.1
  48