target/linux/sunxi/patches-3.12/130-sun7i-enable-i2c-ctrlers.patch

   1 From 220d6c860e0c7853aea6509ea2b5a44463c9af8b Mon Sep 17 00:00:00 2001
   2 From: Maxime Ripard <maxime.ripard@free-electrons.com>
   3 Date: Sat, 31 Aug 2013 23:07:24 +0200
   4 Subject: [PATCH] ARM: sun7i: Enable the I2C controllers
   5
   6 The Allwinner A20 shares the same I2C controller than the one that could
   7 be found on earlier SoCs from Allwinner. There is only a few more of
   8 these controllers. Add all of them in the DTSI.
   9
  10 Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
  11 ---
  12  arch/arm/boot/dts/sun7i-a20.dtsi | 45 ++++++++++++++++++++++++++++++++++++++++
  13  1 file changed, 45 insertions(+)
  14
  15 diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/sun7i-a20.dtsi
  16 index 2e39ed9..0d0ee15 100644
  17 --- a/arch/arm/boot/dts/sun7i-a20.dtsi
  18 +++ b/arch/arm/boot/dts/sun7i-a20.dtsi
  19 @@ -340,6 +340,51 @@
  20                         status = "disabled";
  21                 };
  22
  23 +               i2c0: i2c@01c2ac00 {
  24 +                       compatible = "allwinner,sun4i-i2c";
  25 +                       reg = <0x01c2ac00 0x400>;
  26 +                       interrupts = <0 7 1>;
  27 +                       clocks = <&apb1_gates 0>;
  28 +                       clock-frequency = <100000>;
  29 +                       status = "disabled";
  30 +               };
  31 +
  32 +               i2c1: i2c@01c2b000 {
  33 +                       compatible = "allwinner,sun4i-i2c";
  34 +                       reg = <0x01c2b000 0x400>;
  35 +                       interrupts = <0 8 1>;
  36 +                       clocks = <&apb1_gates 1>;
  37 +                       clock-frequency = <100000>;
  38 +                       status = "disabled";
  39 +               };
  40 +
  41 +               i2c2: i2c@01c2b400 {
  42 +                       compatible = "allwinner,sun4i-i2c";
  43 +                       reg = <0x01c2b400 0x400>;
  44 +                       interrupts = <0 9 1>;
  45 +                       clocks = <&apb1_gates 2>;
  46 +                       clock-frequency = <100000>;
  47 +                       status = "disabled";
  48 +               };
  49 +
  50 +               i2c3: i2c@01c2b800 {
  51 +                       compatible = "allwinner,sun4i-i2c";
  52 +                       reg = <0x01c2b800 0x400>;
  53 +                       interrupts = <0 88 1>;
  54 +                       clocks = <&apb1_gates 3>;
  55 +                       clock-frequency = <100000>;
  56 +                       status = "disabled";
  57 +               };
  58 +
  59 +               i2c4: i2c@01c2bc00 {
  60 +                       compatible = "allwinner,sun4i-i2c";
  61 +                       reg = <0x01c2bc00 0x400>;
  62 +                       interrupts = <0 89 1>;
  63 +                       clocks = <&apb1_gates 15>;
  64 +                       clock-frequency = <100000>;
  65 +                       status = "disabled";
  66 +               };
  67 +
  68                 gic: interrupt-controller@01c81000 {
  69                         compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
  70                         reg = <0x01c81000 0x1000>,
  71 --
  72 1.8.4
  73